1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode
*insn_mo
;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p
: 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros
;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float
;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float
;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32
= -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32
= -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float
= 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float
= 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008
= FALSE
;
278 static struct mips_set_options mips_opts
=
280 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
284 /* soft_float */ FALSE
, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase
;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit
;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask
;
298 unsigned long mips_cprmask
[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa
= ISA_UNKNOWN
;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16
;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips
;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch
= CPU_UNKNOWN
;
328 static const char *mips_arch_string
;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune
= CPU_UNKNOWN
;
333 static const char *mips_tune_string
;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode
= 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic
;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got
= 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap
= 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction
;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder
;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix
;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value
= 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen
= 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS
*, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control
*op_hash
= NULL
;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control
*mips16_op_hash
= NULL
;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control
*micromips_op_hash
= NULL
;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars
[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars
[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars
[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS
[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error
;
632 static int auto_align
= 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset
= -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset
= -1;
644 static int mips_cpreturn_register
= -1;
645 static int mips_gp_register
= GP
;
646 static int mips_gprel_offset
= 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid
= 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg
= SP
;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid
= 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize
= 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug
= 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history
[1 + MAX_NOPS
];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn
;
691 static struct mips_cl_insn mips16_nop_insn
;
692 static struct mips_cl_insn micromips_nop16_insn
;
693 static struct mips_cl_insn micromips_nop32_insn
;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS
*prev_nop_frag
;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds
;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required
;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since
;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup
*next
;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup
*mips_hi_fixup_list
;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS
*prev_reloc_op_frag
;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map
[] =
760 X
, X
, 2, 3, 4, 5, 6, 7,
761 X
, X
, X
, X
, X
, X
, X
, X
,
762 0, 1, X
, X
, X
, X
, X
, X
,
763 X
, X
, X
, X
, X
, X
, X
, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map
[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map
[] =
788 0, X
, 2, 3, X
, X
, X
, X
,
789 X
, X
, X
, X
, X
, X
, X
, X
,
790 4, 1, 5, 6, 7, X
, X
, X
,
791 X
, X
, X
, X
, X
, X
, X
, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map
[] =
797 0, X
, 2, 3, 4, 5, 6, 7,
798 X
, X
, X
, X
, X
, X
, X
, X
,
799 X
, 1, X
, X
, X
, X
, X
, X
,
800 X
, X
, X
, X
, X
, X
, X
, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1
[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2
[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map
[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map
[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map
[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map
[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump
;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop
;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f
;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120
;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130
;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k
;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1
;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch
;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes
[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p
;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length
;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes
[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes
[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns
[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning
;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1272 static void append_insn
1273 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1274 bfd_boolean expansionp
);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS
*, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS
*, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS
*, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn
*ip
, char *str
);
1283 static void mips16_macro (struct mips_cl_insn
* ip
);
1284 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1285 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1291 static void my_getExpression (expressionS
*, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type
);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1328 static int relaxed_branch_length (fragS
*, asection
*, int);
1329 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1330 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1332 /* Table and functions used to map between CPU/ISA names, and
1333 ISA levels, and CPU numbers. */
1335 struct mips_cpu_info
1337 const char *name
; /* CPU or ISA name. */
1338 int flags
; /* MIPS_CPU_* flags. */
1339 int ase
; /* Set of ASEs implemented by the CPU. */
1340 int isa
; /* ISA level. */
1341 int cpu
; /* CPU number (default CPU if ISA). */
1344 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1346 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1347 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1348 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1350 /* Command-line options. */
1351 const char *md_shortopts
= "O::g::G:";
1355 OPTION_MARCH
= OPTION_MD_BASE
,
1379 OPTION_NO_SMARTMIPS
,
1385 OPTION_NO_MICROMIPS
,
1388 OPTION_COMPAT_ARCH_BASE
,
1397 OPTION_M7000_HILO_FIX
,
1398 OPTION_MNO_7000_HILO_FIX
,
1401 OPTION_FIX_LOONGSON2F_JUMP
,
1402 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1403 OPTION_FIX_LOONGSON2F_NOP
,
1404 OPTION_NO_FIX_LOONGSON2F_NOP
,
1406 OPTION_NO_FIX_VR4120
,
1408 OPTION_NO_FIX_VR4130
,
1409 OPTION_FIX_CN63XXP1
,
1410 OPTION_NO_FIX_CN63XXP1
,
1417 OPTION_CONSTRUCT_FLOATS
,
1418 OPTION_NO_CONSTRUCT_FLOATS
,
1421 OPTION_RELAX_BRANCH
,
1422 OPTION_NO_RELAX_BRANCH
,
1431 OPTION_SINGLE_FLOAT
,
1432 OPTION_DOUBLE_FLOAT
,
1445 OPTION_MVXWORKS_PIC
,
1450 struct option md_longopts
[] =
1452 /* Options which specify architecture. */
1453 {"march", required_argument
, NULL
, OPTION_MARCH
},
1454 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1455 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1456 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1457 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1458 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1459 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1460 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1461 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1462 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1463 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1464 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1466 /* Options which specify Application Specific Extensions (ASEs). */
1467 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1468 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1469 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1470 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1471 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1472 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1473 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1474 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1475 {"mmt", no_argument
, NULL
, OPTION_MT
},
1476 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1477 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1478 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1479 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1480 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1481 {"meva", no_argument
, NULL
, OPTION_EVA
},
1482 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1483 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1484 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1485 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1486 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1487 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1488 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1490 /* Old-style architecture options. Don't add more of these. */
1491 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1492 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1493 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1494 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1495 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1496 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1497 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1498 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1500 /* Options which enable bug fixes. */
1501 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1502 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1503 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1504 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1505 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1506 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1507 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1508 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1509 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1510 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1511 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1512 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1513 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1514 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1515 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1517 /* Miscellaneous options. */
1518 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1519 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1520 {"break", no_argument
, NULL
, OPTION_BREAK
},
1521 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1522 {"EB", no_argument
, NULL
, OPTION_EB
},
1523 {"EL", no_argument
, NULL
, OPTION_EL
},
1524 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1525 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1526 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1527 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1528 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1529 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1530 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1531 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1532 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1533 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1534 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1535 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1536 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1537 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1538 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1539 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1540 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1541 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1543 /* Strictly speaking this next option is ELF specific,
1544 but we allow it for other ports as well in order to
1545 make testing easier. */
1546 {"32", no_argument
, NULL
, OPTION_32
},
1548 /* ELF-specific options. */
1549 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1550 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1551 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1552 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1553 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1554 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1555 {"n32", no_argument
, NULL
, OPTION_N32
},
1556 {"64", no_argument
, NULL
, OPTION_64
},
1557 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1558 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1559 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1560 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1561 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1562 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1564 {NULL
, no_argument
, NULL
, 0}
1566 size_t md_longopts_size
= sizeof (md_longopts
);
1568 /* Information about either an Application Specific Extension or an
1569 optional architecture feature that, for simplicity, we treat in the
1570 same way as an ASE. */
1573 /* The name of the ASE, used in both the command-line and .set options. */
1576 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1577 and 64-bit architectures, the flags here refer to the subset that
1578 is available on both. */
1581 /* The ASE_* flag used for instructions that are available on 64-bit
1582 architectures but that are not included in FLAGS. */
1583 unsigned int flags64
;
1585 /* The command-line options that turn the ASE on and off. */
1589 /* The minimum required architecture revisions for MIPS32, MIPS64,
1590 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1593 int micromips32_rev
;
1594 int micromips64_rev
;
1597 /* A table of all supported ASEs. */
1598 static const struct mips_ase mips_ases
[] = {
1599 { "dsp", ASE_DSP
, ASE_DSP64
,
1600 OPTION_DSP
, OPTION_NO_DSP
,
1603 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1604 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1607 { "eva", ASE_EVA
, 0,
1608 OPTION_EVA
, OPTION_NO_EVA
,
1611 { "mcu", ASE_MCU
, 0,
1612 OPTION_MCU
, OPTION_NO_MCU
,
1615 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1616 { "mdmx", ASE_MDMX
, 0,
1617 OPTION_MDMX
, OPTION_NO_MDMX
,
1620 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1621 { "mips3d", ASE_MIPS3D
, 0,
1622 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1626 OPTION_MT
, OPTION_NO_MT
,
1629 { "smartmips", ASE_SMARTMIPS
, 0,
1630 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1633 { "virt", ASE_VIRT
, ASE_VIRT64
,
1634 OPTION_VIRT
, OPTION_NO_VIRT
,
1638 /* The set of ASEs that require -mfp64. */
1639 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1641 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1642 static const unsigned int mips_ase_groups
[] = {
1648 The following pseudo-ops from the Kane and Heinrich MIPS book
1649 should be defined here, but are currently unsupported: .alias,
1650 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1652 The following pseudo-ops from the Kane and Heinrich MIPS book are
1653 specific to the type of debugging information being generated, and
1654 should be defined by the object format: .aent, .begin, .bend,
1655 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1658 The following pseudo-ops from the Kane and Heinrich MIPS book are
1659 not MIPS CPU specific, but are also not specific to the object file
1660 format. This file is probably the best place to define them, but
1661 they are not currently supported: .asm0, .endr, .lab, .struct. */
1663 static const pseudo_typeS mips_pseudo_table
[] =
1665 /* MIPS specific pseudo-ops. */
1666 {"option", s_option
, 0},
1667 {"set", s_mipsset
, 0},
1668 {"rdata", s_change_sec
, 'r'},
1669 {"sdata", s_change_sec
, 's'},
1670 {"livereg", s_ignore
, 0},
1671 {"abicalls", s_abicalls
, 0},
1672 {"cpload", s_cpload
, 0},
1673 {"cpsetup", s_cpsetup
, 0},
1674 {"cplocal", s_cplocal
, 0},
1675 {"cprestore", s_cprestore
, 0},
1676 {"cpreturn", s_cpreturn
, 0},
1677 {"dtprelword", s_dtprelword
, 0},
1678 {"dtpreldword", s_dtpreldword
, 0},
1679 {"tprelword", s_tprelword
, 0},
1680 {"tpreldword", s_tpreldword
, 0},
1681 {"gpvalue", s_gpvalue
, 0},
1682 {"gpword", s_gpword
, 0},
1683 {"gpdword", s_gpdword
, 0},
1684 {"ehword", s_ehword
, 0},
1685 {"cpadd", s_cpadd
, 0},
1686 {"insn", s_insn
, 0},
1689 /* Relatively generic pseudo-ops that happen to be used on MIPS
1691 {"asciiz", stringer
, 8 + 1},
1692 {"bss", s_change_sec
, 'b'},
1694 {"half", s_cons
, 1},
1695 {"dword", s_cons
, 3},
1696 {"weakext", s_mips_weakext
, 0},
1697 {"origin", s_org
, 0},
1698 {"repeat", s_rept
, 0},
1700 /* For MIPS this is non-standard, but we define it for consistency. */
1701 {"sbss", s_change_sec
, 'B'},
1703 /* These pseudo-ops are defined in read.c, but must be overridden
1704 here for one reason or another. */
1705 {"align", s_align
, 0},
1706 {"byte", s_cons
, 0},
1707 {"data", s_change_sec
, 'd'},
1708 {"double", s_float_cons
, 'd'},
1709 {"float", s_float_cons
, 'f'},
1710 {"globl", s_mips_globl
, 0},
1711 {"global", s_mips_globl
, 0},
1712 {"hword", s_cons
, 1},
1714 {"long", s_cons
, 2},
1715 {"octa", s_cons
, 4},
1716 {"quad", s_cons
, 3},
1717 {"section", s_change_section
, 0},
1718 {"short", s_cons
, 1},
1719 {"single", s_float_cons
, 'f'},
1720 {"stabd", s_mips_stab
, 'd'},
1721 {"stabn", s_mips_stab
, 'n'},
1722 {"stabs", s_mips_stab
, 's'},
1723 {"text", s_change_sec
, 't'},
1724 {"word", s_cons
, 2},
1726 { "extern", ecoff_directive_extern
, 0},
1731 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1733 /* These pseudo-ops should be defined by the object file format.
1734 However, a.out doesn't support them, so we have versions here. */
1735 {"aent", s_mips_ent
, 1},
1736 {"bgnb", s_ignore
, 0},
1737 {"end", s_mips_end
, 0},
1738 {"endb", s_ignore
, 0},
1739 {"ent", s_mips_ent
, 0},
1740 {"file", s_mips_file
, 0},
1741 {"fmask", s_mips_mask
, 'F'},
1742 {"frame", s_mips_frame
, 0},
1743 {"loc", s_mips_loc
, 0},
1744 {"mask", s_mips_mask
, 'R'},
1745 {"verstamp", s_ignore
, 0},
1749 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1750 purpose of the `.dc.a' internal pseudo-op. */
1753 mips_address_bytes (void)
1755 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1758 extern void pop_insert (const pseudo_typeS
*);
1761 mips_pop_insert (void)
1763 pop_insert (mips_pseudo_table
);
1764 if (! ECOFF_DEBUGGING
)
1765 pop_insert (mips_nonecoff_pseudo_table
);
1768 /* Symbols labelling the current insn. */
1770 struct insn_label_list
1772 struct insn_label_list
*next
;
1776 static struct insn_label_list
*free_insn_labels
;
1777 #define label_list tc_segment_info_data.labels
1779 static void mips_clear_insn_labels (void);
1780 static void mips_mark_labels (void);
1781 static void mips_compressed_mark_labels (void);
1784 mips_clear_insn_labels (void)
1786 register struct insn_label_list
**pl
;
1787 segment_info_type
*si
;
1791 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1794 si
= seg_info (now_seg
);
1795 *pl
= si
->label_list
;
1796 si
->label_list
= NULL
;
1800 /* Mark instruction labels in MIPS16/microMIPS mode. */
1803 mips_mark_labels (void)
1805 if (HAVE_CODE_COMPRESSION
)
1806 mips_compressed_mark_labels ();
1809 static char *expr_end
;
1811 /* Expressions which appear in macro instructions. These are set by
1812 mips_ip and read by macro. */
1814 static expressionS imm_expr
;
1815 static expressionS imm2_expr
;
1817 /* The relocatable field in an instruction and the relocs associated
1818 with it. These variables are used for instructions like LUI and
1819 JAL as well as true offsets. They are also used for address
1820 operands in macros. */
1822 static expressionS offset_expr
;
1823 static bfd_reloc_code_real_type offset_reloc
[3]
1824 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1826 /* This is set to the resulting size of the instruction to be produced
1827 by mips16_ip if an explicit extension is used or by mips_ip if an
1828 explicit size is supplied. */
1830 static unsigned int forced_insn_length
;
1832 /* True if we are assembling an instruction. All dot symbols defined during
1833 this time should be treated as code labels. */
1835 static bfd_boolean mips_assembling_insn
;
1837 /* The pdr segment for per procedure frame/regmask info. Not used for
1840 static segT pdr_seg
;
1842 /* The default target format to use. */
1844 #if defined (TE_FreeBSD)
1845 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1846 #elif defined (TE_TMIPS)
1847 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1849 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1853 mips_target_format (void)
1855 switch (OUTPUT_FLAVOR
)
1857 case bfd_target_elf_flavour
:
1859 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1860 return (target_big_endian
1861 ? "elf32-bigmips-vxworks"
1862 : "elf32-littlemips-vxworks");
1864 return (target_big_endian
1865 ? (HAVE_64BIT_OBJECTS
1866 ? ELF_TARGET ("elf64-", "big")
1868 ? ELF_TARGET ("elf32-n", "big")
1869 : ELF_TARGET ("elf32-", "big")))
1870 : (HAVE_64BIT_OBJECTS
1871 ? ELF_TARGET ("elf64-", "little")
1873 ? ELF_TARGET ("elf32-n", "little")
1874 : ELF_TARGET ("elf32-", "little"))));
1881 /* Return the ISA revision that is currently in use, or 0 if we are
1882 generating code for MIPS V or below. */
1887 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1890 /* microMIPS implies revision 2 or above. */
1891 if (mips_opts
.micromips
)
1894 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1900 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1903 mips_ase_mask (unsigned int flags
)
1907 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1908 if (flags
& mips_ase_groups
[i
])
1909 flags
|= mips_ase_groups
[i
];
1913 /* Check whether the current ISA supports ASE. Issue a warning if
1917 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1921 static unsigned int warned_isa
;
1922 static unsigned int warned_fp32
;
1924 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1925 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1927 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1928 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1929 && (warned_isa
& ase
->flags
) != ase
->flags
)
1931 warned_isa
|= ase
->flags
;
1932 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1933 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1935 as_warn (_("The %d-bit %s architecture does not support the"
1936 " `%s' extension"), size
, base
, ase
->name
);
1938 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1939 ase
->name
, base
, size
, min_rev
);
1941 if ((ase
->flags
& FP64_ASES
)
1943 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1945 warned_fp32
|= ase
->flags
;
1946 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1950 /* Check all enabled ASEs to see whether they are supported by the
1951 chosen architecture. */
1954 mips_check_isa_supports_ases (void)
1956 unsigned int i
, mask
;
1958 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1960 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1961 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1962 mips_check_isa_supports_ase (&mips_ases
[i
]);
1966 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1967 that were affected. */
1970 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1974 mask
= mips_ase_mask (ase
->flags
);
1975 mips_opts
.ase
&= ~mask
;
1977 mips_opts
.ase
|= ase
->flags
;
1981 /* Return the ASE called NAME, or null if none. */
1983 static const struct mips_ase
*
1984 mips_lookup_ase (const char *name
)
1988 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1989 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1990 return &mips_ases
[i
];
1994 /* Return the length of a microMIPS instruction in bytes. If bits of
1995 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1996 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1997 major opcode) will require further modifications to the opcode
2000 static inline unsigned int
2001 micromips_insn_length (const struct mips_opcode
*mo
)
2003 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2006 /* Return the length of MIPS16 instruction OPCODE. */
2008 static inline unsigned int
2009 mips16_opcode_length (unsigned long opcode
)
2011 return (opcode
>> 16) == 0 ? 2 : 4;
2014 /* Return the length of instruction INSN. */
2016 static inline unsigned int
2017 insn_length (const struct mips_cl_insn
*insn
)
2019 if (mips_opts
.micromips
)
2020 return micromips_insn_length (insn
->insn_mo
);
2021 else if (mips_opts
.mips16
)
2022 return mips16_opcode_length (insn
->insn_opcode
);
2027 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2030 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2035 insn
->insn_opcode
= mo
->match
;
2038 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2039 insn
->fixp
[i
] = NULL
;
2040 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2041 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2042 insn
->mips16_absolute_jump_p
= 0;
2043 insn
->complete_p
= 0;
2044 insn
->cleared_p
= 0;
2047 /* Install UVAL as the value of OPERAND in INSN. */
2050 insn_insert_operand (struct mips_cl_insn
*insn
,
2051 const struct mips_operand
*operand
, unsigned int uval
)
2053 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2056 /* Record the current MIPS16/microMIPS mode in now_seg. */
2059 mips_record_compressed_mode (void)
2061 segment_info_type
*si
;
2063 si
= seg_info (now_seg
);
2064 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2065 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2066 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2067 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2070 /* Read a standard MIPS instruction from BUF. */
2072 static unsigned long
2073 read_insn (char *buf
)
2075 if (target_big_endian
)
2076 return bfd_getb32 ((bfd_byte
*) buf
);
2078 return bfd_getl32 ((bfd_byte
*) buf
);
2081 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2085 write_insn (char *buf
, unsigned int insn
)
2087 md_number_to_chars (buf
, insn
, 4);
2091 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2092 has length LENGTH. */
2094 static unsigned long
2095 read_compressed_insn (char *buf
, unsigned int length
)
2101 for (i
= 0; i
< length
; i
+= 2)
2104 if (target_big_endian
)
2105 insn
|= bfd_getb16 ((char *) buf
);
2107 insn
|= bfd_getl16 ((char *) buf
);
2113 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2114 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2117 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2121 for (i
= 0; i
< length
; i
+= 2)
2122 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2123 return buf
+ length
;
2126 /* Install INSN at the location specified by its "frag" and "where" fields. */
2129 install_insn (const struct mips_cl_insn
*insn
)
2131 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2132 if (HAVE_CODE_COMPRESSION
)
2133 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2135 write_insn (f
, insn
->insn_opcode
);
2136 mips_record_compressed_mode ();
2139 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2140 and install the opcode in the new location. */
2143 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2148 insn
->where
= where
;
2149 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2150 if (insn
->fixp
[i
] != NULL
)
2152 insn
->fixp
[i
]->fx_frag
= frag
;
2153 insn
->fixp
[i
]->fx_where
= where
;
2155 install_insn (insn
);
2158 /* Add INSN to the end of the output. */
2161 add_fixed_insn (struct mips_cl_insn
*insn
)
2163 char *f
= frag_more (insn_length (insn
));
2164 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2167 /* Start a variant frag and move INSN to the start of the variant part,
2168 marking it as fixed. The other arguments are as for frag_var. */
2171 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2172 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2174 frag_grow (max_chars
);
2175 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2177 frag_var (rs_machine_dependent
, max_chars
, var
,
2178 subtype
, symbol
, offset
, NULL
);
2181 /* Insert N copies of INSN into the history buffer, starting at
2182 position FIRST. Neither FIRST nor N need to be clipped. */
2185 insert_into_history (unsigned int first
, unsigned int n
,
2186 const struct mips_cl_insn
*insn
)
2188 if (mips_relax
.sequence
!= 2)
2192 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2194 history
[i
] = history
[i
- n
];
2200 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2201 the idea is to make it obvious at a glance that each errata is
2205 init_vr4120_conflicts (void)
2207 #define CONFLICT(FIRST, SECOND) \
2208 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2210 /* Errata 21 - [D]DIV[U] after [D]MACC */
2211 CONFLICT (MACC
, DIV
);
2212 CONFLICT (DMACC
, DIV
);
2214 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2215 CONFLICT (DMULT
, DMULT
);
2216 CONFLICT (DMULT
, DMACC
);
2217 CONFLICT (DMACC
, DMULT
);
2218 CONFLICT (DMACC
, DMACC
);
2220 /* Errata 24 - MT{LO,HI} after [D]MACC */
2221 CONFLICT (MACC
, MTHILO
);
2222 CONFLICT (DMACC
, MTHILO
);
2224 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2225 instruction is executed immediately after a MACC or DMACC
2226 instruction, the result of [either instruction] is incorrect." */
2227 CONFLICT (MACC
, MULT
);
2228 CONFLICT (MACC
, DMULT
);
2229 CONFLICT (DMACC
, MULT
);
2230 CONFLICT (DMACC
, DMULT
);
2232 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2233 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2234 DDIV or DDIVU instruction, the result of the MACC or
2235 DMACC instruction is incorrect.". */
2236 CONFLICT (DMULT
, MACC
);
2237 CONFLICT (DMULT
, DMACC
);
2238 CONFLICT (DIV
, MACC
);
2239 CONFLICT (DIV
, DMACC
);
2249 #define RTYPE_MASK 0x1ff00
2250 #define RTYPE_NUM 0x00100
2251 #define RTYPE_FPU 0x00200
2252 #define RTYPE_FCC 0x00400
2253 #define RTYPE_VEC 0x00800
2254 #define RTYPE_GP 0x01000
2255 #define RTYPE_CP0 0x02000
2256 #define RTYPE_PC 0x04000
2257 #define RTYPE_ACC 0x08000
2258 #define RTYPE_CCC 0x10000
2259 #define RNUM_MASK 0x000ff
2260 #define RWARN 0x80000
2262 #define GENERIC_REGISTER_NUMBERS \
2263 {"$0", RTYPE_NUM | 0}, \
2264 {"$1", RTYPE_NUM | 1}, \
2265 {"$2", RTYPE_NUM | 2}, \
2266 {"$3", RTYPE_NUM | 3}, \
2267 {"$4", RTYPE_NUM | 4}, \
2268 {"$5", RTYPE_NUM | 5}, \
2269 {"$6", RTYPE_NUM | 6}, \
2270 {"$7", RTYPE_NUM | 7}, \
2271 {"$8", RTYPE_NUM | 8}, \
2272 {"$9", RTYPE_NUM | 9}, \
2273 {"$10", RTYPE_NUM | 10}, \
2274 {"$11", RTYPE_NUM | 11}, \
2275 {"$12", RTYPE_NUM | 12}, \
2276 {"$13", RTYPE_NUM | 13}, \
2277 {"$14", RTYPE_NUM | 14}, \
2278 {"$15", RTYPE_NUM | 15}, \
2279 {"$16", RTYPE_NUM | 16}, \
2280 {"$17", RTYPE_NUM | 17}, \
2281 {"$18", RTYPE_NUM | 18}, \
2282 {"$19", RTYPE_NUM | 19}, \
2283 {"$20", RTYPE_NUM | 20}, \
2284 {"$21", RTYPE_NUM | 21}, \
2285 {"$22", RTYPE_NUM | 22}, \
2286 {"$23", RTYPE_NUM | 23}, \
2287 {"$24", RTYPE_NUM | 24}, \
2288 {"$25", RTYPE_NUM | 25}, \
2289 {"$26", RTYPE_NUM | 26}, \
2290 {"$27", RTYPE_NUM | 27}, \
2291 {"$28", RTYPE_NUM | 28}, \
2292 {"$29", RTYPE_NUM | 29}, \
2293 {"$30", RTYPE_NUM | 30}, \
2294 {"$31", RTYPE_NUM | 31}
2296 #define FPU_REGISTER_NAMES \
2297 {"$f0", RTYPE_FPU | 0}, \
2298 {"$f1", RTYPE_FPU | 1}, \
2299 {"$f2", RTYPE_FPU | 2}, \
2300 {"$f3", RTYPE_FPU | 3}, \
2301 {"$f4", RTYPE_FPU | 4}, \
2302 {"$f5", RTYPE_FPU | 5}, \
2303 {"$f6", RTYPE_FPU | 6}, \
2304 {"$f7", RTYPE_FPU | 7}, \
2305 {"$f8", RTYPE_FPU | 8}, \
2306 {"$f9", RTYPE_FPU | 9}, \
2307 {"$f10", RTYPE_FPU | 10}, \
2308 {"$f11", RTYPE_FPU | 11}, \
2309 {"$f12", RTYPE_FPU | 12}, \
2310 {"$f13", RTYPE_FPU | 13}, \
2311 {"$f14", RTYPE_FPU | 14}, \
2312 {"$f15", RTYPE_FPU | 15}, \
2313 {"$f16", RTYPE_FPU | 16}, \
2314 {"$f17", RTYPE_FPU | 17}, \
2315 {"$f18", RTYPE_FPU | 18}, \
2316 {"$f19", RTYPE_FPU | 19}, \
2317 {"$f20", RTYPE_FPU | 20}, \
2318 {"$f21", RTYPE_FPU | 21}, \
2319 {"$f22", RTYPE_FPU | 22}, \
2320 {"$f23", RTYPE_FPU | 23}, \
2321 {"$f24", RTYPE_FPU | 24}, \
2322 {"$f25", RTYPE_FPU | 25}, \
2323 {"$f26", RTYPE_FPU | 26}, \
2324 {"$f27", RTYPE_FPU | 27}, \
2325 {"$f28", RTYPE_FPU | 28}, \
2326 {"$f29", RTYPE_FPU | 29}, \
2327 {"$f30", RTYPE_FPU | 30}, \
2328 {"$f31", RTYPE_FPU | 31}
2330 #define FPU_CONDITION_CODE_NAMES \
2331 {"$fcc0", RTYPE_FCC | 0}, \
2332 {"$fcc1", RTYPE_FCC | 1}, \
2333 {"$fcc2", RTYPE_FCC | 2}, \
2334 {"$fcc3", RTYPE_FCC | 3}, \
2335 {"$fcc4", RTYPE_FCC | 4}, \
2336 {"$fcc5", RTYPE_FCC | 5}, \
2337 {"$fcc6", RTYPE_FCC | 6}, \
2338 {"$fcc7", RTYPE_FCC | 7}
2340 #define COPROC_CONDITION_CODE_NAMES \
2341 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2342 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2343 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2344 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2345 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2346 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2347 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2348 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2350 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2351 {"$a4", RTYPE_GP | 8}, \
2352 {"$a5", RTYPE_GP | 9}, \
2353 {"$a6", RTYPE_GP | 10}, \
2354 {"$a7", RTYPE_GP | 11}, \
2355 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2356 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2357 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2358 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2359 {"$t0", RTYPE_GP | 12}, \
2360 {"$t1", RTYPE_GP | 13}, \
2361 {"$t2", RTYPE_GP | 14}, \
2362 {"$t3", RTYPE_GP | 15}
2364 #define O32_SYMBOLIC_REGISTER_NAMES \
2365 {"$t0", RTYPE_GP | 8}, \
2366 {"$t1", RTYPE_GP | 9}, \
2367 {"$t2", RTYPE_GP | 10}, \
2368 {"$t3", RTYPE_GP | 11}, \
2369 {"$t4", RTYPE_GP | 12}, \
2370 {"$t5", RTYPE_GP | 13}, \
2371 {"$t6", RTYPE_GP | 14}, \
2372 {"$t7", RTYPE_GP | 15}, \
2373 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2374 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2375 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2376 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2378 /* Remaining symbolic register names */
2379 #define SYMBOLIC_REGISTER_NAMES \
2380 {"$zero", RTYPE_GP | 0}, \
2381 {"$at", RTYPE_GP | 1}, \
2382 {"$AT", RTYPE_GP | 1}, \
2383 {"$v0", RTYPE_GP | 2}, \
2384 {"$v1", RTYPE_GP | 3}, \
2385 {"$a0", RTYPE_GP | 4}, \
2386 {"$a1", RTYPE_GP | 5}, \
2387 {"$a2", RTYPE_GP | 6}, \
2388 {"$a3", RTYPE_GP | 7}, \
2389 {"$s0", RTYPE_GP | 16}, \
2390 {"$s1", RTYPE_GP | 17}, \
2391 {"$s2", RTYPE_GP | 18}, \
2392 {"$s3", RTYPE_GP | 19}, \
2393 {"$s4", RTYPE_GP | 20}, \
2394 {"$s5", RTYPE_GP | 21}, \
2395 {"$s6", RTYPE_GP | 22}, \
2396 {"$s7", RTYPE_GP | 23}, \
2397 {"$t8", RTYPE_GP | 24}, \
2398 {"$t9", RTYPE_GP | 25}, \
2399 {"$k0", RTYPE_GP | 26}, \
2400 {"$kt0", RTYPE_GP | 26}, \
2401 {"$k1", RTYPE_GP | 27}, \
2402 {"$kt1", RTYPE_GP | 27}, \
2403 {"$gp", RTYPE_GP | 28}, \
2404 {"$sp", RTYPE_GP | 29}, \
2405 {"$s8", RTYPE_GP | 30}, \
2406 {"$fp", RTYPE_GP | 30}, \
2407 {"$ra", RTYPE_GP | 31}
2409 #define MIPS16_SPECIAL_REGISTER_NAMES \
2410 {"$pc", RTYPE_PC | 0}
2412 #define MDMX_VECTOR_REGISTER_NAMES \
2413 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2414 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2415 {"$v2", RTYPE_VEC | 2}, \
2416 {"$v3", RTYPE_VEC | 3}, \
2417 {"$v4", RTYPE_VEC | 4}, \
2418 {"$v5", RTYPE_VEC | 5}, \
2419 {"$v6", RTYPE_VEC | 6}, \
2420 {"$v7", RTYPE_VEC | 7}, \
2421 {"$v8", RTYPE_VEC | 8}, \
2422 {"$v9", RTYPE_VEC | 9}, \
2423 {"$v10", RTYPE_VEC | 10}, \
2424 {"$v11", RTYPE_VEC | 11}, \
2425 {"$v12", RTYPE_VEC | 12}, \
2426 {"$v13", RTYPE_VEC | 13}, \
2427 {"$v14", RTYPE_VEC | 14}, \
2428 {"$v15", RTYPE_VEC | 15}, \
2429 {"$v16", RTYPE_VEC | 16}, \
2430 {"$v17", RTYPE_VEC | 17}, \
2431 {"$v18", RTYPE_VEC | 18}, \
2432 {"$v19", RTYPE_VEC | 19}, \
2433 {"$v20", RTYPE_VEC | 20}, \
2434 {"$v21", RTYPE_VEC | 21}, \
2435 {"$v22", RTYPE_VEC | 22}, \
2436 {"$v23", RTYPE_VEC | 23}, \
2437 {"$v24", RTYPE_VEC | 24}, \
2438 {"$v25", RTYPE_VEC | 25}, \
2439 {"$v26", RTYPE_VEC | 26}, \
2440 {"$v27", RTYPE_VEC | 27}, \
2441 {"$v28", RTYPE_VEC | 28}, \
2442 {"$v29", RTYPE_VEC | 29}, \
2443 {"$v30", RTYPE_VEC | 30}, \
2444 {"$v31", RTYPE_VEC | 31}
2446 #define MIPS_DSP_ACCUMULATOR_NAMES \
2447 {"$ac0", RTYPE_ACC | 0}, \
2448 {"$ac1", RTYPE_ACC | 1}, \
2449 {"$ac2", RTYPE_ACC | 2}, \
2450 {"$ac3", RTYPE_ACC | 3}
2452 static const struct regname reg_names
[] = {
2453 GENERIC_REGISTER_NUMBERS
,
2455 FPU_CONDITION_CODE_NAMES
,
2456 COPROC_CONDITION_CODE_NAMES
,
2458 /* The $txx registers depends on the abi,
2459 these will be added later into the symbol table from
2460 one of the tables below once mips_abi is set after
2461 parsing of arguments from the command line. */
2462 SYMBOLIC_REGISTER_NAMES
,
2464 MIPS16_SPECIAL_REGISTER_NAMES
,
2465 MDMX_VECTOR_REGISTER_NAMES
,
2466 MIPS_DSP_ACCUMULATOR_NAMES
,
2470 static const struct regname reg_names_o32
[] = {
2471 O32_SYMBOLIC_REGISTER_NAMES
,
2475 static const struct regname reg_names_n32n64
[] = {
2476 N32N64_SYMBOLIC_REGISTER_NAMES
,
2480 /* Check if S points at a valid register specifier according to TYPES.
2481 If so, then return 1, advance S to consume the specifier and store
2482 the register's number in REGNOP, otherwise return 0. */
2485 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2492 /* Find end of name. */
2494 if (is_name_beginner (*e
))
2496 while (is_part_of_name (*e
))
2499 /* Terminate name. */
2503 /* Look for a register symbol. */
2504 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2506 int r
= S_GET_VALUE (symbolP
);
2508 reg
= r
& RNUM_MASK
;
2509 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2510 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2511 reg
= (r
& RNUM_MASK
) - 2;
2513 /* Else see if this is a register defined in an itbl entry. */
2514 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2521 if (itbl_get_reg_val (n
, &r
))
2522 reg
= r
& RNUM_MASK
;
2525 /* Advance to next token if a register was recognised. */
2528 else if (types
& RWARN
)
2529 as_warn (_("Unrecognized register name `%s'"), *s
);
2537 /* Check if S points at a valid register list according to TYPES.
2538 If so, then return 1, advance S to consume the list and store
2539 the registers present on the list as a bitmask of ones in REGLISTP,
2540 otherwise return 0. A valid list comprises a comma-separated
2541 enumeration of valid single registers and/or dash-separated
2542 contiguous register ranges as determined by their numbers.
2544 As a special exception if one of s0-s7 registers is specified as
2545 the range's lower delimiter and s8 (fp) is its upper one, then no
2546 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2547 are selected; they have to be listed separately if needed. */
2550 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2552 unsigned int reglist
= 0;
2553 unsigned int lastregno
;
2554 bfd_boolean ok
= TRUE
;
2555 unsigned int regmask
;
2556 char *s_endlist
= *s
;
2560 while (reg_lookup (s
, types
, ®no
))
2566 ok
= reg_lookup (s
, types
, &lastregno
);
2567 if (ok
&& lastregno
< regno
)
2573 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2578 regmask
= 1 << lastregno
;
2579 regmask
= (regmask
<< 1) - 1;
2580 regmask
^= (1 << regno
) - 1;
2594 *reglistp
= reglist
;
2595 return ok
&& reglist
!= 0;
2599 mips_lookup_reg_pair (unsigned int regno1
, unsigned int regno2
,
2600 const unsigned int *map1
, const unsigned int *map2
,
2605 for (i
= 0; i
< count
; i
++)
2606 if (map1
[i
] == regno1
&& map2
[i
] == regno2
)
2611 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2612 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2615 is_opcode_valid (const struct mips_opcode
*mo
)
2617 int isa
= mips_opts
.isa
;
2618 int ase
= mips_opts
.ase
;
2622 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2623 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2624 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2625 ase
|= mips_ases
[i
].flags64
;
2627 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2630 /* Check whether the instruction or macro requires single-precision or
2631 double-precision floating-point support. Note that this information is
2632 stored differently in the opcode table for insns and macros. */
2633 if (mo
->pinfo
== INSN_MACRO
)
2635 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2636 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2640 fp_s
= mo
->pinfo
& FP_S
;
2641 fp_d
= mo
->pinfo
& FP_D
;
2644 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2647 if (fp_s
&& mips_opts
.soft_float
)
2653 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2654 selected ISA and architecture. */
2657 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2659 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2662 /* Return TRUE if the size of the microMIPS opcode MO matches one
2663 explicitly requested. Always TRUE in the standard MIPS mode. */
2666 is_size_valid (const struct mips_opcode
*mo
)
2668 if (!mips_opts
.micromips
)
2671 if (mips_opts
.insn32
)
2673 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2675 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2678 if (!forced_insn_length
)
2680 if (mo
->pinfo
== INSN_MACRO
)
2682 return forced_insn_length
== micromips_insn_length (mo
);
2685 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2686 of the preceding instruction. Always TRUE in the standard MIPS mode.
2688 We don't accept macros in 16-bit delay slots to avoid a case where
2689 a macro expansion fails because it relies on a preceding 32-bit real
2690 instruction to have matched and does not handle the operands correctly.
2691 The only macros that may expand to 16-bit instructions are JAL that
2692 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2693 and BGT (that likewise cannot be placed in a delay slot) that decay to
2694 a NOP. In all these cases the macros precede any corresponding real
2695 instruction definitions in the opcode table, so they will match in the
2696 second pass where the size of the delay slot is ignored and therefore
2697 produce correct code. */
2700 is_delay_slot_valid (const struct mips_opcode
*mo
)
2702 if (!mips_opts
.micromips
)
2705 if (mo
->pinfo
== INSN_MACRO
)
2706 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2707 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2708 && micromips_insn_length (mo
) != 4)
2710 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2711 && micromips_insn_length (mo
) != 2)
2717 /* For consistency checking, verify that all bits of OPCODE are
2718 specified either by the match/mask part of the instruction
2719 definition, or by the operand list. INSN_BITS says which
2720 bits of the instruction are significant and DECODE_OPERAND
2721 provides the mips_operand description of each operand. */
2724 validate_mips_insn (const struct mips_opcode
*opcode
,
2725 unsigned long insn_bits
,
2726 const struct mips_operand
*(*decode_operand
) (const char *))
2729 unsigned long used_bits
, doubled
, undefined
;
2730 const struct mips_operand
*operand
;
2732 if ((opcode
->mask
& opcode
->match
) != opcode
->match
)
2734 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2735 opcode
->name
, opcode
->args
);
2739 for (s
= opcode
->args
; *s
; ++s
)
2748 operand
= decode_operand (s
);
2751 as_bad (_("internal: unknown operand type: %s %s"),
2752 opcode
->name
, opcode
->args
);
2755 used_bits
|= ((1 << operand
->size
) - 1) << operand
->lsb
;
2756 if (operand
->type
== OP_MDMX_IMM_REG
)
2757 /* Bit 5 is the format selector (OB vs QH). The opcode table
2758 has separate entries for each format. */
2759 used_bits
&= ~(1 << (operand
->lsb
+ 5));
2760 /* Skip prefix characters. */
2761 if (*s
== '+' || *s
== 'm')
2765 doubled
= used_bits
& opcode
->mask
& insn_bits
;
2768 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2769 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
2772 used_bits
|= opcode
->mask
;
2773 undefined
= ~used_bits
& insn_bits
;
2776 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2777 undefined
, opcode
->name
, opcode
->args
);
2780 used_bits
&= ~insn_bits
;
2783 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2784 used_bits
, opcode
->name
, opcode
->args
);
2790 /* The microMIPS version of validate_mips_insn. */
2793 validate_micromips_insn (const struct mips_opcode
*opc
)
2795 unsigned long insn_bits
;
2796 unsigned long major
;
2797 unsigned int length
;
2799 length
= micromips_insn_length (opc
);
2800 if (length
!= 2 && length
!= 4)
2802 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2803 "%s %s"), length
, opc
->name
, opc
->args
);
2806 major
= opc
->match
>> (10 + 8 * (length
- 2));
2807 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
2808 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
2810 as_bad (_("Internal error: bad microMIPS opcode "
2811 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
2815 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2816 insn_bits
= 1 << 4 * length
;
2817 insn_bits
<<= 4 * length
;
2819 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
);
2822 /* This function is called once, at assembler startup time. It should set up
2823 all the tables, etc. that the MD part of the assembler will need. */
2828 const char *retval
= NULL
;
2832 if (mips_pic
!= NO_PIC
)
2834 if (g_switch_seen
&& g_switch_value
!= 0)
2835 as_bad (_("-G may not be used in position-independent code"));
2839 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2840 as_warn (_("Could not set architecture and machine"));
2842 op_hash
= hash_new ();
2844 for (i
= 0; i
< NUMOPCODES
;)
2846 const char *name
= mips_opcodes
[i
].name
;
2848 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2851 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2852 mips_opcodes
[i
].name
, retval
);
2853 /* Probably a memory allocation problem? Give up now. */
2854 as_fatal (_("Broken assembler. No assembly attempted."));
2858 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2860 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
2861 decode_mips_operand
))
2863 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2865 create_insn (&nop_insn
, mips_opcodes
+ i
);
2866 if (mips_fix_loongson2f_nop
)
2867 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2868 nop_insn
.fixed_p
= 1;
2873 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2876 mips16_op_hash
= hash_new ();
2879 while (i
< bfd_mips16_num_opcodes
)
2881 const char *name
= mips16_opcodes
[i
].name
;
2883 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2885 as_fatal (_("internal: can't hash `%s': %s"),
2886 mips16_opcodes
[i
].name
, retval
);
2889 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2890 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2891 != mips16_opcodes
[i
].match
))
2893 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2894 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2897 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2899 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2900 mips16_nop_insn
.fixed_p
= 1;
2904 while (i
< bfd_mips16_num_opcodes
2905 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2908 micromips_op_hash
= hash_new ();
2911 while (i
< bfd_micromips_num_opcodes
)
2913 const char *name
= micromips_opcodes
[i
].name
;
2915 retval
= hash_insert (micromips_op_hash
, name
,
2916 (void *) µmips_opcodes
[i
]);
2918 as_fatal (_("internal: can't hash `%s': %s"),
2919 micromips_opcodes
[i
].name
, retval
);
2921 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2923 struct mips_cl_insn
*micromips_nop_insn
;
2925 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2928 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2929 micromips_nop_insn
= µmips_nop16_insn
;
2930 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2931 micromips_nop_insn
= µmips_nop32_insn
;
2935 if (micromips_nop_insn
->insn_mo
== NULL
2936 && strcmp (name
, "nop") == 0)
2938 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2939 micromips_nop_insn
->fixed_p
= 1;
2942 while (++i
< bfd_micromips_num_opcodes
2943 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2947 as_fatal (_("Broken assembler. No assembly attempted."));
2949 /* We add all the general register names to the symbol table. This
2950 helps us detect invalid uses of them. */
2951 for (i
= 0; reg_names
[i
].name
; i
++)
2952 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2953 reg_names
[i
].num
, /* & RNUM_MASK, */
2954 &zero_address_frag
));
2956 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2957 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2958 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2959 &zero_address_frag
));
2961 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2962 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2963 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2964 &zero_address_frag
));
2966 mips_no_prev_insn ();
2969 mips_cprmask
[0] = 0;
2970 mips_cprmask
[1] = 0;
2971 mips_cprmask
[2] = 0;
2972 mips_cprmask
[3] = 0;
2974 /* set the default alignment for the text section (2**2) */
2975 record_alignment (text_section
, 2);
2977 bfd_set_gp_size (stdoutput
, g_switch_value
);
2979 /* On a native system other than VxWorks, sections must be aligned
2980 to 16 byte boundaries. When configured for an embedded ELF
2981 target, we don't bother. */
2982 if (strncmp (TARGET_OS
, "elf", 3) != 0
2983 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2985 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2986 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2987 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2990 /* Create a .reginfo section for register masks and a .mdebug
2991 section for debugging information. */
2999 subseg
= now_subseg
;
3001 /* The ABI says this section should be loaded so that the
3002 running program can access it. However, we don't load it
3003 if we are configured for an embedded target */
3004 flags
= SEC_READONLY
| SEC_DATA
;
3005 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3006 flags
|= SEC_ALLOC
| SEC_LOAD
;
3008 if (mips_abi
!= N64_ABI
)
3010 sec
= subseg_new (".reginfo", (subsegT
) 0);
3012 bfd_set_section_flags (stdoutput
, sec
, flags
);
3013 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3015 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3019 /* The 64-bit ABI uses a .MIPS.options section rather than
3020 .reginfo section. */
3021 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3022 bfd_set_section_flags (stdoutput
, sec
, flags
);
3023 bfd_set_section_alignment (stdoutput
, sec
, 3);
3025 /* Set up the option header. */
3027 Elf_Internal_Options opthdr
;
3030 opthdr
.kind
= ODK_REGINFO
;
3031 opthdr
.size
= (sizeof (Elf_External_Options
)
3032 + sizeof (Elf64_External_RegInfo
));
3035 f
= frag_more (sizeof (Elf_External_Options
));
3036 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3037 (Elf_External_Options
*) f
);
3039 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3043 if (ECOFF_DEBUGGING
)
3045 sec
= subseg_new (".mdebug", (subsegT
) 0);
3046 (void) bfd_set_section_flags (stdoutput
, sec
,
3047 SEC_HAS_CONTENTS
| SEC_READONLY
);
3048 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3050 else if (mips_flag_pdr
)
3052 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3053 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3054 SEC_READONLY
| SEC_RELOC
3056 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3059 subseg_set (seg
, subseg
);
3062 if (! ECOFF_DEBUGGING
)
3065 if (mips_fix_vr4120
)
3066 init_vr4120_conflicts ();
3072 mips_emit_delays ();
3073 if (! ECOFF_DEBUGGING
)
3078 md_assemble (char *str
)
3080 struct mips_cl_insn insn
;
3081 bfd_reloc_code_real_type unused_reloc
[3]
3082 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3084 imm_expr
.X_op
= O_absent
;
3085 imm2_expr
.X_op
= O_absent
;
3086 offset_expr
.X_op
= O_absent
;
3087 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3088 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3089 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3091 mips_mark_labels ();
3092 mips_assembling_insn
= TRUE
;
3094 if (mips_opts
.mips16
)
3095 mips16_ip (str
, &insn
);
3098 mips_ip (str
, &insn
);
3099 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3100 str
, insn
.insn_opcode
));
3104 as_bad ("%s `%s'", insn_error
, str
);
3105 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3108 if (mips_opts
.mips16
)
3109 mips16_macro (&insn
);
3116 if (offset_expr
.X_op
!= O_absent
)
3117 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3119 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3122 mips_assembling_insn
= FALSE
;
3125 /* Convenience functions for abstracting away the differences between
3126 MIPS16 and non-MIPS16 relocations. */
3128 static inline bfd_boolean
3129 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3133 case BFD_RELOC_MIPS16_JMP
:
3134 case BFD_RELOC_MIPS16_GPREL
:
3135 case BFD_RELOC_MIPS16_GOT16
:
3136 case BFD_RELOC_MIPS16_CALL16
:
3137 case BFD_RELOC_MIPS16_HI16_S
:
3138 case BFD_RELOC_MIPS16_HI16
:
3139 case BFD_RELOC_MIPS16_LO16
:
3147 static inline bfd_boolean
3148 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3152 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3153 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3154 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3155 case BFD_RELOC_MICROMIPS_GPREL16
:
3156 case BFD_RELOC_MICROMIPS_JMP
:
3157 case BFD_RELOC_MICROMIPS_HI16
:
3158 case BFD_RELOC_MICROMIPS_HI16_S
:
3159 case BFD_RELOC_MICROMIPS_LO16
:
3160 case BFD_RELOC_MICROMIPS_LITERAL
:
3161 case BFD_RELOC_MICROMIPS_GOT16
:
3162 case BFD_RELOC_MICROMIPS_CALL16
:
3163 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3164 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3165 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3166 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3167 case BFD_RELOC_MICROMIPS_SUB
:
3168 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3169 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3170 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3171 case BFD_RELOC_MICROMIPS_HIGHEST
:
3172 case BFD_RELOC_MICROMIPS_HIGHER
:
3173 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3174 case BFD_RELOC_MICROMIPS_JALR
:
3182 static inline bfd_boolean
3183 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3185 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3188 static inline bfd_boolean
3189 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3191 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3192 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3195 static inline bfd_boolean
3196 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3198 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3199 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3202 static inline bfd_boolean
3203 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3205 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3206 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3209 static inline bfd_boolean
3210 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3212 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3215 static inline bfd_boolean
3216 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3218 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3219 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3222 /* Return true if RELOC is a PC-relative relocation that does not have
3223 full address range. */
3225 static inline bfd_boolean
3226 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3230 case BFD_RELOC_16_PCREL_S2
:
3231 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3232 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3233 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3236 case BFD_RELOC_32_PCREL
:
3237 return HAVE_64BIT_ADDRESSES
;
3244 /* Return true if the given relocation might need a matching %lo().
3245 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3246 need a matching %lo() when applied to local symbols. */
3248 static inline bfd_boolean
3249 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3251 return (HAVE_IN_PLACE_ADDENDS
3252 && (hi16_reloc_p (reloc
)
3253 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3254 all GOT16 relocations evaluate to "G". */
3255 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3258 /* Return the type of %lo() reloc needed by RELOC, given that
3259 reloc_needs_lo_p. */
3261 static inline bfd_reloc_code_real_type
3262 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3264 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3265 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3269 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3272 static inline bfd_boolean
3273 fixup_has_matching_lo_p (fixS
*fixp
)
3275 return (fixp
->fx_next
!= NULL
3276 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3277 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3278 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3281 /* This function returns true if modifying a register requires a
3285 reg_needs_delay (unsigned int reg
)
3287 unsigned long prev_pinfo
;
3289 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3290 if (! mips_opts
.noreorder
3291 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3292 && ! gpr_interlocks
)
3293 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3294 && ! cop_interlocks
)))
3296 /* A load from a coprocessor or from memory. All load delays
3297 delay the use of general register rt for one instruction. */
3298 /* Itbl support may require additional care here. */
3299 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3300 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3307 /* Move all labels in LABELS to the current insertion point. TEXT_P
3308 says whether the labels refer to text or data. */
3311 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3313 struct insn_label_list
*l
;
3316 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3318 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3319 symbol_set_frag (l
->label
, frag_now
);
3320 val
= (valueT
) frag_now_fix ();
3321 /* MIPS16/microMIPS text labels are stored as odd. */
3322 if (text_p
&& HAVE_CODE_COMPRESSION
)
3324 S_SET_VALUE (l
->label
, val
);
3328 /* Move all labels in insn_labels to the current insertion point
3329 and treat them as text labels. */
3332 mips_move_text_labels (void)
3334 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3338 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3340 bfd_boolean linkonce
= FALSE
;
3341 segT symseg
= S_GET_SEGMENT (sym
);
3343 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3345 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3347 /* The GNU toolchain uses an extension for ELF: a section
3348 beginning with the magic string .gnu.linkonce is a
3349 linkonce section. */
3350 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3351 sizeof ".gnu.linkonce" - 1) == 0)
3357 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3358 linker to handle them specially, such as generating jalx instructions
3359 when needed. We also make them odd for the duration of the assembly,
3360 in order to generate the right sort of code. We will make them even
3361 in the adjust_symtab routine, while leaving them marked. This is
3362 convenient for the debugger and the disassembler. The linker knows
3363 to make them odd again. */
3366 mips_compressed_mark_label (symbolS
*label
)
3368 gas_assert (HAVE_CODE_COMPRESSION
);
3370 if (mips_opts
.mips16
)
3371 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3373 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3374 if ((S_GET_VALUE (label
) & 1) == 0
3375 /* Don't adjust the address if the label is global or weak, or
3376 in a link-once section, since we'll be emitting symbol reloc
3377 references to it which will be patched up by the linker, and
3378 the final value of the symbol may or may not be MIPS16/microMIPS. */
3379 && !S_IS_WEAK (label
)
3380 && !S_IS_EXTERNAL (label
)
3381 && !s_is_linkonce (label
, now_seg
))
3382 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3385 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3388 mips_compressed_mark_labels (void)
3390 struct insn_label_list
*l
;
3392 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3393 mips_compressed_mark_label (l
->label
);
3396 /* End the current frag. Make it a variant frag and record the
3400 relax_close_frag (void)
3402 mips_macro_warning
.first_frag
= frag_now
;
3403 frag_var (rs_machine_dependent
, 0, 0,
3404 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3405 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3407 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3408 mips_relax
.first_fixup
= 0;
3411 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3412 See the comment above RELAX_ENCODE for more details. */
3415 relax_start (symbolS
*symbol
)
3417 gas_assert (mips_relax
.sequence
== 0);
3418 mips_relax
.sequence
= 1;
3419 mips_relax
.symbol
= symbol
;
3422 /* Start generating the second version of a relaxable sequence.
3423 See the comment above RELAX_ENCODE for more details. */
3428 gas_assert (mips_relax
.sequence
== 1);
3429 mips_relax
.sequence
= 2;
3432 /* End the current relaxable sequence. */
3437 gas_assert (mips_relax
.sequence
== 2);
3438 relax_close_frag ();
3439 mips_relax
.sequence
= 0;
3442 /* Return true if IP is a delayed branch or jump. */
3444 static inline bfd_boolean
3445 delayed_branch_p (const struct mips_cl_insn
*ip
)
3447 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3448 | INSN_COND_BRANCH_DELAY
3449 | INSN_COND_BRANCH_LIKELY
)) != 0;
3452 /* Return true if IP is a compact branch or jump. */
3454 static inline bfd_boolean
3455 compact_branch_p (const struct mips_cl_insn
*ip
)
3457 if (mips_opts
.mips16
)
3458 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3459 | MIPS16_INSN_COND_BRANCH
)) != 0;
3461 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3462 | INSN2_COND_BRANCH
)) != 0;
3465 /* Return true if IP is an unconditional branch or jump. */
3467 static inline bfd_boolean
3468 uncond_branch_p (const struct mips_cl_insn
*ip
)
3470 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3471 || (mips_opts
.mips16
3472 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3473 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3476 /* Return true if IP is a branch-likely instruction. */
3478 static inline bfd_boolean
3479 branch_likely_p (const struct mips_cl_insn
*ip
)
3481 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3484 /* Return the type of nop that should be used to fill the delay slot
3485 of delayed branch IP. */
3487 static struct mips_cl_insn
*
3488 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3490 if (mips_opts
.micromips
3491 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3492 return µmips_nop32_insn
;
3496 /* Return the mask of core registers that IP reads or writes. */
3499 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3501 unsigned long pinfo2
;
3505 pinfo2
= ip
->insn_mo
->pinfo2
;
3506 if (mips_opts
.micromips
)
3508 if (pinfo2
& INSN2_MOD_GPR_MD
)
3509 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3510 if (pinfo2
& INSN2_MOD_GPR_MF
)
3511 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3512 if (pinfo2
& INSN2_MOD_SP
)
3518 /* Return the mask of core registers that IP reads. */
3521 gpr_read_mask (const struct mips_cl_insn
*ip
)
3523 unsigned long pinfo
, pinfo2
;
3526 mask
= gpr_mod_mask (ip
);
3527 pinfo
= ip
->insn_mo
->pinfo
;
3528 pinfo2
= ip
->insn_mo
->pinfo2
;
3529 if (mips_opts
.mips16
)
3531 if (pinfo
& MIPS16_INSN_READ_X
)
3532 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3533 if (pinfo
& MIPS16_INSN_READ_Y
)
3534 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3535 if (pinfo
& MIPS16_INSN_READ_T
)
3537 if (pinfo
& MIPS16_INSN_READ_SP
)
3539 if (pinfo
& MIPS16_INSN_READ_31
)
3541 if (pinfo
& MIPS16_INSN_READ_Z
)
3542 mask
|= 1 << (mips16_to_32_reg_map
3543 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3544 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3545 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3549 if (pinfo2
& INSN2_READ_GPR_D
)
3550 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3551 if (pinfo
& INSN_READ_GPR_T
)
3552 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3553 if (pinfo
& INSN_READ_GPR_S
)
3554 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3555 if (pinfo2
& INSN2_READ_GP
)
3557 if (pinfo2
& INSN2_READ_GPR_31
)
3559 if (pinfo2
& INSN2_READ_GPR_Z
)
3560 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3562 if (mips_opts
.micromips
)
3564 if (pinfo2
& INSN2_READ_GPR_MC
)
3565 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3566 if (pinfo2
& INSN2_READ_GPR_ME
)
3567 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3568 if (pinfo2
& INSN2_READ_GPR_MG
)
3569 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3570 if (pinfo2
& INSN2_READ_GPR_MJ
)
3571 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3572 if (pinfo2
& INSN2_READ_GPR_MMN
)
3574 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3575 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3577 if (pinfo2
& INSN2_READ_GPR_MP
)
3578 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3579 if (pinfo2
& INSN2_READ_GPR_MQ
)
3580 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3582 /* Don't include register 0. */
3586 /* Return the mask of core registers that IP writes. */
3589 gpr_write_mask (const struct mips_cl_insn
*ip
)
3591 unsigned long pinfo
, pinfo2
;
3594 mask
= gpr_mod_mask (ip
);
3595 pinfo
= ip
->insn_mo
->pinfo
;
3596 pinfo2
= ip
->insn_mo
->pinfo2
;
3597 if (mips_opts
.mips16
)
3599 if (pinfo
& MIPS16_INSN_WRITE_X
)
3600 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3601 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3602 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3603 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3604 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3605 if (pinfo
& MIPS16_INSN_WRITE_T
)
3607 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3609 if (pinfo
& MIPS16_INSN_WRITE_31
)
3611 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3612 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3616 if (pinfo
& INSN_WRITE_GPR_D
)
3617 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3618 if (pinfo
& INSN_WRITE_GPR_T
)
3619 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3620 if (pinfo
& INSN_WRITE_GPR_S
)
3621 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3622 if (pinfo
& INSN_WRITE_GPR_31
)
3624 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3625 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3627 if (mips_opts
.micromips
)
3629 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3630 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3631 if (pinfo2
& INSN2_WRITE_GPR_MH
)
3633 mask
|= 1 << micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
3634 mask
|= 1 << micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
3636 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3637 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3638 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3639 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3641 /* Don't include register 0. */
3645 /* Return the mask of floating-point registers that IP reads. */
3648 fpr_read_mask (const struct mips_cl_insn
*ip
)
3650 unsigned long pinfo
, pinfo2
;
3654 pinfo
= ip
->insn_mo
->pinfo
;
3655 pinfo2
= ip
->insn_mo
->pinfo2
;
3656 if (!mips_opts
.mips16
)
3658 if (pinfo2
& INSN2_READ_FPR_D
)
3659 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3660 if (pinfo
& INSN_READ_FPR_S
)
3661 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3662 if (pinfo
& INSN_READ_FPR_T
)
3663 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3664 if (pinfo
& INSN_READ_FPR_R
)
3665 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3666 if (pinfo2
& INSN2_READ_FPR_Z
)
3667 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3669 /* Conservatively treat all operands to an FP_D instruction are doubles.
3670 (This is overly pessimistic for things like cvt.d.s.) */
3671 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3676 /* Return the mask of floating-point registers that IP writes. */
3679 fpr_write_mask (const struct mips_cl_insn
*ip
)
3681 unsigned long pinfo
, pinfo2
;
3685 pinfo
= ip
->insn_mo
->pinfo
;
3686 pinfo2
= ip
->insn_mo
->pinfo2
;
3687 if (!mips_opts
.mips16
)
3689 if (pinfo
& INSN_WRITE_FPR_D
)
3690 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3691 if (pinfo
& INSN_WRITE_FPR_S
)
3692 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3693 if (pinfo
& INSN_WRITE_FPR_T
)
3694 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3695 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3696 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3698 /* Conservatively treat all operands to an FP_D instruction are doubles.
3699 (This is overly pessimistic for things like cvt.s.d.) */
3700 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3705 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3706 Check whether that is allowed. */
3709 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
3711 const char *s
= insn
->name
;
3713 if (insn
->pinfo
== INSN_MACRO
)
3714 /* Let a macro pass, we'll catch it later when it is expanded. */
3717 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
3719 /* Allow odd registers for single-precision ops. */
3720 switch (insn
->pinfo
& (FP_S
| FP_D
))
3731 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3732 s
= strchr (insn
->name
, '.');
3733 if (s
!= NULL
&& opnum
== 2)
3734 s
= strchr (s
+ 1, '.');
3735 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
3738 /* Single-precision coprocessor loads and moves are OK too. */
3739 if ((insn
->pinfo
& FP_S
)
3740 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
3741 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
3748 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3749 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3750 this operand is normally printed in hex or decimal. */
3753 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
3754 offsetT val
, int min_val
, int max_val
,
3755 bfd_boolean print_hex
)
3757 if (print_hex
&& val
>= 0)
3758 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3760 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3762 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3764 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3766 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3768 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3771 /* Report an invalid combination of position and size operands for a bitfield
3772 operation. POS and SIZE are the values that were given. */
3775 report_bad_field (offsetT pos
, offsetT size
)
3777 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3778 (unsigned long) pos
, (unsigned long) size
);
3781 /* Information about an instruction argument that we're trying to match. */
3782 struct mips_arg_info
3784 /* The instruction so far. */
3785 struct mips_cl_insn
*insn
;
3787 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3790 /* The 1-based argument number, for error reporting. This does not
3791 count elided optional registers, etc.. */
3794 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3795 unsigned int last_regno
;
3797 /* If the first operand was an OP_REG, this is the register that it
3798 specified, otherwise it is ILLEGAL_REG. */
3799 unsigned int dest_regno
;
3801 /* The value of the last OP_INT operand. Only used for OP_MSB,
3802 where it gives the lsb position. */
3803 unsigned int last_op_int
;
3805 /* If true, match routines should silently reject invalid arguments.
3806 If false, match routines can accept invalid arguments as long as
3807 they report an appropriate error. They still have the option of
3808 silently rejecting arguments, in which case a generic "Invalid operands"
3809 style of error will be used instead. */
3810 bfd_boolean soft_match
;
3812 /* If true, the OP_INT match routine should treat plain symbolic operands
3813 as if a relocation operator like %lo(...) had been used. This is only
3814 ever true if the operand can be relocated. */
3815 bfd_boolean allow_nonconst
;
3817 /* When true, the OP_INT match routine should allow unsigned N-bit
3818 arguments to be used where a signed N-bit operand is expected. */
3819 bfd_boolean lax_max
;
3821 /* When true, the OP_REG match routine should assume that another operand
3822 appears after this one. It should fail the match if the register it
3823 sees is at the end of the argument list. */
3824 bfd_boolean optional_reg
;
3826 /* True if a reference to the current AT register was seen. */
3827 bfd_boolean seen_at
;
3830 /* Match a constant integer at S for ARG. Return null if the match failed.
3831 Otherwise return the end of the matched string and store the constant value
3832 in *VALUE. In the latter case, use FALLBACK as the value if the match
3833 succeeded with an error. */
3836 match_const_int (struct mips_arg_info
*arg
, char *s
, offsetT
*value
,
3840 bfd_reloc_code_real_type r
[3];
3843 num_relocs
= my_getSmallExpression (&ex
, r
, s
);
3844 if (*s
== '(' && ex
.X_op
== O_register
)
3846 /* Assume that the constant has been elided and that S is a base
3847 register. The rest of the match will fail if the assumption
3848 turns out to be wrong. */
3853 if (num_relocs
== 0 && ex
.X_op
== O_constant
)
3854 *value
= ex
.X_add_number
;
3857 /* If we got a register rather than an expression, the default
3858 "Invalid operands" style of error seems more appropriate. */
3859 if (arg
->soft_match
|| ex
.X_op
== O_register
)
3861 as_bad (_("Operand %d of `%s' must be constant"),
3862 arg
->argnum
, arg
->insn
->insn_mo
->name
);
3868 /* Return the RTYPE_* flags for a register operand of type TYPE that
3869 appears in instruction OPCODE. */
3872 convert_reg_type (const struct mips_opcode
*opcode
,
3873 enum mips_reg_operand_type type
)
3878 return RTYPE_NUM
| RTYPE_GP
;
3881 /* Allow vector register names for MDMX if the instruction is a 64-bit
3882 FPR load, store or move (including moves to and from GPRs). */
3883 if ((mips_opts
.ase
& ASE_MDMX
)
3884 && (opcode
->pinfo
& FP_D
)
3885 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
3886 | INSN_COPROC_MEMORY_DELAY
3887 | INSN_LOAD_COPROC_DELAY
3888 | INSN_LOAD_MEMORY_DELAY
3889 | INSN_STORE_MEMORY
)))
3890 return RTYPE_FPU
| RTYPE_VEC
;
3894 if (opcode
->pinfo
& (FP_D
| FP_S
))
3895 return RTYPE_CCC
| RTYPE_FCC
;
3899 if (opcode
->membership
& INSN_5400
)
3901 return RTYPE_FPU
| RTYPE_VEC
;
3907 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
3908 return RTYPE_NUM
| RTYPE_CP0
;
3917 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
3920 check_regno (struct mips_arg_info
*arg
,
3921 enum mips_reg_operand_type type
, unsigned int regno
)
3923 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
3924 arg
->seen_at
= TRUE
;
3926 if (type
== OP_REG_FP
3929 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
3930 as_warn (_("Float register should be even, was %d"), regno
);
3932 if (type
== OP_REG_CCC
)
3937 name
= arg
->insn
->insn_mo
->name
;
3938 length
= strlen (name
);
3939 if ((regno
& 1) != 0
3940 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
3941 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
3942 as_warn (_("Condition code register should be even for %s, was %d"),
3945 if ((regno
& 3) != 0
3946 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
3947 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
3952 /* OP_INT matcher. */
3955 match_int_operand (struct mips_arg_info
*arg
,
3956 const struct mips_operand
*operand_base
, char *s
)
3958 const struct mips_int_operand
*operand
;
3959 unsigned int uval
, mask
;
3960 int min_val
, max_val
, factor
;
3962 bfd_boolean print_hex
;
3964 operand
= (const struct mips_int_operand
*) operand_base
;
3965 factor
= 1 << operand
->shift
;
3966 mask
= (1 << operand_base
->size
) - 1;
3967 max_val
= (operand
->max_val
+ operand
->bias
) << operand
->shift
;
3968 min_val
= max_val
- (mask
<< operand
->shift
);
3970 max_val
= mask
<< operand
->shift
;
3972 if (operand_base
->lsb
== 0
3973 && operand_base
->size
== 16
3974 && operand
->shift
== 0
3975 && operand
->bias
== 0
3976 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
3978 /* The operand can be relocated. */
3979 offset_reloc
[0] = BFD_RELOC_LO16
;
3980 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3981 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3982 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) > 0)
3983 /* Relocation operators were used. Accept the arguent and
3984 leave the relocation value in offset_expr and offset_relocs
3985 for the caller to process. */
3987 if (*s
== '(' && offset_expr
.X_op
== O_register
)
3988 /* Assume that the constant has been elided and that S is a base
3989 register. The rest of the match will fail if the assumption
3990 turns out to be wrong. */
3995 if (offset_expr
.X_op
!= O_constant
)
3996 /* If non-constant operands are allowed then leave them for
3997 the caller to process, otherwise fail the match. */
3998 return arg
->allow_nonconst
? s
: 0;
3999 sval
= offset_expr
.X_add_number
;
4001 /* Clear the global state; we're going to install the operand
4003 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4004 offset_expr
.X_op
= O_absent
;
4008 s
= match_const_int (arg
, s
, &sval
, min_val
);
4013 arg
->last_op_int
= sval
;
4015 /* Check the range. If there's a problem, record the lowest acceptable
4016 value in arg->last_op_int in order to prevent an unhelpful error
4019 Bit counts have traditionally been printed in hex by the disassembler
4020 but printed as decimal in error messages. Only resort to hex if
4021 the operand is bigger than 6 bits. */
4022 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4023 if (sval
< min_val
|| sval
> max_val
)
4025 if (arg
->soft_match
)
4027 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4029 arg
->last_op_int
= min_val
;
4031 else if (sval
% factor
)
4033 if (arg
->soft_match
)
4035 as_bad (print_hex
&& sval
>= 0
4036 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4037 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4038 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4039 (unsigned long) sval
);
4040 arg
->last_op_int
= min_val
;
4043 uval
= (unsigned int) sval
>> operand
->shift
;
4044 uval
-= operand
->bias
;
4046 /* Handle -mfix-cn63xxp1. */
4048 && mips_fix_cn63xxp1
4049 && !mips_opts
.micromips
4050 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4065 /* The rest must be changed to 28. */
4070 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4074 /* OP_MAPPED_INT matcher. */
4077 match_mapped_int_operand (struct mips_arg_info
*arg
,
4078 const struct mips_operand
*operand_base
, char *s
)
4080 const struct mips_mapped_int_operand
*operand
;
4081 unsigned int uval
, num_vals
;
4084 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4085 s
= match_const_int (arg
, s
, &sval
, operand
->int_map
[0]);
4089 num_vals
= 1 << operand_base
->size
;
4090 for (uval
= 0; uval
< num_vals
; uval
++)
4091 if (operand
->int_map
[uval
] == sval
)
4093 if (uval
== num_vals
)
4096 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4100 /* OP_MSB matcher. */
4103 match_msb_operand (struct mips_arg_info
*arg
,
4104 const struct mips_operand
*operand_base
, char *s
)
4106 const struct mips_msb_operand
*operand
;
4107 int min_val
, max_val
, max_high
;
4108 offsetT size
, sval
, high
;
4110 operand
= (const struct mips_msb_operand
*) operand_base
;
4111 min_val
= operand
->bias
;
4112 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4113 max_high
= operand
->opsize
;
4115 s
= match_const_int (arg
, s
, &size
, 1);
4119 high
= size
+ arg
->last_op_int
;
4120 sval
= operand
->add_lsb
? high
: size
;
4122 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4124 if (arg
->soft_match
)
4126 report_bad_field (arg
->last_op_int
, size
);
4129 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4133 /* OP_REG matcher. */
4136 match_reg_operand (struct mips_arg_info
*arg
,
4137 const struct mips_operand
*operand_base
, char *s
)
4139 const struct mips_reg_operand
*operand
;
4140 unsigned int regno
, uval
, num_vals
, types
;
4142 operand
= (const struct mips_reg_operand
*) operand_base
;
4143 types
= convert_reg_type (arg
->insn
->insn_mo
, operand
->reg_type
);
4144 if (!reg_lookup (&s
, types
, ®no
))
4147 SKIP_SPACE_TABS (s
);
4148 if (arg
->optional_reg
&& *s
== 0)
4151 if (operand
->reg_map
)
4153 num_vals
= 1 << operand
->root
.size
;
4154 for (uval
= 0; uval
< num_vals
; uval
++)
4155 if (operand
->reg_map
[uval
] == regno
)
4157 if (num_vals
== uval
)
4163 check_regno (arg
, operand
->reg_type
, regno
);
4164 arg
->last_regno
= regno
;
4165 if (arg
->opnum
== 1)
4166 arg
->dest_regno
= regno
;
4167 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4171 /* OP_REG_PAIR matcher. */
4174 match_reg_pair_operand (struct mips_arg_info
*arg
,
4175 const struct mips_operand
*operand_base
, char *s
)
4177 const struct mips_reg_pair_operand
*operand
;
4178 unsigned int regno1
, regno2
, uval
, num_vals
, types
;
4180 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4181 types
= convert_reg_type (arg
->insn
->insn_mo
, operand
->reg_type
);
4183 if (!reg_lookup (&s
, types
, ®no1
))
4186 SKIP_SPACE_TABS (s
);
4191 if (!reg_lookup (&s
, types
, ®no2
))
4194 num_vals
= 1 << operand_base
->size
;
4195 for (uval
= 0; uval
< num_vals
; uval
++)
4196 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4198 if (uval
== num_vals
)
4201 check_regno (arg
, operand
->reg_type
, regno1
);
4202 check_regno (arg
, operand
->reg_type
, regno2
);
4203 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4207 /* OP_PCREL matcher. The caller chooses the relocation type. */
4210 match_pcrel_operand (char *s
)
4212 my_getExpression (&offset_expr
, s
);
4216 /* OP_PERF_REG matcher. */
4219 match_perf_reg_operand (struct mips_arg_info
*arg
,
4220 const struct mips_operand
*operand
, char *s
)
4224 s
= match_const_int (arg
, s
, &sval
, 0);
4230 || (mips_opts
.arch
== CPU_R5900
4231 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4232 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4234 if (arg
->soft_match
)
4236 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4239 insn_insert_operand (arg
->insn
, operand
, sval
);
4243 /* OP_ADDIUSP matcher. */
4246 match_addiusp_operand (struct mips_arg_info
*arg
,
4247 const struct mips_operand
*operand
, char *s
)
4252 s
= match_const_int (arg
, s
, &sval
, -256);
4260 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4263 uval
= (unsigned int) sval
;
4264 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4265 insn_insert_operand (arg
->insn
, operand
, uval
);
4269 /* OP_CLO_CLZ_DEST matcher. */
4272 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4273 const struct mips_operand
*operand
, char *s
)
4277 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
4280 check_regno (arg
, OP_REG_GP
, regno
);
4281 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4285 /* OP_LWM_SWM_LIST matcher. */
4288 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4289 const struct mips_operand
*operand
, char *s
)
4291 unsigned int reglist
, sregs
, ra
;
4293 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
4296 if (operand
->size
== 2)
4298 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4304 and any permutations of these. */
4305 if ((reglist
& 0xfff1ffff) != 0x80010000)
4308 sregs
= (reglist
>> 17) & 7;
4313 /* The list must include at least one of ra and s0-sN,
4314 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4315 which are $23 and $30 respectively.) E.g.:
4323 and any permutations of these. */
4324 if ((reglist
& 0x3f00ffff) != 0)
4327 ra
= (reglist
>> 27) & 0x10;
4328 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4331 if ((sregs
& -sregs
) != sregs
)
4334 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4338 /* OP_MDMX_IMM_REG matcher. */
4341 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4342 const struct mips_operand
*operand
, char *s
)
4344 unsigned int regno
, uval
, types
;
4346 const struct mips_opcode
*opcode
;
4348 /* The mips_opcode records whether this is an octobyte or quadhalf
4349 instruction. Start out with that bit in place. */
4350 opcode
= arg
->insn
->insn_mo
;
4351 uval
= mips_extract_operand (operand
, opcode
->match
);
4352 is_qh
= (uval
!= 0);
4354 types
= convert_reg_type (arg
->insn
->insn_mo
, OP_REG_VEC
);
4355 if (reg_lookup (&s
, types
, ®no
))
4357 if ((opcode
->membership
& INSN_5400
)
4358 && strcmp (opcode
->name
, "rzu.ob") == 0)
4360 if (arg
->soft_match
)
4362 as_bad (_("Operand %d of `%s' must be an immediate"),
4363 arg
->argnum
, opcode
->name
);
4366 /* Check whether this is a vector register or a broadcast of
4367 a single element. */
4368 SKIP_SPACE_TABS (s
);
4371 /* Read the element number. */
4375 SKIP_SPACE_TABS (s
);
4376 my_getExpression (&value
, s
);
4378 if (value
.X_op
!= O_constant
4379 || value
.X_add_number
< 0
4380 || value
.X_add_number
> (is_qh
? 3 : 7))
4382 if (arg
->soft_match
)
4384 as_bad (_("Invalid element selector"));
4385 value
.X_add_number
= 0;
4387 uval
|= (unsigned int) value
.X_add_number
<< (is_qh
? 2 : 1) << 5;
4388 SKIP_SPACE_TABS (s
);
4393 if (arg
->soft_match
)
4395 as_bad (_("Expecting ']' found '%s'"), s
);
4400 /* A full vector. */
4401 if ((opcode
->membership
& INSN_5400
)
4402 && (strcmp (opcode
->name
, "sll.ob") == 0
4403 || strcmp (opcode
->name
, "srl.ob") == 0))
4405 if (arg
->soft_match
)
4407 as_bad (_("Operand %d of `%s' must be scalar"),
4408 arg
->argnum
, opcode
->name
);
4412 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
4414 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
4416 check_regno (arg
, OP_REG_FP
, regno
);
4423 s
= match_const_int (arg
, s
, &sval
, 0);
4426 if (sval
< 0 || sval
> 31)
4428 if (arg
->soft_match
)
4430 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
4432 uval
|= (sval
& 31);
4434 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
4436 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
4438 insn_insert_operand (arg
->insn
, operand
, uval
);
4442 /* OP_PC matcher. */
4445 match_pc_operand (char *s
)
4447 if (strncmp (s
, "$pc", 3) != 0)
4450 SKIP_SPACE_TABS (s
);
4454 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4455 register that we need to match. */
4458 match_tied_reg_operand (struct mips_arg_info
*arg
, char *s
,
4459 unsigned int other_regno
)
4463 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
)
4464 || regno
!= other_regno
)
4466 SKIP_SPACE_TABS (s
);
4467 if (arg
->optional_reg
&& *s
== 0)
4472 /* S is the text seen for ARG. Match it against OPERAND. Return the end
4473 of the argument text if the match is successful, otherwise return null. */
4476 match_operand (struct mips_arg_info
*arg
,
4477 const struct mips_operand
*operand
, char *s
)
4479 switch (operand
->type
)
4482 return match_int_operand (arg
, operand
, s
);
4485 return match_mapped_int_operand (arg
, operand
, s
);
4488 return match_msb_operand (arg
, operand
, s
);
4491 return match_reg_operand (arg
, operand
, s
);
4494 return match_reg_pair_operand (arg
, operand
, s
);
4497 return match_pcrel_operand (s
);
4500 return match_perf_reg_operand (arg
, operand
, s
);
4502 case OP_ADDIUSP_INT
:
4503 return match_addiusp_operand (arg
, operand
, s
);
4505 case OP_CLO_CLZ_DEST
:
4506 return match_clo_clz_dest_operand (arg
, operand
, s
);
4508 case OP_LWM_SWM_LIST
:
4509 return match_lwm_swm_list_operand (arg
, operand
, s
);
4511 case OP_ENTRY_EXIT_LIST
:
4512 case OP_SAVE_RESTORE_LIST
:
4515 case OP_MDMX_IMM_REG
:
4516 return match_mdmx_imm_reg_operand (arg
, operand
, s
);
4518 case OP_REPEAT_DEST_REG
:
4519 return match_tied_reg_operand (arg
, s
, arg
->dest_regno
);
4521 case OP_REPEAT_PREV_REG
:
4522 return match_tied_reg_operand (arg
, s
, arg
->last_regno
);
4525 return match_pc_operand (s
);
4530 /* ARG is the state after successfully matching an instruction.
4531 Issue any queued-up warnings. */
4534 check_completed_insn (struct mips_arg_info
*arg
)
4539 as_warn (_("Used $at without \".set noat\""));
4541 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
4546 /* Classify an instruction according to the FIX_VR4120_* enumeration.
4547 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
4548 by VR4120 errata. */
4551 classify_vr4120_insn (const char *name
)
4553 if (strncmp (name
, "macc", 4) == 0)
4554 return FIX_VR4120_MACC
;
4555 if (strncmp (name
, "dmacc", 5) == 0)
4556 return FIX_VR4120_DMACC
;
4557 if (strncmp (name
, "mult", 4) == 0)
4558 return FIX_VR4120_MULT
;
4559 if (strncmp (name
, "dmult", 5) == 0)
4560 return FIX_VR4120_DMULT
;
4561 if (strstr (name
, "div"))
4562 return FIX_VR4120_DIV
;
4563 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
4564 return FIX_VR4120_MTHILO
;
4565 return NUM_FIX_VR4120_CLASSES
;
4568 #define INSN_ERET 0x42000018
4569 #define INSN_DERET 0x4200001f
4571 /* Return the number of instructions that must separate INSN1 and INSN2,
4572 where INSN1 is the earlier instruction. Return the worst-case value
4573 for any INSN2 if INSN2 is null. */
4576 insns_between (const struct mips_cl_insn
*insn1
,
4577 const struct mips_cl_insn
*insn2
)
4579 unsigned long pinfo1
, pinfo2
;
4582 /* This function needs to know which pinfo flags are set for INSN2
4583 and which registers INSN2 uses. The former is stored in PINFO2 and
4584 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
4585 will have every flag set and INSN2_USES_GPR will always return true. */
4586 pinfo1
= insn1
->insn_mo
->pinfo
;
4587 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
4589 #define INSN2_USES_GPR(REG) \
4590 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
4592 /* For most targets, write-after-read dependencies on the HI and LO
4593 registers must be separated by at least two instructions. */
4594 if (!hilo_interlocks
)
4596 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
4598 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
4602 /* If we're working around r7000 errata, there must be two instructions
4603 between an mfhi or mflo and any instruction that uses the result. */
4604 if (mips_7000_hilo_fix
4605 && !mips_opts
.micromips
4606 && MF_HILO_INSN (pinfo1
)
4607 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
4610 /* If we're working around 24K errata, one instruction is required
4611 if an ERET or DERET is followed by a branch instruction. */
4612 if (mips_fix_24k
&& !mips_opts
.micromips
)
4614 if (insn1
->insn_opcode
== INSN_ERET
4615 || insn1
->insn_opcode
== INSN_DERET
)
4618 || insn2
->insn_opcode
== INSN_ERET
4619 || insn2
->insn_opcode
== INSN_DERET
4620 || delayed_branch_p (insn2
))
4625 /* If working around VR4120 errata, check for combinations that need
4626 a single intervening instruction. */
4627 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
4629 unsigned int class1
, class2
;
4631 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
4632 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
4636 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
4637 if (vr4120_conflicts
[class1
] & (1 << class2
))
4642 if (!HAVE_CODE_COMPRESSION
)
4644 /* Check for GPR or coprocessor load delays. All such delays
4645 are on the RT register. */
4646 /* Itbl support may require additional care here. */
4647 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
4648 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
4650 know (pinfo1
& INSN_WRITE_GPR_T
);
4651 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
4655 /* Check for generic coprocessor hazards.
4657 This case is not handled very well. There is no special
4658 knowledge of CP0 handling, and the coprocessors other than
4659 the floating point unit are not distinguished at all. */
4660 /* Itbl support may require additional care here. FIXME!
4661 Need to modify this to include knowledge about
4662 user specified delays! */
4663 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
4664 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
4666 /* Handle cases where INSN1 writes to a known general coprocessor
4667 register. There must be a one instruction delay before INSN2
4668 if INSN2 reads that register, otherwise no delay is needed. */
4669 mask
= fpr_write_mask (insn1
);
4672 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
4677 /* Read-after-write dependencies on the control registers
4678 require a two-instruction gap. */
4679 if ((pinfo1
& INSN_WRITE_COND_CODE
)
4680 && (pinfo2
& INSN_READ_COND_CODE
))
4683 /* We don't know exactly what INSN1 does. If INSN2 is
4684 also a coprocessor instruction, assume there must be
4685 a one instruction gap. */
4686 if (pinfo2
& INSN_COP
)
4691 /* Check for read-after-write dependencies on the coprocessor
4692 control registers in cases where INSN1 does not need a general
4693 coprocessor delay. This means that INSN1 is a floating point
4694 comparison instruction. */
4695 /* Itbl support may require additional care here. */
4696 else if (!cop_interlocks
4697 && (pinfo1
& INSN_WRITE_COND_CODE
)
4698 && (pinfo2
& INSN_READ_COND_CODE
))
4702 #undef INSN2_USES_GPR
4707 /* Return the number of nops that would be needed to work around the
4708 VR4130 mflo/mfhi errata if instruction INSN immediately followed
4709 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
4710 that are contained within the first IGNORE instructions of HIST. */
4713 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
4714 const struct mips_cl_insn
*insn
)
4719 /* Check if the instruction writes to HI or LO. MTHI and MTLO
4720 are not affected by the errata. */
4722 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
4723 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
4724 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
4727 /* Search for the first MFLO or MFHI. */
4728 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
4729 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
4731 /* Extract the destination register. */
4732 mask
= gpr_write_mask (&hist
[i
]);
4734 /* No nops are needed if INSN reads that register. */
4735 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
4738 /* ...or if any of the intervening instructions do. */
4739 for (j
= 0; j
< i
; j
++)
4740 if (gpr_read_mask (&hist
[j
]) & mask
)
4744 return MAX_VR4130_NOPS
- i
;
4749 #define BASE_REG_EQ(INSN1, INSN2) \
4750 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
4751 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
4753 /* Return the minimum alignment for this store instruction. */
4756 fix_24k_align_to (const struct mips_opcode
*mo
)
4758 if (strcmp (mo
->name
, "sh") == 0)
4761 if (strcmp (mo
->name
, "swc1") == 0
4762 || strcmp (mo
->name
, "swc2") == 0
4763 || strcmp (mo
->name
, "sw") == 0
4764 || strcmp (mo
->name
, "sc") == 0
4765 || strcmp (mo
->name
, "s.s") == 0)
4768 if (strcmp (mo
->name
, "sdc1") == 0
4769 || strcmp (mo
->name
, "sdc2") == 0
4770 || strcmp (mo
->name
, "s.d") == 0)
4777 struct fix_24k_store_info
4779 /* Immediate offset, if any, for this store instruction. */
4781 /* Alignment required by this store instruction. */
4783 /* True for register offsets. */
4784 int register_offset
;
4787 /* Comparison function used by qsort. */
4790 fix_24k_sort (const void *a
, const void *b
)
4792 const struct fix_24k_store_info
*pos1
= a
;
4793 const struct fix_24k_store_info
*pos2
= b
;
4795 return (pos1
->off
- pos2
->off
);
4798 /* INSN is a store instruction. Try to record the store information
4799 in STINFO. Return false if the information isn't known. */
4802 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
4803 const struct mips_cl_insn
*insn
)
4805 /* The instruction must have a known offset. */
4806 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
4809 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
4810 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
4814 /* Return the number of nops that would be needed to work around the 24k
4815 "lost data on stores during refill" errata if instruction INSN
4816 immediately followed the 2 instructions described by HIST.
4817 Ignore hazards that are contained within the first IGNORE
4818 instructions of HIST.
4820 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
4821 for the data cache refills and store data. The following describes
4822 the scenario where the store data could be lost.
4824 * A data cache miss, due to either a load or a store, causing fill
4825 data to be supplied by the memory subsystem
4826 * The first three doublewords of fill data are returned and written
4828 * A sequence of four stores occurs in consecutive cycles around the
4829 final doubleword of the fill:
4833 * Zero, One or more instructions
4836 The four stores A-D must be to different doublewords of the line that
4837 is being filled. The fourth instruction in the sequence above permits
4838 the fill of the final doubleword to be transferred from the FSB into
4839 the cache. In the sequence above, the stores may be either integer
4840 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
4841 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
4842 different doublewords on the line. If the floating point unit is
4843 running in 1:2 mode, it is not possible to create the sequence above
4844 using only floating point store instructions.
4846 In this case, the cache line being filled is incorrectly marked
4847 invalid, thereby losing the data from any store to the line that
4848 occurs between the original miss and the completion of the five
4849 cycle sequence shown above.
4851 The workarounds are:
4853 * Run the data cache in write-through mode.
4854 * Insert a non-store instruction between
4855 Store A and Store B or Store B and Store C. */
4858 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
4859 const struct mips_cl_insn
*insn
)
4861 struct fix_24k_store_info pos
[3];
4862 int align
, i
, base_offset
;
4867 /* If the previous instruction wasn't a store, there's nothing to
4869 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
4872 /* If the instructions after the previous one are unknown, we have
4873 to assume the worst. */
4877 /* Check whether we are dealing with three consecutive stores. */
4878 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
4879 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
4882 /* If we don't know the relationship between the store addresses,
4883 assume the worst. */
4884 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
4885 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
4888 if (!fix_24k_record_store_info (&pos
[0], insn
)
4889 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
4890 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
4893 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
4895 /* Pick a value of ALIGN and X such that all offsets are adjusted by
4896 X bytes and such that the base register + X is known to be aligned
4899 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
4903 align
= pos
[0].align_to
;
4904 base_offset
= pos
[0].off
;
4905 for (i
= 1; i
< 3; i
++)
4906 if (align
< pos
[i
].align_to
)
4908 align
= pos
[i
].align_to
;
4909 base_offset
= pos
[i
].off
;
4911 for (i
= 0; i
< 3; i
++)
4912 pos
[i
].off
-= base_offset
;
4915 pos
[0].off
&= ~align
+ 1;
4916 pos
[1].off
&= ~align
+ 1;
4917 pos
[2].off
&= ~align
+ 1;
4919 /* If any two stores write to the same chunk, they also write to the
4920 same doubleword. The offsets are still sorted at this point. */
4921 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
4924 /* A range of at least 9 bytes is needed for the stores to be in
4925 non-overlapping doublewords. */
4926 if (pos
[2].off
- pos
[0].off
<= 8)
4929 if (pos
[2].off
- pos
[1].off
>= 24
4930 || pos
[1].off
- pos
[0].off
>= 24
4931 || pos
[2].off
- pos
[0].off
>= 32)
4937 /* Return the number of nops that would be needed if instruction INSN
4938 immediately followed the MAX_NOPS instructions given by HIST,
4939 where HIST[0] is the most recent instruction. Ignore hazards
4940 between INSN and the first IGNORE instructions in HIST.
4942 If INSN is null, return the worse-case number of nops for any
4946 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
4947 const struct mips_cl_insn
*insn
)
4949 int i
, nops
, tmp_nops
;
4952 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
4954 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
4955 if (tmp_nops
> nops
)
4959 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
4961 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
4962 if (tmp_nops
> nops
)
4966 if (mips_fix_24k
&& !mips_opts
.micromips
)
4968 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
4969 if (tmp_nops
> nops
)
4976 /* The variable arguments provide NUM_INSNS extra instructions that
4977 might be added to HIST. Return the largest number of nops that
4978 would be needed after the extended sequence, ignoring hazards
4979 in the first IGNORE instructions. */
4982 nops_for_sequence (int num_insns
, int ignore
,
4983 const struct mips_cl_insn
*hist
, ...)
4986 struct mips_cl_insn buffer
[MAX_NOPS
];
4987 struct mips_cl_insn
*cursor
;
4990 va_start (args
, hist
);
4991 cursor
= buffer
+ num_insns
;
4992 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
4993 while (cursor
> buffer
)
4994 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
4996 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5001 /* Like nops_for_insn, but if INSN is a branch, take into account the
5002 worst-case delay for the branch target. */
5005 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5006 const struct mips_cl_insn
*insn
)
5010 nops
= nops_for_insn (ignore
, hist
, insn
);
5011 if (delayed_branch_p (insn
))
5013 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5014 hist
, insn
, get_delay_slot_nop (insn
));
5015 if (tmp_nops
> nops
)
5018 else if (compact_branch_p (insn
))
5020 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5021 if (tmp_nops
> nops
)
5027 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5030 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5032 gas_assert (!HAVE_CODE_COMPRESSION
);
5033 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5034 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5037 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5038 jr target pc &= 'hffff_ffff_cfff_ffff. */
5041 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5043 gas_assert (!HAVE_CODE_COMPRESSION
);
5044 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5045 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5046 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5054 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5055 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5058 ep
.X_op
= O_constant
;
5059 ep
.X_add_number
= 0xcfff0000;
5060 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5061 ep
.X_add_number
= 0xffff;
5062 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5063 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5068 fix_loongson2f (struct mips_cl_insn
* ip
)
5070 if (mips_fix_loongson2f_nop
)
5071 fix_loongson2f_nop (ip
);
5073 if (mips_fix_loongson2f_jump
)
5074 fix_loongson2f_jump (ip
);
5077 /* IP is a branch that has a delay slot, and we need to fill it
5078 automatically. Return true if we can do that by swapping IP
5079 with the previous instruction.
5080 ADDRESS_EXPR is an operand of the instruction to be used with
5084 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5085 bfd_reloc_code_real_type
*reloc_type
)
5087 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5088 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5090 /* -O2 and above is required for this optimization. */
5091 if (mips_optimize
< 2)
5094 /* If we have seen .set volatile or .set nomove, don't optimize. */
5095 if (mips_opts
.nomove
)
5098 /* We can't swap if the previous instruction's position is fixed. */
5099 if (history
[0].fixed_p
)
5102 /* If the previous previous insn was in a .set noreorder, we can't
5103 swap. Actually, the MIPS assembler will swap in this situation.
5104 However, gcc configured -with-gnu-as will generate code like
5112 in which we can not swap the bne and INSN. If gcc is not configured
5113 -with-gnu-as, it does not output the .set pseudo-ops. */
5114 if (history
[1].noreorder_p
)
5117 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5118 This means that the previous instruction was a 4-byte one anyhow. */
5119 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5122 /* If the branch is itself the target of a branch, we can not swap.
5123 We cheat on this; all we check for is whether there is a label on
5124 this instruction. If there are any branches to anything other than
5125 a label, users must use .set noreorder. */
5126 if (seg_info (now_seg
)->label_list
)
5129 /* If the previous instruction is in a variant frag other than this
5130 branch's one, we cannot do the swap. This does not apply to
5131 MIPS16 code, which uses variant frags for different purposes. */
5132 if (!mips_opts
.mips16
5134 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5137 /* We do not swap with instructions that cannot architecturally
5138 be placed in a branch delay slot, such as SYNC or ERET. We
5139 also refrain from swapping with a trap instruction, since it
5140 complicates trap handlers to have the trap instruction be in
5142 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5143 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5146 /* Check for conflicts between the branch and the instructions
5147 before the candidate delay slot. */
5148 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5151 /* Check for conflicts between the swapped sequence and the
5152 target of the branch. */
5153 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5156 /* If the branch reads a register that the previous
5157 instruction sets, we can not swap. */
5158 gpr_read
= gpr_read_mask (ip
);
5159 prev_gpr_write
= gpr_write_mask (&history
[0]);
5160 if (gpr_read
& prev_gpr_write
)
5163 /* If the branch writes a register that the previous
5164 instruction sets, we can not swap. */
5165 gpr_write
= gpr_write_mask (ip
);
5166 if (gpr_write
& prev_gpr_write
)
5169 /* If the branch writes a register that the previous
5170 instruction reads, we can not swap. */
5171 prev_gpr_read
= gpr_read_mask (&history
[0]);
5172 if (gpr_write
& prev_gpr_read
)
5175 /* If one instruction sets a condition code and the
5176 other one uses a condition code, we can not swap. */
5177 pinfo
= ip
->insn_mo
->pinfo
;
5178 if ((pinfo
& INSN_READ_COND_CODE
)
5179 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5181 if ((pinfo
& INSN_WRITE_COND_CODE
)
5182 && (prev_pinfo
& INSN_READ_COND_CODE
))
5185 /* If the previous instruction uses the PC, we can not swap. */
5186 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5187 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
5189 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
5192 /* If the previous instruction has an incorrect size for a fixed
5193 branch delay slot in microMIPS mode, we cannot swap. */
5194 pinfo2
= ip
->insn_mo
->pinfo2
;
5195 if (mips_opts
.micromips
5196 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
5197 && insn_length (history
) != 2)
5199 if (mips_opts
.micromips
5200 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
5201 && insn_length (history
) != 4)
5204 /* On R5900 short loops need to be fixed by inserting a nop in
5205 the branch delay slots.
5206 A short loop can be terminated too early. */
5207 if (mips_opts
.arch
== CPU_R5900
5208 /* Check if instruction has a parameter, ignore "j $31". */
5209 && (address_expr
!= NULL
)
5210 /* Parameter must be 16 bit. */
5211 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
5212 /* Branch to same segment. */
5213 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
5214 /* Branch to same code fragment. */
5215 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
5216 /* Can only calculate branch offset if value is known. */
5217 && symbol_constant_p(address_expr
->X_add_symbol
)
5218 /* Check if branch is really conditional. */
5219 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5220 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
5221 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5224 /* Check if loop is shorter than 6 instructions including
5225 branch and delay slot. */
5226 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
5233 /* When the loop includes branches or jumps,
5234 it is not a short loop. */
5235 for (i
= 0; i
< (distance
/ 4); i
++)
5237 if ((history
[i
].cleared_p
)
5238 || delayed_branch_p(&history
[i
]))
5246 /* Insert nop after branch to fix short loop. */
5255 /* Decide how we should add IP to the instruction stream.
5256 ADDRESS_EXPR is an operand of the instruction to be used with
5259 static enum append_method
5260 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5261 bfd_reloc_code_real_type
*reloc_type
)
5263 unsigned long pinfo
;
5265 /* The relaxed version of a macro sequence must be inherently
5267 if (mips_relax
.sequence
== 2)
5270 /* We must not dabble with instructions in a ".set norerorder" block. */
5271 if (mips_opts
.noreorder
)
5274 /* Otherwise, it's our responsibility to fill branch delay slots. */
5275 if (delayed_branch_p (ip
))
5277 if (!branch_likely_p (ip
)
5278 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
5281 pinfo
= ip
->insn_mo
->pinfo
;
5282 if (mips_opts
.mips16
5283 && ISA_SUPPORTS_MIPS16E
5284 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
5285 return APPEND_ADD_COMPACT
;
5287 return APPEND_ADD_WITH_NOP
;
5293 /* IP is a MIPS16 instruction whose opcode we have just changed.
5294 Point IP->insn_mo to the new opcode's definition. */
5297 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
5299 const struct mips_opcode
*mo
, *end
;
5301 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
5302 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
5303 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
5311 /* For microMIPS macros, we need to generate a local number label
5312 as the target of branches. */
5313 #define MICROMIPS_LABEL_CHAR '\037'
5314 static unsigned long micromips_target_label
;
5315 static char micromips_target_name
[32];
5318 micromips_label_name (void)
5320 char *p
= micromips_target_name
;
5321 char symbol_name_temporary
[24];
5329 l
= micromips_target_label
;
5330 #ifdef LOCAL_LABEL_PREFIX
5331 *p
++ = LOCAL_LABEL_PREFIX
;
5334 *p
++ = MICROMIPS_LABEL_CHAR
;
5337 symbol_name_temporary
[i
++] = l
% 10 + '0';
5342 *p
++ = symbol_name_temporary
[--i
];
5345 return micromips_target_name
;
5349 micromips_label_expr (expressionS
*label_expr
)
5351 label_expr
->X_op
= O_symbol
;
5352 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
5353 label_expr
->X_add_number
= 0;
5357 micromips_label_inc (void)
5359 micromips_target_label
++;
5360 *micromips_target_name
= '\0';
5364 micromips_add_label (void)
5368 s
= colon (micromips_label_name ());
5369 micromips_label_inc ();
5370 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
5373 /* If assembling microMIPS code, then return the microMIPS reloc
5374 corresponding to the requested one if any. Otherwise return
5375 the reloc unchanged. */
5377 static bfd_reloc_code_real_type
5378 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
5380 static const bfd_reloc_code_real_type relocs
[][2] =
5382 /* Keep sorted incrementally by the left-hand key. */
5383 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
5384 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
5385 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
5386 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
5387 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
5388 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
5389 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
5390 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
5391 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
5392 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
5393 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
5394 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
5395 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
5396 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
5397 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
5398 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
5399 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
5400 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
5401 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
5402 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
5403 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
5404 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
5405 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
5406 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
5407 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
5408 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
5409 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
5411 bfd_reloc_code_real_type r
;
5414 if (!mips_opts
.micromips
)
5416 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
5422 return relocs
[i
][1];
5427 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5428 Return true on success, storing the resolved value in RESULT. */
5431 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
5436 case BFD_RELOC_MIPS_HIGHEST
:
5437 case BFD_RELOC_MICROMIPS_HIGHEST
:
5438 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
5441 case BFD_RELOC_MIPS_HIGHER
:
5442 case BFD_RELOC_MICROMIPS_HIGHER
:
5443 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
5446 case BFD_RELOC_HI16_S
:
5447 case BFD_RELOC_MICROMIPS_HI16_S
:
5448 case BFD_RELOC_MIPS16_HI16_S
:
5449 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
5452 case BFD_RELOC_HI16
:
5453 case BFD_RELOC_MICROMIPS_HI16
:
5454 case BFD_RELOC_MIPS16_HI16
:
5455 *result
= (operand
>> 16) & 0xffff;
5458 case BFD_RELOC_LO16
:
5459 case BFD_RELOC_MICROMIPS_LO16
:
5460 case BFD_RELOC_MIPS16_LO16
:
5461 *result
= operand
& 0xffff;
5464 case BFD_RELOC_UNUSED
:
5473 /* Output an instruction. IP is the instruction information.
5474 ADDRESS_EXPR is an operand of the instruction to be used with
5475 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5476 a macro expansion. */
5479 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5480 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
5482 unsigned long prev_pinfo2
, pinfo
;
5483 bfd_boolean relaxed_branch
= FALSE
;
5484 enum append_method method
;
5485 bfd_boolean relax32
;
5488 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
5489 fix_loongson2f (ip
);
5491 file_ase_mips16
|= mips_opts
.mips16
;
5492 file_ase_micromips
|= mips_opts
.micromips
;
5494 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5495 pinfo
= ip
->insn_mo
->pinfo
;
5497 if (mips_opts
.micromips
5499 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
5500 && micromips_insn_length (ip
->insn_mo
) != 2)
5501 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
5502 && micromips_insn_length (ip
->insn_mo
) != 4)))
5503 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
5504 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
5506 if (address_expr
== NULL
)
5508 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
5509 && reloc_type
[1] == BFD_RELOC_UNUSED
5510 && reloc_type
[2] == BFD_RELOC_UNUSED
5511 && address_expr
->X_op
== O_constant
)
5513 switch (*reloc_type
)
5515 case BFD_RELOC_MIPS_JMP
:
5519 shift
= mips_opts
.micromips
? 1 : 2;
5520 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
5521 as_bad (_("jump to misaligned address (0x%lx)"),
5522 (unsigned long) address_expr
->X_add_number
);
5523 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
5529 case BFD_RELOC_MIPS16_JMP
:
5530 if ((address_expr
->X_add_number
& 3) != 0)
5531 as_bad (_("jump to misaligned address (0x%lx)"),
5532 (unsigned long) address_expr
->X_add_number
);
5534 (((address_expr
->X_add_number
& 0x7c0000) << 3)
5535 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
5536 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
5540 case BFD_RELOC_16_PCREL_S2
:
5544 shift
= mips_opts
.micromips
? 1 : 2;
5545 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
5546 as_bad (_("branch to misaligned address (0x%lx)"),
5547 (unsigned long) address_expr
->X_add_number
);
5548 if (!mips_relax_branch
)
5550 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
5551 & ~((1 << (shift
+ 16)) - 1))
5552 as_bad (_("branch address range overflow (0x%lx)"),
5553 (unsigned long) address_expr
->X_add_number
);
5554 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
5564 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
5567 ip
->insn_opcode
|= value
& 0xffff;
5575 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
5577 /* There are a lot of optimizations we could do that we don't.
5578 In particular, we do not, in general, reorder instructions.
5579 If you use gcc with optimization, it will reorder
5580 instructions and generally do much more optimization then we
5581 do here; repeating all that work in the assembler would only
5582 benefit hand written assembly code, and does not seem worth
5584 int nops
= (mips_optimize
== 0
5585 ? nops_for_insn (0, history
, NULL
)
5586 : nops_for_insn_or_target (0, history
, ip
));
5590 unsigned long old_frag_offset
;
5593 old_frag
= frag_now
;
5594 old_frag_offset
= frag_now_fix ();
5596 for (i
= 0; i
< nops
; i
++)
5597 add_fixed_insn (NOP_INSN
);
5598 insert_into_history (0, nops
, NOP_INSN
);
5602 listing_prev_line ();
5603 /* We may be at the start of a variant frag. In case we
5604 are, make sure there is enough space for the frag
5605 after the frags created by listing_prev_line. The
5606 argument to frag_grow here must be at least as large
5607 as the argument to all other calls to frag_grow in
5608 this file. We don't have to worry about being in the
5609 middle of a variant frag, because the variants insert
5610 all needed nop instructions themselves. */
5614 mips_move_text_labels ();
5616 #ifndef NO_ECOFF_DEBUGGING
5617 if (ECOFF_DEBUGGING
)
5618 ecoff_fix_loc (old_frag
, old_frag_offset
);
5622 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
5626 /* Work out how many nops in prev_nop_frag are needed by IP,
5627 ignoring hazards generated by the first prev_nop_frag_since
5629 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
5630 gas_assert (nops
<= prev_nop_frag_holds
);
5632 /* Enforce NOPS as a minimum. */
5633 if (nops
> prev_nop_frag_required
)
5634 prev_nop_frag_required
= nops
;
5636 if (prev_nop_frag_holds
== prev_nop_frag_required
)
5638 /* Settle for the current number of nops. Update the history
5639 accordingly (for the benefit of any future .set reorder code). */
5640 prev_nop_frag
= NULL
;
5641 insert_into_history (prev_nop_frag_since
,
5642 prev_nop_frag_holds
, NOP_INSN
);
5646 /* Allow this instruction to replace one of the nops that was
5647 tentatively added to prev_nop_frag. */
5648 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
5649 prev_nop_frag_holds
--;
5650 prev_nop_frag_since
++;
5654 method
= get_append_method (ip
, address_expr
, reloc_type
);
5655 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
5657 dwarf2_emit_insn (0);
5658 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
5659 so "move" the instruction address accordingly.
5661 Also, it doesn't seem appropriate for the assembler to reorder .loc
5662 entries. If this instruction is a branch that we are going to swap
5663 with the previous instruction, the two instructions should be
5664 treated as a unit, and the debug information for both instructions
5665 should refer to the start of the branch sequence. Using the
5666 current position is certainly wrong when swapping a 32-bit branch
5667 and a 16-bit delay slot, since the current position would then be
5668 in the middle of a branch. */
5669 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
5671 relax32
= (mips_relax_branch
5672 /* Don't try branch relaxation within .set nomacro, or within
5673 .set noat if we use $at for PIC computations. If it turns
5674 out that the branch was out-of-range, we'll get an error. */
5675 && !mips_opts
.warn_about_macros
5676 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
5677 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
5678 as they have no complementing branches. */
5679 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
5681 if (!HAVE_CODE_COMPRESSION
5684 && *reloc_type
== BFD_RELOC_16_PCREL_S2
5685 && delayed_branch_p (ip
))
5687 relaxed_branch
= TRUE
;
5688 add_relaxed_insn (ip
, (relaxed_branch_length
5690 uncond_branch_p (ip
) ? -1
5691 : branch_likely_p (ip
) ? 1
5695 uncond_branch_p (ip
),
5696 branch_likely_p (ip
),
5697 pinfo
& INSN_WRITE_GPR_31
,
5699 address_expr
->X_add_symbol
,
5700 address_expr
->X_add_number
);
5701 *reloc_type
= BFD_RELOC_UNUSED
;
5703 else if (mips_opts
.micromips
5705 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
5706 || *reloc_type
> BFD_RELOC_UNUSED
)
5707 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
5708 /* Don't try branch relaxation when users specify
5709 16-bit/32-bit instructions. */
5710 && !forced_insn_length
)
5712 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
5713 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
5714 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
5715 int compact
= compact_branch_p (ip
);
5716 int al
= pinfo
& INSN_WRITE_GPR_31
;
5719 gas_assert (address_expr
!= NULL
);
5720 gas_assert (!mips_relax
.sequence
);
5722 relaxed_branch
= TRUE
;
5723 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
5724 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
5725 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
5727 address_expr
->X_add_symbol
,
5728 address_expr
->X_add_number
);
5729 *reloc_type
= BFD_RELOC_UNUSED
;
5731 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
5733 /* We need to set up a variant frag. */
5734 gas_assert (address_expr
!= NULL
);
5735 add_relaxed_insn (ip
, 4, 0,
5737 (*reloc_type
- BFD_RELOC_UNUSED
,
5738 forced_insn_length
== 2, forced_insn_length
== 4,
5739 delayed_branch_p (&history
[0]),
5740 history
[0].mips16_absolute_jump_p
),
5741 make_expr_symbol (address_expr
), 0);
5743 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
5745 if (!delayed_branch_p (ip
))
5746 /* Make sure there is enough room to swap this instruction with
5747 a following jump instruction. */
5749 add_fixed_insn (ip
);
5753 if (mips_opts
.mips16
5754 && mips_opts
.noreorder
5755 && delayed_branch_p (&history
[0]))
5756 as_warn (_("extended instruction in delay slot"));
5758 if (mips_relax
.sequence
)
5760 /* If we've reached the end of this frag, turn it into a variant
5761 frag and record the information for the instructions we've
5763 if (frag_room () < 4)
5764 relax_close_frag ();
5765 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
5768 if (mips_relax
.sequence
!= 2)
5770 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
5771 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
5772 mips_macro_warning
.sizes
[0] += insn_length (ip
);
5773 mips_macro_warning
.insns
[0]++;
5775 if (mips_relax
.sequence
!= 1)
5777 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
5778 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
5779 mips_macro_warning
.sizes
[1] += insn_length (ip
);
5780 mips_macro_warning
.insns
[1]++;
5783 if (mips_opts
.mips16
)
5786 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
5788 add_fixed_insn (ip
);
5791 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
5793 bfd_reloc_code_real_type final_type
[3];
5794 reloc_howto_type
*howto0
;
5795 reloc_howto_type
*howto
;
5798 /* Perform any necessary conversion to microMIPS relocations
5799 and find out how many relocations there actually are. */
5800 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
5801 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
5803 /* In a compound relocation, it is the final (outermost)
5804 operator that determines the relocated field. */
5805 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
5810 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
5811 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
5812 bfd_get_reloc_size (howto
),
5814 howto0
&& howto0
->pc_relative
,
5817 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
5818 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
5819 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
5821 /* These relocations can have an addend that won't fit in
5822 4 octets for 64bit assembly. */
5824 && ! howto
->partial_inplace
5825 && (reloc_type
[0] == BFD_RELOC_16
5826 || reloc_type
[0] == BFD_RELOC_32
5827 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
5828 || reloc_type
[0] == BFD_RELOC_GPREL16
5829 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
5830 || reloc_type
[0] == BFD_RELOC_GPREL32
5831 || reloc_type
[0] == BFD_RELOC_64
5832 || reloc_type
[0] == BFD_RELOC_CTOR
5833 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
5834 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
5835 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
5836 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
5837 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
5838 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
5839 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
5840 || hi16_reloc_p (reloc_type
[0])
5841 || lo16_reloc_p (reloc_type
[0])))
5842 ip
->fixp
[0]->fx_no_overflow
= 1;
5844 /* These relocations can have an addend that won't fit in 2 octets. */
5845 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
5846 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
5847 ip
->fixp
[0]->fx_no_overflow
= 1;
5849 if (mips_relax
.sequence
)
5851 if (mips_relax
.first_fixup
== 0)
5852 mips_relax
.first_fixup
= ip
->fixp
[0];
5854 else if (reloc_needs_lo_p (*reloc_type
))
5856 struct mips_hi_fixup
*hi_fixup
;
5858 /* Reuse the last entry if it already has a matching %lo. */
5859 hi_fixup
= mips_hi_fixup_list
;
5861 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
5863 hi_fixup
= ((struct mips_hi_fixup
*)
5864 xmalloc (sizeof (struct mips_hi_fixup
)));
5865 hi_fixup
->next
= mips_hi_fixup_list
;
5866 mips_hi_fixup_list
= hi_fixup
;
5868 hi_fixup
->fixp
= ip
->fixp
[0];
5869 hi_fixup
->seg
= now_seg
;
5872 /* Add fixups for the second and third relocations, if given.
5873 Note that the ABI allows the second relocation to be
5874 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
5875 moment we only use RSS_UNDEF, but we could add support
5876 for the others if it ever becomes necessary. */
5877 for (i
= 1; i
< 3; i
++)
5878 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
5880 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
5881 ip
->fixp
[0]->fx_size
, NULL
, 0,
5882 FALSE
, final_type
[i
]);
5884 /* Use fx_tcbit to mark compound relocs. */
5885 ip
->fixp
[0]->fx_tcbit
= 1;
5886 ip
->fixp
[i
]->fx_tcbit
= 1;
5891 /* Update the register mask information. */
5892 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
5893 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
5898 insert_into_history (0, 1, ip
);
5901 case APPEND_ADD_WITH_NOP
:
5903 struct mips_cl_insn
*nop
;
5905 insert_into_history (0, 1, ip
);
5906 nop
= get_delay_slot_nop (ip
);
5907 add_fixed_insn (nop
);
5908 insert_into_history (0, 1, nop
);
5909 if (mips_relax
.sequence
)
5910 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
5914 case APPEND_ADD_COMPACT
:
5915 /* Convert MIPS16 jr/jalr into a "compact" jump. */
5916 gas_assert (mips_opts
.mips16
);
5917 ip
->insn_opcode
|= 0x0080;
5918 find_altered_mips16_opcode (ip
);
5920 insert_into_history (0, 1, ip
);
5925 struct mips_cl_insn delay
= history
[0];
5926 if (mips_opts
.mips16
)
5928 know (delay
.frag
== ip
->frag
);
5929 move_insn (ip
, delay
.frag
, delay
.where
);
5930 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
5932 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
5934 /* Add the delay slot instruction to the end of the
5935 current frag and shrink the fixed part of the
5936 original frag. If the branch occupies the tail of
5937 the latter, move it backwards to cover the gap. */
5938 delay
.frag
->fr_fix
-= branch_disp
;
5939 if (delay
.frag
== ip
->frag
)
5940 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
5941 add_fixed_insn (&delay
);
5945 move_insn (&delay
, ip
->frag
,
5946 ip
->where
- branch_disp
+ insn_length (ip
));
5947 move_insn (ip
, history
[0].frag
, history
[0].where
);
5951 insert_into_history (0, 1, &delay
);
5956 /* If we have just completed an unconditional branch, clear the history. */
5957 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
5958 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
5962 mips_no_prev_insn ();
5964 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5965 history
[i
].cleared_p
= 1;
5968 /* We need to emit a label at the end of branch-likely macros. */
5969 if (emit_branch_likely_macro
)
5971 emit_branch_likely_macro
= FALSE
;
5972 micromips_add_label ();
5975 /* We just output an insn, so the next one doesn't have a label. */
5976 mips_clear_insn_labels ();
5979 /* Forget that there was any previous instruction or label.
5980 When BRANCH is true, the branch history is also flushed. */
5983 mips_no_prev_insn (void)
5985 prev_nop_frag
= NULL
;
5986 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
5987 mips_clear_insn_labels ();
5990 /* This function must be called before we emit something other than
5991 instructions. It is like mips_no_prev_insn except that it inserts
5992 any NOPS that might be needed by previous instructions. */
5995 mips_emit_delays (void)
5997 if (! mips_opts
.noreorder
)
5999 int nops
= nops_for_insn (0, history
, NULL
);
6003 add_fixed_insn (NOP_INSN
);
6004 mips_move_text_labels ();
6007 mips_no_prev_insn ();
6010 /* Start a (possibly nested) noreorder block. */
6013 start_noreorder (void)
6015 if (mips_opts
.noreorder
== 0)
6020 /* None of the instructions before the .set noreorder can be moved. */
6021 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6022 history
[i
].fixed_p
= 1;
6024 /* Insert any nops that might be needed between the .set noreorder
6025 block and the previous instructions. We will later remove any
6026 nops that turn out not to be needed. */
6027 nops
= nops_for_insn (0, history
, NULL
);
6030 if (mips_optimize
!= 0)
6032 /* Record the frag which holds the nop instructions, so
6033 that we can remove them if we don't need them. */
6034 frag_grow (nops
* NOP_INSN_SIZE
);
6035 prev_nop_frag
= frag_now
;
6036 prev_nop_frag_holds
= nops
;
6037 prev_nop_frag_required
= 0;
6038 prev_nop_frag_since
= 0;
6041 for (; nops
> 0; --nops
)
6042 add_fixed_insn (NOP_INSN
);
6044 /* Move on to a new frag, so that it is safe to simply
6045 decrease the size of prev_nop_frag. */
6046 frag_wane (frag_now
);
6048 mips_move_text_labels ();
6050 mips_mark_labels ();
6051 mips_clear_insn_labels ();
6053 mips_opts
.noreorder
++;
6054 mips_any_noreorder
= 1;
6057 /* End a nested noreorder block. */
6060 end_noreorder (void)
6062 mips_opts
.noreorder
--;
6063 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6065 /* Commit to inserting prev_nop_frag_required nops and go back to
6066 handling nop insertion the .set reorder way. */
6067 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6069 insert_into_history (prev_nop_frag_since
,
6070 prev_nop_frag_required
, NOP_INSN
);
6071 prev_nop_frag
= NULL
;
6075 /* Set up global variables for the start of a new macro. */
6080 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6081 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6082 sizeof (mips_macro_warning
.first_insn_sizes
));
6083 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6084 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6085 && delayed_branch_p (&history
[0]));
6086 switch (history
[0].insn_mo
->pinfo2
6087 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6089 case INSN2_BRANCH_DELAY_32BIT
:
6090 mips_macro_warning
.delay_slot_length
= 4;
6092 case INSN2_BRANCH_DELAY_16BIT
:
6093 mips_macro_warning
.delay_slot_length
= 2;
6096 mips_macro_warning
.delay_slot_length
= 0;
6099 mips_macro_warning
.first_frag
= NULL
;
6102 /* Given that a macro is longer than one instruction or of the wrong size,
6103 return the appropriate warning for it. Return null if no warning is
6104 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6105 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6106 and RELAX_NOMACRO. */
6109 macro_warning (relax_substateT subtype
)
6111 if (subtype
& RELAX_DELAY_SLOT
)
6112 return _("Macro instruction expanded into multiple instructions"
6113 " in a branch delay slot");
6114 else if (subtype
& RELAX_NOMACRO
)
6115 return _("Macro instruction expanded into multiple instructions");
6116 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6117 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6118 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6119 ? _("Macro instruction expanded into a wrong size instruction"
6120 " in a 16-bit branch delay slot")
6121 : _("Macro instruction expanded into a wrong size instruction"
6122 " in a 32-bit branch delay slot"));
6127 /* Finish up a macro. Emit warnings as appropriate. */
6132 /* Relaxation warning flags. */
6133 relax_substateT subtype
= 0;
6135 /* Check delay slot size requirements. */
6136 if (mips_macro_warning
.delay_slot_length
== 2)
6137 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6138 if (mips_macro_warning
.delay_slot_length
!= 0)
6140 if (mips_macro_warning
.delay_slot_length
6141 != mips_macro_warning
.first_insn_sizes
[0])
6142 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6143 if (mips_macro_warning
.delay_slot_length
6144 != mips_macro_warning
.first_insn_sizes
[1])
6145 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6148 /* Check instruction count requirements. */
6149 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6151 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6152 subtype
|= RELAX_SECOND_LONGER
;
6153 if (mips_opts
.warn_about_macros
)
6154 subtype
|= RELAX_NOMACRO
;
6155 if (mips_macro_warning
.delay_slot_p
)
6156 subtype
|= RELAX_DELAY_SLOT
;
6159 /* If both alternatives fail to fill a delay slot correctly,
6160 emit the warning now. */
6161 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6162 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6167 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6168 | RELAX_DELAY_SLOT_SIZE_FIRST
6169 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6170 msg
= macro_warning (s
);
6172 as_warn ("%s", msg
);
6176 /* If both implementations are longer than 1 instruction, then emit the
6178 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6183 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6184 msg
= macro_warning (s
);
6186 as_warn ("%s", msg
);
6190 /* If any flags still set, then one implementation might need a warning
6191 and the other either will need one of a different kind or none at all.
6192 Pass any remaining flags over to relaxation. */
6193 if (mips_macro_warning
.first_frag
!= NULL
)
6194 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
6197 /* Instruction operand formats used in macros that vary between
6198 standard MIPS and microMIPS code. */
6200 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
6201 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
6202 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
6203 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
6204 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
6205 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
6206 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
6207 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
6209 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6210 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6211 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6212 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6213 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6214 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6215 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6216 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6218 /* Read a macro's relocation codes from *ARGS and store them in *R.
6219 The first argument in *ARGS will be either the code for a single
6220 relocation or -1 followed by the three codes that make up a
6221 composite relocation. */
6224 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
6228 next
= va_arg (*args
, int);
6230 r
[0] = (bfd_reloc_code_real_type
) next
;
6233 for (i
= 0; i
< 3; i
++)
6234 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
6235 /* This function is only used for 16-bit relocation fields.
6236 To make the macro code simpler, treat an unrelocated value
6237 in the same way as BFD_RELOC_LO16. */
6238 if (r
[0] == BFD_RELOC_UNUSED
)
6239 r
[0] = BFD_RELOC_LO16
;
6243 /* Build an instruction created by a macro expansion. This is passed
6244 a pointer to the count of instructions created so far, an
6245 expression, the name of the instruction to build, an operand format
6246 string, and corresponding arguments. */
6249 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
6251 const struct mips_opcode
*mo
= NULL
;
6252 bfd_reloc_code_real_type r
[3];
6253 const struct mips_opcode
*amo
;
6254 const struct mips_operand
*operand
;
6255 struct hash_control
*hash
;
6256 struct mips_cl_insn insn
;
6260 va_start (args
, fmt
);
6262 if (mips_opts
.mips16
)
6264 mips16_macro_build (ep
, name
, fmt
, &args
);
6269 r
[0] = BFD_RELOC_UNUSED
;
6270 r
[1] = BFD_RELOC_UNUSED
;
6271 r
[2] = BFD_RELOC_UNUSED
;
6272 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
6273 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
6275 gas_assert (strcmp (name
, amo
->name
) == 0);
6279 /* Search until we get a match for NAME. It is assumed here that
6280 macros will never generate MDMX, MIPS-3D, or MT instructions.
6281 We try to match an instruction that fulfils the branch delay
6282 slot instruction length requirement (if any) of the previous
6283 instruction. While doing this we record the first instruction
6284 seen that matches all the other conditions and use it anyway
6285 if the requirement cannot be met; we will issue an appropriate
6286 warning later on. */
6287 if (strcmp (fmt
, amo
->args
) == 0
6288 && amo
->pinfo
!= INSN_MACRO
6289 && is_opcode_valid (amo
)
6290 && is_size_valid (amo
))
6292 if (is_delay_slot_valid (amo
))
6302 gas_assert (amo
->name
);
6304 while (strcmp (name
, amo
->name
) == 0);
6307 create_insn (&insn
, mo
);
6320 macro_read_relocs (&args
, r
);
6321 gas_assert (*r
== BFD_RELOC_GPREL16
6322 || *r
== BFD_RELOC_MIPS_HIGHER
6323 || *r
== BFD_RELOC_HI16_S
6324 || *r
== BFD_RELOC_LO16
6325 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
6329 macro_read_relocs (&args
, r
);
6333 macro_read_relocs (&args
, r
);
6334 gas_assert (ep
!= NULL
6335 && (ep
->X_op
== O_constant
6336 || (ep
->X_op
== O_symbol
6337 && (*r
== BFD_RELOC_MIPS_HIGHEST
6338 || *r
== BFD_RELOC_HI16_S
6339 || *r
== BFD_RELOC_HI16
6340 || *r
== BFD_RELOC_GPREL16
6341 || *r
== BFD_RELOC_MIPS_GOT_HI16
6342 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
6346 gas_assert (ep
!= NULL
);
6349 * This allows macro() to pass an immediate expression for
6350 * creating short branches without creating a symbol.
6352 * We don't allow branch relaxation for these branches, as
6353 * they should only appear in ".set nomacro" anyway.
6355 if (ep
->X_op
== O_constant
)
6357 /* For microMIPS we always use relocations for branches.
6358 So we should not resolve immediate values. */
6359 gas_assert (!mips_opts
.micromips
);
6361 if ((ep
->X_add_number
& 3) != 0)
6362 as_bad (_("branch to misaligned address (0x%lx)"),
6363 (unsigned long) ep
->X_add_number
);
6364 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
6365 as_bad (_("branch address range overflow (0x%lx)"),
6366 (unsigned long) ep
->X_add_number
);
6367 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
6371 *r
= BFD_RELOC_16_PCREL_S2
;
6375 gas_assert (ep
!= NULL
);
6376 *r
= BFD_RELOC_MIPS_JMP
;
6380 operand
= (mips_opts
.micromips
6381 ? decode_micromips_operand (fmt
)
6382 : decode_mips_operand (fmt
));
6386 uval
= va_arg (args
, int);
6387 if (operand
->type
== OP_CLO_CLZ_DEST
)
6388 uval
|= (uval
<< 5);
6389 insn_insert_operand (&insn
, operand
, uval
);
6391 if (*fmt
== '+' || *fmt
== 'm')
6397 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6399 append_insn (&insn
, ep
, r
, TRUE
);
6403 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
6406 struct mips_opcode
*mo
;
6407 struct mips_cl_insn insn
;
6408 const struct mips_operand
*operand
;
6409 bfd_reloc_code_real_type r
[3]
6410 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
6412 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
6414 gas_assert (strcmp (name
, mo
->name
) == 0);
6416 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
6419 gas_assert (mo
->name
);
6420 gas_assert (strcmp (name
, mo
->name
) == 0);
6423 create_insn (&insn
, mo
);
6461 gas_assert (ep
!= NULL
);
6463 if (ep
->X_op
!= O_constant
)
6464 *r
= (int) BFD_RELOC_UNUSED
+ c
;
6465 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
6467 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
6469 *r
= BFD_RELOC_UNUSED
;
6475 operand
= decode_mips16_operand (c
, FALSE
);
6479 insn_insert_operand (&insn
, operand
, va_arg (args
, int));
6484 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6486 append_insn (&insn
, ep
, r
, TRUE
);
6490 * Sign-extend 32-bit mode constants that have bit 31 set and all
6491 * higher bits unset.
6494 normalize_constant_expr (expressionS
*ex
)
6496 if (ex
->X_op
== O_constant
6497 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
6498 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
6503 * Sign-extend 32-bit mode address offsets that have bit 31 set and
6504 * all higher bits unset.
6507 normalize_address_expr (expressionS
*ex
)
6509 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
6510 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
6511 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
6512 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
6517 * Generate a "jalr" instruction with a relocation hint to the called
6518 * function. This occurs in NewABI PIC code.
6521 macro_build_jalr (expressionS
*ep
, int cprestore
)
6523 static const bfd_reloc_code_real_type jalr_relocs
[2]
6524 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
6525 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
6529 if (MIPS_JALR_HINT_P (ep
))
6534 if (mips_opts
.micromips
)
6536 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
6537 ? "jalr" : "jalrs");
6538 if (MIPS_JALR_HINT_P (ep
)
6540 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6541 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
6543 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
6546 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
6547 if (MIPS_JALR_HINT_P (ep
))
6548 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
6552 * Generate a "lui" instruction.
6555 macro_build_lui (expressionS
*ep
, int regnum
)
6557 gas_assert (! mips_opts
.mips16
);
6559 if (ep
->X_op
!= O_constant
)
6561 gas_assert (ep
->X_op
== O_symbol
);
6562 /* _gp_disp is a special case, used from s_cpload.
6563 __gnu_local_gp is used if mips_no_shared. */
6564 gas_assert (mips_pic
== NO_PIC
6566 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
6567 || (! mips_in_shared
6568 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
6569 "__gnu_local_gp") == 0));
6572 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
6575 /* Generate a sequence of instructions to do a load or store from a constant
6576 offset off of a base register (breg) into/from a target register (treg),
6577 using AT if necessary. */
6579 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
6580 int treg
, int breg
, int dbl
)
6582 gas_assert (ep
->X_op
== O_constant
);
6584 /* Sign-extending 32-bit constants makes their handling easier. */
6586 normalize_constant_expr (ep
);
6588 /* Right now, this routine can only handle signed 32-bit constants. */
6589 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
6590 as_warn (_("operand overflow"));
6592 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
6594 /* Signed 16-bit offset will fit in the op. Easy! */
6595 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6599 /* 32-bit offset, need multiple instructions and AT, like:
6600 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
6601 addu $tempreg,$tempreg,$breg
6602 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
6603 to handle the complete offset. */
6604 macro_build_lui (ep
, AT
);
6605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
6606 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6609 as_bad (_("Macro used $at after \".set noat\""));
6614 * Generates code to set the $at register to true (one)
6615 * if reg is less than the immediate expression.
6618 set_at (int reg
, int unsignedp
)
6620 if (imm_expr
.X_op
== O_constant
6621 && imm_expr
.X_add_number
>= -0x8000
6622 && imm_expr
.X_add_number
< 0x8000)
6623 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
6624 AT
, reg
, BFD_RELOC_LO16
);
6627 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6628 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
6632 /* Warn if an expression is not a constant. */
6635 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
6637 if (ex
->X_op
== O_big
)
6638 as_bad (_("unsupported large constant"));
6639 else if (ex
->X_op
!= O_constant
)
6640 as_bad (_("Instruction %s requires absolute expression"),
6643 if (HAVE_32BIT_GPRS
)
6644 normalize_constant_expr (ex
);
6647 /* Count the leading zeroes by performing a binary chop. This is a
6648 bulky bit of source, but performance is a LOT better for the
6649 majority of values than a simple loop to count the bits:
6650 for (lcnt = 0; (lcnt < 32); lcnt++)
6651 if ((v) & (1 << (31 - lcnt)))
6653 However it is not code size friendly, and the gain will drop a bit
6654 on certain cached systems.
6656 #define COUNT_TOP_ZEROES(v) \
6657 (((v) & ~0xffff) == 0 \
6658 ? ((v) & ~0xff) == 0 \
6659 ? ((v) & ~0xf) == 0 \
6660 ? ((v) & ~0x3) == 0 \
6661 ? ((v) & ~0x1) == 0 \
6666 : ((v) & ~0x7) == 0 \
6669 : ((v) & ~0x3f) == 0 \
6670 ? ((v) & ~0x1f) == 0 \
6673 : ((v) & ~0x7f) == 0 \
6676 : ((v) & ~0xfff) == 0 \
6677 ? ((v) & ~0x3ff) == 0 \
6678 ? ((v) & ~0x1ff) == 0 \
6681 : ((v) & ~0x7ff) == 0 \
6684 : ((v) & ~0x3fff) == 0 \
6685 ? ((v) & ~0x1fff) == 0 \
6688 : ((v) & ~0x7fff) == 0 \
6691 : ((v) & ~0xffffff) == 0 \
6692 ? ((v) & ~0xfffff) == 0 \
6693 ? ((v) & ~0x3ffff) == 0 \
6694 ? ((v) & ~0x1ffff) == 0 \
6697 : ((v) & ~0x7ffff) == 0 \
6700 : ((v) & ~0x3fffff) == 0 \
6701 ? ((v) & ~0x1fffff) == 0 \
6704 : ((v) & ~0x7fffff) == 0 \
6707 : ((v) & ~0xfffffff) == 0 \
6708 ? ((v) & ~0x3ffffff) == 0 \
6709 ? ((v) & ~0x1ffffff) == 0 \
6712 : ((v) & ~0x7ffffff) == 0 \
6715 : ((v) & ~0x3fffffff) == 0 \
6716 ? ((v) & ~0x1fffffff) == 0 \
6719 : ((v) & ~0x7fffffff) == 0 \
6724 * This routine generates the least number of instructions necessary to load
6725 * an absolute expression value into a register.
6728 load_register (int reg
, expressionS
*ep
, int dbl
)
6731 expressionS hi32
, lo32
;
6733 if (ep
->X_op
!= O_big
)
6735 gas_assert (ep
->X_op
== O_constant
);
6737 /* Sign-extending 32-bit constants makes their handling easier. */
6739 normalize_constant_expr (ep
);
6741 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
6743 /* We can handle 16 bit signed values with an addiu to
6744 $zero. No need to ever use daddiu here, since $zero and
6745 the result are always correct in 32 bit mode. */
6746 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6749 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
6751 /* We can handle 16 bit unsigned values with an ori to
6753 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6756 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
6758 /* 32 bit values require an lui. */
6759 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6760 if ((ep
->X_add_number
& 0xffff) != 0)
6761 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6766 /* The value is larger than 32 bits. */
6768 if (!dbl
|| HAVE_32BIT_GPRS
)
6772 sprintf_vma (value
, ep
->X_add_number
);
6773 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6774 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6778 if (ep
->X_op
!= O_big
)
6781 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6782 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6783 hi32
.X_add_number
&= 0xffffffff;
6785 lo32
.X_add_number
&= 0xffffffff;
6789 gas_assert (ep
->X_add_number
> 2);
6790 if (ep
->X_add_number
== 3)
6791 generic_bignum
[3] = 0;
6792 else if (ep
->X_add_number
> 4)
6793 as_bad (_("Number larger than 64 bits"));
6794 lo32
.X_op
= O_constant
;
6795 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6796 hi32
.X_op
= O_constant
;
6797 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6800 if (hi32
.X_add_number
== 0)
6805 unsigned long hi
, lo
;
6807 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6809 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6811 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6814 if (lo32
.X_add_number
& 0x80000000)
6816 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6817 if (lo32
.X_add_number
& 0xffff)
6818 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6823 /* Check for 16bit shifted constant. We know that hi32 is
6824 non-zero, so start the mask on the first bit of the hi32
6829 unsigned long himask
, lomask
;
6833 himask
= 0xffff >> (32 - shift
);
6834 lomask
= (0xffff << shift
) & 0xffffffff;
6838 himask
= 0xffff << (shift
- 32);
6841 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6842 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6846 tmp
.X_op
= O_constant
;
6848 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6849 | (lo32
.X_add_number
>> shift
));
6851 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6852 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6853 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6854 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6859 while (shift
<= (64 - 16));
6861 /* Find the bit number of the lowest one bit, and store the
6862 shifted value in hi/lo. */
6863 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6864 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6868 while ((lo
& 1) == 0)
6873 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
6879 while ((hi
& 1) == 0)
6888 /* Optimize if the shifted value is a (power of 2) - 1. */
6889 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
6890 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
6892 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
6897 /* This instruction will set the register to be all
6899 tmp
.X_op
= O_constant
;
6900 tmp
.X_add_number
= (offsetT
) -1;
6901 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6905 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6906 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
6908 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
6909 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6914 /* Sign extend hi32 before calling load_register, because we can
6915 generally get better code when we load a sign extended value. */
6916 if ((hi32
.X_add_number
& 0x80000000) != 0)
6917 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
6918 load_register (reg
, &hi32
, 0);
6921 if ((lo32
.X_add_number
& 0xffff0000) == 0)
6925 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
6933 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
6935 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6936 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
6942 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
6946 mid16
.X_add_number
>>= 16;
6947 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6948 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6951 if ((lo32
.X_add_number
& 0xffff) != 0)
6952 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6956 load_delay_nop (void)
6958 if (!gpr_interlocks
)
6959 macro_build (NULL
, "nop", "");
6962 /* Load an address into a register. */
6965 load_address (int reg
, expressionS
*ep
, int *used_at
)
6967 if (ep
->X_op
!= O_constant
6968 && ep
->X_op
!= O_symbol
)
6970 as_bad (_("expression too complex"));
6971 ep
->X_op
= O_constant
;
6974 if (ep
->X_op
== O_constant
)
6976 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
6980 if (mips_pic
== NO_PIC
)
6982 /* If this is a reference to a GP relative symbol, we want
6983 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6985 lui $reg,<sym> (BFD_RELOC_HI16_S)
6986 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6987 If we have an addend, we always use the latter form.
6989 With 64bit address space and a usable $at we want
6990 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6991 lui $at,<sym> (BFD_RELOC_HI16_S)
6992 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6993 daddiu $at,<sym> (BFD_RELOC_LO16)
6997 If $at is already in use, we use a path which is suboptimal
6998 on superscalar processors.
6999 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7000 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7002 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7004 daddiu $reg,<sym> (BFD_RELOC_LO16)
7006 For GP relative symbols in 64bit address space we can use
7007 the same sequence as in 32bit address space. */
7008 if (HAVE_64BIT_SYMBOLS
)
7010 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7011 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7013 relax_start (ep
->X_add_symbol
);
7014 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7015 mips_gp_register
, BFD_RELOC_GPREL16
);
7019 if (*used_at
== 0 && mips_opts
.at
)
7021 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7022 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7023 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7024 BFD_RELOC_MIPS_HIGHER
);
7025 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7026 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7027 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7032 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7033 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7034 BFD_RELOC_MIPS_HIGHER
);
7035 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7036 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7037 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7038 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7041 if (mips_relax
.sequence
)
7046 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7047 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7049 relax_start (ep
->X_add_symbol
);
7050 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7051 mips_gp_register
, BFD_RELOC_GPREL16
);
7054 macro_build_lui (ep
, reg
);
7055 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7056 reg
, reg
, BFD_RELOC_LO16
);
7057 if (mips_relax
.sequence
)
7061 else if (!mips_big_got
)
7065 /* If this is a reference to an external symbol, we want
7066 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7068 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7070 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7071 If there is a constant, it must be added in after.
7073 If we have NewABI, we want
7074 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7075 unless we're referencing a global symbol with a non-zero
7076 offset, in which case cst must be added separately. */
7079 if (ep
->X_add_number
)
7081 ex
.X_add_number
= ep
->X_add_number
;
7082 ep
->X_add_number
= 0;
7083 relax_start (ep
->X_add_symbol
);
7084 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7085 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7086 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7087 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7088 ex
.X_op
= O_constant
;
7089 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7090 reg
, reg
, BFD_RELOC_LO16
);
7091 ep
->X_add_number
= ex
.X_add_number
;
7094 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7095 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7096 if (mips_relax
.sequence
)
7101 ex
.X_add_number
= ep
->X_add_number
;
7102 ep
->X_add_number
= 0;
7103 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7104 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7106 relax_start (ep
->X_add_symbol
);
7108 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7112 if (ex
.X_add_number
!= 0)
7114 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7115 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7116 ex
.X_op
= O_constant
;
7117 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7118 reg
, reg
, BFD_RELOC_LO16
);
7122 else if (mips_big_got
)
7126 /* This is the large GOT case. If this is a reference to an
7127 external symbol, we want
7128 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7130 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7132 Otherwise, for a reference to a local symbol in old ABI, we want
7133 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7135 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7136 If there is a constant, it must be added in after.
7138 In the NewABI, for local symbols, with or without offsets, we want:
7139 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7140 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7144 ex
.X_add_number
= ep
->X_add_number
;
7145 ep
->X_add_number
= 0;
7146 relax_start (ep
->X_add_symbol
);
7147 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7148 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7149 reg
, reg
, mips_gp_register
);
7150 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7151 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7152 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7153 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7154 else if (ex
.X_add_number
)
7156 ex
.X_op
= O_constant
;
7157 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7161 ep
->X_add_number
= ex
.X_add_number
;
7163 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7164 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7165 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7166 BFD_RELOC_MIPS_GOT_OFST
);
7171 ex
.X_add_number
= ep
->X_add_number
;
7172 ep
->X_add_number
= 0;
7173 relax_start (ep
->X_add_symbol
);
7174 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7176 reg
, reg
, mips_gp_register
);
7177 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7178 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7180 if (reg_needs_delay (mips_gp_register
))
7182 /* We need a nop before loading from $gp. This special
7183 check is required because the lui which starts the main
7184 instruction stream does not refer to $gp, and so will not
7185 insert the nop which may be required. */
7186 macro_build (NULL
, "nop", "");
7188 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7189 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7191 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7195 if (ex
.X_add_number
!= 0)
7197 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7198 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7199 ex
.X_op
= O_constant
;
7200 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7208 if (!mips_opts
.at
&& *used_at
== 1)
7209 as_bad (_("Macro used $at after \".set noat\""));
7212 /* Move the contents of register SOURCE into register DEST. */
7215 move_register (int dest
, int source
)
7217 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7218 instruction specifically requires a 32-bit one. */
7219 if (mips_opts
.micromips
7220 && !mips_opts
.insn32
7221 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7222 macro_build (NULL
, "move", "mp,mj", dest
, source
);
7224 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
7228 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7229 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7230 The two alternatives are:
7232 Global symbol Local sybmol
7233 ------------- ------------
7234 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7236 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7238 load_got_offset emits the first instruction and add_got_offset
7239 emits the second for a 16-bit offset or add_got_offset_hilo emits
7240 a sequence to add a 32-bit offset using a scratch register. */
7243 load_got_offset (int dest
, expressionS
*local
)
7248 global
.X_add_number
= 0;
7250 relax_start (local
->X_add_symbol
);
7251 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7252 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7254 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7255 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7260 add_got_offset (int dest
, expressionS
*local
)
7264 global
.X_op
= O_constant
;
7265 global
.X_op_symbol
= NULL
;
7266 global
.X_add_symbol
= NULL
;
7267 global
.X_add_number
= local
->X_add_number
;
7269 relax_start (local
->X_add_symbol
);
7270 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
7271 dest
, dest
, BFD_RELOC_LO16
);
7273 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
7278 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
7281 int hold_mips_optimize
;
7283 global
.X_op
= O_constant
;
7284 global
.X_op_symbol
= NULL
;
7285 global
.X_add_symbol
= NULL
;
7286 global
.X_add_number
= local
->X_add_number
;
7288 relax_start (local
->X_add_symbol
);
7289 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
7291 /* Set mips_optimize around the lui instruction to avoid
7292 inserting an unnecessary nop after the lw. */
7293 hold_mips_optimize
= mips_optimize
;
7295 macro_build_lui (&global
, tmp
);
7296 mips_optimize
= hold_mips_optimize
;
7297 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
7300 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
7303 /* Emit a sequence of instructions to emulate a branch likely operation.
7304 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7305 is its complementing branch with the original condition negated.
7306 CALL is set if the original branch specified the link operation.
7307 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7309 Code like this is produced in the noreorder mode:
7314 delay slot (executed only if branch taken)
7322 delay slot (executed only if branch taken)
7325 In the reorder mode the delay slot would be filled with a nop anyway,
7326 so code produced is simply:
7331 This function is used when producing code for the microMIPS ASE that
7332 does not implement branch likely instructions in hardware. */
7335 macro_build_branch_likely (const char *br
, const char *brneg
,
7336 int call
, expressionS
*ep
, const char *fmt
,
7337 unsigned int sreg
, unsigned int treg
)
7339 int noreorder
= mips_opts
.noreorder
;
7342 gas_assert (mips_opts
.micromips
);
7346 micromips_label_expr (&expr1
);
7347 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
7348 macro_build (NULL
, "nop", "");
7349 macro_build (ep
, call
? "bal" : "b", "p");
7351 /* Set to true so that append_insn adds a label. */
7352 emit_branch_likely_macro
= TRUE
;
7356 macro_build (ep
, br
, fmt
, sreg
, treg
);
7357 macro_build (NULL
, "nop", "");
7362 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7363 the condition code tested. EP specifies the branch target. */
7366 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
7393 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
7396 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7397 the register tested. EP specifies the branch target. */
7400 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
7402 const char *brneg
= NULL
;
7412 br
= mips_opts
.micromips
? "bgez" : "bgezl";
7416 gas_assert (mips_opts
.micromips
);
7417 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
7425 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
7432 br
= mips_opts
.micromips
? "blez" : "blezl";
7439 br
= mips_opts
.micromips
? "bltz" : "bltzl";
7443 gas_assert (mips_opts
.micromips
);
7444 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
7451 if (mips_opts
.micromips
&& brneg
)
7452 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
7454 macro_build (ep
, br
, "s,p", sreg
);
7457 /* Emit a three-argument branch macro specified by TYPE, using SREG and
7458 TREG as the registers tested. EP specifies the branch target. */
7461 macro_build_branch_rsrt (int type
, expressionS
*ep
,
7462 unsigned int sreg
, unsigned int treg
)
7464 const char *brneg
= NULL
;
7476 br
= mips_opts
.micromips
? "beq" : "beql";
7485 br
= mips_opts
.micromips
? "bne" : "bnel";
7491 if (mips_opts
.micromips
&& brneg
)
7492 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
7494 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
7497 /* Return the high part that should be loaded in order to make the low
7498 part of VALUE accessible using an offset of OFFBITS bits. */
7501 offset_high_part (offsetT value
, unsigned int offbits
)
7508 bias
= 1 << (offbits
- 1);
7509 low_mask
= bias
* 2 - 1;
7510 return (value
+ bias
) & ~low_mask
;
7513 /* Return true if the value stored in offset_expr and offset_reloc
7514 fits into a signed offset of OFFBITS bits. RANGE is the maximum
7515 amount that the caller wants to add without inducing overflow
7516 and ALIGN is the known alignment of the value in bytes. */
7519 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
7523 /* Accept any relocation operator if overflow isn't a concern. */
7524 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7527 /* These relocations are guaranteed not to overflow in correct links. */
7528 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
7529 || gprel16_reloc_p (*offset_reloc
))
7532 if (offset_expr
.X_op
== O_constant
7533 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
7534 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
7541 * This routine implements the seemingly endless macro or synthesized
7542 * instructions and addressing modes in the mips assembly language. Many
7543 * of these macros are simple and are similar to each other. These could
7544 * probably be handled by some kind of table or grammar approach instead of
7545 * this verbose method. Others are not simple macros but are more like
7546 * optimizing code generation.
7547 * One interesting optimization is when several store macros appear
7548 * consecutively that would load AT with the upper half of the same address.
7549 * The ensuing load upper instructions are ommited. This implies some kind
7550 * of global optimization. We currently only optimize within a single macro.
7551 * For many of the load and store macros if the address is specified as a
7552 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
7553 * first load register 'at' with zero and use it as the base register. The
7554 * mips assembler simply uses register $zero. Just one tiny optimization
7558 macro (struct mips_cl_insn
*ip
, char *str
)
7560 unsigned int treg
, sreg
, dreg
, breg
;
7561 unsigned int tempreg
;
7564 expressionS label_expr
;
7579 bfd_boolean large_offset
;
7581 int hold_mips_optimize
;
7584 gas_assert (! mips_opts
.mips16
);
7586 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
7587 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
7588 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
7589 mask
= ip
->insn_mo
->mask
;
7591 label_expr
.X_op
= O_constant
;
7592 label_expr
.X_op_symbol
= NULL
;
7593 label_expr
.X_add_symbol
= NULL
;
7594 label_expr
.X_add_number
= 0;
7596 expr1
.X_op
= O_constant
;
7597 expr1
.X_op_symbol
= NULL
;
7598 expr1
.X_add_symbol
= NULL
;
7599 expr1
.X_add_number
= 1;
7615 if (mips_opts
.micromips
)
7616 micromips_label_expr (&label_expr
);
7618 label_expr
.X_add_number
= 8;
7619 macro_build (&label_expr
, "bgez", "s,p", sreg
);
7621 macro_build (NULL
, "nop", "");
7623 move_register (dreg
, sreg
);
7624 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
7625 if (mips_opts
.micromips
)
7626 micromips_add_label ();
7643 if (!mips_opts
.micromips
)
7645 if (imm_expr
.X_op
== O_constant
7646 && imm_expr
.X_add_number
>= -0x200
7647 && imm_expr
.X_add_number
< 0x200)
7649 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
7658 if (imm_expr
.X_op
== O_constant
7659 && imm_expr
.X_add_number
>= -0x8000
7660 && imm_expr
.X_add_number
< 0x8000)
7662 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7667 load_register (AT
, &imm_expr
, dbl
);
7668 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7687 if (imm_expr
.X_op
== O_constant
7688 && imm_expr
.X_add_number
>= 0
7689 && imm_expr
.X_add_number
< 0x10000)
7691 if (mask
!= M_NOR_I
)
7692 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
7695 macro_build (&imm_expr
, "ori", "t,r,i",
7696 treg
, sreg
, BFD_RELOC_LO16
);
7697 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
7703 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7704 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7708 switch (imm_expr
.X_add_number
)
7711 macro_build (NULL
, "nop", "");
7714 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
7718 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
7719 (int) imm_expr
.X_add_number
);
7722 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
7723 (unsigned long) imm_expr
.X_add_number
);
7732 gas_assert (mips_opts
.micromips
);
7733 macro_build_branch_ccl (mask
, &offset_expr
,
7734 EXTRACT_OPERAND (1, BCC
, *ip
));
7741 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7747 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
7752 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
7759 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
7761 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
7765 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7766 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7767 &offset_expr
, AT
, ZERO
);
7777 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
7783 /* Check for > max integer. */
7784 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7787 /* Result is always false. */
7789 macro_build (NULL
, "nop", "");
7791 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
7794 if (imm_expr
.X_op
!= O_constant
)
7795 as_bad (_("Unsupported large constant"));
7796 ++imm_expr
.X_add_number
;
7800 if (mask
== M_BGEL_I
)
7802 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7804 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7805 &offset_expr
, sreg
);
7808 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7810 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7811 &offset_expr
, sreg
);
7814 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
7817 /* result is always true */
7818 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7819 macro_build (&offset_expr
, "b", "p");
7824 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7825 &offset_expr
, AT
, ZERO
);
7834 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7835 &offset_expr
, ZERO
, treg
);
7839 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7840 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7841 &offset_expr
, AT
, ZERO
);
7850 && imm_expr
.X_op
== O_constant
7851 && imm_expr
.X_add_number
== -1))
7853 if (imm_expr
.X_op
!= O_constant
)
7854 as_bad (_("Unsupported large constant"));
7855 ++imm_expr
.X_add_number
;
7859 if (mask
== M_BGEUL_I
)
7861 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7863 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7864 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7865 &offset_expr
, sreg
, ZERO
);
7870 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7871 &offset_expr
, AT
, ZERO
);
7879 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
7881 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
7885 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7886 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7887 &offset_expr
, AT
, ZERO
);
7895 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7896 &offset_expr
, sreg
, ZERO
);
7902 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7903 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7904 &offset_expr
, AT
, ZERO
);
7912 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7914 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
7918 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7919 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7920 &offset_expr
, AT
, ZERO
);
7927 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7929 if (imm_expr
.X_op
!= O_constant
)
7930 as_bad (_("Unsupported large constant"));
7931 ++imm_expr
.X_add_number
;
7935 if (mask
== M_BLTL_I
)
7937 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7938 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7939 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7940 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7945 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7946 &offset_expr
, AT
, ZERO
);
7954 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7955 &offset_expr
, sreg
, ZERO
);
7961 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7962 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7963 &offset_expr
, AT
, ZERO
);
7972 && imm_expr
.X_op
== O_constant
7973 && imm_expr
.X_add_number
== -1))
7975 if (imm_expr
.X_op
!= O_constant
)
7976 as_bad (_("Unsupported large constant"));
7977 ++imm_expr
.X_add_number
;
7981 if (mask
== M_BLTUL_I
)
7983 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7985 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7986 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7987 &offset_expr
, sreg
, ZERO
);
7992 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7993 &offset_expr
, AT
, ZERO
);
8001 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8003 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
8007 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8008 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8009 &offset_expr
, AT
, ZERO
);
8019 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8020 &offset_expr
, ZERO
, treg
);
8024 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8025 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8026 &offset_expr
, AT
, ZERO
);
8032 /* Use unsigned arithmetic. */
8036 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8038 as_bad (_("Unsupported large constant"));
8043 pos
= imm_expr
.X_add_number
;
8044 size
= imm2_expr
.X_add_number
;
8049 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
8052 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8054 as_bad (_("Improper extract size (%lu, position %lu)"),
8055 (unsigned long) size
, (unsigned long) pos
);
8059 if (size
<= 32 && pos
< 32)
8064 else if (size
<= 32)
8074 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8081 /* Use unsigned arithmetic. */
8085 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8087 as_bad (_("Unsupported large constant"));
8092 pos
= imm_expr
.X_add_number
;
8093 size
= imm2_expr
.X_add_number
;
8098 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
8101 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8103 as_bad (_("Improper insert size (%lu, position %lu)"),
8104 (unsigned long) size
, (unsigned long) pos
);
8108 if (pos
< 32 && (pos
+ size
- 1) < 32)
8123 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8124 (int) (pos
+ size
- 1));
8140 as_warn (_("Divide by zero."));
8142 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8144 macro_build (NULL
, "break", BRK_FMT
, 7);
8151 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8152 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8156 if (mips_opts
.micromips
)
8157 micromips_label_expr (&label_expr
);
8159 label_expr
.X_add_number
= 8;
8160 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8161 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8162 macro_build (NULL
, "break", BRK_FMT
, 7);
8163 if (mips_opts
.micromips
)
8164 micromips_add_label ();
8166 expr1
.X_add_number
= -1;
8168 load_register (AT
, &expr1
, dbl
);
8169 if (mips_opts
.micromips
)
8170 micromips_label_expr (&label_expr
);
8172 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8173 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
8176 expr1
.X_add_number
= 1;
8177 load_register (AT
, &expr1
, dbl
);
8178 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8182 expr1
.X_add_number
= 0x80000000;
8183 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8187 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
8188 /* We want to close the noreorder block as soon as possible, so
8189 that later insns are available for delay slot filling. */
8194 if (mips_opts
.micromips
)
8195 micromips_label_expr (&label_expr
);
8197 label_expr
.X_add_number
= 8;
8198 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
8199 macro_build (NULL
, "nop", "");
8201 /* We want to close the noreorder block as soon as possible, so
8202 that later insns are available for delay slot filling. */
8205 macro_build (NULL
, "break", BRK_FMT
, 6);
8207 if (mips_opts
.micromips
)
8208 micromips_add_label ();
8209 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
8248 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8250 as_warn (_("Divide by zero."));
8252 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8254 macro_build (NULL
, "break", BRK_FMT
, 7);
8257 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8259 if (strcmp (s2
, "mflo") == 0)
8260 move_register (dreg
, sreg
);
8262 move_register (dreg
, ZERO
);
8265 if (imm_expr
.X_op
== O_constant
8266 && imm_expr
.X_add_number
== -1
8267 && s
[strlen (s
) - 1] != 'u')
8269 if (strcmp (s2
, "mflo") == 0)
8271 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
8274 move_register (dreg
, ZERO
);
8279 load_register (AT
, &imm_expr
, dbl
);
8280 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
8281 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8303 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8304 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8305 /* We want to close the noreorder block as soon as possible, so
8306 that later insns are available for delay slot filling. */
8311 if (mips_opts
.micromips
)
8312 micromips_label_expr (&label_expr
);
8314 label_expr
.X_add_number
= 8;
8315 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8316 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8318 /* We want to close the noreorder block as soon as possible, so
8319 that later insns are available for delay slot filling. */
8321 macro_build (NULL
, "break", BRK_FMT
, 7);
8322 if (mips_opts
.micromips
)
8323 micromips_add_label ();
8325 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8337 /* Load the address of a symbol into a register. If breg is not
8338 zero, we then add a base register to it. */
8340 if (dbl
&& HAVE_32BIT_GPRS
)
8341 as_warn (_("dla used to load 32-bit register"));
8343 if (!dbl
&& HAVE_64BIT_OBJECTS
)
8344 as_warn (_("la used to load 64-bit address"));
8346 if (small_offset_p (0, align
, 16))
8348 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", treg
, breg
,
8349 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8353 if (mips_opts
.at
&& (treg
== breg
))
8363 if (offset_expr
.X_op
!= O_symbol
8364 && offset_expr
.X_op
!= O_constant
)
8366 as_bad (_("Expression too complex"));
8367 offset_expr
.X_op
= O_constant
;
8370 if (offset_expr
.X_op
== O_constant
)
8371 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
8372 else if (mips_pic
== NO_PIC
)
8374 /* If this is a reference to a GP relative symbol, we want
8375 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8377 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8378 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8379 If we have a constant, we need two instructions anyhow,
8380 so we may as well always use the latter form.
8382 With 64bit address space and a usable $at we want
8383 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8384 lui $at,<sym> (BFD_RELOC_HI16_S)
8385 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8386 daddiu $at,<sym> (BFD_RELOC_LO16)
8388 daddu $tempreg,$tempreg,$at
8390 If $at is already in use, we use a path which is suboptimal
8391 on superscalar processors.
8392 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8393 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8395 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8397 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8399 For GP relative symbols in 64bit address space we can use
8400 the same sequence as in 32bit address space. */
8401 if (HAVE_64BIT_SYMBOLS
)
8403 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8404 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8406 relax_start (offset_expr
.X_add_symbol
);
8407 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8408 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8412 if (used_at
== 0 && mips_opts
.at
)
8414 macro_build (&offset_expr
, "lui", LUI_FMT
,
8415 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8416 macro_build (&offset_expr
, "lui", LUI_FMT
,
8417 AT
, BFD_RELOC_HI16_S
);
8418 macro_build (&offset_expr
, "daddiu", "t,r,j",
8419 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8420 macro_build (&offset_expr
, "daddiu", "t,r,j",
8421 AT
, AT
, BFD_RELOC_LO16
);
8422 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8423 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8428 macro_build (&offset_expr
, "lui", LUI_FMT
,
8429 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8430 macro_build (&offset_expr
, "daddiu", "t,r,j",
8431 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8432 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8433 macro_build (&offset_expr
, "daddiu", "t,r,j",
8434 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
8435 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8436 macro_build (&offset_expr
, "daddiu", "t,r,j",
8437 tempreg
, tempreg
, BFD_RELOC_LO16
);
8440 if (mips_relax
.sequence
)
8445 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8446 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8448 relax_start (offset_expr
.X_add_symbol
);
8449 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8450 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8453 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8454 as_bad (_("Offset too large"));
8455 macro_build_lui (&offset_expr
, tempreg
);
8456 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8457 tempreg
, tempreg
, BFD_RELOC_LO16
);
8458 if (mips_relax
.sequence
)
8462 else if (!mips_big_got
&& !HAVE_NEWABI
)
8464 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8466 /* If this is a reference to an external symbol, and there
8467 is no constant, we want
8468 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8469 or for lca or if tempreg is PIC_CALL_REG
8470 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8471 For a local symbol, we want
8472 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8474 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8476 If we have a small constant, and this is a reference to
8477 an external symbol, we want
8478 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8480 addiu $tempreg,$tempreg,<constant>
8481 For a local symbol, we want the same instruction
8482 sequence, but we output a BFD_RELOC_LO16 reloc on the
8485 If we have a large constant, and this is a reference to
8486 an external symbol, we want
8487 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8488 lui $at,<hiconstant>
8489 addiu $at,$at,<loconstant>
8490 addu $tempreg,$tempreg,$at
8491 For a local symbol, we want the same instruction
8492 sequence, but we output a BFD_RELOC_LO16 reloc on the
8496 if (offset_expr
.X_add_number
== 0)
8498 if (mips_pic
== SVR4_PIC
8500 && (call
|| tempreg
== PIC_CALL_REG
))
8501 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
8503 relax_start (offset_expr
.X_add_symbol
);
8504 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8505 lw_reloc_type
, mips_gp_register
);
8508 /* We're going to put in an addu instruction using
8509 tempreg, so we may as well insert the nop right
8514 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8515 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8517 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8518 tempreg
, tempreg
, BFD_RELOC_LO16
);
8520 /* FIXME: If breg == 0, and the next instruction uses
8521 $tempreg, then if this variant case is used an extra
8522 nop will be generated. */
8524 else if (offset_expr
.X_add_number
>= -0x8000
8525 && offset_expr
.X_add_number
< 0x8000)
8527 load_got_offset (tempreg
, &offset_expr
);
8529 add_got_offset (tempreg
, &offset_expr
);
8533 expr1
.X_add_number
= offset_expr
.X_add_number
;
8534 offset_expr
.X_add_number
=
8535 SEXT_16BIT (offset_expr
.X_add_number
);
8536 load_got_offset (tempreg
, &offset_expr
);
8537 offset_expr
.X_add_number
= expr1
.X_add_number
;
8538 /* If we are going to add in a base register, and the
8539 target register and the base register are the same,
8540 then we are using AT as a temporary register. Since
8541 we want to load the constant into AT, we add our
8542 current AT (from the global offset table) and the
8543 register into the register now, and pretend we were
8544 not using a base register. */
8548 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8553 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
8557 else if (!mips_big_got
&& HAVE_NEWABI
)
8559 int add_breg_early
= 0;
8561 /* If this is a reference to an external, and there is no
8562 constant, or local symbol (*), with or without a
8564 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8565 or for lca or if tempreg is PIC_CALL_REG
8566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8568 If we have a small constant, and this is a reference to
8569 an external symbol, we want
8570 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8571 addiu $tempreg,$tempreg,<constant>
8573 If we have a large constant, and this is a reference to
8574 an external symbol, we want
8575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8576 lui $at,<hiconstant>
8577 addiu $at,$at,<loconstant>
8578 addu $tempreg,$tempreg,$at
8580 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
8581 local symbols, even though it introduces an additional
8584 if (offset_expr
.X_add_number
)
8586 expr1
.X_add_number
= offset_expr
.X_add_number
;
8587 offset_expr
.X_add_number
= 0;
8589 relax_start (offset_expr
.X_add_symbol
);
8590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8591 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8593 if (expr1
.X_add_number
>= -0x8000
8594 && expr1
.X_add_number
< 0x8000)
8596 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8597 tempreg
, tempreg
, BFD_RELOC_LO16
);
8599 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8601 /* If we are going to add in a base register, and the
8602 target register and the base register are the same,
8603 then we are using AT as a temporary register. Since
8604 we want to load the constant into AT, we add our
8605 current AT (from the global offset table) and the
8606 register into the register now, and pretend we were
8607 not using a base register. */
8612 gas_assert (tempreg
== AT
);
8613 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8619 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8620 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8626 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8629 offset_expr
.X_add_number
= expr1
.X_add_number
;
8631 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8632 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8635 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8636 treg
, tempreg
, breg
);
8642 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
8644 relax_start (offset_expr
.X_add_symbol
);
8645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8646 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
8648 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8649 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8654 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8655 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8658 else if (mips_big_got
&& !HAVE_NEWABI
)
8661 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8662 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8663 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8665 /* This is the large GOT case. If this is a reference to an
8666 external symbol, and there is no constant, we want
8667 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8668 addu $tempreg,$tempreg,$gp
8669 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8670 or for lca or if tempreg is PIC_CALL_REG
8671 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8672 addu $tempreg,$tempreg,$gp
8673 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8674 For a local symbol, we want
8675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8677 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8679 If we have a small constant, and this is a reference to
8680 an external symbol, we want
8681 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8682 addu $tempreg,$tempreg,$gp
8683 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8685 addiu $tempreg,$tempreg,<constant>
8686 For a local symbol, we want
8687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8689 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
8691 If we have a large constant, and this is a reference to
8692 an external symbol, we want
8693 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8694 addu $tempreg,$tempreg,$gp
8695 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8696 lui $at,<hiconstant>
8697 addiu $at,$at,<loconstant>
8698 addu $tempreg,$tempreg,$at
8699 For a local symbol, we want
8700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8701 lui $at,<hiconstant>
8702 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
8703 addu $tempreg,$tempreg,$at
8706 expr1
.X_add_number
= offset_expr
.X_add_number
;
8707 offset_expr
.X_add_number
= 0;
8708 relax_start (offset_expr
.X_add_symbol
);
8709 gpdelay
= reg_needs_delay (mips_gp_register
);
8710 if (expr1
.X_add_number
== 0 && breg
== 0
8711 && (call
|| tempreg
== PIC_CALL_REG
))
8713 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8714 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8716 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8717 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8718 tempreg
, tempreg
, mips_gp_register
);
8719 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8720 tempreg
, lw_reloc_type
, tempreg
);
8721 if (expr1
.X_add_number
== 0)
8725 /* We're going to put in an addu instruction using
8726 tempreg, so we may as well insert the nop right
8731 else if (expr1
.X_add_number
>= -0x8000
8732 && expr1
.X_add_number
< 0x8000)
8735 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8736 tempreg
, tempreg
, BFD_RELOC_LO16
);
8740 /* If we are going to add in a base register, and the
8741 target register and the base register are the same,
8742 then we are using AT as a temporary register. Since
8743 we want to load the constant into AT, we add our
8744 current AT (from the global offset table) and the
8745 register into the register now, and pretend we were
8746 not using a base register. */
8751 gas_assert (tempreg
== AT
);
8753 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8758 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8759 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8763 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
8768 /* This is needed because this instruction uses $gp, but
8769 the first instruction on the main stream does not. */
8770 macro_build (NULL
, "nop", "");
8773 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8774 local_reloc_type
, mips_gp_register
);
8775 if (expr1
.X_add_number
>= -0x8000
8776 && expr1
.X_add_number
< 0x8000)
8779 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8780 tempreg
, tempreg
, BFD_RELOC_LO16
);
8781 /* FIXME: If add_number is 0, and there was no base
8782 register, the external symbol case ended with a load,
8783 so if the symbol turns out to not be external, and
8784 the next instruction uses tempreg, an unnecessary nop
8785 will be inserted. */
8791 /* We must add in the base register now, as in the
8792 external symbol case. */
8793 gas_assert (tempreg
== AT
);
8795 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8798 /* We set breg to 0 because we have arranged to add
8799 it in in both cases. */
8803 macro_build_lui (&expr1
, AT
);
8804 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8805 AT
, AT
, BFD_RELOC_LO16
);
8806 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8807 tempreg
, tempreg
, AT
);
8812 else if (mips_big_got
&& HAVE_NEWABI
)
8814 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8815 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8816 int add_breg_early
= 0;
8818 /* This is the large GOT case. If this is a reference to an
8819 external symbol, and there is no constant, we want
8820 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8821 add $tempreg,$tempreg,$gp
8822 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8823 or for lca or if tempreg is PIC_CALL_REG
8824 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8825 add $tempreg,$tempreg,$gp
8826 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8828 If we have a small constant, and this is a reference to
8829 an external symbol, we want
8830 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8831 add $tempreg,$tempreg,$gp
8832 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8833 addi $tempreg,$tempreg,<constant>
8835 If we have a large constant, and this is a reference to
8836 an external symbol, we want
8837 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8838 addu $tempreg,$tempreg,$gp
8839 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8840 lui $at,<hiconstant>
8841 addi $at,$at,<loconstant>
8842 add $tempreg,$tempreg,$at
8844 If we have NewABI, and we know it's a local symbol, we want
8845 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8846 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8847 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8849 relax_start (offset_expr
.X_add_symbol
);
8851 expr1
.X_add_number
= offset_expr
.X_add_number
;
8852 offset_expr
.X_add_number
= 0;
8854 if (expr1
.X_add_number
== 0 && breg
== 0
8855 && (call
|| tempreg
== PIC_CALL_REG
))
8857 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8858 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8860 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8861 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8862 tempreg
, tempreg
, mips_gp_register
);
8863 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8864 tempreg
, lw_reloc_type
, tempreg
);
8866 if (expr1
.X_add_number
== 0)
8868 else if (expr1
.X_add_number
>= -0x8000
8869 && expr1
.X_add_number
< 0x8000)
8871 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8872 tempreg
, tempreg
, BFD_RELOC_LO16
);
8874 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8876 /* If we are going to add in a base register, and the
8877 target register and the base register are the same,
8878 then we are using AT as a temporary register. Since
8879 we want to load the constant into AT, we add our
8880 current AT (from the global offset table) and the
8881 register into the register now, and pretend we were
8882 not using a base register. */
8887 gas_assert (tempreg
== AT
);
8888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8894 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8895 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8900 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8903 offset_expr
.X_add_number
= expr1
.X_add_number
;
8904 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8905 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8906 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8907 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
8910 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8911 treg
, tempreg
, breg
);
8921 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
8925 gas_assert (!mips_opts
.micromips
);
8926 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x01);
8930 gas_assert (!mips_opts
.micromips
);
8931 macro_build (NULL
, "c2", "C", 0x02);
8935 gas_assert (!mips_opts
.micromips
);
8936 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x02);
8940 gas_assert (!mips_opts
.micromips
);
8941 macro_build (NULL
, "c2", "C", 3);
8945 gas_assert (!mips_opts
.micromips
);
8946 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x03);
8950 /* The j instruction may not be used in PIC code, since it
8951 requires an absolute address. We convert it to a b
8953 if (mips_pic
== NO_PIC
)
8954 macro_build (&offset_expr
, "j", "a");
8956 macro_build (&offset_expr
, "b", "p");
8959 /* The jal instructions must be handled as macros because when
8960 generating PIC code they expand to multi-instruction
8961 sequences. Normally they are simple instructions. */
8966 gas_assert (mips_opts
.micromips
);
8967 if (mips_opts
.insn32
)
8969 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8979 if (mips_pic
== NO_PIC
)
8981 s
= jals
? "jalrs" : "jalr";
8982 if (mips_opts
.micromips
8983 && !mips_opts
.insn32
8985 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8986 macro_build (NULL
, s
, "mj", sreg
);
8988 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8992 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
8993 && mips_cprestore_offset
>= 0);
8995 if (sreg
!= PIC_CALL_REG
)
8996 as_warn (_("MIPS PIC call to register other than $25"));
8998 s
= ((mips_opts
.micromips
8999 && !mips_opts
.insn32
9000 && (!mips_opts
.noreorder
|| cprestore
))
9001 ? "jalrs" : "jalr");
9002 if (mips_opts
.micromips
9003 && !mips_opts
.insn32
9005 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9006 macro_build (NULL
, s
, "mj", sreg
);
9008 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9009 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9011 if (mips_cprestore_offset
< 0)
9012 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9015 if (!mips_frame_reg_valid
)
9017 as_warn (_("No .frame pseudo-op used in PIC code"));
9018 /* Quiet this warning. */
9019 mips_frame_reg_valid
= 1;
9021 if (!mips_cprestore_valid
)
9023 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9024 /* Quiet this warning. */
9025 mips_cprestore_valid
= 1;
9027 if (mips_opts
.noreorder
)
9028 macro_build (NULL
, "nop", "");
9029 expr1
.X_add_number
= mips_cprestore_offset
;
9030 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9033 HAVE_64BIT_ADDRESSES
);
9041 gas_assert (mips_opts
.micromips
);
9042 if (mips_opts
.insn32
)
9044 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9050 if (mips_pic
== NO_PIC
)
9051 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9052 else if (mips_pic
== SVR4_PIC
)
9054 /* If this is a reference to an external symbol, and we are
9055 using a small GOT, we want
9056 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9060 lw $gp,cprestore($sp)
9061 The cprestore value is set using the .cprestore
9062 pseudo-op. If we are using a big GOT, we want
9063 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9065 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9069 lw $gp,cprestore($sp)
9070 If the symbol is not external, we want
9071 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9073 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9076 lw $gp,cprestore($sp)
9078 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9079 sequences above, minus nops, unless the symbol is local,
9080 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9086 relax_start (offset_expr
.X_add_symbol
);
9087 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9088 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9091 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9092 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9098 relax_start (offset_expr
.X_add_symbol
);
9099 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9100 BFD_RELOC_MIPS_CALL_HI16
);
9101 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9102 PIC_CALL_REG
, mips_gp_register
);
9103 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9104 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9107 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9108 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9110 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9111 PIC_CALL_REG
, PIC_CALL_REG
,
9112 BFD_RELOC_MIPS_GOT_OFST
);
9116 macro_build_jalr (&offset_expr
, 0);
9120 relax_start (offset_expr
.X_add_symbol
);
9123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9124 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9133 gpdelay
= reg_needs_delay (mips_gp_register
);
9134 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9135 BFD_RELOC_MIPS_CALL_HI16
);
9136 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9137 PIC_CALL_REG
, mips_gp_register
);
9138 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9139 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9144 macro_build (NULL
, "nop", "");
9146 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9147 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9150 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9151 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9153 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9155 if (mips_cprestore_offset
< 0)
9156 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9159 if (!mips_frame_reg_valid
)
9161 as_warn (_("No .frame pseudo-op used in PIC code"));
9162 /* Quiet this warning. */
9163 mips_frame_reg_valid
= 1;
9165 if (!mips_cprestore_valid
)
9167 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9168 /* Quiet this warning. */
9169 mips_cprestore_valid
= 1;
9171 if (mips_opts
.noreorder
)
9172 macro_build (NULL
, "nop", "");
9173 expr1
.X_add_number
= mips_cprestore_offset
;
9174 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9177 HAVE_64BIT_ADDRESSES
);
9181 else if (mips_pic
== VXWORKS_PIC
)
9182 as_bad (_("Non-PIC jump used in PIC library"));
9260 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9266 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9291 gas_assert (!mips_opts
.micromips
);
9294 /* Itbl support may require additional care here. */
9300 /* Itbl support may require additional care here. */
9306 offbits
= (mips_opts
.micromips
? 12 : 16);
9307 /* Itbl support may require additional care here. */
9311 gas_assert (!mips_opts
.micromips
);
9314 /* Itbl support may require additional care here. */
9320 offbits
= (mips_opts
.micromips
? 12 : 16);
9325 offbits
= (mips_opts
.micromips
? 12 : 16);
9330 /* Itbl support may require additional care here. */
9336 offbits
= (mips_opts
.micromips
? 12 : 16);
9337 /* Itbl support may require additional care here. */
9343 /* Itbl support may require additional care here. */
9349 /* Itbl support may require additional care here. */
9355 offbits
= (mips_opts
.micromips
? 12 : 16);
9360 offbits
= (mips_opts
.micromips
? 12 : 16);
9365 offbits
= (mips_opts
.micromips
? 12 : 16);
9370 offbits
= (mips_opts
.micromips
? 12 : 16);
9375 offbits
= (mips_opts
.micromips
? 12 : 16);
9378 gas_assert (mips_opts
.micromips
);
9385 gas_assert (mips_opts
.micromips
);
9392 gas_assert (mips_opts
.micromips
);
9398 gas_assert (mips_opts
.micromips
);
9405 /* We don't want to use $0 as tempreg. */
9406 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
9409 tempreg
= treg
+ lp
;
9425 gas_assert (!mips_opts
.micromips
);
9428 /* Itbl support may require additional care here. */
9434 /* Itbl support may require additional care here. */
9440 offbits
= (mips_opts
.micromips
? 12 : 16);
9441 /* Itbl support may require additional care here. */
9445 gas_assert (!mips_opts
.micromips
);
9448 /* Itbl support may require additional care here. */
9454 offbits
= (mips_opts
.micromips
? 12 : 16);
9459 offbits
= (mips_opts
.micromips
? 12 : 16);
9464 offbits
= (mips_opts
.micromips
? 12 : 16);
9469 offbits
= (mips_opts
.micromips
? 12 : 16);
9473 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
9474 offbits
= (mips_opts
.micromips
? 12 : 16);
9483 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
9484 offbits
= (mips_opts
.micromips
? 12 : 16);
9495 /* Itbl support may require additional care here. */
9500 offbits
= (mips_opts
.micromips
? 12 : 16);
9501 /* Itbl support may require additional care here. */
9507 /* Itbl support may require additional care here. */
9511 gas_assert (!mips_opts
.micromips
);
9514 /* Itbl support may require additional care here. */
9520 offbits
= (mips_opts
.micromips
? 12 : 16);
9525 offbits
= (mips_opts
.micromips
? 12 : 16);
9528 gas_assert (mips_opts
.micromips
);
9534 gas_assert (mips_opts
.micromips
);
9540 gas_assert (mips_opts
.micromips
);
9546 gas_assert (mips_opts
.micromips
);
9554 if (small_offset_p (0, align
, 16))
9556 /* The first case exists for M_LD_AB and M_SD_AB, which are
9557 macros for o32 but which should act like normal instructions
9560 macro_build (&offset_expr
, s
, fmt
, treg
, -1, offset_reloc
[0],
9561 offset_reloc
[1], offset_reloc
[2], breg
);
9562 else if (small_offset_p (0, align
, offbits
))
9565 macro_build (NULL
, s
, fmt
, treg
, breg
);
9567 macro_build (NULL
, s
, fmt
, treg
,
9568 (int) offset_expr
.X_add_number
, breg
);
9574 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9575 tempreg
, breg
, -1, offset_reloc
[0],
9576 offset_reloc
[1], offset_reloc
[2]);
9578 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9580 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
9588 if (offset_expr
.X_op
!= O_constant
9589 && offset_expr
.X_op
!= O_symbol
)
9591 as_bad (_("Expression too complex"));
9592 offset_expr
.X_op
= O_constant
;
9595 if (HAVE_32BIT_ADDRESSES
9596 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9600 sprintf_vma (value
, offset_expr
.X_add_number
);
9601 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9604 /* A constant expression in PIC code can be handled just as it
9605 is in non PIC code. */
9606 if (offset_expr
.X_op
== O_constant
)
9608 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
9609 offbits
== 0 ? 16 : offbits
);
9610 offset_expr
.X_add_number
-= expr1
.X_add_number
;
9612 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
9614 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9615 tempreg
, tempreg
, breg
);
9618 if (offset_expr
.X_add_number
!= 0)
9619 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
9620 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
9621 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9623 else if (offbits
== 16)
9624 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9626 macro_build (NULL
, s
, fmt
, treg
,
9627 (int) offset_expr
.X_add_number
, tempreg
);
9629 else if (offbits
!= 16)
9631 /* The offset field is too narrow to be used for a low-part
9632 relocation, so load the whole address into the auxillary
9634 load_address (tempreg
, &offset_expr
, &used_at
);
9636 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9637 tempreg
, tempreg
, breg
);
9639 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9641 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
9643 else if (mips_pic
== NO_PIC
)
9645 /* If this is a reference to a GP relative symbol, and there
9646 is no base register, we want
9647 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9648 Otherwise, if there is no base register, we want
9649 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9650 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9651 If we have a constant, we need two instructions anyhow,
9652 so we always use the latter form.
9654 If we have a base register, and this is a reference to a
9655 GP relative symbol, we want
9656 addu $tempreg,$breg,$gp
9657 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
9659 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9660 addu $tempreg,$tempreg,$breg
9661 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9662 With a constant we always use the latter case.
9664 With 64bit address space and no base register and $at usable,
9666 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9667 lui $at,<sym> (BFD_RELOC_HI16_S)
9668 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9671 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9672 If we have a base register, we want
9673 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9674 lui $at,<sym> (BFD_RELOC_HI16_S)
9675 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9679 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9681 Without $at we can't generate the optimal path for superscalar
9682 processors here since this would require two temporary registers.
9683 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9684 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9686 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9688 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9689 If we have a base register, we want
9690 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9691 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9693 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9695 daddu $tempreg,$tempreg,$breg
9696 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9698 For GP relative symbols in 64bit address space we can use
9699 the same sequence as in 32bit address space. */
9700 if (HAVE_64BIT_SYMBOLS
)
9702 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9703 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9705 relax_start (offset_expr
.X_add_symbol
);
9708 macro_build (&offset_expr
, s
, fmt
, treg
,
9709 BFD_RELOC_GPREL16
, mips_gp_register
);
9713 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9714 tempreg
, breg
, mips_gp_register
);
9715 macro_build (&offset_expr
, s
, fmt
, treg
,
9716 BFD_RELOC_GPREL16
, tempreg
);
9721 if (used_at
== 0 && mips_opts
.at
)
9723 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9724 BFD_RELOC_MIPS_HIGHEST
);
9725 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9727 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9728 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9730 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9731 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9732 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9733 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9739 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9740 BFD_RELOC_MIPS_HIGHEST
);
9741 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9742 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9743 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9744 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9745 tempreg
, BFD_RELOC_HI16_S
);
9746 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9748 macro_build (NULL
, "daddu", "d,v,t",
9749 tempreg
, tempreg
, breg
);
9750 macro_build (&offset_expr
, s
, fmt
, treg
,
9751 BFD_RELOC_LO16
, tempreg
);
9754 if (mips_relax
.sequence
)
9761 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9762 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9764 relax_start (offset_expr
.X_add_symbol
);
9765 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9769 macro_build_lui (&offset_expr
, tempreg
);
9770 macro_build (&offset_expr
, s
, fmt
, treg
,
9771 BFD_RELOC_LO16
, tempreg
);
9772 if (mips_relax
.sequence
)
9777 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9778 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9780 relax_start (offset_expr
.X_add_symbol
);
9781 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9782 tempreg
, breg
, mips_gp_register
);
9783 macro_build (&offset_expr
, s
, fmt
, treg
,
9784 BFD_RELOC_GPREL16
, tempreg
);
9787 macro_build_lui (&offset_expr
, tempreg
);
9788 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9789 tempreg
, tempreg
, breg
);
9790 macro_build (&offset_expr
, s
, fmt
, treg
,
9791 BFD_RELOC_LO16
, tempreg
);
9792 if (mips_relax
.sequence
)
9796 else if (!mips_big_got
)
9798 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9800 /* If this is a reference to an external symbol, we want
9801 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9803 <op> $treg,0($tempreg)
9805 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9807 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9808 <op> $treg,0($tempreg)
9811 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9812 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9814 If there is a base register, we add it to $tempreg before
9815 the <op>. If there is a constant, we stick it in the
9816 <op> instruction. We don't handle constants larger than
9817 16 bits, because we have no way to load the upper 16 bits
9818 (actually, we could handle them for the subset of cases
9819 in which we are not using $at). */
9820 gas_assert (offset_expr
.X_op
== O_symbol
);
9823 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9824 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9826 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9827 tempreg
, tempreg
, breg
);
9828 macro_build (&offset_expr
, s
, fmt
, treg
,
9829 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9832 expr1
.X_add_number
= offset_expr
.X_add_number
;
9833 offset_expr
.X_add_number
= 0;
9834 if (expr1
.X_add_number
< -0x8000
9835 || expr1
.X_add_number
>= 0x8000)
9836 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9837 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9838 lw_reloc_type
, mips_gp_register
);
9840 relax_start (offset_expr
.X_add_symbol
);
9842 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9843 tempreg
, BFD_RELOC_LO16
);
9846 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9847 tempreg
, tempreg
, breg
);
9848 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9850 else if (mips_big_got
&& !HAVE_NEWABI
)
9854 /* If this is a reference to an external symbol, we want
9855 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9856 addu $tempreg,$tempreg,$gp
9857 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9858 <op> $treg,0($tempreg)
9860 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9862 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9863 <op> $treg,0($tempreg)
9864 If there is a base register, we add it to $tempreg before
9865 the <op>. If there is a constant, we stick it in the
9866 <op> instruction. We don't handle constants larger than
9867 16 bits, because we have no way to load the upper 16 bits
9868 (actually, we could handle them for the subset of cases
9869 in which we are not using $at). */
9870 gas_assert (offset_expr
.X_op
== O_symbol
);
9871 expr1
.X_add_number
= offset_expr
.X_add_number
;
9872 offset_expr
.X_add_number
= 0;
9873 if (expr1
.X_add_number
< -0x8000
9874 || expr1
.X_add_number
>= 0x8000)
9875 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9876 gpdelay
= reg_needs_delay (mips_gp_register
);
9877 relax_start (offset_expr
.X_add_symbol
);
9878 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9879 BFD_RELOC_MIPS_GOT_HI16
);
9880 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9882 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9883 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9886 macro_build (NULL
, "nop", "");
9887 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9888 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9890 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9891 tempreg
, BFD_RELOC_LO16
);
9895 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9896 tempreg
, tempreg
, breg
);
9897 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9899 else if (mips_big_got
&& HAVE_NEWABI
)
9901 /* If this is a reference to an external symbol, we want
9902 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9903 add $tempreg,$tempreg,$gp
9904 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9905 <op> $treg,<ofst>($tempreg)
9906 Otherwise, for local symbols, we want:
9907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9908 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9909 gas_assert (offset_expr
.X_op
== O_symbol
);
9910 expr1
.X_add_number
= offset_expr
.X_add_number
;
9911 offset_expr
.X_add_number
= 0;
9912 if (expr1
.X_add_number
< -0x8000
9913 || expr1
.X_add_number
>= 0x8000)
9914 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9915 relax_start (offset_expr
.X_add_symbol
);
9916 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9917 BFD_RELOC_MIPS_GOT_HI16
);
9918 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9920 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9921 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9924 tempreg
, tempreg
, breg
);
9925 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9928 offset_expr
.X_add_number
= expr1
.X_add_number
;
9929 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9930 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9932 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9933 tempreg
, tempreg
, breg
);
9934 macro_build (&offset_expr
, s
, fmt
, treg
,
9935 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9944 gas_assert (mips_opts
.micromips
);
9945 gas_assert (mips_opts
.insn32
);
9947 macro_build (NULL
, "jr", "s", RA
);
9948 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
9949 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
9954 gas_assert (mips_opts
.micromips
);
9955 gas_assert (mips_opts
.insn32
);
9956 macro_build (NULL
, "jr", "s", sreg
);
9957 if (mips_opts
.noreorder
)
9958 macro_build (NULL
, "nop", "");
9963 load_register (treg
, &imm_expr
, 0);
9967 load_register (treg
, &imm_expr
, 1);
9971 if (imm_expr
.X_op
== O_constant
)
9974 load_register (AT
, &imm_expr
, 0);
9975 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9980 gas_assert (offset_expr
.X_op
== O_symbol
9981 && strcmp (segment_name (S_GET_SEGMENT
9982 (offset_expr
.X_add_symbol
)),
9984 && offset_expr
.X_add_number
== 0);
9985 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9986 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9991 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9992 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9993 order 32 bits of the value and the low order 32 bits are either
9994 zero or in OFFSET_EXPR. */
9995 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9997 if (HAVE_64BIT_GPRS
)
9998 load_register (treg
, &imm_expr
, 1);
10003 if (target_big_endian
)
10015 load_register (hreg
, &imm_expr
, 0);
10018 if (offset_expr
.X_op
== O_absent
)
10019 move_register (lreg
, 0);
10022 gas_assert (offset_expr
.X_op
== O_constant
);
10023 load_register (lreg
, &offset_expr
, 0);
10030 /* We know that sym is in the .rdata section. First we get the
10031 upper 16 bits of the address. */
10032 if (mips_pic
== NO_PIC
)
10034 macro_build_lui (&offset_expr
, AT
);
10039 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10040 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10044 /* Now we load the register(s). */
10045 if (HAVE_64BIT_GPRS
)
10048 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10053 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10056 /* FIXME: How in the world do we deal with the possible
10058 offset_expr
.X_add_number
+= 4;
10059 macro_build (&offset_expr
, "lw", "t,o(b)",
10060 treg
+ 1, BFD_RELOC_LO16
, AT
);
10066 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10067 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10068 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10069 the value and the low order 32 bits are either zero or in
10071 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10074 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10075 if (HAVE_64BIT_FPRS
)
10077 gas_assert (HAVE_64BIT_GPRS
);
10078 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
10082 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
10083 if (offset_expr
.X_op
== O_absent
)
10084 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
10087 gas_assert (offset_expr
.X_op
== O_constant
);
10088 load_register (AT
, &offset_expr
, 0);
10089 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10095 gas_assert (offset_expr
.X_op
== O_symbol
10096 && offset_expr
.X_add_number
== 0);
10097 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10098 if (strcmp (s
, ".lit8") == 0)
10100 breg
= mips_gp_register
;
10101 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10102 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10103 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10107 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10109 if (mips_pic
!= NO_PIC
)
10110 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10111 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10114 /* FIXME: This won't work for a 64 bit address. */
10115 macro_build_lui (&offset_expr
, AT
);
10119 offset_reloc
[0] = BFD_RELOC_LO16
;
10120 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10121 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10128 * The MIPS assembler seems to check for X_add_number not
10129 * being double aligned and generating:
10130 * lui at,%hi(foo+1)
10132 * addiu at,at,%lo(foo+1)
10135 * But, the resulting address is the same after relocation so why
10136 * generate the extra instruction?
10138 /* Itbl support may require additional care here. */
10141 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10150 gas_assert (!mips_opts
.micromips
);
10151 /* Itbl support may require additional care here. */
10154 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10174 if (HAVE_64BIT_GPRS
)
10184 if (HAVE_64BIT_GPRS
)
10192 /* Even on a big endian machine $fn comes before $fn+1. We have
10193 to adjust when loading from memory. We set coproc if we must
10194 load $fn+1 first. */
10195 /* Itbl support may require additional care here. */
10196 if (!target_big_endian
)
10199 if (small_offset_p (0, align
, 16))
10202 if (!small_offset_p (4, align
, 16))
10204 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
10205 -1, offset_reloc
[0], offset_reloc
[1],
10207 expr1
.X_add_number
= 0;
10211 offset_reloc
[0] = BFD_RELOC_LO16
;
10212 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10213 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10215 if (strcmp (s
, "lw") == 0 && treg
== breg
)
10217 ep
->X_add_number
+= 4;
10218 macro_build (ep
, s
, fmt
, treg
+ 1, -1, offset_reloc
[0],
10219 offset_reloc
[1], offset_reloc
[2], breg
);
10220 ep
->X_add_number
-= 4;
10221 macro_build (ep
, s
, fmt
, treg
, -1, offset_reloc
[0],
10222 offset_reloc
[1], offset_reloc
[2], breg
);
10226 macro_build (ep
, s
, fmt
, coproc
? treg
+ 1 : treg
, -1,
10227 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10229 ep
->X_add_number
+= 4;
10230 macro_build (ep
, s
, fmt
, coproc
? treg
: treg
+ 1, -1,
10231 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10237 if (offset_expr
.X_op
!= O_symbol
10238 && offset_expr
.X_op
!= O_constant
)
10240 as_bad (_("Expression too complex"));
10241 offset_expr
.X_op
= O_constant
;
10244 if (HAVE_32BIT_ADDRESSES
10245 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10249 sprintf_vma (value
, offset_expr
.X_add_number
);
10250 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10253 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
10255 /* If this is a reference to a GP relative symbol, we want
10256 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10257 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10258 If we have a base register, we use this
10260 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10261 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10262 If this is not a GP relative symbol, we want
10263 lui $at,<sym> (BFD_RELOC_HI16_S)
10264 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10265 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10266 If there is a base register, we add it to $at after the
10267 lui instruction. If there is a constant, we always use
10269 if (offset_expr
.X_op
== O_symbol
10270 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10271 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10273 relax_start (offset_expr
.X_add_symbol
);
10276 tempreg
= mips_gp_register
;
10280 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10281 AT
, breg
, mips_gp_register
);
10286 /* Itbl support may require additional care here. */
10287 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10288 BFD_RELOC_GPREL16
, tempreg
);
10289 offset_expr
.X_add_number
+= 4;
10291 /* Set mips_optimize to 2 to avoid inserting an
10293 hold_mips_optimize
= mips_optimize
;
10295 /* Itbl support may require additional care here. */
10296 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10297 BFD_RELOC_GPREL16
, tempreg
);
10298 mips_optimize
= hold_mips_optimize
;
10302 offset_expr
.X_add_number
-= 4;
10305 if (offset_high_part (offset_expr
.X_add_number
, 16)
10306 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
10308 load_address (AT
, &offset_expr
, &used_at
);
10309 offset_expr
.X_op
= O_constant
;
10310 offset_expr
.X_add_number
= 0;
10313 macro_build_lui (&offset_expr
, AT
);
10315 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10316 /* Itbl support may require additional care here. */
10317 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10318 BFD_RELOC_LO16
, AT
);
10319 /* FIXME: How do we handle overflow here? */
10320 offset_expr
.X_add_number
+= 4;
10321 /* Itbl support may require additional care here. */
10322 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10323 BFD_RELOC_LO16
, AT
);
10324 if (mips_relax
.sequence
)
10327 else if (!mips_big_got
)
10329 /* If this is a reference to an external symbol, we want
10330 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10333 <op> $treg+1,4($at)
10335 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10337 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10338 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10339 If there is a base register we add it to $at before the
10340 lwc1 instructions. If there is a constant we include it
10341 in the lwc1 instructions. */
10343 expr1
.X_add_number
= offset_expr
.X_add_number
;
10344 if (expr1
.X_add_number
< -0x8000
10345 || expr1
.X_add_number
>= 0x8000 - 4)
10346 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10347 load_got_offset (AT
, &offset_expr
);
10350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10352 /* Set mips_optimize to 2 to avoid inserting an undesired
10354 hold_mips_optimize
= mips_optimize
;
10357 /* Itbl support may require additional care here. */
10358 relax_start (offset_expr
.X_add_symbol
);
10359 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10360 BFD_RELOC_LO16
, AT
);
10361 expr1
.X_add_number
+= 4;
10362 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10363 BFD_RELOC_LO16
, AT
);
10365 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10366 BFD_RELOC_LO16
, AT
);
10367 offset_expr
.X_add_number
+= 4;
10368 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10369 BFD_RELOC_LO16
, AT
);
10372 mips_optimize
= hold_mips_optimize
;
10374 else if (mips_big_got
)
10378 /* If this is a reference to an external symbol, we want
10379 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10381 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10384 <op> $treg+1,4($at)
10386 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10388 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10389 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10390 If there is a base register we add it to $at before the
10391 lwc1 instructions. If there is a constant we include it
10392 in the lwc1 instructions. */
10394 expr1
.X_add_number
= offset_expr
.X_add_number
;
10395 offset_expr
.X_add_number
= 0;
10396 if (expr1
.X_add_number
< -0x8000
10397 || expr1
.X_add_number
>= 0x8000 - 4)
10398 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10399 gpdelay
= reg_needs_delay (mips_gp_register
);
10400 relax_start (offset_expr
.X_add_symbol
);
10401 macro_build (&offset_expr
, "lui", LUI_FMT
,
10402 AT
, BFD_RELOC_MIPS_GOT_HI16
);
10403 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10404 AT
, AT
, mips_gp_register
);
10405 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10406 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
10409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10410 /* Itbl support may require additional care here. */
10411 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10412 BFD_RELOC_LO16
, AT
);
10413 expr1
.X_add_number
+= 4;
10415 /* Set mips_optimize to 2 to avoid inserting an undesired
10417 hold_mips_optimize
= mips_optimize
;
10419 /* Itbl support may require additional care here. */
10420 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10421 BFD_RELOC_LO16
, AT
);
10422 mips_optimize
= hold_mips_optimize
;
10423 expr1
.X_add_number
-= 4;
10426 offset_expr
.X_add_number
= expr1
.X_add_number
;
10428 macro_build (NULL
, "nop", "");
10429 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10430 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10434 /* Itbl support may require additional care here. */
10435 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10436 BFD_RELOC_LO16
, AT
);
10437 offset_expr
.X_add_number
+= 4;
10439 /* Set mips_optimize to 2 to avoid inserting an undesired
10441 hold_mips_optimize
= mips_optimize
;
10443 /* Itbl support may require additional care here. */
10444 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10445 BFD_RELOC_LO16
, AT
);
10446 mips_optimize
= hold_mips_optimize
;
10465 /* New code added to support COPZ instructions.
10466 This code builds table entries out of the macros in mip_opcodes.
10467 R4000 uses interlocks to handle coproc delays.
10468 Other chips (like the R3000) require nops to be inserted for delays.
10470 FIXME: Currently, we require that the user handle delays.
10471 In order to fill delay slots for non-interlocked chips,
10472 we must have a way to specify delays based on the coprocessor.
10473 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10474 What are the side-effects of the cop instruction?
10475 What cache support might we have and what are its effects?
10476 Both coprocessor & memory require delays. how long???
10477 What registers are read/set/modified?
10479 If an itbl is provided to interpret cop instructions,
10480 this knowledge can be encoded in the itbl spec. */
10494 gas_assert (!mips_opts
.micromips
);
10495 /* For now we just do C (same as Cz). The parameter will be
10496 stored in insn_opcode by mips_ip. */
10497 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
10501 move_register (dreg
, sreg
);
10505 gas_assert (mips_opts
.micromips
);
10506 gas_assert (mips_opts
.insn32
);
10507 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
10508 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
10509 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
10510 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
10511 move_register (dreg
, sreg
);
10512 move_register (breg
, treg
);
10518 if (mips_opts
.arch
== CPU_R5900
)
10520 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
10524 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
10525 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10532 /* The MIPS assembler some times generates shifts and adds. I'm
10533 not trying to be that fancy. GCC should do this for us
10536 load_register (AT
, &imm_expr
, dbl
);
10537 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
10538 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10551 start_noreorder ();
10554 load_register (AT
, &imm_expr
, dbl
);
10555 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
10556 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10557 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
10558 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
10560 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
10563 if (mips_opts
.micromips
)
10564 micromips_label_expr (&label_expr
);
10566 label_expr
.X_add_number
= 8;
10567 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
10568 macro_build (NULL
, "nop", "");
10569 macro_build (NULL
, "break", BRK_FMT
, 6);
10570 if (mips_opts
.micromips
)
10571 micromips_add_label ();
10574 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10587 start_noreorder ();
10590 load_register (AT
, &imm_expr
, dbl
);
10591 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
10592 sreg
, imm
? AT
: treg
);
10593 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
10594 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10596 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
10599 if (mips_opts
.micromips
)
10600 micromips_label_expr (&label_expr
);
10602 label_expr
.X_add_number
= 8;
10603 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
10604 macro_build (NULL
, "nop", "");
10605 macro_build (NULL
, "break", BRK_FMT
, 6);
10606 if (mips_opts
.micromips
)
10607 micromips_add_label ();
10613 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10624 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
10625 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
10629 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10630 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
10631 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
10632 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10636 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10647 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
10648 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
10652 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10653 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
10654 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
10655 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10664 if (imm_expr
.X_op
!= O_constant
)
10665 as_bad (_("Improper rotate count"));
10666 rot
= imm_expr
.X_add_number
& 0x3f;
10667 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10669 rot
= (64 - rot
) & 0x3f;
10671 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10673 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10678 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10681 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10682 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10685 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10686 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10687 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10695 if (imm_expr
.X_op
!= O_constant
)
10696 as_bad (_("Improper rotate count"));
10697 rot
= imm_expr
.X_add_number
& 0x1f;
10698 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10700 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10705 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10709 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10710 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10711 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10716 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10718 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10722 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10723 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10724 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10725 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10729 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10731 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10735 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10736 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10737 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10738 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10747 if (imm_expr
.X_op
!= O_constant
)
10748 as_bad (_("Improper rotate count"));
10749 rot
= imm_expr
.X_add_number
& 0x3f;
10750 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10753 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10755 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10760 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10763 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10764 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10767 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10768 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10769 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10777 if (imm_expr
.X_op
!= O_constant
)
10778 as_bad (_("Improper rotate count"));
10779 rot
= imm_expr
.X_add_number
& 0x1f;
10780 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10782 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10787 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10791 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10792 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10793 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10799 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10800 else if (treg
== 0)
10801 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10804 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10805 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10810 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10812 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10817 as_warn (_("Instruction %s: result is always false"),
10818 ip
->insn_mo
->name
);
10819 move_register (dreg
, 0);
10822 if (CPU_HAS_SEQ (mips_opts
.arch
)
10823 && -512 <= imm_expr
.X_add_number
10824 && imm_expr
.X_add_number
< 512)
10826 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10827 (int) imm_expr
.X_add_number
);
10830 if (imm_expr
.X_op
== O_constant
10831 && imm_expr
.X_add_number
>= 0
10832 && imm_expr
.X_add_number
< 0x10000)
10834 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10836 else if (imm_expr
.X_op
== O_constant
10837 && imm_expr
.X_add_number
> -0x8000
10838 && imm_expr
.X_add_number
< 0)
10840 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10841 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10842 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10844 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10847 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10848 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10853 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10854 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10857 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10860 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10866 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10867 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10870 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10872 if (imm_expr
.X_op
== O_constant
10873 && imm_expr
.X_add_number
>= -0x8000
10874 && imm_expr
.X_add_number
< 0x8000)
10876 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10877 dreg
, sreg
, BFD_RELOC_LO16
);
10881 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10882 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
10886 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10889 case M_SGT
: /* sreg > treg <==> treg < sreg */
10895 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10898 case M_SGT_I
: /* sreg > I <==> I < sreg */
10905 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10906 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10909 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10915 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10916 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10919 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10926 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10927 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10928 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10932 if (imm_expr
.X_op
== O_constant
10933 && imm_expr
.X_add_number
>= -0x8000
10934 && imm_expr
.X_add_number
< 0x8000)
10936 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10940 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10941 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
10945 if (imm_expr
.X_op
== O_constant
10946 && imm_expr
.X_add_number
>= -0x8000
10947 && imm_expr
.X_add_number
< 0x8000)
10949 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
10954 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10955 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
10960 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
10961 else if (treg
== 0)
10962 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10965 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10966 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10971 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10973 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10978 as_warn (_("Instruction %s: result is always true"),
10979 ip
->insn_mo
->name
);
10980 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10981 dreg
, 0, BFD_RELOC_LO16
);
10984 if (CPU_HAS_SEQ (mips_opts
.arch
)
10985 && -512 <= imm_expr
.X_add_number
10986 && imm_expr
.X_add_number
< 512)
10988 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10989 (int) imm_expr
.X_add_number
);
10992 if (imm_expr
.X_op
== O_constant
10993 && imm_expr
.X_add_number
>= 0
10994 && imm_expr
.X_add_number
< 0x10000)
10996 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10998 else if (imm_expr
.X_op
== O_constant
10999 && imm_expr
.X_add_number
> -0x8000
11000 && imm_expr
.X_add_number
< 0)
11002 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11003 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11004 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11006 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11009 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11010 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
11015 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11016 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11019 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11034 if (!mips_opts
.micromips
)
11036 if (imm_expr
.X_op
== O_constant
11037 && imm_expr
.X_add_number
> -0x200
11038 && imm_expr
.X_add_number
<= 0x200)
11040 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
11049 if (imm_expr
.X_op
== O_constant
11050 && imm_expr
.X_add_number
> -0x8000
11051 && imm_expr
.X_add_number
<= 0x8000)
11053 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11054 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11059 load_register (AT
, &imm_expr
, dbl
);
11060 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
11082 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11083 macro_build (NULL
, s
, "s,t", sreg
, AT
);
11088 gas_assert (!mips_opts
.micromips
);
11089 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11091 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
11092 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
11095 * Is the double cfc1 instruction a bug in the mips assembler;
11096 * or is there a reason for it?
11098 start_noreorder ();
11099 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11100 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11101 macro_build (NULL
, "nop", "");
11102 expr1
.X_add_number
= 3;
11103 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
11104 expr1
.X_add_number
= 2;
11105 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11106 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11107 macro_build (NULL
, "nop", "");
11108 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11110 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
11111 macro_build (NULL
, "nop", "");
11128 offbits
= (mips_opts
.micromips
? 12 : 16);
11134 offbits
= (mips_opts
.micromips
? 12 : 16);
11146 offbits
= (mips_opts
.micromips
? 12 : 16);
11153 offbits
= (mips_opts
.micromips
? 12 : 16);
11158 large_offset
= !small_offset_p (off
, align
, offbits
);
11160 expr1
.X_add_number
= 0;
11165 if (small_offset_p (0, align
, 16))
11166 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11167 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11170 load_address (tempreg
, ep
, &used_at
);
11172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11173 tempreg
, tempreg
, breg
);
11175 offset_reloc
[0] = BFD_RELOC_LO16
;
11176 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11177 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11182 else if (!ust
&& treg
== breg
)
11193 if (!target_big_endian
)
11194 ep
->X_add_number
+= off
;
11196 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11198 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11199 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11201 if (!target_big_endian
)
11202 ep
->X_add_number
-= off
;
11204 ep
->X_add_number
+= off
;
11206 macro_build (NULL
, s2
, "t,~(b)",
11207 tempreg
, (int) ep
->X_add_number
, breg
);
11209 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11210 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11212 /* If necessary, move the result in tempreg to the final destination. */
11213 if (!ust
&& treg
!= tempreg
)
11215 /* Protect second load's delay slot. */
11217 move_register (treg
, tempreg
);
11223 if (target_big_endian
== ust
)
11224 ep
->X_add_number
+= off
;
11225 tempreg
= ust
|| large_offset
? treg
: AT
;
11226 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11227 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11229 /* For halfword transfers we need a temporary register to shuffle
11230 bytes. Unfortunately for M_USH_A we have none available before
11231 the next store as AT holds the base address. We deal with this
11232 case by clobbering TREG and then restoring it as with ULH. */
11233 tempreg
= ust
== large_offset
? treg
: AT
;
11235 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
11237 if (target_big_endian
== ust
)
11238 ep
->X_add_number
-= off
;
11240 ep
->X_add_number
+= off
;
11241 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11242 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11244 /* For M_USH_A re-retrieve the LSB. */
11245 if (ust
&& large_offset
)
11247 if (target_big_endian
)
11248 ep
->X_add_number
+= off
;
11250 ep
->X_add_number
-= off
;
11251 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
11252 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
11254 /* For ULH and M_USH_A OR the LSB in. */
11255 if (!ust
|| large_offset
)
11257 tempreg
= !large_offset
? AT
: treg
;
11258 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
11259 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
11264 /* FIXME: Check if this is one of the itbl macros, since they
11265 are added dynamically. */
11266 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
11269 if (!mips_opts
.at
&& used_at
)
11270 as_bad (_("Macro used $at after \".set noat\""));
11273 /* Implement macros in mips16 mode. */
11276 mips16_macro (struct mips_cl_insn
*ip
)
11279 int xreg
, yreg
, zreg
, tmp
;
11282 const char *s
, *s2
, *s3
;
11284 mask
= ip
->insn_mo
->mask
;
11286 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
11287 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
11288 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
11290 expr1
.X_op
= O_constant
;
11291 expr1
.X_op_symbol
= NULL
;
11292 expr1
.X_add_symbol
= NULL
;
11293 expr1
.X_add_number
= 1;
11312 start_noreorder ();
11313 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
11314 expr1
.X_add_number
= 2;
11315 macro_build (&expr1
, "bnez", "x,p", yreg
);
11316 macro_build (NULL
, "break", "6", 7);
11318 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11319 since that causes an overflow. We should do that as well,
11320 but I don't see how to do the comparisons without a temporary
11323 macro_build (NULL
, s
, "x", zreg
);
11342 start_noreorder ();
11343 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
11344 expr1
.X_add_number
= 2;
11345 macro_build (&expr1
, "bnez", "x,p", yreg
);
11346 macro_build (NULL
, "break", "6", 7);
11348 macro_build (NULL
, s2
, "x", zreg
);
11354 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
11355 macro_build (NULL
, "mflo", "x", zreg
);
11363 if (imm_expr
.X_op
!= O_constant
)
11364 as_bad (_("Unsupported large constant"));
11365 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11366 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
11370 if (imm_expr
.X_op
!= O_constant
)
11371 as_bad (_("Unsupported large constant"));
11372 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11373 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
11377 if (imm_expr
.X_op
!= O_constant
)
11378 as_bad (_("Unsupported large constant"));
11379 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11380 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
11402 goto do_reverse_branch
;
11406 goto do_reverse_branch
;
11418 goto do_reverse_branch
;
11429 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
11430 macro_build (&offset_expr
, s2
, "p");
11457 goto do_addone_branch_i
;
11462 goto do_addone_branch_i
;
11477 goto do_addone_branch_i
;
11483 do_addone_branch_i
:
11484 if (imm_expr
.X_op
!= O_constant
)
11485 as_bad (_("Unsupported large constant"));
11486 ++imm_expr
.X_add_number
;
11489 macro_build (&imm_expr
, s
, s3
, xreg
);
11490 macro_build (&offset_expr
, s2
, "p");
11494 expr1
.X_add_number
= 0;
11495 macro_build (&expr1
, "slti", "x,8", yreg
);
11497 move_register (xreg
, yreg
);
11498 expr1
.X_add_number
= 2;
11499 macro_build (&expr1
, "bteqz", "p");
11500 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
11504 /* UDI immediates. */
11505 struct mips_immed
{
11507 unsigned int shift
;
11508 unsigned long mask
;
11512 static const struct mips_immed mips_immed
[] = {
11513 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
11514 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
11515 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
11516 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
11520 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11521 taking bits from BIT up. */
11523 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
11525 return (ep
->X_op
== O_constant
11526 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
11527 && ep
->X_add_number
>= min
<< bit
11528 && ep
->X_add_number
< max
<< bit
);
11531 /* Assemble an instruction into its binary format. If the instruction
11532 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11533 associated with "I", "+I" and "A" operands respectively. Otherwise
11534 store the value of the relocatable field (if any) in offset_expr.
11535 In both cases set offset_reloc to the relocation operators applied
11539 mips_ip (char *str
, struct mips_cl_insn
*ip
)
11541 bfd_boolean wrong_delay_slot_insns
= FALSE
;
11542 bfd_boolean need_delay_slot_ok
= TRUE
;
11543 struct mips_opcode
*firstinsn
= NULL
;
11544 const struct mips_opcode
*past
;
11545 struct hash_control
*hash
;
11549 struct mips_opcode
*insn
;
11551 unsigned int regno
, regno2
;
11552 unsigned int lastregno
;
11553 unsigned int destregno
= 0;
11554 unsigned int lastpos
= 0;
11555 unsigned int limlo
, limhi
;
11558 offsetT min_range
, max_range
;
11562 unsigned int rtype
;
11568 if (mips_opts
.micromips
)
11570 hash
= micromips_op_hash
;
11571 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11576 past
= &mips_opcodes
[NUMOPCODES
];
11578 forced_insn_length
= 0;
11581 /* We first try to match an instruction up to a space or to the end. */
11582 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11585 /* Make a copy of the instruction so that we can fiddle with it. */
11586 name
= alloca (end
+ 1);
11587 memcpy (name
, str
, end
);
11592 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11594 if (insn
!= NULL
|| !mips_opts
.micromips
)
11596 if (forced_insn_length
)
11599 /* See if there's an instruction size override suffix,
11600 either `16' or `32', at the end of the mnemonic proper,
11601 that defines the operation, i.e. before the first `.'
11602 character if any. Strip it and retry. */
11603 dot
= strchr (name
, '.');
11604 opend
= dot
!= NULL
? dot
- name
: end
;
11607 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11608 forced_insn_length
= 2;
11609 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11610 forced_insn_length
= 4;
11613 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11617 insn_error
= _("Unrecognized opcode");
11621 /* For microMIPS instructions placed in a fixed-length branch delay slot
11622 we make up to two passes over the relevant fragment of the opcode
11623 table. First we try instructions that meet the delay slot's length
11624 requirement. If none matched, then we retry with the remaining ones
11625 and if one matches, then we use it and then issue an appropriate
11626 warning later on. */
11627 argsStart
= s
= str
+ end
;
11630 bfd_boolean delay_slot_ok
;
11631 bfd_boolean size_ok
;
11634 gas_assert (strcmp (insn
->name
, name
) == 0);
11636 ok
= is_opcode_valid (insn
);
11637 size_ok
= is_size_valid (insn
);
11638 delay_slot_ok
= is_delay_slot_valid (insn
);
11639 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11642 wrong_delay_slot_insns
= TRUE
;
11644 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11646 static char buf
[256];
11648 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11653 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11655 gas_assert (firstinsn
);
11656 need_delay_slot_ok
= FALSE
;
11666 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11667 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11668 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11669 else if (mips_opts
.insn32
)
11670 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
11672 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11673 8 * forced_insn_length
);
11679 imm_expr
.X_op
= O_absent
;
11680 imm2_expr
.X_op
= O_absent
;
11681 offset_expr
.X_op
= O_absent
;
11682 offset_reloc
[0] = BFD_RELOC_UNUSED
;
11683 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11684 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11686 create_insn (ip
, insn
);
11689 lastregno
= 0xffffffff;
11690 for (args
= insn
->args
;; ++args
)
11694 s
+= strspn (s
, " \t");
11698 case '\0': /* end of args */
11704 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11705 code) or 14 (for microMIPS code). */
11706 my_getExpression (&imm_expr
, s
);
11707 check_absolute_expr (ip
, &imm_expr
);
11708 if ((unsigned long) imm_expr
.X_add_number
!= 1
11709 && (unsigned long) imm_expr
.X_add_number
!= 3)
11711 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11712 (unsigned long) imm_expr
.X_add_number
);
11714 INSERT_OPERAND (mips_opts
.micromips
,
11715 BP
, *ip
, imm_expr
.X_add_number
);
11716 imm_expr
.X_op
= O_absent
;
11721 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11722 code) or 13 (for microMIPS code). */
11724 unsigned long mask
= (mips_opts
.micromips
11725 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11727 my_getExpression (&imm_expr
, s
);
11728 check_absolute_expr (ip
, &imm_expr
);
11729 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11730 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11731 mask
, (unsigned long) imm_expr
.X_add_number
);
11732 INSERT_OPERAND (mips_opts
.micromips
,
11733 SA3
, *ip
, imm_expr
.X_add_number
);
11734 imm_expr
.X_op
= O_absent
;
11740 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11741 code) or 12 (for microMIPS code). */
11743 unsigned long mask
= (mips_opts
.micromips
11744 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11746 my_getExpression (&imm_expr
, s
);
11747 check_absolute_expr (ip
, &imm_expr
);
11748 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11749 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11750 mask
, (unsigned long) imm_expr
.X_add_number
);
11751 INSERT_OPERAND (mips_opts
.micromips
,
11752 SA4
, *ip
, imm_expr
.X_add_number
);
11753 imm_expr
.X_op
= O_absent
;
11759 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11760 code) or 13 (for microMIPS code). */
11762 unsigned long mask
= (mips_opts
.micromips
11763 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11765 my_getExpression (&imm_expr
, s
);
11766 check_absolute_expr (ip
, &imm_expr
);
11767 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11768 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11769 mask
, (unsigned long) imm_expr
.X_add_number
);
11770 INSERT_OPERAND (mips_opts
.micromips
,
11771 IMM8
, *ip
, imm_expr
.X_add_number
);
11772 imm_expr
.X_op
= O_absent
;
11778 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11779 code) or 16 (for microMIPS code). */
11781 unsigned long mask
= (mips_opts
.micromips
11782 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11784 my_getExpression (&imm_expr
, s
);
11785 check_absolute_expr (ip
, &imm_expr
);
11786 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11787 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11788 mask
, (unsigned long) imm_expr
.X_add_number
);
11789 INSERT_OPERAND (mips_opts
.micromips
,
11790 RS
, *ip
, imm_expr
.X_add_number
);
11791 imm_expr
.X_op
= O_absent
;
11797 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11798 or 14 (for microMIPS code). */
11799 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11800 && s
[3] >= '0' && s
[3] <= '3')
11802 regno
= s
[3] - '0';
11804 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11808 as_bad (_("Invalid dsp acc register"));
11812 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11813 code) or 14 (for microMIPS code). */
11815 unsigned long mask
= (mips_opts
.micromips
11816 ? MICROMIPSOP_MASK_WRDSP
11819 my_getExpression (&imm_expr
, s
);
11820 check_absolute_expr (ip
, &imm_expr
);
11821 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11822 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11823 mask
, (unsigned long) imm_expr
.X_add_number
);
11824 INSERT_OPERAND (mips_opts
.micromips
,
11825 WRDSP
, *ip
, imm_expr
.X_add_number
);
11826 imm_expr
.X_op
= O_absent
;
11831 case '9': /* Four DSP accumulators in bits 21,22. */
11832 gas_assert (!mips_opts
.micromips
);
11833 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11834 && s
[3] >= '0' && s
[3] <= '3')
11836 regno
= s
[3] - '0';
11838 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11842 as_bad (_("Invalid dsp acc register"));
11846 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11847 code) or 16 (for microMIPS code). */
11849 long mask
= (mips_opts
.micromips
11850 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11852 my_getExpression (&imm_expr
, s
);
11853 check_absolute_expr (ip
, &imm_expr
);
11854 min_range
= -((mask
+ 1) >> 1);
11855 max_range
= ((mask
+ 1) >> 1) - 1;
11856 if (imm_expr
.X_add_number
< min_range
11857 || imm_expr
.X_add_number
> max_range
)
11858 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11859 (long) min_range
, (long) max_range
,
11860 (long) imm_expr
.X_add_number
);
11861 INSERT_OPERAND (mips_opts
.micromips
,
11862 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11863 imm_expr
.X_op
= O_absent
;
11868 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11869 gas_assert (!mips_opts
.micromips
);
11870 my_getExpression (&imm_expr
, s
);
11871 check_absolute_expr (ip
, &imm_expr
);
11872 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11874 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11876 (unsigned long) imm_expr
.X_add_number
);
11878 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11879 imm_expr
.X_op
= O_absent
;
11883 case ':': /* DSP 7-bit signed immediate in bit 19. */
11884 gas_assert (!mips_opts
.micromips
);
11885 my_getExpression (&imm_expr
, s
);
11886 check_absolute_expr (ip
, &imm_expr
);
11887 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11888 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11889 if (imm_expr
.X_add_number
< min_range
||
11890 imm_expr
.X_add_number
> max_range
)
11892 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11893 (long) min_range
, (long) max_range
,
11894 (long) imm_expr
.X_add_number
);
11896 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11897 imm_expr
.X_op
= O_absent
;
11901 case '@': /* DSP 10-bit signed immediate in bit 16. */
11903 long mask
= (mips_opts
.micromips
11904 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11906 my_getExpression (&imm_expr
, s
);
11907 check_absolute_expr (ip
, &imm_expr
);
11908 min_range
= -((mask
+ 1) >> 1);
11909 max_range
= ((mask
+ 1) >> 1) - 1;
11910 if (imm_expr
.X_add_number
< min_range
11911 || imm_expr
.X_add_number
> max_range
)
11912 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11913 (long) min_range
, (long) max_range
,
11914 (long) imm_expr
.X_add_number
);
11915 INSERT_OPERAND (mips_opts
.micromips
,
11916 IMM10
, *ip
, imm_expr
.X_add_number
);
11917 imm_expr
.X_op
= O_absent
;
11922 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11923 gas_assert (mips_opts
.micromips
);
11924 my_getExpression (&imm_expr
, s
);
11925 check_absolute_expr (ip
, &imm_expr
);
11926 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11927 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11928 MICROMIPSOP_MASK_RD
,
11929 (unsigned long) imm_expr
.X_add_number
);
11930 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11931 imm_expr
.X_op
= O_absent
;
11935 case '!': /* MT usermode flag bit. */
11936 gas_assert (!mips_opts
.micromips
);
11937 my_getExpression (&imm_expr
, s
);
11938 check_absolute_expr (ip
, &imm_expr
);
11939 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11940 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11941 (unsigned long) imm_expr
.X_add_number
);
11942 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11943 imm_expr
.X_op
= O_absent
;
11947 case '$': /* MT load high flag bit. */
11948 gas_assert (!mips_opts
.micromips
);
11949 my_getExpression (&imm_expr
, s
);
11950 check_absolute_expr (ip
, &imm_expr
);
11951 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11952 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11953 (unsigned long) imm_expr
.X_add_number
);
11954 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11955 imm_expr
.X_op
= O_absent
;
11959 case '*': /* Four DSP accumulators in bits 18,19. */
11960 gas_assert (!mips_opts
.micromips
);
11961 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11962 s
[3] >= '0' && s
[3] <= '3')
11964 regno
= s
[3] - '0';
11966 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11970 as_bad (_("Invalid dsp/smartmips acc register"));
11973 case '&': /* Four DSP accumulators in bits 13,14. */
11974 gas_assert (!mips_opts
.micromips
);
11975 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11976 s
[3] >= '0' && s
[3] <= '3')
11978 regno
= s
[3] - '0';
11980 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11984 as_bad (_("Invalid dsp/smartmips acc register"));
11987 case '\\': /* 3-bit bit position. */
11989 unsigned long mask
= (mips_opts
.micromips
11990 ? MICROMIPSOP_MASK_3BITPOS
11991 : OP_MASK_3BITPOS
);
11993 my_getExpression (&imm_expr
, s
);
11994 check_absolute_expr (ip
, &imm_expr
);
11995 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11996 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11998 mask
, (unsigned long) imm_expr
.X_add_number
);
11999 INSERT_OPERAND (mips_opts
.micromips
,
12000 3BITPOS
, *ip
, imm_expr
.X_add_number
);
12001 imm_expr
.X_op
= O_absent
;
12015 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12019 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12023 gas_assert (!mips_opts
.micromips
);
12024 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
12028 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12034 /* Handle optional base register.
12035 Either the base register is omitted or
12036 we must have a left paren. */
12037 /* This is dependent on the next operand specifier
12038 is a base register specification. */
12039 gas_assert (args
[1] == 'b'
12040 || (mips_opts
.micromips
12042 && (args
[2] == 'l' || args
[2] == 'n'
12043 || args
[2] == 's' || args
[2] == 'a')));
12044 if (*s
== '\0' && args
[1] == 'b')
12046 /* Fall through. */
12048 case ')': /* These must match exactly. */
12053 case '+': /* Opcode extension character. */
12056 case '1': /* UDI immediates. */
12060 gas_assert (!mips_opts
.micromips
);
12062 const struct mips_immed
*imm
= mips_immed
;
12064 while (imm
->type
&& imm
->type
!= *args
)
12068 my_getExpression (&imm_expr
, s
);
12069 check_absolute_expr (ip
, &imm_expr
);
12070 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
12072 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
12073 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
12074 (unsigned long) imm_expr
.X_add_number
,
12075 (unsigned long) imm_expr
.X_add_number
);
12076 imm_expr
.X_add_number
&= imm
->mask
;
12078 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
12080 imm_expr
.X_op
= O_absent
;
12085 case 'J': /* 10-bit hypcall code. */
12086 gas_assert (!mips_opts
.micromips
);
12088 unsigned long mask
= OP_MASK_CODE10
;
12090 my_getExpression (&imm_expr
, s
);
12091 check_absolute_expr (ip
, &imm_expr
);
12092 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12093 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12095 mask
, (unsigned long) imm_expr
.X_add_number
);
12096 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
12097 imm_expr
.X_op
= O_absent
;
12102 case 'A': /* ins/ext position, becomes LSB. */
12111 my_getExpression (&imm_expr
, s
);
12112 check_absolute_expr (ip
, &imm_expr
);
12113 if ((unsigned long) imm_expr
.X_add_number
< limlo
12114 || (unsigned long) imm_expr
.X_add_number
> limhi
)
12116 as_bad (_("Improper position (%lu)"),
12117 (unsigned long) imm_expr
.X_add_number
);
12118 imm_expr
.X_add_number
= limlo
;
12120 lastpos
= imm_expr
.X_add_number
;
12121 INSERT_OPERAND (mips_opts
.micromips
,
12122 EXTLSB
, *ip
, imm_expr
.X_add_number
);
12123 imm_expr
.X_op
= O_absent
;
12127 case 'B': /* ins size, becomes MSB. */
12136 my_getExpression (&imm_expr
, s
);
12137 check_absolute_expr (ip
, &imm_expr
);
12138 /* Check for negative input so that small negative numbers
12139 will not succeed incorrectly. The checks against
12140 (pos+size) transitively check "size" itself,
12141 assuming that "pos" is reasonable. */
12142 if ((long) imm_expr
.X_add_number
< 0
12143 || ((unsigned long) imm_expr
.X_add_number
12145 || ((unsigned long) imm_expr
.X_add_number
12146 + lastpos
) > limhi
)
12148 as_bad (_("Improper insert size (%lu, position %lu)"),
12149 (unsigned long) imm_expr
.X_add_number
,
12150 (unsigned long) lastpos
);
12151 imm_expr
.X_add_number
= limlo
- lastpos
;
12153 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
12154 lastpos
+ imm_expr
.X_add_number
- 1);
12155 imm_expr
.X_op
= O_absent
;
12159 case 'C': /* ext size, becomes MSBD. */
12175 my_getExpression (&imm_expr
, s
);
12176 check_absolute_expr (ip
, &imm_expr
);
12177 /* The checks against (pos+size) don't transitively check
12178 "size" itself, assuming that "pos" is reasonable.
12179 We also need to check the lower bound of "size". */
12180 if ((long) imm_expr
.X_add_number
< sizelo
12181 || ((unsigned long) imm_expr
.X_add_number
12183 || ((unsigned long) imm_expr
.X_add_number
12184 + lastpos
) > limhi
)
12186 as_bad (_("Improper extract size (%lu, position %lu)"),
12187 (unsigned long) imm_expr
.X_add_number
,
12188 (unsigned long) lastpos
);
12189 imm_expr
.X_add_number
= limlo
- lastpos
;
12191 INSERT_OPERAND (mips_opts
.micromips
,
12192 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
12193 imm_expr
.X_op
= O_absent
;
12198 /* "+I" is like "I", except that imm2_expr is used. */
12199 my_getExpression (&imm2_expr
, s
);
12200 if (imm2_expr
.X_op
!= O_big
12201 && imm2_expr
.X_op
!= O_constant
)
12202 insn_error
= _("absolute expression required");
12203 if (HAVE_32BIT_GPRS
)
12204 normalize_constant_expr (&imm2_expr
);
12208 case 't': /* Coprocessor register number. */
12209 gas_assert (!mips_opts
.micromips
);
12210 if (s
[0] == '$' && ISDIGIT (s
[1]))
12220 while (ISDIGIT (*s
));
12222 as_bad (_("Invalid register number (%d)"), regno
);
12225 INSERT_OPERAND (0, RT
, *ip
, regno
);
12230 as_bad (_("Invalid coprocessor 0 register number"));
12234 /* bbit[01] and bbit[01]32 bit index. Give error if index
12235 is not in the valid range. */
12236 gas_assert (!mips_opts
.micromips
);
12237 my_getExpression (&imm_expr
, s
);
12238 check_absolute_expr (ip
, &imm_expr
);
12239 if ((unsigned) imm_expr
.X_add_number
> 31)
12241 as_bad (_("Improper bit index (%lu)"),
12242 (unsigned long) imm_expr
.X_add_number
);
12243 imm_expr
.X_add_number
= 0;
12245 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
12246 imm_expr
.X_op
= O_absent
;
12251 /* bbit[01] bit index when bbit is used but we generate
12252 bbit[01]32 because the index is over 32. Move to the
12253 next candidate if index is not in the valid range. */
12254 gas_assert (!mips_opts
.micromips
);
12255 my_getExpression (&imm_expr
, s
);
12256 check_absolute_expr (ip
, &imm_expr
);
12257 if ((unsigned) imm_expr
.X_add_number
< 32
12258 || (unsigned) imm_expr
.X_add_number
> 63)
12260 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
12261 imm_expr
.X_op
= O_absent
;
12266 /* cins, cins32, exts and exts32 position field. Give error
12267 if it's not in the valid range. */
12268 gas_assert (!mips_opts
.micromips
);
12269 my_getExpression (&imm_expr
, s
);
12270 check_absolute_expr (ip
, &imm_expr
);
12271 if ((unsigned) imm_expr
.X_add_number
> 31)
12273 as_bad (_("Improper position (%lu)"),
12274 (unsigned long) imm_expr
.X_add_number
);
12275 imm_expr
.X_add_number
= 0;
12277 lastpos
= imm_expr
.X_add_number
;
12278 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
12279 imm_expr
.X_op
= O_absent
;
12284 /* cins, cins32, exts and exts32 position field. Move to
12285 the next candidate if it's not in the valid range. */
12286 gas_assert (!mips_opts
.micromips
);
12287 my_getExpression (&imm_expr
, s
);
12288 check_absolute_expr (ip
, &imm_expr
);
12289 if ((unsigned) imm_expr
.X_add_number
< 32
12290 || (unsigned) imm_expr
.X_add_number
> 63)
12292 lastpos
= imm_expr
.X_add_number
;
12293 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
12294 imm_expr
.X_op
= O_absent
;
12299 /* cins32 and exts32 length-minus-one field. */
12300 gas_assert (!mips_opts
.micromips
);
12301 my_getExpression (&imm_expr
, s
);
12302 check_absolute_expr (ip
, &imm_expr
);
12303 if ((unsigned long) imm_expr
.X_add_number
> 31
12304 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 31)
12306 as_bad (_("Improper size (%lu)"),
12307 (unsigned long) imm_expr
.X_add_number
);
12308 imm_expr
.X_add_number
= 0;
12310 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12311 imm_expr
.X_op
= O_absent
;
12316 /* cins/exts length-minus-one field. */
12317 gas_assert (!mips_opts
.micromips
);
12318 my_getExpression (&imm_expr
, s
);
12319 check_absolute_expr (ip
, &imm_expr
);
12320 if ((unsigned long) imm_expr
.X_add_number
> 31
12321 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
12323 as_bad (_("Improper size (%lu)"),
12324 (unsigned long) imm_expr
.X_add_number
);
12325 imm_expr
.X_add_number
= 0;
12327 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12328 imm_expr
.X_op
= O_absent
;
12333 /* seqi/snei immediate field. */
12334 gas_assert (!mips_opts
.micromips
);
12335 my_getExpression (&imm_expr
, s
);
12336 check_absolute_expr (ip
, &imm_expr
);
12337 if ((long) imm_expr
.X_add_number
< -512
12338 || (long) imm_expr
.X_add_number
>= 512)
12340 as_bad (_("Improper immediate (%ld)"),
12341 (long) imm_expr
.X_add_number
);
12342 imm_expr
.X_add_number
= 0;
12344 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
12345 imm_expr
.X_op
= O_absent
;
12349 case 'a': /* 8-bit signed offset in bit 6 */
12350 gas_assert (!mips_opts
.micromips
);
12351 my_getExpression (&imm_expr
, s
);
12352 check_absolute_expr (ip
, &imm_expr
);
12353 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
12354 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
12355 if (imm_expr
.X_add_number
< min_range
12356 || imm_expr
.X_add_number
> max_range
)
12358 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12359 (long) min_range
, (long) max_range
,
12360 (long) imm_expr
.X_add_number
);
12362 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
12363 imm_expr
.X_op
= O_absent
;
12367 case 'b': /* 8-bit signed offset in bit 3 */
12368 gas_assert (!mips_opts
.micromips
);
12369 my_getExpression (&imm_expr
, s
);
12370 check_absolute_expr (ip
, &imm_expr
);
12371 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
12372 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
12373 if (imm_expr
.X_add_number
< min_range
12374 || imm_expr
.X_add_number
> max_range
)
12376 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12377 (long) min_range
, (long) max_range
,
12378 (long) imm_expr
.X_add_number
);
12380 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
12381 imm_expr
.X_op
= O_absent
;
12385 case 'c': /* 9-bit signed offset in bit 6 */
12386 gas_assert (!mips_opts
.micromips
);
12387 my_getExpression (&imm_expr
, s
);
12388 check_absolute_expr (ip
, &imm_expr
);
12389 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
12390 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
12391 /* We check the offset range before adjusted. */
12394 if (imm_expr
.X_add_number
< min_range
12395 || imm_expr
.X_add_number
> max_range
)
12397 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12398 (long) min_range
, (long) max_range
,
12399 (long) imm_expr
.X_add_number
);
12401 if (imm_expr
.X_add_number
& 0xf)
12403 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12404 (long) imm_expr
.X_add_number
);
12406 /* Right shift 4 bits to adjust the offset operand. */
12407 INSERT_OPERAND (0, OFFSET_C
, *ip
,
12408 imm_expr
.X_add_number
>> 4);
12409 imm_expr
.X_op
= O_absent
;
12414 gas_assert (!mips_opts
.micromips
);
12415 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
12417 if (regno
== AT
&& mips_opts
.at
)
12419 if (mips_opts
.at
== ATREG
)
12420 as_warn (_("used $at without \".set noat\""));
12422 as_warn (_("used $%u with \".set at=$%u\""),
12423 regno
, mips_opts
.at
);
12425 INSERT_OPERAND (0, RZ
, *ip
, regno
);
12429 gas_assert (!mips_opts
.micromips
);
12430 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
12432 INSERT_OPERAND (0, FZ
, *ip
, regno
);
12442 bfd_reloc_code_real_type r
[3];
12444 /* Check whether there is only a single bracketed expression
12445 left. If so, it must be the base register and the
12446 constant must be zero. */
12447 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12450 /* If this value won't fit into the offset, then go find
12451 a macro that will generate a 16- or 32-bit offset code
12453 i
= my_getSmallExpression (&imm_expr
, r
, s
);
12454 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12455 || imm_expr
.X_add_number
>= 1 << shift
12456 || imm_expr
.X_add_number
< -1 << shift
))
12459 imm_expr
.X_op
= O_absent
;
12462 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
12463 imm_expr
.X_add_number
);
12464 imm_expr
.X_op
= O_absent
;
12470 as_bad (_("Internal error: bad %s opcode "
12471 "(unknown extension operand type `+%c'): %s %s"),
12472 mips_opts
.micromips
? "microMIPS" : "MIPS",
12473 *args
, insn
->name
, insn
->args
);
12474 /* Further processing is fruitless. */
12479 case '.': /* 10-bit offset. */
12480 gas_assert (mips_opts
.micromips
);
12481 case '~': /* 12-bit offset. */
12483 int shift
= *args
== '.' ? 9 : 11;
12485 bfd_reloc_code_real_type r
[3];
12487 /* Check whether there is only a single bracketed expression
12488 left. If so, it must be the base register and the
12489 constant must be zero. */
12490 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12493 /* If this value won't fit into the offset, then go find
12494 a macro that will generate a 16- or 32-bit offset code
12496 i
= my_getSmallExpression (&imm_expr
, r
, s
);
12497 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12498 || imm_expr
.X_add_number
>= 1 << shift
12499 || imm_expr
.X_add_number
< -1 << shift
))
12502 imm_expr
.X_op
= O_absent
;
12506 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
12508 INSERT_OPERAND (mips_opts
.micromips
,
12509 OFFSET12
, *ip
, imm_expr
.X_add_number
);
12510 imm_expr
.X_op
= O_absent
;
12515 case '<': /* must be at least one digit */
12517 * According to the manual, if the shift amount is greater
12518 * than 31 or less than 0, then the shift amount should be
12519 * mod 32. In reality the mips assembler issues an error.
12520 * We issue a warning and mask out all but the low 5 bits.
12522 my_getExpression (&imm_expr
, s
);
12523 check_absolute_expr (ip
, &imm_expr
);
12524 if ((unsigned long) imm_expr
.X_add_number
> 31)
12525 as_warn (_("Improper shift amount (%lu)"),
12526 (unsigned long) imm_expr
.X_add_number
);
12527 INSERT_OPERAND (mips_opts
.micromips
,
12528 SHAMT
, *ip
, imm_expr
.X_add_number
);
12529 imm_expr
.X_op
= O_absent
;
12533 case '>': /* shift amount minus 32 */
12534 my_getExpression (&imm_expr
, s
);
12535 check_absolute_expr (ip
, &imm_expr
);
12536 if ((unsigned long) imm_expr
.X_add_number
< 32
12537 || (unsigned long) imm_expr
.X_add_number
> 63)
12539 INSERT_OPERAND (mips_opts
.micromips
,
12540 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
12541 imm_expr
.X_op
= O_absent
;
12545 case 'k': /* CACHE code. */
12546 case 'h': /* PREFX code. */
12547 case '1': /* SYNC type. */
12548 my_getExpression (&imm_expr
, s
);
12549 check_absolute_expr (ip
, &imm_expr
);
12550 if ((unsigned long) imm_expr
.X_add_number
> 31)
12551 as_warn (_("Invalid value for `%s' (%lu)"),
12553 (unsigned long) imm_expr
.X_add_number
);
12557 if (mips_fix_cn63xxp1
12558 && !mips_opts
.micromips
12559 && strcmp ("pref", insn
->name
) == 0)
12560 switch (imm_expr
.X_add_number
)
12569 case 31: /* These are ok. */
12572 default: /* The rest must be changed to 28. */
12573 imm_expr
.X_add_number
= 28;
12576 INSERT_OPERAND (mips_opts
.micromips
,
12577 CACHE
, *ip
, imm_expr
.X_add_number
);
12580 INSERT_OPERAND (mips_opts
.micromips
,
12581 PREFX
, *ip
, imm_expr
.X_add_number
);
12584 INSERT_OPERAND (mips_opts
.micromips
,
12585 STYPE
, *ip
, imm_expr
.X_add_number
);
12588 imm_expr
.X_op
= O_absent
;
12592 case 'c': /* BREAK code. */
12594 unsigned long mask
= (mips_opts
.micromips
12595 ? MICROMIPSOP_MASK_CODE
12598 my_getExpression (&imm_expr
, s
);
12599 check_absolute_expr (ip
, &imm_expr
);
12600 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12601 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12603 mask
, (unsigned long) imm_expr
.X_add_number
);
12604 INSERT_OPERAND (mips_opts
.micromips
,
12605 CODE
, *ip
, imm_expr
.X_add_number
);
12606 imm_expr
.X_op
= O_absent
;
12611 case 'q': /* Lower BREAK code. */
12613 unsigned long mask
= (mips_opts
.micromips
12614 ? MICROMIPSOP_MASK_CODE2
12617 my_getExpression (&imm_expr
, s
);
12618 check_absolute_expr (ip
, &imm_expr
);
12619 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12620 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12622 mask
, (unsigned long) imm_expr
.X_add_number
);
12623 INSERT_OPERAND (mips_opts
.micromips
,
12624 CODE2
, *ip
, imm_expr
.X_add_number
);
12625 imm_expr
.X_op
= O_absent
;
12630 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12632 unsigned long mask
= (mips_opts
.micromips
12633 ? MICROMIPSOP_MASK_CODE10
12636 my_getExpression (&imm_expr
, s
);
12637 check_absolute_expr (ip
, &imm_expr
);
12638 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12639 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12641 mask
, (unsigned long) imm_expr
.X_add_number
);
12642 if (mips_opts
.micromips
)
12643 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12645 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12646 imm_expr
.X_op
= O_absent
;
12651 case 'C': /* 25- or 23-bit coprocessor code. */
12653 unsigned long mask
= (mips_opts
.micromips
12654 ? MICROMIPSOP_MASK_COPZ
12657 my_getExpression (&imm_expr
, s
);
12658 check_absolute_expr (ip
, &imm_expr
);
12659 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12660 as_warn (_("Coproccesor code > %u bits (%lu)"),
12661 mips_opts
.micromips
? 23U : 25U,
12662 (unsigned long) imm_expr
.X_add_number
);
12663 INSERT_OPERAND (mips_opts
.micromips
,
12664 COPZ
, *ip
, imm_expr
.X_add_number
);
12665 imm_expr
.X_op
= O_absent
;
12670 case 'J': /* 19-bit WAIT code. */
12671 gas_assert (!mips_opts
.micromips
);
12672 my_getExpression (&imm_expr
, s
);
12673 check_absolute_expr (ip
, &imm_expr
);
12674 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12676 as_warn (_("Illegal 19-bit code (%lu)"),
12677 (unsigned long) imm_expr
.X_add_number
);
12678 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12680 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12681 imm_expr
.X_op
= O_absent
;
12685 case 'P': /* Performance register. */
12686 gas_assert (!mips_opts
.micromips
);
12687 my_getExpression (&imm_expr
, s
);
12688 check_absolute_expr (ip
, &imm_expr
);
12689 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12690 as_warn (_("Invalid performance register (%lu)"),
12691 (unsigned long) imm_expr
.X_add_number
);
12692 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12693 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12694 as_warn (_("Invalid performance register (%lu)"),
12695 (unsigned long) imm_expr
.X_add_number
);
12696 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12697 imm_expr
.X_op
= O_absent
;
12701 case 'G': /* Coprocessor destination register. */
12703 unsigned long opcode
= ip
->insn_opcode
;
12704 unsigned long mask
;
12705 unsigned int types
;
12708 if (mips_opts
.micromips
)
12710 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12711 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12712 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12716 case 0x000000fc: /* mfc0 */
12717 case 0x000002fc: /* mtc0 */
12718 case 0x580000fc: /* dmfc0 */
12719 case 0x580002fc: /* dmtc0 */
12729 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12730 cop0
= opcode
== OP_OP_COP0
;
12732 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12733 ok
= reg_lookup (&s
, types
, ®no
);
12734 if (mips_opts
.micromips
)
12735 INSERT_OPERAND (1, RS
, *ip
, regno
);
12737 INSERT_OPERAND (0, RD
, *ip
, regno
);
12746 case 'y': /* ALNV.PS source register. */
12747 gas_assert (mips_opts
.micromips
);
12749 case 'x': /* Ignore register name. */
12750 case 'U': /* Destination register (CLO/CLZ). */
12751 case 'g': /* Coprocessor destination register. */
12752 gas_assert (!mips_opts
.micromips
);
12753 case 'b': /* Base register. */
12754 case 'd': /* Destination register. */
12755 case 's': /* Source register. */
12756 case 't': /* Target register. */
12757 case 'r': /* Both target and source. */
12758 case 'v': /* Both dest and source. */
12759 case 'w': /* Both dest and target. */
12760 case 'E': /* Coprocessor target register. */
12761 case 'K': /* RDHWR destination register. */
12762 case 'z': /* Must be zero register. */
12765 if (*args
== 'E' || *args
== 'K')
12766 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12769 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12770 if (regno
== AT
&& mips_opts
.at
)
12772 if (mips_opts
.at
== ATREG
)
12773 as_warn (_("Used $at without \".set noat\""));
12775 as_warn (_("Used $%u with \".set at=$%u\""),
12776 regno
, mips_opts
.at
);
12786 if (c
== 'r' || c
== 'v' || c
== 'w')
12793 /* 'z' only matches $0. */
12794 if (c
== 'z' && regno
!= 0)
12797 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12799 if (regno
== lastregno
)
12802 = _("Source and destination must be different");
12805 if (regno
== 31 && lastregno
== 0xffffffff)
12808 = _("A destination register must be supplied");
12812 /* Now that we have assembled one operand, we use the args
12813 string to figure out where it goes in the instruction. */
12820 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12824 if (mips_opts
.micromips
)
12825 INSERT_OPERAND (1, RS
, *ip
, regno
);
12827 INSERT_OPERAND (0, RD
, *ip
, regno
);
12832 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12836 gas_assert (!mips_opts
.micromips
);
12837 INSERT_OPERAND (0, RD
, *ip
, regno
);
12838 INSERT_OPERAND (0, RT
, *ip
, regno
);
12844 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12848 gas_assert (mips_opts
.micromips
);
12849 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12853 /* This case exists because on the r3000 trunc
12854 expands into a macro which requires a gp
12855 register. On the r6000 or r4000 it is
12856 assembled into a single instruction which
12857 ignores the register. Thus the insn version
12858 is MIPS_ISA2 and uses 'x', and the macro
12859 version is MIPS_ISA1 and uses 't'. */
12863 /* This case is for the div instruction, which
12864 acts differently if the destination argument
12865 is $0. This only matches $0, and is checked
12866 outside the switch. */
12876 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12880 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12885 case 'O': /* MDMX alignment immediate constant. */
12886 gas_assert (!mips_opts
.micromips
);
12887 my_getExpression (&imm_expr
, s
);
12888 check_absolute_expr (ip
, &imm_expr
);
12889 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12890 as_warn (_("Improper align amount (%ld), using low bits"),
12891 (long) imm_expr
.X_add_number
);
12892 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12893 imm_expr
.X_op
= O_absent
;
12897 case 'Q': /* MDMX vector, element sel, or const. */
12900 /* MDMX Immediate. */
12901 gas_assert (!mips_opts
.micromips
);
12902 my_getExpression (&imm_expr
, s
);
12903 check_absolute_expr (ip
, &imm_expr
);
12904 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12905 as_warn (_("Invalid MDMX Immediate (%ld)"),
12906 (long) imm_expr
.X_add_number
);
12907 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12908 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12909 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12911 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12912 imm_expr
.X_op
= O_absent
;
12916 /* Not MDMX Immediate. Fall through. */
12917 case 'X': /* MDMX destination register. */
12918 case 'Y': /* MDMX source register. */
12919 case 'Z': /* MDMX target register. */
12920 is_mdmx
= !(insn
->membership
& INSN_5400
);
12922 gas_assert (!mips_opts
.micromips
);
12923 case 'D': /* Floating point destination register. */
12924 case 'S': /* Floating point source register. */
12925 case 'T': /* Floating point target register. */
12926 case 'R': /* Floating point source register. */
12930 || ((mips_opts
.ase
& ASE_MDMX
)
12931 && (ip
->insn_mo
->pinfo
& FP_D
)
12932 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12933 | INSN_COPROC_MEMORY_DELAY
12934 | INSN_LOAD_COPROC_DELAY
12935 | INSN_LOAD_MEMORY_DELAY
12936 | INSN_STORE_MEMORY
))))
12937 rtype
|= RTYPE_VEC
;
12939 if (reg_lookup (&s
, rtype
, ®no
))
12941 if ((regno
& 1) != 0
12943 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12944 as_warn (_("Float register should be even, was %d"),
12952 if (c
== 'V' || c
== 'W')
12963 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12969 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12973 /* This is like 'Z', but also needs to fix the MDMX
12974 vector/scalar select bits. Note that the
12975 scalar immediate case is handled above. */
12976 if ((ip
->insn_mo
->membership
& INSN_5400
)
12977 && strcmp (insn
->name
, "rzu.ob") == 0)
12978 as_bad (_("Operand %d of `%s' must be an immediate"),
12979 argnum
, ip
->insn_mo
->name
);
12983 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12984 int max_el
= (is_qh
? 3 : 7);
12986 my_getExpression(&imm_expr
, s
);
12987 check_absolute_expr (ip
, &imm_expr
);
12989 if (imm_expr
.X_add_number
> max_el
)
12990 as_bad (_("Bad element selector %ld"),
12991 (long) imm_expr
.X_add_number
);
12992 imm_expr
.X_add_number
&= max_el
;
12993 ip
->insn_opcode
|= (imm_expr
.X_add_number
12996 imm_expr
.X_op
= O_absent
;
12998 as_warn (_("Expecting ']' found '%s'"), s
);
13004 if ((ip
->insn_mo
->membership
& INSN_5400
)
13005 && (strcmp (insn
->name
, "sll.ob") == 0
13006 || strcmp (insn
->name
, "srl.ob") == 0))
13007 as_bad (_("Operand %d of `%s' must be scalar"),
13008 argnum
, ip
->insn_mo
->name
);
13010 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
13011 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
13014 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
13017 /* Fall through. */
13021 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
13025 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
13035 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
13039 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
13045 my_getExpression (&imm_expr
, s
);
13046 if (imm_expr
.X_op
!= O_big
13047 && imm_expr
.X_op
!= O_constant
)
13048 insn_error
= _("absolute expression required");
13049 if (HAVE_32BIT_GPRS
)
13050 normalize_constant_expr (&imm_expr
);
13055 my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
13056 if (offset_expr
.X_op
== O_register
)
13058 /* Assume that the offset has been elided and that what
13059 we saw was a base register. The match will fail later
13060 if that assumption turns out to be wrong. */
13061 offset_expr
.X_op
= O_constant
;
13062 offset_expr
.X_add_number
= 0;
13066 normalize_address_expr (&offset_expr
);
13080 unsigned char temp
[8];
13082 unsigned int length
;
13087 /* These only appear as the last operand in an
13088 instruction, and every instruction that accepts
13089 them in any variant accepts them in all variants.
13090 This means we don't have to worry about backing out
13091 any changes if the instruction does not match.
13093 The difference between them is the size of the
13094 floating point constant and where it goes. For 'F'
13095 and 'L' the constant is 64 bits; for 'f' and 'l' it
13096 is 32 bits. Where the constant is placed is based
13097 on how the MIPS assembler does things:
13100 f -- immediate value
13103 The .lit4 and .lit8 sections are only used if
13104 permitted by the -G argument.
13106 The code below needs to know whether the target register
13107 is 32 or 64 bits wide. It relies on the fact 'f' and
13108 'F' are used with GPR-based instructions and 'l' and
13109 'L' are used with FPR-based instructions. */
13111 f64
= *args
== 'F' || *args
== 'L';
13112 using_gprs
= *args
== 'F' || *args
== 'f';
13114 save_in
= input_line_pointer
;
13115 input_line_pointer
= s
;
13116 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
13118 s
= input_line_pointer
;
13119 input_line_pointer
= save_in
;
13120 if (err
!= NULL
&& *err
!= '\0')
13122 as_bad (_("Bad floating point constant: %s"), err
);
13123 memset (temp
, '\0', sizeof temp
);
13124 length
= f64
? 8 : 4;
13127 gas_assert (length
== (unsigned) (f64
? 8 : 4));
13131 && (g_switch_value
< 4
13132 || (temp
[0] == 0 && temp
[1] == 0)
13133 || (temp
[2] == 0 && temp
[3] == 0))))
13135 imm_expr
.X_op
= O_constant
;
13136 if (!target_big_endian
)
13137 imm_expr
.X_add_number
= bfd_getl32 (temp
);
13139 imm_expr
.X_add_number
= bfd_getb32 (temp
);
13141 else if (length
> 4
13142 && !mips_disable_float_construction
13143 /* Constants can only be constructed in GPRs and
13144 copied to FPRs if the GPRs are at least as wide
13145 as the FPRs. Force the constant into memory if
13146 we are using 64-bit FPRs but the GPRs are only
13149 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
13150 && ((temp
[0] == 0 && temp
[1] == 0)
13151 || (temp
[2] == 0 && temp
[3] == 0))
13152 && ((temp
[4] == 0 && temp
[5] == 0)
13153 || (temp
[6] == 0 && temp
[7] == 0)))
13155 /* The value is simple enough to load with a couple of
13156 instructions. If using 32-bit registers, set
13157 imm_expr to the high order 32 bits and offset_expr to
13158 the low order 32 bits. Otherwise, set imm_expr to
13159 the entire 64 bit constant. */
13160 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
13162 imm_expr
.X_op
= O_constant
;
13163 offset_expr
.X_op
= O_constant
;
13164 if (!target_big_endian
)
13166 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
13167 offset_expr
.X_add_number
= bfd_getl32 (temp
);
13171 imm_expr
.X_add_number
= bfd_getb32 (temp
);
13172 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
13174 if (offset_expr
.X_add_number
== 0)
13175 offset_expr
.X_op
= O_absent
;
13179 imm_expr
.X_op
= O_constant
;
13180 if (!target_big_endian
)
13181 imm_expr
.X_add_number
= bfd_getl64 (temp
);
13183 imm_expr
.X_add_number
= bfd_getb64 (temp
);
13188 const char *newname
;
13191 /* Switch to the right section. */
13193 subseg
= now_subseg
;
13196 default: /* unused default case avoids warnings. */
13198 newname
= RDATA_SECTION_NAME
;
13199 if (g_switch_value
>= 8)
13203 newname
= RDATA_SECTION_NAME
;
13206 gas_assert (g_switch_value
>= 4);
13210 new_seg
= subseg_new (newname
, (subsegT
) 0);
13211 bfd_set_section_flags (stdoutput
, new_seg
,
13216 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
13217 if (strncmp (TARGET_OS
, "elf", 3) != 0)
13218 record_alignment (new_seg
, 4);
13220 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
13221 if (seg
== now_seg
)
13222 as_bad (_("Can't use floating point insn in this section"));
13224 /* Set the argument to the current address in the
13226 offset_expr
.X_op
= O_symbol
;
13227 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
13228 offset_expr
.X_add_number
= 0;
13230 /* Put the floating point number into the section. */
13231 p
= frag_more ((int) length
);
13232 memcpy (p
, temp
, length
);
13234 /* Switch back to the original section. */
13235 subseg_set (seg
, subseg
);
13240 case 'i': /* 16-bit unsigned immediate. */
13241 case 'j': /* 16-bit signed immediate. */
13242 *offset_reloc
= BFD_RELOC_LO16
;
13243 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0)
13246 offsetT minval
, maxval
;
13248 more
= (insn
+ 1 < past
13249 && strcmp (insn
->name
, insn
[1].name
) == 0);
13251 /* For compatibility with older assemblers, we accept
13252 0x8000-0xffff as signed 16-bit numbers when only
13253 signed numbers are allowed. */
13255 minval
= 0, maxval
= 0xffff;
13257 minval
= -0x8000, maxval
= 0x7fff;
13259 minval
= -0x8000, maxval
= 0xffff;
13261 if (offset_expr
.X_op
!= O_constant
13262 || offset_expr
.X_add_number
< minval
13263 || offset_expr
.X_add_number
> maxval
)
13267 if (offset_expr
.X_op
== O_constant
13268 || offset_expr
.X_op
== O_big
)
13269 as_bad (_("Expression out of range"));
13275 case 'o': /* 16-bit offset. */
13276 offset_reloc
[0] = BFD_RELOC_LO16
;
13277 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13278 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13280 /* Check whether there is only a single bracketed expression
13281 left. If so, it must be the base register and the
13282 constant must be zero. */
13283 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13285 offset_expr
.X_op
= O_constant
;
13286 offset_expr
.X_add_number
= 0;
13290 /* If this value won't fit into a 16 bit offset, then go
13291 find a macro that will generate the 32 bit offset
13293 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
13294 && (offset_expr
.X_op
!= O_constant
13295 || offset_expr
.X_add_number
>= 0x8000
13296 || offset_expr
.X_add_number
< -0x8000))
13302 case 'p': /* PC-relative offset. */
13303 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
13304 my_getExpression (&offset_expr
, s
);
13308 case 'u': /* Upper 16 bits. */
13309 *offset_reloc
= BFD_RELOC_LO16
;
13310 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
13311 && offset_expr
.X_op
== O_constant
13312 && (offset_expr
.X_add_number
< 0
13313 || offset_expr
.X_add_number
>= 0x10000))
13314 as_bad (_("lui expression (%lu) not in range 0..65535"),
13315 (unsigned long) offset_expr
.X_add_number
);
13319 case 'a': /* 26-bit address. */
13321 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
13322 my_getExpression (&offset_expr
, s
);
13326 case 'N': /* 3-bit branch condition code. */
13327 case 'M': /* 3-bit compare condition code. */
13329 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
13330 rtype
|= RTYPE_FCC
;
13331 if (!reg_lookup (&s
, rtype
, ®no
))
13333 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
13334 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
13335 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
13336 && (regno
& 1) != 0)
13337 as_warn (_("Condition code register should be even for %s, "
13340 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
13341 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
13342 && (regno
& 3) != 0)
13343 as_warn (_("Condition code register should be 0 or 4 for %s, "
13347 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
13349 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
13353 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
13364 while (ISDIGIT (*s
));
13367 c
= 8; /* Invalid sel value. */
13370 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13371 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
13375 gas_assert (!mips_opts
.micromips
);
13376 /* Must be at least one digit. */
13377 my_getExpression (&imm_expr
, s
);
13378 check_absolute_expr (ip
, &imm_expr
);
13380 if ((unsigned long) imm_expr
.X_add_number
13381 > (unsigned long) OP_MASK_VECBYTE
)
13383 as_bad (_("bad byte vector index (%ld)"),
13384 (long) imm_expr
.X_add_number
);
13385 imm_expr
.X_add_number
= 0;
13388 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
13389 imm_expr
.X_op
= O_absent
;
13394 gas_assert (!mips_opts
.micromips
);
13395 my_getExpression (&imm_expr
, s
);
13396 check_absolute_expr (ip
, &imm_expr
);
13398 if ((unsigned long) imm_expr
.X_add_number
13399 > (unsigned long) OP_MASK_VECALIGN
)
13401 as_bad (_("bad byte vector index (%ld)"),
13402 (long) imm_expr
.X_add_number
);
13403 imm_expr
.X_add_number
= 0;
13406 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
13407 imm_expr
.X_op
= O_absent
;
13411 case 'm': /* Opcode extension character. */
13412 gas_assert (mips_opts
.micromips
);
13417 if (strncmp (s
, "$pc", 3) == 0)
13444 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
13445 if (regno
== AT
&& mips_opts
.at
)
13447 if (mips_opts
.at
== ATREG
)
13448 as_warn (_("Used $at without \".set noat\""));
13450 as_warn (_("Used $%u with \".set at=$%u\""),
13451 regno
, mips_opts
.at
);
13457 gas_assert (args
[1] == ',');
13463 gas_assert (args
[1] == ',');
13465 continue; /* Nothing to do. */
13471 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
13473 if (regno
== lastregno
)
13476 = _("Source and destination must be different");
13479 if (regno
== 31 && lastregno
== 0xffffffff)
13482 = _("A destination register must be supplied");
13493 gas_assert (args
[1] == ',');
13500 gas_assert (args
[1] == ',');
13503 continue; /* Nothing to do. */
13507 /* Make sure regno is the same as lastregno. */
13508 if (c
== 't' && regno
!= lastregno
)
13511 /* Make sure regno is the same as destregno. */
13512 if (c
== 'x' && regno
!= destregno
)
13515 /* We need to save regno, before regno maps to the
13516 microMIPS register encoding. */
13526 regno
= ILLEGAL_REG
;
13530 regno
= mips32_to_micromips_reg_b_map
[regno
];
13534 regno
= mips32_to_micromips_reg_c_map
[regno
];
13538 regno
= mips32_to_micromips_reg_d_map
[regno
];
13542 regno
= mips32_to_micromips_reg_e_map
[regno
];
13546 regno
= mips32_to_micromips_reg_f_map
[regno
];
13550 regno
= mips32_to_micromips_reg_g_map
[regno
];
13554 s
+= strspn (s
, " \t");
13557 regno
= ILLEGAL_REG
;
13561 s
+= strspn (s
, " \t");
13562 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no2
);
13565 regno
= ILLEGAL_REG
;
13568 if (regno2
== AT
&& mips_opts
.at
)
13570 if (mips_opts
.at
== ATREG
)
13571 as_warn (_("Used $at without \".set noat\""));
13573 as_warn (_("Used $%u with \".set at=$%u\""),
13574 regno2
, mips_opts
.at
);
13576 regno
= (mips_lookup_reg_pair
13578 micromips_to_32_reg_h_map1
,
13579 micromips_to_32_reg_h_map2
, 8));
13583 regno
= mips32_to_micromips_reg_l_map
[regno
];
13587 regno
= mips32_to_micromips_reg_m_map
[regno
];
13591 regno
= mips32_to_micromips_reg_n_map
[regno
];
13595 regno
= mips32_to_micromips_reg_q_map
[regno
];
13600 regno
= ILLEGAL_REG
;
13605 regno
= ILLEGAL_REG
;
13610 regno
= ILLEGAL_REG
;
13613 case 'j': /* Do nothing. */
13623 if (regno
== ILLEGAL_REG
)
13629 INSERT_OPERAND (1, MB
, *ip
, regno
);
13633 INSERT_OPERAND (1, MC
, *ip
, regno
);
13637 INSERT_OPERAND (1, MD
, *ip
, regno
);
13641 INSERT_OPERAND (1, ME
, *ip
, regno
);
13645 INSERT_OPERAND (1, MF
, *ip
, regno
);
13649 INSERT_OPERAND (1, MG
, *ip
, regno
);
13653 INSERT_OPERAND (1, MH
, *ip
, regno
);
13657 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13661 INSERT_OPERAND (1, ML
, *ip
, regno
);
13665 INSERT_OPERAND (1, MM
, *ip
, regno
);
13669 INSERT_OPERAND (1, MN
, *ip
, regno
);
13673 INSERT_OPERAND (1, MP
, *ip
, regno
);
13677 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13680 case 'a': /* Do nothing. */
13681 case 's': /* Do nothing. */
13682 case 't': /* Do nothing. */
13683 case 'x': /* Do nothing. */
13684 case 'y': /* Do nothing. */
13685 case 'z': /* Do nothing. */
13695 bfd_reloc_code_real_type r
[3];
13699 /* Check whether there is only a single bracketed
13700 expression left. If so, it must be the base register
13701 and the constant must be zero. */
13702 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13704 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13708 if (my_getSmallExpression (&ep
, r
, s
) > 0
13709 || !expr_const_in_range (&ep
, -64, 64, 2))
13712 imm
= ep
.X_add_number
>> 2;
13713 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13720 bfd_reloc_code_real_type r
[3];
13724 if (my_getSmallExpression (&ep
, r
, s
) > 0
13725 || ep
.X_op
!= O_constant
)
13728 for (imm
= 0; imm
< 8; imm
++)
13729 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13734 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13741 bfd_reloc_code_real_type r
[3];
13745 if (my_getSmallExpression (&ep
, r
, s
) > 0
13746 || ep
.X_op
!= O_constant
)
13749 for (imm
= 0; imm
< 16; imm
++)
13750 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13755 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13760 case 'D': /* pc relative offset */
13761 case 'E': /* pc relative offset */
13762 my_getExpression (&offset_expr
, s
);
13763 if (offset_expr
.X_op
== O_register
)
13766 if (!forced_insn_length
)
13767 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13769 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13771 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13777 bfd_reloc_code_real_type r
[3];
13781 if (my_getSmallExpression (&ep
, r
, s
) > 0
13782 || !expr_const_in_range (&ep
, 0, 16, 0))
13785 imm
= ep
.X_add_number
;
13786 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13793 bfd_reloc_code_real_type r
[3];
13797 /* Check whether there is only a single bracketed
13798 expression left. If so, it must be the base register
13799 and the constant must be zero. */
13800 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13802 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13806 if (my_getSmallExpression (&ep
, r
, s
) > 0
13807 || !expr_const_in_range (&ep
, -1, 15, 0))
13810 imm
= ep
.X_add_number
& 15;
13811 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13818 bfd_reloc_code_real_type r
[3];
13822 /* Check whether there is only a single bracketed
13823 expression left. If so, it must be the base register
13824 and the constant must be zero. */
13825 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13827 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13831 if (my_getSmallExpression (&ep
, r
, s
) > 0
13832 || !expr_const_in_range (&ep
, 0, 16, 1))
13835 imm
= ep
.X_add_number
>> 1;
13836 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13843 bfd_reloc_code_real_type r
[3];
13847 if (my_getSmallExpression (&ep
, r
, s
) > 0
13848 || !expr_const_in_range (&ep
, -1, 127, 0))
13851 imm
= ep
.X_add_number
& 127;
13852 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13859 bfd_reloc_code_real_type r
[3];
13863 /* Check whether there is only a single bracketed
13864 expression left. If so, it must be the base register
13865 and the constant must be zero. */
13866 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13868 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13872 if (my_getSmallExpression (&ep
, r
, s
) > 0
13873 || !expr_const_in_range (&ep
, 0, 16, 2))
13876 imm
= ep
.X_add_number
>> 2;
13877 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13884 bfd_reloc_code_real_type r
[3];
13888 /* Check whether there is only a single bracketed
13889 expression left. If so, it must be the base register
13890 and the constant must be zero. */
13891 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13893 INSERT_OPERAND (1, IMML
, *ip
, 0);
13897 if (my_getSmallExpression (&ep
, r
, s
) > 0
13898 || !expr_const_in_range (&ep
, 0, 16, 0))
13901 imm
= ep
.X_add_number
;
13902 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13909 bfd_reloc_code_real_type r
[3];
13913 if (my_getSmallExpression (&ep
, r
, s
) > 0
13914 || !expr_const_in_range (&ep
, 1, 9, 0))
13917 imm
= ep
.X_add_number
& 7;
13918 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13923 case 'N': /* Register list for lwm and swm. */
13925 /* A comma-separated list of registers and/or
13926 dash-separated contiguous ranges including
13927 both ra and a set of one or more registers
13928 starting at s0 up to s3 which have to be
13935 and any permutations of these. */
13936 unsigned int reglist
;
13939 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13942 if ((reglist
& 0xfff1ffff) != 0x80010000)
13945 reglist
= (reglist
>> 17) & 7;
13947 if ((reglist
& -reglist
) != reglist
)
13950 imm
= ffs (reglist
) - 1;
13951 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13955 case 'O': /* sdbbp 4-bit code. */
13957 bfd_reloc_code_real_type r
[3];
13961 if (my_getSmallExpression (&ep
, r
, s
) > 0
13962 || !expr_const_in_range (&ep
, 0, 16, 0))
13965 imm
= ep
.X_add_number
;
13966 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13973 bfd_reloc_code_real_type r
[3];
13977 if (my_getSmallExpression (&ep
, r
, s
) > 0
13978 || !expr_const_in_range (&ep
, 0, 32, 2))
13981 imm
= ep
.X_add_number
>> 2;
13982 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13989 bfd_reloc_code_real_type r
[3];
13993 if (my_getSmallExpression (&ep
, r
, s
) > 0
13994 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13997 imm
= ep
.X_add_number
>> 2;
13998 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
14005 bfd_reloc_code_real_type r
[3];
14009 /* Check whether there is only a single bracketed
14010 expression left. If so, it must be the base register
14011 and the constant must be zero. */
14012 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
14014 INSERT_OPERAND (1, IMMU
, *ip
, 0);
14018 if (my_getSmallExpression (&ep
, r
, s
) > 0
14019 || !expr_const_in_range (&ep
, 0, 32, 2))
14022 imm
= ep
.X_add_number
>> 2;
14023 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
14030 bfd_reloc_code_real_type r
[3];
14034 if (my_getSmallExpression (&ep
, r
, s
) > 0
14035 || !expr_const_in_range (&ep
, 0, 64, 2))
14038 imm
= ep
.X_add_number
>> 2;
14039 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
14046 bfd_reloc_code_real_type r
[3];
14050 if (my_getSmallExpression (&ep
, r
, s
) > 0
14051 || !expr_const_in_range (&ep
, -8, 8, 0))
14054 imm
= ep
.X_add_number
;
14055 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
14062 bfd_reloc_code_real_type r
[3];
14066 if (my_getSmallExpression (&ep
, r
, s
) > 0
14067 || expr_const_in_range (&ep
, -2, 2, 2)
14068 || !expr_const_in_range (&ep
, -258, 258, 2))
14071 imm
= ep
.X_add_number
>> 2;
14072 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
14073 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
14080 bfd_reloc_code_real_type r
[3];
14083 if (my_getSmallExpression (&ep
, r
, s
) > 0
14084 || !expr_const_in_range (&ep
, 0, 1, 0))
14091 as_bad (_("Internal error: bad microMIPS opcode "
14092 "(unknown extension operand type `m%c'): %s %s"),
14093 *args
, insn
->name
, insn
->args
);
14094 /* Further processing is fruitless. */
14099 case 'n': /* Register list for 32-bit lwm and swm. */
14100 gas_assert (mips_opts
.micromips
);
14102 /* A comma-separated list of registers and/or
14103 dash-separated contiguous ranges including
14104 at least one of ra and a set of one or more
14105 registers starting at s0 up to s7 and then
14106 s8 which have to be consecutive, e.g.:
14114 and any permutations of these. */
14115 unsigned int reglist
;
14119 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
14122 if ((reglist
& 0x3f00ffff) != 0)
14125 ra
= (reglist
>> 27) & 0x10;
14126 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
14128 if ((reglist
& -reglist
) != reglist
)
14131 imm
= (ffs (reglist
) - 1) | ra
;
14132 INSERT_OPERAND (1, RT
, *ip
, imm
);
14133 imm_expr
.X_op
= O_absent
;
14137 case '|': /* 4-bit trap code. */
14138 gas_assert (mips_opts
.micromips
);
14139 my_getExpression (&imm_expr
, s
);
14140 check_absolute_expr (ip
, &imm_expr
);
14141 if ((unsigned long) imm_expr
.X_add_number
14142 > MICROMIPSOP_MASK_TRAP
)
14143 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
14144 (unsigned long) imm_expr
.X_add_number
,
14145 ip
->insn_mo
->name
);
14146 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
14147 imm_expr
.X_op
= O_absent
;
14152 as_bad (_("Bad char = '%c'\n"), *args
);
14157 /* Args don't match. */
14159 insn_error
= _("Illegal operands");
14160 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
14165 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
14167 gas_assert (firstinsn
);
14168 need_delay_slot_ok
= FALSE
;
14177 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
14179 /* As for mips_ip, but used when assembling MIPS16 code.
14180 Also set forced_insn_length to the resulting instruction size in
14181 bytes if the user explicitly requested a small or extended instruction. */
14184 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
14188 struct mips_opcode
*insn
;
14190 unsigned int regno
;
14191 unsigned int lastregno
= 0;
14197 forced_insn_length
= 0;
14199 for (s
= str
; ISLOWER (*s
); ++s
)
14211 if (s
[1] == 't' && s
[2] == ' ')
14214 forced_insn_length
= 2;
14218 else if (s
[1] == 'e' && s
[2] == ' ')
14221 forced_insn_length
= 4;
14225 /* Fall through. */
14227 insn_error
= _("unknown opcode");
14231 if (mips_opts
.noautoextend
&& !forced_insn_length
)
14232 forced_insn_length
= 2;
14234 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
14236 insn_error
= _("unrecognized opcode");
14246 gas_assert (strcmp (insn
->name
, str
) == 0);
14248 ok
= is_opcode_valid_16 (insn
);
14251 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
14252 && strcmp (insn
->name
, insn
[1].name
) == 0)
14261 static char buf
[100];
14263 _("Opcode not supported on this processor: %s (%s)"),
14264 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
14265 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14272 create_insn (ip
, insn
);
14273 imm_expr
.X_op
= O_absent
;
14274 imm2_expr
.X_op
= O_absent
;
14275 offset_expr
.X_op
= O_absent
;
14276 offset_reloc
[0] = BFD_RELOC_UNUSED
;
14277 offset_reloc
[1] = BFD_RELOC_UNUSED
;
14278 offset_reloc
[2] = BFD_RELOC_UNUSED
;
14280 for (args
= insn
->args
; 1; ++args
)
14287 /* In this switch statement we call break if we did not find
14288 a match, continue if we did find a match, or return if we
14299 /* Stuff the immediate value in now, if we can. */
14300 if (insn
->pinfo
== INSN_MACRO
)
14302 gas_assert (relax_char
== 0);
14303 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
14305 else if (relax_char
14306 && offset_expr
.X_op
== O_constant
14307 && calculate_reloc (*offset_reloc
,
14308 offset_expr
.X_add_number
,
14311 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
14312 forced_insn_length
, &ip
->insn_opcode
);
14313 offset_expr
.X_op
= O_absent
;
14314 *offset_reloc
= BFD_RELOC_UNUSED
;
14316 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
14318 if (forced_insn_length
== 2)
14319 as_bad (_("invalid unextended operand value"));
14320 forced_insn_length
= 4;
14321 ip
->insn_opcode
|= MIPS16_EXTEND
;
14323 else if (relax_char
)
14324 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
14337 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14340 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14356 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14358 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14362 /* Fall through. */
14373 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
14375 if (c
== 'v' || c
== 'w')
14378 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14380 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14391 if (c
== 'v' || c
== 'w')
14393 regno
= mips16_to_32_reg_map
[lastregno
];
14407 regno
= mips32_to_16_reg_map
[regno
];
14412 regno
= ILLEGAL_REG
;
14417 regno
= ILLEGAL_REG
;
14422 regno
= ILLEGAL_REG
;
14427 if (regno
== AT
&& mips_opts
.at
)
14429 if (mips_opts
.at
== ATREG
)
14430 as_warn (_("used $at without \".set noat\""));
14432 as_warn (_("used $%u with \".set at=$%u\""),
14433 regno
, mips_opts
.at
);
14441 if (regno
== ILLEGAL_REG
)
14448 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
14452 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
14455 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
14458 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
14464 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
14467 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
14468 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
14478 if (strncmp (s
, "$pc", 3) == 0)
14495 i
= my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
14502 *offset_reloc
= BFD_RELOC_UNUSED
;
14503 /* Fall through. */
14510 my_getExpression (&offset_expr
, s
);
14511 if (offset_expr
.X_op
== O_register
)
14513 /* What we thought was an expression turned out to
14516 if (s
[0] == '(' && args
[1] == '(')
14518 /* It looks like the expression was omitted
14519 before a register indirection, which means
14520 that the expression is implicitly zero. We
14521 still set up offset_expr, so that we handle
14522 explicit extensions correctly. */
14523 offset_expr
.X_op
= O_constant
;
14524 offset_expr
.X_add_number
= 0;
14532 /* We need to relax this instruction. */
14542 /* We use offset_reloc rather than imm_reloc for the PC
14543 relative operands. This lets macros with both
14544 immediate and address operands work correctly. */
14545 my_getExpression (&offset_expr
, s
);
14547 if (offset_expr
.X_op
== O_register
)
14550 /* We need to relax this instruction. */
14555 case '6': /* break code */
14556 my_getExpression (&imm_expr
, s
);
14557 check_absolute_expr (ip
, &imm_expr
);
14558 if ((unsigned long) imm_expr
.X_add_number
> 63)
14559 as_warn (_("Invalid value for `%s' (%lu)"),
14561 (unsigned long) imm_expr
.X_add_number
);
14562 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
14563 imm_expr
.X_op
= O_absent
;
14568 my_getExpression (&imm_expr
, s
);
14569 if (imm_expr
.X_op
!= O_big
14570 && imm_expr
.X_op
!= O_constant
)
14571 insn_error
= _("absolute expression required");
14572 if (HAVE_32BIT_GPRS
)
14573 normalize_constant_expr (&imm_expr
);
14577 case 'a': /* 26 bit address */
14579 my_getExpression (&offset_expr
, s
);
14581 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
14582 ip
->insn_opcode
<<= 16;
14585 case 'l': /* register list for entry macro */
14586 case 'L': /* register list for exit macro */
14596 unsigned int freg
, reg1
, reg2
;
14598 while (*s
== ' ' || *s
== ',')
14600 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14602 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
14606 as_bad (_("can't parse register list"));
14616 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14617 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14619 as_bad (_("invalid register list"));
14623 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14625 mask
&= ~ (7 << 3);
14628 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14630 mask
&= ~ (7 << 3);
14633 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14634 mask
|= (reg2
- 3) << 3;
14635 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14636 mask
|= (reg2
- 15) << 1;
14637 else if (reg1
== RA
&& reg2
== RA
)
14641 as_bad (_("invalid register list"));
14645 /* The mask is filled in in the opcode table for the
14646 benefit of the disassembler. We remove it before
14647 applying the actual mask. */
14648 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14649 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14653 case 'm': /* Register list for save insn. */
14654 case 'M': /* Register list for restore insn. */
14656 int opcode
= ip
->insn_opcode
;
14657 int framesz
= 0, seen_framesz
= 0;
14658 int nargs
= 0, statics
= 0, sregs
= 0;
14662 unsigned int reg1
, reg2
;
14664 SKIP_SPACE_TABS (s
);
14667 SKIP_SPACE_TABS (s
);
14669 my_getExpression (&imm_expr
, s
);
14670 if (imm_expr
.X_op
== O_constant
)
14672 /* Handle the frame size. */
14675 as_bad (_("more than one frame size in list"));
14679 framesz
= imm_expr
.X_add_number
;
14680 imm_expr
.X_op
= O_absent
;
14685 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14687 as_bad (_("can't parse register list"));
14699 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14702 as_bad (_("can't parse register list"));
14707 while (reg1
<= reg2
)
14709 if (reg1
>= 4 && reg1
<= 7)
14713 nargs
|= 1 << (reg1
- 4);
14715 /* statics $a0-$a3 */
14716 statics
|= 1 << (reg1
- 4);
14718 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14721 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14723 else if (reg1
== 31)
14725 /* Add $ra to insn. */
14730 as_bad (_("unexpected register in list"));
14738 /* Encode args/statics combination. */
14739 if (nargs
& statics
)
14740 as_bad (_("arg/static registers overlap"));
14741 else if (nargs
== 0xf)
14742 /* All $a0-$a3 are args. */
14743 opcode
|= MIPS16_ALL_ARGS
<< 16;
14744 else if (statics
== 0xf)
14745 /* All $a0-$a3 are statics. */
14746 opcode
|= MIPS16_ALL_STATICS
<< 16;
14749 int narg
= 0, nstat
= 0;
14751 /* Count arg registers. */
14752 while (nargs
& 0x1)
14758 as_bad (_("invalid arg register list"));
14760 /* Count static registers. */
14761 while (statics
& 0x8)
14763 statics
= (statics
<< 1) & 0xf;
14767 as_bad (_("invalid static register list"));
14769 /* Encode args/statics. */
14770 opcode
|= ((narg
<< 2) | nstat
) << 16;
14773 /* Encode $s0/$s1. */
14774 if (sregs
& (1 << 0)) /* $s0 */
14776 if (sregs
& (1 << 1)) /* $s1 */
14782 /* Count regs $s2-$s8. */
14790 as_bad (_("invalid static register list"));
14791 /* Encode $s2-$s8. */
14792 opcode
|= nsreg
<< 24;
14795 /* Encode frame size. */
14797 as_bad (_("missing frame size"));
14798 else if ((framesz
& 7) != 0 || framesz
< 0
14799 || framesz
> 0xff * 8)
14800 as_bad (_("invalid frame size"));
14801 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14804 opcode
|= (((framesz
& 0xf0) << 16)
14805 | (framesz
& 0x0f));
14808 /* Finally build the instruction. */
14809 if ((opcode
>> 16) != 0 || framesz
== 0)
14810 opcode
|= MIPS16_EXTEND
;
14811 ip
->insn_opcode
= opcode
;
14815 case 'e': /* extend code */
14816 my_getExpression (&imm_expr
, s
);
14817 check_absolute_expr (ip
, &imm_expr
);
14818 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14820 as_warn (_("Invalid value for `%s' (%lu)"),
14822 (unsigned long) imm_expr
.X_add_number
);
14823 imm_expr
.X_add_number
&= 0x7ff;
14825 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14826 imm_expr
.X_op
= O_absent
;
14836 /* Args don't match. */
14837 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14838 strcmp (insn
->name
, insn
[1].name
) == 0)
14845 insn_error
= _("illegal operands");
14851 /* This structure holds information we know about a mips16 immediate
14854 struct mips16_immed_operand
14856 /* The type code used in the argument string in the opcode table. */
14858 /* The number of bits in the short form of the opcode. */
14860 /* The number of bits in the extended form of the opcode. */
14862 /* The amount by which the short form is shifted when it is used;
14863 for example, the sw instruction has a shift count of 2. */
14865 /* The amount by which the short form is shifted when it is stored
14866 into the instruction code. */
14868 /* Non-zero if the short form is unsigned. */
14870 /* Non-zero if the extended form is unsigned. */
14872 /* Non-zero if the value is PC relative. */
14876 /* The mips16 immediate operand types. */
14878 static const struct mips16_immed_operand mips16_immed_operands
[] =
14880 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14881 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14882 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14883 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14884 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14885 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14886 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14887 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14888 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14889 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14890 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14891 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14892 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14893 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14894 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14895 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14896 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14897 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14898 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14899 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14900 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14903 #define MIPS16_NUM_IMMED \
14904 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14906 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14907 NBITS is the number of significant bits in VAL. */
14909 static unsigned long
14910 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14915 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14918 else if (nbits
== 15)
14920 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14925 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14928 return (extval
<< 16) | val
;
14931 /* Install immediate value VAL into MIPS16 instruction *INSN,
14932 extending it if necessary. The instruction in *INSN may
14933 already be extended.
14935 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14936 if none. In the former case, VAL is a 16-bit number with no
14937 defined signedness.
14939 TYPE is the type of the immediate field. USER_INSN_LENGTH
14940 is the length that the user requested, or 0 if none. */
14943 mips16_immed (char *file
, unsigned int line
, int type
,
14944 bfd_reloc_code_real_type reloc
, offsetT val
,
14945 unsigned int user_insn_length
, unsigned long *insn
)
14947 const struct mips16_immed_operand
*op
;
14948 int mintiny
, maxtiny
;
14950 op
= mips16_immed_operands
;
14951 while (op
->type
!= type
)
14954 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14959 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14962 maxtiny
= 1 << op
->nbits
;
14967 maxtiny
= (1 << op
->nbits
) - 1;
14969 if (reloc
!= BFD_RELOC_UNUSED
)
14974 mintiny
= - (1 << (op
->nbits
- 1));
14975 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14976 if (reloc
!= BFD_RELOC_UNUSED
)
14977 val
= SEXT_16BIT (val
);
14980 /* Branch offsets have an implicit 0 in the lowest bit. */
14981 if (type
== 'p' || type
== 'q')
14984 if ((val
& ((1 << op
->shift
) - 1)) != 0
14985 || val
< (mintiny
<< op
->shift
)
14986 || val
> (maxtiny
<< op
->shift
))
14988 /* We need an extended instruction. */
14989 if (user_insn_length
== 2)
14990 as_bad_where (file
, line
, _("invalid unextended operand value"));
14992 *insn
|= MIPS16_EXTEND
;
14994 else if (user_insn_length
== 4)
14996 /* The operand doesn't force an unextended instruction to be extended.
14997 Warn if the user wanted an extended instruction anyway. */
14998 *insn
|= MIPS16_EXTEND
;
14999 as_warn_where (file
, line
,
15000 _("extended operand requested but not required"));
15003 if (mips16_opcode_length (*insn
) == 2)
15007 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
15008 insnval
<<= op
->op_shift
;
15013 long minext
, maxext
;
15015 if (reloc
== BFD_RELOC_UNUSED
)
15020 maxext
= (1 << op
->extbits
) - 1;
15024 minext
= - (1 << (op
->extbits
- 1));
15025 maxext
= (1 << (op
->extbits
- 1)) - 1;
15027 if (val
< minext
|| val
> maxext
)
15028 as_bad_where (file
, line
,
15029 _("operand value out of range for instruction"));
15032 *insn
|= mips16_immed_extend (val
, op
->extbits
);
15036 struct percent_op_match
15039 bfd_reloc_code_real_type reloc
;
15042 static const struct percent_op_match mips_percent_op
[] =
15044 {"%lo", BFD_RELOC_LO16
},
15045 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
15046 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
15047 {"%call16", BFD_RELOC_MIPS_CALL16
},
15048 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
15049 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
15050 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
15051 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
15052 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
15053 {"%got", BFD_RELOC_MIPS_GOT16
},
15054 {"%gp_rel", BFD_RELOC_GPREL16
},
15055 {"%half", BFD_RELOC_16
},
15056 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
15057 {"%higher", BFD_RELOC_MIPS_HIGHER
},
15058 {"%neg", BFD_RELOC_MIPS_SUB
},
15059 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
15060 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
15061 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
15062 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
15063 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
15064 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
15065 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
15066 {"%hi", BFD_RELOC_HI16_S
}
15069 static const struct percent_op_match mips16_percent_op
[] =
15071 {"%lo", BFD_RELOC_MIPS16_LO16
},
15072 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
15073 {"%got", BFD_RELOC_MIPS16_GOT16
},
15074 {"%call16", BFD_RELOC_MIPS16_CALL16
},
15075 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
15076 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
15077 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
15078 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
15079 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
15080 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
15081 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
15082 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
15086 /* Return true if *STR points to a relocation operator. When returning true,
15087 move *STR over the operator and store its relocation code in *RELOC.
15088 Leave both *STR and *RELOC alone when returning false. */
15091 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
15093 const struct percent_op_match
*percent_op
;
15096 if (mips_opts
.mips16
)
15098 percent_op
= mips16_percent_op
;
15099 limit
= ARRAY_SIZE (mips16_percent_op
);
15103 percent_op
= mips_percent_op
;
15104 limit
= ARRAY_SIZE (mips_percent_op
);
15107 for (i
= 0; i
< limit
; i
++)
15108 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
15110 int len
= strlen (percent_op
[i
].str
);
15112 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
15115 *str
+= strlen (percent_op
[i
].str
);
15116 *reloc
= percent_op
[i
].reloc
;
15118 /* Check whether the output BFD supports this relocation.
15119 If not, issue an error and fall back on something safe. */
15120 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
15122 as_bad (_("relocation %s isn't supported by the current ABI"),
15123 percent_op
[i
].str
);
15124 *reloc
= BFD_RELOC_UNUSED
;
15132 /* Parse string STR as a 16-bit relocatable operand. Store the
15133 expression in *EP and the relocations in the array starting
15134 at RELOC. Return the number of relocation operators used.
15136 On exit, EXPR_END points to the first character after the expression. */
15139 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
15142 bfd_reloc_code_real_type reversed_reloc
[3];
15143 size_t reloc_index
, i
;
15144 int crux_depth
, str_depth
;
15147 /* Search for the start of the main expression, recoding relocations
15148 in REVERSED_RELOC. End the loop with CRUX pointing to the start
15149 of the main expression and with CRUX_DEPTH containing the number
15150 of open brackets at that point. */
15157 crux_depth
= str_depth
;
15159 /* Skip over whitespace and brackets, keeping count of the number
15161 while (*str
== ' ' || *str
== '\t' || *str
== '(')
15166 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
15167 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
15169 my_getExpression (ep
, crux
);
15172 /* Match every open bracket. */
15173 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
15177 if (crux_depth
> 0)
15178 as_bad (_("unclosed '('"));
15182 if (reloc_index
!= 0)
15184 prev_reloc_op_frag
= frag_now
;
15185 for (i
= 0; i
< reloc_index
; i
++)
15186 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
15189 return reloc_index
;
15193 my_getExpression (expressionS
*ep
, char *str
)
15197 save_in
= input_line_pointer
;
15198 input_line_pointer
= str
;
15200 expr_end
= input_line_pointer
;
15201 input_line_pointer
= save_in
;
15205 md_atof (int type
, char *litP
, int *sizeP
)
15207 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
15211 md_number_to_chars (char *buf
, valueT val
, int n
)
15213 if (target_big_endian
)
15214 number_to_chars_bigendian (buf
, val
, n
);
15216 number_to_chars_littleendian (buf
, val
, n
);
15219 static int support_64bit_objects(void)
15221 const char **list
, **l
;
15224 list
= bfd_target_list ();
15225 for (l
= list
; *l
!= NULL
; l
++)
15226 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
15227 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
15229 yes
= (*l
!= NULL
);
15234 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
15235 NEW_VALUE. Warn if another value was already specified. Note:
15236 we have to defer parsing the -march and -mtune arguments in order
15237 to handle 'from-abi' correctly, since the ABI might be specified
15238 in a later argument. */
15241 mips_set_option_string (const char **string_ptr
, const char *new_value
)
15243 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
15244 as_warn (_("A different %s was already specified, is now %s"),
15245 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
15248 *string_ptr
= new_value
;
15252 md_parse_option (int c
, char *arg
)
15256 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
15257 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
15259 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
15260 c
== mips_ases
[i
].option_on
);
15266 case OPTION_CONSTRUCT_FLOATS
:
15267 mips_disable_float_construction
= 0;
15270 case OPTION_NO_CONSTRUCT_FLOATS
:
15271 mips_disable_float_construction
= 1;
15283 target_big_endian
= 1;
15287 target_big_endian
= 0;
15293 else if (arg
[0] == '0')
15295 else if (arg
[0] == '1')
15305 mips_debug
= atoi (arg
);
15309 file_mips_isa
= ISA_MIPS1
;
15313 file_mips_isa
= ISA_MIPS2
;
15317 file_mips_isa
= ISA_MIPS3
;
15321 file_mips_isa
= ISA_MIPS4
;
15325 file_mips_isa
= ISA_MIPS5
;
15328 case OPTION_MIPS32
:
15329 file_mips_isa
= ISA_MIPS32
;
15332 case OPTION_MIPS32R2
:
15333 file_mips_isa
= ISA_MIPS32R2
;
15336 case OPTION_MIPS64R2
:
15337 file_mips_isa
= ISA_MIPS64R2
;
15340 case OPTION_MIPS64
:
15341 file_mips_isa
= ISA_MIPS64
;
15345 mips_set_option_string (&mips_tune_string
, arg
);
15349 mips_set_option_string (&mips_arch_string
, arg
);
15353 mips_set_option_string (&mips_arch_string
, "4650");
15354 mips_set_option_string (&mips_tune_string
, "4650");
15357 case OPTION_NO_M4650
:
15361 mips_set_option_string (&mips_arch_string
, "4010");
15362 mips_set_option_string (&mips_tune_string
, "4010");
15365 case OPTION_NO_M4010
:
15369 mips_set_option_string (&mips_arch_string
, "4100");
15370 mips_set_option_string (&mips_tune_string
, "4100");
15373 case OPTION_NO_M4100
:
15377 mips_set_option_string (&mips_arch_string
, "3900");
15378 mips_set_option_string (&mips_tune_string
, "3900");
15381 case OPTION_NO_M3900
:
15384 case OPTION_MICROMIPS
:
15385 if (mips_opts
.mips16
== 1)
15387 as_bad (_("-mmicromips cannot be used with -mips16"));
15390 mips_opts
.micromips
= 1;
15391 mips_no_prev_insn ();
15394 case OPTION_NO_MICROMIPS
:
15395 mips_opts
.micromips
= 0;
15396 mips_no_prev_insn ();
15399 case OPTION_MIPS16
:
15400 if (mips_opts
.micromips
== 1)
15402 as_bad (_("-mips16 cannot be used with -micromips"));
15405 mips_opts
.mips16
= 1;
15406 mips_no_prev_insn ();
15409 case OPTION_NO_MIPS16
:
15410 mips_opts
.mips16
= 0;
15411 mips_no_prev_insn ();
15414 case OPTION_FIX_24K
:
15418 case OPTION_NO_FIX_24K
:
15422 case OPTION_FIX_LOONGSON2F_JUMP
:
15423 mips_fix_loongson2f_jump
= TRUE
;
15426 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15427 mips_fix_loongson2f_jump
= FALSE
;
15430 case OPTION_FIX_LOONGSON2F_NOP
:
15431 mips_fix_loongson2f_nop
= TRUE
;
15434 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15435 mips_fix_loongson2f_nop
= FALSE
;
15438 case OPTION_FIX_VR4120
:
15439 mips_fix_vr4120
= 1;
15442 case OPTION_NO_FIX_VR4120
:
15443 mips_fix_vr4120
= 0;
15446 case OPTION_FIX_VR4130
:
15447 mips_fix_vr4130
= 1;
15450 case OPTION_NO_FIX_VR4130
:
15451 mips_fix_vr4130
= 0;
15454 case OPTION_FIX_CN63XXP1
:
15455 mips_fix_cn63xxp1
= TRUE
;
15458 case OPTION_NO_FIX_CN63XXP1
:
15459 mips_fix_cn63xxp1
= FALSE
;
15462 case OPTION_RELAX_BRANCH
:
15463 mips_relax_branch
= 1;
15466 case OPTION_NO_RELAX_BRANCH
:
15467 mips_relax_branch
= 0;
15470 case OPTION_INSN32
:
15471 mips_opts
.insn32
= TRUE
;
15474 case OPTION_NO_INSN32
:
15475 mips_opts
.insn32
= FALSE
;
15478 case OPTION_MSHARED
:
15479 mips_in_shared
= TRUE
;
15482 case OPTION_MNO_SHARED
:
15483 mips_in_shared
= FALSE
;
15486 case OPTION_MSYM32
:
15487 mips_opts
.sym32
= TRUE
;
15490 case OPTION_MNO_SYM32
:
15491 mips_opts
.sym32
= FALSE
;
15494 /* When generating ELF code, we permit -KPIC and -call_shared to
15495 select SVR4_PIC, and -non_shared to select no PIC. This is
15496 intended to be compatible with Irix 5. */
15497 case OPTION_CALL_SHARED
:
15498 mips_pic
= SVR4_PIC
;
15499 mips_abicalls
= TRUE
;
15502 case OPTION_CALL_NONPIC
:
15504 mips_abicalls
= TRUE
;
15507 case OPTION_NON_SHARED
:
15509 mips_abicalls
= FALSE
;
15512 /* The -xgot option tells the assembler to use 32 bit offsets
15513 when accessing the got in SVR4_PIC mode. It is for Irix
15520 g_switch_value
= atoi (arg
);
15524 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15527 mips_abi
= O32_ABI
;
15531 mips_abi
= N32_ABI
;
15535 mips_abi
= N64_ABI
;
15536 if (!support_64bit_objects())
15537 as_fatal (_("No compiled in support for 64 bit object file format"));
15541 file_mips_gp32
= 1;
15545 file_mips_gp32
= 0;
15549 file_mips_fp32
= 1;
15553 file_mips_fp32
= 0;
15556 case OPTION_SINGLE_FLOAT
:
15557 file_mips_single_float
= 1;
15560 case OPTION_DOUBLE_FLOAT
:
15561 file_mips_single_float
= 0;
15564 case OPTION_SOFT_FLOAT
:
15565 file_mips_soft_float
= 1;
15568 case OPTION_HARD_FLOAT
:
15569 file_mips_soft_float
= 0;
15573 if (strcmp (arg
, "32") == 0)
15574 mips_abi
= O32_ABI
;
15575 else if (strcmp (arg
, "o64") == 0)
15576 mips_abi
= O64_ABI
;
15577 else if (strcmp (arg
, "n32") == 0)
15578 mips_abi
= N32_ABI
;
15579 else if (strcmp (arg
, "64") == 0)
15581 mips_abi
= N64_ABI
;
15582 if (! support_64bit_objects())
15583 as_fatal (_("No compiled in support for 64 bit object file "
15586 else if (strcmp (arg
, "eabi") == 0)
15587 mips_abi
= EABI_ABI
;
15590 as_fatal (_("invalid abi -mabi=%s"), arg
);
15595 case OPTION_M7000_HILO_FIX
:
15596 mips_7000_hilo_fix
= TRUE
;
15599 case OPTION_MNO_7000_HILO_FIX
:
15600 mips_7000_hilo_fix
= FALSE
;
15603 case OPTION_MDEBUG
:
15604 mips_flag_mdebug
= TRUE
;
15607 case OPTION_NO_MDEBUG
:
15608 mips_flag_mdebug
= FALSE
;
15612 mips_flag_pdr
= TRUE
;
15615 case OPTION_NO_PDR
:
15616 mips_flag_pdr
= FALSE
;
15619 case OPTION_MVXWORKS_PIC
:
15620 mips_pic
= VXWORKS_PIC
;
15624 if (strcmp (arg
, "2008") == 0)
15625 mips_flag_nan2008
= TRUE
;
15626 else if (strcmp (arg
, "legacy") == 0)
15627 mips_flag_nan2008
= FALSE
;
15630 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
15639 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15644 /* Set up globals to generate code for the ISA or processor
15645 described by INFO. */
15648 mips_set_architecture (const struct mips_cpu_info
*info
)
15652 file_mips_arch
= info
->cpu
;
15653 mips_opts
.arch
= info
->cpu
;
15654 mips_opts
.isa
= info
->isa
;
15659 /* Likewise for tuning. */
15662 mips_set_tune (const struct mips_cpu_info
*info
)
15665 mips_tune
= info
->cpu
;
15670 mips_after_parse_args (void)
15672 const struct mips_cpu_info
*arch_info
= 0;
15673 const struct mips_cpu_info
*tune_info
= 0;
15675 /* GP relative stuff not working for PE */
15676 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15678 if (g_switch_seen
&& g_switch_value
!= 0)
15679 as_bad (_("-G not supported in this configuration."));
15680 g_switch_value
= 0;
15683 if (mips_abi
== NO_ABI
)
15684 mips_abi
= MIPS_DEFAULT_ABI
;
15686 /* The following code determines the architecture and register size.
15687 Similar code was added to GCC 3.3 (see override_options() in
15688 config/mips/mips.c). The GAS and GCC code should be kept in sync
15689 as much as possible. */
15691 if (mips_arch_string
!= 0)
15692 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15694 if (file_mips_isa
!= ISA_UNKNOWN
)
15696 /* Handle -mipsN. At this point, file_mips_isa contains the
15697 ISA level specified by -mipsN, while arch_info->isa contains
15698 the -march selection (if any). */
15699 if (arch_info
!= 0)
15701 /* -march takes precedence over -mipsN, since it is more descriptive.
15702 There's no harm in specifying both as long as the ISA levels
15704 if (file_mips_isa
!= arch_info
->isa
)
15705 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15706 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15707 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15710 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15713 if (arch_info
== 0)
15715 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15716 gas_assert (arch_info
);
15719 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15720 as_bad (_("-march=%s is not compatible with the selected ABI"),
15723 mips_set_architecture (arch_info
);
15725 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15726 if (mips_tune_string
!= 0)
15727 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15729 if (tune_info
== 0)
15730 mips_set_tune (arch_info
);
15732 mips_set_tune (tune_info
);
15734 if (file_mips_gp32
>= 0)
15736 /* The user specified the size of the integer registers. Make sure
15737 it agrees with the ABI and ISA. */
15738 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15739 as_bad (_("-mgp64 used with a 32-bit processor"));
15740 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15741 as_bad (_("-mgp32 used with a 64-bit ABI"));
15742 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15743 as_bad (_("-mgp64 used with a 32-bit ABI"));
15747 /* Infer the integer register size from the ABI and processor.
15748 Restrict ourselves to 32-bit registers if that's all the
15749 processor has, or if the ABI cannot handle 64-bit registers. */
15750 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15751 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15754 switch (file_mips_fp32
)
15758 /* No user specified float register size.
15759 ??? GAS treats single-float processors as though they had 64-bit
15760 float registers (although it complains when double-precision
15761 instructions are used). As things stand, saying they have 32-bit
15762 registers would lead to spurious "register must be even" messages.
15763 So here we assume float registers are never smaller than the
15765 if (file_mips_gp32
== 0)
15766 /* 64-bit integer registers implies 64-bit float registers. */
15767 file_mips_fp32
= 0;
15768 else if ((mips_opts
.ase
& FP64_ASES
)
15769 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15770 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15771 file_mips_fp32
= 0;
15773 /* 32-bit float registers. */
15774 file_mips_fp32
= 1;
15777 /* The user specified the size of the float registers. Check if it
15778 agrees with the ABI and ISA. */
15780 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15781 as_bad (_("-mfp64 used with a 32-bit fpu"));
15782 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15783 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15784 as_warn (_("-mfp64 used with a 32-bit ABI"));
15787 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15788 as_warn (_("-mfp32 used with a 64-bit ABI"));
15792 /* End of GCC-shared inference code. */
15794 /* This flag is set when we have a 64-bit capable CPU but use only
15795 32-bit wide registers. Note that EABI does not use it. */
15796 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15797 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15798 || mips_abi
== O32_ABI
))
15799 mips_32bitmode
= 1;
15801 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15802 as_bad (_("trap exception not supported at ISA 1"));
15804 /* If the selected architecture includes support for ASEs, enable
15805 generation of code for them. */
15806 if (mips_opts
.mips16
== -1)
15807 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15808 if (mips_opts
.micromips
== -1)
15809 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15811 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15812 ASEs from being selected implicitly. */
15813 if (file_mips_fp32
== 1)
15814 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
15816 /* If the user didn't explicitly select or deselect a particular ASE,
15817 use the default setting for the CPU. */
15818 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
15820 file_mips_isa
= mips_opts
.isa
;
15821 file_ase
= mips_opts
.ase
;
15822 mips_opts
.gp32
= file_mips_gp32
;
15823 mips_opts
.fp32
= file_mips_fp32
;
15824 mips_opts
.soft_float
= file_mips_soft_float
;
15825 mips_opts
.single_float
= file_mips_single_float
;
15827 mips_check_isa_supports_ases ();
15829 if (mips_flag_mdebug
< 0)
15830 mips_flag_mdebug
= 0;
15834 mips_init_after_args (void)
15836 /* initialize opcodes */
15837 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15838 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15842 md_pcrel_from (fixS
*fixP
)
15844 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15845 switch (fixP
->fx_r_type
)
15847 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15848 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15849 /* Return the address of the delay slot. */
15852 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15853 case BFD_RELOC_MICROMIPS_JMP
:
15854 case BFD_RELOC_16_PCREL_S2
:
15855 case BFD_RELOC_MIPS_JMP
:
15856 /* Return the address of the delay slot. */
15859 case BFD_RELOC_32_PCREL
:
15863 /* We have no relocation type for PC relative MIPS16 instructions. */
15864 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15866 _("PC relative MIPS16 instruction references a different section"));
15871 /* This is called before the symbol table is processed. In order to
15872 work with gcc when using mips-tfile, we must keep all local labels.
15873 However, in other cases, we want to discard them. If we were
15874 called with -g, but we didn't see any debugging information, it may
15875 mean that gcc is smuggling debugging information through to
15876 mips-tfile, in which case we must generate all local labels. */
15879 mips_frob_file_before_adjust (void)
15881 #ifndef NO_ECOFF_DEBUGGING
15882 if (ECOFF_DEBUGGING
15884 && ! ecoff_debugging_seen
)
15885 flag_keep_locals
= 1;
15889 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15890 the corresponding LO16 reloc. This is called before md_apply_fix and
15891 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15892 relocation operators.
15894 For our purposes, a %lo() expression matches a %got() or %hi()
15897 (a) it refers to the same symbol; and
15898 (b) the offset applied in the %lo() expression is no lower than
15899 the offset applied in the %got() or %hi().
15901 (b) allows us to cope with code like:
15904 lh $4,%lo(foo+2)($4)
15906 ...which is legal on RELA targets, and has a well-defined behaviour
15907 if the user knows that adding 2 to "foo" will not induce a carry to
15910 When several %lo()s match a particular %got() or %hi(), we use the
15911 following rules to distinguish them:
15913 (1) %lo()s with smaller offsets are a better match than %lo()s with
15916 (2) %lo()s with no matching %got() or %hi() are better than those
15917 that already have a matching %got() or %hi().
15919 (3) later %lo()s are better than earlier %lo()s.
15921 These rules are applied in order.
15923 (1) means, among other things, that %lo()s with identical offsets are
15924 chosen if they exist.
15926 (2) means that we won't associate several high-part relocations with
15927 the same low-part relocation unless there's no alternative. Having
15928 several high parts for the same low part is a GNU extension; this rule
15929 allows careful users to avoid it.
15931 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15932 with the last high-part relocation being at the front of the list.
15933 It therefore makes sense to choose the last matching low-part
15934 relocation, all other things being equal. It's also easier
15935 to code that way. */
15938 mips_frob_file (void)
15940 struct mips_hi_fixup
*l
;
15941 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15943 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15945 segment_info_type
*seginfo
;
15946 bfd_boolean matched_lo_p
;
15947 fixS
**hi_pos
, **lo_pos
, **pos
;
15949 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15951 /* If a GOT16 relocation turns out to be against a global symbol,
15952 there isn't supposed to be a matching LO. Ignore %gots against
15953 constants; we'll report an error for those later. */
15954 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15955 && !(l
->fixp
->fx_addsy
15956 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15959 /* Check quickly whether the next fixup happens to be a matching %lo. */
15960 if (fixup_has_matching_lo_p (l
->fixp
))
15963 seginfo
= seg_info (l
->seg
);
15965 /* Set HI_POS to the position of this relocation in the chain.
15966 Set LO_POS to the position of the chosen low-part relocation.
15967 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15968 relocation that matches an immediately-preceding high-part
15972 matched_lo_p
= FALSE
;
15973 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15975 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15977 if (*pos
== l
->fixp
)
15980 if ((*pos
)->fx_r_type
== looking_for_rtype
15981 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15982 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15984 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15986 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15989 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15990 && fixup_has_matching_lo_p (*pos
));
15993 /* If we found a match, remove the high-part relocation from its
15994 current position and insert it before the low-part relocation.
15995 Make the offsets match so that fixup_has_matching_lo_p()
15998 We don't warn about unmatched high-part relocations since some
15999 versions of gcc have been known to emit dead "lui ...%hi(...)"
16001 if (lo_pos
!= NULL
)
16003 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
16004 if (l
->fixp
->fx_next
!= *lo_pos
)
16006 *hi_pos
= l
->fixp
->fx_next
;
16007 l
->fixp
->fx_next
= *lo_pos
;
16015 mips_force_relocation (fixS
*fixp
)
16017 if (generic_force_reloc (fixp
))
16020 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
16021 so that the linker relaxation can update targets. */
16022 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16023 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16024 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
16030 /* Read the instruction associated with RELOC from BUF. */
16032 static unsigned int
16033 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
16035 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
16036 return read_compressed_insn (buf
, 4);
16038 return read_insn (buf
);
16041 /* Write instruction INSN to BUF, given that it has been relocated
16045 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
16046 unsigned long insn
)
16048 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
16049 write_compressed_insn (buf
, insn
, 4);
16051 write_insn (buf
, insn
);
16054 /* Apply a fixup to the object file. */
16057 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
16060 unsigned long insn
;
16061 reloc_howto_type
*howto
;
16063 /* We ignore generic BFD relocations we don't know about. */
16064 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
16068 gas_assert (fixP
->fx_size
== 2
16069 || fixP
->fx_size
== 4
16070 || fixP
->fx_r_type
== BFD_RELOC_16
16071 || fixP
->fx_r_type
== BFD_RELOC_64
16072 || fixP
->fx_r_type
== BFD_RELOC_CTOR
16073 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
16074 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
16075 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16076 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
16077 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
16079 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
16081 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16082 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16083 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16084 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16085 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
16087 /* Don't treat parts of a composite relocation as done. There are two
16090 (1) The second and third parts will be against 0 (RSS_UNDEF) but
16091 should nevertheless be emitted if the first part is.
16093 (2) In normal usage, composite relocations are never assembly-time
16094 constants. The easiest way of dealing with the pathological
16095 exceptions is to generate a relocation against STN_UNDEF and
16096 leave everything up to the linker. */
16097 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
16100 switch (fixP
->fx_r_type
)
16102 case BFD_RELOC_MIPS_TLS_GD
:
16103 case BFD_RELOC_MIPS_TLS_LDM
:
16104 case BFD_RELOC_MIPS_TLS_DTPREL32
:
16105 case BFD_RELOC_MIPS_TLS_DTPREL64
:
16106 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
16107 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
16108 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
16109 case BFD_RELOC_MIPS_TLS_TPREL32
:
16110 case BFD_RELOC_MIPS_TLS_TPREL64
:
16111 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
16112 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
16113 case BFD_RELOC_MICROMIPS_TLS_GD
:
16114 case BFD_RELOC_MICROMIPS_TLS_LDM
:
16115 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
16116 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
16117 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
16118 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
16119 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
16120 case BFD_RELOC_MIPS16_TLS_GD
:
16121 case BFD_RELOC_MIPS16_TLS_LDM
:
16122 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
16123 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
16124 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
16125 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
16126 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
16127 if (!fixP
->fx_addsy
)
16129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16130 _("TLS relocation against a constant"));
16133 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
16136 case BFD_RELOC_MIPS_JMP
:
16137 case BFD_RELOC_MIPS_SHIFT5
:
16138 case BFD_RELOC_MIPS_SHIFT6
:
16139 case BFD_RELOC_MIPS_GOT_DISP
:
16140 case BFD_RELOC_MIPS_GOT_PAGE
:
16141 case BFD_RELOC_MIPS_GOT_OFST
:
16142 case BFD_RELOC_MIPS_SUB
:
16143 case BFD_RELOC_MIPS_INSERT_A
:
16144 case BFD_RELOC_MIPS_INSERT_B
:
16145 case BFD_RELOC_MIPS_DELETE
:
16146 case BFD_RELOC_MIPS_HIGHEST
:
16147 case BFD_RELOC_MIPS_HIGHER
:
16148 case BFD_RELOC_MIPS_SCN_DISP
:
16149 case BFD_RELOC_MIPS_REL16
:
16150 case BFD_RELOC_MIPS_RELGOT
:
16151 case BFD_RELOC_MIPS_JALR
:
16152 case BFD_RELOC_HI16
:
16153 case BFD_RELOC_HI16_S
:
16154 case BFD_RELOC_LO16
:
16155 case BFD_RELOC_GPREL16
:
16156 case BFD_RELOC_MIPS_LITERAL
:
16157 case BFD_RELOC_MIPS_CALL16
:
16158 case BFD_RELOC_MIPS_GOT16
:
16159 case BFD_RELOC_GPREL32
:
16160 case BFD_RELOC_MIPS_GOT_HI16
:
16161 case BFD_RELOC_MIPS_GOT_LO16
:
16162 case BFD_RELOC_MIPS_CALL_HI16
:
16163 case BFD_RELOC_MIPS_CALL_LO16
:
16164 case BFD_RELOC_MIPS16_GPREL
:
16165 case BFD_RELOC_MIPS16_GOT16
:
16166 case BFD_RELOC_MIPS16_CALL16
:
16167 case BFD_RELOC_MIPS16_HI16
:
16168 case BFD_RELOC_MIPS16_HI16_S
:
16169 case BFD_RELOC_MIPS16_LO16
:
16170 case BFD_RELOC_MIPS16_JMP
:
16171 case BFD_RELOC_MICROMIPS_JMP
:
16172 case BFD_RELOC_MICROMIPS_GOT_DISP
:
16173 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
16174 case BFD_RELOC_MICROMIPS_GOT_OFST
:
16175 case BFD_RELOC_MICROMIPS_SUB
:
16176 case BFD_RELOC_MICROMIPS_HIGHEST
:
16177 case BFD_RELOC_MICROMIPS_HIGHER
:
16178 case BFD_RELOC_MICROMIPS_SCN_DISP
:
16179 case BFD_RELOC_MICROMIPS_JALR
:
16180 case BFD_RELOC_MICROMIPS_HI16
:
16181 case BFD_RELOC_MICROMIPS_HI16_S
:
16182 case BFD_RELOC_MICROMIPS_LO16
:
16183 case BFD_RELOC_MICROMIPS_GPREL16
:
16184 case BFD_RELOC_MICROMIPS_LITERAL
:
16185 case BFD_RELOC_MICROMIPS_CALL16
:
16186 case BFD_RELOC_MICROMIPS_GOT16
:
16187 case BFD_RELOC_MICROMIPS_GOT_HI16
:
16188 case BFD_RELOC_MICROMIPS_GOT_LO16
:
16189 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16190 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16191 case BFD_RELOC_MIPS_EH
:
16196 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16198 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16199 if (mips16_reloc_p (fixP
->fx_r_type
))
16200 insn
|= mips16_immed_extend (value
, 16);
16202 insn
|= (value
& 0xffff);
16203 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16207 _("Unsupported constant in relocation"));
16212 /* This is handled like BFD_RELOC_32, but we output a sign
16213 extended value if we are only 32 bits. */
16216 if (8 <= sizeof (valueT
))
16217 md_number_to_chars (buf
, *valP
, 8);
16222 if ((*valP
& 0x80000000) != 0)
16226 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16227 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16232 case BFD_RELOC_RVA
:
16234 case BFD_RELOC_32_PCREL
:
16236 /* If we are deleting this reloc entry, we must fill in the
16237 value now. This can happen if we have a .word which is not
16238 resolved when it appears but is later defined. */
16240 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16243 case BFD_RELOC_16_PCREL_S2
:
16244 if ((*valP
& 0x3) != 0)
16245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16246 _("Branch to misaligned address (%lx)"), (long) *valP
);
16248 /* We need to save the bits in the instruction since fixup_segment()
16249 might be deleting the relocation entry (i.e., a branch within
16250 the current segment). */
16251 if (! fixP
->fx_done
)
16254 /* Update old instruction data. */
16255 insn
= read_insn (buf
);
16257 if (*valP
+ 0x20000 <= 0x3ffff)
16259 insn
|= (*valP
>> 2) & 0xffff;
16260 write_insn (buf
, insn
);
16262 else if (mips_pic
== NO_PIC
16264 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16265 && (fixP
->fx_frag
->fr_address
16266 < text_section
->vma
+ bfd_get_section_size (text_section
))
16267 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16268 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16269 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16271 /* The branch offset is too large. If this is an
16272 unconditional branch, and we are not generating PIC code,
16273 we can convert it to an absolute jump instruction. */
16274 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16275 insn
= 0x0c000000; /* jal */
16277 insn
= 0x08000000; /* j */
16278 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16280 fixP
->fx_addsy
= section_symbol (text_section
);
16281 *valP
+= md_pcrel_from (fixP
);
16282 write_insn (buf
, insn
);
16286 /* If we got here, we have branch-relaxation disabled,
16287 and there's nothing we can do to fix this instruction
16288 without turning it into a longer sequence. */
16289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16290 _("Branch out of range"));
16294 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16295 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16296 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16297 /* We adjust the offset back to even. */
16298 if ((*valP
& 0x1) != 0)
16301 if (! fixP
->fx_done
)
16304 /* Should never visit here, because we keep the relocation. */
16308 case BFD_RELOC_VTABLE_INHERIT
:
16311 && !S_IS_DEFINED (fixP
->fx_addsy
)
16312 && !S_IS_WEAK (fixP
->fx_addsy
))
16313 S_SET_WEAK (fixP
->fx_addsy
);
16316 case BFD_RELOC_VTABLE_ENTRY
:
16324 /* Remember value for tc_gen_reloc. */
16325 fixP
->fx_addnumber
= *valP
;
16335 name
= input_line_pointer
;
16336 c
= get_symbol_end ();
16337 p
= (symbolS
*) symbol_find_or_make (name
);
16338 *input_line_pointer
= c
;
16342 /* Align the current frag to a given power of two. If a particular
16343 fill byte should be used, FILL points to an integer that contains
16344 that byte, otherwise FILL is null.
16346 This function used to have the comment:
16348 The MIPS assembler also automatically adjusts any preceding label.
16350 The implementation therefore applied the adjustment to a maximum of
16351 one label. However, other label adjustments are applied to batches
16352 of labels, and adjusting just one caused problems when new labels
16353 were added for the sake of debugging or unwind information.
16354 We therefore adjust all preceding labels (given as LABELS) instead. */
16357 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16359 mips_emit_delays ();
16360 mips_record_compressed_mode ();
16361 if (fill
== NULL
&& subseg_text_p (now_seg
))
16362 frag_align_code (to
, 0);
16364 frag_align (to
, fill
? *fill
: 0, 0);
16365 record_alignment (now_seg
, to
);
16366 mips_move_labels (labels
, FALSE
);
16369 /* Align to a given power of two. .align 0 turns off the automatic
16370 alignment used by the data creating pseudo-ops. */
16373 s_align (int x ATTRIBUTE_UNUSED
)
16375 int temp
, fill_value
, *fill_ptr
;
16376 long max_alignment
= 28;
16378 /* o Note that the assembler pulls down any immediately preceding label
16379 to the aligned address.
16380 o It's not documented but auto alignment is reinstated by
16381 a .align pseudo instruction.
16382 o Note also that after auto alignment is turned off the mips assembler
16383 issues an error on attempt to assemble an improperly aligned data item.
16386 temp
= get_absolute_expression ();
16387 if (temp
> max_alignment
)
16388 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16391 as_warn (_("Alignment negative: 0 assumed."));
16394 if (*input_line_pointer
== ',')
16396 ++input_line_pointer
;
16397 fill_value
= get_absolute_expression ();
16398 fill_ptr
= &fill_value
;
16404 segment_info_type
*si
= seg_info (now_seg
);
16405 struct insn_label_list
*l
= si
->label_list
;
16406 /* Auto alignment should be switched on by next section change. */
16408 mips_align (temp
, fill_ptr
, l
);
16415 demand_empty_rest_of_line ();
16419 s_change_sec (int sec
)
16423 /* The ELF backend needs to know that we are changing sections, so
16424 that .previous works correctly. We could do something like check
16425 for an obj_section_change_hook macro, but that might be confusing
16426 as it would not be appropriate to use it in the section changing
16427 functions in read.c, since obj-elf.c intercepts those. FIXME:
16428 This should be cleaner, somehow. */
16429 obj_elf_section_change_hook ();
16431 mips_emit_delays ();
16442 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16443 demand_empty_rest_of_line ();
16447 seg
= subseg_new (RDATA_SECTION_NAME
,
16448 (subsegT
) get_absolute_expression ());
16449 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16450 | SEC_READONLY
| SEC_RELOC
16452 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16453 record_alignment (seg
, 4);
16454 demand_empty_rest_of_line ();
16458 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16459 bfd_set_section_flags (stdoutput
, seg
,
16460 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16461 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16462 record_alignment (seg
, 4);
16463 demand_empty_rest_of_line ();
16467 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16468 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16469 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16470 record_alignment (seg
, 4);
16471 demand_empty_rest_of_line ();
16479 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16481 char *section_name
;
16486 int section_entry_size
;
16487 int section_alignment
;
16489 section_name
= input_line_pointer
;
16490 c
= get_symbol_end ();
16492 next_c
= *(input_line_pointer
+ 1);
16494 /* Do we have .section Name<,"flags">? */
16495 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16497 /* just after name is now '\0'. */
16498 *input_line_pointer
= c
;
16499 input_line_pointer
= section_name
;
16500 obj_elf_section (ignore
);
16503 input_line_pointer
++;
16505 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16507 section_type
= get_absolute_expression ();
16510 if (*input_line_pointer
++ == ',')
16511 section_flag
= get_absolute_expression ();
16514 if (*input_line_pointer
++ == ',')
16515 section_entry_size
= get_absolute_expression ();
16517 section_entry_size
= 0;
16518 if (*input_line_pointer
++ == ',')
16519 section_alignment
= get_absolute_expression ();
16521 section_alignment
= 0;
16522 /* FIXME: really ignore? */
16523 (void) section_alignment
;
16525 section_name
= xstrdup (section_name
);
16527 /* When using the generic form of .section (as implemented by obj-elf.c),
16528 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16529 traditionally had to fall back on the more common @progbits instead.
16531 There's nothing really harmful in this, since bfd will correct
16532 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16533 means that, for backwards compatibility, the special_section entries
16534 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16536 Even so, we shouldn't force users of the MIPS .section syntax to
16537 incorrectly label the sections as SHT_PROGBITS. The best compromise
16538 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16539 generic type-checking code. */
16540 if (section_type
== SHT_MIPS_DWARF
)
16541 section_type
= SHT_PROGBITS
;
16543 obj_elf_change_section (section_name
, section_type
, section_flag
,
16544 section_entry_size
, 0, 0, 0);
16546 if (now_seg
->name
!= section_name
)
16547 free (section_name
);
16551 mips_enable_auto_align (void)
16557 s_cons (int log_size
)
16559 segment_info_type
*si
= seg_info (now_seg
);
16560 struct insn_label_list
*l
= si
->label_list
;
16562 mips_emit_delays ();
16563 if (log_size
> 0 && auto_align
)
16564 mips_align (log_size
, 0, l
);
16565 cons (1 << log_size
);
16566 mips_clear_insn_labels ();
16570 s_float_cons (int type
)
16572 segment_info_type
*si
= seg_info (now_seg
);
16573 struct insn_label_list
*l
= si
->label_list
;
16575 mips_emit_delays ();
16580 mips_align (3, 0, l
);
16582 mips_align (2, 0, l
);
16586 mips_clear_insn_labels ();
16589 /* Handle .globl. We need to override it because on Irix 5 you are
16592 where foo is an undefined symbol, to mean that foo should be
16593 considered to be the address of a function. */
16596 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16605 name
= input_line_pointer
;
16606 c
= get_symbol_end ();
16607 symbolP
= symbol_find_or_make (name
);
16608 S_SET_EXTERNAL (symbolP
);
16610 *input_line_pointer
= c
;
16611 SKIP_WHITESPACE ();
16613 /* On Irix 5, every global symbol that is not explicitly labelled as
16614 being a function is apparently labelled as being an object. */
16617 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16618 && (*input_line_pointer
!= ','))
16623 secname
= input_line_pointer
;
16624 c
= get_symbol_end ();
16625 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16627 as_bad (_("%s: no such section"), secname
);
16628 *input_line_pointer
= c
;
16630 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16631 flag
= BSF_FUNCTION
;
16634 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16636 c
= *input_line_pointer
;
16639 input_line_pointer
++;
16640 SKIP_WHITESPACE ();
16641 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16647 demand_empty_rest_of_line ();
16651 s_option (int x ATTRIBUTE_UNUSED
)
16656 opt
= input_line_pointer
;
16657 c
= get_symbol_end ();
16661 /* FIXME: What does this mean? */
16663 else if (strncmp (opt
, "pic", 3) == 0)
16667 i
= atoi (opt
+ 3);
16672 mips_pic
= SVR4_PIC
;
16673 mips_abicalls
= TRUE
;
16676 as_bad (_(".option pic%d not supported"), i
);
16678 if (mips_pic
== SVR4_PIC
)
16680 if (g_switch_seen
&& g_switch_value
!= 0)
16681 as_warn (_("-G may not be used with SVR4 PIC code"));
16682 g_switch_value
= 0;
16683 bfd_set_gp_size (stdoutput
, 0);
16687 as_warn (_("Unrecognized option \"%s\""), opt
);
16689 *input_line_pointer
= c
;
16690 demand_empty_rest_of_line ();
16693 /* This structure is used to hold a stack of .set values. */
16695 struct mips_option_stack
16697 struct mips_option_stack
*next
;
16698 struct mips_set_options options
;
16701 static struct mips_option_stack
*mips_opts_stack
;
16703 /* Handle the .set pseudo-op. */
16706 s_mipsset (int x ATTRIBUTE_UNUSED
)
16708 char *name
= input_line_pointer
, ch
;
16709 const struct mips_ase
*ase
;
16711 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16712 ++input_line_pointer
;
16713 ch
= *input_line_pointer
;
16714 *input_line_pointer
= '\0';
16716 if (strcmp (name
, "reorder") == 0)
16718 if (mips_opts
.noreorder
)
16721 else if (strcmp (name
, "noreorder") == 0)
16723 if (!mips_opts
.noreorder
)
16724 start_noreorder ();
16726 else if (strncmp (name
, "at=", 3) == 0)
16728 char *s
= name
+ 3;
16730 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16731 as_bad (_("Unrecognized register name `%s'"), s
);
16733 else if (strcmp (name
, "at") == 0)
16735 mips_opts
.at
= ATREG
;
16737 else if (strcmp (name
, "noat") == 0)
16739 mips_opts
.at
= ZERO
;
16741 else if (strcmp (name
, "macro") == 0)
16743 mips_opts
.warn_about_macros
= 0;
16745 else if (strcmp (name
, "nomacro") == 0)
16747 if (mips_opts
.noreorder
== 0)
16748 as_bad (_("`noreorder' must be set before `nomacro'"));
16749 mips_opts
.warn_about_macros
= 1;
16751 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16753 mips_opts
.nomove
= 0;
16755 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16757 mips_opts
.nomove
= 1;
16759 else if (strcmp (name
, "bopt") == 0)
16761 mips_opts
.nobopt
= 0;
16763 else if (strcmp (name
, "nobopt") == 0)
16765 mips_opts
.nobopt
= 1;
16767 else if (strcmp (name
, "gp=default") == 0)
16768 mips_opts
.gp32
= file_mips_gp32
;
16769 else if (strcmp (name
, "gp=32") == 0)
16770 mips_opts
.gp32
= 1;
16771 else if (strcmp (name
, "gp=64") == 0)
16773 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16774 as_warn (_("%s isa does not support 64-bit registers"),
16775 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16776 mips_opts
.gp32
= 0;
16778 else if (strcmp (name
, "fp=default") == 0)
16779 mips_opts
.fp32
= file_mips_fp32
;
16780 else if (strcmp (name
, "fp=32") == 0)
16781 mips_opts
.fp32
= 1;
16782 else if (strcmp (name
, "fp=64") == 0)
16784 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16785 as_warn (_("%s isa does not support 64-bit floating point registers"),
16786 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16787 mips_opts
.fp32
= 0;
16789 else if (strcmp (name
, "softfloat") == 0)
16790 mips_opts
.soft_float
= 1;
16791 else if (strcmp (name
, "hardfloat") == 0)
16792 mips_opts
.soft_float
= 0;
16793 else if (strcmp (name
, "singlefloat") == 0)
16794 mips_opts
.single_float
= 1;
16795 else if (strcmp (name
, "doublefloat") == 0)
16796 mips_opts
.single_float
= 0;
16797 else if (strcmp (name
, "mips16") == 0
16798 || strcmp (name
, "MIPS-16") == 0)
16800 if (mips_opts
.micromips
== 1)
16801 as_fatal (_("`mips16' cannot be used with `micromips'"));
16802 mips_opts
.mips16
= 1;
16804 else if (strcmp (name
, "nomips16") == 0
16805 || strcmp (name
, "noMIPS-16") == 0)
16806 mips_opts
.mips16
= 0;
16807 else if (strcmp (name
, "micromips") == 0)
16809 if (mips_opts
.mips16
== 1)
16810 as_fatal (_("`micromips' cannot be used with `mips16'"));
16811 mips_opts
.micromips
= 1;
16813 else if (strcmp (name
, "nomicromips") == 0)
16814 mips_opts
.micromips
= 0;
16815 else if (name
[0] == 'n'
16817 && (ase
= mips_lookup_ase (name
+ 2)))
16818 mips_set_ase (ase
, FALSE
);
16819 else if ((ase
= mips_lookup_ase (name
)))
16820 mips_set_ase (ase
, TRUE
);
16821 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16825 /* Permit the user to change the ISA and architecture on the fly.
16826 Needless to say, misuse can cause serious problems. */
16827 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16830 mips_opts
.isa
= file_mips_isa
;
16831 mips_opts
.arch
= file_mips_arch
;
16833 else if (strncmp (name
, "arch=", 5) == 0)
16835 const struct mips_cpu_info
*p
;
16837 p
= mips_parse_cpu("internal use", name
+ 5);
16839 as_bad (_("unknown architecture %s"), name
+ 5);
16842 mips_opts
.arch
= p
->cpu
;
16843 mips_opts
.isa
= p
->isa
;
16846 else if (strncmp (name
, "mips", 4) == 0)
16848 const struct mips_cpu_info
*p
;
16850 p
= mips_parse_cpu("internal use", name
);
16852 as_bad (_("unknown ISA level %s"), name
+ 4);
16855 mips_opts
.arch
= p
->cpu
;
16856 mips_opts
.isa
= p
->isa
;
16860 as_bad (_("unknown ISA or architecture %s"), name
);
16862 switch (mips_opts
.isa
)
16870 mips_opts
.gp32
= 1;
16871 mips_opts
.fp32
= 1;
16878 mips_opts
.gp32
= 0;
16879 if (mips_opts
.arch
== CPU_R5900
)
16881 mips_opts
.fp32
= 1;
16885 mips_opts
.fp32
= 0;
16889 as_bad (_("unknown ISA level %s"), name
+ 4);
16894 mips_opts
.gp32
= file_mips_gp32
;
16895 mips_opts
.fp32
= file_mips_fp32
;
16898 else if (strcmp (name
, "autoextend") == 0)
16899 mips_opts
.noautoextend
= 0;
16900 else if (strcmp (name
, "noautoextend") == 0)
16901 mips_opts
.noautoextend
= 1;
16902 else if (strcmp (name
, "insn32") == 0)
16903 mips_opts
.insn32
= TRUE
;
16904 else if (strcmp (name
, "noinsn32") == 0)
16905 mips_opts
.insn32
= FALSE
;
16906 else if (strcmp (name
, "push") == 0)
16908 struct mips_option_stack
*s
;
16910 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16911 s
->next
= mips_opts_stack
;
16912 s
->options
= mips_opts
;
16913 mips_opts_stack
= s
;
16915 else if (strcmp (name
, "pop") == 0)
16917 struct mips_option_stack
*s
;
16919 s
= mips_opts_stack
;
16921 as_bad (_(".set pop with no .set push"));
16924 /* If we're changing the reorder mode we need to handle
16925 delay slots correctly. */
16926 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16927 start_noreorder ();
16928 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16931 mips_opts
= s
->options
;
16932 mips_opts_stack
= s
->next
;
16936 else if (strcmp (name
, "sym32") == 0)
16937 mips_opts
.sym32
= TRUE
;
16938 else if (strcmp (name
, "nosym32") == 0)
16939 mips_opts
.sym32
= FALSE
;
16940 else if (strchr (name
, ','))
16942 /* Generic ".set" directive; use the generic handler. */
16943 *input_line_pointer
= ch
;
16944 input_line_pointer
= name
;
16950 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16952 mips_check_isa_supports_ases ();
16953 *input_line_pointer
= ch
;
16954 demand_empty_rest_of_line ();
16957 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16958 .option pic2. It means to generate SVR4 PIC calls. */
16961 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16963 mips_pic
= SVR4_PIC
;
16964 mips_abicalls
= TRUE
;
16966 if (g_switch_seen
&& g_switch_value
!= 0)
16967 as_warn (_("-G may not be used with SVR4 PIC code"));
16968 g_switch_value
= 0;
16970 bfd_set_gp_size (stdoutput
, 0);
16971 demand_empty_rest_of_line ();
16974 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16975 PIC code. It sets the $gp register for the function based on the
16976 function address, which is in the register named in the argument.
16977 This uses a relocation against _gp_disp, which is handled specially
16978 by the linker. The result is:
16979 lui $gp,%hi(_gp_disp)
16980 addiu $gp,$gp,%lo(_gp_disp)
16981 addu $gp,$gp,.cpload argument
16982 The .cpload argument is normally $25 == $t9.
16984 The -mno-shared option changes this to:
16985 lui $gp,%hi(__gnu_local_gp)
16986 addiu $gp,$gp,%lo(__gnu_local_gp)
16987 and the argument is ignored. This saves an instruction, but the
16988 resulting code is not position independent; it uses an absolute
16989 address for __gnu_local_gp. Thus code assembled with -mno-shared
16990 can go into an ordinary executable, but not into a shared library. */
16993 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16999 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17000 .cpload is ignored. */
17001 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17007 if (mips_opts
.mips16
)
17009 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
17010 ignore_rest_of_line ();
17014 /* .cpload should be in a .set noreorder section. */
17015 if (mips_opts
.noreorder
== 0)
17016 as_warn (_(".cpload not in noreorder section"));
17018 reg
= tc_get_register (0);
17020 /* If we need to produce a 64-bit address, we are better off using
17021 the default instruction sequence. */
17022 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
17024 ex
.X_op
= O_symbol
;
17025 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
17027 ex
.X_op_symbol
= NULL
;
17028 ex
.X_add_number
= 0;
17030 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17031 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17033 mips_mark_labels ();
17034 mips_assembling_insn
= TRUE
;
17037 macro_build_lui (&ex
, mips_gp_register
);
17038 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17039 mips_gp_register
, BFD_RELOC_LO16
);
17041 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17042 mips_gp_register
, reg
);
17045 mips_assembling_insn
= FALSE
;
17046 demand_empty_rest_of_line ();
17049 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17050 .cpsetup $reg1, offset|$reg2, label
17052 If offset is given, this results in:
17053 sd $gp, offset($sp)
17054 lui $gp, %hi(%neg(%gp_rel(label)))
17055 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17056 daddu $gp, $gp, $reg1
17058 If $reg2 is given, this results in:
17059 daddu $reg2, $gp, $0
17060 lui $gp, %hi(%neg(%gp_rel(label)))
17061 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17062 daddu $gp, $gp, $reg1
17063 $reg1 is normally $25 == $t9.
17065 The -mno-shared option replaces the last three instructions with
17067 addiu $gp,$gp,%lo(_gp) */
17070 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17072 expressionS ex_off
;
17073 expressionS ex_sym
;
17076 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17077 We also need NewABI support. */
17078 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17084 if (mips_opts
.mips16
)
17086 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17087 ignore_rest_of_line ();
17091 reg1
= tc_get_register (0);
17092 SKIP_WHITESPACE ();
17093 if (*input_line_pointer
!= ',')
17095 as_bad (_("missing argument separator ',' for .cpsetup"));
17099 ++input_line_pointer
;
17100 SKIP_WHITESPACE ();
17101 if (*input_line_pointer
== '$')
17103 mips_cpreturn_register
= tc_get_register (0);
17104 mips_cpreturn_offset
= -1;
17108 mips_cpreturn_offset
= get_absolute_expression ();
17109 mips_cpreturn_register
= -1;
17111 SKIP_WHITESPACE ();
17112 if (*input_line_pointer
!= ',')
17114 as_bad (_("missing argument separator ',' for .cpsetup"));
17118 ++input_line_pointer
;
17119 SKIP_WHITESPACE ();
17120 expression (&ex_sym
);
17122 mips_mark_labels ();
17123 mips_assembling_insn
= TRUE
;
17126 if (mips_cpreturn_register
== -1)
17128 ex_off
.X_op
= O_constant
;
17129 ex_off
.X_add_symbol
= NULL
;
17130 ex_off
.X_op_symbol
= NULL
;
17131 ex_off
.X_add_number
= mips_cpreturn_offset
;
17133 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17134 BFD_RELOC_LO16
, SP
);
17137 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
17138 mips_gp_register
, 0);
17140 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17142 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17143 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17146 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17147 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17148 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17151 mips_gp_register
, reg1
);
17157 ex
.X_op
= O_symbol
;
17158 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17159 ex
.X_op_symbol
= NULL
;
17160 ex
.X_add_number
= 0;
17162 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17163 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17165 macro_build_lui (&ex
, mips_gp_register
);
17166 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17167 mips_gp_register
, BFD_RELOC_LO16
);
17172 mips_assembling_insn
= FALSE
;
17173 demand_empty_rest_of_line ();
17177 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17179 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17180 .cplocal is ignored. */
17181 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17187 if (mips_opts
.mips16
)
17189 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17190 ignore_rest_of_line ();
17194 mips_gp_register
= tc_get_register (0);
17195 demand_empty_rest_of_line ();
17198 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17199 offset from $sp. The offset is remembered, and after making a PIC
17200 call $gp is restored from that location. */
17203 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17207 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17208 .cprestore is ignored. */
17209 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17215 if (mips_opts
.mips16
)
17217 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17218 ignore_rest_of_line ();
17222 mips_cprestore_offset
= get_absolute_expression ();
17223 mips_cprestore_valid
= 1;
17225 ex
.X_op
= O_constant
;
17226 ex
.X_add_symbol
= NULL
;
17227 ex
.X_op_symbol
= NULL
;
17228 ex
.X_add_number
= mips_cprestore_offset
;
17230 mips_mark_labels ();
17231 mips_assembling_insn
= TRUE
;
17234 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17235 SP
, HAVE_64BIT_ADDRESSES
);
17238 mips_assembling_insn
= FALSE
;
17239 demand_empty_rest_of_line ();
17242 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17243 was given in the preceding .cpsetup, it results in:
17244 ld $gp, offset($sp)
17246 If a register $reg2 was given there, it results in:
17247 daddu $gp, $reg2, $0 */
17250 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17254 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17255 We also need NewABI support. */
17256 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17262 if (mips_opts
.mips16
)
17264 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17265 ignore_rest_of_line ();
17269 mips_mark_labels ();
17270 mips_assembling_insn
= TRUE
;
17273 if (mips_cpreturn_register
== -1)
17275 ex
.X_op
= O_constant
;
17276 ex
.X_add_symbol
= NULL
;
17277 ex
.X_op_symbol
= NULL
;
17278 ex
.X_add_number
= mips_cpreturn_offset
;
17280 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17283 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
17284 mips_cpreturn_register
, 0);
17287 mips_assembling_insn
= FALSE
;
17288 demand_empty_rest_of_line ();
17291 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17292 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17293 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17294 debug information or MIPS16 TLS. */
17297 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17298 bfd_reloc_code_real_type rtype
)
17305 if (ex
.X_op
!= O_symbol
)
17307 as_bad (_("Unsupported use of %s"), dirstr
);
17308 ignore_rest_of_line ();
17311 p
= frag_more (bytes
);
17312 md_number_to_chars (p
, 0, bytes
);
17313 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17314 demand_empty_rest_of_line ();
17315 mips_clear_insn_labels ();
17318 /* Handle .dtprelword. */
17321 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17323 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17326 /* Handle .dtpreldword. */
17329 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17331 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17334 /* Handle .tprelword. */
17337 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17339 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17342 /* Handle .tpreldword. */
17345 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17347 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17350 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17351 code. It sets the offset to use in gp_rel relocations. */
17354 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17356 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17357 We also need NewABI support. */
17358 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17364 mips_gprel_offset
= get_absolute_expression ();
17366 demand_empty_rest_of_line ();
17369 /* Handle the .gpword pseudo-op. This is used when generating PIC
17370 code. It generates a 32 bit GP relative reloc. */
17373 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17375 segment_info_type
*si
;
17376 struct insn_label_list
*l
;
17380 /* When not generating PIC code, this is treated as .word. */
17381 if (mips_pic
!= SVR4_PIC
)
17387 si
= seg_info (now_seg
);
17388 l
= si
->label_list
;
17389 mips_emit_delays ();
17391 mips_align (2, 0, l
);
17394 mips_clear_insn_labels ();
17396 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17398 as_bad (_("Unsupported use of .gpword"));
17399 ignore_rest_of_line ();
17403 md_number_to_chars (p
, 0, 4);
17404 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17405 BFD_RELOC_GPREL32
);
17407 demand_empty_rest_of_line ();
17411 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17413 segment_info_type
*si
;
17414 struct insn_label_list
*l
;
17418 /* When not generating PIC code, this is treated as .dword. */
17419 if (mips_pic
!= SVR4_PIC
)
17425 si
= seg_info (now_seg
);
17426 l
= si
->label_list
;
17427 mips_emit_delays ();
17429 mips_align (3, 0, l
);
17432 mips_clear_insn_labels ();
17434 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17436 as_bad (_("Unsupported use of .gpdword"));
17437 ignore_rest_of_line ();
17441 md_number_to_chars (p
, 0, 8);
17442 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17443 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17445 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17446 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17447 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17449 demand_empty_rest_of_line ();
17452 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17453 tables. It generates a R_MIPS_EH reloc. */
17456 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17461 mips_emit_delays ();
17464 mips_clear_insn_labels ();
17466 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17468 as_bad (_("Unsupported use of .ehword"));
17469 ignore_rest_of_line ();
17473 md_number_to_chars (p
, 0, 4);
17474 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17475 BFD_RELOC_MIPS_EH
);
17477 demand_empty_rest_of_line ();
17480 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17481 tables in SVR4 PIC code. */
17484 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17488 /* This is ignored when not generating SVR4 PIC code. */
17489 if (mips_pic
!= SVR4_PIC
)
17495 mips_mark_labels ();
17496 mips_assembling_insn
= TRUE
;
17498 /* Add $gp to the register named as an argument. */
17500 reg
= tc_get_register (0);
17501 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17504 mips_assembling_insn
= FALSE
;
17505 demand_empty_rest_of_line ();
17508 /* Handle the .insn pseudo-op. This marks instruction labels in
17509 mips16/micromips mode. This permits the linker to handle them specially,
17510 such as generating jalx instructions when needed. We also make
17511 them odd for the duration of the assembly, in order to generate the
17512 right sort of code. We will make them even in the adjust_symtab
17513 routine, while leaving them marked. This is convenient for the
17514 debugger and the disassembler. The linker knows to make them odd
17518 s_insn (int ignore ATTRIBUTE_UNUSED
)
17520 mips_mark_labels ();
17522 demand_empty_rest_of_line ();
17525 /* Handle the .nan pseudo-op. */
17528 s_nan (int ignore ATTRIBUTE_UNUSED
)
17530 static const char str_legacy
[] = "legacy";
17531 static const char str_2008
[] = "2008";
17534 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17536 if (i
== sizeof (str_2008
) - 1
17537 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17538 mips_flag_nan2008
= TRUE
;
17539 else if (i
== sizeof (str_legacy
) - 1
17540 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17541 mips_flag_nan2008
= FALSE
;
17543 as_bad (_("Bad .nan directive"));
17545 input_line_pointer
+= i
;
17546 demand_empty_rest_of_line ();
17549 /* Handle a .stab[snd] directive. Ideally these directives would be
17550 implemented in a transparent way, so that removing them would not
17551 have any effect on the generated instructions. However, s_stab
17552 internally changes the section, so in practice we need to decide
17553 now whether the preceding label marks compressed code. We do not
17554 support changing the compression mode of a label after a .stab*
17555 directive, such as in:
17561 so the current mode wins. */
17564 s_mips_stab (int type
)
17566 mips_mark_labels ();
17570 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17573 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17580 name
= input_line_pointer
;
17581 c
= get_symbol_end ();
17582 symbolP
= symbol_find_or_make (name
);
17583 S_SET_WEAK (symbolP
);
17584 *input_line_pointer
= c
;
17586 SKIP_WHITESPACE ();
17588 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17590 if (S_IS_DEFINED (symbolP
))
17592 as_bad (_("ignoring attempt to redefine symbol %s"),
17593 S_GET_NAME (symbolP
));
17594 ignore_rest_of_line ();
17598 if (*input_line_pointer
== ',')
17600 ++input_line_pointer
;
17601 SKIP_WHITESPACE ();
17605 if (exp
.X_op
!= O_symbol
)
17607 as_bad (_("bad .weakext directive"));
17608 ignore_rest_of_line ();
17611 symbol_set_value_expression (symbolP
, &exp
);
17614 demand_empty_rest_of_line ();
17617 /* Parse a register string into a number. Called from the ECOFF code
17618 to parse .frame. The argument is non-zero if this is the frame
17619 register, so that we can record it in mips_frame_reg. */
17622 tc_get_register (int frame
)
17626 SKIP_WHITESPACE ();
17627 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17631 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17632 mips_frame_reg_valid
= 1;
17633 mips_cprestore_valid
= 0;
17639 md_section_align (asection
*seg
, valueT addr
)
17641 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17643 /* We don't need to align ELF sections to the full alignment.
17644 However, Irix 5 may prefer that we align them at least to a 16
17645 byte boundary. We don't bother to align the sections if we
17646 are targeted for an embedded system. */
17647 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17652 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17655 /* Utility routine, called from above as well. If called while the
17656 input file is still being read, it's only an approximation. (For
17657 example, a symbol may later become defined which appeared to be
17658 undefined earlier.) */
17661 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17666 if (g_switch_value
> 0)
17668 const char *symname
;
17671 /* Find out whether this symbol can be referenced off the $gp
17672 register. It can be if it is smaller than the -G size or if
17673 it is in the .sdata or .sbss section. Certain symbols can
17674 not be referenced off the $gp, although it appears as though
17676 symname
= S_GET_NAME (sym
);
17677 if (symname
!= (const char *) NULL
17678 && (strcmp (symname
, "eprol") == 0
17679 || strcmp (symname
, "etext") == 0
17680 || strcmp (symname
, "_gp") == 0
17681 || strcmp (symname
, "edata") == 0
17682 || strcmp (symname
, "_fbss") == 0
17683 || strcmp (symname
, "_fdata") == 0
17684 || strcmp (symname
, "_ftext") == 0
17685 || strcmp (symname
, "end") == 0
17686 || strcmp (symname
, "_gp_disp") == 0))
17688 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17690 #ifndef NO_ECOFF_DEBUGGING
17691 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17692 && (symbol_get_obj (sym
)->ecoff_extern_size
17693 <= g_switch_value
))
17695 /* We must defer this decision until after the whole
17696 file has been read, since there might be a .extern
17697 after the first use of this symbol. */
17698 || (before_relaxing
17699 #ifndef NO_ECOFF_DEBUGGING
17700 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17702 && S_GET_VALUE (sym
) == 0)
17703 || (S_GET_VALUE (sym
) != 0
17704 && S_GET_VALUE (sym
) <= g_switch_value
)))
17708 const char *segname
;
17710 segname
= segment_name (S_GET_SEGMENT (sym
));
17711 gas_assert (strcmp (segname
, ".lit8") != 0
17712 && strcmp (segname
, ".lit4") != 0);
17713 change
= (strcmp (segname
, ".sdata") != 0
17714 && strcmp (segname
, ".sbss") != 0
17715 && strncmp (segname
, ".sdata.", 7) != 0
17716 && strncmp (segname
, ".sbss.", 6) != 0
17717 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17718 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17723 /* We are not optimizing for the $gp register. */
17728 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17731 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17735 /* Handle the case of a symbol equated to another symbol. */
17736 while (symbol_equated_reloc_p (sym
))
17740 /* It's possible to get a loop here in a badly written program. */
17741 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17747 if (symbol_section_p (sym
))
17750 symsec
= S_GET_SEGMENT (sym
);
17752 /* This must duplicate the test in adjust_reloc_syms. */
17753 return (!bfd_is_und_section (symsec
)
17754 && !bfd_is_abs_section (symsec
)
17755 && !bfd_is_com_section (symsec
)
17756 && !s_is_linkonce (sym
, segtype
)
17757 /* A global or weak symbol is treated as external. */
17758 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17762 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17763 extended opcode. SEC is the section the frag is in. */
17766 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17769 const struct mips16_immed_operand
*op
;
17771 int mintiny
, maxtiny
;
17775 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17777 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17780 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17781 op
= mips16_immed_operands
;
17782 while (op
->type
!= type
)
17785 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17790 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17793 maxtiny
= 1 << op
->nbits
;
17798 maxtiny
= (1 << op
->nbits
) - 1;
17803 mintiny
= - (1 << (op
->nbits
- 1));
17804 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17807 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17808 val
= S_GET_VALUE (fragp
->fr_symbol
);
17809 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17815 /* We won't have the section when we are called from
17816 mips_relax_frag. However, we will always have been called
17817 from md_estimate_size_before_relax first. If this is a
17818 branch to a different section, we mark it as such. If SEC is
17819 NULL, and the frag is not marked, then it must be a branch to
17820 the same section. */
17823 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17828 /* Must have been called from md_estimate_size_before_relax. */
17831 fragp
->fr_subtype
=
17832 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17834 /* FIXME: We should support this, and let the linker
17835 catch branches and loads that are out of range. */
17836 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17837 _("unsupported PC relative reference to different section"));
17841 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17842 /* Assume non-extended on the first relaxation pass.
17843 The address we have calculated will be bogus if this is
17844 a forward branch to another frag, as the forward frag
17845 will have fr_address == 0. */
17849 /* In this case, we know for sure that the symbol fragment is in
17850 the same section. If the relax_marker of the symbol fragment
17851 differs from the relax_marker of this fragment, we have not
17852 yet adjusted the symbol fragment fr_address. We want to add
17853 in STRETCH in order to get a better estimate of the address.
17854 This particularly matters because of the shift bits. */
17856 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17860 /* Adjust stretch for any alignment frag. Note that if have
17861 been expanding the earlier code, the symbol may be
17862 defined in what appears to be an earlier frag. FIXME:
17863 This doesn't handle the fr_subtype field, which specifies
17864 a maximum number of bytes to skip when doing an
17866 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17868 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17871 stretch
= - ((- stretch
)
17872 & ~ ((1 << (int) f
->fr_offset
) - 1));
17874 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17883 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17885 /* The base address rules are complicated. The base address of
17886 a branch is the following instruction. The base address of a
17887 PC relative load or add is the instruction itself, but if it
17888 is in a delay slot (in which case it can not be extended) use
17889 the address of the instruction whose delay slot it is in. */
17890 if (type
== 'p' || type
== 'q')
17894 /* If we are currently assuming that this frag should be
17895 extended, then, the current address is two bytes
17897 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17900 /* Ignore the low bit in the target, since it will be set
17901 for a text label. */
17902 if ((val
& 1) != 0)
17905 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17907 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17910 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17912 /* Branch offsets have an implicit 0 in the lowest bit. */
17913 if (type
== 'p' || type
== 'q')
17916 /* If any of the shifted bits are set, we must use an extended
17917 opcode. If the address depends on the size of this
17918 instruction, this can lead to a loop, so we arrange to always
17919 use an extended opcode. We only check this when we are in
17920 the main relaxation loop, when SEC is NULL. */
17921 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17923 fragp
->fr_subtype
=
17924 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17928 /* If we are about to mark a frag as extended because the value
17929 is precisely maxtiny + 1, then there is a chance of an
17930 infinite loop as in the following code:
17935 In this case when the la is extended, foo is 0x3fc bytes
17936 away, so the la can be shrunk, but then foo is 0x400 away, so
17937 the la must be extended. To avoid this loop, we mark the
17938 frag as extended if it was small, and is about to become
17939 extended with a value of maxtiny + 1. */
17940 if (val
== ((maxtiny
+ 1) << op
->shift
)
17941 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17944 fragp
->fr_subtype
=
17945 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17949 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17950 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17952 if ((val
& ((1 << op
->shift
) - 1)) != 0
17953 || val
< (mintiny
<< op
->shift
)
17954 || val
> (maxtiny
<< op
->shift
))
17960 /* Compute the length of a branch sequence, and adjust the
17961 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17962 worst-case length is computed, with UPDATE being used to indicate
17963 whether an unconditional (-1), branch-likely (+1) or regular (0)
17964 branch is to be computed. */
17966 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17968 bfd_boolean toofar
;
17972 && S_IS_DEFINED (fragp
->fr_symbol
)
17973 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17978 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17980 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17984 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17987 /* If the symbol is not defined or it's in a different segment,
17988 assume the user knows what's going on and emit a short
17994 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17996 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17997 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17998 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17999 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
18005 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
18008 if (mips_pic
!= NO_PIC
)
18010 /* Additional space for PIC loading of target address. */
18012 if (mips_opts
.isa
== ISA_MIPS1
)
18013 /* Additional space for $at-stabilizing nop. */
18017 /* If branch is conditional. */
18018 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
18025 /* Compute the length of a branch sequence, and adjust the
18026 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18027 worst-case length is computed, with UPDATE being used to indicate
18028 whether an unconditional (-1), or regular (0) branch is to be
18032 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18034 bfd_boolean toofar
;
18038 && S_IS_DEFINED (fragp
->fr_symbol
)
18039 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18044 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18045 /* Ignore the low bit in the target, since it will be set
18046 for a text label. */
18047 if ((val
& 1) != 0)
18050 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18054 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18057 /* If the symbol is not defined or it's in a different segment,
18058 assume the user knows what's going on and emit a short
18064 if (fragp
&& update
18065 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18066 fragp
->fr_subtype
= (toofar
18067 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18068 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18073 bfd_boolean compact_known
= fragp
!= NULL
;
18074 bfd_boolean compact
= FALSE
;
18075 bfd_boolean uncond
;
18078 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18080 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18082 uncond
= update
< 0;
18084 /* If label is out of range, we turn branch <br>:
18086 <br> label # 4 bytes
18092 nop # 2 bytes if compact && !PIC
18095 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
18098 /* If assembling PIC code, we further turn:
18104 lw/ld at, %got(label)(gp) # 4 bytes
18105 d/addiu at, %lo(label) # 4 bytes
18108 if (mips_pic
!= NO_PIC
)
18111 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18113 <brneg> 0f # 4 bytes
18114 nop # 2 bytes if !compact
18117 length
+= (compact_known
&& compact
) ? 4 : 6;
18123 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18124 bit accordingly. */
18127 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18129 bfd_boolean toofar
;
18132 && S_IS_DEFINED (fragp
->fr_symbol
)
18133 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18139 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18140 /* Ignore the low bit in the target, since it will be set
18141 for a text label. */
18142 if ((val
& 1) != 0)
18145 /* Assume this is a 2-byte branch. */
18146 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18148 /* We try to avoid the infinite loop by not adding 2 more bytes for
18153 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18155 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18156 else if (type
== 'E')
18157 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18162 /* If the symbol is not defined or it's in a different segment,
18163 we emit a normal 32-bit branch. */
18166 if (fragp
&& update
18167 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18169 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18170 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18178 /* Estimate the size of a frag before relaxing. Unless this is the
18179 mips16, we are not really relaxing here, and the final size is
18180 encoded in the subtype information. For the mips16, we have to
18181 decide whether we are using an extended opcode or not. */
18184 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18188 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18191 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18193 return fragp
->fr_var
;
18196 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18197 /* We don't want to modify the EXTENDED bit here; it might get us
18198 into infinite loops. We change it only in mips_relax_frag(). */
18199 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
18201 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18205 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18206 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18207 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18208 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18209 fragp
->fr_var
= length
;
18214 if (mips_pic
== NO_PIC
)
18215 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18216 else if (mips_pic
== SVR4_PIC
)
18217 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
18218 else if (mips_pic
== VXWORKS_PIC
)
18219 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18226 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18227 return -RELAX_FIRST (fragp
->fr_subtype
);
18230 return -RELAX_SECOND (fragp
->fr_subtype
);
18233 /* This is called to see whether a reloc against a defined symbol
18234 should be converted into a reloc against a section. */
18237 mips_fix_adjustable (fixS
*fixp
)
18239 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18240 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18243 if (fixp
->fx_addsy
== NULL
)
18246 /* If symbol SYM is in a mergeable section, relocations of the form
18247 SYM + 0 can usually be made section-relative. The mergeable data
18248 is then identified by the section offset rather than by the symbol.
18250 However, if we're generating REL LO16 relocations, the offset is split
18251 between the LO16 and parterning high part relocation. The linker will
18252 need to recalculate the complete offset in order to correctly identify
18255 The linker has traditionally not looked for the parterning high part
18256 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18257 placed anywhere. Rather than break backwards compatibility by changing
18258 this, it seems better not to force the issue, and instead keep the
18259 original symbol. This will work with either linker behavior. */
18260 if ((lo16_reloc_p (fixp
->fx_r_type
)
18261 || reloc_needs_lo_p (fixp
->fx_r_type
))
18262 && HAVE_IN_PLACE_ADDENDS
18263 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18266 /* There is no place to store an in-place offset for JALR relocations.
18267 Likewise an in-range offset of limited PC-relative relocations may
18268 overflow the in-place relocatable field if recalculated against the
18269 start address of the symbol's containing section. */
18270 if (HAVE_IN_PLACE_ADDENDS
18271 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18272 || jalr_reloc_p (fixp
->fx_r_type
)))
18275 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18276 to a floating-point stub. The same is true for non-R_MIPS16_26
18277 relocations against MIPS16 functions; in this case, the stub becomes
18278 the function's canonical address.
18280 Floating-point stubs are stored in unique .mips16.call.* or
18281 .mips16.fn.* sections. If a stub T for function F is in section S,
18282 the first relocation in section S must be against F; this is how the
18283 linker determines the target function. All relocations that might
18284 resolve to T must also be against F. We therefore have the following
18285 restrictions, which are given in an intentionally-redundant way:
18287 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18290 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18291 if that stub might be used.
18293 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18296 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18297 that stub might be used.
18299 There is a further restriction:
18301 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18302 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
18303 targets with in-place addends; the relocation field cannot
18304 encode the low bit.
18306 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18307 against a MIPS16 symbol. We deal with (5) by by not reducing any
18308 such relocations on REL targets.
18310 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18311 relocation against some symbol R, no relocation against R may be
18312 reduced. (Note that this deals with (2) as well as (1) because
18313 relocations against global symbols will never be reduced on ELF
18314 targets.) This approach is a little simpler than trying to detect
18315 stub sections, and gives the "all or nothing" per-symbol consistency
18316 that we have for MIPS16 symbols. */
18317 if (fixp
->fx_subsy
== NULL
18318 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18319 || *symbol_get_tc (fixp
->fx_addsy
)
18320 || (HAVE_IN_PLACE_ADDENDS
18321 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18322 && jmp_reloc_p (fixp
->fx_r_type
))))
18328 /* Translate internal representation of relocation info to BFD target
18332 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18334 static arelent
*retval
[4];
18336 bfd_reloc_code_real_type code
;
18338 memset (retval
, 0, sizeof(retval
));
18339 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
18340 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
18341 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18342 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18344 if (fixp
->fx_pcrel
)
18346 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18347 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18348 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18349 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18350 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
18352 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18353 Relocations want only the symbol offset. */
18354 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18357 reloc
->addend
= fixp
->fx_addnumber
;
18359 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18360 entry to be used in the relocation's section offset. */
18361 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18363 reloc
->address
= reloc
->addend
;
18367 code
= fixp
->fx_r_type
;
18369 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18370 if (reloc
->howto
== NULL
)
18372 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18373 _("Can not represent %s relocation in this object file format"),
18374 bfd_get_reloc_code_name (code
));
18381 /* Relax a machine dependent frag. This returns the amount by which
18382 the current size of the frag should change. */
18385 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18387 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18389 offsetT old_var
= fragp
->fr_var
;
18391 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18393 return fragp
->fr_var
- old_var
;
18396 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18398 offsetT old_var
= fragp
->fr_var
;
18399 offsetT new_var
= 4;
18401 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18402 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18403 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18404 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18405 fragp
->fr_var
= new_var
;
18407 return new_var
- old_var
;
18410 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18413 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18415 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18417 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18422 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18424 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18431 /* Convert a machine dependent frag. */
18434 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18436 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18439 unsigned long insn
;
18443 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18444 insn
= read_insn (buf
);
18446 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18448 /* We generate a fixup instead of applying it right now
18449 because, if there are linker relaxations, we're going to
18450 need the relocations. */
18451 exp
.X_op
= O_symbol
;
18452 exp
.X_add_symbol
= fragp
->fr_symbol
;
18453 exp
.X_add_number
= fragp
->fr_offset
;
18455 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18456 BFD_RELOC_16_PCREL_S2
);
18457 fixp
->fx_file
= fragp
->fr_file
;
18458 fixp
->fx_line
= fragp
->fr_line
;
18460 buf
= write_insn (buf
, insn
);
18466 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18467 _("Relaxed out-of-range branch into a jump"));
18469 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18472 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18474 /* Reverse the branch. */
18475 switch ((insn
>> 28) & 0xf)
18478 /* bc[0-3][tf]l? instructions can have the condition
18479 reversed by tweaking a single TF bit, and their
18480 opcodes all have 0x4???????. */
18481 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18482 insn
^= 0x00010000;
18486 /* bltz 0x04000000 bgez 0x04010000
18487 bltzal 0x04100000 bgezal 0x04110000 */
18488 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18489 insn
^= 0x00010000;
18493 /* beq 0x10000000 bne 0x14000000
18494 blez 0x18000000 bgtz 0x1c000000 */
18495 insn
^= 0x04000000;
18503 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18505 /* Clear the and-link bit. */
18506 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18508 /* bltzal 0x04100000 bgezal 0x04110000
18509 bltzall 0x04120000 bgezall 0x04130000 */
18510 insn
&= ~0x00100000;
18513 /* Branch over the branch (if the branch was likely) or the
18514 full jump (not likely case). Compute the offset from the
18515 current instruction to branch to. */
18516 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18520 /* How many bytes in instructions we've already emitted? */
18521 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18522 /* How many bytes in instructions from here to the end? */
18523 i
= fragp
->fr_var
- i
;
18525 /* Convert to instruction count. */
18527 /* Branch counts from the next instruction. */
18530 /* Branch over the jump. */
18531 buf
= write_insn (buf
, insn
);
18534 buf
= write_insn (buf
, 0);
18536 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18538 /* beql $0, $0, 2f */
18540 /* Compute the PC offset from the current instruction to
18541 the end of the variable frag. */
18542 /* How many bytes in instructions we've already emitted? */
18543 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18544 /* How many bytes in instructions from here to the end? */
18545 i
= fragp
->fr_var
- i
;
18546 /* Convert to instruction count. */
18548 /* Don't decrement i, because we want to branch over the
18552 buf
= write_insn (buf
, insn
);
18553 buf
= write_insn (buf
, 0);
18557 if (mips_pic
== NO_PIC
)
18560 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18561 ? 0x0c000000 : 0x08000000);
18562 exp
.X_op
= O_symbol
;
18563 exp
.X_add_symbol
= fragp
->fr_symbol
;
18564 exp
.X_add_number
= fragp
->fr_offset
;
18566 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18567 FALSE
, BFD_RELOC_MIPS_JMP
);
18568 fixp
->fx_file
= fragp
->fr_file
;
18569 fixp
->fx_line
= fragp
->fr_line
;
18571 buf
= write_insn (buf
, insn
);
18575 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18577 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18578 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18579 insn
|= at
<< OP_SH_RT
;
18580 exp
.X_op
= O_symbol
;
18581 exp
.X_add_symbol
= fragp
->fr_symbol
;
18582 exp
.X_add_number
= fragp
->fr_offset
;
18584 if (fragp
->fr_offset
)
18586 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18587 exp
.X_add_number
= 0;
18590 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18591 FALSE
, BFD_RELOC_MIPS_GOT16
);
18592 fixp
->fx_file
= fragp
->fr_file
;
18593 fixp
->fx_line
= fragp
->fr_line
;
18595 buf
= write_insn (buf
, insn
);
18597 if (mips_opts
.isa
== ISA_MIPS1
)
18599 buf
= write_insn (buf
, 0);
18601 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18602 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18603 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18605 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18606 FALSE
, BFD_RELOC_LO16
);
18607 fixp
->fx_file
= fragp
->fr_file
;
18608 fixp
->fx_line
= fragp
->fr_line
;
18610 buf
= write_insn (buf
, insn
);
18613 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18617 insn
|= at
<< OP_SH_RS
;
18619 buf
= write_insn (buf
, insn
);
18623 fragp
->fr_fix
+= fragp
->fr_var
;
18624 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18628 /* Relax microMIPS branches. */
18629 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18631 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18632 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18633 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18634 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18635 bfd_boolean short_ds
;
18636 unsigned long insn
;
18640 exp
.X_op
= O_symbol
;
18641 exp
.X_add_symbol
= fragp
->fr_symbol
;
18642 exp
.X_add_number
= fragp
->fr_offset
;
18644 fragp
->fr_fix
+= fragp
->fr_var
;
18646 /* Handle 16-bit branches that fit or are forced to fit. */
18647 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18649 /* We generate a fixup instead of applying it right now,
18650 because if there is linker relaxation, we're going to
18651 need the relocations. */
18653 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18654 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18655 else if (type
== 'E')
18656 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18657 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18661 fixp
->fx_file
= fragp
->fr_file
;
18662 fixp
->fx_line
= fragp
->fr_line
;
18664 /* These relocations can have an addend that won't fit in
18666 fixp
->fx_no_overflow
= 1;
18671 /* Handle 32-bit branches that fit or are forced to fit. */
18672 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18673 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18675 /* We generate a fixup instead of applying it right now,
18676 because if there is linker relaxation, we're going to
18677 need the relocations. */
18678 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18679 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18680 fixp
->fx_file
= fragp
->fr_file
;
18681 fixp
->fx_line
= fragp
->fr_line
;
18687 /* Relax 16-bit branches to 32-bit branches. */
18690 insn
= read_compressed_insn (buf
, 2);
18692 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18693 insn
= 0x94000000; /* beq */
18694 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18696 unsigned long regno
;
18698 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18699 regno
= micromips_to_32_reg_d_map
[regno
];
18700 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18701 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18706 /* Nothing else to do, just write it out. */
18707 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18708 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18710 buf
= write_compressed_insn (buf
, insn
, 4);
18711 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18716 insn
= read_compressed_insn (buf
, 4);
18718 /* Relax 32-bit branches to a sequence of instructions. */
18719 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18720 _("Relaxed out-of-range branch into a jump"));
18722 /* Set the short-delay-slot bit. */
18723 short_ds
= al
&& (insn
& 0x02000000) != 0;
18725 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18729 /* Reverse the branch. */
18730 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18731 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18732 insn
^= 0x20000000;
18733 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18734 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18735 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18736 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18737 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18738 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18739 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18740 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18741 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18742 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18743 insn
^= 0x00400000;
18744 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18745 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18746 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18747 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18748 insn
^= 0x00200000;
18754 /* Clear the and-link and short-delay-slot bits. */
18755 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18757 /* bltzal 0x40200000 bgezal 0x40600000 */
18758 /* bltzals 0x42200000 bgezals 0x42600000 */
18759 insn
&= ~0x02200000;
18762 /* Make a label at the end for use with the branch. */
18763 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18764 micromips_label_inc ();
18765 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18768 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18769 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18770 fixp
->fx_file
= fragp
->fr_file
;
18771 fixp
->fx_line
= fragp
->fr_line
;
18773 /* Branch over the jump. */
18774 buf
= write_compressed_insn (buf
, insn
, 4);
18777 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18780 if (mips_pic
== NO_PIC
)
18782 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18784 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18785 insn
= al
? jal
: 0xd4000000;
18787 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18788 BFD_RELOC_MICROMIPS_JMP
);
18789 fixp
->fx_file
= fragp
->fr_file
;
18790 fixp
->fx_line
= fragp
->fr_line
;
18792 buf
= write_compressed_insn (buf
, insn
, 4);
18795 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18799 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18800 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18801 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18803 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18804 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18805 insn
|= at
<< MICROMIPSOP_SH_RT
;
18807 if (exp
.X_add_number
)
18809 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18810 exp
.X_add_number
= 0;
18813 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18814 BFD_RELOC_MICROMIPS_GOT16
);
18815 fixp
->fx_file
= fragp
->fr_file
;
18816 fixp
->fx_line
= fragp
->fr_line
;
18818 buf
= write_compressed_insn (buf
, insn
, 4);
18820 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18821 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18822 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18824 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18825 BFD_RELOC_MICROMIPS_LO16
);
18826 fixp
->fx_file
= fragp
->fr_file
;
18827 fixp
->fx_line
= fragp
->fr_line
;
18829 buf
= write_compressed_insn (buf
, insn
, 4);
18831 /* jr/jrc/jalr/jalrs $at */
18832 insn
= al
? jalr
: jr
;
18833 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18835 buf
= write_compressed_insn (buf
, insn
, 2);
18838 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18842 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18845 const struct mips16_immed_operand
*op
;
18848 unsigned int user_length
, length
;
18849 unsigned long insn
;
18852 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18853 op
= mips16_immed_operands
;
18854 while (op
->type
!= type
)
18857 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18858 val
= resolve_symbol_value (fragp
->fr_symbol
);
18863 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18865 /* The rules for the base address of a PC relative reloc are
18866 complicated; see mips16_extended_frag. */
18867 if (type
== 'p' || type
== 'q')
18872 /* Ignore the low bit in the target, since it will be
18873 set for a text label. */
18874 if ((val
& 1) != 0)
18877 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18879 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18882 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18885 /* Make sure the section winds up with the alignment we have
18888 record_alignment (asec
, op
->shift
);
18892 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18893 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18894 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18895 _("extended instruction in delay slot"));
18897 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18899 insn
= read_compressed_insn (buf
, 2);
18901 insn
|= MIPS16_EXTEND
;
18903 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18905 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18910 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18911 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18913 length
= (ext
? 4 : 2);
18914 gas_assert (mips16_opcode_length (insn
) == length
);
18915 write_compressed_insn (buf
, insn
, length
);
18916 fragp
->fr_fix
+= length
;
18920 relax_substateT subtype
= fragp
->fr_subtype
;
18921 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18922 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18926 first
= RELAX_FIRST (subtype
);
18927 second
= RELAX_SECOND (subtype
);
18928 fixp
= (fixS
*) fragp
->fr_opcode
;
18930 /* If the delay slot chosen does not match the size of the instruction,
18931 then emit a warning. */
18932 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18933 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18938 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18939 | RELAX_DELAY_SLOT_SIZE_FIRST
18940 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18941 msg
= macro_warning (s
);
18943 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18947 /* Possibly emit a warning if we've chosen the longer option. */
18948 if (use_second
== second_longer
)
18954 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18955 msg
= macro_warning (s
);
18957 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18961 /* Go through all the fixups for the first sequence. Disable them
18962 (by marking them as done) if we're going to use the second
18963 sequence instead. */
18965 && fixp
->fx_frag
== fragp
18966 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18968 if (subtype
& RELAX_USE_SECOND
)
18970 fixp
= fixp
->fx_next
;
18973 /* Go through the fixups for the second sequence. Disable them if
18974 we're going to use the first sequence, otherwise adjust their
18975 addresses to account for the relaxation. */
18976 while (fixp
&& fixp
->fx_frag
== fragp
)
18978 if (subtype
& RELAX_USE_SECOND
)
18979 fixp
->fx_where
-= first
;
18982 fixp
= fixp
->fx_next
;
18985 /* Now modify the frag contents. */
18986 if (subtype
& RELAX_USE_SECOND
)
18990 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18991 memmove (start
, start
+ first
, second
);
18992 fragp
->fr_fix
-= first
;
18995 fragp
->fr_fix
-= second
;
18999 /* This function is called after the relocs have been generated.
19000 We've been storing mips16 text labels as odd. Here we convert them
19001 back to even for the convenience of the debugger. */
19004 mips_frob_file_after_relocs (void)
19007 unsigned int count
, i
;
19009 syms
= bfd_get_outsymbols (stdoutput
);
19010 count
= bfd_get_symcount (stdoutput
);
19011 for (i
= 0; i
< count
; i
++, syms
++)
19012 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19013 && ((*syms
)->value
& 1) != 0)
19015 (*syms
)->value
&= ~1;
19016 /* If the symbol has an odd size, it was probably computed
19017 incorrectly, so adjust that as well. */
19018 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19019 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19023 /* This function is called whenever a label is defined, including fake
19024 labels instantiated off the dot special symbol. It is used when
19025 handling branch delays; if a branch has a label, we assume we cannot
19026 move it. This also bumps the value of the symbol by 1 in compressed
19030 mips_record_label (symbolS
*sym
)
19032 segment_info_type
*si
= seg_info (now_seg
);
19033 struct insn_label_list
*l
;
19035 if (free_insn_labels
== NULL
)
19036 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
19039 l
= free_insn_labels
;
19040 free_insn_labels
= l
->next
;
19044 l
->next
= si
->label_list
;
19045 si
->label_list
= l
;
19048 /* This function is called as tc_frob_label() whenever a label is defined
19049 and adds a DWARF-2 record we only want for true labels. */
19052 mips_define_label (symbolS
*sym
)
19054 mips_record_label (sym
);
19055 dwarf2_emit_label (sym
);
19058 /* This function is called by tc_new_dot_label whenever a new dot symbol
19062 mips_add_dot_label (symbolS
*sym
)
19064 mips_record_label (sym
);
19065 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19066 mips_compressed_mark_label (sym
);
19069 /* Some special processing for a MIPS ELF file. */
19072 mips_elf_final_processing (void)
19074 /* Write out the register information. */
19075 if (mips_abi
!= N64_ABI
)
19079 s
.ri_gprmask
= mips_gprmask
;
19080 s
.ri_cprmask
[0] = mips_cprmask
[0];
19081 s
.ri_cprmask
[1] = mips_cprmask
[1];
19082 s
.ri_cprmask
[2] = mips_cprmask
[2];
19083 s
.ri_cprmask
[3] = mips_cprmask
[3];
19084 /* The gp_value field is set by the MIPS ELF backend. */
19086 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19087 ((Elf32_External_RegInfo
*)
19088 mips_regmask_frag
));
19092 Elf64_Internal_RegInfo s
;
19094 s
.ri_gprmask
= mips_gprmask
;
19096 s
.ri_cprmask
[0] = mips_cprmask
[0];
19097 s
.ri_cprmask
[1] = mips_cprmask
[1];
19098 s
.ri_cprmask
[2] = mips_cprmask
[2];
19099 s
.ri_cprmask
[3] = mips_cprmask
[3];
19100 /* The gp_value field is set by the MIPS ELF backend. */
19102 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19103 ((Elf64_External_RegInfo
*)
19104 mips_regmask_frag
));
19107 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19108 sort of BFD interface for this. */
19109 if (mips_any_noreorder
)
19110 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19111 if (mips_pic
!= NO_PIC
)
19113 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19114 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19117 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19119 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19120 defined at present; this might need to change in future. */
19121 if (file_ase_mips16
)
19122 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19123 if (file_ase_micromips
)
19124 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19125 if (file_ase
& ASE_MDMX
)
19126 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19128 /* Set the MIPS ELF ABI flags. */
19129 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19130 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19131 else if (mips_abi
== O64_ABI
)
19132 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19133 else if (mips_abi
== EABI_ABI
)
19135 if (!file_mips_gp32
)
19136 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19138 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19140 else if (mips_abi
== N32_ABI
)
19141 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19143 /* Nothing to do for N64_ABI. */
19145 if (mips_32bitmode
)
19146 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19148 if (mips_flag_nan2008
)
19149 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19151 #if 0 /* XXX FIXME */
19152 /* 32 bit code with 64 bit FP registers. */
19153 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
19154 elf_elfheader (stdoutput
)->e_flags
|= ???;
19158 typedef struct proc
{
19160 symbolS
*func_end_sym
;
19161 unsigned long reg_mask
;
19162 unsigned long reg_offset
;
19163 unsigned long fpreg_mask
;
19164 unsigned long fpreg_offset
;
19165 unsigned long frame_offset
;
19166 unsigned long frame_reg
;
19167 unsigned long pc_reg
;
19170 static procS cur_proc
;
19171 static procS
*cur_proc_ptr
;
19172 static int numprocs
;
19174 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19175 as "2", and a normal nop as "0". */
19177 #define NOP_OPCODE_MIPS 0
19178 #define NOP_OPCODE_MIPS16 1
19179 #define NOP_OPCODE_MICROMIPS 2
19182 mips_nop_opcode (void)
19184 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19185 return NOP_OPCODE_MICROMIPS
;
19186 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19187 return NOP_OPCODE_MIPS16
;
19189 return NOP_OPCODE_MIPS
;
19192 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19193 32-bit microMIPS NOPs here (if applicable). */
19196 mips_handle_align (fragS
*fragp
)
19200 int bytes
, size
, excess
;
19203 if (fragp
->fr_type
!= rs_align_code
)
19206 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19208 switch (nop_opcode
)
19210 case NOP_OPCODE_MICROMIPS
:
19211 opcode
= micromips_nop32_insn
.insn_opcode
;
19214 case NOP_OPCODE_MIPS16
:
19215 opcode
= mips16_nop_insn
.insn_opcode
;
19218 case NOP_OPCODE_MIPS
:
19220 opcode
= nop_insn
.insn_opcode
;
19225 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19226 excess
= bytes
% size
;
19228 /* Handle the leading part if we're not inserting a whole number of
19229 instructions, and make it the end of the fixed part of the frag.
19230 Try to fit in a short microMIPS NOP if applicable and possible,
19231 and use zeroes otherwise. */
19232 gas_assert (excess
< 4);
19233 fragp
->fr_fix
+= excess
;
19238 /* Fall through. */
19240 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19242 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19246 /* Fall through. */
19249 /* Fall through. */
19254 md_number_to_chars (p
, opcode
, size
);
19255 fragp
->fr_var
= size
;
19259 md_obj_begin (void)
19266 /* Check for premature end, nesting errors, etc. */
19268 as_warn (_("missing .end at end of assembly"));
19277 if (*input_line_pointer
== '-')
19279 ++input_line_pointer
;
19282 if (!ISDIGIT (*input_line_pointer
))
19283 as_bad (_("expected simple number"));
19284 if (input_line_pointer
[0] == '0')
19286 if (input_line_pointer
[1] == 'x')
19288 input_line_pointer
+= 2;
19289 while (ISXDIGIT (*input_line_pointer
))
19292 val
|= hex_value (*input_line_pointer
++);
19294 return negative
? -val
: val
;
19298 ++input_line_pointer
;
19299 while (ISDIGIT (*input_line_pointer
))
19302 val
|= *input_line_pointer
++ - '0';
19304 return negative
? -val
: val
;
19307 if (!ISDIGIT (*input_line_pointer
))
19309 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19310 *input_line_pointer
, *input_line_pointer
);
19311 as_warn (_("invalid number"));
19314 while (ISDIGIT (*input_line_pointer
))
19317 val
+= *input_line_pointer
++ - '0';
19319 return negative
? -val
: val
;
19322 /* The .file directive; just like the usual .file directive, but there
19323 is an initial number which is the ECOFF file index. In the non-ECOFF
19324 case .file implies DWARF-2. */
19327 s_mips_file (int x ATTRIBUTE_UNUSED
)
19329 static int first_file_directive
= 0;
19331 if (ECOFF_DEBUGGING
)
19340 filename
= dwarf2_directive_file (0);
19342 /* Versions of GCC up to 3.1 start files with a ".file"
19343 directive even for stabs output. Make sure that this
19344 ".file" is handled. Note that you need a version of GCC
19345 after 3.1 in order to support DWARF-2 on MIPS. */
19346 if (filename
!= NULL
&& ! first_file_directive
)
19348 (void) new_logical_line (filename
, -1);
19349 s_app_file_string (filename
, 0);
19351 first_file_directive
= 1;
19355 /* The .loc directive, implying DWARF-2. */
19358 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19360 if (!ECOFF_DEBUGGING
)
19361 dwarf2_directive_loc (0);
19364 /* The .end directive. */
19367 s_mips_end (int x ATTRIBUTE_UNUSED
)
19371 /* Following functions need their own .frame and .cprestore directives. */
19372 mips_frame_reg_valid
= 0;
19373 mips_cprestore_valid
= 0;
19375 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19378 demand_empty_rest_of_line ();
19383 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19384 as_warn (_(".end not in text section"));
19388 as_warn (_(".end directive without a preceding .ent directive."));
19389 demand_empty_rest_of_line ();
19395 gas_assert (S_GET_NAME (p
));
19396 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19397 as_warn (_(".end symbol does not match .ent symbol."));
19399 if (debug_type
== DEBUG_STABS
)
19400 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19404 as_warn (_(".end directive missing or unknown symbol"));
19406 /* Create an expression to calculate the size of the function. */
19407 if (p
&& cur_proc_ptr
)
19409 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19410 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19413 exp
->X_op
= O_subtract
;
19414 exp
->X_add_symbol
= symbol_temp_new_now ();
19415 exp
->X_op_symbol
= p
;
19416 exp
->X_add_number
= 0;
19418 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19421 /* Generate a .pdr section. */
19422 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19424 segT saved_seg
= now_seg
;
19425 subsegT saved_subseg
= now_subseg
;
19429 #ifdef md_flush_pending_output
19430 md_flush_pending_output ();
19433 gas_assert (pdr_seg
);
19434 subseg_set (pdr_seg
, 0);
19436 /* Write the symbol. */
19437 exp
.X_op
= O_symbol
;
19438 exp
.X_add_symbol
= p
;
19439 exp
.X_add_number
= 0;
19440 emit_expr (&exp
, 4);
19442 fragp
= frag_more (7 * 4);
19444 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19445 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19446 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19447 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19448 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19449 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19450 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19452 subseg_set (saved_seg
, saved_subseg
);
19455 cur_proc_ptr
= NULL
;
19458 /* The .aent and .ent directives. */
19461 s_mips_ent (int aent
)
19465 symbolP
= get_symbol ();
19466 if (*input_line_pointer
== ',')
19467 ++input_line_pointer
;
19468 SKIP_WHITESPACE ();
19469 if (ISDIGIT (*input_line_pointer
)
19470 || *input_line_pointer
== '-')
19473 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19474 as_warn (_(".ent or .aent not in text section."));
19476 if (!aent
&& cur_proc_ptr
)
19477 as_warn (_("missing .end"));
19481 /* This function needs its own .frame and .cprestore directives. */
19482 mips_frame_reg_valid
= 0;
19483 mips_cprestore_valid
= 0;
19485 cur_proc_ptr
= &cur_proc
;
19486 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19488 cur_proc_ptr
->func_sym
= symbolP
;
19492 if (debug_type
== DEBUG_STABS
)
19493 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19494 S_GET_NAME (symbolP
));
19497 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19499 demand_empty_rest_of_line ();
19502 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19503 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19504 s_mips_frame is used so that we can set the PDR information correctly.
19505 We can't use the ecoff routines because they make reference to the ecoff
19506 symbol table (in the mdebug section). */
19509 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19511 if (ECOFF_DEBUGGING
)
19517 if (cur_proc_ptr
== (procS
*) NULL
)
19519 as_warn (_(".frame outside of .ent"));
19520 demand_empty_rest_of_line ();
19524 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19526 SKIP_WHITESPACE ();
19527 if (*input_line_pointer
++ != ','
19528 || get_absolute_expression_and_terminator (&val
) != ',')
19530 as_warn (_("Bad .frame directive"));
19531 --input_line_pointer
;
19532 demand_empty_rest_of_line ();
19536 cur_proc_ptr
->frame_offset
= val
;
19537 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19539 demand_empty_rest_of_line ();
19543 /* The .fmask and .mask directives. If the mdebug section is present
19544 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19545 embedded targets, s_mips_mask is used so that we can set the PDR
19546 information correctly. We can't use the ecoff routines because they
19547 make reference to the ecoff symbol table (in the mdebug section). */
19550 s_mips_mask (int reg_type
)
19552 if (ECOFF_DEBUGGING
)
19553 s_ignore (reg_type
);
19558 if (cur_proc_ptr
== (procS
*) NULL
)
19560 as_warn (_(".mask/.fmask outside of .ent"));
19561 demand_empty_rest_of_line ();
19565 if (get_absolute_expression_and_terminator (&mask
) != ',')
19567 as_warn (_("Bad .mask/.fmask directive"));
19568 --input_line_pointer
;
19569 demand_empty_rest_of_line ();
19573 off
= get_absolute_expression ();
19575 if (reg_type
== 'F')
19577 cur_proc_ptr
->fpreg_mask
= mask
;
19578 cur_proc_ptr
->fpreg_offset
= off
;
19582 cur_proc_ptr
->reg_mask
= mask
;
19583 cur_proc_ptr
->reg_offset
= off
;
19586 demand_empty_rest_of_line ();
19590 /* A table describing all the processors gas knows about. Names are
19591 matched in the order listed.
19593 To ease comparison, please keep this table in the same order as
19594 gcc's mips_cpu_info_table[]. */
19595 static const struct mips_cpu_info mips_cpu_info_table
[] =
19597 /* Entries for generic ISAs */
19598 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19599 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19600 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19601 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19602 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19603 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19604 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19605 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19606 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19609 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19610 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19611 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19614 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19617 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19618 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19619 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19620 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19621 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19622 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19623 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19624 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19625 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19626 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19627 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19628 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19629 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19630 /* ST Microelectronics Loongson 2E and 2F cores */
19631 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19632 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19635 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19636 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19637 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19638 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19639 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19640 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19641 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19642 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19643 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19644 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19645 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19646 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19647 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19648 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19649 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19652 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19653 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19654 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19655 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19657 /* MIPS 32 Release 2 */
19658 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19659 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19660 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19661 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19662 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19663 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19664 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19665 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19666 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19667 ISA_MIPS32R2
, CPU_MIPS32R2
},
19668 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19669 ISA_MIPS32R2
, CPU_MIPS32R2
},
19670 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19671 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19672 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19673 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19674 /* Deprecated forms of the above. */
19675 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19676 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19677 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19678 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19679 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19680 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19681 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19682 /* Deprecated forms of the above. */
19683 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19684 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19685 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19686 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19687 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19688 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19689 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19690 /* Deprecated forms of the above. */
19691 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19692 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19693 /* 34Kn is a 34kc without DSP. */
19694 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19695 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19696 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19697 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19698 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19699 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19700 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19701 /* Deprecated forms of the above. */
19702 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19703 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19704 /* 1004K cores are multiprocessor versions of the 34K. */
19705 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19706 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19707 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19708 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19711 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19712 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19713 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19714 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19716 /* Broadcom SB-1 CPU core */
19717 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19718 /* Broadcom SB-1A CPU core */
19719 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19721 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19723 /* MIPS 64 Release 2 */
19725 /* Cavium Networks Octeon CPU core */
19726 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19727 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19728 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19731 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19734 XLP is mostly like XLR, with the prominent exception that it is
19735 MIPS64R2 rather than MIPS64. */
19736 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19739 { NULL
, 0, 0, 0, 0 }
19743 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19744 with a final "000" replaced by "k". Ignore case.
19746 Note: this function is shared between GCC and GAS. */
19749 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19751 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19752 given
++, canonical
++;
19754 return ((*given
== 0 && *canonical
== 0)
19755 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19759 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19760 CPU name. We've traditionally allowed a lot of variation here.
19762 Note: this function is shared between GCC and GAS. */
19765 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19767 /* First see if the name matches exactly, or with a final "000"
19768 turned into "k". */
19769 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19772 /* If not, try comparing based on numerical designation alone.
19773 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19774 if (TOLOWER (*given
) == 'r')
19776 if (!ISDIGIT (*given
))
19779 /* Skip over some well-known prefixes in the canonical name,
19780 hoping to find a number there too. */
19781 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19783 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19785 else if (TOLOWER (canonical
[0]) == 'r')
19788 return mips_strict_matching_cpu_name_p (canonical
, given
);
19792 /* Parse an option that takes the name of a processor as its argument.
19793 OPTION is the name of the option and CPU_STRING is the argument.
19794 Return the corresponding processor enumeration if the CPU_STRING is
19795 recognized, otherwise report an error and return null.
19797 A similar function exists in GCC. */
19799 static const struct mips_cpu_info
*
19800 mips_parse_cpu (const char *option
, const char *cpu_string
)
19802 const struct mips_cpu_info
*p
;
19804 /* 'from-abi' selects the most compatible architecture for the given
19805 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19806 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19807 version. Look first at the -mgp options, if given, otherwise base
19808 the choice on MIPS_DEFAULT_64BIT.
19810 Treat NO_ABI like the EABIs. One reason to do this is that the
19811 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19812 architecture. This code picks MIPS I for 'mips' and MIPS III for
19813 'mips64', just as we did in the days before 'from-abi'. */
19814 if (strcasecmp (cpu_string
, "from-abi") == 0)
19816 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19817 return mips_cpu_info_from_isa (ISA_MIPS1
);
19819 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19820 return mips_cpu_info_from_isa (ISA_MIPS3
);
19822 if (file_mips_gp32
>= 0)
19823 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19825 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19830 /* 'default' has traditionally been a no-op. Probably not very useful. */
19831 if (strcasecmp (cpu_string
, "default") == 0)
19834 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19835 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19838 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19842 /* Return the canonical processor information for ISA (a member of the
19843 ISA_MIPS* enumeration). */
19845 static const struct mips_cpu_info
*
19846 mips_cpu_info_from_isa (int isa
)
19850 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19851 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19852 && isa
== mips_cpu_info_table
[i
].isa
)
19853 return (&mips_cpu_info_table
[i
]);
19858 static const struct mips_cpu_info
*
19859 mips_cpu_info_from_arch (int arch
)
19863 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19864 if (arch
== mips_cpu_info_table
[i
].cpu
)
19865 return (&mips_cpu_info_table
[i
]);
19871 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19875 fprintf (stream
, "%24s", "");
19880 fprintf (stream
, ", ");
19884 if (*col_p
+ strlen (string
) > 72)
19886 fprintf (stream
, "\n%24s", "");
19890 fprintf (stream
, "%s", string
);
19891 *col_p
+= strlen (string
);
19897 md_show_usage (FILE *stream
)
19902 fprintf (stream
, _("\
19904 -EB generate big endian output\n\
19905 -EL generate little endian output\n\
19906 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19907 -G NUM allow referencing objects up to NUM bytes\n\
19908 implicitly with the gp register [default 8]\n"));
19909 fprintf (stream
, _("\
19910 -mips1 generate MIPS ISA I instructions\n\
19911 -mips2 generate MIPS ISA II instructions\n\
19912 -mips3 generate MIPS ISA III instructions\n\
19913 -mips4 generate MIPS ISA IV instructions\n\
19914 -mips5 generate MIPS ISA V instructions\n\
19915 -mips32 generate MIPS32 ISA instructions\n\
19916 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19917 -mips64 generate MIPS64 ISA instructions\n\
19918 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19919 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19923 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19924 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19925 show (stream
, "from-abi", &column
, &first
);
19926 fputc ('\n', stream
);
19928 fprintf (stream
, _("\
19929 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19930 -no-mCPU don't generate code specific to CPU.\n\
19931 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19935 show (stream
, "3900", &column
, &first
);
19936 show (stream
, "4010", &column
, &first
);
19937 show (stream
, "4100", &column
, &first
);
19938 show (stream
, "4650", &column
, &first
);
19939 fputc ('\n', stream
);
19941 fprintf (stream
, _("\
19942 -mips16 generate mips16 instructions\n\
19943 -no-mips16 do not generate mips16 instructions\n"));
19944 fprintf (stream
, _("\
19945 -mmicromips generate microMIPS instructions\n\
19946 -mno-micromips do not generate microMIPS instructions\n"));
19947 fprintf (stream
, _("\
19948 -msmartmips generate smartmips instructions\n\
19949 -mno-smartmips do not generate smartmips instructions\n"));
19950 fprintf (stream
, _("\
19951 -mdsp generate DSP instructions\n\
19952 -mno-dsp do not generate DSP instructions\n"));
19953 fprintf (stream
, _("\
19954 -mdspr2 generate DSP R2 instructions\n\
19955 -mno-dspr2 do not generate DSP R2 instructions\n"));
19956 fprintf (stream
, _("\
19957 -mmt generate MT instructions\n\
19958 -mno-mt do not generate MT instructions\n"));
19959 fprintf (stream
, _("\
19960 -mmcu generate MCU instructions\n\
19961 -mno-mcu do not generate MCU instructions\n"));
19962 fprintf (stream
, _("\
19963 -mvirt generate Virtualization instructions\n\
19964 -mno-virt do not generate Virtualization instructions\n"));
19965 fprintf (stream
, _("\
19966 -minsn32 only generate 32-bit microMIPS instructions\n\
19967 -mno-insn32 generate all microMIPS instructions\n"));
19968 fprintf (stream
, _("\
19969 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19970 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19971 -mfix-vr4120 work around certain VR4120 errata\n\
19972 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19973 -mfix-24k insert a nop after ERET and DERET instructions\n\
19974 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19975 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19976 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19977 -msym32 assume all symbols have 32-bit values\n\
19978 -O0 remove unneeded NOPs, do not swap branches\n\
19979 -O remove unneeded NOPs and swap branches\n\
19980 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19981 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19982 fprintf (stream
, _("\
19983 -mhard-float allow floating-point instructions\n\
19984 -msoft-float do not allow floating-point instructions\n\
19985 -msingle-float only allow 32-bit floating-point operations\n\
19986 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19987 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19988 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19989 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19993 show (stream
, "legacy", &column
, &first
);
19994 show (stream
, "2008", &column
, &first
);
19996 fputc ('\n', stream
);
19998 fprintf (stream
, _("\
19999 -KPIC, -call_shared generate SVR4 position independent code\n\
20000 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20001 -mvxworks-pic generate VxWorks position independent code\n\
20002 -non_shared do not generate code that can operate with DSOs\n\
20003 -xgot assume a 32 bit GOT\n\
20004 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20005 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20006 position dependent (non shared) code\n\
20007 -mabi=ABI create ABI conformant object file for:\n"));
20011 show (stream
, "32", &column
, &first
);
20012 show (stream
, "o64", &column
, &first
);
20013 show (stream
, "n32", &column
, &first
);
20014 show (stream
, "64", &column
, &first
);
20015 show (stream
, "eabi", &column
, &first
);
20017 fputc ('\n', stream
);
20019 fprintf (stream
, _("\
20020 -32 create o32 ABI object file (default)\n\
20021 -n32 create n32 ABI object file\n\
20022 -64 create 64 ABI object file\n"));
20027 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20029 if (HAVE_64BIT_SYMBOLS
)
20030 return dwarf2_format_64bit_irix
;
20032 return dwarf2_format_32bit
;
20037 mips_dwarf2_addr_size (void)
20039 if (HAVE_64BIT_OBJECTS
)
20045 /* Standard calling conventions leave the CFA at SP on entry. */
20047 mips_cfi_frame_initial_instructions (void)
20049 cfi_add_CFA_def_cfa_register (SP
);
20053 tc_mips_regname_to_dw2regnum (char *regname
)
20055 unsigned int regnum
= -1;
20058 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))