1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_RM7000 \
476 || mips_opts.arch == CPU_VR5500 \
479 /* Whether the processor uses hardware interlocks to protect reads
480 from the GPRs after they are loaded from memory, and thus does not
481 require nops to be inserted. This applies to instructions marked
482 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
484 #define gpr_interlocks \
485 (mips_opts.isa != ISA_MIPS1 \
486 || mips_opts.arch == CPU_R3900)
488 /* Whether the processor uses hardware interlocks to avoid delays
489 required by coprocessor instructions, and thus does not require
490 nops to be inserted. This applies to instructions marked
491 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
492 between instructions marked INSN_WRITE_COND_CODE and ones marked
493 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
494 levels I, II, and III. */
495 /* Itbl support may require additional care here. */
496 #define cop_interlocks \
497 ((mips_opts.isa != ISA_MIPS1 \
498 && mips_opts.isa != ISA_MIPS2 \
499 && mips_opts.isa != ISA_MIPS3) \
500 || mips_opts.arch == CPU_R4300 \
503 /* Whether the processor uses hardware interlocks to protect reads
504 from coprocessor registers after they are loaded from memory, and
505 thus does not require nops to be inserted. This applies to
506 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
507 requires at MIPS ISA level I. */
508 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
510 /* Is this a mfhi or mflo instruction? */
511 #define MF_HILO_INSN(PINFO) \
512 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
514 /* Returns true for a (non floating-point) coprocessor instruction. Reading
515 or writing the condition code is only possible on the coprocessors and
516 these insns are not marked with INSN_COP. Thus for these insns use the
517 condition-code flags. */
518 #define COP_INSN(PINFO) \
519 (PINFO != INSN_MACRO \
520 && ((PINFO) & (FP_S | FP_D)) == 0 \
521 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
523 /* MIPS PIC level. */
525 enum mips_pic_level mips_pic
;
527 /* 1 if we should generate 32 bit offsets from the $gp register in
528 SVR4_PIC mode. Currently has no meaning in other modes. */
529 static int mips_big_got
= 0;
531 /* 1 if trap instructions should used for overflow rather than break
533 static int mips_trap
= 0;
535 /* 1 if double width floating point constants should not be constructed
536 by assembling two single width halves into two single width floating
537 point registers which just happen to alias the double width destination
538 register. On some architectures this aliasing can be disabled by a bit
539 in the status register, and the setting of this bit cannot be determined
540 automatically at assemble time. */
541 static int mips_disable_float_construction
;
543 /* Non-zero if any .set noreorder directives were used. */
545 static int mips_any_noreorder
;
547 /* Non-zero if nops should be inserted when the register referenced in
548 an mfhi/mflo instruction is read in the next two instructions. */
549 static int mips_7000_hilo_fix
;
551 /* The size of objects in the small data section. */
552 static unsigned int g_switch_value
= 8;
553 /* Whether the -G option was used. */
554 static int g_switch_seen
= 0;
559 /* If we can determine in advance that GP optimization won't be
560 possible, we can skip the relaxation stuff that tries to produce
561 GP-relative references. This makes delay slot optimization work
564 This function can only provide a guess, but it seems to work for
565 gcc output. It needs to guess right for gcc, otherwise gcc
566 will put what it thinks is a GP-relative instruction in a branch
569 I don't know if a fix is needed for the SVR4_PIC mode. I've only
570 fixed it for the non-PIC mode. KR 95/04/07 */
571 static int nopic_need_relax (symbolS
*, int);
573 /* handle of the OPCODE hash table */
574 static struct hash_control
*op_hash
= NULL
;
576 /* The opcode hash table we use for the mips16. */
577 static struct hash_control
*mips16_op_hash
= NULL
;
579 /* This array holds the chars that always start a comment. If the
580 pre-processor is disabled, these aren't very useful */
581 const char comment_chars
[] = "#";
583 /* This array holds the chars that only start a comment at the beginning of
584 a line. If the line seems to have the form '# 123 filename'
585 .line and .file directives will appear in the pre-processed output */
586 /* Note that input_file.c hand checks for '#' at the beginning of the
587 first line of the input file. This is because the compiler outputs
588 #NO_APP at the beginning of its output. */
589 /* Also note that C style comments are always supported. */
590 const char line_comment_chars
[] = "#";
592 /* This array holds machine specific line separator characters. */
593 const char line_separator_chars
[] = ";";
595 /* Chars that can be used to separate mant from exp in floating point nums */
596 const char EXP_CHARS
[] = "eE";
598 /* Chars that mean this number is a floating point constant */
601 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
603 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
604 changed in read.c . Ideally it shouldn't have to know about it at all,
605 but nothing is ideal around here.
608 static char *insn_error
;
610 static int auto_align
= 1;
612 /* When outputting SVR4 PIC code, the assembler needs to know the
613 offset in the stack frame from which to restore the $gp register.
614 This is set by the .cprestore pseudo-op, and saved in this
616 static offsetT mips_cprestore_offset
= -1;
618 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
619 more optimizations, it can use a register value instead of a memory-saved
620 offset and even an other register than $gp as global pointer. */
621 static offsetT mips_cpreturn_offset
= -1;
622 static int mips_cpreturn_register
= -1;
623 static int mips_gp_register
= GP
;
624 static int mips_gprel_offset
= 0;
626 /* Whether mips_cprestore_offset has been set in the current function
627 (or whether it has already been warned about, if not). */
628 static int mips_cprestore_valid
= 0;
630 /* This is the register which holds the stack frame, as set by the
631 .frame pseudo-op. This is needed to implement .cprestore. */
632 static int mips_frame_reg
= SP
;
634 /* Whether mips_frame_reg has been set in the current function
635 (or whether it has already been warned about, if not). */
636 static int mips_frame_reg_valid
= 0;
638 /* To output NOP instructions correctly, we need to keep information
639 about the previous two instructions. */
641 /* Whether we are optimizing. The default value of 2 means to remove
642 unneeded NOPs and swap branch instructions when possible. A value
643 of 1 means to not swap branches. A value of 0 means to always
645 static int mips_optimize
= 2;
647 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
648 equivalent to seeing no -g option at all. */
649 static int mips_debug
= 0;
651 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
652 #define MAX_VR4130_NOPS 4
654 /* The maximum number of NOPs needed to fill delay slots. */
655 #define MAX_DELAY_NOPS 2
657 /* The maximum number of NOPs needed for any purpose. */
660 /* A list of previous instructions, with index 0 being the most recent.
661 We need to look back MAX_NOPS instructions when filling delay slots
662 or working around processor errata. We need to look back one
663 instruction further if we're thinking about using history[0] to
664 fill a branch delay slot. */
665 static struct mips_cl_insn history
[1 + MAX_NOPS
];
667 /* Nop instructions used by emit_nop. */
668 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
670 /* The appropriate nop for the current mode. */
671 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
673 /* If this is set, it points to a frag holding nop instructions which
674 were inserted before the start of a noreorder section. If those
675 nops turn out to be unnecessary, the size of the frag can be
677 static fragS
*prev_nop_frag
;
679 /* The number of nop instructions we created in prev_nop_frag. */
680 static int prev_nop_frag_holds
;
682 /* The number of nop instructions that we know we need in
684 static int prev_nop_frag_required
;
686 /* The number of instructions we've seen since prev_nop_frag. */
687 static int prev_nop_frag_since
;
689 /* For ECOFF and ELF, relocations against symbols are done in two
690 parts, with a HI relocation and a LO relocation. Each relocation
691 has only 16 bits of space to store an addend. This means that in
692 order for the linker to handle carries correctly, it must be able
693 to locate both the HI and the LO relocation. This means that the
694 relocations must appear in order in the relocation table.
696 In order to implement this, we keep track of each unmatched HI
697 relocation. We then sort them so that they immediately precede the
698 corresponding LO relocation. */
703 struct mips_hi_fixup
*next
;
706 /* The section this fixup is in. */
710 /* The list of unmatched HI relocs. */
712 static struct mips_hi_fixup
*mips_hi_fixup_list
;
714 /* The frag containing the last explicit relocation operator.
715 Null if explicit relocations have not been used. */
717 static fragS
*prev_reloc_op_frag
;
719 /* Map normal MIPS register numbers to mips16 register numbers. */
721 #define X ILLEGAL_REG
722 static const int mips32_to_16_reg_map
[] =
724 X
, X
, 2, 3, 4, 5, 6, 7,
725 X
, X
, X
, X
, X
, X
, X
, X
,
726 0, 1, X
, X
, X
, X
, X
, X
,
727 X
, X
, X
, X
, X
, X
, X
, X
731 /* Map mips16 register numbers to normal MIPS register numbers. */
733 static const unsigned int mips16_to_32_reg_map
[] =
735 16, 17, 2, 3, 4, 5, 6, 7
738 /* Classifies the kind of instructions we're interested in when
739 implementing -mfix-vr4120. */
740 enum fix_vr4120_class
{
747 NUM_FIX_VR4120_CLASSES
750 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
751 there must be at least one other instruction between an instruction
752 of type X and an instruction of type Y. */
753 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
755 /* True if -mfix-vr4120 is in force. */
756 static int mips_fix_vr4120
;
758 /* ...likewise -mfix-vr4130. */
759 static int mips_fix_vr4130
;
761 /* We don't relax branches by default, since this causes us to expand
762 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
763 fail to compute the offset before expanding the macro to the most
764 efficient expansion. */
766 static int mips_relax_branch
;
768 /* The expansion of many macros depends on the type of symbol that
769 they refer to. For example, when generating position-dependent code,
770 a macro that refers to a symbol may have two different expansions,
771 one which uses GP-relative addresses and one which uses absolute
772 addresses. When generating SVR4-style PIC, a macro may have
773 different expansions for local and global symbols.
775 We handle these situations by generating both sequences and putting
776 them in variant frags. In position-dependent code, the first sequence
777 will be the GP-relative one and the second sequence will be the
778 absolute one. In SVR4 PIC, the first sequence will be for global
779 symbols and the second will be for local symbols.
781 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
782 SECOND are the lengths of the two sequences in bytes. These fields
783 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
784 the subtype has the following flags:
787 Set if it has been decided that we should use the second
788 sequence instead of the first.
791 Set in the first variant frag if the macro's second implementation
792 is longer than its first. This refers to the macro as a whole,
793 not an individual relaxation.
796 Set in the first variant frag if the macro appeared in a .set nomacro
797 block and if one alternative requires a warning but the other does not.
800 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
803 The frag's "opcode" points to the first fixup for relaxable code.
805 Relaxable macros are generated using a sequence such as:
807 relax_start (SYMBOL);
808 ... generate first expansion ...
810 ... generate second expansion ...
813 The code and fixups for the unwanted alternative are discarded
814 by md_convert_frag. */
815 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
817 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
818 #define RELAX_SECOND(X) ((X) & 0xff)
819 #define RELAX_USE_SECOND 0x10000
820 #define RELAX_SECOND_LONGER 0x20000
821 #define RELAX_NOMACRO 0x40000
822 #define RELAX_DELAY_SLOT 0x80000
824 /* Branch without likely bit. If label is out of range, we turn:
826 beq reg1, reg2, label
836 with the following opcode replacements:
843 bltzal <-> bgezal (with jal label instead of j label)
845 Even though keeping the delay slot instruction in the delay slot of
846 the branch would be more efficient, it would be very tricky to do
847 correctly, because we'd have to introduce a variable frag *after*
848 the delay slot instruction, and expand that instead. Let's do it
849 the easy way for now, even if the branch-not-taken case now costs
850 one additional instruction. Out-of-range branches are not supposed
851 to be common, anyway.
853 Branch likely. If label is out of range, we turn:
855 beql reg1, reg2, label
856 delay slot (annulled if branch not taken)
865 delay slot (executed only if branch taken)
868 It would be possible to generate a shorter sequence by losing the
869 likely bit, generating something like:
874 delay slot (executed only if branch taken)
886 bltzall -> bgezal (with jal label instead of j label)
887 bgezall -> bltzal (ditto)
890 but it's not clear that it would actually improve performance. */
891 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
894 | ((toofar) ? 1 : 0) \
896 | ((likely) ? 4 : 0) \
897 | ((uncond) ? 8 : 0)))
898 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
899 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
900 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
901 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
902 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
904 /* For mips16 code, we use an entirely different form of relaxation.
905 mips16 supports two versions of most instructions which take
906 immediate values: a small one which takes some small value, and a
907 larger one which takes a 16 bit value. Since branches also follow
908 this pattern, relaxing these values is required.
910 We can assemble both mips16 and normal MIPS code in a single
911 object. Therefore, we need to support this type of relaxation at
912 the same time that we support the relaxation described above. We
913 use the high bit of the subtype field to distinguish these cases.
915 The information we store for this type of relaxation is the
916 argument code found in the opcode file for this relocation, whether
917 the user explicitly requested a small or extended form, and whether
918 the relocation is in a jump or jal delay slot. That tells us the
919 size of the value, and how it should be stored. We also store
920 whether the fragment is considered to be extended or not. We also
921 store whether this is known to be a branch to a different section,
922 whether we have tried to relax this frag yet, and whether we have
923 ever extended a PC relative fragment because of a shift count. */
924 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
927 | ((small) ? 0x100 : 0) \
928 | ((ext) ? 0x200 : 0) \
929 | ((dslot) ? 0x400 : 0) \
930 | ((jal_dslot) ? 0x800 : 0))
931 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
932 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
933 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
934 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
935 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
936 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
937 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
938 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
939 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
940 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
941 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
942 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
944 /* Is the given value a sign-extended 32-bit value? */
945 #define IS_SEXT_32BIT_NUM(x) \
946 (((x) &~ (offsetT) 0x7fffffff) == 0 \
947 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
949 /* Is the given value a sign-extended 16-bit value? */
950 #define IS_SEXT_16BIT_NUM(x) \
951 (((x) &~ (offsetT) 0x7fff) == 0 \
952 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
954 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
955 #define IS_ZEXT_32BIT_NUM(x) \
956 (((x) &~ (offsetT) 0xffffffff) == 0 \
957 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
959 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
960 VALUE << SHIFT. VALUE is evaluated exactly once. */
961 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
962 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
963 | (((VALUE) & (MASK)) << (SHIFT)))
965 /* Extract bits MASK << SHIFT from STRUCT and shift them right
967 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
968 (((STRUCT) >> (SHIFT)) & (MASK))
970 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
971 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
973 include/opcode/mips.h specifies operand fields using the macros
974 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
975 with "MIPS16OP" instead of "OP". */
976 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
977 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
978 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
979 INSERT_BITS ((INSN).insn_opcode, VALUE, \
980 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
982 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
983 #define EXTRACT_OPERAND(FIELD, INSN) \
984 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
985 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
986 EXTRACT_BITS ((INSN).insn_opcode, \
987 MIPS16OP_MASK_##FIELD, \
990 /* Global variables used when generating relaxable macros. See the
991 comment above RELAX_ENCODE for more details about how relaxation
994 /* 0 if we're not emitting a relaxable macro.
995 1 if we're emitting the first of the two relaxation alternatives.
996 2 if we're emitting the second alternative. */
999 /* The first relaxable fixup in the current frag. (In other words,
1000 the first fixup that refers to relaxable code.) */
1003 /* sizes[0] says how many bytes of the first alternative are stored in
1004 the current frag. Likewise sizes[1] for the second alternative. */
1005 unsigned int sizes
[2];
1007 /* The symbol on which the choice of sequence depends. */
1011 /* Global variables used to decide whether a macro needs a warning. */
1013 /* True if the macro is in a branch delay slot. */
1014 bfd_boolean delay_slot_p
;
1016 /* For relaxable macros, sizes[0] is the length of the first alternative
1017 in bytes and sizes[1] is the length of the second alternative.
1018 For non-relaxable macros, both elements give the length of the
1020 unsigned int sizes
[2];
1022 /* The first variant frag for this macro. */
1024 } mips_macro_warning
;
1026 /* Prototypes for static functions. */
1028 #define internalError() \
1029 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1031 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1033 static void append_insn
1034 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1035 static void mips_no_prev_insn (void);
1036 static void mips16_macro_build
1037 (expressionS
*, const char *, const char *, va_list);
1038 static void load_register (int, expressionS
*, int);
1039 static void macro_start (void);
1040 static void macro_end (void);
1041 static void macro (struct mips_cl_insn
* ip
);
1042 static void mips16_macro (struct mips_cl_insn
* ip
);
1043 #ifdef LOSING_COMPILER
1044 static void macro2 (struct mips_cl_insn
* ip
);
1046 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1047 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1048 static void mips16_immed
1049 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1050 unsigned long *, bfd_boolean
*, unsigned short *);
1051 static size_t my_getSmallExpression
1052 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1053 static void my_getExpression (expressionS
*, char *);
1054 static void s_align (int);
1055 static void s_change_sec (int);
1056 static void s_change_section (int);
1057 static void s_cons (int);
1058 static void s_float_cons (int);
1059 static void s_mips_globl (int);
1060 static void s_option (int);
1061 static void s_mipsset (int);
1062 static void s_abicalls (int);
1063 static void s_cpload (int);
1064 static void s_cpsetup (int);
1065 static void s_cplocal (int);
1066 static void s_cprestore (int);
1067 static void s_cpreturn (int);
1068 static void s_dtprelword (int);
1069 static void s_dtpreldword (int);
1070 static void s_gpvalue (int);
1071 static void s_gpword (int);
1072 static void s_gpdword (int);
1073 static void s_cpadd (int);
1074 static void s_insn (int);
1075 static void md_obj_begin (void);
1076 static void md_obj_end (void);
1077 static void s_mips_ent (int);
1078 static void s_mips_end (int);
1079 static void s_mips_frame (int);
1080 static void s_mips_mask (int reg_type
);
1081 static void s_mips_stab (int);
1082 static void s_mips_weakext (int);
1083 static void s_mips_file (int);
1084 static void s_mips_loc (int);
1085 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1086 static int relaxed_branch_length (fragS
*, asection
*, int);
1087 static int validate_mips_insn (const struct mips_opcode
*);
1089 /* Table and functions used to map between CPU/ISA names, and
1090 ISA levels, and CPU numbers. */
1092 struct mips_cpu_info
1094 const char *name
; /* CPU or ISA name. */
1095 int flags
; /* ASEs available, or ISA flag. */
1096 int isa
; /* ISA level. */
1097 int cpu
; /* CPU number (default CPU if ISA). */
1100 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1101 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1102 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1103 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1104 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1105 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1106 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1108 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1109 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1110 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1114 The following pseudo-ops from the Kane and Heinrich MIPS book
1115 should be defined here, but are currently unsupported: .alias,
1116 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1118 The following pseudo-ops from the Kane and Heinrich MIPS book are
1119 specific to the type of debugging information being generated, and
1120 should be defined by the object format: .aent, .begin, .bend,
1121 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1124 The following pseudo-ops from the Kane and Heinrich MIPS book are
1125 not MIPS CPU specific, but are also not specific to the object file
1126 format. This file is probably the best place to define them, but
1127 they are not currently supported: .asm0, .endr, .lab, .struct. */
1129 static const pseudo_typeS mips_pseudo_table
[] =
1131 /* MIPS specific pseudo-ops. */
1132 {"option", s_option
, 0},
1133 {"set", s_mipsset
, 0},
1134 {"rdata", s_change_sec
, 'r'},
1135 {"sdata", s_change_sec
, 's'},
1136 {"livereg", s_ignore
, 0},
1137 {"abicalls", s_abicalls
, 0},
1138 {"cpload", s_cpload
, 0},
1139 {"cpsetup", s_cpsetup
, 0},
1140 {"cplocal", s_cplocal
, 0},
1141 {"cprestore", s_cprestore
, 0},
1142 {"cpreturn", s_cpreturn
, 0},
1143 {"dtprelword", s_dtprelword
, 0},
1144 {"dtpreldword", s_dtpreldword
, 0},
1145 {"gpvalue", s_gpvalue
, 0},
1146 {"gpword", s_gpword
, 0},
1147 {"gpdword", s_gpdword
, 0},
1148 {"cpadd", s_cpadd
, 0},
1149 {"insn", s_insn
, 0},
1151 /* Relatively generic pseudo-ops that happen to be used on MIPS
1153 {"asciiz", stringer
, 8 + 1},
1154 {"bss", s_change_sec
, 'b'},
1156 {"half", s_cons
, 1},
1157 {"dword", s_cons
, 3},
1158 {"weakext", s_mips_weakext
, 0},
1159 {"origin", s_org
, 0},
1160 {"repeat", s_rept
, 0},
1162 /* These pseudo-ops are defined in read.c, but must be overridden
1163 here for one reason or another. */
1164 {"align", s_align
, 0},
1165 {"byte", s_cons
, 0},
1166 {"data", s_change_sec
, 'd'},
1167 {"double", s_float_cons
, 'd'},
1168 {"float", s_float_cons
, 'f'},
1169 {"globl", s_mips_globl
, 0},
1170 {"global", s_mips_globl
, 0},
1171 {"hword", s_cons
, 1},
1173 {"long", s_cons
, 2},
1174 {"octa", s_cons
, 4},
1175 {"quad", s_cons
, 3},
1176 {"section", s_change_section
, 0},
1177 {"short", s_cons
, 1},
1178 {"single", s_float_cons
, 'f'},
1179 {"stabn", s_mips_stab
, 'n'},
1180 {"text", s_change_sec
, 't'},
1181 {"word", s_cons
, 2},
1183 { "extern", ecoff_directive_extern
, 0},
1188 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1190 /* These pseudo-ops should be defined by the object file format.
1191 However, a.out doesn't support them, so we have versions here. */
1192 {"aent", s_mips_ent
, 1},
1193 {"bgnb", s_ignore
, 0},
1194 {"end", s_mips_end
, 0},
1195 {"endb", s_ignore
, 0},
1196 {"ent", s_mips_ent
, 0},
1197 {"file", s_mips_file
, 0},
1198 {"fmask", s_mips_mask
, 'F'},
1199 {"frame", s_mips_frame
, 0},
1200 {"loc", s_mips_loc
, 0},
1201 {"mask", s_mips_mask
, 'R'},
1202 {"verstamp", s_ignore
, 0},
1206 extern void pop_insert (const pseudo_typeS
*);
1209 mips_pop_insert (void)
1211 pop_insert (mips_pseudo_table
);
1212 if (! ECOFF_DEBUGGING
)
1213 pop_insert (mips_nonecoff_pseudo_table
);
1216 /* Symbols labelling the current insn. */
1218 struct insn_label_list
1220 struct insn_label_list
*next
;
1224 static struct insn_label_list
*free_insn_labels
;
1225 #define label_list tc_segment_info_data.labels
1227 static void mips_clear_insn_labels (void);
1230 mips_clear_insn_labels (void)
1232 register struct insn_label_list
**pl
;
1233 segment_info_type
*si
;
1237 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1240 si
= seg_info (now_seg
);
1241 *pl
= si
->label_list
;
1242 si
->label_list
= NULL
;
1247 static char *expr_end
;
1249 /* Expressions which appear in instructions. These are set by
1252 static expressionS imm_expr
;
1253 static expressionS imm2_expr
;
1254 static expressionS offset_expr
;
1256 /* Relocs associated with imm_expr and offset_expr. */
1258 static bfd_reloc_code_real_type imm_reloc
[3]
1259 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1260 static bfd_reloc_code_real_type offset_reloc
[3]
1261 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1263 /* These are set by mips16_ip if an explicit extension is used. */
1265 static bfd_boolean mips16_small
, mips16_ext
;
1268 /* The pdr segment for per procedure frame/regmask info. Not used for
1271 static segT pdr_seg
;
1274 /* The default target format to use. */
1277 mips_target_format (void)
1279 switch (OUTPUT_FLAVOR
)
1281 case bfd_target_ecoff_flavour
:
1282 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1283 case bfd_target_coff_flavour
:
1285 case bfd_target_elf_flavour
:
1287 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1288 return (target_big_endian
1289 ? "elf32-bigmips-vxworks"
1290 : "elf32-littlemips-vxworks");
1293 /* This is traditional mips. */
1294 return (target_big_endian
1295 ? (HAVE_64BIT_OBJECTS
1296 ? "elf64-tradbigmips"
1298 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1299 : (HAVE_64BIT_OBJECTS
1300 ? "elf64-tradlittlemips"
1302 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1304 return (target_big_endian
1305 ? (HAVE_64BIT_OBJECTS
1308 ? "elf32-nbigmips" : "elf32-bigmips"))
1309 : (HAVE_64BIT_OBJECTS
1310 ? "elf64-littlemips"
1312 ? "elf32-nlittlemips" : "elf32-littlemips")));
1320 /* Return the length of instruction INSN. */
1322 static inline unsigned int
1323 insn_length (const struct mips_cl_insn
*insn
)
1325 if (!mips_opts
.mips16
)
1327 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1330 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1333 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1338 insn
->use_extend
= FALSE
;
1340 insn
->insn_opcode
= mo
->match
;
1343 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1344 insn
->fixp
[i
] = NULL
;
1345 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1346 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1347 insn
->mips16_absolute_jump_p
= 0;
1350 /* Record the current MIPS16 mode in now_seg. */
1353 mips_record_mips16_mode (void)
1355 segment_info_type
*si
;
1357 si
= seg_info (now_seg
);
1358 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1359 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1362 /* Install INSN at the location specified by its "frag" and "where" fields. */
1365 install_insn (const struct mips_cl_insn
*insn
)
1367 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1368 if (!mips_opts
.mips16
)
1369 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1370 else if (insn
->mips16_absolute_jump_p
)
1372 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1373 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1377 if (insn
->use_extend
)
1379 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1382 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1384 mips_record_mips16_mode ();
1387 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1388 and install the opcode in the new location. */
1391 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1396 insn
->where
= where
;
1397 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1398 if (insn
->fixp
[i
] != NULL
)
1400 insn
->fixp
[i
]->fx_frag
= frag
;
1401 insn
->fixp
[i
]->fx_where
= where
;
1403 install_insn (insn
);
1406 /* Add INSN to the end of the output. */
1409 add_fixed_insn (struct mips_cl_insn
*insn
)
1411 char *f
= frag_more (insn_length (insn
));
1412 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1415 /* Start a variant frag and move INSN to the start of the variant part,
1416 marking it as fixed. The other arguments are as for frag_var. */
1419 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1420 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1422 frag_grow (max_chars
);
1423 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1425 frag_var (rs_machine_dependent
, max_chars
, var
,
1426 subtype
, symbol
, offset
, NULL
);
1429 /* Insert N copies of INSN into the history buffer, starting at
1430 position FIRST. Neither FIRST nor N need to be clipped. */
1433 insert_into_history (unsigned int first
, unsigned int n
,
1434 const struct mips_cl_insn
*insn
)
1436 if (mips_relax
.sequence
!= 2)
1440 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1442 history
[i
] = history
[i
- n
];
1448 /* Emit a nop instruction, recording it in the history buffer. */
1453 add_fixed_insn (NOP_INSN
);
1454 insert_into_history (0, 1, NOP_INSN
);
1457 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1458 the idea is to make it obvious at a glance that each errata is
1462 init_vr4120_conflicts (void)
1464 #define CONFLICT(FIRST, SECOND) \
1465 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1467 /* Errata 21 - [D]DIV[U] after [D]MACC */
1468 CONFLICT (MACC
, DIV
);
1469 CONFLICT (DMACC
, DIV
);
1471 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1472 CONFLICT (DMULT
, DMULT
);
1473 CONFLICT (DMULT
, DMACC
);
1474 CONFLICT (DMACC
, DMULT
);
1475 CONFLICT (DMACC
, DMACC
);
1477 /* Errata 24 - MT{LO,HI} after [D]MACC */
1478 CONFLICT (MACC
, MTHILO
);
1479 CONFLICT (DMACC
, MTHILO
);
1481 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1482 instruction is executed immediately after a MACC or DMACC
1483 instruction, the result of [either instruction] is incorrect." */
1484 CONFLICT (MACC
, MULT
);
1485 CONFLICT (MACC
, DMULT
);
1486 CONFLICT (DMACC
, MULT
);
1487 CONFLICT (DMACC
, DMULT
);
1489 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1490 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1491 DDIV or DDIVU instruction, the result of the MACC or
1492 DMACC instruction is incorrect.". */
1493 CONFLICT (DMULT
, MACC
);
1494 CONFLICT (DMULT
, DMACC
);
1495 CONFLICT (DIV
, MACC
);
1496 CONFLICT (DIV
, DMACC
);
1506 #define RTYPE_MASK 0x1ff00
1507 #define RTYPE_NUM 0x00100
1508 #define RTYPE_FPU 0x00200
1509 #define RTYPE_FCC 0x00400
1510 #define RTYPE_VEC 0x00800
1511 #define RTYPE_GP 0x01000
1512 #define RTYPE_CP0 0x02000
1513 #define RTYPE_PC 0x04000
1514 #define RTYPE_ACC 0x08000
1515 #define RTYPE_CCC 0x10000
1516 #define RNUM_MASK 0x000ff
1517 #define RWARN 0x80000
1519 #define GENERIC_REGISTER_NUMBERS \
1520 {"$0", RTYPE_NUM | 0}, \
1521 {"$1", RTYPE_NUM | 1}, \
1522 {"$2", RTYPE_NUM | 2}, \
1523 {"$3", RTYPE_NUM | 3}, \
1524 {"$4", RTYPE_NUM | 4}, \
1525 {"$5", RTYPE_NUM | 5}, \
1526 {"$6", RTYPE_NUM | 6}, \
1527 {"$7", RTYPE_NUM | 7}, \
1528 {"$8", RTYPE_NUM | 8}, \
1529 {"$9", RTYPE_NUM | 9}, \
1530 {"$10", RTYPE_NUM | 10}, \
1531 {"$11", RTYPE_NUM | 11}, \
1532 {"$12", RTYPE_NUM | 12}, \
1533 {"$13", RTYPE_NUM | 13}, \
1534 {"$14", RTYPE_NUM | 14}, \
1535 {"$15", RTYPE_NUM | 15}, \
1536 {"$16", RTYPE_NUM | 16}, \
1537 {"$17", RTYPE_NUM | 17}, \
1538 {"$18", RTYPE_NUM | 18}, \
1539 {"$19", RTYPE_NUM | 19}, \
1540 {"$20", RTYPE_NUM | 20}, \
1541 {"$21", RTYPE_NUM | 21}, \
1542 {"$22", RTYPE_NUM | 22}, \
1543 {"$23", RTYPE_NUM | 23}, \
1544 {"$24", RTYPE_NUM | 24}, \
1545 {"$25", RTYPE_NUM | 25}, \
1546 {"$26", RTYPE_NUM | 26}, \
1547 {"$27", RTYPE_NUM | 27}, \
1548 {"$28", RTYPE_NUM | 28}, \
1549 {"$29", RTYPE_NUM | 29}, \
1550 {"$30", RTYPE_NUM | 30}, \
1551 {"$31", RTYPE_NUM | 31}
1553 #define FPU_REGISTER_NAMES \
1554 {"$f0", RTYPE_FPU | 0}, \
1555 {"$f1", RTYPE_FPU | 1}, \
1556 {"$f2", RTYPE_FPU | 2}, \
1557 {"$f3", RTYPE_FPU | 3}, \
1558 {"$f4", RTYPE_FPU | 4}, \
1559 {"$f5", RTYPE_FPU | 5}, \
1560 {"$f6", RTYPE_FPU | 6}, \
1561 {"$f7", RTYPE_FPU | 7}, \
1562 {"$f8", RTYPE_FPU | 8}, \
1563 {"$f9", RTYPE_FPU | 9}, \
1564 {"$f10", RTYPE_FPU | 10}, \
1565 {"$f11", RTYPE_FPU | 11}, \
1566 {"$f12", RTYPE_FPU | 12}, \
1567 {"$f13", RTYPE_FPU | 13}, \
1568 {"$f14", RTYPE_FPU | 14}, \
1569 {"$f15", RTYPE_FPU | 15}, \
1570 {"$f16", RTYPE_FPU | 16}, \
1571 {"$f17", RTYPE_FPU | 17}, \
1572 {"$f18", RTYPE_FPU | 18}, \
1573 {"$f19", RTYPE_FPU | 19}, \
1574 {"$f20", RTYPE_FPU | 20}, \
1575 {"$f21", RTYPE_FPU | 21}, \
1576 {"$f22", RTYPE_FPU | 22}, \
1577 {"$f23", RTYPE_FPU | 23}, \
1578 {"$f24", RTYPE_FPU | 24}, \
1579 {"$f25", RTYPE_FPU | 25}, \
1580 {"$f26", RTYPE_FPU | 26}, \
1581 {"$f27", RTYPE_FPU | 27}, \
1582 {"$f28", RTYPE_FPU | 28}, \
1583 {"$f29", RTYPE_FPU | 29}, \
1584 {"$f30", RTYPE_FPU | 30}, \
1585 {"$f31", RTYPE_FPU | 31}
1587 #define FPU_CONDITION_CODE_NAMES \
1588 {"$fcc0", RTYPE_FCC | 0}, \
1589 {"$fcc1", RTYPE_FCC | 1}, \
1590 {"$fcc2", RTYPE_FCC | 2}, \
1591 {"$fcc3", RTYPE_FCC | 3}, \
1592 {"$fcc4", RTYPE_FCC | 4}, \
1593 {"$fcc5", RTYPE_FCC | 5}, \
1594 {"$fcc6", RTYPE_FCC | 6}, \
1595 {"$fcc7", RTYPE_FCC | 7}
1597 #define COPROC_CONDITION_CODE_NAMES \
1598 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1599 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1600 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1601 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1602 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1603 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1604 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1605 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1607 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1608 {"$a4", RTYPE_GP | 8}, \
1609 {"$a5", RTYPE_GP | 9}, \
1610 {"$a6", RTYPE_GP | 10}, \
1611 {"$a7", RTYPE_GP | 11}, \
1612 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1613 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1614 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1615 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1616 {"$t0", RTYPE_GP | 12}, \
1617 {"$t1", RTYPE_GP | 13}, \
1618 {"$t2", RTYPE_GP | 14}, \
1619 {"$t3", RTYPE_GP | 15}
1621 #define O32_SYMBOLIC_REGISTER_NAMES \
1622 {"$t0", RTYPE_GP | 8}, \
1623 {"$t1", RTYPE_GP | 9}, \
1624 {"$t2", RTYPE_GP | 10}, \
1625 {"$t3", RTYPE_GP | 11}, \
1626 {"$t4", RTYPE_GP | 12}, \
1627 {"$t5", RTYPE_GP | 13}, \
1628 {"$t6", RTYPE_GP | 14}, \
1629 {"$t7", RTYPE_GP | 15}, \
1630 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1631 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1632 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1633 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1635 /* Remaining symbolic register names */
1636 #define SYMBOLIC_REGISTER_NAMES \
1637 {"$zero", RTYPE_GP | 0}, \
1638 {"$at", RTYPE_GP | 1}, \
1639 {"$AT", RTYPE_GP | 1}, \
1640 {"$v0", RTYPE_GP | 2}, \
1641 {"$v1", RTYPE_GP | 3}, \
1642 {"$a0", RTYPE_GP | 4}, \
1643 {"$a1", RTYPE_GP | 5}, \
1644 {"$a2", RTYPE_GP | 6}, \
1645 {"$a3", RTYPE_GP | 7}, \
1646 {"$s0", RTYPE_GP | 16}, \
1647 {"$s1", RTYPE_GP | 17}, \
1648 {"$s2", RTYPE_GP | 18}, \
1649 {"$s3", RTYPE_GP | 19}, \
1650 {"$s4", RTYPE_GP | 20}, \
1651 {"$s5", RTYPE_GP | 21}, \
1652 {"$s6", RTYPE_GP | 22}, \
1653 {"$s7", RTYPE_GP | 23}, \
1654 {"$t8", RTYPE_GP | 24}, \
1655 {"$t9", RTYPE_GP | 25}, \
1656 {"$k0", RTYPE_GP | 26}, \
1657 {"$kt0", RTYPE_GP | 26}, \
1658 {"$k1", RTYPE_GP | 27}, \
1659 {"$kt1", RTYPE_GP | 27}, \
1660 {"$gp", RTYPE_GP | 28}, \
1661 {"$sp", RTYPE_GP | 29}, \
1662 {"$s8", RTYPE_GP | 30}, \
1663 {"$fp", RTYPE_GP | 30}, \
1664 {"$ra", RTYPE_GP | 31}
1666 #define MIPS16_SPECIAL_REGISTER_NAMES \
1667 {"$pc", RTYPE_PC | 0}
1669 #define MDMX_VECTOR_REGISTER_NAMES \
1670 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1671 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1672 {"$v2", RTYPE_VEC | 2}, \
1673 {"$v3", RTYPE_VEC | 3}, \
1674 {"$v4", RTYPE_VEC | 4}, \
1675 {"$v5", RTYPE_VEC | 5}, \
1676 {"$v6", RTYPE_VEC | 6}, \
1677 {"$v7", RTYPE_VEC | 7}, \
1678 {"$v8", RTYPE_VEC | 8}, \
1679 {"$v9", RTYPE_VEC | 9}, \
1680 {"$v10", RTYPE_VEC | 10}, \
1681 {"$v11", RTYPE_VEC | 11}, \
1682 {"$v12", RTYPE_VEC | 12}, \
1683 {"$v13", RTYPE_VEC | 13}, \
1684 {"$v14", RTYPE_VEC | 14}, \
1685 {"$v15", RTYPE_VEC | 15}, \
1686 {"$v16", RTYPE_VEC | 16}, \
1687 {"$v17", RTYPE_VEC | 17}, \
1688 {"$v18", RTYPE_VEC | 18}, \
1689 {"$v19", RTYPE_VEC | 19}, \
1690 {"$v20", RTYPE_VEC | 20}, \
1691 {"$v21", RTYPE_VEC | 21}, \
1692 {"$v22", RTYPE_VEC | 22}, \
1693 {"$v23", RTYPE_VEC | 23}, \
1694 {"$v24", RTYPE_VEC | 24}, \
1695 {"$v25", RTYPE_VEC | 25}, \
1696 {"$v26", RTYPE_VEC | 26}, \
1697 {"$v27", RTYPE_VEC | 27}, \
1698 {"$v28", RTYPE_VEC | 28}, \
1699 {"$v29", RTYPE_VEC | 29}, \
1700 {"$v30", RTYPE_VEC | 30}, \
1701 {"$v31", RTYPE_VEC | 31}
1703 #define MIPS_DSP_ACCUMULATOR_NAMES \
1704 {"$ac0", RTYPE_ACC | 0}, \
1705 {"$ac1", RTYPE_ACC | 1}, \
1706 {"$ac2", RTYPE_ACC | 2}, \
1707 {"$ac3", RTYPE_ACC | 3}
1709 static const struct regname reg_names
[] = {
1710 GENERIC_REGISTER_NUMBERS
,
1712 FPU_CONDITION_CODE_NAMES
,
1713 COPROC_CONDITION_CODE_NAMES
,
1715 /* The $txx registers depends on the abi,
1716 these will be added later into the symbol table from
1717 one of the tables below once mips_abi is set after
1718 parsing of arguments from the command line. */
1719 SYMBOLIC_REGISTER_NAMES
,
1721 MIPS16_SPECIAL_REGISTER_NAMES
,
1722 MDMX_VECTOR_REGISTER_NAMES
,
1723 MIPS_DSP_ACCUMULATOR_NAMES
,
1727 static const struct regname reg_names_o32
[] = {
1728 O32_SYMBOLIC_REGISTER_NAMES
,
1732 static const struct regname reg_names_n32n64
[] = {
1733 N32N64_SYMBOLIC_REGISTER_NAMES
,
1738 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1745 /* Find end of name. */
1747 if (is_name_beginner (*e
))
1749 while (is_part_of_name (*e
))
1752 /* Terminate name. */
1756 /* Look for a register symbol. */
1757 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1759 int r
= S_GET_VALUE (symbolP
);
1761 reg
= r
& RNUM_MASK
;
1762 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1763 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1764 reg
= (r
& RNUM_MASK
) - 2;
1766 /* Else see if this is a register defined in an itbl entry. */
1767 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1774 if (itbl_get_reg_val (n
, &r
))
1775 reg
= r
& RNUM_MASK
;
1778 /* Advance to next token if a register was recognised. */
1781 else if (types
& RWARN
)
1782 as_warn ("Unrecognized register name `%s'", *s
);
1790 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1791 architecture. If EXPANSIONP is TRUE then this check is done while
1792 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1795 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1797 int isa
= mips_opts
.isa
;
1800 if (mips_opts
.ase_mdmx
)
1802 if (mips_opts
.ase_dsp
)
1804 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1806 if (mips_opts
.ase_dspr2
)
1808 if (mips_opts
.ase_mt
)
1810 if (mips_opts
.ase_mips3d
)
1812 if (mips_opts
.ase_smartmips
)
1813 isa
|= INSN_SMARTMIPS
;
1815 /* For user code we don't check for mips_opts.mips16 since we want
1816 to allow jalx if -mips16 was specified on the command line. */
1817 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1820 /* Don't accept instructions based on the ISA if the CPU does not implement
1821 all the coprocessor insns. */
1822 if (NO_ISA_COP (mips_opts
.arch
)
1823 && COP_INSN (mo
->pinfo
))
1826 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1829 /* Check whether the instruction or macro requires single-precision or
1830 double-precision floating-point support. Note that this information is
1831 stored differently in the opcode table for insns and macros. */
1832 if (mo
->pinfo
== INSN_MACRO
)
1834 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1835 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1839 fp_s
= mo
->pinfo
& FP_S
;
1840 fp_d
= mo
->pinfo
& FP_D
;
1843 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1846 if (fp_s
&& mips_opts
.soft_float
)
1852 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1853 selected ISA and architecture. */
1856 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1858 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1861 /* This function is called once, at assembler startup time. It should set up
1862 all the tables, etc. that the MD part of the assembler will need. */
1867 const char *retval
= NULL
;
1871 if (mips_pic
!= NO_PIC
)
1873 if (g_switch_seen
&& g_switch_value
!= 0)
1874 as_bad (_("-G may not be used in position-independent code"));
1878 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1879 as_warn (_("Could not set architecture and machine"));
1881 op_hash
= hash_new ();
1883 for (i
= 0; i
< NUMOPCODES
;)
1885 const char *name
= mips_opcodes
[i
].name
;
1887 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1890 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1891 mips_opcodes
[i
].name
, retval
);
1892 /* Probably a memory allocation problem? Give up now. */
1893 as_fatal (_("Broken assembler. No assembly attempted."));
1897 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1899 if (!validate_mips_insn (&mips_opcodes
[i
]))
1901 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1903 create_insn (&nop_insn
, mips_opcodes
+ i
);
1904 nop_insn
.fixed_p
= 1;
1909 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1912 mips16_op_hash
= hash_new ();
1915 while (i
< bfd_mips16_num_opcodes
)
1917 const char *name
= mips16_opcodes
[i
].name
;
1919 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1921 as_fatal (_("internal: can't hash `%s': %s"),
1922 mips16_opcodes
[i
].name
, retval
);
1925 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1926 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1927 != mips16_opcodes
[i
].match
))
1929 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1930 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1933 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1935 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1936 mips16_nop_insn
.fixed_p
= 1;
1940 while (i
< bfd_mips16_num_opcodes
1941 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1945 as_fatal (_("Broken assembler. No assembly attempted."));
1947 /* We add all the general register names to the symbol table. This
1948 helps us detect invalid uses of them. */
1949 for (i
= 0; reg_names
[i
].name
; i
++)
1950 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1951 reg_names
[i
].num
, /* & RNUM_MASK, */
1952 &zero_address_frag
));
1954 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1955 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1956 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1957 &zero_address_frag
));
1959 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1960 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1961 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1962 &zero_address_frag
));
1964 mips_no_prev_insn ();
1967 mips_cprmask
[0] = 0;
1968 mips_cprmask
[1] = 0;
1969 mips_cprmask
[2] = 0;
1970 mips_cprmask
[3] = 0;
1972 /* set the default alignment for the text section (2**2) */
1973 record_alignment (text_section
, 2);
1975 bfd_set_gp_size (stdoutput
, g_switch_value
);
1980 /* On a native system other than VxWorks, sections must be aligned
1981 to 16 byte boundaries. When configured for an embedded ELF
1982 target, we don't bother. */
1983 if (strncmp (TARGET_OS
, "elf", 3) != 0
1984 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1986 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1987 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1988 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1991 /* Create a .reginfo section for register masks and a .mdebug
1992 section for debugging information. */
2000 subseg
= now_subseg
;
2002 /* The ABI says this section should be loaded so that the
2003 running program can access it. However, we don't load it
2004 if we are configured for an embedded target */
2005 flags
= SEC_READONLY
| SEC_DATA
;
2006 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2007 flags
|= SEC_ALLOC
| SEC_LOAD
;
2009 if (mips_abi
!= N64_ABI
)
2011 sec
= subseg_new (".reginfo", (subsegT
) 0);
2013 bfd_set_section_flags (stdoutput
, sec
, flags
);
2014 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2016 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2020 /* The 64-bit ABI uses a .MIPS.options section rather than
2021 .reginfo section. */
2022 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2023 bfd_set_section_flags (stdoutput
, sec
, flags
);
2024 bfd_set_section_alignment (stdoutput
, sec
, 3);
2026 /* Set up the option header. */
2028 Elf_Internal_Options opthdr
;
2031 opthdr
.kind
= ODK_REGINFO
;
2032 opthdr
.size
= (sizeof (Elf_External_Options
)
2033 + sizeof (Elf64_External_RegInfo
));
2036 f
= frag_more (sizeof (Elf_External_Options
));
2037 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2038 (Elf_External_Options
*) f
);
2040 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2044 if (ECOFF_DEBUGGING
)
2046 sec
= subseg_new (".mdebug", (subsegT
) 0);
2047 (void) bfd_set_section_flags (stdoutput
, sec
,
2048 SEC_HAS_CONTENTS
| SEC_READONLY
);
2049 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2051 else if (mips_flag_pdr
)
2053 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2054 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2055 SEC_READONLY
| SEC_RELOC
2057 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2060 subseg_set (seg
, subseg
);
2063 #endif /* OBJ_ELF */
2065 if (! ECOFF_DEBUGGING
)
2068 if (mips_fix_vr4120
)
2069 init_vr4120_conflicts ();
2075 if (! ECOFF_DEBUGGING
)
2080 md_assemble (char *str
)
2082 struct mips_cl_insn insn
;
2083 bfd_reloc_code_real_type unused_reloc
[3]
2084 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2086 imm_expr
.X_op
= O_absent
;
2087 imm2_expr
.X_op
= O_absent
;
2088 offset_expr
.X_op
= O_absent
;
2089 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2090 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2091 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2092 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2093 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2094 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2096 if (mips_opts
.mips16
)
2097 mips16_ip (str
, &insn
);
2100 mips_ip (str
, &insn
);
2101 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2102 str
, insn
.insn_opcode
));
2107 as_bad ("%s `%s'", insn_error
, str
);
2111 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2114 if (mips_opts
.mips16
)
2115 mips16_macro (&insn
);
2122 if (imm_expr
.X_op
!= O_absent
)
2123 append_insn (&insn
, &imm_expr
, imm_reloc
);
2124 else if (offset_expr
.X_op
!= O_absent
)
2125 append_insn (&insn
, &offset_expr
, offset_reloc
);
2127 append_insn (&insn
, NULL
, unused_reloc
);
2131 /* Convenience functions for abstracting away the differences between
2132 MIPS16 and non-MIPS16 relocations. */
2134 static inline bfd_boolean
2135 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2139 case BFD_RELOC_MIPS16_JMP
:
2140 case BFD_RELOC_MIPS16_GPREL
:
2141 case BFD_RELOC_MIPS16_GOT16
:
2142 case BFD_RELOC_MIPS16_CALL16
:
2143 case BFD_RELOC_MIPS16_HI16_S
:
2144 case BFD_RELOC_MIPS16_HI16
:
2145 case BFD_RELOC_MIPS16_LO16
:
2153 static inline bfd_boolean
2154 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2156 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2159 static inline bfd_boolean
2160 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2162 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2165 static inline bfd_boolean
2166 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2168 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2171 /* Return true if the given relocation might need a matching %lo().
2172 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2173 need a matching %lo() when applied to local symbols. */
2175 static inline bfd_boolean
2176 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2178 return (HAVE_IN_PLACE_ADDENDS
2179 && (hi16_reloc_p (reloc
)
2180 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2181 all GOT16 relocations evaluate to "G". */
2182 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2185 /* Return the type of %lo() reloc needed by RELOC, given that
2186 reloc_needs_lo_p. */
2188 static inline bfd_reloc_code_real_type
2189 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2191 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2194 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2197 static inline bfd_boolean
2198 fixup_has_matching_lo_p (fixS
*fixp
)
2200 return (fixp
->fx_next
!= NULL
2201 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2202 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2203 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2206 /* See whether instruction IP reads register REG. CLASS is the type
2210 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2211 enum mips_regclass
class)
2213 if (class == MIPS16_REG
)
2215 assert (mips_opts
.mips16
);
2216 reg
= mips16_to_32_reg_map
[reg
];
2217 class = MIPS_GR_REG
;
2220 /* Don't report on general register ZERO, since it never changes. */
2221 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2224 if (class == MIPS_FP_REG
)
2226 assert (! mips_opts
.mips16
);
2227 /* If we are called with either $f0 or $f1, we must check $f0.
2228 This is not optimal, because it will introduce an unnecessary
2229 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2230 need to distinguish reading both $f0 and $f1 or just one of
2231 them. Note that we don't have to check the other way,
2232 because there is no instruction that sets both $f0 and $f1
2233 and requires a delay. */
2234 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2235 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2236 == (reg
&~ (unsigned) 1)))
2238 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2239 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2240 == (reg
&~ (unsigned) 1)))
2243 else if (! mips_opts
.mips16
)
2245 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2246 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2248 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2249 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2254 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2255 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2257 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2258 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2260 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2261 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2264 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2266 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2268 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2270 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2271 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2278 /* This function returns true if modifying a register requires a
2282 reg_needs_delay (unsigned int reg
)
2284 unsigned long prev_pinfo
;
2286 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2287 if (! mips_opts
.noreorder
2288 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2289 && ! gpr_interlocks
)
2290 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2291 && ! cop_interlocks
)))
2293 /* A load from a coprocessor or from memory. All load delays
2294 delay the use of general register rt for one instruction. */
2295 /* Itbl support may require additional care here. */
2296 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2297 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2304 /* Move all labels in insn_labels to the current insertion point. */
2307 mips_move_labels (void)
2309 segment_info_type
*si
= seg_info (now_seg
);
2310 struct insn_label_list
*l
;
2313 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2315 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2316 symbol_set_frag (l
->label
, frag_now
);
2317 val
= (valueT
) frag_now_fix ();
2318 /* mips16 text labels are stored as odd. */
2319 if (mips_opts
.mips16
)
2321 S_SET_VALUE (l
->label
, val
);
2326 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2328 bfd_boolean linkonce
= FALSE
;
2329 segT symseg
= S_GET_SEGMENT (sym
);
2331 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2333 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2336 /* The GNU toolchain uses an extension for ELF: a section
2337 beginning with the magic string .gnu.linkonce is a
2338 linkonce section. */
2339 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2340 sizeof ".gnu.linkonce" - 1) == 0)
2347 /* Mark instruction labels in mips16 mode. This permits the linker to
2348 handle them specially, such as generating jalx instructions when
2349 needed. We also make them odd for the duration of the assembly, in
2350 order to generate the right sort of code. We will make them even
2351 in the adjust_symtab routine, while leaving them marked. This is
2352 convenient for the debugger and the disassembler. The linker knows
2353 to make them odd again. */
2356 mips16_mark_labels (void)
2358 segment_info_type
*si
= seg_info (now_seg
);
2359 struct insn_label_list
*l
;
2361 if (!mips_opts
.mips16
)
2364 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2366 symbolS
*label
= l
->label
;
2368 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2370 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2372 if ((S_GET_VALUE (label
) & 1) == 0
2373 /* Don't adjust the address if the label is global or weak, or
2374 in a link-once section, since we'll be emitting symbol reloc
2375 references to it which will be patched up by the linker, and
2376 the final value of the symbol may or may not be MIPS16. */
2377 && ! S_IS_WEAK (label
)
2378 && ! S_IS_EXTERNAL (label
)
2379 && ! s_is_linkonce (label
, now_seg
))
2380 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2384 /* End the current frag. Make it a variant frag and record the
2388 relax_close_frag (void)
2390 mips_macro_warning
.first_frag
= frag_now
;
2391 frag_var (rs_machine_dependent
, 0, 0,
2392 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2393 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2395 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2396 mips_relax
.first_fixup
= 0;
2399 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2400 See the comment above RELAX_ENCODE for more details. */
2403 relax_start (symbolS
*symbol
)
2405 assert (mips_relax
.sequence
== 0);
2406 mips_relax
.sequence
= 1;
2407 mips_relax
.symbol
= symbol
;
2410 /* Start generating the second version of a relaxable sequence.
2411 See the comment above RELAX_ENCODE for more details. */
2416 assert (mips_relax
.sequence
== 1);
2417 mips_relax
.sequence
= 2;
2420 /* End the current relaxable sequence. */
2425 assert (mips_relax
.sequence
== 2);
2426 relax_close_frag ();
2427 mips_relax
.sequence
= 0;
2430 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2431 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2432 by VR4120 errata. */
2435 classify_vr4120_insn (const char *name
)
2437 if (strncmp (name
, "macc", 4) == 0)
2438 return FIX_VR4120_MACC
;
2439 if (strncmp (name
, "dmacc", 5) == 0)
2440 return FIX_VR4120_DMACC
;
2441 if (strncmp (name
, "mult", 4) == 0)
2442 return FIX_VR4120_MULT
;
2443 if (strncmp (name
, "dmult", 5) == 0)
2444 return FIX_VR4120_DMULT
;
2445 if (strstr (name
, "div"))
2446 return FIX_VR4120_DIV
;
2447 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2448 return FIX_VR4120_MTHILO
;
2449 return NUM_FIX_VR4120_CLASSES
;
2452 /* Return the number of instructions that must separate INSN1 and INSN2,
2453 where INSN1 is the earlier instruction. Return the worst-case value
2454 for any INSN2 if INSN2 is null. */
2457 insns_between (const struct mips_cl_insn
*insn1
,
2458 const struct mips_cl_insn
*insn2
)
2460 unsigned long pinfo1
, pinfo2
;
2462 /* This function needs to know which pinfo flags are set for INSN2
2463 and which registers INSN2 uses. The former is stored in PINFO2 and
2464 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2465 will have every flag set and INSN2_USES_REG will always return true. */
2466 pinfo1
= insn1
->insn_mo
->pinfo
;
2467 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2469 #define INSN2_USES_REG(REG, CLASS) \
2470 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2472 /* For most targets, write-after-read dependencies on the HI and LO
2473 registers must be separated by at least two instructions. */
2474 if (!hilo_interlocks
)
2476 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2478 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2482 /* If we're working around r7000 errata, there must be two instructions
2483 between an mfhi or mflo and any instruction that uses the result. */
2484 if (mips_7000_hilo_fix
2485 && MF_HILO_INSN (pinfo1
)
2486 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2489 /* If working around VR4120 errata, check for combinations that need
2490 a single intervening instruction. */
2491 if (mips_fix_vr4120
)
2493 unsigned int class1
, class2
;
2495 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2496 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2500 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2501 if (vr4120_conflicts
[class1
] & (1 << class2
))
2506 if (!mips_opts
.mips16
)
2508 /* Check for GPR or coprocessor load delays. All such delays
2509 are on the RT register. */
2510 /* Itbl support may require additional care here. */
2511 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2512 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2514 know (pinfo1
& INSN_WRITE_GPR_T
);
2515 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2519 /* Check for generic coprocessor hazards.
2521 This case is not handled very well. There is no special
2522 knowledge of CP0 handling, and the coprocessors other than
2523 the floating point unit are not distinguished at all. */
2524 /* Itbl support may require additional care here. FIXME!
2525 Need to modify this to include knowledge about
2526 user specified delays! */
2527 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2528 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2530 /* Handle cases where INSN1 writes to a known general coprocessor
2531 register. There must be a one instruction delay before INSN2
2532 if INSN2 reads that register, otherwise no delay is needed. */
2533 if (pinfo1
& INSN_WRITE_FPR_T
)
2535 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2538 else if (pinfo1
& INSN_WRITE_FPR_S
)
2540 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2545 /* Read-after-write dependencies on the control registers
2546 require a two-instruction gap. */
2547 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2548 && (pinfo2
& INSN_READ_COND_CODE
))
2551 /* We don't know exactly what INSN1 does. If INSN2 is
2552 also a coprocessor instruction, assume there must be
2553 a one instruction gap. */
2554 if (pinfo2
& INSN_COP
)
2559 /* Check for read-after-write dependencies on the coprocessor
2560 control registers in cases where INSN1 does not need a general
2561 coprocessor delay. This means that INSN1 is a floating point
2562 comparison instruction. */
2563 /* Itbl support may require additional care here. */
2564 else if (!cop_interlocks
2565 && (pinfo1
& INSN_WRITE_COND_CODE
)
2566 && (pinfo2
& INSN_READ_COND_CODE
))
2570 #undef INSN2_USES_REG
2575 /* Return the number of nops that would be needed to work around the
2576 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2577 the MAX_VR4130_NOPS instructions described by HISTORY. */
2580 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2581 const struct mips_cl_insn
*insn
)
2585 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2586 are not affected by the errata. */
2588 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2589 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2590 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2593 /* Search for the first MFLO or MFHI. */
2594 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2595 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2597 /* Extract the destination register. */
2598 if (mips_opts
.mips16
)
2599 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2601 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2603 /* No nops are needed if INSN reads that register. */
2604 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2607 /* ...or if any of the intervening instructions do. */
2608 for (j
= 0; j
< i
; j
++)
2609 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2612 return MAX_VR4130_NOPS
- i
;
2617 /* Return the number of nops that would be needed if instruction INSN
2618 immediately followed the MAX_NOPS instructions given by HISTORY,
2619 where HISTORY[0] is the most recent instruction. If INSN is null,
2620 return the worse-case number of nops for any instruction. */
2623 nops_for_insn (const struct mips_cl_insn
*history
,
2624 const struct mips_cl_insn
*insn
)
2626 int i
, nops
, tmp_nops
;
2629 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2630 if (!history
[i
].noreorder_p
)
2632 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2633 if (tmp_nops
> nops
)
2637 if (mips_fix_vr4130
)
2639 tmp_nops
= nops_for_vr4130 (history
, insn
);
2640 if (tmp_nops
> nops
)
2647 /* The variable arguments provide NUM_INSNS extra instructions that
2648 might be added to HISTORY. Return the largest number of nops that
2649 would be needed after the extended sequence. */
2652 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2655 struct mips_cl_insn buffer
[MAX_NOPS
];
2656 struct mips_cl_insn
*cursor
;
2659 va_start (args
, history
);
2660 cursor
= buffer
+ num_insns
;
2661 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2662 while (cursor
> buffer
)
2663 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2665 nops
= nops_for_insn (buffer
, NULL
);
2670 /* Like nops_for_insn, but if INSN is a branch, take into account the
2671 worst-case delay for the branch target. */
2674 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2675 const struct mips_cl_insn
*insn
)
2679 nops
= nops_for_insn (history
, insn
);
2680 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2681 | INSN_COND_BRANCH_DELAY
2682 | INSN_COND_BRANCH_LIKELY
))
2684 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2685 if (tmp_nops
> nops
)
2688 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2690 tmp_nops
= nops_for_sequence (1, history
, insn
);
2691 if (tmp_nops
> nops
)
2697 /* Output an instruction. IP is the instruction information.
2698 ADDRESS_EXPR is an operand of the instruction to be used with
2702 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2703 bfd_reloc_code_real_type
*reloc_type
)
2705 unsigned long prev_pinfo
, pinfo
;
2706 relax_stateT prev_insn_frag_type
= 0;
2707 bfd_boolean relaxed_branch
= FALSE
;
2708 segment_info_type
*si
= seg_info (now_seg
);
2710 /* Mark instruction labels in mips16 mode. */
2711 mips16_mark_labels ();
2713 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2714 pinfo
= ip
->insn_mo
->pinfo
;
2716 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2718 /* There are a lot of optimizations we could do that we don't.
2719 In particular, we do not, in general, reorder instructions.
2720 If you use gcc with optimization, it will reorder
2721 instructions and generally do much more optimization then we
2722 do here; repeating all that work in the assembler would only
2723 benefit hand written assembly code, and does not seem worth
2725 int nops
= (mips_optimize
== 0
2726 ? nops_for_insn (history
, NULL
)
2727 : nops_for_insn_or_target (history
, ip
));
2731 unsigned long old_frag_offset
;
2734 old_frag
= frag_now
;
2735 old_frag_offset
= frag_now_fix ();
2737 for (i
= 0; i
< nops
; i
++)
2742 listing_prev_line ();
2743 /* We may be at the start of a variant frag. In case we
2744 are, make sure there is enough space for the frag
2745 after the frags created by listing_prev_line. The
2746 argument to frag_grow here must be at least as large
2747 as the argument to all other calls to frag_grow in
2748 this file. We don't have to worry about being in the
2749 middle of a variant frag, because the variants insert
2750 all needed nop instructions themselves. */
2754 mips_move_labels ();
2756 #ifndef NO_ECOFF_DEBUGGING
2757 if (ECOFF_DEBUGGING
)
2758 ecoff_fix_loc (old_frag
, old_frag_offset
);
2762 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2764 /* Work out how many nops in prev_nop_frag are needed by IP. */
2765 int nops
= nops_for_insn_or_target (history
, ip
);
2766 assert (nops
<= prev_nop_frag_holds
);
2768 /* Enforce NOPS as a minimum. */
2769 if (nops
> prev_nop_frag_required
)
2770 prev_nop_frag_required
= nops
;
2772 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2774 /* Settle for the current number of nops. Update the history
2775 accordingly (for the benefit of any future .set reorder code). */
2776 prev_nop_frag
= NULL
;
2777 insert_into_history (prev_nop_frag_since
,
2778 prev_nop_frag_holds
, NOP_INSN
);
2782 /* Allow this instruction to replace one of the nops that was
2783 tentatively added to prev_nop_frag. */
2784 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2785 prev_nop_frag_holds
--;
2786 prev_nop_frag_since
++;
2791 /* The value passed to dwarf2_emit_insn is the distance between
2792 the beginning of the current instruction and the address that
2793 should be recorded in the debug tables. For MIPS16 debug info
2794 we want to use ISA-encoded addresses, so we pass -1 for an
2795 address higher by one than the current. */
2796 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2799 /* Record the frag type before frag_var. */
2800 if (history
[0].frag
)
2801 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2804 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2805 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2806 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2807 && mips_relax_branch
2808 /* Don't try branch relaxation within .set nomacro, or within
2809 .set noat if we use $at for PIC computations. If it turns
2810 out that the branch was out-of-range, we'll get an error. */
2811 && !mips_opts
.warn_about_macros
2812 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2813 && !mips_opts
.mips16
)
2815 relaxed_branch
= TRUE
;
2816 add_relaxed_insn (ip
, (relaxed_branch_length
2818 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2819 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2822 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2823 pinfo
& INSN_COND_BRANCH_LIKELY
,
2824 pinfo
& INSN_WRITE_GPR_31
,
2826 address_expr
->X_add_symbol
,
2827 address_expr
->X_add_number
);
2828 *reloc_type
= BFD_RELOC_UNUSED
;
2830 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2832 /* We need to set up a variant frag. */
2833 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2834 add_relaxed_insn (ip
, 4, 0,
2836 (*reloc_type
- BFD_RELOC_UNUSED
,
2837 mips16_small
, mips16_ext
,
2838 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2839 history
[0].mips16_absolute_jump_p
),
2840 make_expr_symbol (address_expr
), 0);
2842 else if (mips_opts
.mips16
2844 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2846 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2847 /* Make sure there is enough room to swap this instruction with
2848 a following jump instruction. */
2850 add_fixed_insn (ip
);
2854 if (mips_opts
.mips16
2855 && mips_opts
.noreorder
2856 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2857 as_warn (_("extended instruction in delay slot"));
2859 if (mips_relax
.sequence
)
2861 /* If we've reached the end of this frag, turn it into a variant
2862 frag and record the information for the instructions we've
2864 if (frag_room () < 4)
2865 relax_close_frag ();
2866 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2869 if (mips_relax
.sequence
!= 2)
2870 mips_macro_warning
.sizes
[0] += 4;
2871 if (mips_relax
.sequence
!= 1)
2872 mips_macro_warning
.sizes
[1] += 4;
2874 if (mips_opts
.mips16
)
2877 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2879 add_fixed_insn (ip
);
2882 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2884 if (address_expr
->X_op
== O_constant
)
2888 switch (*reloc_type
)
2891 ip
->insn_opcode
|= address_expr
->X_add_number
;
2894 case BFD_RELOC_MIPS_HIGHEST
:
2895 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2896 ip
->insn_opcode
|= tmp
& 0xffff;
2899 case BFD_RELOC_MIPS_HIGHER
:
2900 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2901 ip
->insn_opcode
|= tmp
& 0xffff;
2904 case BFD_RELOC_HI16_S
:
2905 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2906 ip
->insn_opcode
|= tmp
& 0xffff;
2909 case BFD_RELOC_HI16
:
2910 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2913 case BFD_RELOC_UNUSED
:
2914 case BFD_RELOC_LO16
:
2915 case BFD_RELOC_MIPS_GOT_DISP
:
2916 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2919 case BFD_RELOC_MIPS_JMP
:
2920 if ((address_expr
->X_add_number
& 3) != 0)
2921 as_bad (_("jump to misaligned address (0x%lx)"),
2922 (unsigned long) address_expr
->X_add_number
);
2923 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2926 case BFD_RELOC_MIPS16_JMP
:
2927 if ((address_expr
->X_add_number
& 3) != 0)
2928 as_bad (_("jump to misaligned address (0x%lx)"),
2929 (unsigned long) address_expr
->X_add_number
);
2931 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2932 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2933 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2936 case BFD_RELOC_16_PCREL_S2
:
2937 if ((address_expr
->X_add_number
& 3) != 0)
2938 as_bad (_("branch to misaligned address (0x%lx)"),
2939 (unsigned long) address_expr
->X_add_number
);
2940 if (mips_relax_branch
)
2942 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2943 as_bad (_("branch address range overflow (0x%lx)"),
2944 (unsigned long) address_expr
->X_add_number
);
2945 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2952 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2955 reloc_howto_type
*howto
;
2958 /* In a compound relocation, it is the final (outermost)
2959 operator that determines the relocated field. */
2960 for (i
= 1; i
< 3; i
++)
2961 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2964 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2965 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2966 bfd_get_reloc_size (howto
),
2968 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2971 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2972 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2973 && ip
->fixp
[0]->fx_addsy
)
2974 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2976 /* These relocations can have an addend that won't fit in
2977 4 octets for 64bit assembly. */
2979 && ! howto
->partial_inplace
2980 && (reloc_type
[0] == BFD_RELOC_16
2981 || reloc_type
[0] == BFD_RELOC_32
2982 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2983 || reloc_type
[0] == BFD_RELOC_GPREL16
2984 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2985 || reloc_type
[0] == BFD_RELOC_GPREL32
2986 || reloc_type
[0] == BFD_RELOC_64
2987 || reloc_type
[0] == BFD_RELOC_CTOR
2988 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2989 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2990 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2991 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2992 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2993 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2994 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2995 || hi16_reloc_p (reloc_type
[0])
2996 || lo16_reloc_p (reloc_type
[0])))
2997 ip
->fixp
[0]->fx_no_overflow
= 1;
2999 if (mips_relax
.sequence
)
3001 if (mips_relax
.first_fixup
== 0)
3002 mips_relax
.first_fixup
= ip
->fixp
[0];
3004 else if (reloc_needs_lo_p (*reloc_type
))
3006 struct mips_hi_fixup
*hi_fixup
;
3008 /* Reuse the last entry if it already has a matching %lo. */
3009 hi_fixup
= mips_hi_fixup_list
;
3011 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3013 hi_fixup
= ((struct mips_hi_fixup
*)
3014 xmalloc (sizeof (struct mips_hi_fixup
)));
3015 hi_fixup
->next
= mips_hi_fixup_list
;
3016 mips_hi_fixup_list
= hi_fixup
;
3018 hi_fixup
->fixp
= ip
->fixp
[0];
3019 hi_fixup
->seg
= now_seg
;
3022 /* Add fixups for the second and third relocations, if given.
3023 Note that the ABI allows the second relocation to be
3024 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3025 moment we only use RSS_UNDEF, but we could add support
3026 for the others if it ever becomes necessary. */
3027 for (i
= 1; i
< 3; i
++)
3028 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3030 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3031 ip
->fixp
[0]->fx_size
, NULL
, 0,
3032 FALSE
, reloc_type
[i
]);
3034 /* Use fx_tcbit to mark compound relocs. */
3035 ip
->fixp
[0]->fx_tcbit
= 1;
3036 ip
->fixp
[i
]->fx_tcbit
= 1;
3042 /* Update the register mask information. */
3043 if (! mips_opts
.mips16
)
3045 if (pinfo
& INSN_WRITE_GPR_D
)
3046 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3047 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3048 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3049 if (pinfo
& INSN_READ_GPR_S
)
3050 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3051 if (pinfo
& INSN_WRITE_GPR_31
)
3052 mips_gprmask
|= 1 << RA
;
3053 if (pinfo
& INSN_WRITE_FPR_D
)
3054 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3055 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3056 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3057 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3058 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3059 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3060 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3061 if (pinfo
& INSN_COP
)
3063 /* We don't keep enough information to sort these cases out.
3064 The itbl support does keep this information however, although
3065 we currently don't support itbl fprmats as part of the cop
3066 instruction. May want to add this support in the future. */
3068 /* Never set the bit for $0, which is always zero. */
3069 mips_gprmask
&= ~1 << 0;
3073 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3074 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3075 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3076 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3077 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3078 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3079 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3080 mips_gprmask
|= 1 << TREG
;
3081 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3082 mips_gprmask
|= 1 << SP
;
3083 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3084 mips_gprmask
|= 1 << RA
;
3085 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3086 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3087 if (pinfo
& MIPS16_INSN_READ_Z
)
3088 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3089 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3090 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3093 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3095 /* Filling the branch delay slot is more complex. We try to
3096 switch the branch with the previous instruction, which we can
3097 do if the previous instruction does not set up a condition
3098 that the branch tests and if the branch is not itself the
3099 target of any branch. */
3100 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3101 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3103 if (mips_optimize
< 2
3104 /* If we have seen .set volatile or .set nomove, don't
3106 || mips_opts
.nomove
!= 0
3107 /* We can't swap if the previous instruction's position
3109 || history
[0].fixed_p
3110 /* If the previous previous insn was in a .set
3111 noreorder, we can't swap. Actually, the MIPS
3112 assembler will swap in this situation. However, gcc
3113 configured -with-gnu-as will generate code like
3119 in which we can not swap the bne and INSN. If gcc is
3120 not configured -with-gnu-as, it does not output the
3122 || history
[1].noreorder_p
3123 /* If the branch is itself the target of a branch, we
3124 can not swap. We cheat on this; all we check for is
3125 whether there is a label on this instruction. If
3126 there are any branches to anything other than a
3127 label, users must use .set noreorder. */
3128 || si
->label_list
!= NULL
3129 /* If the previous instruction is in a variant frag
3130 other than this branch's one, we cannot do the swap.
3131 This does not apply to the mips16, which uses variant
3132 frags for different purposes. */
3133 || (! mips_opts
.mips16
3134 && prev_insn_frag_type
== rs_machine_dependent
)
3135 /* Check for conflicts between the branch and the instructions
3136 before the candidate delay slot. */
3137 || nops_for_insn (history
+ 1, ip
) > 0
3138 /* Check for conflicts between the swapped sequence and the
3139 target of the branch. */
3140 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3141 /* We do not swap with a trap instruction, since it
3142 complicates trap handlers to have the trap
3143 instruction be in a delay slot. */
3144 || (prev_pinfo
& INSN_TRAP
)
3145 /* If the branch reads a register that the previous
3146 instruction sets, we can not swap. */
3147 || (! mips_opts
.mips16
3148 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3149 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3151 || (! mips_opts
.mips16
3152 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3153 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3155 || (mips_opts
.mips16
3156 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3158 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3160 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3162 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3164 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3166 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3168 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3169 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3170 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3171 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3172 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3173 && insn_uses_reg (ip
,
3174 MIPS16OP_EXTRACT_REG32R
3175 (history
[0].insn_opcode
),
3177 /* If the branch writes a register that the previous
3178 instruction sets, we can not swap (we know that
3179 branches write only to RD or to $31). */
3180 || (! mips_opts
.mips16
3181 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3182 && (((pinfo
& INSN_WRITE_GPR_D
)
3183 && (EXTRACT_OPERAND (RT
, history
[0])
3184 == EXTRACT_OPERAND (RD
, *ip
)))
3185 || ((pinfo
& INSN_WRITE_GPR_31
)
3186 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3187 || (! mips_opts
.mips16
3188 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3189 && (((pinfo
& INSN_WRITE_GPR_D
)
3190 && (EXTRACT_OPERAND (RD
, history
[0])
3191 == EXTRACT_OPERAND (RD
, *ip
)))
3192 || ((pinfo
& INSN_WRITE_GPR_31
)
3193 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3194 || (mips_opts
.mips16
3195 && (pinfo
& MIPS16_INSN_WRITE_31
)
3196 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3197 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3198 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3200 /* If the branch writes a register that the previous
3201 instruction reads, we can not swap (we know that
3202 branches only write to RD or to $31). */
3203 || (! mips_opts
.mips16
3204 && (pinfo
& INSN_WRITE_GPR_D
)
3205 && insn_uses_reg (&history
[0],
3206 EXTRACT_OPERAND (RD
, *ip
),
3208 || (! mips_opts
.mips16
3209 && (pinfo
& INSN_WRITE_GPR_31
)
3210 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3211 || (mips_opts
.mips16
3212 && (pinfo
& MIPS16_INSN_WRITE_31
)
3213 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3214 /* If one instruction sets a condition code and the
3215 other one uses a condition code, we can not swap. */
3216 || ((pinfo
& INSN_READ_COND_CODE
)
3217 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3218 || ((pinfo
& INSN_WRITE_COND_CODE
)
3219 && (prev_pinfo
& INSN_READ_COND_CODE
))
3220 /* If the previous instruction uses the PC, we can not
3222 || (mips_opts
.mips16
3223 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3224 /* If the previous instruction had a fixup in mips16
3225 mode, we can not swap. This normally means that the
3226 previous instruction was a 4 byte branch anyhow. */
3227 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3228 /* If the previous instruction is a sync, sync.l, or
3229 sync.p, we can not swap. */
3230 || (prev_pinfo
& INSN_SYNC
))
3232 if (mips_opts
.mips16
3233 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3234 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3235 && ISA_SUPPORTS_MIPS16E
)
3237 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3238 ip
->insn_opcode
|= 0x0080;
3240 insert_into_history (0, 1, ip
);
3244 /* We could do even better for unconditional branches to
3245 portions of this object file; we could pick up the
3246 instruction at the destination, put it in the delay
3247 slot, and bump the destination address. */
3248 insert_into_history (0, 1, ip
);
3252 if (mips_relax
.sequence
)
3253 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3257 /* It looks like we can actually do the swap. */
3258 struct mips_cl_insn delay
= history
[0];
3259 if (mips_opts
.mips16
)
3261 know (delay
.frag
== ip
->frag
);
3262 move_insn (ip
, delay
.frag
, delay
.where
);
3263 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3265 else if (relaxed_branch
)
3267 /* Add the delay slot instruction to the end of the
3268 current frag and shrink the fixed part of the
3269 original frag. If the branch occupies the tail of
3270 the latter, move it backwards to cover the gap. */
3271 delay
.frag
->fr_fix
-= 4;
3272 if (delay
.frag
== ip
->frag
)
3273 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3274 add_fixed_insn (&delay
);
3278 move_insn (&delay
, ip
->frag
, ip
->where
);
3279 move_insn (ip
, history
[0].frag
, history
[0].where
);
3283 insert_into_history (0, 1, &delay
);
3286 /* If that was an unconditional branch, forget the previous
3287 insn information. */
3288 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3289 mips_no_prev_insn ();
3291 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3293 /* We don't yet optimize a branch likely. What we should do
3294 is look at the target, copy the instruction found there
3295 into the delay slot, and increment the branch to jump to
3296 the next instruction. */
3297 insert_into_history (0, 1, ip
);
3301 insert_into_history (0, 1, ip
);
3304 insert_into_history (0, 1, ip
);
3306 /* We just output an insn, so the next one doesn't have a label. */
3307 mips_clear_insn_labels ();
3310 /* Forget that there was any previous instruction or label. */
3313 mips_no_prev_insn (void)
3315 prev_nop_frag
= NULL
;
3316 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3317 mips_clear_insn_labels ();
3320 /* This function must be called before we emit something other than
3321 instructions. It is like mips_no_prev_insn except that it inserts
3322 any NOPS that might be needed by previous instructions. */
3325 mips_emit_delays (void)
3327 if (! mips_opts
.noreorder
)
3329 int nops
= nops_for_insn (history
, NULL
);
3333 add_fixed_insn (NOP_INSN
);
3334 mips_move_labels ();
3337 mips_no_prev_insn ();
3340 /* Start a (possibly nested) noreorder block. */
3343 start_noreorder (void)
3345 if (mips_opts
.noreorder
== 0)
3350 /* None of the instructions before the .set noreorder can be moved. */
3351 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3352 history
[i
].fixed_p
= 1;
3354 /* Insert any nops that might be needed between the .set noreorder
3355 block and the previous instructions. We will later remove any
3356 nops that turn out not to be needed. */
3357 nops
= nops_for_insn (history
, NULL
);
3360 if (mips_optimize
!= 0)
3362 /* Record the frag which holds the nop instructions, so
3363 that we can remove them if we don't need them. */
3364 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3365 prev_nop_frag
= frag_now
;
3366 prev_nop_frag_holds
= nops
;
3367 prev_nop_frag_required
= 0;
3368 prev_nop_frag_since
= 0;
3371 for (; nops
> 0; --nops
)
3372 add_fixed_insn (NOP_INSN
);
3374 /* Move on to a new frag, so that it is safe to simply
3375 decrease the size of prev_nop_frag. */
3376 frag_wane (frag_now
);
3378 mips_move_labels ();
3380 mips16_mark_labels ();
3381 mips_clear_insn_labels ();
3383 mips_opts
.noreorder
++;
3384 mips_any_noreorder
= 1;
3387 /* End a nested noreorder block. */
3390 end_noreorder (void)
3392 mips_opts
.noreorder
--;
3393 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3395 /* Commit to inserting prev_nop_frag_required nops and go back to
3396 handling nop insertion the .set reorder way. */
3397 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3398 * (mips_opts
.mips16
? 2 : 4));
3399 insert_into_history (prev_nop_frag_since
,
3400 prev_nop_frag_required
, NOP_INSN
);
3401 prev_nop_frag
= NULL
;
3405 /* Set up global variables for the start of a new macro. */
3410 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3411 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3412 && (history
[0].insn_mo
->pinfo
3413 & (INSN_UNCOND_BRANCH_DELAY
3414 | INSN_COND_BRANCH_DELAY
3415 | INSN_COND_BRANCH_LIKELY
)) != 0);
3418 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3419 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3420 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3423 macro_warning (relax_substateT subtype
)
3425 if (subtype
& RELAX_DELAY_SLOT
)
3426 return _("Macro instruction expanded into multiple instructions"
3427 " in a branch delay slot");
3428 else if (subtype
& RELAX_NOMACRO
)
3429 return _("Macro instruction expanded into multiple instructions");
3434 /* Finish up a macro. Emit warnings as appropriate. */
3439 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3441 relax_substateT subtype
;
3443 /* Set up the relaxation warning flags. */
3445 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3446 subtype
|= RELAX_SECOND_LONGER
;
3447 if (mips_opts
.warn_about_macros
)
3448 subtype
|= RELAX_NOMACRO
;
3449 if (mips_macro_warning
.delay_slot_p
)
3450 subtype
|= RELAX_DELAY_SLOT
;
3452 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3454 /* Either the macro has a single implementation or both
3455 implementations are longer than 4 bytes. Emit the
3457 const char *msg
= macro_warning (subtype
);
3463 /* One implementation might need a warning but the other
3464 definitely doesn't. */
3465 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3470 /* Read a macro's relocation codes from *ARGS and store them in *R.
3471 The first argument in *ARGS will be either the code for a single
3472 relocation or -1 followed by the three codes that make up a
3473 composite relocation. */
3476 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3480 next
= va_arg (*args
, int);
3482 r
[0] = (bfd_reloc_code_real_type
) next
;
3484 for (i
= 0; i
< 3; i
++)
3485 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3488 /* Build an instruction created by a macro expansion. This is passed
3489 a pointer to the count of instructions created so far, an
3490 expression, the name of the instruction to build, an operand format
3491 string, and corresponding arguments. */
3494 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3496 const struct mips_opcode
*mo
;
3497 struct mips_cl_insn insn
;
3498 bfd_reloc_code_real_type r
[3];
3501 va_start (args
, fmt
);
3503 if (mips_opts
.mips16
)
3505 mips16_macro_build (ep
, name
, fmt
, args
);
3510 r
[0] = BFD_RELOC_UNUSED
;
3511 r
[1] = BFD_RELOC_UNUSED
;
3512 r
[2] = BFD_RELOC_UNUSED
;
3513 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3515 assert (strcmp (name
, mo
->name
) == 0);
3519 /* Search until we get a match for NAME. It is assumed here that
3520 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3521 if (strcmp (fmt
, mo
->args
) == 0
3522 && mo
->pinfo
!= INSN_MACRO
3523 && is_opcode_valid (mo
, TRUE
))
3528 assert (strcmp (name
, mo
->name
) == 0);
3531 create_insn (&insn
, mo
);
3549 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3554 /* Note that in the macro case, these arguments are already
3555 in MSB form. (When handling the instruction in the
3556 non-macro case, these arguments are sizes from which
3557 MSB values must be calculated.) */
3558 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3564 /* Note that in the macro case, these arguments are already
3565 in MSBD form. (When handling the instruction in the
3566 non-macro case, these arguments are sizes from which
3567 MSBD values must be calculated.) */
3568 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3572 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3581 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3587 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3591 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3596 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3602 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3607 int tmp
= va_arg (args
, int);
3609 INSERT_OPERAND (RT
, insn
, tmp
);
3610 INSERT_OPERAND (RD
, insn
, tmp
);
3616 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3623 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3627 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3631 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3635 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3639 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3646 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3652 macro_read_relocs (&args
, r
);
3653 assert (*r
== BFD_RELOC_GPREL16
3654 || *r
== BFD_RELOC_MIPS_LITERAL
3655 || *r
== BFD_RELOC_MIPS_HIGHER
3656 || *r
== BFD_RELOC_HI16_S
3657 || *r
== BFD_RELOC_LO16
3658 || *r
== BFD_RELOC_MIPS_GOT16
3659 || *r
== BFD_RELOC_MIPS_CALL16
3660 || *r
== BFD_RELOC_MIPS_GOT_DISP
3661 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3662 || *r
== BFD_RELOC_MIPS_GOT_OFST
3663 || *r
== BFD_RELOC_MIPS_GOT_LO16
3664 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3668 macro_read_relocs (&args
, r
);
3670 && (ep
->X_op
== O_constant
3671 || (ep
->X_op
== O_symbol
3672 && (*r
== BFD_RELOC_MIPS_HIGHEST
3673 || *r
== BFD_RELOC_HI16_S
3674 || *r
== BFD_RELOC_HI16
3675 || *r
== BFD_RELOC_GPREL16
3676 || *r
== BFD_RELOC_MIPS_GOT_HI16
3677 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3681 assert (ep
!= NULL
);
3684 * This allows macro() to pass an immediate expression for
3685 * creating short branches without creating a symbol.
3687 * We don't allow branch relaxation for these branches, as
3688 * they should only appear in ".set nomacro" anyway.
3690 if (ep
->X_op
== O_constant
)
3692 if ((ep
->X_add_number
& 3) != 0)
3693 as_bad (_("branch to misaligned address (0x%lx)"),
3694 (unsigned long) ep
->X_add_number
);
3695 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3696 as_bad (_("branch address range overflow (0x%lx)"),
3697 (unsigned long) ep
->X_add_number
);
3698 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3702 *r
= BFD_RELOC_16_PCREL_S2
;
3706 assert (ep
!= NULL
);
3707 *r
= BFD_RELOC_MIPS_JMP
;
3711 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3715 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3724 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3726 append_insn (&insn
, ep
, r
);
3730 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3733 struct mips_opcode
*mo
;
3734 struct mips_cl_insn insn
;
3735 bfd_reloc_code_real_type r
[3]
3736 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3738 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3740 assert (strcmp (name
, mo
->name
) == 0);
3742 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3746 assert (strcmp (name
, mo
->name
) == 0);
3749 create_insn (&insn
, mo
);
3767 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3772 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3776 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3780 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3790 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3797 regno
= va_arg (args
, int);
3798 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3799 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3820 assert (ep
!= NULL
);
3822 if (ep
->X_op
!= O_constant
)
3823 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3826 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3827 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3830 *r
= BFD_RELOC_UNUSED
;
3836 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3843 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3845 append_insn (&insn
, ep
, r
);
3849 * Sign-extend 32-bit mode constants that have bit 31 set and all
3850 * higher bits unset.
3853 normalize_constant_expr (expressionS
*ex
)
3855 if (ex
->X_op
== O_constant
3856 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3857 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3862 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3863 * all higher bits unset.
3866 normalize_address_expr (expressionS
*ex
)
3868 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3869 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3870 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3871 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3876 * Generate a "jalr" instruction with a relocation hint to the called
3877 * function. This occurs in NewABI PIC code.
3880 macro_build_jalr (expressionS
*ep
)
3889 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3891 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3892 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3896 * Generate a "lui" instruction.
3899 macro_build_lui (expressionS
*ep
, int regnum
)
3901 expressionS high_expr
;
3902 const struct mips_opcode
*mo
;
3903 struct mips_cl_insn insn
;
3904 bfd_reloc_code_real_type r
[3]
3905 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3906 const char *name
= "lui";
3907 const char *fmt
= "t,u";
3909 assert (! mips_opts
.mips16
);
3913 if (high_expr
.X_op
== O_constant
)
3915 /* We can compute the instruction now without a relocation entry. */
3916 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3918 *r
= BFD_RELOC_UNUSED
;
3922 assert (ep
->X_op
== O_symbol
);
3923 /* _gp_disp is a special case, used from s_cpload.
3924 __gnu_local_gp is used if mips_no_shared. */
3925 assert (mips_pic
== NO_PIC
3927 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3928 || (! mips_in_shared
3929 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3930 "__gnu_local_gp") == 0));
3931 *r
= BFD_RELOC_HI16_S
;
3934 mo
= hash_find (op_hash
, name
);
3935 assert (strcmp (name
, mo
->name
) == 0);
3936 assert (strcmp (fmt
, mo
->args
) == 0);
3937 create_insn (&insn
, mo
);
3939 insn
.insn_opcode
= insn
.insn_mo
->match
;
3940 INSERT_OPERAND (RT
, insn
, regnum
);
3941 if (*r
== BFD_RELOC_UNUSED
)
3943 insn
.insn_opcode
|= high_expr
.X_add_number
;
3944 append_insn (&insn
, NULL
, r
);
3947 append_insn (&insn
, &high_expr
, r
);
3950 /* Generate a sequence of instructions to do a load or store from a constant
3951 offset off of a base register (breg) into/from a target register (treg),
3952 using AT if necessary. */
3954 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3955 int treg
, int breg
, int dbl
)
3957 assert (ep
->X_op
== O_constant
);
3959 /* Sign-extending 32-bit constants makes their handling easier. */
3961 normalize_constant_expr (ep
);
3963 /* Right now, this routine can only handle signed 32-bit constants. */
3964 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3965 as_warn (_("operand overflow"));
3967 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3969 /* Signed 16-bit offset will fit in the op. Easy! */
3970 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3974 /* 32-bit offset, need multiple instructions and AT, like:
3975 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3976 addu $tempreg,$tempreg,$breg
3977 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3978 to handle the complete offset. */
3979 macro_build_lui (ep
, AT
);
3980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3981 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3984 as_bad (_("Macro used $at after \".set noat\""));
3989 * Generates code to set the $at register to true (one)
3990 * if reg is less than the immediate expression.
3993 set_at (int reg
, int unsignedp
)
3995 if (imm_expr
.X_op
== O_constant
3996 && imm_expr
.X_add_number
>= -0x8000
3997 && imm_expr
.X_add_number
< 0x8000)
3998 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3999 AT
, reg
, BFD_RELOC_LO16
);
4002 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4003 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4007 /* Warn if an expression is not a constant. */
4010 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4012 if (ex
->X_op
== O_big
)
4013 as_bad (_("unsupported large constant"));
4014 else if (ex
->X_op
!= O_constant
)
4015 as_bad (_("Instruction %s requires absolute expression"),
4018 if (HAVE_32BIT_GPRS
)
4019 normalize_constant_expr (ex
);
4022 /* Count the leading zeroes by performing a binary chop. This is a
4023 bulky bit of source, but performance is a LOT better for the
4024 majority of values than a simple loop to count the bits:
4025 for (lcnt = 0; (lcnt < 32); lcnt++)
4026 if ((v) & (1 << (31 - lcnt)))
4028 However it is not code size friendly, and the gain will drop a bit
4029 on certain cached systems.
4031 #define COUNT_TOP_ZEROES(v) \
4032 (((v) & ~0xffff) == 0 \
4033 ? ((v) & ~0xff) == 0 \
4034 ? ((v) & ~0xf) == 0 \
4035 ? ((v) & ~0x3) == 0 \
4036 ? ((v) & ~0x1) == 0 \
4041 : ((v) & ~0x7) == 0 \
4044 : ((v) & ~0x3f) == 0 \
4045 ? ((v) & ~0x1f) == 0 \
4048 : ((v) & ~0x7f) == 0 \
4051 : ((v) & ~0xfff) == 0 \
4052 ? ((v) & ~0x3ff) == 0 \
4053 ? ((v) & ~0x1ff) == 0 \
4056 : ((v) & ~0x7ff) == 0 \
4059 : ((v) & ~0x3fff) == 0 \
4060 ? ((v) & ~0x1fff) == 0 \
4063 : ((v) & ~0x7fff) == 0 \
4066 : ((v) & ~0xffffff) == 0 \
4067 ? ((v) & ~0xfffff) == 0 \
4068 ? ((v) & ~0x3ffff) == 0 \
4069 ? ((v) & ~0x1ffff) == 0 \
4072 : ((v) & ~0x7ffff) == 0 \
4075 : ((v) & ~0x3fffff) == 0 \
4076 ? ((v) & ~0x1fffff) == 0 \
4079 : ((v) & ~0x7fffff) == 0 \
4082 : ((v) & ~0xfffffff) == 0 \
4083 ? ((v) & ~0x3ffffff) == 0 \
4084 ? ((v) & ~0x1ffffff) == 0 \
4087 : ((v) & ~0x7ffffff) == 0 \
4090 : ((v) & ~0x3fffffff) == 0 \
4091 ? ((v) & ~0x1fffffff) == 0 \
4094 : ((v) & ~0x7fffffff) == 0 \
4099 * This routine generates the least number of instructions necessary to load
4100 * an absolute expression value into a register.
4103 load_register (int reg
, expressionS
*ep
, int dbl
)
4106 expressionS hi32
, lo32
;
4108 if (ep
->X_op
!= O_big
)
4110 assert (ep
->X_op
== O_constant
);
4112 /* Sign-extending 32-bit constants makes their handling easier. */
4114 normalize_constant_expr (ep
);
4116 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4118 /* We can handle 16 bit signed values with an addiu to
4119 $zero. No need to ever use daddiu here, since $zero and
4120 the result are always correct in 32 bit mode. */
4121 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4124 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4126 /* We can handle 16 bit unsigned values with an ori to
4128 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4131 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4133 /* 32 bit values require an lui. */
4134 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4135 if ((ep
->X_add_number
& 0xffff) != 0)
4136 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4141 /* The value is larger than 32 bits. */
4143 if (!dbl
|| HAVE_32BIT_GPRS
)
4147 sprintf_vma (value
, ep
->X_add_number
);
4148 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4149 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4153 if (ep
->X_op
!= O_big
)
4156 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4157 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4158 hi32
.X_add_number
&= 0xffffffff;
4160 lo32
.X_add_number
&= 0xffffffff;
4164 assert (ep
->X_add_number
> 2);
4165 if (ep
->X_add_number
== 3)
4166 generic_bignum
[3] = 0;
4167 else if (ep
->X_add_number
> 4)
4168 as_bad (_("Number larger than 64 bits"));
4169 lo32
.X_op
= O_constant
;
4170 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4171 hi32
.X_op
= O_constant
;
4172 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4175 if (hi32
.X_add_number
== 0)
4180 unsigned long hi
, lo
;
4182 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4184 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4186 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4189 if (lo32
.X_add_number
& 0x80000000)
4191 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4192 if (lo32
.X_add_number
& 0xffff)
4193 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4198 /* Check for 16bit shifted constant. We know that hi32 is
4199 non-zero, so start the mask on the first bit of the hi32
4204 unsigned long himask
, lomask
;
4208 himask
= 0xffff >> (32 - shift
);
4209 lomask
= (0xffff << shift
) & 0xffffffff;
4213 himask
= 0xffff << (shift
- 32);
4216 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4217 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4221 tmp
.X_op
= O_constant
;
4223 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4224 | (lo32
.X_add_number
>> shift
));
4226 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4227 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4228 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4229 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4234 while (shift
<= (64 - 16));
4236 /* Find the bit number of the lowest one bit, and store the
4237 shifted value in hi/lo. */
4238 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4239 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4243 while ((lo
& 1) == 0)
4248 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4254 while ((hi
& 1) == 0)
4263 /* Optimize if the shifted value is a (power of 2) - 1. */
4264 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4265 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4267 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4272 /* This instruction will set the register to be all
4274 tmp
.X_op
= O_constant
;
4275 tmp
.X_add_number
= (offsetT
) -1;
4276 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4280 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4281 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4283 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4284 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4289 /* Sign extend hi32 before calling load_register, because we can
4290 generally get better code when we load a sign extended value. */
4291 if ((hi32
.X_add_number
& 0x80000000) != 0)
4292 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4293 load_register (reg
, &hi32
, 0);
4296 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4300 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4308 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4310 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4311 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4317 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4321 mid16
.X_add_number
>>= 16;
4322 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4323 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4326 if ((lo32
.X_add_number
& 0xffff) != 0)
4327 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4331 load_delay_nop (void)
4333 if (!gpr_interlocks
)
4334 macro_build (NULL
, "nop", "");
4337 /* Load an address into a register. */
4340 load_address (int reg
, expressionS
*ep
, int *used_at
)
4342 if (ep
->X_op
!= O_constant
4343 && ep
->X_op
!= O_symbol
)
4345 as_bad (_("expression too complex"));
4346 ep
->X_op
= O_constant
;
4349 if (ep
->X_op
== O_constant
)
4351 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4355 if (mips_pic
== NO_PIC
)
4357 /* If this is a reference to a GP relative symbol, we want
4358 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4360 lui $reg,<sym> (BFD_RELOC_HI16_S)
4361 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4362 If we have an addend, we always use the latter form.
4364 With 64bit address space and a usable $at we want
4365 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4366 lui $at,<sym> (BFD_RELOC_HI16_S)
4367 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4368 daddiu $at,<sym> (BFD_RELOC_LO16)
4372 If $at is already in use, we use a path which is suboptimal
4373 on superscalar processors.
4374 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4375 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4377 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4379 daddiu $reg,<sym> (BFD_RELOC_LO16)
4381 For GP relative symbols in 64bit address space we can use
4382 the same sequence as in 32bit address space. */
4383 if (HAVE_64BIT_SYMBOLS
)
4385 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4386 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4388 relax_start (ep
->X_add_symbol
);
4389 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4390 mips_gp_register
, BFD_RELOC_GPREL16
);
4394 if (*used_at
== 0 && mips_opts
.at
)
4396 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4397 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4398 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4399 BFD_RELOC_MIPS_HIGHER
);
4400 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4401 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4402 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4407 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4408 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4409 BFD_RELOC_MIPS_HIGHER
);
4410 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4411 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4412 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4413 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4416 if (mips_relax
.sequence
)
4421 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4422 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4424 relax_start (ep
->X_add_symbol
);
4425 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4426 mips_gp_register
, BFD_RELOC_GPREL16
);
4429 macro_build_lui (ep
, reg
);
4430 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4431 reg
, reg
, BFD_RELOC_LO16
);
4432 if (mips_relax
.sequence
)
4436 else if (!mips_big_got
)
4440 /* If this is a reference to an external symbol, we want
4441 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4443 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4445 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4446 If there is a constant, it must be added in after.
4448 If we have NewABI, we want
4449 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4450 unless we're referencing a global symbol with a non-zero
4451 offset, in which case cst must be added separately. */
4454 if (ep
->X_add_number
)
4456 ex
.X_add_number
= ep
->X_add_number
;
4457 ep
->X_add_number
= 0;
4458 relax_start (ep
->X_add_symbol
);
4459 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4460 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4461 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4462 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4463 ex
.X_op
= O_constant
;
4464 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4465 reg
, reg
, BFD_RELOC_LO16
);
4466 ep
->X_add_number
= ex
.X_add_number
;
4469 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4470 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4471 if (mips_relax
.sequence
)
4476 ex
.X_add_number
= ep
->X_add_number
;
4477 ep
->X_add_number
= 0;
4478 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4479 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4481 relax_start (ep
->X_add_symbol
);
4483 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4487 if (ex
.X_add_number
!= 0)
4489 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4490 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4491 ex
.X_op
= O_constant
;
4492 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4493 reg
, reg
, BFD_RELOC_LO16
);
4497 else if (mips_big_got
)
4501 /* This is the large GOT case. If this is a reference to an
4502 external symbol, we want
4503 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4505 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4507 Otherwise, for a reference to a local symbol in old ABI, we want
4508 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4510 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4511 If there is a constant, it must be added in after.
4513 In the NewABI, for local symbols, with or without offsets, we want:
4514 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4515 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4519 ex
.X_add_number
= ep
->X_add_number
;
4520 ep
->X_add_number
= 0;
4521 relax_start (ep
->X_add_symbol
);
4522 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4523 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4524 reg
, reg
, mips_gp_register
);
4525 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4526 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4527 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4528 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4529 else if (ex
.X_add_number
)
4531 ex
.X_op
= O_constant
;
4532 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4536 ep
->X_add_number
= ex
.X_add_number
;
4538 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4539 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4540 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4541 BFD_RELOC_MIPS_GOT_OFST
);
4546 ex
.X_add_number
= ep
->X_add_number
;
4547 ep
->X_add_number
= 0;
4548 relax_start (ep
->X_add_symbol
);
4549 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4551 reg
, reg
, mips_gp_register
);
4552 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4553 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4555 if (reg_needs_delay (mips_gp_register
))
4557 /* We need a nop before loading from $gp. This special
4558 check is required because the lui which starts the main
4559 instruction stream does not refer to $gp, and so will not
4560 insert the nop which may be required. */
4561 macro_build (NULL
, "nop", "");
4563 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4564 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4566 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4570 if (ex
.X_add_number
!= 0)
4572 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4573 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4574 ex
.X_op
= O_constant
;
4575 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4583 if (!mips_opts
.at
&& *used_at
== 1)
4584 as_bad (_("Macro used $at after \".set noat\""));
4587 /* Move the contents of register SOURCE into register DEST. */
4590 move_register (int dest
, int source
)
4592 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4596 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4597 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4598 The two alternatives are:
4600 Global symbol Local sybmol
4601 ------------- ------------
4602 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4604 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4606 load_got_offset emits the first instruction and add_got_offset
4607 emits the second for a 16-bit offset or add_got_offset_hilo emits
4608 a sequence to add a 32-bit offset using a scratch register. */
4611 load_got_offset (int dest
, expressionS
*local
)
4616 global
.X_add_number
= 0;
4618 relax_start (local
->X_add_symbol
);
4619 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4620 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4622 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4623 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4628 add_got_offset (int dest
, expressionS
*local
)
4632 global
.X_op
= O_constant
;
4633 global
.X_op_symbol
= NULL
;
4634 global
.X_add_symbol
= NULL
;
4635 global
.X_add_number
= local
->X_add_number
;
4637 relax_start (local
->X_add_symbol
);
4638 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4639 dest
, dest
, BFD_RELOC_LO16
);
4641 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4646 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4649 int hold_mips_optimize
;
4651 global
.X_op
= O_constant
;
4652 global
.X_op_symbol
= NULL
;
4653 global
.X_add_symbol
= NULL
;
4654 global
.X_add_number
= local
->X_add_number
;
4656 relax_start (local
->X_add_symbol
);
4657 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4659 /* Set mips_optimize around the lui instruction to avoid
4660 inserting an unnecessary nop after the lw. */
4661 hold_mips_optimize
= mips_optimize
;
4663 macro_build_lui (&global
, tmp
);
4664 mips_optimize
= hold_mips_optimize
;
4665 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4668 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4673 * This routine implements the seemingly endless macro or synthesized
4674 * instructions and addressing modes in the mips assembly language. Many
4675 * of these macros are simple and are similar to each other. These could
4676 * probably be handled by some kind of table or grammar approach instead of
4677 * this verbose method. Others are not simple macros but are more like
4678 * optimizing code generation.
4679 * One interesting optimization is when several store macros appear
4680 * consecutively that would load AT with the upper half of the same address.
4681 * The ensuing load upper instructions are ommited. This implies some kind
4682 * of global optimization. We currently only optimize within a single macro.
4683 * For many of the load and store macros if the address is specified as a
4684 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4685 * first load register 'at' with zero and use it as the base register. The
4686 * mips assembler simply uses register $zero. Just one tiny optimization
4690 macro (struct mips_cl_insn
*ip
)
4692 unsigned int treg
, sreg
, dreg
, breg
;
4693 unsigned int tempreg
;
4708 bfd_reloc_code_real_type r
;
4709 int hold_mips_optimize
;
4711 assert (! mips_opts
.mips16
);
4713 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4714 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4715 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4716 mask
= ip
->insn_mo
->mask
;
4718 expr1
.X_op
= O_constant
;
4719 expr1
.X_op_symbol
= NULL
;
4720 expr1
.X_add_symbol
= NULL
;
4721 expr1
.X_add_number
= 1;
4735 expr1
.X_add_number
= 8;
4736 macro_build (&expr1
, "bgez", "s,p", sreg
);
4738 macro_build (NULL
, "nop", "", 0);
4740 move_register (dreg
, sreg
);
4741 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4764 if (imm_expr
.X_op
== O_constant
4765 && imm_expr
.X_add_number
>= -0x8000
4766 && imm_expr
.X_add_number
< 0x8000)
4768 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4772 load_register (AT
, &imm_expr
, dbl
);
4773 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4792 if (imm_expr
.X_op
== O_constant
4793 && imm_expr
.X_add_number
>= 0
4794 && imm_expr
.X_add_number
< 0x10000)
4796 if (mask
!= M_NOR_I
)
4797 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4800 macro_build (&imm_expr
, "ori", "t,r,i",
4801 treg
, sreg
, BFD_RELOC_LO16
);
4802 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4808 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4809 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4813 switch (imm_expr
.X_add_number
)
4816 macro_build (NULL
, "nop", "");
4819 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4822 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4823 (int)imm_expr
.X_add_number
);
4842 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4844 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4848 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4849 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4857 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4862 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4866 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4867 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4873 /* check for > max integer */
4874 maxnum
= 0x7fffffff;
4875 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4882 if (imm_expr
.X_op
== O_constant
4883 && imm_expr
.X_add_number
>= maxnum
4884 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4887 /* result is always false */
4889 macro_build (NULL
, "nop", "", 0);
4891 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4894 if (imm_expr
.X_op
!= O_constant
)
4895 as_bad (_("Unsupported large constant"));
4896 ++imm_expr
.X_add_number
;
4900 if (mask
== M_BGEL_I
)
4902 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4904 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4907 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4909 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4912 maxnum
= 0x7fffffff;
4913 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4920 maxnum
= - maxnum
- 1;
4921 if (imm_expr
.X_op
== O_constant
4922 && imm_expr
.X_add_number
<= maxnum
4923 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4926 /* result is always true */
4927 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4928 macro_build (&offset_expr
, "b", "p");
4933 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4943 macro_build (&offset_expr
, likely
? "beql" : "beq",
4948 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4949 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4957 && imm_expr
.X_op
== O_constant
4958 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4960 if (imm_expr
.X_op
!= O_constant
)
4961 as_bad (_("Unsupported large constant"));
4962 ++imm_expr
.X_add_number
;
4966 if (mask
== M_BGEUL_I
)
4968 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4970 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4972 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4978 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4986 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4991 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4995 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4996 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5004 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5011 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5012 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5020 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5025 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5029 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5030 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5036 maxnum
= 0x7fffffff;
5037 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5044 if (imm_expr
.X_op
== O_constant
5045 && imm_expr
.X_add_number
>= maxnum
5046 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5048 if (imm_expr
.X_op
!= O_constant
)
5049 as_bad (_("Unsupported large constant"));
5050 ++imm_expr
.X_add_number
;
5054 if (mask
== M_BLTL_I
)
5056 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5058 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5061 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5063 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5068 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5076 macro_build (&offset_expr
, likely
? "beql" : "beq",
5083 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5084 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5092 && imm_expr
.X_op
== O_constant
5093 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5095 if (imm_expr
.X_op
!= O_constant
)
5096 as_bad (_("Unsupported large constant"));
5097 ++imm_expr
.X_add_number
;
5101 if (mask
== M_BLTUL_I
)
5103 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5105 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5107 macro_build (&offset_expr
, likely
? "beql" : "beq",
5113 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5121 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5126 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5130 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5131 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5141 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5146 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5147 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5155 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5157 as_bad (_("Unsupported large constant"));
5162 pos
= (unsigned long) imm_expr
.X_add_number
;
5163 size
= (unsigned long) imm2_expr
.X_add_number
;
5168 as_bad (_("Improper position (%lu)"), pos
);
5171 if (size
== 0 || size
> 64
5172 || (pos
+ size
- 1) > 63)
5174 as_bad (_("Improper extract size (%lu, position %lu)"),
5179 if (size
<= 32 && pos
< 32)
5184 else if (size
<= 32)
5194 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5203 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5205 as_bad (_("Unsupported large constant"));
5210 pos
= (unsigned long) imm_expr
.X_add_number
;
5211 size
= (unsigned long) imm2_expr
.X_add_number
;
5216 as_bad (_("Improper position (%lu)"), pos
);
5219 if (size
== 0 || size
> 64
5220 || (pos
+ size
- 1) > 63)
5222 as_bad (_("Improper insert size (%lu, position %lu)"),
5227 if (pos
< 32 && (pos
+ size
- 1) < 32)
5242 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5259 as_warn (_("Divide by zero."));
5261 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5263 macro_build (NULL
, "break", "c", 7);
5270 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5271 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5275 expr1
.X_add_number
= 8;
5276 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5277 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5278 macro_build (NULL
, "break", "c", 7);
5280 expr1
.X_add_number
= -1;
5282 load_register (AT
, &expr1
, dbl
);
5283 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5284 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5287 expr1
.X_add_number
= 1;
5288 load_register (AT
, &expr1
, dbl
);
5289 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5293 expr1
.X_add_number
= 0x80000000;
5294 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5298 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5299 /* We want to close the noreorder block as soon as possible, so
5300 that later insns are available for delay slot filling. */
5305 expr1
.X_add_number
= 8;
5306 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5307 macro_build (NULL
, "nop", "", 0);
5309 /* We want to close the noreorder block as soon as possible, so
5310 that later insns are available for delay slot filling. */
5313 macro_build (NULL
, "break", "c", 6);
5315 macro_build (NULL
, s
, "d", dreg
);
5354 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5356 as_warn (_("Divide by zero."));
5358 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5360 macro_build (NULL
, "break", "c", 7);
5363 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5365 if (strcmp (s2
, "mflo") == 0)
5366 move_register (dreg
, sreg
);
5368 move_register (dreg
, 0);
5371 if (imm_expr
.X_op
== O_constant
5372 && imm_expr
.X_add_number
== -1
5373 && s
[strlen (s
) - 1] != 'u')
5375 if (strcmp (s2
, "mflo") == 0)
5377 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5380 move_register (dreg
, 0);
5385 load_register (AT
, &imm_expr
, dbl
);
5386 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5387 macro_build (NULL
, s2
, "d", dreg
);
5409 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5410 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5411 /* We want to close the noreorder block as soon as possible, so
5412 that later insns are available for delay slot filling. */
5417 expr1
.X_add_number
= 8;
5418 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5419 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5421 /* We want to close the noreorder block as soon as possible, so
5422 that later insns are available for delay slot filling. */
5424 macro_build (NULL
, "break", "c", 7);
5426 macro_build (NULL
, s2
, "d", dreg
);
5438 /* Load the address of a symbol into a register. If breg is not
5439 zero, we then add a base register to it. */
5441 if (dbl
&& HAVE_32BIT_GPRS
)
5442 as_warn (_("dla used to load 32-bit register"));
5444 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5445 as_warn (_("la used to load 64-bit address"));
5447 if (offset_expr
.X_op
== O_constant
5448 && offset_expr
.X_add_number
>= -0x8000
5449 && offset_expr
.X_add_number
< 0x8000)
5451 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5452 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5456 if (mips_opts
.at
&& (treg
== breg
))
5466 if (offset_expr
.X_op
!= O_symbol
5467 && offset_expr
.X_op
!= O_constant
)
5469 as_bad (_("expression too complex"));
5470 offset_expr
.X_op
= O_constant
;
5473 if (offset_expr
.X_op
== O_constant
)
5474 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5475 else if (mips_pic
== NO_PIC
)
5477 /* If this is a reference to a GP relative symbol, we want
5478 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5480 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5481 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5482 If we have a constant, we need two instructions anyhow,
5483 so we may as well always use the latter form.
5485 With 64bit address space and a usable $at we want
5486 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5487 lui $at,<sym> (BFD_RELOC_HI16_S)
5488 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5489 daddiu $at,<sym> (BFD_RELOC_LO16)
5491 daddu $tempreg,$tempreg,$at
5493 If $at is already in use, we use a path which is suboptimal
5494 on superscalar processors.
5495 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5496 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5498 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5500 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5502 For GP relative symbols in 64bit address space we can use
5503 the same sequence as in 32bit address space. */
5504 if (HAVE_64BIT_SYMBOLS
)
5506 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5507 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5509 relax_start (offset_expr
.X_add_symbol
);
5510 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5511 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5515 if (used_at
== 0 && mips_opts
.at
)
5517 macro_build (&offset_expr
, "lui", "t,u",
5518 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5519 macro_build (&offset_expr
, "lui", "t,u",
5520 AT
, BFD_RELOC_HI16_S
);
5521 macro_build (&offset_expr
, "daddiu", "t,r,j",
5522 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5523 macro_build (&offset_expr
, "daddiu", "t,r,j",
5524 AT
, AT
, BFD_RELOC_LO16
);
5525 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5526 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5531 macro_build (&offset_expr
, "lui", "t,u",
5532 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5533 macro_build (&offset_expr
, "daddiu", "t,r,j",
5534 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5535 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5536 macro_build (&offset_expr
, "daddiu", "t,r,j",
5537 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5538 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5539 macro_build (&offset_expr
, "daddiu", "t,r,j",
5540 tempreg
, tempreg
, BFD_RELOC_LO16
);
5543 if (mips_relax
.sequence
)
5548 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5549 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5551 relax_start (offset_expr
.X_add_symbol
);
5552 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5553 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5556 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5557 as_bad (_("offset too large"));
5558 macro_build_lui (&offset_expr
, tempreg
);
5559 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5560 tempreg
, tempreg
, BFD_RELOC_LO16
);
5561 if (mips_relax
.sequence
)
5565 else if (!mips_big_got
&& !HAVE_NEWABI
)
5567 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5569 /* If this is a reference to an external symbol, and there
5570 is no constant, we want
5571 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5572 or for lca or if tempreg is PIC_CALL_REG
5573 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5574 For a local symbol, we want
5575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5577 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5579 If we have a small constant, and this is a reference to
5580 an external symbol, we want
5581 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5583 addiu $tempreg,$tempreg,<constant>
5584 For a local symbol, we want the same instruction
5585 sequence, but we output a BFD_RELOC_LO16 reloc on the
5588 If we have a large constant, and this is a reference to
5589 an external symbol, we want
5590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5591 lui $at,<hiconstant>
5592 addiu $at,$at,<loconstant>
5593 addu $tempreg,$tempreg,$at
5594 For a local symbol, we want the same instruction
5595 sequence, but we output a BFD_RELOC_LO16 reloc on the
5599 if (offset_expr
.X_add_number
== 0)
5601 if (mips_pic
== SVR4_PIC
5603 && (call
|| tempreg
== PIC_CALL_REG
))
5604 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5606 relax_start (offset_expr
.X_add_symbol
);
5607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5608 lw_reloc_type
, mips_gp_register
);
5611 /* We're going to put in an addu instruction using
5612 tempreg, so we may as well insert the nop right
5617 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5618 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5620 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5621 tempreg
, tempreg
, BFD_RELOC_LO16
);
5623 /* FIXME: If breg == 0, and the next instruction uses
5624 $tempreg, then if this variant case is used an extra
5625 nop will be generated. */
5627 else if (offset_expr
.X_add_number
>= -0x8000
5628 && offset_expr
.X_add_number
< 0x8000)
5630 load_got_offset (tempreg
, &offset_expr
);
5632 add_got_offset (tempreg
, &offset_expr
);
5636 expr1
.X_add_number
= offset_expr
.X_add_number
;
5637 offset_expr
.X_add_number
=
5638 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5639 load_got_offset (tempreg
, &offset_expr
);
5640 offset_expr
.X_add_number
= expr1
.X_add_number
;
5641 /* If we are going to add in a base register, and the
5642 target register and the base register are the same,
5643 then we are using AT as a temporary register. Since
5644 we want to load the constant into AT, we add our
5645 current AT (from the global offset table) and the
5646 register into the register now, and pretend we were
5647 not using a base register. */
5651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5656 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5660 else if (!mips_big_got
&& HAVE_NEWABI
)
5662 int add_breg_early
= 0;
5664 /* If this is a reference to an external, and there is no
5665 constant, or local symbol (*), with or without a
5667 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5668 or for lca or if tempreg is PIC_CALL_REG
5669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5671 If we have a small constant, and this is a reference to
5672 an external symbol, we want
5673 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5674 addiu $tempreg,$tempreg,<constant>
5676 If we have a large constant, and this is a reference to
5677 an external symbol, we want
5678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5679 lui $at,<hiconstant>
5680 addiu $at,$at,<loconstant>
5681 addu $tempreg,$tempreg,$at
5683 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5684 local symbols, even though it introduces an additional
5687 if (offset_expr
.X_add_number
)
5689 expr1
.X_add_number
= offset_expr
.X_add_number
;
5690 offset_expr
.X_add_number
= 0;
5692 relax_start (offset_expr
.X_add_symbol
);
5693 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5694 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5696 if (expr1
.X_add_number
>= -0x8000
5697 && expr1
.X_add_number
< 0x8000)
5699 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5700 tempreg
, tempreg
, BFD_RELOC_LO16
);
5702 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5706 /* If we are going to add in a base register, and the
5707 target register and the base register are the same,
5708 then we are using AT as a temporary register. Since
5709 we want to load the constant into AT, we add our
5710 current AT (from the global offset table) and the
5711 register into the register now, and pretend we were
5712 not using a base register. */
5717 assert (tempreg
== AT
);
5718 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5724 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5725 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5731 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5734 offset_expr
.X_add_number
= expr1
.X_add_number
;
5736 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5737 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5740 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5741 treg
, tempreg
, breg
);
5747 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5749 relax_start (offset_expr
.X_add_symbol
);
5750 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5751 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5753 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5754 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5759 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5760 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5763 else if (mips_big_got
&& !HAVE_NEWABI
)
5766 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5767 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5768 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5770 /* This is the large GOT case. If this is a reference to an
5771 external symbol, and there is no constant, we want
5772 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5773 addu $tempreg,$tempreg,$gp
5774 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5775 or for lca or if tempreg is PIC_CALL_REG
5776 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5777 addu $tempreg,$tempreg,$gp
5778 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5779 For a local symbol, we want
5780 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5782 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5784 If we have a small constant, and this is a reference to
5785 an external symbol, we want
5786 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5787 addu $tempreg,$tempreg,$gp
5788 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5790 addiu $tempreg,$tempreg,<constant>
5791 For a local symbol, we want
5792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5794 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5796 If we have a large constant, and this is a reference to
5797 an external symbol, we want
5798 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5799 addu $tempreg,$tempreg,$gp
5800 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5801 lui $at,<hiconstant>
5802 addiu $at,$at,<loconstant>
5803 addu $tempreg,$tempreg,$at
5804 For a local symbol, we want
5805 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5806 lui $at,<hiconstant>
5807 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5808 addu $tempreg,$tempreg,$at
5811 expr1
.X_add_number
= offset_expr
.X_add_number
;
5812 offset_expr
.X_add_number
= 0;
5813 relax_start (offset_expr
.X_add_symbol
);
5814 gpdelay
= reg_needs_delay (mips_gp_register
);
5815 if (expr1
.X_add_number
== 0 && breg
== 0
5816 && (call
|| tempreg
== PIC_CALL_REG
))
5818 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5819 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5821 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5822 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5823 tempreg
, tempreg
, mips_gp_register
);
5824 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5825 tempreg
, lw_reloc_type
, tempreg
);
5826 if (expr1
.X_add_number
== 0)
5830 /* We're going to put in an addu instruction using
5831 tempreg, so we may as well insert the nop right
5836 else if (expr1
.X_add_number
>= -0x8000
5837 && expr1
.X_add_number
< 0x8000)
5840 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5841 tempreg
, tempreg
, BFD_RELOC_LO16
);
5847 /* If we are going to add in a base register, and the
5848 target register and the base register are the same,
5849 then we are using AT as a temporary register. Since
5850 we want to load the constant into AT, we add our
5851 current AT (from the global offset table) and the
5852 register into the register now, and pretend we were
5853 not using a base register. */
5858 assert (tempreg
== AT
);
5860 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5865 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5866 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5870 offset_expr
.X_add_number
=
5871 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5876 /* This is needed because this instruction uses $gp, but
5877 the first instruction on the main stream does not. */
5878 macro_build (NULL
, "nop", "");
5881 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5882 local_reloc_type
, mips_gp_register
);
5883 if (expr1
.X_add_number
>= -0x8000
5884 && expr1
.X_add_number
< 0x8000)
5887 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5888 tempreg
, tempreg
, BFD_RELOC_LO16
);
5889 /* FIXME: If add_number is 0, and there was no base
5890 register, the external symbol case ended with a load,
5891 so if the symbol turns out to not be external, and
5892 the next instruction uses tempreg, an unnecessary nop
5893 will be inserted. */
5899 /* We must add in the base register now, as in the
5900 external symbol case. */
5901 assert (tempreg
== AT
);
5903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5906 /* We set breg to 0 because we have arranged to add
5907 it in in both cases. */
5911 macro_build_lui (&expr1
, AT
);
5912 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5913 AT
, AT
, BFD_RELOC_LO16
);
5914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5915 tempreg
, tempreg
, AT
);
5920 else if (mips_big_got
&& HAVE_NEWABI
)
5922 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5923 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5924 int add_breg_early
= 0;
5926 /* This is the large GOT case. If this is a reference to an
5927 external symbol, and there is no constant, we want
5928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5929 add $tempreg,$tempreg,$gp
5930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5931 or for lca or if tempreg is PIC_CALL_REG
5932 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5933 add $tempreg,$tempreg,$gp
5934 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5936 If we have a small constant, and this is a reference to
5937 an external symbol, we want
5938 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5939 add $tempreg,$tempreg,$gp
5940 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5941 addi $tempreg,$tempreg,<constant>
5943 If we have a large constant, and this is a reference to
5944 an external symbol, we want
5945 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5946 addu $tempreg,$tempreg,$gp
5947 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5948 lui $at,<hiconstant>
5949 addi $at,$at,<loconstant>
5950 add $tempreg,$tempreg,$at
5952 If we have NewABI, and we know it's a local symbol, we want
5953 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5954 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5955 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5957 relax_start (offset_expr
.X_add_symbol
);
5959 expr1
.X_add_number
= offset_expr
.X_add_number
;
5960 offset_expr
.X_add_number
= 0;
5962 if (expr1
.X_add_number
== 0 && breg
== 0
5963 && (call
|| tempreg
== PIC_CALL_REG
))
5965 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5966 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5968 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5969 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5970 tempreg
, tempreg
, mips_gp_register
);
5971 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5972 tempreg
, lw_reloc_type
, tempreg
);
5974 if (expr1
.X_add_number
== 0)
5976 else if (expr1
.X_add_number
>= -0x8000
5977 && expr1
.X_add_number
< 0x8000)
5979 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5980 tempreg
, tempreg
, BFD_RELOC_LO16
);
5982 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5986 /* If we are going to add in a base register, and the
5987 target register and the base register are the same,
5988 then we are using AT as a temporary register. Since
5989 we want to load the constant into AT, we add our
5990 current AT (from the global offset table) and the
5991 register into the register now, and pretend we were
5992 not using a base register. */
5997 assert (tempreg
== AT
);
5998 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6004 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6005 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6010 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6013 offset_expr
.X_add_number
= expr1
.X_add_number
;
6014 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6015 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6016 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6017 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6020 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6021 treg
, tempreg
, breg
);
6031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6035 /* The j instruction may not be used in PIC code, since it
6036 requires an absolute address. We convert it to a b
6038 if (mips_pic
== NO_PIC
)
6039 macro_build (&offset_expr
, "j", "a");
6041 macro_build (&offset_expr
, "b", "p");
6044 /* The jal instructions must be handled as macros because when
6045 generating PIC code they expand to multi-instruction
6046 sequences. Normally they are simple instructions. */
6051 if (mips_pic
== NO_PIC
)
6052 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6055 if (sreg
!= PIC_CALL_REG
)
6056 as_warn (_("MIPS PIC call to register other than $25"));
6058 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6059 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6061 if (mips_cprestore_offset
< 0)
6062 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6065 if (! mips_frame_reg_valid
)
6067 as_warn (_("No .frame pseudo-op used in PIC code"));
6068 /* Quiet this warning. */
6069 mips_frame_reg_valid
= 1;
6071 if (! mips_cprestore_valid
)
6073 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6074 /* Quiet this warning. */
6075 mips_cprestore_valid
= 1;
6077 expr1
.X_add_number
= mips_cprestore_offset
;
6078 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6081 HAVE_64BIT_ADDRESSES
);
6089 if (mips_pic
== NO_PIC
)
6090 macro_build (&offset_expr
, "jal", "a");
6091 else if (mips_pic
== SVR4_PIC
)
6093 /* If this is a reference to an external symbol, and we are
6094 using a small GOT, we want
6095 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6099 lw $gp,cprestore($sp)
6100 The cprestore value is set using the .cprestore
6101 pseudo-op. If we are using a big GOT, we want
6102 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6104 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6108 lw $gp,cprestore($sp)
6109 If the symbol is not external, we want
6110 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6112 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6115 lw $gp,cprestore($sp)
6117 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6118 sequences above, minus nops, unless the symbol is local,
6119 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6125 relax_start (offset_expr
.X_add_symbol
);
6126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6127 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6130 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6131 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6137 relax_start (offset_expr
.X_add_symbol
);
6138 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6139 BFD_RELOC_MIPS_CALL_HI16
);
6140 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6141 PIC_CALL_REG
, mips_gp_register
);
6142 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6143 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6146 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6147 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6149 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6150 PIC_CALL_REG
, PIC_CALL_REG
,
6151 BFD_RELOC_MIPS_GOT_OFST
);
6155 macro_build_jalr (&offset_expr
);
6159 relax_start (offset_expr
.X_add_symbol
);
6162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6163 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6172 gpdelay
= reg_needs_delay (mips_gp_register
);
6173 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6174 BFD_RELOC_MIPS_CALL_HI16
);
6175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6176 PIC_CALL_REG
, mips_gp_register
);
6177 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6178 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6183 macro_build (NULL
, "nop", "");
6185 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6186 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6189 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6190 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6192 macro_build_jalr (&offset_expr
);
6194 if (mips_cprestore_offset
< 0)
6195 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6198 if (! mips_frame_reg_valid
)
6200 as_warn (_("No .frame pseudo-op used in PIC code"));
6201 /* Quiet this warning. */
6202 mips_frame_reg_valid
= 1;
6204 if (! mips_cprestore_valid
)
6206 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6207 /* Quiet this warning. */
6208 mips_cprestore_valid
= 1;
6210 if (mips_opts
.noreorder
)
6211 macro_build (NULL
, "nop", "");
6212 expr1
.X_add_number
= mips_cprestore_offset
;
6213 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6216 HAVE_64BIT_ADDRESSES
);
6220 else if (mips_pic
== VXWORKS_PIC
)
6221 as_bad (_("Non-PIC jump used in PIC library"));
6244 /* Itbl support may require additional care here. */
6249 /* Itbl support may require additional care here. */
6254 /* Itbl support may require additional care here. */
6259 /* Itbl support may require additional care here. */
6272 /* Itbl support may require additional care here. */
6277 /* Itbl support may require additional care here. */
6282 /* Itbl support may require additional care here. */
6302 if (breg
== treg
|| coproc
|| lr
)
6323 /* Itbl support may require additional care here. */
6328 /* Itbl support may require additional care here. */
6333 /* Itbl support may require additional care here. */
6338 /* Itbl support may require additional care here. */
6359 /* Itbl support may require additional care here. */
6363 /* Itbl support may require additional care here. */
6368 /* Itbl support may require additional care here. */
6381 && NO_ISA_COP (mips_opts
.arch
)
6382 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6384 as_bad (_("opcode not supported on this processor: %s"),
6385 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6389 /* Itbl support may require additional care here. */
6390 if (mask
== M_LWC1_AB
6391 || mask
== M_SWC1_AB
6392 || mask
== M_LDC1_AB
6393 || mask
== M_SDC1_AB
6397 else if (mask
== M_CACHE_AB
)
6404 if (offset_expr
.X_op
!= O_constant
6405 && offset_expr
.X_op
!= O_symbol
)
6407 as_bad (_("expression too complex"));
6408 offset_expr
.X_op
= O_constant
;
6411 if (HAVE_32BIT_ADDRESSES
6412 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6416 sprintf_vma (value
, offset_expr
.X_add_number
);
6417 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6420 /* A constant expression in PIC code can be handled just as it
6421 is in non PIC code. */
6422 if (offset_expr
.X_op
== O_constant
)
6424 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6425 & ~(bfd_vma
) 0xffff);
6426 normalize_address_expr (&expr1
);
6427 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6429 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6430 tempreg
, tempreg
, breg
);
6431 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6433 else if (mips_pic
== NO_PIC
)
6435 /* If this is a reference to a GP relative symbol, and there
6436 is no base register, we want
6437 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6438 Otherwise, if there is no base register, we want
6439 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6440 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6441 If we have a constant, we need two instructions anyhow,
6442 so we always use the latter form.
6444 If we have a base register, and this is a reference to a
6445 GP relative symbol, we want
6446 addu $tempreg,$breg,$gp
6447 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6449 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6450 addu $tempreg,$tempreg,$breg
6451 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6452 With a constant we always use the latter case.
6454 With 64bit address space and no base register and $at usable,
6456 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6457 lui $at,<sym> (BFD_RELOC_HI16_S)
6458 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6461 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6462 If we have a base register, we want
6463 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6464 lui $at,<sym> (BFD_RELOC_HI16_S)
6465 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6469 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6471 Without $at we can't generate the optimal path for superscalar
6472 processors here since this would require two temporary registers.
6473 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6474 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6476 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6478 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6479 If we have a base register, we want
6480 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6481 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6483 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6485 daddu $tempreg,$tempreg,$breg
6486 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6488 For GP relative symbols in 64bit address space we can use
6489 the same sequence as in 32bit address space. */
6490 if (HAVE_64BIT_SYMBOLS
)
6492 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6493 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6495 relax_start (offset_expr
.X_add_symbol
);
6498 macro_build (&offset_expr
, s
, fmt
, treg
,
6499 BFD_RELOC_GPREL16
, mips_gp_register
);
6503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6504 tempreg
, breg
, mips_gp_register
);
6505 macro_build (&offset_expr
, s
, fmt
, treg
,
6506 BFD_RELOC_GPREL16
, tempreg
);
6511 if (used_at
== 0 && mips_opts
.at
)
6513 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6514 BFD_RELOC_MIPS_HIGHEST
);
6515 macro_build (&offset_expr
, "lui", "t,u", AT
,
6517 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6518 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6520 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6521 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6522 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6523 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6529 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6530 BFD_RELOC_MIPS_HIGHEST
);
6531 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6532 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6533 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6534 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6535 tempreg
, BFD_RELOC_HI16_S
);
6536 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6538 macro_build (NULL
, "daddu", "d,v,t",
6539 tempreg
, tempreg
, breg
);
6540 macro_build (&offset_expr
, s
, fmt
, treg
,
6541 BFD_RELOC_LO16
, tempreg
);
6544 if (mips_relax
.sequence
)
6551 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6552 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6554 relax_start (offset_expr
.X_add_symbol
);
6555 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6559 macro_build_lui (&offset_expr
, tempreg
);
6560 macro_build (&offset_expr
, s
, fmt
, treg
,
6561 BFD_RELOC_LO16
, tempreg
);
6562 if (mips_relax
.sequence
)
6567 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6568 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6570 relax_start (offset_expr
.X_add_symbol
);
6571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6572 tempreg
, breg
, mips_gp_register
);
6573 macro_build (&offset_expr
, s
, fmt
, treg
,
6574 BFD_RELOC_GPREL16
, tempreg
);
6577 macro_build_lui (&offset_expr
, tempreg
);
6578 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6579 tempreg
, tempreg
, breg
);
6580 macro_build (&offset_expr
, s
, fmt
, treg
,
6581 BFD_RELOC_LO16
, tempreg
);
6582 if (mips_relax
.sequence
)
6586 else if (!mips_big_got
)
6588 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6590 /* If this is a reference to an external symbol, we want
6591 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6593 <op> $treg,0($tempreg)
6595 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6597 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6598 <op> $treg,0($tempreg)
6601 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6602 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6604 If there is a base register, we add it to $tempreg before
6605 the <op>. If there is a constant, we stick it in the
6606 <op> instruction. We don't handle constants larger than
6607 16 bits, because we have no way to load the upper 16 bits
6608 (actually, we could handle them for the subset of cases
6609 in which we are not using $at). */
6610 assert (offset_expr
.X_op
== O_symbol
);
6613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6614 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6616 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6617 tempreg
, tempreg
, breg
);
6618 macro_build (&offset_expr
, s
, fmt
, treg
,
6619 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6622 expr1
.X_add_number
= offset_expr
.X_add_number
;
6623 offset_expr
.X_add_number
= 0;
6624 if (expr1
.X_add_number
< -0x8000
6625 || expr1
.X_add_number
>= 0x8000)
6626 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6627 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6628 lw_reloc_type
, mips_gp_register
);
6630 relax_start (offset_expr
.X_add_symbol
);
6632 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6633 tempreg
, BFD_RELOC_LO16
);
6636 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6637 tempreg
, tempreg
, breg
);
6638 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6640 else if (mips_big_got
&& !HAVE_NEWABI
)
6644 /* If this is a reference to an external symbol, we want
6645 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6646 addu $tempreg,$tempreg,$gp
6647 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6648 <op> $treg,0($tempreg)
6650 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6652 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6653 <op> $treg,0($tempreg)
6654 If there is a base register, we add it to $tempreg before
6655 the <op>. If there is a constant, we stick it in the
6656 <op> instruction. We don't handle constants larger than
6657 16 bits, because we have no way to load the upper 16 bits
6658 (actually, we could handle them for the subset of cases
6659 in which we are not using $at). */
6660 assert (offset_expr
.X_op
== O_symbol
);
6661 expr1
.X_add_number
= offset_expr
.X_add_number
;
6662 offset_expr
.X_add_number
= 0;
6663 if (expr1
.X_add_number
< -0x8000
6664 || expr1
.X_add_number
>= 0x8000)
6665 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6666 gpdelay
= reg_needs_delay (mips_gp_register
);
6667 relax_start (offset_expr
.X_add_symbol
);
6668 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6669 BFD_RELOC_MIPS_GOT_HI16
);
6670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6672 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6673 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6676 macro_build (NULL
, "nop", "");
6677 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6678 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6680 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6681 tempreg
, BFD_RELOC_LO16
);
6685 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6686 tempreg
, tempreg
, breg
);
6687 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6689 else if (mips_big_got
&& HAVE_NEWABI
)
6691 /* If this is a reference to an external symbol, we want
6692 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6693 add $tempreg,$tempreg,$gp
6694 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6695 <op> $treg,<ofst>($tempreg)
6696 Otherwise, for local symbols, we want:
6697 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6698 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6699 assert (offset_expr
.X_op
== O_symbol
);
6700 expr1
.X_add_number
= offset_expr
.X_add_number
;
6701 offset_expr
.X_add_number
= 0;
6702 if (expr1
.X_add_number
< -0x8000
6703 || expr1
.X_add_number
>= 0x8000)
6704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6705 relax_start (offset_expr
.X_add_symbol
);
6706 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6707 BFD_RELOC_MIPS_GOT_HI16
);
6708 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6710 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6711 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6713 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6714 tempreg
, tempreg
, breg
);
6715 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6718 offset_expr
.X_add_number
= expr1
.X_add_number
;
6719 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6720 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6722 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6723 tempreg
, tempreg
, breg
);
6724 macro_build (&offset_expr
, s
, fmt
, treg
,
6725 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6735 load_register (treg
, &imm_expr
, 0);
6739 load_register (treg
, &imm_expr
, 1);
6743 if (imm_expr
.X_op
== O_constant
)
6746 load_register (AT
, &imm_expr
, 0);
6747 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6752 assert (offset_expr
.X_op
== O_symbol
6753 && strcmp (segment_name (S_GET_SEGMENT
6754 (offset_expr
.X_add_symbol
)),
6756 && offset_expr
.X_add_number
== 0);
6757 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6758 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6763 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6764 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6765 order 32 bits of the value and the low order 32 bits are either
6766 zero or in OFFSET_EXPR. */
6767 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6769 if (HAVE_64BIT_GPRS
)
6770 load_register (treg
, &imm_expr
, 1);
6775 if (target_big_endian
)
6787 load_register (hreg
, &imm_expr
, 0);
6790 if (offset_expr
.X_op
== O_absent
)
6791 move_register (lreg
, 0);
6794 assert (offset_expr
.X_op
== O_constant
);
6795 load_register (lreg
, &offset_expr
, 0);
6802 /* We know that sym is in the .rdata section. First we get the
6803 upper 16 bits of the address. */
6804 if (mips_pic
== NO_PIC
)
6806 macro_build_lui (&offset_expr
, AT
);
6811 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6812 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6816 /* Now we load the register(s). */
6817 if (HAVE_64BIT_GPRS
)
6820 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6825 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6828 /* FIXME: How in the world do we deal with the possible
6830 offset_expr
.X_add_number
+= 4;
6831 macro_build (&offset_expr
, "lw", "t,o(b)",
6832 treg
+ 1, BFD_RELOC_LO16
, AT
);
6838 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6839 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6840 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6841 the value and the low order 32 bits are either zero or in
6843 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6846 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6847 if (HAVE_64BIT_FPRS
)
6849 assert (HAVE_64BIT_GPRS
);
6850 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6854 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6855 if (offset_expr
.X_op
== O_absent
)
6856 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6859 assert (offset_expr
.X_op
== O_constant
);
6860 load_register (AT
, &offset_expr
, 0);
6861 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6867 assert (offset_expr
.X_op
== O_symbol
6868 && offset_expr
.X_add_number
== 0);
6869 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6870 if (strcmp (s
, ".lit8") == 0)
6872 if (mips_opts
.isa
!= ISA_MIPS1
)
6874 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6875 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6878 breg
= mips_gp_register
;
6879 r
= BFD_RELOC_MIPS_LITERAL
;
6884 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6886 if (mips_pic
!= NO_PIC
)
6887 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6888 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6891 /* FIXME: This won't work for a 64 bit address. */
6892 macro_build_lui (&offset_expr
, AT
);
6895 if (mips_opts
.isa
!= ISA_MIPS1
)
6897 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6898 treg
, BFD_RELOC_LO16
, AT
);
6907 /* Even on a big endian machine $fn comes before $fn+1. We have
6908 to adjust when loading from memory. */
6911 assert (mips_opts
.isa
== ISA_MIPS1
);
6912 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6913 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6914 /* FIXME: A possible overflow which I don't know how to deal
6916 offset_expr
.X_add_number
+= 4;
6917 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6918 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6923 * The MIPS assembler seems to check for X_add_number not
6924 * being double aligned and generating:
6927 * addiu at,at,%lo(foo+1)
6930 * But, the resulting address is the same after relocation so why
6931 * generate the extra instruction?
6933 /* Itbl support may require additional care here. */
6935 if (mips_opts
.isa
!= ISA_MIPS1
)
6946 if (mips_opts
.isa
!= ISA_MIPS1
)
6954 /* Itbl support may require additional care here. */
6959 if (HAVE_64BIT_GPRS
)
6970 if (HAVE_64BIT_GPRS
)
6980 if (offset_expr
.X_op
!= O_symbol
6981 && offset_expr
.X_op
!= O_constant
)
6983 as_bad (_("expression too complex"));
6984 offset_expr
.X_op
= O_constant
;
6987 if (HAVE_32BIT_ADDRESSES
6988 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6992 sprintf_vma (value
, offset_expr
.X_add_number
);
6993 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6996 /* Even on a big endian machine $fn comes before $fn+1. We have
6997 to adjust when loading from memory. We set coproc if we must
6998 load $fn+1 first. */
6999 /* Itbl support may require additional care here. */
7000 if (! target_big_endian
)
7003 if (mips_pic
== NO_PIC
7004 || offset_expr
.X_op
== O_constant
)
7006 /* If this is a reference to a GP relative symbol, we want
7007 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7008 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7009 If we have a base register, we use this
7011 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7012 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7013 If this is not a GP relative symbol, we want
7014 lui $at,<sym> (BFD_RELOC_HI16_S)
7015 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7016 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7017 If there is a base register, we add it to $at after the
7018 lui instruction. If there is a constant, we always use
7020 if (offset_expr
.X_op
== O_symbol
7021 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7022 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7024 relax_start (offset_expr
.X_add_symbol
);
7027 tempreg
= mips_gp_register
;
7031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7032 AT
, breg
, mips_gp_register
);
7037 /* Itbl support may require additional care here. */
7038 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7039 BFD_RELOC_GPREL16
, tempreg
);
7040 offset_expr
.X_add_number
+= 4;
7042 /* Set mips_optimize to 2 to avoid inserting an
7044 hold_mips_optimize
= mips_optimize
;
7046 /* Itbl support may require additional care here. */
7047 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7048 BFD_RELOC_GPREL16
, tempreg
);
7049 mips_optimize
= hold_mips_optimize
;
7053 /* We just generated two relocs. When tc_gen_reloc
7054 handles this case, it will skip the first reloc and
7055 handle the second. The second reloc already has an
7056 extra addend of 4, which we added above. We must
7057 subtract it out, and then subtract another 4 to make
7058 the first reloc come out right. The second reloc
7059 will come out right because we are going to add 4 to
7060 offset_expr when we build its instruction below.
7062 If we have a symbol, then we don't want to include
7063 the offset, because it will wind up being included
7064 when we generate the reloc. */
7066 if (offset_expr
.X_op
== O_constant
)
7067 offset_expr
.X_add_number
-= 8;
7070 offset_expr
.X_add_number
= -4;
7071 offset_expr
.X_op
= O_constant
;
7075 macro_build_lui (&offset_expr
, AT
);
7077 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7078 /* Itbl support may require additional care here. */
7079 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7080 BFD_RELOC_LO16
, AT
);
7081 /* FIXME: How do we handle overflow here? */
7082 offset_expr
.X_add_number
+= 4;
7083 /* Itbl support may require additional care here. */
7084 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7085 BFD_RELOC_LO16
, AT
);
7086 if (mips_relax
.sequence
)
7089 else if (!mips_big_got
)
7091 /* If this is a reference to an external symbol, we want
7092 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7097 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7099 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7100 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7101 If there is a base register we add it to $at before the
7102 lwc1 instructions. If there is a constant we include it
7103 in the lwc1 instructions. */
7105 expr1
.X_add_number
= offset_expr
.X_add_number
;
7106 if (expr1
.X_add_number
< -0x8000
7107 || expr1
.X_add_number
>= 0x8000 - 4)
7108 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7109 load_got_offset (AT
, &offset_expr
);
7112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7114 /* Set mips_optimize to 2 to avoid inserting an undesired
7116 hold_mips_optimize
= mips_optimize
;
7119 /* Itbl support may require additional care here. */
7120 relax_start (offset_expr
.X_add_symbol
);
7121 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7122 BFD_RELOC_LO16
, AT
);
7123 expr1
.X_add_number
+= 4;
7124 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7125 BFD_RELOC_LO16
, AT
);
7127 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7128 BFD_RELOC_LO16
, AT
);
7129 offset_expr
.X_add_number
+= 4;
7130 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7131 BFD_RELOC_LO16
, AT
);
7134 mips_optimize
= hold_mips_optimize
;
7136 else if (mips_big_got
)
7140 /* If this is a reference to an external symbol, we want
7141 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7143 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7148 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7150 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7151 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7152 If there is a base register we add it to $at before the
7153 lwc1 instructions. If there is a constant we include it
7154 in the lwc1 instructions. */
7156 expr1
.X_add_number
= offset_expr
.X_add_number
;
7157 offset_expr
.X_add_number
= 0;
7158 if (expr1
.X_add_number
< -0x8000
7159 || expr1
.X_add_number
>= 0x8000 - 4)
7160 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7161 gpdelay
= reg_needs_delay (mips_gp_register
);
7162 relax_start (offset_expr
.X_add_symbol
);
7163 macro_build (&offset_expr
, "lui", "t,u",
7164 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7165 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7166 AT
, AT
, mips_gp_register
);
7167 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7168 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7171 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7172 /* Itbl support may require additional care here. */
7173 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7174 BFD_RELOC_LO16
, AT
);
7175 expr1
.X_add_number
+= 4;
7177 /* Set mips_optimize to 2 to avoid inserting an undesired
7179 hold_mips_optimize
= mips_optimize
;
7181 /* Itbl support may require additional care here. */
7182 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7183 BFD_RELOC_LO16
, AT
);
7184 mips_optimize
= hold_mips_optimize
;
7185 expr1
.X_add_number
-= 4;
7188 offset_expr
.X_add_number
= expr1
.X_add_number
;
7190 macro_build (NULL
, "nop", "");
7191 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7192 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7195 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7196 /* Itbl support may require additional care here. */
7197 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7198 BFD_RELOC_LO16
, AT
);
7199 offset_expr
.X_add_number
+= 4;
7201 /* Set mips_optimize to 2 to avoid inserting an undesired
7203 hold_mips_optimize
= mips_optimize
;
7205 /* Itbl support may require additional care here. */
7206 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7207 BFD_RELOC_LO16
, AT
);
7208 mips_optimize
= hold_mips_optimize
;
7222 assert (HAVE_32BIT_ADDRESSES
);
7223 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7224 offset_expr
.X_add_number
+= 4;
7225 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7228 /* New code added to support COPZ instructions.
7229 This code builds table entries out of the macros in mip_opcodes.
7230 R4000 uses interlocks to handle coproc delays.
7231 Other chips (like the R3000) require nops to be inserted for delays.
7233 FIXME: Currently, we require that the user handle delays.
7234 In order to fill delay slots for non-interlocked chips,
7235 we must have a way to specify delays based on the coprocessor.
7236 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7237 What are the side-effects of the cop instruction?
7238 What cache support might we have and what are its effects?
7239 Both coprocessor & memory require delays. how long???
7240 What registers are read/set/modified?
7242 If an itbl is provided to interpret cop instructions,
7243 this knowledge can be encoded in the itbl spec. */
7257 if (NO_ISA_COP (mips_opts
.arch
)
7258 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7260 as_bad (_("opcode not supported on this processor: %s"),
7261 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7265 /* For now we just do C (same as Cz). The parameter will be
7266 stored in insn_opcode by mips_ip. */
7267 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7271 move_register (dreg
, sreg
);
7274 #ifdef LOSING_COMPILER
7276 /* Try and see if this is a new itbl instruction.
7277 This code builds table entries out of the macros in mip_opcodes.
7278 FIXME: For now we just assemble the expression and pass it's
7279 value along as a 32-bit immediate.
7280 We may want to have the assembler assemble this value,
7281 so that we gain the assembler's knowledge of delay slots,
7283 Would it be more efficient to use mask (id) here? */
7284 if (itbl_have_entries
7285 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7287 s
= ip
->insn_mo
->name
;
7289 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7290 macro_build (&immed_expr
, s
, "C");
7296 if (!mips_opts
.at
&& used_at
)
7297 as_bad (_("Macro used $at after \".set noat\""));
7301 macro2 (struct mips_cl_insn
*ip
)
7303 unsigned int treg
, sreg
, dreg
, breg
;
7304 unsigned int tempreg
;
7318 bfd_reloc_code_real_type r
;
7320 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7321 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7322 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7323 mask
= ip
->insn_mo
->mask
;
7325 expr1
.X_op
= O_constant
;
7326 expr1
.X_op_symbol
= NULL
;
7327 expr1
.X_add_symbol
= NULL
;
7328 expr1
.X_add_number
= 1;
7332 #endif /* LOSING_COMPILER */
7337 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7338 macro_build (NULL
, "mflo", "d", dreg
);
7344 /* The MIPS assembler some times generates shifts and adds. I'm
7345 not trying to be that fancy. GCC should do this for us
7348 load_register (AT
, &imm_expr
, dbl
);
7349 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7350 macro_build (NULL
, "mflo", "d", dreg
);
7366 load_register (AT
, &imm_expr
, dbl
);
7367 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7368 macro_build (NULL
, "mflo", "d", dreg
);
7369 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7370 macro_build (NULL
, "mfhi", "d", AT
);
7372 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7375 expr1
.X_add_number
= 8;
7376 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7377 macro_build (NULL
, "nop", "", 0);
7378 macro_build (NULL
, "break", "c", 6);
7381 macro_build (NULL
, "mflo", "d", dreg
);
7397 load_register (AT
, &imm_expr
, dbl
);
7398 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7399 sreg
, imm
? AT
: treg
);
7400 macro_build (NULL
, "mfhi", "d", AT
);
7401 macro_build (NULL
, "mflo", "d", dreg
);
7403 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7406 expr1
.X_add_number
= 8;
7407 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7408 macro_build (NULL
, "nop", "", 0);
7409 macro_build (NULL
, "break", "c", 6);
7415 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7426 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7427 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7431 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7432 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7433 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7434 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7438 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7449 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7450 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7454 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7455 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7456 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7457 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7465 if (imm_expr
.X_op
!= O_constant
)
7466 as_bad (_("Improper rotate count"));
7467 rot
= imm_expr
.X_add_number
& 0x3f;
7468 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7470 rot
= (64 - rot
) & 0x3f;
7472 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7474 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7479 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7482 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7483 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7486 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7487 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7488 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7496 if (imm_expr
.X_op
!= O_constant
)
7497 as_bad (_("Improper rotate count"));
7498 rot
= imm_expr
.X_add_number
& 0x1f;
7499 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7501 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7506 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7510 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7511 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7512 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7517 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7519 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7523 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7524 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7525 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7526 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7530 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7532 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7536 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7537 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7538 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7539 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7547 if (imm_expr
.X_op
!= O_constant
)
7548 as_bad (_("Improper rotate count"));
7549 rot
= imm_expr
.X_add_number
& 0x3f;
7550 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7553 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7555 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7560 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7563 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7564 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7567 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7568 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7569 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7577 if (imm_expr
.X_op
!= O_constant
)
7578 as_bad (_("Improper rotate count"));
7579 rot
= imm_expr
.X_add_number
& 0x1f;
7580 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7582 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7587 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7591 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7592 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7593 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7598 assert (mips_opts
.isa
== ISA_MIPS1
);
7599 /* Even on a big endian machine $fn comes before $fn+1. We have
7600 to adjust when storing to memory. */
7601 macro_build (&offset_expr
, "swc1", "T,o(b)",
7602 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7603 offset_expr
.X_add_number
+= 4;
7604 macro_build (&offset_expr
, "swc1", "T,o(b)",
7605 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7610 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7612 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7615 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7616 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7621 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7623 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7628 as_warn (_("Instruction %s: result is always false"),
7630 move_register (dreg
, 0);
7633 if (CPU_HAS_SEQ (mips_opts
.arch
)
7634 && -512 <= imm_expr
.X_add_number
7635 && imm_expr
.X_add_number
< 512)
7637 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7638 imm_expr
.X_add_number
);
7641 if (imm_expr
.X_op
== O_constant
7642 && imm_expr
.X_add_number
>= 0
7643 && imm_expr
.X_add_number
< 0x10000)
7645 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7647 else if (imm_expr
.X_op
== O_constant
7648 && imm_expr
.X_add_number
> -0x8000
7649 && imm_expr
.X_add_number
< 0)
7651 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7652 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7653 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7655 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7658 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7659 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7664 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7665 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7668 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7671 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7677 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7678 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7681 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7683 if (imm_expr
.X_op
== O_constant
7684 && imm_expr
.X_add_number
>= -0x8000
7685 && imm_expr
.X_add_number
< 0x8000)
7687 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7688 dreg
, sreg
, BFD_RELOC_LO16
);
7692 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7693 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7697 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7700 case M_SGT
: /* sreg > treg <==> treg < sreg */
7706 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7709 case M_SGT_I
: /* sreg > I <==> I < sreg */
7716 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7717 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7720 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7726 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7727 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7730 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7737 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7738 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7739 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7743 if (imm_expr
.X_op
== O_constant
7744 && imm_expr
.X_add_number
>= -0x8000
7745 && imm_expr
.X_add_number
< 0x8000)
7747 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7751 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7752 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7756 if (imm_expr
.X_op
== O_constant
7757 && imm_expr
.X_add_number
>= -0x8000
7758 && imm_expr
.X_add_number
< 0x8000)
7760 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7765 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7766 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7771 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7773 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7776 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7777 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7782 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7784 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7789 as_warn (_("Instruction %s: result is always true"),
7791 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7792 dreg
, 0, BFD_RELOC_LO16
);
7795 if (CPU_HAS_SEQ (mips_opts
.arch
)
7796 && -512 <= imm_expr
.X_add_number
7797 && imm_expr
.X_add_number
< 512)
7799 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7800 imm_expr
.X_add_number
);
7803 if (imm_expr
.X_op
== O_constant
7804 && imm_expr
.X_add_number
>= 0
7805 && imm_expr
.X_add_number
< 0x10000)
7807 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7809 else if (imm_expr
.X_op
== O_constant
7810 && imm_expr
.X_add_number
> -0x8000
7811 && imm_expr
.X_add_number
< 0)
7813 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7814 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7815 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7817 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7820 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7821 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7826 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7827 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7830 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7836 if (imm_expr
.X_op
== O_constant
7837 && imm_expr
.X_add_number
> -0x8000
7838 && imm_expr
.X_add_number
<= 0x8000)
7840 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7841 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7842 dreg
, sreg
, BFD_RELOC_LO16
);
7846 load_register (AT
, &imm_expr
, dbl
);
7847 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7853 if (imm_expr
.X_op
== O_constant
7854 && imm_expr
.X_add_number
> -0x8000
7855 && imm_expr
.X_add_number
<= 0x8000)
7857 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7858 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7859 dreg
, sreg
, BFD_RELOC_LO16
);
7863 load_register (AT
, &imm_expr
, dbl
);
7864 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7886 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7887 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7892 assert (mips_opts
.isa
== ISA_MIPS1
);
7894 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7895 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7898 * Is the double cfc1 instruction a bug in the mips assembler;
7899 * or is there a reason for it?
7902 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7903 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7904 macro_build (NULL
, "nop", "");
7905 expr1
.X_add_number
= 3;
7906 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7907 expr1
.X_add_number
= 2;
7908 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7909 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7910 macro_build (NULL
, "nop", "");
7911 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7913 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7914 macro_build (NULL
, "nop", "");
7925 if (offset_expr
.X_add_number
>= 0x7fff)
7926 as_bad (_("operand overflow"));
7927 if (! target_big_endian
)
7928 ++offset_expr
.X_add_number
;
7929 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7930 if (! target_big_endian
)
7931 --offset_expr
.X_add_number
;
7933 ++offset_expr
.X_add_number
;
7934 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7935 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7936 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7949 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7950 as_bad (_("operand overflow"));
7958 if (! target_big_endian
)
7959 offset_expr
.X_add_number
+= off
;
7960 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7961 if (! target_big_endian
)
7962 offset_expr
.X_add_number
-= off
;
7964 offset_expr
.X_add_number
+= off
;
7965 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7967 /* If necessary, move the result in tempreg the final destination. */
7968 if (treg
== tempreg
)
7970 /* Protect second load's delay slot. */
7972 move_register (treg
, tempreg
);
7986 load_address (AT
, &offset_expr
, &used_at
);
7988 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7989 if (! target_big_endian
)
7990 expr1
.X_add_number
= off
;
7992 expr1
.X_add_number
= 0;
7993 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7994 if (! target_big_endian
)
7995 expr1
.X_add_number
= 0;
7997 expr1
.X_add_number
= off
;
7998 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8004 load_address (AT
, &offset_expr
, &used_at
);
8006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8007 if (target_big_endian
)
8008 expr1
.X_add_number
= 0;
8009 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8010 treg
, BFD_RELOC_LO16
, AT
);
8011 if (target_big_endian
)
8012 expr1
.X_add_number
= 1;
8014 expr1
.X_add_number
= 0;
8015 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8016 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8017 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8022 if (offset_expr
.X_add_number
>= 0x7fff)
8023 as_bad (_("operand overflow"));
8024 if (target_big_endian
)
8025 ++offset_expr
.X_add_number
;
8026 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8027 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8028 if (target_big_endian
)
8029 --offset_expr
.X_add_number
;
8031 ++offset_expr
.X_add_number
;
8032 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8045 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8046 as_bad (_("operand overflow"));
8047 if (! target_big_endian
)
8048 offset_expr
.X_add_number
+= off
;
8049 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8050 if (! target_big_endian
)
8051 offset_expr
.X_add_number
-= off
;
8053 offset_expr
.X_add_number
+= off
;
8054 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8068 load_address (AT
, &offset_expr
, &used_at
);
8070 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8071 if (! target_big_endian
)
8072 expr1
.X_add_number
= off
;
8074 expr1
.X_add_number
= 0;
8075 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8076 if (! target_big_endian
)
8077 expr1
.X_add_number
= 0;
8079 expr1
.X_add_number
= off
;
8080 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8085 load_address (AT
, &offset_expr
, &used_at
);
8087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8088 if (! target_big_endian
)
8089 expr1
.X_add_number
= 0;
8090 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8091 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8092 if (! target_big_endian
)
8093 expr1
.X_add_number
= 1;
8095 expr1
.X_add_number
= 0;
8096 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8097 if (! target_big_endian
)
8098 expr1
.X_add_number
= 0;
8100 expr1
.X_add_number
= 1;
8101 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8102 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8103 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8107 /* FIXME: Check if this is one of the itbl macros, since they
8108 are added dynamically. */
8109 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8112 if (!mips_opts
.at
&& used_at
)
8113 as_bad (_("Macro used $at after \".set noat\""));
8116 /* Implement macros in mips16 mode. */
8119 mips16_macro (struct mips_cl_insn
*ip
)
8122 int xreg
, yreg
, zreg
, tmp
;
8125 const char *s
, *s2
, *s3
;
8127 mask
= ip
->insn_mo
->mask
;
8129 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8130 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8131 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8133 expr1
.X_op
= O_constant
;
8134 expr1
.X_op_symbol
= NULL
;
8135 expr1
.X_add_symbol
= NULL
;
8136 expr1
.X_add_number
= 1;
8156 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8157 expr1
.X_add_number
= 2;
8158 macro_build (&expr1
, "bnez", "x,p", yreg
);
8159 macro_build (NULL
, "break", "6", 7);
8161 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8162 since that causes an overflow. We should do that as well,
8163 but I don't see how to do the comparisons without a temporary
8166 macro_build (NULL
, s
, "x", zreg
);
8186 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8187 expr1
.X_add_number
= 2;
8188 macro_build (&expr1
, "bnez", "x,p", yreg
);
8189 macro_build (NULL
, "break", "6", 7);
8191 macro_build (NULL
, s2
, "x", zreg
);
8197 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8198 macro_build (NULL
, "mflo", "x", zreg
);
8206 if (imm_expr
.X_op
!= O_constant
)
8207 as_bad (_("Unsupported large constant"));
8208 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8209 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8213 if (imm_expr
.X_op
!= O_constant
)
8214 as_bad (_("Unsupported large constant"));
8215 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8216 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8220 if (imm_expr
.X_op
!= O_constant
)
8221 as_bad (_("Unsupported large constant"));
8222 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8223 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8245 goto do_reverse_branch
;
8249 goto do_reverse_branch
;
8261 goto do_reverse_branch
;
8272 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8273 macro_build (&offset_expr
, s2
, "p");
8300 goto do_addone_branch_i
;
8305 goto do_addone_branch_i
;
8320 goto do_addone_branch_i
;
8327 if (imm_expr
.X_op
!= O_constant
)
8328 as_bad (_("Unsupported large constant"));
8329 ++imm_expr
.X_add_number
;
8332 macro_build (&imm_expr
, s
, s3
, xreg
);
8333 macro_build (&offset_expr
, s2
, "p");
8337 expr1
.X_add_number
= 0;
8338 macro_build (&expr1
, "slti", "x,8", yreg
);
8340 move_register (xreg
, yreg
);
8341 expr1
.X_add_number
= 2;
8342 macro_build (&expr1
, "bteqz", "p");
8343 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8347 /* For consistency checking, verify that all bits are specified either
8348 by the match/mask part of the instruction definition, or by the
8351 validate_mips_insn (const struct mips_opcode
*opc
)
8353 const char *p
= opc
->args
;
8355 unsigned long used_bits
= opc
->mask
;
8357 if ((used_bits
& opc
->match
) != opc
->match
)
8359 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8360 opc
->name
, opc
->args
);
8363 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8373 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8374 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8375 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8376 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8377 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8378 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8379 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8380 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8381 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8382 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8383 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8384 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8385 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8387 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8388 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8389 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8390 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8391 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8392 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8393 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8394 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8395 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8396 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8399 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8400 c
, opc
->name
, opc
->args
);
8404 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8405 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8407 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8408 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8409 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8410 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8412 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8413 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8415 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8416 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8418 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8419 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8420 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8421 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8422 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8423 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8424 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8425 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8426 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8427 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8428 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8429 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8430 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8431 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8432 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8433 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8434 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8436 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8437 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8438 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8439 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8441 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8442 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8443 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8444 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8445 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8446 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8447 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8448 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8449 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8452 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8453 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8454 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8455 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8456 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8459 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8460 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8461 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8462 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8463 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8464 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8465 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8466 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8467 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8468 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8469 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8470 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8471 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8472 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8473 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8474 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8475 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8476 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8478 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8479 c
, opc
->name
, opc
->args
);
8483 if (used_bits
!= 0xffffffff)
8485 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8486 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8492 /* UDI immediates. */
8500 static const struct mips_immed mips_immed
[] = {
8501 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8502 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8503 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8504 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8508 /* Check whether an odd floating-point register is allowed. */
8510 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8512 const char *s
= insn
->name
;
8514 if (insn
->pinfo
== INSN_MACRO
)
8515 /* Let a macro pass, we'll catch it later when it is expanded. */
8518 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8520 /* Allow odd registers for single-precision ops. */
8521 switch (insn
->pinfo
& (FP_S
| FP_D
))
8525 return 1; /* both single precision - ok */
8527 return 0; /* both double precision - fail */
8532 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8533 s
= strchr (insn
->name
, '.');
8535 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8536 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8539 /* Single-precision coprocessor loads and moves are OK too. */
8540 if ((insn
->pinfo
& FP_S
)
8541 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8542 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8548 /* This routine assembles an instruction into its binary format. As a
8549 side effect, it sets one of the global variables imm_reloc or
8550 offset_reloc to the type of relocation to do if one of the operands
8551 is an address expression. */
8554 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8559 struct mips_opcode
*insn
;
8562 unsigned int lastregno
= 0;
8563 unsigned int lastpos
= 0;
8564 unsigned int limlo
, limhi
;
8567 offsetT min_range
, max_range
;
8573 /* If the instruction contains a '.', we first try to match an instruction
8574 including the '.'. Then we try again without the '.'. */
8576 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8579 /* If we stopped on whitespace, then replace the whitespace with null for
8580 the call to hash_find. Save the character we replaced just in case we
8581 have to re-parse the instruction. */
8588 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8590 /* If we didn't find the instruction in the opcode table, try again, but
8591 this time with just the instruction up to, but not including the
8595 /* Restore the character we overwrite above (if any). */
8599 /* Scan up to the first '.' or whitespace. */
8601 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8605 /* If we did not find a '.', then we can quit now. */
8608 insn_error
= "unrecognized opcode";
8612 /* Lookup the instruction in the hash table. */
8614 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8616 insn_error
= "unrecognized opcode";
8626 assert (strcmp (insn
->name
, str
) == 0);
8628 ok
= is_opcode_valid (insn
, FALSE
);
8631 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8632 && strcmp (insn
->name
, insn
[1].name
) == 0)
8641 static char buf
[100];
8643 _("opcode not supported on this processor: %s (%s)"),
8644 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8645 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8654 create_insn (ip
, insn
);
8657 for (args
= insn
->args
;; ++args
)
8661 s
+= strspn (s
, " \t");
8665 case '\0': /* end of args */
8670 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8671 my_getExpression (&imm_expr
, s
);
8672 check_absolute_expr (ip
, &imm_expr
);
8673 if ((unsigned long) imm_expr
.X_add_number
!= 1
8674 && (unsigned long) imm_expr
.X_add_number
!= 3)
8676 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8677 (unsigned long) imm_expr
.X_add_number
);
8679 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8680 imm_expr
.X_op
= O_absent
;
8684 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8685 my_getExpression (&imm_expr
, s
);
8686 check_absolute_expr (ip
, &imm_expr
);
8687 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8689 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8690 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8692 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8693 imm_expr
.X_op
= O_absent
;
8697 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8698 my_getExpression (&imm_expr
, s
);
8699 check_absolute_expr (ip
, &imm_expr
);
8700 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8702 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8703 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8705 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8706 imm_expr
.X_op
= O_absent
;
8710 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8711 my_getExpression (&imm_expr
, s
);
8712 check_absolute_expr (ip
, &imm_expr
);
8713 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8715 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8716 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8718 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8719 imm_expr
.X_op
= O_absent
;
8723 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8724 my_getExpression (&imm_expr
, s
);
8725 check_absolute_expr (ip
, &imm_expr
);
8726 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8728 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8729 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8731 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8732 imm_expr
.X_op
= O_absent
;
8736 case '7': /* four dsp accumulators in bits 11,12 */
8737 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8738 s
[3] >= '0' && s
[3] <= '3')
8742 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8746 as_bad (_("Invalid dsp acc register"));
8749 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8750 my_getExpression (&imm_expr
, s
);
8751 check_absolute_expr (ip
, &imm_expr
);
8752 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8754 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8756 (unsigned long) imm_expr
.X_add_number
);
8758 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8759 imm_expr
.X_op
= O_absent
;
8763 case '9': /* four dsp accumulators in bits 21,22 */
8764 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8765 s
[3] >= '0' && s
[3] <= '3')
8769 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8773 as_bad (_("Invalid dsp acc register"));
8776 case '0': /* dsp 6-bit signed immediate in bit 20 */
8777 my_getExpression (&imm_expr
, s
);
8778 check_absolute_expr (ip
, &imm_expr
);
8779 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8780 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8781 if (imm_expr
.X_add_number
< min_range
||
8782 imm_expr
.X_add_number
> max_range
)
8784 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8785 (long) min_range
, (long) max_range
,
8786 (long) imm_expr
.X_add_number
);
8788 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8789 imm_expr
.X_op
= O_absent
;
8793 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8794 my_getExpression (&imm_expr
, s
);
8795 check_absolute_expr (ip
, &imm_expr
);
8796 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8798 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8800 (unsigned long) imm_expr
.X_add_number
);
8802 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8803 imm_expr
.X_op
= O_absent
;
8807 case ':': /* dsp 7-bit signed immediate in bit 19 */
8808 my_getExpression (&imm_expr
, s
);
8809 check_absolute_expr (ip
, &imm_expr
);
8810 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8811 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8812 if (imm_expr
.X_add_number
< min_range
||
8813 imm_expr
.X_add_number
> max_range
)
8815 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8816 (long) min_range
, (long) max_range
,
8817 (long) imm_expr
.X_add_number
);
8819 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8820 imm_expr
.X_op
= O_absent
;
8824 case '@': /* dsp 10-bit signed immediate in bit 16 */
8825 my_getExpression (&imm_expr
, s
);
8826 check_absolute_expr (ip
, &imm_expr
);
8827 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8828 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8829 if (imm_expr
.X_add_number
< min_range
||
8830 imm_expr
.X_add_number
> max_range
)
8832 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8833 (long) min_range
, (long) max_range
,
8834 (long) imm_expr
.X_add_number
);
8836 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8837 imm_expr
.X_op
= O_absent
;
8841 case '!': /* MT usermode flag bit. */
8842 my_getExpression (&imm_expr
, s
);
8843 check_absolute_expr (ip
, &imm_expr
);
8844 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8845 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8846 (unsigned long) imm_expr
.X_add_number
);
8847 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8848 imm_expr
.X_op
= O_absent
;
8852 case '$': /* MT load high flag bit. */
8853 my_getExpression (&imm_expr
, s
);
8854 check_absolute_expr (ip
, &imm_expr
);
8855 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8856 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8857 (unsigned long) imm_expr
.X_add_number
);
8858 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8859 imm_expr
.X_op
= O_absent
;
8863 case '*': /* four dsp accumulators in bits 18,19 */
8864 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8865 s
[3] >= '0' && s
[3] <= '3')
8869 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8873 as_bad (_("Invalid dsp/smartmips acc register"));
8876 case '&': /* four dsp accumulators in bits 13,14 */
8877 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8878 s
[3] >= '0' && s
[3] <= '3')
8882 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8886 as_bad (_("Invalid dsp/smartmips acc register"));
8898 INSERT_OPERAND (RS
, *ip
, lastregno
);
8902 INSERT_OPERAND (RT
, *ip
, lastregno
);
8906 INSERT_OPERAND (FT
, *ip
, lastregno
);
8910 INSERT_OPERAND (FS
, *ip
, lastregno
);
8916 /* Handle optional base register.
8917 Either the base register is omitted or
8918 we must have a left paren. */
8919 /* This is dependent on the next operand specifier
8920 is a base register specification. */
8921 assert (args
[1] == 'b' || args
[1] == '5'
8922 || args
[1] == '-' || args
[1] == '4');
8926 case ')': /* these must match exactly */
8933 case '+': /* Opcode extension character. */
8936 case '1': /* UDI immediates. */
8941 const struct mips_immed
*imm
= mips_immed
;
8943 while (imm
->type
&& imm
->type
!= *args
)
8947 my_getExpression (&imm_expr
, s
);
8948 check_absolute_expr (ip
, &imm_expr
);
8949 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8951 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8952 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8953 (unsigned long) imm_expr
.X_add_number
,
8954 (unsigned long) imm_expr
.X_add_number
);
8955 imm_expr
.X_add_number
&= imm
->mask
;
8957 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8959 imm_expr
.X_op
= O_absent
;
8964 case 'A': /* ins/ext position, becomes LSB. */
8973 my_getExpression (&imm_expr
, s
);
8974 check_absolute_expr (ip
, &imm_expr
);
8975 if ((unsigned long) imm_expr
.X_add_number
< limlo
8976 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8978 as_bad (_("Improper position (%lu)"),
8979 (unsigned long) imm_expr
.X_add_number
);
8980 imm_expr
.X_add_number
= limlo
;
8982 lastpos
= imm_expr
.X_add_number
;
8983 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8984 imm_expr
.X_op
= O_absent
;
8988 case 'B': /* ins size, becomes MSB. */
8997 my_getExpression (&imm_expr
, s
);
8998 check_absolute_expr (ip
, &imm_expr
);
8999 /* Check for negative input so that small negative numbers
9000 will not succeed incorrectly. The checks against
9001 (pos+size) transitively check "size" itself,
9002 assuming that "pos" is reasonable. */
9003 if ((long) imm_expr
.X_add_number
< 0
9004 || ((unsigned long) imm_expr
.X_add_number
9006 || ((unsigned long) imm_expr
.X_add_number
9009 as_bad (_("Improper insert size (%lu, position %lu)"),
9010 (unsigned long) imm_expr
.X_add_number
,
9011 (unsigned long) lastpos
);
9012 imm_expr
.X_add_number
= limlo
- lastpos
;
9014 INSERT_OPERAND (INSMSB
, *ip
,
9015 lastpos
+ imm_expr
.X_add_number
- 1);
9016 imm_expr
.X_op
= O_absent
;
9020 case 'C': /* ext size, becomes MSBD. */
9033 my_getExpression (&imm_expr
, s
);
9034 check_absolute_expr (ip
, &imm_expr
);
9035 /* Check for negative input so that small negative numbers
9036 will not succeed incorrectly. The checks against
9037 (pos+size) transitively check "size" itself,
9038 assuming that "pos" is reasonable. */
9039 if ((long) imm_expr
.X_add_number
< 0
9040 || ((unsigned long) imm_expr
.X_add_number
9042 || ((unsigned long) imm_expr
.X_add_number
9045 as_bad (_("Improper extract size (%lu, position %lu)"),
9046 (unsigned long) imm_expr
.X_add_number
,
9047 (unsigned long) lastpos
);
9048 imm_expr
.X_add_number
= limlo
- lastpos
;
9050 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9051 imm_expr
.X_op
= O_absent
;
9056 /* +D is for disassembly only; never match. */
9060 /* "+I" is like "I", except that imm2_expr is used. */
9061 my_getExpression (&imm2_expr
, s
);
9062 if (imm2_expr
.X_op
!= O_big
9063 && imm2_expr
.X_op
!= O_constant
)
9064 insn_error
= _("absolute expression required");
9065 if (HAVE_32BIT_GPRS
)
9066 normalize_constant_expr (&imm2_expr
);
9070 case 'T': /* Coprocessor register. */
9071 /* +T is for disassembly only; never match. */
9074 case 't': /* Coprocessor register number. */
9075 if (s
[0] == '$' && ISDIGIT (s
[1]))
9085 while (ISDIGIT (*s
));
9087 as_bad (_("Invalid register number (%d)"), regno
);
9090 INSERT_OPERAND (RT
, *ip
, regno
);
9095 as_bad (_("Invalid coprocessor 0 register number"));
9099 /* bbit[01] and bbit[01]32 bit index. Give error if index
9100 is not in the valid range. */
9101 my_getExpression (&imm_expr
, s
);
9102 check_absolute_expr (ip
, &imm_expr
);
9103 if ((unsigned) imm_expr
.X_add_number
> 31)
9105 as_bad (_("Improper bit index (%lu)"),
9106 (unsigned long) imm_expr
.X_add_number
);
9107 imm_expr
.X_add_number
= 0;
9109 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9110 imm_expr
.X_op
= O_absent
;
9115 /* bbit[01] bit index when bbit is used but we generate
9116 bbit[01]32 because the index is over 32. Move to the
9117 next candidate if index is not in the valid range. */
9118 my_getExpression (&imm_expr
, s
);
9119 check_absolute_expr (ip
, &imm_expr
);
9120 if ((unsigned) imm_expr
.X_add_number
< 32
9121 || (unsigned) imm_expr
.X_add_number
> 63)
9123 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9124 imm_expr
.X_op
= O_absent
;
9129 /* cins, cins32, exts and exts32 position field. Give error
9130 if it's not in the valid range. */
9131 my_getExpression (&imm_expr
, s
);
9132 check_absolute_expr (ip
, &imm_expr
);
9133 if ((unsigned) imm_expr
.X_add_number
> 31)
9135 as_bad (_("Improper position (%lu)"),
9136 (unsigned long) imm_expr
.X_add_number
);
9137 imm_expr
.X_add_number
= 0;
9139 /* Make the pos explicit to simplify +S. */
9140 lastpos
= imm_expr
.X_add_number
+ 32;
9141 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9142 imm_expr
.X_op
= O_absent
;
9147 /* cins, cins32, exts and exts32 position field. Move to
9148 the next candidate if it's not in the valid range. */
9149 my_getExpression (&imm_expr
, s
);
9150 check_absolute_expr (ip
, &imm_expr
);
9151 if ((unsigned) imm_expr
.X_add_number
< 32
9152 || (unsigned) imm_expr
.X_add_number
> 63)
9154 lastpos
= imm_expr
.X_add_number
;
9155 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9156 imm_expr
.X_op
= O_absent
;
9161 /* cins and exts length-minus-one field. */
9162 my_getExpression (&imm_expr
, s
);
9163 check_absolute_expr (ip
, &imm_expr
);
9164 if ((unsigned long) imm_expr
.X_add_number
> 31)
9166 as_bad (_("Improper size (%lu)"),
9167 (unsigned long) imm_expr
.X_add_number
);
9168 imm_expr
.X_add_number
= 0;
9170 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9171 imm_expr
.X_op
= O_absent
;
9176 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9177 length-minus-one field. */
9178 my_getExpression (&imm_expr
, s
);
9179 check_absolute_expr (ip
, &imm_expr
);
9180 if ((long) imm_expr
.X_add_number
< 0
9181 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9183 as_bad (_("Improper size (%lu)"),
9184 (unsigned long) imm_expr
.X_add_number
);
9185 imm_expr
.X_add_number
= 0;
9187 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9188 imm_expr
.X_op
= O_absent
;
9193 /* seqi/snei immediate field. */
9194 my_getExpression (&imm_expr
, s
);
9195 check_absolute_expr (ip
, &imm_expr
);
9196 if ((long) imm_expr
.X_add_number
< -512
9197 || (long) imm_expr
.X_add_number
>= 512)
9199 as_bad (_("Improper immediate (%ld)"),
9200 (long) imm_expr
.X_add_number
);
9201 imm_expr
.X_add_number
= 0;
9203 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9204 imm_expr
.X_op
= O_absent
;
9209 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9210 *args
, insn
->name
, insn
->args
);
9211 /* Further processing is fruitless. */
9216 case '<': /* must be at least one digit */
9218 * According to the manual, if the shift amount is greater
9219 * than 31 or less than 0, then the shift amount should be
9220 * mod 32. In reality the mips assembler issues an error.
9221 * We issue a warning and mask out all but the low 5 bits.
9223 my_getExpression (&imm_expr
, s
);
9224 check_absolute_expr (ip
, &imm_expr
);
9225 if ((unsigned long) imm_expr
.X_add_number
> 31)
9226 as_warn (_("Improper shift amount (%lu)"),
9227 (unsigned long) imm_expr
.X_add_number
);
9228 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9229 imm_expr
.X_op
= O_absent
;
9233 case '>': /* shift amount minus 32 */
9234 my_getExpression (&imm_expr
, s
);
9235 check_absolute_expr (ip
, &imm_expr
);
9236 if ((unsigned long) imm_expr
.X_add_number
< 32
9237 || (unsigned long) imm_expr
.X_add_number
> 63)
9239 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9240 imm_expr
.X_op
= O_absent
;
9244 case 'k': /* cache code */
9245 case 'h': /* prefx code */
9246 case '1': /* sync type */
9247 my_getExpression (&imm_expr
, s
);
9248 check_absolute_expr (ip
, &imm_expr
);
9249 if ((unsigned long) imm_expr
.X_add_number
> 31)
9250 as_warn (_("Invalid value for `%s' (%lu)"),
9252 (unsigned long) imm_expr
.X_add_number
);
9254 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9255 else if (*args
== 'h')
9256 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9258 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9259 imm_expr
.X_op
= O_absent
;
9263 case 'c': /* break code */
9264 my_getExpression (&imm_expr
, s
);
9265 check_absolute_expr (ip
, &imm_expr
);
9266 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9267 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9269 (unsigned long) imm_expr
.X_add_number
);
9270 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9271 imm_expr
.X_op
= O_absent
;
9275 case 'q': /* lower break code */
9276 my_getExpression (&imm_expr
, s
);
9277 check_absolute_expr (ip
, &imm_expr
);
9278 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9279 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9281 (unsigned long) imm_expr
.X_add_number
);
9282 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9283 imm_expr
.X_op
= O_absent
;
9287 case 'B': /* 20-bit syscall/break code. */
9288 my_getExpression (&imm_expr
, s
);
9289 check_absolute_expr (ip
, &imm_expr
);
9290 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9291 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9293 (unsigned long) imm_expr
.X_add_number
);
9294 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9295 imm_expr
.X_op
= O_absent
;
9299 case 'C': /* Coprocessor code */
9300 my_getExpression (&imm_expr
, s
);
9301 check_absolute_expr (ip
, &imm_expr
);
9302 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9304 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9305 (unsigned long) imm_expr
.X_add_number
);
9306 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9308 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9309 imm_expr
.X_op
= O_absent
;
9313 case 'J': /* 19-bit wait code. */
9314 my_getExpression (&imm_expr
, s
);
9315 check_absolute_expr (ip
, &imm_expr
);
9316 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9318 as_warn (_("Illegal 19-bit code (%lu)"),
9319 (unsigned long) imm_expr
.X_add_number
);
9320 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9322 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9323 imm_expr
.X_op
= O_absent
;
9327 case 'P': /* Performance register. */
9328 my_getExpression (&imm_expr
, s
);
9329 check_absolute_expr (ip
, &imm_expr
);
9330 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9331 as_warn (_("Invalid performance register (%lu)"),
9332 (unsigned long) imm_expr
.X_add_number
);
9333 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9334 imm_expr
.X_op
= O_absent
;
9338 case 'G': /* Coprocessor destination register. */
9339 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9340 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9342 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9343 INSERT_OPERAND (RD
, *ip
, regno
);
9352 case 'b': /* base register */
9353 case 'd': /* destination register */
9354 case 's': /* source register */
9355 case 't': /* target register */
9356 case 'r': /* both target and source */
9357 case 'v': /* both dest and source */
9358 case 'w': /* both dest and target */
9359 case 'E': /* coprocessor target register */
9360 case 'K': /* 'rdhwr' destination register */
9361 case 'x': /* ignore register name */
9362 case 'z': /* must be zero register */
9363 case 'U': /* destination register (clo/clz). */
9364 case 'g': /* coprocessor destination register */
9366 if (*args
== 'E' || *args
== 'K')
9367 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9370 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9371 if (regno
== AT
&& mips_opts
.at
)
9373 if (mips_opts
.at
== ATREG
)
9374 as_warn (_("used $at without \".set noat\""));
9376 as_warn (_("used $%u with \".set at=$%u\""),
9377 regno
, mips_opts
.at
);
9387 if (c
== 'r' || c
== 'v' || c
== 'w')
9394 /* 'z' only matches $0. */
9395 if (c
== 'z' && regno
!= 0)
9398 if (c
== 's' && !strcmp (ip
->insn_mo
->name
, "jalr"))
9400 if (regno
== lastregno
)
9402 insn_error
= _("source and destinationations must be different");
9405 if (regno
== 31 && lastregno
== 0)
9407 insn_error
= _("a destination register must be supplied");
9411 /* Now that we have assembled one operand, we use the args string
9412 * to figure out where it goes in the instruction. */
9419 INSERT_OPERAND (RS
, *ip
, regno
);
9425 INSERT_OPERAND (RD
, *ip
, regno
);
9428 INSERT_OPERAND (RD
, *ip
, regno
);
9429 INSERT_OPERAND (RT
, *ip
, regno
);
9434 INSERT_OPERAND (RT
, *ip
, regno
);
9437 /* This case exists because on the r3000 trunc
9438 expands into a macro which requires a gp
9439 register. On the r6000 or r4000 it is
9440 assembled into a single instruction which
9441 ignores the register. Thus the insn version
9442 is MIPS_ISA2 and uses 'x', and the macro
9443 version is MIPS_ISA1 and uses 't'. */
9446 /* This case is for the div instruction, which
9447 acts differently if the destination argument
9448 is $0. This only matches $0, and is checked
9449 outside the switch. */
9452 /* Itbl operand; not yet implemented. FIXME ?? */
9454 /* What about all other operands like 'i', which
9455 can be specified in the opcode table? */
9464 INSERT_OPERAND (RS
, *ip
, lastregno
);
9467 INSERT_OPERAND (RT
, *ip
, lastregno
);
9472 case 'O': /* MDMX alignment immediate constant. */
9473 my_getExpression (&imm_expr
, s
);
9474 check_absolute_expr (ip
, &imm_expr
);
9475 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9476 as_warn ("Improper align amount (%ld), using low bits",
9477 (long) imm_expr
.X_add_number
);
9478 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9479 imm_expr
.X_op
= O_absent
;
9483 case 'Q': /* MDMX vector, element sel, or const. */
9486 /* MDMX Immediate. */
9487 my_getExpression (&imm_expr
, s
);
9488 check_absolute_expr (ip
, &imm_expr
);
9489 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9490 as_warn (_("Invalid MDMX Immediate (%ld)"),
9491 (long) imm_expr
.X_add_number
);
9492 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9493 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9494 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9496 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9497 imm_expr
.X_op
= O_absent
;
9501 /* Not MDMX Immediate. Fall through. */
9502 case 'X': /* MDMX destination register. */
9503 case 'Y': /* MDMX source register. */
9504 case 'Z': /* MDMX target register. */
9506 case 'D': /* floating point destination register */
9507 case 'S': /* floating point source register */
9508 case 'T': /* floating point target register */
9509 case 'R': /* floating point source register */
9514 || (mips_opts
.ase_mdmx
9515 && (ip
->insn_mo
->pinfo
& FP_D
)
9516 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9517 | INSN_COPROC_MEMORY_DELAY
9518 | INSN_LOAD_COPROC_DELAY
9519 | INSN_LOAD_MEMORY_DELAY
9520 | INSN_STORE_MEMORY
))))
9523 if (reg_lookup (&s
, rtype
, ®no
))
9525 if ((regno
& 1) != 0
9527 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9528 as_warn (_("Float register should be even, was %d"),
9536 if (c
== 'V' || c
== 'W')
9547 INSERT_OPERAND (FD
, *ip
, regno
);
9552 INSERT_OPERAND (FS
, *ip
, regno
);
9555 /* This is like 'Z', but also needs to fix the MDMX
9556 vector/scalar select bits. Note that the
9557 scalar immediate case is handled above. */
9560 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9561 int max_el
= (is_qh
? 3 : 7);
9563 my_getExpression(&imm_expr
, s
);
9564 check_absolute_expr (ip
, &imm_expr
);
9566 if (imm_expr
.X_add_number
> max_el
)
9567 as_bad(_("Bad element selector %ld"),
9568 (long) imm_expr
.X_add_number
);
9569 imm_expr
.X_add_number
&= max_el
;
9570 ip
->insn_opcode
|= (imm_expr
.X_add_number
9573 imm_expr
.X_op
= O_absent
;
9575 as_warn(_("Expecting ']' found '%s'"), s
);
9581 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9582 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9585 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9592 INSERT_OPERAND (FT
, *ip
, regno
);
9595 INSERT_OPERAND (FR
, *ip
, regno
);
9605 INSERT_OPERAND (FS
, *ip
, lastregno
);
9608 INSERT_OPERAND (FT
, *ip
, lastregno
);
9614 my_getExpression (&imm_expr
, s
);
9615 if (imm_expr
.X_op
!= O_big
9616 && imm_expr
.X_op
!= O_constant
)
9617 insn_error
= _("absolute expression required");
9618 if (HAVE_32BIT_GPRS
)
9619 normalize_constant_expr (&imm_expr
);
9624 my_getExpression (&offset_expr
, s
);
9625 normalize_address_expr (&offset_expr
);
9626 *imm_reloc
= BFD_RELOC_32
;
9639 unsigned char temp
[8];
9641 unsigned int length
;
9646 /* These only appear as the last operand in an
9647 instruction, and every instruction that accepts
9648 them in any variant accepts them in all variants.
9649 This means we don't have to worry about backing out
9650 any changes if the instruction does not match.
9652 The difference between them is the size of the
9653 floating point constant and where it goes. For 'F'
9654 and 'L' the constant is 64 bits; for 'f' and 'l' it
9655 is 32 bits. Where the constant is placed is based
9656 on how the MIPS assembler does things:
9659 f -- immediate value
9662 The .lit4 and .lit8 sections are only used if
9663 permitted by the -G argument.
9665 The code below needs to know whether the target register
9666 is 32 or 64 bits wide. It relies on the fact 'f' and
9667 'F' are used with GPR-based instructions and 'l' and
9668 'L' are used with FPR-based instructions. */
9670 f64
= *args
== 'F' || *args
== 'L';
9671 using_gprs
= *args
== 'F' || *args
== 'f';
9673 save_in
= input_line_pointer
;
9674 input_line_pointer
= s
;
9675 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9677 s
= input_line_pointer
;
9678 input_line_pointer
= save_in
;
9679 if (err
!= NULL
&& *err
!= '\0')
9681 as_bad (_("Bad floating point constant: %s"), err
);
9682 memset (temp
, '\0', sizeof temp
);
9683 length
= f64
? 8 : 4;
9686 assert (length
== (unsigned) (f64
? 8 : 4));
9690 && (g_switch_value
< 4
9691 || (temp
[0] == 0 && temp
[1] == 0)
9692 || (temp
[2] == 0 && temp
[3] == 0))))
9694 imm_expr
.X_op
= O_constant
;
9695 if (! target_big_endian
)
9696 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9698 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9701 && ! mips_disable_float_construction
9702 /* Constants can only be constructed in GPRs and
9703 copied to FPRs if the GPRs are at least as wide
9704 as the FPRs. Force the constant into memory if
9705 we are using 64-bit FPRs but the GPRs are only
9708 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9709 && ((temp
[0] == 0 && temp
[1] == 0)
9710 || (temp
[2] == 0 && temp
[3] == 0))
9711 && ((temp
[4] == 0 && temp
[5] == 0)
9712 || (temp
[6] == 0 && temp
[7] == 0)))
9714 /* The value is simple enough to load with a couple of
9715 instructions. If using 32-bit registers, set
9716 imm_expr to the high order 32 bits and offset_expr to
9717 the low order 32 bits. Otherwise, set imm_expr to
9718 the entire 64 bit constant. */
9719 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9721 imm_expr
.X_op
= O_constant
;
9722 offset_expr
.X_op
= O_constant
;
9723 if (! target_big_endian
)
9725 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9726 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9730 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9731 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9733 if (offset_expr
.X_add_number
== 0)
9734 offset_expr
.X_op
= O_absent
;
9736 else if (sizeof (imm_expr
.X_add_number
) > 4)
9738 imm_expr
.X_op
= O_constant
;
9739 if (! target_big_endian
)
9740 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9742 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9746 imm_expr
.X_op
= O_big
;
9747 imm_expr
.X_add_number
= 4;
9748 if (! target_big_endian
)
9750 generic_bignum
[0] = bfd_getl16 (temp
);
9751 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9752 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9753 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9757 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9758 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9759 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9760 generic_bignum
[3] = bfd_getb16 (temp
);
9766 const char *newname
;
9769 /* Switch to the right section. */
9771 subseg
= now_subseg
;
9774 default: /* unused default case avoids warnings. */
9776 newname
= RDATA_SECTION_NAME
;
9777 if (g_switch_value
>= 8)
9781 newname
= RDATA_SECTION_NAME
;
9784 assert (g_switch_value
>= 4);
9788 new_seg
= subseg_new (newname
, (subsegT
) 0);
9790 bfd_set_section_flags (stdoutput
, new_seg
,
9795 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9796 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9797 record_alignment (new_seg
, 4);
9799 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9801 as_bad (_("Can't use floating point insn in this section"));
9803 /* Set the argument to the current address in the
9805 offset_expr
.X_op
= O_symbol
;
9806 offset_expr
.X_add_symbol
=
9807 symbol_new ("L0\001", now_seg
,
9808 (valueT
) frag_now_fix (), frag_now
);
9809 offset_expr
.X_add_number
= 0;
9811 /* Put the floating point number into the section. */
9812 p
= frag_more ((int) length
);
9813 memcpy (p
, temp
, length
);
9815 /* Switch back to the original section. */
9816 subseg_set (seg
, subseg
);
9821 case 'i': /* 16 bit unsigned immediate */
9822 case 'j': /* 16 bit signed immediate */
9823 *imm_reloc
= BFD_RELOC_LO16
;
9824 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9827 offsetT minval
, maxval
;
9829 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9830 && strcmp (insn
->name
, insn
[1].name
) == 0);
9832 /* If the expression was written as an unsigned number,
9833 only treat it as signed if there are no more
9837 && sizeof (imm_expr
.X_add_number
) <= 4
9838 && imm_expr
.X_op
== O_constant
9839 && imm_expr
.X_add_number
< 0
9840 && imm_expr
.X_unsigned
9844 /* For compatibility with older assemblers, we accept
9845 0x8000-0xffff as signed 16-bit numbers when only
9846 signed numbers are allowed. */
9848 minval
= 0, maxval
= 0xffff;
9850 minval
= -0x8000, maxval
= 0x7fff;
9852 minval
= -0x8000, maxval
= 0xffff;
9854 if (imm_expr
.X_op
!= O_constant
9855 || imm_expr
.X_add_number
< minval
9856 || imm_expr
.X_add_number
> maxval
)
9860 if (imm_expr
.X_op
== O_constant
9861 || imm_expr
.X_op
== O_big
)
9862 as_bad (_("expression out of range"));
9868 case 'o': /* 16 bit offset */
9869 /* Check whether there is only a single bracketed expression
9870 left. If so, it must be the base register and the
9871 constant must be zero. */
9872 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9874 offset_expr
.X_op
= O_constant
;
9875 offset_expr
.X_add_number
= 0;
9879 /* If this value won't fit into a 16 bit offset, then go
9880 find a macro that will generate the 32 bit offset
9882 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9883 && (offset_expr
.X_op
!= O_constant
9884 || offset_expr
.X_add_number
>= 0x8000
9885 || offset_expr
.X_add_number
< -0x8000))
9891 case 'p': /* pc relative offset */
9892 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9893 my_getExpression (&offset_expr
, s
);
9897 case 'u': /* upper 16 bits */
9898 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9899 && imm_expr
.X_op
== O_constant
9900 && (imm_expr
.X_add_number
< 0
9901 || imm_expr
.X_add_number
>= 0x10000))
9902 as_bad (_("lui expression not in range 0..65535"));
9906 case 'a': /* 26 bit address */
9907 my_getExpression (&offset_expr
, s
);
9909 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9912 case 'N': /* 3 bit branch condition code */
9913 case 'M': /* 3 bit compare condition code */
9915 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9917 if (!reg_lookup (&s
, rtype
, ®no
))
9919 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9920 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9921 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9922 && (regno
& 1) != 0)
9923 as_warn(_("Condition code register should be even for %s, was %d"),
9925 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9926 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9927 && (regno
& 3) != 0)
9928 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9931 INSERT_OPERAND (BCC
, *ip
, regno
);
9933 INSERT_OPERAND (CCC
, *ip
, regno
);
9937 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9948 while (ISDIGIT (*s
));
9951 c
= 8; /* Invalid sel value. */
9954 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9955 ip
->insn_opcode
|= c
;
9959 /* Must be at least one digit. */
9960 my_getExpression (&imm_expr
, s
);
9961 check_absolute_expr (ip
, &imm_expr
);
9963 if ((unsigned long) imm_expr
.X_add_number
9964 > (unsigned long) OP_MASK_VECBYTE
)
9966 as_bad (_("bad byte vector index (%ld)"),
9967 (long) imm_expr
.X_add_number
);
9968 imm_expr
.X_add_number
= 0;
9971 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9972 imm_expr
.X_op
= O_absent
;
9977 my_getExpression (&imm_expr
, s
);
9978 check_absolute_expr (ip
, &imm_expr
);
9980 if ((unsigned long) imm_expr
.X_add_number
9981 > (unsigned long) OP_MASK_VECALIGN
)
9983 as_bad (_("bad byte vector index (%ld)"),
9984 (long) imm_expr
.X_add_number
);
9985 imm_expr
.X_add_number
= 0;
9988 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9989 imm_expr
.X_op
= O_absent
;
9994 as_bad (_("bad char = '%c'\n"), *args
);
9999 /* Args don't match. */
10000 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10001 !strcmp (insn
->name
, insn
[1].name
))
10005 insn_error
= _("illegal operands");
10009 *(--argsStart
) = save_c
;
10010 insn_error
= _("illegal operands");
10015 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10017 /* This routine assembles an instruction into its binary format when
10018 assembling for the mips16. As a side effect, it sets one of the
10019 global variables imm_reloc or offset_reloc to the type of
10020 relocation to do if one of the operands is an address expression.
10021 It also sets mips16_small and mips16_ext if the user explicitly
10022 requested a small or extended instruction. */
10025 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10029 struct mips_opcode
*insn
;
10031 unsigned int regno
;
10032 unsigned int lastregno
= 0;
10038 mips16_small
= FALSE
;
10039 mips16_ext
= FALSE
;
10041 for (s
= str
; ISLOWER (*s
); ++s
)
10053 if (s
[1] == 't' && s
[2] == ' ')
10056 mips16_small
= TRUE
;
10060 else if (s
[1] == 'e' && s
[2] == ' ')
10067 /* Fall through. */
10069 insn_error
= _("unknown opcode");
10073 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10074 mips16_small
= TRUE
;
10076 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10078 insn_error
= _("unrecognized opcode");
10087 assert (strcmp (insn
->name
, str
) == 0);
10089 ok
= is_opcode_valid_16 (insn
);
10092 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10093 && strcmp (insn
->name
, insn
[1].name
) == 0)
10102 static char buf
[100];
10104 _("opcode not supported on this processor: %s (%s)"),
10105 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10106 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10113 create_insn (ip
, insn
);
10114 imm_expr
.X_op
= O_absent
;
10115 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10116 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10117 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10118 imm2_expr
.X_op
= O_absent
;
10119 offset_expr
.X_op
= O_absent
;
10120 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10121 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10122 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10123 for (args
= insn
->args
; 1; ++args
)
10130 /* In this switch statement we call break if we did not find
10131 a match, continue if we did find a match, or return if we
10140 /* Stuff the immediate value in now, if we can. */
10141 if (imm_expr
.X_op
== O_constant
10142 && *imm_reloc
> BFD_RELOC_UNUSED
10143 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10144 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10145 && insn
->pinfo
!= INSN_MACRO
)
10149 switch (*offset_reloc
)
10151 case BFD_RELOC_MIPS16_HI16_S
:
10152 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10155 case BFD_RELOC_MIPS16_HI16
:
10156 tmp
= imm_expr
.X_add_number
>> 16;
10159 case BFD_RELOC_MIPS16_LO16
:
10160 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10164 case BFD_RELOC_UNUSED
:
10165 tmp
= imm_expr
.X_add_number
;
10171 *offset_reloc
= BFD_RELOC_UNUSED
;
10173 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10174 tmp
, TRUE
, mips16_small
,
10175 mips16_ext
, &ip
->insn_opcode
,
10176 &ip
->use_extend
, &ip
->extend
);
10177 imm_expr
.X_op
= O_absent
;
10178 *imm_reloc
= BFD_RELOC_UNUSED
;
10192 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10195 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10211 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10213 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10217 /* Fall through. */
10228 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10230 if (c
== 'v' || c
== 'w')
10233 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10235 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10246 if (c
== 'v' || c
== 'w')
10248 regno
= mips16_to_32_reg_map
[lastregno
];
10262 regno
= mips32_to_16_reg_map
[regno
];
10267 regno
= ILLEGAL_REG
;
10272 regno
= ILLEGAL_REG
;
10277 regno
= ILLEGAL_REG
;
10282 if (regno
== AT
&& mips_opts
.at
)
10284 if (mips_opts
.at
== ATREG
)
10285 as_warn (_("used $at without \".set noat\""));
10287 as_warn (_("used $%u with \".set at=$%u\""),
10288 regno
, mips_opts
.at
);
10296 if (regno
== ILLEGAL_REG
)
10303 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10307 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10310 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10313 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10319 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10322 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10323 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10333 if (strncmp (s
, "$pc", 3) == 0)
10350 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10353 if (imm_expr
.X_op
!= O_constant
)
10356 ip
->use_extend
= TRUE
;
10361 /* We need to relax this instruction. */
10362 *offset_reloc
= *imm_reloc
;
10363 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10368 *imm_reloc
= BFD_RELOC_UNUSED
;
10369 /* Fall through. */
10376 my_getExpression (&imm_expr
, s
);
10377 if (imm_expr
.X_op
== O_register
)
10379 /* What we thought was an expression turned out to
10382 if (s
[0] == '(' && args
[1] == '(')
10384 /* It looks like the expression was omitted
10385 before a register indirection, which means
10386 that the expression is implicitly zero. We
10387 still set up imm_expr, so that we handle
10388 explicit extensions correctly. */
10389 imm_expr
.X_op
= O_constant
;
10390 imm_expr
.X_add_number
= 0;
10391 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10398 /* We need to relax this instruction. */
10399 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10408 /* We use offset_reloc rather than imm_reloc for the PC
10409 relative operands. This lets macros with both
10410 immediate and address operands work correctly. */
10411 my_getExpression (&offset_expr
, s
);
10413 if (offset_expr
.X_op
== O_register
)
10416 /* We need to relax this instruction. */
10417 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10421 case '6': /* break code */
10422 my_getExpression (&imm_expr
, s
);
10423 check_absolute_expr (ip
, &imm_expr
);
10424 if ((unsigned long) imm_expr
.X_add_number
> 63)
10425 as_warn (_("Invalid value for `%s' (%lu)"),
10427 (unsigned long) imm_expr
.X_add_number
);
10428 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10429 imm_expr
.X_op
= O_absent
;
10433 case 'a': /* 26 bit address */
10434 my_getExpression (&offset_expr
, s
);
10436 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10437 ip
->insn_opcode
<<= 16;
10440 case 'l': /* register list for entry macro */
10441 case 'L': /* register list for exit macro */
10451 unsigned int freg
, reg1
, reg2
;
10453 while (*s
== ' ' || *s
== ',')
10455 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10457 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10461 as_bad (_("can't parse register list"));
10471 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10472 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10474 as_bad (_("invalid register list"));
10478 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10480 mask
&= ~ (7 << 3);
10483 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10485 mask
&= ~ (7 << 3);
10488 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10489 mask
|= (reg2
- 3) << 3;
10490 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10491 mask
|= (reg2
- 15) << 1;
10492 else if (reg1
== RA
&& reg2
== RA
)
10496 as_bad (_("invalid register list"));
10500 /* The mask is filled in in the opcode table for the
10501 benefit of the disassembler. We remove it before
10502 applying the actual mask. */
10503 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10504 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10508 case 'm': /* Register list for save insn. */
10509 case 'M': /* Register list for restore insn. */
10512 int framesz
= 0, seen_framesz
= 0;
10513 int args
= 0, statics
= 0, sregs
= 0;
10517 unsigned int reg1
, reg2
;
10519 SKIP_SPACE_TABS (s
);
10522 SKIP_SPACE_TABS (s
);
10524 my_getExpression (&imm_expr
, s
);
10525 if (imm_expr
.X_op
== O_constant
)
10527 /* Handle the frame size. */
10530 as_bad (_("more than one frame size in list"));
10534 framesz
= imm_expr
.X_add_number
;
10535 imm_expr
.X_op
= O_absent
;
10540 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10542 as_bad (_("can't parse register list"));
10554 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10557 as_bad (_("can't parse register list"));
10562 while (reg1
<= reg2
)
10564 if (reg1
>= 4 && reg1
<= 7)
10568 args
|= 1 << (reg1
- 4);
10570 /* statics $a0-$a3 */
10571 statics
|= 1 << (reg1
- 4);
10573 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10576 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10578 else if (reg1
== 31)
10580 /* Add $ra to insn. */
10585 as_bad (_("unexpected register in list"));
10593 /* Encode args/statics combination. */
10594 if (args
& statics
)
10595 as_bad (_("arg/static registers overlap"));
10596 else if (args
== 0xf)
10597 /* All $a0-$a3 are args. */
10598 opcode
|= MIPS16_ALL_ARGS
<< 16;
10599 else if (statics
== 0xf)
10600 /* All $a0-$a3 are statics. */
10601 opcode
|= MIPS16_ALL_STATICS
<< 16;
10604 int narg
= 0, nstat
= 0;
10606 /* Count arg registers. */
10613 as_bad (_("invalid arg register list"));
10615 /* Count static registers. */
10616 while (statics
& 0x8)
10618 statics
= (statics
<< 1) & 0xf;
10622 as_bad (_("invalid static register list"));
10624 /* Encode args/statics. */
10625 opcode
|= ((narg
<< 2) | nstat
) << 16;
10628 /* Encode $s0/$s1. */
10629 if (sregs
& (1 << 0)) /* $s0 */
10631 if (sregs
& (1 << 1)) /* $s1 */
10637 /* Count regs $s2-$s8. */
10645 as_bad (_("invalid static register list"));
10646 /* Encode $s2-$s8. */
10647 opcode
|= nsreg
<< 24;
10650 /* Encode frame size. */
10652 as_bad (_("missing frame size"));
10653 else if ((framesz
& 7) != 0 || framesz
< 0
10654 || framesz
> 0xff * 8)
10655 as_bad (_("invalid frame size"));
10656 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10659 opcode
|= (((framesz
& 0xf0) << 16)
10660 | (framesz
& 0x0f));
10663 /* Finally build the instruction. */
10664 if ((opcode
>> 16) != 0 || framesz
== 0)
10666 ip
->use_extend
= TRUE
;
10667 ip
->extend
= opcode
>> 16;
10669 ip
->insn_opcode
|= opcode
& 0x7f;
10673 case 'e': /* extend code */
10674 my_getExpression (&imm_expr
, s
);
10675 check_absolute_expr (ip
, &imm_expr
);
10676 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10678 as_warn (_("Invalid value for `%s' (%lu)"),
10680 (unsigned long) imm_expr
.X_add_number
);
10681 imm_expr
.X_add_number
&= 0x7ff;
10683 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10684 imm_expr
.X_op
= O_absent
;
10694 /* Args don't match. */
10695 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10696 strcmp (insn
->name
, insn
[1].name
) == 0)
10703 insn_error
= _("illegal operands");
10709 /* This structure holds information we know about a mips16 immediate
10712 struct mips16_immed_operand
10714 /* The type code used in the argument string in the opcode table. */
10716 /* The number of bits in the short form of the opcode. */
10718 /* The number of bits in the extended form of the opcode. */
10720 /* The amount by which the short form is shifted when it is used;
10721 for example, the sw instruction has a shift count of 2. */
10723 /* The amount by which the short form is shifted when it is stored
10724 into the instruction code. */
10726 /* Non-zero if the short form is unsigned. */
10728 /* Non-zero if the extended form is unsigned. */
10730 /* Non-zero if the value is PC relative. */
10734 /* The mips16 immediate operand types. */
10736 static const struct mips16_immed_operand mips16_immed_operands
[] =
10738 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10739 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10740 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10741 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10742 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10743 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10744 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10745 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10746 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10747 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10748 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10749 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10750 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10751 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10752 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10753 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10754 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10755 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10756 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10757 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10758 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10761 #define MIPS16_NUM_IMMED \
10762 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10764 /* Handle a mips16 instruction with an immediate value. This or's the
10765 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10766 whether an extended value is needed; if one is needed, it sets
10767 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10768 If SMALL is true, an unextended opcode was explicitly requested.
10769 If EXT is true, an extended opcode was explicitly requested. If
10770 WARN is true, warn if EXT does not match reality. */
10773 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10774 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10775 unsigned long *insn
, bfd_boolean
*use_extend
,
10776 unsigned short *extend
)
10778 const struct mips16_immed_operand
*op
;
10779 int mintiny
, maxtiny
;
10780 bfd_boolean needext
;
10782 op
= mips16_immed_operands
;
10783 while (op
->type
!= type
)
10786 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10791 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10794 maxtiny
= 1 << op
->nbits
;
10799 maxtiny
= (1 << op
->nbits
) - 1;
10804 mintiny
= - (1 << (op
->nbits
- 1));
10805 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10808 /* Branch offsets have an implicit 0 in the lowest bit. */
10809 if (type
== 'p' || type
== 'q')
10812 if ((val
& ((1 << op
->shift
) - 1)) != 0
10813 || val
< (mintiny
<< op
->shift
)
10814 || val
> (maxtiny
<< op
->shift
))
10819 if (warn
&& ext
&& ! needext
)
10820 as_warn_where (file
, line
,
10821 _("extended operand requested but not required"));
10822 if (small
&& needext
)
10823 as_bad_where (file
, line
, _("invalid unextended operand value"));
10825 if (small
|| (! ext
&& ! needext
))
10829 *use_extend
= FALSE
;
10830 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10831 insnval
<<= op
->op_shift
;
10836 long minext
, maxext
;
10842 maxext
= (1 << op
->extbits
) - 1;
10846 minext
= - (1 << (op
->extbits
- 1));
10847 maxext
= (1 << (op
->extbits
- 1)) - 1;
10849 if (val
< minext
|| val
> maxext
)
10850 as_bad_where (file
, line
,
10851 _("operand value out of range for instruction"));
10853 *use_extend
= TRUE
;
10854 if (op
->extbits
== 16)
10856 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10859 else if (op
->extbits
== 15)
10861 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10866 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10870 *extend
= (unsigned short) extval
;
10875 struct percent_op_match
10878 bfd_reloc_code_real_type reloc
;
10881 static const struct percent_op_match mips_percent_op
[] =
10883 {"%lo", BFD_RELOC_LO16
},
10885 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10886 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10887 {"%call16", BFD_RELOC_MIPS_CALL16
},
10888 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10889 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10890 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10891 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10892 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10893 {"%got", BFD_RELOC_MIPS_GOT16
},
10894 {"%gp_rel", BFD_RELOC_GPREL16
},
10895 {"%half", BFD_RELOC_16
},
10896 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10897 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10898 {"%neg", BFD_RELOC_MIPS_SUB
},
10899 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10900 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10901 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10902 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10903 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10904 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10905 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10907 {"%hi", BFD_RELOC_HI16_S
}
10910 static const struct percent_op_match mips16_percent_op
[] =
10912 {"%lo", BFD_RELOC_MIPS16_LO16
},
10913 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10914 {"%got", BFD_RELOC_MIPS16_GOT16
},
10915 {"%call16", BFD_RELOC_MIPS16_CALL16
},
10916 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10920 /* Return true if *STR points to a relocation operator. When returning true,
10921 move *STR over the operator and store its relocation code in *RELOC.
10922 Leave both *STR and *RELOC alone when returning false. */
10925 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10927 const struct percent_op_match
*percent_op
;
10930 if (mips_opts
.mips16
)
10932 percent_op
= mips16_percent_op
;
10933 limit
= ARRAY_SIZE (mips16_percent_op
);
10937 percent_op
= mips_percent_op
;
10938 limit
= ARRAY_SIZE (mips_percent_op
);
10941 for (i
= 0; i
< limit
; i
++)
10942 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10944 int len
= strlen (percent_op
[i
].str
);
10946 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10949 *str
+= strlen (percent_op
[i
].str
);
10950 *reloc
= percent_op
[i
].reloc
;
10952 /* Check whether the output BFD supports this relocation.
10953 If not, issue an error and fall back on something safe. */
10954 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10956 as_bad ("relocation %s isn't supported by the current ABI",
10957 percent_op
[i
].str
);
10958 *reloc
= BFD_RELOC_UNUSED
;
10966 /* Parse string STR as a 16-bit relocatable operand. Store the
10967 expression in *EP and the relocations in the array starting
10968 at RELOC. Return the number of relocation operators used.
10970 On exit, EXPR_END points to the first character after the expression. */
10973 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10976 bfd_reloc_code_real_type reversed_reloc
[3];
10977 size_t reloc_index
, i
;
10978 int crux_depth
, str_depth
;
10981 /* Search for the start of the main expression, recoding relocations
10982 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10983 of the main expression and with CRUX_DEPTH containing the number
10984 of open brackets at that point. */
10991 crux_depth
= str_depth
;
10993 /* Skip over whitespace and brackets, keeping count of the number
10995 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11000 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11001 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11003 my_getExpression (ep
, crux
);
11006 /* Match every open bracket. */
11007 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11011 if (crux_depth
> 0)
11012 as_bad ("unclosed '('");
11016 if (reloc_index
!= 0)
11018 prev_reloc_op_frag
= frag_now
;
11019 for (i
= 0; i
< reloc_index
; i
++)
11020 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11023 return reloc_index
;
11027 my_getExpression (expressionS
*ep
, char *str
)
11032 save_in
= input_line_pointer
;
11033 input_line_pointer
= str
;
11035 expr_end
= input_line_pointer
;
11036 input_line_pointer
= save_in
;
11038 /* If we are in mips16 mode, and this is an expression based on `.',
11039 then we bump the value of the symbol by 1 since that is how other
11040 text symbols are handled. We don't bother to handle complex
11041 expressions, just `.' plus or minus a constant. */
11042 if (mips_opts
.mips16
11043 && ep
->X_op
== O_symbol
11044 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
11045 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
11046 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
11047 && symbol_constant_p (ep
->X_add_symbol
)
11048 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
11049 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11053 md_atof (int type
, char *litP
, int *sizeP
)
11055 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11059 md_number_to_chars (char *buf
, valueT val
, int n
)
11061 if (target_big_endian
)
11062 number_to_chars_bigendian (buf
, val
, n
);
11064 number_to_chars_littleendian (buf
, val
, n
);
11068 static int support_64bit_objects(void)
11070 const char **list
, **l
;
11073 list
= bfd_target_list ();
11074 for (l
= list
; *l
!= NULL
; l
++)
11076 /* This is traditional mips */
11077 if (strcmp (*l
, "elf64-tradbigmips") == 0
11078 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11080 if (strcmp (*l
, "elf64-bigmips") == 0
11081 || strcmp (*l
, "elf64-littlemips") == 0)
11084 yes
= (*l
!= NULL
);
11088 #endif /* OBJ_ELF */
11090 const char *md_shortopts
= "O::g::G:";
11092 struct option md_longopts
[] =
11094 /* Options which specify architecture. */
11095 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
11096 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
11097 {"march", required_argument
, NULL
, OPTION_MARCH
},
11098 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
11099 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11100 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
11101 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11102 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11103 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
11104 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11105 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
11106 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11107 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
11108 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11109 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
11110 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11111 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
11112 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11113 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
11114 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11115 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
11116 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11117 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
11118 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11120 /* Options which specify Application Specific Extensions (ASEs). */
11121 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
11122 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
11123 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11124 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
11125 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11126 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
11127 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11128 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
11129 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11130 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
11131 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11132 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
11133 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11134 #define OPTION_DSP (OPTION_ASE_BASE + 6)
11135 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11136 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
11137 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11138 #define OPTION_MT (OPTION_ASE_BASE + 8)
11139 {"mmt", no_argument
, NULL
, OPTION_MT
},
11140 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
11141 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11142 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
11143 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11144 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
11145 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11146 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
11147 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11148 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
11149 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11151 /* Old-style architecture options. Don't add more of these. */
11152 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
11153 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
11154 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11155 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
11156 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11157 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
11158 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11159 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
11160 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11161 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
11162 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11163 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
11164 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11165 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
11166 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11167 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
11168 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11170 /* Options which enable bug fixes. */
11171 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
11172 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
11173 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11174 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
11175 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11176 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11177 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
11178 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
11179 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11180 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11181 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
11182 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
11183 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11184 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11186 /* Miscellaneous options. */
11187 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
11188 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
11189 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11190 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11191 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
11192 {"break", no_argument
, NULL
, OPTION_BREAK
},
11193 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11194 #define OPTION_EB (OPTION_MISC_BASE + 2)
11195 {"EB", no_argument
, NULL
, OPTION_EB
},
11196 #define OPTION_EL (OPTION_MISC_BASE + 3)
11197 {"EL", no_argument
, NULL
, OPTION_EL
},
11198 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
11199 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11200 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
11201 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11202 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
11203 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11204 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
11205 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11206 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
11207 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11208 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
11209 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11210 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
11211 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
11212 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11213 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11214 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
11215 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
11216 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11217 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11218 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
11219 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
11220 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11221 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11222 #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16)
11223 #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17)
11224 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11225 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11226 #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18)
11227 #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19)
11228 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11229 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11231 /* ELF-specific options. */
11233 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20)
11234 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
11235 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11236 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11237 #define OPTION_CALL_NONPIC (OPTION_ELF_BASE + 1)
11238 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11239 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 2)
11240 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11241 #define OPTION_XGOT (OPTION_ELF_BASE + 3)
11242 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11243 #define OPTION_MABI (OPTION_ELF_BASE + 4)
11244 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11245 #define OPTION_32 (OPTION_ELF_BASE + 5)
11246 {"32", no_argument
, NULL
, OPTION_32
},
11247 #define OPTION_N32 (OPTION_ELF_BASE + 6)
11248 {"n32", no_argument
, NULL
, OPTION_N32
},
11249 #define OPTION_64 (OPTION_ELF_BASE + 7)
11250 {"64", no_argument
, NULL
, OPTION_64
},
11251 #define OPTION_MDEBUG (OPTION_ELF_BASE + 8)
11252 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11253 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 9)
11254 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11255 #define OPTION_PDR (OPTION_ELF_BASE + 10)
11256 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11257 #define OPTION_NO_PDR (OPTION_ELF_BASE + 11)
11258 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11259 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 12)
11260 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11261 #endif /* OBJ_ELF */
11263 {NULL
, no_argument
, NULL
, 0}
11265 size_t md_longopts_size
= sizeof (md_longopts
);
11267 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11268 NEW_VALUE. Warn if another value was already specified. Note:
11269 we have to defer parsing the -march and -mtune arguments in order
11270 to handle 'from-abi' correctly, since the ABI might be specified
11271 in a later argument. */
11274 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11276 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11277 as_warn (_("A different %s was already specified, is now %s"),
11278 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11281 *string_ptr
= new_value
;
11285 md_parse_option (int c
, char *arg
)
11289 case OPTION_CONSTRUCT_FLOATS
:
11290 mips_disable_float_construction
= 0;
11293 case OPTION_NO_CONSTRUCT_FLOATS
:
11294 mips_disable_float_construction
= 1;
11306 target_big_endian
= 1;
11310 target_big_endian
= 0;
11316 else if (arg
[0] == '0')
11318 else if (arg
[0] == '1')
11328 mips_debug
= atoi (arg
);
11332 file_mips_isa
= ISA_MIPS1
;
11336 file_mips_isa
= ISA_MIPS2
;
11340 file_mips_isa
= ISA_MIPS3
;
11344 file_mips_isa
= ISA_MIPS4
;
11348 file_mips_isa
= ISA_MIPS5
;
11351 case OPTION_MIPS32
:
11352 file_mips_isa
= ISA_MIPS32
;
11355 case OPTION_MIPS32R2
:
11356 file_mips_isa
= ISA_MIPS32R2
;
11359 case OPTION_MIPS64R2
:
11360 file_mips_isa
= ISA_MIPS64R2
;
11363 case OPTION_MIPS64
:
11364 file_mips_isa
= ISA_MIPS64
;
11368 mips_set_option_string (&mips_tune_string
, arg
);
11372 mips_set_option_string (&mips_arch_string
, arg
);
11376 mips_set_option_string (&mips_arch_string
, "4650");
11377 mips_set_option_string (&mips_tune_string
, "4650");
11380 case OPTION_NO_M4650
:
11384 mips_set_option_string (&mips_arch_string
, "4010");
11385 mips_set_option_string (&mips_tune_string
, "4010");
11388 case OPTION_NO_M4010
:
11392 mips_set_option_string (&mips_arch_string
, "4100");
11393 mips_set_option_string (&mips_tune_string
, "4100");
11396 case OPTION_NO_M4100
:
11400 mips_set_option_string (&mips_arch_string
, "3900");
11401 mips_set_option_string (&mips_tune_string
, "3900");
11404 case OPTION_NO_M3900
:
11408 mips_opts
.ase_mdmx
= 1;
11411 case OPTION_NO_MDMX
:
11412 mips_opts
.ase_mdmx
= 0;
11416 mips_opts
.ase_dsp
= 1;
11417 mips_opts
.ase_dspr2
= 0;
11420 case OPTION_NO_DSP
:
11421 mips_opts
.ase_dsp
= 0;
11422 mips_opts
.ase_dspr2
= 0;
11426 mips_opts
.ase_dspr2
= 1;
11427 mips_opts
.ase_dsp
= 1;
11430 case OPTION_NO_DSPR2
:
11431 mips_opts
.ase_dspr2
= 0;
11432 mips_opts
.ase_dsp
= 0;
11436 mips_opts
.ase_mt
= 1;
11440 mips_opts
.ase_mt
= 0;
11443 case OPTION_MIPS16
:
11444 mips_opts
.mips16
= 1;
11445 mips_no_prev_insn ();
11448 case OPTION_NO_MIPS16
:
11449 mips_opts
.mips16
= 0;
11450 mips_no_prev_insn ();
11453 case OPTION_MIPS3D
:
11454 mips_opts
.ase_mips3d
= 1;
11457 case OPTION_NO_MIPS3D
:
11458 mips_opts
.ase_mips3d
= 0;
11461 case OPTION_SMARTMIPS
:
11462 mips_opts
.ase_smartmips
= 1;
11465 case OPTION_NO_SMARTMIPS
:
11466 mips_opts
.ase_smartmips
= 0;
11469 case OPTION_FIX_VR4120
:
11470 mips_fix_vr4120
= 1;
11473 case OPTION_NO_FIX_VR4120
:
11474 mips_fix_vr4120
= 0;
11477 case OPTION_FIX_VR4130
:
11478 mips_fix_vr4130
= 1;
11481 case OPTION_NO_FIX_VR4130
:
11482 mips_fix_vr4130
= 0;
11485 case OPTION_RELAX_BRANCH
:
11486 mips_relax_branch
= 1;
11489 case OPTION_NO_RELAX_BRANCH
:
11490 mips_relax_branch
= 0;
11493 case OPTION_MSHARED
:
11494 mips_in_shared
= TRUE
;
11497 case OPTION_MNO_SHARED
:
11498 mips_in_shared
= FALSE
;
11501 case OPTION_MSYM32
:
11502 mips_opts
.sym32
= TRUE
;
11505 case OPTION_MNO_SYM32
:
11506 mips_opts
.sym32
= FALSE
;
11510 /* When generating ELF code, we permit -KPIC and -call_shared to
11511 select SVR4_PIC, and -non_shared to select no PIC. This is
11512 intended to be compatible with Irix 5. */
11513 case OPTION_CALL_SHARED
:
11516 as_bad (_("-call_shared is supported only for ELF format"));
11519 mips_pic
= SVR4_PIC
;
11520 mips_abicalls
= TRUE
;
11523 case OPTION_CALL_NONPIC
:
11526 as_bad (_("-call_nonpic is supported only for ELF format"));
11530 mips_abicalls
= TRUE
;
11533 case OPTION_NON_SHARED
:
11536 as_bad (_("-non_shared is supported only for ELF format"));
11540 mips_abicalls
= FALSE
;
11543 /* The -xgot option tells the assembler to use 32 bit offsets
11544 when accessing the got in SVR4_PIC mode. It is for Irix
11549 #endif /* OBJ_ELF */
11552 g_switch_value
= atoi (arg
);
11557 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11562 as_bad (_("-32 is supported for ELF format only"));
11565 mips_abi
= O32_ABI
;
11571 as_bad (_("-n32 is supported for ELF format only"));
11574 mips_abi
= N32_ABI
;
11580 as_bad (_("-64 is supported for ELF format only"));
11583 mips_abi
= N64_ABI
;
11584 if (!support_64bit_objects())
11585 as_fatal (_("No compiled in support for 64 bit object file format"));
11587 #endif /* OBJ_ELF */
11590 file_mips_gp32
= 1;
11594 file_mips_gp32
= 0;
11598 file_mips_fp32
= 1;
11602 file_mips_fp32
= 0;
11605 case OPTION_SINGLE_FLOAT
:
11606 file_mips_single_float
= 1;
11609 case OPTION_DOUBLE_FLOAT
:
11610 file_mips_single_float
= 0;
11613 case OPTION_SOFT_FLOAT
:
11614 file_mips_soft_float
= 1;
11617 case OPTION_HARD_FLOAT
:
11618 file_mips_soft_float
= 0;
11625 as_bad (_("-mabi is supported for ELF format only"));
11628 if (strcmp (arg
, "32") == 0)
11629 mips_abi
= O32_ABI
;
11630 else if (strcmp (arg
, "o64") == 0)
11631 mips_abi
= O64_ABI
;
11632 else if (strcmp (arg
, "n32") == 0)
11633 mips_abi
= N32_ABI
;
11634 else if (strcmp (arg
, "64") == 0)
11636 mips_abi
= N64_ABI
;
11637 if (! support_64bit_objects())
11638 as_fatal (_("No compiled in support for 64 bit object file "
11641 else if (strcmp (arg
, "eabi") == 0)
11642 mips_abi
= EABI_ABI
;
11645 as_fatal (_("invalid abi -mabi=%s"), arg
);
11649 #endif /* OBJ_ELF */
11651 case OPTION_M7000_HILO_FIX
:
11652 mips_7000_hilo_fix
= TRUE
;
11655 case OPTION_MNO_7000_HILO_FIX
:
11656 mips_7000_hilo_fix
= FALSE
;
11660 case OPTION_MDEBUG
:
11661 mips_flag_mdebug
= TRUE
;
11664 case OPTION_NO_MDEBUG
:
11665 mips_flag_mdebug
= FALSE
;
11669 mips_flag_pdr
= TRUE
;
11672 case OPTION_NO_PDR
:
11673 mips_flag_pdr
= FALSE
;
11676 case OPTION_MVXWORKS_PIC
:
11677 mips_pic
= VXWORKS_PIC
;
11679 #endif /* OBJ_ELF */
11688 /* Set up globals to generate code for the ISA or processor
11689 described by INFO. */
11692 mips_set_architecture (const struct mips_cpu_info
*info
)
11696 file_mips_arch
= info
->cpu
;
11697 mips_opts
.arch
= info
->cpu
;
11698 mips_opts
.isa
= info
->isa
;
11703 /* Likewise for tuning. */
11706 mips_set_tune (const struct mips_cpu_info
*info
)
11709 mips_tune
= info
->cpu
;
11714 mips_after_parse_args (void)
11716 const struct mips_cpu_info
*arch_info
= 0;
11717 const struct mips_cpu_info
*tune_info
= 0;
11719 /* GP relative stuff not working for PE */
11720 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11722 if (g_switch_seen
&& g_switch_value
!= 0)
11723 as_bad (_("-G not supported in this configuration."));
11724 g_switch_value
= 0;
11727 if (mips_abi
== NO_ABI
)
11728 mips_abi
= MIPS_DEFAULT_ABI
;
11730 /* The following code determines the architecture and register size.
11731 Similar code was added to GCC 3.3 (see override_options() in
11732 config/mips/mips.c). The GAS and GCC code should be kept in sync
11733 as much as possible. */
11735 if (mips_arch_string
!= 0)
11736 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11738 if (file_mips_isa
!= ISA_UNKNOWN
)
11740 /* Handle -mipsN. At this point, file_mips_isa contains the
11741 ISA level specified by -mipsN, while arch_info->isa contains
11742 the -march selection (if any). */
11743 if (arch_info
!= 0)
11745 /* -march takes precedence over -mipsN, since it is more descriptive.
11746 There's no harm in specifying both as long as the ISA levels
11748 if (file_mips_isa
!= arch_info
->isa
)
11749 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11750 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11751 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11754 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11757 if (arch_info
== 0)
11758 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11760 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11761 as_bad ("-march=%s is not compatible with the selected ABI",
11764 mips_set_architecture (arch_info
);
11766 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11767 if (mips_tune_string
!= 0)
11768 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11770 if (tune_info
== 0)
11771 mips_set_tune (arch_info
);
11773 mips_set_tune (tune_info
);
11775 if (file_mips_gp32
>= 0)
11777 /* The user specified the size of the integer registers. Make sure
11778 it agrees with the ABI and ISA. */
11779 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11780 as_bad (_("-mgp64 used with a 32-bit processor"));
11781 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11782 as_bad (_("-mgp32 used with a 64-bit ABI"));
11783 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11784 as_bad (_("-mgp64 used with a 32-bit ABI"));
11788 /* Infer the integer register size from the ABI and processor.
11789 Restrict ourselves to 32-bit registers if that's all the
11790 processor has, or if the ABI cannot handle 64-bit registers. */
11791 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11792 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11795 switch (file_mips_fp32
)
11799 /* No user specified float register size.
11800 ??? GAS treats single-float processors as though they had 64-bit
11801 float registers (although it complains when double-precision
11802 instructions are used). As things stand, saying they have 32-bit
11803 registers would lead to spurious "register must be even" messages.
11804 So here we assume float registers are never smaller than the
11806 if (file_mips_gp32
== 0)
11807 /* 64-bit integer registers implies 64-bit float registers. */
11808 file_mips_fp32
= 0;
11809 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11810 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11811 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11812 file_mips_fp32
= 0;
11814 /* 32-bit float registers. */
11815 file_mips_fp32
= 1;
11818 /* The user specified the size of the float registers. Check if it
11819 agrees with the ABI and ISA. */
11821 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11822 as_bad (_("-mfp64 used with a 32-bit fpu"));
11823 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11824 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11825 as_warn (_("-mfp64 used with a 32-bit ABI"));
11828 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11829 as_warn (_("-mfp32 used with a 64-bit ABI"));
11833 /* End of GCC-shared inference code. */
11835 /* This flag is set when we have a 64-bit capable CPU but use only
11836 32-bit wide registers. Note that EABI does not use it. */
11837 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11838 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11839 || mips_abi
== O32_ABI
))
11840 mips_32bitmode
= 1;
11842 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11843 as_bad (_("trap exception not supported at ISA 1"));
11845 /* If the selected architecture includes support for ASEs, enable
11846 generation of code for them. */
11847 if (mips_opts
.mips16
== -1)
11848 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11849 if (mips_opts
.ase_mips3d
== -1)
11850 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11851 && file_mips_fp32
== 0) ? 1 : 0;
11852 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11853 as_bad (_("-mfp32 used with -mips3d"));
11855 if (mips_opts
.ase_mdmx
== -1)
11856 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11857 && file_mips_fp32
== 0) ? 1 : 0;
11858 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11859 as_bad (_("-mfp32 used with -mdmx"));
11861 if (mips_opts
.ase_smartmips
== -1)
11862 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11863 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11864 as_warn ("%s ISA does not support SmartMIPS",
11865 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11867 if (mips_opts
.ase_dsp
== -1)
11868 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11869 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11870 as_warn ("%s ISA does not support DSP ASE",
11871 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11873 if (mips_opts
.ase_dspr2
== -1)
11875 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11876 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11878 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11879 as_warn ("%s ISA does not support DSP R2 ASE",
11880 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11882 if (mips_opts
.ase_mt
== -1)
11883 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11884 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11885 as_warn ("%s ISA does not support MT ASE",
11886 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11888 file_mips_isa
= mips_opts
.isa
;
11889 file_ase_mips16
= mips_opts
.mips16
;
11890 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11891 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11892 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11893 file_ase_dsp
= mips_opts
.ase_dsp
;
11894 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11895 file_ase_mt
= mips_opts
.ase_mt
;
11896 mips_opts
.gp32
= file_mips_gp32
;
11897 mips_opts
.fp32
= file_mips_fp32
;
11898 mips_opts
.soft_float
= file_mips_soft_float
;
11899 mips_opts
.single_float
= file_mips_single_float
;
11901 if (mips_flag_mdebug
< 0)
11903 #ifdef OBJ_MAYBE_ECOFF
11904 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11905 mips_flag_mdebug
= 1;
11907 #endif /* OBJ_MAYBE_ECOFF */
11908 mips_flag_mdebug
= 0;
11913 mips_init_after_args (void)
11915 /* initialize opcodes */
11916 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11917 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11921 md_pcrel_from (fixS
*fixP
)
11923 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11924 switch (fixP
->fx_r_type
)
11926 case BFD_RELOC_16_PCREL_S2
:
11927 case BFD_RELOC_MIPS_JMP
:
11928 /* Return the address of the delay slot. */
11931 /* We have no relocation type for PC relative MIPS16 instructions. */
11932 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11934 _("PC relative MIPS16 instruction references a different section"));
11939 /* This is called before the symbol table is processed. In order to
11940 work with gcc when using mips-tfile, we must keep all local labels.
11941 However, in other cases, we want to discard them. If we were
11942 called with -g, but we didn't see any debugging information, it may
11943 mean that gcc is smuggling debugging information through to
11944 mips-tfile, in which case we must generate all local labels. */
11947 mips_frob_file_before_adjust (void)
11949 #ifndef NO_ECOFF_DEBUGGING
11950 if (ECOFF_DEBUGGING
11952 && ! ecoff_debugging_seen
)
11953 flag_keep_locals
= 1;
11957 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11958 the corresponding LO16 reloc. This is called before md_apply_fix and
11959 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11960 relocation operators.
11962 For our purposes, a %lo() expression matches a %got() or %hi()
11965 (a) it refers to the same symbol; and
11966 (b) the offset applied in the %lo() expression is no lower than
11967 the offset applied in the %got() or %hi().
11969 (b) allows us to cope with code like:
11972 lh $4,%lo(foo+2)($4)
11974 ...which is legal on RELA targets, and has a well-defined behaviour
11975 if the user knows that adding 2 to "foo" will not induce a carry to
11978 When several %lo()s match a particular %got() or %hi(), we use the
11979 following rules to distinguish them:
11981 (1) %lo()s with smaller offsets are a better match than %lo()s with
11984 (2) %lo()s with no matching %got() or %hi() are better than those
11985 that already have a matching %got() or %hi().
11987 (3) later %lo()s are better than earlier %lo()s.
11989 These rules are applied in order.
11991 (1) means, among other things, that %lo()s with identical offsets are
11992 chosen if they exist.
11994 (2) means that we won't associate several high-part relocations with
11995 the same low-part relocation unless there's no alternative. Having
11996 several high parts for the same low part is a GNU extension; this rule
11997 allows careful users to avoid it.
11999 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12000 with the last high-part relocation being at the front of the list.
12001 It therefore makes sense to choose the last matching low-part
12002 relocation, all other things being equal. It's also easier
12003 to code that way. */
12006 mips_frob_file (void)
12008 struct mips_hi_fixup
*l
;
12009 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12011 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12013 segment_info_type
*seginfo
;
12014 bfd_boolean matched_lo_p
;
12015 fixS
**hi_pos
, **lo_pos
, **pos
;
12017 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12019 /* If a GOT16 relocation turns out to be against a global symbol,
12020 there isn't supposed to be a matching LO. */
12021 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12022 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12025 /* Check quickly whether the next fixup happens to be a matching %lo. */
12026 if (fixup_has_matching_lo_p (l
->fixp
))
12029 seginfo
= seg_info (l
->seg
);
12031 /* Set HI_POS to the position of this relocation in the chain.
12032 Set LO_POS to the position of the chosen low-part relocation.
12033 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12034 relocation that matches an immediately-preceding high-part
12038 matched_lo_p
= FALSE
;
12039 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12041 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12043 if (*pos
== l
->fixp
)
12046 if ((*pos
)->fx_r_type
== looking_for_rtype
12047 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
12048 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12050 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12052 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12055 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12056 && fixup_has_matching_lo_p (*pos
));
12059 /* If we found a match, remove the high-part relocation from its
12060 current position and insert it before the low-part relocation.
12061 Make the offsets match so that fixup_has_matching_lo_p()
12064 We don't warn about unmatched high-part relocations since some
12065 versions of gcc have been known to emit dead "lui ...%hi(...)"
12067 if (lo_pos
!= NULL
)
12069 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12070 if (l
->fixp
->fx_next
!= *lo_pos
)
12072 *hi_pos
= l
->fixp
->fx_next
;
12073 l
->fixp
->fx_next
= *lo_pos
;
12080 /* We may have combined relocations without symbols in the N32/N64 ABI.
12081 We have to prevent gas from dropping them. */
12084 mips_force_relocation (fixS
*fixp
)
12086 if (generic_force_reloc (fixp
))
12090 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12091 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12092 || hi16_reloc_p (fixp
->fx_r_type
)
12093 || lo16_reloc_p (fixp
->fx_r_type
)))
12099 /* Apply a fixup to the object file. */
12102 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12106 reloc_howto_type
*howto
;
12108 /* We ignore generic BFD relocations we don't know about. */
12109 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12113 assert (fixP
->fx_size
== 4
12114 || fixP
->fx_r_type
== BFD_RELOC_16
12115 || fixP
->fx_r_type
== BFD_RELOC_64
12116 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12117 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12118 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12119 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12120 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12122 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12124 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12126 /* Don't treat parts of a composite relocation as done. There are two
12129 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12130 should nevertheless be emitted if the first part is.
12132 (2) In normal usage, composite relocations are never assembly-time
12133 constants. The easiest way of dealing with the pathological
12134 exceptions is to generate a relocation against STN_UNDEF and
12135 leave everything up to the linker. */
12136 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12139 switch (fixP
->fx_r_type
)
12141 case BFD_RELOC_MIPS_TLS_GD
:
12142 case BFD_RELOC_MIPS_TLS_LDM
:
12143 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12144 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12145 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12146 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12147 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12148 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12149 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12150 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12153 case BFD_RELOC_MIPS_JMP
:
12154 case BFD_RELOC_MIPS_SHIFT5
:
12155 case BFD_RELOC_MIPS_SHIFT6
:
12156 case BFD_RELOC_MIPS_GOT_DISP
:
12157 case BFD_RELOC_MIPS_GOT_PAGE
:
12158 case BFD_RELOC_MIPS_GOT_OFST
:
12159 case BFD_RELOC_MIPS_SUB
:
12160 case BFD_RELOC_MIPS_INSERT_A
:
12161 case BFD_RELOC_MIPS_INSERT_B
:
12162 case BFD_RELOC_MIPS_DELETE
:
12163 case BFD_RELOC_MIPS_HIGHEST
:
12164 case BFD_RELOC_MIPS_HIGHER
:
12165 case BFD_RELOC_MIPS_SCN_DISP
:
12166 case BFD_RELOC_MIPS_REL16
:
12167 case BFD_RELOC_MIPS_RELGOT
:
12168 case BFD_RELOC_MIPS_JALR
:
12169 case BFD_RELOC_HI16
:
12170 case BFD_RELOC_HI16_S
:
12171 case BFD_RELOC_GPREL16
:
12172 case BFD_RELOC_MIPS_LITERAL
:
12173 case BFD_RELOC_MIPS_CALL16
:
12174 case BFD_RELOC_MIPS_GOT16
:
12175 case BFD_RELOC_GPREL32
:
12176 case BFD_RELOC_MIPS_GOT_HI16
:
12177 case BFD_RELOC_MIPS_GOT_LO16
:
12178 case BFD_RELOC_MIPS_CALL_HI16
:
12179 case BFD_RELOC_MIPS_CALL_LO16
:
12180 case BFD_RELOC_MIPS16_GPREL
:
12181 case BFD_RELOC_MIPS16_GOT16
:
12182 case BFD_RELOC_MIPS16_CALL16
:
12183 case BFD_RELOC_MIPS16_HI16
:
12184 case BFD_RELOC_MIPS16_HI16_S
:
12185 case BFD_RELOC_MIPS16_JMP
:
12186 /* Nothing needed to do. The value comes from the reloc entry. */
12190 /* This is handled like BFD_RELOC_32, but we output a sign
12191 extended value if we are only 32 bits. */
12194 if (8 <= sizeof (valueT
))
12195 md_number_to_chars ((char *) buf
, *valP
, 8);
12200 if ((*valP
& 0x80000000) != 0)
12204 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12206 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12212 case BFD_RELOC_RVA
:
12215 /* If we are deleting this reloc entry, we must fill in the
12216 value now. This can happen if we have a .word which is not
12217 resolved when it appears but is later defined. */
12219 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12222 case BFD_RELOC_LO16
:
12223 case BFD_RELOC_MIPS16_LO16
:
12224 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12225 may be safe to remove, but if so it's not obvious. */
12226 /* When handling an embedded PIC switch statement, we can wind
12227 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12230 if (*valP
+ 0x8000 > 0xffff)
12231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12232 _("relocation overflow"));
12233 if (target_big_endian
)
12235 md_number_to_chars ((char *) buf
, *valP
, 2);
12239 case BFD_RELOC_16_PCREL_S2
:
12240 if ((*valP
& 0x3) != 0)
12241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12242 _("Branch to misaligned address (%lx)"), (long) *valP
);
12244 /* We need to save the bits in the instruction since fixup_segment()
12245 might be deleting the relocation entry (i.e., a branch within
12246 the current segment). */
12247 if (! fixP
->fx_done
)
12250 /* Update old instruction data. */
12251 if (target_big_endian
)
12252 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12254 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12256 if (*valP
+ 0x20000 <= 0x3ffff)
12258 insn
|= (*valP
>> 2) & 0xffff;
12259 md_number_to_chars ((char *) buf
, insn
, 4);
12261 else if (mips_pic
== NO_PIC
12263 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12264 && (fixP
->fx_frag
->fr_address
12265 < text_section
->vma
+ bfd_get_section_size (text_section
))
12266 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12267 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12268 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12270 /* The branch offset is too large. If this is an
12271 unconditional branch, and we are not generating PIC code,
12272 we can convert it to an absolute jump instruction. */
12273 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12274 insn
= 0x0c000000; /* jal */
12276 insn
= 0x08000000; /* j */
12277 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12279 fixP
->fx_addsy
= section_symbol (text_section
);
12280 *valP
+= md_pcrel_from (fixP
);
12281 md_number_to_chars ((char *) buf
, insn
, 4);
12285 /* If we got here, we have branch-relaxation disabled,
12286 and there's nothing we can do to fix this instruction
12287 without turning it into a longer sequence. */
12288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12289 _("Branch out of range"));
12293 case BFD_RELOC_VTABLE_INHERIT
:
12296 && !S_IS_DEFINED (fixP
->fx_addsy
)
12297 && !S_IS_WEAK (fixP
->fx_addsy
))
12298 S_SET_WEAK (fixP
->fx_addsy
);
12301 case BFD_RELOC_VTABLE_ENTRY
:
12309 /* Remember value for tc_gen_reloc. */
12310 fixP
->fx_addnumber
= *valP
;
12320 name
= input_line_pointer
;
12321 c
= get_symbol_end ();
12322 p
= (symbolS
*) symbol_find_or_make (name
);
12323 *input_line_pointer
= c
;
12327 /* Align the current frag to a given power of two. If a particular
12328 fill byte should be used, FILL points to an integer that contains
12329 that byte, otherwise FILL is null.
12331 The MIPS assembler also automatically adjusts any preceding
12335 mips_align (int to
, int *fill
, symbolS
*label
)
12337 mips_emit_delays ();
12338 mips_record_mips16_mode ();
12339 if (fill
== NULL
&& subseg_text_p (now_seg
))
12340 frag_align_code (to
, 0);
12342 frag_align (to
, fill
? *fill
: 0, 0);
12343 record_alignment (now_seg
, to
);
12346 assert (S_GET_SEGMENT (label
) == now_seg
);
12347 symbol_set_frag (label
, frag_now
);
12348 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12352 /* Align to a given power of two. .align 0 turns off the automatic
12353 alignment used by the data creating pseudo-ops. */
12356 s_align (int x ATTRIBUTE_UNUSED
)
12358 int temp
, fill_value
, *fill_ptr
;
12359 long max_alignment
= 28;
12361 /* o Note that the assembler pulls down any immediately preceding label
12362 to the aligned address.
12363 o It's not documented but auto alignment is reinstated by
12364 a .align pseudo instruction.
12365 o Note also that after auto alignment is turned off the mips assembler
12366 issues an error on attempt to assemble an improperly aligned data item.
12369 temp
= get_absolute_expression ();
12370 if (temp
> max_alignment
)
12371 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12374 as_warn (_("Alignment negative: 0 assumed."));
12377 if (*input_line_pointer
== ',')
12379 ++input_line_pointer
;
12380 fill_value
= get_absolute_expression ();
12381 fill_ptr
= &fill_value
;
12387 segment_info_type
*si
= seg_info (now_seg
);
12388 struct insn_label_list
*l
= si
->label_list
;
12389 /* Auto alignment should be switched on by next section change. */
12391 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12398 demand_empty_rest_of_line ();
12402 s_change_sec (int sec
)
12407 /* The ELF backend needs to know that we are changing sections, so
12408 that .previous works correctly. We could do something like check
12409 for an obj_section_change_hook macro, but that might be confusing
12410 as it would not be appropriate to use it in the section changing
12411 functions in read.c, since obj-elf.c intercepts those. FIXME:
12412 This should be cleaner, somehow. */
12414 obj_elf_section_change_hook ();
12417 mips_emit_delays ();
12427 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12428 demand_empty_rest_of_line ();
12432 seg
= subseg_new (RDATA_SECTION_NAME
,
12433 (subsegT
) get_absolute_expression ());
12436 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12437 | SEC_READONLY
| SEC_RELOC
12439 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12440 record_alignment (seg
, 4);
12442 demand_empty_rest_of_line ();
12446 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12449 bfd_set_section_flags (stdoutput
, seg
,
12450 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12451 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12452 record_alignment (seg
, 4);
12454 demand_empty_rest_of_line ();
12462 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12465 char *section_name
;
12470 int section_entry_size
;
12471 int section_alignment
;
12476 section_name
= input_line_pointer
;
12477 c
= get_symbol_end ();
12479 next_c
= *(input_line_pointer
+ 1);
12481 /* Do we have .section Name<,"flags">? */
12482 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12484 /* just after name is now '\0'. */
12485 *input_line_pointer
= c
;
12486 input_line_pointer
= section_name
;
12487 obj_elf_section (ignore
);
12490 input_line_pointer
++;
12492 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12494 section_type
= get_absolute_expression ();
12497 if (*input_line_pointer
++ == ',')
12498 section_flag
= get_absolute_expression ();
12501 if (*input_line_pointer
++ == ',')
12502 section_entry_size
= get_absolute_expression ();
12504 section_entry_size
= 0;
12505 if (*input_line_pointer
++ == ',')
12506 section_alignment
= get_absolute_expression ();
12508 section_alignment
= 0;
12510 section_name
= xstrdup (section_name
);
12512 /* When using the generic form of .section (as implemented by obj-elf.c),
12513 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12514 traditionally had to fall back on the more common @progbits instead.
12516 There's nothing really harmful in this, since bfd will correct
12517 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12518 means that, for backwards compatibility, the special_section entries
12519 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12521 Even so, we shouldn't force users of the MIPS .section syntax to
12522 incorrectly label the sections as SHT_PROGBITS. The best compromise
12523 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12524 generic type-checking code. */
12525 if (section_type
== SHT_MIPS_DWARF
)
12526 section_type
= SHT_PROGBITS
;
12528 obj_elf_change_section (section_name
, section_type
, section_flag
,
12529 section_entry_size
, 0, 0, 0);
12531 if (now_seg
->name
!= section_name
)
12532 free (section_name
);
12533 #endif /* OBJ_ELF */
12537 mips_enable_auto_align (void)
12543 s_cons (int log_size
)
12545 segment_info_type
*si
= seg_info (now_seg
);
12546 struct insn_label_list
*l
= si
->label_list
;
12549 label
= l
!= NULL
? l
->label
: NULL
;
12550 mips_emit_delays ();
12551 if (log_size
> 0 && auto_align
)
12552 mips_align (log_size
, 0, label
);
12553 mips_clear_insn_labels ();
12554 cons (1 << log_size
);
12558 s_float_cons (int type
)
12560 segment_info_type
*si
= seg_info (now_seg
);
12561 struct insn_label_list
*l
= si
->label_list
;
12564 label
= l
!= NULL
? l
->label
: NULL
;
12566 mips_emit_delays ();
12571 mips_align (3, 0, label
);
12573 mips_align (2, 0, label
);
12576 mips_clear_insn_labels ();
12581 /* Handle .globl. We need to override it because on Irix 5 you are
12584 where foo is an undefined symbol, to mean that foo should be
12585 considered to be the address of a function. */
12588 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12597 name
= input_line_pointer
;
12598 c
= get_symbol_end ();
12599 symbolP
= symbol_find_or_make (name
);
12600 S_SET_EXTERNAL (symbolP
);
12602 *input_line_pointer
= c
;
12603 SKIP_WHITESPACE ();
12605 /* On Irix 5, every global symbol that is not explicitly labelled as
12606 being a function is apparently labelled as being an object. */
12609 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12610 && (*input_line_pointer
!= ','))
12615 secname
= input_line_pointer
;
12616 c
= get_symbol_end ();
12617 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12619 as_bad (_("%s: no such section"), secname
);
12620 *input_line_pointer
= c
;
12622 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12623 flag
= BSF_FUNCTION
;
12626 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12628 c
= *input_line_pointer
;
12631 input_line_pointer
++;
12632 SKIP_WHITESPACE ();
12633 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12639 demand_empty_rest_of_line ();
12643 s_option (int x ATTRIBUTE_UNUSED
)
12648 opt
= input_line_pointer
;
12649 c
= get_symbol_end ();
12653 /* FIXME: What does this mean? */
12655 else if (strncmp (opt
, "pic", 3) == 0)
12659 i
= atoi (opt
+ 3);
12664 mips_pic
= SVR4_PIC
;
12665 mips_abicalls
= TRUE
;
12668 as_bad (_(".option pic%d not supported"), i
);
12670 if (mips_pic
== SVR4_PIC
)
12672 if (g_switch_seen
&& g_switch_value
!= 0)
12673 as_warn (_("-G may not be used with SVR4 PIC code"));
12674 g_switch_value
= 0;
12675 bfd_set_gp_size (stdoutput
, 0);
12679 as_warn (_("Unrecognized option \"%s\""), opt
);
12681 *input_line_pointer
= c
;
12682 demand_empty_rest_of_line ();
12685 /* This structure is used to hold a stack of .set values. */
12687 struct mips_option_stack
12689 struct mips_option_stack
*next
;
12690 struct mips_set_options options
;
12693 static struct mips_option_stack
*mips_opts_stack
;
12695 /* Handle the .set pseudo-op. */
12698 s_mipsset (int x ATTRIBUTE_UNUSED
)
12700 char *name
= input_line_pointer
, ch
;
12702 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12703 ++input_line_pointer
;
12704 ch
= *input_line_pointer
;
12705 *input_line_pointer
= '\0';
12707 if (strcmp (name
, "reorder") == 0)
12709 if (mips_opts
.noreorder
)
12712 else if (strcmp (name
, "noreorder") == 0)
12714 if (!mips_opts
.noreorder
)
12715 start_noreorder ();
12717 else if (strncmp (name
, "at=", 3) == 0)
12719 char *s
= name
+ 3;
12721 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12722 as_bad (_("Unrecognized register name `%s'"), s
);
12724 else if (strcmp (name
, "at") == 0)
12726 mips_opts
.at
= ATREG
;
12728 else if (strcmp (name
, "noat") == 0)
12730 mips_opts
.at
= ZERO
;
12732 else if (strcmp (name
, "macro") == 0)
12734 mips_opts
.warn_about_macros
= 0;
12736 else if (strcmp (name
, "nomacro") == 0)
12738 if (mips_opts
.noreorder
== 0)
12739 as_bad (_("`noreorder' must be set before `nomacro'"));
12740 mips_opts
.warn_about_macros
= 1;
12742 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12744 mips_opts
.nomove
= 0;
12746 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12748 mips_opts
.nomove
= 1;
12750 else if (strcmp (name
, "bopt") == 0)
12752 mips_opts
.nobopt
= 0;
12754 else if (strcmp (name
, "nobopt") == 0)
12756 mips_opts
.nobopt
= 1;
12758 else if (strcmp (name
, "gp=default") == 0)
12759 mips_opts
.gp32
= file_mips_gp32
;
12760 else if (strcmp (name
, "gp=32") == 0)
12761 mips_opts
.gp32
= 1;
12762 else if (strcmp (name
, "gp=64") == 0)
12764 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12765 as_warn ("%s isa does not support 64-bit registers",
12766 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12767 mips_opts
.gp32
= 0;
12769 else if (strcmp (name
, "fp=default") == 0)
12770 mips_opts
.fp32
= file_mips_fp32
;
12771 else if (strcmp (name
, "fp=32") == 0)
12772 mips_opts
.fp32
= 1;
12773 else if (strcmp (name
, "fp=64") == 0)
12775 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12776 as_warn ("%s isa does not support 64-bit floating point registers",
12777 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12778 mips_opts
.fp32
= 0;
12780 else if (strcmp (name
, "softfloat") == 0)
12781 mips_opts
.soft_float
= 1;
12782 else if (strcmp (name
, "hardfloat") == 0)
12783 mips_opts
.soft_float
= 0;
12784 else if (strcmp (name
, "singlefloat") == 0)
12785 mips_opts
.single_float
= 1;
12786 else if (strcmp (name
, "doublefloat") == 0)
12787 mips_opts
.single_float
= 0;
12788 else if (strcmp (name
, "mips16") == 0
12789 || strcmp (name
, "MIPS-16") == 0)
12790 mips_opts
.mips16
= 1;
12791 else if (strcmp (name
, "nomips16") == 0
12792 || strcmp (name
, "noMIPS-16") == 0)
12793 mips_opts
.mips16
= 0;
12794 else if (strcmp (name
, "smartmips") == 0)
12796 if (!ISA_SUPPORTS_SMARTMIPS
)
12797 as_warn ("%s ISA does not support SmartMIPS ASE",
12798 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12799 mips_opts
.ase_smartmips
= 1;
12801 else if (strcmp (name
, "nosmartmips") == 0)
12802 mips_opts
.ase_smartmips
= 0;
12803 else if (strcmp (name
, "mips3d") == 0)
12804 mips_opts
.ase_mips3d
= 1;
12805 else if (strcmp (name
, "nomips3d") == 0)
12806 mips_opts
.ase_mips3d
= 0;
12807 else if (strcmp (name
, "mdmx") == 0)
12808 mips_opts
.ase_mdmx
= 1;
12809 else if (strcmp (name
, "nomdmx") == 0)
12810 mips_opts
.ase_mdmx
= 0;
12811 else if (strcmp (name
, "dsp") == 0)
12813 if (!ISA_SUPPORTS_DSP_ASE
)
12814 as_warn ("%s ISA does not support DSP ASE",
12815 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12816 mips_opts
.ase_dsp
= 1;
12817 mips_opts
.ase_dspr2
= 0;
12819 else if (strcmp (name
, "nodsp") == 0)
12821 mips_opts
.ase_dsp
= 0;
12822 mips_opts
.ase_dspr2
= 0;
12824 else if (strcmp (name
, "dspr2") == 0)
12826 if (!ISA_SUPPORTS_DSPR2_ASE
)
12827 as_warn ("%s ISA does not support DSP R2 ASE",
12828 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12829 mips_opts
.ase_dspr2
= 1;
12830 mips_opts
.ase_dsp
= 1;
12832 else if (strcmp (name
, "nodspr2") == 0)
12834 mips_opts
.ase_dspr2
= 0;
12835 mips_opts
.ase_dsp
= 0;
12837 else if (strcmp (name
, "mt") == 0)
12839 if (!ISA_SUPPORTS_MT_ASE
)
12840 as_warn ("%s ISA does not support MT ASE",
12841 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12842 mips_opts
.ase_mt
= 1;
12844 else if (strcmp (name
, "nomt") == 0)
12845 mips_opts
.ase_mt
= 0;
12846 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12850 /* Permit the user to change the ISA and architecture on the fly.
12851 Needless to say, misuse can cause serious problems. */
12852 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12855 mips_opts
.isa
= file_mips_isa
;
12856 mips_opts
.arch
= file_mips_arch
;
12858 else if (strncmp (name
, "arch=", 5) == 0)
12860 const struct mips_cpu_info
*p
;
12862 p
= mips_parse_cpu("internal use", name
+ 5);
12864 as_bad (_("unknown architecture %s"), name
+ 5);
12867 mips_opts
.arch
= p
->cpu
;
12868 mips_opts
.isa
= p
->isa
;
12871 else if (strncmp (name
, "mips", 4) == 0)
12873 const struct mips_cpu_info
*p
;
12875 p
= mips_parse_cpu("internal use", name
);
12877 as_bad (_("unknown ISA level %s"), name
+ 4);
12880 mips_opts
.arch
= p
->cpu
;
12881 mips_opts
.isa
= p
->isa
;
12885 as_bad (_("unknown ISA or architecture %s"), name
);
12887 switch (mips_opts
.isa
)
12895 mips_opts
.gp32
= 1;
12896 mips_opts
.fp32
= 1;
12903 mips_opts
.gp32
= 0;
12904 mips_opts
.fp32
= 0;
12907 as_bad (_("unknown ISA level %s"), name
+ 4);
12912 mips_opts
.gp32
= file_mips_gp32
;
12913 mips_opts
.fp32
= file_mips_fp32
;
12916 else if (strcmp (name
, "autoextend") == 0)
12917 mips_opts
.noautoextend
= 0;
12918 else if (strcmp (name
, "noautoextend") == 0)
12919 mips_opts
.noautoextend
= 1;
12920 else if (strcmp (name
, "push") == 0)
12922 struct mips_option_stack
*s
;
12924 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12925 s
->next
= mips_opts_stack
;
12926 s
->options
= mips_opts
;
12927 mips_opts_stack
= s
;
12929 else if (strcmp (name
, "pop") == 0)
12931 struct mips_option_stack
*s
;
12933 s
= mips_opts_stack
;
12935 as_bad (_(".set pop with no .set push"));
12938 /* If we're changing the reorder mode we need to handle
12939 delay slots correctly. */
12940 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12941 start_noreorder ();
12942 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12945 mips_opts
= s
->options
;
12946 mips_opts_stack
= s
->next
;
12950 else if (strcmp (name
, "sym32") == 0)
12951 mips_opts
.sym32
= TRUE
;
12952 else if (strcmp (name
, "nosym32") == 0)
12953 mips_opts
.sym32
= FALSE
;
12954 else if (strchr (name
, ','))
12956 /* Generic ".set" directive; use the generic handler. */
12957 *input_line_pointer
= ch
;
12958 input_line_pointer
= name
;
12964 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12966 *input_line_pointer
= ch
;
12967 demand_empty_rest_of_line ();
12970 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12971 .option pic2. It means to generate SVR4 PIC calls. */
12974 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12976 mips_pic
= SVR4_PIC
;
12977 mips_abicalls
= TRUE
;
12979 if (g_switch_seen
&& g_switch_value
!= 0)
12980 as_warn (_("-G may not be used with SVR4 PIC code"));
12981 g_switch_value
= 0;
12983 bfd_set_gp_size (stdoutput
, 0);
12984 demand_empty_rest_of_line ();
12987 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12988 PIC code. It sets the $gp register for the function based on the
12989 function address, which is in the register named in the argument.
12990 This uses a relocation against _gp_disp, which is handled specially
12991 by the linker. The result is:
12992 lui $gp,%hi(_gp_disp)
12993 addiu $gp,$gp,%lo(_gp_disp)
12994 addu $gp,$gp,.cpload argument
12995 The .cpload argument is normally $25 == $t9.
12997 The -mno-shared option changes this to:
12998 lui $gp,%hi(__gnu_local_gp)
12999 addiu $gp,$gp,%lo(__gnu_local_gp)
13000 and the argument is ignored. This saves an instruction, but the
13001 resulting code is not position independent; it uses an absolute
13002 address for __gnu_local_gp. Thus code assembled with -mno-shared
13003 can go into an ordinary executable, but not into a shared library. */
13006 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13012 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13013 .cpload is ignored. */
13014 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13020 /* .cpload should be in a .set noreorder section. */
13021 if (mips_opts
.noreorder
== 0)
13022 as_warn (_(".cpload not in noreorder section"));
13024 reg
= tc_get_register (0);
13026 /* If we need to produce a 64-bit address, we are better off using
13027 the default instruction sequence. */
13028 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13030 ex
.X_op
= O_symbol
;
13031 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13033 ex
.X_op_symbol
= NULL
;
13034 ex
.X_add_number
= 0;
13036 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13037 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13040 macro_build_lui (&ex
, mips_gp_register
);
13041 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13042 mips_gp_register
, BFD_RELOC_LO16
);
13044 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13045 mips_gp_register
, reg
);
13048 demand_empty_rest_of_line ();
13051 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13052 .cpsetup $reg1, offset|$reg2, label
13054 If offset is given, this results in:
13055 sd $gp, offset($sp)
13056 lui $gp, %hi(%neg(%gp_rel(label)))
13057 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13058 daddu $gp, $gp, $reg1
13060 If $reg2 is given, this results in:
13061 daddu $reg2, $gp, $0
13062 lui $gp, %hi(%neg(%gp_rel(label)))
13063 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13064 daddu $gp, $gp, $reg1
13065 $reg1 is normally $25 == $t9.
13067 The -mno-shared option replaces the last three instructions with
13069 addiu $gp,$gp,%lo(_gp) */
13072 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13074 expressionS ex_off
;
13075 expressionS ex_sym
;
13078 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13079 We also need NewABI support. */
13080 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13086 reg1
= tc_get_register (0);
13087 SKIP_WHITESPACE ();
13088 if (*input_line_pointer
!= ',')
13090 as_bad (_("missing argument separator ',' for .cpsetup"));
13094 ++input_line_pointer
;
13095 SKIP_WHITESPACE ();
13096 if (*input_line_pointer
== '$')
13098 mips_cpreturn_register
= tc_get_register (0);
13099 mips_cpreturn_offset
= -1;
13103 mips_cpreturn_offset
= get_absolute_expression ();
13104 mips_cpreturn_register
= -1;
13106 SKIP_WHITESPACE ();
13107 if (*input_line_pointer
!= ',')
13109 as_bad (_("missing argument separator ',' for .cpsetup"));
13113 ++input_line_pointer
;
13114 SKIP_WHITESPACE ();
13115 expression (&ex_sym
);
13118 if (mips_cpreturn_register
== -1)
13120 ex_off
.X_op
= O_constant
;
13121 ex_off
.X_add_symbol
= NULL
;
13122 ex_off
.X_op_symbol
= NULL
;
13123 ex_off
.X_add_number
= mips_cpreturn_offset
;
13125 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13126 BFD_RELOC_LO16
, SP
);
13129 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13130 mips_gp_register
, 0);
13132 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13134 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13135 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13138 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13139 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13140 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13143 mips_gp_register
, reg1
);
13149 ex
.X_op
= O_symbol
;
13150 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13151 ex
.X_op_symbol
= NULL
;
13152 ex
.X_add_number
= 0;
13154 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13155 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13157 macro_build_lui (&ex
, mips_gp_register
);
13158 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13159 mips_gp_register
, BFD_RELOC_LO16
);
13164 demand_empty_rest_of_line ();
13168 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13170 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13171 .cplocal is ignored. */
13172 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13178 mips_gp_register
= tc_get_register (0);
13179 demand_empty_rest_of_line ();
13182 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13183 offset from $sp. The offset is remembered, and after making a PIC
13184 call $gp is restored from that location. */
13187 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13191 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13192 .cprestore is ignored. */
13193 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13199 mips_cprestore_offset
= get_absolute_expression ();
13200 mips_cprestore_valid
= 1;
13202 ex
.X_op
= O_constant
;
13203 ex
.X_add_symbol
= NULL
;
13204 ex
.X_op_symbol
= NULL
;
13205 ex
.X_add_number
= mips_cprestore_offset
;
13208 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13209 SP
, HAVE_64BIT_ADDRESSES
);
13212 demand_empty_rest_of_line ();
13215 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13216 was given in the preceding .cpsetup, it results in:
13217 ld $gp, offset($sp)
13219 If a register $reg2 was given there, it results in:
13220 daddu $gp, $reg2, $0 */
13223 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13227 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13228 We also need NewABI support. */
13229 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13236 if (mips_cpreturn_register
== -1)
13238 ex
.X_op
= O_constant
;
13239 ex
.X_add_symbol
= NULL
;
13240 ex
.X_op_symbol
= NULL
;
13241 ex
.X_add_number
= mips_cpreturn_offset
;
13243 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13246 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13247 mips_cpreturn_register
, 0);
13250 demand_empty_rest_of_line ();
13253 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13254 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13255 use in DWARF debug information. */
13258 s_dtprel_internal (size_t bytes
)
13265 if (ex
.X_op
!= O_symbol
)
13267 as_bad (_("Unsupported use of %s"), (bytes
== 8
13270 ignore_rest_of_line ();
13273 p
= frag_more (bytes
);
13274 md_number_to_chars (p
, 0, bytes
);
13275 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13277 ? BFD_RELOC_MIPS_TLS_DTPREL64
13278 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13280 demand_empty_rest_of_line ();
13283 /* Handle .dtprelword. */
13286 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13288 s_dtprel_internal (4);
13291 /* Handle .dtpreldword. */
13294 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13296 s_dtprel_internal (8);
13299 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13300 code. It sets the offset to use in gp_rel relocations. */
13303 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13305 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13306 We also need NewABI support. */
13307 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13313 mips_gprel_offset
= get_absolute_expression ();
13315 demand_empty_rest_of_line ();
13318 /* Handle the .gpword pseudo-op. This is used when generating PIC
13319 code. It generates a 32 bit GP relative reloc. */
13322 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13324 segment_info_type
*si
;
13325 struct insn_label_list
*l
;
13330 /* When not generating PIC code, this is treated as .word. */
13331 if (mips_pic
!= SVR4_PIC
)
13337 si
= seg_info (now_seg
);
13338 l
= si
->label_list
;
13339 label
= l
!= NULL
? l
->label
: NULL
;
13340 mips_emit_delays ();
13342 mips_align (2, 0, label
);
13343 mips_clear_insn_labels ();
13347 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13349 as_bad (_("Unsupported use of .gpword"));
13350 ignore_rest_of_line ();
13354 md_number_to_chars (p
, 0, 4);
13355 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13356 BFD_RELOC_GPREL32
);
13358 demand_empty_rest_of_line ();
13362 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13364 segment_info_type
*si
;
13365 struct insn_label_list
*l
;
13370 /* When not generating PIC code, this is treated as .dword. */
13371 if (mips_pic
!= SVR4_PIC
)
13377 si
= seg_info (now_seg
);
13378 l
= si
->label_list
;
13379 label
= l
!= NULL
? l
->label
: NULL
;
13380 mips_emit_delays ();
13382 mips_align (3, 0, label
);
13383 mips_clear_insn_labels ();
13387 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13389 as_bad (_("Unsupported use of .gpdword"));
13390 ignore_rest_of_line ();
13394 md_number_to_chars (p
, 0, 8);
13395 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13396 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13398 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13399 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13400 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13402 demand_empty_rest_of_line ();
13405 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13406 tables in SVR4 PIC code. */
13409 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13413 /* This is ignored when not generating SVR4 PIC code. */
13414 if (mips_pic
!= SVR4_PIC
)
13420 /* Add $gp to the register named as an argument. */
13422 reg
= tc_get_register (0);
13423 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13426 demand_empty_rest_of_line ();
13429 /* Handle the .insn pseudo-op. This marks instruction labels in
13430 mips16 mode. This permits the linker to handle them specially,
13431 such as generating jalx instructions when needed. We also make
13432 them odd for the duration of the assembly, in order to generate the
13433 right sort of code. We will make them even in the adjust_symtab
13434 routine, while leaving them marked. This is convenient for the
13435 debugger and the disassembler. The linker knows to make them odd
13439 s_insn (int ignore ATTRIBUTE_UNUSED
)
13441 mips16_mark_labels ();
13443 demand_empty_rest_of_line ();
13446 /* Handle a .stabn directive. We need these in order to mark a label
13447 as being a mips16 text label correctly. Sometimes the compiler
13448 will emit a label, followed by a .stabn, and then switch sections.
13449 If the label and .stabn are in mips16 mode, then the label is
13450 really a mips16 text label. */
13453 s_mips_stab (int type
)
13456 mips16_mark_labels ();
13461 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13464 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13471 name
= input_line_pointer
;
13472 c
= get_symbol_end ();
13473 symbolP
= symbol_find_or_make (name
);
13474 S_SET_WEAK (symbolP
);
13475 *input_line_pointer
= c
;
13477 SKIP_WHITESPACE ();
13479 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13481 if (S_IS_DEFINED (symbolP
))
13483 as_bad ("ignoring attempt to redefine symbol %s",
13484 S_GET_NAME (symbolP
));
13485 ignore_rest_of_line ();
13489 if (*input_line_pointer
== ',')
13491 ++input_line_pointer
;
13492 SKIP_WHITESPACE ();
13496 if (exp
.X_op
!= O_symbol
)
13498 as_bad ("bad .weakext directive");
13499 ignore_rest_of_line ();
13502 symbol_set_value_expression (symbolP
, &exp
);
13505 demand_empty_rest_of_line ();
13508 /* Parse a register string into a number. Called from the ECOFF code
13509 to parse .frame. The argument is non-zero if this is the frame
13510 register, so that we can record it in mips_frame_reg. */
13513 tc_get_register (int frame
)
13517 SKIP_WHITESPACE ();
13518 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13522 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13523 mips_frame_reg_valid
= 1;
13524 mips_cprestore_valid
= 0;
13530 md_section_align (asection
*seg
, valueT addr
)
13532 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13536 /* We don't need to align ELF sections to the full alignment.
13537 However, Irix 5 may prefer that we align them at least to a 16
13538 byte boundary. We don't bother to align the sections if we
13539 are targeted for an embedded system. */
13540 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13546 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13549 /* Utility routine, called from above as well. If called while the
13550 input file is still being read, it's only an approximation. (For
13551 example, a symbol may later become defined which appeared to be
13552 undefined earlier.) */
13555 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13560 if (g_switch_value
> 0)
13562 const char *symname
;
13565 /* Find out whether this symbol can be referenced off the $gp
13566 register. It can be if it is smaller than the -G size or if
13567 it is in the .sdata or .sbss section. Certain symbols can
13568 not be referenced off the $gp, although it appears as though
13570 symname
= S_GET_NAME (sym
);
13571 if (symname
!= (const char *) NULL
13572 && (strcmp (symname
, "eprol") == 0
13573 || strcmp (symname
, "etext") == 0
13574 || strcmp (symname
, "_gp") == 0
13575 || strcmp (symname
, "edata") == 0
13576 || strcmp (symname
, "_fbss") == 0
13577 || strcmp (symname
, "_fdata") == 0
13578 || strcmp (symname
, "_ftext") == 0
13579 || strcmp (symname
, "end") == 0
13580 || strcmp (symname
, "_gp_disp") == 0))
13582 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13584 #ifndef NO_ECOFF_DEBUGGING
13585 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13586 && (symbol_get_obj (sym
)->ecoff_extern_size
13587 <= g_switch_value
))
13589 /* We must defer this decision until after the whole
13590 file has been read, since there might be a .extern
13591 after the first use of this symbol. */
13592 || (before_relaxing
13593 #ifndef NO_ECOFF_DEBUGGING
13594 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13596 && S_GET_VALUE (sym
) == 0)
13597 || (S_GET_VALUE (sym
) != 0
13598 && S_GET_VALUE (sym
) <= g_switch_value
)))
13602 const char *segname
;
13604 segname
= segment_name (S_GET_SEGMENT (sym
));
13605 assert (strcmp (segname
, ".lit8") != 0
13606 && strcmp (segname
, ".lit4") != 0);
13607 change
= (strcmp (segname
, ".sdata") != 0
13608 && strcmp (segname
, ".sbss") != 0
13609 && strncmp (segname
, ".sdata.", 7) != 0
13610 && strncmp (segname
, ".sbss.", 6) != 0
13611 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13612 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13617 /* We are not optimizing for the $gp register. */
13622 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13625 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13629 /* Handle the case of a symbol equated to another symbol. */
13630 while (symbol_equated_reloc_p (sym
))
13634 /* It's possible to get a loop here in a badly written program. */
13635 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13641 if (symbol_section_p (sym
))
13644 symsec
= S_GET_SEGMENT (sym
);
13646 /* This must duplicate the test in adjust_reloc_syms. */
13647 return (symsec
!= &bfd_und_section
13648 && symsec
!= &bfd_abs_section
13649 && !bfd_is_com_section (symsec
)
13650 && !s_is_linkonce (sym
, segtype
)
13652 /* A global or weak symbol is treated as external. */
13653 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13659 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13660 extended opcode. SEC is the section the frag is in. */
13663 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13666 const struct mips16_immed_operand
*op
;
13668 int mintiny
, maxtiny
;
13672 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13674 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13677 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13678 op
= mips16_immed_operands
;
13679 while (op
->type
!= type
)
13682 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13687 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13690 maxtiny
= 1 << op
->nbits
;
13695 maxtiny
= (1 << op
->nbits
) - 1;
13700 mintiny
= - (1 << (op
->nbits
- 1));
13701 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13704 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13705 val
= S_GET_VALUE (fragp
->fr_symbol
);
13706 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13712 /* We won't have the section when we are called from
13713 mips_relax_frag. However, we will always have been called
13714 from md_estimate_size_before_relax first. If this is a
13715 branch to a different section, we mark it as such. If SEC is
13716 NULL, and the frag is not marked, then it must be a branch to
13717 the same section. */
13720 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13725 /* Must have been called from md_estimate_size_before_relax. */
13728 fragp
->fr_subtype
=
13729 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13731 /* FIXME: We should support this, and let the linker
13732 catch branches and loads that are out of range. */
13733 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13734 _("unsupported PC relative reference to different section"));
13738 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13739 /* Assume non-extended on the first relaxation pass.
13740 The address we have calculated will be bogus if this is
13741 a forward branch to another frag, as the forward frag
13742 will have fr_address == 0. */
13746 /* In this case, we know for sure that the symbol fragment is in
13747 the same section. If the relax_marker of the symbol fragment
13748 differs from the relax_marker of this fragment, we have not
13749 yet adjusted the symbol fragment fr_address. We want to add
13750 in STRETCH in order to get a better estimate of the address.
13751 This particularly matters because of the shift bits. */
13753 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13757 /* Adjust stretch for any alignment frag. Note that if have
13758 been expanding the earlier code, the symbol may be
13759 defined in what appears to be an earlier frag. FIXME:
13760 This doesn't handle the fr_subtype field, which specifies
13761 a maximum number of bytes to skip when doing an
13763 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13765 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13768 stretch
= - ((- stretch
)
13769 & ~ ((1 << (int) f
->fr_offset
) - 1));
13771 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13780 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13782 /* The base address rules are complicated. The base address of
13783 a branch is the following instruction. The base address of a
13784 PC relative load or add is the instruction itself, but if it
13785 is in a delay slot (in which case it can not be extended) use
13786 the address of the instruction whose delay slot it is in. */
13787 if (type
== 'p' || type
== 'q')
13791 /* If we are currently assuming that this frag should be
13792 extended, then, the current address is two bytes
13794 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13797 /* Ignore the low bit in the target, since it will be set
13798 for a text label. */
13799 if ((val
& 1) != 0)
13802 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13804 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13807 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13809 /* Branch offsets have an implicit 0 in the lowest bit. */
13810 if (type
== 'p' || type
== 'q')
13813 /* If any of the shifted bits are set, we must use an extended
13814 opcode. If the address depends on the size of this
13815 instruction, this can lead to a loop, so we arrange to always
13816 use an extended opcode. We only check this when we are in
13817 the main relaxation loop, when SEC is NULL. */
13818 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13820 fragp
->fr_subtype
=
13821 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13825 /* If we are about to mark a frag as extended because the value
13826 is precisely maxtiny + 1, then there is a chance of an
13827 infinite loop as in the following code:
13832 In this case when the la is extended, foo is 0x3fc bytes
13833 away, so the la can be shrunk, but then foo is 0x400 away, so
13834 the la must be extended. To avoid this loop, we mark the
13835 frag as extended if it was small, and is about to become
13836 extended with a value of maxtiny + 1. */
13837 if (val
== ((maxtiny
+ 1) << op
->shift
)
13838 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13841 fragp
->fr_subtype
=
13842 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13846 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13847 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13849 if ((val
& ((1 << op
->shift
) - 1)) != 0
13850 || val
< (mintiny
<< op
->shift
)
13851 || val
> (maxtiny
<< op
->shift
))
13857 /* Compute the length of a branch sequence, and adjust the
13858 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13859 worst-case length is computed, with UPDATE being used to indicate
13860 whether an unconditional (-1), branch-likely (+1) or regular (0)
13861 branch is to be computed. */
13863 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13865 bfd_boolean toofar
;
13869 && S_IS_DEFINED (fragp
->fr_symbol
)
13870 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13875 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13877 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13881 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13884 /* If the symbol is not defined or it's in a different segment,
13885 assume the user knows what's going on and emit a short
13891 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13893 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13894 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13895 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13901 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13904 if (mips_pic
!= NO_PIC
)
13906 /* Additional space for PIC loading of target address. */
13908 if (mips_opts
.isa
== ISA_MIPS1
)
13909 /* Additional space for $at-stabilizing nop. */
13913 /* If branch is conditional. */
13914 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13921 /* Estimate the size of a frag before relaxing. Unless this is the
13922 mips16, we are not really relaxing here, and the final size is
13923 encoded in the subtype information. For the mips16, we have to
13924 decide whether we are using an extended opcode or not. */
13927 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13931 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13934 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13936 return fragp
->fr_var
;
13939 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13940 /* We don't want to modify the EXTENDED bit here; it might get us
13941 into infinite loops. We change it only in mips_relax_frag(). */
13942 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13944 if (mips_pic
== NO_PIC
)
13945 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13946 else if (mips_pic
== SVR4_PIC
)
13947 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13948 else if (mips_pic
== VXWORKS_PIC
)
13949 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13956 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13957 return -RELAX_FIRST (fragp
->fr_subtype
);
13960 return -RELAX_SECOND (fragp
->fr_subtype
);
13963 /* This is called to see whether a reloc against a defined symbol
13964 should be converted into a reloc against a section. */
13967 mips_fix_adjustable (fixS
*fixp
)
13969 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13970 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13973 if (fixp
->fx_addsy
== NULL
)
13976 /* If symbol SYM is in a mergeable section, relocations of the form
13977 SYM + 0 can usually be made section-relative. The mergeable data
13978 is then identified by the section offset rather than by the symbol.
13980 However, if we're generating REL LO16 relocations, the offset is split
13981 between the LO16 and parterning high part relocation. The linker will
13982 need to recalculate the complete offset in order to correctly identify
13985 The linker has traditionally not looked for the parterning high part
13986 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13987 placed anywhere. Rather than break backwards compatibility by changing
13988 this, it seems better not to force the issue, and instead keep the
13989 original symbol. This will work with either linker behavior. */
13990 if ((lo16_reloc_p (fixp
->fx_r_type
)
13991 || reloc_needs_lo_p (fixp
->fx_r_type
))
13992 && HAVE_IN_PLACE_ADDENDS
13993 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13997 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13998 to a floating-point stub. The same is true for non-R_MIPS16_26
13999 relocations against MIPS16 functions; in this case, the stub becomes
14000 the function's canonical address.
14002 Floating-point stubs are stored in unique .mips16.call.* or
14003 .mips16.fn.* sections. If a stub T for function F is in section S,
14004 the first relocation in section S must be against F; this is how the
14005 linker determines the target function. All relocations that might
14006 resolve to T must also be against F. We therefore have the following
14007 restrictions, which are given in an intentionally-redundant way:
14009 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14012 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14013 if that stub might be used.
14015 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14018 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14019 that stub might be used.
14021 There is a further restriction:
14023 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14024 on targets with in-place addends; the relocation field cannot
14025 encode the low bit.
14027 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14028 against a MIPS16 symbol.
14030 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14031 relocation against some symbol R, no relocation against R may be
14032 reduced. (Note that this deals with (2) as well as (1) because
14033 relocations against global symbols will never be reduced on ELF
14034 targets.) This approach is a little simpler than trying to detect
14035 stub sections, and gives the "all or nothing" per-symbol consistency
14036 that we have for MIPS16 symbols. */
14038 && fixp
->fx_subsy
== NULL
14039 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14040 || *symbol_get_tc (fixp
->fx_addsy
)))
14047 /* Translate internal representation of relocation info to BFD target
14051 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14053 static arelent
*retval
[4];
14055 bfd_reloc_code_real_type code
;
14057 memset (retval
, 0, sizeof(retval
));
14058 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14059 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14060 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14061 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14063 if (fixp
->fx_pcrel
)
14065 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14067 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14068 Relocations want only the symbol offset. */
14069 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14072 /* A gruesome hack which is a result of the gruesome gas
14073 reloc handling. What's worse, for COFF (as opposed to
14074 ECOFF), we might need yet another copy of reloc->address.
14075 See bfd_install_relocation. */
14076 reloc
->addend
+= reloc
->address
;
14080 reloc
->addend
= fixp
->fx_addnumber
;
14082 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14083 entry to be used in the relocation's section offset. */
14084 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14086 reloc
->address
= reloc
->addend
;
14090 code
= fixp
->fx_r_type
;
14092 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14093 if (reloc
->howto
== NULL
)
14095 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14096 _("Can not represent %s relocation in this object file format"),
14097 bfd_get_reloc_code_name (code
));
14104 /* Relax a machine dependent frag. This returns the amount by which
14105 the current size of the frag should change. */
14108 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14110 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14112 offsetT old_var
= fragp
->fr_var
;
14114 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14116 return fragp
->fr_var
- old_var
;
14119 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14122 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14124 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14126 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14131 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14133 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14140 /* Convert a machine dependent frag. */
14143 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14145 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14148 unsigned long insn
;
14152 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14154 if (target_big_endian
)
14155 insn
= bfd_getb32 (buf
);
14157 insn
= bfd_getl32 (buf
);
14159 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14161 /* We generate a fixup instead of applying it right now
14162 because, if there are linker relaxations, we're going to
14163 need the relocations. */
14164 exp
.X_op
= O_symbol
;
14165 exp
.X_add_symbol
= fragp
->fr_symbol
;
14166 exp
.X_add_number
= fragp
->fr_offset
;
14168 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14169 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14170 fixp
->fx_file
= fragp
->fr_file
;
14171 fixp
->fx_line
= fragp
->fr_line
;
14173 md_number_to_chars ((char *) buf
, insn
, 4);
14180 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14181 _("relaxed out-of-range branch into a jump"));
14183 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14186 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14188 /* Reverse the branch. */
14189 switch ((insn
>> 28) & 0xf)
14192 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14193 have the condition reversed by tweaking a single
14194 bit, and their opcodes all have 0x4???????. */
14195 assert ((insn
& 0xf1000000) == 0x41000000);
14196 insn
^= 0x00010000;
14200 /* bltz 0x04000000 bgez 0x04010000
14201 bltzal 0x04100000 bgezal 0x04110000 */
14202 assert ((insn
& 0xfc0e0000) == 0x04000000);
14203 insn
^= 0x00010000;
14207 /* beq 0x10000000 bne 0x14000000
14208 blez 0x18000000 bgtz 0x1c000000 */
14209 insn
^= 0x04000000;
14217 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14219 /* Clear the and-link bit. */
14220 assert ((insn
& 0xfc1c0000) == 0x04100000);
14222 /* bltzal 0x04100000 bgezal 0x04110000
14223 bltzall 0x04120000 bgezall 0x04130000 */
14224 insn
&= ~0x00100000;
14227 /* Branch over the branch (if the branch was likely) or the
14228 full jump (not likely case). Compute the offset from the
14229 current instruction to branch to. */
14230 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14234 /* How many bytes in instructions we've already emitted? */
14235 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14236 /* How many bytes in instructions from here to the end? */
14237 i
= fragp
->fr_var
- i
;
14239 /* Convert to instruction count. */
14241 /* Branch counts from the next instruction. */
14244 /* Branch over the jump. */
14245 md_number_to_chars ((char *) buf
, insn
, 4);
14249 md_number_to_chars ((char *) buf
, 0, 4);
14252 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14254 /* beql $0, $0, 2f */
14256 /* Compute the PC offset from the current instruction to
14257 the end of the variable frag. */
14258 /* How many bytes in instructions we've already emitted? */
14259 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14260 /* How many bytes in instructions from here to the end? */
14261 i
= fragp
->fr_var
- i
;
14262 /* Convert to instruction count. */
14264 /* Don't decrement i, because we want to branch over the
14268 md_number_to_chars ((char *) buf
, insn
, 4);
14271 md_number_to_chars ((char *) buf
, 0, 4);
14276 if (mips_pic
== NO_PIC
)
14279 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14280 ? 0x0c000000 : 0x08000000);
14281 exp
.X_op
= O_symbol
;
14282 exp
.X_add_symbol
= fragp
->fr_symbol
;
14283 exp
.X_add_number
= fragp
->fr_offset
;
14285 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14286 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14287 fixp
->fx_file
= fragp
->fr_file
;
14288 fixp
->fx_line
= fragp
->fr_line
;
14290 md_number_to_chars ((char *) buf
, insn
, 4);
14295 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14296 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14297 exp
.X_op
= O_symbol
;
14298 exp
.X_add_symbol
= fragp
->fr_symbol
;
14299 exp
.X_add_number
= fragp
->fr_offset
;
14301 if (fragp
->fr_offset
)
14303 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14304 exp
.X_add_number
= 0;
14307 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14308 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14309 fixp
->fx_file
= fragp
->fr_file
;
14310 fixp
->fx_line
= fragp
->fr_line
;
14312 md_number_to_chars ((char *) buf
, insn
, 4);
14315 if (mips_opts
.isa
== ISA_MIPS1
)
14318 md_number_to_chars ((char *) buf
, 0, 4);
14322 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14323 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14325 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14326 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14327 fixp
->fx_file
= fragp
->fr_file
;
14328 fixp
->fx_line
= fragp
->fr_line
;
14330 md_number_to_chars ((char *) buf
, insn
, 4);
14334 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14339 md_number_to_chars ((char *) buf
, insn
, 4);
14344 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14345 + fragp
->fr_fix
+ fragp
->fr_var
);
14347 fragp
->fr_fix
+= fragp
->fr_var
;
14352 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14355 const struct mips16_immed_operand
*op
;
14356 bfd_boolean small
, ext
;
14359 unsigned long insn
;
14360 bfd_boolean use_extend
;
14361 unsigned short extend
;
14363 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14364 op
= mips16_immed_operands
;
14365 while (op
->type
!= type
)
14368 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14379 resolve_symbol_value (fragp
->fr_symbol
);
14380 val
= S_GET_VALUE (fragp
->fr_symbol
);
14385 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14387 /* The rules for the base address of a PC relative reloc are
14388 complicated; see mips16_extended_frag. */
14389 if (type
== 'p' || type
== 'q')
14394 /* Ignore the low bit in the target, since it will be
14395 set for a text label. */
14396 if ((val
& 1) != 0)
14399 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14401 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14404 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14407 /* Make sure the section winds up with the alignment we have
14410 record_alignment (asec
, op
->shift
);
14414 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14415 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14416 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14417 _("extended instruction in delay slot"));
14419 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14421 if (target_big_endian
)
14422 insn
= bfd_getb16 (buf
);
14424 insn
= bfd_getl16 (buf
);
14426 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14427 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14428 small
, ext
, &insn
, &use_extend
, &extend
);
14432 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14433 fragp
->fr_fix
+= 2;
14437 md_number_to_chars ((char *) buf
, insn
, 2);
14438 fragp
->fr_fix
+= 2;
14446 first
= RELAX_FIRST (fragp
->fr_subtype
);
14447 second
= RELAX_SECOND (fragp
->fr_subtype
);
14448 fixp
= (fixS
*) fragp
->fr_opcode
;
14450 /* Possibly emit a warning if we've chosen the longer option. */
14451 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14452 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14454 const char *msg
= macro_warning (fragp
->fr_subtype
);
14456 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14459 /* Go through all the fixups for the first sequence. Disable them
14460 (by marking them as done) if we're going to use the second
14461 sequence instead. */
14463 && fixp
->fx_frag
== fragp
14464 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14466 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14468 fixp
= fixp
->fx_next
;
14471 /* Go through the fixups for the second sequence. Disable them if
14472 we're going to use the first sequence, otherwise adjust their
14473 addresses to account for the relaxation. */
14474 while (fixp
&& fixp
->fx_frag
== fragp
)
14476 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14477 fixp
->fx_where
-= first
;
14480 fixp
= fixp
->fx_next
;
14483 /* Now modify the frag contents. */
14484 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14488 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14489 memmove (start
, start
+ first
, second
);
14490 fragp
->fr_fix
-= first
;
14493 fragp
->fr_fix
-= second
;
14499 /* This function is called after the relocs have been generated.
14500 We've been storing mips16 text labels as odd. Here we convert them
14501 back to even for the convenience of the debugger. */
14504 mips_frob_file_after_relocs (void)
14507 unsigned int count
, i
;
14512 syms
= bfd_get_outsymbols (stdoutput
);
14513 count
= bfd_get_symcount (stdoutput
);
14514 for (i
= 0; i
< count
; i
++, syms
++)
14516 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14517 && ((*syms
)->value
& 1) != 0)
14519 (*syms
)->value
&= ~1;
14520 /* If the symbol has an odd size, it was probably computed
14521 incorrectly, so adjust that as well. */
14522 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14523 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14530 /* This function is called whenever a label is defined. It is used
14531 when handling branch delays; if a branch has a label, we assume we
14532 can not move it. */
14535 mips_define_label (symbolS
*sym
)
14537 segment_info_type
*si
= seg_info (now_seg
);
14538 struct insn_label_list
*l
;
14540 if (free_insn_labels
== NULL
)
14541 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14544 l
= free_insn_labels
;
14545 free_insn_labels
= l
->next
;
14549 l
->next
= si
->label_list
;
14550 si
->label_list
= l
;
14553 dwarf2_emit_label (sym
);
14557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14559 /* Some special processing for a MIPS ELF file. */
14562 mips_elf_final_processing (void)
14564 /* Write out the register information. */
14565 if (mips_abi
!= N64_ABI
)
14569 s
.ri_gprmask
= mips_gprmask
;
14570 s
.ri_cprmask
[0] = mips_cprmask
[0];
14571 s
.ri_cprmask
[1] = mips_cprmask
[1];
14572 s
.ri_cprmask
[2] = mips_cprmask
[2];
14573 s
.ri_cprmask
[3] = mips_cprmask
[3];
14574 /* The gp_value field is set by the MIPS ELF backend. */
14576 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14577 ((Elf32_External_RegInfo
*)
14578 mips_regmask_frag
));
14582 Elf64_Internal_RegInfo s
;
14584 s
.ri_gprmask
= mips_gprmask
;
14586 s
.ri_cprmask
[0] = mips_cprmask
[0];
14587 s
.ri_cprmask
[1] = mips_cprmask
[1];
14588 s
.ri_cprmask
[2] = mips_cprmask
[2];
14589 s
.ri_cprmask
[3] = mips_cprmask
[3];
14590 /* The gp_value field is set by the MIPS ELF backend. */
14592 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14593 ((Elf64_External_RegInfo
*)
14594 mips_regmask_frag
));
14597 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14598 sort of BFD interface for this. */
14599 if (mips_any_noreorder
)
14600 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14601 if (mips_pic
!= NO_PIC
)
14603 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14604 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14607 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14609 /* Set MIPS ELF flags for ASEs. */
14610 /* We may need to define a new flag for DSP ASE, and set this flag when
14611 file_ase_dsp is true. */
14612 /* Same for DSP R2. */
14613 /* We may need to define a new flag for MT ASE, and set this flag when
14614 file_ase_mt is true. */
14615 if (file_ase_mips16
)
14616 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14617 #if 0 /* XXX FIXME */
14618 if (file_ase_mips3d
)
14619 elf_elfheader (stdoutput
)->e_flags
|= ???;
14622 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14624 /* Set the MIPS ELF ABI flags. */
14625 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14626 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14627 else if (mips_abi
== O64_ABI
)
14628 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14629 else if (mips_abi
== EABI_ABI
)
14631 if (!file_mips_gp32
)
14632 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14634 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14636 else if (mips_abi
== N32_ABI
)
14637 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14639 /* Nothing to do for N64_ABI. */
14641 if (mips_32bitmode
)
14642 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14644 #if 0 /* XXX FIXME */
14645 /* 32 bit code with 64 bit FP registers. */
14646 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14647 elf_elfheader (stdoutput
)->e_flags
|= ???;
14651 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14653 typedef struct proc
{
14655 symbolS
*func_end_sym
;
14656 unsigned long reg_mask
;
14657 unsigned long reg_offset
;
14658 unsigned long fpreg_mask
;
14659 unsigned long fpreg_offset
;
14660 unsigned long frame_offset
;
14661 unsigned long frame_reg
;
14662 unsigned long pc_reg
;
14665 static procS cur_proc
;
14666 static procS
*cur_proc_ptr
;
14667 static int numprocs
;
14669 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14673 mips_nop_opcode (void)
14675 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14678 /* Fill in an rs_align_code fragment. This only needs to do something
14679 for MIPS16 code, where 0 is not a nop. */
14682 mips_handle_align (fragS
*fragp
)
14686 if (fragp
->fr_type
!= rs_align_code
)
14689 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14694 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14700 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14706 md_obj_begin (void)
14713 /* Check for premature end, nesting errors, etc. */
14715 as_warn (_("missing .end at end of assembly"));
14724 if (*input_line_pointer
== '-')
14726 ++input_line_pointer
;
14729 if (!ISDIGIT (*input_line_pointer
))
14730 as_bad (_("expected simple number"));
14731 if (input_line_pointer
[0] == '0')
14733 if (input_line_pointer
[1] == 'x')
14735 input_line_pointer
+= 2;
14736 while (ISXDIGIT (*input_line_pointer
))
14739 val
|= hex_value (*input_line_pointer
++);
14741 return negative
? -val
: val
;
14745 ++input_line_pointer
;
14746 while (ISDIGIT (*input_line_pointer
))
14749 val
|= *input_line_pointer
++ - '0';
14751 return negative
? -val
: val
;
14754 if (!ISDIGIT (*input_line_pointer
))
14756 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14757 *input_line_pointer
, *input_line_pointer
);
14758 as_warn (_("invalid number"));
14761 while (ISDIGIT (*input_line_pointer
))
14764 val
+= *input_line_pointer
++ - '0';
14766 return negative
? -val
: val
;
14769 /* The .file directive; just like the usual .file directive, but there
14770 is an initial number which is the ECOFF file index. In the non-ECOFF
14771 case .file implies DWARF-2. */
14774 s_mips_file (int x ATTRIBUTE_UNUSED
)
14776 static int first_file_directive
= 0;
14778 if (ECOFF_DEBUGGING
)
14787 filename
= dwarf2_directive_file (0);
14789 /* Versions of GCC up to 3.1 start files with a ".file"
14790 directive even for stabs output. Make sure that this
14791 ".file" is handled. Note that you need a version of GCC
14792 after 3.1 in order to support DWARF-2 on MIPS. */
14793 if (filename
!= NULL
&& ! first_file_directive
)
14795 (void) new_logical_line (filename
, -1);
14796 s_app_file_string (filename
, 0);
14798 first_file_directive
= 1;
14802 /* The .loc directive, implying DWARF-2. */
14805 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14807 if (!ECOFF_DEBUGGING
)
14808 dwarf2_directive_loc (0);
14811 /* The .end directive. */
14814 s_mips_end (int x ATTRIBUTE_UNUSED
)
14818 /* Following functions need their own .frame and .cprestore directives. */
14819 mips_frame_reg_valid
= 0;
14820 mips_cprestore_valid
= 0;
14822 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14825 demand_empty_rest_of_line ();
14830 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14831 as_warn (_(".end not in text section"));
14835 as_warn (_(".end directive without a preceding .ent directive."));
14836 demand_empty_rest_of_line ();
14842 assert (S_GET_NAME (p
));
14843 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14844 as_warn (_(".end symbol does not match .ent symbol."));
14846 if (debug_type
== DEBUG_STABS
)
14847 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14851 as_warn (_(".end directive missing or unknown symbol"));
14854 /* Create an expression to calculate the size of the function. */
14855 if (p
&& cur_proc_ptr
)
14857 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14858 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14861 exp
->X_op
= O_subtract
;
14862 exp
->X_add_symbol
= symbol_temp_new_now ();
14863 exp
->X_op_symbol
= p
;
14864 exp
->X_add_number
= 0;
14866 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14869 /* Generate a .pdr section. */
14870 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14872 segT saved_seg
= now_seg
;
14873 subsegT saved_subseg
= now_subseg
;
14878 dot
= frag_now_fix ();
14880 #ifdef md_flush_pending_output
14881 md_flush_pending_output ();
14885 subseg_set (pdr_seg
, 0);
14887 /* Write the symbol. */
14888 exp
.X_op
= O_symbol
;
14889 exp
.X_add_symbol
= p
;
14890 exp
.X_add_number
= 0;
14891 emit_expr (&exp
, 4);
14893 fragp
= frag_more (7 * 4);
14895 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14896 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14897 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14898 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14899 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14900 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14901 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14903 subseg_set (saved_seg
, saved_subseg
);
14905 #endif /* OBJ_ELF */
14907 cur_proc_ptr
= NULL
;
14910 /* The .aent and .ent directives. */
14913 s_mips_ent (int aent
)
14917 symbolP
= get_symbol ();
14918 if (*input_line_pointer
== ',')
14919 ++input_line_pointer
;
14920 SKIP_WHITESPACE ();
14921 if (ISDIGIT (*input_line_pointer
)
14922 || *input_line_pointer
== '-')
14925 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14926 as_warn (_(".ent or .aent not in text section."));
14928 if (!aent
&& cur_proc_ptr
)
14929 as_warn (_("missing .end"));
14933 /* This function needs its own .frame and .cprestore directives. */
14934 mips_frame_reg_valid
= 0;
14935 mips_cprestore_valid
= 0;
14937 cur_proc_ptr
= &cur_proc
;
14938 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14940 cur_proc_ptr
->func_sym
= symbolP
;
14942 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14946 if (debug_type
== DEBUG_STABS
)
14947 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14948 S_GET_NAME (symbolP
));
14951 demand_empty_rest_of_line ();
14954 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14955 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14956 s_mips_frame is used so that we can set the PDR information correctly.
14957 We can't use the ecoff routines because they make reference to the ecoff
14958 symbol table (in the mdebug section). */
14961 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14964 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14968 if (cur_proc_ptr
== (procS
*) NULL
)
14970 as_warn (_(".frame outside of .ent"));
14971 demand_empty_rest_of_line ();
14975 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14977 SKIP_WHITESPACE ();
14978 if (*input_line_pointer
++ != ','
14979 || get_absolute_expression_and_terminator (&val
) != ',')
14981 as_warn (_("Bad .frame directive"));
14982 --input_line_pointer
;
14983 demand_empty_rest_of_line ();
14987 cur_proc_ptr
->frame_offset
= val
;
14988 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14990 demand_empty_rest_of_line ();
14993 #endif /* OBJ_ELF */
14997 /* The .fmask and .mask directives. If the mdebug section is present
14998 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14999 embedded targets, s_mips_mask is used so that we can set the PDR
15000 information correctly. We can't use the ecoff routines because they
15001 make reference to the ecoff symbol table (in the mdebug section). */
15004 s_mips_mask (int reg_type
)
15007 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15011 if (cur_proc_ptr
== (procS
*) NULL
)
15013 as_warn (_(".mask/.fmask outside of .ent"));
15014 demand_empty_rest_of_line ();
15018 if (get_absolute_expression_and_terminator (&mask
) != ',')
15020 as_warn (_("Bad .mask/.fmask directive"));
15021 --input_line_pointer
;
15022 demand_empty_rest_of_line ();
15026 off
= get_absolute_expression ();
15028 if (reg_type
== 'F')
15030 cur_proc_ptr
->fpreg_mask
= mask
;
15031 cur_proc_ptr
->fpreg_offset
= off
;
15035 cur_proc_ptr
->reg_mask
= mask
;
15036 cur_proc_ptr
->reg_offset
= off
;
15039 demand_empty_rest_of_line ();
15042 #endif /* OBJ_ELF */
15043 s_ignore (reg_type
);
15046 /* A table describing all the processors gas knows about. Names are
15047 matched in the order listed.
15049 To ease comparison, please keep this table in the same order as
15050 gcc's mips_cpu_info_table[]. */
15051 static const struct mips_cpu_info mips_cpu_info_table
[] =
15053 /* Entries for generic ISAs */
15054 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15055 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15056 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15057 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15058 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15059 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15060 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15061 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15062 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15065 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15066 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15067 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15070 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15073 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15074 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15075 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15076 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15077 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15078 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15079 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15080 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15081 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15082 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15083 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15084 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15085 /* ST Microelectronics Loongson 2E and 2F cores */
15086 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15087 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15090 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15091 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15092 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15093 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15094 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15095 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15096 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15097 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15098 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15099 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15100 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15101 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15102 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15105 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15106 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15107 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15108 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15110 /* MIPS 32 Release 2 */
15111 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15112 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15113 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15114 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15115 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15116 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15117 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15118 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15119 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15120 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15121 /* Deprecated forms of the above. */
15122 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15123 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15124 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15125 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15126 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15127 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15128 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15129 /* Deprecated forms of the above. */
15130 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15131 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15132 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15133 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15134 ISA_MIPS32R2
, CPU_MIPS32R2
},
15135 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15136 ISA_MIPS32R2
, CPU_MIPS32R2
},
15137 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15138 ISA_MIPS32R2
, CPU_MIPS32R2
},
15139 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15140 ISA_MIPS32R2
, CPU_MIPS32R2
},
15141 /* Deprecated forms of the above. */
15142 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15143 ISA_MIPS32R2
, CPU_MIPS32R2
},
15144 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15145 ISA_MIPS32R2
, CPU_MIPS32R2
},
15146 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15147 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15148 ISA_MIPS32R2
, CPU_MIPS32R2
},
15149 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15150 ISA_MIPS32R2
, CPU_MIPS32R2
},
15151 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15152 ISA_MIPS32R2
, CPU_MIPS32R2
},
15153 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15154 ISA_MIPS32R2
, CPU_MIPS32R2
},
15155 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15156 ISA_MIPS32R2
, CPU_MIPS32R2
},
15157 /* Deprecated forms of the above. */
15158 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15159 ISA_MIPS32R2
, CPU_MIPS32R2
},
15160 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15161 ISA_MIPS32R2
, CPU_MIPS32R2
},
15164 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15165 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15166 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15167 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15169 /* Broadcom SB-1 CPU core */
15170 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15171 ISA_MIPS64
, CPU_SB1
},
15172 /* Broadcom SB-1A CPU core */
15173 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15174 ISA_MIPS64
, CPU_SB1
},
15176 /* MIPS 64 Release 2 */
15178 /* Cavium Networks Octeon CPU core */
15179 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15186 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15187 with a final "000" replaced by "k". Ignore case.
15189 Note: this function is shared between GCC and GAS. */
15192 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15194 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15195 given
++, canonical
++;
15197 return ((*given
== 0 && *canonical
== 0)
15198 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15202 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15203 CPU name. We've traditionally allowed a lot of variation here.
15205 Note: this function is shared between GCC and GAS. */
15208 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15210 /* First see if the name matches exactly, or with a final "000"
15211 turned into "k". */
15212 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15215 /* If not, try comparing based on numerical designation alone.
15216 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15217 if (TOLOWER (*given
) == 'r')
15219 if (!ISDIGIT (*given
))
15222 /* Skip over some well-known prefixes in the canonical name,
15223 hoping to find a number there too. */
15224 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15226 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15228 else if (TOLOWER (canonical
[0]) == 'r')
15231 return mips_strict_matching_cpu_name_p (canonical
, given
);
15235 /* Parse an option that takes the name of a processor as its argument.
15236 OPTION is the name of the option and CPU_STRING is the argument.
15237 Return the corresponding processor enumeration if the CPU_STRING is
15238 recognized, otherwise report an error and return null.
15240 A similar function exists in GCC. */
15242 static const struct mips_cpu_info
*
15243 mips_parse_cpu (const char *option
, const char *cpu_string
)
15245 const struct mips_cpu_info
*p
;
15247 /* 'from-abi' selects the most compatible architecture for the given
15248 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15249 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15250 version. Look first at the -mgp options, if given, otherwise base
15251 the choice on MIPS_DEFAULT_64BIT.
15253 Treat NO_ABI like the EABIs. One reason to do this is that the
15254 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15255 architecture. This code picks MIPS I for 'mips' and MIPS III for
15256 'mips64', just as we did in the days before 'from-abi'. */
15257 if (strcasecmp (cpu_string
, "from-abi") == 0)
15259 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15260 return mips_cpu_info_from_isa (ISA_MIPS1
);
15262 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15263 return mips_cpu_info_from_isa (ISA_MIPS3
);
15265 if (file_mips_gp32
>= 0)
15266 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15268 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15273 /* 'default' has traditionally been a no-op. Probably not very useful. */
15274 if (strcasecmp (cpu_string
, "default") == 0)
15277 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15278 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15281 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15285 /* Return the canonical processor information for ISA (a member of the
15286 ISA_MIPS* enumeration). */
15288 static const struct mips_cpu_info
*
15289 mips_cpu_info_from_isa (int isa
)
15293 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15294 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15295 && isa
== mips_cpu_info_table
[i
].isa
)
15296 return (&mips_cpu_info_table
[i
]);
15301 static const struct mips_cpu_info
*
15302 mips_cpu_info_from_arch (int arch
)
15306 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15307 if (arch
== mips_cpu_info_table
[i
].cpu
)
15308 return (&mips_cpu_info_table
[i
]);
15314 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15318 fprintf (stream
, "%24s", "");
15323 fprintf (stream
, ", ");
15327 if (*col_p
+ strlen (string
) > 72)
15329 fprintf (stream
, "\n%24s", "");
15333 fprintf (stream
, "%s", string
);
15334 *col_p
+= strlen (string
);
15340 md_show_usage (FILE *stream
)
15345 fprintf (stream
, _("\
15347 -EB generate big endian output\n\
15348 -EL generate little endian output\n\
15349 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15350 -G NUM allow referencing objects up to NUM bytes\n\
15351 implicitly with the gp register [default 8]\n"));
15352 fprintf (stream
, _("\
15353 -mips1 generate MIPS ISA I instructions\n\
15354 -mips2 generate MIPS ISA II instructions\n\
15355 -mips3 generate MIPS ISA III instructions\n\
15356 -mips4 generate MIPS ISA IV instructions\n\
15357 -mips5 generate MIPS ISA V instructions\n\
15358 -mips32 generate MIPS32 ISA instructions\n\
15359 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15360 -mips64 generate MIPS64 ISA instructions\n\
15361 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15362 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15366 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15367 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15368 show (stream
, "from-abi", &column
, &first
);
15369 fputc ('\n', stream
);
15371 fprintf (stream
, _("\
15372 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15373 -no-mCPU don't generate code specific to CPU.\n\
15374 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15378 show (stream
, "3900", &column
, &first
);
15379 show (stream
, "4010", &column
, &first
);
15380 show (stream
, "4100", &column
, &first
);
15381 show (stream
, "4650", &column
, &first
);
15382 fputc ('\n', stream
);
15384 fprintf (stream
, _("\
15385 -mips16 generate mips16 instructions\n\
15386 -no-mips16 do not generate mips16 instructions\n"));
15387 fprintf (stream
, _("\
15388 -msmartmips generate smartmips instructions\n\
15389 -mno-smartmips do not generate smartmips instructions\n"));
15390 fprintf (stream
, _("\
15391 -mdsp generate DSP instructions\n\
15392 -mno-dsp do not generate DSP instructions\n"));
15393 fprintf (stream
, _("\
15394 -mdspr2 generate DSP R2 instructions\n\
15395 -mno-dspr2 do not generate DSP R2 instructions\n"));
15396 fprintf (stream
, _("\
15397 -mmt generate MT instructions\n\
15398 -mno-mt do not generate MT instructions\n"));
15399 fprintf (stream
, _("\
15400 -mfix-vr4120 work around certain VR4120 errata\n\
15401 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15402 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15403 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15404 -msym32 assume all symbols have 32-bit values\n\
15405 -O0 remove unneeded NOPs, do not swap branches\n\
15406 -O remove unneeded NOPs and swap branches\n\
15407 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15408 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15409 fprintf (stream
, _("\
15410 -mhard-float allow floating-point instructions\n\
15411 -msoft-float do not allow floating-point instructions\n\
15412 -msingle-float only allow 32-bit floating-point operations\n\
15413 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15414 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15417 fprintf (stream
, _("\
15418 -KPIC, -call_shared generate SVR4 position independent code\n\
15419 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15420 -mvxworks-pic generate VxWorks position independent code\n\
15421 -non_shared do not generate code that can operate with DSOs\n\
15422 -xgot assume a 32 bit GOT\n\
15423 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15424 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15425 position dependent (non shared) code\n\
15426 -mabi=ABI create ABI conformant object file for:\n"));
15430 show (stream
, "32", &column
, &first
);
15431 show (stream
, "o64", &column
, &first
);
15432 show (stream
, "n32", &column
, &first
);
15433 show (stream
, "64", &column
, &first
);
15434 show (stream
, "eabi", &column
, &first
);
15436 fputc ('\n', stream
);
15438 fprintf (stream
, _("\
15439 -32 create o32 ABI object file (default)\n\
15440 -n32 create n32 ABI object file\n\
15441 -64 create 64 ABI object file\n"));
15446 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15448 if (HAVE_64BIT_SYMBOLS
)
15451 return dwarf2_format_64bit_irix
;
15453 return dwarf2_format_64bit
;
15457 return dwarf2_format_32bit
;
15461 mips_dwarf2_addr_size (void)
15463 if (HAVE_64BIT_SYMBOLS
)
15469 /* Standard calling conventions leave the CFA at SP on entry. */
15471 mips_cfi_frame_initial_instructions (void)
15473 cfi_add_CFA_def_cfa_register (SP
);
15477 tc_mips_regname_to_dw2regnum (char *regname
)
15479 unsigned int regnum
= -1;
15482 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))