1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Whether we are assembling for the mips16 processor. 0 if we are
141 not, 1 if we are, and -1 if the value has not been initialized.
142 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
143 -nomips16 command line options, and the default CPU. */
145 /* Non-zero if we should not reorder instructions. Changed by `.set
146 reorder' and `.set noreorder'. */
148 /* Non-zero if we should not permit the $at ($1) register to be used
149 in instructions. Changed by `.set at' and `.set noat'. */
151 /* Non-zero if we should warn when a macro instruction expands into
152 more than one machine instruction. Changed by `.set nomacro' and
154 int warn_about_macros
;
155 /* Non-zero if we should not move instructions. Changed by `.set
156 move', `.set volatile', `.set nomove', and `.set novolatile'. */
158 /* Non-zero if we should not optimize branches by moving the target
159 of the branch into the delay slot. Actually, we don't perform
160 this optimization anyhow. Changed by `.set bopt' and `.set
163 /* Non-zero if we should not autoextend mips16 instructions.
164 Changed by `.set autoextend' and `.set noautoextend'. */
166 /* Restrict general purpose registers and floating point registers
167 to 32 bit. This is initially determined when -mgp32 or -mfp32
168 is passed but can changed if the assembler code uses .set mipsN. */
171 /* The ABI currently in use. This is changed by .set mipsN to loosen
172 restrictions and doesn't affect the whole file. */
173 enum mips_abi_level abi
;
176 /* True if -mgp32 was passed. */
177 static int file_mips_gp32
= 0;
179 /* True if -mfp32 was passed. */
180 static int file_mips_fp32
= 0;
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
184 -1 to indicate that they have not been initialized. */
186 static struct mips_set_options mips_opts
=
188 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
191 /* These variables are filled in with the masks of registers used.
192 The object format code reads them and puts them in the appropriate
194 unsigned long mips_gprmask
;
195 unsigned long mips_cprmask
[4];
197 /* MIPS ISA we are using for this output file. */
198 static int file_mips_isa
= ISA_UNKNOWN
;
200 /* The argument of the -mcpu= flag. Historical for code generation. */
201 static int mips_cpu
= CPU_UNKNOWN
;
203 /* The argument of the -march= flag. The architecture we are assembling. */
204 static int mips_arch
= CPU_UNKNOWN
;
206 /* The argument of the -mtune= flag. The architecture for which we
208 static int mips_tune
= CPU_UNKNOWN
;
210 /* Whether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64
= 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode
= 0;
217 /* Some ISA's have delay slots for instructions which read or write
218 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
219 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
220 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
221 delay slot in this ISA. The uses of this macro assume that any
222 ISA that has delay slots for one of these, has them for all. They
223 also assume that ISAs which don't have delays for these insns, don't
224 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
225 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 || (ISA) == ISA_MIPS2 \
228 || (ISA) == ISA_MIPS3 \
231 /* Return true if ISA supports 64 bit gp register instructions. */
232 #define ISA_HAS_64BIT_REGS(ISA) ( \
234 || (ISA) == ISA_MIPS4 \
235 || (ISA) == ISA_MIPS5 \
236 || (ISA) == ISA_MIPS64 \
239 #define HAVE_32BIT_GPRS \
241 || mips_opts.abi == O32_ABI \
242 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
244 #define HAVE_32BIT_FPRS \
246 || mips_opts.abi == O32_ABI \
247 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
249 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
250 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
252 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
254 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
256 /* We can only have 64bit addresses if the object file format
258 #define HAVE_32BIT_ADDRESSES \
260 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
261 || ! HAVE_64BIT_OBJECTS) \
262 && mips_pic != EMBEDDED_PIC))
264 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
266 /* Whether the processor uses hardware interlocks to protect
267 reads from the HI and LO registers, and thus does not
268 require nops to be inserted. */
270 #define hilo_interlocks (mips_arch == CPU_R4010 \
271 || mips_arch == CPU_SB1 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_arch == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_arch == CPU_R4300 \
284 || mips_arch == CPU_SB1 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic
;
314 /* Warn about all NOPS that the assembler generates. */
315 static int warn_nops
= 0;
317 /* 1 if we should generate 32 bit offsets from the GP register in
318 SVR4_PIC mode. Currently has no meaning in other modes. */
319 static int mips_big_got
;
321 /* 1 if trap instructions should used for overflow rather than break
323 static int mips_trap
;
325 /* 1 if double width floating point constants should not be constructed
326 by assembling two single width halves into two single width floating
327 point registers which just happen to alias the double width destination
328 register. On some architectures this aliasing can be disabled by a bit
329 in the status register, and the setting of this bit cannot be determined
330 automatically at assemble time. */
331 static int mips_disable_float_construction
;
333 /* Non-zero if any .set noreorder directives were used. */
335 static int mips_any_noreorder
;
337 /* Non-zero if nops should be inserted when the register referenced in
338 an mfhi/mflo instruction is read in the next two instructions. */
339 static int mips_7000_hilo_fix
;
341 /* The size of the small data section. */
342 static unsigned int g_switch_value
= 8;
343 /* Whether the -G option was used. */
344 static int g_switch_seen
= 0;
349 /* If we can determine in advance that GP optimization won't be
350 possible, we can skip the relaxation stuff that tries to produce
351 GP-relative references. This makes delay slot optimization work
354 This function can only provide a guess, but it seems to work for
355 gcc output. It needs to guess right for gcc, otherwise gcc
356 will put what it thinks is a GP-relative instruction in a branch
359 I don't know if a fix is needed for the SVR4_PIC mode. I've only
360 fixed it for the non-PIC mode. KR 95/04/07 */
361 static int nopic_need_relax
PARAMS ((symbolS
*, int));
363 /* handle of the OPCODE hash table */
364 static struct hash_control
*op_hash
= NULL
;
366 /* The opcode hash table we use for the mips16. */
367 static struct hash_control
*mips16_op_hash
= NULL
;
369 /* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371 const char comment_chars
[] = "#";
373 /* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376 /* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379 /* Also note that C style comments are always supported. */
380 const char line_comment_chars
[] = "#";
382 /* This array holds machine specific line separator characters. */
383 const char line_separator_chars
[] = ";";
385 /* Chars that can be used to separate mant from exp in floating point nums */
386 const char EXP_CHARS
[] = "eE";
388 /* Chars that mean this number is a floating point constant */
391 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
393 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
394 changed in read.c . Ideally it shouldn't have to know about it at all,
395 but nothing is ideal around here.
398 static char *insn_error
;
400 static int auto_align
= 1;
402 /* When outputting SVR4 PIC code, the assembler needs to know the
403 offset in the stack frame from which to restore the $gp register.
404 This is set by the .cprestore pseudo-op, and saved in this
406 static offsetT mips_cprestore_offset
= -1;
408 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
409 more optimizations, it can use a register value instead of a memory-saved
410 offset and even an other than GP as global pointer. */
411 static offsetT mips_cpreturn_offset
= -1;
412 static int mips_cpreturn_register
= -1;
413 static int mips_gp_register
= GP
;
415 /* This is the register which holds the stack frame, as set by the
416 .frame pseudo-op. This is needed to implement .cprestore. */
417 static int mips_frame_reg
= SP
;
419 /* To output NOP instructions correctly, we need to keep information
420 about the previous two instructions. */
422 /* Whether we are optimizing. The default value of 2 means to remove
423 unneeded NOPs and swap branch instructions when possible. A value
424 of 1 means to not swap branches. A value of 0 means to always
426 static int mips_optimize
= 2;
428 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
429 equivalent to seeing no -g option at all. */
430 static int mips_debug
= 0;
432 /* The previous instruction. */
433 static struct mips_cl_insn prev_insn
;
435 /* The instruction before prev_insn. */
436 static struct mips_cl_insn prev_prev_insn
;
438 /* If we don't want information for prev_insn or prev_prev_insn, we
439 point the insn_mo field at this dummy integer. */
440 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
442 /* Non-zero if prev_insn is valid. */
443 static int prev_insn_valid
;
445 /* The frag for the previous instruction. */
446 static struct frag
*prev_insn_frag
;
448 /* The offset into prev_insn_frag for the previous instruction. */
449 static long prev_insn_where
;
451 /* The reloc type for the previous instruction, if any. */
452 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
454 /* The reloc for the previous instruction, if any. */
455 static fixS
*prev_insn_fixp
[3];
457 /* Non-zero if the previous instruction was in a delay slot. */
458 static int prev_insn_is_delay_slot
;
460 /* Non-zero if the previous instruction was in a .set noreorder. */
461 static int prev_insn_unreordered
;
463 /* Non-zero if the previous instruction uses an extend opcode (if
465 static int prev_insn_extended
;
467 /* Non-zero if the previous previous instruction was in a .set
469 static int prev_prev_insn_unreordered
;
471 /* If this is set, it points to a frag holding nop instructions which
472 were inserted before the start of a noreorder section. If those
473 nops turn out to be unnecessary, the size of the frag can be
475 static fragS
*prev_nop_frag
;
477 /* The number of nop instructions we created in prev_nop_frag. */
478 static int prev_nop_frag_holds
;
480 /* The number of nop instructions that we know we need in
482 static int prev_nop_frag_required
;
484 /* The number of instructions we've seen since prev_nop_frag. */
485 static int prev_nop_frag_since
;
487 /* For ECOFF and ELF, relocations against symbols are done in two
488 parts, with a HI relocation and a LO relocation. Each relocation
489 has only 16 bits of space to store an addend. This means that in
490 order for the linker to handle carries correctly, it must be able
491 to locate both the HI and the LO relocation. This means that the
492 relocations must appear in order in the relocation table.
494 In order to implement this, we keep track of each unmatched HI
495 relocation. We then sort them so that they immediately precede the
496 corresponding LO relocation. */
501 struct mips_hi_fixup
*next
;
504 /* The section this fixup is in. */
508 /* The list of unmatched HI relocs. */
510 static struct mips_hi_fixup
*mips_hi_fixup_list
;
512 /* Map normal MIPS register numbers to mips16 register numbers. */
514 #define X ILLEGAL_REG
515 static const int mips32_to_16_reg_map
[] =
517 X
, X
, 2, 3, 4, 5, 6, 7,
518 X
, X
, X
, X
, X
, X
, X
, X
,
519 0, 1, X
, X
, X
, X
, X
, X
,
520 X
, X
, X
, X
, X
, X
, X
, X
524 /* Map mips16 register numbers to normal MIPS register numbers. */
526 static const unsigned int mips16_to_32_reg_map
[] =
528 16, 17, 2, 3, 4, 5, 6, 7
531 /* Since the MIPS does not have multiple forms of PC relative
532 instructions, we do not have to do relaxing as is done on other
533 platforms. However, we do have to handle GP relative addressing
534 correctly, which turns out to be a similar problem.
536 Every macro that refers to a symbol can occur in (at least) two
537 forms, one with GP relative addressing and one without. For
538 example, loading a global variable into a register generally uses
539 a macro instruction like this:
541 If i can be addressed off the GP register (this is true if it is in
542 the .sbss or .sdata section, or if it is known to be smaller than
543 the -G argument) this will generate the following instruction:
545 This instruction will use a GPREL reloc. If i can not be addressed
546 off the GP register, the following instruction sequence will be used:
549 In this case the first instruction will have a HI16 reloc, and the
550 second reloc will have a LO16 reloc. Both relocs will be against
553 The issue here is that we may not know whether i is GP addressable
554 until after we see the instruction that uses it. Therefore, we
555 want to be able to choose the final instruction sequence only at
556 the end of the assembly. This is similar to the way other
557 platforms choose the size of a PC relative instruction only at the
560 When generating position independent code we do not use GP
561 addressing in quite the same way, but the issue still arises as
562 external symbols and local symbols must be handled differently.
564 We handle these issues by actually generating both possible
565 instruction sequences. The longer one is put in a frag_var with
566 type rs_machine_dependent. We encode what to do with the frag in
567 the subtype field. We encode (1) the number of existing bytes to
568 replace, (2) the number of new bytes to use, (3) the offset from
569 the start of the existing bytes to the first reloc we must generate
570 (that is, the offset is applied from the start of the existing
571 bytes after they are replaced by the new bytes, if any), (4) the
572 offset from the start of the existing bytes to the second reloc,
573 (5) whether a third reloc is needed (the third reloc is always four
574 bytes after the second reloc), and (6) whether to warn if this
575 variant is used (this is sometimes needed if .set nomacro or .set
576 noat is in effect). All these numbers are reasonably small.
578 Generating two instruction sequences must be handled carefully to
579 ensure that delay slots are handled correctly. Fortunately, there
580 are a limited number of cases. When the second instruction
581 sequence is generated, append_insn is directed to maintain the
582 existing delay slot information, so it continues to apply to any
583 code after the second instruction sequence. This means that the
584 second instruction sequence must not impose any requirements not
585 required by the first instruction sequence.
587 These variant frags are then handled in functions called by the
588 machine independent code. md_estimate_size_before_relax returns
589 the final size of the frag. md_convert_frag sets up the final form
590 of the frag. tc_gen_reloc adjust the first reloc and adds a second
592 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
596 | (((reloc1) + 64) << 9) \
597 | (((reloc2) + 64) << 2) \
598 | ((reloc3) ? (1 << 1) : 0) \
600 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
601 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
602 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
603 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
604 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
605 #define RELAX_WARN(i) ((i) & 1)
607 /* For mips16 code, we use an entirely different form of relaxation.
608 mips16 supports two versions of most instructions which take
609 immediate values: a small one which takes some small value, and a
610 larger one which takes a 16 bit value. Since branches also follow
611 this pattern, relaxing these values is required.
613 We can assemble both mips16 and normal MIPS code in a single
614 object. Therefore, we need to support this type of relaxation at
615 the same time that we support the relaxation described above. We
616 use the high bit of the subtype field to distinguish these cases.
618 The information we store for this type of relaxation is the
619 argument code found in the opcode file for this relocation, whether
620 the user explicitly requested a small or extended form, and whether
621 the relocation is in a jump or jal delay slot. That tells us the
622 size of the value, and how it should be stored. We also store
623 whether the fragment is considered to be extended or not. We also
624 store whether this is known to be a branch to a different section,
625 whether we have tried to relax this frag yet, and whether we have
626 ever extended a PC relative fragment because of a shift count. */
627 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
630 | ((small) ? 0x100 : 0) \
631 | ((ext) ? 0x200 : 0) \
632 | ((dslot) ? 0x400 : 0) \
633 | ((jal_dslot) ? 0x800 : 0))
634 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
635 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
636 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
637 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
638 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
639 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
640 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
641 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
642 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
643 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
644 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
645 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
647 /* Prototypes for static functions. */
650 #define internalError() \
651 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
653 #define internalError() as_fatal (_("MIPS internal Error"));
656 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
658 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
659 unsigned int reg
, enum mips_regclass
class));
660 static int reg_needs_delay
PARAMS ((unsigned int));
661 static void mips16_mark_labels
PARAMS ((void));
662 static void append_insn
PARAMS ((char *place
,
663 struct mips_cl_insn
* ip
,
665 bfd_reloc_code_real_type
*r
,
667 static void mips_no_prev_insn
PARAMS ((int));
668 static void mips_emit_delays
PARAMS ((boolean
));
670 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
671 const char *name
, const char *fmt
,
674 static void macro_build ();
676 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
677 const char *, const char *,
679 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
680 expressionS
* ep
, int regnum
));
681 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
682 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
684 static void load_register
PARAMS ((int *, int, expressionS
*, int));
685 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
686 static void move_register
PARAMS ((int *, int, int));
687 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
688 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
689 #ifdef LOSING_COMPILER
690 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
692 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
693 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
694 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
695 boolean
, boolean
, unsigned long *,
696 boolean
*, unsigned short *));
697 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
698 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
699 static void my_getExpression
PARAMS ((expressionS
*, char *));
700 static int support_64bit_objects
PARAMS((void));
701 static symbolS
*get_symbol
PARAMS ((void));
702 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
703 static void s_align
PARAMS ((int));
704 static void s_change_sec
PARAMS ((int));
705 static void s_cons
PARAMS ((int));
706 static void s_float_cons
PARAMS ((int));
707 static void s_mips_globl
PARAMS ((int));
708 static void s_option
PARAMS ((int));
709 static void s_mipsset
PARAMS ((int));
710 static void s_abicalls
PARAMS ((int));
711 static void s_cpload
PARAMS ((int));
712 static void s_cpsetup
PARAMS ((int));
713 static void s_cplocal
PARAMS ((int));
714 static void s_cprestore
PARAMS ((int));
715 static void s_cpreturn
PARAMS ((int));
716 static void s_gpvalue
PARAMS ((int));
717 static void s_gpword
PARAMS ((int));
718 static void s_cpadd
PARAMS ((int));
719 static void s_insn
PARAMS ((int));
720 static void md_obj_begin
PARAMS ((void));
721 static void md_obj_end
PARAMS ((void));
722 static long get_number
PARAMS ((void));
723 static void s_mips_ent
PARAMS ((int));
724 static void s_mips_end
PARAMS ((int));
725 static void s_mips_frame
PARAMS ((int));
726 static void s_mips_mask
PARAMS ((int));
727 static void s_mips_stab
PARAMS ((int));
728 static void s_mips_weakext
PARAMS ((int));
729 static void s_file
PARAMS ((int));
730 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
731 static const char *mips_isa_to_str
PARAMS ((int));
732 static const char *mips_cpu_to_str
PARAMS ((int));
733 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
734 static void show
PARAMS ((FILE *, char *, int *, int *));
736 /* Return values of my_getSmallExpression(). */
743 /* Direct relocation creation by %percent_op(). */
762 /* Table and functions used to map between CPU/ISA names, and
763 ISA levels, and CPU numbers. */
767 const char *name
; /* CPU or ISA name. */
768 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
769 int isa
; /* ISA level. */
770 int cpu
; /* CPU number (default CPU if ISA). */
773 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
774 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
775 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
779 The following pseudo-ops from the Kane and Heinrich MIPS book
780 should be defined here, but are currently unsupported: .alias,
781 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
783 The following pseudo-ops from the Kane and Heinrich MIPS book are
784 specific to the type of debugging information being generated, and
785 should be defined by the object format: .aent, .begin, .bend,
786 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
789 The following pseudo-ops from the Kane and Heinrich MIPS book are
790 not MIPS CPU specific, but are also not specific to the object file
791 format. This file is probably the best place to define them, but
792 they are not currently supported: .asm0, .endr, .lab, .repeat,
795 static const pseudo_typeS mips_pseudo_table
[] =
797 /* MIPS specific pseudo-ops. */
798 {"option", s_option
, 0},
799 {"set", s_mipsset
, 0},
800 {"rdata", s_change_sec
, 'r'},
801 {"sdata", s_change_sec
, 's'},
802 {"livereg", s_ignore
, 0},
803 {"abicalls", s_abicalls
, 0},
804 {"cpload", s_cpload
, 0},
805 {"cpsetup", s_cpsetup
, 0},
806 {"cplocal", s_cplocal
, 0},
807 {"cprestore", s_cprestore
, 0},
808 {"cpreturn", s_cpreturn
, 0},
809 {"gpvalue", s_gpvalue
, 0},
810 {"gpword", s_gpword
, 0},
811 {"cpadd", s_cpadd
, 0},
814 /* Relatively generic pseudo-ops that happen to be used on MIPS
816 {"asciiz", stringer
, 1},
817 {"bss", s_change_sec
, 'b'},
820 {"dword", s_cons
, 3},
821 {"weakext", s_mips_weakext
, 0},
823 /* These pseudo-ops are defined in read.c, but must be overridden
824 here for one reason or another. */
825 {"align", s_align
, 0},
827 {"data", s_change_sec
, 'd'},
828 {"double", s_float_cons
, 'd'},
829 {"float", s_float_cons
, 'f'},
830 {"globl", s_mips_globl
, 0},
831 {"global", s_mips_globl
, 0},
832 {"hword", s_cons
, 1},
837 {"short", s_cons
, 1},
838 {"single", s_float_cons
, 'f'},
839 {"stabn", s_mips_stab
, 'n'},
840 {"text", s_change_sec
, 't'},
843 #ifdef MIPS_STABS_ELF
844 { "extern", ecoff_directive_extern
, 0},
850 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
852 /* These pseudo-ops should be defined by the object file format.
853 However, a.out doesn't support them, so we have versions here. */
854 {"aent", s_mips_ent
, 1},
855 {"bgnb", s_ignore
, 0},
856 {"end", s_mips_end
, 0},
857 {"endb", s_ignore
, 0},
858 {"ent", s_mips_ent
, 0},
860 {"fmask", s_mips_mask
, 'F'},
861 {"frame", s_mips_frame
, 0},
862 {"loc", s_ignore
, 0},
863 {"mask", s_mips_mask
, 'R'},
864 {"verstamp", s_ignore
, 0},
868 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
873 pop_insert (mips_pseudo_table
);
874 if (! ECOFF_DEBUGGING
)
875 pop_insert (mips_nonecoff_pseudo_table
);
878 /* Symbols labelling the current insn. */
880 struct insn_label_list
882 struct insn_label_list
*next
;
886 static struct insn_label_list
*insn_labels
;
887 static struct insn_label_list
*free_insn_labels
;
889 static void mips_clear_insn_labels
PARAMS ((void));
892 mips_clear_insn_labels ()
894 register struct insn_label_list
**pl
;
896 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
902 static char *expr_end
;
904 /* Expressions which appear in instructions. These are set by
907 static expressionS imm_expr
;
908 static expressionS offset_expr
;
910 /* Relocs associated with imm_expr and offset_expr. */
912 static bfd_reloc_code_real_type imm_reloc
[3]
913 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
914 static bfd_reloc_code_real_type offset_reloc
[3]
915 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
917 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
919 static boolean imm_unmatched_hi
;
921 /* These are set by mips16_ip if an explicit extension is used. */
923 static boolean mips16_small
, mips16_ext
;
925 #ifdef MIPS_STABS_ELF
926 /* The pdr segment for per procedure frame/regmask info */
932 mips_isa_to_str (isa
)
935 const struct mips_cpu_info
*ci
;
938 ci
= mips_cpu_info_from_isa (isa
);
942 sprintf (s
, "ISA#%d", isa
);
947 mips_cpu_to_str (cpu
)
950 const struct mips_cpu_info
*ci
;
953 ci
= mips_cpu_info_from_cpu (cpu
);
957 sprintf (s
, "CPU#%d", cpu
);
961 /* The default target format to use. */
964 mips_target_format ()
966 switch (OUTPUT_FLAVOR
)
968 case bfd_target_aout_flavour
:
969 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
970 case bfd_target_ecoff_flavour
:
971 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
972 case bfd_target_coff_flavour
:
974 case bfd_target_elf_flavour
:
976 /* This is traditional mips */
977 return (target_big_endian
978 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
979 : "elf32-tradbigmips")
980 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
981 : "elf32-tradlittlemips"));
983 return (target_big_endian
984 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
985 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
986 : "elf32-littlemips"));
994 /* This function is called once, at assembler startup time. It should
995 set up all the tables, etc. that the MD part of the assembler will need. */
1000 register const char *retval
= NULL
;
1005 int mips_isa_from_cpu
;
1006 int target_cpu_had_mips16
= 0;
1007 const struct mips_cpu_info
*ci
;
1009 /* GP relative stuff not working for PE */
1010 if (strncmp (TARGET_OS
, "pe", 2) == 0
1011 && g_switch_value
!= 0)
1014 as_bad (_("-G not supported in this configuration."));
1019 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1021 a
= xmalloc (sizeof TARGET_CPU
);
1022 strcpy (a
, TARGET_CPU
);
1023 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1027 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1029 target_cpu_had_mips16
= 1;
1030 cpu
+= sizeof "mips16" - 1;
1033 if (mips_opts
.mips16
< 0)
1034 mips_opts
.mips16
= target_cpu_had_mips16
;
1036 /* Backward compatibility for historic -mcpu= option. Check for
1037 incompatible options, warn if -mcpu is used. */
1038 if (mips_cpu
!= CPU_UNKNOWN
1039 && mips_arch
!= CPU_UNKNOWN
1040 && mips_cpu
!= mips_arch
)
1042 as_fatal (_("The -mcpu option can't be used together with -march. "
1043 "Use -mtune instead of -mcpu."));
1046 if (mips_cpu
!= CPU_UNKNOWN
1047 && mips_tune
!= CPU_UNKNOWN
1048 && mips_cpu
!= mips_tune
)
1050 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1051 "Use -march instead of -mcpu."));
1054 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1056 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1057 assert (ci
!= NULL
);
1058 mips_arch
= ci
->cpu
;
1059 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1060 "-mtune instead."));
1063 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1064 specified on the command line, or some other value if one was.
1065 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1066 the command line, or will be set otherwise if one was. */
1067 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1069 /* We have to check if the isa is the default isa of arch. Otherwise
1070 we'll get invalid object file headers. */
1071 ci
= mips_cpu_info_from_cpu (mips_arch
);
1072 assert (ci
!= NULL
);
1073 if (mips_opts
.isa
!= ci
->isa
)
1075 /* This really should be an error instead of a warning, but old
1076 compilers only have -mcpu which sets both arch and tune. For
1077 now, we discard arch and preserve tune. */
1078 as_warn (_("The -march option is incompatible to -mipsN and "
1079 "therefore ignored."));
1080 if (mips_tune
== CPU_UNKNOWN
)
1081 mips_tune
= mips_arch
;
1082 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1083 assert (ci
!= NULL
);
1084 mips_arch
= ci
->cpu
;
1087 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1089 /* We have ARCH, we need ISA. */
1090 ci
= mips_cpu_info_from_cpu (mips_arch
);
1091 assert (ci
!= NULL
);
1092 mips_opts
.isa
= ci
->isa
;
1094 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1096 /* We have ISA, we need default ARCH. */
1097 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1098 assert (ci
!= NULL
);
1099 mips_arch
= ci
->cpu
;
1103 /* We need to set both ISA and ARCH from target cpu. */
1104 ci
= mips_cpu_info_from_name (cpu
);
1106 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1107 assert (ci
!= NULL
);
1108 mips_opts
.isa
= ci
->isa
;
1109 mips_arch
= ci
->cpu
;
1112 if (mips_tune
== CPU_UNKNOWN
)
1113 mips_tune
= mips_arch
;
1115 ci
= mips_cpu_info_from_cpu (mips_arch
);
1116 assert (ci
!= NULL
);
1117 mips_isa_from_cpu
= ci
->isa
;
1119 /* End of TARGET_CPU processing, get rid of malloced memory
1128 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1129 as_bad (_("trap exception not supported at ISA 1"));
1131 /* Set the EABI kind based on the ISA before the user gets
1132 to change the ISA with directives. This isn't really
1133 the best, but then neither is basing the abi on the isa. */
1134 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1135 && mips_opts
.abi
== EABI_ABI
)
1138 /* If they asked for mips1 or mips2 and a cpu that is
1139 mips3 or greater, then mark the object file 32BITMODE. */
1140 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1141 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1142 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1145 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1146 as_warn (_("Could not set architecture and machine"));
1148 file_mips_isa
= mips_opts
.isa
;
1149 file_mips_abi
= mips_opts
.abi
;
1150 mips_opts
.gp32
= file_mips_gp32
;
1151 mips_opts
.fp32
= file_mips_fp32
;
1153 op_hash
= hash_new ();
1155 for (i
= 0; i
< NUMOPCODES
;)
1157 const char *name
= mips_opcodes
[i
].name
;
1159 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1162 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1163 mips_opcodes
[i
].name
, retval
);
1164 /* Probably a memory allocation problem? Give up now. */
1165 as_fatal (_("Broken assembler. No assembly attempted."));
1169 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1171 if (!validate_mips_insn (&mips_opcodes
[i
]))
1176 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1179 mips16_op_hash
= hash_new ();
1182 while (i
< bfd_mips16_num_opcodes
)
1184 const char *name
= mips16_opcodes
[i
].name
;
1186 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1188 as_fatal (_("internal: can't hash `%s': %s"),
1189 mips16_opcodes
[i
].name
, retval
);
1192 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1193 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1194 != mips16_opcodes
[i
].match
))
1196 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1197 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1202 while (i
< bfd_mips16_num_opcodes
1203 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1207 as_fatal (_("Broken assembler. No assembly attempted."));
1209 /* We add all the general register names to the symbol table. This
1210 helps us detect invalid uses of them. */
1211 for (i
= 0; i
< 32; i
++)
1215 sprintf (buf
, "$%d", i
);
1216 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1217 &zero_address_frag
));
1219 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1220 &zero_address_frag
));
1221 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1222 &zero_address_frag
));
1223 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1224 &zero_address_frag
));
1225 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1226 &zero_address_frag
));
1227 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1228 &zero_address_frag
));
1229 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1230 &zero_address_frag
));
1231 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1232 &zero_address_frag
));
1234 mips_no_prev_insn (false);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 if (USE_GLOBAL_POINTER_OPT
)
1246 bfd_set_gp_size (stdoutput
, g_switch_value
);
1248 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1250 /* On a native system, sections must be aligned to 16 byte
1251 boundaries. When configured for an embedded ELF target, we
1253 if (strcmp (TARGET_OS
, "elf") != 0)
1255 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1257 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1260 /* Create a .reginfo section for register masks and a .mdebug
1261 section for debugging information. */
1269 subseg
= now_subseg
;
1271 /* The ABI says this section should be loaded so that the
1272 running program can access it. However, we don't load it
1273 if we are configured for an embedded target */
1274 flags
= SEC_READONLY
| SEC_DATA
;
1275 if (strcmp (TARGET_OS
, "elf") != 0)
1276 flags
|= SEC_ALLOC
| SEC_LOAD
;
1280 sec
= subseg_new (".reginfo", (subsegT
) 0);
1282 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1283 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1286 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1291 /* The 64-bit ABI uses a .MIPS.options section rather than
1292 .reginfo section. */
1293 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1294 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1295 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1298 /* Set up the option header. */
1300 Elf_Internal_Options opthdr
;
1303 opthdr
.kind
= ODK_REGINFO
;
1304 opthdr
.size
= (sizeof (Elf_External_Options
)
1305 + sizeof (Elf64_External_RegInfo
));
1308 f
= frag_more (sizeof (Elf_External_Options
));
1309 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1310 (Elf_External_Options
*) f
);
1312 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1317 if (ECOFF_DEBUGGING
)
1319 sec
= subseg_new (".mdebug", (subsegT
) 0);
1320 (void) bfd_set_section_flags (stdoutput
, sec
,
1321 SEC_HAS_CONTENTS
| SEC_READONLY
);
1322 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1325 #ifdef MIPS_STABS_ELF
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1329 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1332 subseg_set (seg
, subseg
);
1336 if (! ECOFF_DEBUGGING
)
1343 if (! ECOFF_DEBUGGING
)
1351 struct mips_cl_insn insn
;
1352 bfd_reloc_code_real_type unused_reloc
[3]
1353 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1355 imm_expr
.X_op
= O_absent
;
1356 imm_unmatched_hi
= false;
1357 offset_expr
.X_op
= O_absent
;
1358 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1359 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1361 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1365 if (mips_opts
.mips16
)
1366 mips16_ip (str
, &insn
);
1369 mips_ip (str
, &insn
);
1370 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1371 str
, insn
.insn_opcode
));
1376 as_bad ("%s `%s'", insn_error
, str
);
1380 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1382 if (mips_opts
.mips16
)
1383 mips16_macro (&insn
);
1389 if (imm_expr
.X_op
!= O_absent
)
1390 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1392 else if (offset_expr
.X_op
!= O_absent
)
1393 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1395 append_insn ((char *) NULL
, &insn
, NULL
, unused_reloc
, false);
1399 /* See whether instruction IP reads register REG. CLASS is the type
1403 insn_uses_reg (ip
, reg
, class)
1404 struct mips_cl_insn
*ip
;
1406 enum mips_regclass
class;
1408 if (class == MIPS16_REG
)
1410 assert (mips_opts
.mips16
);
1411 reg
= mips16_to_32_reg_map
[reg
];
1412 class = MIPS_GR_REG
;
1415 /* Don't report on general register 0, since it never changes. */
1416 if (class == MIPS_GR_REG
&& reg
== 0)
1419 if (class == MIPS_FP_REG
)
1421 assert (! mips_opts
.mips16
);
1422 /* If we are called with either $f0 or $f1, we must check $f0.
1423 This is not optimal, because it will introduce an unnecessary
1424 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1425 need to distinguish reading both $f0 and $f1 or just one of
1426 them. Note that we don't have to check the other way,
1427 because there is no instruction that sets both $f0 and $f1
1428 and requires a delay. */
1429 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1430 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1431 == (reg
&~ (unsigned) 1)))
1433 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1434 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1435 == (reg
&~ (unsigned) 1)))
1438 else if (! mips_opts
.mips16
)
1440 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1441 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1443 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1444 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1449 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1450 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1451 & MIPS16OP_MASK_RX
)]
1454 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1455 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1456 & MIPS16OP_MASK_RY
)]
1459 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1460 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1461 & MIPS16OP_MASK_MOVE32Z
)]
1464 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1466 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1468 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1470 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1471 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1472 & MIPS16OP_MASK_REGR32
) == reg
)
1479 /* This function returns true if modifying a register requires a
1483 reg_needs_delay (reg
)
1486 unsigned long prev_pinfo
;
1488 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1489 if (! mips_opts
.noreorder
1490 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1491 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1492 || (! gpr_interlocks
1493 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1495 /* A load from a coprocessor or from memory. All load
1496 delays delay the use of general register rt for one
1497 instruction on the r3000. The r6000 and r4000 use
1499 /* Itbl support may require additional care here. */
1500 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1501 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1508 /* Mark instruction labels in mips16 mode. This permits the linker to
1509 handle them specially, such as generating jalx instructions when
1510 needed. We also make them odd for the duration of the assembly, in
1511 order to generate the right sort of code. We will make them even
1512 in the adjust_symtab routine, while leaving them marked. This is
1513 convenient for the debugger and the disassembler. The linker knows
1514 to make them odd again. */
1517 mips16_mark_labels ()
1519 if (mips_opts
.mips16
)
1521 struct insn_label_list
*l
;
1524 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1527 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1528 S_SET_OTHER (l
->label
, STO_MIPS16
);
1530 val
= S_GET_VALUE (l
->label
);
1532 S_SET_VALUE (l
->label
, val
+ 1);
1537 /* Output an instruction. PLACE is where to put the instruction; if
1538 it is NULL, this uses frag_more to get room. IP is the instruction
1539 information. ADDRESS_EXPR is an operand of the instruction to be
1540 used with RELOC_TYPE. */
1543 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1545 struct mips_cl_insn
*ip
;
1546 expressionS
*address_expr
;
1547 bfd_reloc_code_real_type
*reloc_type
;
1548 boolean unmatched_hi
;
1550 register unsigned long prev_pinfo
, pinfo
;
1555 /* Mark instruction labels in mips16 mode. */
1556 if (mips_opts
.mips16
)
1557 mips16_mark_labels ();
1559 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1560 pinfo
= ip
->insn_mo
->pinfo
;
1562 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1566 /* If the previous insn required any delay slots, see if we need
1567 to insert a NOP or two. There are eight kinds of possible
1568 hazards, of which an instruction can have at most one type.
1569 (1) a load from memory delay
1570 (2) a load from a coprocessor delay
1571 (3) an unconditional branch delay
1572 (4) a conditional branch delay
1573 (5) a move to coprocessor register delay
1574 (6) a load coprocessor register from memory delay
1575 (7) a coprocessor condition code delay
1576 (8) a HI/LO special register delay
1578 There are a lot of optimizations we could do that we don't.
1579 In particular, we do not, in general, reorder instructions.
1580 If you use gcc with optimization, it will reorder
1581 instructions and generally do much more optimization then we
1582 do here; repeating all that work in the assembler would only
1583 benefit hand written assembly code, and does not seem worth
1586 /* This is how a NOP is emitted. */
1587 #define emit_nop() \
1589 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1590 : md_number_to_chars (frag_more (4), 0, 4))
1592 /* The previous insn might require a delay slot, depending upon
1593 the contents of the current insn. */
1594 if (! mips_opts
.mips16
1595 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1596 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1597 && ! cop_interlocks
)
1598 || (! gpr_interlocks
1599 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1601 /* A load from a coprocessor or from memory. All load
1602 delays delay the use of general register rt for one
1603 instruction on the r3000. The r6000 and r4000 use
1605 /* Itbl support may require additional care here. */
1606 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1607 if (mips_optimize
== 0
1608 || insn_uses_reg (ip
,
1609 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1614 else if (! mips_opts
.mips16
1615 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1616 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1617 && ! cop_interlocks
)
1618 || (mips_opts
.isa
== ISA_MIPS1
1619 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1621 /* A generic coprocessor delay. The previous instruction
1622 modified a coprocessor general or control register. If
1623 it modified a control register, we need to avoid any
1624 coprocessor instruction (this is probably not always
1625 required, but it sometimes is). If it modified a general
1626 register, we avoid using that register.
1628 On the r6000 and r4000 loading a coprocessor register
1629 from memory is interlocked, and does not require a delay.
1631 This case is not handled very well. There is no special
1632 knowledge of CP0 handling, and the coprocessors other
1633 than the floating point unit are not distinguished at
1635 /* Itbl support may require additional care here. FIXME!
1636 Need to modify this to include knowledge about
1637 user specified delays! */
1638 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1640 if (mips_optimize
== 0
1641 || insn_uses_reg (ip
,
1642 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1647 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1649 if (mips_optimize
== 0
1650 || insn_uses_reg (ip
,
1651 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1658 /* We don't know exactly what the previous instruction
1659 does. If the current instruction uses a coprocessor
1660 register, we must insert a NOP. If previous
1661 instruction may set the condition codes, and the
1662 current instruction uses them, we must insert two
1664 /* Itbl support may require additional care here. */
1665 if (mips_optimize
== 0
1666 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1667 && (pinfo
& INSN_READ_COND_CODE
)))
1669 else if (pinfo
& INSN_COP
)
1673 else if (! mips_opts
.mips16
1674 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1675 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1676 && ! cop_interlocks
)
1678 /* The previous instruction sets the coprocessor condition
1679 codes, but does not require a general coprocessor delay
1680 (this means it is a floating point comparison
1681 instruction). If this instruction uses the condition
1682 codes, we need to insert a single NOP. */
1683 /* Itbl support may require additional care here. */
1684 if (mips_optimize
== 0
1685 || (pinfo
& INSN_READ_COND_CODE
))
1689 /* If we're fixing up mfhi/mflo for the r7000 and the
1690 previous insn was an mfhi/mflo and the current insn
1691 reads the register that the mfhi/mflo wrote to, then
1694 else if (mips_7000_hilo_fix
1695 && MF_HILO_INSN (prev_pinfo
)
1696 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1703 /* If we're fixing up mfhi/mflo for the r7000 and the
1704 2nd previous insn was an mfhi/mflo and the current insn
1705 reads the register that the mfhi/mflo wrote to, then
1708 else if (mips_7000_hilo_fix
1709 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1710 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1718 else if (prev_pinfo
& INSN_READ_LO
)
1720 /* The previous instruction reads the LO register; if the
1721 current instruction writes to the LO register, we must
1722 insert two NOPS. Some newer processors have interlocks.
1723 Also the tx39's multiply instructions can be exectuted
1724 immediatly after a read from HI/LO (without the delay),
1725 though the tx39's divide insns still do require the
1727 if (! (hilo_interlocks
1728 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1729 && (mips_optimize
== 0
1730 || (pinfo
& INSN_WRITE_LO
)))
1732 /* Most mips16 branch insns don't have a delay slot.
1733 If a read from LO is immediately followed by a branch
1734 to a write to LO we have a read followed by a write
1735 less than 2 insns away. We assume the target of
1736 a branch might be a write to LO, and insert a nop
1737 between a read and an immediately following branch. */
1738 else if (mips_opts
.mips16
1739 && (mips_optimize
== 0
1740 || (pinfo
& MIPS16_INSN_BRANCH
)))
1743 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1745 /* The previous instruction reads the HI register; if the
1746 current instruction writes to the HI register, we must
1747 insert a NOP. Some newer processors have interlocks.
1748 Also the note tx39's multiply above. */
1749 if (! (hilo_interlocks
1750 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1751 && (mips_optimize
== 0
1752 || (pinfo
& INSN_WRITE_HI
)))
1754 /* Most mips16 branch insns don't have a delay slot.
1755 If a read from HI is immediately followed by a branch
1756 to a write to HI we have a read followed by a write
1757 less than 2 insns away. We assume the target of
1758 a branch might be a write to HI, and insert a nop
1759 between a read and an immediately following branch. */
1760 else if (mips_opts
.mips16
1761 && (mips_optimize
== 0
1762 || (pinfo
& MIPS16_INSN_BRANCH
)))
1766 /* If the previous instruction was in a noreorder section, then
1767 we don't want to insert the nop after all. */
1768 /* Itbl support may require additional care here. */
1769 if (prev_insn_unreordered
)
1772 /* There are two cases which require two intervening
1773 instructions: 1) setting the condition codes using a move to
1774 coprocessor instruction which requires a general coprocessor
1775 delay and then reading the condition codes 2) reading the HI
1776 or LO register and then writing to it (except on processors
1777 which have interlocks). If we are not already emitting a NOP
1778 instruction, we must check for these cases compared to the
1779 instruction previous to the previous instruction. */
1780 if ((! mips_opts
.mips16
1781 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1782 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1783 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1784 && (pinfo
& INSN_READ_COND_CODE
)
1785 && ! cop_interlocks
)
1786 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1787 && (pinfo
& INSN_WRITE_LO
)
1788 && ! (hilo_interlocks
1789 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1790 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1791 && (pinfo
& INSN_WRITE_HI
)
1792 && ! (hilo_interlocks
1793 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1798 if (prev_prev_insn_unreordered
)
1801 if (prev_prev_nop
&& nops
== 0)
1804 /* If we are being given a nop instruction, don't bother with
1805 one of the nops we would otherwise output. This will only
1806 happen when a nop instruction is used with mips_optimize set
1809 && ! mips_opts
.noreorder
1810 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1813 /* Now emit the right number of NOP instructions. */
1814 if (nops
> 0 && ! mips_opts
.noreorder
)
1817 unsigned long old_frag_offset
;
1819 struct insn_label_list
*l
;
1821 old_frag
= frag_now
;
1822 old_frag_offset
= frag_now_fix ();
1824 for (i
= 0; i
< nops
; i
++)
1829 listing_prev_line ();
1830 /* We may be at the start of a variant frag. In case we
1831 are, make sure there is enough space for the frag
1832 after the frags created by listing_prev_line. The
1833 argument to frag_grow here must be at least as large
1834 as the argument to all other calls to frag_grow in
1835 this file. We don't have to worry about being in the
1836 middle of a variant frag, because the variants insert
1837 all needed nop instructions themselves. */
1841 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1845 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1846 symbol_set_frag (l
->label
, frag_now
);
1847 val
= (valueT
) frag_now_fix ();
1848 /* mips16 text labels are stored as odd. */
1849 if (mips_opts
.mips16
)
1851 S_SET_VALUE (l
->label
, val
);
1854 #ifndef NO_ECOFF_DEBUGGING
1855 if (ECOFF_DEBUGGING
)
1856 ecoff_fix_loc (old_frag
, old_frag_offset
);
1859 else if (prev_nop_frag
!= NULL
)
1861 /* We have a frag holding nops we may be able to remove. If
1862 we don't need any nops, we can decrease the size of
1863 prev_nop_frag by the size of one instruction. If we do
1864 need some nops, we count them in prev_nops_required. */
1865 if (prev_nop_frag_since
== 0)
1869 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1870 --prev_nop_frag_holds
;
1873 prev_nop_frag_required
+= nops
;
1877 if (prev_prev_nop
== 0)
1879 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1880 --prev_nop_frag_holds
;
1883 ++prev_nop_frag_required
;
1886 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1887 prev_nop_frag
= NULL
;
1889 ++prev_nop_frag_since
;
1891 /* Sanity check: by the time we reach the second instruction
1892 after prev_nop_frag, we should have used up all the nops
1893 one way or another. */
1894 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1898 if (*reloc_type
> BFD_RELOC_UNUSED
)
1900 /* We need to set up a variant frag. */
1901 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1902 f
= frag_var (rs_machine_dependent
, 4, 0,
1903 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1904 mips16_small
, mips16_ext
,
1906 & INSN_UNCOND_BRANCH_DELAY
),
1907 (*prev_insn_reloc_type
1908 == BFD_RELOC_MIPS16_JMP
)),
1909 make_expr_symbol (address_expr
), (offsetT
) 0,
1912 else if (place
!= NULL
)
1914 else if (mips_opts
.mips16
1916 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1918 /* Make sure there is enough room to swap this instruction with
1919 a following jump instruction. */
1925 if (mips_opts
.mips16
1926 && mips_opts
.noreorder
1927 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1928 as_warn (_("extended instruction in delay slot"));
1933 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1934 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1936 if (address_expr
->X_op
== O_constant
)
1940 switch (*reloc_type
)
1943 ip
->insn_opcode
|= address_expr
->X_add_number
;
1946 case BFD_RELOC_MIPS_HIGHEST
:
1947 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1949 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1952 case BFD_RELOC_MIPS_HIGHER
:
1953 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1954 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1957 case BFD_RELOC_HI16_S
:
1958 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1962 case BFD_RELOC_HI16
:
1963 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1966 case BFD_RELOC_LO16
:
1967 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1970 case BFD_RELOC_MIPS_JMP
:
1971 if ((address_expr
->X_add_number
& 3) != 0)
1972 as_bad (_("jump to misaligned address (0x%lx)"),
1973 (unsigned long) address_expr
->X_add_number
);
1974 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1977 case BFD_RELOC_MIPS16_JMP
:
1978 if ((address_expr
->X_add_number
& 3) != 0)
1979 as_bad (_("jump to misaligned address (0x%lx)"),
1980 (unsigned long) address_expr
->X_add_number
);
1982 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1983 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1984 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1987 case BFD_RELOC_16_PCREL
:
1988 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1991 case BFD_RELOC_16_PCREL_S2
:
2001 /* Don't generate a reloc if we are writing into a variant frag. */
2004 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2006 (*reloc_type
== BFD_RELOC_16_PCREL
2007 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2010 /* These relocations can have an addend that won't fit in
2011 4 octets for 64bit assembly. */
2012 if (HAVE_64BIT_GPRS
&&
2013 (*reloc_type
== BFD_RELOC_16
2014 || *reloc_type
== BFD_RELOC_32
2015 || *reloc_type
== BFD_RELOC_MIPS_JMP
2016 || *reloc_type
== BFD_RELOC_HI16_S
2017 || *reloc_type
== BFD_RELOC_LO16
2018 || *reloc_type
== BFD_RELOC_GPREL16
2019 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2020 || *reloc_type
== BFD_RELOC_GPREL32
2021 || *reloc_type
== BFD_RELOC_64
2022 || *reloc_type
== BFD_RELOC_CTOR
2023 || *reloc_type
== BFD_RELOC_MIPS_SUB
2024 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2025 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2026 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2027 || *reloc_type
== BFD_RELOC_MIPS_REL16
2028 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2029 fixp
[0]->fx_no_overflow
= 1;
2033 struct mips_hi_fixup
*hi_fixup
;
2035 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2036 hi_fixup
= ((struct mips_hi_fixup
*)
2037 xmalloc (sizeof (struct mips_hi_fixup
)));
2038 hi_fixup
->fixp
= fixp
[0];
2039 hi_fixup
->seg
= now_seg
;
2040 hi_fixup
->next
= mips_hi_fixup_list
;
2041 mips_hi_fixup_list
= hi_fixup
;
2044 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2046 /* FIXME: This symbol can be one of
2047 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2048 address_expr
->X_op
= O_absent
;
2049 address_expr
->X_add_symbol
= 0;
2050 address_expr
->X_add_number
= 0;
2052 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2053 4, address_expr
, false,
2056 /* These relocations can have an addend that won't fit in
2057 4 octets for 64bit assembly. */
2058 if (HAVE_64BIT_GPRS
&&
2059 (*reloc_type
== BFD_RELOC_16
2060 || *reloc_type
== BFD_RELOC_32
2061 || *reloc_type
== BFD_RELOC_MIPS_JMP
2062 || *reloc_type
== BFD_RELOC_HI16_S
2063 || *reloc_type
== BFD_RELOC_LO16
2064 || *reloc_type
== BFD_RELOC_GPREL16
2065 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2066 || *reloc_type
== BFD_RELOC_GPREL32
2067 || *reloc_type
== BFD_RELOC_64
2068 || *reloc_type
== BFD_RELOC_CTOR
2069 || *reloc_type
== BFD_RELOC_MIPS_SUB
2070 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2071 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2072 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2073 || *reloc_type
== BFD_RELOC_MIPS_REL16
2074 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2075 fixp
[1]->fx_no_overflow
= 1;
2077 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2079 address_expr
->X_op
= O_absent
;
2080 address_expr
->X_add_symbol
= 0;
2081 address_expr
->X_add_number
= 0;
2083 fixp
[2] = fix_new_exp (frag_now
,
2084 f
- frag_now
->fr_literal
, 4,
2085 address_expr
, false,
2088 /* These relocations can have an addend that won't fit in
2089 4 octets for 64bit assembly. */
2090 if (HAVE_64BIT_GPRS
&&
2091 (*reloc_type
== BFD_RELOC_16
2092 || *reloc_type
== BFD_RELOC_32
2093 || *reloc_type
== BFD_RELOC_MIPS_JMP
2094 || *reloc_type
== BFD_RELOC_HI16_S
2095 || *reloc_type
== BFD_RELOC_LO16
2096 || *reloc_type
== BFD_RELOC_GPREL16
2097 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2098 || *reloc_type
== BFD_RELOC_GPREL32
2099 || *reloc_type
== BFD_RELOC_64
2100 || *reloc_type
== BFD_RELOC_CTOR
2101 || *reloc_type
== BFD_RELOC_MIPS_SUB
2102 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2103 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2104 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2105 || *reloc_type
== BFD_RELOC_MIPS_REL16
2106 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2107 fixp
[2]->fx_no_overflow
= 1;
2114 if (! mips_opts
.mips16
)
2115 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2116 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2118 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2119 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2125 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2128 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2131 /* Update the register mask information. */
2132 if (! mips_opts
.mips16
)
2134 if (pinfo
& INSN_WRITE_GPR_D
)
2135 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2136 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2137 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2138 if (pinfo
& INSN_READ_GPR_S
)
2139 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2140 if (pinfo
& INSN_WRITE_GPR_31
)
2141 mips_gprmask
|= 1 << 31;
2142 if (pinfo
& INSN_WRITE_FPR_D
)
2143 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2144 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2145 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2146 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2147 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2148 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2149 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2150 if (pinfo
& INSN_COP
)
2152 /* We don't keep enough information to sort these cases out.
2153 The itbl support does keep this information however, although
2154 we currently don't support itbl fprmats as part of the cop
2155 instruction. May want to add this support in the future. */
2157 /* Never set the bit for $0, which is always zero. */
2158 mips_gprmask
&= ~1 << 0;
2162 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2163 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2164 & MIPS16OP_MASK_RX
);
2165 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2166 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2167 & MIPS16OP_MASK_RY
);
2168 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2169 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2170 & MIPS16OP_MASK_RZ
);
2171 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2172 mips_gprmask
|= 1 << TREG
;
2173 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2174 mips_gprmask
|= 1 << SP
;
2175 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2176 mips_gprmask
|= 1 << RA
;
2177 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2178 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2179 if (pinfo
& MIPS16_INSN_READ_Z
)
2180 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2181 & MIPS16OP_MASK_MOVE32Z
);
2182 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2183 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2184 & MIPS16OP_MASK_REGR32
);
2187 if (place
== NULL
&& ! mips_opts
.noreorder
)
2189 /* Filling the branch delay slot is more complex. We try to
2190 switch the branch with the previous instruction, which we can
2191 do if the previous instruction does not set up a condition
2192 that the branch tests and if the branch is not itself the
2193 target of any branch. */
2194 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2195 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2197 if (mips_optimize
< 2
2198 /* If we have seen .set volatile or .set nomove, don't
2200 || mips_opts
.nomove
!= 0
2201 /* If we had to emit any NOP instructions, then we
2202 already know we can not swap. */
2204 /* If we don't even know the previous insn, we can not
2206 || ! prev_insn_valid
2207 /* If the previous insn is already in a branch delay
2208 slot, then we can not swap. */
2209 || prev_insn_is_delay_slot
2210 /* If the previous previous insn was in a .set
2211 noreorder, we can't swap. Actually, the MIPS
2212 assembler will swap in this situation. However, gcc
2213 configured -with-gnu-as will generate code like
2219 in which we can not swap the bne and INSN. If gcc is
2220 not configured -with-gnu-as, it does not output the
2221 .set pseudo-ops. We don't have to check
2222 prev_insn_unreordered, because prev_insn_valid will
2223 be 0 in that case. We don't want to use
2224 prev_prev_insn_valid, because we do want to be able
2225 to swap at the start of a function. */
2226 || prev_prev_insn_unreordered
2227 /* If the branch is itself the target of a branch, we
2228 can not swap. We cheat on this; all we check for is
2229 whether there is a label on this instruction. If
2230 there are any branches to anything other than a
2231 label, users must use .set noreorder. */
2232 || insn_labels
!= NULL
2233 /* If the previous instruction is in a variant frag, we
2234 can not do the swap. This does not apply to the
2235 mips16, which uses variant frags for different
2237 || (! mips_opts
.mips16
2238 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2239 /* If the branch reads the condition codes, we don't
2240 even try to swap, because in the sequence
2245 we can not swap, and I don't feel like handling that
2247 || (! mips_opts
.mips16
2248 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2249 && (pinfo
& INSN_READ_COND_CODE
))
2250 /* We can not swap with an instruction that requires a
2251 delay slot, becase the target of the branch might
2252 interfere with that instruction. */
2253 || (! mips_opts
.mips16
2254 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2256 /* Itbl support may require additional care here. */
2257 & (INSN_LOAD_COPROC_DELAY
2258 | INSN_COPROC_MOVE_DELAY
2259 | INSN_WRITE_COND_CODE
)))
2260 || (! (hilo_interlocks
2261 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2265 || (! mips_opts
.mips16
2267 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2268 || (! mips_opts
.mips16
2269 && mips_opts
.isa
== ISA_MIPS1
2270 /* Itbl support may require additional care here. */
2271 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2272 /* We can not swap with a branch instruction. */
2274 & (INSN_UNCOND_BRANCH_DELAY
2275 | INSN_COND_BRANCH_DELAY
2276 | INSN_COND_BRANCH_LIKELY
))
2277 /* We do not swap with a trap instruction, since it
2278 complicates trap handlers to have the trap
2279 instruction be in a delay slot. */
2280 || (prev_pinfo
& INSN_TRAP
)
2281 /* If the branch reads a register that the previous
2282 instruction sets, we can not swap. */
2283 || (! mips_opts
.mips16
2284 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2285 && insn_uses_reg (ip
,
2286 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2289 || (! mips_opts
.mips16
2290 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2291 && insn_uses_reg (ip
,
2292 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2295 || (mips_opts
.mips16
2296 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2297 && insn_uses_reg (ip
,
2298 ((prev_insn
.insn_opcode
2300 & MIPS16OP_MASK_RX
),
2302 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2303 && insn_uses_reg (ip
,
2304 ((prev_insn
.insn_opcode
2306 & MIPS16OP_MASK_RY
),
2308 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2309 && insn_uses_reg (ip
,
2310 ((prev_insn
.insn_opcode
2312 & MIPS16OP_MASK_RZ
),
2314 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2315 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2316 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2317 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2318 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2319 && insn_uses_reg (ip
,
2320 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2323 /* If the branch writes a register that the previous
2324 instruction sets, we can not swap (we know that
2325 branches write only to RD or to $31). */
2326 || (! mips_opts
.mips16
2327 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2328 && (((pinfo
& INSN_WRITE_GPR_D
)
2329 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2330 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2331 || ((pinfo
& INSN_WRITE_GPR_31
)
2332 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2335 || (! mips_opts
.mips16
2336 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2337 && (((pinfo
& INSN_WRITE_GPR_D
)
2338 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2339 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2340 || ((pinfo
& INSN_WRITE_GPR_31
)
2341 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2344 || (mips_opts
.mips16
2345 && (pinfo
& MIPS16_INSN_WRITE_31
)
2346 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2347 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2348 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2350 /* If the branch writes a register that the previous
2351 instruction reads, we can not swap (we know that
2352 branches only write to RD or to $31). */
2353 || (! mips_opts
.mips16
2354 && (pinfo
& INSN_WRITE_GPR_D
)
2355 && insn_uses_reg (&prev_insn
,
2356 ((ip
->insn_opcode
>> OP_SH_RD
)
2359 || (! mips_opts
.mips16
2360 && (pinfo
& INSN_WRITE_GPR_31
)
2361 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2362 || (mips_opts
.mips16
2363 && (pinfo
& MIPS16_INSN_WRITE_31
)
2364 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2365 /* If we are generating embedded PIC code, the branch
2366 might be expanded into a sequence which uses $at, so
2367 we can't swap with an instruction which reads it. */
2368 || (mips_pic
== EMBEDDED_PIC
2369 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2370 /* If the previous previous instruction has a load
2371 delay, and sets a register that the branch reads, we
2373 || (! mips_opts
.mips16
2374 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2375 /* Itbl support may require additional care here. */
2376 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2377 || (! gpr_interlocks
2378 && (prev_prev_insn
.insn_mo
->pinfo
2379 & INSN_LOAD_MEMORY_DELAY
)))
2380 && insn_uses_reg (ip
,
2381 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2384 /* If one instruction sets a condition code and the
2385 other one uses a condition code, we can not swap. */
2386 || ((pinfo
& INSN_READ_COND_CODE
)
2387 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2388 || ((pinfo
& INSN_WRITE_COND_CODE
)
2389 && (prev_pinfo
& INSN_READ_COND_CODE
))
2390 /* If the previous instruction uses the PC, we can not
2392 || (mips_opts
.mips16
2393 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2394 /* If the previous instruction was extended, we can not
2396 || (mips_opts
.mips16
&& prev_insn_extended
)
2397 /* If the previous instruction had a fixup in mips16
2398 mode, we can not swap. This normally means that the
2399 previous instruction was a 4 byte branch anyhow. */
2400 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2401 /* If the previous instruction is a sync, sync.l, or
2402 sync.p, we can not swap. */
2403 || (prev_pinfo
& INSN_SYNC
))
2405 /* We could do even better for unconditional branches to
2406 portions of this object file; we could pick up the
2407 instruction at the destination, put it in the delay
2408 slot, and bump the destination address. */
2410 /* Update the previous insn information. */
2411 prev_prev_insn
= *ip
;
2412 prev_insn
.insn_mo
= &dummy_opcode
;
2416 /* It looks like we can actually do the swap. */
2417 if (! mips_opts
.mips16
)
2422 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2423 memcpy (temp
, prev_f
, 4);
2424 memcpy (prev_f
, f
, 4);
2425 memcpy (f
, temp
, 4);
2426 if (prev_insn_fixp
[0])
2428 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2429 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2431 if (prev_insn_fixp
[1])
2433 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2434 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2436 if (prev_insn_fixp
[2])
2438 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2439 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2443 fixp
[0]->fx_frag
= prev_insn_frag
;
2444 fixp
[0]->fx_where
= prev_insn_where
;
2448 fixp
[1]->fx_frag
= prev_insn_frag
;
2449 fixp
[1]->fx_where
= prev_insn_where
;
2453 fixp
[2]->fx_frag
= prev_insn_frag
;
2454 fixp
[2]->fx_where
= prev_insn_where
;
2462 assert (prev_insn_fixp
[0] == NULL
);
2463 assert (prev_insn_fixp
[1] == NULL
);
2464 assert (prev_insn_fixp
[2] == NULL
);
2465 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2466 memcpy (temp
, prev_f
, 2);
2467 memcpy (prev_f
, f
, 2);
2468 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2470 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2471 memcpy (f
, temp
, 2);
2475 memcpy (f
, f
+ 2, 2);
2476 memcpy (f
+ 2, temp
, 2);
2480 fixp
[0]->fx_frag
= prev_insn_frag
;
2481 fixp
[0]->fx_where
= prev_insn_where
;
2485 fixp
[1]->fx_frag
= prev_insn_frag
;
2486 fixp
[1]->fx_where
= prev_insn_where
;
2490 fixp
[2]->fx_frag
= prev_insn_frag
;
2491 fixp
[2]->fx_where
= prev_insn_where
;
2495 /* Update the previous insn information; leave prev_insn
2497 prev_prev_insn
= *ip
;
2499 prev_insn_is_delay_slot
= 1;
2501 /* If that was an unconditional branch, forget the previous
2502 insn information. */
2503 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2505 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2506 prev_insn
.insn_mo
= &dummy_opcode
;
2509 prev_insn_fixp
[0] = NULL
;
2510 prev_insn_fixp
[1] = NULL
;
2511 prev_insn_fixp
[2] = NULL
;
2512 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2513 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2514 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2515 prev_insn_extended
= 0;
2517 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2519 /* We don't yet optimize a branch likely. What we should do
2520 is look at the target, copy the instruction found there
2521 into the delay slot, and increment the branch to jump to
2522 the next instruction. */
2524 /* Update the previous insn information. */
2525 prev_prev_insn
= *ip
;
2526 prev_insn
.insn_mo
= &dummy_opcode
;
2527 prev_insn_fixp
[0] = NULL
;
2528 prev_insn_fixp
[1] = NULL
;
2529 prev_insn_fixp
[2] = NULL
;
2530 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2531 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2532 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2533 prev_insn_extended
= 0;
2537 /* Update the previous insn information. */
2539 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2541 prev_prev_insn
= prev_insn
;
2544 /* Any time we see a branch, we always fill the delay slot
2545 immediately; since this insn is not a branch, we know it
2546 is not in a delay slot. */
2547 prev_insn_is_delay_slot
= 0;
2549 prev_insn_fixp
[0] = fixp
[0];
2550 prev_insn_fixp
[1] = fixp
[1];
2551 prev_insn_fixp
[2] = fixp
[2];
2552 prev_insn_reloc_type
[0] = reloc_type
[0];
2553 prev_insn_reloc_type
[1] = reloc_type
[1];
2554 prev_insn_reloc_type
[2] = reloc_type
[2];
2555 if (mips_opts
.mips16
)
2556 prev_insn_extended
= (ip
->use_extend
2557 || *reloc_type
> BFD_RELOC_UNUSED
);
2560 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2561 prev_insn_unreordered
= 0;
2562 prev_insn_frag
= frag_now
;
2563 prev_insn_where
= f
- frag_now
->fr_literal
;
2564 prev_insn_valid
= 1;
2566 else if (place
== NULL
)
2568 /* We need to record a bit of information even when we are not
2569 reordering, in order to determine the base address for mips16
2570 PC relative relocs. */
2571 prev_prev_insn
= prev_insn
;
2573 prev_insn_reloc_type
[0] = reloc_type
[0];
2574 prev_insn_reloc_type
[1] = reloc_type
[1];
2575 prev_insn_reloc_type
[2] = reloc_type
[2];
2576 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2577 prev_insn_unreordered
= 1;
2580 /* We just output an insn, so the next one doesn't have a label. */
2581 mips_clear_insn_labels ();
2583 /* We must ensure that a fixup associated with an unmatched %hi
2584 reloc does not become a variant frag. Otherwise, the
2585 rearrangement of %hi relocs in frob_file may confuse
2589 frag_wane (frag_now
);
2594 /* This function forgets that there was any previous instruction or
2595 label. If PRESERVE is non-zero, it remembers enough information to
2596 know whether nops are needed before a noreorder section. */
2599 mips_no_prev_insn (preserve
)
2604 prev_insn
.insn_mo
= &dummy_opcode
;
2605 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2606 prev_nop_frag
= NULL
;
2607 prev_nop_frag_holds
= 0;
2608 prev_nop_frag_required
= 0;
2609 prev_nop_frag_since
= 0;
2611 prev_insn_valid
= 0;
2612 prev_insn_is_delay_slot
= 0;
2613 prev_insn_unreordered
= 0;
2614 prev_insn_extended
= 0;
2615 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2616 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2617 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2618 prev_prev_insn_unreordered
= 0;
2619 mips_clear_insn_labels ();
2622 /* This function must be called whenever we turn on noreorder or emit
2623 something other than instructions. It inserts any NOPS which might
2624 be needed by the previous instruction, and clears the information
2625 kept for the previous instructions. The INSNS parameter is true if
2626 instructions are to follow. */
2629 mips_emit_delays (insns
)
2632 if (! mips_opts
.noreorder
)
2637 if ((! mips_opts
.mips16
2638 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2639 && (! cop_interlocks
2640 && (prev_insn
.insn_mo
->pinfo
2641 & (INSN_LOAD_COPROC_DELAY
2642 | INSN_COPROC_MOVE_DELAY
2643 | INSN_WRITE_COND_CODE
))))
2644 || (! hilo_interlocks
2645 && (prev_insn
.insn_mo
->pinfo
2648 || (! mips_opts
.mips16
2650 && (prev_insn
.insn_mo
->pinfo
2651 & INSN_LOAD_MEMORY_DELAY
))
2652 || (! mips_opts
.mips16
2653 && mips_opts
.isa
== ISA_MIPS1
2654 && (prev_insn
.insn_mo
->pinfo
2655 & INSN_COPROC_MEMORY_DELAY
)))
2657 /* Itbl support may require additional care here. */
2659 if ((! mips_opts
.mips16
2660 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2661 && (! cop_interlocks
2662 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2663 || (! hilo_interlocks
2664 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2665 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2668 if (prev_insn_unreordered
)
2671 else if ((! mips_opts
.mips16
2672 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2673 && (! cop_interlocks
2674 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2675 || (! hilo_interlocks
2676 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2677 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2679 /* Itbl support may require additional care here. */
2680 if (! prev_prev_insn_unreordered
)
2686 struct insn_label_list
*l
;
2690 /* Record the frag which holds the nop instructions, so
2691 that we can remove them if we don't need them. */
2692 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2693 prev_nop_frag
= frag_now
;
2694 prev_nop_frag_holds
= nops
;
2695 prev_nop_frag_required
= 0;
2696 prev_nop_frag_since
= 0;
2699 for (; nops
> 0; --nops
)
2704 /* Move on to a new frag, so that it is safe to simply
2705 decrease the size of prev_nop_frag. */
2706 frag_wane (frag_now
);
2710 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2714 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2715 symbol_set_frag (l
->label
, frag_now
);
2716 val
= (valueT
) frag_now_fix ();
2717 /* mips16 text labels are stored as odd. */
2718 if (mips_opts
.mips16
)
2720 S_SET_VALUE (l
->label
, val
);
2725 /* Mark instruction labels in mips16 mode. */
2726 if (mips_opts
.mips16
&& insns
)
2727 mips16_mark_labels ();
2729 mips_no_prev_insn (insns
);
2732 /* Build an instruction created by a macro expansion. This is passed
2733 a pointer to the count of instructions created so far, an
2734 expression, the name of the instruction to build, an operand format
2735 string, and corresponding arguments. */
2739 macro_build (char *place
,
2747 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2756 struct mips_cl_insn insn
;
2757 bfd_reloc_code_real_type r
[3];
2761 va_start (args
, fmt
);
2767 * If the macro is about to expand into a second instruction,
2768 * print a warning if needed. We need to pass ip as a parameter
2769 * to generate a better warning message here...
2771 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2772 as_warn (_("Macro instruction expanded into multiple instructions"));
2775 *counter
+= 1; /* bump instruction counter */
2777 if (mips_opts
.mips16
)
2779 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2784 r
[0] = BFD_RELOC_UNUSED
;
2785 r
[1] = BFD_RELOC_UNUSED
;
2786 r
[2] = BFD_RELOC_UNUSED
;
2787 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2788 assert (insn
.insn_mo
);
2789 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2791 /* Search until we get a match for NAME. */
2794 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2795 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2796 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2797 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2801 assert (insn
.insn_mo
->name
);
2802 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2805 insn
.insn_opcode
= insn
.insn_mo
->match
;
2821 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2825 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2830 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2835 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2840 int tmp
= va_arg (args
, int);
2842 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2843 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2849 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2856 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2860 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2864 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2868 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2872 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2879 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2885 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2886 assert (*r
== BFD_RELOC_MIPS_GPREL
2887 || *r
== BFD_RELOC_MIPS_LITERAL
2888 || *r
== BFD_RELOC_MIPS_HIGHER
2889 || *r
== BFD_RELOC_HI16_S
2890 || *r
== BFD_RELOC_LO16
2891 || *r
== BFD_RELOC_MIPS_GOT16
2892 || *r
== BFD_RELOC_MIPS_CALL16
2893 || *r
== BFD_RELOC_MIPS_GOT_LO16
2894 || *r
== BFD_RELOC_MIPS_CALL_LO16
2895 || (ep
->X_op
== O_subtract
2896 && *r
== BFD_RELOC_PCREL_LO16
));
2900 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2902 && (ep
->X_op
== O_constant
2903 || (ep
->X_op
== O_symbol
2904 && (*r
== BFD_RELOC_MIPS_HIGHEST
2905 || *r
== BFD_RELOC_HI16_S
2906 || *r
== BFD_RELOC_HI16
2907 || *r
== BFD_RELOC_GPREL16
2908 || *r
== BFD_RELOC_MIPS_GOT_HI16
2909 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2910 || (ep
->X_op
== O_subtract
2911 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2915 assert (ep
!= NULL
);
2917 * This allows macro() to pass an immediate expression for
2918 * creating short branches without creating a symbol.
2919 * Note that the expression still might come from the assembly
2920 * input, in which case the value is not checked for range nor
2921 * is a relocation entry generated (yuck).
2923 if (ep
->X_op
== O_constant
)
2925 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2929 if (mips_pic
== EMBEDDED_PIC
)
2930 *r
= BFD_RELOC_16_PCREL_S2
;
2932 *r
= BFD_RELOC_16_PCREL
;
2936 assert (ep
!= NULL
);
2937 *r
= BFD_RELOC_MIPS_JMP
;
2941 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2950 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2952 append_insn (place
, &insn
, ep
, r
, false);
2956 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2958 int *counter ATTRIBUTE_UNUSED
;
2964 struct mips_cl_insn insn
;
2965 bfd_reloc_code_real_type r
[3]
2966 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2968 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2969 assert (insn
.insn_mo
);
2970 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2972 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2973 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2976 assert (insn
.insn_mo
->name
);
2977 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2980 insn
.insn_opcode
= insn
.insn_mo
->match
;
2981 insn
.use_extend
= false;
3000 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3005 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3009 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3013 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3023 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3030 regno
= va_arg (args
, int);
3031 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3032 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3053 assert (ep
!= NULL
);
3055 if (ep
->X_op
!= O_constant
)
3056 *r
= BFD_RELOC_UNUSED
+ c
;
3059 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
3060 false, false, &insn
.insn_opcode
,
3061 &insn
.use_extend
, &insn
.extend
);
3063 *r
= BFD_RELOC_UNUSED
;
3069 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3076 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3078 append_insn (place
, &insn
, ep
, r
, false);
3082 * Generate a "lui" instruction.
3085 macro_build_lui (place
, counter
, ep
, regnum
)
3091 expressionS high_expr
;
3092 struct mips_cl_insn insn
;
3093 bfd_reloc_code_real_type r
[3]
3094 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3095 CONST
char *name
= "lui";
3096 CONST
char *fmt
= "t,u";
3098 assert (! mips_opts
.mips16
);
3104 high_expr
.X_op
= O_constant
;
3105 high_expr
.X_add_number
= ep
->X_add_number
;
3108 if (high_expr
.X_op
== O_constant
)
3110 /* we can compute the instruction now without a relocation entry */
3111 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3113 *r
= BFD_RELOC_UNUSED
;
3115 else if (! HAVE_NEWABI
)
3117 assert (ep
->X_op
== O_symbol
);
3118 /* _gp_disp is a special case, used from s_cpload. */
3119 assert (mips_pic
== NO_PIC
3120 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3121 *r
= BFD_RELOC_HI16_S
;
3125 * If the macro is about to expand into a second instruction,
3126 * print a warning if needed. We need to pass ip as a parameter
3127 * to generate a better warning message here...
3129 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3130 as_warn (_("Macro instruction expanded into multiple instructions"));
3133 *counter
+= 1; /* bump instruction counter */
3135 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3136 assert (insn
.insn_mo
);
3137 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3138 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3140 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3141 if (*r
== BFD_RELOC_UNUSED
)
3143 insn
.insn_opcode
|= high_expr
.X_add_number
;
3144 append_insn (place
, &insn
, NULL
, r
, false);
3147 append_insn (place
, &insn
, &high_expr
, r
, false);
3151 * Generates code to set the $at register to true (one)
3152 * if reg is less than the immediate expression.
3155 set_at (counter
, reg
, unsignedp
)
3160 if (imm_expr
.X_op
== O_constant
3161 && imm_expr
.X_add_number
>= -0x8000
3162 && imm_expr
.X_add_number
< 0x8000)
3163 macro_build ((char *) NULL
, counter
, &imm_expr
,
3164 unsignedp
? "sltiu" : "slti",
3165 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3168 load_register (counter
, AT
, &imm_expr
, 0);
3169 macro_build ((char *) NULL
, counter
, NULL
,
3170 unsignedp
? "sltu" : "slt",
3171 "d,v,t", AT
, reg
, AT
);
3175 /* Warn if an expression is not a constant. */
3178 check_absolute_expr (ip
, ex
)
3179 struct mips_cl_insn
*ip
;
3182 if (ex
->X_op
== O_big
)
3183 as_bad (_("unsupported large constant"));
3184 else if (ex
->X_op
!= O_constant
)
3185 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3188 /* Count the leading zeroes by performing a binary chop. This is a
3189 bulky bit of source, but performance is a LOT better for the
3190 majority of values than a simple loop to count the bits:
3191 for (lcnt = 0; (lcnt < 32); lcnt++)
3192 if ((v) & (1 << (31 - lcnt)))
3194 However it is not code size friendly, and the gain will drop a bit
3195 on certain cached systems.
3197 #define COUNT_TOP_ZEROES(v) \
3198 (((v) & ~0xffff) == 0 \
3199 ? ((v) & ~0xff) == 0 \
3200 ? ((v) & ~0xf) == 0 \
3201 ? ((v) & ~0x3) == 0 \
3202 ? ((v) & ~0x1) == 0 \
3207 : ((v) & ~0x7) == 0 \
3210 : ((v) & ~0x3f) == 0 \
3211 ? ((v) & ~0x1f) == 0 \
3214 : ((v) & ~0x7f) == 0 \
3217 : ((v) & ~0xfff) == 0 \
3218 ? ((v) & ~0x3ff) == 0 \
3219 ? ((v) & ~0x1ff) == 0 \
3222 : ((v) & ~0x7ff) == 0 \
3225 : ((v) & ~0x3fff) == 0 \
3226 ? ((v) & ~0x1fff) == 0 \
3229 : ((v) & ~0x7fff) == 0 \
3232 : ((v) & ~0xffffff) == 0 \
3233 ? ((v) & ~0xfffff) == 0 \
3234 ? ((v) & ~0x3ffff) == 0 \
3235 ? ((v) & ~0x1ffff) == 0 \
3238 : ((v) & ~0x7ffff) == 0 \
3241 : ((v) & ~0x3fffff) == 0 \
3242 ? ((v) & ~0x1fffff) == 0 \
3245 : ((v) & ~0x7fffff) == 0 \
3248 : ((v) & ~0xfffffff) == 0 \
3249 ? ((v) & ~0x3ffffff) == 0 \
3250 ? ((v) & ~0x1ffffff) == 0 \
3253 : ((v) & ~0x7ffffff) == 0 \
3256 : ((v) & ~0x3fffffff) == 0 \
3257 ? ((v) & ~0x1fffffff) == 0 \
3260 : ((v) & ~0x7fffffff) == 0 \
3265 * This routine generates the least number of instructions neccessary to load
3266 * an absolute expression value into a register.
3269 load_register (counter
, reg
, ep
, dbl
)
3276 expressionS hi32
, lo32
;
3278 if (ep
->X_op
!= O_big
)
3280 assert (ep
->X_op
== O_constant
);
3281 if (ep
->X_add_number
< 0x8000
3282 && (ep
->X_add_number
>= 0
3283 || (ep
->X_add_number
>= -0x8000
3286 || sizeof (ep
->X_add_number
) > 4))))
3288 /* We can handle 16 bit signed values with an addiu to
3289 $zero. No need to ever use daddiu here, since $zero and
3290 the result are always correct in 32 bit mode. */
3291 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3292 (int) BFD_RELOC_LO16
);
3295 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3297 /* We can handle 16 bit unsigned values with an ori to
3299 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3300 (int) BFD_RELOC_LO16
);
3303 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3304 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3305 == ~ (offsetT
) 0x7fffffff))
3308 || sizeof (ep
->X_add_number
) > 4
3309 || (ep
->X_add_number
& 0x80000000) == 0))
3310 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3311 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3314 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3315 == ~ (offsetT
) 0xffffffff)))
3317 /* 32 bit values require an lui. */
3318 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3319 (int) BFD_RELOC_HI16
);
3320 if ((ep
->X_add_number
& 0xffff) != 0)
3321 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3322 (int) BFD_RELOC_LO16
);
3327 /* The value is larger than 32 bits. */
3329 if (HAVE_32BIT_GPRS
)
3331 as_bad (_("Number larger than 32 bits"));
3332 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3333 (int) BFD_RELOC_LO16
);
3337 if (ep
->X_op
!= O_big
)
3340 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3341 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3342 hi32
.X_add_number
&= 0xffffffff;
3344 lo32
.X_add_number
&= 0xffffffff;
3348 assert (ep
->X_add_number
> 2);
3349 if (ep
->X_add_number
== 3)
3350 generic_bignum
[3] = 0;
3351 else if (ep
->X_add_number
> 4)
3352 as_bad (_("Number larger than 64 bits"));
3353 lo32
.X_op
= O_constant
;
3354 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3355 hi32
.X_op
= O_constant
;
3356 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3359 if (hi32
.X_add_number
== 0)
3364 unsigned long hi
, lo
;
3366 if (hi32
.X_add_number
== 0xffffffff)
3368 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3370 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3371 reg
, 0, (int) BFD_RELOC_LO16
);
3374 if (lo32
.X_add_number
& 0x80000000)
3376 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3377 (int) BFD_RELOC_HI16
);
3378 if (lo32
.X_add_number
& 0xffff)
3379 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3380 reg
, reg
, (int) BFD_RELOC_LO16
);
3385 /* Check for 16bit shifted constant. We know that hi32 is
3386 non-zero, so start the mask on the first bit of the hi32
3391 unsigned long himask
, lomask
;
3395 himask
= 0xffff >> (32 - shift
);
3396 lomask
= (0xffff << shift
) & 0xffffffff;
3400 himask
= 0xffff << (shift
- 32);
3403 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3404 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3408 tmp
.X_op
= O_constant
;
3410 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3411 | (lo32
.X_add_number
>> shift
));
3413 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3414 macro_build ((char *) NULL
, counter
, &tmp
,
3415 "ori", "t,r,i", reg
, 0,
3416 (int) BFD_RELOC_LO16
);
3417 macro_build ((char *) NULL
, counter
, NULL
,
3418 (shift
>= 32) ? "dsll32" : "dsll",
3420 (shift
>= 32) ? shift
- 32 : shift
);
3425 while (shift
<= (64 - 16));
3427 /* Find the bit number of the lowest one bit, and store the
3428 shifted value in hi/lo. */
3429 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3430 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3434 while ((lo
& 1) == 0)
3439 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3445 while ((hi
& 1) == 0)
3454 /* Optimize if the shifted value is a (power of 2) - 1. */
3455 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3456 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3458 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3463 /* This instruction will set the register to be all
3465 tmp
.X_op
= O_constant
;
3466 tmp
.X_add_number
= (offsetT
) -1;
3467 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3468 reg
, 0, (int) BFD_RELOC_LO16
);
3472 macro_build ((char *) NULL
, counter
, NULL
,
3473 (bit
>= 32) ? "dsll32" : "dsll",
3475 (bit
>= 32) ? bit
- 32 : bit
);
3477 macro_build ((char *) NULL
, counter
, NULL
,
3478 (shift
>= 32) ? "dsrl32" : "dsrl",
3480 (shift
>= 32) ? shift
- 32 : shift
);
3485 /* Sign extend hi32 before calling load_register, because we can
3486 generally get better code when we load a sign extended value. */
3487 if ((hi32
.X_add_number
& 0x80000000) != 0)
3488 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3489 load_register (counter
, reg
, &hi32
, 0);
3492 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3496 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3505 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3507 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3508 (int) BFD_RELOC_HI16
);
3509 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3516 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3521 mid16
.X_add_number
>>= 16;
3522 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3523 freg
, (int) BFD_RELOC_LO16
);
3524 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3528 if ((lo32
.X_add_number
& 0xffff) != 0)
3529 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3530 (int) BFD_RELOC_LO16
);
3533 /* Load an address into a register. */
3536 load_address (counter
, reg
, ep
, dbl
, used_at
)
3545 if (ep
->X_op
!= O_constant
3546 && ep
->X_op
!= O_symbol
)
3548 as_bad (_("expression too complex"));
3549 ep
->X_op
= O_constant
;
3552 if (ep
->X_op
== O_constant
)
3554 load_register (counter
, reg
, ep
, dbl
);
3558 if (mips_pic
== NO_PIC
)
3560 /* If this is a reference to a GP relative symbol, we want
3561 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3563 lui $reg,<sym> (BFD_RELOC_HI16_S)
3564 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3565 If we have an addend, we always use the latter form.
3567 With 64bit address space and a usable $at we want
3568 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3569 lui $at,<sym> (BFD_RELOC_HI16_S)
3570 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3571 daddiu $at,<sym> (BFD_RELOC_LO16)
3575 If $at is already in use, we use an path which is suboptimal
3576 on superscalar processors.
3577 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3578 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3580 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3582 daddiu $reg,<sym> (BFD_RELOC_LO16)
3584 if (HAVE_64BIT_ADDRESSES
)
3588 /* We don't do GP optimization for now because RELAX_ENCODE can't
3589 hold the data for such large chunks. */
3593 macro_build (p
, counter
, ep
, "lui", "t,u",
3594 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3595 macro_build (p
, counter
, ep
, "lui", "t,u",
3596 AT
, (int) BFD_RELOC_HI16_S
);
3597 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3598 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3599 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3600 AT
, AT
, (int) BFD_RELOC_LO16
);
3601 macro_build (p
, counter
, NULL
, "dsll32", "d,w,<",
3603 macro_build (p
, counter
, NULL
, "dadd", "d,v,t",
3609 macro_build (p
, counter
, ep
, "lui", "t,u",
3610 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3611 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3612 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3613 macro_build (p
, counter
, NULL
, "dsll", "d,w,<",
3615 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3616 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3617 macro_build (p
, counter
, NULL
, "dsll", "d,w,<",
3619 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3620 reg
, reg
, (int) BFD_RELOC_LO16
);
3626 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3627 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3630 macro_build ((char *) NULL
, counter
, ep
,
3631 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3632 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3633 p
= frag_var (rs_machine_dependent
, 8, 0,
3634 RELAX_ENCODE (4, 8, 0, 4, 0,
3635 mips_opts
.warn_about_macros
),
3636 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3638 macro_build_lui (p
, counter
, ep
, reg
);
3641 macro_build (p
, counter
, ep
,
3642 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3643 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3646 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3650 /* If this is a reference to an external symbol, we want
3651 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3653 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3655 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3656 If there is a constant, it must be added in after. */
3657 ex
.X_add_number
= ep
->X_add_number
;
3658 ep
->X_add_number
= 0;
3660 macro_build ((char *) NULL
, counter
, ep
,
3661 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3662 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3663 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3664 p
= frag_var (rs_machine_dependent
, 4, 0,
3665 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3666 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3667 macro_build (p
, counter
, ep
,
3668 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3669 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3670 if (ex
.X_add_number
!= 0)
3672 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3673 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3674 ex
.X_op
= O_constant
;
3675 macro_build ((char *) NULL
, counter
, &ex
,
3676 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3677 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3680 else if (mips_pic
== SVR4_PIC
)
3685 /* This is the large GOT case. If this is a reference to an
3686 external symbol, we want
3687 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3689 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3690 Otherwise, for a reference to a local symbol, we want
3691 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3693 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3694 If there is a constant, it must be added in after. */
3695 ex
.X_add_number
= ep
->X_add_number
;
3696 ep
->X_add_number
= 0;
3697 if (reg_needs_delay (GP
))
3702 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3703 (int) BFD_RELOC_MIPS_GOT_HI16
);
3704 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3705 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3706 "d,v,t", reg
, reg
, GP
);
3707 macro_build ((char *) NULL
, counter
, ep
,
3708 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3709 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3710 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3711 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3712 mips_opts
.warn_about_macros
),
3713 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3716 /* We need a nop before loading from $gp. This special
3717 check is required because the lui which starts the main
3718 instruction stream does not refer to $gp, and so will not
3719 insert the nop which may be required. */
3720 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3723 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3724 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3726 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3728 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3729 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3730 if (ex
.X_add_number
!= 0)
3732 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3733 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3734 ex
.X_op
= O_constant
;
3735 macro_build ((char *) NULL
, counter
, &ex
,
3736 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3737 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3740 else if (mips_pic
== EMBEDDED_PIC
)
3743 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3745 macro_build ((char *) NULL
, counter
, ep
,
3746 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3747 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3753 /* Move the contents of register SOURCE into register DEST. */
3756 move_register (counter
, dest
, source
)
3761 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3762 HAVE_32BIT_GPRS
? "addu" : "daddu",
3763 "d,v,t", dest
, source
, 0);
3768 * This routine implements the seemingly endless macro or synthesized
3769 * instructions and addressing modes in the mips assembly language. Many
3770 * of these macros are simple and are similar to each other. These could
3771 * probably be handled by some kind of table or grammer aproach instead of
3772 * this verbose method. Others are not simple macros but are more like
3773 * optimizing code generation.
3774 * One interesting optimization is when several store macros appear
3775 * consecutivly that would load AT with the upper half of the same address.
3776 * The ensuing load upper instructions are ommited. This implies some kind
3777 * of global optimization. We currently only optimize within a single macro.
3778 * For many of the load and store macros if the address is specified as a
3779 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3780 * first load register 'at' with zero and use it as the base register. The
3781 * mips assembler simply uses register $zero. Just one tiny optimization
3786 struct mips_cl_insn
*ip
;
3788 register int treg
, sreg
, dreg
, breg
;
3804 bfd_reloc_code_real_type r
;
3806 int hold_mips_optimize
;
3808 assert (! mips_opts
.mips16
);
3810 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3811 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3812 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3813 mask
= ip
->insn_mo
->mask
;
3815 expr1
.X_op
= O_constant
;
3816 expr1
.X_op_symbol
= NULL
;
3817 expr1
.X_add_symbol
= NULL
;
3818 expr1
.X_add_number
= 1;
3830 mips_emit_delays (true);
3831 ++mips_opts
.noreorder
;
3832 mips_any_noreorder
= 1;
3834 expr1
.X_add_number
= 8;
3835 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3839 move_register (&icnt
, dreg
, sreg
);
3840 macro_build ((char *) NULL
, &icnt
, NULL
,
3841 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3843 --mips_opts
.noreorder
;
3864 if (imm_expr
.X_op
== O_constant
3865 && imm_expr
.X_add_number
>= -0x8000
3866 && imm_expr
.X_add_number
< 0x8000)
3868 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3869 (int) BFD_RELOC_LO16
);
3872 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3873 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3892 if (imm_expr
.X_op
== O_constant
3893 && imm_expr
.X_add_number
>= 0
3894 && imm_expr
.X_add_number
< 0x10000)
3896 if (mask
!= M_NOR_I
)
3897 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3898 sreg
, (int) BFD_RELOC_LO16
);
3901 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3902 treg
, sreg
, (int) BFD_RELOC_LO16
);
3903 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3909 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3910 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3927 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3933 load_register (&icnt
, AT
, &imm_expr
, 0);
3934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3942 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3943 likely
? "bgezl" : "bgez",
3949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3950 likely
? "blezl" : "blez",
3954 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3956 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3962 /* check for > max integer */
3963 maxnum
= 0x7fffffff;
3964 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3971 if (imm_expr
.X_op
== O_constant
3972 && imm_expr
.X_add_number
>= maxnum
3973 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3976 /* result is always false */
3980 as_warn (_("Branch %s is always false (nop)"),
3982 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3987 as_warn (_("Branch likely %s is always false"),
3989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3994 if (imm_expr
.X_op
!= O_constant
)
3995 as_bad (_("Unsupported large constant"));
3996 imm_expr
.X_add_number
++;
4000 if (mask
== M_BGEL_I
)
4002 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4005 likely
? "bgezl" : "bgez", "s,p", sreg
);
4008 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4010 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4011 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4014 maxnum
= 0x7fffffff;
4015 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4022 maxnum
= - maxnum
- 1;
4023 if (imm_expr
.X_op
== O_constant
4024 && imm_expr
.X_add_number
<= maxnum
4025 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4028 /* result is always true */
4029 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4033 set_at (&icnt
, sreg
, 0);
4034 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4035 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4045 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4046 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4051 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4052 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4060 && imm_expr
.X_op
== O_constant
4061 && imm_expr
.X_add_number
== 0xffffffff))
4063 if (imm_expr
.X_op
!= O_constant
)
4064 as_bad (_("Unsupported large constant"));
4065 imm_expr
.X_add_number
++;
4069 if (mask
== M_BGEUL_I
)
4071 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4073 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4076 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4079 set_at (&icnt
, sreg
, 1);
4080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4081 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4090 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4095 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4096 likely
? "bltzl" : "bltz", "s,p", treg
);
4099 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4101 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4109 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4110 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4115 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4118 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4126 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4127 likely
? "blezl" : "blez", "s,p", sreg
);
4132 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4133 likely
? "bgezl" : "bgez", "s,p", treg
);
4136 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4137 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4138 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4144 maxnum
= 0x7fffffff;
4145 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4152 if (imm_expr
.X_op
== O_constant
4153 && imm_expr
.X_add_number
>= maxnum
4154 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4156 if (imm_expr
.X_op
!= O_constant
)
4157 as_bad (_("Unsupported large constant"));
4158 imm_expr
.X_add_number
++;
4162 if (mask
== M_BLTL_I
)
4164 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4166 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4167 likely
? "bltzl" : "bltz", "s,p", sreg
);
4170 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 likely
? "blezl" : "blez", "s,p", sreg
);
4176 set_at (&icnt
, sreg
, 0);
4177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4178 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4186 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4187 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4192 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4194 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4195 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4203 && imm_expr
.X_op
== O_constant
4204 && imm_expr
.X_add_number
== 0xffffffff))
4206 if (imm_expr
.X_op
!= O_constant
)
4207 as_bad (_("Unsupported large constant"));
4208 imm_expr
.X_add_number
++;
4212 if (mask
== M_BLTUL_I
)
4214 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4216 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4218 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4219 likely
? "beql" : "beq",
4223 set_at (&icnt
, sreg
, 1);
4224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4225 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4234 likely
? "bltzl" : "bltz", "s,p", sreg
);
4239 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4240 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4243 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4245 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4256 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4259 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4262 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4277 as_warn (_("Divide by zero."));
4279 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4281 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4285 mips_emit_delays (true);
4286 ++mips_opts
.noreorder
;
4287 mips_any_noreorder
= 1;
4290 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4291 macro_build ((char *) NULL
, &icnt
, NULL
,
4292 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4296 expr1
.X_add_number
= 8;
4297 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4298 macro_build ((char *) NULL
, &icnt
, NULL
,
4299 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4300 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4302 expr1
.X_add_number
= -1;
4303 macro_build ((char *) NULL
, &icnt
, &expr1
,
4304 dbl
? "daddiu" : "addiu",
4305 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4306 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4307 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4310 expr1
.X_add_number
= 1;
4311 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4312 (int) BFD_RELOC_LO16
);
4313 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4318 expr1
.X_add_number
= 0x80000000;
4319 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4320 (int) BFD_RELOC_HI16
);
4324 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4325 /* We want to close the noreorder block as soon as possible, so
4326 that later insns are available for delay slot filling. */
4327 --mips_opts
.noreorder
;
4331 expr1
.X_add_number
= 8;
4332 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4333 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4335 /* We want to close the noreorder block as soon as possible, so
4336 that later insns are available for delay slot filling. */
4337 --mips_opts
.noreorder
;
4339 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4341 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4380 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4382 as_warn (_("Divide by zero."));
4384 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4386 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4389 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4391 if (strcmp (s2
, "mflo") == 0)
4392 move_register (&icnt
, dreg
, sreg
);
4394 move_register (&icnt
, dreg
, 0);
4397 if (imm_expr
.X_op
== O_constant
4398 && imm_expr
.X_add_number
== -1
4399 && s
[strlen (s
) - 1] != 'u')
4401 if (strcmp (s2
, "mflo") == 0)
4403 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4407 move_register (&icnt
, dreg
, 0);
4411 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4412 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4413 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4432 mips_emit_delays (true);
4433 ++mips_opts
.noreorder
;
4434 mips_any_noreorder
= 1;
4437 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4438 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4439 /* We want to close the noreorder block as soon as possible, so
4440 that later insns are available for delay slot filling. */
4441 --mips_opts
.noreorder
;
4445 expr1
.X_add_number
= 8;
4446 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4447 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4449 /* We want to close the noreorder block as soon as possible, so
4450 that later insns are available for delay slot filling. */
4451 --mips_opts
.noreorder
;
4452 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4454 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4460 /* Load the address of a symbol into a register. If breg is not
4461 zero, we then add a base register to it. */
4474 /* When generating embedded PIC code, we permit expressions of
4477 la $treg,foo-bar($breg)
4478 where bar is an address in the current section. These are used
4479 when getting the addresses of functions. We don't permit
4480 X_add_number to be non-zero, because if the symbol is
4481 external the relaxing code needs to know that any addend is
4482 purely the offset to X_op_symbol. */
4483 if (mips_pic
== EMBEDDED_PIC
4484 && offset_expr
.X_op
== O_subtract
4485 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4486 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4487 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4489 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4492 && (offset_expr
.X_add_number
== 0
4493 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4499 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4500 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4504 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4505 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4507 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4508 "d,v,t", tempreg
, tempreg
, breg
);
4510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4511 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4512 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4518 if (offset_expr
.X_op
!= O_symbol
4519 && offset_expr
.X_op
!= O_constant
)
4521 as_bad (_("expression too complex"));
4522 offset_expr
.X_op
= O_constant
;
4525 if (offset_expr
.X_op
== O_constant
)
4526 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4527 else if (mips_pic
== NO_PIC
)
4529 /* If this is a reference to a GP relative symbol, we want
4530 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4532 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4533 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4534 If we have a constant, we need two instructions anyhow,
4535 so we may as well always use the latter form.
4537 With 64bit address space and a usable $at we want
4538 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4539 lui $at,<sym> (BFD_RELOC_HI16_S)
4540 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4541 daddiu $at,<sym> (BFD_RELOC_LO16)
4543 dadd $tempreg,$tempreg,$at
4545 If $at is already in use, we use an path which is suboptimal
4546 on superscalar processors.
4547 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4548 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4550 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4552 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4555 if (HAVE_64BIT_ADDRESSES
)
4557 /* We don't do GP optimization for now because RELAX_ENCODE can't
4558 hold the data for such large chunks. */
4562 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4563 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4564 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4565 AT
, (int) BFD_RELOC_HI16_S
);
4566 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4567 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4568 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4569 AT
, AT
, (int) BFD_RELOC_LO16
);
4570 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
4571 tempreg
, tempreg
, 0);
4572 macro_build (p
, &icnt
, NULL
, "dadd", "d,v,t",
4573 tempreg
, tempreg
, AT
);
4578 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4579 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4580 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4581 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4582 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4583 tempreg
, tempreg
, 16);
4584 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4585 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4586 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4587 tempreg
, tempreg
, 16);
4588 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4589 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4594 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4595 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4598 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4599 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4600 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4601 p
= frag_var (rs_machine_dependent
, 8, 0,
4602 RELAX_ENCODE (4, 8, 0, 4, 0,
4603 mips_opts
.warn_about_macros
),
4604 offset_expr
.X_add_symbol
, (offsetT
) 0,
4607 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4610 macro_build (p
, &icnt
, &offset_expr
,
4611 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4612 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4615 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4617 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4619 /* If this is a reference to an external symbol, and there
4620 is no constant, we want
4621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4622 or if tempreg is PIC_CALL_REG
4623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4624 For a local symbol, we want
4625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4627 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4629 If we have a small constant, and this is a reference to
4630 an external symbol, we want
4631 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4633 addiu $tempreg,$tempreg,<constant>
4634 For a local symbol, we want the same instruction
4635 sequence, but we output a BFD_RELOC_LO16 reloc on the
4638 If we have a large constant, and this is a reference to
4639 an external symbol, we want
4640 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4641 lui $at,<hiconstant>
4642 addiu $at,$at,<loconstant>
4643 addu $tempreg,$tempreg,$at
4644 For a local symbol, we want the same instruction
4645 sequence, but we output a BFD_RELOC_LO16 reloc on the
4646 addiu instruction. */
4647 expr1
.X_add_number
= offset_expr
.X_add_number
;
4648 offset_expr
.X_add_number
= 0;
4650 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4651 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4654 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4655 if (expr1
.X_add_number
== 0)
4663 /* We're going to put in an addu instruction using
4664 tempreg, so we may as well insert the nop right
4666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4670 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4671 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4673 ? mips_opts
.warn_about_macros
4675 offset_expr
.X_add_symbol
, (offsetT
) 0,
4679 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4682 macro_build (p
, &icnt
, &expr1
,
4683 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4684 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4685 /* FIXME: If breg == 0, and the next instruction uses
4686 $tempreg, then if this variant case is used an extra
4687 nop will be generated. */
4689 else if (expr1
.X_add_number
>= -0x8000
4690 && expr1
.X_add_number
< 0x8000)
4692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4694 macro_build ((char *) NULL
, &icnt
, &expr1
,
4695 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4696 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4697 (void) frag_var (rs_machine_dependent
, 0, 0,
4698 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4699 offset_expr
.X_add_symbol
, (offsetT
) 0,
4706 /* If we are going to add in a base register, and the
4707 target register and the base register are the same,
4708 then we are using AT as a temporary register. Since
4709 we want to load the constant into AT, we add our
4710 current AT (from the global offset table) and the
4711 register into the register now, and pretend we were
4712 not using a base register. */
4717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4719 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4720 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4721 "d,v,t", treg
, AT
, breg
);
4727 /* Set mips_optimize around the lui instruction to avoid
4728 inserting an unnecessary nop after the lw. */
4729 hold_mips_optimize
= mips_optimize
;
4731 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4732 mips_optimize
= hold_mips_optimize
;
4734 macro_build ((char *) NULL
, &icnt
, &expr1
,
4735 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4736 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4738 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4739 "d,v,t", tempreg
, tempreg
, AT
);
4740 (void) frag_var (rs_machine_dependent
, 0, 0,
4741 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4742 offset_expr
.X_add_symbol
, (offsetT
) 0,
4747 else if (mips_pic
== SVR4_PIC
)
4750 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4751 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4753 /* This is the large GOT case. If this is a reference to an
4754 external symbol, and there is no constant, we want
4755 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4756 addu $tempreg,$tempreg,$gp
4757 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4758 or if tempreg is PIC_CALL_REG
4759 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4760 addu $tempreg,$tempreg,$gp
4761 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4762 For a local symbol, we want
4763 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4765 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4767 If we have a small constant, and this is a reference to
4768 an external symbol, we want
4769 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4770 addu $tempreg,$tempreg,$gp
4771 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4773 addiu $tempreg,$tempreg,<constant>
4774 For a local symbol, we want
4775 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4777 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4779 If we have a large constant, and this is a reference to
4780 an external symbol, we want
4781 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4782 addu $tempreg,$tempreg,$gp
4783 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4784 lui $at,<hiconstant>
4785 addiu $at,$at,<loconstant>
4786 addu $tempreg,$tempreg,$at
4787 For a local symbol, we want
4788 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4789 lui $at,<hiconstant>
4790 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4791 addu $tempreg,$tempreg,$at
4793 expr1
.X_add_number
= offset_expr
.X_add_number
;
4794 offset_expr
.X_add_number
= 0;
4796 if (reg_needs_delay (GP
))
4800 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4802 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4803 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4806 tempreg
, lui_reloc_type
);
4807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4808 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4809 "d,v,t", tempreg
, tempreg
, GP
);
4810 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4812 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4813 if (expr1
.X_add_number
== 0)
4821 /* We're going to put in an addu instruction using
4822 tempreg, so we may as well insert the nop right
4824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4829 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4830 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4833 ? mips_opts
.warn_about_macros
4835 offset_expr
.X_add_symbol
, (offsetT
) 0,
4838 else if (expr1
.X_add_number
>= -0x8000
4839 && expr1
.X_add_number
< 0x8000)
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4843 macro_build ((char *) NULL
, &icnt
, &expr1
,
4844 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4845 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4847 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4848 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4850 ? mips_opts
.warn_about_macros
4852 offset_expr
.X_add_symbol
, (offsetT
) 0,
4859 /* If we are going to add in a base register, and the
4860 target register and the base register are the same,
4861 then we are using AT as a temporary register. Since
4862 we want to load the constant into AT, we add our
4863 current AT (from the global offset table) and the
4864 register into the register now, and pretend we were
4865 not using a base register. */
4873 assert (tempreg
== AT
);
4874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4877 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4878 "d,v,t", treg
, AT
, breg
);
4883 /* Set mips_optimize around the lui instruction to avoid
4884 inserting an unnecessary nop after the lw. */
4885 hold_mips_optimize
= mips_optimize
;
4887 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4888 mips_optimize
= hold_mips_optimize
;
4890 macro_build ((char *) NULL
, &icnt
, &expr1
,
4891 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4892 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4893 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4894 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4895 "d,v,t", dreg
, dreg
, AT
);
4897 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4898 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4901 ? mips_opts
.warn_about_macros
4903 offset_expr
.X_add_symbol
, (offsetT
) 0,
4911 /* This is needed because this instruction uses $gp, but
4912 the first instruction on the main stream does not. */
4913 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4916 macro_build (p
, &icnt
, &offset_expr
,
4918 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4920 if (expr1
.X_add_number
>= -0x8000
4921 && expr1
.X_add_number
< 0x8000)
4923 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4925 macro_build (p
, &icnt
, &expr1
,
4926 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4927 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4928 /* FIXME: If add_number is 0, and there was no base
4929 register, the external symbol case ended with a load,
4930 so if the symbol turns out to not be external, and
4931 the next instruction uses tempreg, an unnecessary nop
4932 will be inserted. */
4938 /* We must add in the base register now, as in the
4939 external symbol case. */
4940 assert (tempreg
== AT
);
4941 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4943 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4944 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4945 "d,v,t", treg
, AT
, breg
);
4948 /* We set breg to 0 because we have arranged to add
4949 it in in both cases. */
4953 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4955 macro_build (p
, &icnt
, &expr1
,
4956 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4957 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4959 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4960 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4961 "d,v,t", tempreg
, tempreg
, AT
);
4965 else if (mips_pic
== EMBEDDED_PIC
)
4968 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4970 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4971 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4972 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4979 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4980 "d,v,t", treg
, tempreg
, breg
);
4988 /* The j instruction may not be used in PIC code, since it
4989 requires an absolute address. We convert it to a b
4991 if (mips_pic
== NO_PIC
)
4992 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4997 /* The jal instructions must be handled as macros because when
4998 generating PIC code they expand to multi-instruction
4999 sequences. Normally they are simple instructions. */
5004 if (mips_pic
== NO_PIC
5005 || mips_pic
== EMBEDDED_PIC
)
5006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5008 else if (mips_pic
== SVR4_PIC
)
5010 if (sreg
!= PIC_CALL_REG
)
5011 as_warn (_("MIPS PIC call to register other than $25"));
5013 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5017 if (mips_cprestore_offset
< 0)
5018 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5021 expr1
.X_add_number
= mips_cprestore_offset
;
5022 macro_build ((char *) NULL
, &icnt
, &expr1
,
5023 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5024 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5034 if (mips_pic
== NO_PIC
)
5035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5036 else if (mips_pic
== SVR4_PIC
)
5038 /* If this is a reference to an external symbol, and we are
5039 using a small GOT, we want
5040 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5044 lw $gp,cprestore($sp)
5045 The cprestore value is set using the .cprestore
5046 pseudo-op. If we are using a big GOT, we want
5047 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5049 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5053 lw $gp,cprestore($sp)
5054 If the symbol is not external, we want
5055 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5057 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5060 lw $gp,cprestore($sp) */
5064 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5065 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5066 "t,o(b)", PIC_CALL_REG
,
5067 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5068 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5070 p
= frag_var (rs_machine_dependent
, 4, 0,
5071 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5072 offset_expr
.X_add_symbol
, (offsetT
) 0,
5079 if (reg_needs_delay (GP
))
5083 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5084 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5085 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5086 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5087 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5089 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5090 "t,o(b)", PIC_CALL_REG
,
5091 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5094 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5095 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5097 offset_expr
.X_add_symbol
, (offsetT
) 0,
5101 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5104 macro_build (p
, &icnt
, &offset_expr
,
5105 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5106 "t,o(b)", PIC_CALL_REG
,
5107 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5109 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5112 macro_build (p
, &icnt
, &offset_expr
,
5113 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5114 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5115 (int) BFD_RELOC_LO16
);
5116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5117 "jalr", "s", PIC_CALL_REG
);
5120 if (mips_cprestore_offset
< 0)
5121 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5124 if (mips_opts
.noreorder
)
5125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5127 expr1
.X_add_number
= mips_cprestore_offset
;
5128 macro_build ((char *) NULL
, &icnt
, &expr1
,
5129 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5130 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5134 else if (mips_pic
== EMBEDDED_PIC
)
5136 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5137 /* The linker may expand the call to a longer sequence which
5138 uses $at, so we must break rather than return. */
5163 /* Itbl support may require additional care here. */
5168 /* Itbl support may require additional care here. */
5173 /* Itbl support may require additional care here. */
5178 /* Itbl support may require additional care here. */
5190 if (mips_arch
== CPU_R4650
)
5192 as_bad (_("opcode not supported on this processor"));
5196 /* Itbl support may require additional care here. */
5201 /* Itbl support may require additional care here. */
5206 /* Itbl support may require additional care here. */
5226 if (breg
== treg
|| coproc
|| lr
)
5248 /* Itbl support may require additional care here. */
5253 /* Itbl support may require additional care here. */
5258 /* Itbl support may require additional care here. */
5263 /* Itbl support may require additional care here. */
5279 if (mips_arch
== CPU_R4650
)
5281 as_bad (_("opcode not supported on this processor"));
5286 /* Itbl support may require additional care here. */
5290 /* Itbl support may require additional care here. */
5295 /* Itbl support may require additional care here. */
5307 /* Itbl support may require additional care here. */
5308 if (mask
== M_LWC1_AB
5309 || mask
== M_SWC1_AB
5310 || mask
== M_LDC1_AB
5311 || mask
== M_SDC1_AB
5320 /* For embedded PIC, we allow loads where the offset is calculated
5321 by subtracting a symbol in the current segment from an unknown
5322 symbol, relative to a base register, e.g.:
5323 <op> $treg, <sym>-<localsym>($breg)
5324 This is used by the compiler for switch statements. */
5325 if (mips_pic
== EMBEDDED_PIC
5326 && offset_expr
.X_op
== O_subtract
5327 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5328 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5329 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5331 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5335 && (offset_expr
.X_add_number
== 0
5336 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5338 /* For this case, we output the instructions:
5339 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5340 addiu $tempreg,$tempreg,$breg
5341 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5342 If the relocation would fit entirely in 16 bits, it would be
5344 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5345 instead, but that seems quite difficult. */
5346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5347 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5349 ((bfd_arch_bits_per_address (stdoutput
) == 32
5350 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5351 ? "addu" : "daddu"),
5352 "d,v,t", tempreg
, tempreg
, breg
);
5353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5354 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5360 if (offset_expr
.X_op
!= O_constant
5361 && offset_expr
.X_op
!= O_symbol
)
5363 as_bad (_("expression too complex"));
5364 offset_expr
.X_op
= O_constant
;
5367 /* A constant expression in PIC code can be handled just as it
5368 is in non PIC code. */
5369 if (mips_pic
== NO_PIC
5370 || offset_expr
.X_op
== O_constant
)
5372 /* If this is a reference to a GP relative symbol, and there
5373 is no base register, we want
5374 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5375 Otherwise, if there is no base register, we want
5376 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5377 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5378 If we have a constant, we need two instructions anyhow,
5379 so we always use the latter form.
5381 If we have a base register, and this is a reference to a
5382 GP relative symbol, we want
5383 addu $tempreg,$breg,$gp
5384 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5386 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5387 addu $tempreg,$tempreg,$breg
5388 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5389 With a constant we always use the latter case.
5391 With 64bit address space and no base register and $at usable,
5393 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5394 lui $at,<sym> (BFD_RELOC_HI16_S)
5395 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5398 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5399 If we have a base register, we want
5400 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5401 lui $at,<sym> (BFD_RELOC_HI16_S)
5402 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5406 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5408 Without $at we can't generate the optimal path for superscalar
5409 processors here since this would require two temporary registers.
5410 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5411 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5413 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5415 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5416 If we have a base register, we want
5417 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5418 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5420 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5422 daddu $tempreg,$tempreg,$breg
5423 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5425 if (HAVE_64BIT_ADDRESSES
)
5429 /* We don't do GP optimization for now because RELAX_ENCODE can't
5430 hold the data for such large chunks. */
5434 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5435 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5436 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5437 AT
, (int) BFD_RELOC_HI16_S
);
5438 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5439 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5441 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5443 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
5444 tempreg
, tempreg
, 0);
5445 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5446 tempreg
, tempreg
, AT
);
5447 macro_build (p
, &icnt
, &offset_expr
, s
,
5448 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5453 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5454 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5455 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5456 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5457 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
5458 tempreg
, tempreg
, 16);
5459 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5460 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5461 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
5462 tempreg
, tempreg
, 16);
5464 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5465 tempreg
, tempreg
, breg
);
5466 macro_build (p
, &icnt
, &offset_expr
, s
,
5467 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5475 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5476 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5482 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5483 p
= frag_var (rs_machine_dependent
, 8, 0,
5484 RELAX_ENCODE (4, 8, 0, 4, 0,
5485 (mips_opts
.warn_about_macros
5487 && mips_opts
.noat
))),
5488 offset_expr
.X_add_symbol
, (offsetT
) 0,
5492 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5495 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5496 (int) BFD_RELOC_LO16
, tempreg
);
5500 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5501 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5507 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5508 "d,v,t", tempreg
, breg
, GP
);
5509 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5510 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5511 p
= frag_var (rs_machine_dependent
, 12, 0,
5512 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5513 offset_expr
.X_add_symbol
, (offsetT
) 0,
5516 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5519 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5520 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5521 "d,v,t", tempreg
, tempreg
, breg
);
5524 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5525 (int) BFD_RELOC_LO16
, tempreg
);
5528 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5530 /* If this is a reference to an external symbol, we want
5531 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5533 <op> $treg,0($tempreg)
5535 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5537 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5538 <op> $treg,0($tempreg)
5539 If there is a base register, we add it to $tempreg before
5540 the <op>. If there is a constant, we stick it in the
5541 <op> instruction. We don't handle constants larger than
5542 16 bits, because we have no way to load the upper 16 bits
5543 (actually, we could handle them for the subset of cases
5544 in which we are not using $at). */
5545 assert (offset_expr
.X_op
== O_symbol
);
5546 expr1
.X_add_number
= offset_expr
.X_add_number
;
5547 offset_expr
.X_add_number
= 0;
5548 if (expr1
.X_add_number
< -0x8000
5549 || expr1
.X_add_number
>= 0x8000)
5550 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5553 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5554 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5556 p
= frag_var (rs_machine_dependent
, 4, 0,
5557 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5558 offset_expr
.X_add_symbol
, (offsetT
) 0,
5560 macro_build (p
, &icnt
, &offset_expr
,
5561 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5562 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5565 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5566 "d,v,t", tempreg
, tempreg
, breg
);
5567 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5568 (int) BFD_RELOC_LO16
, tempreg
);
5570 else if (mips_pic
== SVR4_PIC
)
5574 /* If this is a reference to an external symbol, we want
5575 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5576 addu $tempreg,$tempreg,$gp
5577 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5578 <op> $treg,0($tempreg)
5580 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5582 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5583 <op> $treg,0($tempreg)
5584 If there is a base register, we add it to $tempreg before
5585 the <op>. If there is a constant, we stick it in the
5586 <op> instruction. We don't handle constants larger than
5587 16 bits, because we have no way to load the upper 16 bits
5588 (actually, we could handle them for the subset of cases
5589 in which we are not using $at). */
5590 assert (offset_expr
.X_op
== O_symbol
);
5591 expr1
.X_add_number
= offset_expr
.X_add_number
;
5592 offset_expr
.X_add_number
= 0;
5593 if (expr1
.X_add_number
< -0x8000
5594 || expr1
.X_add_number
>= 0x8000)
5595 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5596 if (reg_needs_delay (GP
))
5601 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5602 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5604 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5605 "d,v,t", tempreg
, tempreg
, GP
);
5606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5607 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5608 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5610 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5611 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5612 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5615 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5618 macro_build (p
, &icnt
, &offset_expr
,
5619 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5620 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5622 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5624 macro_build (p
, &icnt
, &offset_expr
,
5625 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5626 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5628 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5629 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5630 "d,v,t", tempreg
, tempreg
, breg
);
5631 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5632 (int) BFD_RELOC_LO16
, tempreg
);
5634 else if (mips_pic
== EMBEDDED_PIC
)
5636 /* If there is no base register, we want
5637 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5638 If there is a base register, we want
5639 addu $tempreg,$breg,$gp
5640 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5642 assert (offset_expr
.X_op
== O_symbol
);
5645 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5646 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5651 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5652 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5653 "d,v,t", tempreg
, breg
, GP
);
5654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5655 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5668 load_register (&icnt
, treg
, &imm_expr
, 0);
5672 load_register (&icnt
, treg
, &imm_expr
, 1);
5676 if (imm_expr
.X_op
== O_constant
)
5678 load_register (&icnt
, AT
, &imm_expr
, 0);
5679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5680 "mtc1", "t,G", AT
, treg
);
5685 assert (offset_expr
.X_op
== O_symbol
5686 && strcmp (segment_name (S_GET_SEGMENT
5687 (offset_expr
.X_add_symbol
)),
5689 && offset_expr
.X_add_number
== 0);
5690 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5691 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5696 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5697 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5698 order 32 bits of the value and the low order 32 bits are either
5699 zero or in OFFSET_EXPR. */
5700 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5702 if (HAVE_64BIT_GPRS
)
5703 load_register (&icnt
, treg
, &imm_expr
, 1);
5708 if (target_big_endian
)
5720 load_register (&icnt
, hreg
, &imm_expr
, 0);
5723 if (offset_expr
.X_op
== O_absent
)
5724 move_register (&icnt
, lreg
, 0);
5727 assert (offset_expr
.X_op
== O_constant
);
5728 load_register (&icnt
, lreg
, &offset_expr
, 0);
5735 /* We know that sym is in the .rdata section. First we get the
5736 upper 16 bits of the address. */
5737 if (mips_pic
== NO_PIC
)
5739 /* FIXME: This won't work for a 64 bit address. */
5740 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5742 else if (mips_pic
== SVR4_PIC
)
5744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5745 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5746 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5748 else if (mips_pic
== EMBEDDED_PIC
)
5750 /* For embedded PIC we pick up the entire address off $gp in
5751 a single instruction. */
5752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5753 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5754 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5755 offset_expr
.X_op
= O_constant
;
5756 offset_expr
.X_add_number
= 0;
5761 /* Now we load the register(s). */
5762 if (HAVE_64BIT_GPRS
)
5763 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5764 treg
, (int) BFD_RELOC_LO16
, AT
);
5767 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5768 treg
, (int) BFD_RELOC_LO16
, AT
);
5771 /* FIXME: How in the world do we deal with the possible
5773 offset_expr
.X_add_number
+= 4;
5774 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5775 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5779 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5780 does not become a variant frag. */
5781 frag_wane (frag_now
);
5787 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5788 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5789 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5790 the value and the low order 32 bits are either zero or in
5792 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5794 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5795 if (HAVE_64BIT_FPRS
)
5797 assert (HAVE_64BIT_GPRS
);
5798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5799 "dmtc1", "t,S", AT
, treg
);
5803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5804 "mtc1", "t,G", AT
, treg
+ 1);
5805 if (offset_expr
.X_op
== O_absent
)
5806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5807 "mtc1", "t,G", 0, treg
);
5810 assert (offset_expr
.X_op
== O_constant
);
5811 load_register (&icnt
, AT
, &offset_expr
, 0);
5812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5813 "mtc1", "t,G", AT
, treg
);
5819 assert (offset_expr
.X_op
== O_symbol
5820 && offset_expr
.X_add_number
== 0);
5821 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5822 if (strcmp (s
, ".lit8") == 0)
5824 if (mips_opts
.isa
!= ISA_MIPS1
)
5826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5827 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5831 r
= BFD_RELOC_MIPS_LITERAL
;
5836 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5837 if (mips_pic
== SVR4_PIC
)
5838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5839 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5840 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5843 /* FIXME: This won't work for a 64 bit address. */
5844 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5847 if (mips_opts
.isa
!= ISA_MIPS1
)
5849 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5850 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5852 /* To avoid confusion in tc_gen_reloc, we must ensure
5853 that this does not become a variant frag. */
5854 frag_wane (frag_now
);
5865 if (mips_arch
== CPU_R4650
)
5867 as_bad (_("opcode not supported on this processor"));
5870 /* Even on a big endian machine $fn comes before $fn+1. We have
5871 to adjust when loading from memory. */
5874 assert (mips_opts
.isa
== ISA_MIPS1
);
5875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5876 target_big_endian
? treg
+ 1 : treg
,
5878 /* FIXME: A possible overflow which I don't know how to deal
5880 offset_expr
.X_add_number
+= 4;
5881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5882 target_big_endian
? treg
: treg
+ 1,
5885 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5886 does not become a variant frag. */
5887 frag_wane (frag_now
);
5896 * The MIPS assembler seems to check for X_add_number not
5897 * being double aligned and generating:
5900 * addiu at,at,%lo(foo+1)
5903 * But, the resulting address is the same after relocation so why
5904 * generate the extra instruction?
5906 if (mips_arch
== CPU_R4650
)
5908 as_bad (_("opcode not supported on this processor"));
5911 /* Itbl support may require additional care here. */
5913 if (mips_opts
.isa
!= ISA_MIPS1
)
5924 if (mips_arch
== CPU_R4650
)
5926 as_bad (_("opcode not supported on this processor"));
5930 if (mips_opts
.isa
!= ISA_MIPS1
)
5938 /* Itbl support may require additional care here. */
5943 if (HAVE_64BIT_GPRS
)
5954 if (HAVE_64BIT_GPRS
)
5964 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
5965 loads for the case of doing a pair of loads to simulate an 'ld'.
5966 This is not currently done by the compiler, and assembly coders
5967 writing embedded-pic code can cope. */
5969 if (offset_expr
.X_op
!= O_symbol
5970 && offset_expr
.X_op
!= O_constant
)
5972 as_bad (_("expression too complex"));
5973 offset_expr
.X_op
= O_constant
;
5976 /* Even on a big endian machine $fn comes before $fn+1. We have
5977 to adjust when loading from memory. We set coproc if we must
5978 load $fn+1 first. */
5979 /* Itbl support may require additional care here. */
5980 if (! target_big_endian
)
5983 if (mips_pic
== NO_PIC
5984 || offset_expr
.X_op
== O_constant
)
5986 /* If this is a reference to a GP relative symbol, we want
5987 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5988 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5989 If we have a base register, we use this
5991 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5992 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5993 If this is not a GP relative symbol, we want
5994 lui $at,<sym> (BFD_RELOC_HI16_S)
5995 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5996 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5997 If there is a base register, we add it to $at after the
5998 lui instruction. If there is a constant, we always use
6000 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6001 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6021 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6022 "d,v,t", AT
, breg
, GP
);
6028 /* Itbl support may require additional care here. */
6029 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6030 coproc
? treg
+ 1 : treg
,
6031 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6032 offset_expr
.X_add_number
+= 4;
6034 /* Set mips_optimize to 2 to avoid inserting an
6036 hold_mips_optimize
= mips_optimize
;
6038 /* Itbl support may require additional care here. */
6039 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6040 coproc
? treg
: treg
+ 1,
6041 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6042 mips_optimize
= hold_mips_optimize
;
6044 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6045 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6046 used_at
&& mips_opts
.noat
),
6047 offset_expr
.X_add_symbol
, (offsetT
) 0,
6050 /* We just generated two relocs. When tc_gen_reloc
6051 handles this case, it will skip the first reloc and
6052 handle the second. The second reloc already has an
6053 extra addend of 4, which we added above. We must
6054 subtract it out, and then subtract another 4 to make
6055 the first reloc come out right. The second reloc
6056 will come out right because we are going to add 4 to
6057 offset_expr when we build its instruction below.
6059 If we have a symbol, then we don't want to include
6060 the offset, because it will wind up being included
6061 when we generate the reloc. */
6063 if (offset_expr
.X_op
== O_constant
)
6064 offset_expr
.X_add_number
-= 8;
6067 offset_expr
.X_add_number
= -4;
6068 offset_expr
.X_op
= O_constant
;
6071 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6076 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6077 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6078 "d,v,t", AT
, breg
, AT
);
6082 /* Itbl support may require additional care here. */
6083 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6084 coproc
? treg
+ 1 : treg
,
6085 (int) BFD_RELOC_LO16
, AT
);
6088 /* FIXME: How do we handle overflow here? */
6089 offset_expr
.X_add_number
+= 4;
6090 /* Itbl support may require additional care here. */
6091 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6092 coproc
? treg
: treg
+ 1,
6093 (int) BFD_RELOC_LO16
, AT
);
6095 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6099 /* If this is a reference to an external symbol, we want
6100 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6105 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6107 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6108 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6109 If there is a base register we add it to $at before the
6110 lwc1 instructions. If there is a constant we include it
6111 in the lwc1 instructions. */
6113 expr1
.X_add_number
= offset_expr
.X_add_number
;
6114 offset_expr
.X_add_number
= 0;
6115 if (expr1
.X_add_number
< -0x8000
6116 || expr1
.X_add_number
>= 0x8000 - 4)
6117 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6122 frag_grow (24 + off
);
6123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6124 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6125 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6129 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6130 "d,v,t", AT
, breg
, AT
);
6131 /* Itbl support may require additional care here. */
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6133 coproc
? treg
+ 1 : treg
,
6134 (int) BFD_RELOC_LO16
, AT
);
6135 expr1
.X_add_number
+= 4;
6137 /* Set mips_optimize to 2 to avoid inserting an undesired
6139 hold_mips_optimize
= mips_optimize
;
6141 /* Itbl support may require additional care here. */
6142 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6143 coproc
? treg
: treg
+ 1,
6144 (int) BFD_RELOC_LO16
, AT
);
6145 mips_optimize
= hold_mips_optimize
;
6147 (void) frag_var (rs_machine_dependent
, 0, 0,
6148 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6149 offset_expr
.X_add_symbol
, (offsetT
) 0,
6152 else if (mips_pic
== SVR4_PIC
)
6156 /* If this is a reference to an external symbol, we want
6157 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6159 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6164 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6166 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6167 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6168 If there is a base register we add it to $at before the
6169 lwc1 instructions. If there is a constant we include it
6170 in the lwc1 instructions. */
6172 expr1
.X_add_number
= offset_expr
.X_add_number
;
6173 offset_expr
.X_add_number
= 0;
6174 if (expr1
.X_add_number
< -0x8000
6175 || expr1
.X_add_number
>= 0x8000 - 4)
6176 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6177 if (reg_needs_delay (GP
))
6186 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6187 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6189 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6190 "d,v,t", AT
, AT
, GP
);
6191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6192 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6193 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6194 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6197 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6198 "d,v,t", AT
, breg
, AT
);
6199 /* Itbl support may require additional care here. */
6200 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6201 coproc
? treg
+ 1 : treg
,
6202 (int) BFD_RELOC_LO16
, AT
);
6203 expr1
.X_add_number
+= 4;
6205 /* Set mips_optimize to 2 to avoid inserting an undesired
6207 hold_mips_optimize
= mips_optimize
;
6209 /* Itbl support may require additional care here. */
6210 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6211 coproc
? treg
: treg
+ 1,
6212 (int) BFD_RELOC_LO16
, AT
);
6213 mips_optimize
= hold_mips_optimize
;
6214 expr1
.X_add_number
-= 4;
6216 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6217 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6218 8 + gpdel
+ off
, 1, 0),
6219 offset_expr
.X_add_symbol
, (offsetT
) 0,
6223 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6226 macro_build (p
, &icnt
, &offset_expr
,
6227 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6228 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6230 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6234 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6235 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6236 "d,v,t", AT
, breg
, AT
);
6239 /* Itbl support may require additional care here. */
6240 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6241 coproc
? treg
+ 1 : treg
,
6242 (int) BFD_RELOC_LO16
, AT
);
6244 expr1
.X_add_number
+= 4;
6246 /* Set mips_optimize to 2 to avoid inserting an undesired
6248 hold_mips_optimize
= mips_optimize
;
6250 /* Itbl support may require additional care here. */
6251 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6252 coproc
? treg
: treg
+ 1,
6253 (int) BFD_RELOC_LO16
, AT
);
6254 mips_optimize
= hold_mips_optimize
;
6256 else if (mips_pic
== EMBEDDED_PIC
)
6258 /* If there is no base register, we use
6259 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
6260 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
6261 If we have a base register, we use
6263 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
6264 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
6273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6274 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6275 "d,v,t", AT
, breg
, GP
);
6280 /* Itbl support may require additional care here. */
6281 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6282 coproc
? treg
+ 1 : treg
,
6283 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6284 offset_expr
.X_add_number
+= 4;
6285 /* Itbl support may require additional care here. */
6286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6287 coproc
? treg
: treg
+ 1,
6288 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6304 assert (HAVE_32BIT_ADDRESSES
);
6305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6306 (int) BFD_RELOC_LO16
, breg
);
6307 offset_expr
.X_add_number
+= 4;
6308 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6309 (int) BFD_RELOC_LO16
, breg
);
6312 /* New code added to support COPZ instructions.
6313 This code builds table entries out of the macros in mip_opcodes.
6314 R4000 uses interlocks to handle coproc delays.
6315 Other chips (like the R3000) require nops to be inserted for delays.
6317 FIXME: Currently, we require that the user handle delays.
6318 In order to fill delay slots for non-interlocked chips,
6319 we must have a way to specify delays based on the coprocessor.
6320 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6321 What are the side-effects of the cop instruction?
6322 What cache support might we have and what are its effects?
6323 Both coprocessor & memory require delays. how long???
6324 What registers are read/set/modified?
6326 If an itbl is provided to interpret cop instructions,
6327 this knowledge can be encoded in the itbl spec. */
6341 /* For now we just do C (same as Cz). The parameter will be
6342 stored in insn_opcode by mips_ip. */
6343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6348 move_register (&icnt
, dreg
, sreg
);
6351 #ifdef LOSING_COMPILER
6353 /* Try and see if this is a new itbl instruction.
6354 This code builds table entries out of the macros in mip_opcodes.
6355 FIXME: For now we just assemble the expression and pass it's
6356 value along as a 32-bit immediate.
6357 We may want to have the assembler assemble this value,
6358 so that we gain the assembler's knowledge of delay slots,
6360 Would it be more efficient to use mask (id) here? */
6361 if (itbl_have_entries
6362 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6364 s
= ip
->insn_mo
->name
;
6366 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6367 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6374 as_warn (_("Macro used $at after \".set noat\""));
6379 struct mips_cl_insn
*ip
;
6381 register int treg
, sreg
, dreg
, breg
;
6397 bfd_reloc_code_real_type r
;
6400 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6401 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6402 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6403 mask
= ip
->insn_mo
->mask
;
6405 expr1
.X_op
= O_constant
;
6406 expr1
.X_op_symbol
= NULL
;
6407 expr1
.X_add_symbol
= NULL
;
6408 expr1
.X_add_number
= 1;
6412 #endif /* LOSING_COMPILER */
6417 macro_build ((char *) NULL
, &icnt
, NULL
,
6418 dbl
? "dmultu" : "multu",
6420 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6426 /* The MIPS assembler some times generates shifts and adds. I'm
6427 not trying to be that fancy. GCC should do this for us
6429 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6430 macro_build ((char *) NULL
, &icnt
, NULL
,
6431 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6432 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6445 mips_emit_delays (true);
6446 ++mips_opts
.noreorder
;
6447 mips_any_noreorder
= 1;
6449 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6450 macro_build ((char *) NULL
, &icnt
, NULL
,
6451 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6452 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6453 macro_build ((char *) NULL
, &icnt
, NULL
,
6454 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6455 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6457 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6460 expr1
.X_add_number
= 8;
6461 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6462 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6463 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6465 --mips_opts
.noreorder
;
6466 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6479 mips_emit_delays (true);
6480 ++mips_opts
.noreorder
;
6481 mips_any_noreorder
= 1;
6483 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6484 macro_build ((char *) NULL
, &icnt
, NULL
,
6485 dbl
? "dmultu" : "multu",
6486 "s,t", sreg
, imm
? AT
: treg
);
6487 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6488 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6490 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6493 expr1
.X_add_number
= 8;
6494 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6495 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6496 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6498 --mips_opts
.noreorder
;
6502 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6503 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6504 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6506 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6510 if (imm_expr
.X_op
!= O_constant
)
6511 as_bad (_("rotate count too large"));
6512 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6513 (int) (imm_expr
.X_add_number
& 0x1f));
6514 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6515 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6516 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6520 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6521 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6522 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6524 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6528 if (imm_expr
.X_op
!= O_constant
)
6529 as_bad (_("rotate count too large"));
6530 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6531 (int) (imm_expr
.X_add_number
& 0x1f));
6532 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6533 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6534 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6538 if (mips_arch
== CPU_R4650
)
6540 as_bad (_("opcode not supported on this processor"));
6543 assert (mips_opts
.isa
== ISA_MIPS1
);
6544 /* Even on a big endian machine $fn comes before $fn+1. We have
6545 to adjust when storing to memory. */
6546 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6547 target_big_endian
? treg
+ 1 : treg
,
6548 (int) BFD_RELOC_LO16
, breg
);
6549 offset_expr
.X_add_number
+= 4;
6550 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6551 target_big_endian
? treg
: treg
+ 1,
6552 (int) BFD_RELOC_LO16
, breg
);
6557 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6558 treg
, (int) BFD_RELOC_LO16
);
6560 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6561 sreg
, (int) BFD_RELOC_LO16
);
6564 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6566 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6567 dreg
, (int) BFD_RELOC_LO16
);
6572 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6574 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6575 sreg
, (int) BFD_RELOC_LO16
);
6580 as_warn (_("Instruction %s: result is always false"),
6582 move_register (&icnt
, dreg
, 0);
6585 if (imm_expr
.X_op
== O_constant
6586 && imm_expr
.X_add_number
>= 0
6587 && imm_expr
.X_add_number
< 0x10000)
6589 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6590 sreg
, (int) BFD_RELOC_LO16
);
6593 else if (imm_expr
.X_op
== O_constant
6594 && imm_expr
.X_add_number
> -0x8000
6595 && imm_expr
.X_add_number
< 0)
6597 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6598 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6599 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6600 "t,r,j", dreg
, sreg
,
6601 (int) BFD_RELOC_LO16
);
6606 load_register (&icnt
, AT
, &imm_expr
, 0);
6607 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6611 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6612 (int) BFD_RELOC_LO16
);
6617 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6623 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6624 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6625 (int) BFD_RELOC_LO16
);
6628 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6630 if (imm_expr
.X_op
== O_constant
6631 && imm_expr
.X_add_number
>= -0x8000
6632 && imm_expr
.X_add_number
< 0x8000)
6634 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6635 mask
== M_SGE_I
? "slti" : "sltiu",
6636 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6641 load_register (&icnt
, AT
, &imm_expr
, 0);
6642 macro_build ((char *) NULL
, &icnt
, NULL
,
6643 mask
== M_SGE_I
? "slt" : "sltu",
6644 "d,v,t", dreg
, sreg
, AT
);
6647 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6648 (int) BFD_RELOC_LO16
);
6653 case M_SGT
: /* sreg > treg <==> treg < sreg */
6659 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6662 case M_SGT_I
: /* sreg > I <==> I < sreg */
6668 load_register (&icnt
, AT
, &imm_expr
, 0);
6669 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6672 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6678 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6679 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6680 (int) BFD_RELOC_LO16
);
6683 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6689 load_register (&icnt
, AT
, &imm_expr
, 0);
6690 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6691 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6692 (int) BFD_RELOC_LO16
);
6696 if (imm_expr
.X_op
== O_constant
6697 && imm_expr
.X_add_number
>= -0x8000
6698 && imm_expr
.X_add_number
< 0x8000)
6700 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6701 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6704 load_register (&icnt
, AT
, &imm_expr
, 0);
6705 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6709 if (imm_expr
.X_op
== O_constant
6710 && imm_expr
.X_add_number
>= -0x8000
6711 && imm_expr
.X_add_number
< 0x8000)
6713 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6714 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6717 load_register (&icnt
, AT
, &imm_expr
, 0);
6718 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6724 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6727 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6731 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6733 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6739 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6741 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6747 as_warn (_("Instruction %s: result is always true"),
6749 macro_build ((char *) NULL
, &icnt
, &expr1
,
6750 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6751 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6754 if (imm_expr
.X_op
== O_constant
6755 && imm_expr
.X_add_number
>= 0
6756 && imm_expr
.X_add_number
< 0x10000)
6758 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6759 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6762 else if (imm_expr
.X_op
== O_constant
6763 && imm_expr
.X_add_number
> -0x8000
6764 && imm_expr
.X_add_number
< 0)
6766 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6767 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6768 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6769 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6774 load_register (&icnt
, AT
, &imm_expr
, 0);
6775 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6779 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6787 if (imm_expr
.X_op
== O_constant
6788 && imm_expr
.X_add_number
> -0x8000
6789 && imm_expr
.X_add_number
<= 0x8000)
6791 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6792 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6793 dbl
? "daddi" : "addi",
6794 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6797 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6798 macro_build ((char *) NULL
, &icnt
, NULL
,
6799 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6805 if (imm_expr
.X_op
== O_constant
6806 && imm_expr
.X_add_number
> -0x8000
6807 && imm_expr
.X_add_number
<= 0x8000)
6809 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6810 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6811 dbl
? "daddiu" : "addiu",
6812 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6815 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6816 macro_build ((char *) NULL
, &icnt
, NULL
,
6817 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6838 load_register (&icnt
, AT
, &imm_expr
, 0);
6839 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6844 assert (mips_opts
.isa
== ISA_MIPS1
);
6845 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6846 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6849 * Is the double cfc1 instruction a bug in the mips assembler;
6850 * or is there a reason for it?
6852 mips_emit_delays (true);
6853 ++mips_opts
.noreorder
;
6854 mips_any_noreorder
= 1;
6855 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6856 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6857 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6858 expr1
.X_add_number
= 3;
6859 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6860 (int) BFD_RELOC_LO16
);
6861 expr1
.X_add_number
= 2;
6862 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6863 (int) BFD_RELOC_LO16
);
6864 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6865 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6866 macro_build ((char *) NULL
, &icnt
, NULL
,
6867 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6868 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6869 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6870 --mips_opts
.noreorder
;
6879 if (offset_expr
.X_add_number
>= 0x7fff)
6880 as_bad (_("operand overflow"));
6881 /* avoid load delay */
6882 if (! target_big_endian
)
6883 offset_expr
.X_add_number
+= 1;
6884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6885 (int) BFD_RELOC_LO16
, breg
);
6886 if (! target_big_endian
)
6887 offset_expr
.X_add_number
-= 1;
6889 offset_expr
.X_add_number
+= 1;
6890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6891 (int) BFD_RELOC_LO16
, breg
);
6892 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6893 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6906 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6907 as_bad (_("operand overflow"));
6908 if (! target_big_endian
)
6909 offset_expr
.X_add_number
+= off
;
6910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6911 (int) BFD_RELOC_LO16
, breg
);
6912 if (! target_big_endian
)
6913 offset_expr
.X_add_number
-= off
;
6915 offset_expr
.X_add_number
+= off
;
6916 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6917 (int) BFD_RELOC_LO16
, breg
);
6931 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6934 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6935 "d,v,t", AT
, AT
, breg
);
6936 if (! target_big_endian
)
6937 expr1
.X_add_number
= off
;
6939 expr1
.X_add_number
= 0;
6940 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6941 (int) BFD_RELOC_LO16
, AT
);
6942 if (! target_big_endian
)
6943 expr1
.X_add_number
= 0;
6945 expr1
.X_add_number
= off
;
6946 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6947 (int) BFD_RELOC_LO16
, AT
);
6953 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6956 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6957 "d,v,t", AT
, AT
, breg
);
6958 if (target_big_endian
)
6959 expr1
.X_add_number
= 0;
6960 macro_build ((char *) NULL
, &icnt
, &expr1
,
6961 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6962 (int) BFD_RELOC_LO16
, AT
);
6963 if (target_big_endian
)
6964 expr1
.X_add_number
= 1;
6966 expr1
.X_add_number
= 0;
6967 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6968 (int) BFD_RELOC_LO16
, AT
);
6969 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6971 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6976 if (offset_expr
.X_add_number
>= 0x7fff)
6977 as_bad (_("operand overflow"));
6978 if (target_big_endian
)
6979 offset_expr
.X_add_number
+= 1;
6980 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6981 (int) BFD_RELOC_LO16
, breg
);
6982 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6983 if (target_big_endian
)
6984 offset_expr
.X_add_number
-= 1;
6986 offset_expr
.X_add_number
+= 1;
6987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6988 (int) BFD_RELOC_LO16
, breg
);
7001 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7002 as_bad (_("operand overflow"));
7003 if (! target_big_endian
)
7004 offset_expr
.X_add_number
+= off
;
7005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7006 (int) BFD_RELOC_LO16
, breg
);
7007 if (! target_big_endian
)
7008 offset_expr
.X_add_number
-= off
;
7010 offset_expr
.X_add_number
+= off
;
7011 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7012 (int) BFD_RELOC_LO16
, breg
);
7026 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7029 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7030 "d,v,t", AT
, AT
, breg
);
7031 if (! target_big_endian
)
7032 expr1
.X_add_number
= off
;
7034 expr1
.X_add_number
= 0;
7035 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7036 (int) BFD_RELOC_LO16
, AT
);
7037 if (! target_big_endian
)
7038 expr1
.X_add_number
= 0;
7040 expr1
.X_add_number
= off
;
7041 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7042 (int) BFD_RELOC_LO16
, AT
);
7047 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7049 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7050 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7051 "d,v,t", AT
, AT
, breg
);
7052 if (! target_big_endian
)
7053 expr1
.X_add_number
= 0;
7054 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7055 (int) BFD_RELOC_LO16
, AT
);
7056 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
7058 if (! target_big_endian
)
7059 expr1
.X_add_number
= 1;
7061 expr1
.X_add_number
= 0;
7062 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7063 (int) BFD_RELOC_LO16
, AT
);
7064 if (! target_big_endian
)
7065 expr1
.X_add_number
= 0;
7067 expr1
.X_add_number
= 1;
7068 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7069 (int) BFD_RELOC_LO16
, AT
);
7070 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
7072 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
7077 /* FIXME: Check if this is one of the itbl macros, since they
7078 are added dynamically. */
7079 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7083 as_warn (_("Macro used $at after \".set noat\""));
7086 /* Implement macros in mips16 mode. */
7090 struct mips_cl_insn
*ip
;
7093 int xreg
, yreg
, zreg
, tmp
;
7097 const char *s
, *s2
, *s3
;
7099 mask
= ip
->insn_mo
->mask
;
7101 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7102 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7103 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7107 expr1
.X_op
= O_constant
;
7108 expr1
.X_op_symbol
= NULL
;
7109 expr1
.X_add_symbol
= NULL
;
7110 expr1
.X_add_number
= 1;
7129 mips_emit_delays (true);
7130 ++mips_opts
.noreorder
;
7131 mips_any_noreorder
= 1;
7132 macro_build ((char *) NULL
, &icnt
, NULL
,
7133 dbl
? "ddiv" : "div",
7134 "0,x,y", xreg
, yreg
);
7135 expr1
.X_add_number
= 2;
7136 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7137 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
7139 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7140 since that causes an overflow. We should do that as well,
7141 but I don't see how to do the comparisons without a temporary
7143 --mips_opts
.noreorder
;
7144 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
7163 mips_emit_delays (true);
7164 ++mips_opts
.noreorder
;
7165 mips_any_noreorder
= 1;
7166 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
7167 expr1
.X_add_number
= 2;
7168 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7169 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
7170 --mips_opts
.noreorder
;
7171 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
7177 macro_build ((char *) NULL
, &icnt
, NULL
,
7178 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7179 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
7187 if (imm_expr
.X_op
!= O_constant
)
7188 as_bad (_("Unsupported large constant"));
7189 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7190 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7191 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7195 if (imm_expr
.X_op
!= O_constant
)
7196 as_bad (_("Unsupported large constant"));
7197 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7198 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7203 if (imm_expr
.X_op
!= O_constant
)
7204 as_bad (_("Unsupported large constant"));
7205 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7206 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7229 goto do_reverse_branch
;
7233 goto do_reverse_branch
;
7245 goto do_reverse_branch
;
7256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7285 goto do_addone_branch_i
;
7290 goto do_addone_branch_i
;
7305 goto do_addone_branch_i
;
7312 if (imm_expr
.X_op
!= O_constant
)
7313 as_bad (_("Unsupported large constant"));
7314 ++imm_expr
.X_add_number
;
7317 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7322 expr1
.X_add_number
= 0;
7323 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7325 move_register (&icnt
, xreg
, yreg
);
7326 expr1
.X_add_number
= 2;
7327 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7329 "neg", "x,w", xreg
, xreg
);
7333 /* For consistency checking, verify that all bits are specified either
7334 by the match/mask part of the instruction definition, or by the
7337 validate_mips_insn (opc
)
7338 const struct mips_opcode
*opc
;
7340 const char *p
= opc
->args
;
7342 unsigned long used_bits
= opc
->mask
;
7344 if ((used_bits
& opc
->match
) != opc
->match
)
7346 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7347 opc
->name
, opc
->args
);
7350 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7357 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7358 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7360 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7361 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7362 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7363 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7365 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7366 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7368 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7370 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7371 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7372 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7373 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7374 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7375 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7376 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7377 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7378 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7379 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7380 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7382 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7383 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7384 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7385 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7387 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7388 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7389 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7390 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7391 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7392 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7393 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7394 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7395 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7398 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7399 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7400 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7402 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7403 c
, opc
->name
, opc
->args
);
7407 if (used_bits
!= 0xffffffff)
7409 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7410 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7416 /* This routine assembles an instruction into its binary format. As a
7417 side effect, it sets one of the global variables imm_reloc or
7418 offset_reloc to the type of relocation to do if one of the operands
7419 is an address expression. */
7424 struct mips_cl_insn
*ip
;
7429 struct mips_opcode
*insn
;
7432 unsigned int lastregno
= 0;
7435 int full_opcode_match
= 1;
7439 /* If the instruction contains a '.', we first try to match an instruction
7440 including the '.'. Then we try again without the '.'. */
7442 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7445 /* If we stopped on whitespace, then replace the whitespace with null for
7446 the call to hash_find. Save the character we replaced just in case we
7447 have to re-parse the instruction. */
7454 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7456 /* If we didn't find the instruction in the opcode table, try again, but
7457 this time with just the instruction up to, but not including the
7461 /* Restore the character we overwrite above (if any). */
7465 /* Scan up to the first '.' or whitespace. */
7467 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7471 /* If we did not find a '.', then we can quit now. */
7474 insn_error
= "unrecognized opcode";
7478 /* Lookup the instruction in the hash table. */
7480 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7482 insn_error
= "unrecognized opcode";
7486 full_opcode_match
= 0;
7494 assert (strcmp (insn
->name
, str
) == 0);
7496 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7501 if (insn
->pinfo
!= INSN_MACRO
)
7503 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7509 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7510 && strcmp (insn
->name
, insn
[1].name
) == 0)
7519 static char buf
[100];
7521 _("opcode not supported on this processor: %s (%s)"),
7522 mips_cpu_to_str (mips_arch
),
7523 mips_isa_to_str (mips_opts
.isa
));
7534 ip
->insn_opcode
= insn
->match
;
7536 for (args
= insn
->args
;; ++args
)
7538 s
+= strspn (s
, " \t");
7541 case '\0': /* end of args */
7554 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7558 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7562 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7566 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7572 /* Handle optional base register.
7573 Either the base register is omitted or
7574 we must have a left paren. */
7575 /* This is dependent on the next operand specifier
7576 is a base register specification. */
7577 assert (args
[1] == 'b' || args
[1] == '5'
7578 || args
[1] == '-' || args
[1] == '4');
7582 case ')': /* these must match exactly */
7587 case '<': /* must be at least one digit */
7589 * According to the manual, if the shift amount is greater
7590 * than 31 or less than 0, then the shift amount should be
7591 * mod 32. In reality the mips assembler issues an error.
7592 * We issue a warning and mask out all but the low 5 bits.
7594 my_getExpression (&imm_expr
, s
);
7595 check_absolute_expr (ip
, &imm_expr
);
7596 if ((unsigned long) imm_expr
.X_add_number
> 31)
7598 as_warn (_("Improper shift amount (%ld)"),
7599 (long) imm_expr
.X_add_number
);
7600 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7602 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7603 imm_expr
.X_op
= O_absent
;
7607 case '>': /* shift amount minus 32 */
7608 my_getExpression (&imm_expr
, s
);
7609 check_absolute_expr (ip
, &imm_expr
);
7610 if ((unsigned long) imm_expr
.X_add_number
< 32
7611 || (unsigned long) imm_expr
.X_add_number
> 63)
7613 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7614 imm_expr
.X_op
= O_absent
;
7618 case 'k': /* cache code */
7619 case 'h': /* prefx code */
7620 my_getExpression (&imm_expr
, s
);
7621 check_absolute_expr (ip
, &imm_expr
);
7622 if ((unsigned long) imm_expr
.X_add_number
> 31)
7624 as_warn (_("Invalid value for `%s' (%lu)"),
7626 (unsigned long) imm_expr
.X_add_number
);
7627 imm_expr
.X_add_number
&= 0x1f;
7630 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7632 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7633 imm_expr
.X_op
= O_absent
;
7637 case 'c': /* break code */
7638 my_getExpression (&imm_expr
, s
);
7639 check_absolute_expr (ip
, &imm_expr
);
7640 if ((unsigned) imm_expr
.X_add_number
> 1023)
7642 as_warn (_("Illegal break code (%ld)"),
7643 (long) imm_expr
.X_add_number
);
7644 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7646 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7647 imm_expr
.X_op
= O_absent
;
7651 case 'q': /* lower break code */
7652 my_getExpression (&imm_expr
, s
);
7653 check_absolute_expr (ip
, &imm_expr
);
7654 if ((unsigned) imm_expr
.X_add_number
> 1023)
7656 as_warn (_("Illegal lower break code (%ld)"),
7657 (long) imm_expr
.X_add_number
);
7658 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7660 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7661 imm_expr
.X_op
= O_absent
;
7665 case 'B': /* 20-bit syscall/break code. */
7666 my_getExpression (&imm_expr
, s
);
7667 check_absolute_expr (ip
, &imm_expr
);
7668 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7669 as_warn (_("Illegal 20-bit code (%ld)"),
7670 (long) imm_expr
.X_add_number
);
7671 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7672 imm_expr
.X_op
= O_absent
;
7676 case 'C': /* Coprocessor code */
7677 my_getExpression (&imm_expr
, s
);
7678 check_absolute_expr (ip
, &imm_expr
);
7679 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7681 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7682 (long) imm_expr
.X_add_number
);
7683 imm_expr
.X_add_number
&= ((1<<25) - 1);
7685 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7686 imm_expr
.X_op
= O_absent
;
7690 case 'J': /* 19-bit wait code. */
7691 my_getExpression (&imm_expr
, s
);
7692 check_absolute_expr (ip
, &imm_expr
);
7693 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7694 as_warn (_("Illegal 19-bit code (%ld)"),
7695 (long) imm_expr
.X_add_number
);
7696 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7697 imm_expr
.X_op
= O_absent
;
7701 case 'P': /* Performance register */
7702 my_getExpression (&imm_expr
, s
);
7703 check_absolute_expr (ip
, &imm_expr
);
7704 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7706 as_warn (_("Invalid performance register (%ld)"),
7707 (long) imm_expr
.X_add_number
);
7708 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7710 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7711 imm_expr
.X_op
= O_absent
;
7715 case 'b': /* base register */
7716 case 'd': /* destination register */
7717 case 's': /* source register */
7718 case 't': /* target register */
7719 case 'r': /* both target and source */
7720 case 'v': /* both dest and source */
7721 case 'w': /* both dest and target */
7722 case 'E': /* coprocessor target register */
7723 case 'G': /* coprocessor destination register */
7724 case 'x': /* ignore register name */
7725 case 'z': /* must be zero register */
7726 case 'U': /* destination register (clo/clz). */
7741 while (ISDIGIT (*s
));
7743 as_bad (_("Invalid register number (%d)"), regno
);
7745 else if (*args
== 'E' || *args
== 'G')
7749 if (s
[1] == 'f' && s
[2] == 'p')
7754 else if (s
[1] == 's' && s
[2] == 'p')
7759 else if (s
[1] == 'g' && s
[2] == 'p')
7764 else if (s
[1] == 'a' && s
[2] == 't')
7769 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7774 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7779 else if (itbl_have_entries
)
7784 p
= s
+ 1; /* advance past '$' */
7785 n
= itbl_get_field (&p
); /* n is name */
7787 /* See if this is a register defined in an
7789 if (itbl_get_reg_val (n
, &r
))
7791 /* Get_field advances to the start of
7792 the next field, so we need to back
7793 rack to the end of the last field. */
7797 s
= strchr (s
, '\0');
7810 as_warn (_("Used $at without \".set noat\""));
7816 if (c
== 'r' || c
== 'v' || c
== 'w')
7823 /* 'z' only matches $0. */
7824 if (c
== 'z' && regno
!= 0)
7827 /* Now that we have assembled one operand, we use the args string
7828 * to figure out where it goes in the instruction. */
7835 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7839 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7842 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7843 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7848 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7851 /* This case exists because on the r3000 trunc
7852 expands into a macro which requires a gp
7853 register. On the r6000 or r4000 it is
7854 assembled into a single instruction which
7855 ignores the register. Thus the insn version
7856 is MIPS_ISA2 and uses 'x', and the macro
7857 version is MIPS_ISA1 and uses 't'. */
7860 /* This case is for the div instruction, which
7861 acts differently if the destination argument
7862 is $0. This only matches $0, and is checked
7863 outside the switch. */
7866 /* Itbl operand; not yet implemented. FIXME ?? */
7868 /* What about all other operands like 'i', which
7869 can be specified in the opcode table? */
7879 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7882 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7887 case 'D': /* floating point destination register */
7888 case 'S': /* floating point source register */
7889 case 'T': /* floating point target register */
7890 case 'R': /* floating point source register */
7894 if (s
[0] == '$' && s
[1] == 'f'
7905 while (ISDIGIT (*s
));
7908 as_bad (_("Invalid float register number (%d)"), regno
);
7910 if ((regno
& 1) != 0
7912 && ! (strcmp (str
, "mtc1") == 0
7913 || strcmp (str
, "mfc1") == 0
7914 || strcmp (str
, "lwc1") == 0
7915 || strcmp (str
, "swc1") == 0
7916 || strcmp (str
, "l.s") == 0
7917 || strcmp (str
, "s.s") == 0))
7918 as_warn (_("Float register should be even, was %d"),
7926 if (c
== 'V' || c
== 'W')
7936 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7940 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7944 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7947 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7957 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7960 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7966 my_getExpression (&imm_expr
, s
);
7967 if (imm_expr
.X_op
!= O_big
7968 && imm_expr
.X_op
!= O_constant
)
7969 insn_error
= _("absolute expression required");
7974 my_getExpression (&offset_expr
, s
);
7975 *imm_reloc
= BFD_RELOC_32
;
7988 unsigned char temp
[8];
7990 unsigned int length
;
7995 /* These only appear as the last operand in an
7996 instruction, and every instruction that accepts
7997 them in any variant accepts them in all variants.
7998 This means we don't have to worry about backing out
7999 any changes if the instruction does not match.
8001 The difference between them is the size of the
8002 floating point constant and where it goes. For 'F'
8003 and 'L' the constant is 64 bits; for 'f' and 'l' it
8004 is 32 bits. Where the constant is placed is based
8005 on how the MIPS assembler does things:
8008 f -- immediate value
8011 The .lit4 and .lit8 sections are only used if
8012 permitted by the -G argument.
8014 When generating embedded PIC code, we use the
8015 .lit8 section but not the .lit4 section (we can do
8016 .lit4 inline easily; we need to put .lit8
8017 somewhere in the data segment, and using .lit8
8018 permits the linker to eventually combine identical
8021 The code below needs to know whether the target register
8022 is 32 or 64 bits wide. It relies on the fact 'f' and
8023 'F' are used with GPR-based instructions and 'l' and
8024 'L' are used with FPR-based instructions. */
8026 f64
= *args
== 'F' || *args
== 'L';
8027 using_gprs
= *args
== 'F' || *args
== 'f';
8029 save_in
= input_line_pointer
;
8030 input_line_pointer
= s
;
8031 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8033 s
= input_line_pointer
;
8034 input_line_pointer
= save_in
;
8035 if (err
!= NULL
&& *err
!= '\0')
8037 as_bad (_("Bad floating point constant: %s"), err
);
8038 memset (temp
, '\0', sizeof temp
);
8039 length
= f64
? 8 : 4;
8042 assert (length
== (unsigned) (f64
? 8 : 4));
8046 && (! USE_GLOBAL_POINTER_OPT
8047 || mips_pic
== EMBEDDED_PIC
8048 || g_switch_value
< 4
8049 || (temp
[0] == 0 && temp
[1] == 0)
8050 || (temp
[2] == 0 && temp
[3] == 0))))
8052 imm_expr
.X_op
= O_constant
;
8053 if (! target_big_endian
)
8054 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8056 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8059 && ! mips_disable_float_construction
8060 /* Constants can only be constructed in GPRs and
8061 copied to FPRs if the GPRs are at least as wide
8062 as the FPRs. Force the constant into memory if
8063 we are using 64-bit FPRs but the GPRs are only
8066 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8067 && ((temp
[0] == 0 && temp
[1] == 0)
8068 || (temp
[2] == 0 && temp
[3] == 0))
8069 && ((temp
[4] == 0 && temp
[5] == 0)
8070 || (temp
[6] == 0 && temp
[7] == 0)))
8072 /* The value is simple enough to load with a couple of
8073 instructions. If using 32-bit registers, set
8074 imm_expr to the high order 32 bits and offset_expr to
8075 the low order 32 bits. Otherwise, set imm_expr to
8076 the entire 64 bit constant. */
8077 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8079 imm_expr
.X_op
= O_constant
;
8080 offset_expr
.X_op
= O_constant
;
8081 if (! target_big_endian
)
8083 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8084 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8088 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8089 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8091 if (offset_expr
.X_add_number
== 0)
8092 offset_expr
.X_op
= O_absent
;
8094 else if (sizeof (imm_expr
.X_add_number
) > 4)
8096 imm_expr
.X_op
= O_constant
;
8097 if (! target_big_endian
)
8098 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8100 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8104 imm_expr
.X_op
= O_big
;
8105 imm_expr
.X_add_number
= 4;
8106 if (! target_big_endian
)
8108 generic_bignum
[0] = bfd_getl16 (temp
);
8109 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8110 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8111 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8115 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8116 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8117 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8118 generic_bignum
[3] = bfd_getb16 (temp
);
8124 const char *newname
;
8127 /* Switch to the right section. */
8129 subseg
= now_subseg
;
8132 default: /* unused default case avoids warnings. */
8134 newname
= RDATA_SECTION_NAME
;
8135 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8136 || mips_pic
== EMBEDDED_PIC
)
8140 if (mips_pic
== EMBEDDED_PIC
)
8143 newname
= RDATA_SECTION_NAME
;
8146 assert (!USE_GLOBAL_POINTER_OPT
8147 || g_switch_value
>= 4);
8151 new_seg
= subseg_new (newname
, (subsegT
) 0);
8152 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8153 bfd_set_section_flags (stdoutput
, new_seg
,
8158 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8159 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8160 && strcmp (TARGET_OS
, "elf") != 0)
8161 record_alignment (new_seg
, 4);
8163 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8165 as_bad (_("Can't use floating point insn in this section"));
8167 /* Set the argument to the current address in the
8169 offset_expr
.X_op
= O_symbol
;
8170 offset_expr
.X_add_symbol
=
8171 symbol_new ("L0\001", now_seg
,
8172 (valueT
) frag_now_fix (), frag_now
);
8173 offset_expr
.X_add_number
= 0;
8175 /* Put the floating point number into the section. */
8176 p
= frag_more ((int) length
);
8177 memcpy (p
, temp
, length
);
8179 /* Switch back to the original section. */
8180 subseg_set (seg
, subseg
);
8185 case 'i': /* 16 bit unsigned immediate */
8186 case 'j': /* 16 bit signed immediate */
8187 *imm_reloc
= BFD_RELOC_LO16
;
8188 c
= my_getSmallExpression (&imm_expr
, s
);
8193 if (imm_expr
.X_op
== O_constant
)
8194 imm_expr
.X_add_number
=
8195 (imm_expr
.X_add_number
>> 16) & 0xffff;
8197 else if (c
== S_EX_HIGHEST
)
8198 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8199 else if (c
== S_EX_HIGHER
)
8200 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8201 else if (c
== S_EX_GP_REL
)
8203 /* This occurs in NewABI only. */
8204 c
= my_getSmallExpression (&imm_expr
, s
);
8206 as_bad (_("bad composition of relocations"));
8209 c
= my_getSmallExpression (&imm_expr
, s
);
8211 as_bad (_("bad composition of relocations"));
8214 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8215 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8216 imm_reloc
[2] = BFD_RELOC_LO16
;
8221 else if (c
== S_EX_HI
)
8223 *imm_reloc
= BFD_RELOC_HI16_S
;
8224 imm_unmatched_hi
= true;
8227 *imm_reloc
= BFD_RELOC_HI16
;
8229 else if (imm_expr
.X_op
== O_constant
)
8230 imm_expr
.X_add_number
&= 0xffff;
8234 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8235 || ((imm_expr
.X_add_number
< 0
8236 || imm_expr
.X_add_number
>= 0x10000)
8237 && imm_expr
.X_op
== O_constant
))
8239 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8240 !strcmp (insn
->name
, insn
[1].name
))
8242 if (imm_expr
.X_op
== O_constant
8243 || imm_expr
.X_op
== O_big
)
8244 as_bad (_("16 bit expression not in range 0..65535"));
8252 /* The upper bound should be 0x8000, but
8253 unfortunately the MIPS assembler accepts numbers
8254 from 0x8000 to 0xffff and sign extends them, and
8255 we want to be compatible. We only permit this
8256 extended range for an instruction which does not
8257 provide any further alternates, since those
8258 alternates may handle other cases. People should
8259 use the numbers they mean, rather than relying on
8260 a mysterious sign extension. */
8261 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8262 strcmp (insn
->name
, insn
[1].name
) == 0);
8267 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8268 || ((imm_expr
.X_add_number
< -0x8000
8269 || imm_expr
.X_add_number
>= max
)
8270 && imm_expr
.X_op
== O_constant
)
8272 && imm_expr
.X_add_number
< 0
8274 && imm_expr
.X_unsigned
8275 && sizeof (imm_expr
.X_add_number
) <= 4))
8279 if (imm_expr
.X_op
== O_constant
8280 || imm_expr
.X_op
== O_big
)
8281 as_bad (_("16 bit expression not in range -32768..32767"));
8287 case 'o': /* 16 bit offset */
8288 c
= my_getSmallExpression (&offset_expr
, s
);
8290 /* If this value won't fit into a 16 bit offset, then go
8291 find a macro that will generate the 32 bit offset
8294 && (offset_expr
.X_op
!= O_constant
8295 || offset_expr
.X_add_number
>= 0x8000
8296 || offset_expr
.X_add_number
< -0x8000))
8301 if (offset_expr
.X_op
!= O_constant
)
8303 offset_expr
.X_add_number
=
8304 (offset_expr
.X_add_number
>> 16) & 0xffff;
8306 *offset_reloc
= BFD_RELOC_LO16
;
8310 case 'p': /* pc relative offset */
8311 if (mips_pic
== EMBEDDED_PIC
)
8312 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8314 *offset_reloc
= BFD_RELOC_16_PCREL
;
8315 my_getExpression (&offset_expr
, s
);
8319 case 'u': /* upper 16 bits */
8320 c
= my_getSmallExpression (&imm_expr
, s
);
8321 *imm_reloc
= BFD_RELOC_LO16
;
8326 if (imm_expr
.X_op
== O_constant
)
8327 imm_expr
.X_add_number
=
8328 (imm_expr
.X_add_number
>> 16) & 0xffff;
8330 else if (c
== S_EX_HIGHEST
)
8331 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8332 else if (c
== S_EX_HI
)
8334 *imm_reloc
= BFD_RELOC_HI16_S
;
8335 imm_unmatched_hi
= true;
8337 else if (c
== S_EX_GP_REL
)
8339 /* This occurs in NewABI only. */
8340 c
= my_getSmallExpression (&imm_expr
, s
);
8342 as_bad (_("bad composition of relocations"));
8345 c
= my_getSmallExpression (&imm_expr
, s
);
8347 as_bad (_("bad composition of relocations"));
8350 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8351 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8352 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8358 *imm_reloc
= BFD_RELOC_HI16
;
8360 else if (imm_expr
.X_op
== O_constant
)
8361 imm_expr
.X_add_number
&= 0xffff;
8363 if (imm_expr
.X_op
== O_constant
8364 && (imm_expr
.X_add_number
< 0
8365 || imm_expr
.X_add_number
>= 0x10000))
8366 as_bad (_("lui expression not in range 0..65535"));
8370 case 'a': /* 26 bit address */
8371 my_getExpression (&offset_expr
, s
);
8373 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8376 case 'N': /* 3 bit branch condition code */
8377 case 'M': /* 3 bit compare condition code */
8378 if (strncmp (s
, "$fcc", 4) != 0)
8388 while (ISDIGIT (*s
));
8390 as_bad (_("invalid condition code register $fcc%d"), regno
);
8392 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8394 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8398 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8409 while (ISDIGIT (*s
));
8412 c
= 8; /* Invalid sel value. */
8415 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8416 ip
->insn_opcode
|= c
;
8420 as_bad (_("bad char = '%c'\n"), *args
);
8425 /* Args don't match. */
8426 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8427 !strcmp (insn
->name
, insn
[1].name
))
8431 insn_error
= _("illegal operands");
8436 insn_error
= _("illegal operands");
8441 /* This routine assembles an instruction into its binary format when
8442 assembling for the mips16. As a side effect, it sets one of the
8443 global variables imm_reloc or offset_reloc to the type of
8444 relocation to do if one of the operands is an address expression.
8445 It also sets mips16_small and mips16_ext if the user explicitly
8446 requested a small or extended instruction. */
8451 struct mips_cl_insn
*ip
;
8455 struct mips_opcode
*insn
;
8458 unsigned int lastregno
= 0;
8463 mips16_small
= false;
8466 for (s
= str
; ISLOWER (*s
); ++s
)
8478 if (s
[1] == 't' && s
[2] == ' ')
8481 mips16_small
= true;
8485 else if (s
[1] == 'e' && s
[2] == ' ')
8494 insn_error
= _("unknown opcode");
8498 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8499 mips16_small
= true;
8501 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8503 insn_error
= _("unrecognized opcode");
8510 assert (strcmp (insn
->name
, str
) == 0);
8513 ip
->insn_opcode
= insn
->match
;
8514 ip
->use_extend
= false;
8515 imm_expr
.X_op
= O_absent
;
8516 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8517 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8518 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8519 offset_expr
.X_op
= O_absent
;
8520 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8521 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8522 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8523 for (args
= insn
->args
; 1; ++args
)
8530 /* In this switch statement we call break if we did not find
8531 a match, continue if we did find a match, or return if we
8540 /* Stuff the immediate value in now, if we can. */
8541 if (imm_expr
.X_op
== O_constant
8542 && *imm_reloc
> BFD_RELOC_UNUSED
8543 && insn
->pinfo
!= INSN_MACRO
)
8545 mips16_immed ((char *) NULL
, 0,
8546 *imm_reloc
- BFD_RELOC_UNUSED
,
8547 imm_expr
.X_add_number
, true, mips16_small
,
8548 mips16_ext
, &ip
->insn_opcode
,
8549 &ip
->use_extend
, &ip
->extend
);
8550 imm_expr
.X_op
= O_absent
;
8551 *imm_reloc
= BFD_RELOC_UNUSED
;
8565 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8568 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8584 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8586 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8613 while (ISDIGIT (*s
));
8616 as_bad (_("invalid register number (%d)"), regno
);
8622 if (s
[1] == 'f' && s
[2] == 'p')
8627 else if (s
[1] == 's' && s
[2] == 'p')
8632 else if (s
[1] == 'g' && s
[2] == 'p')
8637 else if (s
[1] == 'a' && s
[2] == 't')
8642 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8647 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8660 if (c
== 'v' || c
== 'w')
8662 regno
= mips16_to_32_reg_map
[lastregno
];
8676 regno
= mips32_to_16_reg_map
[regno
];
8681 regno
= ILLEGAL_REG
;
8686 regno
= ILLEGAL_REG
;
8691 regno
= ILLEGAL_REG
;
8696 if (regno
== AT
&& ! mips_opts
.noat
)
8697 as_warn (_("used $at without \".set noat\""));
8704 if (regno
== ILLEGAL_REG
)
8711 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8715 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8718 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8721 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8727 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8730 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8731 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8741 if (strncmp (s
, "$pc", 3) == 0)
8765 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8767 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8768 and generate the appropriate reloc. If the text
8769 inside %gprel is not a symbol name with an
8770 optional offset, then we generate a normal reloc
8771 and will probably fail later. */
8772 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8773 if (imm_expr
.X_op
== O_symbol
)
8776 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8778 ip
->use_extend
= true;
8785 /* Just pick up a normal expression. */
8786 my_getExpression (&imm_expr
, s
);
8789 if (imm_expr
.X_op
== O_register
)
8791 /* What we thought was an expression turned out to
8794 if (s
[0] == '(' && args
[1] == '(')
8796 /* It looks like the expression was omitted
8797 before a register indirection, which means
8798 that the expression is implicitly zero. We
8799 still set up imm_expr, so that we handle
8800 explicit extensions correctly. */
8801 imm_expr
.X_op
= O_constant
;
8802 imm_expr
.X_add_number
= 0;
8803 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8810 /* We need to relax this instruction. */
8811 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8820 /* We use offset_reloc rather than imm_reloc for the PC
8821 relative operands. This lets macros with both
8822 immediate and address operands work correctly. */
8823 my_getExpression (&offset_expr
, s
);
8825 if (offset_expr
.X_op
== O_register
)
8828 /* We need to relax this instruction. */
8829 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8833 case '6': /* break code */
8834 my_getExpression (&imm_expr
, s
);
8835 check_absolute_expr (ip
, &imm_expr
);
8836 if ((unsigned long) imm_expr
.X_add_number
> 63)
8838 as_warn (_("Invalid value for `%s' (%lu)"),
8840 (unsigned long) imm_expr
.X_add_number
);
8841 imm_expr
.X_add_number
&= 0x3f;
8843 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8844 imm_expr
.X_op
= O_absent
;
8848 case 'a': /* 26 bit address */
8849 my_getExpression (&offset_expr
, s
);
8851 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8852 ip
->insn_opcode
<<= 16;
8855 case 'l': /* register list for entry macro */
8856 case 'L': /* register list for exit macro */
8866 int freg
, reg1
, reg2
;
8868 while (*s
== ' ' || *s
== ',')
8872 as_bad (_("can't parse register list"));
8884 while (ISDIGIT (*s
))
8906 as_bad (_("invalid register list"));
8911 while (ISDIGIT (*s
))
8918 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8923 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8928 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8929 mask
|= (reg2
- 3) << 3;
8930 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8931 mask
|= (reg2
- 15) << 1;
8932 else if (reg1
== 31 && reg2
== 31)
8936 as_bad (_("invalid register list"));
8940 /* The mask is filled in in the opcode table for the
8941 benefit of the disassembler. We remove it before
8942 applying the actual mask. */
8943 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8944 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8948 case 'e': /* extend code */
8949 my_getExpression (&imm_expr
, s
);
8950 check_absolute_expr (ip
, &imm_expr
);
8951 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8953 as_warn (_("Invalid value for `%s' (%lu)"),
8955 (unsigned long) imm_expr
.X_add_number
);
8956 imm_expr
.X_add_number
&= 0x7ff;
8958 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8959 imm_expr
.X_op
= O_absent
;
8969 /* Args don't match. */
8970 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8971 strcmp (insn
->name
, insn
[1].name
) == 0)
8978 insn_error
= _("illegal operands");
8984 /* This structure holds information we know about a mips16 immediate
8987 struct mips16_immed_operand
8989 /* The type code used in the argument string in the opcode table. */
8991 /* The number of bits in the short form of the opcode. */
8993 /* The number of bits in the extended form of the opcode. */
8995 /* The amount by which the short form is shifted when it is used;
8996 for example, the sw instruction has a shift count of 2. */
8998 /* The amount by which the short form is shifted when it is stored
8999 into the instruction code. */
9001 /* Non-zero if the short form is unsigned. */
9003 /* Non-zero if the extended form is unsigned. */
9005 /* Non-zero if the value is PC relative. */
9009 /* The mips16 immediate operand types. */
9011 static const struct mips16_immed_operand mips16_immed_operands
[] =
9013 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9014 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9015 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9016 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9017 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9018 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9019 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9020 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9021 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9022 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9023 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9024 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9025 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9026 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9027 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9028 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9029 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9030 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9031 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9032 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9033 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9036 #define MIPS16_NUM_IMMED \
9037 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9039 /* Handle a mips16 instruction with an immediate value. This or's the
9040 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9041 whether an extended value is needed; if one is needed, it sets
9042 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9043 If SMALL is true, an unextended opcode was explicitly requested.
9044 If EXT is true, an extended opcode was explicitly requested. If
9045 WARN is true, warn if EXT does not match reality. */
9048 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9057 unsigned long *insn
;
9058 boolean
*use_extend
;
9059 unsigned short *extend
;
9061 register const struct mips16_immed_operand
*op
;
9062 int mintiny
, maxtiny
;
9065 op
= mips16_immed_operands
;
9066 while (op
->type
!= type
)
9069 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9074 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9077 maxtiny
= 1 << op
->nbits
;
9082 maxtiny
= (1 << op
->nbits
) - 1;
9087 mintiny
= - (1 << (op
->nbits
- 1));
9088 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9091 /* Branch offsets have an implicit 0 in the lowest bit. */
9092 if (type
== 'p' || type
== 'q')
9095 if ((val
& ((1 << op
->shift
) - 1)) != 0
9096 || val
< (mintiny
<< op
->shift
)
9097 || val
> (maxtiny
<< op
->shift
))
9102 if (warn
&& ext
&& ! needext
)
9103 as_warn_where (file
, line
,
9104 _("extended operand requested but not required"));
9105 if (small
&& needext
)
9106 as_bad_where (file
, line
, _("invalid unextended operand value"));
9108 if (small
|| (! ext
&& ! needext
))
9112 *use_extend
= false;
9113 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9114 insnval
<<= op
->op_shift
;
9119 long minext
, maxext
;
9125 maxext
= (1 << op
->extbits
) - 1;
9129 minext
= - (1 << (op
->extbits
- 1));
9130 maxext
= (1 << (op
->extbits
- 1)) - 1;
9132 if (val
< minext
|| val
> maxext
)
9133 as_bad_where (file
, line
,
9134 _("operand value out of range for instruction"));
9137 if (op
->extbits
== 16)
9139 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9142 else if (op
->extbits
== 15)
9144 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9149 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9153 *extend
= (unsigned short) extval
;
9158 static struct percent_op_match
9161 const enum small_ex_type type
;
9165 {"%half", S_EX_HALF
},
9170 {"%gp_rel", S_EX_GP_REL
},
9172 {"%call16", S_EX_CALL16
},
9173 {"%got_disp", S_EX_GOT_DISP
},
9174 {"%got_page", S_EX_GOT_PAGE
},
9175 {"%got_ofst", S_EX_GOT_OFST
},
9176 {"%got_hi", S_EX_GOT_HI
},
9177 {"%got_lo", S_EX_GOT_LO
},
9179 {"%higher", S_EX_HIGHER
},
9180 {"%highest", S_EX_HIGHEST
},
9181 {"%call_hi", S_EX_CALL_HI
},
9182 {"%call_lo", S_EX_CALL_LO
}
9186 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9187 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9188 can be nested, this is handled by blanking the innermost, parsing the
9189 rest by subsequent calls. */
9192 my_getSmallParser (str
, len
, nestlevel
)
9197 int type
= S_EX_NONE
;
9200 *str
+= strspn (*str
, " \t");
9203 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9206 /* Check for base register. */
9210 && (e
= b
+ strcspn (b
, ") \t"))
9211 && e
- b
> 1 && e
- b
< 4)
9214 && ((b
[1] == 'f' && b
[2] == 'p')
9215 || (b
[1] == 's' && b
[2] == 'p')
9216 || (b
[1] == 'g' && b
[2] == 'p')
9217 || (b
[1] == 'a' && b
[2] == 't')
9219 && ISDIGIT (b
[2]))))
9220 || (ISDIGIT (b
[1])))
9222 *len
= strcspn (*str
, ")") + 1;
9223 return S_EX_REGISTER
;
9227 else if (b
[0] == '%')
9233 /* Some other expression in the braces. */
9234 *len
= strcspn (*str
, ")") + 1;
9236 /* Check for percent_op. */
9237 else if (*str
[0] == '%')
9246 while (ISALPHA (*tmp
) || *tmp
== '_')
9248 *tmp
= TOLOWER (*tmp
);
9251 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9253 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9257 type
= percent_op
[i
].type
;
9259 /* Only %hi and %lo are allowed for OldABI. */
9260 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9263 *len
= strlen (percent_op
[i
].str
);
9270 /* Any other expression. */
9275 my_getSmallExpression (ep
, str
)
9279 static char *oldstr
= NULL
;
9285 /* Don't update oldstr if the last call had nested percent_op's. */
9292 c
= my_getSmallParser (&str
, &len
, &nest_level
);
9293 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9296 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9298 /* A percent_op was encountered. */
9301 /* Don't try to get an expression if it is already blanked out. */
9302 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9306 save
= *(str
+ len
);
9307 *(str
+ len
) = '\0';
9308 my_getExpression (ep
, str
);
9309 *(str
+ len
) = save
;
9313 /* blank out including the % sign. */
9314 char *p
= strrchr (oldstr
, '%');
9315 memset (p
, ' ', str
- p
+ len
);
9320 expr_end
= strchr (str
, ')') + 1;
9324 else if (c
== S_EX_NONE
)
9326 my_getExpression (ep
, str
);
9328 else if (c
== S_EX_REGISTER
)
9330 ep
->X_op
= O_constant
;
9332 ep
->X_add_symbol
= NULL
;
9333 ep
->X_op_symbol
= NULL
;
9334 ep
->X_add_number
= 0;
9338 as_fatal(_("internal error"));
9341 if (nest_level
<= 1)
9348 my_getExpression (ep
, str
)
9355 save_in
= input_line_pointer
;
9356 input_line_pointer
= str
;
9358 expr_end
= input_line_pointer
;
9359 input_line_pointer
= save_in
;
9361 /* If we are in mips16 mode, and this is an expression based on `.',
9362 then we bump the value of the symbol by 1 since that is how other
9363 text symbols are handled. We don't bother to handle complex
9364 expressions, just `.' plus or minus a constant. */
9365 if (mips_opts
.mips16
9366 && ep
->X_op
== O_symbol
9367 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9368 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9369 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9370 && symbol_constant_p (ep
->X_add_symbol
)
9371 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9372 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9375 /* Turn a string in input_line_pointer into a floating point constant
9376 of type TYPE, and store the appropriate bytes in *LITP. The number
9377 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9378 returned, or NULL on OK. */
9381 md_atof (type
, litP
, sizeP
)
9387 LITTLENUM_TYPE words
[4];
9403 return _("bad call to md_atof");
9406 t
= atof_ieee (input_line_pointer
, type
, words
);
9408 input_line_pointer
= t
;
9412 if (! target_big_endian
)
9414 for (i
= prec
- 1; i
>= 0; i
--)
9416 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9422 for (i
= 0; i
< prec
; i
++)
9424 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9433 md_number_to_chars (buf
, val
, n
)
9438 if (target_big_endian
)
9439 number_to_chars_bigendian (buf
, val
, n
);
9441 number_to_chars_littleendian (buf
, val
, n
);
9444 static int support_64bit_objects(void)
9446 const char **list
, **l
;
9448 list
= bfd_target_list ();
9449 for (l
= list
; *l
!= NULL
; l
++)
9451 /* This is traditional mips */
9452 if (strcmp (*l
, "elf64-tradbigmips") == 0
9453 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9455 if (strcmp (*l
, "elf64-bigmips") == 0
9456 || strcmp (*l
, "elf64-littlemips") == 0)
9460 return (*l
!= NULL
);
9463 CONST
char *md_shortopts
= "nO::g::G:";
9465 struct option md_longopts
[] =
9467 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9468 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9469 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9470 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9471 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9472 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9473 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9474 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9475 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9476 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9477 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9478 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9479 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9480 #define OPTION_TRAP (OPTION_MD_BASE + 7)
9481 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9482 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9483 #define OPTION_BREAK (OPTION_MD_BASE + 8)
9484 {"break", no_argument
, NULL
, OPTION_BREAK
},
9485 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9486 #define OPTION_EB (OPTION_MD_BASE + 9)
9487 {"EB", no_argument
, NULL
, OPTION_EB
},
9488 #define OPTION_EL (OPTION_MD_BASE + 10)
9489 {"EL", no_argument
, NULL
, OPTION_EL
},
9490 #define OPTION_M4650 (OPTION_MD_BASE + 11)
9491 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9492 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
9493 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9494 #define OPTION_M4010 (OPTION_MD_BASE + 13)
9495 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9496 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
9497 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9498 #define OPTION_M4100 (OPTION_MD_BASE + 15)
9499 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9500 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
9501 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9502 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
9503 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9504 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
9505 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9506 #define OPTION_M3900 (OPTION_MD_BASE + 19)
9507 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9508 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
9509 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9510 #define OPTION_MABI (OPTION_MD_BASE + 21)
9511 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9512 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
9513 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9514 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
9515 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9516 #define OPTION_GP32 (OPTION_MD_BASE + 24)
9517 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9518 #define OPTION_GP64 (OPTION_MD_BASE + 25)
9519 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9520 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
9521 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9522 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
9523 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9524 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
9525 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9526 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
9527 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9528 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
9529 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9530 #define OPTION_MARCH (OPTION_MD_BASE + 31)
9531 {"march", required_argument
, NULL
, OPTION_MARCH
},
9532 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
9533 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9534 #define OPTION_FP32 (OPTION_MD_BASE + 33)
9535 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9537 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9538 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9539 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9540 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9541 #define OPTION_32 (OPTION_ELF_BASE + 3)
9542 #define OPTION_N32 (OPTION_ELF_BASE + 4)
9543 #define OPTION_64 (OPTION_ELF_BASE + 5)
9544 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9545 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9546 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9547 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9548 {"32", no_argument
, NULL
, OPTION_32
},
9549 {"n32", no_argument
, NULL
, OPTION_N32
},
9550 {"64", no_argument
, NULL
, OPTION_64
},
9553 {NULL
, no_argument
, NULL
, 0}
9555 size_t md_longopts_size
= sizeof (md_longopts
);
9558 md_parse_option (c
, arg
)
9564 case OPTION_CONSTRUCT_FLOATS
:
9565 mips_disable_float_construction
= 0;
9568 case OPTION_NO_CONSTRUCT_FLOATS
:
9569 mips_disable_float_construction
= 1;
9581 target_big_endian
= 1;
9585 target_big_endian
= 0;
9593 if (arg
&& arg
[1] == '0')
9603 mips_debug
= atoi (arg
);
9604 /* When the MIPS assembler sees -g or -g2, it does not do
9605 optimizations which limit full symbolic debugging. We take
9606 that to be equivalent to -O0. */
9607 if (mips_debug
== 2)
9612 mips_opts
.isa
= ISA_MIPS1
;
9616 mips_opts
.isa
= ISA_MIPS2
;
9620 mips_opts
.isa
= ISA_MIPS3
;
9624 mips_opts
.isa
= ISA_MIPS4
;
9628 mips_opts
.isa
= ISA_MIPS5
;
9632 mips_opts
.isa
= ISA_MIPS32
;
9636 mips_opts
.isa
= ISA_MIPS64
;
9643 int cpu
= CPU_UNKNOWN
;
9645 /* Identify the processor type. */
9646 if (strcasecmp (arg
, "default") != 0)
9648 const struct mips_cpu_info
*ci
;
9650 ci
= mips_cpu_info_from_name (arg
);
9651 if (ci
== NULL
|| ci
->is_isa
)
9656 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9659 as_fatal (_("invalid architecture -march=%s"), arg
);
9662 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9673 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9674 as_warn(_("A different -mtune= was already specified, is now "
9679 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9680 as_warn(_("A different -march= was already specified, is now "
9685 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9686 as_warn(_("A different -mcpu= was already specified, is now "
9694 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9695 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9696 as_warn(_("A different -march= or -mtune= was already specified, "
9698 mips_arch
= CPU_R4650
;
9699 mips_tune
= CPU_R4650
;
9702 case OPTION_NO_M4650
:
9706 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9707 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9708 as_warn(_("A different -march= or -mtune= was already specified, "
9710 mips_arch
= CPU_R4010
;
9711 mips_tune
= CPU_R4010
;
9714 case OPTION_NO_M4010
:
9718 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9719 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9720 as_warn(_("A different -march= or -mtune= was already specified, "
9722 mips_arch
= CPU_VR4100
;
9723 mips_tune
= CPU_VR4100
;
9726 case OPTION_NO_M4100
:
9730 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9731 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9732 as_warn(_("A different -march= or -mtune= was already specified, "
9734 mips_arch
= CPU_R3900
;
9735 mips_tune
= CPU_R3900
;
9738 case OPTION_NO_M3900
:
9742 mips_opts
.mips16
= 1;
9743 mips_no_prev_insn (false);
9746 case OPTION_NO_MIPS16
:
9747 mips_opts
.mips16
= 0;
9748 mips_no_prev_insn (false);
9751 case OPTION_MEMBEDDED_PIC
:
9752 mips_pic
= EMBEDDED_PIC
;
9753 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9755 as_bad (_("-G may not be used with embedded PIC code"));
9758 g_switch_value
= 0x7fffffff;
9762 /* When generating ELF code, we permit -KPIC and -call_shared to
9763 select SVR4_PIC, and -non_shared to select no PIC. This is
9764 intended to be compatible with Irix 5. */
9765 case OPTION_CALL_SHARED
:
9766 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9768 as_bad (_("-call_shared is supported only for ELF format"));
9771 mips_pic
= SVR4_PIC
;
9772 if (g_switch_seen
&& g_switch_value
!= 0)
9774 as_bad (_("-G may not be used with SVR4 PIC code"));
9780 case OPTION_NON_SHARED
:
9781 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9783 as_bad (_("-non_shared is supported only for ELF format"));
9789 /* The -xgot option tells the assembler to use 32 offsets when
9790 accessing the got in SVR4_PIC mode. It is for Irix
9795 #endif /* OBJ_ELF */
9798 if (! USE_GLOBAL_POINTER_OPT
)
9800 as_bad (_("-G is not supported for this configuration"));
9803 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9805 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9809 g_switch_value
= atoi (arg
);
9814 /* The -32 and -64 options tell the assembler to output the 32
9815 bit or the 64 bit MIPS ELF format. */
9817 mips_opts
.abi
= O32_ABI
;
9821 mips_opts
.abi
= N32_ABI
;
9825 mips_opts
.abi
= N64_ABI
;
9826 if (! support_64bit_objects())
9827 as_fatal (_("No compiled in support for 64 bit object file format"));
9832 if (mips_opts
.abi
!= O32_ABI
)
9833 mips_opts
.abi
= NO_ABI
;
9838 if (mips_opts
.abi
== O32_ABI
)
9839 mips_opts
.abi
= NO_ABI
;
9844 if (mips_opts
.abi
!= O32_ABI
)
9845 mips_opts
.abi
= NO_ABI
;
9849 if (strcmp (arg
, "32") == 0)
9850 mips_opts
.abi
= O32_ABI
;
9851 else if (strcmp (arg
, "o64") == 0)
9852 mips_opts
.abi
= O64_ABI
;
9853 else if (strcmp (arg
, "n32") == 0)
9854 mips_opts
.abi
= N32_ABI
;
9855 else if (strcmp (arg
, "64") == 0)
9857 mips_opts
.abi
= N64_ABI
;
9858 if (! support_64bit_objects())
9859 as_fatal (_("No compiled in support for 64 bit object file "
9862 else if (strcmp (arg
, "eabi") == 0)
9863 mips_opts
.abi
= EABI_ABI
;
9865 mips_opts
.abi
= NO_ABI
;
9867 #endif /* OBJ_ELF */
9869 case OPTION_M7000_HILO_FIX
:
9870 mips_7000_hilo_fix
= true;
9873 case OPTION_NO_M7000_HILO_FIX
:
9874 mips_7000_hilo_fix
= false;
9885 show (stream
, string
, col_p
, first_p
)
9893 fprintf (stream
, "%24s", "");
9898 fprintf (stream
, ", ");
9902 if (*col_p
+ strlen (string
) > 72)
9904 fprintf (stream
, "\n%24s", "");
9908 fprintf (stream
, "%s", string
);
9909 *col_p
+= strlen (string
);
9915 md_show_usage (stream
)
9920 fprintf (stream
, _("\
9922 -membedded-pic generate embedded position independent code\n\
9923 -EB generate big endian output\n\
9924 -EL generate little endian output\n\
9925 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9926 -G NUM allow referencing objects up to NUM bytes\n\
9927 implicitly with the gp register [default 8]\n"));
9928 fprintf (stream
, _("\
9929 -mips1 generate MIPS ISA I instructions\n\
9930 -mips2 generate MIPS ISA II instructions\n\
9931 -mips3 generate MIPS ISA III instructions\n\
9932 -mips4 generate MIPS ISA IV instructions\n\
9933 -mips5 generate MIPS ISA V instructions\n\
9934 -mips32 generate MIPS32 ISA instructions\n\
9935 -mips64 generate MIPS64 ISA instructions\n\
9936 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9940 show (stream
, "2000", &column
, &first
);
9941 show (stream
, "3000", &column
, &first
);
9942 show (stream
, "3900", &column
, &first
);
9943 show (stream
, "4000", &column
, &first
);
9944 show (stream
, "4010", &column
, &first
);
9945 show (stream
, "4100", &column
, &first
);
9946 show (stream
, "4111", &column
, &first
);
9947 show (stream
, "4300", &column
, &first
);
9948 show (stream
, "4400", &column
, &first
);
9949 show (stream
, "4600", &column
, &first
);
9950 show (stream
, "4650", &column
, &first
);
9951 show (stream
, "5000", &column
, &first
);
9952 show (stream
, "5200", &column
, &first
);
9953 show (stream
, "5230", &column
, &first
);
9954 show (stream
, "5231", &column
, &first
);
9955 show (stream
, "5261", &column
, &first
);
9956 show (stream
, "5721", &column
, &first
);
9957 show (stream
, "6000", &column
, &first
);
9958 show (stream
, "8000", &column
, &first
);
9959 show (stream
, "10000", &column
, &first
);
9960 show (stream
, "12000", &column
, &first
);
9961 show (stream
, "sb1", &column
, &first
);
9962 fputc ('\n', stream
);
9964 fprintf (stream
, _("\
9965 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9966 -no-mCPU don't generate code specific to CPU.\n\
9967 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9971 show (stream
, "3900", &column
, &first
);
9972 show (stream
, "4010", &column
, &first
);
9973 show (stream
, "4100", &column
, &first
);
9974 show (stream
, "4650", &column
, &first
);
9975 fputc ('\n', stream
);
9977 fprintf (stream
, _("\
9978 -mips16 generate mips16 instructions\n\
9979 -no-mips16 do not generate mips16 instructions\n"));
9980 fprintf (stream
, _("\
9981 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9982 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9983 -O0 remove unneeded NOPs, do not swap branches\n\
9984 -O remove unneeded NOPs and swap branches\n\
9985 -n warn about NOPs generated from macros\n\
9986 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9987 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9988 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9990 fprintf (stream
, _("\
9991 -KPIC, -call_shared generate SVR4 position independent code\n\
9992 -non_shared do not generate position independent code\n\
9993 -xgot assume a 32 bit GOT\n\
9994 -32 create o32 ABI object file (default)\n\
9995 -n32 create n32 ABI object file\n\
9996 -64 create 64 ABI object file\n"));
10001 mips_init_after_args ()
10003 /* initialize opcodes */
10004 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10005 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10009 md_pcrel_from (fixP
)
10012 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10013 && fixP
->fx_addsy
!= (symbolS
*) NULL
10014 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10016 /* This makes a branch to an undefined symbol be a branch to the
10017 current location. */
10018 if (mips_pic
== EMBEDDED_PIC
)
10024 /* return the address of the delay slot */
10025 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10028 /* This is called before the symbol table is processed. In order to
10029 work with gcc when using mips-tfile, we must keep all local labels.
10030 However, in other cases, we want to discard them. If we were
10031 called with -g, but we didn't see any debugging information, it may
10032 mean that gcc is smuggling debugging information through to
10033 mips-tfile, in which case we must generate all local labels. */
10036 mips_frob_file_before_adjust ()
10038 #ifndef NO_ECOFF_DEBUGGING
10039 if (ECOFF_DEBUGGING
10041 && ! ecoff_debugging_seen
)
10042 flag_keep_locals
= 1;
10046 /* Sort any unmatched HI16_S relocs so that they immediately precede
10047 the corresponding LO reloc. This is called before md_apply_fix and
10048 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10049 explicit use of the %hi modifier. */
10054 struct mips_hi_fixup
*l
;
10056 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10058 segment_info_type
*seginfo
;
10061 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10063 /* Check quickly whether the next fixup happens to be a matching
10065 if (l
->fixp
->fx_next
!= NULL
10066 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10067 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10068 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10071 /* Look through the fixups for this segment for a matching %lo.
10072 When we find one, move the %hi just in front of it. We do
10073 this in two passes. In the first pass, we try to find a
10074 unique %lo. In the second pass, we permit multiple %hi
10075 relocs for a single %lo (this is a GNU extension). */
10076 seginfo
= seg_info (l
->seg
);
10077 for (pass
= 0; pass
< 2; pass
++)
10082 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10084 /* Check whether this is a %lo fixup which matches l->fixp. */
10085 if (f
->fx_r_type
== BFD_RELOC_LO16
10086 && f
->fx_addsy
== l
->fixp
->fx_addsy
10087 && f
->fx_offset
== l
->fixp
->fx_offset
10090 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10091 || prev
->fx_addsy
!= f
->fx_addsy
10092 || prev
->fx_offset
!= f
->fx_offset
))
10096 /* Move l->fixp before f. */
10097 for (pf
= &seginfo
->fix_root
;
10099 pf
= &(*pf
)->fx_next
)
10100 assert (*pf
!= NULL
);
10102 *pf
= l
->fixp
->fx_next
;
10104 l
->fixp
->fx_next
= f
;
10106 seginfo
->fix_root
= l
->fixp
;
10108 prev
->fx_next
= l
->fixp
;
10119 #if 0 /* GCC code motion plus incomplete dead code elimination
10120 can leave a %hi without a %lo. */
10122 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10123 _("Unmatched %%hi reloc"));
10129 /* When generating embedded PIC code we need to use a special
10130 relocation to represent the difference of two symbols in the .text
10131 section (switch tables use a difference of this sort). See
10132 include/coff/mips.h for details. This macro checks whether this
10133 fixup requires the special reloc. */
10134 #define SWITCH_TABLE(fixp) \
10135 ((fixp)->fx_r_type == BFD_RELOC_32 \
10136 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10137 && (fixp)->fx_addsy != NULL \
10138 && (fixp)->fx_subsy != NULL \
10139 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10140 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10142 /* When generating embedded PIC code we must keep all PC relative
10143 relocations, in case the linker has to relax a call. We also need
10144 to keep relocations for switch table entries.
10146 We may have combined relocations without symbols in the N32/N64 ABI.
10147 We have to prevent gas from dropping them. */
10150 mips_force_relocation (fixp
)
10153 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10154 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10158 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10159 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10160 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10161 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10164 return (mips_pic
== EMBEDDED_PIC
10166 || SWITCH_TABLE (fixp
)
10167 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10168 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10171 /* Apply a fixup to the object file. */
10174 md_apply_fix (fixP
, valueP
)
10178 unsigned char *buf
;
10182 assert (fixP
->fx_size
== 4
10183 || fixP
->fx_r_type
== BFD_RELOC_16
10184 || fixP
->fx_r_type
== BFD_RELOC_32
10185 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10186 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10187 || fixP
->fx_r_type
== BFD_RELOC_LO16
10188 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10189 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10190 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10191 || fixP
->fx_r_type
== BFD_RELOC_64
10192 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10193 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10194 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10195 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10196 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10197 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10198 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10199 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10200 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10204 /* If we aren't adjusting this fixup to be against the section
10205 symbol, we need to adjust the value. */
10207 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10209 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10210 || ((S_IS_WEAK (fixP
->fx_addsy
)
10211 || S_IS_EXTERN (fixP
->fx_addsy
))
10212 && !S_IS_COMMON (fixP
->fx_addsy
))
10213 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10214 && (((bfd_get_section_flags (stdoutput
,
10215 S_GET_SEGMENT (fixP
->fx_addsy
))
10216 & SEC_LINK_ONCE
) != 0)
10217 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10219 sizeof (".gnu.linkonce") - 1))))
10222 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10225 && ! fixP
->fx_pcrel
10226 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
10228 /* In this case, the bfd_install_relocation routine will
10229 incorrectly add the symbol value back in. We just want
10230 the addend to appear in the object file. */
10233 /* Make sure the addend is still non-zero. If it became zero
10234 after the last operation, set it to a spurious value and
10235 subtract the same value from the object file's contents. */
10240 /* The in-place addends for LO16 relocations are signed;
10241 leave the matching HI16 in-place addends as zero. */
10242 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10244 reloc_howto_type
*howto
;
10245 bfd_vma contents
, mask
, field
;
10247 howto
= bfd_reloc_type_lookup (stdoutput
,
10250 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10253 target_big_endian
);
10255 /* MASK has bits set where the relocation should go.
10256 FIELD is -value, shifted into the appropriate place
10257 for this relocation. */
10258 mask
= 1 << (howto
->bitsize
- 1);
10259 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10260 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10262 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10263 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10265 target_big_endian
);
10271 /* This code was generated using trial and error and so is
10272 fragile and not trustworthy. If you change it, you should
10273 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10274 they still pass. */
10275 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10277 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10279 /* BFD's REL handling, for MIPS, is _very_ weird.
10280 This gives the right results, but it can't possibly
10281 be the way things are supposed to work. */
10282 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10283 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10284 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10285 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10290 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10292 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10295 switch (fixP
->fx_r_type
)
10297 case BFD_RELOC_MIPS_JMP
:
10298 case BFD_RELOC_MIPS_SHIFT5
:
10299 case BFD_RELOC_MIPS_SHIFT6
:
10300 case BFD_RELOC_MIPS_GOT_DISP
:
10301 case BFD_RELOC_MIPS_GOT_PAGE
:
10302 case BFD_RELOC_MIPS_GOT_OFST
:
10303 case BFD_RELOC_MIPS_SUB
:
10304 case BFD_RELOC_MIPS_INSERT_A
:
10305 case BFD_RELOC_MIPS_INSERT_B
:
10306 case BFD_RELOC_MIPS_DELETE
:
10307 case BFD_RELOC_MIPS_HIGHEST
:
10308 case BFD_RELOC_MIPS_HIGHER
:
10309 case BFD_RELOC_MIPS_SCN_DISP
:
10310 case BFD_RELOC_MIPS_REL16
:
10311 case BFD_RELOC_MIPS_RELGOT
:
10312 case BFD_RELOC_MIPS_JALR
:
10313 case BFD_RELOC_HI16
:
10314 case BFD_RELOC_HI16_S
:
10315 case BFD_RELOC_MIPS_GPREL
:
10316 case BFD_RELOC_MIPS_LITERAL
:
10317 case BFD_RELOC_MIPS_CALL16
:
10318 case BFD_RELOC_MIPS_GOT16
:
10319 case BFD_RELOC_MIPS_GPREL32
:
10320 case BFD_RELOC_MIPS_GOT_HI16
:
10321 case BFD_RELOC_MIPS_GOT_LO16
:
10322 case BFD_RELOC_MIPS_CALL_HI16
:
10323 case BFD_RELOC_MIPS_CALL_LO16
:
10324 case BFD_RELOC_MIPS16_GPREL
:
10325 if (fixP
->fx_pcrel
)
10326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10327 _("Invalid PC relative reloc"));
10328 /* Nothing needed to do. The value comes from the reloc entry */
10331 case BFD_RELOC_MIPS16_JMP
:
10332 /* We currently always generate a reloc against a symbol, which
10333 means that we don't want an addend even if the symbol is
10335 fixP
->fx_addnumber
= 0;
10338 case BFD_RELOC_PCREL_HI16_S
:
10339 /* The addend for this is tricky if it is internal, so we just
10340 do everything here rather than in bfd_install_relocation. */
10341 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10346 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10348 /* For an external symbol adjust by the address to make it
10349 pcrel_offset. We use the address of the RELLO reloc
10350 which follows this one. */
10351 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10352 + fixP
->fx_next
->fx_where
);
10354 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10355 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10356 if (target_big_endian
)
10358 md_number_to_chars (buf
, value
, 2);
10361 case BFD_RELOC_PCREL_LO16
:
10362 /* The addend for this is tricky if it is internal, so we just
10363 do everything here rather than in bfd_install_relocation. */
10364 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10369 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10370 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10371 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10372 if (target_big_endian
)
10374 md_number_to_chars (buf
, value
, 2);
10378 /* This is handled like BFD_RELOC_32, but we output a sign
10379 extended value if we are only 32 bits. */
10381 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10383 if (8 <= sizeof (valueT
))
10384 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10391 w1
= w2
= fixP
->fx_where
;
10392 if (target_big_endian
)
10396 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10397 if ((value
& 0x80000000) != 0)
10401 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10406 case BFD_RELOC_RVA
:
10408 /* If we are deleting this reloc entry, we must fill in the
10409 value now. This can happen if we have a .word which is not
10410 resolved when it appears but is later defined. We also need
10411 to fill in the value if this is an embedded PIC switch table
10414 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10415 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10420 /* If we are deleting this reloc entry, we must fill in the
10422 assert (fixP
->fx_size
== 2);
10424 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10428 case BFD_RELOC_LO16
:
10429 /* When handling an embedded PIC switch statement, we can wind
10430 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10433 if (value
+ 0x8000 > 0xffff)
10434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10435 _("relocation overflow"));
10436 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10437 if (target_big_endian
)
10439 md_number_to_chars (buf
, value
, 2);
10443 case BFD_RELOC_16_PCREL_S2
:
10444 if ((value
& 0x3) != 0)
10445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10446 _("Branch to odd address (%lx)"), (long) value
);
10448 /* Fall through. */
10450 case BFD_RELOC_16_PCREL
:
10452 * We need to save the bits in the instruction since fixup_segment()
10453 * might be deleting the relocation entry (i.e., a branch within
10454 * the current segment).
10456 if (!fixP
->fx_done
&& value
!= 0)
10458 /* If 'value' is zero, the remaining reloc code won't actually
10459 do the store, so it must be done here. This is probably
10460 a bug somewhere. */
10461 if (!fixP
->fx_done
)
10462 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10464 value
= (offsetT
) value
>> 2;
10466 /* update old instruction data */
10467 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10468 if (target_big_endian
)
10469 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10471 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10473 if (value
+ 0x8000 <= 0xffff)
10474 insn
|= value
& 0xffff;
10477 /* The branch offset is too large. If this is an
10478 unconditional branch, and we are not generating PIC code,
10479 we can convert it to an absolute jump instruction. */
10480 if (mips_pic
== NO_PIC
10482 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10483 && (fixP
->fx_frag
->fr_address
10484 < text_section
->vma
+ text_section
->_raw_size
)
10485 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10486 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10487 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10489 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10490 insn
= 0x0c000000; /* jal */
10492 insn
= 0x08000000; /* j */
10493 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10495 fixP
->fx_addsy
= section_symbol (text_section
);
10496 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10500 /* FIXME. It would be possible in principle to handle
10501 conditional branches which overflow. They could be
10502 transformed into a branch around a jump. This would
10503 require setting up variant frags for each different
10504 branch type. The native MIPS assembler attempts to
10505 handle these cases, but it appears to do it
10507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10508 _("Branch out of range"));
10512 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10515 case BFD_RELOC_VTABLE_INHERIT
:
10518 && !S_IS_DEFINED (fixP
->fx_addsy
)
10519 && !S_IS_WEAK (fixP
->fx_addsy
))
10520 S_SET_WEAK (fixP
->fx_addsy
);
10523 case BFD_RELOC_VTABLE_ENTRY
:
10539 const struct mips_opcode
*p
;
10540 int treg
, sreg
, dreg
, shamt
;
10545 for (i
= 0; i
< NUMOPCODES
; ++i
)
10547 p
= &mips_opcodes
[i
];
10548 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10550 printf ("%08lx %s\t", oc
, p
->name
);
10551 treg
= (oc
>> 16) & 0x1f;
10552 sreg
= (oc
>> 21) & 0x1f;
10553 dreg
= (oc
>> 11) & 0x1f;
10554 shamt
= (oc
>> 6) & 0x1f;
10556 for (args
= p
->args
;; ++args
)
10567 printf ("%c", *args
);
10571 assert (treg
== sreg
);
10572 printf ("$%d,$%d", treg
, sreg
);
10577 printf ("$%d", dreg
);
10582 printf ("$%d", treg
);
10586 printf ("0x%x", treg
);
10591 printf ("$%d", sreg
);
10595 printf ("0x%08lx", oc
& 0x1ffffff);
10602 printf ("%d", imm
);
10607 printf ("$%d", shamt
);
10618 printf (_("%08lx UNDEFINED\n"), oc
);
10629 name
= input_line_pointer
;
10630 c
= get_symbol_end ();
10631 p
= (symbolS
*) symbol_find_or_make (name
);
10632 *input_line_pointer
= c
;
10636 /* Align the current frag to a given power of two. The MIPS assembler
10637 also automatically adjusts any preceding label. */
10640 mips_align (to
, fill
, label
)
10645 mips_emit_delays (false);
10646 frag_align (to
, fill
, 0);
10647 record_alignment (now_seg
, to
);
10650 assert (S_GET_SEGMENT (label
) == now_seg
);
10651 symbol_set_frag (label
, frag_now
);
10652 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10656 /* Align to a given power of two. .align 0 turns off the automatic
10657 alignment used by the data creating pseudo-ops. */
10661 int x ATTRIBUTE_UNUSED
;
10664 register long temp_fill
;
10665 long max_alignment
= 15;
10669 o Note that the assembler pulls down any immediately preceeding label
10670 to the aligned address.
10671 o It's not documented but auto alignment is reinstated by
10672 a .align pseudo instruction.
10673 o Note also that after auto alignment is turned off the mips assembler
10674 issues an error on attempt to assemble an improperly aligned data item.
10679 temp
= get_absolute_expression ();
10680 if (temp
> max_alignment
)
10681 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10684 as_warn (_("Alignment negative: 0 assumed."));
10687 if (*input_line_pointer
== ',')
10689 input_line_pointer
++;
10690 temp_fill
= get_absolute_expression ();
10697 mips_align (temp
, (int) temp_fill
,
10698 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10705 demand_empty_rest_of_line ();
10709 mips_flush_pending_output ()
10711 mips_emit_delays (false);
10712 mips_clear_insn_labels ();
10721 /* When generating embedded PIC code, we only use the .text, .lit8,
10722 .sdata and .sbss sections. We change the .data and .rdata
10723 pseudo-ops to use .sdata. */
10724 if (mips_pic
== EMBEDDED_PIC
10725 && (sec
== 'd' || sec
== 'r'))
10729 /* The ELF backend needs to know that we are changing sections, so
10730 that .previous works correctly. We could do something like check
10731 for an obj_section_change_hook macro, but that might be confusing
10732 as it would not be appropriate to use it in the section changing
10733 functions in read.c, since obj-elf.c intercepts those. FIXME:
10734 This should be cleaner, somehow. */
10735 obj_elf_section_change_hook ();
10738 mips_emit_delays (false);
10748 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10749 demand_empty_rest_of_line ();
10753 if (USE_GLOBAL_POINTER_OPT
)
10755 seg
= subseg_new (RDATA_SECTION_NAME
,
10756 (subsegT
) get_absolute_expression ());
10757 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10759 bfd_set_section_flags (stdoutput
, seg
,
10765 if (strcmp (TARGET_OS
, "elf") != 0)
10766 record_alignment (seg
, 4);
10768 demand_empty_rest_of_line ();
10772 as_bad (_("No read only data section in this object file format"));
10773 demand_empty_rest_of_line ();
10779 if (USE_GLOBAL_POINTER_OPT
)
10781 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10782 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10784 bfd_set_section_flags (stdoutput
, seg
,
10785 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10787 if (strcmp (TARGET_OS
, "elf") != 0)
10788 record_alignment (seg
, 4);
10790 demand_empty_rest_of_line ();
10795 as_bad (_("Global pointers not supported; recompile -G 0"));
10796 demand_empty_rest_of_line ();
10805 mips_enable_auto_align ()
10816 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10817 mips_emit_delays (false);
10818 if (log_size
> 0 && auto_align
)
10819 mips_align (log_size
, 0, label
);
10820 mips_clear_insn_labels ();
10821 cons (1 << log_size
);
10825 s_float_cons (type
)
10830 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10832 mips_emit_delays (false);
10837 mips_align (3, 0, label
);
10839 mips_align (2, 0, label
);
10842 mips_clear_insn_labels ();
10847 /* Handle .globl. We need to override it because on Irix 5 you are
10850 where foo is an undefined symbol, to mean that foo should be
10851 considered to be the address of a function. */
10855 int x ATTRIBUTE_UNUSED
;
10862 name
= input_line_pointer
;
10863 c
= get_symbol_end ();
10864 symbolP
= symbol_find_or_make (name
);
10865 *input_line_pointer
= c
;
10866 SKIP_WHITESPACE ();
10868 /* On Irix 5, every global symbol that is not explicitly labelled as
10869 being a function is apparently labelled as being an object. */
10872 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10877 secname
= input_line_pointer
;
10878 c
= get_symbol_end ();
10879 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10881 as_bad (_("%s: no such section"), secname
);
10882 *input_line_pointer
= c
;
10884 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10885 flag
= BSF_FUNCTION
;
10888 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10890 S_SET_EXTERNAL (symbolP
);
10891 demand_empty_rest_of_line ();
10896 int x ATTRIBUTE_UNUSED
;
10901 opt
= input_line_pointer
;
10902 c
= get_symbol_end ();
10906 /* FIXME: What does this mean? */
10908 else if (strncmp (opt
, "pic", 3) == 0)
10912 i
= atoi (opt
+ 3);
10916 mips_pic
= SVR4_PIC
;
10918 as_bad (_(".option pic%d not supported"), i
);
10920 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10922 if (g_switch_seen
&& g_switch_value
!= 0)
10923 as_warn (_("-G may not be used with SVR4 PIC code"));
10924 g_switch_value
= 0;
10925 bfd_set_gp_size (stdoutput
, 0);
10929 as_warn (_("Unrecognized option \"%s\""), opt
);
10931 *input_line_pointer
= c
;
10932 demand_empty_rest_of_line ();
10935 /* This structure is used to hold a stack of .set values. */
10937 struct mips_option_stack
10939 struct mips_option_stack
*next
;
10940 struct mips_set_options options
;
10943 static struct mips_option_stack
*mips_opts_stack
;
10945 /* Handle the .set pseudo-op. */
10949 int x ATTRIBUTE_UNUSED
;
10951 char *name
= input_line_pointer
, ch
;
10953 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10954 input_line_pointer
++;
10955 ch
= *input_line_pointer
;
10956 *input_line_pointer
= '\0';
10958 if (strcmp (name
, "reorder") == 0)
10960 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10962 /* If we still have pending nops, we can discard them. The
10963 usual nop handling will insert any that are still
10965 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10966 * (mips_opts
.mips16
? 2 : 4));
10967 prev_nop_frag
= NULL
;
10969 mips_opts
.noreorder
= 0;
10971 else if (strcmp (name
, "noreorder") == 0)
10973 mips_emit_delays (true);
10974 mips_opts
.noreorder
= 1;
10975 mips_any_noreorder
= 1;
10977 else if (strcmp (name
, "at") == 0)
10979 mips_opts
.noat
= 0;
10981 else if (strcmp (name
, "noat") == 0)
10983 mips_opts
.noat
= 1;
10985 else if (strcmp (name
, "macro") == 0)
10987 mips_opts
.warn_about_macros
= 0;
10989 else if (strcmp (name
, "nomacro") == 0)
10991 if (mips_opts
.noreorder
== 0)
10992 as_bad (_("`noreorder' must be set before `nomacro'"));
10993 mips_opts
.warn_about_macros
= 1;
10995 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10997 mips_opts
.nomove
= 0;
10999 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11001 mips_opts
.nomove
= 1;
11003 else if (strcmp (name
, "bopt") == 0)
11005 mips_opts
.nobopt
= 0;
11007 else if (strcmp (name
, "nobopt") == 0)
11009 mips_opts
.nobopt
= 1;
11011 else if (strcmp (name
, "mips16") == 0
11012 || strcmp (name
, "MIPS-16") == 0)
11013 mips_opts
.mips16
= 1;
11014 else if (strcmp (name
, "nomips16") == 0
11015 || strcmp (name
, "noMIPS-16") == 0)
11016 mips_opts
.mips16
= 0;
11017 else if (strncmp (name
, "mips", 4) == 0)
11021 /* Permit the user to change the ISA on the fly. Needless to
11022 say, misuse can cause serious problems. */
11023 isa
= atoi (name
+ 4);
11027 mips_opts
.gp32
= file_mips_gp32
;
11028 mips_opts
.fp32
= file_mips_fp32
;
11029 mips_opts
.abi
= file_mips_abi
;
11034 mips_opts
.gp32
= 1;
11035 mips_opts
.fp32
= 1;
11041 /* Loosen ABI register width restriction. */
11042 if (mips_opts
.abi
== O32_ABI
)
11043 mips_opts
.abi
= NO_ABI
;
11044 mips_opts
.gp32
= 0;
11045 mips_opts
.fp32
= 0;
11048 as_bad (_("unknown ISA level %s"), name
+ 4);
11054 case 0: mips_opts
.isa
= file_mips_isa
; break;
11055 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11056 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11057 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11058 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11059 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11060 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11061 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11062 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11065 else if (strcmp (name
, "autoextend") == 0)
11066 mips_opts
.noautoextend
= 0;
11067 else if (strcmp (name
, "noautoextend") == 0)
11068 mips_opts
.noautoextend
= 1;
11069 else if (strcmp (name
, "push") == 0)
11071 struct mips_option_stack
*s
;
11073 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11074 s
->next
= mips_opts_stack
;
11075 s
->options
= mips_opts
;
11076 mips_opts_stack
= s
;
11078 else if (strcmp (name
, "pop") == 0)
11080 struct mips_option_stack
*s
;
11082 s
= mips_opts_stack
;
11084 as_bad (_(".set pop with no .set push"));
11087 /* If we're changing the reorder mode we need to handle
11088 delay slots correctly. */
11089 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11090 mips_emit_delays (true);
11091 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11093 if (prev_nop_frag
!= NULL
)
11095 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11096 * (mips_opts
.mips16
? 2 : 4));
11097 prev_nop_frag
= NULL
;
11101 mips_opts
= s
->options
;
11102 mips_opts_stack
= s
->next
;
11108 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11110 *input_line_pointer
= ch
;
11111 demand_empty_rest_of_line ();
11114 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11115 .option pic2. It means to generate SVR4 PIC calls. */
11118 s_abicalls (ignore
)
11119 int ignore ATTRIBUTE_UNUSED
;
11121 mips_pic
= SVR4_PIC
;
11122 if (USE_GLOBAL_POINTER_OPT
)
11124 if (g_switch_seen
&& g_switch_value
!= 0)
11125 as_warn (_("-G may not be used with SVR4 PIC code"));
11126 g_switch_value
= 0;
11128 bfd_set_gp_size (stdoutput
, 0);
11129 demand_empty_rest_of_line ();
11132 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11133 PIC code. It sets the $gp register for the function based on the
11134 function address, which is in the register named in the argument.
11135 This uses a relocation against _gp_disp, which is handled specially
11136 by the linker. The result is:
11137 lui $gp,%hi(_gp_disp)
11138 addiu $gp,$gp,%lo(_gp_disp)
11139 addu $gp,$gp,.cpload argument
11140 The .cpload argument is normally $25 == $t9. */
11144 int ignore ATTRIBUTE_UNUSED
;
11149 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11150 .cpload is ignored. */
11151 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11157 /* .cpload should be in a .set noreorder section. */
11158 if (mips_opts
.noreorder
== 0)
11159 as_warn (_(".cpload not in noreorder section"));
11161 ex
.X_op
= O_symbol
;
11162 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11163 ex
.X_op_symbol
= NULL
;
11164 ex
.X_add_number
= 0;
11166 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11167 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11169 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
11170 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11171 (int) BFD_RELOC_LO16
);
11173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11174 GP
, GP
, tc_get_register (0));
11176 demand_empty_rest_of_line ();
11179 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11180 .cpsetup $reg1, offset|$reg2, label
11182 If offset is given, this results in:
11183 sd $gp, offset($sp)
11184 lui $gp, %gp_rel(%neg(%hi(label)))
11185 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11186 addu $gp, $gp, $reg1
11188 If $reg2 is given, this results in:
11189 daddu $reg2, $gp, $0
11190 lui $gp, %gp_rel(%neg(%hi(label)))
11191 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11192 addu $gp, $gp, $reg1
11196 int ignore ATTRIBUTE_UNUSED
;
11198 expressionS ex_off
;
11199 expressionS ex_sym
;
11204 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11205 We also need NewABI support. */
11206 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11212 reg1
= tc_get_register (0);
11213 SKIP_WHITESPACE ();
11214 if (*input_line_pointer
!= ',')
11216 as_bad (_("missing argument separator ',' for .cpsetup"));
11220 input_line_pointer
++;
11221 SKIP_WHITESPACE ();
11222 if (*input_line_pointer
== '$')
11223 mips_cpreturn_register
= tc_get_register (0);
11225 mips_cpreturn_offset
= get_absolute_expression ();
11226 SKIP_WHITESPACE ();
11227 if (*input_line_pointer
!= ',')
11229 as_bad (_("missing argument separator ',' for .cpsetup"));
11233 input_line_pointer
++;
11234 SKIP_WHITESPACE ();
11235 sym
= input_line_pointer
;
11236 while (ISALNUM (*input_line_pointer
))
11237 input_line_pointer
++;
11238 *input_line_pointer
= 0;
11240 ex_sym
.X_op
= O_symbol
;
11241 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11242 ex_sym
.X_op_symbol
= NULL
;
11243 ex_sym
.X_add_number
= 0;
11245 if (mips_cpreturn_register
== -1)
11247 ex_off
.X_op
= O_constant
;
11248 ex_off
.X_add_symbol
= NULL
;
11249 ex_off
.X_op_symbol
= NULL
;
11250 ex_off
.X_add_number
= mips_cpreturn_offset
;
11252 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11253 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11257 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11259 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11260 (int) BFD_RELOC_GPREL16
);
11261 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11262 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11263 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11264 NULL
, 0, 0, BFD_RELOC_HI16_S
);
11265 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11266 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11267 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11268 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11269 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11270 NULL
, 0, 0, BFD_RELOC_LO16
);
11271 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11272 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
11274 demand_empty_rest_of_line ();
11279 int ignore ATTRIBUTE_UNUSED
;
11281 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11282 .cplocal is ignored. */
11283 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11289 mips_gp_register
= tc_get_register (0);
11292 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11293 offset from $sp. The offset is remembered, and after making a PIC
11294 call $gp is restored from that location. */
11297 s_cprestore (ignore
)
11298 int ignore ATTRIBUTE_UNUSED
;
11303 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11304 .cprestore is ignored. */
11305 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11311 mips_cprestore_offset
= get_absolute_expression ();
11313 ex
.X_op
= O_constant
;
11314 ex
.X_add_symbol
= NULL
;
11315 ex
.X_op_symbol
= NULL
;
11316 ex
.X_add_number
= mips_cprestore_offset
;
11318 macro_build ((char *) NULL
, &icnt
, &ex
,
11319 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11320 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11322 demand_empty_rest_of_line ();
11325 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11326 was given in the preceeding .gpsetup, it results in:
11327 ld $gp, offset($sp)
11329 If a register $reg2 was given there, it results in:
11330 daddiu $gp, $gp, $reg2
11333 s_cpreturn (ignore
)
11334 int ignore ATTRIBUTE_UNUSED
;
11339 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11340 We also need NewABI support. */
11341 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11347 if (mips_cpreturn_register
== -1)
11349 ex
.X_op
= O_constant
;
11350 ex
.X_add_symbol
= NULL
;
11351 ex
.X_op_symbol
= NULL
;
11352 ex
.X_add_number
= mips_cpreturn_offset
;
11354 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11355 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11359 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11361 demand_empty_rest_of_line ();
11364 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11365 code. It sets the offset to use in gp_rel relocations. */
11369 int ignore ATTRIBUTE_UNUSED
;
11371 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11372 We also need NewABI support. */
11373 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11379 mips_cpreturn_offset
= get_absolute_expression ();
11381 demand_empty_rest_of_line ();
11384 /* Handle the .gpword pseudo-op. This is used when generating PIC
11385 code. It generates a 32 bit GP relative reloc. */
11389 int ignore ATTRIBUTE_UNUSED
;
11395 /* When not generating PIC code, this is treated as .word. */
11396 if (mips_pic
!= SVR4_PIC
)
11402 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11403 mips_emit_delays (true);
11405 mips_align (2, 0, label
);
11406 mips_clear_insn_labels ();
11410 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11412 as_bad (_("Unsupported use of .gpword"));
11413 ignore_rest_of_line ();
11417 md_number_to_chars (p
, (valueT
) 0, 4);
11418 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11419 BFD_RELOC_MIPS_GPREL32
);
11421 demand_empty_rest_of_line ();
11424 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11425 tables in SVR4 PIC code. */
11429 int ignore ATTRIBUTE_UNUSED
;
11434 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11436 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11442 /* Add $gp to the register named as an argument. */
11443 reg
= tc_get_register (0);
11444 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11445 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11446 "d,v,t", reg
, reg
, GP
);
11448 demand_empty_rest_of_line ();
11451 /* Handle the .insn pseudo-op. This marks instruction labels in
11452 mips16 mode. This permits the linker to handle them specially,
11453 such as generating jalx instructions when needed. We also make
11454 them odd for the duration of the assembly, in order to generate the
11455 right sort of code. We will make them even in the adjust_symtab
11456 routine, while leaving them marked. This is convenient for the
11457 debugger and the disassembler. The linker knows to make them odd
11462 int ignore ATTRIBUTE_UNUSED
;
11464 if (mips_opts
.mips16
)
11465 mips16_mark_labels ();
11467 demand_empty_rest_of_line ();
11470 /* Handle a .stabn directive. We need these in order to mark a label
11471 as being a mips16 text label correctly. Sometimes the compiler
11472 will emit a label, followed by a .stabn, and then switch sections.
11473 If the label and .stabn are in mips16 mode, then the label is
11474 really a mips16 text label. */
11480 if (type
== 'n' && mips_opts
.mips16
)
11481 mips16_mark_labels ();
11486 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11490 s_mips_weakext (ignore
)
11491 int ignore ATTRIBUTE_UNUSED
;
11498 name
= input_line_pointer
;
11499 c
= get_symbol_end ();
11500 symbolP
= symbol_find_or_make (name
);
11501 S_SET_WEAK (symbolP
);
11502 *input_line_pointer
= c
;
11504 SKIP_WHITESPACE ();
11506 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11508 if (S_IS_DEFINED (symbolP
))
11510 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11511 S_GET_NAME (symbolP
));
11512 ignore_rest_of_line ();
11516 if (*input_line_pointer
== ',')
11518 ++input_line_pointer
;
11519 SKIP_WHITESPACE ();
11523 if (exp
.X_op
!= O_symbol
)
11525 as_bad ("bad .weakext directive");
11526 ignore_rest_of_line();
11529 symbol_set_value_expression (symbolP
, &exp
);
11532 demand_empty_rest_of_line ();
11535 /* Parse a register string into a number. Called from the ECOFF code
11536 to parse .frame. The argument is non-zero if this is the frame
11537 register, so that we can record it in mips_frame_reg. */
11540 tc_get_register (frame
)
11545 SKIP_WHITESPACE ();
11546 if (*input_line_pointer
++ != '$')
11548 as_warn (_("expected `$'"));
11551 else if (ISDIGIT (*input_line_pointer
))
11553 reg
= get_absolute_expression ();
11554 if (reg
< 0 || reg
>= 32)
11556 as_warn (_("Bad register number"));
11562 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11564 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11566 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11568 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11572 as_warn (_("Unrecognized register name"));
11575 input_line_pointer
+= 2;
11578 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11583 md_section_align (seg
, addr
)
11587 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11590 /* We don't need to align ELF sections to the full alignment.
11591 However, Irix 5 may prefer that we align them at least to a 16
11592 byte boundary. We don't bother to align the sections if we are
11593 targeted for an embedded system. */
11594 if (strcmp (TARGET_OS
, "elf") == 0)
11600 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11603 /* Utility routine, called from above as well. If called while the
11604 input file is still being read, it's only an approximation. (For
11605 example, a symbol may later become defined which appeared to be
11606 undefined earlier.) */
11609 nopic_need_relax (sym
, before_relaxing
)
11611 int before_relaxing
;
11616 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11618 const char *symname
;
11621 /* Find out whether this symbol can be referenced off the GP
11622 register. It can be if it is smaller than the -G size or if
11623 it is in the .sdata or .sbss section. Certain symbols can
11624 not be referenced off the GP, although it appears as though
11626 symname
= S_GET_NAME (sym
);
11627 if (symname
!= (const char *) NULL
11628 && (strcmp (symname
, "eprol") == 0
11629 || strcmp (symname
, "etext") == 0
11630 || strcmp (symname
, "_gp") == 0
11631 || strcmp (symname
, "edata") == 0
11632 || strcmp (symname
, "_fbss") == 0
11633 || strcmp (symname
, "_fdata") == 0
11634 || strcmp (symname
, "_ftext") == 0
11635 || strcmp (symname
, "end") == 0
11636 || strcmp (symname
, "_gp_disp") == 0))
11638 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11640 #ifndef NO_ECOFF_DEBUGGING
11641 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11642 && (symbol_get_obj (sym
)->ecoff_extern_size
11643 <= g_switch_value
))
11645 /* We must defer this decision until after the whole
11646 file has been read, since there might be a .extern
11647 after the first use of this symbol. */
11648 || (before_relaxing
11649 #ifndef NO_ECOFF_DEBUGGING
11650 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11652 && S_GET_VALUE (sym
) == 0)
11653 || (S_GET_VALUE (sym
) != 0
11654 && S_GET_VALUE (sym
) <= g_switch_value
)))
11658 const char *segname
;
11660 segname
= segment_name (S_GET_SEGMENT (sym
));
11661 assert (strcmp (segname
, ".lit8") != 0
11662 && strcmp (segname
, ".lit4") != 0);
11663 change
= (strcmp (segname
, ".sdata") != 0
11664 && strcmp (segname
, ".sbss") != 0
11665 && strncmp (segname
, ".sdata.", 7) != 0
11666 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11671 /* We are not optimizing for the GP register. */
11675 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11676 extended opcode. SEC is the section the frag is in. */
11679 mips16_extended_frag (fragp
, sec
, stretch
)
11685 register const struct mips16_immed_operand
*op
;
11687 int mintiny
, maxtiny
;
11691 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11693 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11696 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11697 op
= mips16_immed_operands
;
11698 while (op
->type
!= type
)
11701 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11706 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11709 maxtiny
= 1 << op
->nbits
;
11714 maxtiny
= (1 << op
->nbits
) - 1;
11719 mintiny
= - (1 << (op
->nbits
- 1));
11720 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11723 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11724 val
= S_GET_VALUE (fragp
->fr_symbol
);
11725 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11731 /* We won't have the section when we are called from
11732 mips_relax_frag. However, we will always have been called
11733 from md_estimate_size_before_relax first. If this is a
11734 branch to a different section, we mark it as such. If SEC is
11735 NULL, and the frag is not marked, then it must be a branch to
11736 the same section. */
11739 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11744 /* Must have been called from md_estimate_size_before_relax. */
11747 fragp
->fr_subtype
=
11748 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11750 /* FIXME: We should support this, and let the linker
11751 catch branches and loads that are out of range. */
11752 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11753 _("unsupported PC relative reference to different section"));
11757 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11758 /* Assume non-extended on the first relaxation pass.
11759 The address we have calculated will be bogus if this is
11760 a forward branch to another frag, as the forward frag
11761 will have fr_address == 0. */
11765 /* In this case, we know for sure that the symbol fragment is in
11766 the same section. If the relax_marker of the symbol fragment
11767 differs from the relax_marker of this fragment, we have not
11768 yet adjusted the symbol fragment fr_address. We want to add
11769 in STRETCH in order to get a better estimate of the address.
11770 This particularly matters because of the shift bits. */
11772 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11776 /* Adjust stretch for any alignment frag. Note that if have
11777 been expanding the earlier code, the symbol may be
11778 defined in what appears to be an earlier frag. FIXME:
11779 This doesn't handle the fr_subtype field, which specifies
11780 a maximum number of bytes to skip when doing an
11782 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11784 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11787 stretch
= - ((- stretch
)
11788 & ~ ((1 << (int) f
->fr_offset
) - 1));
11790 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11799 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11801 /* The base address rules are complicated. The base address of
11802 a branch is the following instruction. The base address of a
11803 PC relative load or add is the instruction itself, but if it
11804 is in a delay slot (in which case it can not be extended) use
11805 the address of the instruction whose delay slot it is in. */
11806 if (type
== 'p' || type
== 'q')
11810 /* If we are currently assuming that this frag should be
11811 extended, then, the current address is two bytes
11813 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11816 /* Ignore the low bit in the target, since it will be set
11817 for a text label. */
11818 if ((val
& 1) != 0)
11821 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11823 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11826 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11828 /* Branch offsets have an implicit 0 in the lowest bit. */
11829 if (type
== 'p' || type
== 'q')
11832 /* If any of the shifted bits are set, we must use an extended
11833 opcode. If the address depends on the size of this
11834 instruction, this can lead to a loop, so we arrange to always
11835 use an extended opcode. We only check this when we are in
11836 the main relaxation loop, when SEC is NULL. */
11837 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11839 fragp
->fr_subtype
=
11840 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11844 /* If we are about to mark a frag as extended because the value
11845 is precisely maxtiny + 1, then there is a chance of an
11846 infinite loop as in the following code:
11851 In this case when the la is extended, foo is 0x3fc bytes
11852 away, so the la can be shrunk, but then foo is 0x400 away, so
11853 the la must be extended. To avoid this loop, we mark the
11854 frag as extended if it was small, and is about to become
11855 extended with a value of maxtiny + 1. */
11856 if (val
== ((maxtiny
+ 1) << op
->shift
)
11857 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11860 fragp
->fr_subtype
=
11861 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11865 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11866 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11868 if ((val
& ((1 << op
->shift
) - 1)) != 0
11869 || val
< (mintiny
<< op
->shift
)
11870 || val
> (maxtiny
<< op
->shift
))
11876 /* Estimate the size of a frag before relaxing. Unless this is the
11877 mips16, we are not really relaxing here, and the final size is
11878 encoded in the subtype information. For the mips16, we have to
11879 decide whether we are using an extended opcode or not. */
11882 md_estimate_size_before_relax (fragp
, segtype
)
11887 boolean linkonce
= false;
11889 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11891 if (mips16_extended_frag (fragp
, segtype
, 0))
11893 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11898 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11903 if (mips_pic
== NO_PIC
)
11905 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11907 else if (mips_pic
== SVR4_PIC
)
11912 sym
= fragp
->fr_symbol
;
11914 /* Handle the case of a symbol equated to another symbol. */
11915 while (symbol_equated_reloc_p (sym
))
11919 /* It's possible to get a loop here in a badly written
11921 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11927 symsec
= S_GET_SEGMENT (sym
);
11929 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11930 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11932 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11936 /* The GNU toolchain uses an extension for ELF: a section
11937 beginning with the magic string .gnu.linkonce is a linkonce
11939 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11940 sizeof ".gnu.linkonce" - 1) == 0)
11944 /* This must duplicate the test in adjust_reloc_syms. */
11945 change
= (symsec
!= &bfd_und_section
11946 && symsec
!= &bfd_abs_section
11947 && ! bfd_is_com_section (symsec
)
11950 /* A global or weak symbol is treated as external. */
11951 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11952 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11961 /* Record the offset to the first reloc in the fr_opcode field.
11962 This lets md_convert_frag and tc_gen_reloc know that the code
11963 must be expanded. */
11964 fragp
->fr_opcode
= (fragp
->fr_literal
11966 - RELAX_OLD (fragp
->fr_subtype
)
11967 + RELAX_RELOC1 (fragp
->fr_subtype
));
11968 /* FIXME: This really needs as_warn_where. */
11969 if (RELAX_WARN (fragp
->fr_subtype
))
11970 as_warn (_("AT used after \".set noat\" or macro used after "
11971 "\".set nomacro\""));
11973 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11979 /* This is called to see whether a reloc against a defined symbol
11980 should be converted into a reloc against a section. Don't adjust
11981 MIPS16 jump relocations, so we don't have to worry about the format
11982 of the offset in the .o file. Don't adjust relocations against
11983 mips16 symbols, so that the linker can find them if it needs to set
11987 mips_fix_adjustable (fixp
)
11991 /* Prevent all adjustments to global symbols. */
11992 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11993 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
11996 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11998 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11999 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12001 if (fixp
->fx_addsy
== NULL
)
12004 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12005 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12006 && fixp
->fx_subsy
== NULL
)
12012 /* Translate internal representation of relocation info to BFD target
12016 tc_gen_reloc (section
, fixp
)
12017 asection
*section ATTRIBUTE_UNUSED
;
12020 static arelent
*retval
[4];
12022 bfd_reloc_code_real_type code
;
12024 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12027 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12028 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12029 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12031 if (mips_pic
== EMBEDDED_PIC
12032 && SWITCH_TABLE (fixp
))
12034 /* For a switch table entry we use a special reloc. The addend
12035 is actually the difference between the reloc address and the
12037 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12038 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12039 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12040 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12042 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12043 reloc
->addend
= fixp
->fx_addnumber
;
12044 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12046 /* We use a special addend for an internal RELLO reloc. */
12047 if (symbol_section_p (fixp
->fx_addsy
))
12048 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12050 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12052 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12054 assert (fixp
->fx_next
!= NULL
12055 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12056 /* We use a special addend for an internal RELHI reloc. The
12057 reloc is relative to the RELLO; adjust the addend
12059 if (symbol_section_p (fixp
->fx_addsy
))
12060 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12061 + fixp
->fx_next
->fx_where
12062 - S_GET_VALUE (fixp
->fx_subsy
));
12064 reloc
->addend
= (fixp
->fx_addnumber
12065 + fixp
->fx_next
->fx_frag
->fr_address
12066 + fixp
->fx_next
->fx_where
);
12070 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12071 /* A gruesome hack which is a result of the gruesome gas reloc
12073 reloc
->addend
= reloc
->address
;
12075 reloc
->addend
= -reloc
->address
;
12078 /* If this is a variant frag, we may need to adjust the existing
12079 reloc and generate a new one. */
12080 if (fixp
->fx_frag
->fr_opcode
!= NULL
12081 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12082 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12083 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12084 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12085 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12086 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12087 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12092 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12094 /* If this is not the last reloc in this frag, then we have two
12095 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12096 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12097 the second one handle all of them. */
12098 if (fixp
->fx_next
!= NULL
12099 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12101 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12102 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
12103 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12104 && (fixp
->fx_next
->fx_r_type
12105 == BFD_RELOC_MIPS_GOT_LO16
))
12106 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12107 && (fixp
->fx_next
->fx_r_type
12108 == BFD_RELOC_MIPS_CALL_LO16
)));
12113 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12114 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12115 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12117 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12118 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12119 reloc2
->address
= (reloc
->address
12120 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12121 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12122 reloc2
->addend
= fixp
->fx_addnumber
;
12123 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12124 assert (reloc2
->howto
!= NULL
);
12126 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12130 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12133 reloc3
->address
+= 4;
12136 if (mips_pic
== NO_PIC
)
12138 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
12139 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12141 else if (mips_pic
== SVR4_PIC
)
12143 switch (fixp
->fx_r_type
)
12147 case BFD_RELOC_MIPS_GOT16
:
12149 case BFD_RELOC_MIPS_CALL16
:
12150 case BFD_RELOC_MIPS_GOT_LO16
:
12151 case BFD_RELOC_MIPS_CALL_LO16
:
12152 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12160 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12161 to be used in the relocation's section offset. */
12162 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12164 reloc
->address
= reloc
->addend
;
12168 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12169 fixup_segment converted a non-PC relative reloc into a PC
12170 relative reloc. In such a case, we need to convert the reloc
12172 code
= fixp
->fx_r_type
;
12173 if (fixp
->fx_pcrel
)
12178 code
= BFD_RELOC_8_PCREL
;
12181 code
= BFD_RELOC_16_PCREL
;
12184 code
= BFD_RELOC_32_PCREL
;
12187 code
= BFD_RELOC_64_PCREL
;
12189 case BFD_RELOC_8_PCREL
:
12190 case BFD_RELOC_16_PCREL
:
12191 case BFD_RELOC_32_PCREL
:
12192 case BFD_RELOC_64_PCREL
:
12193 case BFD_RELOC_16_PCREL_S2
:
12194 case BFD_RELOC_PCREL_HI16_S
:
12195 case BFD_RELOC_PCREL_LO16
:
12198 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12199 _("Cannot make %s relocation PC relative"),
12200 bfd_get_reloc_code_name (code
));
12204 /* To support a PC relative reloc when generating embedded PIC code
12205 for ECOFF, we use a Cygnus extension. We check for that here to
12206 make sure that we don't let such a reloc escape normally. */
12207 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12208 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12209 && code
== BFD_RELOC_16_PCREL_S2
12210 && mips_pic
!= EMBEDDED_PIC
)
12211 reloc
->howto
= NULL
;
12213 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12215 if (reloc
->howto
== NULL
)
12217 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12218 _("Can not represent %s relocation in this object file format"),
12219 bfd_get_reloc_code_name (code
));
12226 /* Relax a machine dependent frag. This returns the amount by which
12227 the current size of the frag should change. */
12230 mips_relax_frag (fragp
, stretch
)
12234 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12237 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
12239 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12241 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12246 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12248 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12255 /* Convert a machine dependent frag. */
12258 md_convert_frag (abfd
, asec
, fragp
)
12259 bfd
*abfd ATTRIBUTE_UNUSED
;
12266 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12269 register const struct mips16_immed_operand
*op
;
12270 boolean small
, ext
;
12273 unsigned long insn
;
12274 boolean use_extend
;
12275 unsigned short extend
;
12277 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12278 op
= mips16_immed_operands
;
12279 while (op
->type
!= type
)
12282 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12293 resolve_symbol_value (fragp
->fr_symbol
);
12294 val
= S_GET_VALUE (fragp
->fr_symbol
);
12299 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12301 /* The rules for the base address of a PC relative reloc are
12302 complicated; see mips16_extended_frag. */
12303 if (type
== 'p' || type
== 'q')
12308 /* Ignore the low bit in the target, since it will be
12309 set for a text label. */
12310 if ((val
& 1) != 0)
12313 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12315 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12318 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12321 /* Make sure the section winds up with the alignment we have
12324 record_alignment (asec
, op
->shift
);
12328 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12329 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12330 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12331 _("extended instruction in delay slot"));
12333 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12335 if (target_big_endian
)
12336 insn
= bfd_getb16 (buf
);
12338 insn
= bfd_getl16 (buf
);
12340 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12341 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12342 small
, ext
, &insn
, &use_extend
, &extend
);
12346 md_number_to_chars (buf
, 0xf000 | extend
, 2);
12347 fragp
->fr_fix
+= 2;
12351 md_number_to_chars (buf
, insn
, 2);
12352 fragp
->fr_fix
+= 2;
12357 if (fragp
->fr_opcode
== NULL
)
12360 old
= RELAX_OLD (fragp
->fr_subtype
);
12361 new = RELAX_NEW (fragp
->fr_subtype
);
12362 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12365 memcpy (fixptr
- old
, fixptr
, new);
12367 fragp
->fr_fix
+= new - old
;
12373 /* This function is called after the relocs have been generated.
12374 We've been storing mips16 text labels as odd. Here we convert them
12375 back to even for the convenience of the debugger. */
12378 mips_frob_file_after_relocs ()
12381 unsigned int count
, i
;
12383 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12386 syms
= bfd_get_outsymbols (stdoutput
);
12387 count
= bfd_get_symcount (stdoutput
);
12388 for (i
= 0; i
< count
; i
++, syms
++)
12390 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12391 && ((*syms
)->value
& 1) != 0)
12393 (*syms
)->value
&= ~1;
12394 /* If the symbol has an odd size, it was probably computed
12395 incorrectly, so adjust that as well. */
12396 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12397 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12404 /* This function is called whenever a label is defined. It is used
12405 when handling branch delays; if a branch has a label, we assume we
12406 can not move it. */
12409 mips_define_label (sym
)
12412 struct insn_label_list
*l
;
12414 if (free_insn_labels
== NULL
)
12415 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12418 l
= free_insn_labels
;
12419 free_insn_labels
= l
->next
;
12423 l
->next
= insn_labels
;
12427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12429 /* Some special processing for a MIPS ELF file. */
12432 mips_elf_final_processing ()
12434 /* Write out the register information. */
12439 s
.ri_gprmask
= mips_gprmask
;
12440 s
.ri_cprmask
[0] = mips_cprmask
[0];
12441 s
.ri_cprmask
[1] = mips_cprmask
[1];
12442 s
.ri_cprmask
[2] = mips_cprmask
[2];
12443 s
.ri_cprmask
[3] = mips_cprmask
[3];
12444 /* The gp_value field is set by the MIPS ELF backend. */
12446 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12447 ((Elf32_External_RegInfo
*)
12448 mips_regmask_frag
));
12452 Elf64_Internal_RegInfo s
;
12454 s
.ri_gprmask
= mips_gprmask
;
12456 s
.ri_cprmask
[0] = mips_cprmask
[0];
12457 s
.ri_cprmask
[1] = mips_cprmask
[1];
12458 s
.ri_cprmask
[2] = mips_cprmask
[2];
12459 s
.ri_cprmask
[3] = mips_cprmask
[3];
12460 /* The gp_value field is set by the MIPS ELF backend. */
12462 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12463 ((Elf64_External_RegInfo
*)
12464 mips_regmask_frag
));
12467 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12468 sort of BFD interface for this. */
12469 if (mips_any_noreorder
)
12470 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12471 if (mips_pic
!= NO_PIC
)
12472 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12474 /* Set the MIPS ELF ABI flags. */
12475 if (file_mips_abi
== NO_ABI
)
12477 else if (file_mips_abi
== O32_ABI
)
12478 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12479 else if (file_mips_abi
== O64_ABI
)
12480 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12481 else if (file_mips_abi
== EABI_ABI
)
12484 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12486 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12488 else if (file_mips_abi
== N32_ABI
)
12489 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12491 /* Nothing to do for "64". */
12493 if (mips_32bitmode
)
12494 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12497 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12499 typedef struct proc
{
12501 unsigned long reg_mask
;
12502 unsigned long reg_offset
;
12503 unsigned long fpreg_mask
;
12504 unsigned long fpreg_offset
;
12505 unsigned long frame_offset
;
12506 unsigned long frame_reg
;
12507 unsigned long pc_reg
;
12510 static procS cur_proc
;
12511 static procS
*cur_proc_ptr
;
12512 static int numprocs
;
12514 /* Fill in an rs_align_code fragment. */
12517 mips_handle_align (fragp
)
12520 if (fragp
->fr_type
!= rs_align_code
)
12523 if (mips_opts
.mips16
)
12525 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12526 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12531 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12532 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12537 fragp
->fr_fix
+= 1;
12540 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12544 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12555 /* check for premature end, nesting errors, etc */
12557 as_warn (_("missing .end at end of assembly"));
12566 if (*input_line_pointer
== '-')
12568 ++input_line_pointer
;
12571 if (!ISDIGIT (*input_line_pointer
))
12572 as_bad (_("Expected simple number."));
12573 if (input_line_pointer
[0] == '0')
12575 if (input_line_pointer
[1] == 'x')
12577 input_line_pointer
+= 2;
12578 while (ISXDIGIT (*input_line_pointer
))
12581 val
|= hex_value (*input_line_pointer
++);
12583 return negative
? -val
: val
;
12587 ++input_line_pointer
;
12588 while (ISDIGIT (*input_line_pointer
))
12591 val
|= *input_line_pointer
++ - '0';
12593 return negative
? -val
: val
;
12596 if (!ISDIGIT (*input_line_pointer
))
12598 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12599 *input_line_pointer
, *input_line_pointer
);
12600 as_warn (_("Invalid number"));
12603 while (ISDIGIT (*input_line_pointer
))
12606 val
+= *input_line_pointer
++ - '0';
12608 return negative
? -val
: val
;
12611 /* The .file directive; just like the usual .file directive, but there
12612 is an initial number which is the ECOFF file index. */
12616 int x ATTRIBUTE_UNUSED
;
12620 line
= get_number ();
12624 /* The .end directive. */
12628 int x ATTRIBUTE_UNUSED
;
12633 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12636 demand_empty_rest_of_line ();
12641 #ifdef BFD_ASSEMBLER
12642 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12647 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12654 as_warn (_(".end not in text section"));
12658 as_warn (_(".end directive without a preceding .ent directive."));
12659 demand_empty_rest_of_line ();
12665 assert (S_GET_NAME (p
));
12666 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12667 as_warn (_(".end symbol does not match .ent symbol."));
12670 as_warn (_(".end directive missing or unknown symbol"));
12672 #ifdef MIPS_STABS_ELF
12674 segT saved_seg
= now_seg
;
12675 subsegT saved_subseg
= now_subseg
;
12680 dot
= frag_now_fix ();
12682 #ifdef md_flush_pending_output
12683 md_flush_pending_output ();
12687 subseg_set (pdr_seg
, 0);
12689 /* Write the symbol. */
12690 exp
.X_op
= O_symbol
;
12691 exp
.X_add_symbol
= p
;
12692 exp
.X_add_number
= 0;
12693 emit_expr (&exp
, 4);
12695 fragp
= frag_more (7 * 4);
12697 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12698 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12699 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12700 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12701 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12702 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12703 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12705 subseg_set (saved_seg
, saved_subseg
);
12709 cur_proc_ptr
= NULL
;
12712 /* The .aent and .ent directives. */
12722 symbolP
= get_symbol ();
12723 if (*input_line_pointer
== ',')
12724 input_line_pointer
++;
12725 SKIP_WHITESPACE ();
12726 if (ISDIGIT (*input_line_pointer
)
12727 || *input_line_pointer
== '-')
12728 number
= get_number ();
12730 #ifdef BFD_ASSEMBLER
12731 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12736 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12743 as_warn (_(".ent or .aent not in text section."));
12745 if (!aent
&& cur_proc_ptr
)
12746 as_warn (_("missing .end"));
12750 cur_proc_ptr
= &cur_proc
;
12751 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12753 cur_proc_ptr
->isym
= symbolP
;
12755 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12760 demand_empty_rest_of_line ();
12763 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12764 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12765 s_mips_frame is used so that we can set the PDR information correctly.
12766 We can't use the ecoff routines because they make reference to the ecoff
12767 symbol table (in the mdebug section). */
12770 s_mips_frame (ignore
)
12771 int ignore ATTRIBUTE_UNUSED
;
12773 #ifdef MIPS_STABS_ELF
12777 if (cur_proc_ptr
== (procS
*) NULL
)
12779 as_warn (_(".frame outside of .ent"));
12780 demand_empty_rest_of_line ();
12784 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12786 SKIP_WHITESPACE ();
12787 if (*input_line_pointer
++ != ','
12788 || get_absolute_expression_and_terminator (&val
) != ',')
12790 as_warn (_("Bad .frame directive"));
12791 --input_line_pointer
;
12792 demand_empty_rest_of_line ();
12796 cur_proc_ptr
->frame_offset
= val
;
12797 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12799 demand_empty_rest_of_line ();
12802 #endif /* MIPS_STABS_ELF */
12805 /* The .fmask and .mask directives. If the mdebug section is present
12806 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12807 embedded targets, s_mips_mask is used so that we can set the PDR
12808 information correctly. We can't use the ecoff routines because they
12809 make reference to the ecoff symbol table (in the mdebug section). */
12812 s_mips_mask (reg_type
)
12815 #ifdef MIPS_STABS_ELF
12818 if (cur_proc_ptr
== (procS
*) NULL
)
12820 as_warn (_(".mask/.fmask outside of .ent"));
12821 demand_empty_rest_of_line ();
12825 if (get_absolute_expression_and_terminator (&mask
) != ',')
12827 as_warn (_("Bad .mask/.fmask directive"));
12828 --input_line_pointer
;
12829 demand_empty_rest_of_line ();
12833 off
= get_absolute_expression ();
12835 if (reg_type
== 'F')
12837 cur_proc_ptr
->fpreg_mask
= mask
;
12838 cur_proc_ptr
->fpreg_offset
= off
;
12842 cur_proc_ptr
->reg_mask
= mask
;
12843 cur_proc_ptr
->reg_offset
= off
;
12846 demand_empty_rest_of_line ();
12848 s_ignore (reg_type
);
12849 #endif /* MIPS_STABS_ELF */
12852 /* The .loc directive. */
12863 assert (now_seg
== text_section
);
12865 lineno
= get_number ();
12866 addroff
= frag_now_fix ();
12868 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12869 S_SET_TYPE (symbolP
, N_SLINE
);
12870 S_SET_OTHER (symbolP
, 0);
12871 S_SET_DESC (symbolP
, lineno
);
12872 symbolP
->sy_segment
= now_seg
;
12876 /* CPU name/ISA/number mapping table.
12878 Entries are grouped by type. The first matching CPU or ISA entry
12879 gets chosen by CPU or ISA, so it should be the 'canonical' name
12880 for that type. Entries after that within the type are sorted
12883 Case is ignored in comparison, so put the canonical entry in the
12884 appropriate case but everything else in lower case to ease eye pain. */
12885 static const struct mips_cpu_info mips_cpu_info_table
[] =
12888 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12889 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12892 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12895 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12898 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12901 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12902 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12905 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12906 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12907 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12908 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12909 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12910 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12912 /* For historical reasons. */
12913 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12916 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12917 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12918 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12919 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12922 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12923 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12924 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12925 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12928 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12929 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12930 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12931 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12934 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12935 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12936 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12939 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12940 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12941 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12942 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12945 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12946 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12949 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12950 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12953 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12954 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12955 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12956 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12959 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12960 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12963 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12964 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12965 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12966 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12969 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12970 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12971 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12972 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12975 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12976 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12977 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12978 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12981 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12982 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12983 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12984 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12987 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12988 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12989 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12990 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12993 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12994 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12995 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12996 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12999 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13000 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13001 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13002 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13005 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13006 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13007 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13008 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13009 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13010 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13011 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13012 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13013 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13014 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13015 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13016 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13017 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13018 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13019 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13020 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13021 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13023 /* Broadcom SB-1 CPU */
13024 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13025 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13026 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13027 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13030 { NULL
, 0, 0, 0, },
13033 static const struct mips_cpu_info
*
13034 mips_cpu_info_from_name (name
)
13039 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13040 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13041 return (&mips_cpu_info_table
[i
]);
13046 static const struct mips_cpu_info
*
13047 mips_cpu_info_from_isa (isa
)
13052 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13053 if (mips_cpu_info_table
[i
].is_isa
13054 && isa
== mips_cpu_info_table
[i
].isa
)
13055 return (&mips_cpu_info_table
[i
]);
13060 static const struct mips_cpu_info
*
13061 mips_cpu_info_from_cpu (cpu
)
13066 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13067 if (!mips_cpu_info_table
[i
].is_isa
13068 && cpu
== mips_cpu_info_table
[i
].cpu
)
13069 return (&mips_cpu_info_table
[i
]);