1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* The default target format to use. */
90 switch (OUTPUT_FLAVOR
)
92 case bfd_target_aout_flavour
:
93 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
94 case bfd_target_ecoff_flavour
:
95 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
96 case bfd_target_elf_flavour
:
97 return target_big_endian
? "elf32-bigmips" : "elf32-littlemips";
103 /* The name of the readonly data section. */
104 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
106 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
108 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
112 /* These variables are filled in with the masks of registers used.
113 The object format code reads them and puts them in the appropriate
115 unsigned long mips_gprmask
;
116 unsigned long mips_cprmask
[4];
118 /* MIPS ISA (Instruction Set Architecture) level (may be changed
119 temporarily using .set mipsN). */
120 static int mips_isa
= -1;
122 /* MIPS ISA we are using for this output file. */
123 static int file_mips_isa
;
125 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
126 static int mips_cpu
= -1;
128 /* Whether the 4650 instructions (mad/madu) are permitted. */
129 static int mips_4650
= -1;
131 /* Whether the 4010 instructions are permitted. */
132 static int mips_4010
= -1;
134 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
135 static int mips_4100
= -1;
137 /* Whether the processor uses hardware interlocks, and thus does not
138 require nops to be inserted. */
139 static int interlocks
= -1;
141 /* MIPS PIC level. */
145 /* Do not generate PIC code. */
148 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
149 not sure what it is supposed to do. */
152 /* Generate PIC code as in the SVR4 MIPS ABI. */
155 /* Generate PIC code without using a global offset table: the data
156 segment has a maximum size of 64K, all data references are off
157 the $gp register, and all text references are PC relative. This
158 is used on some embedded systems. */
162 static enum mips_pic_level mips_pic
;
164 /* 1 if we should generate 32 bit offsets from the GP register in
165 SVR4_PIC mode. Currently has no meaning in other modes. */
166 static int mips_big_got
;
168 /* 1 if trap instructions should used for overflow rather than break
170 static int mips_trap
;
172 static int mips_warn_about_macros
;
173 static int mips_noreorder
;
174 static int mips_any_noreorder
;
175 static int mips_nomove
;
176 static int mips_noat
;
177 static int mips_nobopt
;
179 /* The size of the small data section. */
180 static int g_switch_value
= 8;
181 /* Whether the -G option was used. */
182 static int g_switch_seen
= 0;
187 /* If we can determine in advance that GP optimization won't be
188 possible, we can skip the relaxation stuff that tries to produce
189 GP-relative references. This makes delay slot optimization work
192 This function can only provide a guess, but it seems to work for
193 gcc output. If it guesses wrong, the only loss should be in
194 efficiency; it shouldn't introduce any bugs.
196 I don't know if a fix is needed for the SVR4_PIC mode. I've only
197 fixed it for the non-PIC mode. KR 95/04/07 */
198 static int nopic_need_relax
PARAMS ((symbolS
*));
200 /* handle of the OPCODE hash table */
201 static struct hash_control
*op_hash
= NULL
;
203 /* This array holds the chars that always start a comment. If the
204 pre-processor is disabled, these aren't very useful */
205 const char comment_chars
[] = "#";
207 /* This array holds the chars that only start a comment at the beginning of
208 a line. If the line seems to have the form '# 123 filename'
209 .line and .file directives will appear in the pre-processed output */
210 /* Note that input_file.c hand checks for '#' at the beginning of the
211 first line of the input file. This is because the compiler outputs
212 #NO_APP at the beginning of its output. */
213 /* Also note that C style comments are always supported. */
214 const char line_comment_chars
[] = "#";
216 /* This array holds machine specific line separator characters. */
217 const char line_separator_chars
[] = "";
219 /* Chars that can be used to separate mant from exp in floating point nums */
220 const char EXP_CHARS
[] = "eE";
222 /* Chars that mean this number is a floating point constant */
225 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
227 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
228 changed in read.c . Ideally it shouldn't have to know about it at all,
229 but nothing is ideal around here.
232 static char *insn_error
;
234 static int byte_order
;
236 static int auto_align
= 1;
238 /* Symbol labelling the current insn. */
239 static symbolS
*insn_label
;
241 /* When outputting SVR4 PIC code, the assembler needs to know the
242 offset in the stack frame from which to restore the $gp register.
243 This is set by the .cprestore pseudo-op, and saved in this
245 static offsetT mips_cprestore_offset
= -1;
247 /* This is the register which holds the stack frame, as set by the
248 .frame pseudo-op. This is needed to implement .cprestore. */
249 static int mips_frame_reg
= SP
;
251 /* To output NOP instructions correctly, we need to keep information
252 about the previous two instructions. */
254 /* Whether we are optimizing. The default value of 2 means to remove
255 unneeded NOPs and swap branch instructions when possible. A value
256 of 1 means to not swap branches. A value of 0 means to always
258 static int mips_optimize
= 2;
260 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
261 equivalent to seeing no -g option at all. */
262 static int mips_debug
= 0;
264 /* The previous instruction. */
265 static struct mips_cl_insn prev_insn
;
267 /* The instruction before prev_insn. */
268 static struct mips_cl_insn prev_prev_insn
;
270 /* If we don't want information for prev_insn or prev_prev_insn, we
271 point the insn_mo field at this dummy integer. */
272 static const struct mips_opcode dummy_opcode
= { 0 };
274 /* Non-zero if prev_insn is valid. */
275 static int prev_insn_valid
;
277 /* The frag for the previous instruction. */
278 static struct frag
*prev_insn_frag
;
280 /* The offset into prev_insn_frag for the previous instruction. */
281 static long prev_insn_where
;
283 /* The reloc for the previous instruction, if any. */
284 static fixS
*prev_insn_fixp
;
286 /* Non-zero if the previous instruction was in a delay slot. */
287 static int prev_insn_is_delay_slot
;
289 /* Non-zero if the previous instruction was in a .set noreorder. */
290 static int prev_insn_unreordered
;
292 /* Non-zero if the previous previous instruction was in a .set
294 static int prev_prev_insn_unreordered
;
296 /* For ECOFF and ELF, relocations against symbols are done in two
297 parts, with a HI relocation and a LO relocation. Each relocation
298 has only 16 bits of space to store an addend. This means that in
299 order for the linker to handle carries correctly, it must be able
300 to locate both the HI and the LO relocation. This means that the
301 relocations must appear in order in the relocation table.
303 In order to implement this, we keep track of each unmatched HI
304 relocation. We then sort them so that they immediately precede the
305 corresponding LO relocation. */
310 struct mips_hi_fixup
*next
;
313 /* The section this fixup is in. */
317 /* The list of unmatched HI relocs. */
319 static struct mips_hi_fixup
*mips_hi_fixup_list
;
321 /* Since the MIPS does not have multiple forms of PC relative
322 instructions, we do not have to do relaxing as is done on other
323 platforms. However, we do have to handle GP relative addressing
324 correctly, which turns out to be a similar problem.
326 Every macro that refers to a symbol can occur in (at least) two
327 forms, one with GP relative addressing and one without. For
328 example, loading a global variable into a register generally uses
329 a macro instruction like this:
331 If i can be addressed off the GP register (this is true if it is in
332 the .sbss or .sdata section, or if it is known to be smaller than
333 the -G argument) this will generate the following instruction:
335 This instruction will use a GPREL reloc. If i can not be addressed
336 off the GP register, the following instruction sequence will be used:
339 In this case the first instruction will have a HI16 reloc, and the
340 second reloc will have a LO16 reloc. Both relocs will be against
343 The issue here is that we may not know whether i is GP addressable
344 until after we see the instruction that uses it. Therefore, we
345 want to be able to choose the final instruction sequence only at
346 the end of the assembly. This is similar to the way other
347 platforms choose the size of a PC relative instruction only at the
350 When generating position independent code we do not use GP
351 addressing in quite the same way, but the issue still arises as
352 external symbols and local symbols must be handled differently.
354 We handle these issues by actually generating both possible
355 instruction sequences. The longer one is put in a frag_var with
356 type rs_machine_dependent. We encode what to do with the frag in
357 the subtype field. We encode (1) the number of existing bytes to
358 replace, (2) the number of new bytes to use, (3) the offset from
359 the start of the existing bytes to the first reloc we must generate
360 (that is, the offset is applied from the start of the existing
361 bytes after they are replaced by the new bytes, if any), (4) the
362 offset from the start of the existing bytes to the second reloc,
363 (5) whether a third reloc is needed (the third reloc is always four
364 bytes after the second reloc), and (6) whether to warn if this
365 variant is used (this is sometimes needed if .set nomacro or .set
366 noat is in effect). All these numbers are reasonably small.
368 Generating two instruction sequences must be handled carefully to
369 ensure that delay slots are handled correctly. Fortunately, there
370 are a limited number of cases. When the second instruction
371 sequence is generated, append_insn is directed to maintain the
372 existing delay slot information, so it continues to apply to any
373 code after the second instruction sequence. This means that the
374 second instruction sequence must not impose any requirements not
375 required by the first instruction sequence.
377 These variant frags are then handled in functions called by the
378 machine independent code. md_estimate_size_before_relax returns
379 the final size of the frag. md_convert_frag sets up the final form
380 of the frag. tc_gen_reloc adjust the first reloc and adds a second
382 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
386 | (((reloc1) + 64) << 9) \
387 | (((reloc2) + 64) << 2) \
388 | ((reloc3) ? (1 << 1) : 0) \
390 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
391 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
392 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
393 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
394 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
395 #define RELAX_WARN(i) ((i) & 1)
397 /* Prototypes for static functions. */
400 #define internalError() \
401 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
403 #define internalError() as_fatal ("MIPS internal Error");
406 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
407 unsigned int reg
, int fpr
));
408 static int reg_needs_delay
PARAMS ((int));
409 static void append_insn
PARAMS ((char *place
,
410 struct mips_cl_insn
* ip
,
412 bfd_reloc_code_real_type r
,
414 static void mips_no_prev_insn
PARAMS ((void));
415 static void mips_emit_delays
PARAMS ((void));
417 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
418 const char *name
, const char *fmt
,
421 static void macro_build ();
423 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
424 expressionS
* ep
, int regnum
));
425 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
426 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
428 static void load_register
PARAMS ((int *, int, expressionS
*, int));
429 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
430 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
431 #ifdef LOSING_COMPILER
432 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
434 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
435 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
436 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
437 static symbolS
*get_symbol
PARAMS ((void));
438 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
439 static void s_align
PARAMS ((int));
440 static void s_change_sec
PARAMS ((int));
441 static void s_cons
PARAMS ((int));
442 static void s_float_cons
PARAMS ((int));
443 static void s_mips_globl
PARAMS ((int));
444 static void s_option
PARAMS ((int));
445 static void s_mipsset
PARAMS ((int));
446 static void s_abicalls
PARAMS ((int));
447 static void s_cpload
PARAMS ((int));
448 static void s_cprestore
PARAMS ((int));
449 static void s_gpword
PARAMS ((int));
450 static void s_cpadd
PARAMS ((int));
451 static void md_obj_begin
PARAMS ((void));
452 static void md_obj_end
PARAMS ((void));
453 static long get_number
PARAMS ((void));
454 static void s_ent
PARAMS ((int));
455 static void s_mipsend
PARAMS ((int));
456 static void s_file
PARAMS ((int));
460 The following pseudo-ops from the Kane and Heinrich MIPS book
461 should be defined here, but are currently unsupported: .alias,
462 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
464 The following pseudo-ops from the Kane and Heinrich MIPS book are
465 specific to the type of debugging information being generated, and
466 should be defined by the object format: .aent, .begin, .bend,
467 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
470 The following pseudo-ops from the Kane and Heinrich MIPS book are
471 not MIPS CPU specific, but are also not specific to the object file
472 format. This file is probably the best place to define them, but
473 they are not currently supported: .asm0, .endr, .lab, .repeat,
474 .struct, .weakext. */
476 static const pseudo_typeS mips_pseudo_table
[] =
478 /* MIPS specific pseudo-ops. */
479 {"option", s_option
, 0},
480 {"set", s_mipsset
, 0},
481 {"rdata", s_change_sec
, 'r'},
482 {"sdata", s_change_sec
, 's'},
483 {"livereg", s_ignore
, 0},
484 {"abicalls", s_abicalls
, 0},
485 {"cpload", s_cpload
, 0},
486 {"cprestore", s_cprestore
, 0},
487 {"gpword", s_gpword
, 0},
488 {"cpadd", s_cpadd
, 0},
490 /* Relatively generic pseudo-ops that happen to be used on MIPS
492 {"asciiz", stringer
, 1},
493 {"bss", s_change_sec
, 'b'},
496 {"dword", s_cons
, 3},
498 /* These pseudo-ops are defined in read.c, but must be overridden
499 here for one reason or another. */
500 {"align", s_align
, 0},
502 {"data", s_change_sec
, 'd'},
503 {"double", s_float_cons
, 'd'},
504 {"float", s_float_cons
, 'f'},
505 {"globl", s_mips_globl
, 0},
506 {"global", s_mips_globl
, 0},
507 {"hword", s_cons
, 1},
512 {"short", s_cons
, 1},
513 {"single", s_float_cons
, 'f'},
514 {"text", s_change_sec
, 't'},
519 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
520 /* These pseudo-ops should be defined by the object file format.
521 However, a.out doesn't support them, so we have versions here. */
523 {"bgnb", s_ignore
, 0},
524 {"end", s_mipsend
, 0},
525 {"endb", s_ignore
, 0},
528 {"fmask", s_ignore
, 'F'},
529 {"frame", s_ignore
, 0},
530 {"loc", s_ignore
, 0},
531 {"mask", s_ignore
, 'R'},
532 {"verstamp", s_ignore
, 0},
536 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
541 pop_insert (mips_pseudo_table
);
542 if (! ECOFF_DEBUGGING
)
543 pop_insert (mips_nonecoff_pseudo_table
);
546 static char *expr_end
;
548 /* Expressions which appear in instructions. These are set by
551 static expressionS imm_expr
;
552 static expressionS offset_expr
;
554 /* Relocs associated with imm_expr and offset_expr. */
556 static bfd_reloc_code_real_type imm_reloc
;
557 static bfd_reloc_code_real_type offset_reloc
;
559 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
561 static boolean imm_unmatched_hi
;
564 * This function is called once, at assembler startup time. It should
565 * set up all the tables, etc. that the MD part of the assembler will need.
571 register const char *retval
= NULL
;
572 register unsigned int i
= 0;
580 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
582 a
= xmalloc (sizeof TARGET_CPU
);
583 strcpy (a
, TARGET_CPU
);
584 a
[(sizeof TARGET_CPU
) - 3] = '\0';
588 if (strcmp (cpu
, "mips") == 0)
594 else if (strcmp (cpu
, "r6000") == 0
595 || strcmp (cpu
, "mips2") == 0)
601 else if (strcmp (cpu
, "mips64") == 0
602 || strcmp (cpu
, "r4000") == 0
603 || strcmp (cpu
, "mips3") == 0)
609 else if (strcmp (cpu
, "r4400") == 0)
615 else if (strcmp (cpu
, "mips64orion") == 0
616 || strcmp (cpu
, "r4600") == 0)
622 else if (strcmp (cpu
, "r4650") == 0)
630 else if (strcmp (cpu
, "mips64vr4300") == 0)
636 else if (strcmp (cpu
, "mips64vr4100") == 0)
644 else if (strcmp (cpu
, "r4010") == 0)
652 else if (strcmp (cpu
, "r8000") == 0
653 || strcmp (cpu
, "mips4") == 0)
659 else if (strcmp (cpu
, "r10000") == 0)
685 if (mips_4650
|| mips_4010
|| mips_4100
)
690 if (mips_isa
< 2 && mips_trap
)
691 as_bad ("trap exception not supported at ISA 1");
696 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
699 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
702 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
705 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
709 as_warn ("Could not set architecture and machine");
711 file_mips_isa
= mips_isa
;
713 op_hash
= hash_new ();
715 for (i
= 0; i
< NUMOPCODES
;)
717 const char *name
= mips_opcodes
[i
].name
;
719 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
722 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
723 mips_opcodes
[i
].name
, retval
);
724 as_fatal ("Broken assembler. No assembly attempted.");
728 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
729 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
730 != mips_opcodes
[i
].match
))
732 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
733 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
734 as_fatal ("Broken assembler. No assembly attempted.");
738 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
741 mips_no_prev_insn ();
749 /* set the default alignment for the text section (2**2) */
750 record_alignment (text_section
, 2);
752 if (USE_GLOBAL_POINTER_OPT
)
753 bfd_set_gp_size (stdoutput
, g_switch_value
);
755 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
757 /* Sections must be aligned to 16 byte boundaries. */
758 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
759 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
760 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
762 /* Create a .reginfo section for register masks and a .mdebug
763 section for debugging information. */
771 sec
= subseg_new (".reginfo", (subsegT
) 0);
773 /* The ABI says this section should be loaded so that the
774 running program can access it. */
775 (void) bfd_set_section_flags (stdoutput
, sec
,
776 (SEC_ALLOC
| SEC_LOAD
777 | SEC_READONLY
| SEC_DATA
));
778 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
781 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
786 sec
= subseg_new (".mdebug", (subsegT
) 0);
787 (void) bfd_set_section_flags (stdoutput
, sec
,
788 SEC_HAS_CONTENTS
| SEC_READONLY
);
789 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
792 subseg_set (seg
, subseg
);
796 if (! ECOFF_DEBUGGING
)
803 if (! ECOFF_DEBUGGING
)
811 struct mips_cl_insn insn
;
813 imm_expr
.X_op
= O_absent
;
814 imm_reloc
= BFD_RELOC_UNUSED
;
815 imm_unmatched_hi
= false;
816 offset_expr
.X_op
= O_absent
;
817 offset_reloc
= BFD_RELOC_UNUSED
;
819 mips_ip (str
, &insn
);
822 as_bad ("%s `%s'", insn_error
, str
);
825 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
831 if (imm_expr
.X_op
!= O_absent
)
832 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
834 else if (offset_expr
.X_op
!= O_absent
)
835 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
837 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
841 /* See whether instruction IP reads register REG. If FPR is non-zero,
842 REG is a floating point register. */
845 insn_uses_reg (ip
, reg
, fpr
)
846 struct mips_cl_insn
*ip
;
850 /* Don't report on general register 0, since it never changes. */
851 if (! fpr
&& reg
== 0)
856 /* If we are called with either $f0 or $f1, we must check $f0.
857 This is not optimal, because it will introduce an unnecessary
858 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
859 need to distinguish reading both $f0 and $f1 or just one of
860 them. Note that we don't have to check the other way,
861 because there is no instruction that sets both $f0 and $f1
862 and requires a delay. */
863 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
864 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
865 == (reg
&~ (unsigned) 1)))
867 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
868 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
869 == (reg
&~ (unsigned) 1)))
874 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
875 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
877 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
878 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
885 /* This function returns true if modifying a register requires a
889 reg_needs_delay (reg
)
892 unsigned long prev_pinfo
;
894 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
897 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
899 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
901 /* A load from a coprocessor or from memory. All load
902 delays delay the use of general register rt for one
903 instruction on the r3000. The r6000 and r4000 use
905 know (prev_pinfo
& INSN_WRITE_GPR_T
);
906 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
913 /* Output an instruction. PLACE is where to put the instruction; if
914 it is NULL, this uses frag_more to get room. IP is the instruction
915 information. ADDRESS_EXPR is an operand of the instruction to be
916 used with RELOC_TYPE. */
919 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
921 struct mips_cl_insn
*ip
;
922 expressionS
*address_expr
;
923 bfd_reloc_code_real_type reloc_type
;
924 boolean unmatched_hi
;
926 register unsigned long prev_pinfo
, pinfo
;
931 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
932 pinfo
= ip
->insn_mo
->pinfo
;
934 if (place
== NULL
&& ! mips_noreorder
)
936 /* If the previous insn required any delay slots, see if we need
937 to insert a NOP or two. There are eight kinds of possible
938 hazards, of which an instruction can have at most one type.
939 (1) a load from memory delay
940 (2) a load from a coprocessor delay
941 (3) an unconditional branch delay
942 (4) a conditional branch delay
943 (5) a move to coprocessor register delay
944 (6) a load coprocessor register from memory delay
945 (7) a coprocessor condition code delay
946 (8) a HI/LO special register delay
948 There are a lot of optimizations we could do that we don't.
949 In particular, we do not, in general, reorder instructions.
950 If you use gcc with optimization, it will reorder
951 instructions and generally do much more optimization then we
952 do here; repeating all that work in the assembler would only
953 benefit hand written assembly code, and does not seem worth
956 /* This is how a NOP is emitted. */
957 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
959 /* The previous insn might require a delay slot, depending upon
960 the contents of the current insn. */
962 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
964 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
966 /* A load from a coprocessor or from memory. All load
967 delays delay the use of general register rt for one
968 instruction on the r3000. The r6000 and r4000 use
970 know (prev_pinfo
& INSN_WRITE_GPR_T
);
971 if (mips_optimize
== 0
972 || insn_uses_reg (ip
,
973 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
978 else if (mips_isa
< 4
979 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
981 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
983 /* A generic coprocessor delay. The previous instruction
984 modified a coprocessor general or control register. If
985 it modified a control register, we need to avoid any
986 coprocessor instruction (this is probably not always
987 required, but it sometimes is). If it modified a general
988 register, we avoid using that register.
990 On the r6000 and r4000 loading a coprocessor register
991 from memory is interlocked, and does not require a delay.
993 This case is not handled very well. There is no special
994 knowledge of CP0 handling, and the coprocessors other
995 than the floating point unit are not distinguished at
997 if (prev_pinfo
& INSN_WRITE_FPR_T
)
999 if (mips_optimize
== 0
1000 || insn_uses_reg (ip
,
1001 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1006 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1008 if (mips_optimize
== 0
1009 || insn_uses_reg (ip
,
1010 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1017 /* We don't know exactly what the previous instruction
1018 does. If the current instruction uses a coprocessor
1019 register, we must insert a NOP. If previous
1020 instruction may set the condition codes, and the
1021 current instruction uses them, we must insert two
1023 if (mips_optimize
== 0
1024 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1025 && (pinfo
& INSN_READ_COND_CODE
)))
1027 else if (pinfo
& INSN_COP
)
1031 else if (mips_isa
< 4
1032 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1034 /* The previous instruction sets the coprocessor condition
1035 codes, but does not require a general coprocessor delay
1036 (this means it is a floating point comparison
1037 instruction). If this instruction uses the condition
1038 codes, we need to insert a single NOP. */
1039 if (mips_optimize
== 0
1040 || (pinfo
& INSN_READ_COND_CODE
))
1043 else if (prev_pinfo
& INSN_READ_LO
)
1045 /* The previous instruction reads the LO register; if the
1046 current instruction writes to the LO register, we must
1047 insert two NOPS. The R4650 and VR4100 have interlocks. */
1049 && (mips_optimize
== 0
1050 || (pinfo
& INSN_WRITE_LO
)))
1053 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1055 /* The previous instruction reads the HI register; if the
1056 current instruction writes to the HI register, we must
1057 insert a NOP. The R4650 and VR4100 have interlocks. */
1059 && (mips_optimize
== 0
1060 || (pinfo
& INSN_WRITE_HI
)))
1064 /* There are two cases which require two intervening
1065 instructions: 1) setting the condition codes using a move to
1066 coprocessor instruction which requires a general coprocessor
1067 delay and then reading the condition codes 2) reading the HI
1068 or LO register and then writing to it (except on the R4650,
1069 and VR4100 which have interlocks). If we are not already
1070 emitting a NOP instruction, we must check for these cases
1071 compared to the instruction previous to the previous
1075 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1076 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1077 && (pinfo
& INSN_READ_COND_CODE
))
1078 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1079 && (pinfo
& INSN_WRITE_LO
)
1081 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1082 && (pinfo
& INSN_WRITE_HI
)
1086 /* If we are being given a nop instruction, don't bother with
1087 one of the nops we would otherwise output. This will only
1088 happen when a nop instruction is used with mips_optimize set
1090 if (nops
> 0 && ip
->insn_opcode
== 0)
1093 /* Now emit the right number of NOP instructions. */
1098 for (i
= 0; i
< nops
; i
++)
1102 listing_prev_line ();
1103 /* We may be at the start of a variant frag. In case we
1104 are, make sure there is enough space for the frag
1105 after the frags created by listing_prev_line. The
1106 argument to frag_grow here must be at least as large
1107 as the argument to all other calls to frag_grow in
1108 this file. We don't have to worry about being in the
1109 middle of a variant frag, because the variants insert
1110 all needed nop instructions themselves. */
1113 if (insn_label
!= NULL
)
1115 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1116 insn_label
->sy_frag
= frag_now
;
1117 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1127 if (address_expr
!= NULL
)
1129 if (address_expr
->X_op
== O_constant
)
1134 ip
->insn_opcode
|= address_expr
->X_add_number
;
1137 case BFD_RELOC_LO16
:
1138 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1141 case BFD_RELOC_MIPS_JMP
:
1142 case BFD_RELOC_16_PCREL_S2
:
1151 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1153 /* Don't generate a reloc if we are writing into a variant
1157 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1159 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1163 struct mips_hi_fixup
*hi_fixup
;
1165 assert (reloc_type
== BFD_RELOC_HI16_S
);
1166 hi_fixup
= ((struct mips_hi_fixup
*)
1167 xmalloc (sizeof (struct mips_hi_fixup
)));
1168 hi_fixup
->fixp
= fixp
;
1169 hi_fixup
->seg
= now_seg
;
1170 hi_fixup
->next
= mips_hi_fixup_list
;
1171 mips_hi_fixup_list
= hi_fixup
;
1177 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1179 /* Update the register mask information. */
1180 if (pinfo
& INSN_WRITE_GPR_D
)
1181 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1182 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1183 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1184 if (pinfo
& INSN_READ_GPR_S
)
1185 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1186 if (pinfo
& INSN_WRITE_GPR_31
)
1187 mips_gprmask
|= 1 << 31;
1188 if (pinfo
& INSN_WRITE_FPR_D
)
1189 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1190 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1191 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1192 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1193 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1194 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1195 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1196 if (pinfo
& INSN_COP
)
1198 /* We don't keep enough information to sort these cases out. */
1200 /* Never set the bit for $0, which is always zero. */
1201 mips_gprmask
&=~ 1 << 0;
1203 if (place
== NULL
&& ! mips_noreorder
)
1205 /* Filling the branch delay slot is more complex. We try to
1206 switch the branch with the previous instruction, which we can
1207 do if the previous instruction does not set up a condition
1208 that the branch tests and if the branch is not itself the
1209 target of any branch. */
1210 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1211 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1213 if (mips_optimize
< 2
1214 /* If we have seen .set volatile or .set nomove, don't
1217 /* If we had to emit any NOP instructions, then we
1218 already know we can not swap. */
1220 /* If we don't even know the previous insn, we can not
1222 || ! prev_insn_valid
1223 /* If the previous insn is already in a branch delay
1224 slot, then we can not swap. */
1225 || prev_insn_is_delay_slot
1226 /* If the previous previous insn was in a .set
1227 noreorder, we can't swap. Actually, the MIPS
1228 assembler will swap in this situation. However, gcc
1229 configured -with-gnu-as will generate code like
1235 in which we can not swap the bne and INSN. If gcc is
1236 not configured -with-gnu-as, it does not output the
1237 .set pseudo-ops. We don't have to check
1238 prev_insn_unreordered, because prev_insn_valid will
1239 be 0 in that case. We don't want to use
1240 prev_prev_insn_valid, because we do want to be able
1241 to swap at the start of a function. */
1242 || prev_prev_insn_unreordered
1243 /* If the branch is itself the target of a branch, we
1244 can not swap. We cheat on this; all we check for is
1245 whether there is a label on this instruction. If
1246 there are any branches to anything other than a
1247 label, users must use .set noreorder. */
1248 || insn_label
!= NULL
1249 /* If the previous instruction is in a variant frag, we
1250 can not do the swap. */
1251 || prev_insn_frag
->fr_type
== rs_machine_dependent
1252 /* If the branch reads the condition codes, we don't
1253 even try to swap, because in the sequence
1258 we can not swap, and I don't feel like handling that
1261 && (pinfo
& INSN_READ_COND_CODE
))
1262 /* We can not swap with an instruction that requires a
1263 delay slot, becase the target of the branch might
1264 interfere with that instruction. */
1267 & (INSN_LOAD_COPROC_DELAY
1268 | INSN_COPROC_MOVE_DELAY
1269 | INSN_WRITE_COND_CODE
)))
1276 & (INSN_LOAD_MEMORY_DELAY
1277 | INSN_COPROC_MEMORY_DELAY
)))
1278 /* We can not swap with a branch instruction. */
1280 & (INSN_UNCOND_BRANCH_DELAY
1281 | INSN_COND_BRANCH_DELAY
1282 | INSN_COND_BRANCH_LIKELY
))
1283 /* We do not swap with a trap instruction, since it
1284 complicates trap handlers to have the trap
1285 instruction be in a delay slot. */
1286 || (prev_pinfo
& INSN_TRAP
)
1287 /* If the branch reads a register that the previous
1288 instruction sets, we can not swap. */
1289 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1290 && insn_uses_reg (ip
,
1291 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1294 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1295 && insn_uses_reg (ip
,
1296 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1299 /* If the branch writes a register that the previous
1300 instruction sets, we can not swap (we know that
1301 branches write only to RD or to $31). */
1302 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1303 && (((pinfo
& INSN_WRITE_GPR_D
)
1304 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1305 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1306 || ((pinfo
& INSN_WRITE_GPR_31
)
1307 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1310 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1311 && (((pinfo
& INSN_WRITE_GPR_D
)
1312 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1313 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1314 || ((pinfo
& INSN_WRITE_GPR_31
)
1315 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1318 /* If the branch writes a register that the previous
1319 instruction reads, we can not swap (we know that
1320 branches only write to RD or to $31). */
1321 || ((pinfo
& INSN_WRITE_GPR_D
)
1322 && insn_uses_reg (&prev_insn
,
1323 ((ip
->insn_opcode
>> OP_SH_RD
)
1326 || ((pinfo
& INSN_WRITE_GPR_31
)
1327 && insn_uses_reg (&prev_insn
, 31, 0))
1328 /* If we are generating embedded PIC code, the branch
1329 might be expanded into a sequence which uses $at, so
1330 we can't swap with an instruction which reads it. */
1331 || (mips_pic
== EMBEDDED_PIC
1332 && insn_uses_reg (&prev_insn
, AT
, 0))
1333 /* If the previous previous instruction has a load
1334 delay, and sets a register that the branch reads, we
1337 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1339 && (prev_prev_insn
.insn_mo
->pinfo
1340 & INSN_LOAD_MEMORY_DELAY
)))
1341 && insn_uses_reg (ip
,
1342 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1346 /* We could do even better for unconditional branches to
1347 portions of this object file; we could pick up the
1348 instruction at the destination, put it in the delay
1349 slot, and bump the destination address. */
1351 /* Update the previous insn information. */
1352 prev_prev_insn
= *ip
;
1353 prev_insn
.insn_mo
= &dummy_opcode
;
1360 /* It looks like we can actually do the swap. */
1361 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1362 memcpy (temp
, prev_f
, 4);
1363 memcpy (prev_f
, f
, 4);
1364 memcpy (f
, temp
, 4);
1367 prev_insn_fixp
->fx_frag
= frag_now
;
1368 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1372 fixp
->fx_frag
= prev_insn_frag
;
1373 fixp
->fx_where
= prev_insn_where
;
1375 /* Update the previous insn information; leave prev_insn
1377 prev_prev_insn
= *ip
;
1379 prev_insn_is_delay_slot
= 1;
1381 /* If that was an unconditional branch, forget the previous
1382 insn information. */
1383 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1385 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1386 prev_insn
.insn_mo
= &dummy_opcode
;
1389 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1391 /* We don't yet optimize a branch likely. What we should do
1392 is look at the target, copy the instruction found there
1393 into the delay slot, and increment the branch to jump to
1394 the next instruction. */
1396 /* Update the previous insn information. */
1397 prev_prev_insn
= *ip
;
1398 prev_insn
.insn_mo
= &dummy_opcode
;
1402 /* Update the previous insn information. */
1404 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1406 prev_prev_insn
= prev_insn
;
1409 /* Any time we see a branch, we always fill the delay slot
1410 immediately; since this insn is not a branch, we know it
1411 is not in a delay slot. */
1412 prev_insn_is_delay_slot
= 0;
1415 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1416 prev_insn_unreordered
= 0;
1417 prev_insn_frag
= frag_now
;
1418 prev_insn_where
= f
- frag_now
->fr_literal
;
1419 prev_insn_fixp
= fixp
;
1420 prev_insn_valid
= 1;
1423 /* We just output an insn, so the next one doesn't have a label. */
1427 /* This function forgets that there was any previous instruction or
1431 mips_no_prev_insn ()
1433 prev_insn
.insn_mo
= &dummy_opcode
;
1434 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1435 prev_insn_valid
= 0;
1436 prev_insn_is_delay_slot
= 0;
1437 prev_insn_unreordered
= 0;
1438 prev_prev_insn_unreordered
= 0;
1442 /* This function must be called whenever we turn on noreorder or emit
1443 something other than instructions. It inserts any NOPS which might
1444 be needed by the previous instruction, and clears the information
1445 kept for the previous instructions. */
1450 if (! mips_noreorder
)
1456 && (prev_insn
.insn_mo
->pinfo
1457 & (INSN_LOAD_COPROC_DELAY
1458 | INSN_COPROC_MOVE_DELAY
1459 | INSN_WRITE_COND_CODE
)))
1461 && (prev_insn
.insn_mo
->pinfo
1465 && (prev_insn
.insn_mo
->pinfo
1466 & (INSN_LOAD_MEMORY_DELAY
1467 | INSN_COPROC_MEMORY_DELAY
))))
1471 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1473 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1474 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1477 else if ((mips_isa
< 4
1478 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1480 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1481 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1486 if (insn_label
!= NULL
)
1488 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1489 insn_label
->sy_frag
= frag_now
;
1490 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1495 mips_no_prev_insn ();
1498 /* Build an instruction created by a macro expansion. This is passed
1499 a pointer to the count of instructions created so far, an
1500 expression, the name of the instruction to build, an operand format
1501 string, and corresponding arguments. */
1505 macro_build (char *place
,
1513 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1522 struct mips_cl_insn insn
;
1523 bfd_reloc_code_real_type r
;
1527 va_start (args
, fmt
);
1533 * If the macro is about to expand into a second instruction,
1534 * print a warning if needed. We need to pass ip as a parameter
1535 * to generate a better warning message here...
1537 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1538 as_warn ("Macro instruction expanded into multiple instructions");
1541 *counter
+= 1; /* bump instruction counter */
1543 r
= BFD_RELOC_UNUSED
;
1544 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1545 assert (insn
.insn_mo
);
1546 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1548 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1549 || insn
.insn_mo
->pinfo
== INSN_MACRO
1550 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1552 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1554 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1556 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1558 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1560 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1564 assert (insn
.insn_mo
->name
);
1565 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1567 insn
.insn_opcode
= insn
.insn_mo
->match
;
1583 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1589 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1594 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1599 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1606 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1610 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1614 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1621 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1627 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1628 assert (r
== BFD_RELOC_MIPS_GPREL
1629 || r
== BFD_RELOC_MIPS_LITERAL
1630 || r
== BFD_RELOC_LO16
1631 || r
== BFD_RELOC_MIPS_GOT16
1632 || r
== BFD_RELOC_MIPS_CALL16
1633 || r
== BFD_RELOC_MIPS_GOT_LO16
1634 || r
== BFD_RELOC_MIPS_CALL_LO16
1635 || (ep
->X_op
== O_subtract
1636 && now_seg
== text_section
1637 && r
== BFD_RELOC_PCREL_LO16
));
1641 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1643 && (ep
->X_op
== O_constant
1644 || (ep
->X_op
== O_symbol
1645 && (r
== BFD_RELOC_HI16_S
1646 || r
== BFD_RELOC_HI16
1647 || r
== BFD_RELOC_MIPS_GOT_HI16
1648 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1649 || (ep
->X_op
== O_subtract
1650 && now_seg
== text_section
1651 && r
== BFD_RELOC_PCREL_HI16_S
)));
1652 if (ep
->X_op
== O_constant
)
1654 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1656 r
= BFD_RELOC_UNUSED
;
1661 assert (ep
!= NULL
);
1663 * This allows macro() to pass an immediate expression for
1664 * creating short branches without creating a symbol.
1665 * Note that the expression still might come from the assembly
1666 * input, in which case the value is not checked for range nor
1667 * is a relocation entry generated (yuck).
1669 if (ep
->X_op
== O_constant
)
1671 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1675 r
= BFD_RELOC_16_PCREL_S2
;
1679 assert (ep
!= NULL
);
1680 r
= BFD_RELOC_MIPS_JMP
;
1689 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1691 append_insn (place
, &insn
, ep
, r
, false);
1695 * Generate a "lui" instruction.
1698 macro_build_lui (place
, counter
, ep
, regnum
)
1704 expressionS high_expr
;
1705 struct mips_cl_insn insn
;
1706 bfd_reloc_code_real_type r
;
1707 CONST
char *name
= "lui";
1708 CONST
char *fmt
= "t,u";
1714 high_expr
.X_op
= O_constant
;
1715 high_expr
.X_add_number
= ep
->X_add_number
;
1718 if (high_expr
.X_op
== O_constant
)
1720 /* we can compute the instruction now without a relocation entry */
1721 if (high_expr
.X_add_number
& 0x8000)
1722 high_expr
.X_add_number
+= 0x10000;
1723 high_expr
.X_add_number
=
1724 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1725 r
= BFD_RELOC_UNUSED
;
1729 assert (ep
->X_op
== O_symbol
);
1730 /* _gp_disp is a special case, used from s_cpload. */
1731 assert (mips_pic
== NO_PIC
1732 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1733 r
= BFD_RELOC_HI16_S
;
1737 * If the macro is about to expand into a second instruction,
1738 * print a warning if needed. We need to pass ip as a parameter
1739 * to generate a better warning message here...
1741 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1742 as_warn ("Macro instruction expanded into multiple instructions");
1745 *counter
+= 1; /* bump instruction counter */
1747 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1748 assert (insn
.insn_mo
);
1749 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1750 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1752 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1753 if (r
== BFD_RELOC_UNUSED
)
1755 insn
.insn_opcode
|= high_expr
.X_add_number
;
1756 append_insn (place
, &insn
, NULL
, r
, false);
1759 append_insn (place
, &insn
, &high_expr
, r
, false);
1763 * Generates code to set the $at register to true (one)
1764 * if reg is less than the immediate expression.
1767 set_at (counter
, reg
, unsignedp
)
1772 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1773 macro_build ((char *) NULL
, counter
, &imm_expr
,
1774 unsignedp
? "sltiu" : "slti",
1775 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1778 load_register (counter
, AT
, &imm_expr
, 0);
1779 macro_build ((char *) NULL
, counter
, NULL
,
1780 unsignedp
? "sltu" : "slt",
1781 "d,v,t", AT
, reg
, AT
);
1785 /* Warn if an expression is not a constant. */
1788 check_absolute_expr (ip
, ex
)
1789 struct mips_cl_insn
*ip
;
1792 if (ex
->X_op
!= O_constant
)
1793 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1797 * This routine generates the least number of instructions neccessary to load
1798 * an absolute expression value into a register.
1801 load_register (counter
, reg
, ep
, dbl
)
1808 expressionS hi32
, lo32
, tmp
;
1810 if (ep
->X_op
!= O_big
)
1812 assert (ep
->X_op
== O_constant
);
1813 if (ep
->X_add_number
< 0x8000
1814 && (ep
->X_add_number
>= 0
1815 || (ep
->X_add_number
>= -0x8000
1818 || sizeof (ep
->X_add_number
) > 4))))
1820 /* We can handle 16 bit signed values with an addiu to
1821 $zero. No need to ever use daddiu here, since $zero and
1822 the result are always correct in 32 bit mode. */
1823 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1824 (int) BFD_RELOC_LO16
);
1827 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1829 /* We can handle 16 bit unsigned values with an ori to
1831 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1832 (int) BFD_RELOC_LO16
);
1835 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1836 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1837 == ~ (offsetT
) 0x7fffffff))
1840 || sizeof (ep
->X_add_number
) > 4
1841 || (ep
->X_add_number
& 0x80000000) == 0))
1843 /* 32 bit values require an lui. */
1844 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1845 (int) BFD_RELOC_HI16
);
1846 if ((ep
->X_add_number
& 0xffff) != 0)
1847 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1848 (int) BFD_RELOC_LO16
);
1853 /* 32 bit value with high bit set being loaded into a 64 bit
1854 register. We can't use lui, because that would
1855 incorrectly set the 32 high bits. */
1856 generic_bignum
[3] = 0;
1857 generic_bignum
[2] = 0;
1858 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1859 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1861 tmp
.X_add_number
= 4;
1866 /* The value is larger than 32 bits. */
1870 as_bad ("Number larger than 32 bits");
1871 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1872 (int) BFD_RELOC_LO16
);
1876 if (ep
->X_op
!= O_big
)
1880 hi32
.X_add_number
>>= shift
;
1881 hi32
.X_add_number
&= 0xffffffff;
1882 if ((hi32
.X_add_number
& 0x80000000) != 0)
1883 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1885 lo32
.X_add_number
&= 0xffffffff;
1889 assert (ep
->X_add_number
> 2);
1890 if (ep
->X_add_number
== 3)
1891 generic_bignum
[3] = 0;
1892 else if (ep
->X_add_number
> 4)
1893 as_bad ("Number larger than 64 bits");
1894 lo32
.X_op
= O_constant
;
1895 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1896 hi32
.X_op
= O_constant
;
1897 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1900 if (hi32
.X_add_number
== 0)
1904 if (hi32
.X_add_number
== 0xffffffff)
1906 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1908 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1909 (int) BFD_RELOC_LO16
);
1912 if (lo32
.X_add_number
& 0x80000000)
1914 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1915 (int) BFD_RELOC_HI16
);
1916 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1917 (int) BFD_RELOC_LO16
);
1921 load_register (counter
, reg
, &hi32
, 0);
1924 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1928 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1937 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1939 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1940 (int) BFD_RELOC_HI16
);
1941 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1948 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1953 mid16
.X_add_number
>>= 16;
1954 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1955 freg
, (int) BFD_RELOC_LO16
);
1956 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1960 if ((lo32
.X_add_number
& 0xffff) != 0)
1961 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1962 (int) BFD_RELOC_LO16
);
1965 /* Load an address into a register. */
1968 load_address (counter
, reg
, ep
)
1975 if (ep
->X_op
!= O_constant
1976 && ep
->X_op
!= O_symbol
)
1978 as_bad ("expression too complex");
1979 ep
->X_op
= O_constant
;
1982 if (ep
->X_op
== O_constant
)
1984 load_register (counter
, reg
, ep
, 0);
1988 if (mips_pic
== NO_PIC
)
1990 /* If this is a reference to a GP relative symbol, we want
1991 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1993 lui $reg,<sym> (BFD_RELOC_HI16_S)
1994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1995 If we have an addend, we always use the latter form. */
1996 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
1997 || nopic_need_relax (ep
->X_add_symbol
))
2002 macro_build ((char *) NULL
, counter
, ep
,
2003 mips_isa
< 3 ? "addiu" : "daddiu",
2004 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2005 p
= frag_var (rs_machine_dependent
, 8, 0,
2006 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2007 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2009 macro_build_lui (p
, counter
, ep
, reg
);
2012 macro_build (p
, counter
, ep
,
2013 mips_isa
< 3 ? "addiu" : "daddiu",
2014 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2016 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2020 /* If this is a reference to an external symbol, we want
2021 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2023 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2025 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2026 If there is a constant, it must be added in after. */
2027 ex
.X_add_number
= ep
->X_add_number
;
2028 ep
->X_add_number
= 0;
2030 macro_build ((char *) NULL
, counter
, ep
,
2031 mips_isa
< 3 ? "lw" : "ld",
2032 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2033 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2034 p
= frag_var (rs_machine_dependent
, 4, 0,
2035 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2036 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2037 macro_build (p
, counter
, ep
,
2038 mips_isa
< 3 ? "addiu" : "daddiu",
2039 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2040 if (ex
.X_add_number
!= 0)
2042 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2043 as_bad ("PIC code offset overflow (max 16 signed bits)");
2044 ex
.X_op
= O_constant
;
2045 macro_build ((char *) NULL
, counter
, &ex
,
2046 mips_isa
< 3 ? "addiu" : "daddiu",
2047 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2050 else if (mips_pic
== SVR4_PIC
)
2055 /* This is the large GOT case. If this is a reference to an
2056 external symbol, we want
2057 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2059 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2060 Otherwise, for a reference to a local symbol, we want
2061 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2063 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2064 If there is a constant, it must be added in after. */
2065 ex
.X_add_number
= ep
->X_add_number
;
2066 ep
->X_add_number
= 0;
2067 if (reg_needs_delay (GP
))
2072 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2073 (int) BFD_RELOC_MIPS_GOT_HI16
);
2074 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2075 mips_isa
< 3 ? "addu" : "daddu",
2076 "d,v,t", reg
, reg
, GP
);
2077 macro_build ((char *) NULL
, counter
, ep
,
2078 mips_isa
< 3 ? "lw" : "ld",
2079 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2080 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2081 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2082 mips_warn_about_macros
),
2083 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2086 /* We need a nop before loading from $gp. This special
2087 check is required because the lui which starts the main
2088 instruction stream does not refer to $gp, and so will not
2089 insert the nop which may be required. */
2090 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2093 macro_build (p
, counter
, ep
,
2094 mips_isa
< 3 ? "lw" : "ld",
2095 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2097 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2099 macro_build (p
, counter
, ep
,
2100 mips_isa
< 3 ? "addiu" : "daddiu",
2101 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2102 if (ex
.X_add_number
!= 0)
2104 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2105 as_bad ("PIC code offset overflow (max 16 signed bits)");
2106 ex
.X_op
= O_constant
;
2107 macro_build ((char *) NULL
, counter
, &ex
,
2108 mips_isa
< 3 ? "addiu" : "daddiu",
2109 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2112 else if (mips_pic
== EMBEDDED_PIC
)
2115 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2117 macro_build ((char *) NULL
, counter
, ep
,
2118 mips_isa
< 3 ? "addiu" : "daddiu",
2119 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2127 * This routine implements the seemingly endless macro or synthesized
2128 * instructions and addressing modes in the mips assembly language. Many
2129 * of these macros are simple and are similar to each other. These could
2130 * probably be handled by some kind of table or grammer aproach instead of
2131 * this verbose method. Others are not simple macros but are more like
2132 * optimizing code generation.
2133 * One interesting optimization is when several store macros appear
2134 * consecutivly that would load AT with the upper half of the same address.
2135 * The ensuing load upper instructions are ommited. This implies some kind
2136 * of global optimization. We currently only optimize within a single macro.
2137 * For many of the load and store macros if the address is specified as a
2138 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2139 * first load register 'at' with zero and use it as the base register. The
2140 * mips assembler simply uses register $zero. Just one tiny optimization
2145 struct mips_cl_insn
*ip
;
2147 register int treg
, sreg
, dreg
, breg
;
2162 bfd_reloc_code_real_type r
;
2164 int hold_mips_optimize
;
2166 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2167 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2168 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2169 mask
= ip
->insn_mo
->mask
;
2171 expr1
.X_op
= O_constant
;
2172 expr1
.X_op_symbol
= NULL
;
2173 expr1
.X_add_symbol
= NULL
;
2174 expr1
.X_add_number
= 1;
2186 mips_emit_delays ();
2188 mips_any_noreorder
= 1;
2190 expr1
.X_add_number
= 8;
2191 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2193 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2195 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2196 macro_build ((char *) NULL
, &icnt
, NULL
,
2197 dbl
? "dsub" : "sub",
2198 "d,v,t", dreg
, 0, sreg
);
2221 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2223 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2224 (int) BFD_RELOC_LO16
);
2227 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2228 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2247 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2249 if (mask
!= M_NOR_I
)
2250 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2251 sreg
, (int) BFD_RELOC_LO16
);
2254 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2255 treg
, sreg
, (int) BFD_RELOC_LO16
);
2256 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2262 load_register (&icnt
, AT
, &imm_expr
, 0);
2263 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2280 if (imm_expr
.X_add_number
== 0)
2282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2286 load_register (&icnt
, AT
, &imm_expr
, 0);
2287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2296 likely
? "bgezl" : "bgez",
2302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2303 likely
? "blezl" : "blez",
2307 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2309 likely
? "beql" : "beq",
2316 /* check for > max integer */
2317 maxnum
= 0x7fffffff;
2325 if (imm_expr
.X_add_number
>= maxnum
2326 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2329 /* result is always false */
2332 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2333 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2337 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2338 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2343 imm_expr
.X_add_number
++;
2347 if (mask
== M_BGEL_I
)
2349 if (imm_expr
.X_add_number
== 0)
2351 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2352 likely
? "bgezl" : "bgez",
2356 if (imm_expr
.X_add_number
== 1)
2358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2359 likely
? "bgtzl" : "bgtz",
2363 maxnum
= 0x7fffffff;
2371 maxnum
= - maxnum
- 1;
2372 if (imm_expr
.X_add_number
<= maxnum
2373 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2376 /* result is always true */
2377 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2378 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2381 set_at (&icnt
, sreg
, 0);
2382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2383 likely
? "beql" : "beq",
2394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2395 likely
? "beql" : "beq",
2399 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2401 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2402 likely
? "beql" : "beq",
2409 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2411 imm_expr
.X_add_number
++;
2415 if (mask
== M_BGEUL_I
)
2417 if (imm_expr
.X_add_number
== 0)
2419 if (imm_expr
.X_add_number
== 1)
2421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2422 likely
? "bnel" : "bne",
2426 set_at (&icnt
, sreg
, 1);
2427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2428 likely
? "beql" : "beq",
2437 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2438 likely
? "bgtzl" : "bgtz",
2444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2445 likely
? "bltzl" : "bltz",
2449 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2451 likely
? "bnel" : "bne",
2460 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2461 likely
? "bnel" : "bne",
2467 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2470 likely
? "bnel" : "bne",
2479 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2480 likely
? "blezl" : "blez",
2486 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2487 likely
? "bgezl" : "bgez",
2491 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2493 likely
? "beql" : "beq",
2500 maxnum
= 0x7fffffff;
2508 if (imm_expr
.X_add_number
>= maxnum
2509 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2511 imm_expr
.X_add_number
++;
2515 if (mask
== M_BLTL_I
)
2517 if (imm_expr
.X_add_number
== 0)
2519 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2520 likely
? "bltzl" : "bltz",
2524 if (imm_expr
.X_add_number
== 1)
2526 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2527 likely
? "blezl" : "blez",
2531 set_at (&icnt
, sreg
, 0);
2532 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2533 likely
? "bnel" : "bne",
2542 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2543 likely
? "beql" : "beq",
2549 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2551 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2552 likely
? "beql" : "beq",
2559 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2561 imm_expr
.X_add_number
++;
2565 if (mask
== M_BLTUL_I
)
2567 if (imm_expr
.X_add_number
== 0)
2569 if (imm_expr
.X_add_number
== 1)
2571 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2572 likely
? "beql" : "beq",
2576 set_at (&icnt
, sreg
, 1);
2577 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2578 likely
? "bnel" : "bne",
2587 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2588 likely
? "bltzl" : "bltz",
2594 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2595 likely
? "bgtzl" : "bgtz",
2599 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2601 likely
? "bnel" : "bne",
2612 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2613 likely
? "bnel" : "bne",
2617 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2620 likely
? "bnel" : "bne",
2636 as_warn ("Divide by zero.");
2638 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2640 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2644 mips_emit_delays ();
2646 mips_any_noreorder
= 1;
2647 macro_build ((char *) NULL
, &icnt
, NULL
,
2648 dbl
? "ddiv" : "div",
2649 "z,s,t", sreg
, treg
);
2651 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2654 expr1
.X_add_number
= 8;
2655 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2656 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2657 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2659 expr1
.X_add_number
= -1;
2660 macro_build ((char *) NULL
, &icnt
, &expr1
,
2661 dbl
? "daddiu" : "addiu",
2662 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2663 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2664 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2667 expr1
.X_add_number
= 1;
2668 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2669 (int) BFD_RELOC_LO16
);
2670 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2675 expr1
.X_add_number
= 0x80000000;
2676 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2677 (int) BFD_RELOC_HI16
);
2680 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2683 expr1
.X_add_number
= 8;
2684 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2685 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2686 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2689 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2728 if (imm_expr
.X_add_number
== 0)
2730 as_warn ("Divide by zero.");
2732 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2734 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2737 if (imm_expr
.X_add_number
== 1)
2739 if (strcmp (s2
, "mflo") == 0)
2740 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2743 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2746 if (imm_expr
.X_add_number
== -1
2747 && s
[strlen (s
) - 1] != 'u')
2749 if (strcmp (s2
, "mflo") == 0)
2752 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2755 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2759 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2763 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2764 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2765 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2784 mips_emit_delays ();
2786 mips_any_noreorder
= 1;
2787 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2789 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2792 expr1
.X_add_number
= 8;
2793 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2794 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2795 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2798 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2804 /* Load the address of a symbol into a register. If breg is not
2805 zero, we then add a base register to it. */
2807 /* When generating embedded PIC code, we permit expressions of
2810 where bar is an address in the .text section. These are used
2811 when getting the addresses of functions. We don't permit
2812 X_add_number to be non-zero, because if the symbol is
2813 external the relaxing code needs to know that any addend is
2814 purely the offset to X_op_symbol. */
2815 if (mips_pic
== EMBEDDED_PIC
2816 && offset_expr
.X_op
== O_subtract
2817 && now_seg
== text_section
2818 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2819 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2820 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2821 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2822 ->sy_value
.X_add_symbol
)
2825 && offset_expr
.X_add_number
== 0)
2827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2828 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2830 mips_isa
< 3 ? "addiu" : "daddiu",
2831 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2835 if (offset_expr
.X_op
!= O_symbol
2836 && offset_expr
.X_op
!= O_constant
)
2838 as_bad ("expression too complex");
2839 offset_expr
.X_op
= O_constant
;
2853 if (offset_expr
.X_op
== O_constant
)
2854 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2855 else if (mips_pic
== NO_PIC
)
2857 /* If this is a reference to an GP relative symbol, we want
2858 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2860 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2861 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2862 If we have a constant, we need two instructions anyhow,
2863 so we may as well always use the latter form. */
2864 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2865 || nopic_need_relax (offset_expr
.X_add_symbol
))
2870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2871 mips_isa
< 3 ? "addiu" : "daddiu",
2872 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2873 p
= frag_var (rs_machine_dependent
, 8, 0,
2874 RELAX_ENCODE (4, 8, 0, 4, 0,
2875 mips_warn_about_macros
),
2876 offset_expr
.X_add_symbol
, (long) 0,
2879 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2882 macro_build (p
, &icnt
, &offset_expr
,
2883 mips_isa
< 3 ? "addiu" : "daddiu",
2884 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2886 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2888 /* If this is a reference to an external symbol, and there
2889 is no constant, we want
2890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2891 For a local symbol, we want
2892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2894 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2896 If we have a small constant, and this is a reference to
2897 an external symbol, we want
2898 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2900 addiu $tempreg,$tempreg,<constant>
2901 For a local symbol, we want the same instruction
2902 sequence, but we output a BFD_RELOC_LO16 reloc on the
2905 If we have a large constant, and this is a reference to
2906 an external symbol, we want
2907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2908 lui $at,<hiconstant>
2909 addiu $at,$at,<loconstant>
2910 addu $tempreg,$tempreg,$at
2911 For a local symbol, we want the same instruction
2912 sequence, but we output a BFD_RELOC_LO16 reloc on the
2913 addiu instruction. */
2914 expr1
.X_add_number
= offset_expr
.X_add_number
;
2915 offset_expr
.X_add_number
= 0;
2917 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2919 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2920 if (expr1
.X_add_number
== 0)
2928 /* We're going to put in an addu instruction using
2929 tempreg, so we may as well insert the nop right
2931 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2935 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2936 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2938 ? mips_warn_about_macros
2940 offset_expr
.X_add_symbol
, (long) 0,
2944 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2947 macro_build (p
, &icnt
, &expr1
,
2948 mips_isa
< 3 ? "addiu" : "daddiu",
2949 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2950 /* FIXME: If breg == 0, and the next instruction uses
2951 $tempreg, then if this variant case is used an extra
2952 nop will be generated. */
2954 else if (expr1
.X_add_number
>= -0x8000
2955 && expr1
.X_add_number
< 0x8000)
2957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2959 macro_build ((char *) NULL
, &icnt
, &expr1
,
2960 mips_isa
< 3 ? "addiu" : "daddiu",
2961 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2962 (void) frag_var (rs_machine_dependent
, 0, 0,
2963 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2964 offset_expr
.X_add_symbol
, (long) 0,
2971 /* If we are going to add in a base register, and the
2972 target register and the base register are the same,
2973 then we are using AT as a temporary register. Since
2974 we want to load the constant into AT, we add our
2975 current AT (from the global offset table) and the
2976 register into the register now, and pretend we were
2977 not using a base register. */
2982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2984 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2985 mips_isa
< 3 ? "addu" : "daddu",
2986 "d,v,t", treg
, AT
, breg
);
2992 /* Set mips_optimize around the lui instruction to avoid
2993 inserting an unnecessary nop after the lw. */
2994 hold_mips_optimize
= mips_optimize
;
2996 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2997 mips_optimize
= hold_mips_optimize
;
2999 macro_build ((char *) NULL
, &icnt
, &expr1
,
3000 mips_isa
< 3 ? "addiu" : "daddiu",
3001 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3003 mips_isa
< 3 ? "addu" : "daddu",
3004 "d,v,t", tempreg
, tempreg
, AT
);
3005 (void) frag_var (rs_machine_dependent
, 0, 0,
3006 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3007 offset_expr
.X_add_symbol
, (long) 0,
3012 else if (mips_pic
== SVR4_PIC
)
3016 /* This is the large GOT case. If this is a reference to an
3017 external symbol, and there is no constant, we want
3018 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3019 addu $tempreg,$tempreg,$gp
3020 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3021 For a local symbol, we want
3022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3024 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3026 If we have a small constant, and this is a reference to
3027 an external symbol, we want
3028 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3029 addu $tempreg,$tempreg,$gp
3030 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3032 addiu $tempreg,$tempreg,<constant>
3033 For a local symbol, we want
3034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3036 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3038 If we have a large constant, and this is a reference to
3039 an external symbol, we want
3040 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3041 addu $tempreg,$tempreg,$gp
3042 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3043 lui $at,<hiconstant>
3044 addiu $at,$at,<loconstant>
3045 addu $tempreg,$tempreg,$at
3046 For a local symbol, we want
3047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3048 lui $at,<hiconstant>
3049 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3050 addu $tempreg,$tempreg,$at
3052 expr1
.X_add_number
= offset_expr
.X_add_number
;
3053 offset_expr
.X_add_number
= 0;
3055 if (reg_needs_delay (GP
))
3059 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3060 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3062 mips_isa
< 3 ? "addu" : "daddu",
3063 "d,v,t", tempreg
, tempreg
, GP
);
3064 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3066 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3068 if (expr1
.X_add_number
== 0)
3076 /* We're going to put in an addu instruction using
3077 tempreg, so we may as well insert the nop right
3079 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3084 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3085 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3088 ? mips_warn_about_macros
3090 offset_expr
.X_add_symbol
, (long) 0,
3093 else if (expr1
.X_add_number
>= -0x8000
3094 && expr1
.X_add_number
< 0x8000)
3096 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3098 macro_build ((char *) NULL
, &icnt
, &expr1
,
3099 mips_isa
< 3 ? "addiu" : "daddiu",
3100 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3102 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3103 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3105 ? mips_warn_about_macros
3107 offset_expr
.X_add_symbol
, (long) 0,
3114 /* If we are going to add in a base register, and the
3115 target register and the base register are the same,
3116 then we are using AT as a temporary register. Since
3117 we want to load the constant into AT, we add our
3118 current AT (from the global offset table) and the
3119 register into the register now, and pretend we were
3120 not using a base register. */
3128 assert (tempreg
== AT
);
3129 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3132 mips_isa
< 3 ? "addu" : "daddu",
3133 "d,v,t", treg
, AT
, breg
);
3138 /* Set mips_optimize around the lui instruction to avoid
3139 inserting an unnecessary nop after the lw. */
3140 hold_mips_optimize
= mips_optimize
;
3142 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3143 mips_optimize
= hold_mips_optimize
;
3145 macro_build ((char *) NULL
, &icnt
, &expr1
,
3146 mips_isa
< 3 ? "addiu" : "daddiu",
3147 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3148 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3149 mips_isa
< 3 ? "addu" : "daddu",
3150 "d,v,t", dreg
, dreg
, AT
);
3152 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3153 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3156 ? mips_warn_about_macros
3158 offset_expr
.X_add_symbol
, (long) 0,
3166 /* This is needed because this instruction uses $gp, but
3167 the first instruction on the main stream does not. */
3168 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3171 macro_build (p
, &icnt
, &offset_expr
,
3173 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3175 if (expr1
.X_add_number
>= -0x8000
3176 && expr1
.X_add_number
< 0x8000)
3178 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3180 macro_build (p
, &icnt
, &expr1
,
3181 mips_isa
< 3 ? "addiu" : "daddiu",
3182 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3183 /* FIXME: If add_number is 0, and there was no base
3184 register, the external symbol case ended with a load,
3185 so if the symbol turns out to not be external, and
3186 the next instruction uses tempreg, an unnecessary nop
3187 will be inserted. */
3193 /* We must add in the base register now, as in the
3194 external symbol case. */
3195 assert (tempreg
== AT
);
3196 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3198 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3199 mips_isa
< 3 ? "addu" : "daddu",
3200 "d,v,t", treg
, AT
, breg
);
3203 /* We set breg to 0 because we have arranged to add
3204 it in in both cases. */
3208 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3210 macro_build (p
, &icnt
, &expr1
,
3211 mips_isa
< 3 ? "addiu" : "daddiu",
3212 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3214 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3215 mips_isa
< 3 ? "addu" : "daddu",
3216 "d,v,t", tempreg
, tempreg
, AT
);
3220 else if (mips_pic
== EMBEDDED_PIC
)
3223 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3226 mips_isa
< 3 ? "addiu" : "daddiu",
3227 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3233 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3234 mips_isa
< 3 ? "addu" : "daddu",
3235 "d,v,t", treg
, tempreg
, breg
);
3243 /* The j instruction may not be used in PIC code, since it
3244 requires an absolute address. We convert it to a b
3246 if (mips_pic
== NO_PIC
)
3247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3249 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3252 /* The jal instructions must be handled as macros because when
3253 generating PIC code they expand to multi-instruction
3254 sequences. Normally they are simple instructions. */
3259 if (mips_pic
== NO_PIC
3260 || mips_pic
== EMBEDDED_PIC
)
3261 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3263 else if (mips_pic
== SVR4_PIC
)
3265 if (sreg
!= PIC_CALL_REG
)
3266 as_warn ("MIPS PIC call to register other than $25");
3268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3270 if (mips_cprestore_offset
< 0)
3271 as_warn ("No .cprestore pseudo-op used in PIC code");
3274 expr1
.X_add_number
= mips_cprestore_offset
;
3275 macro_build ((char *) NULL
, &icnt
, &expr1
,
3276 mips_isa
< 3 ? "lw" : "ld",
3277 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3286 if (mips_pic
== NO_PIC
)
3287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3288 else if (mips_pic
== SVR4_PIC
)
3290 /* If this is a reference to an external symbol, and we are
3291 using a small GOT, we want
3292 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3296 lw $gp,cprestore($sp)
3297 The cprestore value is set using the .cprestore
3298 pseudo-op. If we are using a big GOT, we want
3299 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3301 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3305 lw $gp,cprestore($sp)
3306 If the symbol is not external, we want
3307 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3309 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3312 lw $gp,cprestore($sp) */
3316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3317 mips_isa
< 3 ? "lw" : "ld",
3318 "t,o(b)", PIC_CALL_REG
,
3319 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3322 p
= frag_var (rs_machine_dependent
, 4, 0,
3323 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3324 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3330 if (reg_needs_delay (GP
))
3334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3335 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3337 mips_isa
< 3 ? "addu" : "daddu",
3338 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3339 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3340 mips_isa
< 3 ? "lw" : "ld",
3341 "t,o(b)", PIC_CALL_REG
,
3342 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3345 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3346 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3348 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3351 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3354 macro_build (p
, &icnt
, &offset_expr
,
3355 mips_isa
< 3 ? "lw" : "ld",
3356 "t,o(b)", PIC_CALL_REG
,
3357 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3359 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3362 macro_build (p
, &icnt
, &offset_expr
,
3363 mips_isa
< 3 ? "addiu" : "daddiu",
3364 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3365 (int) BFD_RELOC_LO16
);
3366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3367 "jalr", "s", PIC_CALL_REG
);
3368 if (mips_cprestore_offset
< 0)
3369 as_warn ("No .cprestore pseudo-op used in PIC code");
3373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3375 expr1
.X_add_number
= mips_cprestore_offset
;
3376 macro_build ((char *) NULL
, &icnt
, &expr1
,
3377 mips_isa
< 3 ? "lw" : "ld",
3378 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3382 else if (mips_pic
== EMBEDDED_PIC
)
3384 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3385 /* The linker may expand the call to a longer sequence which
3386 uses $at, so we must break rather than return. */
3462 if (breg
== treg
|| coproc
|| lr
)
3531 if (mask
== M_LWC1_AB
3532 || mask
== M_SWC1_AB
3533 || mask
== M_LDC1_AB
3534 || mask
== M_SDC1_AB
3543 if (offset_expr
.X_op
!= O_constant
3544 && offset_expr
.X_op
!= O_symbol
)
3546 as_bad ("expression too complex");
3547 offset_expr
.X_op
= O_constant
;
3550 /* A constant expression in PIC code can be handled just as it
3551 is in non PIC code. */
3552 if (mips_pic
== NO_PIC
3553 || offset_expr
.X_op
== O_constant
)
3555 /* If this is a reference to a GP relative symbol, and there
3556 is no base register, we want
3557 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3558 Otherwise, if there is no base register, we want
3559 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3560 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3561 If we have a constant, we need two instructions anyhow,
3562 so we always use the latter form.
3564 If we have a base register, and this is a reference to a
3565 GP relative symbol, we want
3566 addu $tempreg,$breg,$gp
3567 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3569 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3570 addu $tempreg,$tempreg,$breg
3571 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3572 With a constant we always use the latter case. */
3575 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3576 || nopic_need_relax (offset_expr
.X_add_symbol
))
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3582 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3583 p
= frag_var (rs_machine_dependent
, 8, 0,
3584 RELAX_ENCODE (4, 8, 0, 4, 0,
3585 (mips_warn_about_macros
3586 || (used_at
&& mips_noat
))),
3587 offset_expr
.X_add_symbol
, (long) 0,
3591 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3594 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3595 (int) BFD_RELOC_LO16
, tempreg
);
3599 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3600 || nopic_need_relax (offset_expr
.X_add_symbol
))
3605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3606 mips_isa
< 3 ? "addu" : "daddu",
3607 "d,v,t", tempreg
, breg
, GP
);
3608 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3609 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3610 p
= frag_var (rs_machine_dependent
, 12, 0,
3611 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3612 offset_expr
.X_add_symbol
, (long) 0,
3615 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3618 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3619 mips_isa
< 3 ? "addu" : "daddu",
3620 "d,v,t", tempreg
, tempreg
, breg
);
3623 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3624 (int) BFD_RELOC_LO16
, tempreg
);
3627 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3629 /* If this is a reference to an external symbol, we want
3630 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3632 <op> $treg,0($tempreg)
3634 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3636 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3637 <op> $treg,0($tempreg)
3638 If there is a base register, we add it to $tempreg before
3639 the <op>. If there is a constant, we stick it in the
3640 <op> instruction. We don't handle constants larger than
3641 16 bits, because we have no way to load the upper 16 bits
3642 (actually, we could handle them for the subset of cases
3643 in which we are not using $at). */
3644 assert (offset_expr
.X_op
== O_symbol
);
3645 expr1
.X_add_number
= offset_expr
.X_add_number
;
3646 offset_expr
.X_add_number
= 0;
3647 if (expr1
.X_add_number
< -0x8000
3648 || expr1
.X_add_number
>= 0x8000)
3649 as_bad ("PIC code offset overflow (max 16 signed bits)");
3651 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3652 mips_isa
< 3 ? "lw" : "ld",
3653 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3655 p
= frag_var (rs_machine_dependent
, 4, 0,
3656 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3657 offset_expr
.X_add_symbol
, (long) 0,
3659 macro_build (p
, &icnt
, &offset_expr
,
3660 mips_isa
< 3 ? "addiu" : "daddiu",
3661 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3664 mips_isa
< 3 ? "addu" : "daddu",
3665 "d,v,t", tempreg
, tempreg
, breg
);
3666 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3667 (int) BFD_RELOC_LO16
, tempreg
);
3669 else if (mips_pic
== SVR4_PIC
)
3673 /* If this is a reference to an external symbol, we want
3674 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3675 addu $tempreg,$tempreg,$gp
3676 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3677 <op> $treg,0($tempreg)
3679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3681 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3682 <op> $treg,0($tempreg)
3683 If there is a base register, we add it to $tempreg before
3684 the <op>. If there is a constant, we stick it in the
3685 <op> instruction. We don't handle constants larger than
3686 16 bits, because we have no way to load the upper 16 bits
3687 (actually, we could handle them for the subset of cases
3688 in which we are not using $at). */
3689 assert (offset_expr
.X_op
== O_symbol
);
3690 expr1
.X_add_number
= offset_expr
.X_add_number
;
3691 offset_expr
.X_add_number
= 0;
3692 if (expr1
.X_add_number
< -0x8000
3693 || expr1
.X_add_number
>= 0x8000)
3694 as_bad ("PIC code offset overflow (max 16 signed bits)");
3695 if (reg_needs_delay (GP
))
3700 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3701 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3703 mips_isa
< 3 ? "addu" : "daddu",
3704 "d,v,t", tempreg
, tempreg
, GP
);
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3706 mips_isa
< 3 ? "lw" : "ld",
3707 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3709 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3710 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3711 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3714 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3717 macro_build (p
, &icnt
, &offset_expr
,
3718 mips_isa
< 3 ? "lw" : "ld",
3719 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3721 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3723 macro_build (p
, &icnt
, &offset_expr
,
3724 mips_isa
< 3 ? "addiu" : "daddiu",
3725 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3728 mips_isa
< 3 ? "addu" : "daddu",
3729 "d,v,t", tempreg
, tempreg
, breg
);
3730 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3731 (int) BFD_RELOC_LO16
, tempreg
);
3733 else if (mips_pic
== EMBEDDED_PIC
)
3735 /* If there is no base register, we want
3736 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3737 If there is a base register, we want
3738 addu $tempreg,$breg,$gp
3739 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3741 assert (offset_expr
.X_op
== O_symbol
);
3744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3745 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3750 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3751 mips_isa
< 3 ? "addu" : "daddu",
3752 "d,v,t", tempreg
, breg
, GP
);
3753 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3754 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3767 load_register (&icnt
, treg
, &imm_expr
, 0);
3771 load_register (&icnt
, treg
, &imm_expr
, 1);
3775 if (imm_expr
.X_op
== O_constant
)
3777 load_register (&icnt
, AT
, &imm_expr
, 0);
3778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3779 "mtc1", "t,G", AT
, treg
);
3784 assert (offset_expr
.X_op
== O_symbol
3785 && strcmp (segment_name (S_GET_SEGMENT
3786 (offset_expr
.X_add_symbol
)),
3788 && offset_expr
.X_add_number
== 0);
3789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3790 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3795 /* We know that sym is in the .rdata section. First we get the
3796 upper 16 bits of the address. */
3797 if (mips_pic
== NO_PIC
)
3799 /* FIXME: This won't work for a 64 bit address. */
3800 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3802 else if (mips_pic
== SVR4_PIC
)
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3805 mips_isa
< 3 ? "lw" : "ld",
3806 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3808 else if (mips_pic
== EMBEDDED_PIC
)
3810 /* For embedded PIC we pick up the entire address off $gp in
3811 a single instruction. */
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3813 mips_isa
< 3 ? "addiu" : "daddiu",
3814 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3815 offset_expr
.X_op
= O_constant
;
3816 offset_expr
.X_add_number
= 0;
3821 /* Now we load the register(s). */
3823 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3824 treg
, (int) BFD_RELOC_LO16
, AT
);
3827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3828 treg
, (int) BFD_RELOC_LO16
, AT
);
3831 /* FIXME: How in the world do we deal with the possible
3833 offset_expr
.X_add_number
+= 4;
3834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3835 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3839 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3840 does not become a variant frag. */
3841 frag_wane (frag_now
);
3847 assert (offset_expr
.X_op
== O_symbol
3848 && offset_expr
.X_add_number
== 0);
3849 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3850 if (strcmp (s
, ".lit8") == 0)
3854 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3855 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3859 r
= BFD_RELOC_MIPS_LITERAL
;
3864 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3865 if (mips_pic
== SVR4_PIC
)
3866 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3867 mips_isa
< 3 ? "lw" : "ld",
3868 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3871 /* FIXME: This won't work for a 64 bit address. */
3872 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3878 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3880 /* To avoid confusion in tc_gen_reloc, we must ensure
3881 that this does not become a variant frag. */
3882 frag_wane (frag_now
);
3893 /* Even on a big endian machine $fn comes before $fn+1. We have
3894 to adjust when loading from memory. */
3897 assert (mips_isa
< 2);
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3899 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3901 /* FIXME: A possible overflow which I don't know how to deal
3903 offset_expr
.X_add_number
+= 4;
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3905 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3908 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3909 does not become a variant frag. */
3910 frag_wane (frag_now
);
3919 * The MIPS assembler seems to check for X_add_number not
3920 * being double aligned and generating:
3923 * addiu at,at,%lo(foo+1)
3926 * But, the resulting address is the same after relocation so why
3927 * generate the extra instruction?
3974 if (offset_expr
.X_op
!= O_symbol
3975 && offset_expr
.X_op
!= O_constant
)
3977 as_bad ("expression too complex");
3978 offset_expr
.X_op
= O_constant
;
3981 /* Even on a big endian machine $fn comes before $fn+1. We have
3982 to adjust when loading from memory. We set coproc if we must
3983 load $fn+1 first. */
3984 if (byte_order
== LITTLE_ENDIAN
)
3987 if (mips_pic
== NO_PIC
3988 || offset_expr
.X_op
== O_constant
)
3990 /* If this is a reference to a GP relative symbol, we want
3991 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3992 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3993 If we have a base register, we use this
3995 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3996 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3997 If this is not a GP relative symbol, we want
3998 lui $at,<sym> (BFD_RELOC_HI16_S)
3999 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4000 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4001 If there is a base register, we add it to $at after the
4002 lui instruction. If there is a constant, we always use
4004 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4005 || nopic_need_relax (offset_expr
.X_add_symbol
))
4024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4025 mips_isa
< 3 ? "addu" : "daddu",
4026 "d,v,t", AT
, breg
, GP
);
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4033 coproc
? treg
+ 1 : treg
,
4034 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4035 offset_expr
.X_add_number
+= 4;
4037 /* Set mips_optimize to 2 to avoid inserting an
4039 hold_mips_optimize
= mips_optimize
;
4041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4042 coproc
? treg
: treg
+ 1,
4043 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4044 mips_optimize
= hold_mips_optimize
;
4046 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4047 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4048 used_at
&& mips_noat
),
4049 offset_expr
.X_add_symbol
, (long) 0,
4052 /* We just generated two relocs. When tc_gen_reloc
4053 handles this case, it will skip the first reloc and
4054 handle the second. The second reloc already has an
4055 extra addend of 4, which we added above. We must
4056 subtract it out, and then subtract another 4 to make
4057 the first reloc come out right. The second reloc
4058 will come out right because we are going to add 4 to
4059 offset_expr when we build its instruction below. */
4060 offset_expr
.X_add_number
-= 8;
4061 offset_expr
.X_op
= O_constant
;
4063 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4068 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4069 mips_isa
< 3 ? "addu" : "daddu",
4070 "d,v,t", AT
, breg
, AT
);
4074 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4075 coproc
? treg
+ 1 : treg
,
4076 (int) BFD_RELOC_LO16
, AT
);
4079 /* FIXME: How do we handle overflow here? */
4080 offset_expr
.X_add_number
+= 4;
4081 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4082 coproc
? treg
: treg
+ 1,
4083 (int) BFD_RELOC_LO16
, AT
);
4085 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4089 /* If this is a reference to an external symbol, we want
4090 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4095 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4097 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4098 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4099 If there is a base register we add it to $at before the
4100 lwc1 instructions. If there is a constant we include it
4101 in the lwc1 instructions. */
4103 expr1
.X_add_number
= offset_expr
.X_add_number
;
4104 offset_expr
.X_add_number
= 0;
4105 if (expr1
.X_add_number
< -0x8000
4106 || expr1
.X_add_number
>= 0x8000 - 4)
4107 as_bad ("PIC code offset overflow (max 16 signed bits)");
4112 frag_grow (24 + off
);
4113 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4114 mips_isa
< 3 ? "lw" : "ld",
4115 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4119 mips_isa
< 3 ? "addu" : "daddu",
4120 "d,v,t", AT
, breg
, AT
);
4121 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4122 coproc
? treg
+ 1 : treg
,
4123 (int) BFD_RELOC_LO16
, AT
);
4124 expr1
.X_add_number
+= 4;
4126 /* Set mips_optimize to 2 to avoid inserting an undesired
4128 hold_mips_optimize
= mips_optimize
;
4130 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4131 coproc
? treg
: treg
+ 1,
4132 (int) BFD_RELOC_LO16
, AT
);
4133 mips_optimize
= hold_mips_optimize
;
4135 (void) frag_var (rs_machine_dependent
, 0, 0,
4136 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4137 offset_expr
.X_add_symbol
, (long) 0,
4140 else if (mips_pic
== SVR4_PIC
)
4144 /* If this is a reference to an external symbol, we want
4145 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4147 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4152 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4154 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4156 If there is a base register we add it to $at before the
4157 lwc1 instructions. If there is a constant we include it
4158 in the lwc1 instructions. */
4160 expr1
.X_add_number
= offset_expr
.X_add_number
;
4161 offset_expr
.X_add_number
= 0;
4162 if (expr1
.X_add_number
< -0x8000
4163 || expr1
.X_add_number
>= 0x8000 - 4)
4164 as_bad ("PIC code offset overflow (max 16 signed bits)");
4165 if (reg_needs_delay (GP
))
4174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4175 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4177 mips_isa
< 3 ? "addu" : "daddu",
4178 "d,v,t", AT
, AT
, GP
);
4179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4180 mips_isa
< 3 ? "lw" : "ld",
4181 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4185 mips_isa
< 3 ? "addu" : "daddu",
4186 "d,v,t", AT
, breg
, AT
);
4187 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4188 coproc
? treg
+ 1 : treg
,
4189 (int) BFD_RELOC_LO16
, AT
);
4190 expr1
.X_add_number
+= 4;
4192 /* Set mips_optimize to 2 to avoid inserting an undesired
4194 hold_mips_optimize
= mips_optimize
;
4196 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4197 coproc
? treg
: treg
+ 1,
4198 (int) BFD_RELOC_LO16
, AT
);
4199 mips_optimize
= hold_mips_optimize
;
4200 expr1
.X_add_number
-= 4;
4202 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4203 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4204 8 + gpdel
+ off
, 1, 0),
4205 offset_expr
.X_add_symbol
, (long) 0,
4209 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4212 macro_build (p
, &icnt
, &offset_expr
,
4213 mips_isa
< 3 ? "lw" : "ld",
4214 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4216 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4220 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4221 mips_isa
< 3 ? "addu" : "daddu",
4222 "d,v,t", AT
, breg
, AT
);
4225 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4226 coproc
? treg
+ 1 : treg
,
4227 (int) BFD_RELOC_LO16
, AT
);
4229 expr1
.X_add_number
+= 4;
4231 /* Set mips_optimize to 2 to avoid inserting an undesired
4233 hold_mips_optimize
= mips_optimize
;
4235 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4236 coproc
? treg
: treg
+ 1,
4237 (int) BFD_RELOC_LO16
, AT
);
4238 mips_optimize
= hold_mips_optimize
;
4240 else if (mips_pic
== EMBEDDED_PIC
)
4242 /* If there is no base register, we use
4243 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4244 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4245 If we have a base register, we use
4247 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4248 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4257 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4258 mips_isa
< 3 ? "addu" : "daddu",
4259 "d,v,t", AT
, breg
, GP
);
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4265 coproc
? treg
+ 1 : treg
,
4266 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4267 offset_expr
.X_add_number
+= 4;
4268 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4269 coproc
? treg
: treg
+ 1,
4270 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4286 assert (mips_isa
< 3);
4287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4288 (int) BFD_RELOC_LO16
, breg
);
4289 offset_expr
.X_add_number
+= 4;
4290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4291 (int) BFD_RELOC_LO16
, breg
);
4293 #ifdef LOSING_COMPILER
4299 as_warn ("Macro used $at after \".set noat\"");
4304 struct mips_cl_insn
*ip
;
4306 register int treg
, sreg
, dreg
, breg
;
4321 bfd_reloc_code_real_type r
;
4324 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4325 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4326 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4327 mask
= ip
->insn_mo
->mask
;
4329 expr1
.X_op
= O_constant
;
4330 expr1
.X_op_symbol
= NULL
;
4331 expr1
.X_add_symbol
= NULL
;
4332 expr1
.X_add_number
= 1;
4336 #endif /* LOSING_COMPILER */
4341 macro_build ((char *) NULL
, &icnt
, NULL
,
4342 dbl
? "dmultu" : "multu",
4344 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4350 /* The MIPS assembler some times generates shifts and adds. I'm
4351 not trying to be that fancy. GCC should do this for us
4353 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4354 macro_build ((char *) NULL
, &icnt
, NULL
,
4355 dbl
? "dmult" : "mult",
4357 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4363 mips_emit_delays ();
4365 mips_any_noreorder
= 1;
4366 macro_build ((char *) NULL
, &icnt
, NULL
,
4367 dbl
? "dmult" : "mult",
4369 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4370 macro_build ((char *) NULL
, &icnt
, NULL
,
4371 dbl
? "dsra32" : "sra",
4372 "d,w,<", dreg
, dreg
, 31);
4373 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4375 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4378 expr1
.X_add_number
= 8;
4379 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4380 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4381 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4384 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4390 mips_emit_delays ();
4392 mips_any_noreorder
= 1;
4393 macro_build ((char *) NULL
, &icnt
, NULL
,
4394 dbl
? "dmultu" : "multu",
4396 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4397 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4399 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4402 expr1
.X_add_number
= 8;
4403 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4404 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4405 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4411 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4412 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4413 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4415 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4419 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4420 (int) (imm_expr
.X_add_number
& 0x1f));
4421 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4422 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4423 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4427 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4428 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4429 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4431 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4435 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4436 (int) (imm_expr
.X_add_number
& 0x1f));
4437 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4438 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4439 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4443 assert (mips_isa
< 2);
4444 /* Even on a big endian machine $fn comes before $fn+1. We have
4445 to adjust when storing to memory. */
4446 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4447 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4448 (int) BFD_RELOC_LO16
, breg
);
4449 offset_expr
.X_add_number
+= 4;
4450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4451 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4452 (int) BFD_RELOC_LO16
, breg
);
4457 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4458 treg
, (int) BFD_RELOC_LO16
);
4460 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4461 sreg
, (int) BFD_RELOC_LO16
);
4464 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4466 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4467 dreg
, (int) BFD_RELOC_LO16
);
4472 if (imm_expr
.X_add_number
== 0)
4474 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4475 sreg
, (int) BFD_RELOC_LO16
);
4480 as_warn ("Instruction %s: result is always false",
4482 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4485 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4487 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4488 sreg
, (int) BFD_RELOC_LO16
);
4491 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4493 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4494 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4495 mips_isa
< 3 ? "addiu" : "daddiu",
4496 "t,r,j", dreg
, sreg
,
4497 (int) BFD_RELOC_LO16
);
4502 load_register (&icnt
, AT
, &imm_expr
, 0);
4503 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4507 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4508 (int) BFD_RELOC_LO16
);
4513 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4519 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4520 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4521 (int) BFD_RELOC_LO16
);
4524 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4526 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4528 macro_build ((char *) NULL
, &icnt
, &expr1
,
4529 mask
== M_SGE_I
? "slti" : "sltiu",
4530 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4535 load_register (&icnt
, AT
, &imm_expr
, 0);
4536 macro_build ((char *) NULL
, &icnt
, NULL
,
4537 mask
== M_SGE_I
? "slt" : "sltu",
4538 "d,v,t", dreg
, sreg
, AT
);
4541 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4542 (int) BFD_RELOC_LO16
);
4547 case M_SGT
: /* sreg > treg <==> treg < sreg */
4553 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4556 case M_SGT_I
: /* sreg > I <==> I < sreg */
4562 load_register (&icnt
, AT
, &imm_expr
, 0);
4563 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4566 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4572 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4573 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4574 (int) BFD_RELOC_LO16
);
4577 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4583 load_register (&icnt
, AT
, &imm_expr
, 0);
4584 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4585 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4586 (int) BFD_RELOC_LO16
);
4590 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4592 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4593 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4596 load_register (&icnt
, AT
, &imm_expr
, 0);
4597 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4601 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4603 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4604 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4607 load_register (&icnt
, AT
, &imm_expr
, 0);
4608 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4614 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4617 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4621 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4623 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4629 if (imm_expr
.X_add_number
== 0)
4631 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4637 as_warn ("Instruction %s: result is always true",
4639 macro_build ((char *) NULL
, &icnt
, &expr1
,
4640 mips_isa
< 3 ? "addiu" : "daddiu",
4641 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4644 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4646 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4647 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4650 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4652 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4653 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4654 mips_isa
< 3 ? "addiu" : "daddiu",
4655 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4660 load_register (&icnt
, AT
, &imm_expr
, 0);
4661 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4665 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4673 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4675 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4676 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4677 dbl
? "daddi" : "addi",
4678 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4681 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4682 macro_build ((char *) NULL
, &icnt
, NULL
,
4683 dbl
? "dsub" : "sub",
4684 "d,v,t", dreg
, sreg
, AT
);
4690 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4692 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4693 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4694 dbl
? "daddiu" : "addiu",
4695 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4698 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4699 macro_build ((char *) NULL
, &icnt
, NULL
,
4700 dbl
? "dsubu" : "subu",
4701 "d,v,t", dreg
, sreg
, AT
);
4722 load_register (&icnt
, AT
, &imm_expr
, 0);
4723 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4728 assert (mips_isa
< 2);
4729 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4730 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4733 * Is the double cfc1 instruction a bug in the mips assembler;
4734 * or is there a reason for it?
4736 mips_emit_delays ();
4738 mips_any_noreorder
= 1;
4739 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4740 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4741 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4742 expr1
.X_add_number
= 3;
4743 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4744 (int) BFD_RELOC_LO16
);
4745 expr1
.X_add_number
= 2;
4746 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4747 (int) BFD_RELOC_LO16
);
4748 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4749 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4750 macro_build ((char *) NULL
, &icnt
, NULL
,
4751 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4752 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4753 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4763 if (offset_expr
.X_add_number
>= 0x7fff)
4764 as_bad ("operand overflow");
4765 /* avoid load delay */
4766 if (byte_order
== LITTLE_ENDIAN
)
4767 offset_expr
.X_add_number
+= 1;
4768 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4769 (int) BFD_RELOC_LO16
, breg
);
4770 if (byte_order
== LITTLE_ENDIAN
)
4771 offset_expr
.X_add_number
-= 1;
4773 offset_expr
.X_add_number
+= 1;
4774 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4775 (int) BFD_RELOC_LO16
, breg
);
4776 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4777 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4790 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4791 as_bad ("operand overflow");
4792 if (byte_order
== LITTLE_ENDIAN
)
4793 offset_expr
.X_add_number
+= off
;
4794 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4795 (int) BFD_RELOC_LO16
, breg
);
4796 if (byte_order
== LITTLE_ENDIAN
)
4797 offset_expr
.X_add_number
-= off
;
4799 offset_expr
.X_add_number
+= off
;
4800 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4801 (int) BFD_RELOC_LO16
, breg
);
4814 load_address (&icnt
, AT
, &offset_expr
);
4816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4817 mips_isa
< 3 ? "addu" : "daddu",
4818 "d,v,t", AT
, AT
, breg
);
4819 if (byte_order
== LITTLE_ENDIAN
)
4820 expr1
.X_add_number
= off
;
4822 expr1
.X_add_number
= 0;
4823 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4824 (int) BFD_RELOC_LO16
, AT
);
4825 if (byte_order
== LITTLE_ENDIAN
)
4826 expr1
.X_add_number
= 0;
4828 expr1
.X_add_number
= off
;
4829 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4830 (int) BFD_RELOC_LO16
, AT
);
4835 load_address (&icnt
, AT
, &offset_expr
);
4837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4838 mips_isa
< 3 ? "addu" : "daddu",
4839 "d,v,t", AT
, AT
, breg
);
4840 if (byte_order
== BIG_ENDIAN
)
4841 expr1
.X_add_number
= 0;
4842 macro_build ((char *) NULL
, &icnt
, &expr1
,
4843 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4844 (int) BFD_RELOC_LO16
, AT
);
4845 if (byte_order
== BIG_ENDIAN
)
4846 expr1
.X_add_number
= 1;
4848 expr1
.X_add_number
= 0;
4849 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4850 (int) BFD_RELOC_LO16
, AT
);
4851 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4853 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4858 if (offset_expr
.X_add_number
>= 0x7fff)
4859 as_bad ("operand overflow");
4860 if (byte_order
== BIG_ENDIAN
)
4861 offset_expr
.X_add_number
+= 1;
4862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4863 (int) BFD_RELOC_LO16
, breg
);
4864 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4865 if (byte_order
== BIG_ENDIAN
)
4866 offset_expr
.X_add_number
-= 1;
4868 offset_expr
.X_add_number
+= 1;
4869 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4870 (int) BFD_RELOC_LO16
, breg
);
4883 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4884 as_bad ("operand overflow");
4885 if (byte_order
== LITTLE_ENDIAN
)
4886 offset_expr
.X_add_number
+= off
;
4887 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4888 (int) BFD_RELOC_LO16
, breg
);
4889 if (byte_order
== LITTLE_ENDIAN
)
4890 offset_expr
.X_add_number
-= off
;
4892 offset_expr
.X_add_number
+= off
;
4893 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4894 (int) BFD_RELOC_LO16
, breg
);
4907 load_address (&icnt
, AT
, &offset_expr
);
4909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4910 mips_isa
< 3 ? "addu" : "daddu",
4911 "d,v,t", AT
, AT
, breg
);
4912 if (byte_order
== LITTLE_ENDIAN
)
4913 expr1
.X_add_number
= off
;
4915 expr1
.X_add_number
= 0;
4916 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4917 (int) BFD_RELOC_LO16
, AT
);
4918 if (byte_order
== LITTLE_ENDIAN
)
4919 expr1
.X_add_number
= 0;
4921 expr1
.X_add_number
= off
;
4922 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4923 (int) BFD_RELOC_LO16
, AT
);
4927 load_address (&icnt
, AT
, &offset_expr
);
4929 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4930 mips_isa
< 3 ? "addu" : "daddu",
4931 "d,v,t", AT
, AT
, breg
);
4932 if (byte_order
== LITTLE_ENDIAN
)
4933 expr1
.X_add_number
= 0;
4934 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4935 (int) BFD_RELOC_LO16
, AT
);
4936 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4938 if (byte_order
== LITTLE_ENDIAN
)
4939 expr1
.X_add_number
= 1;
4941 expr1
.X_add_number
= 0;
4942 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4943 (int) BFD_RELOC_LO16
, AT
);
4944 if (byte_order
== LITTLE_ENDIAN
)
4945 expr1
.X_add_number
= 0;
4947 expr1
.X_add_number
= 1;
4948 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4949 (int) BFD_RELOC_LO16
, AT
);
4950 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4952 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4957 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4961 as_warn ("Macro used $at after \".set noat\"");
4964 /* This routine assembles an instruction into its binary format. As a
4965 side effect, it sets one of the global variables imm_reloc or
4966 offset_reloc to the type of relocation to do if one of the operands
4967 is an address expression. */
4972 struct mips_cl_insn
*ip
;
4977 struct mips_opcode
*insn
;
4980 unsigned int lastregno
= 0;
4985 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
4997 as_fatal ("Unknown opcode: `%s'", str
);
4999 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5001 as_warn ("`%s' not in hash table.", str
);
5002 insn_error
= "ERROR: Unrecognized opcode";
5010 assert (strcmp (insn
->name
, str
) == 0);
5012 if (insn
->pinfo
== INSN_MACRO
)
5013 insn_isa
= insn
->match
;
5014 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5016 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5018 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5023 if (insn_isa
> mips_isa
5024 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5026 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5028 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5031 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5032 && strcmp (insn
->name
, insn
[1].name
) == 0)
5037 as_warn ("Instruction not supported on this processor");
5041 ip
->insn_opcode
= insn
->match
;
5042 for (args
= insn
->args
;; ++args
)
5048 case '\0': /* end of args */
5061 ip
->insn_opcode
|= lastregno
<< 21;
5066 ip
->insn_opcode
|= lastregno
<< 16;
5070 ip
->insn_opcode
|= lastregno
<< 11;
5076 /* handle optional base register.
5077 Either the base register is omitted or
5078 we must have a left paren. */
5079 /* this is dependent on the next operand specifier
5080 is a 'b' for base register */
5081 assert (args
[1] == 'b');
5085 case ')': /* these must match exactly */
5090 case '<': /* must be at least one digit */
5092 * According to the manual, if the shift amount is greater
5093 * than 31 or less than 0 the the shift amount should be
5094 * mod 32. In reality the mips assembler issues an error.
5095 * We issue a warning and mask out all but the low 5 bits.
5097 my_getExpression (&imm_expr
, s
);
5098 check_absolute_expr (ip
, &imm_expr
);
5099 if ((unsigned long) imm_expr
.X_add_number
> 31)
5101 as_warn ("Improper shift amount (%ld)",
5102 (long) imm_expr
.X_add_number
);
5103 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5105 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5106 imm_expr
.X_op
= O_absent
;
5110 case '>': /* shift amount minus 32 */
5111 my_getExpression (&imm_expr
, s
);
5112 check_absolute_expr (ip
, &imm_expr
);
5113 if ((unsigned long) imm_expr
.X_add_number
< 32
5114 || (unsigned long) imm_expr
.X_add_number
> 63)
5116 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5117 imm_expr
.X_op
= O_absent
;
5121 case 'k': /* cache code */
5122 case 'h': /* prefx code */
5123 my_getExpression (&imm_expr
, s
);
5124 check_absolute_expr (ip
, &imm_expr
);
5125 if ((unsigned long) imm_expr
.X_add_number
> 31)
5127 as_warn ("Invalid value for `%s' (%lu)",
5129 (unsigned long) imm_expr
.X_add_number
);
5130 imm_expr
.X_add_number
&= 0x1f;
5133 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5135 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5136 imm_expr
.X_op
= O_absent
;
5140 case 'c': /* break code */
5141 my_getExpression (&imm_expr
, s
);
5142 check_absolute_expr (ip
, &imm_expr
);
5143 if ((unsigned) imm_expr
.X_add_number
> 1023)
5144 as_warn ("Illegal break code (%ld)",
5145 (long) imm_expr
.X_add_number
);
5146 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5147 imm_expr
.X_op
= O_absent
;
5151 case 'B': /* syscall code */
5152 my_getExpression (&imm_expr
, s
);
5153 check_absolute_expr (ip
, &imm_expr
);
5154 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5155 as_warn ("Illegal syscall code (%ld)",
5156 (long) imm_expr
.X_add_number
);
5157 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5158 imm_expr
.X_op
= O_absent
;
5162 case 'C': /* Coprocessor code */
5163 my_getExpression (&imm_expr
, s
);
5164 check_absolute_expr (ip
, &imm_expr
);
5165 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5167 as_warn ("Coproccesor code > 25 bits (%ld)",
5168 (long) imm_expr
.X_add_number
);
5169 imm_expr
.X_add_number
&= ((1<<25) - 1);
5171 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5172 imm_expr
.X_op
= O_absent
;
5176 case 'b': /* base register */
5177 case 'd': /* destination register */
5178 case 's': /* source register */
5179 case 't': /* target register */
5180 case 'r': /* both target and source */
5181 case 'v': /* both dest and source */
5182 case 'w': /* both dest and target */
5183 case 'E': /* coprocessor target register */
5184 case 'G': /* coprocessor destination register */
5185 case 'x': /* ignore register name */
5186 case 'z': /* must be zero register */
5200 while (isdigit (*s
));
5202 as_bad ("Invalid register number (%d)", regno
);
5204 else if (*args
== 'E' || *args
== 'G')
5208 if (s
[1] == 'f' && s
[2] == 'p')
5213 else if (s
[1] == 's' && s
[2] == 'p')
5218 else if (s
[1] == 'g' && s
[2] == 'p')
5223 else if (s
[1] == 'a' && s
[2] == 't')
5228 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5233 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5241 if (regno
== AT
&& ! mips_noat
)
5242 as_warn ("Used $at without \".set noat\"");
5248 if (c
== 'r' || c
== 'v' || c
== 'w')
5255 /* 'z' only matches $0. */
5256 if (c
== 'z' && regno
!= 0)
5264 ip
->insn_opcode
|= regno
<< 21;
5268 ip
->insn_opcode
|= regno
<< 11;
5273 ip
->insn_opcode
|= regno
<< 16;
5276 /* This case exists because on the r3000 trunc
5277 expands into a macro which requires a gp
5278 register. On the r6000 or r4000 it is
5279 assembled into a single instruction which
5280 ignores the register. Thus the insn version
5281 is MIPS_ISA2 and uses 'x', and the macro
5282 version is MIPS_ISA1 and uses 't'. */
5285 /* This case is for the div instruction, which
5286 acts differently if the destination argument
5287 is $0. This only matches $0, and is checked
5288 outside the switch. */
5299 ip
->insn_opcode
|= lastregno
<< 21;
5302 ip
->insn_opcode
|= lastregno
<< 16;
5307 case 'D': /* floating point destination register */
5308 case 'S': /* floating point source register */
5309 case 'T': /* floating point target register */
5310 case 'R': /* floating point source register */
5314 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5324 while (isdigit (*s
));
5327 as_bad ("Invalid float register number (%d)", regno
);
5329 if ((regno
& 1) != 0
5331 && ! (strcmp (str
, "mtc1") == 0 ||
5332 strcmp (str
, "mfc1") == 0 ||
5333 strcmp (str
, "lwc1") == 0 ||
5334 strcmp (str
, "swc1") == 0))
5335 as_warn ("Float register should be even, was %d",
5343 if (c
== 'V' || c
== 'W')
5353 ip
->insn_opcode
|= regno
<< 6;
5357 ip
->insn_opcode
|= regno
<< 11;
5361 ip
->insn_opcode
|= regno
<< 16;
5364 ip
->insn_opcode
|= regno
<< 21;
5373 ip
->insn_opcode
|= lastregno
<< 11;
5376 ip
->insn_opcode
|= lastregno
<< 16;
5382 my_getExpression (&imm_expr
, s
);
5383 if (imm_expr
.X_op
!= O_big
)
5384 check_absolute_expr (ip
, &imm_expr
);
5389 my_getExpression (&offset_expr
, s
);
5390 imm_reloc
= BFD_RELOC_32
;
5402 unsigned char temp
[8];
5404 unsigned int length
;
5409 /* These only appear as the last operand in an
5410 instruction, and every instruction that accepts
5411 them in any variant accepts them in all variants.
5412 This means we don't have to worry about backing out
5413 any changes if the instruction does not match.
5415 The difference between them is the size of the
5416 floating point constant and where it goes. For 'F'
5417 and 'L' the constant is 64 bits; for 'f' and 'l' it
5418 is 32 bits. Where the constant is placed is based
5419 on how the MIPS assembler does things:
5422 f -- immediate value
5425 The .lit4 and .lit8 sections are only used if
5426 permitted by the -G argument.
5428 When generating embedded PIC code, we use the
5429 .lit8 section but not the .lit4 section (we can do
5430 .lit4 inline easily; we need to put .lit8
5431 somewhere in the data segment, and using .lit8
5432 permits the linker to eventually combine identical
5435 f64
= *args
== 'F' || *args
== 'L';
5437 save_in
= input_line_pointer
;
5438 input_line_pointer
= s
;
5439 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5441 s
= input_line_pointer
;
5442 input_line_pointer
= save_in
;
5443 if (err
!= NULL
&& *err
!= '\0')
5445 as_bad ("Bad floating point constant: %s", err
);
5446 memset (temp
, '\0', sizeof temp
);
5447 length
= f64
? 8 : 4;
5450 assert (length
== (f64
? 8 : 4));
5454 && (! USE_GLOBAL_POINTER_OPT
5455 || mips_pic
== EMBEDDED_PIC
5456 || g_switch_value
< 4)
5459 imm_expr
.X_op
= O_constant
;
5460 if (byte_order
== LITTLE_ENDIAN
)
5461 imm_expr
.X_add_number
=
5462 (((((((int) temp
[3] << 8)
5467 imm_expr
.X_add_number
=
5468 (((((((int) temp
[0] << 8)
5475 const char *newname
;
5478 /* Switch to the right section. */
5480 subseg
= now_subseg
;
5483 default: /* unused default case avoids warnings. */
5485 newname
= RDATA_SECTION_NAME
;
5486 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5490 newname
= RDATA_SECTION_NAME
;
5493 assert (!USE_GLOBAL_POINTER_OPT
5494 || g_switch_value
>= 4);
5498 new_seg
= subseg_new (newname
, (subsegT
) 0);
5499 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5500 bfd_set_section_flags (stdoutput
, new_seg
,
5505 frag_align (*args
== 'l' ? 2 : 3, 0);
5506 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5507 record_alignment (new_seg
, 4);
5509 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5511 as_bad ("Can't use floating point insn in this section");
5513 /* Set the argument to the current address in the
5515 offset_expr
.X_op
= O_symbol
;
5516 offset_expr
.X_add_symbol
=
5517 symbol_new ("L0\001", now_seg
,
5518 (valueT
) frag_now_fix (), frag_now
);
5519 offset_expr
.X_add_number
= 0;
5521 /* Put the floating point number into the section. */
5522 p
= frag_more ((int) length
);
5523 memcpy (p
, temp
, length
);
5525 /* Switch back to the original section. */
5526 subseg_set (seg
, subseg
);
5531 case 'i': /* 16 bit unsigned immediate */
5532 case 'j': /* 16 bit signed immediate */
5533 imm_reloc
= BFD_RELOC_LO16
;
5534 c
= my_getSmallExpression (&imm_expr
, s
);
5539 if (imm_expr
.X_op
== O_constant
)
5540 imm_expr
.X_add_number
=
5541 (imm_expr
.X_add_number
>> 16) & 0xffff;
5544 imm_reloc
= BFD_RELOC_HI16_S
;
5545 imm_unmatched_hi
= true;
5548 imm_reloc
= BFD_RELOC_HI16
;
5551 else if (imm_expr
.X_op
!= O_big
)
5552 check_absolute_expr (ip
, &imm_expr
);
5555 if (imm_expr
.X_op
== O_big
5556 || imm_expr
.X_add_number
< 0
5557 || imm_expr
.X_add_number
>= 0x10000)
5559 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5560 !strcmp (insn
->name
, insn
[1].name
))
5562 as_bad ("16 bit expression not in range 0..65535");
5570 /* The upper bound should be 0x8000, but
5571 unfortunately the MIPS assembler accepts numbers
5572 from 0x8000 to 0xffff and sign extends them, and
5573 we want to be compatible. We only permit this
5574 extended range for an instruction which does not
5575 provide any further alternates, since those
5576 alternates may handle other cases. People should
5577 use the numbers they mean, rather than relying on
5578 a mysterious sign extension. */
5579 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5580 strcmp (insn
->name
, insn
[1].name
) == 0);
5585 if (imm_expr
.X_op
== O_big
5586 || imm_expr
.X_add_number
< -0x8000
5587 || imm_expr
.X_add_number
>= max
5589 && imm_expr
.X_add_number
< 0
5591 && imm_expr
.X_unsigned
5592 && sizeof (imm_expr
.X_add_number
) <= 4))
5596 as_bad ("16 bit expression not in range -32768..32767");
5602 case 'o': /* 16 bit offset */
5603 c
= my_getSmallExpression (&offset_expr
, s
);
5605 /* If this value won't fit into a 16 bit offset, then go
5606 find a macro that will generate the 32 bit offset
5607 code pattern. As a special hack, we accept the
5608 difference of two local symbols as a constant. This
5609 is required to suppose embedded PIC switches, which
5610 use an instruction which looks like
5611 lw $4,$L12-$LS12($4)
5612 The problem with handling this in a more general
5613 fashion is that the macro function doesn't expect to
5614 see anything which can be handled in a single
5615 constant instruction. */
5617 && (offset_expr
.X_op
!= O_constant
5618 || offset_expr
.X_add_number
>= 0x8000
5619 || offset_expr
.X_add_number
< -0x8000)
5620 && (mips_pic
!= EMBEDDED_PIC
5621 || offset_expr
.X_op
!= O_subtract
5622 || now_seg
!= text_section
5623 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5627 offset_reloc
= BFD_RELOC_LO16
;
5628 if (c
== 'h' || c
== 'H')
5630 assert (offset_expr
.X_op
== O_constant
);
5631 offset_expr
.X_add_number
=
5632 (offset_expr
.X_add_number
>> 16) & 0xffff;
5637 case 'p': /* pc relative offset */
5638 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5639 my_getExpression (&offset_expr
, s
);
5643 case 'u': /* upper 16 bits */
5644 c
= my_getSmallExpression (&imm_expr
, s
);
5645 if (imm_expr
.X_op
== O_constant
5646 && (imm_expr
.X_add_number
< 0
5647 || imm_expr
.X_add_number
>= 0x10000))
5648 as_bad ("lui expression not in range 0..65535");
5649 imm_reloc
= BFD_RELOC_LO16
;
5654 if (imm_expr
.X_op
== O_constant
)
5655 imm_expr
.X_add_number
=
5656 (imm_expr
.X_add_number
>> 16) & 0xffff;
5659 imm_reloc
= BFD_RELOC_HI16_S
;
5660 imm_unmatched_hi
= true;
5663 imm_reloc
= BFD_RELOC_HI16
;
5669 case 'a': /* 26 bit address */
5670 my_getExpression (&offset_expr
, s
);
5672 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5675 case 'N': /* 3 bit branch condition code */
5676 case 'M': /* 3 bit compare condition code */
5677 my_getExpression (&imm_expr
, s
);
5678 check_absolute_expr (ip
, &imm_expr
);
5679 if ((unsigned long) imm_expr
.X_add_number
> 7)
5681 as_warn ("Condition code > 7 (%ld)",
5682 (long) imm_expr
.X_add_number
);
5683 imm_expr
.X_add_number
&= 7;
5686 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5688 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5689 imm_expr
.X_op
= O_absent
;
5694 fprintf (stderr
, "bad char = '%c'\n", *args
);
5699 /* Args don't match. */
5700 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5701 !strcmp (insn
->name
, insn
[1].name
))
5707 insn_error
= "ERROR: Illegal operands";
5716 my_getSmallExpression (ep
, str
)
5727 ((str
[1] == 'h' && str
[2] == 'i')
5728 || (str
[1] == 'H' && str
[2] == 'I')
5729 || (str
[1] == 'l' && str
[2] == 'o'))
5741 * A small expression may be followed by a base register.
5742 * Scan to the end of this operand, and then back over a possible
5743 * base register. Then scan the small expression up to that
5744 * point. (Based on code in sparc.c...)
5746 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5748 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5750 if (isdigit (sp
[-2]))
5752 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5754 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5760 else if (sp
- 5 >= str
5763 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5764 || (sp
[-3] == 's' && sp
[-2] == 'p')
5765 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5766 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5772 /* no expression means zero offset */
5775 /* %xx(reg) is an error */
5776 ep
->X_op
= O_absent
;
5781 ep
->X_op
= O_constant
;
5784 ep
->X_add_symbol
= NULL
;
5785 ep
->X_op_symbol
= NULL
;
5786 ep
->X_add_number
= 0;
5791 my_getExpression (ep
, str
);
5798 my_getExpression (ep
, str
);
5799 return c
; /* => %hi or %lo encountered */
5803 my_getExpression (ep
, str
)
5809 save_in
= input_line_pointer
;
5810 input_line_pointer
= str
;
5812 expr_end
= input_line_pointer
;
5813 input_line_pointer
= save_in
;
5816 /* Turn a string in input_line_pointer into a floating point constant
5817 of type type, and store the appropriate bytes in *litP. The number
5818 of LITTLENUMS emitted is stored in *sizeP . An error message is
5819 returned, or NULL on OK. */
5822 md_atof (type
, litP
, sizeP
)
5828 LITTLENUM_TYPE words
[4];
5844 return "bad call to md_atof";
5847 t
= atof_ieee (input_line_pointer
, type
, words
);
5849 input_line_pointer
= t
;
5853 if (byte_order
== LITTLE_ENDIAN
)
5855 for (i
= prec
- 1; i
>= 0; i
--)
5857 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5863 for (i
= 0; i
< prec
; i
++)
5865 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5874 md_number_to_chars (buf
, val
, n
)
5882 number_to_chars_littleendian (buf
, val
, n
);
5886 number_to_chars_bigendian (buf
, val
, n
);
5894 CONST
char *md_shortopts
= "O::g::G:";
5896 struct option md_longopts
[] = {
5897 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5898 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5899 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5900 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5901 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5902 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5903 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5904 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5905 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5906 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5907 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5908 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5909 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5910 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5911 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5912 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5913 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5914 {"break", no_argument
, NULL
, OPTION_BREAK
},
5915 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5916 #define OPTION_EB (OPTION_MD_BASE + 11)
5917 {"EB", no_argument
, NULL
, OPTION_EB
},
5918 #define OPTION_EL (OPTION_MD_BASE + 12)
5919 {"EL", no_argument
, NULL
, OPTION_EL
},
5920 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5921 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5922 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5923 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5924 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5925 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5926 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5927 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5928 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5929 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5930 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5931 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5933 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5934 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5935 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5937 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5938 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5939 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5940 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5943 {NULL
, no_argument
, NULL
, 0}
5945 size_t md_longopts_size
= sizeof(md_longopts
);
5948 md_parse_option (c
, arg
)
5963 target_big_endian
= 1;
5967 target_big_endian
= 0;
5971 if (arg
&& arg
[1] == '0')
5981 mips_debug
= atoi (arg
);
5982 /* When the MIPS assembler sees -g or -g2, it does not do
5983 optimizations which limit full symbolic debugging. We take
5984 that to be equivalent to -O0. */
5985 if (mips_debug
== 2)
6017 /* Identify the processor type */
6019 if (strcmp (p
, "default") == 0
6020 || strcmp (p
, "DEFAULT") == 0)
6026 /* We need to cope with the various "vr" prefixes for the 4300
6028 if (*p
== 'v' || *p
== 'V')
6034 if (*p
== 'r' || *p
== 'R')
6041 if (strcmp (p
, "10000") == 0
6042 || strcmp (p
, "10k") == 0
6043 || strcmp (p
, "10K") == 0)
6048 if (strcmp (p
, "2000") == 0
6049 || strcmp (p
, "2k") == 0
6050 || strcmp (p
, "2K") == 0)
6055 if (strcmp (p
, "3000") == 0
6056 || strcmp (p
, "3k") == 0
6057 || strcmp (p
, "3K") == 0)
6062 if (strcmp (p
, "4000") == 0
6063 || strcmp (p
, "4k") == 0
6064 || strcmp (p
, "4K") == 0)
6066 else if (strcmp (p
, "4100") == 0)
6072 else if (strcmp (p
, "4300") == 0)
6074 else if (strcmp (p
, "4400") == 0)
6076 else if (strcmp (p
, "4600") == 0)
6078 else if (strcmp (p
, "4650") == 0)
6084 else if (strcmp (p
, "4010") == 0)
6093 if (strcmp (p
, "6000") == 0
6094 || strcmp (p
, "6k") == 0
6095 || strcmp (p
, "6K") == 0)
6100 if (strcmp (p
, "8000") == 0
6101 || strcmp (p
, "8k") == 0
6102 || strcmp (p
, "8K") == 0)
6107 if (strcmp (p
, "orion") == 0)
6112 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6114 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6120 as_bad ("invalid architecture -mcpu=%s", arg
);
6131 case OPTION_NO_M4650
:
6139 case OPTION_NO_M4010
:
6147 case OPTION_NO_M4100
:
6151 case OPTION_MEMBEDDED_PIC
:
6152 mips_pic
= EMBEDDED_PIC
;
6153 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6155 as_bad ("-G may not be used with embedded PIC code");
6158 g_switch_value
= 0x7fffffff;
6161 /* When generating ELF code, we permit -KPIC and -call_shared to
6162 select SVR4_PIC, and -non_shared to select no PIC. This is
6163 intended to be compatible with Irix 5. */
6164 case OPTION_CALL_SHARED
:
6165 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6167 as_bad ("-call_shared is supported only for ELF format");
6170 mips_pic
= SVR4_PIC
;
6171 if (g_switch_seen
&& g_switch_value
!= 0)
6173 as_bad ("-G may not be used with SVR4 PIC code");
6179 case OPTION_NON_SHARED
:
6180 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6182 as_bad ("-non_shared is supported only for ELF format");
6188 /* The -xgot option tells the assembler to use 32 offsets when
6189 accessing the got in SVR4_PIC mode. It is for Irix
6196 if (! USE_GLOBAL_POINTER_OPT
)
6198 as_bad ("-G is not supported for this configuration");
6201 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6203 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6207 g_switch_value
= atoi (arg
);
6219 md_show_usage (stream
)
6224 -membedded-pic generate embedded position independent code\n\
6225 -EB generate big endian output\n\
6226 -EL generate little endian output\n\
6227 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6228 -G NUM allow referencing objects up to NUM bytes\n\
6229 implicitly with the gp register [default 8]\n");
6231 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6232 -mips2, -mcpu=r6000 generate code for r6000\n\
6233 -mips3, -mcpu=r4000 generate code for r4000\n\
6234 -mips4, -mcpu=r8000 generate code for r8000\n\
6235 -mcpu=vr4300 generate code for vr4300\n\
6236 -mcpu=vr4100 generate code for vr4100\n\
6237 -m4650 permit R4650 instructions\n\
6238 -no-m4650 do not permit R4650 instructions\n\
6239 -m4010 permit R4010 instructions\n\
6240 -no-m4010 do not permit R4010 instructions\n\
6241 -m4100 permit VR4100 instructions\n\
6242 -no-m4100 do not permit VR4100 instructions\n");
6244 -O0 remove unneeded NOPs, do not swap branches\n\
6245 -O remove unneeded NOPs and swap branches\n\
6246 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6247 --break, --no-trap break exception on div by 0 and mult overflow\n");
6250 -KPIC, -call_shared generate SVR4 position independent code\n\
6251 -non_shared do not generate position independent code\n\
6252 -xgot assume a 32 bit GOT\n");
6257 mips_init_after_args ()
6259 if (target_big_endian
)
6260 byte_order
= BIG_ENDIAN
;
6262 byte_order
= LITTLE_ENDIAN
;
6266 md_pcrel_from (fixP
)
6269 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6270 && fixP
->fx_addsy
!= (symbolS
*) NULL
6271 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6273 /* This makes a branch to an undefined symbol be a branch to the
6274 current location. */
6278 /* return the address of the delay slot */
6279 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6282 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6283 reloc for a cons. We could use the definition there, except that
6284 we want to handle 64 bit relocs specially. */
6287 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6290 unsigned int nbytes
;
6293 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6295 FIXME: There is no way to select anything but 32 bit mode right
6299 if (byte_order
== BIG_ENDIAN
)
6304 if (nbytes
!= 2 && nbytes
!= 4)
6305 as_bad ("Unsupported reloc size %d", nbytes
);
6307 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6308 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
6311 /* Sort any unmatched HI16_S relocs so that they immediately precede
6312 the corresponding LO reloc. This is called before md_apply_fix and
6313 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6314 explicit use of the %hi modifier. */
6319 struct mips_hi_fixup
*l
;
6321 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6323 segment_info_type
*seginfo
;
6326 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6328 /* Check quickly whether the next fixup happens to be a matching
6330 if (l
->fixp
->fx_next
!= NULL
6331 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6332 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6333 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6336 /* Look through the fixups for this segment for a matching %lo.
6337 When we find one, move the %hi just in front of it. We do
6338 this in two passes. In the first pass, we try to find a
6339 unique %lo. In the second pass, we permit multiple %hi
6340 relocs for a single %lo (this is a GNU extension). */
6341 seginfo
= seg_info (l
->seg
);
6342 for (pass
= 0; pass
< 2; pass
++)
6347 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6349 /* Check whether this is a %lo fixup which matches l->fixp. */
6350 if (f
->fx_r_type
== BFD_RELOC_LO16
6351 && f
->fx_addsy
== l
->fixp
->fx_addsy
6352 && f
->fx_offset
== l
->fixp
->fx_offset
6355 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6356 || prev
->fx_addsy
!= f
->fx_addsy
6357 || prev
->fx_offset
!= f
->fx_offset
))
6361 /* Move l->fixp before f. */
6362 for (pf
= &seginfo
->fix_root
;
6364 pf
= &(*pf
)->fx_next
)
6365 assert (*pf
!= NULL
);
6367 *pf
= l
->fixp
->fx_next
;
6369 l
->fixp
->fx_next
= f
;
6371 seginfo
->fix_root
= l
->fixp
;
6373 prev
->fx_next
= l
->fixp
;
6385 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6386 "Unmatched %%hi reloc");
6391 /* When generating embedded PIC code we need to use a special
6392 relocation to represent the difference of two symbols in the .text
6393 section (switch tables use a difference of this sort). See
6394 include/coff/mips.h for details. This macro checks whether this
6395 fixup requires the special reloc. */
6396 #define SWITCH_TABLE(fixp) \
6397 ((fixp)->fx_r_type == BFD_RELOC_32 \
6398 && (fixp)->fx_addsy != NULL \
6399 && (fixp)->fx_subsy != NULL \
6400 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6401 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6403 /* When generating embedded PIC code we must keep all PC relative
6404 relocations, in case the linker has to relax a call. We also need
6405 to keep relocations for switch table entries. */
6409 mips_force_relocation (fixp
)
6412 return (mips_pic
== EMBEDDED_PIC
6414 || SWITCH_TABLE (fixp
)
6415 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6416 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6419 /* Apply a fixup to the object file. */
6422 md_apply_fix (fixP
, valueP
)
6429 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6432 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6434 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6437 switch (fixP
->fx_r_type
)
6439 case BFD_RELOC_MIPS_JMP
:
6440 case BFD_RELOC_HI16
:
6441 case BFD_RELOC_HI16_S
:
6442 case BFD_RELOC_MIPS_GPREL
:
6443 case BFD_RELOC_MIPS_LITERAL
:
6444 case BFD_RELOC_MIPS_CALL16
:
6445 case BFD_RELOC_MIPS_GOT16
:
6446 case BFD_RELOC_MIPS_GPREL32
:
6447 case BFD_RELOC_MIPS_GOT_HI16
:
6448 case BFD_RELOC_MIPS_GOT_LO16
:
6449 case BFD_RELOC_MIPS_CALL_HI16
:
6450 case BFD_RELOC_MIPS_CALL_LO16
:
6452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6453 "Invalid PC relative reloc");
6454 /* Nothing needed to do. The value comes from the reloc entry */
6457 case BFD_RELOC_PCREL_HI16_S
:
6458 /* The addend for this is tricky if it is internal, so we just
6459 do everything here rather than in bfd_perform_relocation. */
6460 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6462 /* For an external symbol adjust by the address to make it
6463 pcrel_offset. We use the address of the RELLO reloc
6464 which follows this one. */
6465 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6466 + fixP
->fx_next
->fx_where
);
6471 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6472 if (byte_order
== BIG_ENDIAN
)
6474 md_number_to_chars (buf
, value
, 2);
6477 case BFD_RELOC_PCREL_LO16
:
6478 /* The addend for this is tricky if it is internal, so we just
6479 do everything here rather than in bfd_perform_relocation. */
6480 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6481 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6482 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6483 if (byte_order
== BIG_ENDIAN
)
6485 md_number_to_chars (buf
, value
, 2);
6489 /* If we are deleting this reloc entry, we must fill in the
6490 value now. This can happen if we have a .word which is not
6491 resolved when it appears but is later defined. We also need
6492 to fill in the value if this is an embedded PIC switch table
6495 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6496 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6501 /* If we are deleting this reloc entry, we must fill in the
6503 assert (fixP
->fx_size
== 2);
6505 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6509 case BFD_RELOC_LO16
:
6510 /* When handling an embedded PIC switch statement, we can wind
6511 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6514 if (value
< -0x8000 || value
> 0x7fff)
6515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6516 "relocation overflow");
6517 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6518 if (byte_order
== BIG_ENDIAN
)
6520 md_number_to_chars (buf
, value
, 2);
6524 case BFD_RELOC_16_PCREL_S2
:
6526 * We need to save the bits in the instruction since fixup_segment()
6527 * might be deleting the relocation entry (i.e., a branch within
6528 * the current segment).
6531 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6532 "Branch to odd address (%lx)", value
);
6535 /* update old instruction data */
6536 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6540 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6544 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6552 if (value
>= -0x8000 && value
< 0x8000)
6553 insn
|= value
& 0xffff;
6556 /* The branch offset is too large. If this is an
6557 unconditional branch, and we are not generating PIC code,
6558 we can convert it to an absolute jump instruction. */
6559 if (mips_pic
== NO_PIC
6561 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6562 && (fixP
->fx_frag
->fr_address
6563 < text_section
->vma
+ text_section
->_raw_size
)
6564 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6565 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6566 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6568 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6569 insn
= 0x0c000000; /* jal */
6571 insn
= 0x08000000; /* j */
6572 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6574 fixP
->fx_addsy
= section_symbol (text_section
);
6575 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6579 /* FIXME. It would be possible in principle to handle
6580 conditional branches which overflow. They could be
6581 transformed into a branch around a jump. This would
6582 require setting up variant frags for each different
6583 branch type. The native MIPS assembler attempts to
6584 handle these cases, but it appears to do it
6586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6587 "Relocation overflow");
6591 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6606 const struct mips_opcode
*p
;
6607 int treg
, sreg
, dreg
, shamt
;
6612 for (i
= 0; i
< NUMOPCODES
; ++i
)
6614 p
= &mips_opcodes
[i
];
6615 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6617 printf ("%08lx %s\t", oc
, p
->name
);
6618 treg
= (oc
>> 16) & 0x1f;
6619 sreg
= (oc
>> 21) & 0x1f;
6620 dreg
= (oc
>> 11) & 0x1f;
6621 shamt
= (oc
>> 6) & 0x1f;
6623 for (args
= p
->args
;; ++args
)
6634 printf ("%c", *args
);
6638 assert (treg
== sreg
);
6639 printf ("$%d,$%d", treg
, sreg
);
6644 printf ("$%d", dreg
);
6649 printf ("$%d", treg
);
6653 printf ("0x%x", treg
);
6658 printf ("$%d", sreg
);
6662 printf ("0x%08lx", oc
& 0x1ffffff);
6674 printf ("$%d", shamt
);
6685 printf ("%08lx UNDEFINED\n", oc
);
6696 name
= input_line_pointer
;
6697 c
= get_symbol_end ();
6698 p
= (symbolS
*) symbol_find_or_make (name
);
6699 *input_line_pointer
= c
;
6703 /* Align the current frag to a given power of two. The MIPS assembler
6704 also automatically adjusts any preceding label. */
6707 mips_align (to
, fill
, label
)
6712 mips_emit_delays ();
6713 frag_align (to
, fill
);
6714 record_alignment (now_seg
, to
);
6717 assert (S_GET_SEGMENT (label
) == now_seg
);
6718 label
->sy_frag
= frag_now
;
6719 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6723 /* Align to a given power of two. .align 0 turns off the automatic
6724 alignment used by the data creating pseudo-ops. */
6731 register long temp_fill
;
6732 long max_alignment
= 15;
6736 o Note that the assembler pulls down any immediately preceeding label
6737 to the aligned address.
6738 o It's not documented but auto alignment is reinstated by
6739 a .align pseudo instruction.
6740 o Note also that after auto alignment is turned off the mips assembler
6741 issues an error on attempt to assemble an improperly aligned data item.
6746 temp
= get_absolute_expression ();
6747 if (temp
> max_alignment
)
6748 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6751 as_warn ("Alignment negative: 0 assumed.");
6754 if (*input_line_pointer
== ',')
6756 input_line_pointer
++;
6757 temp_fill
= get_absolute_expression ();
6764 mips_align (temp
, (int) temp_fill
, insn_label
);
6771 demand_empty_rest_of_line ();
6775 mips_flush_pending_output ()
6777 mips_emit_delays ();
6787 /* When generating embedded PIC code, we only use the .text, .lit8,
6788 .sdata and .sbss sections. We change the .data and .rdata
6789 pseudo-ops to use .sdata. */
6790 if (mips_pic
== EMBEDDED_PIC
6791 && (sec
== 'd' || sec
== 'r'))
6794 mips_emit_delays ();
6804 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6805 demand_empty_rest_of_line ();
6809 if (USE_GLOBAL_POINTER_OPT
)
6811 seg
= subseg_new (RDATA_SECTION_NAME
,
6812 (subsegT
) get_absolute_expression ());
6813 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6815 bfd_set_section_flags (stdoutput
, seg
,
6821 bfd_set_section_alignment (stdoutput
, seg
, 4);
6823 demand_empty_rest_of_line ();
6827 as_bad ("No read only data section in this object file format");
6828 demand_empty_rest_of_line ();
6834 if (USE_GLOBAL_POINTER_OPT
)
6836 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6837 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6839 bfd_set_section_flags (stdoutput
, seg
,
6840 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6842 bfd_set_section_alignment (stdoutput
, seg
, 4);
6844 demand_empty_rest_of_line ();
6849 as_bad ("Global pointers not supported; recompile -G 0");
6850 demand_empty_rest_of_line ();
6859 mips_enable_auto_align ()
6871 mips_emit_delays ();
6872 if (log_size
> 0 && auto_align
)
6873 mips_align (log_size
, 0, label
);
6875 cons (1 << log_size
);
6886 mips_emit_delays ();
6890 mips_align (3, 0, label
);
6892 mips_align (2, 0, label
);
6899 /* Handle .globl. We need to override it because on Irix 5 you are
6902 where foo is an undefined symbol, to mean that foo should be
6903 considered to be the address of a function. */
6914 name
= input_line_pointer
;
6915 c
= get_symbol_end ();
6916 symbolP
= symbol_find_or_make (name
);
6917 *input_line_pointer
= c
;
6920 /* On Irix 5, every global symbol that is not explicitly labelled as
6921 being a function is apparently labelled as being an object. */
6924 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6929 secname
= input_line_pointer
;
6930 c
= get_symbol_end ();
6931 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6933 as_bad ("%s: no such section", secname
);
6934 *input_line_pointer
= c
;
6936 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6937 flag
= BSF_FUNCTION
;
6940 symbolP
->bsym
->flags
|= flag
;
6942 S_SET_EXTERNAL (symbolP
);
6943 demand_empty_rest_of_line ();
6953 opt
= input_line_pointer
;
6954 c
= get_symbol_end ();
6958 /* FIXME: What does this mean? */
6960 else if (strncmp (opt
, "pic", 3) == 0)
6968 mips_pic
= SVR4_PIC
;
6970 as_bad (".option pic%d not supported", i
);
6972 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6974 if (g_switch_seen
&& g_switch_value
!= 0)
6975 as_warn ("-G may not be used with SVR4 PIC code");
6977 bfd_set_gp_size (stdoutput
, 0);
6981 as_warn ("Unrecognized option \"%s\"", opt
);
6983 *input_line_pointer
= c
;
6984 demand_empty_rest_of_line ();
6991 char *name
= input_line_pointer
, ch
;
6993 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6994 input_line_pointer
++;
6995 ch
= *input_line_pointer
;
6996 *input_line_pointer
= '\0';
6998 if (strcmp (name
, "reorder") == 0)
7002 prev_insn_unreordered
= 1;
7003 prev_prev_insn_unreordered
= 1;
7007 else if (strcmp (name
, "noreorder") == 0)
7009 mips_emit_delays ();
7011 mips_any_noreorder
= 1;
7013 else if (strcmp (name
, "at") == 0)
7017 else if (strcmp (name
, "noat") == 0)
7021 else if (strcmp (name
, "macro") == 0)
7023 mips_warn_about_macros
= 0;
7025 else if (strcmp (name
, "nomacro") == 0)
7027 if (mips_noreorder
== 0)
7028 as_bad ("`noreorder' must be set before `nomacro'");
7029 mips_warn_about_macros
= 1;
7031 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7035 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7039 else if (strcmp (name
, "bopt") == 0)
7043 else if (strcmp (name
, "nobopt") == 0)
7047 else if (strncmp (name
, "mips", 4) == 0)
7051 /* Permit the user to change the ISA on the fly. Needless to
7052 say, misuse can cause serious problems. */
7053 isa
= atoi (name
+ 4);
7055 mips_isa
= file_mips_isa
;
7056 else if (isa
< 1 || isa
> 4)
7057 as_bad ("unknown ISA level");
7063 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7065 *input_line_pointer
= ch
;
7066 demand_empty_rest_of_line ();
7069 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7070 .option pic2. It means to generate SVR4 PIC calls. */
7076 mips_pic
= SVR4_PIC
;
7077 if (USE_GLOBAL_POINTER_OPT
)
7079 if (g_switch_seen
&& g_switch_value
!= 0)
7080 as_warn ("-G may not be used with SVR4 PIC code");
7083 bfd_set_gp_size (stdoutput
, 0);
7084 demand_empty_rest_of_line ();
7087 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7088 PIC code. It sets the $gp register for the function based on the
7089 function address, which is in the register named in the argument.
7090 This uses a relocation against _gp_disp, which is handled specially
7091 by the linker. The result is:
7092 lui $gp,%hi(_gp_disp)
7093 addiu $gp,$gp,%lo(_gp_disp)
7094 addu $gp,$gp,.cpload argument
7095 The .cpload argument is normally $25 == $t9. */
7104 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7105 if (mips_pic
!= SVR4_PIC
)
7111 /* .cpload should be a in .set noreorder section. */
7112 if (mips_noreorder
== 0)
7113 as_warn (".cpload not in noreorder section");
7116 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7117 ex
.X_op_symbol
= NULL
;
7118 ex
.X_add_number
= 0;
7120 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7121 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7123 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7124 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7125 (int) BFD_RELOC_LO16
);
7127 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7128 GP
, GP
, tc_get_register (0));
7130 demand_empty_rest_of_line ();
7133 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7134 offset from $sp. The offset is remembered, and after making a PIC
7135 call $gp is restored from that location. */
7138 s_cprestore (ignore
)
7144 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7145 if (mips_pic
!= SVR4_PIC
)
7151 mips_cprestore_offset
= get_absolute_expression ();
7153 ex
.X_op
= O_constant
;
7154 ex
.X_add_symbol
= NULL
;
7155 ex
.X_op_symbol
= NULL
;
7156 ex
.X_add_number
= mips_cprestore_offset
;
7158 macro_build ((char *) NULL
, &icnt
, &ex
,
7159 mips_isa
< 3 ? "sw" : "sd",
7160 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7162 demand_empty_rest_of_line ();
7165 /* Handle the .gpword pseudo-op. This is used when generating PIC
7166 code. It generates a 32 bit GP relative reloc. */
7176 /* When not generating PIC code, this is treated as .word. */
7177 if (mips_pic
!= SVR4_PIC
)
7184 mips_emit_delays ();
7186 mips_align (2, 0, label
);
7191 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7193 as_bad ("Unsupported use of .gpword");
7194 ignore_rest_of_line ();
7198 md_number_to_chars (p
, (valueT
) 0, 4);
7199 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7200 BFD_RELOC_MIPS_GPREL32
);
7202 demand_empty_rest_of_line ();
7205 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7206 tables in SVR4 PIC code. */
7215 /* This is ignored when not generating SVR4 PIC code. */
7216 if (mips_pic
!= SVR4_PIC
)
7222 /* Add $gp to the register named as an argument. */
7223 reg
= tc_get_register (0);
7224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7225 mips_isa
< 3 ? "addu" : "daddu",
7226 "d,v,t", reg
, reg
, GP
);
7228 demand_empty_rest_of_line ();
7231 /* Parse a register string into a number. Called from the ECOFF code
7232 to parse .frame. The argument is non-zero if this is the frame
7233 register, so that we can record it in mips_frame_reg. */
7236 tc_get_register (frame
)
7242 if (*input_line_pointer
++ != '$')
7244 as_warn ("expected `$'");
7247 else if (isdigit ((unsigned char) *input_line_pointer
))
7249 reg
= get_absolute_expression ();
7250 if (reg
< 0 || reg
>= 32)
7252 as_warn ("Bad register number");
7258 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7260 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7262 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7264 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7268 as_warn ("Unrecognized register name");
7271 input_line_pointer
+= 2;
7274 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7279 md_section_align (seg
, addr
)
7283 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7285 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7288 /* Utility routine, called from above as well. If called while the
7289 input file is still being read, it's only an approximation. (For
7290 example, a symbol may later become defined which appeared to be
7291 undefined earlier.) */
7294 nopic_need_relax (sym
)
7300 if (USE_GLOBAL_POINTER_OPT
)
7302 const char *symname
;
7305 /* Find out whether this symbol can be referenced off the GP
7306 register. It can be if it is smaller than the -G size or if
7307 it is in the .sdata or .sbss section. Certain symbols can
7308 not be referenced off the GP, although it appears as though
7310 symname
= S_GET_NAME (sym
);
7311 if (symname
!= (const char *) NULL
7312 && (strcmp (symname
, "eprol") == 0
7313 || strcmp (symname
, "etext") == 0
7314 || strcmp (symname
, "_gp") == 0
7315 || strcmp (symname
, "edata") == 0
7316 || strcmp (symname
, "_fbss") == 0
7317 || strcmp (symname
, "_fdata") == 0
7318 || strcmp (symname
, "_ftext") == 0
7319 || strcmp (symname
, "end") == 0
7320 || strcmp (symname
, "_gp_disp") == 0))
7322 else if (! S_IS_DEFINED (sym
)
7324 #ifndef NO_ECOFF_DEBUGGING
7325 || (sym
->ecoff_extern_size
!= 0
7326 && sym
->ecoff_extern_size
<= g_switch_value
)
7328 || (S_GET_VALUE (sym
) != 0
7329 && S_GET_VALUE (sym
) <= g_switch_value
)))
7333 const char *segname
;
7335 segname
= segment_name (S_GET_SEGMENT (sym
));
7336 assert (strcmp (segname
, ".lit8") != 0
7337 && strcmp (segname
, ".lit4") != 0);
7338 change
= (strcmp (segname
, ".sdata") != 0
7339 && strcmp (segname
, ".sbss") != 0);
7344 /* We are not optimizing for the GP register. */
7348 /* Estimate the size of a frag before relaxing. We are not really
7349 relaxing here, and the final size is encoded in the subtype
7354 md_estimate_size_before_relax (fragp
, segtype
)
7360 if (mips_pic
== NO_PIC
)
7362 change
= nopic_need_relax (fragp
->fr_symbol
);
7364 else if (mips_pic
== SVR4_PIC
)
7366 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7368 /* This must duplicate the test in adjust_reloc_syms. */
7369 change
= (symsec
!= &bfd_und_section
7370 && symsec
!= &bfd_abs_section
7371 && ! bfd_is_com_section (symsec
));
7378 /* Record the offset to the first reloc in the fr_opcode field.
7379 This lets md_convert_frag and tc_gen_reloc know that the code
7380 must be expanded. */
7381 fragp
->fr_opcode
= (fragp
->fr_literal
7383 - RELAX_OLD (fragp
->fr_subtype
)
7384 + RELAX_RELOC1 (fragp
->fr_subtype
));
7385 /* FIXME: This really needs as_warn_where. */
7386 if (RELAX_WARN (fragp
->fr_subtype
))
7387 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7393 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7396 /* Translate internal representation of relocation info to BFD target
7400 tc_gen_reloc (section
, fixp
)
7404 static arelent
*retval
[4];
7407 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7410 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7411 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7413 if (mips_pic
== EMBEDDED_PIC
7414 && SWITCH_TABLE (fixp
))
7416 /* For a switch table entry we use a special reloc. The addend
7417 is actually the difference between the reloc address and the
7419 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7420 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7421 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7422 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7424 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7426 /* We use a special addend for an internal RELLO reloc. */
7427 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7428 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7430 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7432 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7434 assert (fixp
->fx_next
!= NULL
7435 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7436 /* We use a special addend for an internal RELHI reloc. The
7437 reloc is relative to the RELLO; adjust the addend
7439 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7440 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7441 + fixp
->fx_next
->fx_where
7442 - S_GET_VALUE (fixp
->fx_subsy
));
7444 reloc
->addend
= (fixp
->fx_addnumber
7445 + fixp
->fx_next
->fx_frag
->fr_address
7446 + fixp
->fx_next
->fx_where
);
7448 else if (fixp
->fx_pcrel
== 0)
7449 reloc
->addend
= fixp
->fx_addnumber
;
7452 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7453 /* A gruesome hack which is a result of the gruesome gas reloc
7455 reloc
->addend
= reloc
->address
;
7457 reloc
->addend
= -reloc
->address
;
7460 /* If this is a variant frag, we may need to adjust the existing
7461 reloc and generate a new one. */
7462 if (fixp
->fx_frag
->fr_opcode
!= NULL
7463 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7464 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7465 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7466 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7467 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7468 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7469 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7473 /* If this is not the last reloc in this frag, then we have two
7474 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7475 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7476 the second one handle all of them. */
7477 if (fixp
->fx_next
!= NULL
7478 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7480 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7481 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7482 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7483 && (fixp
->fx_next
->fx_r_type
7484 == BFD_RELOC_MIPS_GOT_LO16
))
7485 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7486 && (fixp
->fx_next
->fx_r_type
7487 == BFD_RELOC_MIPS_CALL_LO16
)));
7492 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7493 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7494 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7496 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7497 reloc2
->address
= (reloc
->address
7498 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7499 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7500 reloc2
->addend
= fixp
->fx_addnumber
;
7501 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7502 assert (reloc2
->howto
!= NULL
);
7504 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7508 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7511 reloc3
->address
+= 4;
7514 if (mips_pic
== NO_PIC
)
7516 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7517 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7519 else if (mips_pic
== SVR4_PIC
)
7521 switch (fixp
->fx_r_type
)
7525 case BFD_RELOC_MIPS_GOT16
:
7527 case BFD_RELOC_MIPS_CALL16
:
7528 case BFD_RELOC_MIPS_GOT_LO16
:
7529 case BFD_RELOC_MIPS_CALL_LO16
:
7530 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7538 /* To support a PC relative reloc when generating embedded PIC code
7539 for ECOFF, we use a Cygnus extension. We check for that here to
7540 make sure that we don't let such a reloc escape normally. */
7541 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7542 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7543 && mips_pic
!= EMBEDDED_PIC
)
7544 reloc
->howto
= NULL
;
7546 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7548 if (reloc
->howto
== NULL
)
7550 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7551 "Can not represent relocation in this object file format");
7558 /* Convert a machine dependent frag. */
7561 md_convert_frag (abfd
, asec
, fragp
)
7569 if (fragp
->fr_opcode
== NULL
)
7572 old
= RELAX_OLD (fragp
->fr_subtype
);
7573 new = RELAX_NEW (fragp
->fr_subtype
);
7574 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7577 memcpy (fixptr
- old
, fixptr
, new);
7579 fragp
->fr_fix
+= new - old
;
7582 /* This function is called whenever a label is defined. It is used
7583 when handling branch delays; if a branch has a label, we assume we
7587 mips_define_label (sym
)
7593 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7594 In order to work with gcc when using mips-tfile, we must keep all
7595 local labels. However, in other cases, we want to discard them,
7596 since they are useless. */
7599 mips_local_label (name
)
7602 #ifndef NO_ECOFF_DEBUGGING
7605 && ! ecoff_debugging_seen
)
7607 /* We were called with -g, but we didn't see any debugging
7608 information. That may mean that gcc is smuggling debugging
7609 information through to mips-tfile, in which case we must
7610 generate all local labels. */
7615 /* Here it's OK to discard local labels. */
7617 return name
[0] == '$';
7620 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7622 /* Some special processing for a MIPS ELF file. */
7625 mips_elf_final_processing ()
7629 /* Write out the .reginfo section. */
7630 s
.ri_gprmask
= mips_gprmask
;
7631 s
.ri_cprmask
[0] = mips_cprmask
[0];
7632 s
.ri_cprmask
[1] = mips_cprmask
[1];
7633 s
.ri_cprmask
[2] = mips_cprmask
[2];
7634 s
.ri_cprmask
[3] = mips_cprmask
[3];
7635 /* The gp_value field is set by the MIPS ELF backend. */
7637 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7638 ((Elf32_External_RegInfo
*)
7639 mips_regmask_frag
));
7641 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7642 sort of BFD interface for this. */
7643 if (mips_any_noreorder
)
7644 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7645 if (mips_pic
!= NO_PIC
)
7646 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7649 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7651 /* These functions should really be defined by the object file format,
7652 since they are related to debugging information. However, this
7653 code has to work for the a.out format, which does not define them,
7654 so we provide simple versions here. These don't actually generate
7655 any debugging information, but they do simple checking and someday
7656 somebody may make them useful. */
7660 struct loc
*loc_next
;
7661 unsigned long loc_fileno
;
7662 unsigned long loc_lineno
;
7663 unsigned long loc_offset
;
7664 unsigned short loc_delta
;
7665 unsigned short loc_count
;
7674 struct proc
*proc_next
;
7675 struct symbol
*proc_isym
;
7676 struct symbol
*proc_end
;
7677 unsigned long proc_reg_mask
;
7678 unsigned long proc_reg_offset
;
7679 unsigned long proc_fpreg_mask
;
7680 unsigned long proc_fpreg_offset
;
7681 unsigned long proc_frameoffset
;
7682 unsigned long proc_framereg
;
7683 unsigned long proc_pcreg
;
7685 struct file
*proc_file
;
7692 struct file
*file_next
;
7693 unsigned long file_fileno
;
7694 struct symbol
*file_symbol
;
7695 struct symbol
*file_end
;
7696 struct proc
*file_proc
;
7701 static struct obstack proc_frags
;
7702 static procS
*proc_lastP
;
7703 static procS
*proc_rootP
;
7704 static int numprocs
;
7709 obstack_begin (&proc_frags
, 0x2000);
7715 /* check for premature end, nesting errors, etc */
7716 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7717 as_warn ("missing `.end' at end of assembly");
7726 if (*input_line_pointer
== '-')
7728 ++input_line_pointer
;
7731 if (!isdigit (*input_line_pointer
))
7732 as_bad ("Expected simple number.");
7733 if (input_line_pointer
[0] == '0')
7735 if (input_line_pointer
[1] == 'x')
7737 input_line_pointer
+= 2;
7738 while (isxdigit (*input_line_pointer
))
7741 val
|= hex_value (*input_line_pointer
++);
7743 return negative
? -val
: val
;
7747 ++input_line_pointer
;
7748 while (isdigit (*input_line_pointer
))
7751 val
|= *input_line_pointer
++ - '0';
7753 return negative
? -val
: val
;
7756 if (!isdigit (*input_line_pointer
))
7758 printf (" *input_line_pointer == '%c' 0x%02x\n",
7759 *input_line_pointer
, *input_line_pointer
);
7760 as_warn ("Invalid number");
7763 while (isdigit (*input_line_pointer
))
7766 val
+= *input_line_pointer
++ - '0';
7768 return negative
? -val
: val
;
7771 /* The .file directive; just like the usual .file directive, but there
7772 is an initial number which is the ECOFF file index. */
7780 line
= get_number ();
7785 /* The .end directive. */
7793 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7796 demand_empty_rest_of_line ();
7800 if (now_seg
!= text_section
)
7801 as_warn (".end not in text section");
7804 as_warn (".end and no .ent seen yet.");
7810 assert (S_GET_NAME (p
));
7811 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7812 as_warn (".end symbol does not match .ent symbol.");
7815 proc_lastP
->proc_end
= (symbolS
*) 1;
7818 /* The .aent and .ent directives. */
7828 symbolP
= get_symbol ();
7829 if (*input_line_pointer
== ',')
7830 input_line_pointer
++;
7832 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7833 number
= get_number ();
7834 if (now_seg
!= text_section
)
7835 as_warn (".ent or .aent not in text section.");
7837 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7838 as_warn ("missing `.end'");
7842 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7843 procP
->proc_isym
= symbolP
;
7844 procP
->proc_reg_mask
= 0;
7845 procP
->proc_reg_offset
= 0;
7846 procP
->proc_fpreg_mask
= 0;
7847 procP
->proc_fpreg_offset
= 0;
7848 procP
->proc_frameoffset
= 0;
7849 procP
->proc_framereg
= 0;
7850 procP
->proc_pcreg
= 0;
7851 procP
->proc_end
= NULL
;
7852 procP
->proc_next
= NULL
;
7854 proc_lastP
->proc_next
= procP
;
7860 demand_empty_rest_of_line ();
7863 /* The .frame directive. */
7876 frame_reg
= tc_get_register (1);
7877 if (*input_line_pointer
== ',')
7878 input_line_pointer
++;
7879 frame_off
= get_absolute_expression ();
7880 if (*input_line_pointer
== ',')
7881 input_line_pointer
++;
7882 pcreg
= tc_get_register (0);
7885 assert (proc_rootP
);
7886 proc_rootP
->proc_framereg
= frame_reg
;
7887 proc_rootP
->proc_frameoffset
= frame_off
;
7888 proc_rootP
->proc_pcreg
= pcreg
;
7889 /* bob macho .frame */
7891 /* We don't have to write out a frame stab for unoptimized code. */
7892 if (!(frame_reg
== FP
&& frame_off
== 0))
7895 as_warn ("No .ent for .frame to use.");
7896 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7897 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7898 S_SET_TYPE (symP
, N_RMASK
);
7899 S_SET_OTHER (symP
, 0);
7900 S_SET_DESC (symP
, 0);
7901 symP
->sy_forward
= proc_lastP
->proc_isym
;
7902 /* bob perhaps I should have used pseudo set */
7904 demand_empty_rest_of_line ();
7908 /* The .fmask and .mask directives. */
7915 char str
[100], *strP
;
7921 mask
= get_number ();
7922 if (*input_line_pointer
== ',')
7923 input_line_pointer
++;
7924 off
= get_absolute_expression ();
7926 /* bob only for coff */
7927 assert (proc_rootP
);
7928 if (reg_type
== 'F')
7930 proc_rootP
->proc_fpreg_mask
= mask
;
7931 proc_rootP
->proc_fpreg_offset
= off
;
7935 proc_rootP
->proc_reg_mask
= mask
;
7936 proc_rootP
->proc_reg_offset
= off
;
7939 /* bob macho .mask + .fmask */
7941 /* We don't have to write out a mask stab if no saved regs. */
7945 as_warn ("No .ent for .mask to use.");
7947 for (i
= 0; i
< 32; i
++)
7951 sprintf (strP
, "%c%d,", reg_type
, i
);
7952 strP
+= strlen (strP
);
7956 sprintf (strP
, ";%d,", off
);
7957 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7958 S_SET_TYPE (symP
, N_RMASK
);
7959 S_SET_OTHER (symP
, 0);
7960 S_SET_DESC (symP
, 0);
7961 symP
->sy_forward
= proc_lastP
->proc_isym
;
7962 /* bob perhaps I should have used pseudo set */
7967 /* The .loc directive. */
7978 assert (now_seg
== text_section
);
7980 lineno
= get_number ();
7981 addroff
= frag_now_fix ();
7983 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7984 S_SET_TYPE (symbolP
, N_SLINE
);
7985 S_SET_OTHER (symbolP
, 0);
7986 S_SET_DESC (symbolP
, lineno
);
7987 symbolP
->sy_segment
= now_seg
;