[ gas/ChangeLog ]
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26 #include "as.h"
27 #include "config.h"
28 #include "subsegs.h"
29 #include "safe-ctype.h"
30
31 #include <stdarg.h>
32
33 #include "opcode/mips.h"
34 #include "itbl-ops.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
37
38 #ifdef DEBUG
39 #define DBG(x) printf x
40 #else
41 #define DBG(x)
42 #endif
43
44 #ifdef OBJ_MAYBE_ELF
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
48 #undef OBJ_PROCESS_STAB
49 #undef OUTPUT_FLAVOR
50 #undef S_GET_ALIGN
51 #undef S_GET_SIZE
52 #undef S_SET_ALIGN
53 #undef S_SET_SIZE
54 #undef obj_frob_file
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
57 #undef obj_pop_insert
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60
61 #include "obj-elf.h"
62 /* Fix any of them that we actually care about. */
63 #undef OUTPUT_FLAVOR
64 #define OUTPUT_FLAVOR mips_output_flavor()
65 #endif
66
67 #if defined (OBJ_ELF)
68 #include "elf/mips.h"
69 #endif
70
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
74 #endif
75
76 int mips_flag_mdebug = -1;
77
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
81 #ifdef TE_IRIX
82 int mips_flag_pdr = FALSE;
83 #else
84 int mips_flag_pdr = TRUE;
85 #endif
86
87 #include "ecoff.h"
88
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag;
91 #endif
92
93 #define ZERO 0
94 #define AT 1
95 #define TREG 24
96 #define PIC_CALL_REG 25
97 #define KT0 26
98 #define KT1 27
99 #define GP 28
100 #define SP 29
101 #define FP 30
102 #define RA 31
103
104 #define ILLEGAL_REG (32)
105
106 /* Allow override of standard little-endian ECOFF format. */
107
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 #endif
111
112 extern int target_big_endian;
113
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 ? ".rdata" \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 ? ".rdata" \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 ? ".rodata" \
121 : (abort (), ""))
122
123 /* Information about an instruction, including its format, operands
124 and fixups. */
125 struct mips_cl_insn
126 {
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode *insn_mo;
129
130 /* True if this is a mips16 instruction and if we want the extended
131 form of INSN_MO. */
132 bfd_boolean use_extend;
133
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend;
136
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode;
140
141 /* The frag that contains the instruction. */
142 struct frag *frag;
143
144 /* The offset into FRAG of the first instruction byte. */
145 long where;
146
147 /* The relocs associated with the instruction, if any. */
148 fixS *fixp[3];
149
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p : 1;
152
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p : 1;
155
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p : 1;
158 };
159
160 /* The ABI to use. */
161 enum mips_abi_level
162 {
163 NO_ABI = 0,
164 O32_ABI,
165 O64_ABI,
166 N32_ABI,
167 N64_ABI,
168 EABI_ABI
169 };
170
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi = NO_ABI;
173
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls = FALSE;
176
177 /* Whether or not we have code which can be put into a shared
178 library. */
179 static bfd_boolean mips_in_shared = TRUE;
180
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
183 reliable. */
184
185 struct mips_set_options
186 {
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
190 int isa;
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
194 int ase_mips3d;
195 int ase_mdmx;
196 int ase_smartmips;
197 int ase_dsp;
198 int ase_mt;
199 /* Whether we are assembling for the mips16 processor. 0 if we are
200 not, 1 if we are, and -1 if the value has not been initialized.
201 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
202 -nomips16 command line options, and the default CPU. */
203 int mips16;
204 /* Non-zero if we should not reorder instructions. Changed by `.set
205 reorder' and `.set noreorder'. */
206 int noreorder;
207 /* Non-zero if we should not permit the $at ($1) register to be used
208 in instructions. Changed by `.set at' and `.set noat'. */
209 int noat;
210 /* Non-zero if we should warn when a macro instruction expands into
211 more than one machine instruction. Changed by `.set nomacro' and
212 `.set macro'. */
213 int warn_about_macros;
214 /* Non-zero if we should not move instructions. Changed by `.set
215 move', `.set volatile', `.set nomove', and `.set novolatile'. */
216 int nomove;
217 /* Non-zero if we should not optimize branches by moving the target
218 of the branch into the delay slot. Actually, we don't perform
219 this optimization anyhow. Changed by `.set bopt' and `.set
220 nobopt'. */
221 int nobopt;
222 /* Non-zero if we should not autoextend mips16 instructions.
223 Changed by `.set autoextend' and `.set noautoextend'. */
224 int noautoextend;
225 /* Restrict general purpose registers and floating point registers
226 to 32 bit. This is initially determined when -mgp32 or -mfp32
227 is passed but can changed if the assembler code uses .set mipsN. */
228 int gp32;
229 int fp32;
230 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
231 command line option, and the default CPU. */
232 int arch;
233 /* True if ".set sym32" is in effect. */
234 bfd_boolean sym32;
235 };
236
237 /* True if -mgp32 was passed. */
238 static int file_mips_gp32 = -1;
239
240 /* True if -mfp32 was passed. */
241 static int file_mips_fp32 = -1;
242
243 /* This is the struct we use to hold the current set of options. Note
244 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
245 -1 to indicate that they have not been initialized. */
246
247 static struct mips_set_options mips_opts =
248 {
249 ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
250 };
251
252 /* These variables are filled in with the masks of registers used.
253 The object format code reads them and puts them in the appropriate
254 place. */
255 unsigned long mips_gprmask;
256 unsigned long mips_cprmask[4];
257
258 /* MIPS ISA we are using for this output file. */
259 static int file_mips_isa = ISA_UNKNOWN;
260
261 /* True if -mips16 was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips16;
264
265 /* True if -mips3d was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mips3d;
268
269 /* True if -mdmx was passed or implied by arguments passed on the
270 command line (e.g., by -march). */
271 static int file_ase_mdmx;
272
273 /* True if -msmartmips was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_smartmips;
276
277 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
278 || mips_opts.isa == ISA_MIPS32R2)
279
280 /* True if -mdsp was passed or implied by arguments passed on the
281 command line (e.g., by -march). */
282 static int file_ase_dsp;
283
284 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
285 || mips_opts.isa == ISA_MIPS64R2)
286
287 /* True if -mmt was passed or implied by arguments passed on the
288 command line (e.g., by -march). */
289 static int file_ase_mt;
290
291 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
292 || mips_opts.isa == ISA_MIPS64R2)
293
294 /* The argument of the -march= flag. The architecture we are assembling. */
295 static int file_mips_arch = CPU_UNKNOWN;
296 static const char *mips_arch_string;
297
298 /* The argument of the -mtune= flag. The architecture for which we
299 are optimizing. */
300 static int mips_tune = CPU_UNKNOWN;
301 static const char *mips_tune_string;
302
303 /* True when generating 32-bit code for a 64-bit processor. */
304 static int mips_32bitmode = 0;
305
306 /* True if the given ABI requires 32-bit registers. */
307 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
308
309 /* Likewise 64-bit registers. */
310 #define ABI_NEEDS_64BIT_REGS(ABI) \
311 ((ABI) == N32_ABI \
312 || (ABI) == N64_ABI \
313 || (ABI) == O64_ABI)
314
315 /* Return true if ISA supports 64 bit wide gp registers. */
316 #define ISA_HAS_64BIT_REGS(ISA) \
317 ((ISA) == ISA_MIPS3 \
318 || (ISA) == ISA_MIPS4 \
319 || (ISA) == ISA_MIPS5 \
320 || (ISA) == ISA_MIPS64 \
321 || (ISA) == ISA_MIPS64R2)
322
323 /* Return true if ISA supports 64 bit wide float registers. */
324 #define ISA_HAS_64BIT_FPRS(ISA) \
325 ((ISA) == ISA_MIPS3 \
326 || (ISA) == ISA_MIPS4 \
327 || (ISA) == ISA_MIPS5 \
328 || (ISA) == ISA_MIPS32R2 \
329 || (ISA) == ISA_MIPS64 \
330 || (ISA) == ISA_MIPS64R2)
331
332 /* Return true if ISA supports 64-bit right rotate (dror et al.)
333 instructions. */
334 #define ISA_HAS_DROR(ISA) \
335 ((ISA) == ISA_MIPS64R2)
336
337 /* Return true if ISA supports 32-bit right rotate (ror et al.)
338 instructions. */
339 #define ISA_HAS_ROR(ISA) \
340 ((ISA) == ISA_MIPS32R2 \
341 || (ISA) == ISA_MIPS64R2 \
342 || mips_opts.ase_smartmips)
343
344 /* Return true if ISA supports single-precision floats in odd registers. */
345 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
346 ((ISA) == ISA_MIPS32 \
347 || (ISA) == ISA_MIPS32R2 \
348 || (ISA) == ISA_MIPS64 \
349 || (ISA) == ISA_MIPS64R2)
350
351 /* Return true if ISA supports move to/from high part of a 64-bit
352 floating-point register. */
353 #define ISA_HAS_MXHC1(ISA) \
354 ((ISA) == ISA_MIPS32R2 \
355 || (ISA) == ISA_MIPS64R2)
356
357 #define HAVE_32BIT_GPRS \
358 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
359
360 #define HAVE_32BIT_FPRS \
361 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
362
363 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
364 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
365
366 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
367
368 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
369
370 /* True if relocations are stored in-place. */
371 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
372
373 /* The ABI-derived address size. */
374 #define HAVE_64BIT_ADDRESSES \
375 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
376 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
377
378 /* The size of symbolic constants (i.e., expressions of the form
379 "SYMBOL" or "SYMBOL + OFFSET"). */
380 #define HAVE_32BIT_SYMBOLS \
381 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
382 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
383
384 /* Addresses are loaded in different ways, depending on the address size
385 in use. The n32 ABI Documentation also mandates the use of additions
386 with overflow checking, but existing implementations don't follow it. */
387 #define ADDRESS_ADD_INSN \
388 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
389
390 #define ADDRESS_ADDI_INSN \
391 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
392
393 #define ADDRESS_LOAD_INSN \
394 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
395
396 #define ADDRESS_STORE_INSN \
397 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
398
399 /* Return true if the given CPU supports the MIPS16 ASE. */
400 #define CPU_HAS_MIPS16(cpu) \
401 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
402 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
403
404 /* Return true if the given CPU supports the MIPS3D ASE. */
405 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
406 )
407
408 /* Return true if the given CPU supports the MDMX ASE. */
409 #define CPU_HAS_MDMX(cpu) (FALSE \
410 )
411
412 /* Return true if the given CPU supports the DSP ASE. */
413 #define CPU_HAS_DSP(cpu) (FALSE \
414 )
415
416 /* Return true if the given CPU supports the MT ASE. */
417 #define CPU_HAS_MT(cpu) (FALSE \
418 )
419
420 /* True if CPU has a dror instruction. */
421 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
422
423 /* True if CPU has a ror instruction. */
424 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
425
426 /* True if mflo and mfhi can be immediately followed by instructions
427 which write to the HI and LO registers.
428
429 According to MIPS specifications, MIPS ISAs I, II, and III need
430 (at least) two instructions between the reads of HI/LO and
431 instructions which write them, and later ISAs do not. Contradicting
432 the MIPS specifications, some MIPS IV processor user manuals (e.g.
433 the UM for the NEC Vr5000) document needing the instructions between
434 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
435 MIPS64 and later ISAs to have the interlocks, plus any specific
436 earlier-ISA CPUs for which CPU documentation declares that the
437 instructions are really interlocked. */
438 #define hilo_interlocks \
439 (mips_opts.isa == ISA_MIPS32 \
440 || mips_opts.isa == ISA_MIPS32R2 \
441 || mips_opts.isa == ISA_MIPS64 \
442 || mips_opts.isa == ISA_MIPS64R2 \
443 || mips_opts.arch == CPU_R4010 \
444 || mips_opts.arch == CPU_R10000 \
445 || mips_opts.arch == CPU_R12000 \
446 || mips_opts.arch == CPU_RM7000 \
447 || mips_opts.arch == CPU_VR5500 \
448 )
449
450 /* Whether the processor uses hardware interlocks to protect reads
451 from the GPRs after they are loaded from memory, and thus does not
452 require nops to be inserted. This applies to instructions marked
453 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
454 level I. */
455 #define gpr_interlocks \
456 (mips_opts.isa != ISA_MIPS1 \
457 || mips_opts.arch == CPU_R3900)
458
459 /* Whether the processor uses hardware interlocks to avoid delays
460 required by coprocessor instructions, and thus does not require
461 nops to be inserted. This applies to instructions marked
462 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
463 between instructions marked INSN_WRITE_COND_CODE and ones marked
464 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
465 levels I, II, and III. */
466 /* Itbl support may require additional care here. */
467 #define cop_interlocks \
468 ((mips_opts.isa != ISA_MIPS1 \
469 && mips_opts.isa != ISA_MIPS2 \
470 && mips_opts.isa != ISA_MIPS3) \
471 || mips_opts.arch == CPU_R4300 \
472 )
473
474 /* Whether the processor uses hardware interlocks to protect reads
475 from coprocessor registers after they are loaded from memory, and
476 thus does not require nops to be inserted. This applies to
477 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
478 requires at MIPS ISA level I. */
479 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
480
481 /* Is this a mfhi or mflo instruction? */
482 #define MF_HILO_INSN(PINFO) \
483 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
484
485 /* MIPS PIC level. */
486
487 enum mips_pic_level mips_pic;
488
489 /* 1 if we should generate 32 bit offsets from the $gp register in
490 SVR4_PIC mode. Currently has no meaning in other modes. */
491 static int mips_big_got = 0;
492
493 /* 1 if trap instructions should used for overflow rather than break
494 instructions. */
495 static int mips_trap = 0;
496
497 /* 1 if double width floating point constants should not be constructed
498 by assembling two single width halves into two single width floating
499 point registers which just happen to alias the double width destination
500 register. On some architectures this aliasing can be disabled by a bit
501 in the status register, and the setting of this bit cannot be determined
502 automatically at assemble time. */
503 static int mips_disable_float_construction;
504
505 /* Non-zero if any .set noreorder directives were used. */
506
507 static int mips_any_noreorder;
508
509 /* Non-zero if nops should be inserted when the register referenced in
510 an mfhi/mflo instruction is read in the next two instructions. */
511 static int mips_7000_hilo_fix;
512
513 /* The size of the small data section. */
514 static unsigned int g_switch_value = 8;
515 /* Whether the -G option was used. */
516 static int g_switch_seen = 0;
517
518 #define N_RMASK 0xc4
519 #define N_VFP 0xd4
520
521 /* If we can determine in advance that GP optimization won't be
522 possible, we can skip the relaxation stuff that tries to produce
523 GP-relative references. This makes delay slot optimization work
524 better.
525
526 This function can only provide a guess, but it seems to work for
527 gcc output. It needs to guess right for gcc, otherwise gcc
528 will put what it thinks is a GP-relative instruction in a branch
529 delay slot.
530
531 I don't know if a fix is needed for the SVR4_PIC mode. I've only
532 fixed it for the non-PIC mode. KR 95/04/07 */
533 static int nopic_need_relax (symbolS *, int);
534
535 /* handle of the OPCODE hash table */
536 static struct hash_control *op_hash = NULL;
537
538 /* The opcode hash table we use for the mips16. */
539 static struct hash_control *mips16_op_hash = NULL;
540
541 /* This array holds the chars that always start a comment. If the
542 pre-processor is disabled, these aren't very useful */
543 const char comment_chars[] = "#";
544
545 /* This array holds the chars that only start a comment at the beginning of
546 a line. If the line seems to have the form '# 123 filename'
547 .line and .file directives will appear in the pre-processed output */
548 /* Note that input_file.c hand checks for '#' at the beginning of the
549 first line of the input file. This is because the compiler outputs
550 #NO_APP at the beginning of its output. */
551 /* Also note that C style comments are always supported. */
552 const char line_comment_chars[] = "#";
553
554 /* This array holds machine specific line separator characters. */
555 const char line_separator_chars[] = ";";
556
557 /* Chars that can be used to separate mant from exp in floating point nums */
558 const char EXP_CHARS[] = "eE";
559
560 /* Chars that mean this number is a floating point constant */
561 /* As in 0f12.456 */
562 /* or 0d1.2345e12 */
563 const char FLT_CHARS[] = "rRsSfFdDxXpP";
564
565 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
566 changed in read.c . Ideally it shouldn't have to know about it at all,
567 but nothing is ideal around here.
568 */
569
570 static char *insn_error;
571
572 static int auto_align = 1;
573
574 /* When outputting SVR4 PIC code, the assembler needs to know the
575 offset in the stack frame from which to restore the $gp register.
576 This is set by the .cprestore pseudo-op, and saved in this
577 variable. */
578 static offsetT mips_cprestore_offset = -1;
579
580 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
581 more optimizations, it can use a register value instead of a memory-saved
582 offset and even an other register than $gp as global pointer. */
583 static offsetT mips_cpreturn_offset = -1;
584 static int mips_cpreturn_register = -1;
585 static int mips_gp_register = GP;
586 static int mips_gprel_offset = 0;
587
588 /* Whether mips_cprestore_offset has been set in the current function
589 (or whether it has already been warned about, if not). */
590 static int mips_cprestore_valid = 0;
591
592 /* This is the register which holds the stack frame, as set by the
593 .frame pseudo-op. This is needed to implement .cprestore. */
594 static int mips_frame_reg = SP;
595
596 /* Whether mips_frame_reg has been set in the current function
597 (or whether it has already been warned about, if not). */
598 static int mips_frame_reg_valid = 0;
599
600 /* To output NOP instructions correctly, we need to keep information
601 about the previous two instructions. */
602
603 /* Whether we are optimizing. The default value of 2 means to remove
604 unneeded NOPs and swap branch instructions when possible. A value
605 of 1 means to not swap branches. A value of 0 means to always
606 insert NOPs. */
607 static int mips_optimize = 2;
608
609 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
610 equivalent to seeing no -g option at all. */
611 static int mips_debug = 0;
612
613 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
614 #define MAX_VR4130_NOPS 4
615
616 /* The maximum number of NOPs needed to fill delay slots. */
617 #define MAX_DELAY_NOPS 2
618
619 /* The maximum number of NOPs needed for any purpose. */
620 #define MAX_NOPS 4
621
622 /* A list of previous instructions, with index 0 being the most recent.
623 We need to look back MAX_NOPS instructions when filling delay slots
624 or working around processor errata. We need to look back one
625 instruction further if we're thinking about using history[0] to
626 fill a branch delay slot. */
627 static struct mips_cl_insn history[1 + MAX_NOPS];
628
629 /* Nop instructions used by emit_nop. */
630 static struct mips_cl_insn nop_insn, mips16_nop_insn;
631
632 /* The appropriate nop for the current mode. */
633 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
634
635 /* If this is set, it points to a frag holding nop instructions which
636 were inserted before the start of a noreorder section. If those
637 nops turn out to be unnecessary, the size of the frag can be
638 decreased. */
639 static fragS *prev_nop_frag;
640
641 /* The number of nop instructions we created in prev_nop_frag. */
642 static int prev_nop_frag_holds;
643
644 /* The number of nop instructions that we know we need in
645 prev_nop_frag. */
646 static int prev_nop_frag_required;
647
648 /* The number of instructions we've seen since prev_nop_frag. */
649 static int prev_nop_frag_since;
650
651 /* For ECOFF and ELF, relocations against symbols are done in two
652 parts, with a HI relocation and a LO relocation. Each relocation
653 has only 16 bits of space to store an addend. This means that in
654 order for the linker to handle carries correctly, it must be able
655 to locate both the HI and the LO relocation. This means that the
656 relocations must appear in order in the relocation table.
657
658 In order to implement this, we keep track of each unmatched HI
659 relocation. We then sort them so that they immediately precede the
660 corresponding LO relocation. */
661
662 struct mips_hi_fixup
663 {
664 /* Next HI fixup. */
665 struct mips_hi_fixup *next;
666 /* This fixup. */
667 fixS *fixp;
668 /* The section this fixup is in. */
669 segT seg;
670 };
671
672 /* The list of unmatched HI relocs. */
673
674 static struct mips_hi_fixup *mips_hi_fixup_list;
675
676 /* The frag containing the last explicit relocation operator.
677 Null if explicit relocations have not been used. */
678
679 static fragS *prev_reloc_op_frag;
680
681 /* Map normal MIPS register numbers to mips16 register numbers. */
682
683 #define X ILLEGAL_REG
684 static const int mips32_to_16_reg_map[] =
685 {
686 X, X, 2, 3, 4, 5, 6, 7,
687 X, X, X, X, X, X, X, X,
688 0, 1, X, X, X, X, X, X,
689 X, X, X, X, X, X, X, X
690 };
691 #undef X
692
693 /* Map mips16 register numbers to normal MIPS register numbers. */
694
695 static const unsigned int mips16_to_32_reg_map[] =
696 {
697 16, 17, 2, 3, 4, 5, 6, 7
698 };
699
700 /* Classifies the kind of instructions we're interested in when
701 implementing -mfix-vr4120. */
702 enum fix_vr4120_class {
703 FIX_VR4120_MACC,
704 FIX_VR4120_DMACC,
705 FIX_VR4120_MULT,
706 FIX_VR4120_DMULT,
707 FIX_VR4120_DIV,
708 FIX_VR4120_MTHILO,
709 NUM_FIX_VR4120_CLASSES
710 };
711
712 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
713 there must be at least one other instruction between an instruction
714 of type X and an instruction of type Y. */
715 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
716
717 /* True if -mfix-vr4120 is in force. */
718 static int mips_fix_vr4120;
719
720 /* ...likewise -mfix-vr4130. */
721 static int mips_fix_vr4130;
722
723 /* We don't relax branches by default, since this causes us to expand
724 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
725 fail to compute the offset before expanding the macro to the most
726 efficient expansion. */
727
728 static int mips_relax_branch;
729 \f
730 /* The expansion of many macros depends on the type of symbol that
731 they refer to. For example, when generating position-dependent code,
732 a macro that refers to a symbol may have two different expansions,
733 one which uses GP-relative addresses and one which uses absolute
734 addresses. When generating SVR4-style PIC, a macro may have
735 different expansions for local and global symbols.
736
737 We handle these situations by generating both sequences and putting
738 them in variant frags. In position-dependent code, the first sequence
739 will be the GP-relative one and the second sequence will be the
740 absolute one. In SVR4 PIC, the first sequence will be for global
741 symbols and the second will be for local symbols.
742
743 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
744 SECOND are the lengths of the two sequences in bytes. These fields
745 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
746 the subtype has the following flags:
747
748 RELAX_USE_SECOND
749 Set if it has been decided that we should use the second
750 sequence instead of the first.
751
752 RELAX_SECOND_LONGER
753 Set in the first variant frag if the macro's second implementation
754 is longer than its first. This refers to the macro as a whole,
755 not an individual relaxation.
756
757 RELAX_NOMACRO
758 Set in the first variant frag if the macro appeared in a .set nomacro
759 block and if one alternative requires a warning but the other does not.
760
761 RELAX_DELAY_SLOT
762 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
763 delay slot.
764
765 The frag's "opcode" points to the first fixup for relaxable code.
766
767 Relaxable macros are generated using a sequence such as:
768
769 relax_start (SYMBOL);
770 ... generate first expansion ...
771 relax_switch ();
772 ... generate second expansion ...
773 relax_end ();
774
775 The code and fixups for the unwanted alternative are discarded
776 by md_convert_frag. */
777 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
778
779 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
780 #define RELAX_SECOND(X) ((X) & 0xff)
781 #define RELAX_USE_SECOND 0x10000
782 #define RELAX_SECOND_LONGER 0x20000
783 #define RELAX_NOMACRO 0x40000
784 #define RELAX_DELAY_SLOT 0x80000
785
786 /* Branch without likely bit. If label is out of range, we turn:
787
788 beq reg1, reg2, label
789 delay slot
790
791 into
792
793 bne reg1, reg2, 0f
794 nop
795 j label
796 0: delay slot
797
798 with the following opcode replacements:
799
800 beq <-> bne
801 blez <-> bgtz
802 bltz <-> bgez
803 bc1f <-> bc1t
804
805 bltzal <-> bgezal (with jal label instead of j label)
806
807 Even though keeping the delay slot instruction in the delay slot of
808 the branch would be more efficient, it would be very tricky to do
809 correctly, because we'd have to introduce a variable frag *after*
810 the delay slot instruction, and expand that instead. Let's do it
811 the easy way for now, even if the branch-not-taken case now costs
812 one additional instruction. Out-of-range branches are not supposed
813 to be common, anyway.
814
815 Branch likely. If label is out of range, we turn:
816
817 beql reg1, reg2, label
818 delay slot (annulled if branch not taken)
819
820 into
821
822 beql reg1, reg2, 1f
823 nop
824 beql $0, $0, 2f
825 nop
826 1: j[al] label
827 delay slot (executed only if branch taken)
828 2:
829
830 It would be possible to generate a shorter sequence by losing the
831 likely bit, generating something like:
832
833 bne reg1, reg2, 0f
834 nop
835 j[al] label
836 delay slot (executed only if branch taken)
837 0:
838
839 beql -> bne
840 bnel -> beq
841 blezl -> bgtz
842 bgtzl -> blez
843 bltzl -> bgez
844 bgezl -> bltz
845 bc1fl -> bc1t
846 bc1tl -> bc1f
847
848 bltzall -> bgezal (with jal label instead of j label)
849 bgezall -> bltzal (ditto)
850
851
852 but it's not clear that it would actually improve performance. */
853 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
854 ((relax_substateT) \
855 (0xc0000000 \
856 | ((toofar) ? 1 : 0) \
857 | ((link) ? 2 : 0) \
858 | ((likely) ? 4 : 0) \
859 | ((uncond) ? 8 : 0)))
860 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
861 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
862 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
863 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
864 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
865
866 /* For mips16 code, we use an entirely different form of relaxation.
867 mips16 supports two versions of most instructions which take
868 immediate values: a small one which takes some small value, and a
869 larger one which takes a 16 bit value. Since branches also follow
870 this pattern, relaxing these values is required.
871
872 We can assemble both mips16 and normal MIPS code in a single
873 object. Therefore, we need to support this type of relaxation at
874 the same time that we support the relaxation described above. We
875 use the high bit of the subtype field to distinguish these cases.
876
877 The information we store for this type of relaxation is the
878 argument code found in the opcode file for this relocation, whether
879 the user explicitly requested a small or extended form, and whether
880 the relocation is in a jump or jal delay slot. That tells us the
881 size of the value, and how it should be stored. We also store
882 whether the fragment is considered to be extended or not. We also
883 store whether this is known to be a branch to a different section,
884 whether we have tried to relax this frag yet, and whether we have
885 ever extended a PC relative fragment because of a shift count. */
886 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
887 (0x80000000 \
888 | ((type) & 0xff) \
889 | ((small) ? 0x100 : 0) \
890 | ((ext) ? 0x200 : 0) \
891 | ((dslot) ? 0x400 : 0) \
892 | ((jal_dslot) ? 0x800 : 0))
893 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
894 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
895 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
896 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
897 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
898 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
899 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
900 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
901 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
902 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
903 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
904 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
905
906 /* Is the given value a sign-extended 32-bit value? */
907 #define IS_SEXT_32BIT_NUM(x) \
908 (((x) &~ (offsetT) 0x7fffffff) == 0 \
909 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
910
911 /* Is the given value a sign-extended 16-bit value? */
912 #define IS_SEXT_16BIT_NUM(x) \
913 (((x) &~ (offsetT) 0x7fff) == 0 \
914 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
915
916 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
917 #define IS_ZEXT_32BIT_NUM(x) \
918 (((x) &~ (offsetT) 0xffffffff) == 0 \
919 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
920
921 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
922 VALUE << SHIFT. VALUE is evaluated exactly once. */
923 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
924 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
925 | (((VALUE) & (MASK)) << (SHIFT)))
926
927 /* Extract bits MASK << SHIFT from STRUCT and shift them right
928 SHIFT places. */
929 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
930 (((STRUCT) >> (SHIFT)) & (MASK))
931
932 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
933 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
934
935 include/opcode/mips.h specifies operand fields using the macros
936 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
937 with "MIPS16OP" instead of "OP". */
938 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
939 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
940 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
941 INSERT_BITS ((INSN).insn_opcode, VALUE, \
942 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
943
944 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
945 #define EXTRACT_OPERAND(FIELD, INSN) \
946 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
947 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
948 EXTRACT_BITS ((INSN).insn_opcode, \
949 MIPS16OP_MASK_##FIELD, \
950 MIPS16OP_SH_##FIELD)
951 \f
952 /* Global variables used when generating relaxable macros. See the
953 comment above RELAX_ENCODE for more details about how relaxation
954 is used. */
955 static struct {
956 /* 0 if we're not emitting a relaxable macro.
957 1 if we're emitting the first of the two relaxation alternatives.
958 2 if we're emitting the second alternative. */
959 int sequence;
960
961 /* The first relaxable fixup in the current frag. (In other words,
962 the first fixup that refers to relaxable code.) */
963 fixS *first_fixup;
964
965 /* sizes[0] says how many bytes of the first alternative are stored in
966 the current frag. Likewise sizes[1] for the second alternative. */
967 unsigned int sizes[2];
968
969 /* The symbol on which the choice of sequence depends. */
970 symbolS *symbol;
971 } mips_relax;
972 \f
973 /* Global variables used to decide whether a macro needs a warning. */
974 static struct {
975 /* True if the macro is in a branch delay slot. */
976 bfd_boolean delay_slot_p;
977
978 /* For relaxable macros, sizes[0] is the length of the first alternative
979 in bytes and sizes[1] is the length of the second alternative.
980 For non-relaxable macros, both elements give the length of the
981 macro in bytes. */
982 unsigned int sizes[2];
983
984 /* The first variant frag for this macro. */
985 fragS *first_frag;
986 } mips_macro_warning;
987 \f
988 /* Prototypes for static functions. */
989
990 #define internalError() \
991 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
992
993 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
994
995 static void append_insn
996 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
997 static void mips_no_prev_insn (void);
998 static void mips16_macro_build
999 (expressionS *, const char *, const char *, va_list);
1000 static void load_register (int, expressionS *, int);
1001 static void macro_start (void);
1002 static void macro_end (void);
1003 static void macro (struct mips_cl_insn * ip);
1004 static void mips16_macro (struct mips_cl_insn * ip);
1005 #ifdef LOSING_COMPILER
1006 static void macro2 (struct mips_cl_insn * ip);
1007 #endif
1008 static void mips_ip (char *str, struct mips_cl_insn * ip);
1009 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1010 static void mips16_immed
1011 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1012 unsigned long *, bfd_boolean *, unsigned short *);
1013 static size_t my_getSmallExpression
1014 (expressionS *, bfd_reloc_code_real_type *, char *);
1015 static void my_getExpression (expressionS *, char *);
1016 static void s_align (int);
1017 static void s_change_sec (int);
1018 static void s_change_section (int);
1019 static void s_cons (int);
1020 static void s_float_cons (int);
1021 static void s_mips_globl (int);
1022 static void s_option (int);
1023 static void s_mipsset (int);
1024 static void s_abicalls (int);
1025 static void s_cpload (int);
1026 static void s_cpsetup (int);
1027 static void s_cplocal (int);
1028 static void s_cprestore (int);
1029 static void s_cpreturn (int);
1030 static void s_gpvalue (int);
1031 static void s_gpword (int);
1032 static void s_gpdword (int);
1033 static void s_cpadd (int);
1034 static void s_insn (int);
1035 static void md_obj_begin (void);
1036 static void md_obj_end (void);
1037 static void s_mips_ent (int);
1038 static void s_mips_end (int);
1039 static void s_mips_frame (int);
1040 static void s_mips_mask (int reg_type);
1041 static void s_mips_stab (int);
1042 static void s_mips_weakext (int);
1043 static void s_mips_file (int);
1044 static void s_mips_loc (int);
1045 static bfd_boolean pic_need_relax (symbolS *, asection *);
1046 static int relaxed_branch_length (fragS *, asection *, int);
1047 static int validate_mips_insn (const struct mips_opcode *);
1048
1049 /* Table and functions used to map between CPU/ISA names, and
1050 ISA levels, and CPU numbers. */
1051
1052 struct mips_cpu_info
1053 {
1054 const char *name; /* CPU or ISA name. */
1055 int flags; /* ASEs available, or ISA flag. */
1056 int isa; /* ISA level. */
1057 int cpu; /* CPU number (default CPU if ISA). */
1058 };
1059
1060 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1061 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1062 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1063 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1064 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1065 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1066
1067 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1068 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1069 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1070 \f
1071 /* Pseudo-op table.
1072
1073 The following pseudo-ops from the Kane and Heinrich MIPS book
1074 should be defined here, but are currently unsupported: .alias,
1075 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1076
1077 The following pseudo-ops from the Kane and Heinrich MIPS book are
1078 specific to the type of debugging information being generated, and
1079 should be defined by the object format: .aent, .begin, .bend,
1080 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1081 .vreg.
1082
1083 The following pseudo-ops from the Kane and Heinrich MIPS book are
1084 not MIPS CPU specific, but are also not specific to the object file
1085 format. This file is probably the best place to define them, but
1086 they are not currently supported: .asm0, .endr, .lab, .repeat,
1087 .struct. */
1088
1089 static const pseudo_typeS mips_pseudo_table[] =
1090 {
1091 /* MIPS specific pseudo-ops. */
1092 {"option", s_option, 0},
1093 {"set", s_mipsset, 0},
1094 {"rdata", s_change_sec, 'r'},
1095 {"sdata", s_change_sec, 's'},
1096 {"livereg", s_ignore, 0},
1097 {"abicalls", s_abicalls, 0},
1098 {"cpload", s_cpload, 0},
1099 {"cpsetup", s_cpsetup, 0},
1100 {"cplocal", s_cplocal, 0},
1101 {"cprestore", s_cprestore, 0},
1102 {"cpreturn", s_cpreturn, 0},
1103 {"gpvalue", s_gpvalue, 0},
1104 {"gpword", s_gpword, 0},
1105 {"gpdword", s_gpdword, 0},
1106 {"cpadd", s_cpadd, 0},
1107 {"insn", s_insn, 0},
1108
1109 /* Relatively generic pseudo-ops that happen to be used on MIPS
1110 chips. */
1111 {"asciiz", stringer, 1},
1112 {"bss", s_change_sec, 'b'},
1113 {"err", s_err, 0},
1114 {"half", s_cons, 1},
1115 {"dword", s_cons, 3},
1116 {"weakext", s_mips_weakext, 0},
1117
1118 /* These pseudo-ops are defined in read.c, but must be overridden
1119 here for one reason or another. */
1120 {"align", s_align, 0},
1121 {"byte", s_cons, 0},
1122 {"data", s_change_sec, 'd'},
1123 {"double", s_float_cons, 'd'},
1124 {"float", s_float_cons, 'f'},
1125 {"globl", s_mips_globl, 0},
1126 {"global", s_mips_globl, 0},
1127 {"hword", s_cons, 1},
1128 {"int", s_cons, 2},
1129 {"long", s_cons, 2},
1130 {"octa", s_cons, 4},
1131 {"quad", s_cons, 3},
1132 {"section", s_change_section, 0},
1133 {"short", s_cons, 1},
1134 {"single", s_float_cons, 'f'},
1135 {"stabn", s_mips_stab, 'n'},
1136 {"text", s_change_sec, 't'},
1137 {"word", s_cons, 2},
1138
1139 { "extern", ecoff_directive_extern, 0},
1140
1141 { NULL, NULL, 0 },
1142 };
1143
1144 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1145 {
1146 /* These pseudo-ops should be defined by the object file format.
1147 However, a.out doesn't support them, so we have versions here. */
1148 {"aent", s_mips_ent, 1},
1149 {"bgnb", s_ignore, 0},
1150 {"end", s_mips_end, 0},
1151 {"endb", s_ignore, 0},
1152 {"ent", s_mips_ent, 0},
1153 {"file", s_mips_file, 0},
1154 {"fmask", s_mips_mask, 'F'},
1155 {"frame", s_mips_frame, 0},
1156 {"loc", s_mips_loc, 0},
1157 {"mask", s_mips_mask, 'R'},
1158 {"verstamp", s_ignore, 0},
1159 { NULL, NULL, 0 },
1160 };
1161
1162 extern void pop_insert (const pseudo_typeS *);
1163
1164 void
1165 mips_pop_insert (void)
1166 {
1167 pop_insert (mips_pseudo_table);
1168 if (! ECOFF_DEBUGGING)
1169 pop_insert (mips_nonecoff_pseudo_table);
1170 }
1171 \f
1172 /* Symbols labelling the current insn. */
1173
1174 struct insn_label_list
1175 {
1176 struct insn_label_list *next;
1177 symbolS *label;
1178 };
1179
1180 static struct insn_label_list *insn_labels;
1181 static struct insn_label_list *free_insn_labels;
1182
1183 static void mips_clear_insn_labels (void);
1184
1185 static inline void
1186 mips_clear_insn_labels (void)
1187 {
1188 register struct insn_label_list **pl;
1189
1190 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1191 ;
1192 *pl = insn_labels;
1193 insn_labels = NULL;
1194 }
1195 \f
1196 static char *expr_end;
1197
1198 /* Expressions which appear in instructions. These are set by
1199 mips_ip. */
1200
1201 static expressionS imm_expr;
1202 static expressionS imm2_expr;
1203 static expressionS offset_expr;
1204
1205 /* Relocs associated with imm_expr and offset_expr. */
1206
1207 static bfd_reloc_code_real_type imm_reloc[3]
1208 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1209 static bfd_reloc_code_real_type offset_reloc[3]
1210 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1211
1212 /* These are set by mips16_ip if an explicit extension is used. */
1213
1214 static bfd_boolean mips16_small, mips16_ext;
1215
1216 #ifdef OBJ_ELF
1217 /* The pdr segment for per procedure frame/regmask info. Not used for
1218 ECOFF debugging. */
1219
1220 static segT pdr_seg;
1221 #endif
1222
1223 /* The default target format to use. */
1224
1225 const char *
1226 mips_target_format (void)
1227 {
1228 switch (OUTPUT_FLAVOR)
1229 {
1230 case bfd_target_ecoff_flavour:
1231 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1232 case bfd_target_coff_flavour:
1233 return "pe-mips";
1234 case bfd_target_elf_flavour:
1235 #ifdef TE_VXWORKS
1236 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1237 return (target_big_endian
1238 ? "elf32-bigmips-vxworks"
1239 : "elf32-littlemips-vxworks");
1240 #endif
1241 #ifdef TE_TMIPS
1242 /* This is traditional mips. */
1243 return (target_big_endian
1244 ? (HAVE_64BIT_OBJECTS
1245 ? "elf64-tradbigmips"
1246 : (HAVE_NEWABI
1247 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1248 : (HAVE_64BIT_OBJECTS
1249 ? "elf64-tradlittlemips"
1250 : (HAVE_NEWABI
1251 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1252 #else
1253 return (target_big_endian
1254 ? (HAVE_64BIT_OBJECTS
1255 ? "elf64-bigmips"
1256 : (HAVE_NEWABI
1257 ? "elf32-nbigmips" : "elf32-bigmips"))
1258 : (HAVE_64BIT_OBJECTS
1259 ? "elf64-littlemips"
1260 : (HAVE_NEWABI
1261 ? "elf32-nlittlemips" : "elf32-littlemips")));
1262 #endif
1263 default:
1264 abort ();
1265 return NULL;
1266 }
1267 }
1268
1269 /* Return the length of instruction INSN. */
1270
1271 static inline unsigned int
1272 insn_length (const struct mips_cl_insn *insn)
1273 {
1274 if (!mips_opts.mips16)
1275 return 4;
1276 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1277 }
1278
1279 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1280
1281 static void
1282 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1283 {
1284 size_t i;
1285
1286 insn->insn_mo = mo;
1287 insn->use_extend = FALSE;
1288 insn->extend = 0;
1289 insn->insn_opcode = mo->match;
1290 insn->frag = NULL;
1291 insn->where = 0;
1292 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1293 insn->fixp[i] = NULL;
1294 insn->fixed_p = (mips_opts.noreorder > 0);
1295 insn->noreorder_p = (mips_opts.noreorder > 0);
1296 insn->mips16_absolute_jump_p = 0;
1297 }
1298
1299 /* Install INSN at the location specified by its "frag" and "where" fields. */
1300
1301 static void
1302 install_insn (const struct mips_cl_insn *insn)
1303 {
1304 char *f = insn->frag->fr_literal + insn->where;
1305 if (!mips_opts.mips16)
1306 md_number_to_chars (f, insn->insn_opcode, 4);
1307 else if (insn->mips16_absolute_jump_p)
1308 {
1309 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1310 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1311 }
1312 else
1313 {
1314 if (insn->use_extend)
1315 {
1316 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1317 f += 2;
1318 }
1319 md_number_to_chars (f, insn->insn_opcode, 2);
1320 }
1321 }
1322
1323 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1324 and install the opcode in the new location. */
1325
1326 static void
1327 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1328 {
1329 size_t i;
1330
1331 insn->frag = frag;
1332 insn->where = where;
1333 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1334 if (insn->fixp[i] != NULL)
1335 {
1336 insn->fixp[i]->fx_frag = frag;
1337 insn->fixp[i]->fx_where = where;
1338 }
1339 install_insn (insn);
1340 }
1341
1342 /* Add INSN to the end of the output. */
1343
1344 static void
1345 add_fixed_insn (struct mips_cl_insn *insn)
1346 {
1347 char *f = frag_more (insn_length (insn));
1348 move_insn (insn, frag_now, f - frag_now->fr_literal);
1349 }
1350
1351 /* Start a variant frag and move INSN to the start of the variant part,
1352 marking it as fixed. The other arguments are as for frag_var. */
1353
1354 static void
1355 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1356 relax_substateT subtype, symbolS *symbol, offsetT offset)
1357 {
1358 frag_grow (max_chars);
1359 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1360 insn->fixed_p = 1;
1361 frag_var (rs_machine_dependent, max_chars, var,
1362 subtype, symbol, offset, NULL);
1363 }
1364
1365 /* Insert N copies of INSN into the history buffer, starting at
1366 position FIRST. Neither FIRST nor N need to be clipped. */
1367
1368 static void
1369 insert_into_history (unsigned int first, unsigned int n,
1370 const struct mips_cl_insn *insn)
1371 {
1372 if (mips_relax.sequence != 2)
1373 {
1374 unsigned int i;
1375
1376 for (i = ARRAY_SIZE (history); i-- > first;)
1377 if (i >= first + n)
1378 history[i] = history[i - n];
1379 else
1380 history[i] = *insn;
1381 }
1382 }
1383
1384 /* Emit a nop instruction, recording it in the history buffer. */
1385
1386 static void
1387 emit_nop (void)
1388 {
1389 add_fixed_insn (NOP_INSN);
1390 insert_into_history (0, 1, NOP_INSN);
1391 }
1392
1393 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1394 the idea is to make it obvious at a glance that each errata is
1395 included. */
1396
1397 static void
1398 init_vr4120_conflicts (void)
1399 {
1400 #define CONFLICT(FIRST, SECOND) \
1401 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1402
1403 /* Errata 21 - [D]DIV[U] after [D]MACC */
1404 CONFLICT (MACC, DIV);
1405 CONFLICT (DMACC, DIV);
1406
1407 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1408 CONFLICT (DMULT, DMULT);
1409 CONFLICT (DMULT, DMACC);
1410 CONFLICT (DMACC, DMULT);
1411 CONFLICT (DMACC, DMACC);
1412
1413 /* Errata 24 - MT{LO,HI} after [D]MACC */
1414 CONFLICT (MACC, MTHILO);
1415 CONFLICT (DMACC, MTHILO);
1416
1417 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1418 instruction is executed immediately after a MACC or DMACC
1419 instruction, the result of [either instruction] is incorrect." */
1420 CONFLICT (MACC, MULT);
1421 CONFLICT (MACC, DMULT);
1422 CONFLICT (DMACC, MULT);
1423 CONFLICT (DMACC, DMULT);
1424
1425 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1426 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1427 DDIV or DDIVU instruction, the result of the MACC or
1428 DMACC instruction is incorrect.". */
1429 CONFLICT (DMULT, MACC);
1430 CONFLICT (DMULT, DMACC);
1431 CONFLICT (DIV, MACC);
1432 CONFLICT (DIV, DMACC);
1433
1434 #undef CONFLICT
1435 }
1436
1437 struct regname {
1438 const char *name;
1439 unsigned int num;
1440 };
1441
1442 #define RTYPE_MASK 0x1ff00
1443 #define RTYPE_NUM 0x00100
1444 #define RTYPE_FPU 0x00200
1445 #define RTYPE_FCC 0x00400
1446 #define RTYPE_VEC 0x00800
1447 #define RTYPE_GP 0x01000
1448 #define RTYPE_CP0 0x02000
1449 #define RTYPE_PC 0x04000
1450 #define RTYPE_ACC 0x08000
1451 #define RTYPE_CCC 0x10000
1452 #define RNUM_MASK 0x000ff
1453 #define RWARN 0x80000
1454
1455 #define GENERIC_REGISTER_NUMBERS \
1456 {"$0", RTYPE_NUM | 0}, \
1457 {"$1", RTYPE_NUM | 1}, \
1458 {"$2", RTYPE_NUM | 2}, \
1459 {"$3", RTYPE_NUM | 3}, \
1460 {"$4", RTYPE_NUM | 4}, \
1461 {"$5", RTYPE_NUM | 5}, \
1462 {"$6", RTYPE_NUM | 6}, \
1463 {"$7", RTYPE_NUM | 7}, \
1464 {"$8", RTYPE_NUM | 8}, \
1465 {"$9", RTYPE_NUM | 9}, \
1466 {"$10", RTYPE_NUM | 10}, \
1467 {"$11", RTYPE_NUM | 11}, \
1468 {"$12", RTYPE_NUM | 12}, \
1469 {"$13", RTYPE_NUM | 13}, \
1470 {"$14", RTYPE_NUM | 14}, \
1471 {"$15", RTYPE_NUM | 15}, \
1472 {"$16", RTYPE_NUM | 16}, \
1473 {"$17", RTYPE_NUM | 17}, \
1474 {"$18", RTYPE_NUM | 18}, \
1475 {"$19", RTYPE_NUM | 19}, \
1476 {"$20", RTYPE_NUM | 20}, \
1477 {"$21", RTYPE_NUM | 21}, \
1478 {"$22", RTYPE_NUM | 22}, \
1479 {"$23", RTYPE_NUM | 23}, \
1480 {"$24", RTYPE_NUM | 24}, \
1481 {"$25", RTYPE_NUM | 25}, \
1482 {"$26", RTYPE_NUM | 26}, \
1483 {"$27", RTYPE_NUM | 27}, \
1484 {"$28", RTYPE_NUM | 28}, \
1485 {"$29", RTYPE_NUM | 29}, \
1486 {"$30", RTYPE_NUM | 30}, \
1487 {"$31", RTYPE_NUM | 31}
1488
1489 #define FPU_REGISTER_NAMES \
1490 {"$f0", RTYPE_FPU | 0}, \
1491 {"$f1", RTYPE_FPU | 1}, \
1492 {"$f2", RTYPE_FPU | 2}, \
1493 {"$f3", RTYPE_FPU | 3}, \
1494 {"$f4", RTYPE_FPU | 4}, \
1495 {"$f5", RTYPE_FPU | 5}, \
1496 {"$f6", RTYPE_FPU | 6}, \
1497 {"$f7", RTYPE_FPU | 7}, \
1498 {"$f8", RTYPE_FPU | 8}, \
1499 {"$f9", RTYPE_FPU | 9}, \
1500 {"$f10", RTYPE_FPU | 10}, \
1501 {"$f11", RTYPE_FPU | 11}, \
1502 {"$f12", RTYPE_FPU | 12}, \
1503 {"$f13", RTYPE_FPU | 13}, \
1504 {"$f14", RTYPE_FPU | 14}, \
1505 {"$f15", RTYPE_FPU | 15}, \
1506 {"$f16", RTYPE_FPU | 16}, \
1507 {"$f17", RTYPE_FPU | 17}, \
1508 {"$f18", RTYPE_FPU | 18}, \
1509 {"$f19", RTYPE_FPU | 19}, \
1510 {"$f20", RTYPE_FPU | 20}, \
1511 {"$f21", RTYPE_FPU | 21}, \
1512 {"$f22", RTYPE_FPU | 22}, \
1513 {"$f23", RTYPE_FPU | 23}, \
1514 {"$f24", RTYPE_FPU | 24}, \
1515 {"$f25", RTYPE_FPU | 25}, \
1516 {"$f26", RTYPE_FPU | 26}, \
1517 {"$f27", RTYPE_FPU | 27}, \
1518 {"$f28", RTYPE_FPU | 28}, \
1519 {"$f29", RTYPE_FPU | 29}, \
1520 {"$f30", RTYPE_FPU | 30}, \
1521 {"$f31", RTYPE_FPU | 31}
1522
1523 #define FPU_CONDITION_CODE_NAMES \
1524 {"$fcc0", RTYPE_FCC | 0}, \
1525 {"$fcc1", RTYPE_FCC | 1}, \
1526 {"$fcc2", RTYPE_FCC | 2}, \
1527 {"$fcc3", RTYPE_FCC | 3}, \
1528 {"$fcc4", RTYPE_FCC | 4}, \
1529 {"$fcc5", RTYPE_FCC | 5}, \
1530 {"$fcc6", RTYPE_FCC | 6}, \
1531 {"$fcc7", RTYPE_FCC | 7}
1532
1533 #define COPROC_CONDITION_CODE_NAMES \
1534 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1535 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1536 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1537 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1538 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1539 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1540 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1541 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1542
1543 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1544 {"$a4", RTYPE_GP | 8}, \
1545 {"$a5", RTYPE_GP | 9}, \
1546 {"$a6", RTYPE_GP | 10}, \
1547 {"$a7", RTYPE_GP | 11}, \
1548 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1549 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1550 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1551 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1552 {"$t0", RTYPE_GP | 12}, \
1553 {"$t1", RTYPE_GP | 13}, \
1554 {"$t2", RTYPE_GP | 14}, \
1555 {"$t3", RTYPE_GP | 15}
1556
1557 #define O32_SYMBOLIC_REGISTER_NAMES \
1558 {"$t0", RTYPE_GP | 8}, \
1559 {"$t1", RTYPE_GP | 9}, \
1560 {"$t2", RTYPE_GP | 10}, \
1561 {"$t3", RTYPE_GP | 11}, \
1562 {"$t4", RTYPE_GP | 12}, \
1563 {"$t5", RTYPE_GP | 13}, \
1564 {"$t6", RTYPE_GP | 14}, \
1565 {"$t7", RTYPE_GP | 15}, \
1566 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1567 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1568 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1569 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1570
1571 /* Remaining symbolic register names */
1572 #define SYMBOLIC_REGISTER_NAMES \
1573 {"$zero", RTYPE_GP | 0}, \
1574 {"$at", RTYPE_GP | 1}, \
1575 {"$AT", RTYPE_GP | 1}, \
1576 {"$v0", RTYPE_GP | 2}, \
1577 {"$v1", RTYPE_GP | 3}, \
1578 {"$a0", RTYPE_GP | 4}, \
1579 {"$a1", RTYPE_GP | 5}, \
1580 {"$a2", RTYPE_GP | 6}, \
1581 {"$a3", RTYPE_GP | 7}, \
1582 {"$s0", RTYPE_GP | 16}, \
1583 {"$s1", RTYPE_GP | 17}, \
1584 {"$s2", RTYPE_GP | 18}, \
1585 {"$s3", RTYPE_GP | 19}, \
1586 {"$s4", RTYPE_GP | 20}, \
1587 {"$s5", RTYPE_GP | 21}, \
1588 {"$s6", RTYPE_GP | 22}, \
1589 {"$s7", RTYPE_GP | 23}, \
1590 {"$t8", RTYPE_GP | 24}, \
1591 {"$t9", RTYPE_GP | 25}, \
1592 {"$k0", RTYPE_GP | 26}, \
1593 {"$kt0", RTYPE_GP | 26}, \
1594 {"$k1", RTYPE_GP | 27}, \
1595 {"$kt1", RTYPE_GP | 27}, \
1596 {"$gp", RTYPE_GP | 28}, \
1597 {"$sp", RTYPE_GP | 29}, \
1598 {"$s8", RTYPE_GP | 30}, \
1599 {"$fp", RTYPE_GP | 30}, \
1600 {"$ra", RTYPE_GP | 31}
1601
1602 #define MIPS16_SPECIAL_REGISTER_NAMES \
1603 {"$pc", RTYPE_PC | 0}
1604
1605 #define MDMX_VECTOR_REGISTER_NAMES \
1606 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1607 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1608 {"$v2", RTYPE_VEC | 2}, \
1609 {"$v3", RTYPE_VEC | 3}, \
1610 {"$v4", RTYPE_VEC | 4}, \
1611 {"$v5", RTYPE_VEC | 5}, \
1612 {"$v6", RTYPE_VEC | 6}, \
1613 {"$v7", RTYPE_VEC | 7}, \
1614 {"$v8", RTYPE_VEC | 8}, \
1615 {"$v9", RTYPE_VEC | 9}, \
1616 {"$v10", RTYPE_VEC | 10}, \
1617 {"$v11", RTYPE_VEC | 11}, \
1618 {"$v12", RTYPE_VEC | 12}, \
1619 {"$v13", RTYPE_VEC | 13}, \
1620 {"$v14", RTYPE_VEC | 14}, \
1621 {"$v15", RTYPE_VEC | 15}, \
1622 {"$v16", RTYPE_VEC | 16}, \
1623 {"$v17", RTYPE_VEC | 17}, \
1624 {"$v18", RTYPE_VEC | 18}, \
1625 {"$v19", RTYPE_VEC | 19}, \
1626 {"$v20", RTYPE_VEC | 20}, \
1627 {"$v21", RTYPE_VEC | 21}, \
1628 {"$v22", RTYPE_VEC | 22}, \
1629 {"$v23", RTYPE_VEC | 23}, \
1630 {"$v24", RTYPE_VEC | 24}, \
1631 {"$v25", RTYPE_VEC | 25}, \
1632 {"$v26", RTYPE_VEC | 26}, \
1633 {"$v27", RTYPE_VEC | 27}, \
1634 {"$v28", RTYPE_VEC | 28}, \
1635 {"$v29", RTYPE_VEC | 29}, \
1636 {"$v30", RTYPE_VEC | 30}, \
1637 {"$v31", RTYPE_VEC | 31}
1638
1639 #define MIPS_DSP_ACCUMULATOR_NAMES \
1640 {"$ac0", RTYPE_ACC | 0}, \
1641 {"$ac1", RTYPE_ACC | 1}, \
1642 {"$ac2", RTYPE_ACC | 2}, \
1643 {"$ac3", RTYPE_ACC | 3}
1644
1645 static const struct regname reg_names[] = {
1646 GENERIC_REGISTER_NUMBERS,
1647 FPU_REGISTER_NAMES,
1648 FPU_CONDITION_CODE_NAMES,
1649 COPROC_CONDITION_CODE_NAMES,
1650
1651 /* The $txx registers depends on the abi,
1652 these will be added later into the symbol table from
1653 one of the tables below once mips_abi is set after
1654 parsing of arguments from the command line. */
1655 SYMBOLIC_REGISTER_NAMES,
1656
1657 MIPS16_SPECIAL_REGISTER_NAMES,
1658 MDMX_VECTOR_REGISTER_NAMES,
1659 MIPS_DSP_ACCUMULATOR_NAMES,
1660 {0, 0}
1661 };
1662
1663 static const struct regname reg_names_o32[] = {
1664 O32_SYMBOLIC_REGISTER_NAMES,
1665 {0, 0}
1666 };
1667
1668 static const struct regname reg_names_n32n64[] = {
1669 N32N64_SYMBOLIC_REGISTER_NAMES,
1670 {0, 0}
1671 };
1672
1673 static int
1674 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1675 {
1676 symbolS *symbolP;
1677 char *e;
1678 char save_c;
1679 int reg = -1;
1680
1681 /* Find end of name. */
1682 e = *s;
1683 if (is_name_beginner (*e))
1684 ++e;
1685 while (is_part_of_name (*e))
1686 ++e;
1687
1688 /* Terminate name. */
1689 save_c = *e;
1690 *e = '\0';
1691
1692 /* Look for a register symbol. */
1693 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1694 {
1695 int r = S_GET_VALUE (symbolP);
1696 if (r & types)
1697 reg = r & RNUM_MASK;
1698 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1699 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1700 reg = (r & RNUM_MASK) - 2;
1701 }
1702 /* Else see if this is a register defined in an itbl entry. */
1703 else if ((types & RTYPE_GP) && itbl_have_entries)
1704 {
1705 char *n = *s;
1706 unsigned long r;
1707
1708 if (*n == '$')
1709 ++n;
1710 if (itbl_get_reg_val (n, &r))
1711 reg = r & RNUM_MASK;
1712 }
1713
1714 /* Advance to next token if a register was recognised. */
1715 if (reg >= 0)
1716 *s = e;
1717 else if (types & RWARN)
1718 as_warn ("Unrecognized register name `%s'", *s);
1719
1720 *e = save_c;
1721 if (regnop)
1722 *regnop = reg;
1723 return reg >= 0;
1724 }
1725
1726 /* This function is called once, at assembler startup time. It should set up
1727 all the tables, etc. that the MD part of the assembler will need. */
1728
1729 void
1730 md_begin (void)
1731 {
1732 register const char *retval = NULL;
1733 int i = 0;
1734 int broken = 0;
1735
1736 if (mips_pic != NO_PIC)
1737 {
1738 if (g_switch_seen && g_switch_value != 0)
1739 as_bad (_("-G may not be used in position-independent code"));
1740 g_switch_value = 0;
1741 }
1742
1743 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1744 as_warn (_("Could not set architecture and machine"));
1745
1746 op_hash = hash_new ();
1747
1748 for (i = 0; i < NUMOPCODES;)
1749 {
1750 const char *name = mips_opcodes[i].name;
1751
1752 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1753 if (retval != NULL)
1754 {
1755 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1756 mips_opcodes[i].name, retval);
1757 /* Probably a memory allocation problem? Give up now. */
1758 as_fatal (_("Broken assembler. No assembly attempted."));
1759 }
1760 do
1761 {
1762 if (mips_opcodes[i].pinfo != INSN_MACRO)
1763 {
1764 if (!validate_mips_insn (&mips_opcodes[i]))
1765 broken = 1;
1766 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1767 {
1768 create_insn (&nop_insn, mips_opcodes + i);
1769 nop_insn.fixed_p = 1;
1770 }
1771 }
1772 ++i;
1773 }
1774 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1775 }
1776
1777 mips16_op_hash = hash_new ();
1778
1779 i = 0;
1780 while (i < bfd_mips16_num_opcodes)
1781 {
1782 const char *name = mips16_opcodes[i].name;
1783
1784 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1785 if (retval != NULL)
1786 as_fatal (_("internal: can't hash `%s': %s"),
1787 mips16_opcodes[i].name, retval);
1788 do
1789 {
1790 if (mips16_opcodes[i].pinfo != INSN_MACRO
1791 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1792 != mips16_opcodes[i].match))
1793 {
1794 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1795 mips16_opcodes[i].name, mips16_opcodes[i].args);
1796 broken = 1;
1797 }
1798 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1799 {
1800 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1801 mips16_nop_insn.fixed_p = 1;
1802 }
1803 ++i;
1804 }
1805 while (i < bfd_mips16_num_opcodes
1806 && strcmp (mips16_opcodes[i].name, name) == 0);
1807 }
1808
1809 if (broken)
1810 as_fatal (_("Broken assembler. No assembly attempted."));
1811
1812 /* We add all the general register names to the symbol table. This
1813 helps us detect invalid uses of them. */
1814 for (i = 0; reg_names[i].name; i++)
1815 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1816 reg_names[i].num, // & RNUM_MASK,
1817 &zero_address_frag));
1818 if (HAVE_NEWABI)
1819 for (i = 0; reg_names_n32n64[i].name; i++)
1820 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1821 reg_names_n32n64[i].num, // & RNUM_MASK,
1822 &zero_address_frag));
1823 else
1824 for (i = 0; reg_names_o32[i].name; i++)
1825 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1826 reg_names_o32[i].num, // & RNUM_MASK,
1827 &zero_address_frag));
1828
1829 mips_no_prev_insn ();
1830
1831 mips_gprmask = 0;
1832 mips_cprmask[0] = 0;
1833 mips_cprmask[1] = 0;
1834 mips_cprmask[2] = 0;
1835 mips_cprmask[3] = 0;
1836
1837 /* set the default alignment for the text section (2**2) */
1838 record_alignment (text_section, 2);
1839
1840 bfd_set_gp_size (stdoutput, g_switch_value);
1841
1842 #ifdef OBJ_ELF
1843 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1844 {
1845 /* On a native system other than VxWorks, sections must be aligned
1846 to 16 byte boundaries. When configured for an embedded ELF
1847 target, we don't bother. */
1848 if (strcmp (TARGET_OS, "elf") != 0
1849 && strcmp (TARGET_OS, "vxworks") != 0)
1850 {
1851 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1852 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1853 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1854 }
1855
1856 /* Create a .reginfo section for register masks and a .mdebug
1857 section for debugging information. */
1858 {
1859 segT seg;
1860 subsegT subseg;
1861 flagword flags;
1862 segT sec;
1863
1864 seg = now_seg;
1865 subseg = now_subseg;
1866
1867 /* The ABI says this section should be loaded so that the
1868 running program can access it. However, we don't load it
1869 if we are configured for an embedded target */
1870 flags = SEC_READONLY | SEC_DATA;
1871 if (strcmp (TARGET_OS, "elf") != 0)
1872 flags |= SEC_ALLOC | SEC_LOAD;
1873
1874 if (mips_abi != N64_ABI)
1875 {
1876 sec = subseg_new (".reginfo", (subsegT) 0);
1877
1878 bfd_set_section_flags (stdoutput, sec, flags);
1879 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1880
1881 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1882 }
1883 else
1884 {
1885 /* The 64-bit ABI uses a .MIPS.options section rather than
1886 .reginfo section. */
1887 sec = subseg_new (".MIPS.options", (subsegT) 0);
1888 bfd_set_section_flags (stdoutput, sec, flags);
1889 bfd_set_section_alignment (stdoutput, sec, 3);
1890
1891 /* Set up the option header. */
1892 {
1893 Elf_Internal_Options opthdr;
1894 char *f;
1895
1896 opthdr.kind = ODK_REGINFO;
1897 opthdr.size = (sizeof (Elf_External_Options)
1898 + sizeof (Elf64_External_RegInfo));
1899 opthdr.section = 0;
1900 opthdr.info = 0;
1901 f = frag_more (sizeof (Elf_External_Options));
1902 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1903 (Elf_External_Options *) f);
1904
1905 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1906 }
1907 }
1908
1909 if (ECOFF_DEBUGGING)
1910 {
1911 sec = subseg_new (".mdebug", (subsegT) 0);
1912 (void) bfd_set_section_flags (stdoutput, sec,
1913 SEC_HAS_CONTENTS | SEC_READONLY);
1914 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1915 }
1916 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1917 {
1918 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1919 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1920 SEC_READONLY | SEC_RELOC
1921 | SEC_DEBUGGING);
1922 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1923 }
1924
1925 subseg_set (seg, subseg);
1926 }
1927 }
1928 #endif /* OBJ_ELF */
1929
1930 if (! ECOFF_DEBUGGING)
1931 md_obj_begin ();
1932
1933 if (mips_fix_vr4120)
1934 init_vr4120_conflicts ();
1935 }
1936
1937 void
1938 md_mips_end (void)
1939 {
1940 if (! ECOFF_DEBUGGING)
1941 md_obj_end ();
1942 }
1943
1944 void
1945 md_assemble (char *str)
1946 {
1947 struct mips_cl_insn insn;
1948 bfd_reloc_code_real_type unused_reloc[3]
1949 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1950
1951 imm_expr.X_op = O_absent;
1952 imm2_expr.X_op = O_absent;
1953 offset_expr.X_op = O_absent;
1954 imm_reloc[0] = BFD_RELOC_UNUSED;
1955 imm_reloc[1] = BFD_RELOC_UNUSED;
1956 imm_reloc[2] = BFD_RELOC_UNUSED;
1957 offset_reloc[0] = BFD_RELOC_UNUSED;
1958 offset_reloc[1] = BFD_RELOC_UNUSED;
1959 offset_reloc[2] = BFD_RELOC_UNUSED;
1960
1961 if (mips_opts.mips16)
1962 mips16_ip (str, &insn);
1963 else
1964 {
1965 mips_ip (str, &insn);
1966 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1967 str, insn.insn_opcode));
1968 }
1969
1970 if (insn_error)
1971 {
1972 as_bad ("%s `%s'", insn_error, str);
1973 return;
1974 }
1975
1976 if (insn.insn_mo->pinfo == INSN_MACRO)
1977 {
1978 macro_start ();
1979 if (mips_opts.mips16)
1980 mips16_macro (&insn);
1981 else
1982 macro (&insn);
1983 macro_end ();
1984 }
1985 else
1986 {
1987 if (imm_expr.X_op != O_absent)
1988 append_insn (&insn, &imm_expr, imm_reloc);
1989 else if (offset_expr.X_op != O_absent)
1990 append_insn (&insn, &offset_expr, offset_reloc);
1991 else
1992 append_insn (&insn, NULL, unused_reloc);
1993 }
1994 }
1995
1996 /* Return true if the given relocation might need a matching %lo().
1997 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1998 need a matching %lo() when applied to local symbols. */
1999
2000 static inline bfd_boolean
2001 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2002 {
2003 return (HAVE_IN_PLACE_ADDENDS
2004 && (reloc == BFD_RELOC_HI16_S
2005 || reloc == BFD_RELOC_MIPS16_HI16_S
2006 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2007 all GOT16 relocations evaluate to "G". */
2008 || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC)));
2009 }
2010
2011 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2012 relocation. */
2013
2014 static inline bfd_boolean
2015 fixup_has_matching_lo_p (fixS *fixp)
2016 {
2017 return (fixp->fx_next != NULL
2018 && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
2019 || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
2020 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2021 && fixp->fx_offset == fixp->fx_next->fx_offset);
2022 }
2023
2024 /* See whether instruction IP reads register REG. CLASS is the type
2025 of register. */
2026
2027 static int
2028 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2029 enum mips_regclass class)
2030 {
2031 if (class == MIPS16_REG)
2032 {
2033 assert (mips_opts.mips16);
2034 reg = mips16_to_32_reg_map[reg];
2035 class = MIPS_GR_REG;
2036 }
2037
2038 /* Don't report on general register ZERO, since it never changes. */
2039 if (class == MIPS_GR_REG && reg == ZERO)
2040 return 0;
2041
2042 if (class == MIPS_FP_REG)
2043 {
2044 assert (! mips_opts.mips16);
2045 /* If we are called with either $f0 or $f1, we must check $f0.
2046 This is not optimal, because it will introduce an unnecessary
2047 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2048 need to distinguish reading both $f0 and $f1 or just one of
2049 them. Note that we don't have to check the other way,
2050 because there is no instruction that sets both $f0 and $f1
2051 and requires a delay. */
2052 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2053 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2054 == (reg &~ (unsigned) 1)))
2055 return 1;
2056 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2057 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2058 == (reg &~ (unsigned) 1)))
2059 return 1;
2060 }
2061 else if (! mips_opts.mips16)
2062 {
2063 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2064 && EXTRACT_OPERAND (RS, *ip) == reg)
2065 return 1;
2066 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2067 && EXTRACT_OPERAND (RT, *ip) == reg)
2068 return 1;
2069 }
2070 else
2071 {
2072 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2073 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2074 return 1;
2075 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2076 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2077 return 1;
2078 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2079 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2080 == reg))
2081 return 1;
2082 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2083 return 1;
2084 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2085 return 1;
2086 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2087 return 1;
2088 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2089 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2090 return 1;
2091 }
2092
2093 return 0;
2094 }
2095
2096 /* This function returns true if modifying a register requires a
2097 delay. */
2098
2099 static int
2100 reg_needs_delay (unsigned int reg)
2101 {
2102 unsigned long prev_pinfo;
2103
2104 prev_pinfo = history[0].insn_mo->pinfo;
2105 if (! mips_opts.noreorder
2106 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2107 && ! gpr_interlocks)
2108 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2109 && ! cop_interlocks)))
2110 {
2111 /* A load from a coprocessor or from memory. All load delays
2112 delay the use of general register rt for one instruction. */
2113 /* Itbl support may require additional care here. */
2114 know (prev_pinfo & INSN_WRITE_GPR_T);
2115 if (reg == EXTRACT_OPERAND (RT, history[0]))
2116 return 1;
2117 }
2118
2119 return 0;
2120 }
2121
2122 /* Move all labels in insn_labels to the current insertion point. */
2123
2124 static void
2125 mips_move_labels (void)
2126 {
2127 struct insn_label_list *l;
2128 valueT val;
2129
2130 for (l = insn_labels; l != NULL; l = l->next)
2131 {
2132 assert (S_GET_SEGMENT (l->label) == now_seg);
2133 symbol_set_frag (l->label, frag_now);
2134 val = (valueT) frag_now_fix ();
2135 /* mips16 text labels are stored as odd. */
2136 if (mips_opts.mips16)
2137 ++val;
2138 S_SET_VALUE (l->label, val);
2139 }
2140 }
2141
2142 /* Mark instruction labels in mips16 mode. This permits the linker to
2143 handle them specially, such as generating jalx instructions when
2144 needed. We also make them odd for the duration of the assembly, in
2145 order to generate the right sort of code. We will make them even
2146 in the adjust_symtab routine, while leaving them marked. This is
2147 convenient for the debugger and the disassembler. The linker knows
2148 to make them odd again. */
2149
2150 static void
2151 mips16_mark_labels (void)
2152 {
2153 if (mips_opts.mips16)
2154 {
2155 struct insn_label_list *l;
2156 valueT val;
2157
2158 for (l = insn_labels; l != NULL; l = l->next)
2159 {
2160 #ifdef OBJ_ELF
2161 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
2162 S_SET_OTHER (l->label, STO_MIPS16);
2163 #endif
2164 val = S_GET_VALUE (l->label);
2165 if ((val & 1) == 0)
2166 S_SET_VALUE (l->label, val + 1);
2167 }
2168 }
2169 }
2170
2171 /* End the current frag. Make it a variant frag and record the
2172 relaxation info. */
2173
2174 static void
2175 relax_close_frag (void)
2176 {
2177 mips_macro_warning.first_frag = frag_now;
2178 frag_var (rs_machine_dependent, 0, 0,
2179 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2180 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2181
2182 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2183 mips_relax.first_fixup = 0;
2184 }
2185
2186 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2187 See the comment above RELAX_ENCODE for more details. */
2188
2189 static void
2190 relax_start (symbolS *symbol)
2191 {
2192 assert (mips_relax.sequence == 0);
2193 mips_relax.sequence = 1;
2194 mips_relax.symbol = symbol;
2195 }
2196
2197 /* Start generating the second version of a relaxable sequence.
2198 See the comment above RELAX_ENCODE for more details. */
2199
2200 static void
2201 relax_switch (void)
2202 {
2203 assert (mips_relax.sequence == 1);
2204 mips_relax.sequence = 2;
2205 }
2206
2207 /* End the current relaxable sequence. */
2208
2209 static void
2210 relax_end (void)
2211 {
2212 assert (mips_relax.sequence == 2);
2213 relax_close_frag ();
2214 mips_relax.sequence = 0;
2215 }
2216
2217 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2218 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2219 by VR4120 errata. */
2220
2221 static unsigned int
2222 classify_vr4120_insn (const char *name)
2223 {
2224 if (strncmp (name, "macc", 4) == 0)
2225 return FIX_VR4120_MACC;
2226 if (strncmp (name, "dmacc", 5) == 0)
2227 return FIX_VR4120_DMACC;
2228 if (strncmp (name, "mult", 4) == 0)
2229 return FIX_VR4120_MULT;
2230 if (strncmp (name, "dmult", 5) == 0)
2231 return FIX_VR4120_DMULT;
2232 if (strstr (name, "div"))
2233 return FIX_VR4120_DIV;
2234 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2235 return FIX_VR4120_MTHILO;
2236 return NUM_FIX_VR4120_CLASSES;
2237 }
2238
2239 /* Return the number of instructions that must separate INSN1 and INSN2,
2240 where INSN1 is the earlier instruction. Return the worst-case value
2241 for any INSN2 if INSN2 is null. */
2242
2243 static unsigned int
2244 insns_between (const struct mips_cl_insn *insn1,
2245 const struct mips_cl_insn *insn2)
2246 {
2247 unsigned long pinfo1, pinfo2;
2248
2249 /* This function needs to know which pinfo flags are set for INSN2
2250 and which registers INSN2 uses. The former is stored in PINFO2 and
2251 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2252 will have every flag set and INSN2_USES_REG will always return true. */
2253 pinfo1 = insn1->insn_mo->pinfo;
2254 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2255
2256 #define INSN2_USES_REG(REG, CLASS) \
2257 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2258
2259 /* For most targets, write-after-read dependencies on the HI and LO
2260 registers must be separated by at least two instructions. */
2261 if (!hilo_interlocks)
2262 {
2263 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2264 return 2;
2265 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2266 return 2;
2267 }
2268
2269 /* If we're working around r7000 errata, there must be two instructions
2270 between an mfhi or mflo and any instruction that uses the result. */
2271 if (mips_7000_hilo_fix
2272 && MF_HILO_INSN (pinfo1)
2273 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2274 return 2;
2275
2276 /* If working around VR4120 errata, check for combinations that need
2277 a single intervening instruction. */
2278 if (mips_fix_vr4120)
2279 {
2280 unsigned int class1, class2;
2281
2282 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2283 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2284 {
2285 if (insn2 == NULL)
2286 return 1;
2287 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2288 if (vr4120_conflicts[class1] & (1 << class2))
2289 return 1;
2290 }
2291 }
2292
2293 if (!mips_opts.mips16)
2294 {
2295 /* Check for GPR or coprocessor load delays. All such delays
2296 are on the RT register. */
2297 /* Itbl support may require additional care here. */
2298 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2299 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2300 {
2301 know (pinfo1 & INSN_WRITE_GPR_T);
2302 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2303 return 1;
2304 }
2305
2306 /* Check for generic coprocessor hazards.
2307
2308 This case is not handled very well. There is no special
2309 knowledge of CP0 handling, and the coprocessors other than
2310 the floating point unit are not distinguished at all. */
2311 /* Itbl support may require additional care here. FIXME!
2312 Need to modify this to include knowledge about
2313 user specified delays! */
2314 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2315 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2316 {
2317 /* Handle cases where INSN1 writes to a known general coprocessor
2318 register. There must be a one instruction delay before INSN2
2319 if INSN2 reads that register, otherwise no delay is needed. */
2320 if (pinfo1 & INSN_WRITE_FPR_T)
2321 {
2322 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2323 return 1;
2324 }
2325 else if (pinfo1 & INSN_WRITE_FPR_S)
2326 {
2327 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2328 return 1;
2329 }
2330 else
2331 {
2332 /* Read-after-write dependencies on the control registers
2333 require a two-instruction gap. */
2334 if ((pinfo1 & INSN_WRITE_COND_CODE)
2335 && (pinfo2 & INSN_READ_COND_CODE))
2336 return 2;
2337
2338 /* We don't know exactly what INSN1 does. If INSN2 is
2339 also a coprocessor instruction, assume there must be
2340 a one instruction gap. */
2341 if (pinfo2 & INSN_COP)
2342 return 1;
2343 }
2344 }
2345
2346 /* Check for read-after-write dependencies on the coprocessor
2347 control registers in cases where INSN1 does not need a general
2348 coprocessor delay. This means that INSN1 is a floating point
2349 comparison instruction. */
2350 /* Itbl support may require additional care here. */
2351 else if (!cop_interlocks
2352 && (pinfo1 & INSN_WRITE_COND_CODE)
2353 && (pinfo2 & INSN_READ_COND_CODE))
2354 return 1;
2355 }
2356
2357 #undef INSN2_USES_REG
2358
2359 return 0;
2360 }
2361
2362 /* Return the number of nops that would be needed to work around the
2363 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2364 the MAX_VR4130_NOPS instructions described by HISTORY. */
2365
2366 static int
2367 nops_for_vr4130 (const struct mips_cl_insn *history,
2368 const struct mips_cl_insn *insn)
2369 {
2370 int i, j, reg;
2371
2372 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2373 are not affected by the errata. */
2374 if (insn != 0
2375 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2376 || strcmp (insn->insn_mo->name, "mtlo") == 0
2377 || strcmp (insn->insn_mo->name, "mthi") == 0))
2378 return 0;
2379
2380 /* Search for the first MFLO or MFHI. */
2381 for (i = 0; i < MAX_VR4130_NOPS; i++)
2382 if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
2383 {
2384 /* Extract the destination register. */
2385 if (mips_opts.mips16)
2386 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2387 else
2388 reg = EXTRACT_OPERAND (RD, history[i]);
2389
2390 /* No nops are needed if INSN reads that register. */
2391 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2392 return 0;
2393
2394 /* ...or if any of the intervening instructions do. */
2395 for (j = 0; j < i; j++)
2396 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2397 return 0;
2398
2399 return MAX_VR4130_NOPS - i;
2400 }
2401 return 0;
2402 }
2403
2404 /* Return the number of nops that would be needed if instruction INSN
2405 immediately followed the MAX_NOPS instructions given by HISTORY,
2406 where HISTORY[0] is the most recent instruction. If INSN is null,
2407 return the worse-case number of nops for any instruction. */
2408
2409 static int
2410 nops_for_insn (const struct mips_cl_insn *history,
2411 const struct mips_cl_insn *insn)
2412 {
2413 int i, nops, tmp_nops;
2414
2415 nops = 0;
2416 for (i = 0; i < MAX_DELAY_NOPS; i++)
2417 if (!history[i].noreorder_p)
2418 {
2419 tmp_nops = insns_between (history + i, insn) - i;
2420 if (tmp_nops > nops)
2421 nops = tmp_nops;
2422 }
2423
2424 if (mips_fix_vr4130)
2425 {
2426 tmp_nops = nops_for_vr4130 (history, insn);
2427 if (tmp_nops > nops)
2428 nops = tmp_nops;
2429 }
2430
2431 return nops;
2432 }
2433
2434 /* The variable arguments provide NUM_INSNS extra instructions that
2435 might be added to HISTORY. Return the largest number of nops that
2436 would be needed after the extended sequence. */
2437
2438 static int
2439 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2440 {
2441 va_list args;
2442 struct mips_cl_insn buffer[MAX_NOPS];
2443 struct mips_cl_insn *cursor;
2444 int nops;
2445
2446 va_start (args, history);
2447 cursor = buffer + num_insns;
2448 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2449 while (cursor > buffer)
2450 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2451
2452 nops = nops_for_insn (buffer, NULL);
2453 va_end (args);
2454 return nops;
2455 }
2456
2457 /* Like nops_for_insn, but if INSN is a branch, take into account the
2458 worst-case delay for the branch target. */
2459
2460 static int
2461 nops_for_insn_or_target (const struct mips_cl_insn *history,
2462 const struct mips_cl_insn *insn)
2463 {
2464 int nops, tmp_nops;
2465
2466 nops = nops_for_insn (history, insn);
2467 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2468 | INSN_COND_BRANCH_DELAY
2469 | INSN_COND_BRANCH_LIKELY))
2470 {
2471 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2472 if (tmp_nops > nops)
2473 nops = tmp_nops;
2474 }
2475 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2476 {
2477 tmp_nops = nops_for_sequence (1, history, insn);
2478 if (tmp_nops > nops)
2479 nops = tmp_nops;
2480 }
2481 return nops;
2482 }
2483
2484 /* Output an instruction. IP is the instruction information.
2485 ADDRESS_EXPR is an operand of the instruction to be used with
2486 RELOC_TYPE. */
2487
2488 static void
2489 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2490 bfd_reloc_code_real_type *reloc_type)
2491 {
2492 register unsigned long prev_pinfo, pinfo;
2493 relax_stateT prev_insn_frag_type = 0;
2494 bfd_boolean relaxed_branch = FALSE;
2495
2496 /* Mark instruction labels in mips16 mode. */
2497 mips16_mark_labels ();
2498
2499 prev_pinfo = history[0].insn_mo->pinfo;
2500 pinfo = ip->insn_mo->pinfo;
2501
2502 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2503 {
2504 /* There are a lot of optimizations we could do that we don't.
2505 In particular, we do not, in general, reorder instructions.
2506 If you use gcc with optimization, it will reorder
2507 instructions and generally do much more optimization then we
2508 do here; repeating all that work in the assembler would only
2509 benefit hand written assembly code, and does not seem worth
2510 it. */
2511 int nops = (mips_optimize == 0
2512 ? nops_for_insn (history, NULL)
2513 : nops_for_insn_or_target (history, ip));
2514 if (nops > 0)
2515 {
2516 fragS *old_frag;
2517 unsigned long old_frag_offset;
2518 int i;
2519
2520 old_frag = frag_now;
2521 old_frag_offset = frag_now_fix ();
2522
2523 for (i = 0; i < nops; i++)
2524 emit_nop ();
2525
2526 if (listing)
2527 {
2528 listing_prev_line ();
2529 /* We may be at the start of a variant frag. In case we
2530 are, make sure there is enough space for the frag
2531 after the frags created by listing_prev_line. The
2532 argument to frag_grow here must be at least as large
2533 as the argument to all other calls to frag_grow in
2534 this file. We don't have to worry about being in the
2535 middle of a variant frag, because the variants insert
2536 all needed nop instructions themselves. */
2537 frag_grow (40);
2538 }
2539
2540 mips_move_labels ();
2541
2542 #ifndef NO_ECOFF_DEBUGGING
2543 if (ECOFF_DEBUGGING)
2544 ecoff_fix_loc (old_frag, old_frag_offset);
2545 #endif
2546 }
2547 }
2548 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2549 {
2550 /* Work out how many nops in prev_nop_frag are needed by IP. */
2551 int nops = nops_for_insn_or_target (history, ip);
2552 assert (nops <= prev_nop_frag_holds);
2553
2554 /* Enforce NOPS as a minimum. */
2555 if (nops > prev_nop_frag_required)
2556 prev_nop_frag_required = nops;
2557
2558 if (prev_nop_frag_holds == prev_nop_frag_required)
2559 {
2560 /* Settle for the current number of nops. Update the history
2561 accordingly (for the benefit of any future .set reorder code). */
2562 prev_nop_frag = NULL;
2563 insert_into_history (prev_nop_frag_since,
2564 prev_nop_frag_holds, NOP_INSN);
2565 }
2566 else
2567 {
2568 /* Allow this instruction to replace one of the nops that was
2569 tentatively added to prev_nop_frag. */
2570 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2571 prev_nop_frag_holds--;
2572 prev_nop_frag_since++;
2573 }
2574 }
2575
2576 #ifdef OBJ_ELF
2577 /* The value passed to dwarf2_emit_insn is the distance between
2578 the beginning of the current instruction and the address that
2579 should be recorded in the debug tables. For MIPS16 debug info
2580 we want to use ISA-encoded addresses, so we pass -1 for an
2581 address higher by one than the current. */
2582 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2583 #endif
2584
2585 /* Record the frag type before frag_var. */
2586 if (history[0].frag)
2587 prev_insn_frag_type = history[0].frag->fr_type;
2588
2589 if (address_expr
2590 && *reloc_type == BFD_RELOC_16_PCREL_S2
2591 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2592 || pinfo & INSN_COND_BRANCH_LIKELY)
2593 && mips_relax_branch
2594 /* Don't try branch relaxation within .set nomacro, or within
2595 .set noat if we use $at for PIC computations. If it turns
2596 out that the branch was out-of-range, we'll get an error. */
2597 && !mips_opts.warn_about_macros
2598 && !(mips_opts.noat && mips_pic != NO_PIC)
2599 && !mips_opts.mips16)
2600 {
2601 relaxed_branch = TRUE;
2602 add_relaxed_insn (ip, (relaxed_branch_length
2603 (NULL, NULL,
2604 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2605 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2606 : 0)), 4,
2607 RELAX_BRANCH_ENCODE
2608 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2609 pinfo & INSN_COND_BRANCH_LIKELY,
2610 pinfo & INSN_WRITE_GPR_31,
2611 0),
2612 address_expr->X_add_symbol,
2613 address_expr->X_add_number);
2614 *reloc_type = BFD_RELOC_UNUSED;
2615 }
2616 else if (*reloc_type > BFD_RELOC_UNUSED)
2617 {
2618 /* We need to set up a variant frag. */
2619 assert (mips_opts.mips16 && address_expr != NULL);
2620 add_relaxed_insn (ip, 4, 0,
2621 RELAX_MIPS16_ENCODE
2622 (*reloc_type - BFD_RELOC_UNUSED,
2623 mips16_small, mips16_ext,
2624 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2625 history[0].mips16_absolute_jump_p),
2626 make_expr_symbol (address_expr), 0);
2627 }
2628 else if (mips_opts.mips16
2629 && ! ip->use_extend
2630 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2631 {
2632 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2633 /* Make sure there is enough room to swap this instruction with
2634 a following jump instruction. */
2635 frag_grow (6);
2636 add_fixed_insn (ip);
2637 }
2638 else
2639 {
2640 if (mips_opts.mips16
2641 && mips_opts.noreorder
2642 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2643 as_warn (_("extended instruction in delay slot"));
2644
2645 if (mips_relax.sequence)
2646 {
2647 /* If we've reached the end of this frag, turn it into a variant
2648 frag and record the information for the instructions we've
2649 written so far. */
2650 if (frag_room () < 4)
2651 relax_close_frag ();
2652 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2653 }
2654
2655 if (mips_relax.sequence != 2)
2656 mips_macro_warning.sizes[0] += 4;
2657 if (mips_relax.sequence != 1)
2658 mips_macro_warning.sizes[1] += 4;
2659
2660 if (mips_opts.mips16)
2661 {
2662 ip->fixed_p = 1;
2663 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2664 }
2665 add_fixed_insn (ip);
2666 }
2667
2668 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2669 {
2670 if (address_expr->X_op == O_constant)
2671 {
2672 unsigned int tmp;
2673
2674 switch (*reloc_type)
2675 {
2676 case BFD_RELOC_32:
2677 ip->insn_opcode |= address_expr->X_add_number;
2678 break;
2679
2680 case BFD_RELOC_MIPS_HIGHEST:
2681 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2682 ip->insn_opcode |= tmp & 0xffff;
2683 break;
2684
2685 case BFD_RELOC_MIPS_HIGHER:
2686 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2687 ip->insn_opcode |= tmp & 0xffff;
2688 break;
2689
2690 case BFD_RELOC_HI16_S:
2691 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2692 ip->insn_opcode |= tmp & 0xffff;
2693 break;
2694
2695 case BFD_RELOC_HI16:
2696 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2697 break;
2698
2699 case BFD_RELOC_UNUSED:
2700 case BFD_RELOC_LO16:
2701 case BFD_RELOC_MIPS_GOT_DISP:
2702 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2703 break;
2704
2705 case BFD_RELOC_MIPS_JMP:
2706 if ((address_expr->X_add_number & 3) != 0)
2707 as_bad (_("jump to misaligned address (0x%lx)"),
2708 (unsigned long) address_expr->X_add_number);
2709 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2710 break;
2711
2712 case BFD_RELOC_MIPS16_JMP:
2713 if ((address_expr->X_add_number & 3) != 0)
2714 as_bad (_("jump to misaligned address (0x%lx)"),
2715 (unsigned long) address_expr->X_add_number);
2716 ip->insn_opcode |=
2717 (((address_expr->X_add_number & 0x7c0000) << 3)
2718 | ((address_expr->X_add_number & 0xf800000) >> 7)
2719 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2720 break;
2721
2722 case BFD_RELOC_16_PCREL_S2:
2723 if ((address_expr->X_add_number & 3) != 0)
2724 as_bad (_("branch to misaligned address (0x%lx)"),
2725 (unsigned long) address_expr->X_add_number);
2726 if (mips_relax_branch)
2727 goto need_reloc;
2728 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
2729 as_bad (_("branch address range overflow (0x%lx)"),
2730 (unsigned long) address_expr->X_add_number);
2731 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
2732 break;
2733
2734 default:
2735 internalError ();
2736 }
2737 }
2738 else if (*reloc_type < BFD_RELOC_UNUSED)
2739 need_reloc:
2740 {
2741 reloc_howto_type *howto;
2742 int i;
2743
2744 /* In a compound relocation, it is the final (outermost)
2745 operator that determines the relocated field. */
2746 for (i = 1; i < 3; i++)
2747 if (reloc_type[i] == BFD_RELOC_UNUSED)
2748 break;
2749
2750 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2751 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
2752 bfd_get_reloc_size (howto),
2753 address_expr,
2754 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2755 reloc_type[0]);
2756
2757 /* These relocations can have an addend that won't fit in
2758 4 octets for 64bit assembly. */
2759 if (HAVE_64BIT_GPRS
2760 && ! howto->partial_inplace
2761 && (reloc_type[0] == BFD_RELOC_16
2762 || reloc_type[0] == BFD_RELOC_32
2763 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2764 || reloc_type[0] == BFD_RELOC_HI16_S
2765 || reloc_type[0] == BFD_RELOC_LO16
2766 || reloc_type[0] == BFD_RELOC_GPREL16
2767 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2768 || reloc_type[0] == BFD_RELOC_GPREL32
2769 || reloc_type[0] == BFD_RELOC_64
2770 || reloc_type[0] == BFD_RELOC_CTOR
2771 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2772 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2773 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2774 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2775 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2776 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
2777 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
2778 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
2779 || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
2780 ip->fixp[0]->fx_no_overflow = 1;
2781
2782 if (mips_relax.sequence)
2783 {
2784 if (mips_relax.first_fixup == 0)
2785 mips_relax.first_fixup = ip->fixp[0];
2786 }
2787 else if (reloc_needs_lo_p (*reloc_type))
2788 {
2789 struct mips_hi_fixup *hi_fixup;
2790
2791 /* Reuse the last entry if it already has a matching %lo. */
2792 hi_fixup = mips_hi_fixup_list;
2793 if (hi_fixup == 0
2794 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2795 {
2796 hi_fixup = ((struct mips_hi_fixup *)
2797 xmalloc (sizeof (struct mips_hi_fixup)));
2798 hi_fixup->next = mips_hi_fixup_list;
2799 mips_hi_fixup_list = hi_fixup;
2800 }
2801 hi_fixup->fixp = ip->fixp[0];
2802 hi_fixup->seg = now_seg;
2803 }
2804
2805 /* Add fixups for the second and third relocations, if given.
2806 Note that the ABI allows the second relocation to be
2807 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2808 moment we only use RSS_UNDEF, but we could add support
2809 for the others if it ever becomes necessary. */
2810 for (i = 1; i < 3; i++)
2811 if (reloc_type[i] != BFD_RELOC_UNUSED)
2812 {
2813 ip->fixp[i] = fix_new (ip->frag, ip->where,
2814 ip->fixp[0]->fx_size, NULL, 0,
2815 FALSE, reloc_type[i]);
2816
2817 /* Use fx_tcbit to mark compound relocs. */
2818 ip->fixp[0]->fx_tcbit = 1;
2819 ip->fixp[i]->fx_tcbit = 1;
2820 }
2821 }
2822 }
2823 install_insn (ip);
2824
2825 /* Update the register mask information. */
2826 if (! mips_opts.mips16)
2827 {
2828 if (pinfo & INSN_WRITE_GPR_D)
2829 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
2830 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2831 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
2832 if (pinfo & INSN_READ_GPR_S)
2833 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
2834 if (pinfo & INSN_WRITE_GPR_31)
2835 mips_gprmask |= 1 << RA;
2836 if (pinfo & INSN_WRITE_FPR_D)
2837 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
2838 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2839 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
2840 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2841 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
2842 if ((pinfo & INSN_READ_FPR_R) != 0)
2843 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
2844 if (pinfo & INSN_COP)
2845 {
2846 /* We don't keep enough information to sort these cases out.
2847 The itbl support does keep this information however, although
2848 we currently don't support itbl fprmats as part of the cop
2849 instruction. May want to add this support in the future. */
2850 }
2851 /* Never set the bit for $0, which is always zero. */
2852 mips_gprmask &= ~1 << 0;
2853 }
2854 else
2855 {
2856 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2857 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
2858 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2859 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
2860 if (pinfo & MIPS16_INSN_WRITE_Z)
2861 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
2862 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2863 mips_gprmask |= 1 << TREG;
2864 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2865 mips_gprmask |= 1 << SP;
2866 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2867 mips_gprmask |= 1 << RA;
2868 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2869 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2870 if (pinfo & MIPS16_INSN_READ_Z)
2871 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
2872 if (pinfo & MIPS16_INSN_READ_GPR_X)
2873 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2874 }
2875
2876 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2877 {
2878 /* Filling the branch delay slot is more complex. We try to
2879 switch the branch with the previous instruction, which we can
2880 do if the previous instruction does not set up a condition
2881 that the branch tests and if the branch is not itself the
2882 target of any branch. */
2883 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2884 || (pinfo & INSN_COND_BRANCH_DELAY))
2885 {
2886 if (mips_optimize < 2
2887 /* If we have seen .set volatile or .set nomove, don't
2888 optimize. */
2889 || mips_opts.nomove != 0
2890 /* We can't swap if the previous instruction's position
2891 is fixed. */
2892 || history[0].fixed_p
2893 /* If the previous previous insn was in a .set
2894 noreorder, we can't swap. Actually, the MIPS
2895 assembler will swap in this situation. However, gcc
2896 configured -with-gnu-as will generate code like
2897 .set noreorder
2898 lw $4,XXX
2899 .set reorder
2900 INSN
2901 bne $4,$0,foo
2902 in which we can not swap the bne and INSN. If gcc is
2903 not configured -with-gnu-as, it does not output the
2904 .set pseudo-ops. */
2905 || history[1].noreorder_p
2906 /* If the branch is itself the target of a branch, we
2907 can not swap. We cheat on this; all we check for is
2908 whether there is a label on this instruction. If
2909 there are any branches to anything other than a
2910 label, users must use .set noreorder. */
2911 || insn_labels != NULL
2912 /* If the previous instruction is in a variant frag
2913 other than this branch's one, we cannot do the swap.
2914 This does not apply to the mips16, which uses variant
2915 frags for different purposes. */
2916 || (! mips_opts.mips16
2917 && prev_insn_frag_type == rs_machine_dependent)
2918 /* Check for conflicts between the branch and the instructions
2919 before the candidate delay slot. */
2920 || nops_for_insn (history + 1, ip) > 0
2921 /* Check for conflicts between the swapped sequence and the
2922 target of the branch. */
2923 || nops_for_sequence (2, history + 1, ip, history) > 0
2924 /* We do not swap with a trap instruction, since it
2925 complicates trap handlers to have the trap
2926 instruction be in a delay slot. */
2927 || (prev_pinfo & INSN_TRAP)
2928 /* If the branch reads a register that the previous
2929 instruction sets, we can not swap. */
2930 || (! mips_opts.mips16
2931 && (prev_pinfo & INSN_WRITE_GPR_T)
2932 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
2933 MIPS_GR_REG))
2934 || (! mips_opts.mips16
2935 && (prev_pinfo & INSN_WRITE_GPR_D)
2936 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
2937 MIPS_GR_REG))
2938 || (mips_opts.mips16
2939 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2940 && (insn_uses_reg
2941 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
2942 MIPS16_REG)))
2943 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2944 && (insn_uses_reg
2945 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
2946 MIPS16_REG)))
2947 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2948 && (insn_uses_reg
2949 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
2950 MIPS16_REG)))
2951 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2952 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2953 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2954 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2955 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2956 && insn_uses_reg (ip,
2957 MIPS16OP_EXTRACT_REG32R
2958 (history[0].insn_opcode),
2959 MIPS_GR_REG))))
2960 /* If the branch writes a register that the previous
2961 instruction sets, we can not swap (we know that
2962 branches write only to RD or to $31). */
2963 || (! mips_opts.mips16
2964 && (prev_pinfo & INSN_WRITE_GPR_T)
2965 && (((pinfo & INSN_WRITE_GPR_D)
2966 && (EXTRACT_OPERAND (RT, history[0])
2967 == EXTRACT_OPERAND (RD, *ip)))
2968 || ((pinfo & INSN_WRITE_GPR_31)
2969 && EXTRACT_OPERAND (RT, history[0]) == RA)))
2970 || (! mips_opts.mips16
2971 && (prev_pinfo & INSN_WRITE_GPR_D)
2972 && (((pinfo & INSN_WRITE_GPR_D)
2973 && (EXTRACT_OPERAND (RD, history[0])
2974 == EXTRACT_OPERAND (RD, *ip)))
2975 || ((pinfo & INSN_WRITE_GPR_31)
2976 && EXTRACT_OPERAND (RD, history[0]) == RA)))
2977 || (mips_opts.mips16
2978 && (pinfo & MIPS16_INSN_WRITE_31)
2979 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2980 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2981 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
2982 == RA))))
2983 /* If the branch writes a register that the previous
2984 instruction reads, we can not swap (we know that
2985 branches only write to RD or to $31). */
2986 || (! mips_opts.mips16
2987 && (pinfo & INSN_WRITE_GPR_D)
2988 && insn_uses_reg (&history[0],
2989 EXTRACT_OPERAND (RD, *ip),
2990 MIPS_GR_REG))
2991 || (! mips_opts.mips16
2992 && (pinfo & INSN_WRITE_GPR_31)
2993 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
2994 || (mips_opts.mips16
2995 && (pinfo & MIPS16_INSN_WRITE_31)
2996 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
2997 /* If one instruction sets a condition code and the
2998 other one uses a condition code, we can not swap. */
2999 || ((pinfo & INSN_READ_COND_CODE)
3000 && (prev_pinfo & INSN_WRITE_COND_CODE))
3001 || ((pinfo & INSN_WRITE_COND_CODE)
3002 && (prev_pinfo & INSN_READ_COND_CODE))
3003 /* If the previous instruction uses the PC, we can not
3004 swap. */
3005 || (mips_opts.mips16
3006 && (prev_pinfo & MIPS16_INSN_READ_PC))
3007 /* If the previous instruction had a fixup in mips16
3008 mode, we can not swap. This normally means that the
3009 previous instruction was a 4 byte branch anyhow. */
3010 || (mips_opts.mips16 && history[0].fixp[0])
3011 /* If the previous instruction is a sync, sync.l, or
3012 sync.p, we can not swap. */
3013 || (prev_pinfo & INSN_SYNC))
3014 {
3015 if (mips_opts.mips16
3016 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3017 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3018 && (mips_opts.isa == ISA_MIPS32
3019 || mips_opts.isa == ISA_MIPS32R2
3020 || mips_opts.isa == ISA_MIPS64
3021 || mips_opts.isa == ISA_MIPS64R2))
3022 {
3023 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3024 ip->insn_opcode |= 0x0080;
3025 install_insn (ip);
3026 insert_into_history (0, 1, ip);
3027 }
3028 else
3029 {
3030 /* We could do even better for unconditional branches to
3031 portions of this object file; we could pick up the
3032 instruction at the destination, put it in the delay
3033 slot, and bump the destination address. */
3034 insert_into_history (0, 1, ip);
3035 emit_nop ();
3036 }
3037
3038 if (mips_relax.sequence)
3039 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3040 }
3041 else
3042 {
3043 /* It looks like we can actually do the swap. */
3044 struct mips_cl_insn delay = history[0];
3045 if (mips_opts.mips16)
3046 {
3047 know (delay.frag == ip->frag);
3048 move_insn (ip, delay.frag, delay.where);
3049 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3050 }
3051 else if (relaxed_branch)
3052 {
3053 /* Add the delay slot instruction to the end of the
3054 current frag and shrink the fixed part of the
3055 original frag. If the branch occupies the tail of
3056 the latter, move it backwards to cover the gap. */
3057 delay.frag->fr_fix -= 4;
3058 if (delay.frag == ip->frag)
3059 move_insn (ip, ip->frag, ip->where - 4);
3060 add_fixed_insn (&delay);
3061 }
3062 else
3063 {
3064 move_insn (&delay, ip->frag, ip->where);
3065 move_insn (ip, history[0].frag, history[0].where);
3066 }
3067 history[0] = *ip;
3068 delay.fixed_p = 1;
3069 insert_into_history (0, 1, &delay);
3070 }
3071
3072 /* If that was an unconditional branch, forget the previous
3073 insn information. */
3074 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3075 mips_no_prev_insn ();
3076 }
3077 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3078 {
3079 /* We don't yet optimize a branch likely. What we should do
3080 is look at the target, copy the instruction found there
3081 into the delay slot, and increment the branch to jump to
3082 the next instruction. */
3083 insert_into_history (0, 1, ip);
3084 emit_nop ();
3085 }
3086 else
3087 insert_into_history (0, 1, ip);
3088 }
3089 else
3090 insert_into_history (0, 1, ip);
3091
3092 /* We just output an insn, so the next one doesn't have a label. */
3093 mips_clear_insn_labels ();
3094 }
3095
3096 /* Forget that there was any previous instruction or label. */
3097
3098 static void
3099 mips_no_prev_insn (void)
3100 {
3101 prev_nop_frag = NULL;
3102 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3103 mips_clear_insn_labels ();
3104 }
3105
3106 /* This function must be called before we emit something other than
3107 instructions. It is like mips_no_prev_insn except that it inserts
3108 any NOPS that might be needed by previous instructions. */
3109
3110 void
3111 mips_emit_delays (void)
3112 {
3113 if (! mips_opts.noreorder)
3114 {
3115 int nops = nops_for_insn (history, NULL);
3116 if (nops > 0)
3117 {
3118 while (nops-- > 0)
3119 add_fixed_insn (NOP_INSN);
3120 mips_move_labels ();
3121 }
3122 }
3123 mips_no_prev_insn ();
3124 }
3125
3126 /* Start a (possibly nested) noreorder block. */
3127
3128 static void
3129 start_noreorder (void)
3130 {
3131 if (mips_opts.noreorder == 0)
3132 {
3133 unsigned int i;
3134 int nops;
3135
3136 /* None of the instructions before the .set noreorder can be moved. */
3137 for (i = 0; i < ARRAY_SIZE (history); i++)
3138 history[i].fixed_p = 1;
3139
3140 /* Insert any nops that might be needed between the .set noreorder
3141 block and the previous instructions. We will later remove any
3142 nops that turn out not to be needed. */
3143 nops = nops_for_insn (history, NULL);
3144 if (nops > 0)
3145 {
3146 if (mips_optimize != 0)
3147 {
3148 /* Record the frag which holds the nop instructions, so
3149 that we can remove them if we don't need them. */
3150 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3151 prev_nop_frag = frag_now;
3152 prev_nop_frag_holds = nops;
3153 prev_nop_frag_required = 0;
3154 prev_nop_frag_since = 0;
3155 }
3156
3157 for (; nops > 0; --nops)
3158 add_fixed_insn (NOP_INSN);
3159
3160 /* Move on to a new frag, so that it is safe to simply
3161 decrease the size of prev_nop_frag. */
3162 frag_wane (frag_now);
3163 frag_new (0);
3164 mips_move_labels ();
3165 }
3166 mips16_mark_labels ();
3167 mips_clear_insn_labels ();
3168 }
3169 mips_opts.noreorder++;
3170 mips_any_noreorder = 1;
3171 }
3172
3173 /* End a nested noreorder block. */
3174
3175 static void
3176 end_noreorder (void)
3177 {
3178 mips_opts.noreorder--;
3179 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3180 {
3181 /* Commit to inserting prev_nop_frag_required nops and go back to
3182 handling nop insertion the .set reorder way. */
3183 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3184 * (mips_opts.mips16 ? 2 : 4));
3185 insert_into_history (prev_nop_frag_since,
3186 prev_nop_frag_required, NOP_INSN);
3187 prev_nop_frag = NULL;
3188 }
3189 }
3190
3191 /* Set up global variables for the start of a new macro. */
3192
3193 static void
3194 macro_start (void)
3195 {
3196 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3197 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3198 && (history[0].insn_mo->pinfo
3199 & (INSN_UNCOND_BRANCH_DELAY
3200 | INSN_COND_BRANCH_DELAY
3201 | INSN_COND_BRANCH_LIKELY)) != 0);
3202 }
3203
3204 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3205 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3206 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3207
3208 static const char *
3209 macro_warning (relax_substateT subtype)
3210 {
3211 if (subtype & RELAX_DELAY_SLOT)
3212 return _("Macro instruction expanded into multiple instructions"
3213 " in a branch delay slot");
3214 else if (subtype & RELAX_NOMACRO)
3215 return _("Macro instruction expanded into multiple instructions");
3216 else
3217 return 0;
3218 }
3219
3220 /* Finish up a macro. Emit warnings as appropriate. */
3221
3222 static void
3223 macro_end (void)
3224 {
3225 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3226 {
3227 relax_substateT subtype;
3228
3229 /* Set up the relaxation warning flags. */
3230 subtype = 0;
3231 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3232 subtype |= RELAX_SECOND_LONGER;
3233 if (mips_opts.warn_about_macros)
3234 subtype |= RELAX_NOMACRO;
3235 if (mips_macro_warning.delay_slot_p)
3236 subtype |= RELAX_DELAY_SLOT;
3237
3238 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3239 {
3240 /* Either the macro has a single implementation or both
3241 implementations are longer than 4 bytes. Emit the
3242 warning now. */
3243 const char *msg = macro_warning (subtype);
3244 if (msg != 0)
3245 as_warn (msg);
3246 }
3247 else
3248 {
3249 /* One implementation might need a warning but the other
3250 definitely doesn't. */
3251 mips_macro_warning.first_frag->fr_subtype |= subtype;
3252 }
3253 }
3254 }
3255
3256 /* Read a macro's relocation codes from *ARGS and store them in *R.
3257 The first argument in *ARGS will be either the code for a single
3258 relocation or -1 followed by the three codes that make up a
3259 composite relocation. */
3260
3261 static void
3262 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3263 {
3264 int i, next;
3265
3266 next = va_arg (*args, int);
3267 if (next >= 0)
3268 r[0] = (bfd_reloc_code_real_type) next;
3269 else
3270 for (i = 0; i < 3; i++)
3271 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3272 }
3273
3274 /* Build an instruction created by a macro expansion. This is passed
3275 a pointer to the count of instructions created so far, an
3276 expression, the name of the instruction to build, an operand format
3277 string, and corresponding arguments. */
3278
3279 static void
3280 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3281 {
3282 const struct mips_opcode *mo;
3283 struct mips_cl_insn insn;
3284 bfd_reloc_code_real_type r[3];
3285 va_list args;
3286
3287 va_start (args, fmt);
3288
3289 if (mips_opts.mips16)
3290 {
3291 mips16_macro_build (ep, name, fmt, args);
3292 va_end (args);
3293 return;
3294 }
3295
3296 r[0] = BFD_RELOC_UNUSED;
3297 r[1] = BFD_RELOC_UNUSED;
3298 r[2] = BFD_RELOC_UNUSED;
3299 mo = (struct mips_opcode *) hash_find (op_hash, name);
3300 assert (mo);
3301 assert (strcmp (name, mo->name) == 0);
3302
3303 /* Search until we get a match for NAME. It is assumed here that
3304 macros will never generate MDMX or MIPS-3D instructions. */
3305 while (strcmp (fmt, mo->args) != 0
3306 || mo->pinfo == INSN_MACRO
3307 || !OPCODE_IS_MEMBER (mo,
3308 (mips_opts.isa
3309 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
3310 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
3311 mips_opts.arch)
3312 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
3313 {
3314 ++mo;
3315 assert (mo->name);
3316 assert (strcmp (name, mo->name) == 0);
3317 }
3318
3319 create_insn (&insn, mo);
3320 for (;;)
3321 {
3322 switch (*fmt++)
3323 {
3324 case '\0':
3325 break;
3326
3327 case ',':
3328 case '(':
3329 case ')':
3330 continue;
3331
3332 case '+':
3333 switch (*fmt++)
3334 {
3335 case 'A':
3336 case 'E':
3337 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3338 continue;
3339
3340 case 'B':
3341 case 'F':
3342 /* Note that in the macro case, these arguments are already
3343 in MSB form. (When handling the instruction in the
3344 non-macro case, these arguments are sizes from which
3345 MSB values must be calculated.) */
3346 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3347 continue;
3348
3349 case 'C':
3350 case 'G':
3351 case 'H':
3352 /* Note that in the macro case, these arguments are already
3353 in MSBD form. (When handling the instruction in the
3354 non-macro case, these arguments are sizes from which
3355 MSBD values must be calculated.) */
3356 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3357 continue;
3358
3359 default:
3360 internalError ();
3361 }
3362 continue;
3363
3364 case 't':
3365 case 'w':
3366 case 'E':
3367 INSERT_OPERAND (RT, insn, va_arg (args, int));
3368 continue;
3369
3370 case 'c':
3371 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3372 continue;
3373
3374 case 'T':
3375 case 'W':
3376 INSERT_OPERAND (FT, insn, va_arg (args, int));
3377 continue;
3378
3379 case 'd':
3380 case 'G':
3381 case 'K':
3382 INSERT_OPERAND (RD, insn, va_arg (args, int));
3383 continue;
3384
3385 case 'U':
3386 {
3387 int tmp = va_arg (args, int);
3388
3389 INSERT_OPERAND (RT, insn, tmp);
3390 INSERT_OPERAND (RD, insn, tmp);
3391 continue;
3392 }
3393
3394 case 'V':
3395 case 'S':
3396 INSERT_OPERAND (FS, insn, va_arg (args, int));
3397 continue;
3398
3399 case 'z':
3400 continue;
3401
3402 case '<':
3403 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3404 continue;
3405
3406 case 'D':
3407 INSERT_OPERAND (FD, insn, va_arg (args, int));
3408 continue;
3409
3410 case 'B':
3411 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3412 continue;
3413
3414 case 'J':
3415 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3416 continue;
3417
3418 case 'q':
3419 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3420 continue;
3421
3422 case 'b':
3423 case 's':
3424 case 'r':
3425 case 'v':
3426 INSERT_OPERAND (RS, insn, va_arg (args, int));
3427 continue;
3428
3429 case 'i':
3430 case 'j':
3431 case 'o':
3432 macro_read_relocs (&args, r);
3433 assert (*r == BFD_RELOC_GPREL16
3434 || *r == BFD_RELOC_MIPS_LITERAL
3435 || *r == BFD_RELOC_MIPS_HIGHER
3436 || *r == BFD_RELOC_HI16_S
3437 || *r == BFD_RELOC_LO16
3438 || *r == BFD_RELOC_MIPS_GOT16
3439 || *r == BFD_RELOC_MIPS_CALL16
3440 || *r == BFD_RELOC_MIPS_GOT_DISP
3441 || *r == BFD_RELOC_MIPS_GOT_PAGE
3442 || *r == BFD_RELOC_MIPS_GOT_OFST
3443 || *r == BFD_RELOC_MIPS_GOT_LO16
3444 || *r == BFD_RELOC_MIPS_CALL_LO16);
3445 continue;
3446
3447 case 'u':
3448 macro_read_relocs (&args, r);
3449 assert (ep != NULL
3450 && (ep->X_op == O_constant
3451 || (ep->X_op == O_symbol
3452 && (*r == BFD_RELOC_MIPS_HIGHEST
3453 || *r == BFD_RELOC_HI16_S
3454 || *r == BFD_RELOC_HI16
3455 || *r == BFD_RELOC_GPREL16
3456 || *r == BFD_RELOC_MIPS_GOT_HI16
3457 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3458 continue;
3459
3460 case 'p':
3461 assert (ep != NULL);
3462
3463 /*
3464 * This allows macro() to pass an immediate expression for
3465 * creating short branches without creating a symbol.
3466 *
3467 * We don't allow branch relaxation for these branches, as
3468 * they should only appear in ".set nomacro" anyway.
3469 */
3470 if (ep->X_op == O_constant)
3471 {
3472 if ((ep->X_add_number & 3) != 0)
3473 as_bad (_("branch to misaligned address (0x%lx)"),
3474 (unsigned long) ep->X_add_number);
3475 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3476 as_bad (_("branch address range overflow (0x%lx)"),
3477 (unsigned long) ep->X_add_number);
3478 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3479 ep = NULL;
3480 }
3481 else
3482 *r = BFD_RELOC_16_PCREL_S2;
3483 continue;
3484
3485 case 'a':
3486 assert (ep != NULL);
3487 *r = BFD_RELOC_MIPS_JMP;
3488 continue;
3489
3490 case 'C':
3491 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3492 continue;
3493
3494 case 'k':
3495 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3496 continue;
3497
3498 default:
3499 internalError ();
3500 }
3501 break;
3502 }
3503 va_end (args);
3504 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3505
3506 append_insn (&insn, ep, r);
3507 }
3508
3509 static void
3510 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3511 va_list args)
3512 {
3513 struct mips_opcode *mo;
3514 struct mips_cl_insn insn;
3515 bfd_reloc_code_real_type r[3]
3516 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3517
3518 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3519 assert (mo);
3520 assert (strcmp (name, mo->name) == 0);
3521
3522 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3523 {
3524 ++mo;
3525 assert (mo->name);
3526 assert (strcmp (name, mo->name) == 0);
3527 }
3528
3529 create_insn (&insn, mo);
3530 for (;;)
3531 {
3532 int c;
3533
3534 c = *fmt++;
3535 switch (c)
3536 {
3537 case '\0':
3538 break;
3539
3540 case ',':
3541 case '(':
3542 case ')':
3543 continue;
3544
3545 case 'y':
3546 case 'w':
3547 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3548 continue;
3549
3550 case 'x':
3551 case 'v':
3552 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3553 continue;
3554
3555 case 'z':
3556 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3557 continue;
3558
3559 case 'Z':
3560 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3561 continue;
3562
3563 case '0':
3564 case 'S':
3565 case 'P':
3566 case 'R':
3567 continue;
3568
3569 case 'X':
3570 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3571 continue;
3572
3573 case 'Y':
3574 {
3575 int regno;
3576
3577 regno = va_arg (args, int);
3578 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3579 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3580 }
3581 continue;
3582
3583 case '<':
3584 case '>':
3585 case '4':
3586 case '5':
3587 case 'H':
3588 case 'W':
3589 case 'D':
3590 case 'j':
3591 case '8':
3592 case 'V':
3593 case 'C':
3594 case 'U':
3595 case 'k':
3596 case 'K':
3597 case 'p':
3598 case 'q':
3599 {
3600 assert (ep != NULL);
3601
3602 if (ep->X_op != O_constant)
3603 *r = (int) BFD_RELOC_UNUSED + c;
3604 else
3605 {
3606 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3607 FALSE, &insn.insn_opcode, &insn.use_extend,
3608 &insn.extend);
3609 ep = NULL;
3610 *r = BFD_RELOC_UNUSED;
3611 }
3612 }
3613 continue;
3614
3615 case '6':
3616 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3617 continue;
3618 }
3619
3620 break;
3621 }
3622
3623 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3624
3625 append_insn (&insn, ep, r);
3626 }
3627
3628 /*
3629 * Sign-extend 32-bit mode constants that have bit 31 set and all
3630 * higher bits unset.
3631 */
3632 static void
3633 normalize_constant_expr (expressionS *ex)
3634 {
3635 if (ex->X_op == O_constant
3636 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3637 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3638 - 0x80000000);
3639 }
3640
3641 /*
3642 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3643 * all higher bits unset.
3644 */
3645 static void
3646 normalize_address_expr (expressionS *ex)
3647 {
3648 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3649 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3650 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3651 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3652 - 0x80000000);
3653 }
3654
3655 /*
3656 * Generate a "jalr" instruction with a relocation hint to the called
3657 * function. This occurs in NewABI PIC code.
3658 */
3659 static void
3660 macro_build_jalr (expressionS *ep)
3661 {
3662 char *f = NULL;
3663
3664 if (HAVE_NEWABI)
3665 {
3666 frag_grow (8);
3667 f = frag_more (0);
3668 }
3669 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3670 if (HAVE_NEWABI)
3671 fix_new_exp (frag_now, f - frag_now->fr_literal,
3672 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3673 }
3674
3675 /*
3676 * Generate a "lui" instruction.
3677 */
3678 static void
3679 macro_build_lui (expressionS *ep, int regnum)
3680 {
3681 expressionS high_expr;
3682 const struct mips_opcode *mo;
3683 struct mips_cl_insn insn;
3684 bfd_reloc_code_real_type r[3]
3685 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3686 const char *name = "lui";
3687 const char *fmt = "t,u";
3688
3689 assert (! mips_opts.mips16);
3690
3691 high_expr = *ep;
3692
3693 if (high_expr.X_op == O_constant)
3694 {
3695 /* we can compute the instruction now without a relocation entry */
3696 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3697 >> 16) & 0xffff;
3698 *r = BFD_RELOC_UNUSED;
3699 }
3700 else
3701 {
3702 assert (ep->X_op == O_symbol);
3703 /* _gp_disp is a special case, used from s_cpload.
3704 __gnu_local_gp is used if mips_no_shared. */
3705 assert (mips_pic == NO_PIC
3706 || (! HAVE_NEWABI
3707 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
3708 || (! mips_in_shared
3709 && strcmp (S_GET_NAME (ep->X_add_symbol),
3710 "__gnu_local_gp") == 0));
3711 *r = BFD_RELOC_HI16_S;
3712 }
3713
3714 mo = hash_find (op_hash, name);
3715 assert (strcmp (name, mo->name) == 0);
3716 assert (strcmp (fmt, mo->args) == 0);
3717 create_insn (&insn, mo);
3718
3719 insn.insn_opcode = insn.insn_mo->match;
3720 INSERT_OPERAND (RT, insn, regnum);
3721 if (*r == BFD_RELOC_UNUSED)
3722 {
3723 insn.insn_opcode |= high_expr.X_add_number;
3724 append_insn (&insn, NULL, r);
3725 }
3726 else
3727 append_insn (&insn, &high_expr, r);
3728 }
3729
3730 /* Generate a sequence of instructions to do a load or store from a constant
3731 offset off of a base register (breg) into/from a target register (treg),
3732 using AT if necessary. */
3733 static void
3734 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3735 int treg, int breg, int dbl)
3736 {
3737 assert (ep->X_op == O_constant);
3738
3739 /* Sign-extending 32-bit constants makes their handling easier. */
3740 if (!dbl)
3741 normalize_constant_expr (ep);
3742
3743 /* Right now, this routine can only handle signed 32-bit constants. */
3744 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3745 as_warn (_("operand overflow"));
3746
3747 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3748 {
3749 /* Signed 16-bit offset will fit in the op. Easy! */
3750 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3751 }
3752 else
3753 {
3754 /* 32-bit offset, need multiple instructions and AT, like:
3755 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3756 addu $tempreg,$tempreg,$breg
3757 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3758 to handle the complete offset. */
3759 macro_build_lui (ep, AT);
3760 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3761 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3762
3763 if (mips_opts.noat)
3764 as_bad (_("Macro used $at after \".set noat\""));
3765 }
3766 }
3767
3768 /* set_at()
3769 * Generates code to set the $at register to true (one)
3770 * if reg is less than the immediate expression.
3771 */
3772 static void
3773 set_at (int reg, int unsignedp)
3774 {
3775 if (imm_expr.X_op == O_constant
3776 && imm_expr.X_add_number >= -0x8000
3777 && imm_expr.X_add_number < 0x8000)
3778 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3779 AT, reg, BFD_RELOC_LO16);
3780 else
3781 {
3782 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3783 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3784 }
3785 }
3786
3787 /* Warn if an expression is not a constant. */
3788
3789 static void
3790 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3791 {
3792 if (ex->X_op == O_big)
3793 as_bad (_("unsupported large constant"));
3794 else if (ex->X_op != O_constant)
3795 as_bad (_("Instruction %s requires absolute expression"),
3796 ip->insn_mo->name);
3797
3798 if (HAVE_32BIT_GPRS)
3799 normalize_constant_expr (ex);
3800 }
3801
3802 /* Count the leading zeroes by performing a binary chop. This is a
3803 bulky bit of source, but performance is a LOT better for the
3804 majority of values than a simple loop to count the bits:
3805 for (lcnt = 0; (lcnt < 32); lcnt++)
3806 if ((v) & (1 << (31 - lcnt)))
3807 break;
3808 However it is not code size friendly, and the gain will drop a bit
3809 on certain cached systems.
3810 */
3811 #define COUNT_TOP_ZEROES(v) \
3812 (((v) & ~0xffff) == 0 \
3813 ? ((v) & ~0xff) == 0 \
3814 ? ((v) & ~0xf) == 0 \
3815 ? ((v) & ~0x3) == 0 \
3816 ? ((v) & ~0x1) == 0 \
3817 ? !(v) \
3818 ? 32 \
3819 : 31 \
3820 : 30 \
3821 : ((v) & ~0x7) == 0 \
3822 ? 29 \
3823 : 28 \
3824 : ((v) & ~0x3f) == 0 \
3825 ? ((v) & ~0x1f) == 0 \
3826 ? 27 \
3827 : 26 \
3828 : ((v) & ~0x7f) == 0 \
3829 ? 25 \
3830 : 24 \
3831 : ((v) & ~0xfff) == 0 \
3832 ? ((v) & ~0x3ff) == 0 \
3833 ? ((v) & ~0x1ff) == 0 \
3834 ? 23 \
3835 : 22 \
3836 : ((v) & ~0x7ff) == 0 \
3837 ? 21 \
3838 : 20 \
3839 : ((v) & ~0x3fff) == 0 \
3840 ? ((v) & ~0x1fff) == 0 \
3841 ? 19 \
3842 : 18 \
3843 : ((v) & ~0x7fff) == 0 \
3844 ? 17 \
3845 : 16 \
3846 : ((v) & ~0xffffff) == 0 \
3847 ? ((v) & ~0xfffff) == 0 \
3848 ? ((v) & ~0x3ffff) == 0 \
3849 ? ((v) & ~0x1ffff) == 0 \
3850 ? 15 \
3851 : 14 \
3852 : ((v) & ~0x7ffff) == 0 \
3853 ? 13 \
3854 : 12 \
3855 : ((v) & ~0x3fffff) == 0 \
3856 ? ((v) & ~0x1fffff) == 0 \
3857 ? 11 \
3858 : 10 \
3859 : ((v) & ~0x7fffff) == 0 \
3860 ? 9 \
3861 : 8 \
3862 : ((v) & ~0xfffffff) == 0 \
3863 ? ((v) & ~0x3ffffff) == 0 \
3864 ? ((v) & ~0x1ffffff) == 0 \
3865 ? 7 \
3866 : 6 \
3867 : ((v) & ~0x7ffffff) == 0 \
3868 ? 5 \
3869 : 4 \
3870 : ((v) & ~0x3fffffff) == 0 \
3871 ? ((v) & ~0x1fffffff) == 0 \
3872 ? 3 \
3873 : 2 \
3874 : ((v) & ~0x7fffffff) == 0 \
3875 ? 1 \
3876 : 0)
3877
3878 /* load_register()
3879 * This routine generates the least number of instructions necessary to load
3880 * an absolute expression value into a register.
3881 */
3882 static void
3883 load_register (int reg, expressionS *ep, int dbl)
3884 {
3885 int freg;
3886 expressionS hi32, lo32;
3887
3888 if (ep->X_op != O_big)
3889 {
3890 assert (ep->X_op == O_constant);
3891
3892 /* Sign-extending 32-bit constants makes their handling easier. */
3893 if (!dbl)
3894 normalize_constant_expr (ep);
3895
3896 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3897 {
3898 /* We can handle 16 bit signed values with an addiu to
3899 $zero. No need to ever use daddiu here, since $zero and
3900 the result are always correct in 32 bit mode. */
3901 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3902 return;
3903 }
3904 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3905 {
3906 /* We can handle 16 bit unsigned values with an ori to
3907 $zero. */
3908 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3909 return;
3910 }
3911 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3912 {
3913 /* 32 bit values require an lui. */
3914 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3915 if ((ep->X_add_number & 0xffff) != 0)
3916 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3917 return;
3918 }
3919 }
3920
3921 /* The value is larger than 32 bits. */
3922
3923 if (!dbl || HAVE_32BIT_GPRS)
3924 {
3925 char value[32];
3926
3927 sprintf_vma (value, ep->X_add_number);
3928 as_bad (_("Number (0x%s) larger than 32 bits"), value);
3929 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3930 return;
3931 }
3932
3933 if (ep->X_op != O_big)
3934 {
3935 hi32 = *ep;
3936 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3937 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3938 hi32.X_add_number &= 0xffffffff;
3939 lo32 = *ep;
3940 lo32.X_add_number &= 0xffffffff;
3941 }
3942 else
3943 {
3944 assert (ep->X_add_number > 2);
3945 if (ep->X_add_number == 3)
3946 generic_bignum[3] = 0;
3947 else if (ep->X_add_number > 4)
3948 as_bad (_("Number larger than 64 bits"));
3949 lo32.X_op = O_constant;
3950 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3951 hi32.X_op = O_constant;
3952 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3953 }
3954
3955 if (hi32.X_add_number == 0)
3956 freg = 0;
3957 else
3958 {
3959 int shift, bit;
3960 unsigned long hi, lo;
3961
3962 if (hi32.X_add_number == (offsetT) 0xffffffff)
3963 {
3964 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3965 {
3966 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3967 return;
3968 }
3969 if (lo32.X_add_number & 0x80000000)
3970 {
3971 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3972 if (lo32.X_add_number & 0xffff)
3973 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3974 return;
3975 }
3976 }
3977
3978 /* Check for 16bit shifted constant. We know that hi32 is
3979 non-zero, so start the mask on the first bit of the hi32
3980 value. */
3981 shift = 17;
3982 do
3983 {
3984 unsigned long himask, lomask;
3985
3986 if (shift < 32)
3987 {
3988 himask = 0xffff >> (32 - shift);
3989 lomask = (0xffff << shift) & 0xffffffff;
3990 }
3991 else
3992 {
3993 himask = 0xffff << (shift - 32);
3994 lomask = 0;
3995 }
3996 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3997 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3998 {
3999 expressionS tmp;
4000
4001 tmp.X_op = O_constant;
4002 if (shift < 32)
4003 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4004 | (lo32.X_add_number >> shift));
4005 else
4006 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4007 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4008 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4009 reg, reg, (shift >= 32) ? shift - 32 : shift);
4010 return;
4011 }
4012 ++shift;
4013 }
4014 while (shift <= (64 - 16));
4015
4016 /* Find the bit number of the lowest one bit, and store the
4017 shifted value in hi/lo. */
4018 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4019 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4020 if (lo != 0)
4021 {
4022 bit = 0;
4023 while ((lo & 1) == 0)
4024 {
4025 lo >>= 1;
4026 ++bit;
4027 }
4028 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4029 hi >>= bit;
4030 }
4031 else
4032 {
4033 bit = 32;
4034 while ((hi & 1) == 0)
4035 {
4036 hi >>= 1;
4037 ++bit;
4038 }
4039 lo = hi;
4040 hi = 0;
4041 }
4042
4043 /* Optimize if the shifted value is a (power of 2) - 1. */
4044 if ((hi == 0 && ((lo + 1) & lo) == 0)
4045 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4046 {
4047 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4048 if (shift != 0)
4049 {
4050 expressionS tmp;
4051
4052 /* This instruction will set the register to be all
4053 ones. */
4054 tmp.X_op = O_constant;
4055 tmp.X_add_number = (offsetT) -1;
4056 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4057 if (bit != 0)
4058 {
4059 bit += shift;
4060 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4061 reg, reg, (bit >= 32) ? bit - 32 : bit);
4062 }
4063 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4064 reg, reg, (shift >= 32) ? shift - 32 : shift);
4065 return;
4066 }
4067 }
4068
4069 /* Sign extend hi32 before calling load_register, because we can
4070 generally get better code when we load a sign extended value. */
4071 if ((hi32.X_add_number & 0x80000000) != 0)
4072 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4073 load_register (reg, &hi32, 0);
4074 freg = reg;
4075 }
4076 if ((lo32.X_add_number & 0xffff0000) == 0)
4077 {
4078 if (freg != 0)
4079 {
4080 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4081 freg = reg;
4082 }
4083 }
4084 else
4085 {
4086 expressionS mid16;
4087
4088 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4089 {
4090 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4091 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4092 return;
4093 }
4094
4095 if (freg != 0)
4096 {
4097 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4098 freg = reg;
4099 }
4100 mid16 = lo32;
4101 mid16.X_add_number >>= 16;
4102 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4103 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4104 freg = reg;
4105 }
4106 if ((lo32.X_add_number & 0xffff) != 0)
4107 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4108 }
4109
4110 static inline void
4111 load_delay_nop (void)
4112 {
4113 if (!gpr_interlocks)
4114 macro_build (NULL, "nop", "");
4115 }
4116
4117 /* Load an address into a register. */
4118
4119 static void
4120 load_address (int reg, expressionS *ep, int *used_at)
4121 {
4122 if (ep->X_op != O_constant
4123 && ep->X_op != O_symbol)
4124 {
4125 as_bad (_("expression too complex"));
4126 ep->X_op = O_constant;
4127 }
4128
4129 if (ep->X_op == O_constant)
4130 {
4131 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4132 return;
4133 }
4134
4135 if (mips_pic == NO_PIC)
4136 {
4137 /* If this is a reference to a GP relative symbol, we want
4138 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4139 Otherwise we want
4140 lui $reg,<sym> (BFD_RELOC_HI16_S)
4141 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4142 If we have an addend, we always use the latter form.
4143
4144 With 64bit address space and a usable $at we want
4145 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4146 lui $at,<sym> (BFD_RELOC_HI16_S)
4147 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4148 daddiu $at,<sym> (BFD_RELOC_LO16)
4149 dsll32 $reg,0
4150 daddu $reg,$reg,$at
4151
4152 If $at is already in use, we use a path which is suboptimal
4153 on superscalar processors.
4154 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4155 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4156 dsll $reg,16
4157 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4158 dsll $reg,16
4159 daddiu $reg,<sym> (BFD_RELOC_LO16)
4160
4161 For GP relative symbols in 64bit address space we can use
4162 the same sequence as in 32bit address space. */
4163 if (HAVE_64BIT_SYMBOLS)
4164 {
4165 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4166 && !nopic_need_relax (ep->X_add_symbol, 1))
4167 {
4168 relax_start (ep->X_add_symbol);
4169 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4170 mips_gp_register, BFD_RELOC_GPREL16);
4171 relax_switch ();
4172 }
4173
4174 if (*used_at == 0 && !mips_opts.noat)
4175 {
4176 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4177 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4178 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4179 BFD_RELOC_MIPS_HIGHER);
4180 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4181 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4182 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4183 *used_at = 1;
4184 }
4185 else
4186 {
4187 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4188 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4189 BFD_RELOC_MIPS_HIGHER);
4190 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4191 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4192 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4193 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4194 }
4195
4196 if (mips_relax.sequence)
4197 relax_end ();
4198 }
4199 else
4200 {
4201 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4202 && !nopic_need_relax (ep->X_add_symbol, 1))
4203 {
4204 relax_start (ep->X_add_symbol);
4205 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4206 mips_gp_register, BFD_RELOC_GPREL16);
4207 relax_switch ();
4208 }
4209 macro_build_lui (ep, reg);
4210 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4211 reg, reg, BFD_RELOC_LO16);
4212 if (mips_relax.sequence)
4213 relax_end ();
4214 }
4215 }
4216 else if (!mips_big_got)
4217 {
4218 expressionS ex;
4219
4220 /* If this is a reference to an external symbol, we want
4221 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4222 Otherwise we want
4223 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4224 nop
4225 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4226 If there is a constant, it must be added in after.
4227
4228 If we have NewABI, we want
4229 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4230 unless we're referencing a global symbol with a non-zero
4231 offset, in which case cst must be added separately. */
4232 if (HAVE_NEWABI)
4233 {
4234 if (ep->X_add_number)
4235 {
4236 ex.X_add_number = ep->X_add_number;
4237 ep->X_add_number = 0;
4238 relax_start (ep->X_add_symbol);
4239 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4240 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4241 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4242 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4243 ex.X_op = O_constant;
4244 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4245 reg, reg, BFD_RELOC_LO16);
4246 ep->X_add_number = ex.X_add_number;
4247 relax_switch ();
4248 }
4249 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4250 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4251 if (mips_relax.sequence)
4252 relax_end ();
4253 }
4254 else
4255 {
4256 ex.X_add_number = ep->X_add_number;
4257 ep->X_add_number = 0;
4258 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4259 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4260 load_delay_nop ();
4261 relax_start (ep->X_add_symbol);
4262 relax_switch ();
4263 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4264 BFD_RELOC_LO16);
4265 relax_end ();
4266
4267 if (ex.X_add_number != 0)
4268 {
4269 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4270 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4271 ex.X_op = O_constant;
4272 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4273 reg, reg, BFD_RELOC_LO16);
4274 }
4275 }
4276 }
4277 else if (mips_big_got)
4278 {
4279 expressionS ex;
4280
4281 /* This is the large GOT case. If this is a reference to an
4282 external symbol, we want
4283 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4284 addu $reg,$reg,$gp
4285 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4286
4287 Otherwise, for a reference to a local symbol in old ABI, we want
4288 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4289 nop
4290 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4291 If there is a constant, it must be added in after.
4292
4293 In the NewABI, for local symbols, with or without offsets, we want:
4294 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4295 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4296 */
4297 if (HAVE_NEWABI)
4298 {
4299 ex.X_add_number = ep->X_add_number;
4300 ep->X_add_number = 0;
4301 relax_start (ep->X_add_symbol);
4302 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4303 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4304 reg, reg, mips_gp_register);
4305 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4306 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4307 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4308 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4309 else if (ex.X_add_number)
4310 {
4311 ex.X_op = O_constant;
4312 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4313 BFD_RELOC_LO16);
4314 }
4315
4316 ep->X_add_number = ex.X_add_number;
4317 relax_switch ();
4318 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4319 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4320 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4321 BFD_RELOC_MIPS_GOT_OFST);
4322 relax_end ();
4323 }
4324 else
4325 {
4326 ex.X_add_number = ep->X_add_number;
4327 ep->X_add_number = 0;
4328 relax_start (ep->X_add_symbol);
4329 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4331 reg, reg, mips_gp_register);
4332 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4333 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4334 relax_switch ();
4335 if (reg_needs_delay (mips_gp_register))
4336 {
4337 /* We need a nop before loading from $gp. This special
4338 check is required because the lui which starts the main
4339 instruction stream does not refer to $gp, and so will not
4340 insert the nop which may be required. */
4341 macro_build (NULL, "nop", "");
4342 }
4343 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4344 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4345 load_delay_nop ();
4346 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4347 BFD_RELOC_LO16);
4348 relax_end ();
4349
4350 if (ex.X_add_number != 0)
4351 {
4352 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4353 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4354 ex.X_op = O_constant;
4355 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4356 BFD_RELOC_LO16);
4357 }
4358 }
4359 }
4360 else
4361 abort ();
4362
4363 if (mips_opts.noat && *used_at == 1)
4364 as_bad (_("Macro used $at after \".set noat\""));
4365 }
4366
4367 /* Move the contents of register SOURCE into register DEST. */
4368
4369 static void
4370 move_register (int dest, int source)
4371 {
4372 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4373 dest, source, 0);
4374 }
4375
4376 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4377 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4378 The two alternatives are:
4379
4380 Global symbol Local sybmol
4381 ------------- ------------
4382 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4383 ... ...
4384 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4385
4386 load_got_offset emits the first instruction and add_got_offset
4387 emits the second for a 16-bit offset or add_got_offset_hilo emits
4388 a sequence to add a 32-bit offset using a scratch register. */
4389
4390 static void
4391 load_got_offset (int dest, expressionS *local)
4392 {
4393 expressionS global;
4394
4395 global = *local;
4396 global.X_add_number = 0;
4397
4398 relax_start (local->X_add_symbol);
4399 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4400 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4401 relax_switch ();
4402 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4403 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4404 relax_end ();
4405 }
4406
4407 static void
4408 add_got_offset (int dest, expressionS *local)
4409 {
4410 expressionS global;
4411
4412 global.X_op = O_constant;
4413 global.X_op_symbol = NULL;
4414 global.X_add_symbol = NULL;
4415 global.X_add_number = local->X_add_number;
4416
4417 relax_start (local->X_add_symbol);
4418 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4419 dest, dest, BFD_RELOC_LO16);
4420 relax_switch ();
4421 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4422 relax_end ();
4423 }
4424
4425 static void
4426 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4427 {
4428 expressionS global;
4429 int hold_mips_optimize;
4430
4431 global.X_op = O_constant;
4432 global.X_op_symbol = NULL;
4433 global.X_add_symbol = NULL;
4434 global.X_add_number = local->X_add_number;
4435
4436 relax_start (local->X_add_symbol);
4437 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4438 relax_switch ();
4439 /* Set mips_optimize around the lui instruction to avoid
4440 inserting an unnecessary nop after the lw. */
4441 hold_mips_optimize = mips_optimize;
4442 mips_optimize = 2;
4443 macro_build_lui (&global, tmp);
4444 mips_optimize = hold_mips_optimize;
4445 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4446 relax_end ();
4447
4448 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4449 }
4450
4451 /*
4452 * Build macros
4453 * This routine implements the seemingly endless macro or synthesized
4454 * instructions and addressing modes in the mips assembly language. Many
4455 * of these macros are simple and are similar to each other. These could
4456 * probably be handled by some kind of table or grammar approach instead of
4457 * this verbose method. Others are not simple macros but are more like
4458 * optimizing code generation.
4459 * One interesting optimization is when several store macros appear
4460 * consecutively that would load AT with the upper half of the same address.
4461 * The ensuing load upper instructions are ommited. This implies some kind
4462 * of global optimization. We currently only optimize within a single macro.
4463 * For many of the load and store macros if the address is specified as a
4464 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4465 * first load register 'at' with zero and use it as the base register. The
4466 * mips assembler simply uses register $zero. Just one tiny optimization
4467 * we're missing.
4468 */
4469 static void
4470 macro (struct mips_cl_insn *ip)
4471 {
4472 register int treg, sreg, dreg, breg;
4473 int tempreg;
4474 int mask;
4475 int used_at = 0;
4476 expressionS expr1;
4477 const char *s;
4478 const char *s2;
4479 const char *fmt;
4480 int likely = 0;
4481 int dbl = 0;
4482 int coproc = 0;
4483 int lr = 0;
4484 int imm = 0;
4485 int call = 0;
4486 int off;
4487 offsetT maxnum;
4488 bfd_reloc_code_real_type r;
4489 int hold_mips_optimize;
4490
4491 assert (! mips_opts.mips16);
4492
4493 treg = (ip->insn_opcode >> 16) & 0x1f;
4494 dreg = (ip->insn_opcode >> 11) & 0x1f;
4495 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4496 mask = ip->insn_mo->mask;
4497
4498 expr1.X_op = O_constant;
4499 expr1.X_op_symbol = NULL;
4500 expr1.X_add_symbol = NULL;
4501 expr1.X_add_number = 1;
4502
4503 switch (mask)
4504 {
4505 case M_DABS:
4506 dbl = 1;
4507 case M_ABS:
4508 /* bgez $a0,.+12
4509 move v0,$a0
4510 sub v0,$zero,$a0
4511 */
4512
4513 start_noreorder ();
4514
4515 expr1.X_add_number = 8;
4516 macro_build (&expr1, "bgez", "s,p", sreg);
4517 if (dreg == sreg)
4518 macro_build (NULL, "nop", "", 0);
4519 else
4520 move_register (dreg, sreg);
4521 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4522
4523 end_noreorder ();
4524 break;
4525
4526 case M_ADD_I:
4527 s = "addi";
4528 s2 = "add";
4529 goto do_addi;
4530 case M_ADDU_I:
4531 s = "addiu";
4532 s2 = "addu";
4533 goto do_addi;
4534 case M_DADD_I:
4535 dbl = 1;
4536 s = "daddi";
4537 s2 = "dadd";
4538 goto do_addi;
4539 case M_DADDU_I:
4540 dbl = 1;
4541 s = "daddiu";
4542 s2 = "daddu";
4543 do_addi:
4544 if (imm_expr.X_op == O_constant
4545 && imm_expr.X_add_number >= -0x8000
4546 && imm_expr.X_add_number < 0x8000)
4547 {
4548 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4549 break;
4550 }
4551 used_at = 1;
4552 load_register (AT, &imm_expr, dbl);
4553 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4554 break;
4555
4556 case M_AND_I:
4557 s = "andi";
4558 s2 = "and";
4559 goto do_bit;
4560 case M_OR_I:
4561 s = "ori";
4562 s2 = "or";
4563 goto do_bit;
4564 case M_NOR_I:
4565 s = "";
4566 s2 = "nor";
4567 goto do_bit;
4568 case M_XOR_I:
4569 s = "xori";
4570 s2 = "xor";
4571 do_bit:
4572 if (imm_expr.X_op == O_constant
4573 && imm_expr.X_add_number >= 0
4574 && imm_expr.X_add_number < 0x10000)
4575 {
4576 if (mask != M_NOR_I)
4577 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4578 else
4579 {
4580 macro_build (&imm_expr, "ori", "t,r,i",
4581 treg, sreg, BFD_RELOC_LO16);
4582 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4583 }
4584 break;
4585 }
4586
4587 used_at = 1;
4588 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4589 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4590 break;
4591
4592 case M_BEQ_I:
4593 s = "beq";
4594 goto beq_i;
4595 case M_BEQL_I:
4596 s = "beql";
4597 likely = 1;
4598 goto beq_i;
4599 case M_BNE_I:
4600 s = "bne";
4601 goto beq_i;
4602 case M_BNEL_I:
4603 s = "bnel";
4604 likely = 1;
4605 beq_i:
4606 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4607 {
4608 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4609 break;
4610 }
4611 used_at = 1;
4612 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4613 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4614 break;
4615
4616 case M_BGEL:
4617 likely = 1;
4618 case M_BGE:
4619 if (treg == 0)
4620 {
4621 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4622 break;
4623 }
4624 if (sreg == 0)
4625 {
4626 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4627 break;
4628 }
4629 used_at = 1;
4630 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4631 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4632 break;
4633
4634 case M_BGTL_I:
4635 likely = 1;
4636 case M_BGT_I:
4637 /* check for > max integer */
4638 maxnum = 0x7fffffff;
4639 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4640 {
4641 maxnum <<= 16;
4642 maxnum |= 0xffff;
4643 maxnum <<= 16;
4644 maxnum |= 0xffff;
4645 }
4646 if (imm_expr.X_op == O_constant
4647 && imm_expr.X_add_number >= maxnum
4648 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4649 {
4650 do_false:
4651 /* result is always false */
4652 if (! likely)
4653 macro_build (NULL, "nop", "", 0);
4654 else
4655 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4656 break;
4657 }
4658 if (imm_expr.X_op != O_constant)
4659 as_bad (_("Unsupported large constant"));
4660 ++imm_expr.X_add_number;
4661 /* FALLTHROUGH */
4662 case M_BGE_I:
4663 case M_BGEL_I:
4664 if (mask == M_BGEL_I)
4665 likely = 1;
4666 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4667 {
4668 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4669 break;
4670 }
4671 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4672 {
4673 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4674 break;
4675 }
4676 maxnum = 0x7fffffff;
4677 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4678 {
4679 maxnum <<= 16;
4680 maxnum |= 0xffff;
4681 maxnum <<= 16;
4682 maxnum |= 0xffff;
4683 }
4684 maxnum = - maxnum - 1;
4685 if (imm_expr.X_op == O_constant
4686 && imm_expr.X_add_number <= maxnum
4687 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4688 {
4689 do_true:
4690 /* result is always true */
4691 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4692 macro_build (&offset_expr, "b", "p");
4693 break;
4694 }
4695 used_at = 1;
4696 set_at (sreg, 0);
4697 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4698 break;
4699
4700 case M_BGEUL:
4701 likely = 1;
4702 case M_BGEU:
4703 if (treg == 0)
4704 goto do_true;
4705 if (sreg == 0)
4706 {
4707 macro_build (&offset_expr, likely ? "beql" : "beq",
4708 "s,t,p", 0, treg);
4709 break;
4710 }
4711 used_at = 1;
4712 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4713 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4714 break;
4715
4716 case M_BGTUL_I:
4717 likely = 1;
4718 case M_BGTU_I:
4719 if (sreg == 0
4720 || (HAVE_32BIT_GPRS
4721 && imm_expr.X_op == O_constant
4722 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4723 goto do_false;
4724 if (imm_expr.X_op != O_constant)
4725 as_bad (_("Unsupported large constant"));
4726 ++imm_expr.X_add_number;
4727 /* FALLTHROUGH */
4728 case M_BGEU_I:
4729 case M_BGEUL_I:
4730 if (mask == M_BGEUL_I)
4731 likely = 1;
4732 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4733 goto do_true;
4734 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4735 {
4736 macro_build (&offset_expr, likely ? "bnel" : "bne",
4737 "s,t,p", sreg, 0);
4738 break;
4739 }
4740 used_at = 1;
4741 set_at (sreg, 1);
4742 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4743 break;
4744
4745 case M_BGTL:
4746 likely = 1;
4747 case M_BGT:
4748 if (treg == 0)
4749 {
4750 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4751 break;
4752 }
4753 if (sreg == 0)
4754 {
4755 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4756 break;
4757 }
4758 used_at = 1;
4759 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4760 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4761 break;
4762
4763 case M_BGTUL:
4764 likely = 1;
4765 case M_BGTU:
4766 if (treg == 0)
4767 {
4768 macro_build (&offset_expr, likely ? "bnel" : "bne",
4769 "s,t,p", sreg, 0);
4770 break;
4771 }
4772 if (sreg == 0)
4773 goto do_false;
4774 used_at = 1;
4775 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4776 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4777 break;
4778
4779 case M_BLEL:
4780 likely = 1;
4781 case M_BLE:
4782 if (treg == 0)
4783 {
4784 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4785 break;
4786 }
4787 if (sreg == 0)
4788 {
4789 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4790 break;
4791 }
4792 used_at = 1;
4793 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4794 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4795 break;
4796
4797 case M_BLEL_I:
4798 likely = 1;
4799 case M_BLE_I:
4800 maxnum = 0x7fffffff;
4801 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4802 {
4803 maxnum <<= 16;
4804 maxnum |= 0xffff;
4805 maxnum <<= 16;
4806 maxnum |= 0xffff;
4807 }
4808 if (imm_expr.X_op == O_constant
4809 && imm_expr.X_add_number >= maxnum
4810 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4811 goto do_true;
4812 if (imm_expr.X_op != O_constant)
4813 as_bad (_("Unsupported large constant"));
4814 ++imm_expr.X_add_number;
4815 /* FALLTHROUGH */
4816 case M_BLT_I:
4817 case M_BLTL_I:
4818 if (mask == M_BLTL_I)
4819 likely = 1;
4820 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4821 {
4822 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4823 break;
4824 }
4825 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4826 {
4827 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4828 break;
4829 }
4830 used_at = 1;
4831 set_at (sreg, 0);
4832 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4833 break;
4834
4835 case M_BLEUL:
4836 likely = 1;
4837 case M_BLEU:
4838 if (treg == 0)
4839 {
4840 macro_build (&offset_expr, likely ? "beql" : "beq",
4841 "s,t,p", sreg, 0);
4842 break;
4843 }
4844 if (sreg == 0)
4845 goto do_true;
4846 used_at = 1;
4847 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4848 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4849 break;
4850
4851 case M_BLEUL_I:
4852 likely = 1;
4853 case M_BLEU_I:
4854 if (sreg == 0
4855 || (HAVE_32BIT_GPRS
4856 && imm_expr.X_op == O_constant
4857 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4858 goto do_true;
4859 if (imm_expr.X_op != O_constant)
4860 as_bad (_("Unsupported large constant"));
4861 ++imm_expr.X_add_number;
4862 /* FALLTHROUGH */
4863 case M_BLTU_I:
4864 case M_BLTUL_I:
4865 if (mask == M_BLTUL_I)
4866 likely = 1;
4867 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4868 goto do_false;
4869 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4870 {
4871 macro_build (&offset_expr, likely ? "beql" : "beq",
4872 "s,t,p", sreg, 0);
4873 break;
4874 }
4875 used_at = 1;
4876 set_at (sreg, 1);
4877 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4878 break;
4879
4880 case M_BLTL:
4881 likely = 1;
4882 case M_BLT:
4883 if (treg == 0)
4884 {
4885 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4886 break;
4887 }
4888 if (sreg == 0)
4889 {
4890 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4891 break;
4892 }
4893 used_at = 1;
4894 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4895 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4896 break;
4897
4898 case M_BLTUL:
4899 likely = 1;
4900 case M_BLTU:
4901 if (treg == 0)
4902 goto do_false;
4903 if (sreg == 0)
4904 {
4905 macro_build (&offset_expr, likely ? "bnel" : "bne",
4906 "s,t,p", 0, treg);
4907 break;
4908 }
4909 used_at = 1;
4910 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4911 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4912 break;
4913
4914 case M_DEXT:
4915 {
4916 unsigned long pos;
4917 unsigned long size;
4918
4919 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4920 {
4921 as_bad (_("Unsupported large constant"));
4922 pos = size = 1;
4923 }
4924 else
4925 {
4926 pos = (unsigned long) imm_expr.X_add_number;
4927 size = (unsigned long) imm2_expr.X_add_number;
4928 }
4929
4930 if (pos > 63)
4931 {
4932 as_bad (_("Improper position (%lu)"), pos);
4933 pos = 1;
4934 }
4935 if (size == 0 || size > 64
4936 || (pos + size - 1) > 63)
4937 {
4938 as_bad (_("Improper extract size (%lu, position %lu)"),
4939 size, pos);
4940 size = 1;
4941 }
4942
4943 if (size <= 32 && pos < 32)
4944 {
4945 s = "dext";
4946 fmt = "t,r,+A,+C";
4947 }
4948 else if (size <= 32)
4949 {
4950 s = "dextu";
4951 fmt = "t,r,+E,+H";
4952 }
4953 else
4954 {
4955 s = "dextm";
4956 fmt = "t,r,+A,+G";
4957 }
4958 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4959 }
4960 break;
4961
4962 case M_DINS:
4963 {
4964 unsigned long pos;
4965 unsigned long size;
4966
4967 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4968 {
4969 as_bad (_("Unsupported large constant"));
4970 pos = size = 1;
4971 }
4972 else
4973 {
4974 pos = (unsigned long) imm_expr.X_add_number;
4975 size = (unsigned long) imm2_expr.X_add_number;
4976 }
4977
4978 if (pos > 63)
4979 {
4980 as_bad (_("Improper position (%lu)"), pos);
4981 pos = 1;
4982 }
4983 if (size == 0 || size > 64
4984 || (pos + size - 1) > 63)
4985 {
4986 as_bad (_("Improper insert size (%lu, position %lu)"),
4987 size, pos);
4988 size = 1;
4989 }
4990
4991 if (pos < 32 && (pos + size - 1) < 32)
4992 {
4993 s = "dins";
4994 fmt = "t,r,+A,+B";
4995 }
4996 else if (pos >= 32)
4997 {
4998 s = "dinsu";
4999 fmt = "t,r,+E,+F";
5000 }
5001 else
5002 {
5003 s = "dinsm";
5004 fmt = "t,r,+A,+F";
5005 }
5006 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
5007 pos + size - 1);
5008 }
5009 break;
5010
5011 case M_DDIV_3:
5012 dbl = 1;
5013 case M_DIV_3:
5014 s = "mflo";
5015 goto do_div3;
5016 case M_DREM_3:
5017 dbl = 1;
5018 case M_REM_3:
5019 s = "mfhi";
5020 do_div3:
5021 if (treg == 0)
5022 {
5023 as_warn (_("Divide by zero."));
5024 if (mips_trap)
5025 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5026 else
5027 macro_build (NULL, "break", "c", 7);
5028 break;
5029 }
5030
5031 start_noreorder ();
5032 if (mips_trap)
5033 {
5034 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5035 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5036 }
5037 else
5038 {
5039 expr1.X_add_number = 8;
5040 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5041 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5042 macro_build (NULL, "break", "c", 7);
5043 }
5044 expr1.X_add_number = -1;
5045 used_at = 1;
5046 load_register (AT, &expr1, dbl);
5047 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5048 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5049 if (dbl)
5050 {
5051 expr1.X_add_number = 1;
5052 load_register (AT, &expr1, dbl);
5053 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5054 }
5055 else
5056 {
5057 expr1.X_add_number = 0x80000000;
5058 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5059 }
5060 if (mips_trap)
5061 {
5062 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5063 /* We want to close the noreorder block as soon as possible, so
5064 that later insns are available for delay slot filling. */
5065 end_noreorder ();
5066 }
5067 else
5068 {
5069 expr1.X_add_number = 8;
5070 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5071 macro_build (NULL, "nop", "", 0);
5072
5073 /* We want to close the noreorder block as soon as possible, so
5074 that later insns are available for delay slot filling. */
5075 end_noreorder ();
5076
5077 macro_build (NULL, "break", "c", 6);
5078 }
5079 macro_build (NULL, s, "d", dreg);
5080 break;
5081
5082 case M_DIV_3I:
5083 s = "div";
5084 s2 = "mflo";
5085 goto do_divi;
5086 case M_DIVU_3I:
5087 s = "divu";
5088 s2 = "mflo";
5089 goto do_divi;
5090 case M_REM_3I:
5091 s = "div";
5092 s2 = "mfhi";
5093 goto do_divi;
5094 case M_REMU_3I:
5095 s = "divu";
5096 s2 = "mfhi";
5097 goto do_divi;
5098 case M_DDIV_3I:
5099 dbl = 1;
5100 s = "ddiv";
5101 s2 = "mflo";
5102 goto do_divi;
5103 case M_DDIVU_3I:
5104 dbl = 1;
5105 s = "ddivu";
5106 s2 = "mflo";
5107 goto do_divi;
5108 case M_DREM_3I:
5109 dbl = 1;
5110 s = "ddiv";
5111 s2 = "mfhi";
5112 goto do_divi;
5113 case M_DREMU_3I:
5114 dbl = 1;
5115 s = "ddivu";
5116 s2 = "mfhi";
5117 do_divi:
5118 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5119 {
5120 as_warn (_("Divide by zero."));
5121 if (mips_trap)
5122 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5123 else
5124 macro_build (NULL, "break", "c", 7);
5125 break;
5126 }
5127 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5128 {
5129 if (strcmp (s2, "mflo") == 0)
5130 move_register (dreg, sreg);
5131 else
5132 move_register (dreg, 0);
5133 break;
5134 }
5135 if (imm_expr.X_op == O_constant
5136 && imm_expr.X_add_number == -1
5137 && s[strlen (s) - 1] != 'u')
5138 {
5139 if (strcmp (s2, "mflo") == 0)
5140 {
5141 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5142 }
5143 else
5144 move_register (dreg, 0);
5145 break;
5146 }
5147
5148 used_at = 1;
5149 load_register (AT, &imm_expr, dbl);
5150 macro_build (NULL, s, "z,s,t", sreg, AT);
5151 macro_build (NULL, s2, "d", dreg);
5152 break;
5153
5154 case M_DIVU_3:
5155 s = "divu";
5156 s2 = "mflo";
5157 goto do_divu3;
5158 case M_REMU_3:
5159 s = "divu";
5160 s2 = "mfhi";
5161 goto do_divu3;
5162 case M_DDIVU_3:
5163 s = "ddivu";
5164 s2 = "mflo";
5165 goto do_divu3;
5166 case M_DREMU_3:
5167 s = "ddivu";
5168 s2 = "mfhi";
5169 do_divu3:
5170 start_noreorder ();
5171 if (mips_trap)
5172 {
5173 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5174 macro_build (NULL, s, "z,s,t", sreg, treg);
5175 /* We want to close the noreorder block as soon as possible, so
5176 that later insns are available for delay slot filling. */
5177 end_noreorder ();
5178 }
5179 else
5180 {
5181 expr1.X_add_number = 8;
5182 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5183 macro_build (NULL, s, "z,s,t", sreg, treg);
5184
5185 /* We want to close the noreorder block as soon as possible, so
5186 that later insns are available for delay slot filling. */
5187 end_noreorder ();
5188 macro_build (NULL, "break", "c", 7);
5189 }
5190 macro_build (NULL, s2, "d", dreg);
5191 break;
5192
5193 case M_DLCA_AB:
5194 dbl = 1;
5195 case M_LCA_AB:
5196 call = 1;
5197 goto do_la;
5198 case M_DLA_AB:
5199 dbl = 1;
5200 case M_LA_AB:
5201 do_la:
5202 /* Load the address of a symbol into a register. If breg is not
5203 zero, we then add a base register to it. */
5204
5205 if (dbl && HAVE_32BIT_GPRS)
5206 as_warn (_("dla used to load 32-bit register"));
5207
5208 if (! dbl && HAVE_64BIT_OBJECTS)
5209 as_warn (_("la used to load 64-bit address"));
5210
5211 if (offset_expr.X_op == O_constant
5212 && offset_expr.X_add_number >= -0x8000
5213 && offset_expr.X_add_number < 0x8000)
5214 {
5215 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5216 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5217 break;
5218 }
5219
5220 if (!mips_opts.noat && (treg == breg))
5221 {
5222 tempreg = AT;
5223 used_at = 1;
5224 }
5225 else
5226 {
5227 tempreg = treg;
5228 }
5229
5230 if (offset_expr.X_op != O_symbol
5231 && offset_expr.X_op != O_constant)
5232 {
5233 as_bad (_("expression too complex"));
5234 offset_expr.X_op = O_constant;
5235 }
5236
5237 if (offset_expr.X_op == O_constant)
5238 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5239 else if (mips_pic == NO_PIC)
5240 {
5241 /* If this is a reference to a GP relative symbol, we want
5242 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5243 Otherwise we want
5244 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5245 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5246 If we have a constant, we need two instructions anyhow,
5247 so we may as well always use the latter form.
5248
5249 With 64bit address space and a usable $at we want
5250 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5251 lui $at,<sym> (BFD_RELOC_HI16_S)
5252 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5253 daddiu $at,<sym> (BFD_RELOC_LO16)
5254 dsll32 $tempreg,0
5255 daddu $tempreg,$tempreg,$at
5256
5257 If $at is already in use, we use a path which is suboptimal
5258 on superscalar processors.
5259 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5260 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5261 dsll $tempreg,16
5262 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5263 dsll $tempreg,16
5264 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5265
5266 For GP relative symbols in 64bit address space we can use
5267 the same sequence as in 32bit address space. */
5268 if (HAVE_64BIT_SYMBOLS)
5269 {
5270 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5271 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5272 {
5273 relax_start (offset_expr.X_add_symbol);
5274 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5275 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5276 relax_switch ();
5277 }
5278
5279 if (used_at == 0 && !mips_opts.noat)
5280 {
5281 macro_build (&offset_expr, "lui", "t,u",
5282 tempreg, BFD_RELOC_MIPS_HIGHEST);
5283 macro_build (&offset_expr, "lui", "t,u",
5284 AT, BFD_RELOC_HI16_S);
5285 macro_build (&offset_expr, "daddiu", "t,r,j",
5286 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5287 macro_build (&offset_expr, "daddiu", "t,r,j",
5288 AT, AT, BFD_RELOC_LO16);
5289 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5290 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5291 used_at = 1;
5292 }
5293 else
5294 {
5295 macro_build (&offset_expr, "lui", "t,u",
5296 tempreg, BFD_RELOC_MIPS_HIGHEST);
5297 macro_build (&offset_expr, "daddiu", "t,r,j",
5298 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5299 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5300 macro_build (&offset_expr, "daddiu", "t,r,j",
5301 tempreg, tempreg, BFD_RELOC_HI16_S);
5302 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5303 macro_build (&offset_expr, "daddiu", "t,r,j",
5304 tempreg, tempreg, BFD_RELOC_LO16);
5305 }
5306
5307 if (mips_relax.sequence)
5308 relax_end ();
5309 }
5310 else
5311 {
5312 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5313 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5314 {
5315 relax_start (offset_expr.X_add_symbol);
5316 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5317 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5318 relax_switch ();
5319 }
5320 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5321 as_bad (_("offset too large"));
5322 macro_build_lui (&offset_expr, tempreg);
5323 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5324 tempreg, tempreg, BFD_RELOC_LO16);
5325 if (mips_relax.sequence)
5326 relax_end ();
5327 }
5328 }
5329 else if (!mips_big_got && !HAVE_NEWABI)
5330 {
5331 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5332
5333 /* If this is a reference to an external symbol, and there
5334 is no constant, we want
5335 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5336 or for lca or if tempreg is PIC_CALL_REG
5337 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5338 For a local symbol, we want
5339 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5340 nop
5341 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5342
5343 If we have a small constant, and this is a reference to
5344 an external symbol, we want
5345 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5346 nop
5347 addiu $tempreg,$tempreg,<constant>
5348 For a local symbol, we want the same instruction
5349 sequence, but we output a BFD_RELOC_LO16 reloc on the
5350 addiu instruction.
5351
5352 If we have a large constant, and this is a reference to
5353 an external symbol, we want
5354 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5355 lui $at,<hiconstant>
5356 addiu $at,$at,<loconstant>
5357 addu $tempreg,$tempreg,$at
5358 For a local symbol, we want the same instruction
5359 sequence, but we output a BFD_RELOC_LO16 reloc on the
5360 addiu instruction.
5361 */
5362
5363 if (offset_expr.X_add_number == 0)
5364 {
5365 if (mips_pic == SVR4_PIC
5366 && breg == 0
5367 && (call || tempreg == PIC_CALL_REG))
5368 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5369
5370 relax_start (offset_expr.X_add_symbol);
5371 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5372 lw_reloc_type, mips_gp_register);
5373 if (breg != 0)
5374 {
5375 /* We're going to put in an addu instruction using
5376 tempreg, so we may as well insert the nop right
5377 now. */
5378 load_delay_nop ();
5379 }
5380 relax_switch ();
5381 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5382 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5383 load_delay_nop ();
5384 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5385 tempreg, tempreg, BFD_RELOC_LO16);
5386 relax_end ();
5387 /* FIXME: If breg == 0, and the next instruction uses
5388 $tempreg, then if this variant case is used an extra
5389 nop will be generated. */
5390 }
5391 else if (offset_expr.X_add_number >= -0x8000
5392 && offset_expr.X_add_number < 0x8000)
5393 {
5394 load_got_offset (tempreg, &offset_expr);
5395 load_delay_nop ();
5396 add_got_offset (tempreg, &offset_expr);
5397 }
5398 else
5399 {
5400 expr1.X_add_number = offset_expr.X_add_number;
5401 offset_expr.X_add_number =
5402 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5403 load_got_offset (tempreg, &offset_expr);
5404 offset_expr.X_add_number = expr1.X_add_number;
5405 /* If we are going to add in a base register, and the
5406 target register and the base register are the same,
5407 then we are using AT as a temporary register. Since
5408 we want to load the constant into AT, we add our
5409 current AT (from the global offset table) and the
5410 register into the register now, and pretend we were
5411 not using a base register. */
5412 if (breg == treg)
5413 {
5414 load_delay_nop ();
5415 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5416 treg, AT, breg);
5417 breg = 0;
5418 tempreg = treg;
5419 }
5420 add_got_offset_hilo (tempreg, &offset_expr, AT);
5421 used_at = 1;
5422 }
5423 }
5424 else if (!mips_big_got && HAVE_NEWABI)
5425 {
5426 int add_breg_early = 0;
5427
5428 /* If this is a reference to an external, and there is no
5429 constant, or local symbol (*), with or without a
5430 constant, we want
5431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5432 or for lca or if tempreg is PIC_CALL_REG
5433 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5434
5435 If we have a small constant, and this is a reference to
5436 an external symbol, we want
5437 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5438 addiu $tempreg,$tempreg,<constant>
5439
5440 If we have a large constant, and this is a reference to
5441 an external symbol, we want
5442 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5443 lui $at,<hiconstant>
5444 addiu $at,$at,<loconstant>
5445 addu $tempreg,$tempreg,$at
5446
5447 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5448 local symbols, even though it introduces an additional
5449 instruction. */
5450
5451 if (offset_expr.X_add_number)
5452 {
5453 expr1.X_add_number = offset_expr.X_add_number;
5454 offset_expr.X_add_number = 0;
5455
5456 relax_start (offset_expr.X_add_symbol);
5457 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5458 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5459
5460 if (expr1.X_add_number >= -0x8000
5461 && expr1.X_add_number < 0x8000)
5462 {
5463 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5464 tempreg, tempreg, BFD_RELOC_LO16);
5465 }
5466 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5467 {
5468 int dreg;
5469
5470 /* If we are going to add in a base register, and the
5471 target register and the base register are the same,
5472 then we are using AT as a temporary register. Since
5473 we want to load the constant into AT, we add our
5474 current AT (from the global offset table) and the
5475 register into the register now, and pretend we were
5476 not using a base register. */
5477 if (breg != treg)
5478 dreg = tempreg;
5479 else
5480 {
5481 assert (tempreg == AT);
5482 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5483 treg, AT, breg);
5484 dreg = treg;
5485 add_breg_early = 1;
5486 }
5487
5488 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5489 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5490 dreg, dreg, AT);
5491
5492 used_at = 1;
5493 }
5494 else
5495 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5496
5497 relax_switch ();
5498 offset_expr.X_add_number = expr1.X_add_number;
5499
5500 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5501 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5502 if (add_breg_early)
5503 {
5504 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5505 treg, tempreg, breg);
5506 breg = 0;
5507 tempreg = treg;
5508 }
5509 relax_end ();
5510 }
5511 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5512 {
5513 relax_start (offset_expr.X_add_symbol);
5514 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5515 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5516 relax_switch ();
5517 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5518 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5519 relax_end ();
5520 }
5521 else
5522 {
5523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5524 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5525 }
5526 }
5527 else if (mips_big_got && !HAVE_NEWABI)
5528 {
5529 int gpdelay;
5530 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5531 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5532 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5533
5534 /* This is the large GOT case. If this is a reference to an
5535 external symbol, and there is no constant, we want
5536 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5537 addu $tempreg,$tempreg,$gp
5538 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5539 or for lca or if tempreg is PIC_CALL_REG
5540 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5541 addu $tempreg,$tempreg,$gp
5542 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5543 For a local symbol, we want
5544 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5545 nop
5546 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5547
5548 If we have a small constant, and this is a reference to
5549 an external symbol, we want
5550 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5551 addu $tempreg,$tempreg,$gp
5552 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5553 nop
5554 addiu $tempreg,$tempreg,<constant>
5555 For a local symbol, we want
5556 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5557 nop
5558 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5559
5560 If we have a large constant, and this is a reference to
5561 an external symbol, we want
5562 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5563 addu $tempreg,$tempreg,$gp
5564 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5565 lui $at,<hiconstant>
5566 addiu $at,$at,<loconstant>
5567 addu $tempreg,$tempreg,$at
5568 For a local symbol, we want
5569 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5570 lui $at,<hiconstant>
5571 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5572 addu $tempreg,$tempreg,$at
5573 */
5574
5575 expr1.X_add_number = offset_expr.X_add_number;
5576 offset_expr.X_add_number = 0;
5577 relax_start (offset_expr.X_add_symbol);
5578 gpdelay = reg_needs_delay (mips_gp_register);
5579 if (expr1.X_add_number == 0 && breg == 0
5580 && (call || tempreg == PIC_CALL_REG))
5581 {
5582 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5583 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5584 }
5585 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5586 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5587 tempreg, tempreg, mips_gp_register);
5588 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5589 tempreg, lw_reloc_type, tempreg);
5590 if (expr1.X_add_number == 0)
5591 {
5592 if (breg != 0)
5593 {
5594 /* We're going to put in an addu instruction using
5595 tempreg, so we may as well insert the nop right
5596 now. */
5597 load_delay_nop ();
5598 }
5599 }
5600 else if (expr1.X_add_number >= -0x8000
5601 && expr1.X_add_number < 0x8000)
5602 {
5603 load_delay_nop ();
5604 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5605 tempreg, tempreg, BFD_RELOC_LO16);
5606 }
5607 else
5608 {
5609 int dreg;
5610
5611 /* If we are going to add in a base register, and the
5612 target register and the base register are the same,
5613 then we are using AT as a temporary register. Since
5614 we want to load the constant into AT, we add our
5615 current AT (from the global offset table) and the
5616 register into the register now, and pretend we were
5617 not using a base register. */
5618 if (breg != treg)
5619 dreg = tempreg;
5620 else
5621 {
5622 assert (tempreg == AT);
5623 load_delay_nop ();
5624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5625 treg, AT, breg);
5626 dreg = treg;
5627 }
5628
5629 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5630 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5631
5632 used_at = 1;
5633 }
5634 offset_expr.X_add_number =
5635 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5636 relax_switch ();
5637
5638 if (gpdelay)
5639 {
5640 /* This is needed because this instruction uses $gp, but
5641 the first instruction on the main stream does not. */
5642 macro_build (NULL, "nop", "");
5643 }
5644
5645 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5646 local_reloc_type, mips_gp_register);
5647 if (expr1.X_add_number >= -0x8000
5648 && expr1.X_add_number < 0x8000)
5649 {
5650 load_delay_nop ();
5651 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5652 tempreg, tempreg, BFD_RELOC_LO16);
5653 /* FIXME: If add_number is 0, and there was no base
5654 register, the external symbol case ended with a load,
5655 so if the symbol turns out to not be external, and
5656 the next instruction uses tempreg, an unnecessary nop
5657 will be inserted. */
5658 }
5659 else
5660 {
5661 if (breg == treg)
5662 {
5663 /* We must add in the base register now, as in the
5664 external symbol case. */
5665 assert (tempreg == AT);
5666 load_delay_nop ();
5667 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5668 treg, AT, breg);
5669 tempreg = treg;
5670 /* We set breg to 0 because we have arranged to add
5671 it in in both cases. */
5672 breg = 0;
5673 }
5674
5675 macro_build_lui (&expr1, AT);
5676 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5677 AT, AT, BFD_RELOC_LO16);
5678 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5679 tempreg, tempreg, AT);
5680 used_at = 1;
5681 }
5682 relax_end ();
5683 }
5684 else if (mips_big_got && HAVE_NEWABI)
5685 {
5686 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5687 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5688 int add_breg_early = 0;
5689
5690 /* This is the large GOT case. If this is a reference to an
5691 external symbol, and there is no constant, we want
5692 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5693 add $tempreg,$tempreg,$gp
5694 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5695 or for lca or if tempreg is PIC_CALL_REG
5696 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5697 add $tempreg,$tempreg,$gp
5698 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5699
5700 If we have a small constant, and this is a reference to
5701 an external symbol, we want
5702 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5703 add $tempreg,$tempreg,$gp
5704 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5705 addi $tempreg,$tempreg,<constant>
5706
5707 If we have a large constant, and this is a reference to
5708 an external symbol, we want
5709 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5710 addu $tempreg,$tempreg,$gp
5711 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5712 lui $at,<hiconstant>
5713 addi $at,$at,<loconstant>
5714 add $tempreg,$tempreg,$at
5715
5716 If we have NewABI, and we know it's a local symbol, we want
5717 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5718 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5719 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5720
5721 relax_start (offset_expr.X_add_symbol);
5722
5723 expr1.X_add_number = offset_expr.X_add_number;
5724 offset_expr.X_add_number = 0;
5725
5726 if (expr1.X_add_number == 0 && breg == 0
5727 && (call || tempreg == PIC_CALL_REG))
5728 {
5729 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5730 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5731 }
5732 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5733 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5734 tempreg, tempreg, mips_gp_register);
5735 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5736 tempreg, lw_reloc_type, tempreg);
5737
5738 if (expr1.X_add_number == 0)
5739 ;
5740 else if (expr1.X_add_number >= -0x8000
5741 && expr1.X_add_number < 0x8000)
5742 {
5743 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5744 tempreg, tempreg, BFD_RELOC_LO16);
5745 }
5746 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5747 {
5748 int dreg;
5749
5750 /* If we are going to add in a base register, and the
5751 target register and the base register are the same,
5752 then we are using AT as a temporary register. Since
5753 we want to load the constant into AT, we add our
5754 current AT (from the global offset table) and the
5755 register into the register now, and pretend we were
5756 not using a base register. */
5757 if (breg != treg)
5758 dreg = tempreg;
5759 else
5760 {
5761 assert (tempreg == AT);
5762 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5763 treg, AT, breg);
5764 dreg = treg;
5765 add_breg_early = 1;
5766 }
5767
5768 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5769 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5770
5771 used_at = 1;
5772 }
5773 else
5774 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5775
5776 relax_switch ();
5777 offset_expr.X_add_number = expr1.X_add_number;
5778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5779 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5780 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5781 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5782 if (add_breg_early)
5783 {
5784 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5785 treg, tempreg, breg);
5786 breg = 0;
5787 tempreg = treg;
5788 }
5789 relax_end ();
5790 }
5791 else
5792 abort ();
5793
5794 if (breg != 0)
5795 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
5796 break;
5797
5798 case M_J_A:
5799 /* The j instruction may not be used in PIC code, since it
5800 requires an absolute address. We convert it to a b
5801 instruction. */
5802 if (mips_pic == NO_PIC)
5803 macro_build (&offset_expr, "j", "a");
5804 else
5805 macro_build (&offset_expr, "b", "p");
5806 break;
5807
5808 /* The jal instructions must be handled as macros because when
5809 generating PIC code they expand to multi-instruction
5810 sequences. Normally they are simple instructions. */
5811 case M_JAL_1:
5812 dreg = RA;
5813 /* Fall through. */
5814 case M_JAL_2:
5815 if (mips_pic == NO_PIC)
5816 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5817 else
5818 {
5819 if (sreg != PIC_CALL_REG)
5820 as_warn (_("MIPS PIC call to register other than $25"));
5821
5822 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5823 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
5824 {
5825 if (mips_cprestore_offset < 0)
5826 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5827 else
5828 {
5829 if (! mips_frame_reg_valid)
5830 {
5831 as_warn (_("No .frame pseudo-op used in PIC code"));
5832 /* Quiet this warning. */
5833 mips_frame_reg_valid = 1;
5834 }
5835 if (! mips_cprestore_valid)
5836 {
5837 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5838 /* Quiet this warning. */
5839 mips_cprestore_valid = 1;
5840 }
5841 expr1.X_add_number = mips_cprestore_offset;
5842 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5843 mips_gp_register,
5844 mips_frame_reg,
5845 HAVE_64BIT_ADDRESSES);
5846 }
5847 }
5848 }
5849
5850 break;
5851
5852 case M_JAL_A:
5853 if (mips_pic == NO_PIC)
5854 macro_build (&offset_expr, "jal", "a");
5855 else if (mips_pic == SVR4_PIC)
5856 {
5857 /* If this is a reference to an external symbol, and we are
5858 using a small GOT, we want
5859 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5860 nop
5861 jalr $ra,$25
5862 nop
5863 lw $gp,cprestore($sp)
5864 The cprestore value is set using the .cprestore
5865 pseudo-op. If we are using a big GOT, we want
5866 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5867 addu $25,$25,$gp
5868 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5869 nop
5870 jalr $ra,$25
5871 nop
5872 lw $gp,cprestore($sp)
5873 If the symbol is not external, we want
5874 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5875 nop
5876 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5877 jalr $ra,$25
5878 nop
5879 lw $gp,cprestore($sp)
5880
5881 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5882 sequences above, minus nops, unless the symbol is local,
5883 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5884 GOT_DISP. */
5885 if (HAVE_NEWABI)
5886 {
5887 if (! mips_big_got)
5888 {
5889 relax_start (offset_expr.X_add_symbol);
5890 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5891 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5892 mips_gp_register);
5893 relax_switch ();
5894 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5895 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5896 mips_gp_register);
5897 relax_end ();
5898 }
5899 else
5900 {
5901 relax_start (offset_expr.X_add_symbol);
5902 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5903 BFD_RELOC_MIPS_CALL_HI16);
5904 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5905 PIC_CALL_REG, mips_gp_register);
5906 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5907 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5908 PIC_CALL_REG);
5909 relax_switch ();
5910 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5911 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5912 mips_gp_register);
5913 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5914 PIC_CALL_REG, PIC_CALL_REG,
5915 BFD_RELOC_MIPS_GOT_OFST);
5916 relax_end ();
5917 }
5918
5919 macro_build_jalr (&offset_expr);
5920 }
5921 else
5922 {
5923 relax_start (offset_expr.X_add_symbol);
5924 if (! mips_big_got)
5925 {
5926 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5927 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5928 mips_gp_register);
5929 load_delay_nop ();
5930 relax_switch ();
5931 }
5932 else
5933 {
5934 int gpdelay;
5935
5936 gpdelay = reg_needs_delay (mips_gp_register);
5937 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5938 BFD_RELOC_MIPS_CALL_HI16);
5939 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5940 PIC_CALL_REG, mips_gp_register);
5941 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5942 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5943 PIC_CALL_REG);
5944 load_delay_nop ();
5945 relax_switch ();
5946 if (gpdelay)
5947 macro_build (NULL, "nop", "");
5948 }
5949 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5950 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5951 mips_gp_register);
5952 load_delay_nop ();
5953 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5954 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5955 relax_end ();
5956 macro_build_jalr (&offset_expr);
5957
5958 if (mips_cprestore_offset < 0)
5959 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5960 else
5961 {
5962 if (! mips_frame_reg_valid)
5963 {
5964 as_warn (_("No .frame pseudo-op used in PIC code"));
5965 /* Quiet this warning. */
5966 mips_frame_reg_valid = 1;
5967 }
5968 if (! mips_cprestore_valid)
5969 {
5970 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5971 /* Quiet this warning. */
5972 mips_cprestore_valid = 1;
5973 }
5974 if (mips_opts.noreorder)
5975 macro_build (NULL, "nop", "");
5976 expr1.X_add_number = mips_cprestore_offset;
5977 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5978 mips_gp_register,
5979 mips_frame_reg,
5980 HAVE_64BIT_ADDRESSES);
5981 }
5982 }
5983 }
5984 else if (mips_pic == VXWORKS_PIC)
5985 as_bad (_("Non-PIC jump used in PIC library"));
5986 else
5987 abort ();
5988
5989 break;
5990
5991 case M_LB_AB:
5992 s = "lb";
5993 goto ld;
5994 case M_LBU_AB:
5995 s = "lbu";
5996 goto ld;
5997 case M_LH_AB:
5998 s = "lh";
5999 goto ld;
6000 case M_LHU_AB:
6001 s = "lhu";
6002 goto ld;
6003 case M_LW_AB:
6004 s = "lw";
6005 goto ld;
6006 case M_LWC0_AB:
6007 s = "lwc0";
6008 /* Itbl support may require additional care here. */
6009 coproc = 1;
6010 goto ld;
6011 case M_LWC1_AB:
6012 s = "lwc1";
6013 /* Itbl support may require additional care here. */
6014 coproc = 1;
6015 goto ld;
6016 case M_LWC2_AB:
6017 s = "lwc2";
6018 /* Itbl support may require additional care here. */
6019 coproc = 1;
6020 goto ld;
6021 case M_LWC3_AB:
6022 s = "lwc3";
6023 /* Itbl support may require additional care here. */
6024 coproc = 1;
6025 goto ld;
6026 case M_LWL_AB:
6027 s = "lwl";
6028 lr = 1;
6029 goto ld;
6030 case M_LWR_AB:
6031 s = "lwr";
6032 lr = 1;
6033 goto ld;
6034 case M_LDC1_AB:
6035 if (mips_opts.arch == CPU_R4650)
6036 {
6037 as_bad (_("opcode not supported on this processor"));
6038 break;
6039 }
6040 s = "ldc1";
6041 /* Itbl support may require additional care here. */
6042 coproc = 1;
6043 goto ld;
6044 case M_LDC2_AB:
6045 s = "ldc2";
6046 /* Itbl support may require additional care here. */
6047 coproc = 1;
6048 goto ld;
6049 case M_LDC3_AB:
6050 s = "ldc3";
6051 /* Itbl support may require additional care here. */
6052 coproc = 1;
6053 goto ld;
6054 case M_LDL_AB:
6055 s = "ldl";
6056 lr = 1;
6057 goto ld;
6058 case M_LDR_AB:
6059 s = "ldr";
6060 lr = 1;
6061 goto ld;
6062 case M_LL_AB:
6063 s = "ll";
6064 goto ld;
6065 case M_LLD_AB:
6066 s = "lld";
6067 goto ld;
6068 case M_LWU_AB:
6069 s = "lwu";
6070 ld:
6071 if (breg == treg || coproc || lr)
6072 {
6073 tempreg = AT;
6074 used_at = 1;
6075 }
6076 else
6077 {
6078 tempreg = treg;
6079 }
6080 goto ld_st;
6081 case M_SB_AB:
6082 s = "sb";
6083 goto st;
6084 case M_SH_AB:
6085 s = "sh";
6086 goto st;
6087 case M_SW_AB:
6088 s = "sw";
6089 goto st;
6090 case M_SWC0_AB:
6091 s = "swc0";
6092 /* Itbl support may require additional care here. */
6093 coproc = 1;
6094 goto st;
6095 case M_SWC1_AB:
6096 s = "swc1";
6097 /* Itbl support may require additional care here. */
6098 coproc = 1;
6099 goto st;
6100 case M_SWC2_AB:
6101 s = "swc2";
6102 /* Itbl support may require additional care here. */
6103 coproc = 1;
6104 goto st;
6105 case M_SWC3_AB:
6106 s = "swc3";
6107 /* Itbl support may require additional care here. */
6108 coproc = 1;
6109 goto st;
6110 case M_SWL_AB:
6111 s = "swl";
6112 goto st;
6113 case M_SWR_AB:
6114 s = "swr";
6115 goto st;
6116 case M_SC_AB:
6117 s = "sc";
6118 goto st;
6119 case M_SCD_AB:
6120 s = "scd";
6121 goto st;
6122 case M_CACHE_AB:
6123 s = "cache";
6124 goto st;
6125 case M_SDC1_AB:
6126 if (mips_opts.arch == CPU_R4650)
6127 {
6128 as_bad (_("opcode not supported on this processor"));
6129 break;
6130 }
6131 s = "sdc1";
6132 coproc = 1;
6133 /* Itbl support may require additional care here. */
6134 goto st;
6135 case M_SDC2_AB:
6136 s = "sdc2";
6137 /* Itbl support may require additional care here. */
6138 coproc = 1;
6139 goto st;
6140 case M_SDC3_AB:
6141 s = "sdc3";
6142 /* Itbl support may require additional care here. */
6143 coproc = 1;
6144 goto st;
6145 case M_SDL_AB:
6146 s = "sdl";
6147 goto st;
6148 case M_SDR_AB:
6149 s = "sdr";
6150 st:
6151 tempreg = AT;
6152 used_at = 1;
6153 ld_st:
6154 /* Itbl support may require additional care here. */
6155 if (mask == M_LWC1_AB
6156 || mask == M_SWC1_AB
6157 || mask == M_LDC1_AB
6158 || mask == M_SDC1_AB
6159 || mask == M_L_DAB
6160 || mask == M_S_DAB)
6161 fmt = "T,o(b)";
6162 else if (mask == M_CACHE_AB)
6163 fmt = "k,o(b)";
6164 else if (coproc)
6165 fmt = "E,o(b)";
6166 else
6167 fmt = "t,o(b)";
6168
6169 if (offset_expr.X_op != O_constant
6170 && offset_expr.X_op != O_symbol)
6171 {
6172 as_bad (_("expression too complex"));
6173 offset_expr.X_op = O_constant;
6174 }
6175
6176 if (HAVE_32BIT_ADDRESSES
6177 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6178 {
6179 char value [32];
6180
6181 sprintf_vma (value, offset_expr.X_add_number);
6182 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6183 }
6184
6185 /* A constant expression in PIC code can be handled just as it
6186 is in non PIC code. */
6187 if (offset_expr.X_op == O_constant)
6188 {
6189 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6190 & ~(bfd_vma) 0xffff);
6191 normalize_address_expr (&expr1);
6192 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6193 if (breg != 0)
6194 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6195 tempreg, tempreg, breg);
6196 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6197 }
6198 else if (mips_pic == NO_PIC)
6199 {
6200 /* If this is a reference to a GP relative symbol, and there
6201 is no base register, we want
6202 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6203 Otherwise, if there is no base register, we want
6204 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6205 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6206 If we have a constant, we need two instructions anyhow,
6207 so we always use the latter form.
6208
6209 If we have a base register, and this is a reference to a
6210 GP relative symbol, we want
6211 addu $tempreg,$breg,$gp
6212 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6213 Otherwise we want
6214 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6215 addu $tempreg,$tempreg,$breg
6216 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6217 With a constant we always use the latter case.
6218
6219 With 64bit address space and no base register and $at usable,
6220 we want
6221 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6222 lui $at,<sym> (BFD_RELOC_HI16_S)
6223 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6224 dsll32 $tempreg,0
6225 daddu $tempreg,$at
6226 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6227 If we have a base register, we want
6228 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6229 lui $at,<sym> (BFD_RELOC_HI16_S)
6230 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6231 daddu $at,$breg
6232 dsll32 $tempreg,0
6233 daddu $tempreg,$at
6234 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6235
6236 Without $at we can't generate the optimal path for superscalar
6237 processors here since this would require two temporary registers.
6238 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6239 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6240 dsll $tempreg,16
6241 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6242 dsll $tempreg,16
6243 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6244 If we have a base register, we want
6245 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6246 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6247 dsll $tempreg,16
6248 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6249 dsll $tempreg,16
6250 daddu $tempreg,$tempreg,$breg
6251 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6252
6253 For GP relative symbols in 64bit address space we can use
6254 the same sequence as in 32bit address space. */
6255 if (HAVE_64BIT_SYMBOLS)
6256 {
6257 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6258 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6259 {
6260 relax_start (offset_expr.X_add_symbol);
6261 if (breg == 0)
6262 {
6263 macro_build (&offset_expr, s, fmt, treg,
6264 BFD_RELOC_GPREL16, mips_gp_register);
6265 }
6266 else
6267 {
6268 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6269 tempreg, breg, mips_gp_register);
6270 macro_build (&offset_expr, s, fmt, treg,
6271 BFD_RELOC_GPREL16, tempreg);
6272 }
6273 relax_switch ();
6274 }
6275
6276 if (used_at == 0 && !mips_opts.noat)
6277 {
6278 macro_build (&offset_expr, "lui", "t,u", tempreg,
6279 BFD_RELOC_MIPS_HIGHEST);
6280 macro_build (&offset_expr, "lui", "t,u", AT,
6281 BFD_RELOC_HI16_S);
6282 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6283 tempreg, BFD_RELOC_MIPS_HIGHER);
6284 if (breg != 0)
6285 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6286 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6287 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6288 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6289 tempreg);
6290 used_at = 1;
6291 }
6292 else
6293 {
6294 macro_build (&offset_expr, "lui", "t,u", tempreg,
6295 BFD_RELOC_MIPS_HIGHEST);
6296 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6297 tempreg, BFD_RELOC_MIPS_HIGHER);
6298 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6299 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6300 tempreg, BFD_RELOC_HI16_S);
6301 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6302 if (breg != 0)
6303 macro_build (NULL, "daddu", "d,v,t",
6304 tempreg, tempreg, breg);
6305 macro_build (&offset_expr, s, fmt, treg,
6306 BFD_RELOC_LO16, tempreg);
6307 }
6308
6309 if (mips_relax.sequence)
6310 relax_end ();
6311 break;
6312 }
6313
6314 if (breg == 0)
6315 {
6316 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6317 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6318 {
6319 relax_start (offset_expr.X_add_symbol);
6320 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6321 mips_gp_register);
6322 relax_switch ();
6323 }
6324 macro_build_lui (&offset_expr, tempreg);
6325 macro_build (&offset_expr, s, fmt, treg,
6326 BFD_RELOC_LO16, tempreg);
6327 if (mips_relax.sequence)
6328 relax_end ();
6329 }
6330 else
6331 {
6332 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6333 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6334 {
6335 relax_start (offset_expr.X_add_symbol);
6336 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6337 tempreg, breg, mips_gp_register);
6338 macro_build (&offset_expr, s, fmt, treg,
6339 BFD_RELOC_GPREL16, tempreg);
6340 relax_switch ();
6341 }
6342 macro_build_lui (&offset_expr, tempreg);
6343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6344 tempreg, tempreg, breg);
6345 macro_build (&offset_expr, s, fmt, treg,
6346 BFD_RELOC_LO16, tempreg);
6347 if (mips_relax.sequence)
6348 relax_end ();
6349 }
6350 }
6351 else if (!mips_big_got)
6352 {
6353 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6354
6355 /* If this is a reference to an external symbol, we want
6356 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6357 nop
6358 <op> $treg,0($tempreg)
6359 Otherwise we want
6360 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6361 nop
6362 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6363 <op> $treg,0($tempreg)
6364
6365 For NewABI, we want
6366 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6367 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6368
6369 If there is a base register, we add it to $tempreg before
6370 the <op>. If there is a constant, we stick it in the
6371 <op> instruction. We don't handle constants larger than
6372 16 bits, because we have no way to load the upper 16 bits
6373 (actually, we could handle them for the subset of cases
6374 in which we are not using $at). */
6375 assert (offset_expr.X_op == O_symbol);
6376 if (HAVE_NEWABI)
6377 {
6378 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6379 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6380 if (breg != 0)
6381 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6382 tempreg, tempreg, breg);
6383 macro_build (&offset_expr, s, fmt, treg,
6384 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6385 break;
6386 }
6387 expr1.X_add_number = offset_expr.X_add_number;
6388 offset_expr.X_add_number = 0;
6389 if (expr1.X_add_number < -0x8000
6390 || expr1.X_add_number >= 0x8000)
6391 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6392 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6393 lw_reloc_type, mips_gp_register);
6394 load_delay_nop ();
6395 relax_start (offset_expr.X_add_symbol);
6396 relax_switch ();
6397 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6398 tempreg, BFD_RELOC_LO16);
6399 relax_end ();
6400 if (breg != 0)
6401 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6402 tempreg, tempreg, breg);
6403 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6404 }
6405 else if (mips_big_got && !HAVE_NEWABI)
6406 {
6407 int gpdelay;
6408
6409 /* If this is a reference to an external symbol, we want
6410 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6411 addu $tempreg,$tempreg,$gp
6412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6413 <op> $treg,0($tempreg)
6414 Otherwise we want
6415 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6416 nop
6417 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6418 <op> $treg,0($tempreg)
6419 If there is a base register, we add it to $tempreg before
6420 the <op>. If there is a constant, we stick it in the
6421 <op> instruction. We don't handle constants larger than
6422 16 bits, because we have no way to load the upper 16 bits
6423 (actually, we could handle them for the subset of cases
6424 in which we are not using $at). */
6425 assert (offset_expr.X_op == O_symbol);
6426 expr1.X_add_number = offset_expr.X_add_number;
6427 offset_expr.X_add_number = 0;
6428 if (expr1.X_add_number < -0x8000
6429 || expr1.X_add_number >= 0x8000)
6430 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6431 gpdelay = reg_needs_delay (mips_gp_register);
6432 relax_start (offset_expr.X_add_symbol);
6433 macro_build (&offset_expr, "lui", "t,u", tempreg,
6434 BFD_RELOC_MIPS_GOT_HI16);
6435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6436 mips_gp_register);
6437 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6438 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6439 relax_switch ();
6440 if (gpdelay)
6441 macro_build (NULL, "nop", "");
6442 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6443 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6444 load_delay_nop ();
6445 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6446 tempreg, BFD_RELOC_LO16);
6447 relax_end ();
6448
6449 if (breg != 0)
6450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6451 tempreg, tempreg, breg);
6452 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6453 }
6454 else if (mips_big_got && HAVE_NEWABI)
6455 {
6456 /* If this is a reference to an external symbol, we want
6457 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6458 add $tempreg,$tempreg,$gp
6459 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6460 <op> $treg,<ofst>($tempreg)
6461 Otherwise, for local symbols, we want:
6462 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6463 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6464 assert (offset_expr.X_op == O_symbol);
6465 expr1.X_add_number = offset_expr.X_add_number;
6466 offset_expr.X_add_number = 0;
6467 if (expr1.X_add_number < -0x8000
6468 || expr1.X_add_number >= 0x8000)
6469 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6470 relax_start (offset_expr.X_add_symbol);
6471 macro_build (&offset_expr, "lui", "t,u", tempreg,
6472 BFD_RELOC_MIPS_GOT_HI16);
6473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6474 mips_gp_register);
6475 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6476 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6477 if (breg != 0)
6478 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6479 tempreg, tempreg, breg);
6480 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6481
6482 relax_switch ();
6483 offset_expr.X_add_number = expr1.X_add_number;
6484 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6485 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6486 if (breg != 0)
6487 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6488 tempreg, tempreg, breg);
6489 macro_build (&offset_expr, s, fmt, treg,
6490 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6491 relax_end ();
6492 }
6493 else
6494 abort ();
6495
6496 break;
6497
6498 case M_LI:
6499 case M_LI_S:
6500 load_register (treg, &imm_expr, 0);
6501 break;
6502
6503 case M_DLI:
6504 load_register (treg, &imm_expr, 1);
6505 break;
6506
6507 case M_LI_SS:
6508 if (imm_expr.X_op == O_constant)
6509 {
6510 used_at = 1;
6511 load_register (AT, &imm_expr, 0);
6512 macro_build (NULL, "mtc1", "t,G", AT, treg);
6513 break;
6514 }
6515 else
6516 {
6517 assert (offset_expr.X_op == O_symbol
6518 && strcmp (segment_name (S_GET_SEGMENT
6519 (offset_expr.X_add_symbol)),
6520 ".lit4") == 0
6521 && offset_expr.X_add_number == 0);
6522 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6523 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6524 break;
6525 }
6526
6527 case M_LI_D:
6528 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6529 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6530 order 32 bits of the value and the low order 32 bits are either
6531 zero or in OFFSET_EXPR. */
6532 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6533 {
6534 if (HAVE_64BIT_GPRS)
6535 load_register (treg, &imm_expr, 1);
6536 else
6537 {
6538 int hreg, lreg;
6539
6540 if (target_big_endian)
6541 {
6542 hreg = treg;
6543 lreg = treg + 1;
6544 }
6545 else
6546 {
6547 hreg = treg + 1;
6548 lreg = treg;
6549 }
6550
6551 if (hreg <= 31)
6552 load_register (hreg, &imm_expr, 0);
6553 if (lreg <= 31)
6554 {
6555 if (offset_expr.X_op == O_absent)
6556 move_register (lreg, 0);
6557 else
6558 {
6559 assert (offset_expr.X_op == O_constant);
6560 load_register (lreg, &offset_expr, 0);
6561 }
6562 }
6563 }
6564 break;
6565 }
6566
6567 /* We know that sym is in the .rdata section. First we get the
6568 upper 16 bits of the address. */
6569 if (mips_pic == NO_PIC)
6570 {
6571 macro_build_lui (&offset_expr, AT);
6572 used_at = 1;
6573 }
6574 else
6575 {
6576 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6577 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6578 used_at = 1;
6579 }
6580
6581 /* Now we load the register(s). */
6582 if (HAVE_64BIT_GPRS)
6583 {
6584 used_at = 1;
6585 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6586 }
6587 else
6588 {
6589 used_at = 1;
6590 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6591 if (treg != RA)
6592 {
6593 /* FIXME: How in the world do we deal with the possible
6594 overflow here? */
6595 offset_expr.X_add_number += 4;
6596 macro_build (&offset_expr, "lw", "t,o(b)",
6597 treg + 1, BFD_RELOC_LO16, AT);
6598 }
6599 }
6600 break;
6601
6602 case M_LI_DD:
6603 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6604 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6605 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6606 the value and the low order 32 bits are either zero or in
6607 OFFSET_EXPR. */
6608 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6609 {
6610 used_at = 1;
6611 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6612 if (HAVE_64BIT_FPRS)
6613 {
6614 assert (HAVE_64BIT_GPRS);
6615 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6616 }
6617 else
6618 {
6619 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6620 if (offset_expr.X_op == O_absent)
6621 macro_build (NULL, "mtc1", "t,G", 0, treg);
6622 else
6623 {
6624 assert (offset_expr.X_op == O_constant);
6625 load_register (AT, &offset_expr, 0);
6626 macro_build (NULL, "mtc1", "t,G", AT, treg);
6627 }
6628 }
6629 break;
6630 }
6631
6632 assert (offset_expr.X_op == O_symbol
6633 && offset_expr.X_add_number == 0);
6634 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6635 if (strcmp (s, ".lit8") == 0)
6636 {
6637 if (mips_opts.isa != ISA_MIPS1)
6638 {
6639 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6640 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6641 break;
6642 }
6643 breg = mips_gp_register;
6644 r = BFD_RELOC_MIPS_LITERAL;
6645 goto dob;
6646 }
6647 else
6648 {
6649 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6650 used_at = 1;
6651 if (mips_pic != NO_PIC)
6652 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6653 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6654 else
6655 {
6656 /* FIXME: This won't work for a 64 bit address. */
6657 macro_build_lui (&offset_expr, AT);
6658 }
6659
6660 if (mips_opts.isa != ISA_MIPS1)
6661 {
6662 macro_build (&offset_expr, "ldc1", "T,o(b)",
6663 treg, BFD_RELOC_LO16, AT);
6664 break;
6665 }
6666 breg = AT;
6667 r = BFD_RELOC_LO16;
6668 goto dob;
6669 }
6670
6671 case M_L_DOB:
6672 if (mips_opts.arch == CPU_R4650)
6673 {
6674 as_bad (_("opcode not supported on this processor"));
6675 break;
6676 }
6677 /* Even on a big endian machine $fn comes before $fn+1. We have
6678 to adjust when loading from memory. */
6679 r = BFD_RELOC_LO16;
6680 dob:
6681 assert (mips_opts.isa == ISA_MIPS1);
6682 macro_build (&offset_expr, "lwc1", "T,o(b)",
6683 target_big_endian ? treg + 1 : treg, r, breg);
6684 /* FIXME: A possible overflow which I don't know how to deal
6685 with. */
6686 offset_expr.X_add_number += 4;
6687 macro_build (&offset_expr, "lwc1", "T,o(b)",
6688 target_big_endian ? treg : treg + 1, r, breg);
6689 break;
6690
6691 case M_L_DAB:
6692 /*
6693 * The MIPS assembler seems to check for X_add_number not
6694 * being double aligned and generating:
6695 * lui at,%hi(foo+1)
6696 * addu at,at,v1
6697 * addiu at,at,%lo(foo+1)
6698 * lwc1 f2,0(at)
6699 * lwc1 f3,4(at)
6700 * But, the resulting address is the same after relocation so why
6701 * generate the extra instruction?
6702 */
6703 if (mips_opts.arch == CPU_R4650)
6704 {
6705 as_bad (_("opcode not supported on this processor"));
6706 break;
6707 }
6708 /* Itbl support may require additional care here. */
6709 coproc = 1;
6710 if (mips_opts.isa != ISA_MIPS1)
6711 {
6712 s = "ldc1";
6713 goto ld;
6714 }
6715
6716 s = "lwc1";
6717 fmt = "T,o(b)";
6718 goto ldd_std;
6719
6720 case M_S_DAB:
6721 if (mips_opts.arch == CPU_R4650)
6722 {
6723 as_bad (_("opcode not supported on this processor"));
6724 break;
6725 }
6726
6727 if (mips_opts.isa != ISA_MIPS1)
6728 {
6729 s = "sdc1";
6730 goto st;
6731 }
6732
6733 s = "swc1";
6734 fmt = "T,o(b)";
6735 /* Itbl support may require additional care here. */
6736 coproc = 1;
6737 goto ldd_std;
6738
6739 case M_LD_AB:
6740 if (HAVE_64BIT_GPRS)
6741 {
6742 s = "ld";
6743 goto ld;
6744 }
6745
6746 s = "lw";
6747 fmt = "t,o(b)";
6748 goto ldd_std;
6749
6750 case M_SD_AB:
6751 if (HAVE_64BIT_GPRS)
6752 {
6753 s = "sd";
6754 goto st;
6755 }
6756
6757 s = "sw";
6758 fmt = "t,o(b)";
6759
6760 ldd_std:
6761 if (offset_expr.X_op != O_symbol
6762 && offset_expr.X_op != O_constant)
6763 {
6764 as_bad (_("expression too complex"));
6765 offset_expr.X_op = O_constant;
6766 }
6767
6768 if (HAVE_32BIT_ADDRESSES
6769 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6770 {
6771 char value [32];
6772
6773 sprintf_vma (value, offset_expr.X_add_number);
6774 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6775 }
6776
6777 /* Even on a big endian machine $fn comes before $fn+1. We have
6778 to adjust when loading from memory. We set coproc if we must
6779 load $fn+1 first. */
6780 /* Itbl support may require additional care here. */
6781 if (! target_big_endian)
6782 coproc = 0;
6783
6784 if (mips_pic == NO_PIC
6785 || offset_expr.X_op == O_constant)
6786 {
6787 /* If this is a reference to a GP relative symbol, we want
6788 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6789 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6790 If we have a base register, we use this
6791 addu $at,$breg,$gp
6792 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6793 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6794 If this is not a GP relative symbol, we want
6795 lui $at,<sym> (BFD_RELOC_HI16_S)
6796 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6797 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6798 If there is a base register, we add it to $at after the
6799 lui instruction. If there is a constant, we always use
6800 the last case. */
6801 if (offset_expr.X_op == O_symbol
6802 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6803 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6804 {
6805 relax_start (offset_expr.X_add_symbol);
6806 if (breg == 0)
6807 {
6808 tempreg = mips_gp_register;
6809 }
6810 else
6811 {
6812 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6813 AT, breg, mips_gp_register);
6814 tempreg = AT;
6815 used_at = 1;
6816 }
6817
6818 /* Itbl support may require additional care here. */
6819 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6820 BFD_RELOC_GPREL16, tempreg);
6821 offset_expr.X_add_number += 4;
6822
6823 /* Set mips_optimize to 2 to avoid inserting an
6824 undesired nop. */
6825 hold_mips_optimize = mips_optimize;
6826 mips_optimize = 2;
6827 /* Itbl support may require additional care here. */
6828 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6829 BFD_RELOC_GPREL16, tempreg);
6830 mips_optimize = hold_mips_optimize;
6831
6832 relax_switch ();
6833
6834 /* We just generated two relocs. When tc_gen_reloc
6835 handles this case, it will skip the first reloc and
6836 handle the second. The second reloc already has an
6837 extra addend of 4, which we added above. We must
6838 subtract it out, and then subtract another 4 to make
6839 the first reloc come out right. The second reloc
6840 will come out right because we are going to add 4 to
6841 offset_expr when we build its instruction below.
6842
6843 If we have a symbol, then we don't want to include
6844 the offset, because it will wind up being included
6845 when we generate the reloc. */
6846
6847 if (offset_expr.X_op == O_constant)
6848 offset_expr.X_add_number -= 8;
6849 else
6850 {
6851 offset_expr.X_add_number = -4;
6852 offset_expr.X_op = O_constant;
6853 }
6854 }
6855 used_at = 1;
6856 macro_build_lui (&offset_expr, AT);
6857 if (breg != 0)
6858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6859 /* Itbl support may require additional care here. */
6860 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6861 BFD_RELOC_LO16, AT);
6862 /* FIXME: How do we handle overflow here? */
6863 offset_expr.X_add_number += 4;
6864 /* Itbl support may require additional care here. */
6865 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6866 BFD_RELOC_LO16, AT);
6867 if (mips_relax.sequence)
6868 relax_end ();
6869 }
6870 else if (!mips_big_got)
6871 {
6872 /* If this is a reference to an external symbol, we want
6873 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6874 nop
6875 <op> $treg,0($at)
6876 <op> $treg+1,4($at)
6877 Otherwise we want
6878 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6879 nop
6880 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6881 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6882 If there is a base register we add it to $at before the
6883 lwc1 instructions. If there is a constant we include it
6884 in the lwc1 instructions. */
6885 used_at = 1;
6886 expr1.X_add_number = offset_expr.X_add_number;
6887 if (expr1.X_add_number < -0x8000
6888 || expr1.X_add_number >= 0x8000 - 4)
6889 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6890 load_got_offset (AT, &offset_expr);
6891 load_delay_nop ();
6892 if (breg != 0)
6893 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6894
6895 /* Set mips_optimize to 2 to avoid inserting an undesired
6896 nop. */
6897 hold_mips_optimize = mips_optimize;
6898 mips_optimize = 2;
6899
6900 /* Itbl support may require additional care here. */
6901 relax_start (offset_expr.X_add_symbol);
6902 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6903 BFD_RELOC_LO16, AT);
6904 expr1.X_add_number += 4;
6905 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6906 BFD_RELOC_LO16, AT);
6907 relax_switch ();
6908 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6909 BFD_RELOC_LO16, AT);
6910 offset_expr.X_add_number += 4;
6911 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6912 BFD_RELOC_LO16, AT);
6913 relax_end ();
6914
6915 mips_optimize = hold_mips_optimize;
6916 }
6917 else if (mips_big_got)
6918 {
6919 int gpdelay;
6920
6921 /* If this is a reference to an external symbol, we want
6922 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6923 addu $at,$at,$gp
6924 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6925 nop
6926 <op> $treg,0($at)
6927 <op> $treg+1,4($at)
6928 Otherwise we want
6929 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6930 nop
6931 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6932 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6933 If there is a base register we add it to $at before the
6934 lwc1 instructions. If there is a constant we include it
6935 in the lwc1 instructions. */
6936 used_at = 1;
6937 expr1.X_add_number = offset_expr.X_add_number;
6938 offset_expr.X_add_number = 0;
6939 if (expr1.X_add_number < -0x8000
6940 || expr1.X_add_number >= 0x8000 - 4)
6941 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6942 gpdelay = reg_needs_delay (mips_gp_register);
6943 relax_start (offset_expr.X_add_symbol);
6944 macro_build (&offset_expr, "lui", "t,u",
6945 AT, BFD_RELOC_MIPS_GOT_HI16);
6946 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6947 AT, AT, mips_gp_register);
6948 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6949 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6950 load_delay_nop ();
6951 if (breg != 0)
6952 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6953 /* Itbl support may require additional care here. */
6954 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6955 BFD_RELOC_LO16, AT);
6956 expr1.X_add_number += 4;
6957
6958 /* Set mips_optimize to 2 to avoid inserting an undesired
6959 nop. */
6960 hold_mips_optimize = mips_optimize;
6961 mips_optimize = 2;
6962 /* Itbl support may require additional care here. */
6963 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6964 BFD_RELOC_LO16, AT);
6965 mips_optimize = hold_mips_optimize;
6966 expr1.X_add_number -= 4;
6967
6968 relax_switch ();
6969 offset_expr.X_add_number = expr1.X_add_number;
6970 if (gpdelay)
6971 macro_build (NULL, "nop", "");
6972 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6973 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6974 load_delay_nop ();
6975 if (breg != 0)
6976 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6977 /* Itbl support may require additional care here. */
6978 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6979 BFD_RELOC_LO16, AT);
6980 offset_expr.X_add_number += 4;
6981
6982 /* Set mips_optimize to 2 to avoid inserting an undesired
6983 nop. */
6984 hold_mips_optimize = mips_optimize;
6985 mips_optimize = 2;
6986 /* Itbl support may require additional care here. */
6987 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6988 BFD_RELOC_LO16, AT);
6989 mips_optimize = hold_mips_optimize;
6990 relax_end ();
6991 }
6992 else
6993 abort ();
6994
6995 break;
6996
6997 case M_LD_OB:
6998 s = "lw";
6999 goto sd_ob;
7000 case M_SD_OB:
7001 s = "sw";
7002 sd_ob:
7003 assert (HAVE_32BIT_ADDRESSES);
7004 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7005 offset_expr.X_add_number += 4;
7006 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7007 break;
7008
7009 /* New code added to support COPZ instructions.
7010 This code builds table entries out of the macros in mip_opcodes.
7011 R4000 uses interlocks to handle coproc delays.
7012 Other chips (like the R3000) require nops to be inserted for delays.
7013
7014 FIXME: Currently, we require that the user handle delays.
7015 In order to fill delay slots for non-interlocked chips,
7016 we must have a way to specify delays based on the coprocessor.
7017 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7018 What are the side-effects of the cop instruction?
7019 What cache support might we have and what are its effects?
7020 Both coprocessor & memory require delays. how long???
7021 What registers are read/set/modified?
7022
7023 If an itbl is provided to interpret cop instructions,
7024 this knowledge can be encoded in the itbl spec. */
7025
7026 case M_COP0:
7027 s = "c0";
7028 goto copz;
7029 case M_COP1:
7030 s = "c1";
7031 goto copz;
7032 case M_COP2:
7033 s = "c2";
7034 goto copz;
7035 case M_COP3:
7036 s = "c3";
7037 copz:
7038 /* For now we just do C (same as Cz). The parameter will be
7039 stored in insn_opcode by mips_ip. */
7040 macro_build (NULL, s, "C", ip->insn_opcode);
7041 break;
7042
7043 case M_MOVE:
7044 move_register (dreg, sreg);
7045 break;
7046
7047 #ifdef LOSING_COMPILER
7048 default:
7049 /* Try and see if this is a new itbl instruction.
7050 This code builds table entries out of the macros in mip_opcodes.
7051 FIXME: For now we just assemble the expression and pass it's
7052 value along as a 32-bit immediate.
7053 We may want to have the assembler assemble this value,
7054 so that we gain the assembler's knowledge of delay slots,
7055 symbols, etc.
7056 Would it be more efficient to use mask (id) here? */
7057 if (itbl_have_entries
7058 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7059 {
7060 s = ip->insn_mo->name;
7061 s2 = "cop3";
7062 coproc = ITBL_DECODE_PNUM (immed_expr);;
7063 macro_build (&immed_expr, s, "C");
7064 break;
7065 }
7066 macro2 (ip);
7067 break;
7068 }
7069 if (mips_opts.noat && used_at)
7070 as_bad (_("Macro used $at after \".set noat\""));
7071 }
7072
7073 static void
7074 macro2 (struct mips_cl_insn *ip)
7075 {
7076 register int treg, sreg, dreg, breg;
7077 int tempreg;
7078 int mask;
7079 int used_at;
7080 expressionS expr1;
7081 const char *s;
7082 const char *s2;
7083 const char *fmt;
7084 int likely = 0;
7085 int dbl = 0;
7086 int coproc = 0;
7087 int lr = 0;
7088 int imm = 0;
7089 int off;
7090 offsetT maxnum;
7091 bfd_reloc_code_real_type r;
7092
7093 treg = (ip->insn_opcode >> 16) & 0x1f;
7094 dreg = (ip->insn_opcode >> 11) & 0x1f;
7095 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7096 mask = ip->insn_mo->mask;
7097
7098 expr1.X_op = O_constant;
7099 expr1.X_op_symbol = NULL;
7100 expr1.X_add_symbol = NULL;
7101 expr1.X_add_number = 1;
7102
7103 switch (mask)
7104 {
7105 #endif /* LOSING_COMPILER */
7106
7107 case M_DMUL:
7108 dbl = 1;
7109 case M_MUL:
7110 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7111 macro_build (NULL, "mflo", "d", dreg);
7112 break;
7113
7114 case M_DMUL_I:
7115 dbl = 1;
7116 case M_MUL_I:
7117 /* The MIPS assembler some times generates shifts and adds. I'm
7118 not trying to be that fancy. GCC should do this for us
7119 anyway. */
7120 used_at = 1;
7121 load_register (AT, &imm_expr, dbl);
7122 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7123 macro_build (NULL, "mflo", "d", dreg);
7124 break;
7125
7126 case M_DMULO_I:
7127 dbl = 1;
7128 case M_MULO_I:
7129 imm = 1;
7130 goto do_mulo;
7131
7132 case M_DMULO:
7133 dbl = 1;
7134 case M_MULO:
7135 do_mulo:
7136 start_noreorder ();
7137 used_at = 1;
7138 if (imm)
7139 load_register (AT, &imm_expr, dbl);
7140 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7141 macro_build (NULL, "mflo", "d", dreg);
7142 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7143 macro_build (NULL, "mfhi", "d", AT);
7144 if (mips_trap)
7145 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7146 else
7147 {
7148 expr1.X_add_number = 8;
7149 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7150 macro_build (NULL, "nop", "", 0);
7151 macro_build (NULL, "break", "c", 6);
7152 }
7153 end_noreorder ();
7154 macro_build (NULL, "mflo", "d", dreg);
7155 break;
7156
7157 case M_DMULOU_I:
7158 dbl = 1;
7159 case M_MULOU_I:
7160 imm = 1;
7161 goto do_mulou;
7162
7163 case M_DMULOU:
7164 dbl = 1;
7165 case M_MULOU:
7166 do_mulou:
7167 start_noreorder ();
7168 used_at = 1;
7169 if (imm)
7170 load_register (AT, &imm_expr, dbl);
7171 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7172 sreg, imm ? AT : treg);
7173 macro_build (NULL, "mfhi", "d", AT);
7174 macro_build (NULL, "mflo", "d", dreg);
7175 if (mips_trap)
7176 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7177 else
7178 {
7179 expr1.X_add_number = 8;
7180 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7181 macro_build (NULL, "nop", "", 0);
7182 macro_build (NULL, "break", "c", 6);
7183 }
7184 end_noreorder ();
7185 break;
7186
7187 case M_DROL:
7188 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7189 {
7190 if (dreg == sreg)
7191 {
7192 tempreg = AT;
7193 used_at = 1;
7194 }
7195 else
7196 {
7197 tempreg = dreg;
7198 }
7199 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7200 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7201 break;
7202 }
7203 used_at = 1;
7204 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7205 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7206 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7207 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7208 break;
7209
7210 case M_ROL:
7211 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7212 {
7213 if (dreg == sreg)
7214 {
7215 tempreg = AT;
7216 used_at = 1;
7217 }
7218 else
7219 {
7220 tempreg = dreg;
7221 }
7222 macro_build (NULL, "negu", "d,w", tempreg, treg);
7223 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7224 break;
7225 }
7226 used_at = 1;
7227 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7228 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7229 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7230 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7231 break;
7232
7233 case M_DROL_I:
7234 {
7235 unsigned int rot;
7236 char *l, *r;
7237
7238 if (imm_expr.X_op != O_constant)
7239 as_bad (_("Improper rotate count"));
7240 rot = imm_expr.X_add_number & 0x3f;
7241 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7242 {
7243 rot = (64 - rot) & 0x3f;
7244 if (rot >= 32)
7245 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7246 else
7247 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7248 break;
7249 }
7250 if (rot == 0)
7251 {
7252 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7253 break;
7254 }
7255 l = (rot < 0x20) ? "dsll" : "dsll32";
7256 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7257 rot &= 0x1f;
7258 used_at = 1;
7259 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7260 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7261 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7262 }
7263 break;
7264
7265 case M_ROL_I:
7266 {
7267 unsigned int rot;
7268
7269 if (imm_expr.X_op != O_constant)
7270 as_bad (_("Improper rotate count"));
7271 rot = imm_expr.X_add_number & 0x1f;
7272 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7273 {
7274 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7275 break;
7276 }
7277 if (rot == 0)
7278 {
7279 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7280 break;
7281 }
7282 used_at = 1;
7283 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7284 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7285 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7286 }
7287 break;
7288
7289 case M_DROR:
7290 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7291 {
7292 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7293 break;
7294 }
7295 used_at = 1;
7296 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7297 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7298 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7299 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7300 break;
7301
7302 case M_ROR:
7303 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7304 {
7305 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7306 break;
7307 }
7308 used_at = 1;
7309 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7310 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7311 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7312 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7313 break;
7314
7315 case M_DROR_I:
7316 {
7317 unsigned int rot;
7318 char *l, *r;
7319
7320 if (imm_expr.X_op != O_constant)
7321 as_bad (_("Improper rotate count"));
7322 rot = imm_expr.X_add_number & 0x3f;
7323 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7324 {
7325 if (rot >= 32)
7326 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7327 else
7328 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7329 break;
7330 }
7331 if (rot == 0)
7332 {
7333 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7334 break;
7335 }
7336 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7337 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7338 rot &= 0x1f;
7339 used_at = 1;
7340 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7341 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7342 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7343 }
7344 break;
7345
7346 case M_ROR_I:
7347 {
7348 unsigned int rot;
7349
7350 if (imm_expr.X_op != O_constant)
7351 as_bad (_("Improper rotate count"));
7352 rot = imm_expr.X_add_number & 0x1f;
7353 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7354 {
7355 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7356 break;
7357 }
7358 if (rot == 0)
7359 {
7360 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7361 break;
7362 }
7363 used_at = 1;
7364 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7365 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7366 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7367 }
7368 break;
7369
7370 case M_S_DOB:
7371 if (mips_opts.arch == CPU_R4650)
7372 {
7373 as_bad (_("opcode not supported on this processor"));
7374 break;
7375 }
7376 assert (mips_opts.isa == ISA_MIPS1);
7377 /* Even on a big endian machine $fn comes before $fn+1. We have
7378 to adjust when storing to memory. */
7379 macro_build (&offset_expr, "swc1", "T,o(b)",
7380 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7381 offset_expr.X_add_number += 4;
7382 macro_build (&offset_expr, "swc1", "T,o(b)",
7383 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7384 break;
7385
7386 case M_SEQ:
7387 if (sreg == 0)
7388 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7389 else if (treg == 0)
7390 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7391 else
7392 {
7393 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7394 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7395 }
7396 break;
7397
7398 case M_SEQ_I:
7399 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7400 {
7401 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7402 break;
7403 }
7404 if (sreg == 0)
7405 {
7406 as_warn (_("Instruction %s: result is always false"),
7407 ip->insn_mo->name);
7408 move_register (dreg, 0);
7409 break;
7410 }
7411 if (imm_expr.X_op == O_constant
7412 && imm_expr.X_add_number >= 0
7413 && imm_expr.X_add_number < 0x10000)
7414 {
7415 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7416 }
7417 else if (imm_expr.X_op == O_constant
7418 && imm_expr.X_add_number > -0x8000
7419 && imm_expr.X_add_number < 0)
7420 {
7421 imm_expr.X_add_number = -imm_expr.X_add_number;
7422 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7423 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7424 }
7425 else
7426 {
7427 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7428 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7429 used_at = 1;
7430 }
7431 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7432 break;
7433
7434 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7435 s = "slt";
7436 goto sge;
7437 case M_SGEU:
7438 s = "sltu";
7439 sge:
7440 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7441 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7442 break;
7443
7444 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7445 case M_SGEU_I:
7446 if (imm_expr.X_op == O_constant
7447 && imm_expr.X_add_number >= -0x8000
7448 && imm_expr.X_add_number < 0x8000)
7449 {
7450 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7451 dreg, sreg, BFD_RELOC_LO16);
7452 }
7453 else
7454 {
7455 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7456 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7457 dreg, sreg, AT);
7458 used_at = 1;
7459 }
7460 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7461 break;
7462
7463 case M_SGT: /* sreg > treg <==> treg < sreg */
7464 s = "slt";
7465 goto sgt;
7466 case M_SGTU:
7467 s = "sltu";
7468 sgt:
7469 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7470 break;
7471
7472 case M_SGT_I: /* sreg > I <==> I < sreg */
7473 s = "slt";
7474 goto sgti;
7475 case M_SGTU_I:
7476 s = "sltu";
7477 sgti:
7478 used_at = 1;
7479 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7480 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7481 break;
7482
7483 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7484 s = "slt";
7485 goto sle;
7486 case M_SLEU:
7487 s = "sltu";
7488 sle:
7489 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7490 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7491 break;
7492
7493 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7494 s = "slt";
7495 goto slei;
7496 case M_SLEU_I:
7497 s = "sltu";
7498 slei:
7499 used_at = 1;
7500 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7501 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7502 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7503 break;
7504
7505 case M_SLT_I:
7506 if (imm_expr.X_op == O_constant
7507 && imm_expr.X_add_number >= -0x8000
7508 && imm_expr.X_add_number < 0x8000)
7509 {
7510 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7511 break;
7512 }
7513 used_at = 1;
7514 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7515 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7516 break;
7517
7518 case M_SLTU_I:
7519 if (imm_expr.X_op == O_constant
7520 && imm_expr.X_add_number >= -0x8000
7521 && imm_expr.X_add_number < 0x8000)
7522 {
7523 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7524 BFD_RELOC_LO16);
7525 break;
7526 }
7527 used_at = 1;
7528 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7529 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7530 break;
7531
7532 case M_SNE:
7533 if (sreg == 0)
7534 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7535 else if (treg == 0)
7536 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7537 else
7538 {
7539 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7540 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7541 }
7542 break;
7543
7544 case M_SNE_I:
7545 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7546 {
7547 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7548 break;
7549 }
7550 if (sreg == 0)
7551 {
7552 as_warn (_("Instruction %s: result is always true"),
7553 ip->insn_mo->name);
7554 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7555 dreg, 0, BFD_RELOC_LO16);
7556 break;
7557 }
7558 if (imm_expr.X_op == O_constant
7559 && imm_expr.X_add_number >= 0
7560 && imm_expr.X_add_number < 0x10000)
7561 {
7562 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7563 }
7564 else if (imm_expr.X_op == O_constant
7565 && imm_expr.X_add_number > -0x8000
7566 && imm_expr.X_add_number < 0)
7567 {
7568 imm_expr.X_add_number = -imm_expr.X_add_number;
7569 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7570 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7571 }
7572 else
7573 {
7574 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7575 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7576 used_at = 1;
7577 }
7578 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7579 break;
7580
7581 case M_DSUB_I:
7582 dbl = 1;
7583 case M_SUB_I:
7584 if (imm_expr.X_op == O_constant
7585 && imm_expr.X_add_number > -0x8000
7586 && imm_expr.X_add_number <= 0x8000)
7587 {
7588 imm_expr.X_add_number = -imm_expr.X_add_number;
7589 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7590 dreg, sreg, BFD_RELOC_LO16);
7591 break;
7592 }
7593 used_at = 1;
7594 load_register (AT, &imm_expr, dbl);
7595 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7596 break;
7597
7598 case M_DSUBU_I:
7599 dbl = 1;
7600 case M_SUBU_I:
7601 if (imm_expr.X_op == O_constant
7602 && imm_expr.X_add_number > -0x8000
7603 && imm_expr.X_add_number <= 0x8000)
7604 {
7605 imm_expr.X_add_number = -imm_expr.X_add_number;
7606 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7607 dreg, sreg, BFD_RELOC_LO16);
7608 break;
7609 }
7610 used_at = 1;
7611 load_register (AT, &imm_expr, dbl);
7612 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7613 break;
7614
7615 case M_TEQ_I:
7616 s = "teq";
7617 goto trap;
7618 case M_TGE_I:
7619 s = "tge";
7620 goto trap;
7621 case M_TGEU_I:
7622 s = "tgeu";
7623 goto trap;
7624 case M_TLT_I:
7625 s = "tlt";
7626 goto trap;
7627 case M_TLTU_I:
7628 s = "tltu";
7629 goto trap;
7630 case M_TNE_I:
7631 s = "tne";
7632 trap:
7633 used_at = 1;
7634 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7635 macro_build (NULL, s, "s,t", sreg, AT);
7636 break;
7637
7638 case M_TRUNCWS:
7639 case M_TRUNCWD:
7640 assert (mips_opts.isa == ISA_MIPS1);
7641 used_at = 1;
7642 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7643 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7644
7645 /*
7646 * Is the double cfc1 instruction a bug in the mips assembler;
7647 * or is there a reason for it?
7648 */
7649 start_noreorder ();
7650 macro_build (NULL, "cfc1", "t,G", treg, RA);
7651 macro_build (NULL, "cfc1", "t,G", treg, RA);
7652 macro_build (NULL, "nop", "");
7653 expr1.X_add_number = 3;
7654 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7655 expr1.X_add_number = 2;
7656 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7657 macro_build (NULL, "ctc1", "t,G", AT, RA);
7658 macro_build (NULL, "nop", "");
7659 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7660 dreg, sreg);
7661 macro_build (NULL, "ctc1", "t,G", treg, RA);
7662 macro_build (NULL, "nop", "");
7663 end_noreorder ();
7664 break;
7665
7666 case M_ULH:
7667 s = "lb";
7668 goto ulh;
7669 case M_ULHU:
7670 s = "lbu";
7671 ulh:
7672 used_at = 1;
7673 if (offset_expr.X_add_number >= 0x7fff)
7674 as_bad (_("operand overflow"));
7675 if (! target_big_endian)
7676 ++offset_expr.X_add_number;
7677 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7678 if (! target_big_endian)
7679 --offset_expr.X_add_number;
7680 else
7681 ++offset_expr.X_add_number;
7682 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7683 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7684 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7685 break;
7686
7687 case M_ULD:
7688 s = "ldl";
7689 s2 = "ldr";
7690 off = 7;
7691 goto ulw;
7692 case M_ULW:
7693 s = "lwl";
7694 s2 = "lwr";
7695 off = 3;
7696 ulw:
7697 if (offset_expr.X_add_number >= 0x8000 - off)
7698 as_bad (_("operand overflow"));
7699 if (treg != breg)
7700 tempreg = treg;
7701 else
7702 {
7703 used_at = 1;
7704 tempreg = AT;
7705 }
7706 if (! target_big_endian)
7707 offset_expr.X_add_number += off;
7708 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7709 if (! target_big_endian)
7710 offset_expr.X_add_number -= off;
7711 else
7712 offset_expr.X_add_number += off;
7713 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7714
7715 /* If necessary, move the result in tempreg the final destination. */
7716 if (treg == tempreg)
7717 break;
7718 /* Protect second load's delay slot. */
7719 load_delay_nop ();
7720 move_register (treg, tempreg);
7721 break;
7722
7723 case M_ULD_A:
7724 s = "ldl";
7725 s2 = "ldr";
7726 off = 7;
7727 goto ulwa;
7728 case M_ULW_A:
7729 s = "lwl";
7730 s2 = "lwr";
7731 off = 3;
7732 ulwa:
7733 used_at = 1;
7734 load_address (AT, &offset_expr, &used_at);
7735 if (breg != 0)
7736 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7737 if (! target_big_endian)
7738 expr1.X_add_number = off;
7739 else
7740 expr1.X_add_number = 0;
7741 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7742 if (! target_big_endian)
7743 expr1.X_add_number = 0;
7744 else
7745 expr1.X_add_number = off;
7746 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7747 break;
7748
7749 case M_ULH_A:
7750 case M_ULHU_A:
7751 used_at = 1;
7752 load_address (AT, &offset_expr, &used_at);
7753 if (breg != 0)
7754 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7755 if (target_big_endian)
7756 expr1.X_add_number = 0;
7757 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7758 treg, BFD_RELOC_LO16, AT);
7759 if (target_big_endian)
7760 expr1.X_add_number = 1;
7761 else
7762 expr1.X_add_number = 0;
7763 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7764 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7765 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7766 break;
7767
7768 case M_USH:
7769 used_at = 1;
7770 if (offset_expr.X_add_number >= 0x7fff)
7771 as_bad (_("operand overflow"));
7772 if (target_big_endian)
7773 ++offset_expr.X_add_number;
7774 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7775 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7776 if (target_big_endian)
7777 --offset_expr.X_add_number;
7778 else
7779 ++offset_expr.X_add_number;
7780 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7781 break;
7782
7783 case M_USD:
7784 s = "sdl";
7785 s2 = "sdr";
7786 off = 7;
7787 goto usw;
7788 case M_USW:
7789 s = "swl";
7790 s2 = "swr";
7791 off = 3;
7792 usw:
7793 if (offset_expr.X_add_number >= 0x8000 - off)
7794 as_bad (_("operand overflow"));
7795 if (! target_big_endian)
7796 offset_expr.X_add_number += off;
7797 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7798 if (! target_big_endian)
7799 offset_expr.X_add_number -= off;
7800 else
7801 offset_expr.X_add_number += off;
7802 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7803 break;
7804
7805 case M_USD_A:
7806 s = "sdl";
7807 s2 = "sdr";
7808 off = 7;
7809 goto uswa;
7810 case M_USW_A:
7811 s = "swl";
7812 s2 = "swr";
7813 off = 3;
7814 uswa:
7815 used_at = 1;
7816 load_address (AT, &offset_expr, &used_at);
7817 if (breg != 0)
7818 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7819 if (! target_big_endian)
7820 expr1.X_add_number = off;
7821 else
7822 expr1.X_add_number = 0;
7823 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7824 if (! target_big_endian)
7825 expr1.X_add_number = 0;
7826 else
7827 expr1.X_add_number = off;
7828 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7829 break;
7830
7831 case M_USH_A:
7832 used_at = 1;
7833 load_address (AT, &offset_expr, &used_at);
7834 if (breg != 0)
7835 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7836 if (! target_big_endian)
7837 expr1.X_add_number = 0;
7838 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7839 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7840 if (! target_big_endian)
7841 expr1.X_add_number = 1;
7842 else
7843 expr1.X_add_number = 0;
7844 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7845 if (! target_big_endian)
7846 expr1.X_add_number = 0;
7847 else
7848 expr1.X_add_number = 1;
7849 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7850 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7851 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7852 break;
7853
7854 default:
7855 /* FIXME: Check if this is one of the itbl macros, since they
7856 are added dynamically. */
7857 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7858 break;
7859 }
7860 if (mips_opts.noat && used_at)
7861 as_bad (_("Macro used $at after \".set noat\""));
7862 }
7863
7864 /* Implement macros in mips16 mode. */
7865
7866 static void
7867 mips16_macro (struct mips_cl_insn *ip)
7868 {
7869 int mask;
7870 int xreg, yreg, zreg, tmp;
7871 expressionS expr1;
7872 int dbl;
7873 const char *s, *s2, *s3;
7874
7875 mask = ip->insn_mo->mask;
7876
7877 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
7878 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
7879 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
7880
7881 expr1.X_op = O_constant;
7882 expr1.X_op_symbol = NULL;
7883 expr1.X_add_symbol = NULL;
7884 expr1.X_add_number = 1;
7885
7886 dbl = 0;
7887
7888 switch (mask)
7889 {
7890 default:
7891 internalError ();
7892
7893 case M_DDIV_3:
7894 dbl = 1;
7895 case M_DIV_3:
7896 s = "mflo";
7897 goto do_div3;
7898 case M_DREM_3:
7899 dbl = 1;
7900 case M_REM_3:
7901 s = "mfhi";
7902 do_div3:
7903 start_noreorder ();
7904 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7905 expr1.X_add_number = 2;
7906 macro_build (&expr1, "bnez", "x,p", yreg);
7907 macro_build (NULL, "break", "6", 7);
7908
7909 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7910 since that causes an overflow. We should do that as well,
7911 but I don't see how to do the comparisons without a temporary
7912 register. */
7913 end_noreorder ();
7914 macro_build (NULL, s, "x", zreg);
7915 break;
7916
7917 case M_DIVU_3:
7918 s = "divu";
7919 s2 = "mflo";
7920 goto do_divu3;
7921 case M_REMU_3:
7922 s = "divu";
7923 s2 = "mfhi";
7924 goto do_divu3;
7925 case M_DDIVU_3:
7926 s = "ddivu";
7927 s2 = "mflo";
7928 goto do_divu3;
7929 case M_DREMU_3:
7930 s = "ddivu";
7931 s2 = "mfhi";
7932 do_divu3:
7933 start_noreorder ();
7934 macro_build (NULL, s, "0,x,y", xreg, yreg);
7935 expr1.X_add_number = 2;
7936 macro_build (&expr1, "bnez", "x,p", yreg);
7937 macro_build (NULL, "break", "6", 7);
7938 end_noreorder ();
7939 macro_build (NULL, s2, "x", zreg);
7940 break;
7941
7942 case M_DMUL:
7943 dbl = 1;
7944 case M_MUL:
7945 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7946 macro_build (NULL, "mflo", "x", zreg);
7947 break;
7948
7949 case M_DSUBU_I:
7950 dbl = 1;
7951 goto do_subu;
7952 case M_SUBU_I:
7953 do_subu:
7954 if (imm_expr.X_op != O_constant)
7955 as_bad (_("Unsupported large constant"));
7956 imm_expr.X_add_number = -imm_expr.X_add_number;
7957 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7958 break;
7959
7960 case M_SUBU_I_2:
7961 if (imm_expr.X_op != O_constant)
7962 as_bad (_("Unsupported large constant"));
7963 imm_expr.X_add_number = -imm_expr.X_add_number;
7964 macro_build (&imm_expr, "addiu", "x,k", xreg);
7965 break;
7966
7967 case M_DSUBU_I_2:
7968 if (imm_expr.X_op != O_constant)
7969 as_bad (_("Unsupported large constant"));
7970 imm_expr.X_add_number = -imm_expr.X_add_number;
7971 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7972 break;
7973
7974 case M_BEQ:
7975 s = "cmp";
7976 s2 = "bteqz";
7977 goto do_branch;
7978 case M_BNE:
7979 s = "cmp";
7980 s2 = "btnez";
7981 goto do_branch;
7982 case M_BLT:
7983 s = "slt";
7984 s2 = "btnez";
7985 goto do_branch;
7986 case M_BLTU:
7987 s = "sltu";
7988 s2 = "btnez";
7989 goto do_branch;
7990 case M_BLE:
7991 s = "slt";
7992 s2 = "bteqz";
7993 goto do_reverse_branch;
7994 case M_BLEU:
7995 s = "sltu";
7996 s2 = "bteqz";
7997 goto do_reverse_branch;
7998 case M_BGE:
7999 s = "slt";
8000 s2 = "bteqz";
8001 goto do_branch;
8002 case M_BGEU:
8003 s = "sltu";
8004 s2 = "bteqz";
8005 goto do_branch;
8006 case M_BGT:
8007 s = "slt";
8008 s2 = "btnez";
8009 goto do_reverse_branch;
8010 case M_BGTU:
8011 s = "sltu";
8012 s2 = "btnez";
8013
8014 do_reverse_branch:
8015 tmp = xreg;
8016 xreg = yreg;
8017 yreg = tmp;
8018
8019 do_branch:
8020 macro_build (NULL, s, "x,y", xreg, yreg);
8021 macro_build (&offset_expr, s2, "p");
8022 break;
8023
8024 case M_BEQ_I:
8025 s = "cmpi";
8026 s2 = "bteqz";
8027 s3 = "x,U";
8028 goto do_branch_i;
8029 case M_BNE_I:
8030 s = "cmpi";
8031 s2 = "btnez";
8032 s3 = "x,U";
8033 goto do_branch_i;
8034 case M_BLT_I:
8035 s = "slti";
8036 s2 = "btnez";
8037 s3 = "x,8";
8038 goto do_branch_i;
8039 case M_BLTU_I:
8040 s = "sltiu";
8041 s2 = "btnez";
8042 s3 = "x,8";
8043 goto do_branch_i;
8044 case M_BLE_I:
8045 s = "slti";
8046 s2 = "btnez";
8047 s3 = "x,8";
8048 goto do_addone_branch_i;
8049 case M_BLEU_I:
8050 s = "sltiu";
8051 s2 = "btnez";
8052 s3 = "x,8";
8053 goto do_addone_branch_i;
8054 case M_BGE_I:
8055 s = "slti";
8056 s2 = "bteqz";
8057 s3 = "x,8";
8058 goto do_branch_i;
8059 case M_BGEU_I:
8060 s = "sltiu";
8061 s2 = "bteqz";
8062 s3 = "x,8";
8063 goto do_branch_i;
8064 case M_BGT_I:
8065 s = "slti";
8066 s2 = "bteqz";
8067 s3 = "x,8";
8068 goto do_addone_branch_i;
8069 case M_BGTU_I:
8070 s = "sltiu";
8071 s2 = "bteqz";
8072 s3 = "x,8";
8073
8074 do_addone_branch_i:
8075 if (imm_expr.X_op != O_constant)
8076 as_bad (_("Unsupported large constant"));
8077 ++imm_expr.X_add_number;
8078
8079 do_branch_i:
8080 macro_build (&imm_expr, s, s3, xreg);
8081 macro_build (&offset_expr, s2, "p");
8082 break;
8083
8084 case M_ABS:
8085 expr1.X_add_number = 0;
8086 macro_build (&expr1, "slti", "x,8", yreg);
8087 if (xreg != yreg)
8088 move_register (xreg, yreg);
8089 expr1.X_add_number = 2;
8090 macro_build (&expr1, "bteqz", "p");
8091 macro_build (NULL, "neg", "x,w", xreg, xreg);
8092 }
8093 }
8094
8095 /* For consistency checking, verify that all bits are specified either
8096 by the match/mask part of the instruction definition, or by the
8097 operand list. */
8098 static int
8099 validate_mips_insn (const struct mips_opcode *opc)
8100 {
8101 const char *p = opc->args;
8102 char c;
8103 unsigned long used_bits = opc->mask;
8104
8105 if ((used_bits & opc->match) != opc->match)
8106 {
8107 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8108 opc->name, opc->args);
8109 return 0;
8110 }
8111 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8112 while (*p)
8113 switch (c = *p++)
8114 {
8115 case ',': break;
8116 case '(': break;
8117 case ')': break;
8118 case '+':
8119 switch (c = *p++)
8120 {
8121 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8122 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8123 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8124 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8125 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8126 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8127 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8128 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8129 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8130 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8131 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8132 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8133 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8134 case 'I': break;
8135 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8136 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8137 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8138 default:
8139 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8140 c, opc->name, opc->args);
8141 return 0;
8142 }
8143 break;
8144 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8145 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8146 case 'A': break;
8147 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8148 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8149 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8150 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8151 case 'F': break;
8152 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8153 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8154 case 'I': break;
8155 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8156 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8157 case 'L': break;
8158 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8159 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8160 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8161 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8162 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8163 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8164 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8165 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8166 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8167 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8168 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8169 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8170 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8171 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8172 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8173 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8174 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8175 case 'f': break;
8176 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8177 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8178 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8179 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8180 case 'l': break;
8181 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8182 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8183 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8184 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8185 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8186 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8187 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8188 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8189 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8190 case 'x': break;
8191 case 'z': break;
8192 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8193 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8194 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8195 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8196 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8197 case '[': break;
8198 case ']': break;
8199 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8200 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8201 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8202 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8203 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8204 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8205 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8206 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8207 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8208 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8209 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8210 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8211 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8212 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8213 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8214 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8215 default:
8216 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8217 c, opc->name, opc->args);
8218 return 0;
8219 }
8220 #undef USE_BITS
8221 if (used_bits != 0xffffffff)
8222 {
8223 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8224 ~used_bits & 0xffffffff, opc->name, opc->args);
8225 return 0;
8226 }
8227 return 1;
8228 }
8229
8230 /* UDI immediates. */
8231 struct mips_immed {
8232 char type;
8233 unsigned int shift;
8234 unsigned long mask;
8235 const char * desc;
8236 };
8237
8238 static const struct mips_immed mips_immed[] = {
8239 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8240 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8241 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8242 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8243 { 0,0,0,0 }
8244 };
8245
8246 /* Check whether an odd floating-point register is allowed. */
8247 static int
8248 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8249 {
8250 const char *s = insn->name;
8251
8252 if (insn->pinfo == INSN_MACRO)
8253 /* Let a macro pass, we'll catch it later when it is expanded. */
8254 return 1;
8255
8256 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8257 {
8258 /* Allow odd registers for single-precision ops. */
8259 switch (insn->pinfo & (FP_S | FP_D))
8260 {
8261 case FP_S:
8262 case 0:
8263 return 1; /* both single precision - ok */
8264 case FP_D:
8265 return 0; /* both double precision - fail */
8266 default:
8267 break;
8268 }
8269
8270 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8271 s = strchr (insn->name, '.');
8272 if (argnum == 2)
8273 s = s != NULL ? strchr (s + 1, '.') : NULL;
8274 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8275 }
8276
8277 /* Single-precision coprocessor loads and moves are OK too. */
8278 if ((insn->pinfo & FP_S)
8279 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8280 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8281 return 1;
8282
8283 return 0;
8284 }
8285
8286 /* This routine assembles an instruction into its binary format. As a
8287 side effect, it sets one of the global variables imm_reloc or
8288 offset_reloc to the type of relocation to do if one of the operands
8289 is an address expression. */
8290
8291 static void
8292 mips_ip (char *str, struct mips_cl_insn *ip)
8293 {
8294 char *s;
8295 const char *args;
8296 char c = 0;
8297 struct mips_opcode *insn;
8298 char *argsStart;
8299 unsigned int regno;
8300 unsigned int lastregno = 0;
8301 unsigned int lastpos = 0;
8302 unsigned int limlo, limhi;
8303 char *s_reset;
8304 char save_c = 0;
8305 offsetT min_range, max_range;
8306 int argnum;
8307 unsigned int rtype;
8308
8309 insn_error = NULL;
8310
8311 /* If the instruction contains a '.', we first try to match an instruction
8312 including the '.'. Then we try again without the '.'. */
8313 insn = NULL;
8314 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8315 continue;
8316
8317 /* If we stopped on whitespace, then replace the whitespace with null for
8318 the call to hash_find. Save the character we replaced just in case we
8319 have to re-parse the instruction. */
8320 if (ISSPACE (*s))
8321 {
8322 save_c = *s;
8323 *s++ = '\0';
8324 }
8325
8326 insn = (struct mips_opcode *) hash_find (op_hash, str);
8327
8328 /* If we didn't find the instruction in the opcode table, try again, but
8329 this time with just the instruction up to, but not including the
8330 first '.'. */
8331 if (insn == NULL)
8332 {
8333 /* Restore the character we overwrite above (if any). */
8334 if (save_c)
8335 *(--s) = save_c;
8336
8337 /* Scan up to the first '.' or whitespace. */
8338 for (s = str;
8339 *s != '\0' && *s != '.' && !ISSPACE (*s);
8340 ++s)
8341 continue;
8342
8343 /* If we did not find a '.', then we can quit now. */
8344 if (*s != '.')
8345 {
8346 insn_error = "unrecognized opcode";
8347 return;
8348 }
8349
8350 /* Lookup the instruction in the hash table. */
8351 *s++ = '\0';
8352 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8353 {
8354 insn_error = "unrecognized opcode";
8355 return;
8356 }
8357 }
8358
8359 argsStart = s;
8360 for (;;)
8361 {
8362 bfd_boolean ok;
8363
8364 assert (strcmp (insn->name, str) == 0);
8365
8366 if (OPCODE_IS_MEMBER (insn,
8367 (mips_opts.isa
8368 /* We don't check for mips_opts.mips16 here since
8369 we want to allow jalx if -mips16 was specified
8370 on the command line. */
8371 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8372 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8373 | (mips_opts.ase_dsp ? INSN_DSP : 0)
8374 | (mips_opts.ase_mt ? INSN_MT : 0)
8375 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
8376 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
8377 mips_opts.arch))
8378 ok = TRUE;
8379 else
8380 ok = FALSE;
8381
8382 if (insn->pinfo != INSN_MACRO)
8383 {
8384 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8385 ok = FALSE;
8386 }
8387
8388 if (! ok)
8389 {
8390 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8391 && strcmp (insn->name, insn[1].name) == 0)
8392 {
8393 ++insn;
8394 continue;
8395 }
8396 else
8397 {
8398 if (!insn_error)
8399 {
8400 static char buf[100];
8401 sprintf (buf,
8402 _("opcode not supported on this processor: %s (%s)"),
8403 mips_cpu_info_from_arch (mips_opts.arch)->name,
8404 mips_cpu_info_from_isa (mips_opts.isa)->name);
8405 insn_error = buf;
8406 }
8407 if (save_c)
8408 *(--s) = save_c;
8409 return;
8410 }
8411 }
8412
8413 create_insn (ip, insn);
8414 insn_error = NULL;
8415 argnum = 1;
8416 for (args = insn->args;; ++args)
8417 {
8418 int is_mdmx;
8419
8420 s += strspn (s, " \t");
8421 is_mdmx = 0;
8422 switch (*args)
8423 {
8424 case '\0': /* end of args */
8425 if (*s == '\0')
8426 return;
8427 break;
8428
8429 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8430 my_getExpression (&imm_expr, s);
8431 check_absolute_expr (ip, &imm_expr);
8432 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8433 {
8434 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8435 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8436 }
8437 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8438 imm_expr.X_op = O_absent;
8439 s = expr_end;
8440 continue;
8441
8442 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8443 my_getExpression (&imm_expr, s);
8444 check_absolute_expr (ip, &imm_expr);
8445 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8446 {
8447 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8448 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8449 }
8450 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8451 imm_expr.X_op = O_absent;
8452 s = expr_end;
8453 continue;
8454
8455 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8456 my_getExpression (&imm_expr, s);
8457 check_absolute_expr (ip, &imm_expr);
8458 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8459 {
8460 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8461 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8462 }
8463 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8464 imm_expr.X_op = O_absent;
8465 s = expr_end;
8466 continue;
8467
8468 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8469 my_getExpression (&imm_expr, s);
8470 check_absolute_expr (ip, &imm_expr);
8471 if (imm_expr.X_add_number & ~OP_MASK_RS)
8472 {
8473 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8474 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8475 }
8476 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8477 imm_expr.X_op = O_absent;
8478 s = expr_end;
8479 continue;
8480
8481 case '7': /* four dsp accumulators in bits 11,12 */
8482 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8483 s[3] >= '0' && s[3] <= '3')
8484 {
8485 regno = s[3] - '0';
8486 s += 4;
8487 INSERT_OPERAND (DSPACC, *ip, regno);
8488 continue;
8489 }
8490 else
8491 as_bad (_("Invalid dsp acc register"));
8492 break;
8493
8494 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8495 my_getExpression (&imm_expr, s);
8496 check_absolute_expr (ip, &imm_expr);
8497 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8498 {
8499 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8500 OP_MASK_WRDSP,
8501 (unsigned long) imm_expr.X_add_number);
8502 }
8503 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8504 imm_expr.X_op = O_absent;
8505 s = expr_end;
8506 continue;
8507
8508 case '9': /* four dsp accumulators in bits 21,22 */
8509 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8510 s[3] >= '0' && s[3] <= '3')
8511 {
8512 regno = s[3] - '0';
8513 s += 4;
8514 INSERT_OPERAND (DSPACC_S, *ip, regno);
8515 continue;
8516 }
8517 else
8518 as_bad (_("Invalid dsp acc register"));
8519 break;
8520
8521 case '0': /* dsp 6-bit signed immediate in bit 20 */
8522 my_getExpression (&imm_expr, s);
8523 check_absolute_expr (ip, &imm_expr);
8524 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8525 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8526 if (imm_expr.X_add_number < min_range ||
8527 imm_expr.X_add_number > max_range)
8528 {
8529 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8530 (long) min_range, (long) max_range,
8531 (long) imm_expr.X_add_number);
8532 }
8533 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8534 imm_expr.X_op = O_absent;
8535 s = expr_end;
8536 continue;
8537
8538 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8539 my_getExpression (&imm_expr, s);
8540 check_absolute_expr (ip, &imm_expr);
8541 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8542 {
8543 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8544 OP_MASK_RDDSP,
8545 (unsigned long) imm_expr.X_add_number);
8546 }
8547 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8548 imm_expr.X_op = O_absent;
8549 s = expr_end;
8550 continue;
8551
8552 case ':': /* dsp 7-bit signed immediate in bit 19 */
8553 my_getExpression (&imm_expr, s);
8554 check_absolute_expr (ip, &imm_expr);
8555 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8556 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8557 if (imm_expr.X_add_number < min_range ||
8558 imm_expr.X_add_number > max_range)
8559 {
8560 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8561 (long) min_range, (long) max_range,
8562 (long) imm_expr.X_add_number);
8563 }
8564 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8565 imm_expr.X_op = O_absent;
8566 s = expr_end;
8567 continue;
8568
8569 case '@': /* dsp 10-bit signed immediate in bit 16 */
8570 my_getExpression (&imm_expr, s);
8571 check_absolute_expr (ip, &imm_expr);
8572 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8573 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8574 if (imm_expr.X_add_number < min_range ||
8575 imm_expr.X_add_number > max_range)
8576 {
8577 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8578 (long) min_range, (long) max_range,
8579 (long) imm_expr.X_add_number);
8580 }
8581 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8582 imm_expr.X_op = O_absent;
8583 s = expr_end;
8584 continue;
8585
8586 case '!': /* MT usermode flag bit. */
8587 my_getExpression (&imm_expr, s);
8588 check_absolute_expr (ip, &imm_expr);
8589 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8590 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8591 (unsigned long) imm_expr.X_add_number);
8592 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8593 imm_expr.X_op = O_absent;
8594 s = expr_end;
8595 continue;
8596
8597 case '$': /* MT load high flag bit. */
8598 my_getExpression (&imm_expr, s);
8599 check_absolute_expr (ip, &imm_expr);
8600 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8601 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8602 (unsigned long) imm_expr.X_add_number);
8603 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8604 imm_expr.X_op = O_absent;
8605 s = expr_end;
8606 continue;
8607
8608 case '*': /* four dsp accumulators in bits 18,19 */
8609 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8610 s[3] >= '0' && s[3] <= '3')
8611 {
8612 regno = s[3] - '0';
8613 s += 4;
8614 INSERT_OPERAND (MTACC_T, *ip, regno);
8615 continue;
8616 }
8617 else
8618 as_bad (_("Invalid dsp/smartmips acc register"));
8619 break;
8620
8621 case '&': /* four dsp accumulators in bits 13,14 */
8622 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8623 s[3] >= '0' && s[3] <= '3')
8624 {
8625 regno = s[3] - '0';
8626 s += 4;
8627 INSERT_OPERAND (MTACC_D, *ip, regno);
8628 continue;
8629 }
8630 else
8631 as_bad (_("Invalid dsp/smartmips acc register"));
8632 break;
8633
8634 case ',':
8635 if (*s++ == *args)
8636 continue;
8637 s--;
8638 switch (*++args)
8639 {
8640 case 'r':
8641 case 'v':
8642 INSERT_OPERAND (RS, *ip, lastregno);
8643 continue;
8644
8645 case 'w':
8646 INSERT_OPERAND (RT, *ip, lastregno);
8647 continue;
8648
8649 case 'W':
8650 INSERT_OPERAND (FT, *ip, lastregno);
8651 continue;
8652
8653 case 'V':
8654 INSERT_OPERAND (FS, *ip, lastregno);
8655 continue;
8656 }
8657 break;
8658
8659 case '(':
8660 /* Handle optional base register.
8661 Either the base register is omitted or
8662 we must have a left paren. */
8663 /* This is dependent on the next operand specifier
8664 is a base register specification. */
8665 assert (args[1] == 'b' || args[1] == '5'
8666 || args[1] == '-' || args[1] == '4');
8667 if (*s == '\0')
8668 return;
8669
8670 case ')': /* these must match exactly */
8671 case '[':
8672 case ']':
8673 if (*s++ == *args)
8674 continue;
8675 break;
8676
8677 case '+': /* Opcode extension character. */
8678 switch (*++args)
8679 {
8680 case '1': /* UDI immediates. */
8681 case '2':
8682 case '3':
8683 case '4':
8684 {
8685 const struct mips_immed *imm = mips_immed;
8686
8687 while (imm->type && imm->type != *args)
8688 ++imm;
8689 if (! imm->type)
8690 internalError ();
8691 my_getExpression (&imm_expr, s);
8692 check_absolute_expr (ip, &imm_expr);
8693 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
8694 {
8695 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8696 imm->desc ? imm->desc : ip->insn_mo->name,
8697 (unsigned long) imm_expr.X_add_number,
8698 (unsigned long) imm_expr.X_add_number);
8699 imm_expr.X_add_number &= imm->mask;
8700 }
8701 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8702 << imm->shift);
8703 imm_expr.X_op = O_absent;
8704 s = expr_end;
8705 }
8706 continue;
8707
8708 case 'A': /* ins/ext position, becomes LSB. */
8709 limlo = 0;
8710 limhi = 31;
8711 goto do_lsb;
8712 case 'E':
8713 limlo = 32;
8714 limhi = 63;
8715 goto do_lsb;
8716 do_lsb:
8717 my_getExpression (&imm_expr, s);
8718 check_absolute_expr (ip, &imm_expr);
8719 if ((unsigned long) imm_expr.X_add_number < limlo
8720 || (unsigned long) imm_expr.X_add_number > limhi)
8721 {
8722 as_bad (_("Improper position (%lu)"),
8723 (unsigned long) imm_expr.X_add_number);
8724 imm_expr.X_add_number = limlo;
8725 }
8726 lastpos = imm_expr.X_add_number;
8727 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8728 imm_expr.X_op = O_absent;
8729 s = expr_end;
8730 continue;
8731
8732 case 'B': /* ins size, becomes MSB. */
8733 limlo = 1;
8734 limhi = 32;
8735 goto do_msb;
8736 case 'F':
8737 limlo = 33;
8738 limhi = 64;
8739 goto do_msb;
8740 do_msb:
8741 my_getExpression (&imm_expr, s);
8742 check_absolute_expr (ip, &imm_expr);
8743 /* Check for negative input so that small negative numbers
8744 will not succeed incorrectly. The checks against
8745 (pos+size) transitively check "size" itself,
8746 assuming that "pos" is reasonable. */
8747 if ((long) imm_expr.X_add_number < 0
8748 || ((unsigned long) imm_expr.X_add_number
8749 + lastpos) < limlo
8750 || ((unsigned long) imm_expr.X_add_number
8751 + lastpos) > limhi)
8752 {
8753 as_bad (_("Improper insert size (%lu, position %lu)"),
8754 (unsigned long) imm_expr.X_add_number,
8755 (unsigned long) lastpos);
8756 imm_expr.X_add_number = limlo - lastpos;
8757 }
8758 INSERT_OPERAND (INSMSB, *ip,
8759 lastpos + imm_expr.X_add_number - 1);
8760 imm_expr.X_op = O_absent;
8761 s = expr_end;
8762 continue;
8763
8764 case 'C': /* ext size, becomes MSBD. */
8765 limlo = 1;
8766 limhi = 32;
8767 goto do_msbd;
8768 case 'G':
8769 limlo = 33;
8770 limhi = 64;
8771 goto do_msbd;
8772 case 'H':
8773 limlo = 33;
8774 limhi = 64;
8775 goto do_msbd;
8776 do_msbd:
8777 my_getExpression (&imm_expr, s);
8778 check_absolute_expr (ip, &imm_expr);
8779 /* Check for negative input so that small negative numbers
8780 will not succeed incorrectly. The checks against
8781 (pos+size) transitively check "size" itself,
8782 assuming that "pos" is reasonable. */
8783 if ((long) imm_expr.X_add_number < 0
8784 || ((unsigned long) imm_expr.X_add_number
8785 + lastpos) < limlo
8786 || ((unsigned long) imm_expr.X_add_number
8787 + lastpos) > limhi)
8788 {
8789 as_bad (_("Improper extract size (%lu, position %lu)"),
8790 (unsigned long) imm_expr.X_add_number,
8791 (unsigned long) lastpos);
8792 imm_expr.X_add_number = limlo - lastpos;
8793 }
8794 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
8795 imm_expr.X_op = O_absent;
8796 s = expr_end;
8797 continue;
8798
8799 case 'D':
8800 /* +D is for disassembly only; never match. */
8801 break;
8802
8803 case 'I':
8804 /* "+I" is like "I", except that imm2_expr is used. */
8805 my_getExpression (&imm2_expr, s);
8806 if (imm2_expr.X_op != O_big
8807 && imm2_expr.X_op != O_constant)
8808 insn_error = _("absolute expression required");
8809 if (HAVE_32BIT_GPRS)
8810 normalize_constant_expr (&imm2_expr);
8811 s = expr_end;
8812 continue;
8813
8814 case 'T': /* Coprocessor register. */
8815 /* +T is for disassembly only; never match. */
8816 break;
8817
8818 case 't': /* Coprocessor register number. */
8819 if (s[0] == '$' && ISDIGIT (s[1]))
8820 {
8821 ++s;
8822 regno = 0;
8823 do
8824 {
8825 regno *= 10;
8826 regno += *s - '0';
8827 ++s;
8828 }
8829 while (ISDIGIT (*s));
8830 if (regno > 31)
8831 as_bad (_("Invalid register number (%d)"), regno);
8832 else
8833 {
8834 INSERT_OPERAND (RT, *ip, regno);
8835 continue;
8836 }
8837 }
8838 else
8839 as_bad (_("Invalid coprocessor 0 register number"));
8840 break;
8841
8842 default:
8843 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8844 *args, insn->name, insn->args);
8845 /* Further processing is fruitless. */
8846 return;
8847 }
8848 break;
8849
8850 case '<': /* must be at least one digit */
8851 /*
8852 * According to the manual, if the shift amount is greater
8853 * than 31 or less than 0, then the shift amount should be
8854 * mod 32. In reality the mips assembler issues an error.
8855 * We issue a warning and mask out all but the low 5 bits.
8856 */
8857 my_getExpression (&imm_expr, s);
8858 check_absolute_expr (ip, &imm_expr);
8859 if ((unsigned long) imm_expr.X_add_number > 31)
8860 as_warn (_("Improper shift amount (%lu)"),
8861 (unsigned long) imm_expr.X_add_number);
8862 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8863 imm_expr.X_op = O_absent;
8864 s = expr_end;
8865 continue;
8866
8867 case '>': /* shift amount minus 32 */
8868 my_getExpression (&imm_expr, s);
8869 check_absolute_expr (ip, &imm_expr);
8870 if ((unsigned long) imm_expr.X_add_number < 32
8871 || (unsigned long) imm_expr.X_add_number > 63)
8872 break;
8873 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
8874 imm_expr.X_op = O_absent;
8875 s = expr_end;
8876 continue;
8877
8878 case 'k': /* cache code */
8879 case 'h': /* prefx code */
8880 my_getExpression (&imm_expr, s);
8881 check_absolute_expr (ip, &imm_expr);
8882 if ((unsigned long) imm_expr.X_add_number > 31)
8883 as_warn (_("Invalid value for `%s' (%lu)"),
8884 ip->insn_mo->name,
8885 (unsigned long) imm_expr.X_add_number);
8886 if (*args == 'k')
8887 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
8888 else
8889 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
8890 imm_expr.X_op = O_absent;
8891 s = expr_end;
8892 continue;
8893
8894 case 'c': /* break code */
8895 my_getExpression (&imm_expr, s);
8896 check_absolute_expr (ip, &imm_expr);
8897 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
8898 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8899 ip->insn_mo->name,
8900 (unsigned long) imm_expr.X_add_number);
8901 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
8902 imm_expr.X_op = O_absent;
8903 s = expr_end;
8904 continue;
8905
8906 case 'q': /* lower break code */
8907 my_getExpression (&imm_expr, s);
8908 check_absolute_expr (ip, &imm_expr);
8909 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
8910 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
8911 ip->insn_mo->name,
8912 (unsigned long) imm_expr.X_add_number);
8913 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
8914 imm_expr.X_op = O_absent;
8915 s = expr_end;
8916 continue;
8917
8918 case 'B': /* 20-bit syscall/break code. */
8919 my_getExpression (&imm_expr, s);
8920 check_absolute_expr (ip, &imm_expr);
8921 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8922 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
8923 ip->insn_mo->name,
8924 (unsigned long) imm_expr.X_add_number);
8925 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
8926 imm_expr.X_op = O_absent;
8927 s = expr_end;
8928 continue;
8929
8930 case 'C': /* Coprocessor code */
8931 my_getExpression (&imm_expr, s);
8932 check_absolute_expr (ip, &imm_expr);
8933 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
8934 {
8935 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8936 (unsigned long) imm_expr.X_add_number);
8937 imm_expr.X_add_number &= OP_MASK_COPZ;
8938 }
8939 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
8940 imm_expr.X_op = O_absent;
8941 s = expr_end;
8942 continue;
8943
8944 case 'J': /* 19-bit wait code. */
8945 my_getExpression (&imm_expr, s);
8946 check_absolute_expr (ip, &imm_expr);
8947 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8948 {
8949 as_warn (_("Illegal 19-bit code (%lu)"),
8950 (unsigned long) imm_expr.X_add_number);
8951 imm_expr.X_add_number &= OP_MASK_CODE19;
8952 }
8953 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
8954 imm_expr.X_op = O_absent;
8955 s = expr_end;
8956 continue;
8957
8958 case 'P': /* Performance register. */
8959 my_getExpression (&imm_expr, s);
8960 check_absolute_expr (ip, &imm_expr);
8961 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8962 as_warn (_("Invalid performance register (%lu)"),
8963 (unsigned long) imm_expr.X_add_number);
8964 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
8965 imm_expr.X_op = O_absent;
8966 s = expr_end;
8967 continue;
8968
8969 case 'G': /* Coprocessor destination register. */
8970 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
8971 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
8972 else
8973 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
8974 INSERT_OPERAND (RD, *ip, regno);
8975 if (ok)
8976 {
8977 lastregno = regno;
8978 continue;
8979 }
8980 else
8981 break;
8982
8983 case 'b': /* base register */
8984 case 'd': /* destination register */
8985 case 's': /* source register */
8986 case 't': /* target register */
8987 case 'r': /* both target and source */
8988 case 'v': /* both dest and source */
8989 case 'w': /* both dest and target */
8990 case 'E': /* coprocessor target register */
8991 case 'K': /* 'rdhwr' destination register */
8992 case 'x': /* ignore register name */
8993 case 'z': /* must be zero register */
8994 case 'U': /* destination register (clo/clz). */
8995 case 'g': /* coprocessor destination register */
8996 s_reset = s;
8997 if (*args == 'E' || *args == 'K')
8998 ok = reg_lookup (&s, RTYPE_NUM, &regno);
8999 else
9000 {
9001 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9002 if (regno == AT && ! mips_opts.noat)
9003 as_warn ("Used $at without \".set noat\"");
9004 }
9005 if (ok)
9006 {
9007 c = *args;
9008 if (*s == ' ')
9009 ++s;
9010 if (args[1] != *s)
9011 {
9012 if (c == 'r' || c == 'v' || c == 'w')
9013 {
9014 regno = lastregno;
9015 s = s_reset;
9016 ++args;
9017 }
9018 }
9019 /* 'z' only matches $0. */
9020 if (c == 'z' && regno != 0)
9021 break;
9022
9023 /* Now that we have assembled one operand, we use the args string
9024 * to figure out where it goes in the instruction. */
9025 switch (c)
9026 {
9027 case 'r':
9028 case 's':
9029 case 'v':
9030 case 'b':
9031 INSERT_OPERAND (RS, *ip, regno);
9032 break;
9033 case 'd':
9034 case 'G':
9035 case 'K':
9036 case 'g':
9037 INSERT_OPERAND (RD, *ip, regno);
9038 break;
9039 case 'U':
9040 INSERT_OPERAND (RD, *ip, regno);
9041 INSERT_OPERAND (RT, *ip, regno);
9042 break;
9043 case 'w':
9044 case 't':
9045 case 'E':
9046 INSERT_OPERAND (RT, *ip, regno);
9047 break;
9048 case 'x':
9049 /* This case exists because on the r3000 trunc
9050 expands into a macro which requires a gp
9051 register. On the r6000 or r4000 it is
9052 assembled into a single instruction which
9053 ignores the register. Thus the insn version
9054 is MIPS_ISA2 and uses 'x', and the macro
9055 version is MIPS_ISA1 and uses 't'. */
9056 break;
9057 case 'z':
9058 /* This case is for the div instruction, which
9059 acts differently if the destination argument
9060 is $0. This only matches $0, and is checked
9061 outside the switch. */
9062 break;
9063 case 'D':
9064 /* Itbl operand; not yet implemented. FIXME ?? */
9065 break;
9066 /* What about all other operands like 'i', which
9067 can be specified in the opcode table? */
9068 }
9069 lastregno = regno;
9070 continue;
9071 }
9072 switch (*args++)
9073 {
9074 case 'r':
9075 case 'v':
9076 INSERT_OPERAND (RS, *ip, lastregno);
9077 continue;
9078 case 'w':
9079 INSERT_OPERAND (RT, *ip, lastregno);
9080 continue;
9081 }
9082 break;
9083
9084 case 'O': /* MDMX alignment immediate constant. */
9085 my_getExpression (&imm_expr, s);
9086 check_absolute_expr (ip, &imm_expr);
9087 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9088 as_warn ("Improper align amount (%ld), using low bits",
9089 (long) imm_expr.X_add_number);
9090 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9091 imm_expr.X_op = O_absent;
9092 s = expr_end;
9093 continue;
9094
9095 case 'Q': /* MDMX vector, element sel, or const. */
9096 if (s[0] != '$')
9097 {
9098 /* MDMX Immediate. */
9099 my_getExpression (&imm_expr, s);
9100 check_absolute_expr (ip, &imm_expr);
9101 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9102 as_warn (_("Invalid MDMX Immediate (%ld)"),
9103 (long) imm_expr.X_add_number);
9104 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9105 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9106 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9107 else
9108 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9109 imm_expr.X_op = O_absent;
9110 s = expr_end;
9111 continue;
9112 }
9113 /* Not MDMX Immediate. Fall through. */
9114 case 'X': /* MDMX destination register. */
9115 case 'Y': /* MDMX source register. */
9116 case 'Z': /* MDMX target register. */
9117 is_mdmx = 1;
9118 case 'D': /* floating point destination register */
9119 case 'S': /* floating point source register */
9120 case 'T': /* floating point target register */
9121 case 'R': /* floating point source register */
9122 case 'V':
9123 case 'W':
9124 rtype = RTYPE_FPU;
9125 if (is_mdmx
9126 || (mips_opts.ase_mdmx
9127 && (ip->insn_mo->pinfo & FP_D)
9128 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9129 | INSN_COPROC_MEMORY_DELAY
9130 | INSN_LOAD_COPROC_DELAY
9131 | INSN_LOAD_MEMORY_DELAY
9132 | INSN_STORE_MEMORY))))
9133 rtype |= RTYPE_VEC;
9134 s_reset = s;
9135 if (reg_lookup (&s, rtype, &regno))
9136 {
9137 if ((regno & 1) != 0
9138 && HAVE_32BIT_FPRS
9139 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9140 as_warn (_("Float register should be even, was %d"),
9141 regno);
9142
9143 c = *args;
9144 if (*s == ' ')
9145 ++s;
9146 if (args[1] != *s)
9147 {
9148 if (c == 'V' || c == 'W')
9149 {
9150 regno = lastregno;
9151 s = s_reset;
9152 ++args;
9153 }
9154 }
9155 switch (c)
9156 {
9157 case 'D':
9158 case 'X':
9159 INSERT_OPERAND (FD, *ip, regno);
9160 break;
9161 case 'V':
9162 case 'S':
9163 case 'Y':
9164 INSERT_OPERAND (FS, *ip, regno);
9165 break;
9166 case 'Q':
9167 /* This is like 'Z', but also needs to fix the MDMX
9168 vector/scalar select bits. Note that the
9169 scalar immediate case is handled above. */
9170 if (*s == '[')
9171 {
9172 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9173 int max_el = (is_qh ? 3 : 7);
9174 s++;
9175 my_getExpression(&imm_expr, s);
9176 check_absolute_expr (ip, &imm_expr);
9177 s = expr_end;
9178 if (imm_expr.X_add_number > max_el)
9179 as_bad(_("Bad element selector %ld"),
9180 (long) imm_expr.X_add_number);
9181 imm_expr.X_add_number &= max_el;
9182 ip->insn_opcode |= (imm_expr.X_add_number
9183 << (OP_SH_VSEL +
9184 (is_qh ? 2 : 1)));
9185 imm_expr.X_op = O_absent;
9186 if (*s != ']')
9187 as_warn(_("Expecting ']' found '%s'"), s);
9188 else
9189 s++;
9190 }
9191 else
9192 {
9193 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9194 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9195 << OP_SH_VSEL);
9196 else
9197 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9198 OP_SH_VSEL);
9199 }
9200 /* Fall through */
9201 case 'W':
9202 case 'T':
9203 case 'Z':
9204 INSERT_OPERAND (FT, *ip, regno);
9205 break;
9206 case 'R':
9207 INSERT_OPERAND (FR, *ip, regno);
9208 break;
9209 }
9210 lastregno = regno;
9211 continue;
9212 }
9213
9214 switch (*args++)
9215 {
9216 case 'V':
9217 INSERT_OPERAND (FS, *ip, lastregno);
9218 continue;
9219 case 'W':
9220 INSERT_OPERAND (FT, *ip, lastregno);
9221 continue;
9222 }
9223 break;
9224
9225 case 'I':
9226 my_getExpression (&imm_expr, s);
9227 if (imm_expr.X_op != O_big
9228 && imm_expr.X_op != O_constant)
9229 insn_error = _("absolute expression required");
9230 if (HAVE_32BIT_GPRS)
9231 normalize_constant_expr (&imm_expr);
9232 s = expr_end;
9233 continue;
9234
9235 case 'A':
9236 my_getExpression (&offset_expr, s);
9237 normalize_address_expr (&offset_expr);
9238 *imm_reloc = BFD_RELOC_32;
9239 s = expr_end;
9240 continue;
9241
9242 case 'F':
9243 case 'L':
9244 case 'f':
9245 case 'l':
9246 {
9247 int f64;
9248 int using_gprs;
9249 char *save_in;
9250 char *err;
9251 unsigned char temp[8];
9252 int len;
9253 unsigned int length;
9254 segT seg;
9255 subsegT subseg;
9256 char *p;
9257
9258 /* These only appear as the last operand in an
9259 instruction, and every instruction that accepts
9260 them in any variant accepts them in all variants.
9261 This means we don't have to worry about backing out
9262 any changes if the instruction does not match.
9263
9264 The difference between them is the size of the
9265 floating point constant and where it goes. For 'F'
9266 and 'L' the constant is 64 bits; for 'f' and 'l' it
9267 is 32 bits. Where the constant is placed is based
9268 on how the MIPS assembler does things:
9269 F -- .rdata
9270 L -- .lit8
9271 f -- immediate value
9272 l -- .lit4
9273
9274 The .lit4 and .lit8 sections are only used if
9275 permitted by the -G argument.
9276
9277 The code below needs to know whether the target register
9278 is 32 or 64 bits wide. It relies on the fact 'f' and
9279 'F' are used with GPR-based instructions and 'l' and
9280 'L' are used with FPR-based instructions. */
9281
9282 f64 = *args == 'F' || *args == 'L';
9283 using_gprs = *args == 'F' || *args == 'f';
9284
9285 save_in = input_line_pointer;
9286 input_line_pointer = s;
9287 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9288 length = len;
9289 s = input_line_pointer;
9290 input_line_pointer = save_in;
9291 if (err != NULL && *err != '\0')
9292 {
9293 as_bad (_("Bad floating point constant: %s"), err);
9294 memset (temp, '\0', sizeof temp);
9295 length = f64 ? 8 : 4;
9296 }
9297
9298 assert (length == (unsigned) (f64 ? 8 : 4));
9299
9300 if (*args == 'f'
9301 || (*args == 'l'
9302 && (g_switch_value < 4
9303 || (temp[0] == 0 && temp[1] == 0)
9304 || (temp[2] == 0 && temp[3] == 0))))
9305 {
9306 imm_expr.X_op = O_constant;
9307 if (! target_big_endian)
9308 imm_expr.X_add_number = bfd_getl32 (temp);
9309 else
9310 imm_expr.X_add_number = bfd_getb32 (temp);
9311 }
9312 else if (length > 4
9313 && ! mips_disable_float_construction
9314 /* Constants can only be constructed in GPRs and
9315 copied to FPRs if the GPRs are at least as wide
9316 as the FPRs. Force the constant into memory if
9317 we are using 64-bit FPRs but the GPRs are only
9318 32 bits wide. */
9319 && (using_gprs
9320 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9321 && ((temp[0] == 0 && temp[1] == 0)
9322 || (temp[2] == 0 && temp[3] == 0))
9323 && ((temp[4] == 0 && temp[5] == 0)
9324 || (temp[6] == 0 && temp[7] == 0)))
9325 {
9326 /* The value is simple enough to load with a couple of
9327 instructions. If using 32-bit registers, set
9328 imm_expr to the high order 32 bits and offset_expr to
9329 the low order 32 bits. Otherwise, set imm_expr to
9330 the entire 64 bit constant. */
9331 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9332 {
9333 imm_expr.X_op = O_constant;
9334 offset_expr.X_op = O_constant;
9335 if (! target_big_endian)
9336 {
9337 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9338 offset_expr.X_add_number = bfd_getl32 (temp);
9339 }
9340 else
9341 {
9342 imm_expr.X_add_number = bfd_getb32 (temp);
9343 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9344 }
9345 if (offset_expr.X_add_number == 0)
9346 offset_expr.X_op = O_absent;
9347 }
9348 else if (sizeof (imm_expr.X_add_number) > 4)
9349 {
9350 imm_expr.X_op = O_constant;
9351 if (! target_big_endian)
9352 imm_expr.X_add_number = bfd_getl64 (temp);
9353 else
9354 imm_expr.X_add_number = bfd_getb64 (temp);
9355 }
9356 else
9357 {
9358 imm_expr.X_op = O_big;
9359 imm_expr.X_add_number = 4;
9360 if (! target_big_endian)
9361 {
9362 generic_bignum[0] = bfd_getl16 (temp);
9363 generic_bignum[1] = bfd_getl16 (temp + 2);
9364 generic_bignum[2] = bfd_getl16 (temp + 4);
9365 generic_bignum[3] = bfd_getl16 (temp + 6);
9366 }
9367 else
9368 {
9369 generic_bignum[0] = bfd_getb16 (temp + 6);
9370 generic_bignum[1] = bfd_getb16 (temp + 4);
9371 generic_bignum[2] = bfd_getb16 (temp + 2);
9372 generic_bignum[3] = bfd_getb16 (temp);
9373 }
9374 }
9375 }
9376 else
9377 {
9378 const char *newname;
9379 segT new_seg;
9380
9381 /* Switch to the right section. */
9382 seg = now_seg;
9383 subseg = now_subseg;
9384 switch (*args)
9385 {
9386 default: /* unused default case avoids warnings. */
9387 case 'L':
9388 newname = RDATA_SECTION_NAME;
9389 if (g_switch_value >= 8)
9390 newname = ".lit8";
9391 break;
9392 case 'F':
9393 newname = RDATA_SECTION_NAME;
9394 break;
9395 case 'l':
9396 assert (g_switch_value >= 4);
9397 newname = ".lit4";
9398 break;
9399 }
9400 new_seg = subseg_new (newname, (subsegT) 0);
9401 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9402 bfd_set_section_flags (stdoutput, new_seg,
9403 (SEC_ALLOC
9404 | SEC_LOAD
9405 | SEC_READONLY
9406 | SEC_DATA));
9407 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9408 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9409 && strcmp (TARGET_OS, "elf") != 0)
9410 record_alignment (new_seg, 4);
9411 else
9412 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9413 if (seg == now_seg)
9414 as_bad (_("Can't use floating point insn in this section"));
9415
9416 /* Set the argument to the current address in the
9417 section. */
9418 offset_expr.X_op = O_symbol;
9419 offset_expr.X_add_symbol =
9420 symbol_new ("L0\001", now_seg,
9421 (valueT) frag_now_fix (), frag_now);
9422 offset_expr.X_add_number = 0;
9423
9424 /* Put the floating point number into the section. */
9425 p = frag_more ((int) length);
9426 memcpy (p, temp, length);
9427
9428 /* Switch back to the original section. */
9429 subseg_set (seg, subseg);
9430 }
9431 }
9432 continue;
9433
9434 case 'i': /* 16 bit unsigned immediate */
9435 case 'j': /* 16 bit signed immediate */
9436 *imm_reloc = BFD_RELOC_LO16;
9437 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9438 {
9439 int more;
9440 offsetT minval, maxval;
9441
9442 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9443 && strcmp (insn->name, insn[1].name) == 0);
9444
9445 /* If the expression was written as an unsigned number,
9446 only treat it as signed if there are no more
9447 alternatives. */
9448 if (more
9449 && *args == 'j'
9450 && sizeof (imm_expr.X_add_number) <= 4
9451 && imm_expr.X_op == O_constant
9452 && imm_expr.X_add_number < 0
9453 && imm_expr.X_unsigned
9454 && HAVE_64BIT_GPRS)
9455 break;
9456
9457 /* For compatibility with older assemblers, we accept
9458 0x8000-0xffff as signed 16-bit numbers when only
9459 signed numbers are allowed. */
9460 if (*args == 'i')
9461 minval = 0, maxval = 0xffff;
9462 else if (more)
9463 minval = -0x8000, maxval = 0x7fff;
9464 else
9465 minval = -0x8000, maxval = 0xffff;
9466
9467 if (imm_expr.X_op != O_constant
9468 || imm_expr.X_add_number < minval
9469 || imm_expr.X_add_number > maxval)
9470 {
9471 if (more)
9472 break;
9473 if (imm_expr.X_op == O_constant
9474 || imm_expr.X_op == O_big)
9475 as_bad (_("expression out of range"));
9476 }
9477 }
9478 s = expr_end;
9479 continue;
9480
9481 case 'o': /* 16 bit offset */
9482 /* Check whether there is only a single bracketed expression
9483 left. If so, it must be the base register and the
9484 constant must be zero. */
9485 if (*s == '(' && strchr (s + 1, '(') == 0)
9486 {
9487 offset_expr.X_op = O_constant;
9488 offset_expr.X_add_number = 0;
9489 continue;
9490 }
9491
9492 /* If this value won't fit into a 16 bit offset, then go
9493 find a macro that will generate the 32 bit offset
9494 code pattern. */
9495 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9496 && (offset_expr.X_op != O_constant
9497 || offset_expr.X_add_number >= 0x8000
9498 || offset_expr.X_add_number < -0x8000))
9499 break;
9500
9501 s = expr_end;
9502 continue;
9503
9504 case 'p': /* pc relative offset */
9505 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9506 my_getExpression (&offset_expr, s);
9507 s = expr_end;
9508 continue;
9509
9510 case 'u': /* upper 16 bits */
9511 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9512 && imm_expr.X_op == O_constant
9513 && (imm_expr.X_add_number < 0
9514 || imm_expr.X_add_number >= 0x10000))
9515 as_bad (_("lui expression not in range 0..65535"));
9516 s = expr_end;
9517 continue;
9518
9519 case 'a': /* 26 bit address */
9520 my_getExpression (&offset_expr, s);
9521 s = expr_end;
9522 *offset_reloc = BFD_RELOC_MIPS_JMP;
9523 continue;
9524
9525 case 'N': /* 3 bit branch condition code */
9526 case 'M': /* 3 bit compare condition code */
9527 rtype = RTYPE_CCC;
9528 if (ip->insn_mo->pinfo & (FP_D| FP_S))
9529 rtype |= RTYPE_FCC;
9530 if (!reg_lookup (&s, rtype, &regno))
9531 break;
9532 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9533 || strcmp(str + strlen(str) - 5, "any2f") == 0
9534 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9535 && (regno & 1) != 0)
9536 as_warn(_("Condition code register should be even for %s, was %d"),
9537 str, regno);
9538 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9539 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9540 && (regno & 3) != 0)
9541 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9542 str, regno);
9543 if (*args == 'N')
9544 INSERT_OPERAND (BCC, *ip, regno);
9545 else
9546 INSERT_OPERAND (CCC, *ip, regno);
9547 continue;
9548
9549 case 'H':
9550 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9551 s += 2;
9552 if (ISDIGIT (*s))
9553 {
9554 c = 0;
9555 do
9556 {
9557 c *= 10;
9558 c += *s - '0';
9559 ++s;
9560 }
9561 while (ISDIGIT (*s));
9562 }
9563 else
9564 c = 8; /* Invalid sel value. */
9565
9566 if (c > 7)
9567 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9568 ip->insn_opcode |= c;
9569 continue;
9570
9571 case 'e':
9572 /* Must be at least one digit. */
9573 my_getExpression (&imm_expr, s);
9574 check_absolute_expr (ip, &imm_expr);
9575
9576 if ((unsigned long) imm_expr.X_add_number
9577 > (unsigned long) OP_MASK_VECBYTE)
9578 {
9579 as_bad (_("bad byte vector index (%ld)"),
9580 (long) imm_expr.X_add_number);
9581 imm_expr.X_add_number = 0;
9582 }
9583
9584 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
9585 imm_expr.X_op = O_absent;
9586 s = expr_end;
9587 continue;
9588
9589 case '%':
9590 my_getExpression (&imm_expr, s);
9591 check_absolute_expr (ip, &imm_expr);
9592
9593 if ((unsigned long) imm_expr.X_add_number
9594 > (unsigned long) OP_MASK_VECALIGN)
9595 {
9596 as_bad (_("bad byte vector index (%ld)"),
9597 (long) imm_expr.X_add_number);
9598 imm_expr.X_add_number = 0;
9599 }
9600
9601 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
9602 imm_expr.X_op = O_absent;
9603 s = expr_end;
9604 continue;
9605
9606 default:
9607 as_bad (_("bad char = '%c'\n"), *args);
9608 internalError ();
9609 }
9610 break;
9611 }
9612 /* Args don't match. */
9613 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9614 !strcmp (insn->name, insn[1].name))
9615 {
9616 ++insn;
9617 s = argsStart;
9618 insn_error = _("illegal operands");
9619 continue;
9620 }
9621 if (save_c)
9622 *(--s) = save_c;
9623 insn_error = _("illegal operands");
9624 return;
9625 }
9626 }
9627
9628 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9629
9630 /* This routine assembles an instruction into its binary format when
9631 assembling for the mips16. As a side effect, it sets one of the
9632 global variables imm_reloc or offset_reloc to the type of
9633 relocation to do if one of the operands is an address expression.
9634 It also sets mips16_small and mips16_ext if the user explicitly
9635 requested a small or extended instruction. */
9636
9637 static void
9638 mips16_ip (char *str, struct mips_cl_insn *ip)
9639 {
9640 char *s;
9641 const char *args;
9642 struct mips_opcode *insn;
9643 char *argsstart;
9644 unsigned int regno;
9645 unsigned int lastregno = 0;
9646 char *s_reset;
9647 size_t i;
9648
9649 insn_error = NULL;
9650
9651 mips16_small = FALSE;
9652 mips16_ext = FALSE;
9653
9654 for (s = str; ISLOWER (*s); ++s)
9655 ;
9656 switch (*s)
9657 {
9658 case '\0':
9659 break;
9660
9661 case ' ':
9662 *s++ = '\0';
9663 break;
9664
9665 case '.':
9666 if (s[1] == 't' && s[2] == ' ')
9667 {
9668 *s = '\0';
9669 mips16_small = TRUE;
9670 s += 3;
9671 break;
9672 }
9673 else if (s[1] == 'e' && s[2] == ' ')
9674 {
9675 *s = '\0';
9676 mips16_ext = TRUE;
9677 s += 3;
9678 break;
9679 }
9680 /* Fall through. */
9681 default:
9682 insn_error = _("unknown opcode");
9683 return;
9684 }
9685
9686 if (mips_opts.noautoextend && ! mips16_ext)
9687 mips16_small = TRUE;
9688
9689 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9690 {
9691 insn_error = _("unrecognized opcode");
9692 return;
9693 }
9694
9695 argsstart = s;
9696 for (;;)
9697 {
9698 bfd_boolean ok;
9699
9700 assert (strcmp (insn->name, str) == 0);
9701
9702 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
9703 ok = TRUE;
9704 else
9705 ok = FALSE;
9706
9707 if (! ok)
9708 {
9709 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
9710 && strcmp (insn->name, insn[1].name) == 0)
9711 {
9712 ++insn;
9713 continue;
9714 }
9715 else
9716 {
9717 if (!insn_error)
9718 {
9719 static char buf[100];
9720 sprintf (buf,
9721 _("opcode not supported on this processor: %s (%s)"),
9722 mips_cpu_info_from_arch (mips_opts.arch)->name,
9723 mips_cpu_info_from_isa (mips_opts.isa)->name);
9724 insn_error = buf;
9725 }
9726 return;
9727 }
9728 }
9729
9730 create_insn (ip, insn);
9731 imm_expr.X_op = O_absent;
9732 imm_reloc[0] = BFD_RELOC_UNUSED;
9733 imm_reloc[1] = BFD_RELOC_UNUSED;
9734 imm_reloc[2] = BFD_RELOC_UNUSED;
9735 imm2_expr.X_op = O_absent;
9736 offset_expr.X_op = O_absent;
9737 offset_reloc[0] = BFD_RELOC_UNUSED;
9738 offset_reloc[1] = BFD_RELOC_UNUSED;
9739 offset_reloc[2] = BFD_RELOC_UNUSED;
9740 for (args = insn->args; 1; ++args)
9741 {
9742 int c;
9743
9744 if (*s == ' ')
9745 ++s;
9746
9747 /* In this switch statement we call break if we did not find
9748 a match, continue if we did find a match, or return if we
9749 are done. */
9750
9751 c = *args;
9752 switch (c)
9753 {
9754 case '\0':
9755 if (*s == '\0')
9756 {
9757 /* Stuff the immediate value in now, if we can. */
9758 if (imm_expr.X_op == O_constant
9759 && *imm_reloc > BFD_RELOC_UNUSED
9760 && insn->pinfo != INSN_MACRO)
9761 {
9762 valueT tmp;
9763
9764 switch (*offset_reloc)
9765 {
9766 case BFD_RELOC_MIPS16_HI16_S:
9767 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
9768 break;
9769
9770 case BFD_RELOC_MIPS16_HI16:
9771 tmp = imm_expr.X_add_number >> 16;
9772 break;
9773
9774 case BFD_RELOC_MIPS16_LO16:
9775 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
9776 - 0x8000;
9777 break;
9778
9779 case BFD_RELOC_UNUSED:
9780 tmp = imm_expr.X_add_number;
9781 break;
9782
9783 default:
9784 internalError ();
9785 }
9786 *offset_reloc = BFD_RELOC_UNUSED;
9787
9788 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9789 tmp, TRUE, mips16_small,
9790 mips16_ext, &ip->insn_opcode,
9791 &ip->use_extend, &ip->extend);
9792 imm_expr.X_op = O_absent;
9793 *imm_reloc = BFD_RELOC_UNUSED;
9794 }
9795
9796 return;
9797 }
9798 break;
9799
9800 case ',':
9801 if (*s++ == c)
9802 continue;
9803 s--;
9804 switch (*++args)
9805 {
9806 case 'v':
9807 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9808 continue;
9809 case 'w':
9810 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9811 continue;
9812 }
9813 break;
9814
9815 case '(':
9816 case ')':
9817 if (*s++ == c)
9818 continue;
9819 break;
9820
9821 case 'v':
9822 case 'w':
9823 if (s[0] != '$')
9824 {
9825 if (c == 'v')
9826 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9827 else
9828 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9829 ++args;
9830 continue;
9831 }
9832 /* Fall through. */
9833 case 'x':
9834 case 'y':
9835 case 'z':
9836 case 'Z':
9837 case '0':
9838 case 'S':
9839 case 'R':
9840 case 'X':
9841 case 'Y':
9842 s_reset = s;
9843 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
9844 {
9845 if (c == 'v' || c == 'w')
9846 {
9847 if (c == 'v')
9848 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9849 else
9850 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9851 ++args;
9852 continue;
9853 }
9854 break;
9855 }
9856
9857 if (*s == ' ')
9858 ++s;
9859 if (args[1] != *s)
9860 {
9861 if (c == 'v' || c == 'w')
9862 {
9863 regno = mips16_to_32_reg_map[lastregno];
9864 s = s_reset;
9865 ++args;
9866 }
9867 }
9868
9869 switch (c)
9870 {
9871 case 'x':
9872 case 'y':
9873 case 'z':
9874 case 'v':
9875 case 'w':
9876 case 'Z':
9877 regno = mips32_to_16_reg_map[regno];
9878 break;
9879
9880 case '0':
9881 if (regno != 0)
9882 regno = ILLEGAL_REG;
9883 break;
9884
9885 case 'S':
9886 if (regno != SP)
9887 regno = ILLEGAL_REG;
9888 break;
9889
9890 case 'R':
9891 if (regno != RA)
9892 regno = ILLEGAL_REG;
9893 break;
9894
9895 case 'X':
9896 case 'Y':
9897 if (regno == AT && ! mips_opts.noat)
9898 as_warn (_("used $at without \".set noat\""));
9899 break;
9900
9901 default:
9902 internalError ();
9903 }
9904
9905 if (regno == ILLEGAL_REG)
9906 break;
9907
9908 switch (c)
9909 {
9910 case 'x':
9911 case 'v':
9912 MIPS16_INSERT_OPERAND (RX, *ip, regno);
9913 break;
9914 case 'y':
9915 case 'w':
9916 MIPS16_INSERT_OPERAND (RY, *ip, regno);
9917 break;
9918 case 'z':
9919 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
9920 break;
9921 case 'Z':
9922 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
9923 case '0':
9924 case 'S':
9925 case 'R':
9926 break;
9927 case 'X':
9928 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
9929 break;
9930 case 'Y':
9931 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9932 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
9933 break;
9934 default:
9935 internalError ();
9936 }
9937
9938 lastregno = regno;
9939 continue;
9940
9941 case 'P':
9942 if (strncmp (s, "$pc", 3) == 0)
9943 {
9944 s += 3;
9945 continue;
9946 }
9947 break;
9948
9949 case '5':
9950 case 'H':
9951 case 'W':
9952 case 'D':
9953 case 'j':
9954 case 'V':
9955 case 'C':
9956 case 'U':
9957 case 'k':
9958 case 'K':
9959 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
9960 if (i > 0)
9961 {
9962 if (imm_expr.X_op != O_constant)
9963 {
9964 mips16_ext = TRUE;
9965 ip->use_extend = TRUE;
9966 ip->extend = 0;
9967 }
9968 else
9969 {
9970 /* We need to relax this instruction. */
9971 *offset_reloc = *imm_reloc;
9972 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9973 }
9974 s = expr_end;
9975 continue;
9976 }
9977 *imm_reloc = BFD_RELOC_UNUSED;
9978 /* Fall through. */
9979 case '<':
9980 case '>':
9981 case '[':
9982 case ']':
9983 case '4':
9984 case '8':
9985 my_getExpression (&imm_expr, s);
9986 if (imm_expr.X_op == O_register)
9987 {
9988 /* What we thought was an expression turned out to
9989 be a register. */
9990
9991 if (s[0] == '(' && args[1] == '(')
9992 {
9993 /* It looks like the expression was omitted
9994 before a register indirection, which means
9995 that the expression is implicitly zero. We
9996 still set up imm_expr, so that we handle
9997 explicit extensions correctly. */
9998 imm_expr.X_op = O_constant;
9999 imm_expr.X_add_number = 0;
10000 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10001 continue;
10002 }
10003
10004 break;
10005 }
10006
10007 /* We need to relax this instruction. */
10008 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10009 s = expr_end;
10010 continue;
10011
10012 case 'p':
10013 case 'q':
10014 case 'A':
10015 case 'B':
10016 case 'E':
10017 /* We use offset_reloc rather than imm_reloc for the PC
10018 relative operands. This lets macros with both
10019 immediate and address operands work correctly. */
10020 my_getExpression (&offset_expr, s);
10021
10022 if (offset_expr.X_op == O_register)
10023 break;
10024
10025 /* We need to relax this instruction. */
10026 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10027 s = expr_end;
10028 continue;
10029
10030 case '6': /* break code */
10031 my_getExpression (&imm_expr, s);
10032 check_absolute_expr (ip, &imm_expr);
10033 if ((unsigned long) imm_expr.X_add_number > 63)
10034 as_warn (_("Invalid value for `%s' (%lu)"),
10035 ip->insn_mo->name,
10036 (unsigned long) imm_expr.X_add_number);
10037 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10038 imm_expr.X_op = O_absent;
10039 s = expr_end;
10040 continue;
10041
10042 case 'a': /* 26 bit address */
10043 my_getExpression (&offset_expr, s);
10044 s = expr_end;
10045 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10046 ip->insn_opcode <<= 16;
10047 continue;
10048
10049 case 'l': /* register list for entry macro */
10050 case 'L': /* register list for exit macro */
10051 {
10052 int mask;
10053
10054 if (c == 'l')
10055 mask = 0;
10056 else
10057 mask = 7 << 3;
10058 while (*s != '\0')
10059 {
10060 unsigned int freg, reg1, reg2;
10061
10062 while (*s == ' ' || *s == ',')
10063 ++s;
10064 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10065 freg = 0;
10066 else if (reg_lookup (&s, RTYPE_FPU, &reg1))
10067 freg = 1;
10068 else
10069 {
10070 as_bad (_("can't parse register list"));
10071 break;
10072 }
10073 if (*s == ' ')
10074 ++s;
10075 if (*s != '-')
10076 reg2 = reg1;
10077 else
10078 {
10079 ++s;
10080 if (!reg_lookup (&s, freg ? RTYPE_FPU
10081 : (RTYPE_GP | RTYPE_NUM), &reg2))
10082 {
10083 as_bad (_("invalid register list"));
10084 break;
10085 }
10086 }
10087 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10088 {
10089 mask &= ~ (7 << 3);
10090 mask |= 5 << 3;
10091 }
10092 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10093 {
10094 mask &= ~ (7 << 3);
10095 mask |= 6 << 3;
10096 }
10097 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10098 mask |= (reg2 - 3) << 3;
10099 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10100 mask |= (reg2 - 15) << 1;
10101 else if (reg1 == RA && reg2 == RA)
10102 mask |= 1;
10103 else
10104 {
10105 as_bad (_("invalid register list"));
10106 break;
10107 }
10108 }
10109 /* The mask is filled in in the opcode table for the
10110 benefit of the disassembler. We remove it before
10111 applying the actual mask. */
10112 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10113 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10114 }
10115 continue;
10116
10117 case 'm': /* Register list for save insn. */
10118 case 'M': /* Register list for restore insn. */
10119 {
10120 int opcode = 0;
10121 int framesz = 0, seen_framesz = 0;
10122 int args = 0, statics = 0, sregs = 0;
10123
10124 while (*s != '\0')
10125 {
10126 unsigned int reg1, reg2;
10127
10128 SKIP_SPACE_TABS (s);
10129 while (*s == ',')
10130 ++s;
10131 SKIP_SPACE_TABS (s);
10132
10133 my_getExpression (&imm_expr, s);
10134 if (imm_expr.X_op == O_constant)
10135 {
10136 /* Handle the frame size. */
10137 if (seen_framesz)
10138 {
10139 as_bad (_("more than one frame size in list"));
10140 break;
10141 }
10142 seen_framesz = 1;
10143 framesz = imm_expr.X_add_number;
10144 imm_expr.X_op = O_absent;
10145 s = expr_end;
10146 continue;
10147 }
10148
10149 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10150 {
10151 as_bad (_("can't parse register list"));
10152 break;
10153 }
10154
10155 while (*s == ' ')
10156 ++s;
10157
10158 if (*s != '-')
10159 reg2 = reg1;
10160 else
10161 {
10162 ++s;
10163 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
10164 || reg2 < reg1)
10165 {
10166 as_bad (_("can't parse register list"));
10167 break;
10168 }
10169 }
10170
10171 while (reg1 <= reg2)
10172 {
10173 if (reg1 >= 4 && reg1 <= 7)
10174 {
10175 if (c == 'm' && !seen_framesz)
10176 /* args $a0-$a3 */
10177 args |= 1 << (reg1 - 4);
10178 else
10179 /* statics $a0-$a3 */
10180 statics |= 1 << (reg1 - 4);
10181 }
10182 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10183 {
10184 /* $s0-$s8 */
10185 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10186 }
10187 else if (reg1 == 31)
10188 {
10189 /* Add $ra to insn. */
10190 opcode |= 0x40;
10191 }
10192 else
10193 {
10194 as_bad (_("unexpected register in list"));
10195 break;
10196 }
10197 if (++reg1 == 24)
10198 reg1 = 30;
10199 }
10200 }
10201
10202 /* Encode args/statics combination. */
10203 if (args & statics)
10204 as_bad (_("arg/static registers overlap"));
10205 else if (args == 0xf)
10206 /* All $a0-$a3 are args. */
10207 opcode |= MIPS16_ALL_ARGS << 16;
10208 else if (statics == 0xf)
10209 /* All $a0-$a3 are statics. */
10210 opcode |= MIPS16_ALL_STATICS << 16;
10211 else
10212 {
10213 int narg = 0, nstat = 0;
10214
10215 /* Count arg registers. */
10216 while (args & 0x1)
10217 {
10218 args >>= 1;
10219 narg++;
10220 }
10221 if (args != 0)
10222 as_bad (_("invalid arg register list"));
10223
10224 /* Count static registers. */
10225 while (statics & 0x8)
10226 {
10227 statics = (statics << 1) & 0xf;
10228 nstat++;
10229 }
10230 if (statics != 0)
10231 as_bad (_("invalid static register list"));
10232
10233 /* Encode args/statics. */
10234 opcode |= ((narg << 2) | nstat) << 16;
10235 }
10236
10237 /* Encode $s0/$s1. */
10238 if (sregs & (1 << 0)) /* $s0 */
10239 opcode |= 0x20;
10240 if (sregs & (1 << 1)) /* $s1 */
10241 opcode |= 0x10;
10242 sregs >>= 2;
10243
10244 if (sregs != 0)
10245 {
10246 /* Count regs $s2-$s8. */
10247 int nsreg = 0;
10248 while (sregs & 1)
10249 {
10250 sregs >>= 1;
10251 nsreg++;
10252 }
10253 if (sregs != 0)
10254 as_bad (_("invalid static register list"));
10255 /* Encode $s2-$s8. */
10256 opcode |= nsreg << 24;
10257 }
10258
10259 /* Encode frame size. */
10260 if (!seen_framesz)
10261 as_bad (_("missing frame size"));
10262 else if ((framesz & 7) != 0 || framesz < 0
10263 || framesz > 0xff * 8)
10264 as_bad (_("invalid frame size"));
10265 else if (framesz != 128 || (opcode >> 16) != 0)
10266 {
10267 framesz /= 8;
10268 opcode |= (((framesz & 0xf0) << 16)
10269 | (framesz & 0x0f));
10270 }
10271
10272 /* Finally build the instruction. */
10273 if ((opcode >> 16) != 0 || framesz == 0)
10274 {
10275 ip->use_extend = TRUE;
10276 ip->extend = opcode >> 16;
10277 }
10278 ip->insn_opcode |= opcode & 0x7f;
10279 }
10280 continue;
10281
10282 case 'e': /* extend code */
10283 my_getExpression (&imm_expr, s);
10284 check_absolute_expr (ip, &imm_expr);
10285 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10286 {
10287 as_warn (_("Invalid value for `%s' (%lu)"),
10288 ip->insn_mo->name,
10289 (unsigned long) imm_expr.X_add_number);
10290 imm_expr.X_add_number &= 0x7ff;
10291 }
10292 ip->insn_opcode |= imm_expr.X_add_number;
10293 imm_expr.X_op = O_absent;
10294 s = expr_end;
10295 continue;
10296
10297 default:
10298 internalError ();
10299 }
10300 break;
10301 }
10302
10303 /* Args don't match. */
10304 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10305 strcmp (insn->name, insn[1].name) == 0)
10306 {
10307 ++insn;
10308 s = argsstart;
10309 continue;
10310 }
10311
10312 insn_error = _("illegal operands");
10313
10314 return;
10315 }
10316 }
10317
10318 /* This structure holds information we know about a mips16 immediate
10319 argument type. */
10320
10321 struct mips16_immed_operand
10322 {
10323 /* The type code used in the argument string in the opcode table. */
10324 int type;
10325 /* The number of bits in the short form of the opcode. */
10326 int nbits;
10327 /* The number of bits in the extended form of the opcode. */
10328 int extbits;
10329 /* The amount by which the short form is shifted when it is used;
10330 for example, the sw instruction has a shift count of 2. */
10331 int shift;
10332 /* The amount by which the short form is shifted when it is stored
10333 into the instruction code. */
10334 int op_shift;
10335 /* Non-zero if the short form is unsigned. */
10336 int unsp;
10337 /* Non-zero if the extended form is unsigned. */
10338 int extu;
10339 /* Non-zero if the value is PC relative. */
10340 int pcrel;
10341 };
10342
10343 /* The mips16 immediate operand types. */
10344
10345 static const struct mips16_immed_operand mips16_immed_operands[] =
10346 {
10347 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10348 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10349 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10350 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10351 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10352 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10353 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10354 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10355 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10356 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10357 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10358 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10359 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10360 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10361 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10362 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10363 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10364 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10365 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10366 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10367 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10368 };
10369
10370 #define MIPS16_NUM_IMMED \
10371 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10372
10373 /* Handle a mips16 instruction with an immediate value. This or's the
10374 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10375 whether an extended value is needed; if one is needed, it sets
10376 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10377 If SMALL is true, an unextended opcode was explicitly requested.
10378 If EXT is true, an extended opcode was explicitly requested. If
10379 WARN is true, warn if EXT does not match reality. */
10380
10381 static void
10382 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10383 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10384 unsigned long *insn, bfd_boolean *use_extend,
10385 unsigned short *extend)
10386 {
10387 register const struct mips16_immed_operand *op;
10388 int mintiny, maxtiny;
10389 bfd_boolean needext;
10390
10391 op = mips16_immed_operands;
10392 while (op->type != type)
10393 {
10394 ++op;
10395 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10396 }
10397
10398 if (op->unsp)
10399 {
10400 if (type == '<' || type == '>' || type == '[' || type == ']')
10401 {
10402 mintiny = 1;
10403 maxtiny = 1 << op->nbits;
10404 }
10405 else
10406 {
10407 mintiny = 0;
10408 maxtiny = (1 << op->nbits) - 1;
10409 }
10410 }
10411 else
10412 {
10413 mintiny = - (1 << (op->nbits - 1));
10414 maxtiny = (1 << (op->nbits - 1)) - 1;
10415 }
10416
10417 /* Branch offsets have an implicit 0 in the lowest bit. */
10418 if (type == 'p' || type == 'q')
10419 val /= 2;
10420
10421 if ((val & ((1 << op->shift) - 1)) != 0
10422 || val < (mintiny << op->shift)
10423 || val > (maxtiny << op->shift))
10424 needext = TRUE;
10425 else
10426 needext = FALSE;
10427
10428 if (warn && ext && ! needext)
10429 as_warn_where (file, line,
10430 _("extended operand requested but not required"));
10431 if (small && needext)
10432 as_bad_where (file, line, _("invalid unextended operand value"));
10433
10434 if (small || (! ext && ! needext))
10435 {
10436 int insnval;
10437
10438 *use_extend = FALSE;
10439 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10440 insnval <<= op->op_shift;
10441 *insn |= insnval;
10442 }
10443 else
10444 {
10445 long minext, maxext;
10446 int extval;
10447
10448 if (op->extu)
10449 {
10450 minext = 0;
10451 maxext = (1 << op->extbits) - 1;
10452 }
10453 else
10454 {
10455 minext = - (1 << (op->extbits - 1));
10456 maxext = (1 << (op->extbits - 1)) - 1;
10457 }
10458 if (val < minext || val > maxext)
10459 as_bad_where (file, line,
10460 _("operand value out of range for instruction"));
10461
10462 *use_extend = TRUE;
10463 if (op->extbits == 16)
10464 {
10465 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10466 val &= 0x1f;
10467 }
10468 else if (op->extbits == 15)
10469 {
10470 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10471 val &= 0xf;
10472 }
10473 else
10474 {
10475 extval = ((val & 0x1f) << 6) | (val & 0x20);
10476 val = 0;
10477 }
10478
10479 *extend = (unsigned short) extval;
10480 *insn |= val;
10481 }
10482 }
10483 \f
10484 struct percent_op_match
10485 {
10486 const char *str;
10487 bfd_reloc_code_real_type reloc;
10488 };
10489
10490 static const struct percent_op_match mips_percent_op[] =
10491 {
10492 {"%lo", BFD_RELOC_LO16},
10493 #ifdef OBJ_ELF
10494 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10495 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10496 {"%call16", BFD_RELOC_MIPS_CALL16},
10497 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10498 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10499 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10500 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10501 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10502 {"%got", BFD_RELOC_MIPS_GOT16},
10503 {"%gp_rel", BFD_RELOC_GPREL16},
10504 {"%half", BFD_RELOC_16},
10505 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10506 {"%higher", BFD_RELOC_MIPS_HIGHER},
10507 {"%neg", BFD_RELOC_MIPS_SUB},
10508 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
10509 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
10510 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
10511 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
10512 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
10513 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
10514 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
10515 #endif
10516 {"%hi", BFD_RELOC_HI16_S}
10517 };
10518
10519 static const struct percent_op_match mips16_percent_op[] =
10520 {
10521 {"%lo", BFD_RELOC_MIPS16_LO16},
10522 {"%gprel", BFD_RELOC_MIPS16_GPREL},
10523 {"%hi", BFD_RELOC_MIPS16_HI16_S}
10524 };
10525
10526
10527 /* Return true if *STR points to a relocation operator. When returning true,
10528 move *STR over the operator and store its relocation code in *RELOC.
10529 Leave both *STR and *RELOC alone when returning false. */
10530
10531 static bfd_boolean
10532 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10533 {
10534 const struct percent_op_match *percent_op;
10535 size_t limit, i;
10536
10537 if (mips_opts.mips16)
10538 {
10539 percent_op = mips16_percent_op;
10540 limit = ARRAY_SIZE (mips16_percent_op);
10541 }
10542 else
10543 {
10544 percent_op = mips_percent_op;
10545 limit = ARRAY_SIZE (mips_percent_op);
10546 }
10547
10548 for (i = 0; i < limit; i++)
10549 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10550 {
10551 int len = strlen (percent_op[i].str);
10552
10553 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
10554 continue;
10555
10556 *str += strlen (percent_op[i].str);
10557 *reloc = percent_op[i].reloc;
10558
10559 /* Check whether the output BFD supports this relocation.
10560 If not, issue an error and fall back on something safe. */
10561 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10562 {
10563 as_bad ("relocation %s isn't supported by the current ABI",
10564 percent_op[i].str);
10565 *reloc = BFD_RELOC_UNUSED;
10566 }
10567 return TRUE;
10568 }
10569 return FALSE;
10570 }
10571
10572
10573 /* Parse string STR as a 16-bit relocatable operand. Store the
10574 expression in *EP and the relocations in the array starting
10575 at RELOC. Return the number of relocation operators used.
10576
10577 On exit, EXPR_END points to the first character after the expression. */
10578
10579 static size_t
10580 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10581 char *str)
10582 {
10583 bfd_reloc_code_real_type reversed_reloc[3];
10584 size_t reloc_index, i;
10585 int crux_depth, str_depth;
10586 char *crux;
10587
10588 /* Search for the start of the main expression, recoding relocations
10589 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10590 of the main expression and with CRUX_DEPTH containing the number
10591 of open brackets at that point. */
10592 reloc_index = -1;
10593 str_depth = 0;
10594 do
10595 {
10596 reloc_index++;
10597 crux = str;
10598 crux_depth = str_depth;
10599
10600 /* Skip over whitespace and brackets, keeping count of the number
10601 of brackets. */
10602 while (*str == ' ' || *str == '\t' || *str == '(')
10603 if (*str++ == '(')
10604 str_depth++;
10605 }
10606 while (*str == '%'
10607 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10608 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10609
10610 my_getExpression (ep, crux);
10611 str = expr_end;
10612
10613 /* Match every open bracket. */
10614 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10615 if (*str++ == ')')
10616 crux_depth--;
10617
10618 if (crux_depth > 0)
10619 as_bad ("unclosed '('");
10620
10621 expr_end = str;
10622
10623 if (reloc_index != 0)
10624 {
10625 prev_reloc_op_frag = frag_now;
10626 for (i = 0; i < reloc_index; i++)
10627 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10628 }
10629
10630 return reloc_index;
10631 }
10632
10633 static void
10634 my_getExpression (expressionS *ep, char *str)
10635 {
10636 char *save_in;
10637 valueT val;
10638
10639 save_in = input_line_pointer;
10640 input_line_pointer = str;
10641 expression (ep);
10642 expr_end = input_line_pointer;
10643 input_line_pointer = save_in;
10644
10645 /* If we are in mips16 mode, and this is an expression based on `.',
10646 then we bump the value of the symbol by 1 since that is how other
10647 text symbols are handled. We don't bother to handle complex
10648 expressions, just `.' plus or minus a constant. */
10649 if (mips_opts.mips16
10650 && ep->X_op == O_symbol
10651 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10652 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10653 && symbol_get_frag (ep->X_add_symbol) == frag_now
10654 && symbol_constant_p (ep->X_add_symbol)
10655 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10656 S_SET_VALUE (ep->X_add_symbol, val + 1);
10657 }
10658
10659 /* Turn a string in input_line_pointer into a floating point constant
10660 of type TYPE, and store the appropriate bytes in *LITP. The number
10661 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10662 returned, or NULL on OK. */
10663
10664 char *
10665 md_atof (int type, char *litP, int *sizeP)
10666 {
10667 int prec;
10668 LITTLENUM_TYPE words[4];
10669 char *t;
10670 int i;
10671
10672 switch (type)
10673 {
10674 case 'f':
10675 prec = 2;
10676 break;
10677
10678 case 'd':
10679 prec = 4;
10680 break;
10681
10682 default:
10683 *sizeP = 0;
10684 return _("bad call to md_atof");
10685 }
10686
10687 t = atof_ieee (input_line_pointer, type, words);
10688 if (t)
10689 input_line_pointer = t;
10690
10691 *sizeP = prec * 2;
10692
10693 if (! target_big_endian)
10694 {
10695 for (i = prec - 1; i >= 0; i--)
10696 {
10697 md_number_to_chars (litP, words[i], 2);
10698 litP += 2;
10699 }
10700 }
10701 else
10702 {
10703 for (i = 0; i < prec; i++)
10704 {
10705 md_number_to_chars (litP, words[i], 2);
10706 litP += 2;
10707 }
10708 }
10709
10710 return NULL;
10711 }
10712
10713 void
10714 md_number_to_chars (char *buf, valueT val, int n)
10715 {
10716 if (target_big_endian)
10717 number_to_chars_bigendian (buf, val, n);
10718 else
10719 number_to_chars_littleendian (buf, val, n);
10720 }
10721 \f
10722 #ifdef OBJ_ELF
10723 static int support_64bit_objects(void)
10724 {
10725 const char **list, **l;
10726 int yes;
10727
10728 list = bfd_target_list ();
10729 for (l = list; *l != NULL; l++)
10730 #ifdef TE_TMIPS
10731 /* This is traditional mips */
10732 if (strcmp (*l, "elf64-tradbigmips") == 0
10733 || strcmp (*l, "elf64-tradlittlemips") == 0)
10734 #else
10735 if (strcmp (*l, "elf64-bigmips") == 0
10736 || strcmp (*l, "elf64-littlemips") == 0)
10737 #endif
10738 break;
10739 yes = (*l != NULL);
10740 free (list);
10741 return yes;
10742 }
10743 #endif /* OBJ_ELF */
10744
10745 const char *md_shortopts = "O::g::G:";
10746
10747 struct option md_longopts[] =
10748 {
10749 /* Options which specify architecture. */
10750 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10751 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10752 {"march", required_argument, NULL, OPTION_MARCH},
10753 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10754 {"mtune", required_argument, NULL, OPTION_MTUNE},
10755 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10756 {"mips0", no_argument, NULL, OPTION_MIPS1},
10757 {"mips1", no_argument, NULL, OPTION_MIPS1},
10758 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10759 {"mips2", no_argument, NULL, OPTION_MIPS2},
10760 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10761 {"mips3", no_argument, NULL, OPTION_MIPS3},
10762 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10763 {"mips4", no_argument, NULL, OPTION_MIPS4},
10764 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10765 {"mips5", no_argument, NULL, OPTION_MIPS5},
10766 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10767 {"mips32", no_argument, NULL, OPTION_MIPS32},
10768 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10769 {"mips64", no_argument, NULL, OPTION_MIPS64},
10770 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10771 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10772 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10773 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10774
10775 /* Options which specify Application Specific Extensions (ASEs). */
10776 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10777 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10778 {"mips16", no_argument, NULL, OPTION_MIPS16},
10779 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10780 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10781 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10782 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10783 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10784 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10785 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10786 {"mdmx", no_argument, NULL, OPTION_MDMX},
10787 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10788 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10789 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10790 {"mdsp", no_argument, NULL, OPTION_DSP},
10791 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10792 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
10793 #define OPTION_MT (OPTION_ASE_BASE + 8)
10794 {"mmt", no_argument, NULL, OPTION_MT},
10795 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10796 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
10797 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10798 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
10799 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10800 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
10801
10802 /* Old-style architecture options. Don't add more of these. */
10803 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10804 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10805 {"m4650", no_argument, NULL, OPTION_M4650},
10806 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10807 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10808 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10809 {"m4010", no_argument, NULL, OPTION_M4010},
10810 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10811 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10812 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10813 {"m4100", no_argument, NULL, OPTION_M4100},
10814 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10815 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10816 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10817 {"m3900", no_argument, NULL, OPTION_M3900},
10818 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10819 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10820
10821 /* Options which enable bug fixes. */
10822 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10823 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10824 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10825 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10826 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10827 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10828 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10829 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10830 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10831 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10832 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10833 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10834 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
10835 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
10836
10837 /* Miscellaneous options. */
10838 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10839 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10840 {"trap", no_argument, NULL, OPTION_TRAP},
10841 {"no-break", no_argument, NULL, OPTION_TRAP},
10842 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10843 {"break", no_argument, NULL, OPTION_BREAK},
10844 {"no-trap", no_argument, NULL, OPTION_BREAK},
10845 #define OPTION_EB (OPTION_MISC_BASE + 2)
10846 {"EB", no_argument, NULL, OPTION_EB},
10847 #define OPTION_EL (OPTION_MISC_BASE + 3)
10848 {"EL", no_argument, NULL, OPTION_EL},
10849 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10850 {"mfp32", no_argument, NULL, OPTION_FP32},
10851 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10852 {"mgp32", no_argument, NULL, OPTION_GP32},
10853 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10854 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10855 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10856 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10857 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10858 {"mfp64", no_argument, NULL, OPTION_FP64},
10859 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10860 {"mgp64", no_argument, NULL, OPTION_GP64},
10861 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10862 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10863 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10864 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10865 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10866 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10867 {"mshared", no_argument, NULL, OPTION_MSHARED},
10868 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
10869 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10870 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10871 {"msym32", no_argument, NULL, OPTION_MSYM32},
10872 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
10873
10874 /* ELF-specific options. */
10875 #ifdef OBJ_ELF
10876 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10877 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10878 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10879 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10880 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10881 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10882 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10883 {"xgot", no_argument, NULL, OPTION_XGOT},
10884 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10885 {"mabi", required_argument, NULL, OPTION_MABI},
10886 #define OPTION_32 (OPTION_ELF_BASE + 4)
10887 {"32", no_argument, NULL, OPTION_32},
10888 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10889 {"n32", no_argument, NULL, OPTION_N32},
10890 #define OPTION_64 (OPTION_ELF_BASE + 6)
10891 {"64", no_argument, NULL, OPTION_64},
10892 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10893 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10894 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10895 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10896 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10897 {"mpdr", no_argument, NULL, OPTION_PDR},
10898 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10899 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10900 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10901 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
10902 #endif /* OBJ_ELF */
10903
10904 {NULL, no_argument, NULL, 0}
10905 };
10906 size_t md_longopts_size = sizeof (md_longopts);
10907
10908 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10909 NEW_VALUE. Warn if another value was already specified. Note:
10910 we have to defer parsing the -march and -mtune arguments in order
10911 to handle 'from-abi' correctly, since the ABI might be specified
10912 in a later argument. */
10913
10914 static void
10915 mips_set_option_string (const char **string_ptr, const char *new_value)
10916 {
10917 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10918 as_warn (_("A different %s was already specified, is now %s"),
10919 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10920 new_value);
10921
10922 *string_ptr = new_value;
10923 }
10924
10925 int
10926 md_parse_option (int c, char *arg)
10927 {
10928 switch (c)
10929 {
10930 case OPTION_CONSTRUCT_FLOATS:
10931 mips_disable_float_construction = 0;
10932 break;
10933
10934 case OPTION_NO_CONSTRUCT_FLOATS:
10935 mips_disable_float_construction = 1;
10936 break;
10937
10938 case OPTION_TRAP:
10939 mips_trap = 1;
10940 break;
10941
10942 case OPTION_BREAK:
10943 mips_trap = 0;
10944 break;
10945
10946 case OPTION_EB:
10947 target_big_endian = 1;
10948 break;
10949
10950 case OPTION_EL:
10951 target_big_endian = 0;
10952 break;
10953
10954 case 'O':
10955 if (arg && arg[1] == '0')
10956 mips_optimize = 1;
10957 else
10958 mips_optimize = 2;
10959 break;
10960
10961 case 'g':
10962 if (arg == NULL)
10963 mips_debug = 2;
10964 else
10965 mips_debug = atoi (arg);
10966 /* When the MIPS assembler sees -g or -g2, it does not do
10967 optimizations which limit full symbolic debugging. We take
10968 that to be equivalent to -O0. */
10969 if (mips_debug == 2)
10970 mips_optimize = 1;
10971 break;
10972
10973 case OPTION_MIPS1:
10974 file_mips_isa = ISA_MIPS1;
10975 break;
10976
10977 case OPTION_MIPS2:
10978 file_mips_isa = ISA_MIPS2;
10979 break;
10980
10981 case OPTION_MIPS3:
10982 file_mips_isa = ISA_MIPS3;
10983 break;
10984
10985 case OPTION_MIPS4:
10986 file_mips_isa = ISA_MIPS4;
10987 break;
10988
10989 case OPTION_MIPS5:
10990 file_mips_isa = ISA_MIPS5;
10991 break;
10992
10993 case OPTION_MIPS32:
10994 file_mips_isa = ISA_MIPS32;
10995 break;
10996
10997 case OPTION_MIPS32R2:
10998 file_mips_isa = ISA_MIPS32R2;
10999 break;
11000
11001 case OPTION_MIPS64R2:
11002 file_mips_isa = ISA_MIPS64R2;
11003 break;
11004
11005 case OPTION_MIPS64:
11006 file_mips_isa = ISA_MIPS64;
11007 break;
11008
11009 case OPTION_MTUNE:
11010 mips_set_option_string (&mips_tune_string, arg);
11011 break;
11012
11013 case OPTION_MARCH:
11014 mips_set_option_string (&mips_arch_string, arg);
11015 break;
11016
11017 case OPTION_M4650:
11018 mips_set_option_string (&mips_arch_string, "4650");
11019 mips_set_option_string (&mips_tune_string, "4650");
11020 break;
11021
11022 case OPTION_NO_M4650:
11023 break;
11024
11025 case OPTION_M4010:
11026 mips_set_option_string (&mips_arch_string, "4010");
11027 mips_set_option_string (&mips_tune_string, "4010");
11028 break;
11029
11030 case OPTION_NO_M4010:
11031 break;
11032
11033 case OPTION_M4100:
11034 mips_set_option_string (&mips_arch_string, "4100");
11035 mips_set_option_string (&mips_tune_string, "4100");
11036 break;
11037
11038 case OPTION_NO_M4100:
11039 break;
11040
11041 case OPTION_M3900:
11042 mips_set_option_string (&mips_arch_string, "3900");
11043 mips_set_option_string (&mips_tune_string, "3900");
11044 break;
11045
11046 case OPTION_NO_M3900:
11047 break;
11048
11049 case OPTION_MDMX:
11050 mips_opts.ase_mdmx = 1;
11051 break;
11052
11053 case OPTION_NO_MDMX:
11054 mips_opts.ase_mdmx = 0;
11055 break;
11056
11057 case OPTION_DSP:
11058 mips_opts.ase_dsp = 1;
11059 break;
11060
11061 case OPTION_NO_DSP:
11062 mips_opts.ase_dsp = 0;
11063 break;
11064
11065 case OPTION_MT:
11066 mips_opts.ase_mt = 1;
11067 break;
11068
11069 case OPTION_NO_MT:
11070 mips_opts.ase_mt = 0;
11071 break;
11072
11073 case OPTION_MIPS16:
11074 mips_opts.mips16 = 1;
11075 mips_no_prev_insn ();
11076 break;
11077
11078 case OPTION_NO_MIPS16:
11079 mips_opts.mips16 = 0;
11080 mips_no_prev_insn ();
11081 break;
11082
11083 case OPTION_MIPS3D:
11084 mips_opts.ase_mips3d = 1;
11085 break;
11086
11087 case OPTION_NO_MIPS3D:
11088 mips_opts.ase_mips3d = 0;
11089 break;
11090
11091 case OPTION_SMARTMIPS:
11092 mips_opts.ase_smartmips = 1;
11093 break;
11094
11095 case OPTION_NO_SMARTMIPS:
11096 mips_opts.ase_smartmips = 0;
11097 break;
11098
11099 case OPTION_FIX_VR4120:
11100 mips_fix_vr4120 = 1;
11101 break;
11102
11103 case OPTION_NO_FIX_VR4120:
11104 mips_fix_vr4120 = 0;
11105 break;
11106
11107 case OPTION_FIX_VR4130:
11108 mips_fix_vr4130 = 1;
11109 break;
11110
11111 case OPTION_NO_FIX_VR4130:
11112 mips_fix_vr4130 = 0;
11113 break;
11114
11115 case OPTION_RELAX_BRANCH:
11116 mips_relax_branch = 1;
11117 break;
11118
11119 case OPTION_NO_RELAX_BRANCH:
11120 mips_relax_branch = 0;
11121 break;
11122
11123 case OPTION_MSHARED:
11124 mips_in_shared = TRUE;
11125 break;
11126
11127 case OPTION_MNO_SHARED:
11128 mips_in_shared = FALSE;
11129 break;
11130
11131 case OPTION_MSYM32:
11132 mips_opts.sym32 = TRUE;
11133 break;
11134
11135 case OPTION_MNO_SYM32:
11136 mips_opts.sym32 = FALSE;
11137 break;
11138
11139 #ifdef OBJ_ELF
11140 /* When generating ELF code, we permit -KPIC and -call_shared to
11141 select SVR4_PIC, and -non_shared to select no PIC. This is
11142 intended to be compatible with Irix 5. */
11143 case OPTION_CALL_SHARED:
11144 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11145 {
11146 as_bad (_("-call_shared is supported only for ELF format"));
11147 return 0;
11148 }
11149 mips_pic = SVR4_PIC;
11150 mips_abicalls = TRUE;
11151 break;
11152
11153 case OPTION_NON_SHARED:
11154 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11155 {
11156 as_bad (_("-non_shared is supported only for ELF format"));
11157 return 0;
11158 }
11159 mips_pic = NO_PIC;
11160 mips_abicalls = FALSE;
11161 break;
11162
11163 /* The -xgot option tells the assembler to use 32 bit offsets
11164 when accessing the got in SVR4_PIC mode. It is for Irix
11165 compatibility. */
11166 case OPTION_XGOT:
11167 mips_big_got = 1;
11168 break;
11169 #endif /* OBJ_ELF */
11170
11171 case 'G':
11172 g_switch_value = atoi (arg);
11173 g_switch_seen = 1;
11174 break;
11175
11176 #ifdef OBJ_ELF
11177 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11178 and -mabi=64. */
11179 case OPTION_32:
11180 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11181 {
11182 as_bad (_("-32 is supported for ELF format only"));
11183 return 0;
11184 }
11185 mips_abi = O32_ABI;
11186 break;
11187
11188 case OPTION_N32:
11189 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11190 {
11191 as_bad (_("-n32 is supported for ELF format only"));
11192 return 0;
11193 }
11194 mips_abi = N32_ABI;
11195 break;
11196
11197 case OPTION_64:
11198 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11199 {
11200 as_bad (_("-64 is supported for ELF format only"));
11201 return 0;
11202 }
11203 mips_abi = N64_ABI;
11204 if (! support_64bit_objects())
11205 as_fatal (_("No compiled in support for 64 bit object file format"));
11206 break;
11207 #endif /* OBJ_ELF */
11208
11209 case OPTION_GP32:
11210 file_mips_gp32 = 1;
11211 break;
11212
11213 case OPTION_GP64:
11214 file_mips_gp32 = 0;
11215 break;
11216
11217 case OPTION_FP32:
11218 file_mips_fp32 = 1;
11219 break;
11220
11221 case OPTION_FP64:
11222 file_mips_fp32 = 0;
11223 break;
11224
11225 #ifdef OBJ_ELF
11226 case OPTION_MABI:
11227 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11228 {
11229 as_bad (_("-mabi is supported for ELF format only"));
11230 return 0;
11231 }
11232 if (strcmp (arg, "32") == 0)
11233 mips_abi = O32_ABI;
11234 else if (strcmp (arg, "o64") == 0)
11235 mips_abi = O64_ABI;
11236 else if (strcmp (arg, "n32") == 0)
11237 mips_abi = N32_ABI;
11238 else if (strcmp (arg, "64") == 0)
11239 {
11240 mips_abi = N64_ABI;
11241 if (! support_64bit_objects())
11242 as_fatal (_("No compiled in support for 64 bit object file "
11243 "format"));
11244 }
11245 else if (strcmp (arg, "eabi") == 0)
11246 mips_abi = EABI_ABI;
11247 else
11248 {
11249 as_fatal (_("invalid abi -mabi=%s"), arg);
11250 return 0;
11251 }
11252 break;
11253 #endif /* OBJ_ELF */
11254
11255 case OPTION_M7000_HILO_FIX:
11256 mips_7000_hilo_fix = TRUE;
11257 break;
11258
11259 case OPTION_MNO_7000_HILO_FIX:
11260 mips_7000_hilo_fix = FALSE;
11261 break;
11262
11263 #ifdef OBJ_ELF
11264 case OPTION_MDEBUG:
11265 mips_flag_mdebug = TRUE;
11266 break;
11267
11268 case OPTION_NO_MDEBUG:
11269 mips_flag_mdebug = FALSE;
11270 break;
11271
11272 case OPTION_PDR:
11273 mips_flag_pdr = TRUE;
11274 break;
11275
11276 case OPTION_NO_PDR:
11277 mips_flag_pdr = FALSE;
11278 break;
11279
11280 case OPTION_MVXWORKS_PIC:
11281 mips_pic = VXWORKS_PIC;
11282 break;
11283 #endif /* OBJ_ELF */
11284
11285 default:
11286 return 0;
11287 }
11288
11289 return 1;
11290 }
11291 \f
11292 /* Set up globals to generate code for the ISA or processor
11293 described by INFO. */
11294
11295 static void
11296 mips_set_architecture (const struct mips_cpu_info *info)
11297 {
11298 if (info != 0)
11299 {
11300 file_mips_arch = info->cpu;
11301 mips_opts.arch = info->cpu;
11302 mips_opts.isa = info->isa;
11303 }
11304 }
11305
11306
11307 /* Likewise for tuning. */
11308
11309 static void
11310 mips_set_tune (const struct mips_cpu_info *info)
11311 {
11312 if (info != 0)
11313 mips_tune = info->cpu;
11314 }
11315
11316
11317 void
11318 mips_after_parse_args (void)
11319 {
11320 const struct mips_cpu_info *arch_info = 0;
11321 const struct mips_cpu_info *tune_info = 0;
11322
11323 /* GP relative stuff not working for PE */
11324 if (strncmp (TARGET_OS, "pe", 2) == 0)
11325 {
11326 if (g_switch_seen && g_switch_value != 0)
11327 as_bad (_("-G not supported in this configuration."));
11328 g_switch_value = 0;
11329 }
11330
11331 if (mips_abi == NO_ABI)
11332 mips_abi = MIPS_DEFAULT_ABI;
11333
11334 /* The following code determines the architecture and register size.
11335 Similar code was added to GCC 3.3 (see override_options() in
11336 config/mips/mips.c). The GAS and GCC code should be kept in sync
11337 as much as possible. */
11338
11339 if (mips_arch_string != 0)
11340 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11341
11342 if (file_mips_isa != ISA_UNKNOWN)
11343 {
11344 /* Handle -mipsN. At this point, file_mips_isa contains the
11345 ISA level specified by -mipsN, while arch_info->isa contains
11346 the -march selection (if any). */
11347 if (arch_info != 0)
11348 {
11349 /* -march takes precedence over -mipsN, since it is more descriptive.
11350 There's no harm in specifying both as long as the ISA levels
11351 are the same. */
11352 if (file_mips_isa != arch_info->isa)
11353 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11354 mips_cpu_info_from_isa (file_mips_isa)->name,
11355 mips_cpu_info_from_isa (arch_info->isa)->name);
11356 }
11357 else
11358 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11359 }
11360
11361 if (arch_info == 0)
11362 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11363
11364 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11365 as_bad ("-march=%s is not compatible with the selected ABI",
11366 arch_info->name);
11367
11368 mips_set_architecture (arch_info);
11369
11370 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11371 if (mips_tune_string != 0)
11372 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11373
11374 if (tune_info == 0)
11375 mips_set_tune (arch_info);
11376 else
11377 mips_set_tune (tune_info);
11378
11379 if (file_mips_gp32 >= 0)
11380 {
11381 /* The user specified the size of the integer registers. Make sure
11382 it agrees with the ABI and ISA. */
11383 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11384 as_bad (_("-mgp64 used with a 32-bit processor"));
11385 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11386 as_bad (_("-mgp32 used with a 64-bit ABI"));
11387 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11388 as_bad (_("-mgp64 used with a 32-bit ABI"));
11389 }
11390 else
11391 {
11392 /* Infer the integer register size from the ABI and processor.
11393 Restrict ourselves to 32-bit registers if that's all the
11394 processor has, or if the ABI cannot handle 64-bit registers. */
11395 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11396 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11397 }
11398
11399 switch (file_mips_fp32)
11400 {
11401 default:
11402 case -1:
11403 /* No user specified float register size.
11404 ??? GAS treats single-float processors as though they had 64-bit
11405 float registers (although it complains when double-precision
11406 instructions are used). As things stand, saying they have 32-bit
11407 registers would lead to spurious "register must be even" messages.
11408 So here we assume float registers are never smaller than the
11409 integer ones. */
11410 if (file_mips_gp32 == 0)
11411 /* 64-bit integer registers implies 64-bit float registers. */
11412 file_mips_fp32 = 0;
11413 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11414 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11415 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11416 file_mips_fp32 = 0;
11417 else
11418 /* 32-bit float registers. */
11419 file_mips_fp32 = 1;
11420 break;
11421
11422 /* The user specified the size of the float registers. Check if it
11423 agrees with the ABI and ISA. */
11424 case 0:
11425 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11426 as_bad (_("-mfp64 used with a 32-bit fpu"));
11427 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11428 && !ISA_HAS_MXHC1 (mips_opts.isa))
11429 as_warn (_("-mfp64 used with a 32-bit ABI"));
11430 break;
11431 case 1:
11432 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11433 as_warn (_("-mfp32 used with a 64-bit ABI"));
11434 break;
11435 }
11436
11437 /* End of GCC-shared inference code. */
11438
11439 /* This flag is set when we have a 64-bit capable CPU but use only
11440 32-bit wide registers. Note that EABI does not use it. */
11441 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11442 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11443 || mips_abi == O32_ABI))
11444 mips_32bitmode = 1;
11445
11446 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11447 as_bad (_("trap exception not supported at ISA 1"));
11448
11449 /* If the selected architecture includes support for ASEs, enable
11450 generation of code for them. */
11451 if (mips_opts.mips16 == -1)
11452 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11453 if (mips_opts.ase_mips3d == -1)
11454 mips_opts.ase_mips3d = ((CPU_HAS_MIPS3D (file_mips_arch)
11455 || (arch_info->flags & MIPS_CPU_ASE_MIPS3D))
11456 && file_mips_fp32 == 0) ? 1 : 0;
11457 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
11458 as_bad (_("-mfp32 used with -mips3d"));
11459
11460 if (mips_opts.ase_mdmx == -1)
11461 mips_opts.ase_mdmx = ((CPU_HAS_MDMX (file_mips_arch)
11462 || (arch_info->flags & MIPS_CPU_ASE_MDMX))
11463 && file_mips_fp32 == 0) ? 1 : 0;
11464 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
11465 as_bad (_("-mfp32 used with -mdmx"));
11466
11467 if (mips_opts.ase_smartmips == -1)
11468 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
11469 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
11470 as_warn ("%s ISA does not support SmartMIPS",
11471 mips_cpu_info_from_isa (mips_opts.isa)->name);
11472
11473 if (mips_opts.ase_dsp == -1)
11474 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11475 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
11476 as_warn ("%s ISA does not support DSP ASE",
11477 mips_cpu_info_from_isa (mips_opts.isa)->name);
11478
11479 if (mips_opts.ase_mt == -1)
11480 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
11481 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
11482 as_warn ("%s ISA does not support MT ASE",
11483 mips_cpu_info_from_isa (mips_opts.isa)->name);
11484
11485 file_mips_isa = mips_opts.isa;
11486 file_ase_mips16 = mips_opts.mips16;
11487 file_ase_mips3d = mips_opts.ase_mips3d;
11488 file_ase_mdmx = mips_opts.ase_mdmx;
11489 file_ase_smartmips = mips_opts.ase_smartmips;
11490 file_ase_dsp = mips_opts.ase_dsp;
11491 file_ase_mt = mips_opts.ase_mt;
11492 mips_opts.gp32 = file_mips_gp32;
11493 mips_opts.fp32 = file_mips_fp32;
11494
11495 if (mips_flag_mdebug < 0)
11496 {
11497 #ifdef OBJ_MAYBE_ECOFF
11498 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11499 mips_flag_mdebug = 1;
11500 else
11501 #endif /* OBJ_MAYBE_ECOFF */
11502 mips_flag_mdebug = 0;
11503 }
11504 }
11505 \f
11506 void
11507 mips_init_after_args (void)
11508 {
11509 /* initialize opcodes */
11510 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11511 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11512 }
11513
11514 long
11515 md_pcrel_from (fixS *fixP)
11516 {
11517 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11518 switch (fixP->fx_r_type)
11519 {
11520 case BFD_RELOC_16_PCREL_S2:
11521 case BFD_RELOC_MIPS_JMP:
11522 /* Return the address of the delay slot. */
11523 return addr + 4;
11524 default:
11525 return addr;
11526 }
11527 }
11528
11529 /* This is called before the symbol table is processed. In order to
11530 work with gcc when using mips-tfile, we must keep all local labels.
11531 However, in other cases, we want to discard them. If we were
11532 called with -g, but we didn't see any debugging information, it may
11533 mean that gcc is smuggling debugging information through to
11534 mips-tfile, in which case we must generate all local labels. */
11535
11536 void
11537 mips_frob_file_before_adjust (void)
11538 {
11539 #ifndef NO_ECOFF_DEBUGGING
11540 if (ECOFF_DEBUGGING
11541 && mips_debug != 0
11542 && ! ecoff_debugging_seen)
11543 flag_keep_locals = 1;
11544 #endif
11545 }
11546
11547 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11548 the corresponding LO16 reloc. This is called before md_apply_fix and
11549 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11550 relocation operators.
11551
11552 For our purposes, a %lo() expression matches a %got() or %hi()
11553 expression if:
11554
11555 (a) it refers to the same symbol; and
11556 (b) the offset applied in the %lo() expression is no lower than
11557 the offset applied in the %got() or %hi().
11558
11559 (b) allows us to cope with code like:
11560
11561 lui $4,%hi(foo)
11562 lh $4,%lo(foo+2)($4)
11563
11564 ...which is legal on RELA targets, and has a well-defined behaviour
11565 if the user knows that adding 2 to "foo" will not induce a carry to
11566 the high 16 bits.
11567
11568 When several %lo()s match a particular %got() or %hi(), we use the
11569 following rules to distinguish them:
11570
11571 (1) %lo()s with smaller offsets are a better match than %lo()s with
11572 higher offsets.
11573
11574 (2) %lo()s with no matching %got() or %hi() are better than those
11575 that already have a matching %got() or %hi().
11576
11577 (3) later %lo()s are better than earlier %lo()s.
11578
11579 These rules are applied in order.
11580
11581 (1) means, among other things, that %lo()s with identical offsets are
11582 chosen if they exist.
11583
11584 (2) means that we won't associate several high-part relocations with
11585 the same low-part relocation unless there's no alternative. Having
11586 several high parts for the same low part is a GNU extension; this rule
11587 allows careful users to avoid it.
11588
11589 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11590 with the last high-part relocation being at the front of the list.
11591 It therefore makes sense to choose the last matching low-part
11592 relocation, all other things being equal. It's also easier
11593 to code that way. */
11594
11595 void
11596 mips_frob_file (void)
11597 {
11598 struct mips_hi_fixup *l;
11599
11600 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11601 {
11602 segment_info_type *seginfo;
11603 bfd_boolean matched_lo_p;
11604 fixS **hi_pos, **lo_pos, **pos;
11605
11606 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11607
11608 /* If a GOT16 relocation turns out to be against a global symbol,
11609 there isn't supposed to be a matching LO. */
11610 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11611 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11612 continue;
11613
11614 /* Check quickly whether the next fixup happens to be a matching %lo. */
11615 if (fixup_has_matching_lo_p (l->fixp))
11616 continue;
11617
11618 seginfo = seg_info (l->seg);
11619
11620 /* Set HI_POS to the position of this relocation in the chain.
11621 Set LO_POS to the position of the chosen low-part relocation.
11622 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11623 relocation that matches an immediately-preceding high-part
11624 relocation. */
11625 hi_pos = NULL;
11626 lo_pos = NULL;
11627 matched_lo_p = FALSE;
11628 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
11629 {
11630 if (*pos == l->fixp)
11631 hi_pos = pos;
11632
11633 if (((*pos)->fx_r_type == BFD_RELOC_LO16
11634 || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16)
11635 && (*pos)->fx_addsy == l->fixp->fx_addsy
11636 && (*pos)->fx_offset >= l->fixp->fx_offset
11637 && (lo_pos == NULL
11638 || (*pos)->fx_offset < (*lo_pos)->fx_offset
11639 || (!matched_lo_p
11640 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
11641 lo_pos = pos;
11642
11643 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
11644 && fixup_has_matching_lo_p (*pos));
11645 }
11646
11647 /* If we found a match, remove the high-part relocation from its
11648 current position and insert it before the low-part relocation.
11649 Make the offsets match so that fixup_has_matching_lo_p()
11650 will return true.
11651
11652 We don't warn about unmatched high-part relocations since some
11653 versions of gcc have been known to emit dead "lui ...%hi(...)"
11654 instructions. */
11655 if (lo_pos != NULL)
11656 {
11657 l->fixp->fx_offset = (*lo_pos)->fx_offset;
11658 if (l->fixp->fx_next != *lo_pos)
11659 {
11660 *hi_pos = l->fixp->fx_next;
11661 l->fixp->fx_next = *lo_pos;
11662 *lo_pos = l->fixp;
11663 }
11664 }
11665 }
11666 }
11667
11668 /* We may have combined relocations without symbols in the N32/N64 ABI.
11669 We have to prevent gas from dropping them. */
11670
11671 int
11672 mips_force_relocation (fixS *fixp)
11673 {
11674 if (generic_force_reloc (fixp))
11675 return 1;
11676
11677 if (HAVE_NEWABI
11678 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11679 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11680 || fixp->fx_r_type == BFD_RELOC_HI16_S
11681 || fixp->fx_r_type == BFD_RELOC_LO16))
11682 return 1;
11683
11684 return 0;
11685 }
11686
11687 /* Apply a fixup to the object file. */
11688
11689 void
11690 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11691 {
11692 bfd_byte *buf;
11693 long insn;
11694 reloc_howto_type *howto;
11695
11696 /* We ignore generic BFD relocations we don't know about. */
11697 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11698 if (! howto)
11699 return;
11700
11701 assert (fixP->fx_size == 4
11702 || fixP->fx_r_type == BFD_RELOC_16
11703 || fixP->fx_r_type == BFD_RELOC_64
11704 || fixP->fx_r_type == BFD_RELOC_CTOR
11705 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11706 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11707 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11708
11709 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11710
11711 assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
11712
11713 /* Don't treat parts of a composite relocation as done. There are two
11714 reasons for this:
11715
11716 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11717 should nevertheless be emitted if the first part is.
11718
11719 (2) In normal usage, composite relocations are never assembly-time
11720 constants. The easiest way of dealing with the pathological
11721 exceptions is to generate a relocation against STN_UNDEF and
11722 leave everything up to the linker. */
11723 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
11724 fixP->fx_done = 1;
11725
11726 switch (fixP->fx_r_type)
11727 {
11728 case BFD_RELOC_MIPS_TLS_GD:
11729 case BFD_RELOC_MIPS_TLS_LDM:
11730 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
11731 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
11732 case BFD_RELOC_MIPS_TLS_GOTTPREL:
11733 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
11734 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
11735 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11736 /* fall through */
11737
11738 case BFD_RELOC_MIPS_JMP:
11739 case BFD_RELOC_MIPS_SHIFT5:
11740 case BFD_RELOC_MIPS_SHIFT6:
11741 case BFD_RELOC_MIPS_GOT_DISP:
11742 case BFD_RELOC_MIPS_GOT_PAGE:
11743 case BFD_RELOC_MIPS_GOT_OFST:
11744 case BFD_RELOC_MIPS_SUB:
11745 case BFD_RELOC_MIPS_INSERT_A:
11746 case BFD_RELOC_MIPS_INSERT_B:
11747 case BFD_RELOC_MIPS_DELETE:
11748 case BFD_RELOC_MIPS_HIGHEST:
11749 case BFD_RELOC_MIPS_HIGHER:
11750 case BFD_RELOC_MIPS_SCN_DISP:
11751 case BFD_RELOC_MIPS_REL16:
11752 case BFD_RELOC_MIPS_RELGOT:
11753 case BFD_RELOC_MIPS_JALR:
11754 case BFD_RELOC_HI16:
11755 case BFD_RELOC_HI16_S:
11756 case BFD_RELOC_GPREL16:
11757 case BFD_RELOC_MIPS_LITERAL:
11758 case BFD_RELOC_MIPS_CALL16:
11759 case BFD_RELOC_MIPS_GOT16:
11760 case BFD_RELOC_GPREL32:
11761 case BFD_RELOC_MIPS_GOT_HI16:
11762 case BFD_RELOC_MIPS_GOT_LO16:
11763 case BFD_RELOC_MIPS_CALL_HI16:
11764 case BFD_RELOC_MIPS_CALL_LO16:
11765 case BFD_RELOC_MIPS16_GPREL:
11766 case BFD_RELOC_MIPS16_HI16:
11767 case BFD_RELOC_MIPS16_HI16_S:
11768 /* Nothing needed to do. The value comes from the reloc entry */
11769 break;
11770
11771 case BFD_RELOC_MIPS16_JMP:
11772 /* We currently always generate a reloc against a symbol, which
11773 means that we don't want an addend even if the symbol is
11774 defined. */
11775 *valP = 0;
11776 break;
11777
11778 case BFD_RELOC_64:
11779 /* This is handled like BFD_RELOC_32, but we output a sign
11780 extended value if we are only 32 bits. */
11781 if (fixP->fx_done)
11782 {
11783 if (8 <= sizeof (valueT))
11784 md_number_to_chars ((char *) buf, *valP, 8);
11785 else
11786 {
11787 valueT hiv;
11788
11789 if ((*valP & 0x80000000) != 0)
11790 hiv = 0xffffffff;
11791 else
11792 hiv = 0;
11793 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
11794 *valP, 4);
11795 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
11796 hiv, 4);
11797 }
11798 }
11799 break;
11800
11801 case BFD_RELOC_RVA:
11802 case BFD_RELOC_32:
11803 /* If we are deleting this reloc entry, we must fill in the
11804 value now. This can happen if we have a .word which is not
11805 resolved when it appears but is later defined. */
11806 if (fixP->fx_done)
11807 md_number_to_chars ((char *) buf, *valP, 4);
11808 break;
11809
11810 case BFD_RELOC_16:
11811 /* If we are deleting this reloc entry, we must fill in the
11812 value now. */
11813 if (fixP->fx_done)
11814 md_number_to_chars ((char *) buf, *valP, 2);
11815 break;
11816
11817 case BFD_RELOC_LO16:
11818 case BFD_RELOC_MIPS16_LO16:
11819 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11820 may be safe to remove, but if so it's not obvious. */
11821 /* When handling an embedded PIC switch statement, we can wind
11822 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11823 if (fixP->fx_done)
11824 {
11825 if (*valP + 0x8000 > 0xffff)
11826 as_bad_where (fixP->fx_file, fixP->fx_line,
11827 _("relocation overflow"));
11828 if (target_big_endian)
11829 buf += 2;
11830 md_number_to_chars ((char *) buf, *valP, 2);
11831 }
11832 break;
11833
11834 case BFD_RELOC_16_PCREL_S2:
11835 if ((*valP & 0x3) != 0)
11836 as_bad_where (fixP->fx_file, fixP->fx_line,
11837 _("Branch to misaligned address (%lx)"), (long) *valP);
11838
11839 /*
11840 * We need to save the bits in the instruction since fixup_segment()
11841 * might be deleting the relocation entry (i.e., a branch within
11842 * the current segment).
11843 */
11844 if (! fixP->fx_done)
11845 break;
11846
11847 /* update old instruction data */
11848 if (target_big_endian)
11849 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11850 else
11851 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11852
11853 if (*valP + 0x20000 <= 0x3ffff)
11854 {
11855 insn |= (*valP >> 2) & 0xffff;
11856 md_number_to_chars ((char *) buf, insn, 4);
11857 }
11858 else if (mips_pic == NO_PIC
11859 && fixP->fx_done
11860 && fixP->fx_frag->fr_address >= text_section->vma
11861 && (fixP->fx_frag->fr_address
11862 < text_section->vma + bfd_get_section_size (text_section))
11863 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11864 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11865 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11866 {
11867 /* The branch offset is too large. If this is an
11868 unconditional branch, and we are not generating PIC code,
11869 we can convert it to an absolute jump instruction. */
11870 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11871 insn = 0x0c000000; /* jal */
11872 else
11873 insn = 0x08000000; /* j */
11874 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11875 fixP->fx_done = 0;
11876 fixP->fx_addsy = section_symbol (text_section);
11877 *valP += md_pcrel_from (fixP);
11878 md_number_to_chars ((char *) buf, insn, 4);
11879 }
11880 else
11881 {
11882 /* If we got here, we have branch-relaxation disabled,
11883 and there's nothing we can do to fix this instruction
11884 without turning it into a longer sequence. */
11885 as_bad_where (fixP->fx_file, fixP->fx_line,
11886 _("Branch out of range"));
11887 }
11888 break;
11889
11890 case BFD_RELOC_VTABLE_INHERIT:
11891 fixP->fx_done = 0;
11892 if (fixP->fx_addsy
11893 && !S_IS_DEFINED (fixP->fx_addsy)
11894 && !S_IS_WEAK (fixP->fx_addsy))
11895 S_SET_WEAK (fixP->fx_addsy);
11896 break;
11897
11898 case BFD_RELOC_VTABLE_ENTRY:
11899 fixP->fx_done = 0;
11900 break;
11901
11902 default:
11903 internalError ();
11904 }
11905
11906 /* Remember value for tc_gen_reloc. */
11907 fixP->fx_addnumber = *valP;
11908 }
11909
11910 static symbolS *
11911 get_symbol (void)
11912 {
11913 int c;
11914 char *name;
11915 symbolS *p;
11916
11917 name = input_line_pointer;
11918 c = get_symbol_end ();
11919 p = (symbolS *) symbol_find_or_make (name);
11920 *input_line_pointer = c;
11921 return p;
11922 }
11923
11924 /* Align the current frag to a given power of two. The MIPS assembler
11925 also automatically adjusts any preceding label. */
11926
11927 static void
11928 mips_align (int to, int fill, symbolS *label)
11929 {
11930 mips_emit_delays ();
11931 frag_align (to, fill, 0);
11932 record_alignment (now_seg, to);
11933 if (label != NULL)
11934 {
11935 assert (S_GET_SEGMENT (label) == now_seg);
11936 symbol_set_frag (label, frag_now);
11937 S_SET_VALUE (label, (valueT) frag_now_fix ());
11938 }
11939 }
11940
11941 /* Align to a given power of two. .align 0 turns off the automatic
11942 alignment used by the data creating pseudo-ops. */
11943
11944 static void
11945 s_align (int x ATTRIBUTE_UNUSED)
11946 {
11947 register int temp;
11948 register long temp_fill;
11949 long max_alignment = 15;
11950
11951 /*
11952
11953 o Note that the assembler pulls down any immediately preceding label
11954 to the aligned address.
11955 o It's not documented but auto alignment is reinstated by
11956 a .align pseudo instruction.
11957 o Note also that after auto alignment is turned off the mips assembler
11958 issues an error on attempt to assemble an improperly aligned data item.
11959 We don't.
11960
11961 */
11962
11963 temp = get_absolute_expression ();
11964 if (temp > max_alignment)
11965 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11966 else if (temp < 0)
11967 {
11968 as_warn (_("Alignment negative: 0 assumed."));
11969 temp = 0;
11970 }
11971 if (*input_line_pointer == ',')
11972 {
11973 ++input_line_pointer;
11974 temp_fill = get_absolute_expression ();
11975 }
11976 else
11977 temp_fill = 0;
11978 if (temp)
11979 {
11980 auto_align = 1;
11981 mips_align (temp, (int) temp_fill,
11982 insn_labels != NULL ? insn_labels->label : NULL);
11983 }
11984 else
11985 {
11986 auto_align = 0;
11987 }
11988
11989 demand_empty_rest_of_line ();
11990 }
11991
11992 static void
11993 s_change_sec (int sec)
11994 {
11995 segT seg;
11996
11997 #ifdef OBJ_ELF
11998 /* The ELF backend needs to know that we are changing sections, so
11999 that .previous works correctly. We could do something like check
12000 for an obj_section_change_hook macro, but that might be confusing
12001 as it would not be appropriate to use it in the section changing
12002 functions in read.c, since obj-elf.c intercepts those. FIXME:
12003 This should be cleaner, somehow. */
12004 obj_elf_section_change_hook ();
12005 #endif
12006
12007 mips_emit_delays ();
12008 switch (sec)
12009 {
12010 case 't':
12011 s_text (0);
12012 break;
12013 case 'd':
12014 s_data (0);
12015 break;
12016 case 'b':
12017 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12018 demand_empty_rest_of_line ();
12019 break;
12020
12021 case 'r':
12022 seg = subseg_new (RDATA_SECTION_NAME,
12023 (subsegT) get_absolute_expression ());
12024 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12025 {
12026 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12027 | SEC_READONLY | SEC_RELOC
12028 | SEC_DATA));
12029 if (strcmp (TARGET_OS, "elf") != 0)
12030 record_alignment (seg, 4);
12031 }
12032 demand_empty_rest_of_line ();
12033 break;
12034
12035 case 's':
12036 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12037 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12038 {
12039 bfd_set_section_flags (stdoutput, seg,
12040 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12041 if (strcmp (TARGET_OS, "elf") != 0)
12042 record_alignment (seg, 4);
12043 }
12044 demand_empty_rest_of_line ();
12045 break;
12046 }
12047
12048 auto_align = 1;
12049 }
12050
12051 void
12052 s_change_section (int ignore ATTRIBUTE_UNUSED)
12053 {
12054 #ifdef OBJ_ELF
12055 char *section_name;
12056 char c;
12057 char next_c = 0;
12058 int section_type;
12059 int section_flag;
12060 int section_entry_size;
12061 int section_alignment;
12062
12063 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12064 return;
12065
12066 section_name = input_line_pointer;
12067 c = get_symbol_end ();
12068 if (c)
12069 next_c = *(input_line_pointer + 1);
12070
12071 /* Do we have .section Name<,"flags">? */
12072 if (c != ',' || (c == ',' && next_c == '"'))
12073 {
12074 /* just after name is now '\0'. */
12075 *input_line_pointer = c;
12076 input_line_pointer = section_name;
12077 obj_elf_section (ignore);
12078 return;
12079 }
12080 input_line_pointer++;
12081
12082 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12083 if (c == ',')
12084 section_type = get_absolute_expression ();
12085 else
12086 section_type = 0;
12087 if (*input_line_pointer++ == ',')
12088 section_flag = get_absolute_expression ();
12089 else
12090 section_flag = 0;
12091 if (*input_line_pointer++ == ',')
12092 section_entry_size = get_absolute_expression ();
12093 else
12094 section_entry_size = 0;
12095 if (*input_line_pointer++ == ',')
12096 section_alignment = get_absolute_expression ();
12097 else
12098 section_alignment = 0;
12099
12100 section_name = xstrdup (section_name);
12101
12102 /* When using the generic form of .section (as implemented by obj-elf.c),
12103 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12104 traditionally had to fall back on the more common @progbits instead.
12105
12106 There's nothing really harmful in this, since bfd will correct
12107 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12108 means that, for backwards compatibility, the special_section entries
12109 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12110
12111 Even so, we shouldn't force users of the MIPS .section syntax to
12112 incorrectly label the sections as SHT_PROGBITS. The best compromise
12113 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12114 generic type-checking code. */
12115 if (section_type == SHT_MIPS_DWARF)
12116 section_type = SHT_PROGBITS;
12117
12118 obj_elf_change_section (section_name, section_type, section_flag,
12119 section_entry_size, 0, 0, 0);
12120
12121 if (now_seg->name != section_name)
12122 free (section_name);
12123 #endif /* OBJ_ELF */
12124 }
12125
12126 void
12127 mips_enable_auto_align (void)
12128 {
12129 auto_align = 1;
12130 }
12131
12132 static void
12133 s_cons (int log_size)
12134 {
12135 symbolS *label;
12136
12137 label = insn_labels != NULL ? insn_labels->label : NULL;
12138 mips_emit_delays ();
12139 if (log_size > 0 && auto_align)
12140 mips_align (log_size, 0, label);
12141 mips_clear_insn_labels ();
12142 cons (1 << log_size);
12143 }
12144
12145 static void
12146 s_float_cons (int type)
12147 {
12148 symbolS *label;
12149
12150 label = insn_labels != NULL ? insn_labels->label : NULL;
12151
12152 mips_emit_delays ();
12153
12154 if (auto_align)
12155 {
12156 if (type == 'd')
12157 mips_align (3, 0, label);
12158 else
12159 mips_align (2, 0, label);
12160 }
12161
12162 mips_clear_insn_labels ();
12163
12164 float_cons (type);
12165 }
12166
12167 /* Handle .globl. We need to override it because on Irix 5 you are
12168 permitted to say
12169 .globl foo .text
12170 where foo is an undefined symbol, to mean that foo should be
12171 considered to be the address of a function. */
12172
12173 static void
12174 s_mips_globl (int x ATTRIBUTE_UNUSED)
12175 {
12176 char *name;
12177 int c;
12178 symbolS *symbolP;
12179 flagword flag;
12180
12181 do
12182 {
12183 name = input_line_pointer;
12184 c = get_symbol_end ();
12185 symbolP = symbol_find_or_make (name);
12186 S_SET_EXTERNAL (symbolP);
12187
12188 *input_line_pointer = c;
12189 SKIP_WHITESPACE ();
12190
12191 /* On Irix 5, every global symbol that is not explicitly labelled as
12192 being a function is apparently labelled as being an object. */
12193 flag = BSF_OBJECT;
12194
12195 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12196 && (*input_line_pointer != ','))
12197 {
12198 char *secname;
12199 asection *sec;
12200
12201 secname = input_line_pointer;
12202 c = get_symbol_end ();
12203 sec = bfd_get_section_by_name (stdoutput, secname);
12204 if (sec == NULL)
12205 as_bad (_("%s: no such section"), secname);
12206 *input_line_pointer = c;
12207
12208 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12209 flag = BSF_FUNCTION;
12210 }
12211
12212 symbol_get_bfdsym (symbolP)->flags |= flag;
12213
12214 c = *input_line_pointer;
12215 if (c == ',')
12216 {
12217 input_line_pointer++;
12218 SKIP_WHITESPACE ();
12219 if (is_end_of_line[(unsigned char) *input_line_pointer])
12220 c = '\n';
12221 }
12222 }
12223 while (c == ',');
12224
12225 demand_empty_rest_of_line ();
12226 }
12227
12228 static void
12229 s_option (int x ATTRIBUTE_UNUSED)
12230 {
12231 char *opt;
12232 char c;
12233
12234 opt = input_line_pointer;
12235 c = get_symbol_end ();
12236
12237 if (*opt == 'O')
12238 {
12239 /* FIXME: What does this mean? */
12240 }
12241 else if (strncmp (opt, "pic", 3) == 0)
12242 {
12243 int i;
12244
12245 i = atoi (opt + 3);
12246 if (i == 0)
12247 mips_pic = NO_PIC;
12248 else if (i == 2)
12249 {
12250 mips_pic = SVR4_PIC;
12251 mips_abicalls = TRUE;
12252 }
12253 else
12254 as_bad (_(".option pic%d not supported"), i);
12255
12256 if (mips_pic == SVR4_PIC)
12257 {
12258 if (g_switch_seen && g_switch_value != 0)
12259 as_warn (_("-G may not be used with SVR4 PIC code"));
12260 g_switch_value = 0;
12261 bfd_set_gp_size (stdoutput, 0);
12262 }
12263 }
12264 else
12265 as_warn (_("Unrecognized option \"%s\""), opt);
12266
12267 *input_line_pointer = c;
12268 demand_empty_rest_of_line ();
12269 }
12270
12271 /* This structure is used to hold a stack of .set values. */
12272
12273 struct mips_option_stack
12274 {
12275 struct mips_option_stack *next;
12276 struct mips_set_options options;
12277 };
12278
12279 static struct mips_option_stack *mips_opts_stack;
12280
12281 /* Handle the .set pseudo-op. */
12282
12283 static void
12284 s_mipsset (int x ATTRIBUTE_UNUSED)
12285 {
12286 char *name = input_line_pointer, ch;
12287
12288 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12289 ++input_line_pointer;
12290 ch = *input_line_pointer;
12291 *input_line_pointer = '\0';
12292
12293 if (strcmp (name, "reorder") == 0)
12294 {
12295 if (mips_opts.noreorder)
12296 end_noreorder ();
12297 }
12298 else if (strcmp (name, "noreorder") == 0)
12299 {
12300 if (!mips_opts.noreorder)
12301 start_noreorder ();
12302 }
12303 else if (strcmp (name, "at") == 0)
12304 {
12305 mips_opts.noat = 0;
12306 }
12307 else if (strcmp (name, "noat") == 0)
12308 {
12309 mips_opts.noat = 1;
12310 }
12311 else if (strcmp (name, "macro") == 0)
12312 {
12313 mips_opts.warn_about_macros = 0;
12314 }
12315 else if (strcmp (name, "nomacro") == 0)
12316 {
12317 if (mips_opts.noreorder == 0)
12318 as_bad (_("`noreorder' must be set before `nomacro'"));
12319 mips_opts.warn_about_macros = 1;
12320 }
12321 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12322 {
12323 mips_opts.nomove = 0;
12324 }
12325 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12326 {
12327 mips_opts.nomove = 1;
12328 }
12329 else if (strcmp (name, "bopt") == 0)
12330 {
12331 mips_opts.nobopt = 0;
12332 }
12333 else if (strcmp (name, "nobopt") == 0)
12334 {
12335 mips_opts.nobopt = 1;
12336 }
12337 else if (strcmp (name, "gp=default") == 0)
12338 mips_opts.gp32 = file_mips_gp32;
12339 else if (strcmp (name, "gp=32") == 0)
12340 mips_opts.gp32 = 1;
12341 else if (strcmp (name, "gp=64") == 0)
12342 {
12343 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12344 as_warn ("%s isa does not support 64-bit registers",
12345 mips_cpu_info_from_isa (mips_opts.isa)->name);
12346 mips_opts.gp32 = 0;
12347 }
12348 else if (strcmp (name, "fp=default") == 0)
12349 mips_opts.fp32 = file_mips_fp32;
12350 else if (strcmp (name, "fp=32") == 0)
12351 mips_opts.fp32 = 1;
12352 else if (strcmp (name, "fp=64") == 0)
12353 {
12354 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12355 as_warn ("%s isa does not support 64-bit floating point registers",
12356 mips_cpu_info_from_isa (mips_opts.isa)->name);
12357 mips_opts.fp32 = 0;
12358 }
12359 else if (strcmp (name, "mips16") == 0
12360 || strcmp (name, "MIPS-16") == 0)
12361 mips_opts.mips16 = 1;
12362 else if (strcmp (name, "nomips16") == 0
12363 || strcmp (name, "noMIPS-16") == 0)
12364 mips_opts.mips16 = 0;
12365 else if (strcmp (name, "smartmips") == 0)
12366 {
12367 if (!ISA_SUPPORTS_SMARTMIPS)
12368 as_warn ("%s ISA does not support SmartMIPS ASE",
12369 mips_cpu_info_from_isa (mips_opts.isa)->name);
12370 mips_opts.ase_smartmips = 1;
12371 }
12372 else if (strcmp (name, "nosmartmips") == 0)
12373 mips_opts.ase_smartmips = 0;
12374 else if (strcmp (name, "mips3d") == 0)
12375 mips_opts.ase_mips3d = 1;
12376 else if (strcmp (name, "nomips3d") == 0)
12377 mips_opts.ase_mips3d = 0;
12378 else if (strcmp (name, "mdmx") == 0)
12379 mips_opts.ase_mdmx = 1;
12380 else if (strcmp (name, "nomdmx") == 0)
12381 mips_opts.ase_mdmx = 0;
12382 else if (strcmp (name, "dsp") == 0)
12383 {
12384 if (!ISA_SUPPORTS_DSP_ASE)
12385 as_warn ("%s ISA does not support DSP ASE",
12386 mips_cpu_info_from_isa (mips_opts.isa)->name);
12387 mips_opts.ase_dsp = 1;
12388 }
12389 else if (strcmp (name, "nodsp") == 0)
12390 mips_opts.ase_dsp = 0;
12391 else if (strcmp (name, "mt") == 0)
12392 {
12393 if (!ISA_SUPPORTS_MT_ASE)
12394 as_warn ("%s ISA does not support MT ASE",
12395 mips_cpu_info_from_isa (mips_opts.isa)->name);
12396 mips_opts.ase_mt = 1;
12397 }
12398 else if (strcmp (name, "nomt") == 0)
12399 mips_opts.ase_mt = 0;
12400 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12401 {
12402 int reset = 0;
12403
12404 /* Permit the user to change the ISA and architecture on the fly.
12405 Needless to say, misuse can cause serious problems. */
12406 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
12407 {
12408 reset = 1;
12409 mips_opts.isa = file_mips_isa;
12410 mips_opts.arch = file_mips_arch;
12411 }
12412 else if (strncmp (name, "arch=", 5) == 0)
12413 {
12414 const struct mips_cpu_info *p;
12415
12416 p = mips_parse_cpu("internal use", name + 5);
12417 if (!p)
12418 as_bad (_("unknown architecture %s"), name + 5);
12419 else
12420 {
12421 mips_opts.arch = p->cpu;
12422 mips_opts.isa = p->isa;
12423 }
12424 }
12425 else if (strncmp (name, "mips", 4) == 0)
12426 {
12427 const struct mips_cpu_info *p;
12428
12429 p = mips_parse_cpu("internal use", name);
12430 if (!p)
12431 as_bad (_("unknown ISA level %s"), name + 4);
12432 else
12433 {
12434 mips_opts.arch = p->cpu;
12435 mips_opts.isa = p->isa;
12436 }
12437 }
12438 else
12439 as_bad (_("unknown ISA or architecture %s"), name);
12440
12441 switch (mips_opts.isa)
12442 {
12443 case 0:
12444 break;
12445 case ISA_MIPS1:
12446 case ISA_MIPS2:
12447 case ISA_MIPS32:
12448 case ISA_MIPS32R2:
12449 mips_opts.gp32 = 1;
12450 mips_opts.fp32 = 1;
12451 break;
12452 case ISA_MIPS3:
12453 case ISA_MIPS4:
12454 case ISA_MIPS5:
12455 case ISA_MIPS64:
12456 case ISA_MIPS64R2:
12457 mips_opts.gp32 = 0;
12458 mips_opts.fp32 = 0;
12459 break;
12460 default:
12461 as_bad (_("unknown ISA level %s"), name + 4);
12462 break;
12463 }
12464 if (reset)
12465 {
12466 mips_opts.gp32 = file_mips_gp32;
12467 mips_opts.fp32 = file_mips_fp32;
12468 }
12469 }
12470 else if (strcmp (name, "autoextend") == 0)
12471 mips_opts.noautoextend = 0;
12472 else if (strcmp (name, "noautoextend") == 0)
12473 mips_opts.noautoextend = 1;
12474 else if (strcmp (name, "push") == 0)
12475 {
12476 struct mips_option_stack *s;
12477
12478 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12479 s->next = mips_opts_stack;
12480 s->options = mips_opts;
12481 mips_opts_stack = s;
12482 }
12483 else if (strcmp (name, "pop") == 0)
12484 {
12485 struct mips_option_stack *s;
12486
12487 s = mips_opts_stack;
12488 if (s == NULL)
12489 as_bad (_(".set pop with no .set push"));
12490 else
12491 {
12492 /* If we're changing the reorder mode we need to handle
12493 delay slots correctly. */
12494 if (s->options.noreorder && ! mips_opts.noreorder)
12495 start_noreorder ();
12496 else if (! s->options.noreorder && mips_opts.noreorder)
12497 end_noreorder ();
12498
12499 mips_opts = s->options;
12500 mips_opts_stack = s->next;
12501 free (s);
12502 }
12503 }
12504 else if (strcmp (name, "sym32") == 0)
12505 mips_opts.sym32 = TRUE;
12506 else if (strcmp (name, "nosym32") == 0)
12507 mips_opts.sym32 = FALSE;
12508 else
12509 {
12510 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12511 }
12512 *input_line_pointer = ch;
12513 demand_empty_rest_of_line ();
12514 }
12515
12516 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12517 .option pic2. It means to generate SVR4 PIC calls. */
12518
12519 static void
12520 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12521 {
12522 mips_pic = SVR4_PIC;
12523 mips_abicalls = TRUE;
12524
12525 if (g_switch_seen && g_switch_value != 0)
12526 as_warn (_("-G may not be used with SVR4 PIC code"));
12527 g_switch_value = 0;
12528
12529 bfd_set_gp_size (stdoutput, 0);
12530 demand_empty_rest_of_line ();
12531 }
12532
12533 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12534 PIC code. It sets the $gp register for the function based on the
12535 function address, which is in the register named in the argument.
12536 This uses a relocation against _gp_disp, which is handled specially
12537 by the linker. The result is:
12538 lui $gp,%hi(_gp_disp)
12539 addiu $gp,$gp,%lo(_gp_disp)
12540 addu $gp,$gp,.cpload argument
12541 The .cpload argument is normally $25 == $t9.
12542
12543 The -mno-shared option changes this to:
12544 lui $gp,%hi(__gnu_local_gp)
12545 addiu $gp,$gp,%lo(__gnu_local_gp)
12546 and the argument is ignored. This saves an instruction, but the
12547 resulting code is not position independent; it uses an absolute
12548 address for __gnu_local_gp. Thus code assembled with -mno-shared
12549 can go into an ordinary executable, but not into a shared library. */
12550
12551 static void
12552 s_cpload (int ignore ATTRIBUTE_UNUSED)
12553 {
12554 expressionS ex;
12555 int reg;
12556 int in_shared;
12557
12558 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12559 .cpload is ignored. */
12560 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12561 {
12562 s_ignore (0);
12563 return;
12564 }
12565
12566 /* .cpload should be in a .set noreorder section. */
12567 if (mips_opts.noreorder == 0)
12568 as_warn (_(".cpload not in noreorder section"));
12569
12570 reg = tc_get_register (0);
12571
12572 /* If we need to produce a 64-bit address, we are better off using
12573 the default instruction sequence. */
12574 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
12575
12576 ex.X_op = O_symbol;
12577 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
12578 "__gnu_local_gp");
12579 ex.X_op_symbol = NULL;
12580 ex.X_add_number = 0;
12581
12582 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12583 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12584
12585 macro_start ();
12586 macro_build_lui (&ex, mips_gp_register);
12587 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12588 mips_gp_register, BFD_RELOC_LO16);
12589 if (in_shared)
12590 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12591 mips_gp_register, reg);
12592 macro_end ();
12593
12594 demand_empty_rest_of_line ();
12595 }
12596
12597 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12598 .cpsetup $reg1, offset|$reg2, label
12599
12600 If offset is given, this results in:
12601 sd $gp, offset($sp)
12602 lui $gp, %hi(%neg(%gp_rel(label)))
12603 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12604 daddu $gp, $gp, $reg1
12605
12606 If $reg2 is given, this results in:
12607 daddu $reg2, $gp, $0
12608 lui $gp, %hi(%neg(%gp_rel(label)))
12609 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12610 daddu $gp, $gp, $reg1
12611 $reg1 is normally $25 == $t9.
12612
12613 The -mno-shared option replaces the last three instructions with
12614 lui $gp,%hi(_gp)
12615 addiu $gp,$gp,%lo(_gp)
12616 */
12617
12618 static void
12619 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12620 {
12621 expressionS ex_off;
12622 expressionS ex_sym;
12623 int reg1;
12624
12625 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12626 We also need NewABI support. */
12627 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12628 {
12629 s_ignore (0);
12630 return;
12631 }
12632
12633 reg1 = tc_get_register (0);
12634 SKIP_WHITESPACE ();
12635 if (*input_line_pointer != ',')
12636 {
12637 as_bad (_("missing argument separator ',' for .cpsetup"));
12638 return;
12639 }
12640 else
12641 ++input_line_pointer;
12642 SKIP_WHITESPACE ();
12643 if (*input_line_pointer == '$')
12644 {
12645 mips_cpreturn_register = tc_get_register (0);
12646 mips_cpreturn_offset = -1;
12647 }
12648 else
12649 {
12650 mips_cpreturn_offset = get_absolute_expression ();
12651 mips_cpreturn_register = -1;
12652 }
12653 SKIP_WHITESPACE ();
12654 if (*input_line_pointer != ',')
12655 {
12656 as_bad (_("missing argument separator ',' for .cpsetup"));
12657 return;
12658 }
12659 else
12660 ++input_line_pointer;
12661 SKIP_WHITESPACE ();
12662 expression (&ex_sym);
12663
12664 macro_start ();
12665 if (mips_cpreturn_register == -1)
12666 {
12667 ex_off.X_op = O_constant;
12668 ex_off.X_add_symbol = NULL;
12669 ex_off.X_op_symbol = NULL;
12670 ex_off.X_add_number = mips_cpreturn_offset;
12671
12672 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12673 BFD_RELOC_LO16, SP);
12674 }
12675 else
12676 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12677 mips_gp_register, 0);
12678
12679 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
12680 {
12681 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
12682 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
12683 BFD_RELOC_HI16_S);
12684
12685 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12686 mips_gp_register, -1, BFD_RELOC_GPREL16,
12687 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
12688
12689 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12690 mips_gp_register, reg1);
12691 }
12692 else
12693 {
12694 expressionS ex;
12695
12696 ex.X_op = O_symbol;
12697 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
12698 ex.X_op_symbol = NULL;
12699 ex.X_add_number = 0;
12700
12701 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12702 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12703
12704 macro_build_lui (&ex, mips_gp_register);
12705 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12706 mips_gp_register, BFD_RELOC_LO16);
12707 }
12708
12709 macro_end ();
12710
12711 demand_empty_rest_of_line ();
12712 }
12713
12714 static void
12715 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12716 {
12717 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12718 .cplocal is ignored. */
12719 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12720 {
12721 s_ignore (0);
12722 return;
12723 }
12724
12725 mips_gp_register = tc_get_register (0);
12726 demand_empty_rest_of_line ();
12727 }
12728
12729 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12730 offset from $sp. The offset is remembered, and after making a PIC
12731 call $gp is restored from that location. */
12732
12733 static void
12734 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12735 {
12736 expressionS ex;
12737
12738 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12739 .cprestore is ignored. */
12740 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12741 {
12742 s_ignore (0);
12743 return;
12744 }
12745
12746 mips_cprestore_offset = get_absolute_expression ();
12747 mips_cprestore_valid = 1;
12748
12749 ex.X_op = O_constant;
12750 ex.X_add_symbol = NULL;
12751 ex.X_op_symbol = NULL;
12752 ex.X_add_number = mips_cprestore_offset;
12753
12754 macro_start ();
12755 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12756 SP, HAVE_64BIT_ADDRESSES);
12757 macro_end ();
12758
12759 demand_empty_rest_of_line ();
12760 }
12761
12762 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12763 was given in the preceding .cpsetup, it results in:
12764 ld $gp, offset($sp)
12765
12766 If a register $reg2 was given there, it results in:
12767 daddu $gp, $reg2, $0
12768 */
12769 static void
12770 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12771 {
12772 expressionS ex;
12773
12774 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12775 We also need NewABI support. */
12776 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12777 {
12778 s_ignore (0);
12779 return;
12780 }
12781
12782 macro_start ();
12783 if (mips_cpreturn_register == -1)
12784 {
12785 ex.X_op = O_constant;
12786 ex.X_add_symbol = NULL;
12787 ex.X_op_symbol = NULL;
12788 ex.X_add_number = mips_cpreturn_offset;
12789
12790 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12791 }
12792 else
12793 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12794 mips_cpreturn_register, 0);
12795 macro_end ();
12796
12797 demand_empty_rest_of_line ();
12798 }
12799
12800 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12801 code. It sets the offset to use in gp_rel relocations. */
12802
12803 static void
12804 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12805 {
12806 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12807 We also need NewABI support. */
12808 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12809 {
12810 s_ignore (0);
12811 return;
12812 }
12813
12814 mips_gprel_offset = get_absolute_expression ();
12815
12816 demand_empty_rest_of_line ();
12817 }
12818
12819 /* Handle the .gpword pseudo-op. This is used when generating PIC
12820 code. It generates a 32 bit GP relative reloc. */
12821
12822 static void
12823 s_gpword (int ignore ATTRIBUTE_UNUSED)
12824 {
12825 symbolS *label;
12826 expressionS ex;
12827 char *p;
12828
12829 /* When not generating PIC code, this is treated as .word. */
12830 if (mips_pic != SVR4_PIC)
12831 {
12832 s_cons (2);
12833 return;
12834 }
12835
12836 label = insn_labels != NULL ? insn_labels->label : NULL;
12837 mips_emit_delays ();
12838 if (auto_align)
12839 mips_align (2, 0, label);
12840 mips_clear_insn_labels ();
12841
12842 expression (&ex);
12843
12844 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12845 {
12846 as_bad (_("Unsupported use of .gpword"));
12847 ignore_rest_of_line ();
12848 }
12849
12850 p = frag_more (4);
12851 md_number_to_chars (p, 0, 4);
12852 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12853 BFD_RELOC_GPREL32);
12854
12855 demand_empty_rest_of_line ();
12856 }
12857
12858 static void
12859 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12860 {
12861 symbolS *label;
12862 expressionS ex;
12863 char *p;
12864
12865 /* When not generating PIC code, this is treated as .dword. */
12866 if (mips_pic != SVR4_PIC)
12867 {
12868 s_cons (3);
12869 return;
12870 }
12871
12872 label = insn_labels != NULL ? insn_labels->label : NULL;
12873 mips_emit_delays ();
12874 if (auto_align)
12875 mips_align (3, 0, label);
12876 mips_clear_insn_labels ();
12877
12878 expression (&ex);
12879
12880 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12881 {
12882 as_bad (_("Unsupported use of .gpdword"));
12883 ignore_rest_of_line ();
12884 }
12885
12886 p = frag_more (8);
12887 md_number_to_chars (p, 0, 8);
12888 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12889 BFD_RELOC_GPREL32)->fx_tcbit = 1;
12890
12891 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12892 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
12893 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
12894
12895 demand_empty_rest_of_line ();
12896 }
12897
12898 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12899 tables in SVR4 PIC code. */
12900
12901 static void
12902 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12903 {
12904 int reg;
12905
12906 /* This is ignored when not generating SVR4 PIC code. */
12907 if (mips_pic != SVR4_PIC)
12908 {
12909 s_ignore (0);
12910 return;
12911 }
12912
12913 /* Add $gp to the register named as an argument. */
12914 macro_start ();
12915 reg = tc_get_register (0);
12916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12917 macro_end ();
12918
12919 demand_empty_rest_of_line ();
12920 }
12921
12922 /* Handle the .insn pseudo-op. This marks instruction labels in
12923 mips16 mode. This permits the linker to handle them specially,
12924 such as generating jalx instructions when needed. We also make
12925 them odd for the duration of the assembly, in order to generate the
12926 right sort of code. We will make them even in the adjust_symtab
12927 routine, while leaving them marked. This is convenient for the
12928 debugger and the disassembler. The linker knows to make them odd
12929 again. */
12930
12931 static void
12932 s_insn (int ignore ATTRIBUTE_UNUSED)
12933 {
12934 mips16_mark_labels ();
12935
12936 demand_empty_rest_of_line ();
12937 }
12938
12939 /* Handle a .stabn directive. We need these in order to mark a label
12940 as being a mips16 text label correctly. Sometimes the compiler
12941 will emit a label, followed by a .stabn, and then switch sections.
12942 If the label and .stabn are in mips16 mode, then the label is
12943 really a mips16 text label. */
12944
12945 static void
12946 s_mips_stab (int type)
12947 {
12948 if (type == 'n')
12949 mips16_mark_labels ();
12950
12951 s_stab (type);
12952 }
12953
12954 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12955 */
12956
12957 static void
12958 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12959 {
12960 char *name;
12961 int c;
12962 symbolS *symbolP;
12963 expressionS exp;
12964
12965 name = input_line_pointer;
12966 c = get_symbol_end ();
12967 symbolP = symbol_find_or_make (name);
12968 S_SET_WEAK (symbolP);
12969 *input_line_pointer = c;
12970
12971 SKIP_WHITESPACE ();
12972
12973 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12974 {
12975 if (S_IS_DEFINED (symbolP))
12976 {
12977 as_bad ("ignoring attempt to redefine symbol %s",
12978 S_GET_NAME (symbolP));
12979 ignore_rest_of_line ();
12980 return;
12981 }
12982
12983 if (*input_line_pointer == ',')
12984 {
12985 ++input_line_pointer;
12986 SKIP_WHITESPACE ();
12987 }
12988
12989 expression (&exp);
12990 if (exp.X_op != O_symbol)
12991 {
12992 as_bad ("bad .weakext directive");
12993 ignore_rest_of_line ();
12994 return;
12995 }
12996 symbol_set_value_expression (symbolP, &exp);
12997 }
12998
12999 demand_empty_rest_of_line ();
13000 }
13001
13002 /* Parse a register string into a number. Called from the ECOFF code
13003 to parse .frame. The argument is non-zero if this is the frame
13004 register, so that we can record it in mips_frame_reg. */
13005
13006 int
13007 tc_get_register (int frame)
13008 {
13009 unsigned int reg;
13010
13011 SKIP_WHITESPACE ();
13012 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
13013 reg = 0;
13014 if (frame)
13015 {
13016 mips_frame_reg = reg != 0 ? reg : SP;
13017 mips_frame_reg_valid = 1;
13018 mips_cprestore_valid = 0;
13019 }
13020 return reg;
13021 }
13022
13023 valueT
13024 md_section_align (asection *seg, valueT addr)
13025 {
13026 int align = bfd_get_section_alignment (stdoutput, seg);
13027
13028 #ifdef OBJ_ELF
13029 /* We don't need to align ELF sections to the full alignment.
13030 However, Irix 5 may prefer that we align them at least to a 16
13031 byte boundary. We don't bother to align the sections if we are
13032 targeted for an embedded system. */
13033 if (strcmp (TARGET_OS, "elf") == 0)
13034 return addr;
13035 if (align > 4)
13036 align = 4;
13037 #endif
13038
13039 return ((addr + (1 << align) - 1) & (-1 << align));
13040 }
13041
13042 /* Utility routine, called from above as well. If called while the
13043 input file is still being read, it's only an approximation. (For
13044 example, a symbol may later become defined which appeared to be
13045 undefined earlier.) */
13046
13047 static int
13048 nopic_need_relax (symbolS *sym, int before_relaxing)
13049 {
13050 if (sym == 0)
13051 return 0;
13052
13053 if (g_switch_value > 0)
13054 {
13055 const char *symname;
13056 int change;
13057
13058 /* Find out whether this symbol can be referenced off the $gp
13059 register. It can be if it is smaller than the -G size or if
13060 it is in the .sdata or .sbss section. Certain symbols can
13061 not be referenced off the $gp, although it appears as though
13062 they can. */
13063 symname = S_GET_NAME (sym);
13064 if (symname != (const char *) NULL
13065 && (strcmp (symname, "eprol") == 0
13066 || strcmp (symname, "etext") == 0
13067 || strcmp (symname, "_gp") == 0
13068 || strcmp (symname, "edata") == 0
13069 || strcmp (symname, "_fbss") == 0
13070 || strcmp (symname, "_fdata") == 0
13071 || strcmp (symname, "_ftext") == 0
13072 || strcmp (symname, "end") == 0
13073 || strcmp (symname, "_gp_disp") == 0))
13074 change = 1;
13075 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13076 && (0
13077 #ifndef NO_ECOFF_DEBUGGING
13078 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13079 && (symbol_get_obj (sym)->ecoff_extern_size
13080 <= g_switch_value))
13081 #endif
13082 /* We must defer this decision until after the whole
13083 file has been read, since there might be a .extern
13084 after the first use of this symbol. */
13085 || (before_relaxing
13086 #ifndef NO_ECOFF_DEBUGGING
13087 && symbol_get_obj (sym)->ecoff_extern_size == 0
13088 #endif
13089 && S_GET_VALUE (sym) == 0)
13090 || (S_GET_VALUE (sym) != 0
13091 && S_GET_VALUE (sym) <= g_switch_value)))
13092 change = 0;
13093 else
13094 {
13095 const char *segname;
13096
13097 segname = segment_name (S_GET_SEGMENT (sym));
13098 assert (strcmp (segname, ".lit8") != 0
13099 && strcmp (segname, ".lit4") != 0);
13100 change = (strcmp (segname, ".sdata") != 0
13101 && strcmp (segname, ".sbss") != 0
13102 && strncmp (segname, ".sdata.", 7) != 0
13103 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13104 }
13105 return change;
13106 }
13107 else
13108 /* We are not optimizing for the $gp register. */
13109 return 1;
13110 }
13111
13112
13113 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13114
13115 static bfd_boolean
13116 pic_need_relax (symbolS *sym, asection *segtype)
13117 {
13118 asection *symsec;
13119 bfd_boolean linkonce;
13120
13121 /* Handle the case of a symbol equated to another symbol. */
13122 while (symbol_equated_reloc_p (sym))
13123 {
13124 symbolS *n;
13125
13126 /* It's possible to get a loop here in a badly written
13127 program. */
13128 n = symbol_get_value_expression (sym)->X_add_symbol;
13129 if (n == sym)
13130 break;
13131 sym = n;
13132 }
13133
13134 symsec = S_GET_SEGMENT (sym);
13135
13136 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13137 linkonce = FALSE;
13138 if (symsec != segtype && ! S_IS_LOCAL (sym))
13139 {
13140 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
13141 != 0)
13142 linkonce = TRUE;
13143
13144 /* The GNU toolchain uses an extension for ELF: a section
13145 beginning with the magic string .gnu.linkonce is a linkonce
13146 section. */
13147 if (strncmp (segment_name (symsec), ".gnu.linkonce",
13148 sizeof ".gnu.linkonce" - 1) == 0)
13149 linkonce = TRUE;
13150 }
13151
13152 /* This must duplicate the test in adjust_reloc_syms. */
13153 return (symsec != &bfd_und_section
13154 && symsec != &bfd_abs_section
13155 && ! bfd_is_com_section (symsec)
13156 && !linkonce
13157 #ifdef OBJ_ELF
13158 /* A global or weak symbol is treated as external. */
13159 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
13160 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13161 #endif
13162 );
13163 }
13164
13165
13166 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13167 extended opcode. SEC is the section the frag is in. */
13168
13169 static int
13170 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13171 {
13172 int type;
13173 register const struct mips16_immed_operand *op;
13174 offsetT val;
13175 int mintiny, maxtiny;
13176 segT symsec;
13177 fragS *sym_frag;
13178
13179 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13180 return 0;
13181 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13182 return 1;
13183
13184 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13185 op = mips16_immed_operands;
13186 while (op->type != type)
13187 {
13188 ++op;
13189 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13190 }
13191
13192 if (op->unsp)
13193 {
13194 if (type == '<' || type == '>' || type == '[' || type == ']')
13195 {
13196 mintiny = 1;
13197 maxtiny = 1 << op->nbits;
13198 }
13199 else
13200 {
13201 mintiny = 0;
13202 maxtiny = (1 << op->nbits) - 1;
13203 }
13204 }
13205 else
13206 {
13207 mintiny = - (1 << (op->nbits - 1));
13208 maxtiny = (1 << (op->nbits - 1)) - 1;
13209 }
13210
13211 sym_frag = symbol_get_frag (fragp->fr_symbol);
13212 val = S_GET_VALUE (fragp->fr_symbol);
13213 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13214
13215 if (op->pcrel)
13216 {
13217 addressT addr;
13218
13219 /* We won't have the section when we are called from
13220 mips_relax_frag. However, we will always have been called
13221 from md_estimate_size_before_relax first. If this is a
13222 branch to a different section, we mark it as such. If SEC is
13223 NULL, and the frag is not marked, then it must be a branch to
13224 the same section. */
13225 if (sec == NULL)
13226 {
13227 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13228 return 1;
13229 }
13230 else
13231 {
13232 /* Must have been called from md_estimate_size_before_relax. */
13233 if (symsec != sec)
13234 {
13235 fragp->fr_subtype =
13236 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13237
13238 /* FIXME: We should support this, and let the linker
13239 catch branches and loads that are out of range. */
13240 as_bad_where (fragp->fr_file, fragp->fr_line,
13241 _("unsupported PC relative reference to different section"));
13242
13243 return 1;
13244 }
13245 if (fragp != sym_frag && sym_frag->fr_address == 0)
13246 /* Assume non-extended on the first relaxation pass.
13247 The address we have calculated will be bogus if this is
13248 a forward branch to another frag, as the forward frag
13249 will have fr_address == 0. */
13250 return 0;
13251 }
13252
13253 /* In this case, we know for sure that the symbol fragment is in
13254 the same section. If the relax_marker of the symbol fragment
13255 differs from the relax_marker of this fragment, we have not
13256 yet adjusted the symbol fragment fr_address. We want to add
13257 in STRETCH in order to get a better estimate of the address.
13258 This particularly matters because of the shift bits. */
13259 if (stretch != 0
13260 && sym_frag->relax_marker != fragp->relax_marker)
13261 {
13262 fragS *f;
13263
13264 /* Adjust stretch for any alignment frag. Note that if have
13265 been expanding the earlier code, the symbol may be
13266 defined in what appears to be an earlier frag. FIXME:
13267 This doesn't handle the fr_subtype field, which specifies
13268 a maximum number of bytes to skip when doing an
13269 alignment. */
13270 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13271 {
13272 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13273 {
13274 if (stretch < 0)
13275 stretch = - ((- stretch)
13276 & ~ ((1 << (int) f->fr_offset) - 1));
13277 else
13278 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13279 if (stretch == 0)
13280 break;
13281 }
13282 }
13283 if (f != NULL)
13284 val += stretch;
13285 }
13286
13287 addr = fragp->fr_address + fragp->fr_fix;
13288
13289 /* The base address rules are complicated. The base address of
13290 a branch is the following instruction. The base address of a
13291 PC relative load or add is the instruction itself, but if it
13292 is in a delay slot (in which case it can not be extended) use
13293 the address of the instruction whose delay slot it is in. */
13294 if (type == 'p' || type == 'q')
13295 {
13296 addr += 2;
13297
13298 /* If we are currently assuming that this frag should be
13299 extended, then, the current address is two bytes
13300 higher. */
13301 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13302 addr += 2;
13303
13304 /* Ignore the low bit in the target, since it will be set
13305 for a text label. */
13306 if ((val & 1) != 0)
13307 --val;
13308 }
13309 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13310 addr -= 4;
13311 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13312 addr -= 2;
13313
13314 val -= addr & ~ ((1 << op->shift) - 1);
13315
13316 /* Branch offsets have an implicit 0 in the lowest bit. */
13317 if (type == 'p' || type == 'q')
13318 val /= 2;
13319
13320 /* If any of the shifted bits are set, we must use an extended
13321 opcode. If the address depends on the size of this
13322 instruction, this can lead to a loop, so we arrange to always
13323 use an extended opcode. We only check this when we are in
13324 the main relaxation loop, when SEC is NULL. */
13325 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13326 {
13327 fragp->fr_subtype =
13328 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13329 return 1;
13330 }
13331
13332 /* If we are about to mark a frag as extended because the value
13333 is precisely maxtiny + 1, then there is a chance of an
13334 infinite loop as in the following code:
13335 la $4,foo
13336 .skip 1020
13337 .align 2
13338 foo:
13339 In this case when the la is extended, foo is 0x3fc bytes
13340 away, so the la can be shrunk, but then foo is 0x400 away, so
13341 the la must be extended. To avoid this loop, we mark the
13342 frag as extended if it was small, and is about to become
13343 extended with a value of maxtiny + 1. */
13344 if (val == ((maxtiny + 1) << op->shift)
13345 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13346 && sec == NULL)
13347 {
13348 fragp->fr_subtype =
13349 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13350 return 1;
13351 }
13352 }
13353 else if (symsec != absolute_section && sec != NULL)
13354 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13355
13356 if ((val & ((1 << op->shift) - 1)) != 0
13357 || val < (mintiny << op->shift)
13358 || val > (maxtiny << op->shift))
13359 return 1;
13360 else
13361 return 0;
13362 }
13363
13364 /* Compute the length of a branch sequence, and adjust the
13365 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13366 worst-case length is computed, with UPDATE being used to indicate
13367 whether an unconditional (-1), branch-likely (+1) or regular (0)
13368 branch is to be computed. */
13369 static int
13370 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13371 {
13372 bfd_boolean toofar;
13373 int length;
13374
13375 if (fragp
13376 && S_IS_DEFINED (fragp->fr_symbol)
13377 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13378 {
13379 addressT addr;
13380 offsetT val;
13381
13382 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13383
13384 addr = fragp->fr_address + fragp->fr_fix + 4;
13385
13386 val -= addr;
13387
13388 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13389 }
13390 else if (fragp)
13391 /* If the symbol is not defined or it's in a different segment,
13392 assume the user knows what's going on and emit a short
13393 branch. */
13394 toofar = FALSE;
13395 else
13396 toofar = TRUE;
13397
13398 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13399 fragp->fr_subtype
13400 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13401 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13402 RELAX_BRANCH_LINK (fragp->fr_subtype),
13403 toofar);
13404
13405 length = 4;
13406 if (toofar)
13407 {
13408 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13409 length += 8;
13410
13411 if (mips_pic != NO_PIC)
13412 {
13413 /* Additional space for PIC loading of target address. */
13414 length += 8;
13415 if (mips_opts.isa == ISA_MIPS1)
13416 /* Additional space for $at-stabilizing nop. */
13417 length += 4;
13418 }
13419
13420 /* If branch is conditional. */
13421 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13422 length += 8;
13423 }
13424
13425 return length;
13426 }
13427
13428 /* Estimate the size of a frag before relaxing. Unless this is the
13429 mips16, we are not really relaxing here, and the final size is
13430 encoded in the subtype information. For the mips16, we have to
13431 decide whether we are using an extended opcode or not. */
13432
13433 int
13434 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13435 {
13436 int change;
13437
13438 if (RELAX_BRANCH_P (fragp->fr_subtype))
13439 {
13440
13441 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13442
13443 return fragp->fr_var;
13444 }
13445
13446 if (RELAX_MIPS16_P (fragp->fr_subtype))
13447 /* We don't want to modify the EXTENDED bit here; it might get us
13448 into infinite loops. We change it only in mips_relax_frag(). */
13449 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13450
13451 if (mips_pic == NO_PIC)
13452 change = nopic_need_relax (fragp->fr_symbol, 0);
13453 else if (mips_pic == SVR4_PIC)
13454 change = pic_need_relax (fragp->fr_symbol, segtype);
13455 else if (mips_pic == VXWORKS_PIC)
13456 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13457 change = 0;
13458 else
13459 abort ();
13460
13461 if (change)
13462 {
13463 fragp->fr_subtype |= RELAX_USE_SECOND;
13464 return -RELAX_FIRST (fragp->fr_subtype);
13465 }
13466 else
13467 return -RELAX_SECOND (fragp->fr_subtype);
13468 }
13469
13470 /* This is called to see whether a reloc against a defined symbol
13471 should be converted into a reloc against a section. */
13472
13473 int
13474 mips_fix_adjustable (fixS *fixp)
13475 {
13476 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13477 about the format of the offset in the .o file. */
13478 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13479 return 0;
13480
13481 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13482 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13483 return 0;
13484
13485 if (fixp->fx_addsy == NULL)
13486 return 1;
13487
13488 /* If symbol SYM is in a mergeable section, relocations of the form
13489 SYM + 0 can usually be made section-relative. The mergeable data
13490 is then identified by the section offset rather than by the symbol.
13491
13492 However, if we're generating REL LO16 relocations, the offset is split
13493 between the LO16 and parterning high part relocation. The linker will
13494 need to recalculate the complete offset in order to correctly identify
13495 the merge data.
13496
13497 The linker has traditionally not looked for the parterning high part
13498 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13499 placed anywhere. Rather than break backwards compatibility by changing
13500 this, it seems better not to force the issue, and instead keep the
13501 original symbol. This will work with either linker behavior. */
13502 if ((fixp->fx_r_type == BFD_RELOC_LO16
13503 || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16
13504 || reloc_needs_lo_p (fixp->fx_r_type))
13505 && HAVE_IN_PLACE_ADDENDS
13506 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13507 return 0;
13508
13509 #ifdef OBJ_ELF
13510 /* Don't adjust relocations against mips16 symbols, so that the linker
13511 can find them if it needs to set up a stub. */
13512 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13513 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13514 && fixp->fx_subsy == NULL)
13515 return 0;
13516 #endif
13517
13518 return 1;
13519 }
13520
13521 /* Translate internal representation of relocation info to BFD target
13522 format. */
13523
13524 arelent **
13525 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13526 {
13527 static arelent *retval[4];
13528 arelent *reloc;
13529 bfd_reloc_code_real_type code;
13530
13531 memset (retval, 0, sizeof(retval));
13532 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13533 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13534 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13535 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13536
13537 if (fixp->fx_pcrel)
13538 {
13539 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
13540
13541 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13542 Relocations want only the symbol offset. */
13543 reloc->addend = fixp->fx_addnumber + reloc->address;
13544 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13545 {
13546 /* A gruesome hack which is a result of the gruesome gas
13547 reloc handling. What's worse, for COFF (as opposed to
13548 ECOFF), we might need yet another copy of reloc->address.
13549 See bfd_install_relocation. */
13550 reloc->addend += reloc->address;
13551 }
13552 }
13553 else
13554 reloc->addend = fixp->fx_addnumber;
13555
13556 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13557 entry to be used in the relocation's section offset. */
13558 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13559 {
13560 reloc->address = reloc->addend;
13561 reloc->addend = 0;
13562 }
13563
13564 code = fixp->fx_r_type;
13565
13566 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13567 if (reloc->howto == NULL)
13568 {
13569 as_bad_where (fixp->fx_file, fixp->fx_line,
13570 _("Can not represent %s relocation in this object file format"),
13571 bfd_get_reloc_code_name (code));
13572 retval[0] = NULL;
13573 }
13574
13575 return retval;
13576 }
13577
13578 /* Relax a machine dependent frag. This returns the amount by which
13579 the current size of the frag should change. */
13580
13581 int
13582 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13583 {
13584 if (RELAX_BRANCH_P (fragp->fr_subtype))
13585 {
13586 offsetT old_var = fragp->fr_var;
13587
13588 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13589
13590 return fragp->fr_var - old_var;
13591 }
13592
13593 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13594 return 0;
13595
13596 if (mips16_extended_frag (fragp, NULL, stretch))
13597 {
13598 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13599 return 0;
13600 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13601 return 2;
13602 }
13603 else
13604 {
13605 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13606 return 0;
13607 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13608 return -2;
13609 }
13610
13611 return 0;
13612 }
13613
13614 /* Convert a machine dependent frag. */
13615
13616 void
13617 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13618 {
13619 if (RELAX_BRANCH_P (fragp->fr_subtype))
13620 {
13621 bfd_byte *buf;
13622 unsigned long insn;
13623 expressionS exp;
13624 fixS *fixp;
13625
13626 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13627
13628 if (target_big_endian)
13629 insn = bfd_getb32 (buf);
13630 else
13631 insn = bfd_getl32 (buf);
13632
13633 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13634 {
13635 /* We generate a fixup instead of applying it right now
13636 because, if there are linker relaxations, we're going to
13637 need the relocations. */
13638 exp.X_op = O_symbol;
13639 exp.X_add_symbol = fragp->fr_symbol;
13640 exp.X_add_number = fragp->fr_offset;
13641
13642 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13643 4, &exp, 1, BFD_RELOC_16_PCREL_S2);
13644 fixp->fx_file = fragp->fr_file;
13645 fixp->fx_line = fragp->fr_line;
13646
13647 md_number_to_chars ((char *) buf, insn, 4);
13648 buf += 4;
13649 }
13650 else
13651 {
13652 int i;
13653
13654 as_warn_where (fragp->fr_file, fragp->fr_line,
13655 _("relaxed out-of-range branch into a jump"));
13656
13657 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13658 goto uncond;
13659
13660 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13661 {
13662 /* Reverse the branch. */
13663 switch ((insn >> 28) & 0xf)
13664 {
13665 case 4:
13666 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13667 have the condition reversed by tweaking a single
13668 bit, and their opcodes all have 0x4???????. */
13669 assert ((insn & 0xf1000000) == 0x41000000);
13670 insn ^= 0x00010000;
13671 break;
13672
13673 case 0:
13674 /* bltz 0x04000000 bgez 0x04010000
13675 bltzal 0x04100000 bgezal 0x04110000 */
13676 assert ((insn & 0xfc0e0000) == 0x04000000);
13677 insn ^= 0x00010000;
13678 break;
13679
13680 case 1:
13681 /* beq 0x10000000 bne 0x14000000
13682 blez 0x18000000 bgtz 0x1c000000 */
13683 insn ^= 0x04000000;
13684 break;
13685
13686 default:
13687 abort ();
13688 }
13689 }
13690
13691 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13692 {
13693 /* Clear the and-link bit. */
13694 assert ((insn & 0xfc1c0000) == 0x04100000);
13695
13696 /* bltzal 0x04100000 bgezal 0x04110000
13697 bltzall 0x04120000 bgezall 0x04130000 */
13698 insn &= ~0x00100000;
13699 }
13700
13701 /* Branch over the branch (if the branch was likely) or the
13702 full jump (not likely case). Compute the offset from the
13703 current instruction to branch to. */
13704 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13705 i = 16;
13706 else
13707 {
13708 /* How many bytes in instructions we've already emitted? */
13709 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13710 /* How many bytes in instructions from here to the end? */
13711 i = fragp->fr_var - i;
13712 }
13713 /* Convert to instruction count. */
13714 i >>= 2;
13715 /* Branch counts from the next instruction. */
13716 i--;
13717 insn |= i;
13718 /* Branch over the jump. */
13719 md_number_to_chars ((char *) buf, insn, 4);
13720 buf += 4;
13721
13722 /* Nop */
13723 md_number_to_chars ((char *) buf, 0, 4);
13724 buf += 4;
13725
13726 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13727 {
13728 /* beql $0, $0, 2f */
13729 insn = 0x50000000;
13730 /* Compute the PC offset from the current instruction to
13731 the end of the variable frag. */
13732 /* How many bytes in instructions we've already emitted? */
13733 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13734 /* How many bytes in instructions from here to the end? */
13735 i = fragp->fr_var - i;
13736 /* Convert to instruction count. */
13737 i >>= 2;
13738 /* Don't decrement i, because we want to branch over the
13739 delay slot. */
13740
13741 insn |= i;
13742 md_number_to_chars ((char *) buf, insn, 4);
13743 buf += 4;
13744
13745 md_number_to_chars ((char *) buf, 0, 4);
13746 buf += 4;
13747 }
13748
13749 uncond:
13750 if (mips_pic == NO_PIC)
13751 {
13752 /* j or jal. */
13753 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13754 ? 0x0c000000 : 0x08000000);
13755 exp.X_op = O_symbol;
13756 exp.X_add_symbol = fragp->fr_symbol;
13757 exp.X_add_number = fragp->fr_offset;
13758
13759 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13760 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13761 fixp->fx_file = fragp->fr_file;
13762 fixp->fx_line = fragp->fr_line;
13763
13764 md_number_to_chars ((char *) buf, insn, 4);
13765 buf += 4;
13766 }
13767 else
13768 {
13769 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13770 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13771 exp.X_op = O_symbol;
13772 exp.X_add_symbol = fragp->fr_symbol;
13773 exp.X_add_number = fragp->fr_offset;
13774
13775 if (fragp->fr_offset)
13776 {
13777 exp.X_add_symbol = make_expr_symbol (&exp);
13778 exp.X_add_number = 0;
13779 }
13780
13781 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13782 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13783 fixp->fx_file = fragp->fr_file;
13784 fixp->fx_line = fragp->fr_line;
13785
13786 md_number_to_chars ((char *) buf, insn, 4);
13787 buf += 4;
13788
13789 if (mips_opts.isa == ISA_MIPS1)
13790 {
13791 /* nop */
13792 md_number_to_chars ((char *) buf, 0, 4);
13793 buf += 4;
13794 }
13795
13796 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13797 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13798
13799 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13800 4, &exp, 0, BFD_RELOC_LO16);
13801 fixp->fx_file = fragp->fr_file;
13802 fixp->fx_line = fragp->fr_line;
13803
13804 md_number_to_chars ((char *) buf, insn, 4);
13805 buf += 4;
13806
13807 /* j(al)r $at. */
13808 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13809 insn = 0x0020f809;
13810 else
13811 insn = 0x00200008;
13812
13813 md_number_to_chars ((char *) buf, insn, 4);
13814 buf += 4;
13815 }
13816 }
13817
13818 assert (buf == (bfd_byte *)fragp->fr_literal
13819 + fragp->fr_fix + fragp->fr_var);
13820
13821 fragp->fr_fix += fragp->fr_var;
13822
13823 return;
13824 }
13825
13826 if (RELAX_MIPS16_P (fragp->fr_subtype))
13827 {
13828 int type;
13829 register const struct mips16_immed_operand *op;
13830 bfd_boolean small, ext;
13831 offsetT val;
13832 bfd_byte *buf;
13833 unsigned long insn;
13834 bfd_boolean use_extend;
13835 unsigned short extend;
13836
13837 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13838 op = mips16_immed_operands;
13839 while (op->type != type)
13840 ++op;
13841
13842 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13843 {
13844 small = FALSE;
13845 ext = TRUE;
13846 }
13847 else
13848 {
13849 small = TRUE;
13850 ext = FALSE;
13851 }
13852
13853 resolve_symbol_value (fragp->fr_symbol);
13854 val = S_GET_VALUE (fragp->fr_symbol);
13855 if (op->pcrel)
13856 {
13857 addressT addr;
13858
13859 addr = fragp->fr_address + fragp->fr_fix;
13860
13861 /* The rules for the base address of a PC relative reloc are
13862 complicated; see mips16_extended_frag. */
13863 if (type == 'p' || type == 'q')
13864 {
13865 addr += 2;
13866 if (ext)
13867 addr += 2;
13868 /* Ignore the low bit in the target, since it will be
13869 set for a text label. */
13870 if ((val & 1) != 0)
13871 --val;
13872 }
13873 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13874 addr -= 4;
13875 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13876 addr -= 2;
13877
13878 addr &= ~ (addressT) ((1 << op->shift) - 1);
13879 val -= addr;
13880
13881 /* Make sure the section winds up with the alignment we have
13882 assumed. */
13883 if (op->shift > 0)
13884 record_alignment (asec, op->shift);
13885 }
13886
13887 if (ext
13888 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13889 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13890 as_warn_where (fragp->fr_file, fragp->fr_line,
13891 _("extended instruction in delay slot"));
13892
13893 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13894
13895 if (target_big_endian)
13896 insn = bfd_getb16 (buf);
13897 else
13898 insn = bfd_getl16 (buf);
13899
13900 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13901 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13902 small, ext, &insn, &use_extend, &extend);
13903
13904 if (use_extend)
13905 {
13906 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13907 fragp->fr_fix += 2;
13908 buf += 2;
13909 }
13910
13911 md_number_to_chars ((char *) buf, insn, 2);
13912 fragp->fr_fix += 2;
13913 buf += 2;
13914 }
13915 else
13916 {
13917 int first, second;
13918 fixS *fixp;
13919
13920 first = RELAX_FIRST (fragp->fr_subtype);
13921 second = RELAX_SECOND (fragp->fr_subtype);
13922 fixp = (fixS *) fragp->fr_opcode;
13923
13924 /* Possibly emit a warning if we've chosen the longer option. */
13925 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13926 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13927 {
13928 const char *msg = macro_warning (fragp->fr_subtype);
13929 if (msg != 0)
13930 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13931 }
13932
13933 /* Go through all the fixups for the first sequence. Disable them
13934 (by marking them as done) if we're going to use the second
13935 sequence instead. */
13936 while (fixp
13937 && fixp->fx_frag == fragp
13938 && fixp->fx_where < fragp->fr_fix - second)
13939 {
13940 if (fragp->fr_subtype & RELAX_USE_SECOND)
13941 fixp->fx_done = 1;
13942 fixp = fixp->fx_next;
13943 }
13944
13945 /* Go through the fixups for the second sequence. Disable them if
13946 we're going to use the first sequence, otherwise adjust their
13947 addresses to account for the relaxation. */
13948 while (fixp && fixp->fx_frag == fragp)
13949 {
13950 if (fragp->fr_subtype & RELAX_USE_SECOND)
13951 fixp->fx_where -= first;
13952 else
13953 fixp->fx_done = 1;
13954 fixp = fixp->fx_next;
13955 }
13956
13957 /* Now modify the frag contents. */
13958 if (fragp->fr_subtype & RELAX_USE_SECOND)
13959 {
13960 char *start;
13961
13962 start = fragp->fr_literal + fragp->fr_fix - first - second;
13963 memmove (start, start + first, second);
13964 fragp->fr_fix -= first;
13965 }
13966 else
13967 fragp->fr_fix -= second;
13968 }
13969 }
13970
13971 #ifdef OBJ_ELF
13972
13973 /* This function is called after the relocs have been generated.
13974 We've been storing mips16 text labels as odd. Here we convert them
13975 back to even for the convenience of the debugger. */
13976
13977 void
13978 mips_frob_file_after_relocs (void)
13979 {
13980 asymbol **syms;
13981 unsigned int count, i;
13982
13983 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13984 return;
13985
13986 syms = bfd_get_outsymbols (stdoutput);
13987 count = bfd_get_symcount (stdoutput);
13988 for (i = 0; i < count; i++, syms++)
13989 {
13990 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13991 && ((*syms)->value & 1) != 0)
13992 {
13993 (*syms)->value &= ~1;
13994 /* If the symbol has an odd size, it was probably computed
13995 incorrectly, so adjust that as well. */
13996 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13997 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13998 }
13999 }
14000 }
14001
14002 #endif
14003
14004 /* This function is called whenever a label is defined. It is used
14005 when handling branch delays; if a branch has a label, we assume we
14006 can not move it. */
14007
14008 void
14009 mips_define_label (symbolS *sym)
14010 {
14011 struct insn_label_list *l;
14012
14013 if (free_insn_labels == NULL)
14014 l = (struct insn_label_list *) xmalloc (sizeof *l);
14015 else
14016 {
14017 l = free_insn_labels;
14018 free_insn_labels = l->next;
14019 }
14020
14021 l->label = sym;
14022 l->next = insn_labels;
14023 insn_labels = l;
14024
14025 #ifdef OBJ_ELF
14026 dwarf2_emit_label (sym);
14027 #endif
14028 }
14029 \f
14030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14031
14032 /* Some special processing for a MIPS ELF file. */
14033
14034 void
14035 mips_elf_final_processing (void)
14036 {
14037 /* Write out the register information. */
14038 if (mips_abi != N64_ABI)
14039 {
14040 Elf32_RegInfo s;
14041
14042 s.ri_gprmask = mips_gprmask;
14043 s.ri_cprmask[0] = mips_cprmask[0];
14044 s.ri_cprmask[1] = mips_cprmask[1];
14045 s.ri_cprmask[2] = mips_cprmask[2];
14046 s.ri_cprmask[3] = mips_cprmask[3];
14047 /* The gp_value field is set by the MIPS ELF backend. */
14048
14049 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14050 ((Elf32_External_RegInfo *)
14051 mips_regmask_frag));
14052 }
14053 else
14054 {
14055 Elf64_Internal_RegInfo s;
14056
14057 s.ri_gprmask = mips_gprmask;
14058 s.ri_pad = 0;
14059 s.ri_cprmask[0] = mips_cprmask[0];
14060 s.ri_cprmask[1] = mips_cprmask[1];
14061 s.ri_cprmask[2] = mips_cprmask[2];
14062 s.ri_cprmask[3] = mips_cprmask[3];
14063 /* The gp_value field is set by the MIPS ELF backend. */
14064
14065 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14066 ((Elf64_External_RegInfo *)
14067 mips_regmask_frag));
14068 }
14069
14070 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14071 sort of BFD interface for this. */
14072 if (mips_any_noreorder)
14073 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14074 if (mips_pic != NO_PIC)
14075 {
14076 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14077 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14078 }
14079 if (mips_abicalls)
14080 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14081
14082 /* Set MIPS ELF flags for ASEs. */
14083 /* We may need to define a new flag for DSP ASE, and set this flag when
14084 file_ase_dsp is true. */
14085 /* We may need to define a new flag for MT ASE, and set this flag when
14086 file_ase_mt is true. */
14087 if (file_ase_mips16)
14088 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14089 #if 0 /* XXX FIXME */
14090 if (file_ase_mips3d)
14091 elf_elfheader (stdoutput)->e_flags |= ???;
14092 #endif
14093 if (file_ase_mdmx)
14094 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14095
14096 /* Set the MIPS ELF ABI flags. */
14097 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14098 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14099 else if (mips_abi == O64_ABI)
14100 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14101 else if (mips_abi == EABI_ABI)
14102 {
14103 if (!file_mips_gp32)
14104 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14105 else
14106 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14107 }
14108 else if (mips_abi == N32_ABI)
14109 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14110
14111 /* Nothing to do for N64_ABI. */
14112
14113 if (mips_32bitmode)
14114 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14115
14116 #if 0 /* XXX FIXME */
14117 /* 32 bit code with 64 bit FP registers. */
14118 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14119 elf_elfheader (stdoutput)->e_flags |= ???;
14120 #endif
14121 }
14122
14123 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14124 \f
14125 typedef struct proc {
14126 symbolS *func_sym;
14127 symbolS *func_end_sym;
14128 unsigned long reg_mask;
14129 unsigned long reg_offset;
14130 unsigned long fpreg_mask;
14131 unsigned long fpreg_offset;
14132 unsigned long frame_offset;
14133 unsigned long frame_reg;
14134 unsigned long pc_reg;
14135 } procS;
14136
14137 static procS cur_proc;
14138 static procS *cur_proc_ptr;
14139 static int numprocs;
14140
14141 /* Fill in an rs_align_code fragment. */
14142
14143 void
14144 mips_handle_align (fragS *fragp)
14145 {
14146 if (fragp->fr_type != rs_align_code)
14147 return;
14148
14149 if (mips_opts.mips16)
14150 {
14151 static const unsigned char be_nop[] = { 0x65, 0x00 };
14152 static const unsigned char le_nop[] = { 0x00, 0x65 };
14153
14154 int bytes;
14155 char *p;
14156
14157 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14158 p = fragp->fr_literal + fragp->fr_fix;
14159
14160 if (bytes & 1)
14161 {
14162 *p++ = 0;
14163 fragp->fr_fix++;
14164 }
14165
14166 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14167 fragp->fr_var = 2;
14168 }
14169
14170 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14171 }
14172
14173 static void
14174 md_obj_begin (void)
14175 {
14176 }
14177
14178 static void
14179 md_obj_end (void)
14180 {
14181 /* check for premature end, nesting errors, etc */
14182 if (cur_proc_ptr)
14183 as_warn (_("missing .end at end of assembly"));
14184 }
14185
14186 static long
14187 get_number (void)
14188 {
14189 int negative = 0;
14190 long val = 0;
14191
14192 if (*input_line_pointer == '-')
14193 {
14194 ++input_line_pointer;
14195 negative = 1;
14196 }
14197 if (!ISDIGIT (*input_line_pointer))
14198 as_bad (_("expected simple number"));
14199 if (input_line_pointer[0] == '0')
14200 {
14201 if (input_line_pointer[1] == 'x')
14202 {
14203 input_line_pointer += 2;
14204 while (ISXDIGIT (*input_line_pointer))
14205 {
14206 val <<= 4;
14207 val |= hex_value (*input_line_pointer++);
14208 }
14209 return negative ? -val : val;
14210 }
14211 else
14212 {
14213 ++input_line_pointer;
14214 while (ISDIGIT (*input_line_pointer))
14215 {
14216 val <<= 3;
14217 val |= *input_line_pointer++ - '0';
14218 }
14219 return negative ? -val : val;
14220 }
14221 }
14222 if (!ISDIGIT (*input_line_pointer))
14223 {
14224 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14225 *input_line_pointer, *input_line_pointer);
14226 as_warn (_("invalid number"));
14227 return -1;
14228 }
14229 while (ISDIGIT (*input_line_pointer))
14230 {
14231 val *= 10;
14232 val += *input_line_pointer++ - '0';
14233 }
14234 return negative ? -val : val;
14235 }
14236
14237 /* The .file directive; just like the usual .file directive, but there
14238 is an initial number which is the ECOFF file index. In the non-ECOFF
14239 case .file implies DWARF-2. */
14240
14241 static void
14242 s_mips_file (int x ATTRIBUTE_UNUSED)
14243 {
14244 static int first_file_directive = 0;
14245
14246 if (ECOFF_DEBUGGING)
14247 {
14248 get_number ();
14249 s_app_file (0);
14250 }
14251 else
14252 {
14253 char *filename;
14254
14255 filename = dwarf2_directive_file (0);
14256
14257 /* Versions of GCC up to 3.1 start files with a ".file"
14258 directive even for stabs output. Make sure that this
14259 ".file" is handled. Note that you need a version of GCC
14260 after 3.1 in order to support DWARF-2 on MIPS. */
14261 if (filename != NULL && ! first_file_directive)
14262 {
14263 (void) new_logical_line (filename, -1);
14264 s_app_file_string (filename, 0);
14265 }
14266 first_file_directive = 1;
14267 }
14268 }
14269
14270 /* The .loc directive, implying DWARF-2. */
14271
14272 static void
14273 s_mips_loc (int x ATTRIBUTE_UNUSED)
14274 {
14275 if (!ECOFF_DEBUGGING)
14276 dwarf2_directive_loc (0);
14277 }
14278
14279 /* The .end directive. */
14280
14281 static void
14282 s_mips_end (int x ATTRIBUTE_UNUSED)
14283 {
14284 symbolS *p;
14285
14286 /* Following functions need their own .frame and .cprestore directives. */
14287 mips_frame_reg_valid = 0;
14288 mips_cprestore_valid = 0;
14289
14290 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14291 {
14292 p = get_symbol ();
14293 demand_empty_rest_of_line ();
14294 }
14295 else
14296 p = NULL;
14297
14298 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14299 as_warn (_(".end not in text section"));
14300
14301 if (!cur_proc_ptr)
14302 {
14303 as_warn (_(".end directive without a preceding .ent directive."));
14304 demand_empty_rest_of_line ();
14305 return;
14306 }
14307
14308 if (p != NULL)
14309 {
14310 assert (S_GET_NAME (p));
14311 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
14312 as_warn (_(".end symbol does not match .ent symbol."));
14313
14314 if (debug_type == DEBUG_STABS)
14315 stabs_generate_asm_endfunc (S_GET_NAME (p),
14316 S_GET_NAME (p));
14317 }
14318 else
14319 as_warn (_(".end directive missing or unknown symbol"));
14320
14321 #ifdef OBJ_ELF
14322 /* Create an expression to calculate the size of the function. */
14323 if (p && cur_proc_ptr)
14324 {
14325 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
14326 expressionS *exp = xmalloc (sizeof (expressionS));
14327
14328 obj->size = exp;
14329 exp->X_op = O_subtract;
14330 exp->X_add_symbol = symbol_temp_new_now ();
14331 exp->X_op_symbol = p;
14332 exp->X_add_number = 0;
14333
14334 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14335 }
14336
14337 /* Generate a .pdr section. */
14338 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14339 && mips_flag_pdr)
14340 {
14341 segT saved_seg = now_seg;
14342 subsegT saved_subseg = now_subseg;
14343 valueT dot;
14344 expressionS exp;
14345 char *fragp;
14346
14347 dot = frag_now_fix ();
14348
14349 #ifdef md_flush_pending_output
14350 md_flush_pending_output ();
14351 #endif
14352
14353 assert (pdr_seg);
14354 subseg_set (pdr_seg, 0);
14355
14356 /* Write the symbol. */
14357 exp.X_op = O_symbol;
14358 exp.X_add_symbol = p;
14359 exp.X_add_number = 0;
14360 emit_expr (&exp, 4);
14361
14362 fragp = frag_more (7 * 4);
14363
14364 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14365 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14366 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14367 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14368 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14369 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14370 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14371
14372 subseg_set (saved_seg, saved_subseg);
14373 }
14374 #endif /* OBJ_ELF */
14375
14376 cur_proc_ptr = NULL;
14377 }
14378
14379 /* The .aent and .ent directives. */
14380
14381 static void
14382 s_mips_ent (int aent)
14383 {
14384 symbolS *symbolP;
14385
14386 symbolP = get_symbol ();
14387 if (*input_line_pointer == ',')
14388 ++input_line_pointer;
14389 SKIP_WHITESPACE ();
14390 if (ISDIGIT (*input_line_pointer)
14391 || *input_line_pointer == '-')
14392 get_number ();
14393
14394 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14395 as_warn (_(".ent or .aent not in text section."));
14396
14397 if (!aent && cur_proc_ptr)
14398 as_warn (_("missing .end"));
14399
14400 if (!aent)
14401 {
14402 /* This function needs its own .frame and .cprestore directives. */
14403 mips_frame_reg_valid = 0;
14404 mips_cprestore_valid = 0;
14405
14406 cur_proc_ptr = &cur_proc;
14407 memset (cur_proc_ptr, '\0', sizeof (procS));
14408
14409 cur_proc_ptr->func_sym = symbolP;
14410
14411 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14412
14413 ++numprocs;
14414
14415 if (debug_type == DEBUG_STABS)
14416 stabs_generate_asm_func (S_GET_NAME (symbolP),
14417 S_GET_NAME (symbolP));
14418 }
14419
14420 demand_empty_rest_of_line ();
14421 }
14422
14423 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14424 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14425 s_mips_frame is used so that we can set the PDR information correctly.
14426 We can't use the ecoff routines because they make reference to the ecoff
14427 symbol table (in the mdebug section). */
14428
14429 static void
14430 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14431 {
14432 #ifdef OBJ_ELF
14433 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14434 {
14435 long val;
14436
14437 if (cur_proc_ptr == (procS *) NULL)
14438 {
14439 as_warn (_(".frame outside of .ent"));
14440 demand_empty_rest_of_line ();
14441 return;
14442 }
14443
14444 cur_proc_ptr->frame_reg = tc_get_register (1);
14445
14446 SKIP_WHITESPACE ();
14447 if (*input_line_pointer++ != ','
14448 || get_absolute_expression_and_terminator (&val) != ',')
14449 {
14450 as_warn (_("Bad .frame directive"));
14451 --input_line_pointer;
14452 demand_empty_rest_of_line ();
14453 return;
14454 }
14455
14456 cur_proc_ptr->frame_offset = val;
14457 cur_proc_ptr->pc_reg = tc_get_register (0);
14458
14459 demand_empty_rest_of_line ();
14460 }
14461 else
14462 #endif /* OBJ_ELF */
14463 s_ignore (ignore);
14464 }
14465
14466 /* The .fmask and .mask directives. If the mdebug section is present
14467 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14468 embedded targets, s_mips_mask is used so that we can set the PDR
14469 information correctly. We can't use the ecoff routines because they
14470 make reference to the ecoff symbol table (in the mdebug section). */
14471
14472 static void
14473 s_mips_mask (int reg_type)
14474 {
14475 #ifdef OBJ_ELF
14476 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14477 {
14478 long mask, off;
14479
14480 if (cur_proc_ptr == (procS *) NULL)
14481 {
14482 as_warn (_(".mask/.fmask outside of .ent"));
14483 demand_empty_rest_of_line ();
14484 return;
14485 }
14486
14487 if (get_absolute_expression_and_terminator (&mask) != ',')
14488 {
14489 as_warn (_("Bad .mask/.fmask directive"));
14490 --input_line_pointer;
14491 demand_empty_rest_of_line ();
14492 return;
14493 }
14494
14495 off = get_absolute_expression ();
14496
14497 if (reg_type == 'F')
14498 {
14499 cur_proc_ptr->fpreg_mask = mask;
14500 cur_proc_ptr->fpreg_offset = off;
14501 }
14502 else
14503 {
14504 cur_proc_ptr->reg_mask = mask;
14505 cur_proc_ptr->reg_offset = off;
14506 }
14507
14508 demand_empty_rest_of_line ();
14509 }
14510 else
14511 #endif /* OBJ_ELF */
14512 s_ignore (reg_type);
14513 }
14514
14515 /* A table describing all the processors gas knows about. Names are
14516 matched in the order listed.
14517
14518 To ease comparison, please keep this table in the same order as
14519 gcc's mips_cpu_info_table[]. */
14520 static const struct mips_cpu_info mips_cpu_info_table[] =
14521 {
14522 /* Entries for generic ISAs */
14523 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
14524 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
14525 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
14526 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
14527 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
14528 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
14529 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
14530 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
14531 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
14532
14533 /* MIPS I */
14534 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14535 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14536 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14537
14538 /* MIPS II */
14539 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14540
14541 /* MIPS III */
14542 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14543 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14544 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14545 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14546 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14547 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14548 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14549 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14550 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14551 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14552 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14553 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14554
14555 /* MIPS IV */
14556 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14557 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14558 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14559 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14560 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14561 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14562 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14563 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14564 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14565 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14566 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14567 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14568 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
14569
14570 /* MIPS 32 */
14571 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14572 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14573 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14574 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
14575
14576 /* MIPS 32 Release 2 */
14577 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14578 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14579 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14580 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
14581 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14582 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14583 { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14584 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14585 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14586 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14587 /* 24ke is a 24k with DSP ASE, other ASEs are optional. */
14588 { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14589 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14590 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14591 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14592 /* 34k is a 24k with MT ASE, other ASEs are optional. */
14593 { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
14594 { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
14595 { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
14596
14597 /* MIPS 64 */
14598 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14599 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
14600 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
14601
14602 /* MIPS 64 Release 2 */
14603 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64R2, CPU_MIPS64R2 },
14604
14605 /* Broadcom SB-1 CPU core */
14606 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14607
14608 /* End marker */
14609 { NULL, 0, 0, 0 }
14610 };
14611
14612
14613 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14614 with a final "000" replaced by "k". Ignore case.
14615
14616 Note: this function is shared between GCC and GAS. */
14617
14618 static bfd_boolean
14619 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14620 {
14621 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14622 given++, canonical++;
14623
14624 return ((*given == 0 && *canonical == 0)
14625 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14626 }
14627
14628
14629 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14630 CPU name. We've traditionally allowed a lot of variation here.
14631
14632 Note: this function is shared between GCC and GAS. */
14633
14634 static bfd_boolean
14635 mips_matching_cpu_name_p (const char *canonical, const char *given)
14636 {
14637 /* First see if the name matches exactly, or with a final "000"
14638 turned into "k". */
14639 if (mips_strict_matching_cpu_name_p (canonical, given))
14640 return TRUE;
14641
14642 /* If not, try comparing based on numerical designation alone.
14643 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14644 if (TOLOWER (*given) == 'r')
14645 given++;
14646 if (!ISDIGIT (*given))
14647 return FALSE;
14648
14649 /* Skip over some well-known prefixes in the canonical name,
14650 hoping to find a number there too. */
14651 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14652 canonical += 2;
14653 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14654 canonical += 2;
14655 else if (TOLOWER (canonical[0]) == 'r')
14656 canonical += 1;
14657
14658 return mips_strict_matching_cpu_name_p (canonical, given);
14659 }
14660
14661
14662 /* Parse an option that takes the name of a processor as its argument.
14663 OPTION is the name of the option and CPU_STRING is the argument.
14664 Return the corresponding processor enumeration if the CPU_STRING is
14665 recognized, otherwise report an error and return null.
14666
14667 A similar function exists in GCC. */
14668
14669 static const struct mips_cpu_info *
14670 mips_parse_cpu (const char *option, const char *cpu_string)
14671 {
14672 const struct mips_cpu_info *p;
14673
14674 /* 'from-abi' selects the most compatible architecture for the given
14675 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14676 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14677 version. Look first at the -mgp options, if given, otherwise base
14678 the choice on MIPS_DEFAULT_64BIT.
14679
14680 Treat NO_ABI like the EABIs. One reason to do this is that the
14681 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14682 architecture. This code picks MIPS I for 'mips' and MIPS III for
14683 'mips64', just as we did in the days before 'from-abi'. */
14684 if (strcasecmp (cpu_string, "from-abi") == 0)
14685 {
14686 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14687 return mips_cpu_info_from_isa (ISA_MIPS1);
14688
14689 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14690 return mips_cpu_info_from_isa (ISA_MIPS3);
14691
14692 if (file_mips_gp32 >= 0)
14693 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14694
14695 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14696 ? ISA_MIPS3
14697 : ISA_MIPS1);
14698 }
14699
14700 /* 'default' has traditionally been a no-op. Probably not very useful. */
14701 if (strcasecmp (cpu_string, "default") == 0)
14702 return 0;
14703
14704 for (p = mips_cpu_info_table; p->name != 0; p++)
14705 if (mips_matching_cpu_name_p (p->name, cpu_string))
14706 return p;
14707
14708 as_bad ("Bad value (%s) for %s", cpu_string, option);
14709 return 0;
14710 }
14711
14712 /* Return the canonical processor information for ISA (a member of the
14713 ISA_MIPS* enumeration). */
14714
14715 static const struct mips_cpu_info *
14716 mips_cpu_info_from_isa (int isa)
14717 {
14718 int i;
14719
14720 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14721 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
14722 && isa == mips_cpu_info_table[i].isa)
14723 return (&mips_cpu_info_table[i]);
14724
14725 return NULL;
14726 }
14727
14728 static const struct mips_cpu_info *
14729 mips_cpu_info_from_arch (int arch)
14730 {
14731 int i;
14732
14733 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14734 if (arch == mips_cpu_info_table[i].cpu)
14735 return (&mips_cpu_info_table[i]);
14736
14737 return NULL;
14738 }
14739 \f
14740 static void
14741 show (FILE *stream, const char *string, int *col_p, int *first_p)
14742 {
14743 if (*first_p)
14744 {
14745 fprintf (stream, "%24s", "");
14746 *col_p = 24;
14747 }
14748 else
14749 {
14750 fprintf (stream, ", ");
14751 *col_p += 2;
14752 }
14753
14754 if (*col_p + strlen (string) > 72)
14755 {
14756 fprintf (stream, "\n%24s", "");
14757 *col_p = 24;
14758 }
14759
14760 fprintf (stream, "%s", string);
14761 *col_p += strlen (string);
14762
14763 *first_p = 0;
14764 }
14765
14766 void
14767 md_show_usage (FILE *stream)
14768 {
14769 int column, first;
14770 size_t i;
14771
14772 fprintf (stream, _("\
14773 MIPS options:\n\
14774 -EB generate big endian output\n\
14775 -EL generate little endian output\n\
14776 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14777 -G NUM allow referencing objects up to NUM bytes\n\
14778 implicitly with the gp register [default 8]\n"));
14779 fprintf (stream, _("\
14780 -mips1 generate MIPS ISA I instructions\n\
14781 -mips2 generate MIPS ISA II instructions\n\
14782 -mips3 generate MIPS ISA III instructions\n\
14783 -mips4 generate MIPS ISA IV instructions\n\
14784 -mips5 generate MIPS ISA V instructions\n\
14785 -mips32 generate MIPS32 ISA instructions\n\
14786 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14787 -mips64 generate MIPS64 ISA instructions\n\
14788 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14789 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14790
14791 first = 1;
14792
14793 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14794 show (stream, mips_cpu_info_table[i].name, &column, &first);
14795 show (stream, "from-abi", &column, &first);
14796 fputc ('\n', stream);
14797
14798 fprintf (stream, _("\
14799 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14800 -no-mCPU don't generate code specific to CPU.\n\
14801 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14802
14803 first = 1;
14804
14805 show (stream, "3900", &column, &first);
14806 show (stream, "4010", &column, &first);
14807 show (stream, "4100", &column, &first);
14808 show (stream, "4650", &column, &first);
14809 fputc ('\n', stream);
14810
14811 fprintf (stream, _("\
14812 -mips16 generate mips16 instructions\n\
14813 -no-mips16 do not generate mips16 instructions\n"));
14814 fprintf (stream, _("\
14815 -msmartmips generate smartmips instructions\n\
14816 -mno-smartmips do not generate smartmips instructions\n"));
14817 fprintf (stream, _("\
14818 -mdsp generate DSP instructions\n\
14819 -mno-dsp do not generate DSP instructions\n"));
14820 fprintf (stream, _("\
14821 -mmt generate MT instructions\n\
14822 -mno-mt do not generate MT instructions\n"));
14823 fprintf (stream, _("\
14824 -mfix-vr4120 work around certain VR4120 errata\n\
14825 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14826 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14827 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14828 -mno-shared optimize output for executables\n\
14829 -msym32 assume all symbols have 32-bit values\n\
14830 -O0 remove unneeded NOPs, do not swap branches\n\
14831 -O remove unneeded NOPs and swap branches\n\
14832 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14833 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14834 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14835 #ifdef OBJ_ELF
14836 fprintf (stream, _("\
14837 -KPIC, -call_shared generate SVR4 position independent code\n\
14838 -non_shared do not generate position independent code\n\
14839 -xgot assume a 32 bit GOT\n\
14840 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14841 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14842 non-shared code\n\
14843 -mabi=ABI create ABI conformant object file for:\n"));
14844
14845 first = 1;
14846
14847 show (stream, "32", &column, &first);
14848 show (stream, "o64", &column, &first);
14849 show (stream, "n32", &column, &first);
14850 show (stream, "64", &column, &first);
14851 show (stream, "eabi", &column, &first);
14852
14853 fputc ('\n', stream);
14854
14855 fprintf (stream, _("\
14856 -32 create o32 ABI object file (default)\n\
14857 -n32 create n32 ABI object file\n\
14858 -64 create 64 ABI object file\n"));
14859 #endif
14860 }
14861
14862 enum dwarf2_format
14863 mips_dwarf2_format (void)
14864 {
14865 if (mips_abi == N64_ABI)
14866 {
14867 #ifdef TE_IRIX
14868 return dwarf2_format_64bit_irix;
14869 #else
14870 return dwarf2_format_64bit;
14871 #endif
14872 }
14873 else
14874 return dwarf2_format_32bit;
14875 }
14876
14877 int
14878 mips_dwarf2_addr_size (void)
14879 {
14880 if (mips_abi == N64_ABI)
14881 return 8;
14882 else
14883 return 4;
14884 }
14885
14886 /* Standard calling conventions leave the CFA at SP on entry. */
14887 void
14888 mips_cfi_frame_initial_instructions (void)
14889 {
14890 cfi_add_CFA_def_cfa_register (SP);
14891 }
14892
14893 int
14894 tc_mips_regname_to_dw2regnum (char *regname)
14895 {
14896 unsigned int regnum = -1;
14897 unsigned int reg;
14898
14899 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
14900 regnum = reg;
14901
14902 return regnum;
14903 }
This page took 0.587652 seconds and 5 git commands to generate.