1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode
*insn_mo
;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p
: 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros
;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float
;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float
;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32
= -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32
= -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float
= 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float
= 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008
= FALSE
;
278 static struct mips_set_options mips_opts
=
280 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
284 /* soft_float */ FALSE
, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase
;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit
;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask
;
298 unsigned long mips_cprmask
[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa
= ISA_UNKNOWN
;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16
;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips
;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch
= CPU_UNKNOWN
;
328 static const char *mips_arch_string
;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune
= CPU_UNKNOWN
;
333 static const char *mips_tune_string
;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode
= 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic
;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got
= 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap
= 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction
;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder
;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix
;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value
= 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen
= 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS
*, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control
*op_hash
= NULL
;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control
*mips16_op_hash
= NULL
;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control
*micromips_op_hash
= NULL
;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars
[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars
[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars
[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS
[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error
;
632 static int auto_align
= 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset
= -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset
= -1;
644 static int mips_cpreturn_register
= -1;
645 static int mips_gp_register
= GP
;
646 static int mips_gprel_offset
= 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid
= 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg
= SP
;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid
= 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize
= 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug
= 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history
[1 + MAX_NOPS
];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn
;
691 static struct mips_cl_insn mips16_nop_insn
;
692 static struct mips_cl_insn micromips_nop16_insn
;
693 static struct mips_cl_insn micromips_nop32_insn
;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS
*prev_nop_frag
;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds
;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required
;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since
;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup
*next
;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup
*mips_hi_fixup_list
;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS
*prev_reloc_op_frag
;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map
[] =
760 X
, X
, 2, 3, 4, 5, 6, 7,
761 X
, X
, X
, X
, X
, X
, X
, X
,
762 0, 1, X
, X
, X
, X
, X
, X
,
763 X
, X
, X
, X
, X
, X
, X
, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map
[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map
[] =
788 0, X
, 2, 3, X
, X
, X
, X
,
789 X
, X
, X
, X
, X
, X
, X
, X
,
790 4, 1, 5, 6, 7, X
, X
, X
,
791 X
, X
, X
, X
, X
, X
, X
, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map
[] =
797 0, X
, 2, 3, 4, 5, 6, 7,
798 X
, X
, X
, X
, X
, X
, X
, X
,
799 X
, 1, X
, X
, X
, X
, X
, X
,
800 X
, X
, X
, X
, X
, X
, X
, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1
[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2
[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map
[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map
[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map
[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map
[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump
;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop
;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f
;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120
;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130
;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k
;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1
;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch
;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes
[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p
;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length
;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes
[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes
[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns
[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning
;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1272 static void append_insn
1273 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1274 bfd_boolean expansionp
);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS
*, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS
*, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS
*, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn
*ip
, char *str
);
1283 static void mips16_macro (struct mips_cl_insn
* ip
);
1284 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1285 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1291 static void my_getExpression (expressionS
*, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type
);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1328 static int relaxed_branch_length (fragS
*, asection
*, int);
1329 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1330 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1332 /* Table and functions used to map between CPU/ISA names, and
1333 ISA levels, and CPU numbers. */
1335 struct mips_cpu_info
1337 const char *name
; /* CPU or ISA name. */
1338 int flags
; /* MIPS_CPU_* flags. */
1339 int ase
; /* Set of ASEs implemented by the CPU. */
1340 int isa
; /* ISA level. */
1341 int cpu
; /* CPU number (default CPU if ISA). */
1344 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1346 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1347 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1348 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1350 /* Command-line options. */
1351 const char *md_shortopts
= "O::g::G:";
1355 OPTION_MARCH
= OPTION_MD_BASE
,
1379 OPTION_NO_SMARTMIPS
,
1385 OPTION_NO_MICROMIPS
,
1388 OPTION_COMPAT_ARCH_BASE
,
1397 OPTION_M7000_HILO_FIX
,
1398 OPTION_MNO_7000_HILO_FIX
,
1401 OPTION_FIX_LOONGSON2F_JUMP
,
1402 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1403 OPTION_FIX_LOONGSON2F_NOP
,
1404 OPTION_NO_FIX_LOONGSON2F_NOP
,
1406 OPTION_NO_FIX_VR4120
,
1408 OPTION_NO_FIX_VR4130
,
1409 OPTION_FIX_CN63XXP1
,
1410 OPTION_NO_FIX_CN63XXP1
,
1417 OPTION_CONSTRUCT_FLOATS
,
1418 OPTION_NO_CONSTRUCT_FLOATS
,
1421 OPTION_RELAX_BRANCH
,
1422 OPTION_NO_RELAX_BRANCH
,
1431 OPTION_SINGLE_FLOAT
,
1432 OPTION_DOUBLE_FLOAT
,
1445 OPTION_MVXWORKS_PIC
,
1450 struct option md_longopts
[] =
1452 /* Options which specify architecture. */
1453 {"march", required_argument
, NULL
, OPTION_MARCH
},
1454 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1455 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1456 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1457 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1458 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1459 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1460 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1461 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1462 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1463 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1464 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1466 /* Options which specify Application Specific Extensions (ASEs). */
1467 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1468 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1469 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1470 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1471 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1472 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1473 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1474 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1475 {"mmt", no_argument
, NULL
, OPTION_MT
},
1476 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1477 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1478 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1479 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1480 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1481 {"meva", no_argument
, NULL
, OPTION_EVA
},
1482 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1483 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1484 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1485 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1486 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1487 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1488 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1490 /* Old-style architecture options. Don't add more of these. */
1491 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1492 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1493 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1494 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1495 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1496 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1497 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1498 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1500 /* Options which enable bug fixes. */
1501 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1502 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1503 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1504 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1505 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1506 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1507 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1508 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1509 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1510 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1511 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1512 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1513 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1514 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1515 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1517 /* Miscellaneous options. */
1518 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1519 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1520 {"break", no_argument
, NULL
, OPTION_BREAK
},
1521 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1522 {"EB", no_argument
, NULL
, OPTION_EB
},
1523 {"EL", no_argument
, NULL
, OPTION_EL
},
1524 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1525 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1526 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1527 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1528 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1529 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1530 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1531 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1532 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1533 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1534 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1535 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1536 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1537 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1538 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1539 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1540 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1541 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1543 /* Strictly speaking this next option is ELF specific,
1544 but we allow it for other ports as well in order to
1545 make testing easier. */
1546 {"32", no_argument
, NULL
, OPTION_32
},
1548 /* ELF-specific options. */
1549 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1550 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1551 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1552 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1553 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1554 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1555 {"n32", no_argument
, NULL
, OPTION_N32
},
1556 {"64", no_argument
, NULL
, OPTION_64
},
1557 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1558 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1559 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1560 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1561 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1562 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1564 {NULL
, no_argument
, NULL
, 0}
1566 size_t md_longopts_size
= sizeof (md_longopts
);
1568 /* Information about either an Application Specific Extension or an
1569 optional architecture feature that, for simplicity, we treat in the
1570 same way as an ASE. */
1573 /* The name of the ASE, used in both the command-line and .set options. */
1576 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1577 and 64-bit architectures, the flags here refer to the subset that
1578 is available on both. */
1581 /* The ASE_* flag used for instructions that are available on 64-bit
1582 architectures but that are not included in FLAGS. */
1583 unsigned int flags64
;
1585 /* The command-line options that turn the ASE on and off. */
1589 /* The minimum required architecture revisions for MIPS32, MIPS64,
1590 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1593 int micromips32_rev
;
1594 int micromips64_rev
;
1597 /* A table of all supported ASEs. */
1598 static const struct mips_ase mips_ases
[] = {
1599 { "dsp", ASE_DSP
, ASE_DSP64
,
1600 OPTION_DSP
, OPTION_NO_DSP
,
1603 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1604 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1607 { "eva", ASE_EVA
, 0,
1608 OPTION_EVA
, OPTION_NO_EVA
,
1611 { "mcu", ASE_MCU
, 0,
1612 OPTION_MCU
, OPTION_NO_MCU
,
1615 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1616 { "mdmx", ASE_MDMX
, 0,
1617 OPTION_MDMX
, OPTION_NO_MDMX
,
1620 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1621 { "mips3d", ASE_MIPS3D
, 0,
1622 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1626 OPTION_MT
, OPTION_NO_MT
,
1629 { "smartmips", ASE_SMARTMIPS
, 0,
1630 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1633 { "virt", ASE_VIRT
, ASE_VIRT64
,
1634 OPTION_VIRT
, OPTION_NO_VIRT
,
1638 /* The set of ASEs that require -mfp64. */
1639 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1641 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1642 static const unsigned int mips_ase_groups
[] = {
1648 The following pseudo-ops from the Kane and Heinrich MIPS book
1649 should be defined here, but are currently unsupported: .alias,
1650 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1652 The following pseudo-ops from the Kane and Heinrich MIPS book are
1653 specific to the type of debugging information being generated, and
1654 should be defined by the object format: .aent, .begin, .bend,
1655 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1658 The following pseudo-ops from the Kane and Heinrich MIPS book are
1659 not MIPS CPU specific, but are also not specific to the object file
1660 format. This file is probably the best place to define them, but
1661 they are not currently supported: .asm0, .endr, .lab, .struct. */
1663 static const pseudo_typeS mips_pseudo_table
[] =
1665 /* MIPS specific pseudo-ops. */
1666 {"option", s_option
, 0},
1667 {"set", s_mipsset
, 0},
1668 {"rdata", s_change_sec
, 'r'},
1669 {"sdata", s_change_sec
, 's'},
1670 {"livereg", s_ignore
, 0},
1671 {"abicalls", s_abicalls
, 0},
1672 {"cpload", s_cpload
, 0},
1673 {"cpsetup", s_cpsetup
, 0},
1674 {"cplocal", s_cplocal
, 0},
1675 {"cprestore", s_cprestore
, 0},
1676 {"cpreturn", s_cpreturn
, 0},
1677 {"dtprelword", s_dtprelword
, 0},
1678 {"dtpreldword", s_dtpreldword
, 0},
1679 {"tprelword", s_tprelword
, 0},
1680 {"tpreldword", s_tpreldword
, 0},
1681 {"gpvalue", s_gpvalue
, 0},
1682 {"gpword", s_gpword
, 0},
1683 {"gpdword", s_gpdword
, 0},
1684 {"ehword", s_ehword
, 0},
1685 {"cpadd", s_cpadd
, 0},
1686 {"insn", s_insn
, 0},
1689 /* Relatively generic pseudo-ops that happen to be used on MIPS
1691 {"asciiz", stringer
, 8 + 1},
1692 {"bss", s_change_sec
, 'b'},
1694 {"half", s_cons
, 1},
1695 {"dword", s_cons
, 3},
1696 {"weakext", s_mips_weakext
, 0},
1697 {"origin", s_org
, 0},
1698 {"repeat", s_rept
, 0},
1700 /* For MIPS this is non-standard, but we define it for consistency. */
1701 {"sbss", s_change_sec
, 'B'},
1703 /* These pseudo-ops are defined in read.c, but must be overridden
1704 here for one reason or another. */
1705 {"align", s_align
, 0},
1706 {"byte", s_cons
, 0},
1707 {"data", s_change_sec
, 'd'},
1708 {"double", s_float_cons
, 'd'},
1709 {"float", s_float_cons
, 'f'},
1710 {"globl", s_mips_globl
, 0},
1711 {"global", s_mips_globl
, 0},
1712 {"hword", s_cons
, 1},
1714 {"long", s_cons
, 2},
1715 {"octa", s_cons
, 4},
1716 {"quad", s_cons
, 3},
1717 {"section", s_change_section
, 0},
1718 {"short", s_cons
, 1},
1719 {"single", s_float_cons
, 'f'},
1720 {"stabd", s_mips_stab
, 'd'},
1721 {"stabn", s_mips_stab
, 'n'},
1722 {"stabs", s_mips_stab
, 's'},
1723 {"text", s_change_sec
, 't'},
1724 {"word", s_cons
, 2},
1726 { "extern", ecoff_directive_extern
, 0},
1731 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1733 /* These pseudo-ops should be defined by the object file format.
1734 However, a.out doesn't support them, so we have versions here. */
1735 {"aent", s_mips_ent
, 1},
1736 {"bgnb", s_ignore
, 0},
1737 {"end", s_mips_end
, 0},
1738 {"endb", s_ignore
, 0},
1739 {"ent", s_mips_ent
, 0},
1740 {"file", s_mips_file
, 0},
1741 {"fmask", s_mips_mask
, 'F'},
1742 {"frame", s_mips_frame
, 0},
1743 {"loc", s_mips_loc
, 0},
1744 {"mask", s_mips_mask
, 'R'},
1745 {"verstamp", s_ignore
, 0},
1749 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1750 purpose of the `.dc.a' internal pseudo-op. */
1753 mips_address_bytes (void)
1755 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1758 extern void pop_insert (const pseudo_typeS
*);
1761 mips_pop_insert (void)
1763 pop_insert (mips_pseudo_table
);
1764 if (! ECOFF_DEBUGGING
)
1765 pop_insert (mips_nonecoff_pseudo_table
);
1768 /* Symbols labelling the current insn. */
1770 struct insn_label_list
1772 struct insn_label_list
*next
;
1776 static struct insn_label_list
*free_insn_labels
;
1777 #define label_list tc_segment_info_data.labels
1779 static void mips_clear_insn_labels (void);
1780 static void mips_mark_labels (void);
1781 static void mips_compressed_mark_labels (void);
1784 mips_clear_insn_labels (void)
1786 register struct insn_label_list
**pl
;
1787 segment_info_type
*si
;
1791 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1794 si
= seg_info (now_seg
);
1795 *pl
= si
->label_list
;
1796 si
->label_list
= NULL
;
1800 /* Mark instruction labels in MIPS16/microMIPS mode. */
1803 mips_mark_labels (void)
1805 if (HAVE_CODE_COMPRESSION
)
1806 mips_compressed_mark_labels ();
1809 static char *expr_end
;
1811 /* Expressions which appear in macro instructions. These are set by
1812 mips_ip and read by macro. */
1814 static expressionS imm_expr
;
1815 static expressionS imm2_expr
;
1817 /* The relocatable field in an instruction and the relocs associated
1818 with it. These variables are used for instructions like LUI and
1819 JAL as well as true offsets. They are also used for address
1820 operands in macros. */
1822 static expressionS offset_expr
;
1823 static bfd_reloc_code_real_type offset_reloc
[3]
1824 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1826 /* This is set to the resulting size of the instruction to be produced
1827 by mips16_ip if an explicit extension is used or by mips_ip if an
1828 explicit size is supplied. */
1830 static unsigned int forced_insn_length
;
1832 /* True if we are assembling an instruction. All dot symbols defined during
1833 this time should be treated as code labels. */
1835 static bfd_boolean mips_assembling_insn
;
1837 /* The pdr segment for per procedure frame/regmask info. Not used for
1840 static segT pdr_seg
;
1842 /* The default target format to use. */
1844 #if defined (TE_FreeBSD)
1845 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1846 #elif defined (TE_TMIPS)
1847 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1849 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1853 mips_target_format (void)
1855 switch (OUTPUT_FLAVOR
)
1857 case bfd_target_elf_flavour
:
1859 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1860 return (target_big_endian
1861 ? "elf32-bigmips-vxworks"
1862 : "elf32-littlemips-vxworks");
1864 return (target_big_endian
1865 ? (HAVE_64BIT_OBJECTS
1866 ? ELF_TARGET ("elf64-", "big")
1868 ? ELF_TARGET ("elf32-n", "big")
1869 : ELF_TARGET ("elf32-", "big")))
1870 : (HAVE_64BIT_OBJECTS
1871 ? ELF_TARGET ("elf64-", "little")
1873 ? ELF_TARGET ("elf32-n", "little")
1874 : ELF_TARGET ("elf32-", "little"))));
1881 /* Return the ISA revision that is currently in use, or 0 if we are
1882 generating code for MIPS V or below. */
1887 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1890 /* microMIPS implies revision 2 or above. */
1891 if (mips_opts
.micromips
)
1894 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1900 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1903 mips_ase_mask (unsigned int flags
)
1907 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1908 if (flags
& mips_ase_groups
[i
])
1909 flags
|= mips_ase_groups
[i
];
1913 /* Check whether the current ISA supports ASE. Issue a warning if
1917 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1921 static unsigned int warned_isa
;
1922 static unsigned int warned_fp32
;
1924 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1925 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1927 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1928 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1929 && (warned_isa
& ase
->flags
) != ase
->flags
)
1931 warned_isa
|= ase
->flags
;
1932 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1933 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1935 as_warn (_("The %d-bit %s architecture does not support the"
1936 " `%s' extension"), size
, base
, ase
->name
);
1938 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1939 ase
->name
, base
, size
, min_rev
);
1941 if ((ase
->flags
& FP64_ASES
)
1943 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1945 warned_fp32
|= ase
->flags
;
1946 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1950 /* Check all enabled ASEs to see whether they are supported by the
1951 chosen architecture. */
1954 mips_check_isa_supports_ases (void)
1956 unsigned int i
, mask
;
1958 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1960 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1961 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1962 mips_check_isa_supports_ase (&mips_ases
[i
]);
1966 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1967 that were affected. */
1970 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1974 mask
= mips_ase_mask (ase
->flags
);
1975 mips_opts
.ase
&= ~mask
;
1977 mips_opts
.ase
|= ase
->flags
;
1981 /* Return the ASE called NAME, or null if none. */
1983 static const struct mips_ase
*
1984 mips_lookup_ase (const char *name
)
1988 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1989 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1990 return &mips_ases
[i
];
1994 /* Return the length of a microMIPS instruction in bytes. If bits of
1995 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1996 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1997 major opcode) will require further modifications to the opcode
2000 static inline unsigned int
2001 micromips_insn_length (const struct mips_opcode
*mo
)
2003 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2006 /* Return the length of MIPS16 instruction OPCODE. */
2008 static inline unsigned int
2009 mips16_opcode_length (unsigned long opcode
)
2011 return (opcode
>> 16) == 0 ? 2 : 4;
2014 /* Return the length of instruction INSN. */
2016 static inline unsigned int
2017 insn_length (const struct mips_cl_insn
*insn
)
2019 if (mips_opts
.micromips
)
2020 return micromips_insn_length (insn
->insn_mo
);
2021 else if (mips_opts
.mips16
)
2022 return mips16_opcode_length (insn
->insn_opcode
);
2027 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2030 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2035 insn
->insn_opcode
= mo
->match
;
2038 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2039 insn
->fixp
[i
] = NULL
;
2040 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2041 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2042 insn
->mips16_absolute_jump_p
= 0;
2043 insn
->complete_p
= 0;
2044 insn
->cleared_p
= 0;
2047 /* Record the current MIPS16/microMIPS mode in now_seg. */
2050 mips_record_compressed_mode (void)
2052 segment_info_type
*si
;
2054 si
= seg_info (now_seg
);
2055 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2056 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2057 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2058 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2061 /* Read a standard MIPS instruction from BUF. */
2063 static unsigned long
2064 read_insn (char *buf
)
2066 if (target_big_endian
)
2067 return bfd_getb32 ((bfd_byte
*) buf
);
2069 return bfd_getl32 ((bfd_byte
*) buf
);
2072 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2076 write_insn (char *buf
, unsigned int insn
)
2078 md_number_to_chars (buf
, insn
, 4);
2082 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2083 has length LENGTH. */
2085 static unsigned long
2086 read_compressed_insn (char *buf
, unsigned int length
)
2092 for (i
= 0; i
< length
; i
+= 2)
2095 if (target_big_endian
)
2096 insn
|= bfd_getb16 ((char *) buf
);
2098 insn
|= bfd_getl16 ((char *) buf
);
2104 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2105 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2108 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2112 for (i
= 0; i
< length
; i
+= 2)
2113 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2114 return buf
+ length
;
2117 /* Install INSN at the location specified by its "frag" and "where" fields. */
2120 install_insn (const struct mips_cl_insn
*insn
)
2122 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2123 if (HAVE_CODE_COMPRESSION
)
2124 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2126 write_insn (f
, insn
->insn_opcode
);
2127 mips_record_compressed_mode ();
2130 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2131 and install the opcode in the new location. */
2134 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2139 insn
->where
= where
;
2140 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2141 if (insn
->fixp
[i
] != NULL
)
2143 insn
->fixp
[i
]->fx_frag
= frag
;
2144 insn
->fixp
[i
]->fx_where
= where
;
2146 install_insn (insn
);
2149 /* Add INSN to the end of the output. */
2152 add_fixed_insn (struct mips_cl_insn
*insn
)
2154 char *f
= frag_more (insn_length (insn
));
2155 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2158 /* Start a variant frag and move INSN to the start of the variant part,
2159 marking it as fixed. The other arguments are as for frag_var. */
2162 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2163 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2165 frag_grow (max_chars
);
2166 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2168 frag_var (rs_machine_dependent
, max_chars
, var
,
2169 subtype
, symbol
, offset
, NULL
);
2172 /* Insert N copies of INSN into the history buffer, starting at
2173 position FIRST. Neither FIRST nor N need to be clipped. */
2176 insert_into_history (unsigned int first
, unsigned int n
,
2177 const struct mips_cl_insn
*insn
)
2179 if (mips_relax
.sequence
!= 2)
2183 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2185 history
[i
] = history
[i
- n
];
2191 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2192 the idea is to make it obvious at a glance that each errata is
2196 init_vr4120_conflicts (void)
2198 #define CONFLICT(FIRST, SECOND) \
2199 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2201 /* Errata 21 - [D]DIV[U] after [D]MACC */
2202 CONFLICT (MACC
, DIV
);
2203 CONFLICT (DMACC
, DIV
);
2205 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2206 CONFLICT (DMULT
, DMULT
);
2207 CONFLICT (DMULT
, DMACC
);
2208 CONFLICT (DMACC
, DMULT
);
2209 CONFLICT (DMACC
, DMACC
);
2211 /* Errata 24 - MT{LO,HI} after [D]MACC */
2212 CONFLICT (MACC
, MTHILO
);
2213 CONFLICT (DMACC
, MTHILO
);
2215 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2216 instruction is executed immediately after a MACC or DMACC
2217 instruction, the result of [either instruction] is incorrect." */
2218 CONFLICT (MACC
, MULT
);
2219 CONFLICT (MACC
, DMULT
);
2220 CONFLICT (DMACC
, MULT
);
2221 CONFLICT (DMACC
, DMULT
);
2223 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2224 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2225 DDIV or DDIVU instruction, the result of the MACC or
2226 DMACC instruction is incorrect.". */
2227 CONFLICT (DMULT
, MACC
);
2228 CONFLICT (DMULT
, DMACC
);
2229 CONFLICT (DIV
, MACC
);
2230 CONFLICT (DIV
, DMACC
);
2240 #define RTYPE_MASK 0x1ff00
2241 #define RTYPE_NUM 0x00100
2242 #define RTYPE_FPU 0x00200
2243 #define RTYPE_FCC 0x00400
2244 #define RTYPE_VEC 0x00800
2245 #define RTYPE_GP 0x01000
2246 #define RTYPE_CP0 0x02000
2247 #define RTYPE_PC 0x04000
2248 #define RTYPE_ACC 0x08000
2249 #define RTYPE_CCC 0x10000
2250 #define RNUM_MASK 0x000ff
2251 #define RWARN 0x80000
2253 #define GENERIC_REGISTER_NUMBERS \
2254 {"$0", RTYPE_NUM | 0}, \
2255 {"$1", RTYPE_NUM | 1}, \
2256 {"$2", RTYPE_NUM | 2}, \
2257 {"$3", RTYPE_NUM | 3}, \
2258 {"$4", RTYPE_NUM | 4}, \
2259 {"$5", RTYPE_NUM | 5}, \
2260 {"$6", RTYPE_NUM | 6}, \
2261 {"$7", RTYPE_NUM | 7}, \
2262 {"$8", RTYPE_NUM | 8}, \
2263 {"$9", RTYPE_NUM | 9}, \
2264 {"$10", RTYPE_NUM | 10}, \
2265 {"$11", RTYPE_NUM | 11}, \
2266 {"$12", RTYPE_NUM | 12}, \
2267 {"$13", RTYPE_NUM | 13}, \
2268 {"$14", RTYPE_NUM | 14}, \
2269 {"$15", RTYPE_NUM | 15}, \
2270 {"$16", RTYPE_NUM | 16}, \
2271 {"$17", RTYPE_NUM | 17}, \
2272 {"$18", RTYPE_NUM | 18}, \
2273 {"$19", RTYPE_NUM | 19}, \
2274 {"$20", RTYPE_NUM | 20}, \
2275 {"$21", RTYPE_NUM | 21}, \
2276 {"$22", RTYPE_NUM | 22}, \
2277 {"$23", RTYPE_NUM | 23}, \
2278 {"$24", RTYPE_NUM | 24}, \
2279 {"$25", RTYPE_NUM | 25}, \
2280 {"$26", RTYPE_NUM | 26}, \
2281 {"$27", RTYPE_NUM | 27}, \
2282 {"$28", RTYPE_NUM | 28}, \
2283 {"$29", RTYPE_NUM | 29}, \
2284 {"$30", RTYPE_NUM | 30}, \
2285 {"$31", RTYPE_NUM | 31}
2287 #define FPU_REGISTER_NAMES \
2288 {"$f0", RTYPE_FPU | 0}, \
2289 {"$f1", RTYPE_FPU | 1}, \
2290 {"$f2", RTYPE_FPU | 2}, \
2291 {"$f3", RTYPE_FPU | 3}, \
2292 {"$f4", RTYPE_FPU | 4}, \
2293 {"$f5", RTYPE_FPU | 5}, \
2294 {"$f6", RTYPE_FPU | 6}, \
2295 {"$f7", RTYPE_FPU | 7}, \
2296 {"$f8", RTYPE_FPU | 8}, \
2297 {"$f9", RTYPE_FPU | 9}, \
2298 {"$f10", RTYPE_FPU | 10}, \
2299 {"$f11", RTYPE_FPU | 11}, \
2300 {"$f12", RTYPE_FPU | 12}, \
2301 {"$f13", RTYPE_FPU | 13}, \
2302 {"$f14", RTYPE_FPU | 14}, \
2303 {"$f15", RTYPE_FPU | 15}, \
2304 {"$f16", RTYPE_FPU | 16}, \
2305 {"$f17", RTYPE_FPU | 17}, \
2306 {"$f18", RTYPE_FPU | 18}, \
2307 {"$f19", RTYPE_FPU | 19}, \
2308 {"$f20", RTYPE_FPU | 20}, \
2309 {"$f21", RTYPE_FPU | 21}, \
2310 {"$f22", RTYPE_FPU | 22}, \
2311 {"$f23", RTYPE_FPU | 23}, \
2312 {"$f24", RTYPE_FPU | 24}, \
2313 {"$f25", RTYPE_FPU | 25}, \
2314 {"$f26", RTYPE_FPU | 26}, \
2315 {"$f27", RTYPE_FPU | 27}, \
2316 {"$f28", RTYPE_FPU | 28}, \
2317 {"$f29", RTYPE_FPU | 29}, \
2318 {"$f30", RTYPE_FPU | 30}, \
2319 {"$f31", RTYPE_FPU | 31}
2321 #define FPU_CONDITION_CODE_NAMES \
2322 {"$fcc0", RTYPE_FCC | 0}, \
2323 {"$fcc1", RTYPE_FCC | 1}, \
2324 {"$fcc2", RTYPE_FCC | 2}, \
2325 {"$fcc3", RTYPE_FCC | 3}, \
2326 {"$fcc4", RTYPE_FCC | 4}, \
2327 {"$fcc5", RTYPE_FCC | 5}, \
2328 {"$fcc6", RTYPE_FCC | 6}, \
2329 {"$fcc7", RTYPE_FCC | 7}
2331 #define COPROC_CONDITION_CODE_NAMES \
2332 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2333 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2334 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2335 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2336 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2337 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2338 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2339 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2341 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2342 {"$a4", RTYPE_GP | 8}, \
2343 {"$a5", RTYPE_GP | 9}, \
2344 {"$a6", RTYPE_GP | 10}, \
2345 {"$a7", RTYPE_GP | 11}, \
2346 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2347 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2348 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2349 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2350 {"$t0", RTYPE_GP | 12}, \
2351 {"$t1", RTYPE_GP | 13}, \
2352 {"$t2", RTYPE_GP | 14}, \
2353 {"$t3", RTYPE_GP | 15}
2355 #define O32_SYMBOLIC_REGISTER_NAMES \
2356 {"$t0", RTYPE_GP | 8}, \
2357 {"$t1", RTYPE_GP | 9}, \
2358 {"$t2", RTYPE_GP | 10}, \
2359 {"$t3", RTYPE_GP | 11}, \
2360 {"$t4", RTYPE_GP | 12}, \
2361 {"$t5", RTYPE_GP | 13}, \
2362 {"$t6", RTYPE_GP | 14}, \
2363 {"$t7", RTYPE_GP | 15}, \
2364 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2365 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2366 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2367 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2369 /* Remaining symbolic register names */
2370 #define SYMBOLIC_REGISTER_NAMES \
2371 {"$zero", RTYPE_GP | 0}, \
2372 {"$at", RTYPE_GP | 1}, \
2373 {"$AT", RTYPE_GP | 1}, \
2374 {"$v0", RTYPE_GP | 2}, \
2375 {"$v1", RTYPE_GP | 3}, \
2376 {"$a0", RTYPE_GP | 4}, \
2377 {"$a1", RTYPE_GP | 5}, \
2378 {"$a2", RTYPE_GP | 6}, \
2379 {"$a3", RTYPE_GP | 7}, \
2380 {"$s0", RTYPE_GP | 16}, \
2381 {"$s1", RTYPE_GP | 17}, \
2382 {"$s2", RTYPE_GP | 18}, \
2383 {"$s3", RTYPE_GP | 19}, \
2384 {"$s4", RTYPE_GP | 20}, \
2385 {"$s5", RTYPE_GP | 21}, \
2386 {"$s6", RTYPE_GP | 22}, \
2387 {"$s7", RTYPE_GP | 23}, \
2388 {"$t8", RTYPE_GP | 24}, \
2389 {"$t9", RTYPE_GP | 25}, \
2390 {"$k0", RTYPE_GP | 26}, \
2391 {"$kt0", RTYPE_GP | 26}, \
2392 {"$k1", RTYPE_GP | 27}, \
2393 {"$kt1", RTYPE_GP | 27}, \
2394 {"$gp", RTYPE_GP | 28}, \
2395 {"$sp", RTYPE_GP | 29}, \
2396 {"$s8", RTYPE_GP | 30}, \
2397 {"$fp", RTYPE_GP | 30}, \
2398 {"$ra", RTYPE_GP | 31}
2400 #define MIPS16_SPECIAL_REGISTER_NAMES \
2401 {"$pc", RTYPE_PC | 0}
2403 #define MDMX_VECTOR_REGISTER_NAMES \
2404 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2405 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2406 {"$v2", RTYPE_VEC | 2}, \
2407 {"$v3", RTYPE_VEC | 3}, \
2408 {"$v4", RTYPE_VEC | 4}, \
2409 {"$v5", RTYPE_VEC | 5}, \
2410 {"$v6", RTYPE_VEC | 6}, \
2411 {"$v7", RTYPE_VEC | 7}, \
2412 {"$v8", RTYPE_VEC | 8}, \
2413 {"$v9", RTYPE_VEC | 9}, \
2414 {"$v10", RTYPE_VEC | 10}, \
2415 {"$v11", RTYPE_VEC | 11}, \
2416 {"$v12", RTYPE_VEC | 12}, \
2417 {"$v13", RTYPE_VEC | 13}, \
2418 {"$v14", RTYPE_VEC | 14}, \
2419 {"$v15", RTYPE_VEC | 15}, \
2420 {"$v16", RTYPE_VEC | 16}, \
2421 {"$v17", RTYPE_VEC | 17}, \
2422 {"$v18", RTYPE_VEC | 18}, \
2423 {"$v19", RTYPE_VEC | 19}, \
2424 {"$v20", RTYPE_VEC | 20}, \
2425 {"$v21", RTYPE_VEC | 21}, \
2426 {"$v22", RTYPE_VEC | 22}, \
2427 {"$v23", RTYPE_VEC | 23}, \
2428 {"$v24", RTYPE_VEC | 24}, \
2429 {"$v25", RTYPE_VEC | 25}, \
2430 {"$v26", RTYPE_VEC | 26}, \
2431 {"$v27", RTYPE_VEC | 27}, \
2432 {"$v28", RTYPE_VEC | 28}, \
2433 {"$v29", RTYPE_VEC | 29}, \
2434 {"$v30", RTYPE_VEC | 30}, \
2435 {"$v31", RTYPE_VEC | 31}
2437 #define MIPS_DSP_ACCUMULATOR_NAMES \
2438 {"$ac0", RTYPE_ACC | 0}, \
2439 {"$ac1", RTYPE_ACC | 1}, \
2440 {"$ac2", RTYPE_ACC | 2}, \
2441 {"$ac3", RTYPE_ACC | 3}
2443 static const struct regname reg_names
[] = {
2444 GENERIC_REGISTER_NUMBERS
,
2446 FPU_CONDITION_CODE_NAMES
,
2447 COPROC_CONDITION_CODE_NAMES
,
2449 /* The $txx registers depends on the abi,
2450 these will be added later into the symbol table from
2451 one of the tables below once mips_abi is set after
2452 parsing of arguments from the command line. */
2453 SYMBOLIC_REGISTER_NAMES
,
2455 MIPS16_SPECIAL_REGISTER_NAMES
,
2456 MDMX_VECTOR_REGISTER_NAMES
,
2457 MIPS_DSP_ACCUMULATOR_NAMES
,
2461 static const struct regname reg_names_o32
[] = {
2462 O32_SYMBOLIC_REGISTER_NAMES
,
2466 static const struct regname reg_names_n32n64
[] = {
2467 N32N64_SYMBOLIC_REGISTER_NAMES
,
2471 /* Check if S points at a valid register specifier according to TYPES.
2472 If so, then return 1, advance S to consume the specifier and store
2473 the register's number in REGNOP, otherwise return 0. */
2476 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2483 /* Find end of name. */
2485 if (is_name_beginner (*e
))
2487 while (is_part_of_name (*e
))
2490 /* Terminate name. */
2494 /* Look for a register symbol. */
2495 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2497 int r
= S_GET_VALUE (symbolP
);
2499 reg
= r
& RNUM_MASK
;
2500 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2501 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2502 reg
= (r
& RNUM_MASK
) - 2;
2504 /* Else see if this is a register defined in an itbl entry. */
2505 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2512 if (itbl_get_reg_val (n
, &r
))
2513 reg
= r
& RNUM_MASK
;
2516 /* Advance to next token if a register was recognised. */
2519 else if (types
& RWARN
)
2520 as_warn (_("Unrecognized register name `%s'"), *s
);
2528 /* Check if S points at a valid register list according to TYPES.
2529 If so, then return 1, advance S to consume the list and store
2530 the registers present on the list as a bitmask of ones in REGLISTP,
2531 otherwise return 0. A valid list comprises a comma-separated
2532 enumeration of valid single registers and/or dash-separated
2533 contiguous register ranges as determined by their numbers.
2535 As a special exception if one of s0-s7 registers is specified as
2536 the range's lower delimiter and s8 (fp) is its upper one, then no
2537 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2538 are selected; they have to be listed separately if needed. */
2541 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2543 unsigned int reglist
= 0;
2544 unsigned int lastregno
;
2545 bfd_boolean ok
= TRUE
;
2546 unsigned int regmask
;
2547 char *s_endlist
= *s
;
2551 while (reg_lookup (s
, types
, ®no
))
2557 ok
= reg_lookup (s
, types
, &lastregno
);
2558 if (ok
&& lastregno
< regno
)
2564 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2569 regmask
= 1 << lastregno
;
2570 regmask
= (regmask
<< 1) - 1;
2571 regmask
^= (1 << regno
) - 1;
2585 *reglistp
= reglist
;
2586 return ok
&& reglist
!= 0;
2590 mips_lookup_reg_pair (unsigned int regno1
, unsigned int regno2
,
2591 const unsigned int *map1
, const unsigned int *map2
,
2596 for (i
= 0; i
< count
; i
++)
2597 if (map1
[i
] == regno1
&& map2
[i
] == regno2
)
2602 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2603 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2606 is_opcode_valid (const struct mips_opcode
*mo
)
2608 int isa
= mips_opts
.isa
;
2609 int ase
= mips_opts
.ase
;
2613 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2614 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2615 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2616 ase
|= mips_ases
[i
].flags64
;
2618 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2621 /* Check whether the instruction or macro requires single-precision or
2622 double-precision floating-point support. Note that this information is
2623 stored differently in the opcode table for insns and macros. */
2624 if (mo
->pinfo
== INSN_MACRO
)
2626 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2627 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2631 fp_s
= mo
->pinfo
& FP_S
;
2632 fp_d
= mo
->pinfo
& FP_D
;
2635 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2638 if (fp_s
&& mips_opts
.soft_float
)
2644 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2645 selected ISA and architecture. */
2648 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2650 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2653 /* Return TRUE if the size of the microMIPS opcode MO matches one
2654 explicitly requested. Always TRUE in the standard MIPS mode. */
2657 is_size_valid (const struct mips_opcode
*mo
)
2659 if (!mips_opts
.micromips
)
2662 if (mips_opts
.insn32
)
2664 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2666 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2669 if (!forced_insn_length
)
2671 if (mo
->pinfo
== INSN_MACRO
)
2673 return forced_insn_length
== micromips_insn_length (mo
);
2676 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2677 of the preceding instruction. Always TRUE in the standard MIPS mode.
2679 We don't accept macros in 16-bit delay slots to avoid a case where
2680 a macro expansion fails because it relies on a preceding 32-bit real
2681 instruction to have matched and does not handle the operands correctly.
2682 The only macros that may expand to 16-bit instructions are JAL that
2683 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2684 and BGT (that likewise cannot be placed in a delay slot) that decay to
2685 a NOP. In all these cases the macros precede any corresponding real
2686 instruction definitions in the opcode table, so they will match in the
2687 second pass where the size of the delay slot is ignored and therefore
2688 produce correct code. */
2691 is_delay_slot_valid (const struct mips_opcode
*mo
)
2693 if (!mips_opts
.micromips
)
2696 if (mo
->pinfo
== INSN_MACRO
)
2697 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2698 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2699 && micromips_insn_length (mo
) != 4)
2701 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2702 && micromips_insn_length (mo
) != 2)
2708 /* For consistency checking, verify that all bits of OPCODE are
2709 specified either by the match/mask part of the instruction
2710 definition, or by the operand list. INSN_BITS says which
2711 bits of the instruction are significant and DECODE_OPERAND
2712 provides the mips_operand description of each operand. */
2715 validate_mips_insn (const struct mips_opcode
*opcode
,
2716 unsigned long insn_bits
,
2717 const struct mips_operand
*(*decode_operand
) (const char *))
2720 unsigned long used_bits
, doubled
, undefined
;
2721 const struct mips_operand
*operand
;
2723 if ((opcode
->mask
& opcode
->match
) != opcode
->match
)
2725 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2726 opcode
->name
, opcode
->args
);
2730 for (s
= opcode
->args
; *s
; ++s
)
2739 operand
= decode_operand (s
);
2742 as_bad (_("internal: unknown operand type: %s %s"),
2743 opcode
->name
, opcode
->args
);
2746 used_bits
|= ((1 << operand
->size
) - 1) << operand
->lsb
;
2747 if (operand
->type
== OP_MDMX_IMM_REG
)
2748 /* Bit 5 is the format selector (OB vs QH). The opcode table
2749 has separate entries for each format. */
2750 used_bits
&= ~(1 << (operand
->lsb
+ 5));
2751 /* Skip prefix characters. */
2752 if (*s
== '+' || *s
== 'm')
2756 doubled
= used_bits
& opcode
->mask
& insn_bits
;
2759 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2760 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
2763 used_bits
|= opcode
->mask
;
2764 undefined
= ~used_bits
& insn_bits
;
2767 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2768 undefined
, opcode
->name
, opcode
->args
);
2771 used_bits
&= ~insn_bits
;
2774 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2775 used_bits
, opcode
->name
, opcode
->args
);
2781 /* The microMIPS version of validate_mips_insn. */
2784 validate_micromips_insn (const struct mips_opcode
*opc
)
2786 unsigned long insn_bits
;
2787 unsigned long major
;
2788 unsigned int length
;
2790 length
= micromips_insn_length (opc
);
2791 if (length
!= 2 && length
!= 4)
2793 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2794 "%s %s"), length
, opc
->name
, opc
->args
);
2797 major
= opc
->match
>> (10 + 8 * (length
- 2));
2798 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
2799 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
2801 as_bad (_("Internal error: bad microMIPS opcode "
2802 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
2806 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2807 insn_bits
= 1 << 4 * length
;
2808 insn_bits
<<= 4 * length
;
2810 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
);
2813 /* This function is called once, at assembler startup time. It should set up
2814 all the tables, etc. that the MD part of the assembler will need. */
2819 const char *retval
= NULL
;
2823 if (mips_pic
!= NO_PIC
)
2825 if (g_switch_seen
&& g_switch_value
!= 0)
2826 as_bad (_("-G may not be used in position-independent code"));
2830 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2831 as_warn (_("Could not set architecture and machine"));
2833 op_hash
= hash_new ();
2835 for (i
= 0; i
< NUMOPCODES
;)
2837 const char *name
= mips_opcodes
[i
].name
;
2839 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2842 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2843 mips_opcodes
[i
].name
, retval
);
2844 /* Probably a memory allocation problem? Give up now. */
2845 as_fatal (_("Broken assembler. No assembly attempted."));
2849 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2851 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
2852 decode_mips_operand
))
2854 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2856 create_insn (&nop_insn
, mips_opcodes
+ i
);
2857 if (mips_fix_loongson2f_nop
)
2858 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2859 nop_insn
.fixed_p
= 1;
2864 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2867 mips16_op_hash
= hash_new ();
2870 while (i
< bfd_mips16_num_opcodes
)
2872 const char *name
= mips16_opcodes
[i
].name
;
2874 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2876 as_fatal (_("internal: can't hash `%s': %s"),
2877 mips16_opcodes
[i
].name
, retval
);
2880 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2881 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2882 != mips16_opcodes
[i
].match
))
2884 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2885 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2888 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2890 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2891 mips16_nop_insn
.fixed_p
= 1;
2895 while (i
< bfd_mips16_num_opcodes
2896 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2899 micromips_op_hash
= hash_new ();
2902 while (i
< bfd_micromips_num_opcodes
)
2904 const char *name
= micromips_opcodes
[i
].name
;
2906 retval
= hash_insert (micromips_op_hash
, name
,
2907 (void *) µmips_opcodes
[i
]);
2909 as_fatal (_("internal: can't hash `%s': %s"),
2910 micromips_opcodes
[i
].name
, retval
);
2912 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2914 struct mips_cl_insn
*micromips_nop_insn
;
2916 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2919 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2920 micromips_nop_insn
= µmips_nop16_insn
;
2921 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2922 micromips_nop_insn
= µmips_nop32_insn
;
2926 if (micromips_nop_insn
->insn_mo
== NULL
2927 && strcmp (name
, "nop") == 0)
2929 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2930 micromips_nop_insn
->fixed_p
= 1;
2933 while (++i
< bfd_micromips_num_opcodes
2934 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2938 as_fatal (_("Broken assembler. No assembly attempted."));
2940 /* We add all the general register names to the symbol table. This
2941 helps us detect invalid uses of them. */
2942 for (i
= 0; reg_names
[i
].name
; i
++)
2943 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2944 reg_names
[i
].num
, /* & RNUM_MASK, */
2945 &zero_address_frag
));
2947 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2948 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2949 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2950 &zero_address_frag
));
2952 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2953 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2954 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2955 &zero_address_frag
));
2957 mips_no_prev_insn ();
2960 mips_cprmask
[0] = 0;
2961 mips_cprmask
[1] = 0;
2962 mips_cprmask
[2] = 0;
2963 mips_cprmask
[3] = 0;
2965 /* set the default alignment for the text section (2**2) */
2966 record_alignment (text_section
, 2);
2968 bfd_set_gp_size (stdoutput
, g_switch_value
);
2970 /* On a native system other than VxWorks, sections must be aligned
2971 to 16 byte boundaries. When configured for an embedded ELF
2972 target, we don't bother. */
2973 if (strncmp (TARGET_OS
, "elf", 3) != 0
2974 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2976 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2977 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2978 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2981 /* Create a .reginfo section for register masks and a .mdebug
2982 section for debugging information. */
2990 subseg
= now_subseg
;
2992 /* The ABI says this section should be loaded so that the
2993 running program can access it. However, we don't load it
2994 if we are configured for an embedded target */
2995 flags
= SEC_READONLY
| SEC_DATA
;
2996 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2997 flags
|= SEC_ALLOC
| SEC_LOAD
;
2999 if (mips_abi
!= N64_ABI
)
3001 sec
= subseg_new (".reginfo", (subsegT
) 0);
3003 bfd_set_section_flags (stdoutput
, sec
, flags
);
3004 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3006 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3010 /* The 64-bit ABI uses a .MIPS.options section rather than
3011 .reginfo section. */
3012 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3013 bfd_set_section_flags (stdoutput
, sec
, flags
);
3014 bfd_set_section_alignment (stdoutput
, sec
, 3);
3016 /* Set up the option header. */
3018 Elf_Internal_Options opthdr
;
3021 opthdr
.kind
= ODK_REGINFO
;
3022 opthdr
.size
= (sizeof (Elf_External_Options
)
3023 + sizeof (Elf64_External_RegInfo
));
3026 f
= frag_more (sizeof (Elf_External_Options
));
3027 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3028 (Elf_External_Options
*) f
);
3030 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3034 if (ECOFF_DEBUGGING
)
3036 sec
= subseg_new (".mdebug", (subsegT
) 0);
3037 (void) bfd_set_section_flags (stdoutput
, sec
,
3038 SEC_HAS_CONTENTS
| SEC_READONLY
);
3039 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3041 else if (mips_flag_pdr
)
3043 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3044 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3045 SEC_READONLY
| SEC_RELOC
3047 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3050 subseg_set (seg
, subseg
);
3053 if (! ECOFF_DEBUGGING
)
3056 if (mips_fix_vr4120
)
3057 init_vr4120_conflicts ();
3063 mips_emit_delays ();
3064 if (! ECOFF_DEBUGGING
)
3069 md_assemble (char *str
)
3071 struct mips_cl_insn insn
;
3072 bfd_reloc_code_real_type unused_reloc
[3]
3073 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3075 imm_expr
.X_op
= O_absent
;
3076 imm2_expr
.X_op
= O_absent
;
3077 offset_expr
.X_op
= O_absent
;
3078 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3079 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3080 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3082 mips_mark_labels ();
3083 mips_assembling_insn
= TRUE
;
3085 if (mips_opts
.mips16
)
3086 mips16_ip (str
, &insn
);
3089 mips_ip (str
, &insn
);
3090 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3091 str
, insn
.insn_opcode
));
3095 as_bad ("%s `%s'", insn_error
, str
);
3096 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3099 if (mips_opts
.mips16
)
3100 mips16_macro (&insn
);
3107 if (offset_expr
.X_op
!= O_absent
)
3108 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3110 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3113 mips_assembling_insn
= FALSE
;
3116 /* Convenience functions for abstracting away the differences between
3117 MIPS16 and non-MIPS16 relocations. */
3119 static inline bfd_boolean
3120 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3124 case BFD_RELOC_MIPS16_JMP
:
3125 case BFD_RELOC_MIPS16_GPREL
:
3126 case BFD_RELOC_MIPS16_GOT16
:
3127 case BFD_RELOC_MIPS16_CALL16
:
3128 case BFD_RELOC_MIPS16_HI16_S
:
3129 case BFD_RELOC_MIPS16_HI16
:
3130 case BFD_RELOC_MIPS16_LO16
:
3138 static inline bfd_boolean
3139 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3143 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3144 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3145 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3146 case BFD_RELOC_MICROMIPS_GPREL16
:
3147 case BFD_RELOC_MICROMIPS_JMP
:
3148 case BFD_RELOC_MICROMIPS_HI16
:
3149 case BFD_RELOC_MICROMIPS_HI16_S
:
3150 case BFD_RELOC_MICROMIPS_LO16
:
3151 case BFD_RELOC_MICROMIPS_LITERAL
:
3152 case BFD_RELOC_MICROMIPS_GOT16
:
3153 case BFD_RELOC_MICROMIPS_CALL16
:
3154 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3155 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3156 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3157 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3158 case BFD_RELOC_MICROMIPS_SUB
:
3159 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3160 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3161 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3162 case BFD_RELOC_MICROMIPS_HIGHEST
:
3163 case BFD_RELOC_MICROMIPS_HIGHER
:
3164 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3165 case BFD_RELOC_MICROMIPS_JALR
:
3173 static inline bfd_boolean
3174 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3176 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3179 static inline bfd_boolean
3180 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3182 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3183 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3186 static inline bfd_boolean
3187 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3189 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3190 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3193 static inline bfd_boolean
3194 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3196 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3197 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3200 static inline bfd_boolean
3201 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3203 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3206 static inline bfd_boolean
3207 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3209 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3210 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3213 /* Return true if RELOC is a PC-relative relocation that does not have
3214 full address range. */
3216 static inline bfd_boolean
3217 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3221 case BFD_RELOC_16_PCREL_S2
:
3222 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3223 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3224 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3227 case BFD_RELOC_32_PCREL
:
3228 return HAVE_64BIT_ADDRESSES
;
3235 /* Return true if the given relocation might need a matching %lo().
3236 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3237 need a matching %lo() when applied to local symbols. */
3239 static inline bfd_boolean
3240 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3242 return (HAVE_IN_PLACE_ADDENDS
3243 && (hi16_reloc_p (reloc
)
3244 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3245 all GOT16 relocations evaluate to "G". */
3246 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3249 /* Return the type of %lo() reloc needed by RELOC, given that
3250 reloc_needs_lo_p. */
3252 static inline bfd_reloc_code_real_type
3253 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3255 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3256 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3260 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3263 static inline bfd_boolean
3264 fixup_has_matching_lo_p (fixS
*fixp
)
3266 return (fixp
->fx_next
!= NULL
3267 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3268 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3269 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3272 /* This function returns true if modifying a register requires a
3276 reg_needs_delay (unsigned int reg
)
3278 unsigned long prev_pinfo
;
3280 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3281 if (! mips_opts
.noreorder
3282 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3283 && ! gpr_interlocks
)
3284 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3285 && ! cop_interlocks
)))
3287 /* A load from a coprocessor or from memory. All load delays
3288 delay the use of general register rt for one instruction. */
3289 /* Itbl support may require additional care here. */
3290 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3291 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3298 /* Move all labels in LABELS to the current insertion point. TEXT_P
3299 says whether the labels refer to text or data. */
3302 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3304 struct insn_label_list
*l
;
3307 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3309 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3310 symbol_set_frag (l
->label
, frag_now
);
3311 val
= (valueT
) frag_now_fix ();
3312 /* MIPS16/microMIPS text labels are stored as odd. */
3313 if (text_p
&& HAVE_CODE_COMPRESSION
)
3315 S_SET_VALUE (l
->label
, val
);
3319 /* Move all labels in insn_labels to the current insertion point
3320 and treat them as text labels. */
3323 mips_move_text_labels (void)
3325 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3329 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3331 bfd_boolean linkonce
= FALSE
;
3332 segT symseg
= S_GET_SEGMENT (sym
);
3334 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3336 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3338 /* The GNU toolchain uses an extension for ELF: a section
3339 beginning with the magic string .gnu.linkonce is a
3340 linkonce section. */
3341 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3342 sizeof ".gnu.linkonce" - 1) == 0)
3348 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3349 linker to handle them specially, such as generating jalx instructions
3350 when needed. We also make them odd for the duration of the assembly,
3351 in order to generate the right sort of code. We will make them even
3352 in the adjust_symtab routine, while leaving them marked. This is
3353 convenient for the debugger and the disassembler. The linker knows
3354 to make them odd again. */
3357 mips_compressed_mark_label (symbolS
*label
)
3359 gas_assert (HAVE_CODE_COMPRESSION
);
3361 if (mips_opts
.mips16
)
3362 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3364 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3365 if ((S_GET_VALUE (label
) & 1) == 0
3366 /* Don't adjust the address if the label is global or weak, or
3367 in a link-once section, since we'll be emitting symbol reloc
3368 references to it which will be patched up by the linker, and
3369 the final value of the symbol may or may not be MIPS16/microMIPS. */
3370 && !S_IS_WEAK (label
)
3371 && !S_IS_EXTERNAL (label
)
3372 && !s_is_linkonce (label
, now_seg
))
3373 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3376 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3379 mips_compressed_mark_labels (void)
3381 struct insn_label_list
*l
;
3383 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3384 mips_compressed_mark_label (l
->label
);
3387 /* End the current frag. Make it a variant frag and record the
3391 relax_close_frag (void)
3393 mips_macro_warning
.first_frag
= frag_now
;
3394 frag_var (rs_machine_dependent
, 0, 0,
3395 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3396 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3398 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3399 mips_relax
.first_fixup
= 0;
3402 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3403 See the comment above RELAX_ENCODE for more details. */
3406 relax_start (symbolS
*symbol
)
3408 gas_assert (mips_relax
.sequence
== 0);
3409 mips_relax
.sequence
= 1;
3410 mips_relax
.symbol
= symbol
;
3413 /* Start generating the second version of a relaxable sequence.
3414 See the comment above RELAX_ENCODE for more details. */
3419 gas_assert (mips_relax
.sequence
== 1);
3420 mips_relax
.sequence
= 2;
3423 /* End the current relaxable sequence. */
3428 gas_assert (mips_relax
.sequence
== 2);
3429 relax_close_frag ();
3430 mips_relax
.sequence
= 0;
3433 /* Return true if IP is a delayed branch or jump. */
3435 static inline bfd_boolean
3436 delayed_branch_p (const struct mips_cl_insn
*ip
)
3438 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3439 | INSN_COND_BRANCH_DELAY
3440 | INSN_COND_BRANCH_LIKELY
)) != 0;
3443 /* Return true if IP is a compact branch or jump. */
3445 static inline bfd_boolean
3446 compact_branch_p (const struct mips_cl_insn
*ip
)
3448 if (mips_opts
.mips16
)
3449 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3450 | MIPS16_INSN_COND_BRANCH
)) != 0;
3452 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3453 | INSN2_COND_BRANCH
)) != 0;
3456 /* Return true if IP is an unconditional branch or jump. */
3458 static inline bfd_boolean
3459 uncond_branch_p (const struct mips_cl_insn
*ip
)
3461 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3462 || (mips_opts
.mips16
3463 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3464 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3467 /* Return true if IP is a branch-likely instruction. */
3469 static inline bfd_boolean
3470 branch_likely_p (const struct mips_cl_insn
*ip
)
3472 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3475 /* Return the type of nop that should be used to fill the delay slot
3476 of delayed branch IP. */
3478 static struct mips_cl_insn
*
3479 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3481 if (mips_opts
.micromips
3482 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3483 return µmips_nop32_insn
;
3487 /* Return the mask of core registers that IP reads or writes. */
3490 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3492 unsigned long pinfo2
;
3496 pinfo2
= ip
->insn_mo
->pinfo2
;
3497 if (mips_opts
.micromips
)
3499 if (pinfo2
& INSN2_MOD_GPR_MD
)
3500 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3501 if (pinfo2
& INSN2_MOD_GPR_MF
)
3502 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3503 if (pinfo2
& INSN2_MOD_SP
)
3509 /* Return the mask of core registers that IP reads. */
3512 gpr_read_mask (const struct mips_cl_insn
*ip
)
3514 unsigned long pinfo
, pinfo2
;
3517 mask
= gpr_mod_mask (ip
);
3518 pinfo
= ip
->insn_mo
->pinfo
;
3519 pinfo2
= ip
->insn_mo
->pinfo2
;
3520 if (mips_opts
.mips16
)
3522 if (pinfo
& MIPS16_INSN_READ_X
)
3523 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3524 if (pinfo
& MIPS16_INSN_READ_Y
)
3525 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3526 if (pinfo
& MIPS16_INSN_READ_T
)
3528 if (pinfo
& MIPS16_INSN_READ_SP
)
3530 if (pinfo
& MIPS16_INSN_READ_31
)
3532 if (pinfo
& MIPS16_INSN_READ_Z
)
3533 mask
|= 1 << (mips16_to_32_reg_map
3534 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3535 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3536 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3540 if (pinfo2
& INSN2_READ_GPR_D
)
3541 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3542 if (pinfo
& INSN_READ_GPR_T
)
3543 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3544 if (pinfo
& INSN_READ_GPR_S
)
3545 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3546 if (pinfo2
& INSN2_READ_GP
)
3548 if (pinfo2
& INSN2_READ_GPR_31
)
3550 if (pinfo2
& INSN2_READ_GPR_Z
)
3551 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3553 if (mips_opts
.micromips
)
3555 if (pinfo2
& INSN2_READ_GPR_MC
)
3556 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3557 if (pinfo2
& INSN2_READ_GPR_ME
)
3558 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3559 if (pinfo2
& INSN2_READ_GPR_MG
)
3560 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3561 if (pinfo2
& INSN2_READ_GPR_MJ
)
3562 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3563 if (pinfo2
& INSN2_READ_GPR_MMN
)
3565 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3566 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3568 if (pinfo2
& INSN2_READ_GPR_MP
)
3569 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3570 if (pinfo2
& INSN2_READ_GPR_MQ
)
3571 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3573 /* Don't include register 0. */
3577 /* Return the mask of core registers that IP writes. */
3580 gpr_write_mask (const struct mips_cl_insn
*ip
)
3582 unsigned long pinfo
, pinfo2
;
3585 mask
= gpr_mod_mask (ip
);
3586 pinfo
= ip
->insn_mo
->pinfo
;
3587 pinfo2
= ip
->insn_mo
->pinfo2
;
3588 if (mips_opts
.mips16
)
3590 if (pinfo
& MIPS16_INSN_WRITE_X
)
3591 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3592 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3593 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3594 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3595 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3596 if (pinfo
& MIPS16_INSN_WRITE_T
)
3598 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3600 if (pinfo
& MIPS16_INSN_WRITE_31
)
3602 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3603 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3607 if (pinfo
& INSN_WRITE_GPR_D
)
3608 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3609 if (pinfo
& INSN_WRITE_GPR_T
)
3610 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3611 if (pinfo
& INSN_WRITE_GPR_S
)
3612 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3613 if (pinfo
& INSN_WRITE_GPR_31
)
3615 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3616 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3618 if (mips_opts
.micromips
)
3620 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3621 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3622 if (pinfo2
& INSN2_WRITE_GPR_MH
)
3624 mask
|= 1 << micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
3625 mask
|= 1 << micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
3627 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3628 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3629 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3630 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3632 /* Don't include register 0. */
3636 /* Return the mask of floating-point registers that IP reads. */
3639 fpr_read_mask (const struct mips_cl_insn
*ip
)
3641 unsigned long pinfo
, pinfo2
;
3645 pinfo
= ip
->insn_mo
->pinfo
;
3646 pinfo2
= ip
->insn_mo
->pinfo2
;
3647 if (!mips_opts
.mips16
)
3649 if (pinfo2
& INSN2_READ_FPR_D
)
3650 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3651 if (pinfo
& INSN_READ_FPR_S
)
3652 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3653 if (pinfo
& INSN_READ_FPR_T
)
3654 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3655 if (pinfo
& INSN_READ_FPR_R
)
3656 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3657 if (pinfo2
& INSN2_READ_FPR_Z
)
3658 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3660 /* Conservatively treat all operands to an FP_D instruction are doubles.
3661 (This is overly pessimistic for things like cvt.d.s.) */
3662 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3667 /* Return the mask of floating-point registers that IP writes. */
3670 fpr_write_mask (const struct mips_cl_insn
*ip
)
3672 unsigned long pinfo
, pinfo2
;
3676 pinfo
= ip
->insn_mo
->pinfo
;
3677 pinfo2
= ip
->insn_mo
->pinfo2
;
3678 if (!mips_opts
.mips16
)
3680 if (pinfo
& INSN_WRITE_FPR_D
)
3681 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3682 if (pinfo
& INSN_WRITE_FPR_S
)
3683 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3684 if (pinfo
& INSN_WRITE_FPR_T
)
3685 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3686 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3687 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3689 /* Conservatively treat all operands to an FP_D instruction are doubles.
3690 (This is overly pessimistic for things like cvt.s.d.) */
3691 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3696 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3697 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3698 by VR4120 errata. */
3701 classify_vr4120_insn (const char *name
)
3703 if (strncmp (name
, "macc", 4) == 0)
3704 return FIX_VR4120_MACC
;
3705 if (strncmp (name
, "dmacc", 5) == 0)
3706 return FIX_VR4120_DMACC
;
3707 if (strncmp (name
, "mult", 4) == 0)
3708 return FIX_VR4120_MULT
;
3709 if (strncmp (name
, "dmult", 5) == 0)
3710 return FIX_VR4120_DMULT
;
3711 if (strstr (name
, "div"))
3712 return FIX_VR4120_DIV
;
3713 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3714 return FIX_VR4120_MTHILO
;
3715 return NUM_FIX_VR4120_CLASSES
;
3718 #define INSN_ERET 0x42000018
3719 #define INSN_DERET 0x4200001f
3721 /* Return the number of instructions that must separate INSN1 and INSN2,
3722 where INSN1 is the earlier instruction. Return the worst-case value
3723 for any INSN2 if INSN2 is null. */
3726 insns_between (const struct mips_cl_insn
*insn1
,
3727 const struct mips_cl_insn
*insn2
)
3729 unsigned long pinfo1
, pinfo2
;
3732 /* This function needs to know which pinfo flags are set for INSN2
3733 and which registers INSN2 uses. The former is stored in PINFO2 and
3734 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3735 will have every flag set and INSN2_USES_GPR will always return true. */
3736 pinfo1
= insn1
->insn_mo
->pinfo
;
3737 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3739 #define INSN2_USES_GPR(REG) \
3740 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3742 /* For most targets, write-after-read dependencies on the HI and LO
3743 registers must be separated by at least two instructions. */
3744 if (!hilo_interlocks
)
3746 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3748 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3752 /* If we're working around r7000 errata, there must be two instructions
3753 between an mfhi or mflo and any instruction that uses the result. */
3754 if (mips_7000_hilo_fix
3755 && !mips_opts
.micromips
3756 && MF_HILO_INSN (pinfo1
)
3757 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3760 /* If we're working around 24K errata, one instruction is required
3761 if an ERET or DERET is followed by a branch instruction. */
3762 if (mips_fix_24k
&& !mips_opts
.micromips
)
3764 if (insn1
->insn_opcode
== INSN_ERET
3765 || insn1
->insn_opcode
== INSN_DERET
)
3768 || insn2
->insn_opcode
== INSN_ERET
3769 || insn2
->insn_opcode
== INSN_DERET
3770 || delayed_branch_p (insn2
))
3775 /* If working around VR4120 errata, check for combinations that need
3776 a single intervening instruction. */
3777 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3779 unsigned int class1
, class2
;
3781 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3782 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3786 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3787 if (vr4120_conflicts
[class1
] & (1 << class2
))
3792 if (!HAVE_CODE_COMPRESSION
)
3794 /* Check for GPR or coprocessor load delays. All such delays
3795 are on the RT register. */
3796 /* Itbl support may require additional care here. */
3797 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3798 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3800 know (pinfo1
& INSN_WRITE_GPR_T
);
3801 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3805 /* Check for generic coprocessor hazards.
3807 This case is not handled very well. There is no special
3808 knowledge of CP0 handling, and the coprocessors other than
3809 the floating point unit are not distinguished at all. */
3810 /* Itbl support may require additional care here. FIXME!
3811 Need to modify this to include knowledge about
3812 user specified delays! */
3813 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3814 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3816 /* Handle cases where INSN1 writes to a known general coprocessor
3817 register. There must be a one instruction delay before INSN2
3818 if INSN2 reads that register, otherwise no delay is needed. */
3819 mask
= fpr_write_mask (insn1
);
3822 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3827 /* Read-after-write dependencies on the control registers
3828 require a two-instruction gap. */
3829 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3830 && (pinfo2
& INSN_READ_COND_CODE
))
3833 /* We don't know exactly what INSN1 does. If INSN2 is
3834 also a coprocessor instruction, assume there must be
3835 a one instruction gap. */
3836 if (pinfo2
& INSN_COP
)
3841 /* Check for read-after-write dependencies on the coprocessor
3842 control registers in cases where INSN1 does not need a general
3843 coprocessor delay. This means that INSN1 is a floating point
3844 comparison instruction. */
3845 /* Itbl support may require additional care here. */
3846 else if (!cop_interlocks
3847 && (pinfo1
& INSN_WRITE_COND_CODE
)
3848 && (pinfo2
& INSN_READ_COND_CODE
))
3852 #undef INSN2_USES_GPR
3857 /* Return the number of nops that would be needed to work around the
3858 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3859 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3860 that are contained within the first IGNORE instructions of HIST. */
3863 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3864 const struct mips_cl_insn
*insn
)
3869 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3870 are not affected by the errata. */
3872 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3873 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3874 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3877 /* Search for the first MFLO or MFHI. */
3878 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3879 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3881 /* Extract the destination register. */
3882 mask
= gpr_write_mask (&hist
[i
]);
3884 /* No nops are needed if INSN reads that register. */
3885 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3888 /* ...or if any of the intervening instructions do. */
3889 for (j
= 0; j
< i
; j
++)
3890 if (gpr_read_mask (&hist
[j
]) & mask
)
3894 return MAX_VR4130_NOPS
- i
;
3899 #define BASE_REG_EQ(INSN1, INSN2) \
3900 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3901 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3903 /* Return the minimum alignment for this store instruction. */
3906 fix_24k_align_to (const struct mips_opcode
*mo
)
3908 if (strcmp (mo
->name
, "sh") == 0)
3911 if (strcmp (mo
->name
, "swc1") == 0
3912 || strcmp (mo
->name
, "swc2") == 0
3913 || strcmp (mo
->name
, "sw") == 0
3914 || strcmp (mo
->name
, "sc") == 0
3915 || strcmp (mo
->name
, "s.s") == 0)
3918 if (strcmp (mo
->name
, "sdc1") == 0
3919 || strcmp (mo
->name
, "sdc2") == 0
3920 || strcmp (mo
->name
, "s.d") == 0)
3927 struct fix_24k_store_info
3929 /* Immediate offset, if any, for this store instruction. */
3931 /* Alignment required by this store instruction. */
3933 /* True for register offsets. */
3934 int register_offset
;
3937 /* Comparison function used by qsort. */
3940 fix_24k_sort (const void *a
, const void *b
)
3942 const struct fix_24k_store_info
*pos1
= a
;
3943 const struct fix_24k_store_info
*pos2
= b
;
3945 return (pos1
->off
- pos2
->off
);
3948 /* INSN is a store instruction. Try to record the store information
3949 in STINFO. Return false if the information isn't known. */
3952 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3953 const struct mips_cl_insn
*insn
)
3955 /* The instruction must have a known offset. */
3956 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3959 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3960 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3964 /* Return the number of nops that would be needed to work around the 24k
3965 "lost data on stores during refill" errata if instruction INSN
3966 immediately followed the 2 instructions described by HIST.
3967 Ignore hazards that are contained within the first IGNORE
3968 instructions of HIST.
3970 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3971 for the data cache refills and store data. The following describes
3972 the scenario where the store data could be lost.
3974 * A data cache miss, due to either a load or a store, causing fill
3975 data to be supplied by the memory subsystem
3976 * The first three doublewords of fill data are returned and written
3978 * A sequence of four stores occurs in consecutive cycles around the
3979 final doubleword of the fill:
3983 * Zero, One or more instructions
3986 The four stores A-D must be to different doublewords of the line that
3987 is being filled. The fourth instruction in the sequence above permits
3988 the fill of the final doubleword to be transferred from the FSB into
3989 the cache. In the sequence above, the stores may be either integer
3990 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3991 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3992 different doublewords on the line. If the floating point unit is
3993 running in 1:2 mode, it is not possible to create the sequence above
3994 using only floating point store instructions.
3996 In this case, the cache line being filled is incorrectly marked
3997 invalid, thereby losing the data from any store to the line that
3998 occurs between the original miss and the completion of the five
3999 cycle sequence shown above.
4001 The workarounds are:
4003 * Run the data cache in write-through mode.
4004 * Insert a non-store instruction between
4005 Store A and Store B or Store B and Store C. */
4008 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
4009 const struct mips_cl_insn
*insn
)
4011 struct fix_24k_store_info pos
[3];
4012 int align
, i
, base_offset
;
4017 /* If the previous instruction wasn't a store, there's nothing to
4019 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
4022 /* If the instructions after the previous one are unknown, we have
4023 to assume the worst. */
4027 /* Check whether we are dealing with three consecutive stores. */
4028 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
4029 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
4032 /* If we don't know the relationship between the store addresses,
4033 assume the worst. */
4034 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
4035 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
4038 if (!fix_24k_record_store_info (&pos
[0], insn
)
4039 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
4040 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
4043 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
4045 /* Pick a value of ALIGN and X such that all offsets are adjusted by
4046 X bytes and such that the base register + X is known to be aligned
4049 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
4053 align
= pos
[0].align_to
;
4054 base_offset
= pos
[0].off
;
4055 for (i
= 1; i
< 3; i
++)
4056 if (align
< pos
[i
].align_to
)
4058 align
= pos
[i
].align_to
;
4059 base_offset
= pos
[i
].off
;
4061 for (i
= 0; i
< 3; i
++)
4062 pos
[i
].off
-= base_offset
;
4065 pos
[0].off
&= ~align
+ 1;
4066 pos
[1].off
&= ~align
+ 1;
4067 pos
[2].off
&= ~align
+ 1;
4069 /* If any two stores write to the same chunk, they also write to the
4070 same doubleword. The offsets are still sorted at this point. */
4071 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
4074 /* A range of at least 9 bytes is needed for the stores to be in
4075 non-overlapping doublewords. */
4076 if (pos
[2].off
- pos
[0].off
<= 8)
4079 if (pos
[2].off
- pos
[1].off
>= 24
4080 || pos
[1].off
- pos
[0].off
>= 24
4081 || pos
[2].off
- pos
[0].off
>= 32)
4087 /* Return the number of nops that would be needed if instruction INSN
4088 immediately followed the MAX_NOPS instructions given by HIST,
4089 where HIST[0] is the most recent instruction. Ignore hazards
4090 between INSN and the first IGNORE instructions in HIST.
4092 If INSN is null, return the worse-case number of nops for any
4096 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
4097 const struct mips_cl_insn
*insn
)
4099 int i
, nops
, tmp_nops
;
4102 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
4104 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
4105 if (tmp_nops
> nops
)
4109 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
4111 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
4112 if (tmp_nops
> nops
)
4116 if (mips_fix_24k
&& !mips_opts
.micromips
)
4118 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
4119 if (tmp_nops
> nops
)
4126 /* The variable arguments provide NUM_INSNS extra instructions that
4127 might be added to HIST. Return the largest number of nops that
4128 would be needed after the extended sequence, ignoring hazards
4129 in the first IGNORE instructions. */
4132 nops_for_sequence (int num_insns
, int ignore
,
4133 const struct mips_cl_insn
*hist
, ...)
4136 struct mips_cl_insn buffer
[MAX_NOPS
];
4137 struct mips_cl_insn
*cursor
;
4140 va_start (args
, hist
);
4141 cursor
= buffer
+ num_insns
;
4142 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
4143 while (cursor
> buffer
)
4144 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
4146 nops
= nops_for_insn (ignore
, buffer
, NULL
);
4151 /* Like nops_for_insn, but if INSN is a branch, take into account the
4152 worst-case delay for the branch target. */
4155 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
4156 const struct mips_cl_insn
*insn
)
4160 nops
= nops_for_insn (ignore
, hist
, insn
);
4161 if (delayed_branch_p (insn
))
4163 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
4164 hist
, insn
, get_delay_slot_nop (insn
));
4165 if (tmp_nops
> nops
)
4168 else if (compact_branch_p (insn
))
4170 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
4171 if (tmp_nops
> nops
)
4177 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4180 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
4182 gas_assert (!HAVE_CODE_COMPRESSION
);
4183 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
4184 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
4187 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4188 jr target pc &= 'hffff_ffff_cfff_ffff. */
4191 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
4193 gas_assert (!HAVE_CODE_COMPRESSION
);
4194 if (strcmp (ip
->insn_mo
->name
, "j") == 0
4195 || strcmp (ip
->insn_mo
->name
, "jr") == 0
4196 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
4204 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
4205 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
4208 ep
.X_op
= O_constant
;
4209 ep
.X_add_number
= 0xcfff0000;
4210 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
4211 ep
.X_add_number
= 0xffff;
4212 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
4213 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
4218 fix_loongson2f (struct mips_cl_insn
* ip
)
4220 if (mips_fix_loongson2f_nop
)
4221 fix_loongson2f_nop (ip
);
4223 if (mips_fix_loongson2f_jump
)
4224 fix_loongson2f_jump (ip
);
4227 /* IP is a branch that has a delay slot, and we need to fill it
4228 automatically. Return true if we can do that by swapping IP
4229 with the previous instruction.
4230 ADDRESS_EXPR is an operand of the instruction to be used with
4234 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4235 bfd_reloc_code_real_type
*reloc_type
)
4237 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
4238 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
4240 /* -O2 and above is required for this optimization. */
4241 if (mips_optimize
< 2)
4244 /* If we have seen .set volatile or .set nomove, don't optimize. */
4245 if (mips_opts
.nomove
)
4248 /* We can't swap if the previous instruction's position is fixed. */
4249 if (history
[0].fixed_p
)
4252 /* If the previous previous insn was in a .set noreorder, we can't
4253 swap. Actually, the MIPS assembler will swap in this situation.
4254 However, gcc configured -with-gnu-as will generate code like
4262 in which we can not swap the bne and INSN. If gcc is not configured
4263 -with-gnu-as, it does not output the .set pseudo-ops. */
4264 if (history
[1].noreorder_p
)
4267 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4268 This means that the previous instruction was a 4-byte one anyhow. */
4269 if (mips_opts
.mips16
&& history
[0].fixp
[0])
4272 /* If the branch is itself the target of a branch, we can not swap.
4273 We cheat on this; all we check for is whether there is a label on
4274 this instruction. If there are any branches to anything other than
4275 a label, users must use .set noreorder. */
4276 if (seg_info (now_seg
)->label_list
)
4279 /* If the previous instruction is in a variant frag other than this
4280 branch's one, we cannot do the swap. This does not apply to
4281 MIPS16 code, which uses variant frags for different purposes. */
4282 if (!mips_opts
.mips16
4284 && history
[0].frag
->fr_type
== rs_machine_dependent
)
4287 /* We do not swap with instructions that cannot architecturally
4288 be placed in a branch delay slot, such as SYNC or ERET. We
4289 also refrain from swapping with a trap instruction, since it
4290 complicates trap handlers to have the trap instruction be in
4292 prev_pinfo
= history
[0].insn_mo
->pinfo
;
4293 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
4296 /* Check for conflicts between the branch and the instructions
4297 before the candidate delay slot. */
4298 if (nops_for_insn (0, history
+ 1, ip
) > 0)
4301 /* Check for conflicts between the swapped sequence and the
4302 target of the branch. */
4303 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
4306 /* If the branch reads a register that the previous
4307 instruction sets, we can not swap. */
4308 gpr_read
= gpr_read_mask (ip
);
4309 prev_gpr_write
= gpr_write_mask (&history
[0]);
4310 if (gpr_read
& prev_gpr_write
)
4313 /* If the branch writes a register that the previous
4314 instruction sets, we can not swap. */
4315 gpr_write
= gpr_write_mask (ip
);
4316 if (gpr_write
& prev_gpr_write
)
4319 /* If the branch writes a register that the previous
4320 instruction reads, we can not swap. */
4321 prev_gpr_read
= gpr_read_mask (&history
[0]);
4322 if (gpr_write
& prev_gpr_read
)
4325 /* If one instruction sets a condition code and the
4326 other one uses a condition code, we can not swap. */
4327 pinfo
= ip
->insn_mo
->pinfo
;
4328 if ((pinfo
& INSN_READ_COND_CODE
)
4329 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
4331 if ((pinfo
& INSN_WRITE_COND_CODE
)
4332 && (prev_pinfo
& INSN_READ_COND_CODE
))
4335 /* If the previous instruction uses the PC, we can not swap. */
4336 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4337 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
4339 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
4342 /* If the previous instruction has an incorrect size for a fixed
4343 branch delay slot in microMIPS mode, we cannot swap. */
4344 pinfo2
= ip
->insn_mo
->pinfo2
;
4345 if (mips_opts
.micromips
4346 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
4347 && insn_length (history
) != 2)
4349 if (mips_opts
.micromips
4350 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
4351 && insn_length (history
) != 4)
4354 /* On R5900 short loops need to be fixed by inserting a nop in
4355 the branch delay slots.
4356 A short loop can be terminated too early. */
4357 if (mips_opts
.arch
== CPU_R5900
4358 /* Check if instruction has a parameter, ignore "j $31". */
4359 && (address_expr
!= NULL
)
4360 /* Parameter must be 16 bit. */
4361 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
4362 /* Branch to same segment. */
4363 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
4364 /* Branch to same code fragment. */
4365 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
4366 /* Can only calculate branch offset if value is known. */
4367 && symbol_constant_p(address_expr
->X_add_symbol
)
4368 /* Check if branch is really conditional. */
4369 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
4370 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
4371 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
4374 /* Check if loop is shorter than 6 instructions including
4375 branch and delay slot. */
4376 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
4383 /* When the loop includes branches or jumps,
4384 it is not a short loop. */
4385 for (i
= 0; i
< (distance
/ 4); i
++)
4387 if ((history
[i
].cleared_p
)
4388 || delayed_branch_p(&history
[i
]))
4396 /* Insert nop after branch to fix short loop. */
4405 /* Decide how we should add IP to the instruction stream.
4406 ADDRESS_EXPR is an operand of the instruction to be used with
4409 static enum append_method
4410 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4411 bfd_reloc_code_real_type
*reloc_type
)
4413 unsigned long pinfo
;
4415 /* The relaxed version of a macro sequence must be inherently
4417 if (mips_relax
.sequence
== 2)
4420 /* We must not dabble with instructions in a ".set norerorder" block. */
4421 if (mips_opts
.noreorder
)
4424 /* Otherwise, it's our responsibility to fill branch delay slots. */
4425 if (delayed_branch_p (ip
))
4427 if (!branch_likely_p (ip
)
4428 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
4431 pinfo
= ip
->insn_mo
->pinfo
;
4432 if (mips_opts
.mips16
4433 && ISA_SUPPORTS_MIPS16E
4434 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
4435 return APPEND_ADD_COMPACT
;
4437 return APPEND_ADD_WITH_NOP
;
4443 /* IP is a MIPS16 instruction whose opcode we have just changed.
4444 Point IP->insn_mo to the new opcode's definition. */
4447 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4449 const struct mips_opcode
*mo
, *end
;
4451 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4452 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4453 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4461 /* For microMIPS macros, we need to generate a local number label
4462 as the target of branches. */
4463 #define MICROMIPS_LABEL_CHAR '\037'
4464 static unsigned long micromips_target_label
;
4465 static char micromips_target_name
[32];
4468 micromips_label_name (void)
4470 char *p
= micromips_target_name
;
4471 char symbol_name_temporary
[24];
4479 l
= micromips_target_label
;
4480 #ifdef LOCAL_LABEL_PREFIX
4481 *p
++ = LOCAL_LABEL_PREFIX
;
4484 *p
++ = MICROMIPS_LABEL_CHAR
;
4487 symbol_name_temporary
[i
++] = l
% 10 + '0';
4492 *p
++ = symbol_name_temporary
[--i
];
4495 return micromips_target_name
;
4499 micromips_label_expr (expressionS
*label_expr
)
4501 label_expr
->X_op
= O_symbol
;
4502 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4503 label_expr
->X_add_number
= 0;
4507 micromips_label_inc (void)
4509 micromips_target_label
++;
4510 *micromips_target_name
= '\0';
4514 micromips_add_label (void)
4518 s
= colon (micromips_label_name ());
4519 micromips_label_inc ();
4520 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4523 /* If assembling microMIPS code, then return the microMIPS reloc
4524 corresponding to the requested one if any. Otherwise return
4525 the reloc unchanged. */
4527 static bfd_reloc_code_real_type
4528 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4530 static const bfd_reloc_code_real_type relocs
[][2] =
4532 /* Keep sorted incrementally by the left-hand key. */
4533 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4534 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4535 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4536 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4537 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4538 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4539 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4540 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4541 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4542 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4543 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4544 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4545 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4546 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4547 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4548 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4549 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4550 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4551 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4552 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4553 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4554 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4555 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4556 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4557 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4558 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4559 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4561 bfd_reloc_code_real_type r
;
4564 if (!mips_opts
.micromips
)
4566 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4572 return relocs
[i
][1];
4577 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4578 Return true on success, storing the resolved value in RESULT. */
4581 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4586 case BFD_RELOC_MIPS_HIGHEST
:
4587 case BFD_RELOC_MICROMIPS_HIGHEST
:
4588 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4591 case BFD_RELOC_MIPS_HIGHER
:
4592 case BFD_RELOC_MICROMIPS_HIGHER
:
4593 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4596 case BFD_RELOC_HI16_S
:
4597 case BFD_RELOC_MICROMIPS_HI16_S
:
4598 case BFD_RELOC_MIPS16_HI16_S
:
4599 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4602 case BFD_RELOC_HI16
:
4603 case BFD_RELOC_MICROMIPS_HI16
:
4604 case BFD_RELOC_MIPS16_HI16
:
4605 *result
= (operand
>> 16) & 0xffff;
4608 case BFD_RELOC_LO16
:
4609 case BFD_RELOC_MICROMIPS_LO16
:
4610 case BFD_RELOC_MIPS16_LO16
:
4611 *result
= operand
& 0xffff;
4614 case BFD_RELOC_UNUSED
:
4623 /* Output an instruction. IP is the instruction information.
4624 ADDRESS_EXPR is an operand of the instruction to be used with
4625 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4626 a macro expansion. */
4629 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4630 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4632 unsigned long prev_pinfo2
, pinfo
;
4633 bfd_boolean relaxed_branch
= FALSE
;
4634 enum append_method method
;
4635 bfd_boolean relax32
;
4638 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4639 fix_loongson2f (ip
);
4641 file_ase_mips16
|= mips_opts
.mips16
;
4642 file_ase_micromips
|= mips_opts
.micromips
;
4644 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4645 pinfo
= ip
->insn_mo
->pinfo
;
4647 if (mips_opts
.micromips
4649 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4650 && micromips_insn_length (ip
->insn_mo
) != 2)
4651 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4652 && micromips_insn_length (ip
->insn_mo
) != 4)))
4653 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4654 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4656 if (address_expr
== NULL
)
4658 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4659 && reloc_type
[1] == BFD_RELOC_UNUSED
4660 && reloc_type
[2] == BFD_RELOC_UNUSED
4661 && address_expr
->X_op
== O_constant
)
4663 switch (*reloc_type
)
4665 case BFD_RELOC_MIPS_JMP
:
4669 shift
= mips_opts
.micromips
? 1 : 2;
4670 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4671 as_bad (_("jump to misaligned address (0x%lx)"),
4672 (unsigned long) address_expr
->X_add_number
);
4673 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4679 case BFD_RELOC_MIPS16_JMP
:
4680 if ((address_expr
->X_add_number
& 3) != 0)
4681 as_bad (_("jump to misaligned address (0x%lx)"),
4682 (unsigned long) address_expr
->X_add_number
);
4684 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4685 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4686 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4690 case BFD_RELOC_16_PCREL_S2
:
4694 shift
= mips_opts
.micromips
? 1 : 2;
4695 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4696 as_bad (_("branch to misaligned address (0x%lx)"),
4697 (unsigned long) address_expr
->X_add_number
);
4698 if (!mips_relax_branch
)
4700 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4701 & ~((1 << (shift
+ 16)) - 1))
4702 as_bad (_("branch address range overflow (0x%lx)"),
4703 (unsigned long) address_expr
->X_add_number
);
4704 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4714 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4717 ip
->insn_opcode
|= value
& 0xffff;
4725 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4727 /* There are a lot of optimizations we could do that we don't.
4728 In particular, we do not, in general, reorder instructions.
4729 If you use gcc with optimization, it will reorder
4730 instructions and generally do much more optimization then we
4731 do here; repeating all that work in the assembler would only
4732 benefit hand written assembly code, and does not seem worth
4734 int nops
= (mips_optimize
== 0
4735 ? nops_for_insn (0, history
, NULL
)
4736 : nops_for_insn_or_target (0, history
, ip
));
4740 unsigned long old_frag_offset
;
4743 old_frag
= frag_now
;
4744 old_frag_offset
= frag_now_fix ();
4746 for (i
= 0; i
< nops
; i
++)
4747 add_fixed_insn (NOP_INSN
);
4748 insert_into_history (0, nops
, NOP_INSN
);
4752 listing_prev_line ();
4753 /* We may be at the start of a variant frag. In case we
4754 are, make sure there is enough space for the frag
4755 after the frags created by listing_prev_line. The
4756 argument to frag_grow here must be at least as large
4757 as the argument to all other calls to frag_grow in
4758 this file. We don't have to worry about being in the
4759 middle of a variant frag, because the variants insert
4760 all needed nop instructions themselves. */
4764 mips_move_text_labels ();
4766 #ifndef NO_ECOFF_DEBUGGING
4767 if (ECOFF_DEBUGGING
)
4768 ecoff_fix_loc (old_frag
, old_frag_offset
);
4772 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4776 /* Work out how many nops in prev_nop_frag are needed by IP,
4777 ignoring hazards generated by the first prev_nop_frag_since
4779 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4780 gas_assert (nops
<= prev_nop_frag_holds
);
4782 /* Enforce NOPS as a minimum. */
4783 if (nops
> prev_nop_frag_required
)
4784 prev_nop_frag_required
= nops
;
4786 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4788 /* Settle for the current number of nops. Update the history
4789 accordingly (for the benefit of any future .set reorder code). */
4790 prev_nop_frag
= NULL
;
4791 insert_into_history (prev_nop_frag_since
,
4792 prev_nop_frag_holds
, NOP_INSN
);
4796 /* Allow this instruction to replace one of the nops that was
4797 tentatively added to prev_nop_frag. */
4798 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4799 prev_nop_frag_holds
--;
4800 prev_nop_frag_since
++;
4804 method
= get_append_method (ip
, address_expr
, reloc_type
);
4805 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4807 dwarf2_emit_insn (0);
4808 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4809 so "move" the instruction address accordingly.
4811 Also, it doesn't seem appropriate for the assembler to reorder .loc
4812 entries. If this instruction is a branch that we are going to swap
4813 with the previous instruction, the two instructions should be
4814 treated as a unit, and the debug information for both instructions
4815 should refer to the start of the branch sequence. Using the
4816 current position is certainly wrong when swapping a 32-bit branch
4817 and a 16-bit delay slot, since the current position would then be
4818 in the middle of a branch. */
4819 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
4821 relax32
= (mips_relax_branch
4822 /* Don't try branch relaxation within .set nomacro, or within
4823 .set noat if we use $at for PIC computations. If it turns
4824 out that the branch was out-of-range, we'll get an error. */
4825 && !mips_opts
.warn_about_macros
4826 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4827 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4828 as they have no complementing branches. */
4829 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
4831 if (!HAVE_CODE_COMPRESSION
4834 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4835 && delayed_branch_p (ip
))
4837 relaxed_branch
= TRUE
;
4838 add_relaxed_insn (ip
, (relaxed_branch_length
4840 uncond_branch_p (ip
) ? -1
4841 : branch_likely_p (ip
) ? 1
4845 uncond_branch_p (ip
),
4846 branch_likely_p (ip
),
4847 pinfo
& INSN_WRITE_GPR_31
,
4849 address_expr
->X_add_symbol
,
4850 address_expr
->X_add_number
);
4851 *reloc_type
= BFD_RELOC_UNUSED
;
4853 else if (mips_opts
.micromips
4855 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4856 || *reloc_type
> BFD_RELOC_UNUSED
)
4857 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4858 /* Don't try branch relaxation when users specify
4859 16-bit/32-bit instructions. */
4860 && !forced_insn_length
)
4862 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4863 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4864 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4865 int compact
= compact_branch_p (ip
);
4866 int al
= pinfo
& INSN_WRITE_GPR_31
;
4869 gas_assert (address_expr
!= NULL
);
4870 gas_assert (!mips_relax
.sequence
);
4872 relaxed_branch
= TRUE
;
4873 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4874 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4875 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4877 address_expr
->X_add_symbol
,
4878 address_expr
->X_add_number
);
4879 *reloc_type
= BFD_RELOC_UNUSED
;
4881 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4883 /* We need to set up a variant frag. */
4884 gas_assert (address_expr
!= NULL
);
4885 add_relaxed_insn (ip
, 4, 0,
4887 (*reloc_type
- BFD_RELOC_UNUSED
,
4888 forced_insn_length
== 2, forced_insn_length
== 4,
4889 delayed_branch_p (&history
[0]),
4890 history
[0].mips16_absolute_jump_p
),
4891 make_expr_symbol (address_expr
), 0);
4893 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4895 if (!delayed_branch_p (ip
))
4896 /* Make sure there is enough room to swap this instruction with
4897 a following jump instruction. */
4899 add_fixed_insn (ip
);
4903 if (mips_opts
.mips16
4904 && mips_opts
.noreorder
4905 && delayed_branch_p (&history
[0]))
4906 as_warn (_("extended instruction in delay slot"));
4908 if (mips_relax
.sequence
)
4910 /* If we've reached the end of this frag, turn it into a variant
4911 frag and record the information for the instructions we've
4913 if (frag_room () < 4)
4914 relax_close_frag ();
4915 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4918 if (mips_relax
.sequence
!= 2)
4920 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4921 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4922 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4923 mips_macro_warning
.insns
[0]++;
4925 if (mips_relax
.sequence
!= 1)
4927 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4928 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4929 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4930 mips_macro_warning
.insns
[1]++;
4933 if (mips_opts
.mips16
)
4936 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4938 add_fixed_insn (ip
);
4941 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4943 bfd_reloc_code_real_type final_type
[3];
4944 reloc_howto_type
*howto0
;
4945 reloc_howto_type
*howto
;
4948 /* Perform any necessary conversion to microMIPS relocations
4949 and find out how many relocations there actually are. */
4950 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4951 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4953 /* In a compound relocation, it is the final (outermost)
4954 operator that determines the relocated field. */
4955 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4960 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4961 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4962 bfd_get_reloc_size (howto
),
4964 howto0
&& howto0
->pc_relative
,
4967 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4968 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4969 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4971 /* These relocations can have an addend that won't fit in
4972 4 octets for 64bit assembly. */
4974 && ! howto
->partial_inplace
4975 && (reloc_type
[0] == BFD_RELOC_16
4976 || reloc_type
[0] == BFD_RELOC_32
4977 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4978 || reloc_type
[0] == BFD_RELOC_GPREL16
4979 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4980 || reloc_type
[0] == BFD_RELOC_GPREL32
4981 || reloc_type
[0] == BFD_RELOC_64
4982 || reloc_type
[0] == BFD_RELOC_CTOR
4983 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4984 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4985 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4986 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4987 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4988 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4989 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4990 || hi16_reloc_p (reloc_type
[0])
4991 || lo16_reloc_p (reloc_type
[0])))
4992 ip
->fixp
[0]->fx_no_overflow
= 1;
4994 /* These relocations can have an addend that won't fit in 2 octets. */
4995 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4996 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4997 ip
->fixp
[0]->fx_no_overflow
= 1;
4999 if (mips_relax
.sequence
)
5001 if (mips_relax
.first_fixup
== 0)
5002 mips_relax
.first_fixup
= ip
->fixp
[0];
5004 else if (reloc_needs_lo_p (*reloc_type
))
5006 struct mips_hi_fixup
*hi_fixup
;
5008 /* Reuse the last entry if it already has a matching %lo. */
5009 hi_fixup
= mips_hi_fixup_list
;
5011 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
5013 hi_fixup
= ((struct mips_hi_fixup
*)
5014 xmalloc (sizeof (struct mips_hi_fixup
)));
5015 hi_fixup
->next
= mips_hi_fixup_list
;
5016 mips_hi_fixup_list
= hi_fixup
;
5018 hi_fixup
->fixp
= ip
->fixp
[0];
5019 hi_fixup
->seg
= now_seg
;
5022 /* Add fixups for the second and third relocations, if given.
5023 Note that the ABI allows the second relocation to be
5024 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
5025 moment we only use RSS_UNDEF, but we could add support
5026 for the others if it ever becomes necessary. */
5027 for (i
= 1; i
< 3; i
++)
5028 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
5030 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
5031 ip
->fixp
[0]->fx_size
, NULL
, 0,
5032 FALSE
, final_type
[i
]);
5034 /* Use fx_tcbit to mark compound relocs. */
5035 ip
->fixp
[0]->fx_tcbit
= 1;
5036 ip
->fixp
[i
]->fx_tcbit
= 1;
5041 /* Update the register mask information. */
5042 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
5043 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
5048 insert_into_history (0, 1, ip
);
5051 case APPEND_ADD_WITH_NOP
:
5053 struct mips_cl_insn
*nop
;
5055 insert_into_history (0, 1, ip
);
5056 nop
= get_delay_slot_nop (ip
);
5057 add_fixed_insn (nop
);
5058 insert_into_history (0, 1, nop
);
5059 if (mips_relax
.sequence
)
5060 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
5064 case APPEND_ADD_COMPACT
:
5065 /* Convert MIPS16 jr/jalr into a "compact" jump. */
5066 gas_assert (mips_opts
.mips16
);
5067 ip
->insn_opcode
|= 0x0080;
5068 find_altered_mips16_opcode (ip
);
5070 insert_into_history (0, 1, ip
);
5075 struct mips_cl_insn delay
= history
[0];
5076 if (mips_opts
.mips16
)
5078 know (delay
.frag
== ip
->frag
);
5079 move_insn (ip
, delay
.frag
, delay
.where
);
5080 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
5082 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
5084 /* Add the delay slot instruction to the end of the
5085 current frag and shrink the fixed part of the
5086 original frag. If the branch occupies the tail of
5087 the latter, move it backwards to cover the gap. */
5088 delay
.frag
->fr_fix
-= branch_disp
;
5089 if (delay
.frag
== ip
->frag
)
5090 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
5091 add_fixed_insn (&delay
);
5095 move_insn (&delay
, ip
->frag
,
5096 ip
->where
- branch_disp
+ insn_length (ip
));
5097 move_insn (ip
, history
[0].frag
, history
[0].where
);
5101 insert_into_history (0, 1, &delay
);
5106 /* If we have just completed an unconditional branch, clear the history. */
5107 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
5108 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
5112 mips_no_prev_insn ();
5114 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5115 history
[i
].cleared_p
= 1;
5118 /* We need to emit a label at the end of branch-likely macros. */
5119 if (emit_branch_likely_macro
)
5121 emit_branch_likely_macro
= FALSE
;
5122 micromips_add_label ();
5125 /* We just output an insn, so the next one doesn't have a label. */
5126 mips_clear_insn_labels ();
5129 /* Forget that there was any previous instruction or label.
5130 When BRANCH is true, the branch history is also flushed. */
5133 mips_no_prev_insn (void)
5135 prev_nop_frag
= NULL
;
5136 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
5137 mips_clear_insn_labels ();
5140 /* This function must be called before we emit something other than
5141 instructions. It is like mips_no_prev_insn except that it inserts
5142 any NOPS that might be needed by previous instructions. */
5145 mips_emit_delays (void)
5147 if (! mips_opts
.noreorder
)
5149 int nops
= nops_for_insn (0, history
, NULL
);
5153 add_fixed_insn (NOP_INSN
);
5154 mips_move_text_labels ();
5157 mips_no_prev_insn ();
5160 /* Start a (possibly nested) noreorder block. */
5163 start_noreorder (void)
5165 if (mips_opts
.noreorder
== 0)
5170 /* None of the instructions before the .set noreorder can be moved. */
5171 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5172 history
[i
].fixed_p
= 1;
5174 /* Insert any nops that might be needed between the .set noreorder
5175 block and the previous instructions. We will later remove any
5176 nops that turn out not to be needed. */
5177 nops
= nops_for_insn (0, history
, NULL
);
5180 if (mips_optimize
!= 0)
5182 /* Record the frag which holds the nop instructions, so
5183 that we can remove them if we don't need them. */
5184 frag_grow (nops
* NOP_INSN_SIZE
);
5185 prev_nop_frag
= frag_now
;
5186 prev_nop_frag_holds
= nops
;
5187 prev_nop_frag_required
= 0;
5188 prev_nop_frag_since
= 0;
5191 for (; nops
> 0; --nops
)
5192 add_fixed_insn (NOP_INSN
);
5194 /* Move on to a new frag, so that it is safe to simply
5195 decrease the size of prev_nop_frag. */
5196 frag_wane (frag_now
);
5198 mips_move_text_labels ();
5200 mips_mark_labels ();
5201 mips_clear_insn_labels ();
5203 mips_opts
.noreorder
++;
5204 mips_any_noreorder
= 1;
5207 /* End a nested noreorder block. */
5210 end_noreorder (void)
5212 mips_opts
.noreorder
--;
5213 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
5215 /* Commit to inserting prev_nop_frag_required nops and go back to
5216 handling nop insertion the .set reorder way. */
5217 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
5219 insert_into_history (prev_nop_frag_since
,
5220 prev_nop_frag_required
, NOP_INSN
);
5221 prev_nop_frag
= NULL
;
5225 /* Set up global variables for the start of a new macro. */
5230 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
5231 memset (&mips_macro_warning
.first_insn_sizes
, 0,
5232 sizeof (mips_macro_warning
.first_insn_sizes
));
5233 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
5234 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
5235 && delayed_branch_p (&history
[0]));
5236 switch (history
[0].insn_mo
->pinfo2
5237 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
5239 case INSN2_BRANCH_DELAY_32BIT
:
5240 mips_macro_warning
.delay_slot_length
= 4;
5242 case INSN2_BRANCH_DELAY_16BIT
:
5243 mips_macro_warning
.delay_slot_length
= 2;
5246 mips_macro_warning
.delay_slot_length
= 0;
5249 mips_macro_warning
.first_frag
= NULL
;
5252 /* Given that a macro is longer than one instruction or of the wrong size,
5253 return the appropriate warning for it. Return null if no warning is
5254 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5255 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5256 and RELAX_NOMACRO. */
5259 macro_warning (relax_substateT subtype
)
5261 if (subtype
& RELAX_DELAY_SLOT
)
5262 return _("Macro instruction expanded into multiple instructions"
5263 " in a branch delay slot");
5264 else if (subtype
& RELAX_NOMACRO
)
5265 return _("Macro instruction expanded into multiple instructions");
5266 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
5267 | RELAX_DELAY_SLOT_SIZE_SECOND
))
5268 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
5269 ? _("Macro instruction expanded into a wrong size instruction"
5270 " in a 16-bit branch delay slot")
5271 : _("Macro instruction expanded into a wrong size instruction"
5272 " in a 32-bit branch delay slot"));
5277 /* Finish up a macro. Emit warnings as appropriate. */
5282 /* Relaxation warning flags. */
5283 relax_substateT subtype
= 0;
5285 /* Check delay slot size requirements. */
5286 if (mips_macro_warning
.delay_slot_length
== 2)
5287 subtype
|= RELAX_DELAY_SLOT_16BIT
;
5288 if (mips_macro_warning
.delay_slot_length
!= 0)
5290 if (mips_macro_warning
.delay_slot_length
5291 != mips_macro_warning
.first_insn_sizes
[0])
5292 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
5293 if (mips_macro_warning
.delay_slot_length
5294 != mips_macro_warning
.first_insn_sizes
[1])
5295 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
5298 /* Check instruction count requirements. */
5299 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
5301 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
5302 subtype
|= RELAX_SECOND_LONGER
;
5303 if (mips_opts
.warn_about_macros
)
5304 subtype
|= RELAX_NOMACRO
;
5305 if (mips_macro_warning
.delay_slot_p
)
5306 subtype
|= RELAX_DELAY_SLOT
;
5309 /* If both alternatives fail to fill a delay slot correctly,
5310 emit the warning now. */
5311 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
5312 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
5317 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
5318 | RELAX_DELAY_SLOT_SIZE_FIRST
5319 | RELAX_DELAY_SLOT_SIZE_SECOND
);
5320 msg
= macro_warning (s
);
5322 as_warn ("%s", msg
);
5326 /* If both implementations are longer than 1 instruction, then emit the
5328 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
5333 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
5334 msg
= macro_warning (s
);
5336 as_warn ("%s", msg
);
5340 /* If any flags still set, then one implementation might need a warning
5341 and the other either will need one of a different kind or none at all.
5342 Pass any remaining flags over to relaxation. */
5343 if (mips_macro_warning
.first_frag
!= NULL
)
5344 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
5347 /* Instruction operand formats used in macros that vary between
5348 standard MIPS and microMIPS code. */
5350 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
5351 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
5352 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
5353 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
5354 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
5355 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
5356 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
5357 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
5359 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5360 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5361 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5362 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5363 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5364 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5365 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5366 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5368 /* Read a macro's relocation codes from *ARGS and store them in *R.
5369 The first argument in *ARGS will be either the code for a single
5370 relocation or -1 followed by the three codes that make up a
5371 composite relocation. */
5374 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
5378 next
= va_arg (*args
, int);
5380 r
[0] = (bfd_reloc_code_real_type
) next
;
5383 for (i
= 0; i
< 3; i
++)
5384 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
5385 /* This function is only used for 16-bit relocation fields.
5386 To make the macro code simpler, treat an unrelocated value
5387 in the same way as BFD_RELOC_LO16. */
5388 if (r
[0] == BFD_RELOC_UNUSED
)
5389 r
[0] = BFD_RELOC_LO16
;
5393 /* Build an instruction created by a macro expansion. This is passed
5394 a pointer to the count of instructions created so far, an
5395 expression, the name of the instruction to build, an operand format
5396 string, and corresponding arguments. */
5399 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
5401 const struct mips_opcode
*mo
= NULL
;
5402 bfd_reloc_code_real_type r
[3];
5403 const struct mips_opcode
*amo
;
5404 struct hash_control
*hash
;
5405 struct mips_cl_insn insn
;
5408 va_start (args
, fmt
);
5410 if (mips_opts
.mips16
)
5412 mips16_macro_build (ep
, name
, fmt
, &args
);
5417 r
[0] = BFD_RELOC_UNUSED
;
5418 r
[1] = BFD_RELOC_UNUSED
;
5419 r
[2] = BFD_RELOC_UNUSED
;
5420 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
5421 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
5423 gas_assert (strcmp (name
, amo
->name
) == 0);
5427 /* Search until we get a match for NAME. It is assumed here that
5428 macros will never generate MDMX, MIPS-3D, or MT instructions.
5429 We try to match an instruction that fulfils the branch delay
5430 slot instruction length requirement (if any) of the previous
5431 instruction. While doing this we record the first instruction
5432 seen that matches all the other conditions and use it anyway
5433 if the requirement cannot be met; we will issue an appropriate
5434 warning later on. */
5435 if (strcmp (fmt
, amo
->args
) == 0
5436 && amo
->pinfo
!= INSN_MACRO
5437 && is_opcode_valid (amo
)
5438 && is_size_valid (amo
))
5440 if (is_delay_slot_valid (amo
))
5450 gas_assert (amo
->name
);
5452 while (strcmp (name
, amo
->name
) == 0);
5455 create_insn (&insn
, mo
);
5473 INSERT_OPERAND (mips_opts
.micromips
,
5474 EXTLSB
, insn
, va_arg (args
, int));
5479 /* Note that in the macro case, these arguments are already
5480 in MSB form. (When handling the instruction in the
5481 non-macro case, these arguments are sizes from which
5482 MSB values must be calculated.) */
5483 INSERT_OPERAND (mips_opts
.micromips
,
5484 INSMSB
, insn
, va_arg (args
, int));
5488 gas_assert (!mips_opts
.micromips
);
5489 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5495 /* Note that in the macro case, these arguments are already
5496 in MSBD form. (When handling the instruction in the
5497 non-macro case, these arguments are sizes from which
5498 MSBD values must be calculated.) */
5499 INSERT_OPERAND (mips_opts
.micromips
,
5500 EXTMSBD
, insn
, va_arg (args
, int));
5504 gas_assert (!mips_opts
.micromips
);
5505 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5509 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, insn
, va_arg (args
, int));
5518 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5522 gas_assert (mips_opts
.micromips
);
5526 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5530 INSERT_OPERAND (mips_opts
.micromips
, CODE
, insn
, va_arg (args
, int));
5534 gas_assert (!mips_opts
.micromips
);
5536 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5540 if (mips_opts
.micromips
)
5541 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5543 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5547 gas_assert (!mips_opts
.micromips
);
5549 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5553 gas_assert (!mips_opts
.micromips
);
5555 int tmp
= va_arg (args
, int);
5557 INSERT_OPERAND (0, RT
, insn
, tmp
);
5558 INSERT_OPERAND (0, RD
, insn
, tmp
);
5564 gas_assert (!mips_opts
.micromips
);
5565 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5572 INSERT_OPERAND (mips_opts
.micromips
,
5573 SHAMT
, insn
, va_arg (args
, int));
5577 gas_assert (!mips_opts
.micromips
);
5578 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5582 gas_assert (!mips_opts
.micromips
);
5583 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5587 gas_assert (!mips_opts
.micromips
);
5588 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5592 gas_assert (!mips_opts
.micromips
);
5593 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5600 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5605 macro_read_relocs (&args
, r
);
5606 gas_assert (*r
== BFD_RELOC_GPREL16
5607 || *r
== BFD_RELOC_MIPS_HIGHER
5608 || *r
== BFD_RELOC_HI16_S
5609 || *r
== BFD_RELOC_LO16
5610 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5614 macro_read_relocs (&args
, r
);
5618 macro_read_relocs (&args
, r
);
5619 gas_assert (ep
!= NULL
5620 && (ep
->X_op
== O_constant
5621 || (ep
->X_op
== O_symbol
5622 && (*r
== BFD_RELOC_MIPS_HIGHEST
5623 || *r
== BFD_RELOC_HI16_S
5624 || *r
== BFD_RELOC_HI16
5625 || *r
== BFD_RELOC_GPREL16
5626 || *r
== BFD_RELOC_MIPS_GOT_HI16
5627 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5631 gas_assert (ep
!= NULL
);
5634 * This allows macro() to pass an immediate expression for
5635 * creating short branches without creating a symbol.
5637 * We don't allow branch relaxation for these branches, as
5638 * they should only appear in ".set nomacro" anyway.
5640 if (ep
->X_op
== O_constant
)
5642 /* For microMIPS we always use relocations for branches.
5643 So we should not resolve immediate values. */
5644 gas_assert (!mips_opts
.micromips
);
5646 if ((ep
->X_add_number
& 3) != 0)
5647 as_bad (_("branch to misaligned address (0x%lx)"),
5648 (unsigned long) ep
->X_add_number
);
5649 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5650 as_bad (_("branch address range overflow (0x%lx)"),
5651 (unsigned long) ep
->X_add_number
);
5652 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5656 *r
= BFD_RELOC_16_PCREL_S2
;
5660 gas_assert (ep
!= NULL
);
5661 *r
= BFD_RELOC_MIPS_JMP
;
5665 gas_assert (!mips_opts
.micromips
);
5666 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, int));
5670 INSERT_OPERAND (mips_opts
.micromips
,
5671 CACHE
, insn
, va_arg (args
, int));
5675 gas_assert (mips_opts
.micromips
);
5676 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5680 gas_assert (mips_opts
.micromips
);
5681 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5685 INSERT_OPERAND (mips_opts
.micromips
,
5686 3BITPOS
, insn
, va_arg (args
, int));
5690 INSERT_OPERAND (mips_opts
.micromips
,
5691 OFFSET12
, insn
, va_arg (args
, int));
5695 gas_assert (mips_opts
.micromips
);
5696 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5699 case 'm': /* Opcode extension character. */
5700 gas_assert (mips_opts
.micromips
);
5704 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5708 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5712 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5726 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5728 append_insn (&insn
, ep
, r
, TRUE
);
5732 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5735 struct mips_opcode
*mo
;
5736 struct mips_cl_insn insn
;
5737 bfd_reloc_code_real_type r
[3]
5738 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5740 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5742 gas_assert (strcmp (name
, mo
->name
) == 0);
5744 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5747 gas_assert (mo
->name
);
5748 gas_assert (strcmp (name
, mo
->name
) == 0);
5751 create_insn (&insn
, mo
);
5769 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5774 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5778 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5782 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5792 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5814 gas_assert (ep
!= NULL
);
5816 if (ep
->X_op
!= O_constant
)
5817 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5818 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5820 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5822 *r
= BFD_RELOC_UNUSED
;
5828 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5835 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5837 append_insn (&insn
, ep
, r
, TRUE
);
5841 * Sign-extend 32-bit mode constants that have bit 31 set and all
5842 * higher bits unset.
5845 normalize_constant_expr (expressionS
*ex
)
5847 if (ex
->X_op
== O_constant
5848 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5849 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5854 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5855 * all higher bits unset.
5858 normalize_address_expr (expressionS
*ex
)
5860 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5861 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5862 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5863 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5868 * Generate a "jalr" instruction with a relocation hint to the called
5869 * function. This occurs in NewABI PIC code.
5872 macro_build_jalr (expressionS
*ep
, int cprestore
)
5874 static const bfd_reloc_code_real_type jalr_relocs
[2]
5875 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5876 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5880 if (MIPS_JALR_HINT_P (ep
))
5885 if (mips_opts
.micromips
)
5887 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
5888 ? "jalr" : "jalrs");
5889 if (MIPS_JALR_HINT_P (ep
)
5891 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5892 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5894 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5897 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5898 if (MIPS_JALR_HINT_P (ep
))
5899 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5903 * Generate a "lui" instruction.
5906 macro_build_lui (expressionS
*ep
, int regnum
)
5908 gas_assert (! mips_opts
.mips16
);
5910 if (ep
->X_op
!= O_constant
)
5912 gas_assert (ep
->X_op
== O_symbol
);
5913 /* _gp_disp is a special case, used from s_cpload.
5914 __gnu_local_gp is used if mips_no_shared. */
5915 gas_assert (mips_pic
== NO_PIC
5917 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5918 || (! mips_in_shared
5919 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5920 "__gnu_local_gp") == 0));
5923 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5926 /* Generate a sequence of instructions to do a load or store from a constant
5927 offset off of a base register (breg) into/from a target register (treg),
5928 using AT if necessary. */
5930 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5931 int treg
, int breg
, int dbl
)
5933 gas_assert (ep
->X_op
== O_constant
);
5935 /* Sign-extending 32-bit constants makes their handling easier. */
5937 normalize_constant_expr (ep
);
5939 /* Right now, this routine can only handle signed 32-bit constants. */
5940 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5941 as_warn (_("operand overflow"));
5943 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5945 /* Signed 16-bit offset will fit in the op. Easy! */
5946 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5950 /* 32-bit offset, need multiple instructions and AT, like:
5951 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5952 addu $tempreg,$tempreg,$breg
5953 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5954 to handle the complete offset. */
5955 macro_build_lui (ep
, AT
);
5956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5957 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5960 as_bad (_("Macro used $at after \".set noat\""));
5965 * Generates code to set the $at register to true (one)
5966 * if reg is less than the immediate expression.
5969 set_at (int reg
, int unsignedp
)
5971 if (imm_expr
.X_op
== O_constant
5972 && imm_expr
.X_add_number
>= -0x8000
5973 && imm_expr
.X_add_number
< 0x8000)
5974 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5975 AT
, reg
, BFD_RELOC_LO16
);
5978 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5979 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5983 /* Warn if an expression is not a constant. */
5986 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5988 if (ex
->X_op
== O_big
)
5989 as_bad (_("unsupported large constant"));
5990 else if (ex
->X_op
!= O_constant
)
5991 as_bad (_("Instruction %s requires absolute expression"),
5994 if (HAVE_32BIT_GPRS
)
5995 normalize_constant_expr (ex
);
5998 /* Count the leading zeroes by performing a binary chop. This is a
5999 bulky bit of source, but performance is a LOT better for the
6000 majority of values than a simple loop to count the bits:
6001 for (lcnt = 0; (lcnt < 32); lcnt++)
6002 if ((v) & (1 << (31 - lcnt)))
6004 However it is not code size friendly, and the gain will drop a bit
6005 on certain cached systems.
6007 #define COUNT_TOP_ZEROES(v) \
6008 (((v) & ~0xffff) == 0 \
6009 ? ((v) & ~0xff) == 0 \
6010 ? ((v) & ~0xf) == 0 \
6011 ? ((v) & ~0x3) == 0 \
6012 ? ((v) & ~0x1) == 0 \
6017 : ((v) & ~0x7) == 0 \
6020 : ((v) & ~0x3f) == 0 \
6021 ? ((v) & ~0x1f) == 0 \
6024 : ((v) & ~0x7f) == 0 \
6027 : ((v) & ~0xfff) == 0 \
6028 ? ((v) & ~0x3ff) == 0 \
6029 ? ((v) & ~0x1ff) == 0 \
6032 : ((v) & ~0x7ff) == 0 \
6035 : ((v) & ~0x3fff) == 0 \
6036 ? ((v) & ~0x1fff) == 0 \
6039 : ((v) & ~0x7fff) == 0 \
6042 : ((v) & ~0xffffff) == 0 \
6043 ? ((v) & ~0xfffff) == 0 \
6044 ? ((v) & ~0x3ffff) == 0 \
6045 ? ((v) & ~0x1ffff) == 0 \
6048 : ((v) & ~0x7ffff) == 0 \
6051 : ((v) & ~0x3fffff) == 0 \
6052 ? ((v) & ~0x1fffff) == 0 \
6055 : ((v) & ~0x7fffff) == 0 \
6058 : ((v) & ~0xfffffff) == 0 \
6059 ? ((v) & ~0x3ffffff) == 0 \
6060 ? ((v) & ~0x1ffffff) == 0 \
6063 : ((v) & ~0x7ffffff) == 0 \
6066 : ((v) & ~0x3fffffff) == 0 \
6067 ? ((v) & ~0x1fffffff) == 0 \
6070 : ((v) & ~0x7fffffff) == 0 \
6075 * This routine generates the least number of instructions necessary to load
6076 * an absolute expression value into a register.
6079 load_register (int reg
, expressionS
*ep
, int dbl
)
6082 expressionS hi32
, lo32
;
6084 if (ep
->X_op
!= O_big
)
6086 gas_assert (ep
->X_op
== O_constant
);
6088 /* Sign-extending 32-bit constants makes their handling easier. */
6090 normalize_constant_expr (ep
);
6092 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
6094 /* We can handle 16 bit signed values with an addiu to
6095 $zero. No need to ever use daddiu here, since $zero and
6096 the result are always correct in 32 bit mode. */
6097 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6100 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
6102 /* We can handle 16 bit unsigned values with an ori to
6104 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6107 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
6109 /* 32 bit values require an lui. */
6110 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6111 if ((ep
->X_add_number
& 0xffff) != 0)
6112 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6117 /* The value is larger than 32 bits. */
6119 if (!dbl
|| HAVE_32BIT_GPRS
)
6123 sprintf_vma (value
, ep
->X_add_number
);
6124 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6125 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6129 if (ep
->X_op
!= O_big
)
6132 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6133 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6134 hi32
.X_add_number
&= 0xffffffff;
6136 lo32
.X_add_number
&= 0xffffffff;
6140 gas_assert (ep
->X_add_number
> 2);
6141 if (ep
->X_add_number
== 3)
6142 generic_bignum
[3] = 0;
6143 else if (ep
->X_add_number
> 4)
6144 as_bad (_("Number larger than 64 bits"));
6145 lo32
.X_op
= O_constant
;
6146 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6147 hi32
.X_op
= O_constant
;
6148 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6151 if (hi32
.X_add_number
== 0)
6156 unsigned long hi
, lo
;
6158 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6160 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6162 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6165 if (lo32
.X_add_number
& 0x80000000)
6167 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6168 if (lo32
.X_add_number
& 0xffff)
6169 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6174 /* Check for 16bit shifted constant. We know that hi32 is
6175 non-zero, so start the mask on the first bit of the hi32
6180 unsigned long himask
, lomask
;
6184 himask
= 0xffff >> (32 - shift
);
6185 lomask
= (0xffff << shift
) & 0xffffffff;
6189 himask
= 0xffff << (shift
- 32);
6192 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6193 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6197 tmp
.X_op
= O_constant
;
6199 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6200 | (lo32
.X_add_number
>> shift
));
6202 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6203 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6204 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6205 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6210 while (shift
<= (64 - 16));
6212 /* Find the bit number of the lowest one bit, and store the
6213 shifted value in hi/lo. */
6214 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6215 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6219 while ((lo
& 1) == 0)
6224 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
6230 while ((hi
& 1) == 0)
6239 /* Optimize if the shifted value is a (power of 2) - 1. */
6240 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
6241 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
6243 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
6248 /* This instruction will set the register to be all
6250 tmp
.X_op
= O_constant
;
6251 tmp
.X_add_number
= (offsetT
) -1;
6252 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6256 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6257 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
6259 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
6260 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6265 /* Sign extend hi32 before calling load_register, because we can
6266 generally get better code when we load a sign extended value. */
6267 if ((hi32
.X_add_number
& 0x80000000) != 0)
6268 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
6269 load_register (reg
, &hi32
, 0);
6272 if ((lo32
.X_add_number
& 0xffff0000) == 0)
6276 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
6284 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
6286 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6287 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
6293 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
6297 mid16
.X_add_number
>>= 16;
6298 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6299 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6302 if ((lo32
.X_add_number
& 0xffff) != 0)
6303 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6307 load_delay_nop (void)
6309 if (!gpr_interlocks
)
6310 macro_build (NULL
, "nop", "");
6313 /* Load an address into a register. */
6316 load_address (int reg
, expressionS
*ep
, int *used_at
)
6318 if (ep
->X_op
!= O_constant
6319 && ep
->X_op
!= O_symbol
)
6321 as_bad (_("expression too complex"));
6322 ep
->X_op
= O_constant
;
6325 if (ep
->X_op
== O_constant
)
6327 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
6331 if (mips_pic
== NO_PIC
)
6333 /* If this is a reference to a GP relative symbol, we want
6334 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6336 lui $reg,<sym> (BFD_RELOC_HI16_S)
6337 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6338 If we have an addend, we always use the latter form.
6340 With 64bit address space and a usable $at we want
6341 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6342 lui $at,<sym> (BFD_RELOC_HI16_S)
6343 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6344 daddiu $at,<sym> (BFD_RELOC_LO16)
6348 If $at is already in use, we use a path which is suboptimal
6349 on superscalar processors.
6350 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6351 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6353 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6355 daddiu $reg,<sym> (BFD_RELOC_LO16)
6357 For GP relative symbols in 64bit address space we can use
6358 the same sequence as in 32bit address space. */
6359 if (HAVE_64BIT_SYMBOLS
)
6361 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6362 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6364 relax_start (ep
->X_add_symbol
);
6365 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6366 mips_gp_register
, BFD_RELOC_GPREL16
);
6370 if (*used_at
== 0 && mips_opts
.at
)
6372 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6373 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
6374 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6375 BFD_RELOC_MIPS_HIGHER
);
6376 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
6377 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
6378 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
6383 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6384 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6385 BFD_RELOC_MIPS_HIGHER
);
6386 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6387 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
6388 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6389 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
6392 if (mips_relax
.sequence
)
6397 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6398 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6400 relax_start (ep
->X_add_symbol
);
6401 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6402 mips_gp_register
, BFD_RELOC_GPREL16
);
6405 macro_build_lui (ep
, reg
);
6406 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
6407 reg
, reg
, BFD_RELOC_LO16
);
6408 if (mips_relax
.sequence
)
6412 else if (!mips_big_got
)
6416 /* If this is a reference to an external symbol, we want
6417 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6419 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6421 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6422 If there is a constant, it must be added in after.
6424 If we have NewABI, we want
6425 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6426 unless we're referencing a global symbol with a non-zero
6427 offset, in which case cst must be added separately. */
6430 if (ep
->X_add_number
)
6432 ex
.X_add_number
= ep
->X_add_number
;
6433 ep
->X_add_number
= 0;
6434 relax_start (ep
->X_add_symbol
);
6435 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6436 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6437 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6439 ex
.X_op
= O_constant
;
6440 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6441 reg
, reg
, BFD_RELOC_LO16
);
6442 ep
->X_add_number
= ex
.X_add_number
;
6445 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6446 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6447 if (mips_relax
.sequence
)
6452 ex
.X_add_number
= ep
->X_add_number
;
6453 ep
->X_add_number
= 0;
6454 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6455 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6457 relax_start (ep
->X_add_symbol
);
6459 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6463 if (ex
.X_add_number
!= 0)
6465 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6466 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6467 ex
.X_op
= O_constant
;
6468 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6469 reg
, reg
, BFD_RELOC_LO16
);
6473 else if (mips_big_got
)
6477 /* This is the large GOT case. If this is a reference to an
6478 external symbol, we want
6479 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6481 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6483 Otherwise, for a reference to a local symbol in old ABI, we want
6484 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6486 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6487 If there is a constant, it must be added in after.
6489 In the NewABI, for local symbols, with or without offsets, we want:
6490 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6491 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6495 ex
.X_add_number
= ep
->X_add_number
;
6496 ep
->X_add_number
= 0;
6497 relax_start (ep
->X_add_symbol
);
6498 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6500 reg
, reg
, mips_gp_register
);
6501 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6502 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6503 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6504 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6505 else if (ex
.X_add_number
)
6507 ex
.X_op
= O_constant
;
6508 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6512 ep
->X_add_number
= ex
.X_add_number
;
6514 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6515 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6516 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6517 BFD_RELOC_MIPS_GOT_OFST
);
6522 ex
.X_add_number
= ep
->X_add_number
;
6523 ep
->X_add_number
= 0;
6524 relax_start (ep
->X_add_symbol
);
6525 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6526 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6527 reg
, reg
, mips_gp_register
);
6528 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6529 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6531 if (reg_needs_delay (mips_gp_register
))
6533 /* We need a nop before loading from $gp. This special
6534 check is required because the lui which starts the main
6535 instruction stream does not refer to $gp, and so will not
6536 insert the nop which may be required. */
6537 macro_build (NULL
, "nop", "");
6539 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6540 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6542 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6546 if (ex
.X_add_number
!= 0)
6548 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6549 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6550 ex
.X_op
= O_constant
;
6551 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6559 if (!mips_opts
.at
&& *used_at
== 1)
6560 as_bad (_("Macro used $at after \".set noat\""));
6563 /* Move the contents of register SOURCE into register DEST. */
6566 move_register (int dest
, int source
)
6568 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6569 instruction specifically requires a 32-bit one. */
6570 if (mips_opts
.micromips
6571 && !mips_opts
.insn32
6572 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6573 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6575 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6579 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6580 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6581 The two alternatives are:
6583 Global symbol Local sybmol
6584 ------------- ------------
6585 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6587 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6589 load_got_offset emits the first instruction and add_got_offset
6590 emits the second for a 16-bit offset or add_got_offset_hilo emits
6591 a sequence to add a 32-bit offset using a scratch register. */
6594 load_got_offset (int dest
, expressionS
*local
)
6599 global
.X_add_number
= 0;
6601 relax_start (local
->X_add_symbol
);
6602 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6603 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6605 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6606 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6611 add_got_offset (int dest
, expressionS
*local
)
6615 global
.X_op
= O_constant
;
6616 global
.X_op_symbol
= NULL
;
6617 global
.X_add_symbol
= NULL
;
6618 global
.X_add_number
= local
->X_add_number
;
6620 relax_start (local
->X_add_symbol
);
6621 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6622 dest
, dest
, BFD_RELOC_LO16
);
6624 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6629 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6632 int hold_mips_optimize
;
6634 global
.X_op
= O_constant
;
6635 global
.X_op_symbol
= NULL
;
6636 global
.X_add_symbol
= NULL
;
6637 global
.X_add_number
= local
->X_add_number
;
6639 relax_start (local
->X_add_symbol
);
6640 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6642 /* Set mips_optimize around the lui instruction to avoid
6643 inserting an unnecessary nop after the lw. */
6644 hold_mips_optimize
= mips_optimize
;
6646 macro_build_lui (&global
, tmp
);
6647 mips_optimize
= hold_mips_optimize
;
6648 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6654 /* Emit a sequence of instructions to emulate a branch likely operation.
6655 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6656 is its complementing branch with the original condition negated.
6657 CALL is set if the original branch specified the link operation.
6658 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6660 Code like this is produced in the noreorder mode:
6665 delay slot (executed only if branch taken)
6673 delay slot (executed only if branch taken)
6676 In the reorder mode the delay slot would be filled with a nop anyway,
6677 so code produced is simply:
6682 This function is used when producing code for the microMIPS ASE that
6683 does not implement branch likely instructions in hardware. */
6686 macro_build_branch_likely (const char *br
, const char *brneg
,
6687 int call
, expressionS
*ep
, const char *fmt
,
6688 unsigned int sreg
, unsigned int treg
)
6690 int noreorder
= mips_opts
.noreorder
;
6693 gas_assert (mips_opts
.micromips
);
6697 micromips_label_expr (&expr1
);
6698 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6699 macro_build (NULL
, "nop", "");
6700 macro_build (ep
, call
? "bal" : "b", "p");
6702 /* Set to true so that append_insn adds a label. */
6703 emit_branch_likely_macro
= TRUE
;
6707 macro_build (ep
, br
, fmt
, sreg
, treg
);
6708 macro_build (NULL
, "nop", "");
6713 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6714 the condition code tested. EP specifies the branch target. */
6717 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6744 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6747 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6748 the register tested. EP specifies the branch target. */
6751 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6753 const char *brneg
= NULL
;
6763 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6767 gas_assert (mips_opts
.micromips
);
6768 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
6776 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6783 br
= mips_opts
.micromips
? "blez" : "blezl";
6790 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6794 gas_assert (mips_opts
.micromips
);
6795 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
6802 if (mips_opts
.micromips
&& brneg
)
6803 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6805 macro_build (ep
, br
, "s,p", sreg
);
6808 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6809 TREG as the registers tested. EP specifies the branch target. */
6812 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6813 unsigned int sreg
, unsigned int treg
)
6815 const char *brneg
= NULL
;
6827 br
= mips_opts
.micromips
? "beq" : "beql";
6836 br
= mips_opts
.micromips
? "bne" : "bnel";
6842 if (mips_opts
.micromips
&& brneg
)
6843 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6845 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6848 /* Return the high part that should be loaded in order to make the low
6849 part of VALUE accessible using an offset of OFFBITS bits. */
6852 offset_high_part (offsetT value
, unsigned int offbits
)
6859 bias
= 1 << (offbits
- 1);
6860 low_mask
= bias
* 2 - 1;
6861 return (value
+ bias
) & ~low_mask
;
6864 /* Return true if the value stored in offset_expr and offset_reloc
6865 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6866 amount that the caller wants to add without inducing overflow
6867 and ALIGN is the known alignment of the value in bytes. */
6870 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
6874 /* Accept any relocation operator if overflow isn't a concern. */
6875 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
6878 /* These relocations are guaranteed not to overflow in correct links. */
6879 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
6880 || gprel16_reloc_p (*offset_reloc
))
6883 if (offset_expr
.X_op
== O_constant
6884 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
6885 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
6892 * This routine implements the seemingly endless macro or synthesized
6893 * instructions and addressing modes in the mips assembly language. Many
6894 * of these macros are simple and are similar to each other. These could
6895 * probably be handled by some kind of table or grammar approach instead of
6896 * this verbose method. Others are not simple macros but are more like
6897 * optimizing code generation.
6898 * One interesting optimization is when several store macros appear
6899 * consecutively that would load AT with the upper half of the same address.
6900 * The ensuing load upper instructions are ommited. This implies some kind
6901 * of global optimization. We currently only optimize within a single macro.
6902 * For many of the load and store macros if the address is specified as a
6903 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6904 * first load register 'at' with zero and use it as the base register. The
6905 * mips assembler simply uses register $zero. Just one tiny optimization
6909 macro (struct mips_cl_insn
*ip
, char *str
)
6911 unsigned int treg
, sreg
, dreg
, breg
;
6912 unsigned int tempreg
;
6915 expressionS label_expr
;
6930 bfd_boolean large_offset
;
6932 int hold_mips_optimize
;
6935 gas_assert (! mips_opts
.mips16
);
6937 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6938 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6939 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6940 mask
= ip
->insn_mo
->mask
;
6942 label_expr
.X_op
= O_constant
;
6943 label_expr
.X_op_symbol
= NULL
;
6944 label_expr
.X_add_symbol
= NULL
;
6945 label_expr
.X_add_number
= 0;
6947 expr1
.X_op
= O_constant
;
6948 expr1
.X_op_symbol
= NULL
;
6949 expr1
.X_add_symbol
= NULL
;
6950 expr1
.X_add_number
= 1;
6966 if (mips_opts
.micromips
)
6967 micromips_label_expr (&label_expr
);
6969 label_expr
.X_add_number
= 8;
6970 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6972 macro_build (NULL
, "nop", "");
6974 move_register (dreg
, sreg
);
6975 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6976 if (mips_opts
.micromips
)
6977 micromips_add_label ();
6994 if (!mips_opts
.micromips
)
6996 if (imm_expr
.X_op
== O_constant
6997 && imm_expr
.X_add_number
>= -0x200
6998 && imm_expr
.X_add_number
< 0x200)
7000 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
7009 if (imm_expr
.X_op
== O_constant
7010 && imm_expr
.X_add_number
>= -0x8000
7011 && imm_expr
.X_add_number
< 0x8000)
7013 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7018 load_register (AT
, &imm_expr
, dbl
);
7019 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7038 if (imm_expr
.X_op
== O_constant
7039 && imm_expr
.X_add_number
>= 0
7040 && imm_expr
.X_add_number
< 0x10000)
7042 if (mask
!= M_NOR_I
)
7043 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
7046 macro_build (&imm_expr
, "ori", "t,r,i",
7047 treg
, sreg
, BFD_RELOC_LO16
);
7048 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
7054 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7055 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7059 switch (imm_expr
.X_add_number
)
7062 macro_build (NULL
, "nop", "");
7065 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
7069 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
7070 (int) imm_expr
.X_add_number
);
7073 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
7074 (unsigned long) imm_expr
.X_add_number
);
7083 gas_assert (mips_opts
.micromips
);
7084 macro_build_branch_ccl (mask
, &offset_expr
,
7085 EXTRACT_OPERAND (1, BCC
, *ip
));
7092 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7098 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
7103 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
7110 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
7112 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
7116 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7117 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7118 &offset_expr
, AT
, ZERO
);
7128 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
7134 /* Check for > max integer. */
7135 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7138 /* Result is always false. */
7140 macro_build (NULL
, "nop", "");
7142 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
7145 if (imm_expr
.X_op
!= O_constant
)
7146 as_bad (_("Unsupported large constant"));
7147 ++imm_expr
.X_add_number
;
7151 if (mask
== M_BGEL_I
)
7153 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7155 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7156 &offset_expr
, sreg
);
7159 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7161 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7162 &offset_expr
, sreg
);
7165 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
7168 /* result is always true */
7169 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7170 macro_build (&offset_expr
, "b", "p");
7175 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7176 &offset_expr
, AT
, ZERO
);
7185 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7186 &offset_expr
, ZERO
, treg
);
7190 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7191 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7192 &offset_expr
, AT
, ZERO
);
7201 && imm_expr
.X_op
== O_constant
7202 && imm_expr
.X_add_number
== -1))
7204 if (imm_expr
.X_op
!= O_constant
)
7205 as_bad (_("Unsupported large constant"));
7206 ++imm_expr
.X_add_number
;
7210 if (mask
== M_BGEUL_I
)
7212 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7214 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7215 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7216 &offset_expr
, sreg
, ZERO
);
7221 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7222 &offset_expr
, AT
, ZERO
);
7230 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
7232 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
7236 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7237 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7238 &offset_expr
, AT
, ZERO
);
7246 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7247 &offset_expr
, sreg
, ZERO
);
7253 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7254 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7255 &offset_expr
, AT
, ZERO
);
7263 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7265 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
7269 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7270 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7271 &offset_expr
, AT
, ZERO
);
7278 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7280 if (imm_expr
.X_op
!= O_constant
)
7281 as_bad (_("Unsupported large constant"));
7282 ++imm_expr
.X_add_number
;
7286 if (mask
== M_BLTL_I
)
7288 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7289 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7290 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7291 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7296 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7297 &offset_expr
, AT
, ZERO
);
7305 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7306 &offset_expr
, sreg
, ZERO
);
7312 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7313 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7314 &offset_expr
, AT
, ZERO
);
7323 && imm_expr
.X_op
== O_constant
7324 && imm_expr
.X_add_number
== -1))
7326 if (imm_expr
.X_op
!= O_constant
)
7327 as_bad (_("Unsupported large constant"));
7328 ++imm_expr
.X_add_number
;
7332 if (mask
== M_BLTUL_I
)
7334 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7336 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7337 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7338 &offset_expr
, sreg
, ZERO
);
7343 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7344 &offset_expr
, AT
, ZERO
);
7352 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7354 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
7358 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7359 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7360 &offset_expr
, AT
, ZERO
);
7370 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7371 &offset_expr
, ZERO
, treg
);
7375 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7376 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7377 &offset_expr
, AT
, ZERO
);
7383 /* Use unsigned arithmetic. */
7387 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7389 as_bad (_("Unsupported large constant"));
7394 pos
= imm_expr
.X_add_number
;
7395 size
= imm2_expr
.X_add_number
;
7400 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7403 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7405 as_bad (_("Improper extract size (%lu, position %lu)"),
7406 (unsigned long) size
, (unsigned long) pos
);
7410 if (size
<= 32 && pos
< 32)
7415 else if (size
<= 32)
7425 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7432 /* Use unsigned arithmetic. */
7436 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7438 as_bad (_("Unsupported large constant"));
7443 pos
= imm_expr
.X_add_number
;
7444 size
= imm2_expr
.X_add_number
;
7449 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7452 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7454 as_bad (_("Improper insert size (%lu, position %lu)"),
7455 (unsigned long) size
, (unsigned long) pos
);
7459 if (pos
< 32 && (pos
+ size
- 1) < 32)
7474 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7475 (int) (pos
+ size
- 1));
7491 as_warn (_("Divide by zero."));
7493 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7495 macro_build (NULL
, "break", BRK_FMT
, 7);
7502 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7503 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7507 if (mips_opts
.micromips
)
7508 micromips_label_expr (&label_expr
);
7510 label_expr
.X_add_number
= 8;
7511 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7512 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7513 macro_build (NULL
, "break", BRK_FMT
, 7);
7514 if (mips_opts
.micromips
)
7515 micromips_add_label ();
7517 expr1
.X_add_number
= -1;
7519 load_register (AT
, &expr1
, dbl
);
7520 if (mips_opts
.micromips
)
7521 micromips_label_expr (&label_expr
);
7523 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7524 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7527 expr1
.X_add_number
= 1;
7528 load_register (AT
, &expr1
, dbl
);
7529 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7533 expr1
.X_add_number
= 0x80000000;
7534 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7538 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7539 /* We want to close the noreorder block as soon as possible, so
7540 that later insns are available for delay slot filling. */
7545 if (mips_opts
.micromips
)
7546 micromips_label_expr (&label_expr
);
7548 label_expr
.X_add_number
= 8;
7549 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7550 macro_build (NULL
, "nop", "");
7552 /* We want to close the noreorder block as soon as possible, so
7553 that later insns are available for delay slot filling. */
7556 macro_build (NULL
, "break", BRK_FMT
, 6);
7558 if (mips_opts
.micromips
)
7559 micromips_add_label ();
7560 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7599 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7601 as_warn (_("Divide by zero."));
7603 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7605 macro_build (NULL
, "break", BRK_FMT
, 7);
7608 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7610 if (strcmp (s2
, "mflo") == 0)
7611 move_register (dreg
, sreg
);
7613 move_register (dreg
, ZERO
);
7616 if (imm_expr
.X_op
== O_constant
7617 && imm_expr
.X_add_number
== -1
7618 && s
[strlen (s
) - 1] != 'u')
7620 if (strcmp (s2
, "mflo") == 0)
7622 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7625 move_register (dreg
, ZERO
);
7630 load_register (AT
, &imm_expr
, dbl
);
7631 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7632 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7654 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7655 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7656 /* We want to close the noreorder block as soon as possible, so
7657 that later insns are available for delay slot filling. */
7662 if (mips_opts
.micromips
)
7663 micromips_label_expr (&label_expr
);
7665 label_expr
.X_add_number
= 8;
7666 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7667 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7669 /* We want to close the noreorder block as soon as possible, so
7670 that later insns are available for delay slot filling. */
7672 macro_build (NULL
, "break", BRK_FMT
, 7);
7673 if (mips_opts
.micromips
)
7674 micromips_add_label ();
7676 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7688 /* Load the address of a symbol into a register. If breg is not
7689 zero, we then add a base register to it. */
7691 if (dbl
&& HAVE_32BIT_GPRS
)
7692 as_warn (_("dla used to load 32-bit register"));
7694 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7695 as_warn (_("la used to load 64-bit address"));
7697 if (small_offset_p (0, align
, 16))
7699 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", treg
, breg
,
7700 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
7704 if (mips_opts
.at
&& (treg
== breg
))
7714 if (offset_expr
.X_op
!= O_symbol
7715 && offset_expr
.X_op
!= O_constant
)
7717 as_bad (_("Expression too complex"));
7718 offset_expr
.X_op
= O_constant
;
7721 if (offset_expr
.X_op
== O_constant
)
7722 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7723 else if (mips_pic
== NO_PIC
)
7725 /* If this is a reference to a GP relative symbol, we want
7726 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7728 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7729 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7730 If we have a constant, we need two instructions anyhow,
7731 so we may as well always use the latter form.
7733 With 64bit address space and a usable $at we want
7734 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7735 lui $at,<sym> (BFD_RELOC_HI16_S)
7736 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7737 daddiu $at,<sym> (BFD_RELOC_LO16)
7739 daddu $tempreg,$tempreg,$at
7741 If $at is already in use, we use a path which is suboptimal
7742 on superscalar processors.
7743 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7744 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7746 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7748 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7750 For GP relative symbols in 64bit address space we can use
7751 the same sequence as in 32bit address space. */
7752 if (HAVE_64BIT_SYMBOLS
)
7754 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7755 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7757 relax_start (offset_expr
.X_add_symbol
);
7758 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7759 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7763 if (used_at
== 0 && mips_opts
.at
)
7765 macro_build (&offset_expr
, "lui", LUI_FMT
,
7766 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7767 macro_build (&offset_expr
, "lui", LUI_FMT
,
7768 AT
, BFD_RELOC_HI16_S
);
7769 macro_build (&offset_expr
, "daddiu", "t,r,j",
7770 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7771 macro_build (&offset_expr
, "daddiu", "t,r,j",
7772 AT
, AT
, BFD_RELOC_LO16
);
7773 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7774 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7779 macro_build (&offset_expr
, "lui", LUI_FMT
,
7780 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7781 macro_build (&offset_expr
, "daddiu", "t,r,j",
7782 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7783 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7784 macro_build (&offset_expr
, "daddiu", "t,r,j",
7785 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7786 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7787 macro_build (&offset_expr
, "daddiu", "t,r,j",
7788 tempreg
, tempreg
, BFD_RELOC_LO16
);
7791 if (mips_relax
.sequence
)
7796 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7797 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7799 relax_start (offset_expr
.X_add_symbol
);
7800 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7801 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7804 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7805 as_bad (_("Offset too large"));
7806 macro_build_lui (&offset_expr
, tempreg
);
7807 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7808 tempreg
, tempreg
, BFD_RELOC_LO16
);
7809 if (mips_relax
.sequence
)
7813 else if (!mips_big_got
&& !HAVE_NEWABI
)
7815 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7817 /* If this is a reference to an external symbol, and there
7818 is no constant, we want
7819 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7820 or for lca or if tempreg is PIC_CALL_REG
7821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7822 For a local symbol, we want
7823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7825 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7827 If we have a small constant, and this is a reference to
7828 an external symbol, we want
7829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7831 addiu $tempreg,$tempreg,<constant>
7832 For a local symbol, we want the same instruction
7833 sequence, but we output a BFD_RELOC_LO16 reloc on the
7836 If we have a large constant, and this is a reference to
7837 an external symbol, we want
7838 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7839 lui $at,<hiconstant>
7840 addiu $at,$at,<loconstant>
7841 addu $tempreg,$tempreg,$at
7842 For a local symbol, we want the same instruction
7843 sequence, but we output a BFD_RELOC_LO16 reloc on the
7847 if (offset_expr
.X_add_number
== 0)
7849 if (mips_pic
== SVR4_PIC
7851 && (call
|| tempreg
== PIC_CALL_REG
))
7852 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7854 relax_start (offset_expr
.X_add_symbol
);
7855 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7856 lw_reloc_type
, mips_gp_register
);
7859 /* We're going to put in an addu instruction using
7860 tempreg, so we may as well insert the nop right
7865 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7866 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7868 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7869 tempreg
, tempreg
, BFD_RELOC_LO16
);
7871 /* FIXME: If breg == 0, and the next instruction uses
7872 $tempreg, then if this variant case is used an extra
7873 nop will be generated. */
7875 else if (offset_expr
.X_add_number
>= -0x8000
7876 && offset_expr
.X_add_number
< 0x8000)
7878 load_got_offset (tempreg
, &offset_expr
);
7880 add_got_offset (tempreg
, &offset_expr
);
7884 expr1
.X_add_number
= offset_expr
.X_add_number
;
7885 offset_expr
.X_add_number
=
7886 SEXT_16BIT (offset_expr
.X_add_number
);
7887 load_got_offset (tempreg
, &offset_expr
);
7888 offset_expr
.X_add_number
= expr1
.X_add_number
;
7889 /* If we are going to add in a base register, and the
7890 target register and the base register are the same,
7891 then we are using AT as a temporary register. Since
7892 we want to load the constant into AT, we add our
7893 current AT (from the global offset table) and the
7894 register into the register now, and pretend we were
7895 not using a base register. */
7899 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7904 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7908 else if (!mips_big_got
&& HAVE_NEWABI
)
7910 int add_breg_early
= 0;
7912 /* If this is a reference to an external, and there is no
7913 constant, or local symbol (*), with or without a
7915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7916 or for lca or if tempreg is PIC_CALL_REG
7917 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7919 If we have a small constant, and this is a reference to
7920 an external symbol, we want
7921 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7922 addiu $tempreg,$tempreg,<constant>
7924 If we have a large constant, and this is a reference to
7925 an external symbol, we want
7926 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7927 lui $at,<hiconstant>
7928 addiu $at,$at,<loconstant>
7929 addu $tempreg,$tempreg,$at
7931 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7932 local symbols, even though it introduces an additional
7935 if (offset_expr
.X_add_number
)
7937 expr1
.X_add_number
= offset_expr
.X_add_number
;
7938 offset_expr
.X_add_number
= 0;
7940 relax_start (offset_expr
.X_add_symbol
);
7941 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7942 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7944 if (expr1
.X_add_number
>= -0x8000
7945 && expr1
.X_add_number
< 0x8000)
7947 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7948 tempreg
, tempreg
, BFD_RELOC_LO16
);
7950 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7952 /* If we are going to add in a base register, and the
7953 target register and the base register are the same,
7954 then we are using AT as a temporary register. Since
7955 we want to load the constant into AT, we add our
7956 current AT (from the global offset table) and the
7957 register into the register now, and pretend we were
7958 not using a base register. */
7963 gas_assert (tempreg
== AT
);
7964 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7970 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7977 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7980 offset_expr
.X_add_number
= expr1
.X_add_number
;
7982 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7983 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7986 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7987 treg
, tempreg
, breg
);
7993 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7995 relax_start (offset_expr
.X_add_symbol
);
7996 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7997 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7999 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8000 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8005 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8006 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8009 else if (mips_big_got
&& !HAVE_NEWABI
)
8012 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8013 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8014 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8016 /* This is the large GOT case. If this is a reference to an
8017 external symbol, and there is no constant, we want
8018 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8019 addu $tempreg,$tempreg,$gp
8020 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8021 or for lca or if tempreg is PIC_CALL_REG
8022 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8023 addu $tempreg,$tempreg,$gp
8024 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8025 For a local symbol, we want
8026 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8028 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8030 If we have a small constant, and this is a reference to
8031 an external symbol, we want
8032 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8033 addu $tempreg,$tempreg,$gp
8034 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8036 addiu $tempreg,$tempreg,<constant>
8037 For a local symbol, we want
8038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8040 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
8042 If we have a large constant, and this is a reference to
8043 an external symbol, we want
8044 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8045 addu $tempreg,$tempreg,$gp
8046 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8047 lui $at,<hiconstant>
8048 addiu $at,$at,<loconstant>
8049 addu $tempreg,$tempreg,$at
8050 For a local symbol, we want
8051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8052 lui $at,<hiconstant>
8053 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
8054 addu $tempreg,$tempreg,$at
8057 expr1
.X_add_number
= offset_expr
.X_add_number
;
8058 offset_expr
.X_add_number
= 0;
8059 relax_start (offset_expr
.X_add_symbol
);
8060 gpdelay
= reg_needs_delay (mips_gp_register
);
8061 if (expr1
.X_add_number
== 0 && breg
== 0
8062 && (call
|| tempreg
== PIC_CALL_REG
))
8064 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8065 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8067 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8069 tempreg
, tempreg
, mips_gp_register
);
8070 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8071 tempreg
, lw_reloc_type
, tempreg
);
8072 if (expr1
.X_add_number
== 0)
8076 /* We're going to put in an addu instruction using
8077 tempreg, so we may as well insert the nop right
8082 else if (expr1
.X_add_number
>= -0x8000
8083 && expr1
.X_add_number
< 0x8000)
8086 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8087 tempreg
, tempreg
, BFD_RELOC_LO16
);
8091 /* If we are going to add in a base register, and the
8092 target register and the base register are the same,
8093 then we are using AT as a temporary register. Since
8094 we want to load the constant into AT, we add our
8095 current AT (from the global offset table) and the
8096 register into the register now, and pretend we were
8097 not using a base register. */
8102 gas_assert (tempreg
== AT
);
8104 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8109 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8114 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
8119 /* This is needed because this instruction uses $gp, but
8120 the first instruction on the main stream does not. */
8121 macro_build (NULL
, "nop", "");
8124 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8125 local_reloc_type
, mips_gp_register
);
8126 if (expr1
.X_add_number
>= -0x8000
8127 && expr1
.X_add_number
< 0x8000)
8130 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8131 tempreg
, tempreg
, BFD_RELOC_LO16
);
8132 /* FIXME: If add_number is 0, and there was no base
8133 register, the external symbol case ended with a load,
8134 so if the symbol turns out to not be external, and
8135 the next instruction uses tempreg, an unnecessary nop
8136 will be inserted. */
8142 /* We must add in the base register now, as in the
8143 external symbol case. */
8144 gas_assert (tempreg
== AT
);
8146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8149 /* We set breg to 0 because we have arranged to add
8150 it in in both cases. */
8154 macro_build_lui (&expr1
, AT
);
8155 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8156 AT
, AT
, BFD_RELOC_LO16
);
8157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8158 tempreg
, tempreg
, AT
);
8163 else if (mips_big_got
&& HAVE_NEWABI
)
8165 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8166 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8167 int add_breg_early
= 0;
8169 /* This is the large GOT case. If this is a reference to an
8170 external symbol, and there is no constant, we want
8171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8172 add $tempreg,$tempreg,$gp
8173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8174 or for lca or if tempreg is PIC_CALL_REG
8175 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8176 add $tempreg,$tempreg,$gp
8177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8179 If we have a small constant, and this is a reference to
8180 an external symbol, we want
8181 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8182 add $tempreg,$tempreg,$gp
8183 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8184 addi $tempreg,$tempreg,<constant>
8186 If we have a large constant, and this is a reference to
8187 an external symbol, we want
8188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8189 addu $tempreg,$tempreg,$gp
8190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8191 lui $at,<hiconstant>
8192 addi $at,$at,<loconstant>
8193 add $tempreg,$tempreg,$at
8195 If we have NewABI, and we know it's a local symbol, we want
8196 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8197 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8198 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8200 relax_start (offset_expr
.X_add_symbol
);
8202 expr1
.X_add_number
= offset_expr
.X_add_number
;
8203 offset_expr
.X_add_number
= 0;
8205 if (expr1
.X_add_number
== 0 && breg
== 0
8206 && (call
|| tempreg
== PIC_CALL_REG
))
8208 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8209 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8211 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8212 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8213 tempreg
, tempreg
, mips_gp_register
);
8214 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8215 tempreg
, lw_reloc_type
, tempreg
);
8217 if (expr1
.X_add_number
== 0)
8219 else if (expr1
.X_add_number
>= -0x8000
8220 && expr1
.X_add_number
< 0x8000)
8222 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8223 tempreg
, tempreg
, BFD_RELOC_LO16
);
8225 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8227 /* If we are going to add in a base register, and the
8228 target register and the base register are the same,
8229 then we are using AT as a temporary register. Since
8230 we want to load the constant into AT, we add our
8231 current AT (from the global offset table) and the
8232 register into the register now, and pretend we were
8233 not using a base register. */
8238 gas_assert (tempreg
== AT
);
8239 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8245 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8251 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8254 offset_expr
.X_add_number
= expr1
.X_add_number
;
8255 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8256 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8257 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8258 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
8261 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8262 treg
, tempreg
, breg
);
8272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
8276 gas_assert (!mips_opts
.micromips
);
8277 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x01);
8281 gas_assert (!mips_opts
.micromips
);
8282 macro_build (NULL
, "c2", "C", 0x02);
8286 gas_assert (!mips_opts
.micromips
);
8287 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x02);
8291 gas_assert (!mips_opts
.micromips
);
8292 macro_build (NULL
, "c2", "C", 3);
8296 gas_assert (!mips_opts
.micromips
);
8297 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x03);
8301 /* The j instruction may not be used in PIC code, since it
8302 requires an absolute address. We convert it to a b
8304 if (mips_pic
== NO_PIC
)
8305 macro_build (&offset_expr
, "j", "a");
8307 macro_build (&offset_expr
, "b", "p");
8310 /* The jal instructions must be handled as macros because when
8311 generating PIC code they expand to multi-instruction
8312 sequences. Normally they are simple instructions. */
8317 gas_assert (mips_opts
.micromips
);
8318 if (mips_opts
.insn32
)
8320 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8330 if (mips_pic
== NO_PIC
)
8332 s
= jals
? "jalrs" : "jalr";
8333 if (mips_opts
.micromips
8334 && !mips_opts
.insn32
8336 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8337 macro_build (NULL
, s
, "mj", sreg
);
8339 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8343 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
8344 && mips_cprestore_offset
>= 0);
8346 if (sreg
!= PIC_CALL_REG
)
8347 as_warn (_("MIPS PIC call to register other than $25"));
8349 s
= ((mips_opts
.micromips
8350 && !mips_opts
.insn32
8351 && (!mips_opts
.noreorder
|| cprestore
))
8352 ? "jalrs" : "jalr");
8353 if (mips_opts
.micromips
8354 && !mips_opts
.insn32
8356 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8357 macro_build (NULL
, s
, "mj", sreg
);
8359 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8360 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
8362 if (mips_cprestore_offset
< 0)
8363 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8366 if (!mips_frame_reg_valid
)
8368 as_warn (_("No .frame pseudo-op used in PIC code"));
8369 /* Quiet this warning. */
8370 mips_frame_reg_valid
= 1;
8372 if (!mips_cprestore_valid
)
8374 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8375 /* Quiet this warning. */
8376 mips_cprestore_valid
= 1;
8378 if (mips_opts
.noreorder
)
8379 macro_build (NULL
, "nop", "");
8380 expr1
.X_add_number
= mips_cprestore_offset
;
8381 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8384 HAVE_64BIT_ADDRESSES
);
8392 gas_assert (mips_opts
.micromips
);
8393 if (mips_opts
.insn32
)
8395 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8401 if (mips_pic
== NO_PIC
)
8402 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
8403 else if (mips_pic
== SVR4_PIC
)
8405 /* If this is a reference to an external symbol, and we are
8406 using a small GOT, we want
8407 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8411 lw $gp,cprestore($sp)
8412 The cprestore value is set using the .cprestore
8413 pseudo-op. If we are using a big GOT, we want
8414 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8416 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8420 lw $gp,cprestore($sp)
8421 If the symbol is not external, we want
8422 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8424 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8427 lw $gp,cprestore($sp)
8429 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8430 sequences above, minus nops, unless the symbol is local,
8431 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8437 relax_start (offset_expr
.X_add_symbol
);
8438 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8439 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8442 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8443 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8449 relax_start (offset_expr
.X_add_symbol
);
8450 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8451 BFD_RELOC_MIPS_CALL_HI16
);
8452 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8453 PIC_CALL_REG
, mips_gp_register
);
8454 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8455 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8458 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8459 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8461 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8462 PIC_CALL_REG
, PIC_CALL_REG
,
8463 BFD_RELOC_MIPS_GOT_OFST
);
8467 macro_build_jalr (&offset_expr
, 0);
8471 relax_start (offset_expr
.X_add_symbol
);
8474 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8475 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8484 gpdelay
= reg_needs_delay (mips_gp_register
);
8485 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8486 BFD_RELOC_MIPS_CALL_HI16
);
8487 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8488 PIC_CALL_REG
, mips_gp_register
);
8489 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8490 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8495 macro_build (NULL
, "nop", "");
8497 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8498 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8501 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8502 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8504 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8506 if (mips_cprestore_offset
< 0)
8507 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8510 if (!mips_frame_reg_valid
)
8512 as_warn (_("No .frame pseudo-op used in PIC code"));
8513 /* Quiet this warning. */
8514 mips_frame_reg_valid
= 1;
8516 if (!mips_cprestore_valid
)
8518 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8519 /* Quiet this warning. */
8520 mips_cprestore_valid
= 1;
8522 if (mips_opts
.noreorder
)
8523 macro_build (NULL
, "nop", "");
8524 expr1
.X_add_number
= mips_cprestore_offset
;
8525 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8528 HAVE_64BIT_ADDRESSES
);
8532 else if (mips_pic
== VXWORKS_PIC
)
8533 as_bad (_("Non-PIC jump used in PIC library"));
8611 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8617 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8642 gas_assert (!mips_opts
.micromips
);
8645 /* Itbl support may require additional care here. */
8651 /* Itbl support may require additional care here. */
8657 offbits
= (mips_opts
.micromips
? 12 : 16);
8658 /* Itbl support may require additional care here. */
8662 gas_assert (!mips_opts
.micromips
);
8665 /* Itbl support may require additional care here. */
8671 offbits
= (mips_opts
.micromips
? 12 : 16);
8676 offbits
= (mips_opts
.micromips
? 12 : 16);
8681 /* Itbl support may require additional care here. */
8687 offbits
= (mips_opts
.micromips
? 12 : 16);
8688 /* Itbl support may require additional care here. */
8694 /* Itbl support may require additional care here. */
8700 /* Itbl support may require additional care here. */
8706 offbits
= (mips_opts
.micromips
? 12 : 16);
8711 offbits
= (mips_opts
.micromips
? 12 : 16);
8716 offbits
= (mips_opts
.micromips
? 12 : 16);
8721 offbits
= (mips_opts
.micromips
? 12 : 16);
8726 offbits
= (mips_opts
.micromips
? 12 : 16);
8729 gas_assert (mips_opts
.micromips
);
8736 gas_assert (mips_opts
.micromips
);
8743 gas_assert (mips_opts
.micromips
);
8749 gas_assert (mips_opts
.micromips
);
8756 /* We don't want to use $0 as tempreg. */
8757 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
8760 tempreg
= treg
+ lp
;
8776 gas_assert (!mips_opts
.micromips
);
8779 /* Itbl support may require additional care here. */
8785 /* Itbl support may require additional care here. */
8791 offbits
= (mips_opts
.micromips
? 12 : 16);
8792 /* Itbl support may require additional care here. */
8796 gas_assert (!mips_opts
.micromips
);
8799 /* Itbl support may require additional care here. */
8805 offbits
= (mips_opts
.micromips
? 12 : 16);
8810 offbits
= (mips_opts
.micromips
? 12 : 16);
8815 offbits
= (mips_opts
.micromips
? 12 : 16);
8820 offbits
= (mips_opts
.micromips
? 12 : 16);
8824 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8825 offbits
= (mips_opts
.micromips
? 12 : 16);
8834 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8835 offbits
= (mips_opts
.micromips
? 12 : 16);
8846 /* Itbl support may require additional care here. */
8851 offbits
= (mips_opts
.micromips
? 12 : 16);
8852 /* Itbl support may require additional care here. */
8858 /* Itbl support may require additional care here. */
8862 gas_assert (!mips_opts
.micromips
);
8865 /* Itbl support may require additional care here. */
8871 offbits
= (mips_opts
.micromips
? 12 : 16);
8876 offbits
= (mips_opts
.micromips
? 12 : 16);
8879 gas_assert (mips_opts
.micromips
);
8885 gas_assert (mips_opts
.micromips
);
8891 gas_assert (mips_opts
.micromips
);
8897 gas_assert (mips_opts
.micromips
);
8905 if (small_offset_p (0, align
, 16))
8907 /* The first case exists for M_LD_AB and M_SD_AB, which are
8908 macros for o32 but which should act like normal instructions
8911 macro_build (&offset_expr
, s
, fmt
, treg
, -1, offset_reloc
[0],
8912 offset_reloc
[1], offset_reloc
[2], breg
);
8913 else if (small_offset_p (0, align
, offbits
))
8916 macro_build (NULL
, s
, fmt
, treg
, breg
);
8918 macro_build (NULL
, s
, fmt
, treg
,
8919 (int) offset_expr
.X_add_number
, breg
);
8925 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8926 tempreg
, breg
, -1, offset_reloc
[0],
8927 offset_reloc
[1], offset_reloc
[2]);
8929 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8931 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
8939 if (offset_expr
.X_op
!= O_constant
8940 && offset_expr
.X_op
!= O_symbol
)
8942 as_bad (_("Expression too complex"));
8943 offset_expr
.X_op
= O_constant
;
8946 if (HAVE_32BIT_ADDRESSES
8947 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8951 sprintf_vma (value
, offset_expr
.X_add_number
);
8952 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8955 /* A constant expression in PIC code can be handled just as it
8956 is in non PIC code. */
8957 if (offset_expr
.X_op
== O_constant
)
8959 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
8960 offbits
== 0 ? 16 : offbits
);
8961 offset_expr
.X_add_number
-= expr1
.X_add_number
;
8963 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8966 tempreg
, tempreg
, breg
);
8969 if (offset_expr
.X_add_number
!= 0)
8970 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8971 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
8972 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8974 else if (offbits
== 16)
8975 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8977 macro_build (NULL
, s
, fmt
, treg
,
8978 (int) offset_expr
.X_add_number
, tempreg
);
8980 else if (offbits
!= 16)
8982 /* The offset field is too narrow to be used for a low-part
8983 relocation, so load the whole address into the auxillary
8985 load_address (tempreg
, &offset_expr
, &used_at
);
8987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8988 tempreg
, tempreg
, breg
);
8990 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8992 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
8994 else if (mips_pic
== NO_PIC
)
8996 /* If this is a reference to a GP relative symbol, and there
8997 is no base register, we want
8998 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8999 Otherwise, if there is no base register, we want
9000 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9001 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9002 If we have a constant, we need two instructions anyhow,
9003 so we always use the latter form.
9005 If we have a base register, and this is a reference to a
9006 GP relative symbol, we want
9007 addu $tempreg,$breg,$gp
9008 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
9010 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9011 addu $tempreg,$tempreg,$breg
9012 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9013 With a constant we always use the latter case.
9015 With 64bit address space and no base register and $at usable,
9017 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9018 lui $at,<sym> (BFD_RELOC_HI16_S)
9019 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9022 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9023 If we have a base register, we want
9024 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9025 lui $at,<sym> (BFD_RELOC_HI16_S)
9026 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9030 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9032 Without $at we can't generate the optimal path for superscalar
9033 processors here since this would require two temporary registers.
9034 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9035 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9037 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9039 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9040 If we have a base register, we want
9041 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9042 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9044 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9046 daddu $tempreg,$tempreg,$breg
9047 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9049 For GP relative symbols in 64bit address space we can use
9050 the same sequence as in 32bit address space. */
9051 if (HAVE_64BIT_SYMBOLS
)
9053 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9054 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9056 relax_start (offset_expr
.X_add_symbol
);
9059 macro_build (&offset_expr
, s
, fmt
, treg
,
9060 BFD_RELOC_GPREL16
, mips_gp_register
);
9064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9065 tempreg
, breg
, mips_gp_register
);
9066 macro_build (&offset_expr
, s
, fmt
, treg
,
9067 BFD_RELOC_GPREL16
, tempreg
);
9072 if (used_at
== 0 && mips_opts
.at
)
9074 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9075 BFD_RELOC_MIPS_HIGHEST
);
9076 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9078 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9079 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9081 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9082 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9083 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9084 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9090 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9091 BFD_RELOC_MIPS_HIGHEST
);
9092 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9093 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9094 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9095 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9096 tempreg
, BFD_RELOC_HI16_S
);
9097 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9099 macro_build (NULL
, "daddu", "d,v,t",
9100 tempreg
, tempreg
, breg
);
9101 macro_build (&offset_expr
, s
, fmt
, treg
,
9102 BFD_RELOC_LO16
, tempreg
);
9105 if (mips_relax
.sequence
)
9112 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9113 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9115 relax_start (offset_expr
.X_add_symbol
);
9116 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9120 macro_build_lui (&offset_expr
, tempreg
);
9121 macro_build (&offset_expr
, s
, fmt
, treg
,
9122 BFD_RELOC_LO16
, tempreg
);
9123 if (mips_relax
.sequence
)
9128 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9129 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9131 relax_start (offset_expr
.X_add_symbol
);
9132 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9133 tempreg
, breg
, mips_gp_register
);
9134 macro_build (&offset_expr
, s
, fmt
, treg
,
9135 BFD_RELOC_GPREL16
, tempreg
);
9138 macro_build_lui (&offset_expr
, tempreg
);
9139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9140 tempreg
, tempreg
, breg
);
9141 macro_build (&offset_expr
, s
, fmt
, treg
,
9142 BFD_RELOC_LO16
, tempreg
);
9143 if (mips_relax
.sequence
)
9147 else if (!mips_big_got
)
9149 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9151 /* If this is a reference to an external symbol, we want
9152 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9154 <op> $treg,0($tempreg)
9156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9158 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9159 <op> $treg,0($tempreg)
9162 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9163 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9165 If there is a base register, we add it to $tempreg before
9166 the <op>. If there is a constant, we stick it in the
9167 <op> instruction. We don't handle constants larger than
9168 16 bits, because we have no way to load the upper 16 bits
9169 (actually, we could handle them for the subset of cases
9170 in which we are not using $at). */
9171 gas_assert (offset_expr
.X_op
== O_symbol
);
9174 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9175 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9177 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9178 tempreg
, tempreg
, breg
);
9179 macro_build (&offset_expr
, s
, fmt
, treg
,
9180 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9183 expr1
.X_add_number
= offset_expr
.X_add_number
;
9184 offset_expr
.X_add_number
= 0;
9185 if (expr1
.X_add_number
< -0x8000
9186 || expr1
.X_add_number
>= 0x8000)
9187 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9188 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9189 lw_reloc_type
, mips_gp_register
);
9191 relax_start (offset_expr
.X_add_symbol
);
9193 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9194 tempreg
, BFD_RELOC_LO16
);
9197 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9198 tempreg
, tempreg
, breg
);
9199 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9201 else if (mips_big_got
&& !HAVE_NEWABI
)
9205 /* If this is a reference to an external symbol, we want
9206 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9207 addu $tempreg,$tempreg,$gp
9208 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9209 <op> $treg,0($tempreg)
9211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9213 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9214 <op> $treg,0($tempreg)
9215 If there is a base register, we add it to $tempreg before
9216 the <op>. If there is a constant, we stick it in the
9217 <op> instruction. We don't handle constants larger than
9218 16 bits, because we have no way to load the upper 16 bits
9219 (actually, we could handle them for the subset of cases
9220 in which we are not using $at). */
9221 gas_assert (offset_expr
.X_op
== O_symbol
);
9222 expr1
.X_add_number
= offset_expr
.X_add_number
;
9223 offset_expr
.X_add_number
= 0;
9224 if (expr1
.X_add_number
< -0x8000
9225 || expr1
.X_add_number
>= 0x8000)
9226 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9227 gpdelay
= reg_needs_delay (mips_gp_register
);
9228 relax_start (offset_expr
.X_add_symbol
);
9229 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9230 BFD_RELOC_MIPS_GOT_HI16
);
9231 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9234 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9237 macro_build (NULL
, "nop", "");
9238 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9239 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9241 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9242 tempreg
, BFD_RELOC_LO16
);
9246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9247 tempreg
, tempreg
, breg
);
9248 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9250 else if (mips_big_got
&& HAVE_NEWABI
)
9252 /* If this is a reference to an external symbol, we want
9253 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9254 add $tempreg,$tempreg,$gp
9255 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9256 <op> $treg,<ofst>($tempreg)
9257 Otherwise, for local symbols, we want:
9258 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9259 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9260 gas_assert (offset_expr
.X_op
== O_symbol
);
9261 expr1
.X_add_number
= offset_expr
.X_add_number
;
9262 offset_expr
.X_add_number
= 0;
9263 if (expr1
.X_add_number
< -0x8000
9264 || expr1
.X_add_number
>= 0x8000)
9265 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9266 relax_start (offset_expr
.X_add_symbol
);
9267 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9268 BFD_RELOC_MIPS_GOT_HI16
);
9269 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9271 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9272 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9275 tempreg
, tempreg
, breg
);
9276 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9279 offset_expr
.X_add_number
= expr1
.X_add_number
;
9280 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9281 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9283 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9284 tempreg
, tempreg
, breg
);
9285 macro_build (&offset_expr
, s
, fmt
, treg
,
9286 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9295 gas_assert (mips_opts
.micromips
);
9296 gas_assert (mips_opts
.insn32
);
9298 macro_build (NULL
, "jr", "s", RA
);
9299 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
9300 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
9305 gas_assert (mips_opts
.micromips
);
9306 gas_assert (mips_opts
.insn32
);
9307 macro_build (NULL
, "jr", "s", sreg
);
9308 if (mips_opts
.noreorder
)
9309 macro_build (NULL
, "nop", "");
9314 load_register (treg
, &imm_expr
, 0);
9318 load_register (treg
, &imm_expr
, 1);
9322 if (imm_expr
.X_op
== O_constant
)
9325 load_register (AT
, &imm_expr
, 0);
9326 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9331 gas_assert (offset_expr
.X_op
== O_symbol
9332 && strcmp (segment_name (S_GET_SEGMENT
9333 (offset_expr
.X_add_symbol
)),
9335 && offset_expr
.X_add_number
== 0);
9336 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9337 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9342 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9343 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9344 order 32 bits of the value and the low order 32 bits are either
9345 zero or in OFFSET_EXPR. */
9346 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9348 if (HAVE_64BIT_GPRS
)
9349 load_register (treg
, &imm_expr
, 1);
9354 if (target_big_endian
)
9366 load_register (hreg
, &imm_expr
, 0);
9369 if (offset_expr
.X_op
== O_absent
)
9370 move_register (lreg
, 0);
9373 gas_assert (offset_expr
.X_op
== O_constant
);
9374 load_register (lreg
, &offset_expr
, 0);
9381 /* We know that sym is in the .rdata section. First we get the
9382 upper 16 bits of the address. */
9383 if (mips_pic
== NO_PIC
)
9385 macro_build_lui (&offset_expr
, AT
);
9390 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9391 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9395 /* Now we load the register(s). */
9396 if (HAVE_64BIT_GPRS
)
9399 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9404 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9407 /* FIXME: How in the world do we deal with the possible
9409 offset_expr
.X_add_number
+= 4;
9410 macro_build (&offset_expr
, "lw", "t,o(b)",
9411 treg
+ 1, BFD_RELOC_LO16
, AT
);
9417 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9418 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9419 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9420 the value and the low order 32 bits are either zero or in
9422 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9425 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
9426 if (HAVE_64BIT_FPRS
)
9428 gas_assert (HAVE_64BIT_GPRS
);
9429 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
9433 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
9434 if (offset_expr
.X_op
== O_absent
)
9435 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
9438 gas_assert (offset_expr
.X_op
== O_constant
);
9439 load_register (AT
, &offset_expr
, 0);
9440 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9446 gas_assert (offset_expr
.X_op
== O_symbol
9447 && offset_expr
.X_add_number
== 0);
9448 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
9449 if (strcmp (s
, ".lit8") == 0)
9451 breg
= mips_gp_register
;
9452 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
9453 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9454 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9458 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
9460 if (mips_pic
!= NO_PIC
)
9461 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9462 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9465 /* FIXME: This won't work for a 64 bit address. */
9466 macro_build_lui (&offset_expr
, AT
);
9470 offset_reloc
[0] = BFD_RELOC_LO16
;
9471 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9472 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9479 * The MIPS assembler seems to check for X_add_number not
9480 * being double aligned and generating:
9483 * addiu at,at,%lo(foo+1)
9486 * But, the resulting address is the same after relocation so why
9487 * generate the extra instruction?
9489 /* Itbl support may require additional care here. */
9492 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9501 gas_assert (!mips_opts
.micromips
);
9502 /* Itbl support may require additional care here. */
9505 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9525 if (HAVE_64BIT_GPRS
)
9535 if (HAVE_64BIT_GPRS
)
9543 /* Even on a big endian machine $fn comes before $fn+1. We have
9544 to adjust when loading from memory. We set coproc if we must
9545 load $fn+1 first. */
9546 /* Itbl support may require additional care here. */
9547 if (!target_big_endian
)
9550 if (small_offset_p (0, align
, 16))
9553 if (!small_offset_p (4, align
, 16))
9555 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
9556 -1, offset_reloc
[0], offset_reloc
[1],
9558 expr1
.X_add_number
= 0;
9562 offset_reloc
[0] = BFD_RELOC_LO16
;
9563 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9564 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9566 if (strcmp (s
, "lw") == 0 && treg
== breg
)
9568 ep
->X_add_number
+= 4;
9569 macro_build (ep
, s
, fmt
, treg
+ 1, -1, offset_reloc
[0],
9570 offset_reloc
[1], offset_reloc
[2], breg
);
9571 ep
->X_add_number
-= 4;
9572 macro_build (ep
, s
, fmt
, treg
, -1, offset_reloc
[0],
9573 offset_reloc
[1], offset_reloc
[2], breg
);
9577 macro_build (ep
, s
, fmt
, coproc
? treg
+ 1 : treg
, -1,
9578 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9580 ep
->X_add_number
+= 4;
9581 macro_build (ep
, s
, fmt
, coproc
? treg
: treg
+ 1, -1,
9582 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9588 if (offset_expr
.X_op
!= O_symbol
9589 && offset_expr
.X_op
!= O_constant
)
9591 as_bad (_("Expression too complex"));
9592 offset_expr
.X_op
= O_constant
;
9595 if (HAVE_32BIT_ADDRESSES
9596 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9600 sprintf_vma (value
, offset_expr
.X_add_number
);
9601 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9604 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9606 /* If this is a reference to a GP relative symbol, we want
9607 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9608 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9609 If we have a base register, we use this
9611 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9612 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9613 If this is not a GP relative symbol, we want
9614 lui $at,<sym> (BFD_RELOC_HI16_S)
9615 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9616 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9617 If there is a base register, we add it to $at after the
9618 lui instruction. If there is a constant, we always use
9620 if (offset_expr
.X_op
== O_symbol
9621 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9622 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9624 relax_start (offset_expr
.X_add_symbol
);
9627 tempreg
= mips_gp_register
;
9631 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9632 AT
, breg
, mips_gp_register
);
9637 /* Itbl support may require additional care here. */
9638 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9639 BFD_RELOC_GPREL16
, tempreg
);
9640 offset_expr
.X_add_number
+= 4;
9642 /* Set mips_optimize to 2 to avoid inserting an
9644 hold_mips_optimize
= mips_optimize
;
9646 /* Itbl support may require additional care here. */
9647 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9648 BFD_RELOC_GPREL16
, tempreg
);
9649 mips_optimize
= hold_mips_optimize
;
9653 offset_expr
.X_add_number
-= 4;
9656 if (offset_high_part (offset_expr
.X_add_number
, 16)
9657 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
9659 load_address (AT
, &offset_expr
, &used_at
);
9660 offset_expr
.X_op
= O_constant
;
9661 offset_expr
.X_add_number
= 0;
9664 macro_build_lui (&offset_expr
, AT
);
9666 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9667 /* Itbl support may require additional care here. */
9668 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9669 BFD_RELOC_LO16
, AT
);
9670 /* FIXME: How do we handle overflow here? */
9671 offset_expr
.X_add_number
+= 4;
9672 /* Itbl support may require additional care here. */
9673 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9674 BFD_RELOC_LO16
, AT
);
9675 if (mips_relax
.sequence
)
9678 else if (!mips_big_got
)
9680 /* If this is a reference to an external symbol, we want
9681 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9686 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9688 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9689 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9690 If there is a base register we add it to $at before the
9691 lwc1 instructions. If there is a constant we include it
9692 in the lwc1 instructions. */
9694 expr1
.X_add_number
= offset_expr
.X_add_number
;
9695 if (expr1
.X_add_number
< -0x8000
9696 || expr1
.X_add_number
>= 0x8000 - 4)
9697 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9698 load_got_offset (AT
, &offset_expr
);
9701 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9703 /* Set mips_optimize to 2 to avoid inserting an undesired
9705 hold_mips_optimize
= mips_optimize
;
9708 /* Itbl support may require additional care here. */
9709 relax_start (offset_expr
.X_add_symbol
);
9710 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9711 BFD_RELOC_LO16
, AT
);
9712 expr1
.X_add_number
+= 4;
9713 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9714 BFD_RELOC_LO16
, AT
);
9716 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9717 BFD_RELOC_LO16
, AT
);
9718 offset_expr
.X_add_number
+= 4;
9719 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9720 BFD_RELOC_LO16
, AT
);
9723 mips_optimize
= hold_mips_optimize
;
9725 else if (mips_big_got
)
9729 /* If this is a reference to an external symbol, we want
9730 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9732 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9737 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9739 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9740 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9741 If there is a base register we add it to $at before the
9742 lwc1 instructions. If there is a constant we include it
9743 in the lwc1 instructions. */
9745 expr1
.X_add_number
= offset_expr
.X_add_number
;
9746 offset_expr
.X_add_number
= 0;
9747 if (expr1
.X_add_number
< -0x8000
9748 || expr1
.X_add_number
>= 0x8000 - 4)
9749 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9750 gpdelay
= reg_needs_delay (mips_gp_register
);
9751 relax_start (offset_expr
.X_add_symbol
);
9752 macro_build (&offset_expr
, "lui", LUI_FMT
,
9753 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9755 AT
, AT
, mips_gp_register
);
9756 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9757 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9761 /* Itbl support may require additional care here. */
9762 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9763 BFD_RELOC_LO16
, AT
);
9764 expr1
.X_add_number
+= 4;
9766 /* Set mips_optimize to 2 to avoid inserting an undesired
9768 hold_mips_optimize
= mips_optimize
;
9770 /* Itbl support may require additional care here. */
9771 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9772 BFD_RELOC_LO16
, AT
);
9773 mips_optimize
= hold_mips_optimize
;
9774 expr1
.X_add_number
-= 4;
9777 offset_expr
.X_add_number
= expr1
.X_add_number
;
9779 macro_build (NULL
, "nop", "");
9780 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9781 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9784 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9785 /* Itbl support may require additional care here. */
9786 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9787 BFD_RELOC_LO16
, AT
);
9788 offset_expr
.X_add_number
+= 4;
9790 /* Set mips_optimize to 2 to avoid inserting an undesired
9792 hold_mips_optimize
= mips_optimize
;
9794 /* Itbl support may require additional care here. */
9795 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9796 BFD_RELOC_LO16
, AT
);
9797 mips_optimize
= hold_mips_optimize
;
9816 /* New code added to support COPZ instructions.
9817 This code builds table entries out of the macros in mip_opcodes.
9818 R4000 uses interlocks to handle coproc delays.
9819 Other chips (like the R3000) require nops to be inserted for delays.
9821 FIXME: Currently, we require that the user handle delays.
9822 In order to fill delay slots for non-interlocked chips,
9823 we must have a way to specify delays based on the coprocessor.
9824 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9825 What are the side-effects of the cop instruction?
9826 What cache support might we have and what are its effects?
9827 Both coprocessor & memory require delays. how long???
9828 What registers are read/set/modified?
9830 If an itbl is provided to interpret cop instructions,
9831 this knowledge can be encoded in the itbl spec. */
9845 gas_assert (!mips_opts
.micromips
);
9846 /* For now we just do C (same as Cz). The parameter will be
9847 stored in insn_opcode by mips_ip. */
9848 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
9852 move_register (dreg
, sreg
);
9856 gas_assert (mips_opts
.micromips
);
9857 gas_assert (mips_opts
.insn32
);
9858 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
9859 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
9860 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
9861 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
9862 move_register (dreg
, sreg
);
9863 move_register (breg
, treg
);
9869 if (mips_opts
.arch
== CPU_R5900
)
9871 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9875 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9876 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9883 /* The MIPS assembler some times generates shifts and adds. I'm
9884 not trying to be that fancy. GCC should do this for us
9887 load_register (AT
, &imm_expr
, dbl
);
9888 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9889 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9905 load_register (AT
, &imm_expr
, dbl
);
9906 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9907 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9908 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9909 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9911 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9914 if (mips_opts
.micromips
)
9915 micromips_label_expr (&label_expr
);
9917 label_expr
.X_add_number
= 8;
9918 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9919 macro_build (NULL
, "nop", "");
9920 macro_build (NULL
, "break", BRK_FMT
, 6);
9921 if (mips_opts
.micromips
)
9922 micromips_add_label ();
9925 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9941 load_register (AT
, &imm_expr
, dbl
);
9942 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9943 sreg
, imm
? AT
: treg
);
9944 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9945 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9947 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9950 if (mips_opts
.micromips
)
9951 micromips_label_expr (&label_expr
);
9953 label_expr
.X_add_number
= 8;
9954 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9955 macro_build (NULL
, "nop", "");
9956 macro_build (NULL
, "break", BRK_FMT
, 6);
9957 if (mips_opts
.micromips
)
9958 micromips_add_label ();
9964 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9975 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9976 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9980 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9981 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9982 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9983 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9987 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9998 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9999 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
10003 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10004 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
10005 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
10006 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10015 if (imm_expr
.X_op
!= O_constant
)
10016 as_bad (_("Improper rotate count"));
10017 rot
= imm_expr
.X_add_number
& 0x3f;
10018 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10020 rot
= (64 - rot
) & 0x3f;
10022 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10024 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10029 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10032 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10033 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10036 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10037 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10038 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10046 if (imm_expr
.X_op
!= O_constant
)
10047 as_bad (_("Improper rotate count"));
10048 rot
= imm_expr
.X_add_number
& 0x1f;
10049 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10051 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10056 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10060 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10061 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10062 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10067 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10069 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10073 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10074 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10075 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10076 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10080 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10082 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10086 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10087 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10088 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10089 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10098 if (imm_expr
.X_op
!= O_constant
)
10099 as_bad (_("Improper rotate count"));
10100 rot
= imm_expr
.X_add_number
& 0x3f;
10101 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10104 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10106 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10111 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10114 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10115 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10118 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10119 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10120 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10128 if (imm_expr
.X_op
!= O_constant
)
10129 as_bad (_("Improper rotate count"));
10130 rot
= imm_expr
.X_add_number
& 0x1f;
10131 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10133 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10138 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10142 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10143 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10144 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10150 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10151 else if (treg
== 0)
10152 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10155 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10156 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10161 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10163 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10168 as_warn (_("Instruction %s: result is always false"),
10169 ip
->insn_mo
->name
);
10170 move_register (dreg
, 0);
10173 if (CPU_HAS_SEQ (mips_opts
.arch
)
10174 && -512 <= imm_expr
.X_add_number
10175 && imm_expr
.X_add_number
< 512)
10177 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10178 (int) imm_expr
.X_add_number
);
10181 if (imm_expr
.X_op
== O_constant
10182 && imm_expr
.X_add_number
>= 0
10183 && imm_expr
.X_add_number
< 0x10000)
10185 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10187 else if (imm_expr
.X_op
== O_constant
10188 && imm_expr
.X_add_number
> -0x8000
10189 && imm_expr
.X_add_number
< 0)
10191 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10192 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10193 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10195 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10198 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10199 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10204 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10205 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10208 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10211 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10217 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10218 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10221 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10223 if (imm_expr
.X_op
== O_constant
10224 && imm_expr
.X_add_number
>= -0x8000
10225 && imm_expr
.X_add_number
< 0x8000)
10227 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10228 dreg
, sreg
, BFD_RELOC_LO16
);
10232 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10233 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
10237 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10240 case M_SGT
: /* sreg > treg <==> treg < sreg */
10246 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10249 case M_SGT_I
: /* sreg > I <==> I < sreg */
10256 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10257 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10260 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10266 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10267 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10270 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10277 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10278 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10279 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10283 if (imm_expr
.X_op
== O_constant
10284 && imm_expr
.X_add_number
>= -0x8000
10285 && imm_expr
.X_add_number
< 0x8000)
10287 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10291 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10292 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
10296 if (imm_expr
.X_op
== O_constant
10297 && imm_expr
.X_add_number
>= -0x8000
10298 && imm_expr
.X_add_number
< 0x8000)
10300 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
10305 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10306 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
10311 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
10312 else if (treg
== 0)
10313 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10316 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10317 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10322 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10324 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10329 as_warn (_("Instruction %s: result is always true"),
10330 ip
->insn_mo
->name
);
10331 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10332 dreg
, 0, BFD_RELOC_LO16
);
10335 if (CPU_HAS_SEQ (mips_opts
.arch
)
10336 && -512 <= imm_expr
.X_add_number
10337 && imm_expr
.X_add_number
< 512)
10339 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10340 (int) imm_expr
.X_add_number
);
10343 if (imm_expr
.X_op
== O_constant
10344 && imm_expr
.X_add_number
>= 0
10345 && imm_expr
.X_add_number
< 0x10000)
10347 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10349 else if (imm_expr
.X_op
== O_constant
10350 && imm_expr
.X_add_number
> -0x8000
10351 && imm_expr
.X_add_number
< 0)
10353 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10354 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10355 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10357 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10360 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10361 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
10366 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10367 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10370 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10385 if (!mips_opts
.micromips
)
10387 if (imm_expr
.X_op
== O_constant
10388 && imm_expr
.X_add_number
> -0x200
10389 && imm_expr
.X_add_number
<= 0x200)
10391 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
10400 if (imm_expr
.X_op
== O_constant
10401 && imm_expr
.X_add_number
> -0x8000
10402 && imm_expr
.X_add_number
<= 0x8000)
10404 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10405 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10410 load_register (AT
, &imm_expr
, dbl
);
10411 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
10433 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10434 macro_build (NULL
, s
, "s,t", sreg
, AT
);
10439 gas_assert (!mips_opts
.micromips
);
10440 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
10442 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
10443 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
10446 * Is the double cfc1 instruction a bug in the mips assembler;
10447 * or is there a reason for it?
10449 start_noreorder ();
10450 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10451 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10452 macro_build (NULL
, "nop", "");
10453 expr1
.X_add_number
= 3;
10454 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
10455 expr1
.X_add_number
= 2;
10456 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
10457 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
10458 macro_build (NULL
, "nop", "");
10459 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
10461 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
10462 macro_build (NULL
, "nop", "");
10479 offbits
= (mips_opts
.micromips
? 12 : 16);
10485 offbits
= (mips_opts
.micromips
? 12 : 16);
10497 offbits
= (mips_opts
.micromips
? 12 : 16);
10504 offbits
= (mips_opts
.micromips
? 12 : 16);
10509 large_offset
= !small_offset_p (off
, align
, offbits
);
10511 expr1
.X_add_number
= 0;
10516 if (small_offset_p (0, align
, 16))
10517 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
10518 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10521 load_address (tempreg
, ep
, &used_at
);
10523 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10524 tempreg
, tempreg
, breg
);
10526 offset_reloc
[0] = BFD_RELOC_LO16
;
10527 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10528 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10533 else if (!ust
&& treg
== breg
)
10544 if (!target_big_endian
)
10545 ep
->X_add_number
+= off
;
10547 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
10549 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
10550 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
10552 if (!target_big_endian
)
10553 ep
->X_add_number
-= off
;
10555 ep
->X_add_number
+= off
;
10557 macro_build (NULL
, s2
, "t,~(b)",
10558 tempreg
, (int) ep
->X_add_number
, breg
);
10560 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
10561 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
10563 /* If necessary, move the result in tempreg to the final destination. */
10564 if (!ust
&& treg
!= tempreg
)
10566 /* Protect second load's delay slot. */
10568 move_register (treg
, tempreg
);
10574 if (target_big_endian
== ust
)
10575 ep
->X_add_number
+= off
;
10576 tempreg
= ust
|| large_offset
? treg
: AT
;
10577 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
10578 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
10580 /* For halfword transfers we need a temporary register to shuffle
10581 bytes. Unfortunately for M_USH_A we have none available before
10582 the next store as AT holds the base address. We deal with this
10583 case by clobbering TREG and then restoring it as with ULH. */
10584 tempreg
= ust
== large_offset
? treg
: AT
;
10586 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10588 if (target_big_endian
== ust
)
10589 ep
->X_add_number
-= off
;
10591 ep
->X_add_number
+= off
;
10592 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
10593 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
10595 /* For M_USH_A re-retrieve the LSB. */
10596 if (ust
&& large_offset
)
10598 if (target_big_endian
)
10599 ep
->X_add_number
+= off
;
10601 ep
->X_add_number
-= off
;
10602 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
10603 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
10605 /* For ULH and M_USH_A OR the LSB in. */
10606 if (!ust
|| large_offset
)
10608 tempreg
= !large_offset
? AT
: treg
;
10609 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10610 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10615 /* FIXME: Check if this is one of the itbl macros, since they
10616 are added dynamically. */
10617 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10620 if (!mips_opts
.at
&& used_at
)
10621 as_bad (_("Macro used $at after \".set noat\""));
10624 /* Implement macros in mips16 mode. */
10627 mips16_macro (struct mips_cl_insn
*ip
)
10630 int xreg
, yreg
, zreg
, tmp
;
10633 const char *s
, *s2
, *s3
;
10635 mask
= ip
->insn_mo
->mask
;
10637 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10638 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10639 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10641 expr1
.X_op
= O_constant
;
10642 expr1
.X_op_symbol
= NULL
;
10643 expr1
.X_add_symbol
= NULL
;
10644 expr1
.X_add_number
= 1;
10663 start_noreorder ();
10664 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10665 expr1
.X_add_number
= 2;
10666 macro_build (&expr1
, "bnez", "x,p", yreg
);
10667 macro_build (NULL
, "break", "6", 7);
10669 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10670 since that causes an overflow. We should do that as well,
10671 but I don't see how to do the comparisons without a temporary
10674 macro_build (NULL
, s
, "x", zreg
);
10693 start_noreorder ();
10694 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10695 expr1
.X_add_number
= 2;
10696 macro_build (&expr1
, "bnez", "x,p", yreg
);
10697 macro_build (NULL
, "break", "6", 7);
10699 macro_build (NULL
, s2
, "x", zreg
);
10705 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10706 macro_build (NULL
, "mflo", "x", zreg
);
10714 if (imm_expr
.X_op
!= O_constant
)
10715 as_bad (_("Unsupported large constant"));
10716 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10717 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10721 if (imm_expr
.X_op
!= O_constant
)
10722 as_bad (_("Unsupported large constant"));
10723 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10724 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10728 if (imm_expr
.X_op
!= O_constant
)
10729 as_bad (_("Unsupported large constant"));
10730 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10731 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10753 goto do_reverse_branch
;
10757 goto do_reverse_branch
;
10769 goto do_reverse_branch
;
10780 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10781 macro_build (&offset_expr
, s2
, "p");
10808 goto do_addone_branch_i
;
10813 goto do_addone_branch_i
;
10828 goto do_addone_branch_i
;
10834 do_addone_branch_i
:
10835 if (imm_expr
.X_op
!= O_constant
)
10836 as_bad (_("Unsupported large constant"));
10837 ++imm_expr
.X_add_number
;
10840 macro_build (&imm_expr
, s
, s3
, xreg
);
10841 macro_build (&offset_expr
, s2
, "p");
10845 expr1
.X_add_number
= 0;
10846 macro_build (&expr1
, "slti", "x,8", yreg
);
10848 move_register (xreg
, yreg
);
10849 expr1
.X_add_number
= 2;
10850 macro_build (&expr1
, "bteqz", "p");
10851 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10855 /* UDI immediates. */
10856 struct mips_immed
{
10858 unsigned int shift
;
10859 unsigned long mask
;
10863 static const struct mips_immed mips_immed
[] = {
10864 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10865 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10866 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10867 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10871 /* Check whether an odd floating-point register is allowed. */
10873 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10875 const char *s
= insn
->name
;
10877 if (insn
->pinfo
== INSN_MACRO
)
10878 /* Let a macro pass, we'll catch it later when it is expanded. */
10881 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10883 /* Allow odd registers for single-precision ops. */
10884 switch (insn
->pinfo
& (FP_S
| FP_D
))
10888 return 1; /* both single precision - ok */
10890 return 0; /* both double precision - fail */
10895 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10896 s
= strchr (insn
->name
, '.');
10898 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10899 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10902 /* Single-precision coprocessor loads and moves are OK too. */
10903 if ((insn
->pinfo
& FP_S
)
10904 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10905 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10911 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10912 taking bits from BIT up. */
10914 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10916 return (ep
->X_op
== O_constant
10917 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10918 && ep
->X_add_number
>= min
<< bit
10919 && ep
->X_add_number
< max
<< bit
);
10922 /* Assemble an instruction into its binary format. If the instruction
10923 is a macro, set imm_expr, imm2_expr and offset_expr to the values
10924 associated with "I", "+I" and "A" operands respectively. Otherwise
10925 store the value of the relocatable field (if any) in offset_expr.
10926 In both cases set offset_reloc to the relocation operators applied
10930 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10932 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10933 bfd_boolean need_delay_slot_ok
= TRUE
;
10934 struct mips_opcode
*firstinsn
= NULL
;
10935 const struct mips_opcode
*past
;
10936 struct hash_control
*hash
;
10940 struct mips_opcode
*insn
;
10942 unsigned int regno
, regno2
;
10943 unsigned int lastregno
;
10944 unsigned int destregno
= 0;
10945 unsigned int lastpos
= 0;
10946 unsigned int limlo
, limhi
;
10949 offsetT min_range
, max_range
;
10953 unsigned int rtype
;
10959 if (mips_opts
.micromips
)
10961 hash
= micromips_op_hash
;
10962 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10967 past
= &mips_opcodes
[NUMOPCODES
];
10969 forced_insn_length
= 0;
10972 /* We first try to match an instruction up to a space or to the end. */
10973 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10976 /* Make a copy of the instruction so that we can fiddle with it. */
10977 name
= alloca (end
+ 1);
10978 memcpy (name
, str
, end
);
10983 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10985 if (insn
!= NULL
|| !mips_opts
.micromips
)
10987 if (forced_insn_length
)
10990 /* See if there's an instruction size override suffix,
10991 either `16' or `32', at the end of the mnemonic proper,
10992 that defines the operation, i.e. before the first `.'
10993 character if any. Strip it and retry. */
10994 dot
= strchr (name
, '.');
10995 opend
= dot
!= NULL
? dot
- name
: end
;
10998 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10999 forced_insn_length
= 2;
11000 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11001 forced_insn_length
= 4;
11004 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11008 insn_error
= _("Unrecognized opcode");
11012 /* For microMIPS instructions placed in a fixed-length branch delay slot
11013 we make up to two passes over the relevant fragment of the opcode
11014 table. First we try instructions that meet the delay slot's length
11015 requirement. If none matched, then we retry with the remaining ones
11016 and if one matches, then we use it and then issue an appropriate
11017 warning later on. */
11018 argsStart
= s
= str
+ end
;
11021 bfd_boolean delay_slot_ok
;
11022 bfd_boolean size_ok
;
11025 gas_assert (strcmp (insn
->name
, name
) == 0);
11027 ok
= is_opcode_valid (insn
);
11028 size_ok
= is_size_valid (insn
);
11029 delay_slot_ok
= is_delay_slot_valid (insn
);
11030 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11033 wrong_delay_slot_insns
= TRUE
;
11035 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11037 static char buf
[256];
11039 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11044 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11046 gas_assert (firstinsn
);
11047 need_delay_slot_ok
= FALSE
;
11057 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11058 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11059 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11060 else if (mips_opts
.insn32
)
11061 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
11063 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11064 8 * forced_insn_length
);
11070 imm_expr
.X_op
= O_absent
;
11071 imm2_expr
.X_op
= O_absent
;
11072 offset_expr
.X_op
= O_absent
;
11073 offset_reloc
[0] = BFD_RELOC_UNUSED
;
11074 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11075 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11077 create_insn (ip
, insn
);
11080 lastregno
= 0xffffffff;
11081 for (args
= insn
->args
;; ++args
)
11085 s
+= strspn (s
, " \t");
11089 case '\0': /* end of args */
11095 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11096 code) or 14 (for microMIPS code). */
11097 my_getExpression (&imm_expr
, s
);
11098 check_absolute_expr (ip
, &imm_expr
);
11099 if ((unsigned long) imm_expr
.X_add_number
!= 1
11100 && (unsigned long) imm_expr
.X_add_number
!= 3)
11102 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11103 (unsigned long) imm_expr
.X_add_number
);
11105 INSERT_OPERAND (mips_opts
.micromips
,
11106 BP
, *ip
, imm_expr
.X_add_number
);
11107 imm_expr
.X_op
= O_absent
;
11112 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11113 code) or 13 (for microMIPS code). */
11115 unsigned long mask
= (mips_opts
.micromips
11116 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11118 my_getExpression (&imm_expr
, s
);
11119 check_absolute_expr (ip
, &imm_expr
);
11120 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11121 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11122 mask
, (unsigned long) imm_expr
.X_add_number
);
11123 INSERT_OPERAND (mips_opts
.micromips
,
11124 SA3
, *ip
, imm_expr
.X_add_number
);
11125 imm_expr
.X_op
= O_absent
;
11131 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11132 code) or 12 (for microMIPS code). */
11134 unsigned long mask
= (mips_opts
.micromips
11135 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11137 my_getExpression (&imm_expr
, s
);
11138 check_absolute_expr (ip
, &imm_expr
);
11139 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11140 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11141 mask
, (unsigned long) imm_expr
.X_add_number
);
11142 INSERT_OPERAND (mips_opts
.micromips
,
11143 SA4
, *ip
, imm_expr
.X_add_number
);
11144 imm_expr
.X_op
= O_absent
;
11150 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11151 code) or 13 (for microMIPS code). */
11153 unsigned long mask
= (mips_opts
.micromips
11154 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11156 my_getExpression (&imm_expr
, s
);
11157 check_absolute_expr (ip
, &imm_expr
);
11158 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11159 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11160 mask
, (unsigned long) imm_expr
.X_add_number
);
11161 INSERT_OPERAND (mips_opts
.micromips
,
11162 IMM8
, *ip
, imm_expr
.X_add_number
);
11163 imm_expr
.X_op
= O_absent
;
11169 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11170 code) or 16 (for microMIPS code). */
11172 unsigned long mask
= (mips_opts
.micromips
11173 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11175 my_getExpression (&imm_expr
, s
);
11176 check_absolute_expr (ip
, &imm_expr
);
11177 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11178 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11179 mask
, (unsigned long) imm_expr
.X_add_number
);
11180 INSERT_OPERAND (mips_opts
.micromips
,
11181 RS
, *ip
, imm_expr
.X_add_number
);
11182 imm_expr
.X_op
= O_absent
;
11188 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11189 or 14 (for microMIPS code). */
11190 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11191 && s
[3] >= '0' && s
[3] <= '3')
11193 regno
= s
[3] - '0';
11195 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11199 as_bad (_("Invalid dsp acc register"));
11203 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11204 code) or 14 (for microMIPS code). */
11206 unsigned long mask
= (mips_opts
.micromips
11207 ? MICROMIPSOP_MASK_WRDSP
11210 my_getExpression (&imm_expr
, s
);
11211 check_absolute_expr (ip
, &imm_expr
);
11212 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11213 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11214 mask
, (unsigned long) imm_expr
.X_add_number
);
11215 INSERT_OPERAND (mips_opts
.micromips
,
11216 WRDSP
, *ip
, imm_expr
.X_add_number
);
11217 imm_expr
.X_op
= O_absent
;
11222 case '9': /* Four DSP accumulators in bits 21,22. */
11223 gas_assert (!mips_opts
.micromips
);
11224 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11225 && s
[3] >= '0' && s
[3] <= '3')
11227 regno
= s
[3] - '0';
11229 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11233 as_bad (_("Invalid dsp acc register"));
11237 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11238 code) or 16 (for microMIPS code). */
11240 long mask
= (mips_opts
.micromips
11241 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11243 my_getExpression (&imm_expr
, s
);
11244 check_absolute_expr (ip
, &imm_expr
);
11245 min_range
= -((mask
+ 1) >> 1);
11246 max_range
= ((mask
+ 1) >> 1) - 1;
11247 if (imm_expr
.X_add_number
< min_range
11248 || imm_expr
.X_add_number
> max_range
)
11249 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11250 (long) min_range
, (long) max_range
,
11251 (long) imm_expr
.X_add_number
);
11252 INSERT_OPERAND (mips_opts
.micromips
,
11253 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11254 imm_expr
.X_op
= O_absent
;
11259 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11260 gas_assert (!mips_opts
.micromips
);
11261 my_getExpression (&imm_expr
, s
);
11262 check_absolute_expr (ip
, &imm_expr
);
11263 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11265 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11267 (unsigned long) imm_expr
.X_add_number
);
11269 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11270 imm_expr
.X_op
= O_absent
;
11274 case ':': /* DSP 7-bit signed immediate in bit 19. */
11275 gas_assert (!mips_opts
.micromips
);
11276 my_getExpression (&imm_expr
, s
);
11277 check_absolute_expr (ip
, &imm_expr
);
11278 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11279 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11280 if (imm_expr
.X_add_number
< min_range
||
11281 imm_expr
.X_add_number
> max_range
)
11283 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11284 (long) min_range
, (long) max_range
,
11285 (long) imm_expr
.X_add_number
);
11287 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11288 imm_expr
.X_op
= O_absent
;
11292 case '@': /* DSP 10-bit signed immediate in bit 16. */
11294 long mask
= (mips_opts
.micromips
11295 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11297 my_getExpression (&imm_expr
, s
);
11298 check_absolute_expr (ip
, &imm_expr
);
11299 min_range
= -((mask
+ 1) >> 1);
11300 max_range
= ((mask
+ 1) >> 1) - 1;
11301 if (imm_expr
.X_add_number
< min_range
11302 || imm_expr
.X_add_number
> max_range
)
11303 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11304 (long) min_range
, (long) max_range
,
11305 (long) imm_expr
.X_add_number
);
11306 INSERT_OPERAND (mips_opts
.micromips
,
11307 IMM10
, *ip
, imm_expr
.X_add_number
);
11308 imm_expr
.X_op
= O_absent
;
11313 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11314 gas_assert (mips_opts
.micromips
);
11315 my_getExpression (&imm_expr
, s
);
11316 check_absolute_expr (ip
, &imm_expr
);
11317 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11318 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11319 MICROMIPSOP_MASK_RD
,
11320 (unsigned long) imm_expr
.X_add_number
);
11321 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11322 imm_expr
.X_op
= O_absent
;
11326 case '!': /* MT usermode flag bit. */
11327 gas_assert (!mips_opts
.micromips
);
11328 my_getExpression (&imm_expr
, s
);
11329 check_absolute_expr (ip
, &imm_expr
);
11330 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11331 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11332 (unsigned long) imm_expr
.X_add_number
);
11333 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11334 imm_expr
.X_op
= O_absent
;
11338 case '$': /* MT load high flag bit. */
11339 gas_assert (!mips_opts
.micromips
);
11340 my_getExpression (&imm_expr
, s
);
11341 check_absolute_expr (ip
, &imm_expr
);
11342 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11343 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11344 (unsigned long) imm_expr
.X_add_number
);
11345 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11346 imm_expr
.X_op
= O_absent
;
11350 case '*': /* Four DSP accumulators in bits 18,19. */
11351 gas_assert (!mips_opts
.micromips
);
11352 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11353 s
[3] >= '0' && s
[3] <= '3')
11355 regno
= s
[3] - '0';
11357 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11361 as_bad (_("Invalid dsp/smartmips acc register"));
11364 case '&': /* Four DSP accumulators in bits 13,14. */
11365 gas_assert (!mips_opts
.micromips
);
11366 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11367 s
[3] >= '0' && s
[3] <= '3')
11369 regno
= s
[3] - '0';
11371 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11375 as_bad (_("Invalid dsp/smartmips acc register"));
11378 case '\\': /* 3-bit bit position. */
11380 unsigned long mask
= (mips_opts
.micromips
11381 ? MICROMIPSOP_MASK_3BITPOS
11382 : OP_MASK_3BITPOS
);
11384 my_getExpression (&imm_expr
, s
);
11385 check_absolute_expr (ip
, &imm_expr
);
11386 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11387 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11389 mask
, (unsigned long) imm_expr
.X_add_number
);
11390 INSERT_OPERAND (mips_opts
.micromips
,
11391 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11392 imm_expr
.X_op
= O_absent
;
11406 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11410 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11414 gas_assert (!mips_opts
.micromips
);
11415 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11419 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11425 /* Handle optional base register.
11426 Either the base register is omitted or
11427 we must have a left paren. */
11428 /* This is dependent on the next operand specifier
11429 is a base register specification. */
11430 gas_assert (args
[1] == 'b'
11431 || (mips_opts
.micromips
11433 && (args
[2] == 'l' || args
[2] == 'n'
11434 || args
[2] == 's' || args
[2] == 'a')));
11435 if (*s
== '\0' && args
[1] == 'b')
11437 /* Fall through. */
11439 case ')': /* These must match exactly. */
11444 case '+': /* Opcode extension character. */
11447 case '1': /* UDI immediates. */
11451 gas_assert (!mips_opts
.micromips
);
11453 const struct mips_immed
*imm
= mips_immed
;
11455 while (imm
->type
&& imm
->type
!= *args
)
11459 my_getExpression (&imm_expr
, s
);
11460 check_absolute_expr (ip
, &imm_expr
);
11461 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11463 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11464 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11465 (unsigned long) imm_expr
.X_add_number
,
11466 (unsigned long) imm_expr
.X_add_number
);
11467 imm_expr
.X_add_number
&= imm
->mask
;
11469 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11471 imm_expr
.X_op
= O_absent
;
11476 case 'J': /* 10-bit hypcall code. */
11477 gas_assert (!mips_opts
.micromips
);
11479 unsigned long mask
= OP_MASK_CODE10
;
11481 my_getExpression (&imm_expr
, s
);
11482 check_absolute_expr (ip
, &imm_expr
);
11483 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11484 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11486 mask
, (unsigned long) imm_expr
.X_add_number
);
11487 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11488 imm_expr
.X_op
= O_absent
;
11493 case 'A': /* ins/ext position, becomes LSB. */
11502 my_getExpression (&imm_expr
, s
);
11503 check_absolute_expr (ip
, &imm_expr
);
11504 if ((unsigned long) imm_expr
.X_add_number
< limlo
11505 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11507 as_bad (_("Improper position (%lu)"),
11508 (unsigned long) imm_expr
.X_add_number
);
11509 imm_expr
.X_add_number
= limlo
;
11511 lastpos
= imm_expr
.X_add_number
;
11512 INSERT_OPERAND (mips_opts
.micromips
,
11513 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11514 imm_expr
.X_op
= O_absent
;
11518 case 'B': /* ins size, becomes MSB. */
11527 my_getExpression (&imm_expr
, s
);
11528 check_absolute_expr (ip
, &imm_expr
);
11529 /* Check for negative input so that small negative numbers
11530 will not succeed incorrectly. The checks against
11531 (pos+size) transitively check "size" itself,
11532 assuming that "pos" is reasonable. */
11533 if ((long) imm_expr
.X_add_number
< 0
11534 || ((unsigned long) imm_expr
.X_add_number
11536 || ((unsigned long) imm_expr
.X_add_number
11537 + lastpos
) > limhi
)
11539 as_bad (_("Improper insert size (%lu, position %lu)"),
11540 (unsigned long) imm_expr
.X_add_number
,
11541 (unsigned long) lastpos
);
11542 imm_expr
.X_add_number
= limlo
- lastpos
;
11544 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11545 lastpos
+ imm_expr
.X_add_number
- 1);
11546 imm_expr
.X_op
= O_absent
;
11550 case 'C': /* ext size, becomes MSBD. */
11566 my_getExpression (&imm_expr
, s
);
11567 check_absolute_expr (ip
, &imm_expr
);
11568 /* The checks against (pos+size) don't transitively check
11569 "size" itself, assuming that "pos" is reasonable.
11570 We also need to check the lower bound of "size". */
11571 if ((long) imm_expr
.X_add_number
< sizelo
11572 || ((unsigned long) imm_expr
.X_add_number
11574 || ((unsigned long) imm_expr
.X_add_number
11575 + lastpos
) > limhi
)
11577 as_bad (_("Improper extract size (%lu, position %lu)"),
11578 (unsigned long) imm_expr
.X_add_number
,
11579 (unsigned long) lastpos
);
11580 imm_expr
.X_add_number
= limlo
- lastpos
;
11582 INSERT_OPERAND (mips_opts
.micromips
,
11583 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11584 imm_expr
.X_op
= O_absent
;
11589 /* "+I" is like "I", except that imm2_expr is used. */
11590 my_getExpression (&imm2_expr
, s
);
11591 if (imm2_expr
.X_op
!= O_big
11592 && imm2_expr
.X_op
!= O_constant
)
11593 insn_error
= _("absolute expression required");
11594 if (HAVE_32BIT_GPRS
)
11595 normalize_constant_expr (&imm2_expr
);
11599 case 't': /* Coprocessor register number. */
11600 gas_assert (!mips_opts
.micromips
);
11601 if (s
[0] == '$' && ISDIGIT (s
[1]))
11611 while (ISDIGIT (*s
));
11613 as_bad (_("Invalid register number (%d)"), regno
);
11616 INSERT_OPERAND (0, RT
, *ip
, regno
);
11621 as_bad (_("Invalid coprocessor 0 register number"));
11625 /* bbit[01] and bbit[01]32 bit index. Give error if index
11626 is not in the valid range. */
11627 gas_assert (!mips_opts
.micromips
);
11628 my_getExpression (&imm_expr
, s
);
11629 check_absolute_expr (ip
, &imm_expr
);
11630 if ((unsigned) imm_expr
.X_add_number
> 31)
11632 as_bad (_("Improper bit index (%lu)"),
11633 (unsigned long) imm_expr
.X_add_number
);
11634 imm_expr
.X_add_number
= 0;
11636 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11637 imm_expr
.X_op
= O_absent
;
11642 /* bbit[01] bit index when bbit is used but we generate
11643 bbit[01]32 because the index is over 32. Move to the
11644 next candidate if index is not in the valid range. */
11645 gas_assert (!mips_opts
.micromips
);
11646 my_getExpression (&imm_expr
, s
);
11647 check_absolute_expr (ip
, &imm_expr
);
11648 if ((unsigned) imm_expr
.X_add_number
< 32
11649 || (unsigned) imm_expr
.X_add_number
> 63)
11651 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11652 imm_expr
.X_op
= O_absent
;
11657 /* cins, cins32, exts and exts32 position field. Give error
11658 if it's not in the valid range. */
11659 gas_assert (!mips_opts
.micromips
);
11660 my_getExpression (&imm_expr
, s
);
11661 check_absolute_expr (ip
, &imm_expr
);
11662 if ((unsigned) imm_expr
.X_add_number
> 31)
11664 as_bad (_("Improper position (%lu)"),
11665 (unsigned long) imm_expr
.X_add_number
);
11666 imm_expr
.X_add_number
= 0;
11668 lastpos
= imm_expr
.X_add_number
;
11669 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11670 imm_expr
.X_op
= O_absent
;
11675 /* cins, cins32, exts and exts32 position field. Move to
11676 the next candidate if it's not in the valid range. */
11677 gas_assert (!mips_opts
.micromips
);
11678 my_getExpression (&imm_expr
, s
);
11679 check_absolute_expr (ip
, &imm_expr
);
11680 if ((unsigned) imm_expr
.X_add_number
< 32
11681 || (unsigned) imm_expr
.X_add_number
> 63)
11683 lastpos
= imm_expr
.X_add_number
;
11684 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11685 imm_expr
.X_op
= O_absent
;
11690 /* cins32 and exts32 length-minus-one field. */
11691 gas_assert (!mips_opts
.micromips
);
11692 my_getExpression (&imm_expr
, s
);
11693 check_absolute_expr (ip
, &imm_expr
);
11694 if ((unsigned long) imm_expr
.X_add_number
> 31
11695 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 31)
11697 as_bad (_("Improper size (%lu)"),
11698 (unsigned long) imm_expr
.X_add_number
);
11699 imm_expr
.X_add_number
= 0;
11701 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11702 imm_expr
.X_op
= O_absent
;
11707 /* cins/exts length-minus-one field. */
11708 gas_assert (!mips_opts
.micromips
);
11709 my_getExpression (&imm_expr
, s
);
11710 check_absolute_expr (ip
, &imm_expr
);
11711 if ((unsigned long) imm_expr
.X_add_number
> 31
11712 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11714 as_bad (_("Improper size (%lu)"),
11715 (unsigned long) imm_expr
.X_add_number
);
11716 imm_expr
.X_add_number
= 0;
11718 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11719 imm_expr
.X_op
= O_absent
;
11724 /* seqi/snei immediate field. */
11725 gas_assert (!mips_opts
.micromips
);
11726 my_getExpression (&imm_expr
, s
);
11727 check_absolute_expr (ip
, &imm_expr
);
11728 if ((long) imm_expr
.X_add_number
< -512
11729 || (long) imm_expr
.X_add_number
>= 512)
11731 as_bad (_("Improper immediate (%ld)"),
11732 (long) imm_expr
.X_add_number
);
11733 imm_expr
.X_add_number
= 0;
11735 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11736 imm_expr
.X_op
= O_absent
;
11740 case 'a': /* 8-bit signed offset in bit 6 */
11741 gas_assert (!mips_opts
.micromips
);
11742 my_getExpression (&imm_expr
, s
);
11743 check_absolute_expr (ip
, &imm_expr
);
11744 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11745 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11746 if (imm_expr
.X_add_number
< min_range
11747 || imm_expr
.X_add_number
> max_range
)
11749 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11750 (long) min_range
, (long) max_range
,
11751 (long) imm_expr
.X_add_number
);
11753 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11754 imm_expr
.X_op
= O_absent
;
11758 case 'b': /* 8-bit signed offset in bit 3 */
11759 gas_assert (!mips_opts
.micromips
);
11760 my_getExpression (&imm_expr
, s
);
11761 check_absolute_expr (ip
, &imm_expr
);
11762 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11763 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11764 if (imm_expr
.X_add_number
< min_range
11765 || imm_expr
.X_add_number
> max_range
)
11767 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11768 (long) min_range
, (long) max_range
,
11769 (long) imm_expr
.X_add_number
);
11771 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11772 imm_expr
.X_op
= O_absent
;
11776 case 'c': /* 9-bit signed offset in bit 6 */
11777 gas_assert (!mips_opts
.micromips
);
11778 my_getExpression (&imm_expr
, s
);
11779 check_absolute_expr (ip
, &imm_expr
);
11780 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11781 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11782 /* We check the offset range before adjusted. */
11785 if (imm_expr
.X_add_number
< min_range
11786 || imm_expr
.X_add_number
> max_range
)
11788 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11789 (long) min_range
, (long) max_range
,
11790 (long) imm_expr
.X_add_number
);
11792 if (imm_expr
.X_add_number
& 0xf)
11794 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11795 (long) imm_expr
.X_add_number
);
11797 /* Right shift 4 bits to adjust the offset operand. */
11798 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11799 imm_expr
.X_add_number
>> 4);
11800 imm_expr
.X_op
= O_absent
;
11805 gas_assert (!mips_opts
.micromips
);
11806 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11808 if (regno
== AT
&& mips_opts
.at
)
11810 if (mips_opts
.at
== ATREG
)
11811 as_warn (_("used $at without \".set noat\""));
11813 as_warn (_("used $%u with \".set at=$%u\""),
11814 regno
, mips_opts
.at
);
11816 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11820 gas_assert (!mips_opts
.micromips
);
11821 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11823 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11833 bfd_reloc_code_real_type r
[3];
11835 /* Check whether there is only a single bracketed expression
11836 left. If so, it must be the base register and the
11837 constant must be zero. */
11838 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11841 /* If this value won't fit into the offset, then go find
11842 a macro that will generate a 16- or 32-bit offset code
11844 i
= my_getSmallExpression (&imm_expr
, r
, s
);
11845 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11846 || imm_expr
.X_add_number
>= 1 << shift
11847 || imm_expr
.X_add_number
< -1 << shift
))
11850 imm_expr
.X_op
= O_absent
;
11853 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
11854 imm_expr
.X_add_number
);
11855 imm_expr
.X_op
= O_absent
;
11861 as_bad (_("Internal error: bad %s opcode "
11862 "(unknown extension operand type `+%c'): %s %s"),
11863 mips_opts
.micromips
? "microMIPS" : "MIPS",
11864 *args
, insn
->name
, insn
->args
);
11865 /* Further processing is fruitless. */
11870 case '.': /* 10-bit offset. */
11871 gas_assert (mips_opts
.micromips
);
11872 case '~': /* 12-bit offset. */
11874 int shift
= *args
== '.' ? 9 : 11;
11876 bfd_reloc_code_real_type r
[3];
11878 /* Check whether there is only a single bracketed expression
11879 left. If so, it must be the base register and the
11880 constant must be zero. */
11881 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11884 /* If this value won't fit into the offset, then go find
11885 a macro that will generate a 16- or 32-bit offset code
11887 i
= my_getSmallExpression (&imm_expr
, r
, s
);
11888 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11889 || imm_expr
.X_add_number
>= 1 << shift
11890 || imm_expr
.X_add_number
< -1 << shift
))
11893 imm_expr
.X_op
= O_absent
;
11897 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11899 INSERT_OPERAND (mips_opts
.micromips
,
11900 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11901 imm_expr
.X_op
= O_absent
;
11906 case '<': /* must be at least one digit */
11908 * According to the manual, if the shift amount is greater
11909 * than 31 or less than 0, then the shift amount should be
11910 * mod 32. In reality the mips assembler issues an error.
11911 * We issue a warning and mask out all but the low 5 bits.
11913 my_getExpression (&imm_expr
, s
);
11914 check_absolute_expr (ip
, &imm_expr
);
11915 if ((unsigned long) imm_expr
.X_add_number
> 31)
11916 as_warn (_("Improper shift amount (%lu)"),
11917 (unsigned long) imm_expr
.X_add_number
);
11918 INSERT_OPERAND (mips_opts
.micromips
,
11919 SHAMT
, *ip
, imm_expr
.X_add_number
);
11920 imm_expr
.X_op
= O_absent
;
11924 case '>': /* shift amount minus 32 */
11925 my_getExpression (&imm_expr
, s
);
11926 check_absolute_expr (ip
, &imm_expr
);
11927 if ((unsigned long) imm_expr
.X_add_number
< 32
11928 || (unsigned long) imm_expr
.X_add_number
> 63)
11930 INSERT_OPERAND (mips_opts
.micromips
,
11931 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11932 imm_expr
.X_op
= O_absent
;
11936 case 'k': /* CACHE code. */
11937 case 'h': /* PREFX code. */
11938 case '1': /* SYNC type. */
11939 my_getExpression (&imm_expr
, s
);
11940 check_absolute_expr (ip
, &imm_expr
);
11941 if ((unsigned long) imm_expr
.X_add_number
> 31)
11942 as_warn (_("Invalid value for `%s' (%lu)"),
11944 (unsigned long) imm_expr
.X_add_number
);
11948 if (mips_fix_cn63xxp1
11949 && !mips_opts
.micromips
11950 && strcmp ("pref", insn
->name
) == 0)
11951 switch (imm_expr
.X_add_number
)
11960 case 31: /* These are ok. */
11963 default: /* The rest must be changed to 28. */
11964 imm_expr
.X_add_number
= 28;
11967 INSERT_OPERAND (mips_opts
.micromips
,
11968 CACHE
, *ip
, imm_expr
.X_add_number
);
11971 INSERT_OPERAND (mips_opts
.micromips
,
11972 PREFX
, *ip
, imm_expr
.X_add_number
);
11975 INSERT_OPERAND (mips_opts
.micromips
,
11976 STYPE
, *ip
, imm_expr
.X_add_number
);
11979 imm_expr
.X_op
= O_absent
;
11983 case 'c': /* BREAK code. */
11985 unsigned long mask
= (mips_opts
.micromips
11986 ? MICROMIPSOP_MASK_CODE
11989 my_getExpression (&imm_expr
, s
);
11990 check_absolute_expr (ip
, &imm_expr
);
11991 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11992 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11994 mask
, (unsigned long) imm_expr
.X_add_number
);
11995 INSERT_OPERAND (mips_opts
.micromips
,
11996 CODE
, *ip
, imm_expr
.X_add_number
);
11997 imm_expr
.X_op
= O_absent
;
12002 case 'q': /* Lower BREAK code. */
12004 unsigned long mask
= (mips_opts
.micromips
12005 ? MICROMIPSOP_MASK_CODE2
12008 my_getExpression (&imm_expr
, s
);
12009 check_absolute_expr (ip
, &imm_expr
);
12010 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12011 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12013 mask
, (unsigned long) imm_expr
.X_add_number
);
12014 INSERT_OPERAND (mips_opts
.micromips
,
12015 CODE2
, *ip
, imm_expr
.X_add_number
);
12016 imm_expr
.X_op
= O_absent
;
12021 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12023 unsigned long mask
= (mips_opts
.micromips
12024 ? MICROMIPSOP_MASK_CODE10
12027 my_getExpression (&imm_expr
, s
);
12028 check_absolute_expr (ip
, &imm_expr
);
12029 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12030 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12032 mask
, (unsigned long) imm_expr
.X_add_number
);
12033 if (mips_opts
.micromips
)
12034 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12036 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12037 imm_expr
.X_op
= O_absent
;
12042 case 'C': /* 25- or 23-bit coprocessor code. */
12044 unsigned long mask
= (mips_opts
.micromips
12045 ? MICROMIPSOP_MASK_COPZ
12048 my_getExpression (&imm_expr
, s
);
12049 check_absolute_expr (ip
, &imm_expr
);
12050 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12051 as_warn (_("Coproccesor code > %u bits (%lu)"),
12052 mips_opts
.micromips
? 23U : 25U,
12053 (unsigned long) imm_expr
.X_add_number
);
12054 INSERT_OPERAND (mips_opts
.micromips
,
12055 COPZ
, *ip
, imm_expr
.X_add_number
);
12056 imm_expr
.X_op
= O_absent
;
12061 case 'J': /* 19-bit WAIT code. */
12062 gas_assert (!mips_opts
.micromips
);
12063 my_getExpression (&imm_expr
, s
);
12064 check_absolute_expr (ip
, &imm_expr
);
12065 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12067 as_warn (_("Illegal 19-bit code (%lu)"),
12068 (unsigned long) imm_expr
.X_add_number
);
12069 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12071 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12072 imm_expr
.X_op
= O_absent
;
12076 case 'P': /* Performance register. */
12077 gas_assert (!mips_opts
.micromips
);
12078 my_getExpression (&imm_expr
, s
);
12079 check_absolute_expr (ip
, &imm_expr
);
12080 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12081 as_warn (_("Invalid performance register (%lu)"),
12082 (unsigned long) imm_expr
.X_add_number
);
12083 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12084 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12085 as_warn (_("Invalid performance register (%lu)"),
12086 (unsigned long) imm_expr
.X_add_number
);
12087 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12088 imm_expr
.X_op
= O_absent
;
12092 case 'G': /* Coprocessor destination register. */
12094 unsigned long opcode
= ip
->insn_opcode
;
12095 unsigned long mask
;
12096 unsigned int types
;
12099 if (mips_opts
.micromips
)
12101 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12102 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12103 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12107 case 0x000000fc: /* mfc0 */
12108 case 0x000002fc: /* mtc0 */
12109 case 0x580000fc: /* dmfc0 */
12110 case 0x580002fc: /* dmtc0 */
12120 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12121 cop0
= opcode
== OP_OP_COP0
;
12123 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12124 ok
= reg_lookup (&s
, types
, ®no
);
12125 if (mips_opts
.micromips
)
12126 INSERT_OPERAND (1, RS
, *ip
, regno
);
12128 INSERT_OPERAND (0, RD
, *ip
, regno
);
12137 case 'y': /* ALNV.PS source register. */
12138 gas_assert (mips_opts
.micromips
);
12140 case 'x': /* Ignore register name. */
12141 case 'U': /* Destination register (CLO/CLZ). */
12142 case 'g': /* Coprocessor destination register. */
12143 gas_assert (!mips_opts
.micromips
);
12144 case 'b': /* Base register. */
12145 case 'd': /* Destination register. */
12146 case 's': /* Source register. */
12147 case 't': /* Target register. */
12148 case 'r': /* Both target and source. */
12149 case 'v': /* Both dest and source. */
12150 case 'w': /* Both dest and target. */
12151 case 'E': /* Coprocessor target register. */
12152 case 'K': /* RDHWR destination register. */
12153 case 'z': /* Must be zero register. */
12156 if (*args
== 'E' || *args
== 'K')
12157 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12160 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12161 if (regno
== AT
&& mips_opts
.at
)
12163 if (mips_opts
.at
== ATREG
)
12164 as_warn (_("Used $at without \".set noat\""));
12166 as_warn (_("Used $%u with \".set at=$%u\""),
12167 regno
, mips_opts
.at
);
12177 if (c
== 'r' || c
== 'v' || c
== 'w')
12184 /* 'z' only matches $0. */
12185 if (c
== 'z' && regno
!= 0)
12188 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12190 if (regno
== lastregno
)
12193 = _("Source and destination must be different");
12196 if (regno
== 31 && lastregno
== 0xffffffff)
12199 = _("A destination register must be supplied");
12203 /* Now that we have assembled one operand, we use the args
12204 string to figure out where it goes in the instruction. */
12211 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12215 if (mips_opts
.micromips
)
12216 INSERT_OPERAND (1, RS
, *ip
, regno
);
12218 INSERT_OPERAND (0, RD
, *ip
, regno
);
12223 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12227 gas_assert (!mips_opts
.micromips
);
12228 INSERT_OPERAND (0, RD
, *ip
, regno
);
12229 INSERT_OPERAND (0, RT
, *ip
, regno
);
12235 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12239 gas_assert (mips_opts
.micromips
);
12240 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12244 /* This case exists because on the r3000 trunc
12245 expands into a macro which requires a gp
12246 register. On the r6000 or r4000 it is
12247 assembled into a single instruction which
12248 ignores the register. Thus the insn version
12249 is MIPS_ISA2 and uses 'x', and the macro
12250 version is MIPS_ISA1 and uses 't'. */
12254 /* This case is for the div instruction, which
12255 acts differently if the destination argument
12256 is $0. This only matches $0, and is checked
12257 outside the switch. */
12267 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12271 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12276 case 'O': /* MDMX alignment immediate constant. */
12277 gas_assert (!mips_opts
.micromips
);
12278 my_getExpression (&imm_expr
, s
);
12279 check_absolute_expr (ip
, &imm_expr
);
12280 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12281 as_warn (_("Improper align amount (%ld), using low bits"),
12282 (long) imm_expr
.X_add_number
);
12283 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12284 imm_expr
.X_op
= O_absent
;
12288 case 'Q': /* MDMX vector, element sel, or const. */
12291 /* MDMX Immediate. */
12292 gas_assert (!mips_opts
.micromips
);
12293 my_getExpression (&imm_expr
, s
);
12294 check_absolute_expr (ip
, &imm_expr
);
12295 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12296 as_warn (_("Invalid MDMX Immediate (%ld)"),
12297 (long) imm_expr
.X_add_number
);
12298 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12299 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12300 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12302 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12303 imm_expr
.X_op
= O_absent
;
12307 /* Not MDMX Immediate. Fall through. */
12308 case 'X': /* MDMX destination register. */
12309 case 'Y': /* MDMX source register. */
12310 case 'Z': /* MDMX target register. */
12311 is_mdmx
= !(insn
->membership
& INSN_5400
);
12313 gas_assert (!mips_opts
.micromips
);
12314 case 'D': /* Floating point destination register. */
12315 case 'S': /* Floating point source register. */
12316 case 'T': /* Floating point target register. */
12317 case 'R': /* Floating point source register. */
12321 || ((mips_opts
.ase
& ASE_MDMX
)
12322 && (ip
->insn_mo
->pinfo
& FP_D
)
12323 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12324 | INSN_COPROC_MEMORY_DELAY
12325 | INSN_LOAD_COPROC_DELAY
12326 | INSN_LOAD_MEMORY_DELAY
12327 | INSN_STORE_MEMORY
))))
12328 rtype
|= RTYPE_VEC
;
12330 if (reg_lookup (&s
, rtype
, ®no
))
12332 if ((regno
& 1) != 0
12334 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12335 as_warn (_("Float register should be even, was %d"),
12343 if (c
== 'V' || c
== 'W')
12354 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12360 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12364 /* This is like 'Z', but also needs to fix the MDMX
12365 vector/scalar select bits. Note that the
12366 scalar immediate case is handled above. */
12367 if ((ip
->insn_mo
->membership
& INSN_5400
)
12368 && strcmp (insn
->name
, "rzu.ob") == 0)
12369 as_bad (_("Operand %d of `%s' must be an immediate"),
12370 argnum
, ip
->insn_mo
->name
);
12374 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12375 int max_el
= (is_qh
? 3 : 7);
12377 my_getExpression(&imm_expr
, s
);
12378 check_absolute_expr (ip
, &imm_expr
);
12380 if (imm_expr
.X_add_number
> max_el
)
12381 as_bad (_("Bad element selector %ld"),
12382 (long) imm_expr
.X_add_number
);
12383 imm_expr
.X_add_number
&= max_el
;
12384 ip
->insn_opcode
|= (imm_expr
.X_add_number
12387 imm_expr
.X_op
= O_absent
;
12389 as_warn (_("Expecting ']' found '%s'"), s
);
12395 if ((ip
->insn_mo
->membership
& INSN_5400
)
12396 && (strcmp (insn
->name
, "sll.ob") == 0
12397 || strcmp (insn
->name
, "srl.ob") == 0))
12398 as_bad (_("Operand %d of `%s' must be scalar"),
12399 argnum
, ip
->insn_mo
->name
);
12401 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12402 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12405 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12408 /* Fall through. */
12412 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12416 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12426 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12430 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12436 my_getExpression (&imm_expr
, s
);
12437 if (imm_expr
.X_op
!= O_big
12438 && imm_expr
.X_op
!= O_constant
)
12439 insn_error
= _("absolute expression required");
12440 if (HAVE_32BIT_GPRS
)
12441 normalize_constant_expr (&imm_expr
);
12446 my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
12447 if (offset_expr
.X_op
== O_register
)
12449 /* Assume that the offset has been elided and that what
12450 we saw was a base register. The match will fail later
12451 if that assumption turns out to be wrong. */
12452 offset_expr
.X_op
= O_constant
;
12453 offset_expr
.X_add_number
= 0;
12457 normalize_address_expr (&offset_expr
);
12471 unsigned char temp
[8];
12473 unsigned int length
;
12478 /* These only appear as the last operand in an
12479 instruction, and every instruction that accepts
12480 them in any variant accepts them in all variants.
12481 This means we don't have to worry about backing out
12482 any changes if the instruction does not match.
12484 The difference between them is the size of the
12485 floating point constant and where it goes. For 'F'
12486 and 'L' the constant is 64 bits; for 'f' and 'l' it
12487 is 32 bits. Where the constant is placed is based
12488 on how the MIPS assembler does things:
12491 f -- immediate value
12494 The .lit4 and .lit8 sections are only used if
12495 permitted by the -G argument.
12497 The code below needs to know whether the target register
12498 is 32 or 64 bits wide. It relies on the fact 'f' and
12499 'F' are used with GPR-based instructions and 'l' and
12500 'L' are used with FPR-based instructions. */
12502 f64
= *args
== 'F' || *args
== 'L';
12503 using_gprs
= *args
== 'F' || *args
== 'f';
12505 save_in
= input_line_pointer
;
12506 input_line_pointer
= s
;
12507 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12509 s
= input_line_pointer
;
12510 input_line_pointer
= save_in
;
12511 if (err
!= NULL
&& *err
!= '\0')
12513 as_bad (_("Bad floating point constant: %s"), err
);
12514 memset (temp
, '\0', sizeof temp
);
12515 length
= f64
? 8 : 4;
12518 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12522 && (g_switch_value
< 4
12523 || (temp
[0] == 0 && temp
[1] == 0)
12524 || (temp
[2] == 0 && temp
[3] == 0))))
12526 imm_expr
.X_op
= O_constant
;
12527 if (!target_big_endian
)
12528 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12530 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12532 else if (length
> 4
12533 && !mips_disable_float_construction
12534 /* Constants can only be constructed in GPRs and
12535 copied to FPRs if the GPRs are at least as wide
12536 as the FPRs. Force the constant into memory if
12537 we are using 64-bit FPRs but the GPRs are only
12540 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12541 && ((temp
[0] == 0 && temp
[1] == 0)
12542 || (temp
[2] == 0 && temp
[3] == 0))
12543 && ((temp
[4] == 0 && temp
[5] == 0)
12544 || (temp
[6] == 0 && temp
[7] == 0)))
12546 /* The value is simple enough to load with a couple of
12547 instructions. If using 32-bit registers, set
12548 imm_expr to the high order 32 bits and offset_expr to
12549 the low order 32 bits. Otherwise, set imm_expr to
12550 the entire 64 bit constant. */
12551 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12553 imm_expr
.X_op
= O_constant
;
12554 offset_expr
.X_op
= O_constant
;
12555 if (!target_big_endian
)
12557 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12558 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12562 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12563 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12565 if (offset_expr
.X_add_number
== 0)
12566 offset_expr
.X_op
= O_absent
;
12570 imm_expr
.X_op
= O_constant
;
12571 if (!target_big_endian
)
12572 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12574 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12579 const char *newname
;
12582 /* Switch to the right section. */
12584 subseg
= now_subseg
;
12587 default: /* unused default case avoids warnings. */
12589 newname
= RDATA_SECTION_NAME
;
12590 if (g_switch_value
>= 8)
12594 newname
= RDATA_SECTION_NAME
;
12597 gas_assert (g_switch_value
>= 4);
12601 new_seg
= subseg_new (newname
, (subsegT
) 0);
12602 bfd_set_section_flags (stdoutput
, new_seg
,
12607 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12608 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12609 record_alignment (new_seg
, 4);
12611 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12612 if (seg
== now_seg
)
12613 as_bad (_("Can't use floating point insn in this section"));
12615 /* Set the argument to the current address in the
12617 offset_expr
.X_op
= O_symbol
;
12618 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12619 offset_expr
.X_add_number
= 0;
12621 /* Put the floating point number into the section. */
12622 p
= frag_more ((int) length
);
12623 memcpy (p
, temp
, length
);
12625 /* Switch back to the original section. */
12626 subseg_set (seg
, subseg
);
12631 case 'i': /* 16-bit unsigned immediate. */
12632 case 'j': /* 16-bit signed immediate. */
12633 *offset_reloc
= BFD_RELOC_LO16
;
12634 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0)
12637 offsetT minval
, maxval
;
12639 more
= (insn
+ 1 < past
12640 && strcmp (insn
->name
, insn
[1].name
) == 0);
12642 /* For compatibility with older assemblers, we accept
12643 0x8000-0xffff as signed 16-bit numbers when only
12644 signed numbers are allowed. */
12646 minval
= 0, maxval
= 0xffff;
12648 minval
= -0x8000, maxval
= 0x7fff;
12650 minval
= -0x8000, maxval
= 0xffff;
12652 if (offset_expr
.X_op
!= O_constant
12653 || offset_expr
.X_add_number
< minval
12654 || offset_expr
.X_add_number
> maxval
)
12658 if (offset_expr
.X_op
== O_constant
12659 || offset_expr
.X_op
== O_big
)
12660 as_bad (_("Expression out of range"));
12666 case 'o': /* 16-bit offset. */
12667 offset_reloc
[0] = BFD_RELOC_LO16
;
12668 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12669 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12671 /* Check whether there is only a single bracketed expression
12672 left. If so, it must be the base register and the
12673 constant must be zero. */
12674 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12676 offset_expr
.X_op
= O_constant
;
12677 offset_expr
.X_add_number
= 0;
12681 /* If this value won't fit into a 16 bit offset, then go
12682 find a macro that will generate the 32 bit offset
12684 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12685 && (offset_expr
.X_op
!= O_constant
12686 || offset_expr
.X_add_number
>= 0x8000
12687 || offset_expr
.X_add_number
< -0x8000))
12693 case 'p': /* PC-relative offset. */
12694 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12695 my_getExpression (&offset_expr
, s
);
12699 case 'u': /* Upper 16 bits. */
12700 *offset_reloc
= BFD_RELOC_LO16
;
12701 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12702 && offset_expr
.X_op
== O_constant
12703 && (offset_expr
.X_add_number
< 0
12704 || offset_expr
.X_add_number
>= 0x10000))
12705 as_bad (_("lui expression (%lu) not in range 0..65535"),
12706 (unsigned long) offset_expr
.X_add_number
);
12710 case 'a': /* 26-bit address. */
12712 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12713 my_getExpression (&offset_expr
, s
);
12717 case 'N': /* 3-bit branch condition code. */
12718 case 'M': /* 3-bit compare condition code. */
12720 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12721 rtype
|= RTYPE_FCC
;
12722 if (!reg_lookup (&s
, rtype
, ®no
))
12724 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12725 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12726 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12727 && (regno
& 1) != 0)
12728 as_warn (_("Condition code register should be even for %s, "
12731 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12732 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12733 && (regno
& 3) != 0)
12734 as_warn (_("Condition code register should be 0 or 4 for %s, "
12738 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12740 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12744 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12755 while (ISDIGIT (*s
));
12758 c
= 8; /* Invalid sel value. */
12761 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12762 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12766 gas_assert (!mips_opts
.micromips
);
12767 /* Must be at least one digit. */
12768 my_getExpression (&imm_expr
, s
);
12769 check_absolute_expr (ip
, &imm_expr
);
12771 if ((unsigned long) imm_expr
.X_add_number
12772 > (unsigned long) OP_MASK_VECBYTE
)
12774 as_bad (_("bad byte vector index (%ld)"),
12775 (long) imm_expr
.X_add_number
);
12776 imm_expr
.X_add_number
= 0;
12779 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12780 imm_expr
.X_op
= O_absent
;
12785 gas_assert (!mips_opts
.micromips
);
12786 my_getExpression (&imm_expr
, s
);
12787 check_absolute_expr (ip
, &imm_expr
);
12789 if ((unsigned long) imm_expr
.X_add_number
12790 > (unsigned long) OP_MASK_VECALIGN
)
12792 as_bad (_("bad byte vector index (%ld)"),
12793 (long) imm_expr
.X_add_number
);
12794 imm_expr
.X_add_number
= 0;
12797 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12798 imm_expr
.X_op
= O_absent
;
12802 case 'm': /* Opcode extension character. */
12803 gas_assert (mips_opts
.micromips
);
12808 if (strncmp (s
, "$pc", 3) == 0)
12835 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12836 if (regno
== AT
&& mips_opts
.at
)
12838 if (mips_opts
.at
== ATREG
)
12839 as_warn (_("Used $at without \".set noat\""));
12841 as_warn (_("Used $%u with \".set at=$%u\""),
12842 regno
, mips_opts
.at
);
12848 gas_assert (args
[1] == ',');
12854 gas_assert (args
[1] == ',');
12856 continue; /* Nothing to do. */
12862 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12864 if (regno
== lastregno
)
12867 = _("Source and destination must be different");
12870 if (regno
== 31 && lastregno
== 0xffffffff)
12873 = _("A destination register must be supplied");
12884 gas_assert (args
[1] == ',');
12891 gas_assert (args
[1] == ',');
12894 continue; /* Nothing to do. */
12898 /* Make sure regno is the same as lastregno. */
12899 if (c
== 't' && regno
!= lastregno
)
12902 /* Make sure regno is the same as destregno. */
12903 if (c
== 'x' && regno
!= destregno
)
12906 /* We need to save regno, before regno maps to the
12907 microMIPS register encoding. */
12917 regno
= ILLEGAL_REG
;
12921 regno
= mips32_to_micromips_reg_b_map
[regno
];
12925 regno
= mips32_to_micromips_reg_c_map
[regno
];
12929 regno
= mips32_to_micromips_reg_d_map
[regno
];
12933 regno
= mips32_to_micromips_reg_e_map
[regno
];
12937 regno
= mips32_to_micromips_reg_f_map
[regno
];
12941 regno
= mips32_to_micromips_reg_g_map
[regno
];
12945 s
+= strspn (s
, " \t");
12948 regno
= ILLEGAL_REG
;
12952 s
+= strspn (s
, " \t");
12953 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no2
);
12956 regno
= ILLEGAL_REG
;
12959 if (regno2
== AT
&& mips_opts
.at
)
12961 if (mips_opts
.at
== ATREG
)
12962 as_warn (_("Used $at without \".set noat\""));
12964 as_warn (_("Used $%u with \".set at=$%u\""),
12965 regno2
, mips_opts
.at
);
12967 regno
= (mips_lookup_reg_pair
12969 micromips_to_32_reg_h_map1
,
12970 micromips_to_32_reg_h_map2
, 8));
12974 regno
= mips32_to_micromips_reg_l_map
[regno
];
12978 regno
= mips32_to_micromips_reg_m_map
[regno
];
12982 regno
= mips32_to_micromips_reg_n_map
[regno
];
12986 regno
= mips32_to_micromips_reg_q_map
[regno
];
12991 regno
= ILLEGAL_REG
;
12996 regno
= ILLEGAL_REG
;
13001 regno
= ILLEGAL_REG
;
13004 case 'j': /* Do nothing. */
13014 if (regno
== ILLEGAL_REG
)
13020 INSERT_OPERAND (1, MB
, *ip
, regno
);
13024 INSERT_OPERAND (1, MC
, *ip
, regno
);
13028 INSERT_OPERAND (1, MD
, *ip
, regno
);
13032 INSERT_OPERAND (1, ME
, *ip
, regno
);
13036 INSERT_OPERAND (1, MF
, *ip
, regno
);
13040 INSERT_OPERAND (1, MG
, *ip
, regno
);
13044 INSERT_OPERAND (1, MH
, *ip
, regno
);
13048 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13052 INSERT_OPERAND (1, ML
, *ip
, regno
);
13056 INSERT_OPERAND (1, MM
, *ip
, regno
);
13060 INSERT_OPERAND (1, MN
, *ip
, regno
);
13064 INSERT_OPERAND (1, MP
, *ip
, regno
);
13068 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13071 case 'a': /* Do nothing. */
13072 case 's': /* Do nothing. */
13073 case 't': /* Do nothing. */
13074 case 'x': /* Do nothing. */
13075 case 'y': /* Do nothing. */
13076 case 'z': /* Do nothing. */
13086 bfd_reloc_code_real_type r
[3];
13090 /* Check whether there is only a single bracketed
13091 expression left. If so, it must be the base register
13092 and the constant must be zero. */
13093 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13095 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13099 if (my_getSmallExpression (&ep
, r
, s
) > 0
13100 || !expr_const_in_range (&ep
, -64, 64, 2))
13103 imm
= ep
.X_add_number
>> 2;
13104 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13111 bfd_reloc_code_real_type r
[3];
13115 if (my_getSmallExpression (&ep
, r
, s
) > 0
13116 || ep
.X_op
!= O_constant
)
13119 for (imm
= 0; imm
< 8; imm
++)
13120 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13125 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13132 bfd_reloc_code_real_type r
[3];
13136 if (my_getSmallExpression (&ep
, r
, s
) > 0
13137 || ep
.X_op
!= O_constant
)
13140 for (imm
= 0; imm
< 16; imm
++)
13141 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13146 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13151 case 'D': /* pc relative offset */
13152 case 'E': /* pc relative offset */
13153 my_getExpression (&offset_expr
, s
);
13154 if (offset_expr
.X_op
== O_register
)
13157 if (!forced_insn_length
)
13158 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13160 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13162 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13168 bfd_reloc_code_real_type r
[3];
13172 if (my_getSmallExpression (&ep
, r
, s
) > 0
13173 || !expr_const_in_range (&ep
, 0, 16, 0))
13176 imm
= ep
.X_add_number
;
13177 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13184 bfd_reloc_code_real_type r
[3];
13188 /* Check whether there is only a single bracketed
13189 expression left. If so, it must be the base register
13190 and the constant must be zero. */
13191 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13193 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13197 if (my_getSmallExpression (&ep
, r
, s
) > 0
13198 || !expr_const_in_range (&ep
, -1, 15, 0))
13201 imm
= ep
.X_add_number
& 15;
13202 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13209 bfd_reloc_code_real_type r
[3];
13213 /* Check whether there is only a single bracketed
13214 expression left. If so, it must be the base register
13215 and the constant must be zero. */
13216 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13218 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13222 if (my_getSmallExpression (&ep
, r
, s
) > 0
13223 || !expr_const_in_range (&ep
, 0, 16, 1))
13226 imm
= ep
.X_add_number
>> 1;
13227 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13234 bfd_reloc_code_real_type r
[3];
13238 if (my_getSmallExpression (&ep
, r
, s
) > 0
13239 || !expr_const_in_range (&ep
, -1, 127, 0))
13242 imm
= ep
.X_add_number
& 127;
13243 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13250 bfd_reloc_code_real_type r
[3];
13254 /* Check whether there is only a single bracketed
13255 expression left. If so, it must be the base register
13256 and the constant must be zero. */
13257 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13259 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13263 if (my_getSmallExpression (&ep
, r
, s
) > 0
13264 || !expr_const_in_range (&ep
, 0, 16, 2))
13267 imm
= ep
.X_add_number
>> 2;
13268 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13275 bfd_reloc_code_real_type r
[3];
13279 /* Check whether there is only a single bracketed
13280 expression left. If so, it must be the base register
13281 and the constant must be zero. */
13282 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13284 INSERT_OPERAND (1, IMML
, *ip
, 0);
13288 if (my_getSmallExpression (&ep
, r
, s
) > 0
13289 || !expr_const_in_range (&ep
, 0, 16, 0))
13292 imm
= ep
.X_add_number
;
13293 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13300 bfd_reloc_code_real_type r
[3];
13304 if (my_getSmallExpression (&ep
, r
, s
) > 0
13305 || !expr_const_in_range (&ep
, 1, 9, 0))
13308 imm
= ep
.X_add_number
& 7;
13309 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13314 case 'N': /* Register list for lwm and swm. */
13316 /* A comma-separated list of registers and/or
13317 dash-separated contiguous ranges including
13318 both ra and a set of one or more registers
13319 starting at s0 up to s3 which have to be
13326 and any permutations of these. */
13327 unsigned int reglist
;
13330 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13333 if ((reglist
& 0xfff1ffff) != 0x80010000)
13336 reglist
= (reglist
>> 17) & 7;
13338 if ((reglist
& -reglist
) != reglist
)
13341 imm
= ffs (reglist
) - 1;
13342 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13346 case 'O': /* sdbbp 4-bit code. */
13348 bfd_reloc_code_real_type r
[3];
13352 if (my_getSmallExpression (&ep
, r
, s
) > 0
13353 || !expr_const_in_range (&ep
, 0, 16, 0))
13356 imm
= ep
.X_add_number
;
13357 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13364 bfd_reloc_code_real_type r
[3];
13368 if (my_getSmallExpression (&ep
, r
, s
) > 0
13369 || !expr_const_in_range (&ep
, 0, 32, 2))
13372 imm
= ep
.X_add_number
>> 2;
13373 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13380 bfd_reloc_code_real_type r
[3];
13384 if (my_getSmallExpression (&ep
, r
, s
) > 0
13385 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13388 imm
= ep
.X_add_number
>> 2;
13389 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13396 bfd_reloc_code_real_type r
[3];
13400 /* Check whether there is only a single bracketed
13401 expression left. If so, it must be the base register
13402 and the constant must be zero. */
13403 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13405 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13409 if (my_getSmallExpression (&ep
, r
, s
) > 0
13410 || !expr_const_in_range (&ep
, 0, 32, 2))
13413 imm
= ep
.X_add_number
>> 2;
13414 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13421 bfd_reloc_code_real_type r
[3];
13425 if (my_getSmallExpression (&ep
, r
, s
) > 0
13426 || !expr_const_in_range (&ep
, 0, 64, 2))
13429 imm
= ep
.X_add_number
>> 2;
13430 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13437 bfd_reloc_code_real_type r
[3];
13441 if (my_getSmallExpression (&ep
, r
, s
) > 0
13442 || !expr_const_in_range (&ep
, -8, 8, 0))
13445 imm
= ep
.X_add_number
;
13446 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13453 bfd_reloc_code_real_type r
[3];
13457 if (my_getSmallExpression (&ep
, r
, s
) > 0
13458 || expr_const_in_range (&ep
, -2, 2, 2)
13459 || !expr_const_in_range (&ep
, -258, 258, 2))
13462 imm
= ep
.X_add_number
>> 2;
13463 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13464 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13471 bfd_reloc_code_real_type r
[3];
13474 if (my_getSmallExpression (&ep
, r
, s
) > 0
13475 || !expr_const_in_range (&ep
, 0, 1, 0))
13482 as_bad (_("Internal error: bad microMIPS opcode "
13483 "(unknown extension operand type `m%c'): %s %s"),
13484 *args
, insn
->name
, insn
->args
);
13485 /* Further processing is fruitless. */
13490 case 'n': /* Register list for 32-bit lwm and swm. */
13491 gas_assert (mips_opts
.micromips
);
13493 /* A comma-separated list of registers and/or
13494 dash-separated contiguous ranges including
13495 at least one of ra and a set of one or more
13496 registers starting at s0 up to s7 and then
13497 s8 which have to be consecutive, e.g.:
13505 and any permutations of these. */
13506 unsigned int reglist
;
13510 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13513 if ((reglist
& 0x3f00ffff) != 0)
13516 ra
= (reglist
>> 27) & 0x10;
13517 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13519 if ((reglist
& -reglist
) != reglist
)
13522 imm
= (ffs (reglist
) - 1) | ra
;
13523 INSERT_OPERAND (1, RT
, *ip
, imm
);
13524 imm_expr
.X_op
= O_absent
;
13528 case '|': /* 4-bit trap code. */
13529 gas_assert (mips_opts
.micromips
);
13530 my_getExpression (&imm_expr
, s
);
13531 check_absolute_expr (ip
, &imm_expr
);
13532 if ((unsigned long) imm_expr
.X_add_number
13533 > MICROMIPSOP_MASK_TRAP
)
13534 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13535 (unsigned long) imm_expr
.X_add_number
,
13536 ip
->insn_mo
->name
);
13537 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13538 imm_expr
.X_op
= O_absent
;
13543 as_bad (_("Bad char = '%c'\n"), *args
);
13548 /* Args don't match. */
13550 insn_error
= _("Illegal operands");
13551 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13556 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13558 gas_assert (firstinsn
);
13559 need_delay_slot_ok
= FALSE
;
13568 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13570 /* As for mips_ip, but used when assembling MIPS16 code.
13571 Also set forced_insn_length to the resulting instruction size in
13572 bytes if the user explicitly requested a small or extended instruction. */
13575 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13579 struct mips_opcode
*insn
;
13581 unsigned int regno
;
13582 unsigned int lastregno
= 0;
13588 forced_insn_length
= 0;
13590 for (s
= str
; ISLOWER (*s
); ++s
)
13602 if (s
[1] == 't' && s
[2] == ' ')
13605 forced_insn_length
= 2;
13609 else if (s
[1] == 'e' && s
[2] == ' ')
13612 forced_insn_length
= 4;
13616 /* Fall through. */
13618 insn_error
= _("unknown opcode");
13622 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13623 forced_insn_length
= 2;
13625 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13627 insn_error
= _("unrecognized opcode");
13637 gas_assert (strcmp (insn
->name
, str
) == 0);
13639 ok
= is_opcode_valid_16 (insn
);
13642 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13643 && strcmp (insn
->name
, insn
[1].name
) == 0)
13652 static char buf
[100];
13654 _("Opcode not supported on this processor: %s (%s)"),
13655 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13656 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13663 create_insn (ip
, insn
);
13664 imm_expr
.X_op
= O_absent
;
13665 imm2_expr
.X_op
= O_absent
;
13666 offset_expr
.X_op
= O_absent
;
13667 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13668 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13669 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13671 for (args
= insn
->args
; 1; ++args
)
13678 /* In this switch statement we call break if we did not find
13679 a match, continue if we did find a match, or return if we
13690 /* Stuff the immediate value in now, if we can. */
13691 if (insn
->pinfo
== INSN_MACRO
)
13693 gas_assert (relax_char
== 0);
13694 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
13696 else if (relax_char
13697 && offset_expr
.X_op
== O_constant
13698 && calculate_reloc (*offset_reloc
,
13699 offset_expr
.X_add_number
,
13702 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
13703 forced_insn_length
, &ip
->insn_opcode
);
13704 offset_expr
.X_op
= O_absent
;
13705 *offset_reloc
= BFD_RELOC_UNUSED
;
13707 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
13709 if (forced_insn_length
== 2)
13710 as_bad (_("invalid unextended operand value"));
13711 forced_insn_length
= 4;
13712 ip
->insn_opcode
|= MIPS16_EXTEND
;
13714 else if (relax_char
)
13715 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
13728 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13731 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13747 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13749 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13753 /* Fall through. */
13764 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13766 if (c
== 'v' || c
== 'w')
13769 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13771 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13782 if (c
== 'v' || c
== 'w')
13784 regno
= mips16_to_32_reg_map
[lastregno
];
13798 regno
= mips32_to_16_reg_map
[regno
];
13803 regno
= ILLEGAL_REG
;
13808 regno
= ILLEGAL_REG
;
13813 regno
= ILLEGAL_REG
;
13818 if (regno
== AT
&& mips_opts
.at
)
13820 if (mips_opts
.at
== ATREG
)
13821 as_warn (_("used $at without \".set noat\""));
13823 as_warn (_("used $%u with \".set at=$%u\""),
13824 regno
, mips_opts
.at
);
13832 if (regno
== ILLEGAL_REG
)
13839 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13843 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13846 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13849 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13855 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13858 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13859 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13869 if (strncmp (s
, "$pc", 3) == 0)
13886 i
= my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
13893 *offset_reloc
= BFD_RELOC_UNUSED
;
13894 /* Fall through. */
13901 my_getExpression (&offset_expr
, s
);
13902 if (offset_expr
.X_op
== O_register
)
13904 /* What we thought was an expression turned out to
13907 if (s
[0] == '(' && args
[1] == '(')
13909 /* It looks like the expression was omitted
13910 before a register indirection, which means
13911 that the expression is implicitly zero. We
13912 still set up offset_expr, so that we handle
13913 explicit extensions correctly. */
13914 offset_expr
.X_op
= O_constant
;
13915 offset_expr
.X_add_number
= 0;
13923 /* We need to relax this instruction. */
13933 /* We use offset_reloc rather than imm_reloc for the PC
13934 relative operands. This lets macros with both
13935 immediate and address operands work correctly. */
13936 my_getExpression (&offset_expr
, s
);
13938 if (offset_expr
.X_op
== O_register
)
13941 /* We need to relax this instruction. */
13946 case '6': /* break code */
13947 my_getExpression (&imm_expr
, s
);
13948 check_absolute_expr (ip
, &imm_expr
);
13949 if ((unsigned long) imm_expr
.X_add_number
> 63)
13950 as_warn (_("Invalid value for `%s' (%lu)"),
13952 (unsigned long) imm_expr
.X_add_number
);
13953 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13954 imm_expr
.X_op
= O_absent
;
13959 my_getExpression (&imm_expr
, s
);
13960 if (imm_expr
.X_op
!= O_big
13961 && imm_expr
.X_op
!= O_constant
)
13962 insn_error
= _("absolute expression required");
13963 if (HAVE_32BIT_GPRS
)
13964 normalize_constant_expr (&imm_expr
);
13968 case 'a': /* 26 bit address */
13970 my_getExpression (&offset_expr
, s
);
13972 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13973 ip
->insn_opcode
<<= 16;
13976 case 'l': /* register list for entry macro */
13977 case 'L': /* register list for exit macro */
13987 unsigned int freg
, reg1
, reg2
;
13989 while (*s
== ' ' || *s
== ',')
13991 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13993 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13997 as_bad (_("can't parse register list"));
14007 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14008 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14010 as_bad (_("invalid register list"));
14014 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14016 mask
&= ~ (7 << 3);
14019 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14021 mask
&= ~ (7 << 3);
14024 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14025 mask
|= (reg2
- 3) << 3;
14026 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14027 mask
|= (reg2
- 15) << 1;
14028 else if (reg1
== RA
&& reg2
== RA
)
14032 as_bad (_("invalid register list"));
14036 /* The mask is filled in in the opcode table for the
14037 benefit of the disassembler. We remove it before
14038 applying the actual mask. */
14039 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14040 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14044 case 'm': /* Register list for save insn. */
14045 case 'M': /* Register list for restore insn. */
14047 int opcode
= ip
->insn_opcode
;
14048 int framesz
= 0, seen_framesz
= 0;
14049 int nargs
= 0, statics
= 0, sregs
= 0;
14053 unsigned int reg1
, reg2
;
14055 SKIP_SPACE_TABS (s
);
14058 SKIP_SPACE_TABS (s
);
14060 my_getExpression (&imm_expr
, s
);
14061 if (imm_expr
.X_op
== O_constant
)
14063 /* Handle the frame size. */
14066 as_bad (_("more than one frame size in list"));
14070 framesz
= imm_expr
.X_add_number
;
14071 imm_expr
.X_op
= O_absent
;
14076 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14078 as_bad (_("can't parse register list"));
14090 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14093 as_bad (_("can't parse register list"));
14098 while (reg1
<= reg2
)
14100 if (reg1
>= 4 && reg1
<= 7)
14104 nargs
|= 1 << (reg1
- 4);
14106 /* statics $a0-$a3 */
14107 statics
|= 1 << (reg1
- 4);
14109 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14112 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14114 else if (reg1
== 31)
14116 /* Add $ra to insn. */
14121 as_bad (_("unexpected register in list"));
14129 /* Encode args/statics combination. */
14130 if (nargs
& statics
)
14131 as_bad (_("arg/static registers overlap"));
14132 else if (nargs
== 0xf)
14133 /* All $a0-$a3 are args. */
14134 opcode
|= MIPS16_ALL_ARGS
<< 16;
14135 else if (statics
== 0xf)
14136 /* All $a0-$a3 are statics. */
14137 opcode
|= MIPS16_ALL_STATICS
<< 16;
14140 int narg
= 0, nstat
= 0;
14142 /* Count arg registers. */
14143 while (nargs
& 0x1)
14149 as_bad (_("invalid arg register list"));
14151 /* Count static registers. */
14152 while (statics
& 0x8)
14154 statics
= (statics
<< 1) & 0xf;
14158 as_bad (_("invalid static register list"));
14160 /* Encode args/statics. */
14161 opcode
|= ((narg
<< 2) | nstat
) << 16;
14164 /* Encode $s0/$s1. */
14165 if (sregs
& (1 << 0)) /* $s0 */
14167 if (sregs
& (1 << 1)) /* $s1 */
14173 /* Count regs $s2-$s8. */
14181 as_bad (_("invalid static register list"));
14182 /* Encode $s2-$s8. */
14183 opcode
|= nsreg
<< 24;
14186 /* Encode frame size. */
14188 as_bad (_("missing frame size"));
14189 else if ((framesz
& 7) != 0 || framesz
< 0
14190 || framesz
> 0xff * 8)
14191 as_bad (_("invalid frame size"));
14192 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14195 opcode
|= (((framesz
& 0xf0) << 16)
14196 | (framesz
& 0x0f));
14199 /* Finally build the instruction. */
14200 if ((opcode
>> 16) != 0 || framesz
== 0)
14201 opcode
|= MIPS16_EXTEND
;
14202 ip
->insn_opcode
= opcode
;
14206 case 'e': /* extend code */
14207 my_getExpression (&imm_expr
, s
);
14208 check_absolute_expr (ip
, &imm_expr
);
14209 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14211 as_warn (_("Invalid value for `%s' (%lu)"),
14213 (unsigned long) imm_expr
.X_add_number
);
14214 imm_expr
.X_add_number
&= 0x7ff;
14216 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14217 imm_expr
.X_op
= O_absent
;
14227 /* Args don't match. */
14228 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14229 strcmp (insn
->name
, insn
[1].name
) == 0)
14236 insn_error
= _("illegal operands");
14242 /* This structure holds information we know about a mips16 immediate
14245 struct mips16_immed_operand
14247 /* The type code used in the argument string in the opcode table. */
14249 /* The number of bits in the short form of the opcode. */
14251 /* The number of bits in the extended form of the opcode. */
14253 /* The amount by which the short form is shifted when it is used;
14254 for example, the sw instruction has a shift count of 2. */
14256 /* The amount by which the short form is shifted when it is stored
14257 into the instruction code. */
14259 /* Non-zero if the short form is unsigned. */
14261 /* Non-zero if the extended form is unsigned. */
14263 /* Non-zero if the value is PC relative. */
14267 /* The mips16 immediate operand types. */
14269 static const struct mips16_immed_operand mips16_immed_operands
[] =
14271 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14272 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14273 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14274 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14275 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14276 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14277 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14278 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14279 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14280 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14281 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14282 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14283 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14284 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14285 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14286 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14287 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14288 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14289 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14290 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14291 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14294 #define MIPS16_NUM_IMMED \
14295 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14297 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14298 NBITS is the number of significant bits in VAL. */
14300 static unsigned long
14301 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14306 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14309 else if (nbits
== 15)
14311 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14316 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14319 return (extval
<< 16) | val
;
14322 /* Install immediate value VAL into MIPS16 instruction *INSN,
14323 extending it if necessary. The instruction in *INSN may
14324 already be extended.
14326 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14327 if none. In the former case, VAL is a 16-bit number with no
14328 defined signedness.
14330 TYPE is the type of the immediate field. USER_INSN_LENGTH
14331 is the length that the user requested, or 0 if none. */
14334 mips16_immed (char *file
, unsigned int line
, int type
,
14335 bfd_reloc_code_real_type reloc
, offsetT val
,
14336 unsigned int user_insn_length
, unsigned long *insn
)
14338 const struct mips16_immed_operand
*op
;
14339 int mintiny
, maxtiny
;
14341 op
= mips16_immed_operands
;
14342 while (op
->type
!= type
)
14345 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14350 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14353 maxtiny
= 1 << op
->nbits
;
14358 maxtiny
= (1 << op
->nbits
) - 1;
14360 if (reloc
!= BFD_RELOC_UNUSED
)
14365 mintiny
= - (1 << (op
->nbits
- 1));
14366 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14367 if (reloc
!= BFD_RELOC_UNUSED
)
14368 val
= SEXT_16BIT (val
);
14371 /* Branch offsets have an implicit 0 in the lowest bit. */
14372 if (type
== 'p' || type
== 'q')
14375 if ((val
& ((1 << op
->shift
) - 1)) != 0
14376 || val
< (mintiny
<< op
->shift
)
14377 || val
> (maxtiny
<< op
->shift
))
14379 /* We need an extended instruction. */
14380 if (user_insn_length
== 2)
14381 as_bad_where (file
, line
, _("invalid unextended operand value"));
14383 *insn
|= MIPS16_EXTEND
;
14385 else if (user_insn_length
== 4)
14387 /* The operand doesn't force an unextended instruction to be extended.
14388 Warn if the user wanted an extended instruction anyway. */
14389 *insn
|= MIPS16_EXTEND
;
14390 as_warn_where (file
, line
,
14391 _("extended operand requested but not required"));
14394 if (mips16_opcode_length (*insn
) == 2)
14398 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14399 insnval
<<= op
->op_shift
;
14404 long minext
, maxext
;
14406 if (reloc
== BFD_RELOC_UNUSED
)
14411 maxext
= (1 << op
->extbits
) - 1;
14415 minext
= - (1 << (op
->extbits
- 1));
14416 maxext
= (1 << (op
->extbits
- 1)) - 1;
14418 if (val
< minext
|| val
> maxext
)
14419 as_bad_where (file
, line
,
14420 _("operand value out of range for instruction"));
14423 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14427 struct percent_op_match
14430 bfd_reloc_code_real_type reloc
;
14433 static const struct percent_op_match mips_percent_op
[] =
14435 {"%lo", BFD_RELOC_LO16
},
14436 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14437 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14438 {"%call16", BFD_RELOC_MIPS_CALL16
},
14439 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14440 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14441 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14442 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14443 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14444 {"%got", BFD_RELOC_MIPS_GOT16
},
14445 {"%gp_rel", BFD_RELOC_GPREL16
},
14446 {"%half", BFD_RELOC_16
},
14447 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14448 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14449 {"%neg", BFD_RELOC_MIPS_SUB
},
14450 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14451 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14452 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14453 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14454 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14455 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14456 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14457 {"%hi", BFD_RELOC_HI16_S
}
14460 static const struct percent_op_match mips16_percent_op
[] =
14462 {"%lo", BFD_RELOC_MIPS16_LO16
},
14463 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14464 {"%got", BFD_RELOC_MIPS16_GOT16
},
14465 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14466 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14467 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14468 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14469 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14470 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14471 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14472 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14473 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14477 /* Return true if *STR points to a relocation operator. When returning true,
14478 move *STR over the operator and store its relocation code in *RELOC.
14479 Leave both *STR and *RELOC alone when returning false. */
14482 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14484 const struct percent_op_match
*percent_op
;
14487 if (mips_opts
.mips16
)
14489 percent_op
= mips16_percent_op
;
14490 limit
= ARRAY_SIZE (mips16_percent_op
);
14494 percent_op
= mips_percent_op
;
14495 limit
= ARRAY_SIZE (mips_percent_op
);
14498 for (i
= 0; i
< limit
; i
++)
14499 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14501 int len
= strlen (percent_op
[i
].str
);
14503 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14506 *str
+= strlen (percent_op
[i
].str
);
14507 *reloc
= percent_op
[i
].reloc
;
14509 /* Check whether the output BFD supports this relocation.
14510 If not, issue an error and fall back on something safe. */
14511 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14513 as_bad (_("relocation %s isn't supported by the current ABI"),
14514 percent_op
[i
].str
);
14515 *reloc
= BFD_RELOC_UNUSED
;
14523 /* Parse string STR as a 16-bit relocatable operand. Store the
14524 expression in *EP and the relocations in the array starting
14525 at RELOC. Return the number of relocation operators used.
14527 On exit, EXPR_END points to the first character after the expression. */
14530 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14533 bfd_reloc_code_real_type reversed_reloc
[3];
14534 size_t reloc_index
, i
;
14535 int crux_depth
, str_depth
;
14538 /* Search for the start of the main expression, recoding relocations
14539 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14540 of the main expression and with CRUX_DEPTH containing the number
14541 of open brackets at that point. */
14548 crux_depth
= str_depth
;
14550 /* Skip over whitespace and brackets, keeping count of the number
14552 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14557 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14558 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14560 my_getExpression (ep
, crux
);
14563 /* Match every open bracket. */
14564 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14568 if (crux_depth
> 0)
14569 as_bad (_("unclosed '('"));
14573 if (reloc_index
!= 0)
14575 prev_reloc_op_frag
= frag_now
;
14576 for (i
= 0; i
< reloc_index
; i
++)
14577 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14580 return reloc_index
;
14584 my_getExpression (expressionS
*ep
, char *str
)
14588 save_in
= input_line_pointer
;
14589 input_line_pointer
= str
;
14591 expr_end
= input_line_pointer
;
14592 input_line_pointer
= save_in
;
14596 md_atof (int type
, char *litP
, int *sizeP
)
14598 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14602 md_number_to_chars (char *buf
, valueT val
, int n
)
14604 if (target_big_endian
)
14605 number_to_chars_bigendian (buf
, val
, n
);
14607 number_to_chars_littleendian (buf
, val
, n
);
14610 static int support_64bit_objects(void)
14612 const char **list
, **l
;
14615 list
= bfd_target_list ();
14616 for (l
= list
; *l
!= NULL
; l
++)
14617 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14618 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14620 yes
= (*l
!= NULL
);
14625 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14626 NEW_VALUE. Warn if another value was already specified. Note:
14627 we have to defer parsing the -march and -mtune arguments in order
14628 to handle 'from-abi' correctly, since the ABI might be specified
14629 in a later argument. */
14632 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14634 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14635 as_warn (_("A different %s was already specified, is now %s"),
14636 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14639 *string_ptr
= new_value
;
14643 md_parse_option (int c
, char *arg
)
14647 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14648 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14650 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
14651 c
== mips_ases
[i
].option_on
);
14657 case OPTION_CONSTRUCT_FLOATS
:
14658 mips_disable_float_construction
= 0;
14661 case OPTION_NO_CONSTRUCT_FLOATS
:
14662 mips_disable_float_construction
= 1;
14674 target_big_endian
= 1;
14678 target_big_endian
= 0;
14684 else if (arg
[0] == '0')
14686 else if (arg
[0] == '1')
14696 mips_debug
= atoi (arg
);
14700 file_mips_isa
= ISA_MIPS1
;
14704 file_mips_isa
= ISA_MIPS2
;
14708 file_mips_isa
= ISA_MIPS3
;
14712 file_mips_isa
= ISA_MIPS4
;
14716 file_mips_isa
= ISA_MIPS5
;
14719 case OPTION_MIPS32
:
14720 file_mips_isa
= ISA_MIPS32
;
14723 case OPTION_MIPS32R2
:
14724 file_mips_isa
= ISA_MIPS32R2
;
14727 case OPTION_MIPS64R2
:
14728 file_mips_isa
= ISA_MIPS64R2
;
14731 case OPTION_MIPS64
:
14732 file_mips_isa
= ISA_MIPS64
;
14736 mips_set_option_string (&mips_tune_string
, arg
);
14740 mips_set_option_string (&mips_arch_string
, arg
);
14744 mips_set_option_string (&mips_arch_string
, "4650");
14745 mips_set_option_string (&mips_tune_string
, "4650");
14748 case OPTION_NO_M4650
:
14752 mips_set_option_string (&mips_arch_string
, "4010");
14753 mips_set_option_string (&mips_tune_string
, "4010");
14756 case OPTION_NO_M4010
:
14760 mips_set_option_string (&mips_arch_string
, "4100");
14761 mips_set_option_string (&mips_tune_string
, "4100");
14764 case OPTION_NO_M4100
:
14768 mips_set_option_string (&mips_arch_string
, "3900");
14769 mips_set_option_string (&mips_tune_string
, "3900");
14772 case OPTION_NO_M3900
:
14775 case OPTION_MICROMIPS
:
14776 if (mips_opts
.mips16
== 1)
14778 as_bad (_("-mmicromips cannot be used with -mips16"));
14781 mips_opts
.micromips
= 1;
14782 mips_no_prev_insn ();
14785 case OPTION_NO_MICROMIPS
:
14786 mips_opts
.micromips
= 0;
14787 mips_no_prev_insn ();
14790 case OPTION_MIPS16
:
14791 if (mips_opts
.micromips
== 1)
14793 as_bad (_("-mips16 cannot be used with -micromips"));
14796 mips_opts
.mips16
= 1;
14797 mips_no_prev_insn ();
14800 case OPTION_NO_MIPS16
:
14801 mips_opts
.mips16
= 0;
14802 mips_no_prev_insn ();
14805 case OPTION_FIX_24K
:
14809 case OPTION_NO_FIX_24K
:
14813 case OPTION_FIX_LOONGSON2F_JUMP
:
14814 mips_fix_loongson2f_jump
= TRUE
;
14817 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14818 mips_fix_loongson2f_jump
= FALSE
;
14821 case OPTION_FIX_LOONGSON2F_NOP
:
14822 mips_fix_loongson2f_nop
= TRUE
;
14825 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14826 mips_fix_loongson2f_nop
= FALSE
;
14829 case OPTION_FIX_VR4120
:
14830 mips_fix_vr4120
= 1;
14833 case OPTION_NO_FIX_VR4120
:
14834 mips_fix_vr4120
= 0;
14837 case OPTION_FIX_VR4130
:
14838 mips_fix_vr4130
= 1;
14841 case OPTION_NO_FIX_VR4130
:
14842 mips_fix_vr4130
= 0;
14845 case OPTION_FIX_CN63XXP1
:
14846 mips_fix_cn63xxp1
= TRUE
;
14849 case OPTION_NO_FIX_CN63XXP1
:
14850 mips_fix_cn63xxp1
= FALSE
;
14853 case OPTION_RELAX_BRANCH
:
14854 mips_relax_branch
= 1;
14857 case OPTION_NO_RELAX_BRANCH
:
14858 mips_relax_branch
= 0;
14861 case OPTION_INSN32
:
14862 mips_opts
.insn32
= TRUE
;
14865 case OPTION_NO_INSN32
:
14866 mips_opts
.insn32
= FALSE
;
14869 case OPTION_MSHARED
:
14870 mips_in_shared
= TRUE
;
14873 case OPTION_MNO_SHARED
:
14874 mips_in_shared
= FALSE
;
14877 case OPTION_MSYM32
:
14878 mips_opts
.sym32
= TRUE
;
14881 case OPTION_MNO_SYM32
:
14882 mips_opts
.sym32
= FALSE
;
14885 /* When generating ELF code, we permit -KPIC and -call_shared to
14886 select SVR4_PIC, and -non_shared to select no PIC. This is
14887 intended to be compatible with Irix 5. */
14888 case OPTION_CALL_SHARED
:
14889 mips_pic
= SVR4_PIC
;
14890 mips_abicalls
= TRUE
;
14893 case OPTION_CALL_NONPIC
:
14895 mips_abicalls
= TRUE
;
14898 case OPTION_NON_SHARED
:
14900 mips_abicalls
= FALSE
;
14903 /* The -xgot option tells the assembler to use 32 bit offsets
14904 when accessing the got in SVR4_PIC mode. It is for Irix
14911 g_switch_value
= atoi (arg
);
14915 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14918 mips_abi
= O32_ABI
;
14922 mips_abi
= N32_ABI
;
14926 mips_abi
= N64_ABI
;
14927 if (!support_64bit_objects())
14928 as_fatal (_("No compiled in support for 64 bit object file format"));
14932 file_mips_gp32
= 1;
14936 file_mips_gp32
= 0;
14940 file_mips_fp32
= 1;
14944 file_mips_fp32
= 0;
14947 case OPTION_SINGLE_FLOAT
:
14948 file_mips_single_float
= 1;
14951 case OPTION_DOUBLE_FLOAT
:
14952 file_mips_single_float
= 0;
14955 case OPTION_SOFT_FLOAT
:
14956 file_mips_soft_float
= 1;
14959 case OPTION_HARD_FLOAT
:
14960 file_mips_soft_float
= 0;
14964 if (strcmp (arg
, "32") == 0)
14965 mips_abi
= O32_ABI
;
14966 else if (strcmp (arg
, "o64") == 0)
14967 mips_abi
= O64_ABI
;
14968 else if (strcmp (arg
, "n32") == 0)
14969 mips_abi
= N32_ABI
;
14970 else if (strcmp (arg
, "64") == 0)
14972 mips_abi
= N64_ABI
;
14973 if (! support_64bit_objects())
14974 as_fatal (_("No compiled in support for 64 bit object file "
14977 else if (strcmp (arg
, "eabi") == 0)
14978 mips_abi
= EABI_ABI
;
14981 as_fatal (_("invalid abi -mabi=%s"), arg
);
14986 case OPTION_M7000_HILO_FIX
:
14987 mips_7000_hilo_fix
= TRUE
;
14990 case OPTION_MNO_7000_HILO_FIX
:
14991 mips_7000_hilo_fix
= FALSE
;
14994 case OPTION_MDEBUG
:
14995 mips_flag_mdebug
= TRUE
;
14998 case OPTION_NO_MDEBUG
:
14999 mips_flag_mdebug
= FALSE
;
15003 mips_flag_pdr
= TRUE
;
15006 case OPTION_NO_PDR
:
15007 mips_flag_pdr
= FALSE
;
15010 case OPTION_MVXWORKS_PIC
:
15011 mips_pic
= VXWORKS_PIC
;
15015 if (strcmp (arg
, "2008") == 0)
15016 mips_flag_nan2008
= TRUE
;
15017 else if (strcmp (arg
, "legacy") == 0)
15018 mips_flag_nan2008
= FALSE
;
15021 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
15030 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15035 /* Set up globals to generate code for the ISA or processor
15036 described by INFO. */
15039 mips_set_architecture (const struct mips_cpu_info
*info
)
15043 file_mips_arch
= info
->cpu
;
15044 mips_opts
.arch
= info
->cpu
;
15045 mips_opts
.isa
= info
->isa
;
15050 /* Likewise for tuning. */
15053 mips_set_tune (const struct mips_cpu_info
*info
)
15056 mips_tune
= info
->cpu
;
15061 mips_after_parse_args (void)
15063 const struct mips_cpu_info
*arch_info
= 0;
15064 const struct mips_cpu_info
*tune_info
= 0;
15066 /* GP relative stuff not working for PE */
15067 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15069 if (g_switch_seen
&& g_switch_value
!= 0)
15070 as_bad (_("-G not supported in this configuration."));
15071 g_switch_value
= 0;
15074 if (mips_abi
== NO_ABI
)
15075 mips_abi
= MIPS_DEFAULT_ABI
;
15077 /* The following code determines the architecture and register size.
15078 Similar code was added to GCC 3.3 (see override_options() in
15079 config/mips/mips.c). The GAS and GCC code should be kept in sync
15080 as much as possible. */
15082 if (mips_arch_string
!= 0)
15083 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15085 if (file_mips_isa
!= ISA_UNKNOWN
)
15087 /* Handle -mipsN. At this point, file_mips_isa contains the
15088 ISA level specified by -mipsN, while arch_info->isa contains
15089 the -march selection (if any). */
15090 if (arch_info
!= 0)
15092 /* -march takes precedence over -mipsN, since it is more descriptive.
15093 There's no harm in specifying both as long as the ISA levels
15095 if (file_mips_isa
!= arch_info
->isa
)
15096 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15097 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15098 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15101 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15104 if (arch_info
== 0)
15106 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15107 gas_assert (arch_info
);
15110 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15111 as_bad (_("-march=%s is not compatible with the selected ABI"),
15114 mips_set_architecture (arch_info
);
15116 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15117 if (mips_tune_string
!= 0)
15118 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15120 if (tune_info
== 0)
15121 mips_set_tune (arch_info
);
15123 mips_set_tune (tune_info
);
15125 if (file_mips_gp32
>= 0)
15127 /* The user specified the size of the integer registers. Make sure
15128 it agrees with the ABI and ISA. */
15129 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15130 as_bad (_("-mgp64 used with a 32-bit processor"));
15131 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15132 as_bad (_("-mgp32 used with a 64-bit ABI"));
15133 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15134 as_bad (_("-mgp64 used with a 32-bit ABI"));
15138 /* Infer the integer register size from the ABI and processor.
15139 Restrict ourselves to 32-bit registers if that's all the
15140 processor has, or if the ABI cannot handle 64-bit registers. */
15141 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15142 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15145 switch (file_mips_fp32
)
15149 /* No user specified float register size.
15150 ??? GAS treats single-float processors as though they had 64-bit
15151 float registers (although it complains when double-precision
15152 instructions are used). As things stand, saying they have 32-bit
15153 registers would lead to spurious "register must be even" messages.
15154 So here we assume float registers are never smaller than the
15156 if (file_mips_gp32
== 0)
15157 /* 64-bit integer registers implies 64-bit float registers. */
15158 file_mips_fp32
= 0;
15159 else if ((mips_opts
.ase
& FP64_ASES
)
15160 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15161 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15162 file_mips_fp32
= 0;
15164 /* 32-bit float registers. */
15165 file_mips_fp32
= 1;
15168 /* The user specified the size of the float registers. Check if it
15169 agrees with the ABI and ISA. */
15171 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15172 as_bad (_("-mfp64 used with a 32-bit fpu"));
15173 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15174 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15175 as_warn (_("-mfp64 used with a 32-bit ABI"));
15178 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15179 as_warn (_("-mfp32 used with a 64-bit ABI"));
15183 /* End of GCC-shared inference code. */
15185 /* This flag is set when we have a 64-bit capable CPU but use only
15186 32-bit wide registers. Note that EABI does not use it. */
15187 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15188 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15189 || mips_abi
== O32_ABI
))
15190 mips_32bitmode
= 1;
15192 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15193 as_bad (_("trap exception not supported at ISA 1"));
15195 /* If the selected architecture includes support for ASEs, enable
15196 generation of code for them. */
15197 if (mips_opts
.mips16
== -1)
15198 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15199 if (mips_opts
.micromips
== -1)
15200 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15202 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15203 ASEs from being selected implicitly. */
15204 if (file_mips_fp32
== 1)
15205 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
15207 /* If the user didn't explicitly select or deselect a particular ASE,
15208 use the default setting for the CPU. */
15209 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
15211 file_mips_isa
= mips_opts
.isa
;
15212 file_ase
= mips_opts
.ase
;
15213 mips_opts
.gp32
= file_mips_gp32
;
15214 mips_opts
.fp32
= file_mips_fp32
;
15215 mips_opts
.soft_float
= file_mips_soft_float
;
15216 mips_opts
.single_float
= file_mips_single_float
;
15218 mips_check_isa_supports_ases ();
15220 if (mips_flag_mdebug
< 0)
15221 mips_flag_mdebug
= 0;
15225 mips_init_after_args (void)
15227 /* initialize opcodes */
15228 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15229 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15233 md_pcrel_from (fixS
*fixP
)
15235 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15236 switch (fixP
->fx_r_type
)
15238 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15239 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15240 /* Return the address of the delay slot. */
15243 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15244 case BFD_RELOC_MICROMIPS_JMP
:
15245 case BFD_RELOC_16_PCREL_S2
:
15246 case BFD_RELOC_MIPS_JMP
:
15247 /* Return the address of the delay slot. */
15250 case BFD_RELOC_32_PCREL
:
15254 /* We have no relocation type for PC relative MIPS16 instructions. */
15255 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15257 _("PC relative MIPS16 instruction references a different section"));
15262 /* This is called before the symbol table is processed. In order to
15263 work with gcc when using mips-tfile, we must keep all local labels.
15264 However, in other cases, we want to discard them. If we were
15265 called with -g, but we didn't see any debugging information, it may
15266 mean that gcc is smuggling debugging information through to
15267 mips-tfile, in which case we must generate all local labels. */
15270 mips_frob_file_before_adjust (void)
15272 #ifndef NO_ECOFF_DEBUGGING
15273 if (ECOFF_DEBUGGING
15275 && ! ecoff_debugging_seen
)
15276 flag_keep_locals
= 1;
15280 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15281 the corresponding LO16 reloc. This is called before md_apply_fix and
15282 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15283 relocation operators.
15285 For our purposes, a %lo() expression matches a %got() or %hi()
15288 (a) it refers to the same symbol; and
15289 (b) the offset applied in the %lo() expression is no lower than
15290 the offset applied in the %got() or %hi().
15292 (b) allows us to cope with code like:
15295 lh $4,%lo(foo+2)($4)
15297 ...which is legal on RELA targets, and has a well-defined behaviour
15298 if the user knows that adding 2 to "foo" will not induce a carry to
15301 When several %lo()s match a particular %got() or %hi(), we use the
15302 following rules to distinguish them:
15304 (1) %lo()s with smaller offsets are a better match than %lo()s with
15307 (2) %lo()s with no matching %got() or %hi() are better than those
15308 that already have a matching %got() or %hi().
15310 (3) later %lo()s are better than earlier %lo()s.
15312 These rules are applied in order.
15314 (1) means, among other things, that %lo()s with identical offsets are
15315 chosen if they exist.
15317 (2) means that we won't associate several high-part relocations with
15318 the same low-part relocation unless there's no alternative. Having
15319 several high parts for the same low part is a GNU extension; this rule
15320 allows careful users to avoid it.
15322 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15323 with the last high-part relocation being at the front of the list.
15324 It therefore makes sense to choose the last matching low-part
15325 relocation, all other things being equal. It's also easier
15326 to code that way. */
15329 mips_frob_file (void)
15331 struct mips_hi_fixup
*l
;
15332 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15334 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15336 segment_info_type
*seginfo
;
15337 bfd_boolean matched_lo_p
;
15338 fixS
**hi_pos
, **lo_pos
, **pos
;
15340 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15342 /* If a GOT16 relocation turns out to be against a global symbol,
15343 there isn't supposed to be a matching LO. Ignore %gots against
15344 constants; we'll report an error for those later. */
15345 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15346 && !(l
->fixp
->fx_addsy
15347 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15350 /* Check quickly whether the next fixup happens to be a matching %lo. */
15351 if (fixup_has_matching_lo_p (l
->fixp
))
15354 seginfo
= seg_info (l
->seg
);
15356 /* Set HI_POS to the position of this relocation in the chain.
15357 Set LO_POS to the position of the chosen low-part relocation.
15358 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15359 relocation that matches an immediately-preceding high-part
15363 matched_lo_p
= FALSE
;
15364 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15366 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15368 if (*pos
== l
->fixp
)
15371 if ((*pos
)->fx_r_type
== looking_for_rtype
15372 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15373 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15375 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15377 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15380 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15381 && fixup_has_matching_lo_p (*pos
));
15384 /* If we found a match, remove the high-part relocation from its
15385 current position and insert it before the low-part relocation.
15386 Make the offsets match so that fixup_has_matching_lo_p()
15389 We don't warn about unmatched high-part relocations since some
15390 versions of gcc have been known to emit dead "lui ...%hi(...)"
15392 if (lo_pos
!= NULL
)
15394 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15395 if (l
->fixp
->fx_next
!= *lo_pos
)
15397 *hi_pos
= l
->fixp
->fx_next
;
15398 l
->fixp
->fx_next
= *lo_pos
;
15406 mips_force_relocation (fixS
*fixp
)
15408 if (generic_force_reloc (fixp
))
15411 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15412 so that the linker relaxation can update targets. */
15413 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15414 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15415 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15421 /* Read the instruction associated with RELOC from BUF. */
15423 static unsigned int
15424 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15426 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15427 return read_compressed_insn (buf
, 4);
15429 return read_insn (buf
);
15432 /* Write instruction INSN to BUF, given that it has been relocated
15436 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15437 unsigned long insn
)
15439 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15440 write_compressed_insn (buf
, insn
, 4);
15442 write_insn (buf
, insn
);
15445 /* Apply a fixup to the object file. */
15448 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15451 unsigned long insn
;
15452 reloc_howto_type
*howto
;
15454 /* We ignore generic BFD relocations we don't know about. */
15455 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15459 gas_assert (fixP
->fx_size
== 2
15460 || fixP
->fx_size
== 4
15461 || fixP
->fx_r_type
== BFD_RELOC_16
15462 || fixP
->fx_r_type
== BFD_RELOC_64
15463 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15464 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15465 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15466 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15467 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15468 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15470 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15472 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15473 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15474 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15475 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15476 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15478 /* Don't treat parts of a composite relocation as done. There are two
15481 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15482 should nevertheless be emitted if the first part is.
15484 (2) In normal usage, composite relocations are never assembly-time
15485 constants. The easiest way of dealing with the pathological
15486 exceptions is to generate a relocation against STN_UNDEF and
15487 leave everything up to the linker. */
15488 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15491 switch (fixP
->fx_r_type
)
15493 case BFD_RELOC_MIPS_TLS_GD
:
15494 case BFD_RELOC_MIPS_TLS_LDM
:
15495 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15496 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15497 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15498 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15499 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15500 case BFD_RELOC_MIPS_TLS_TPREL32
:
15501 case BFD_RELOC_MIPS_TLS_TPREL64
:
15502 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15503 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15504 case BFD_RELOC_MICROMIPS_TLS_GD
:
15505 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15506 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15507 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15508 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15509 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15510 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15511 case BFD_RELOC_MIPS16_TLS_GD
:
15512 case BFD_RELOC_MIPS16_TLS_LDM
:
15513 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15514 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15515 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15516 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15517 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15518 if (!fixP
->fx_addsy
)
15520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15521 _("TLS relocation against a constant"));
15524 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15527 case BFD_RELOC_MIPS_JMP
:
15528 case BFD_RELOC_MIPS_SHIFT5
:
15529 case BFD_RELOC_MIPS_SHIFT6
:
15530 case BFD_RELOC_MIPS_GOT_DISP
:
15531 case BFD_RELOC_MIPS_GOT_PAGE
:
15532 case BFD_RELOC_MIPS_GOT_OFST
:
15533 case BFD_RELOC_MIPS_SUB
:
15534 case BFD_RELOC_MIPS_INSERT_A
:
15535 case BFD_RELOC_MIPS_INSERT_B
:
15536 case BFD_RELOC_MIPS_DELETE
:
15537 case BFD_RELOC_MIPS_HIGHEST
:
15538 case BFD_RELOC_MIPS_HIGHER
:
15539 case BFD_RELOC_MIPS_SCN_DISP
:
15540 case BFD_RELOC_MIPS_REL16
:
15541 case BFD_RELOC_MIPS_RELGOT
:
15542 case BFD_RELOC_MIPS_JALR
:
15543 case BFD_RELOC_HI16
:
15544 case BFD_RELOC_HI16_S
:
15545 case BFD_RELOC_LO16
:
15546 case BFD_RELOC_GPREL16
:
15547 case BFD_RELOC_MIPS_LITERAL
:
15548 case BFD_RELOC_MIPS_CALL16
:
15549 case BFD_RELOC_MIPS_GOT16
:
15550 case BFD_RELOC_GPREL32
:
15551 case BFD_RELOC_MIPS_GOT_HI16
:
15552 case BFD_RELOC_MIPS_GOT_LO16
:
15553 case BFD_RELOC_MIPS_CALL_HI16
:
15554 case BFD_RELOC_MIPS_CALL_LO16
:
15555 case BFD_RELOC_MIPS16_GPREL
:
15556 case BFD_RELOC_MIPS16_GOT16
:
15557 case BFD_RELOC_MIPS16_CALL16
:
15558 case BFD_RELOC_MIPS16_HI16
:
15559 case BFD_RELOC_MIPS16_HI16_S
:
15560 case BFD_RELOC_MIPS16_LO16
:
15561 case BFD_RELOC_MIPS16_JMP
:
15562 case BFD_RELOC_MICROMIPS_JMP
:
15563 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15564 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15565 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15566 case BFD_RELOC_MICROMIPS_SUB
:
15567 case BFD_RELOC_MICROMIPS_HIGHEST
:
15568 case BFD_RELOC_MICROMIPS_HIGHER
:
15569 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15570 case BFD_RELOC_MICROMIPS_JALR
:
15571 case BFD_RELOC_MICROMIPS_HI16
:
15572 case BFD_RELOC_MICROMIPS_HI16_S
:
15573 case BFD_RELOC_MICROMIPS_LO16
:
15574 case BFD_RELOC_MICROMIPS_GPREL16
:
15575 case BFD_RELOC_MICROMIPS_LITERAL
:
15576 case BFD_RELOC_MICROMIPS_CALL16
:
15577 case BFD_RELOC_MICROMIPS_GOT16
:
15578 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15579 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15580 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15581 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15582 case BFD_RELOC_MIPS_EH
:
15587 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15589 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15590 if (mips16_reloc_p (fixP
->fx_r_type
))
15591 insn
|= mips16_immed_extend (value
, 16);
15593 insn
|= (value
& 0xffff);
15594 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15598 _("Unsupported constant in relocation"));
15603 /* This is handled like BFD_RELOC_32, but we output a sign
15604 extended value if we are only 32 bits. */
15607 if (8 <= sizeof (valueT
))
15608 md_number_to_chars (buf
, *valP
, 8);
15613 if ((*valP
& 0x80000000) != 0)
15617 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15618 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15623 case BFD_RELOC_RVA
:
15625 case BFD_RELOC_32_PCREL
:
15627 /* If we are deleting this reloc entry, we must fill in the
15628 value now. This can happen if we have a .word which is not
15629 resolved when it appears but is later defined. */
15631 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15634 case BFD_RELOC_16_PCREL_S2
:
15635 if ((*valP
& 0x3) != 0)
15636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15637 _("Branch to misaligned address (%lx)"), (long) *valP
);
15639 /* We need to save the bits in the instruction since fixup_segment()
15640 might be deleting the relocation entry (i.e., a branch within
15641 the current segment). */
15642 if (! fixP
->fx_done
)
15645 /* Update old instruction data. */
15646 insn
= read_insn (buf
);
15648 if (*valP
+ 0x20000 <= 0x3ffff)
15650 insn
|= (*valP
>> 2) & 0xffff;
15651 write_insn (buf
, insn
);
15653 else if (mips_pic
== NO_PIC
15655 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15656 && (fixP
->fx_frag
->fr_address
15657 < text_section
->vma
+ bfd_get_section_size (text_section
))
15658 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15659 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15660 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15662 /* The branch offset is too large. If this is an
15663 unconditional branch, and we are not generating PIC code,
15664 we can convert it to an absolute jump instruction. */
15665 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15666 insn
= 0x0c000000; /* jal */
15668 insn
= 0x08000000; /* j */
15669 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15671 fixP
->fx_addsy
= section_symbol (text_section
);
15672 *valP
+= md_pcrel_from (fixP
);
15673 write_insn (buf
, insn
);
15677 /* If we got here, we have branch-relaxation disabled,
15678 and there's nothing we can do to fix this instruction
15679 without turning it into a longer sequence. */
15680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15681 _("Branch out of range"));
15685 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15686 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15687 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15688 /* We adjust the offset back to even. */
15689 if ((*valP
& 0x1) != 0)
15692 if (! fixP
->fx_done
)
15695 /* Should never visit here, because we keep the relocation. */
15699 case BFD_RELOC_VTABLE_INHERIT
:
15702 && !S_IS_DEFINED (fixP
->fx_addsy
)
15703 && !S_IS_WEAK (fixP
->fx_addsy
))
15704 S_SET_WEAK (fixP
->fx_addsy
);
15707 case BFD_RELOC_VTABLE_ENTRY
:
15715 /* Remember value for tc_gen_reloc. */
15716 fixP
->fx_addnumber
= *valP
;
15726 name
= input_line_pointer
;
15727 c
= get_symbol_end ();
15728 p
= (symbolS
*) symbol_find_or_make (name
);
15729 *input_line_pointer
= c
;
15733 /* Align the current frag to a given power of two. If a particular
15734 fill byte should be used, FILL points to an integer that contains
15735 that byte, otherwise FILL is null.
15737 This function used to have the comment:
15739 The MIPS assembler also automatically adjusts any preceding label.
15741 The implementation therefore applied the adjustment to a maximum of
15742 one label. However, other label adjustments are applied to batches
15743 of labels, and adjusting just one caused problems when new labels
15744 were added for the sake of debugging or unwind information.
15745 We therefore adjust all preceding labels (given as LABELS) instead. */
15748 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15750 mips_emit_delays ();
15751 mips_record_compressed_mode ();
15752 if (fill
== NULL
&& subseg_text_p (now_seg
))
15753 frag_align_code (to
, 0);
15755 frag_align (to
, fill
? *fill
: 0, 0);
15756 record_alignment (now_seg
, to
);
15757 mips_move_labels (labels
, FALSE
);
15760 /* Align to a given power of two. .align 0 turns off the automatic
15761 alignment used by the data creating pseudo-ops. */
15764 s_align (int x ATTRIBUTE_UNUSED
)
15766 int temp
, fill_value
, *fill_ptr
;
15767 long max_alignment
= 28;
15769 /* o Note that the assembler pulls down any immediately preceding label
15770 to the aligned address.
15771 o It's not documented but auto alignment is reinstated by
15772 a .align pseudo instruction.
15773 o Note also that after auto alignment is turned off the mips assembler
15774 issues an error on attempt to assemble an improperly aligned data item.
15777 temp
= get_absolute_expression ();
15778 if (temp
> max_alignment
)
15779 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15782 as_warn (_("Alignment negative: 0 assumed."));
15785 if (*input_line_pointer
== ',')
15787 ++input_line_pointer
;
15788 fill_value
= get_absolute_expression ();
15789 fill_ptr
= &fill_value
;
15795 segment_info_type
*si
= seg_info (now_seg
);
15796 struct insn_label_list
*l
= si
->label_list
;
15797 /* Auto alignment should be switched on by next section change. */
15799 mips_align (temp
, fill_ptr
, l
);
15806 demand_empty_rest_of_line ();
15810 s_change_sec (int sec
)
15814 /* The ELF backend needs to know that we are changing sections, so
15815 that .previous works correctly. We could do something like check
15816 for an obj_section_change_hook macro, but that might be confusing
15817 as it would not be appropriate to use it in the section changing
15818 functions in read.c, since obj-elf.c intercepts those. FIXME:
15819 This should be cleaner, somehow. */
15820 obj_elf_section_change_hook ();
15822 mips_emit_delays ();
15833 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15834 demand_empty_rest_of_line ();
15838 seg
= subseg_new (RDATA_SECTION_NAME
,
15839 (subsegT
) get_absolute_expression ());
15840 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15841 | SEC_READONLY
| SEC_RELOC
15843 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15844 record_alignment (seg
, 4);
15845 demand_empty_rest_of_line ();
15849 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15850 bfd_set_section_flags (stdoutput
, seg
,
15851 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15852 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15853 record_alignment (seg
, 4);
15854 demand_empty_rest_of_line ();
15858 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15859 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15860 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15861 record_alignment (seg
, 4);
15862 demand_empty_rest_of_line ();
15870 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15872 char *section_name
;
15877 int section_entry_size
;
15878 int section_alignment
;
15880 section_name
= input_line_pointer
;
15881 c
= get_symbol_end ();
15883 next_c
= *(input_line_pointer
+ 1);
15885 /* Do we have .section Name<,"flags">? */
15886 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15888 /* just after name is now '\0'. */
15889 *input_line_pointer
= c
;
15890 input_line_pointer
= section_name
;
15891 obj_elf_section (ignore
);
15894 input_line_pointer
++;
15896 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15898 section_type
= get_absolute_expression ();
15901 if (*input_line_pointer
++ == ',')
15902 section_flag
= get_absolute_expression ();
15905 if (*input_line_pointer
++ == ',')
15906 section_entry_size
= get_absolute_expression ();
15908 section_entry_size
= 0;
15909 if (*input_line_pointer
++ == ',')
15910 section_alignment
= get_absolute_expression ();
15912 section_alignment
= 0;
15913 /* FIXME: really ignore? */
15914 (void) section_alignment
;
15916 section_name
= xstrdup (section_name
);
15918 /* When using the generic form of .section (as implemented by obj-elf.c),
15919 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15920 traditionally had to fall back on the more common @progbits instead.
15922 There's nothing really harmful in this, since bfd will correct
15923 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15924 means that, for backwards compatibility, the special_section entries
15925 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15927 Even so, we shouldn't force users of the MIPS .section syntax to
15928 incorrectly label the sections as SHT_PROGBITS. The best compromise
15929 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15930 generic type-checking code. */
15931 if (section_type
== SHT_MIPS_DWARF
)
15932 section_type
= SHT_PROGBITS
;
15934 obj_elf_change_section (section_name
, section_type
, section_flag
,
15935 section_entry_size
, 0, 0, 0);
15937 if (now_seg
->name
!= section_name
)
15938 free (section_name
);
15942 mips_enable_auto_align (void)
15948 s_cons (int log_size
)
15950 segment_info_type
*si
= seg_info (now_seg
);
15951 struct insn_label_list
*l
= si
->label_list
;
15953 mips_emit_delays ();
15954 if (log_size
> 0 && auto_align
)
15955 mips_align (log_size
, 0, l
);
15956 cons (1 << log_size
);
15957 mips_clear_insn_labels ();
15961 s_float_cons (int type
)
15963 segment_info_type
*si
= seg_info (now_seg
);
15964 struct insn_label_list
*l
= si
->label_list
;
15966 mips_emit_delays ();
15971 mips_align (3, 0, l
);
15973 mips_align (2, 0, l
);
15977 mips_clear_insn_labels ();
15980 /* Handle .globl. We need to override it because on Irix 5 you are
15983 where foo is an undefined symbol, to mean that foo should be
15984 considered to be the address of a function. */
15987 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15996 name
= input_line_pointer
;
15997 c
= get_symbol_end ();
15998 symbolP
= symbol_find_or_make (name
);
15999 S_SET_EXTERNAL (symbolP
);
16001 *input_line_pointer
= c
;
16002 SKIP_WHITESPACE ();
16004 /* On Irix 5, every global symbol that is not explicitly labelled as
16005 being a function is apparently labelled as being an object. */
16008 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16009 && (*input_line_pointer
!= ','))
16014 secname
= input_line_pointer
;
16015 c
= get_symbol_end ();
16016 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16018 as_bad (_("%s: no such section"), secname
);
16019 *input_line_pointer
= c
;
16021 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16022 flag
= BSF_FUNCTION
;
16025 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16027 c
= *input_line_pointer
;
16030 input_line_pointer
++;
16031 SKIP_WHITESPACE ();
16032 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16038 demand_empty_rest_of_line ();
16042 s_option (int x ATTRIBUTE_UNUSED
)
16047 opt
= input_line_pointer
;
16048 c
= get_symbol_end ();
16052 /* FIXME: What does this mean? */
16054 else if (strncmp (opt
, "pic", 3) == 0)
16058 i
= atoi (opt
+ 3);
16063 mips_pic
= SVR4_PIC
;
16064 mips_abicalls
= TRUE
;
16067 as_bad (_(".option pic%d not supported"), i
);
16069 if (mips_pic
== SVR4_PIC
)
16071 if (g_switch_seen
&& g_switch_value
!= 0)
16072 as_warn (_("-G may not be used with SVR4 PIC code"));
16073 g_switch_value
= 0;
16074 bfd_set_gp_size (stdoutput
, 0);
16078 as_warn (_("Unrecognized option \"%s\""), opt
);
16080 *input_line_pointer
= c
;
16081 demand_empty_rest_of_line ();
16084 /* This structure is used to hold a stack of .set values. */
16086 struct mips_option_stack
16088 struct mips_option_stack
*next
;
16089 struct mips_set_options options
;
16092 static struct mips_option_stack
*mips_opts_stack
;
16094 /* Handle the .set pseudo-op. */
16097 s_mipsset (int x ATTRIBUTE_UNUSED
)
16099 char *name
= input_line_pointer
, ch
;
16100 const struct mips_ase
*ase
;
16102 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16103 ++input_line_pointer
;
16104 ch
= *input_line_pointer
;
16105 *input_line_pointer
= '\0';
16107 if (strcmp (name
, "reorder") == 0)
16109 if (mips_opts
.noreorder
)
16112 else if (strcmp (name
, "noreorder") == 0)
16114 if (!mips_opts
.noreorder
)
16115 start_noreorder ();
16117 else if (strncmp (name
, "at=", 3) == 0)
16119 char *s
= name
+ 3;
16121 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16122 as_bad (_("Unrecognized register name `%s'"), s
);
16124 else if (strcmp (name
, "at") == 0)
16126 mips_opts
.at
= ATREG
;
16128 else if (strcmp (name
, "noat") == 0)
16130 mips_opts
.at
= ZERO
;
16132 else if (strcmp (name
, "macro") == 0)
16134 mips_opts
.warn_about_macros
= 0;
16136 else if (strcmp (name
, "nomacro") == 0)
16138 if (mips_opts
.noreorder
== 0)
16139 as_bad (_("`noreorder' must be set before `nomacro'"));
16140 mips_opts
.warn_about_macros
= 1;
16142 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16144 mips_opts
.nomove
= 0;
16146 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16148 mips_opts
.nomove
= 1;
16150 else if (strcmp (name
, "bopt") == 0)
16152 mips_opts
.nobopt
= 0;
16154 else if (strcmp (name
, "nobopt") == 0)
16156 mips_opts
.nobopt
= 1;
16158 else if (strcmp (name
, "gp=default") == 0)
16159 mips_opts
.gp32
= file_mips_gp32
;
16160 else if (strcmp (name
, "gp=32") == 0)
16161 mips_opts
.gp32
= 1;
16162 else if (strcmp (name
, "gp=64") == 0)
16164 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16165 as_warn (_("%s isa does not support 64-bit registers"),
16166 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16167 mips_opts
.gp32
= 0;
16169 else if (strcmp (name
, "fp=default") == 0)
16170 mips_opts
.fp32
= file_mips_fp32
;
16171 else if (strcmp (name
, "fp=32") == 0)
16172 mips_opts
.fp32
= 1;
16173 else if (strcmp (name
, "fp=64") == 0)
16175 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16176 as_warn (_("%s isa does not support 64-bit floating point registers"),
16177 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16178 mips_opts
.fp32
= 0;
16180 else if (strcmp (name
, "softfloat") == 0)
16181 mips_opts
.soft_float
= 1;
16182 else if (strcmp (name
, "hardfloat") == 0)
16183 mips_opts
.soft_float
= 0;
16184 else if (strcmp (name
, "singlefloat") == 0)
16185 mips_opts
.single_float
= 1;
16186 else if (strcmp (name
, "doublefloat") == 0)
16187 mips_opts
.single_float
= 0;
16188 else if (strcmp (name
, "mips16") == 0
16189 || strcmp (name
, "MIPS-16") == 0)
16191 if (mips_opts
.micromips
== 1)
16192 as_fatal (_("`mips16' cannot be used with `micromips'"));
16193 mips_opts
.mips16
= 1;
16195 else if (strcmp (name
, "nomips16") == 0
16196 || strcmp (name
, "noMIPS-16") == 0)
16197 mips_opts
.mips16
= 0;
16198 else if (strcmp (name
, "micromips") == 0)
16200 if (mips_opts
.mips16
== 1)
16201 as_fatal (_("`micromips' cannot be used with `mips16'"));
16202 mips_opts
.micromips
= 1;
16204 else if (strcmp (name
, "nomicromips") == 0)
16205 mips_opts
.micromips
= 0;
16206 else if (name
[0] == 'n'
16208 && (ase
= mips_lookup_ase (name
+ 2)))
16209 mips_set_ase (ase
, FALSE
);
16210 else if ((ase
= mips_lookup_ase (name
)))
16211 mips_set_ase (ase
, TRUE
);
16212 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16216 /* Permit the user to change the ISA and architecture on the fly.
16217 Needless to say, misuse can cause serious problems. */
16218 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16221 mips_opts
.isa
= file_mips_isa
;
16222 mips_opts
.arch
= file_mips_arch
;
16224 else if (strncmp (name
, "arch=", 5) == 0)
16226 const struct mips_cpu_info
*p
;
16228 p
= mips_parse_cpu("internal use", name
+ 5);
16230 as_bad (_("unknown architecture %s"), name
+ 5);
16233 mips_opts
.arch
= p
->cpu
;
16234 mips_opts
.isa
= p
->isa
;
16237 else if (strncmp (name
, "mips", 4) == 0)
16239 const struct mips_cpu_info
*p
;
16241 p
= mips_parse_cpu("internal use", name
);
16243 as_bad (_("unknown ISA level %s"), name
+ 4);
16246 mips_opts
.arch
= p
->cpu
;
16247 mips_opts
.isa
= p
->isa
;
16251 as_bad (_("unknown ISA or architecture %s"), name
);
16253 switch (mips_opts
.isa
)
16261 mips_opts
.gp32
= 1;
16262 mips_opts
.fp32
= 1;
16269 mips_opts
.gp32
= 0;
16270 if (mips_opts
.arch
== CPU_R5900
)
16272 mips_opts
.fp32
= 1;
16276 mips_opts
.fp32
= 0;
16280 as_bad (_("unknown ISA level %s"), name
+ 4);
16285 mips_opts
.gp32
= file_mips_gp32
;
16286 mips_opts
.fp32
= file_mips_fp32
;
16289 else if (strcmp (name
, "autoextend") == 0)
16290 mips_opts
.noautoextend
= 0;
16291 else if (strcmp (name
, "noautoextend") == 0)
16292 mips_opts
.noautoextend
= 1;
16293 else if (strcmp (name
, "insn32") == 0)
16294 mips_opts
.insn32
= TRUE
;
16295 else if (strcmp (name
, "noinsn32") == 0)
16296 mips_opts
.insn32
= FALSE
;
16297 else if (strcmp (name
, "push") == 0)
16299 struct mips_option_stack
*s
;
16301 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16302 s
->next
= mips_opts_stack
;
16303 s
->options
= mips_opts
;
16304 mips_opts_stack
= s
;
16306 else if (strcmp (name
, "pop") == 0)
16308 struct mips_option_stack
*s
;
16310 s
= mips_opts_stack
;
16312 as_bad (_(".set pop with no .set push"));
16315 /* If we're changing the reorder mode we need to handle
16316 delay slots correctly. */
16317 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16318 start_noreorder ();
16319 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16322 mips_opts
= s
->options
;
16323 mips_opts_stack
= s
->next
;
16327 else if (strcmp (name
, "sym32") == 0)
16328 mips_opts
.sym32
= TRUE
;
16329 else if (strcmp (name
, "nosym32") == 0)
16330 mips_opts
.sym32
= FALSE
;
16331 else if (strchr (name
, ','))
16333 /* Generic ".set" directive; use the generic handler. */
16334 *input_line_pointer
= ch
;
16335 input_line_pointer
= name
;
16341 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16343 mips_check_isa_supports_ases ();
16344 *input_line_pointer
= ch
;
16345 demand_empty_rest_of_line ();
16348 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16349 .option pic2. It means to generate SVR4 PIC calls. */
16352 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16354 mips_pic
= SVR4_PIC
;
16355 mips_abicalls
= TRUE
;
16357 if (g_switch_seen
&& g_switch_value
!= 0)
16358 as_warn (_("-G may not be used with SVR4 PIC code"));
16359 g_switch_value
= 0;
16361 bfd_set_gp_size (stdoutput
, 0);
16362 demand_empty_rest_of_line ();
16365 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16366 PIC code. It sets the $gp register for the function based on the
16367 function address, which is in the register named in the argument.
16368 This uses a relocation against _gp_disp, which is handled specially
16369 by the linker. The result is:
16370 lui $gp,%hi(_gp_disp)
16371 addiu $gp,$gp,%lo(_gp_disp)
16372 addu $gp,$gp,.cpload argument
16373 The .cpload argument is normally $25 == $t9.
16375 The -mno-shared option changes this to:
16376 lui $gp,%hi(__gnu_local_gp)
16377 addiu $gp,$gp,%lo(__gnu_local_gp)
16378 and the argument is ignored. This saves an instruction, but the
16379 resulting code is not position independent; it uses an absolute
16380 address for __gnu_local_gp. Thus code assembled with -mno-shared
16381 can go into an ordinary executable, but not into a shared library. */
16384 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16390 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16391 .cpload is ignored. */
16392 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16398 if (mips_opts
.mips16
)
16400 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16401 ignore_rest_of_line ();
16405 /* .cpload should be in a .set noreorder section. */
16406 if (mips_opts
.noreorder
== 0)
16407 as_warn (_(".cpload not in noreorder section"));
16409 reg
= tc_get_register (0);
16411 /* If we need to produce a 64-bit address, we are better off using
16412 the default instruction sequence. */
16413 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16415 ex
.X_op
= O_symbol
;
16416 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16418 ex
.X_op_symbol
= NULL
;
16419 ex
.X_add_number
= 0;
16421 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16422 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16424 mips_mark_labels ();
16425 mips_assembling_insn
= TRUE
;
16428 macro_build_lui (&ex
, mips_gp_register
);
16429 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16430 mips_gp_register
, BFD_RELOC_LO16
);
16432 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16433 mips_gp_register
, reg
);
16436 mips_assembling_insn
= FALSE
;
16437 demand_empty_rest_of_line ();
16440 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16441 .cpsetup $reg1, offset|$reg2, label
16443 If offset is given, this results in:
16444 sd $gp, offset($sp)
16445 lui $gp, %hi(%neg(%gp_rel(label)))
16446 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16447 daddu $gp, $gp, $reg1
16449 If $reg2 is given, this results in:
16450 daddu $reg2, $gp, $0
16451 lui $gp, %hi(%neg(%gp_rel(label)))
16452 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16453 daddu $gp, $gp, $reg1
16454 $reg1 is normally $25 == $t9.
16456 The -mno-shared option replaces the last three instructions with
16458 addiu $gp,$gp,%lo(_gp) */
16461 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16463 expressionS ex_off
;
16464 expressionS ex_sym
;
16467 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16468 We also need NewABI support. */
16469 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16475 if (mips_opts
.mips16
)
16477 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16478 ignore_rest_of_line ();
16482 reg1
= tc_get_register (0);
16483 SKIP_WHITESPACE ();
16484 if (*input_line_pointer
!= ',')
16486 as_bad (_("missing argument separator ',' for .cpsetup"));
16490 ++input_line_pointer
;
16491 SKIP_WHITESPACE ();
16492 if (*input_line_pointer
== '$')
16494 mips_cpreturn_register
= tc_get_register (0);
16495 mips_cpreturn_offset
= -1;
16499 mips_cpreturn_offset
= get_absolute_expression ();
16500 mips_cpreturn_register
= -1;
16502 SKIP_WHITESPACE ();
16503 if (*input_line_pointer
!= ',')
16505 as_bad (_("missing argument separator ',' for .cpsetup"));
16509 ++input_line_pointer
;
16510 SKIP_WHITESPACE ();
16511 expression (&ex_sym
);
16513 mips_mark_labels ();
16514 mips_assembling_insn
= TRUE
;
16517 if (mips_cpreturn_register
== -1)
16519 ex_off
.X_op
= O_constant
;
16520 ex_off
.X_add_symbol
= NULL
;
16521 ex_off
.X_op_symbol
= NULL
;
16522 ex_off
.X_add_number
= mips_cpreturn_offset
;
16524 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16525 BFD_RELOC_LO16
, SP
);
16528 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16529 mips_gp_register
, 0);
16531 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16533 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16534 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16537 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16538 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16539 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16542 mips_gp_register
, reg1
);
16548 ex
.X_op
= O_symbol
;
16549 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16550 ex
.X_op_symbol
= NULL
;
16551 ex
.X_add_number
= 0;
16553 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16554 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16556 macro_build_lui (&ex
, mips_gp_register
);
16557 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16558 mips_gp_register
, BFD_RELOC_LO16
);
16563 mips_assembling_insn
= FALSE
;
16564 demand_empty_rest_of_line ();
16568 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16570 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16571 .cplocal is ignored. */
16572 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16578 if (mips_opts
.mips16
)
16580 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16581 ignore_rest_of_line ();
16585 mips_gp_register
= tc_get_register (0);
16586 demand_empty_rest_of_line ();
16589 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16590 offset from $sp. The offset is remembered, and after making a PIC
16591 call $gp is restored from that location. */
16594 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16598 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16599 .cprestore is ignored. */
16600 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16606 if (mips_opts
.mips16
)
16608 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16609 ignore_rest_of_line ();
16613 mips_cprestore_offset
= get_absolute_expression ();
16614 mips_cprestore_valid
= 1;
16616 ex
.X_op
= O_constant
;
16617 ex
.X_add_symbol
= NULL
;
16618 ex
.X_op_symbol
= NULL
;
16619 ex
.X_add_number
= mips_cprestore_offset
;
16621 mips_mark_labels ();
16622 mips_assembling_insn
= TRUE
;
16625 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16626 SP
, HAVE_64BIT_ADDRESSES
);
16629 mips_assembling_insn
= FALSE
;
16630 demand_empty_rest_of_line ();
16633 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16634 was given in the preceding .cpsetup, it results in:
16635 ld $gp, offset($sp)
16637 If a register $reg2 was given there, it results in:
16638 daddu $gp, $reg2, $0 */
16641 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16645 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16646 We also need NewABI support. */
16647 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16653 if (mips_opts
.mips16
)
16655 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16656 ignore_rest_of_line ();
16660 mips_mark_labels ();
16661 mips_assembling_insn
= TRUE
;
16664 if (mips_cpreturn_register
== -1)
16666 ex
.X_op
= O_constant
;
16667 ex
.X_add_symbol
= NULL
;
16668 ex
.X_op_symbol
= NULL
;
16669 ex
.X_add_number
= mips_cpreturn_offset
;
16671 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16674 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16675 mips_cpreturn_register
, 0);
16678 mips_assembling_insn
= FALSE
;
16679 demand_empty_rest_of_line ();
16682 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16683 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16684 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16685 debug information or MIPS16 TLS. */
16688 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16689 bfd_reloc_code_real_type rtype
)
16696 if (ex
.X_op
!= O_symbol
)
16698 as_bad (_("Unsupported use of %s"), dirstr
);
16699 ignore_rest_of_line ();
16702 p
= frag_more (bytes
);
16703 md_number_to_chars (p
, 0, bytes
);
16704 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16705 demand_empty_rest_of_line ();
16706 mips_clear_insn_labels ();
16709 /* Handle .dtprelword. */
16712 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16714 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16717 /* Handle .dtpreldword. */
16720 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16722 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16725 /* Handle .tprelword. */
16728 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16730 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16733 /* Handle .tpreldword. */
16736 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16738 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16741 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16742 code. It sets the offset to use in gp_rel relocations. */
16745 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16747 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16748 We also need NewABI support. */
16749 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16755 mips_gprel_offset
= get_absolute_expression ();
16757 demand_empty_rest_of_line ();
16760 /* Handle the .gpword pseudo-op. This is used when generating PIC
16761 code. It generates a 32 bit GP relative reloc. */
16764 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16766 segment_info_type
*si
;
16767 struct insn_label_list
*l
;
16771 /* When not generating PIC code, this is treated as .word. */
16772 if (mips_pic
!= SVR4_PIC
)
16778 si
= seg_info (now_seg
);
16779 l
= si
->label_list
;
16780 mips_emit_delays ();
16782 mips_align (2, 0, l
);
16785 mips_clear_insn_labels ();
16787 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16789 as_bad (_("Unsupported use of .gpword"));
16790 ignore_rest_of_line ();
16794 md_number_to_chars (p
, 0, 4);
16795 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16796 BFD_RELOC_GPREL32
);
16798 demand_empty_rest_of_line ();
16802 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16804 segment_info_type
*si
;
16805 struct insn_label_list
*l
;
16809 /* When not generating PIC code, this is treated as .dword. */
16810 if (mips_pic
!= SVR4_PIC
)
16816 si
= seg_info (now_seg
);
16817 l
= si
->label_list
;
16818 mips_emit_delays ();
16820 mips_align (3, 0, l
);
16823 mips_clear_insn_labels ();
16825 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16827 as_bad (_("Unsupported use of .gpdword"));
16828 ignore_rest_of_line ();
16832 md_number_to_chars (p
, 0, 8);
16833 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16834 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16836 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16837 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16838 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16840 demand_empty_rest_of_line ();
16843 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16844 tables. It generates a R_MIPS_EH reloc. */
16847 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16852 mips_emit_delays ();
16855 mips_clear_insn_labels ();
16857 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16859 as_bad (_("Unsupported use of .ehword"));
16860 ignore_rest_of_line ();
16864 md_number_to_chars (p
, 0, 4);
16865 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16866 BFD_RELOC_MIPS_EH
);
16868 demand_empty_rest_of_line ();
16871 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16872 tables in SVR4 PIC code. */
16875 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16879 /* This is ignored when not generating SVR4 PIC code. */
16880 if (mips_pic
!= SVR4_PIC
)
16886 mips_mark_labels ();
16887 mips_assembling_insn
= TRUE
;
16889 /* Add $gp to the register named as an argument. */
16891 reg
= tc_get_register (0);
16892 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16895 mips_assembling_insn
= FALSE
;
16896 demand_empty_rest_of_line ();
16899 /* Handle the .insn pseudo-op. This marks instruction labels in
16900 mips16/micromips mode. This permits the linker to handle them specially,
16901 such as generating jalx instructions when needed. We also make
16902 them odd for the duration of the assembly, in order to generate the
16903 right sort of code. We will make them even in the adjust_symtab
16904 routine, while leaving them marked. This is convenient for the
16905 debugger and the disassembler. The linker knows to make them odd
16909 s_insn (int ignore ATTRIBUTE_UNUSED
)
16911 mips_mark_labels ();
16913 demand_empty_rest_of_line ();
16916 /* Handle the .nan pseudo-op. */
16919 s_nan (int ignore ATTRIBUTE_UNUSED
)
16921 static const char str_legacy
[] = "legacy";
16922 static const char str_2008
[] = "2008";
16925 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16927 if (i
== sizeof (str_2008
) - 1
16928 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16929 mips_flag_nan2008
= TRUE
;
16930 else if (i
== sizeof (str_legacy
) - 1
16931 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16932 mips_flag_nan2008
= FALSE
;
16934 as_bad (_("Bad .nan directive"));
16936 input_line_pointer
+= i
;
16937 demand_empty_rest_of_line ();
16940 /* Handle a .stab[snd] directive. Ideally these directives would be
16941 implemented in a transparent way, so that removing them would not
16942 have any effect on the generated instructions. However, s_stab
16943 internally changes the section, so in practice we need to decide
16944 now whether the preceding label marks compressed code. We do not
16945 support changing the compression mode of a label after a .stab*
16946 directive, such as in:
16952 so the current mode wins. */
16955 s_mips_stab (int type
)
16957 mips_mark_labels ();
16961 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16964 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16971 name
= input_line_pointer
;
16972 c
= get_symbol_end ();
16973 symbolP
= symbol_find_or_make (name
);
16974 S_SET_WEAK (symbolP
);
16975 *input_line_pointer
= c
;
16977 SKIP_WHITESPACE ();
16979 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16981 if (S_IS_DEFINED (symbolP
))
16983 as_bad (_("ignoring attempt to redefine symbol %s"),
16984 S_GET_NAME (symbolP
));
16985 ignore_rest_of_line ();
16989 if (*input_line_pointer
== ',')
16991 ++input_line_pointer
;
16992 SKIP_WHITESPACE ();
16996 if (exp
.X_op
!= O_symbol
)
16998 as_bad (_("bad .weakext directive"));
16999 ignore_rest_of_line ();
17002 symbol_set_value_expression (symbolP
, &exp
);
17005 demand_empty_rest_of_line ();
17008 /* Parse a register string into a number. Called from the ECOFF code
17009 to parse .frame. The argument is non-zero if this is the frame
17010 register, so that we can record it in mips_frame_reg. */
17013 tc_get_register (int frame
)
17017 SKIP_WHITESPACE ();
17018 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17022 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17023 mips_frame_reg_valid
= 1;
17024 mips_cprestore_valid
= 0;
17030 md_section_align (asection
*seg
, valueT addr
)
17032 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17034 /* We don't need to align ELF sections to the full alignment.
17035 However, Irix 5 may prefer that we align them at least to a 16
17036 byte boundary. We don't bother to align the sections if we
17037 are targeted for an embedded system. */
17038 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17043 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17046 /* Utility routine, called from above as well. If called while the
17047 input file is still being read, it's only an approximation. (For
17048 example, a symbol may later become defined which appeared to be
17049 undefined earlier.) */
17052 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17057 if (g_switch_value
> 0)
17059 const char *symname
;
17062 /* Find out whether this symbol can be referenced off the $gp
17063 register. It can be if it is smaller than the -G size or if
17064 it is in the .sdata or .sbss section. Certain symbols can
17065 not be referenced off the $gp, although it appears as though
17067 symname
= S_GET_NAME (sym
);
17068 if (symname
!= (const char *) NULL
17069 && (strcmp (symname
, "eprol") == 0
17070 || strcmp (symname
, "etext") == 0
17071 || strcmp (symname
, "_gp") == 0
17072 || strcmp (symname
, "edata") == 0
17073 || strcmp (symname
, "_fbss") == 0
17074 || strcmp (symname
, "_fdata") == 0
17075 || strcmp (symname
, "_ftext") == 0
17076 || strcmp (symname
, "end") == 0
17077 || strcmp (symname
, "_gp_disp") == 0))
17079 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17081 #ifndef NO_ECOFF_DEBUGGING
17082 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17083 && (symbol_get_obj (sym
)->ecoff_extern_size
17084 <= g_switch_value
))
17086 /* We must defer this decision until after the whole
17087 file has been read, since there might be a .extern
17088 after the first use of this symbol. */
17089 || (before_relaxing
17090 #ifndef NO_ECOFF_DEBUGGING
17091 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17093 && S_GET_VALUE (sym
) == 0)
17094 || (S_GET_VALUE (sym
) != 0
17095 && S_GET_VALUE (sym
) <= g_switch_value
)))
17099 const char *segname
;
17101 segname
= segment_name (S_GET_SEGMENT (sym
));
17102 gas_assert (strcmp (segname
, ".lit8") != 0
17103 && strcmp (segname
, ".lit4") != 0);
17104 change
= (strcmp (segname
, ".sdata") != 0
17105 && strcmp (segname
, ".sbss") != 0
17106 && strncmp (segname
, ".sdata.", 7) != 0
17107 && strncmp (segname
, ".sbss.", 6) != 0
17108 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17109 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17114 /* We are not optimizing for the $gp register. */
17119 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17122 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17126 /* Handle the case of a symbol equated to another symbol. */
17127 while (symbol_equated_reloc_p (sym
))
17131 /* It's possible to get a loop here in a badly written program. */
17132 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17138 if (symbol_section_p (sym
))
17141 symsec
= S_GET_SEGMENT (sym
);
17143 /* This must duplicate the test in adjust_reloc_syms. */
17144 return (!bfd_is_und_section (symsec
)
17145 && !bfd_is_abs_section (symsec
)
17146 && !bfd_is_com_section (symsec
)
17147 && !s_is_linkonce (sym
, segtype
)
17148 /* A global or weak symbol is treated as external. */
17149 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17153 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17154 extended opcode. SEC is the section the frag is in. */
17157 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17160 const struct mips16_immed_operand
*op
;
17162 int mintiny
, maxtiny
;
17166 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17168 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17171 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17172 op
= mips16_immed_operands
;
17173 while (op
->type
!= type
)
17176 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17181 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17184 maxtiny
= 1 << op
->nbits
;
17189 maxtiny
= (1 << op
->nbits
) - 1;
17194 mintiny
= - (1 << (op
->nbits
- 1));
17195 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17198 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17199 val
= S_GET_VALUE (fragp
->fr_symbol
);
17200 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17206 /* We won't have the section when we are called from
17207 mips_relax_frag. However, we will always have been called
17208 from md_estimate_size_before_relax first. If this is a
17209 branch to a different section, we mark it as such. If SEC is
17210 NULL, and the frag is not marked, then it must be a branch to
17211 the same section. */
17214 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17219 /* Must have been called from md_estimate_size_before_relax. */
17222 fragp
->fr_subtype
=
17223 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17225 /* FIXME: We should support this, and let the linker
17226 catch branches and loads that are out of range. */
17227 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17228 _("unsupported PC relative reference to different section"));
17232 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17233 /* Assume non-extended on the first relaxation pass.
17234 The address we have calculated will be bogus if this is
17235 a forward branch to another frag, as the forward frag
17236 will have fr_address == 0. */
17240 /* In this case, we know for sure that the symbol fragment is in
17241 the same section. If the relax_marker of the symbol fragment
17242 differs from the relax_marker of this fragment, we have not
17243 yet adjusted the symbol fragment fr_address. We want to add
17244 in STRETCH in order to get a better estimate of the address.
17245 This particularly matters because of the shift bits. */
17247 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17251 /* Adjust stretch for any alignment frag. Note that if have
17252 been expanding the earlier code, the symbol may be
17253 defined in what appears to be an earlier frag. FIXME:
17254 This doesn't handle the fr_subtype field, which specifies
17255 a maximum number of bytes to skip when doing an
17257 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17259 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17262 stretch
= - ((- stretch
)
17263 & ~ ((1 << (int) f
->fr_offset
) - 1));
17265 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17274 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17276 /* The base address rules are complicated. The base address of
17277 a branch is the following instruction. The base address of a
17278 PC relative load or add is the instruction itself, but if it
17279 is in a delay slot (in which case it can not be extended) use
17280 the address of the instruction whose delay slot it is in. */
17281 if (type
== 'p' || type
== 'q')
17285 /* If we are currently assuming that this frag should be
17286 extended, then, the current address is two bytes
17288 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17291 /* Ignore the low bit in the target, since it will be set
17292 for a text label. */
17293 if ((val
& 1) != 0)
17296 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17298 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17301 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17303 /* Branch offsets have an implicit 0 in the lowest bit. */
17304 if (type
== 'p' || type
== 'q')
17307 /* If any of the shifted bits are set, we must use an extended
17308 opcode. If the address depends on the size of this
17309 instruction, this can lead to a loop, so we arrange to always
17310 use an extended opcode. We only check this when we are in
17311 the main relaxation loop, when SEC is NULL. */
17312 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17314 fragp
->fr_subtype
=
17315 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17319 /* If we are about to mark a frag as extended because the value
17320 is precisely maxtiny + 1, then there is a chance of an
17321 infinite loop as in the following code:
17326 In this case when the la is extended, foo is 0x3fc bytes
17327 away, so the la can be shrunk, but then foo is 0x400 away, so
17328 the la must be extended. To avoid this loop, we mark the
17329 frag as extended if it was small, and is about to become
17330 extended with a value of maxtiny + 1. */
17331 if (val
== ((maxtiny
+ 1) << op
->shift
)
17332 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17335 fragp
->fr_subtype
=
17336 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17340 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17341 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17343 if ((val
& ((1 << op
->shift
) - 1)) != 0
17344 || val
< (mintiny
<< op
->shift
)
17345 || val
> (maxtiny
<< op
->shift
))
17351 /* Compute the length of a branch sequence, and adjust the
17352 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17353 worst-case length is computed, with UPDATE being used to indicate
17354 whether an unconditional (-1), branch-likely (+1) or regular (0)
17355 branch is to be computed. */
17357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17359 bfd_boolean toofar
;
17363 && S_IS_DEFINED (fragp
->fr_symbol
)
17364 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17369 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17371 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17375 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17378 /* If the symbol is not defined or it's in a different segment,
17379 assume the user knows what's going on and emit a short
17385 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17387 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17388 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17389 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17390 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17396 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17399 if (mips_pic
!= NO_PIC
)
17401 /* Additional space for PIC loading of target address. */
17403 if (mips_opts
.isa
== ISA_MIPS1
)
17404 /* Additional space for $at-stabilizing nop. */
17408 /* If branch is conditional. */
17409 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17416 /* Compute the length of a branch sequence, and adjust the
17417 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17418 worst-case length is computed, with UPDATE being used to indicate
17419 whether an unconditional (-1), or regular (0) branch is to be
17423 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17425 bfd_boolean toofar
;
17429 && S_IS_DEFINED (fragp
->fr_symbol
)
17430 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17435 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17436 /* Ignore the low bit in the target, since it will be set
17437 for a text label. */
17438 if ((val
& 1) != 0)
17441 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17445 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17448 /* If the symbol is not defined or it's in a different segment,
17449 assume the user knows what's going on and emit a short
17455 if (fragp
&& update
17456 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17457 fragp
->fr_subtype
= (toofar
17458 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17459 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17464 bfd_boolean compact_known
= fragp
!= NULL
;
17465 bfd_boolean compact
= FALSE
;
17466 bfd_boolean uncond
;
17469 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17471 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17473 uncond
= update
< 0;
17475 /* If label is out of range, we turn branch <br>:
17477 <br> label # 4 bytes
17483 nop # 2 bytes if compact && !PIC
17486 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17489 /* If assembling PIC code, we further turn:
17495 lw/ld at, %got(label)(gp) # 4 bytes
17496 d/addiu at, %lo(label) # 4 bytes
17499 if (mips_pic
!= NO_PIC
)
17502 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17504 <brneg> 0f # 4 bytes
17505 nop # 2 bytes if !compact
17508 length
+= (compact_known
&& compact
) ? 4 : 6;
17514 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17515 bit accordingly. */
17518 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17520 bfd_boolean toofar
;
17523 && S_IS_DEFINED (fragp
->fr_symbol
)
17524 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17530 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17531 /* Ignore the low bit in the target, since it will be set
17532 for a text label. */
17533 if ((val
& 1) != 0)
17536 /* Assume this is a 2-byte branch. */
17537 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17539 /* We try to avoid the infinite loop by not adding 2 more bytes for
17544 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17546 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17547 else if (type
== 'E')
17548 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17553 /* If the symbol is not defined or it's in a different segment,
17554 we emit a normal 32-bit branch. */
17557 if (fragp
&& update
17558 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17560 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17561 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17569 /* Estimate the size of a frag before relaxing. Unless this is the
17570 mips16, we are not really relaxing here, and the final size is
17571 encoded in the subtype information. For the mips16, we have to
17572 decide whether we are using an extended opcode or not. */
17575 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17579 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17582 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17584 return fragp
->fr_var
;
17587 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17588 /* We don't want to modify the EXTENDED bit here; it might get us
17589 into infinite loops. We change it only in mips_relax_frag(). */
17590 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17592 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17596 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17597 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17598 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17599 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17600 fragp
->fr_var
= length
;
17605 if (mips_pic
== NO_PIC
)
17606 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17607 else if (mips_pic
== SVR4_PIC
)
17608 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17609 else if (mips_pic
== VXWORKS_PIC
)
17610 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17617 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17618 return -RELAX_FIRST (fragp
->fr_subtype
);
17621 return -RELAX_SECOND (fragp
->fr_subtype
);
17624 /* This is called to see whether a reloc against a defined symbol
17625 should be converted into a reloc against a section. */
17628 mips_fix_adjustable (fixS
*fixp
)
17630 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17631 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17634 if (fixp
->fx_addsy
== NULL
)
17637 /* If symbol SYM is in a mergeable section, relocations of the form
17638 SYM + 0 can usually be made section-relative. The mergeable data
17639 is then identified by the section offset rather than by the symbol.
17641 However, if we're generating REL LO16 relocations, the offset is split
17642 between the LO16 and parterning high part relocation. The linker will
17643 need to recalculate the complete offset in order to correctly identify
17646 The linker has traditionally not looked for the parterning high part
17647 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17648 placed anywhere. Rather than break backwards compatibility by changing
17649 this, it seems better not to force the issue, and instead keep the
17650 original symbol. This will work with either linker behavior. */
17651 if ((lo16_reloc_p (fixp
->fx_r_type
)
17652 || reloc_needs_lo_p (fixp
->fx_r_type
))
17653 && HAVE_IN_PLACE_ADDENDS
17654 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17657 /* There is no place to store an in-place offset for JALR relocations.
17658 Likewise an in-range offset of limited PC-relative relocations may
17659 overflow the in-place relocatable field if recalculated against the
17660 start address of the symbol's containing section. */
17661 if (HAVE_IN_PLACE_ADDENDS
17662 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17663 || jalr_reloc_p (fixp
->fx_r_type
)))
17666 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17667 to a floating-point stub. The same is true for non-R_MIPS16_26
17668 relocations against MIPS16 functions; in this case, the stub becomes
17669 the function's canonical address.
17671 Floating-point stubs are stored in unique .mips16.call.* or
17672 .mips16.fn.* sections. If a stub T for function F is in section S,
17673 the first relocation in section S must be against F; this is how the
17674 linker determines the target function. All relocations that might
17675 resolve to T must also be against F. We therefore have the following
17676 restrictions, which are given in an intentionally-redundant way:
17678 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17681 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17682 if that stub might be used.
17684 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17687 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17688 that stub might be used.
17690 There is a further restriction:
17692 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17693 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17694 targets with in-place addends; the relocation field cannot
17695 encode the low bit.
17697 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17698 against a MIPS16 symbol. We deal with (5) by by not reducing any
17699 such relocations on REL targets.
17701 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17702 relocation against some symbol R, no relocation against R may be
17703 reduced. (Note that this deals with (2) as well as (1) because
17704 relocations against global symbols will never be reduced on ELF
17705 targets.) This approach is a little simpler than trying to detect
17706 stub sections, and gives the "all or nothing" per-symbol consistency
17707 that we have for MIPS16 symbols. */
17708 if (fixp
->fx_subsy
== NULL
17709 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17710 || *symbol_get_tc (fixp
->fx_addsy
)
17711 || (HAVE_IN_PLACE_ADDENDS
17712 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17713 && jmp_reloc_p (fixp
->fx_r_type
))))
17719 /* Translate internal representation of relocation info to BFD target
17723 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17725 static arelent
*retval
[4];
17727 bfd_reloc_code_real_type code
;
17729 memset (retval
, 0, sizeof(retval
));
17730 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17731 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17732 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17733 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17735 if (fixp
->fx_pcrel
)
17737 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17738 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17739 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17740 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17741 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
17743 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17744 Relocations want only the symbol offset. */
17745 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17748 reloc
->addend
= fixp
->fx_addnumber
;
17750 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17751 entry to be used in the relocation's section offset. */
17752 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17754 reloc
->address
= reloc
->addend
;
17758 code
= fixp
->fx_r_type
;
17760 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17761 if (reloc
->howto
== NULL
)
17763 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17764 _("Can not represent %s relocation in this object file format"),
17765 bfd_get_reloc_code_name (code
));
17772 /* Relax a machine dependent frag. This returns the amount by which
17773 the current size of the frag should change. */
17776 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17778 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17780 offsetT old_var
= fragp
->fr_var
;
17782 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17784 return fragp
->fr_var
- old_var
;
17787 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17789 offsetT old_var
= fragp
->fr_var
;
17790 offsetT new_var
= 4;
17792 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17793 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17794 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17795 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17796 fragp
->fr_var
= new_var
;
17798 return new_var
- old_var
;
17801 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17804 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17806 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17808 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17813 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17815 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17822 /* Convert a machine dependent frag. */
17825 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17827 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17830 unsigned long insn
;
17834 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17835 insn
= read_insn (buf
);
17837 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17839 /* We generate a fixup instead of applying it right now
17840 because, if there are linker relaxations, we're going to
17841 need the relocations. */
17842 exp
.X_op
= O_symbol
;
17843 exp
.X_add_symbol
= fragp
->fr_symbol
;
17844 exp
.X_add_number
= fragp
->fr_offset
;
17846 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17847 BFD_RELOC_16_PCREL_S2
);
17848 fixp
->fx_file
= fragp
->fr_file
;
17849 fixp
->fx_line
= fragp
->fr_line
;
17851 buf
= write_insn (buf
, insn
);
17857 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17858 _("Relaxed out-of-range branch into a jump"));
17860 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17863 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17865 /* Reverse the branch. */
17866 switch ((insn
>> 28) & 0xf)
17869 /* bc[0-3][tf]l? instructions can have the condition
17870 reversed by tweaking a single TF bit, and their
17871 opcodes all have 0x4???????. */
17872 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17873 insn
^= 0x00010000;
17877 /* bltz 0x04000000 bgez 0x04010000
17878 bltzal 0x04100000 bgezal 0x04110000 */
17879 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17880 insn
^= 0x00010000;
17884 /* beq 0x10000000 bne 0x14000000
17885 blez 0x18000000 bgtz 0x1c000000 */
17886 insn
^= 0x04000000;
17894 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17896 /* Clear the and-link bit. */
17897 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17899 /* bltzal 0x04100000 bgezal 0x04110000
17900 bltzall 0x04120000 bgezall 0x04130000 */
17901 insn
&= ~0x00100000;
17904 /* Branch over the branch (if the branch was likely) or the
17905 full jump (not likely case). Compute the offset from the
17906 current instruction to branch to. */
17907 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17911 /* How many bytes in instructions we've already emitted? */
17912 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17913 /* How many bytes in instructions from here to the end? */
17914 i
= fragp
->fr_var
- i
;
17916 /* Convert to instruction count. */
17918 /* Branch counts from the next instruction. */
17921 /* Branch over the jump. */
17922 buf
= write_insn (buf
, insn
);
17925 buf
= write_insn (buf
, 0);
17927 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17929 /* beql $0, $0, 2f */
17931 /* Compute the PC offset from the current instruction to
17932 the end of the variable frag. */
17933 /* How many bytes in instructions we've already emitted? */
17934 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17935 /* How many bytes in instructions from here to the end? */
17936 i
= fragp
->fr_var
- i
;
17937 /* Convert to instruction count. */
17939 /* Don't decrement i, because we want to branch over the
17943 buf
= write_insn (buf
, insn
);
17944 buf
= write_insn (buf
, 0);
17948 if (mips_pic
== NO_PIC
)
17951 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17952 ? 0x0c000000 : 0x08000000);
17953 exp
.X_op
= O_symbol
;
17954 exp
.X_add_symbol
= fragp
->fr_symbol
;
17955 exp
.X_add_number
= fragp
->fr_offset
;
17957 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17958 FALSE
, BFD_RELOC_MIPS_JMP
);
17959 fixp
->fx_file
= fragp
->fr_file
;
17960 fixp
->fx_line
= fragp
->fr_line
;
17962 buf
= write_insn (buf
, insn
);
17966 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17968 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17969 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17970 insn
|= at
<< OP_SH_RT
;
17971 exp
.X_op
= O_symbol
;
17972 exp
.X_add_symbol
= fragp
->fr_symbol
;
17973 exp
.X_add_number
= fragp
->fr_offset
;
17975 if (fragp
->fr_offset
)
17977 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17978 exp
.X_add_number
= 0;
17981 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17982 FALSE
, BFD_RELOC_MIPS_GOT16
);
17983 fixp
->fx_file
= fragp
->fr_file
;
17984 fixp
->fx_line
= fragp
->fr_line
;
17986 buf
= write_insn (buf
, insn
);
17988 if (mips_opts
.isa
== ISA_MIPS1
)
17990 buf
= write_insn (buf
, 0);
17992 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17993 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17994 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17996 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17997 FALSE
, BFD_RELOC_LO16
);
17998 fixp
->fx_file
= fragp
->fr_file
;
17999 fixp
->fx_line
= fragp
->fr_line
;
18001 buf
= write_insn (buf
, insn
);
18004 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18008 insn
|= at
<< OP_SH_RS
;
18010 buf
= write_insn (buf
, insn
);
18014 fragp
->fr_fix
+= fragp
->fr_var
;
18015 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18019 /* Relax microMIPS branches. */
18020 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18022 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18023 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18024 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18025 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18026 bfd_boolean short_ds
;
18027 unsigned long insn
;
18031 exp
.X_op
= O_symbol
;
18032 exp
.X_add_symbol
= fragp
->fr_symbol
;
18033 exp
.X_add_number
= fragp
->fr_offset
;
18035 fragp
->fr_fix
+= fragp
->fr_var
;
18037 /* Handle 16-bit branches that fit or are forced to fit. */
18038 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18040 /* We generate a fixup instead of applying it right now,
18041 because if there is linker relaxation, we're going to
18042 need the relocations. */
18044 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18045 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18046 else if (type
== 'E')
18047 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18048 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18052 fixp
->fx_file
= fragp
->fr_file
;
18053 fixp
->fx_line
= fragp
->fr_line
;
18055 /* These relocations can have an addend that won't fit in
18057 fixp
->fx_no_overflow
= 1;
18062 /* Handle 32-bit branches that fit or are forced to fit. */
18063 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18064 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18066 /* We generate a fixup instead of applying it right now,
18067 because if there is linker relaxation, we're going to
18068 need the relocations. */
18069 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18070 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18071 fixp
->fx_file
= fragp
->fr_file
;
18072 fixp
->fx_line
= fragp
->fr_line
;
18078 /* Relax 16-bit branches to 32-bit branches. */
18081 insn
= read_compressed_insn (buf
, 2);
18083 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18084 insn
= 0x94000000; /* beq */
18085 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18087 unsigned long regno
;
18089 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18090 regno
= micromips_to_32_reg_d_map
[regno
];
18091 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18092 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18097 /* Nothing else to do, just write it out. */
18098 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18099 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18101 buf
= write_compressed_insn (buf
, insn
, 4);
18102 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18107 insn
= read_compressed_insn (buf
, 4);
18109 /* Relax 32-bit branches to a sequence of instructions. */
18110 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18111 _("Relaxed out-of-range branch into a jump"));
18113 /* Set the short-delay-slot bit. */
18114 short_ds
= al
&& (insn
& 0x02000000) != 0;
18116 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18120 /* Reverse the branch. */
18121 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18122 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18123 insn
^= 0x20000000;
18124 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18125 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18126 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18127 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18128 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18129 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18130 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18131 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18132 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18133 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18134 insn
^= 0x00400000;
18135 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18136 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18137 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18138 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18139 insn
^= 0x00200000;
18145 /* Clear the and-link and short-delay-slot bits. */
18146 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18148 /* bltzal 0x40200000 bgezal 0x40600000 */
18149 /* bltzals 0x42200000 bgezals 0x42600000 */
18150 insn
&= ~0x02200000;
18153 /* Make a label at the end for use with the branch. */
18154 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18155 micromips_label_inc ();
18156 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18159 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18160 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18161 fixp
->fx_file
= fragp
->fr_file
;
18162 fixp
->fx_line
= fragp
->fr_line
;
18164 /* Branch over the jump. */
18165 buf
= write_compressed_insn (buf
, insn
, 4);
18168 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18171 if (mips_pic
== NO_PIC
)
18173 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18175 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18176 insn
= al
? jal
: 0xd4000000;
18178 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18179 BFD_RELOC_MICROMIPS_JMP
);
18180 fixp
->fx_file
= fragp
->fr_file
;
18181 fixp
->fx_line
= fragp
->fr_line
;
18183 buf
= write_compressed_insn (buf
, insn
, 4);
18186 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18190 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18191 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18192 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18194 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18195 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18196 insn
|= at
<< MICROMIPSOP_SH_RT
;
18198 if (exp
.X_add_number
)
18200 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18201 exp
.X_add_number
= 0;
18204 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18205 BFD_RELOC_MICROMIPS_GOT16
);
18206 fixp
->fx_file
= fragp
->fr_file
;
18207 fixp
->fx_line
= fragp
->fr_line
;
18209 buf
= write_compressed_insn (buf
, insn
, 4);
18211 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18212 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18213 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18215 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18216 BFD_RELOC_MICROMIPS_LO16
);
18217 fixp
->fx_file
= fragp
->fr_file
;
18218 fixp
->fx_line
= fragp
->fr_line
;
18220 buf
= write_compressed_insn (buf
, insn
, 4);
18222 /* jr/jrc/jalr/jalrs $at */
18223 insn
= al
? jalr
: jr
;
18224 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18226 buf
= write_compressed_insn (buf
, insn
, 2);
18229 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18233 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18236 const struct mips16_immed_operand
*op
;
18239 unsigned int user_length
, length
;
18240 unsigned long insn
;
18243 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18244 op
= mips16_immed_operands
;
18245 while (op
->type
!= type
)
18248 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18249 val
= resolve_symbol_value (fragp
->fr_symbol
);
18254 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18256 /* The rules for the base address of a PC relative reloc are
18257 complicated; see mips16_extended_frag. */
18258 if (type
== 'p' || type
== 'q')
18263 /* Ignore the low bit in the target, since it will be
18264 set for a text label. */
18265 if ((val
& 1) != 0)
18268 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18270 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18273 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18276 /* Make sure the section winds up with the alignment we have
18279 record_alignment (asec
, op
->shift
);
18283 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18284 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18285 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18286 _("extended instruction in delay slot"));
18288 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18290 insn
= read_compressed_insn (buf
, 2);
18292 insn
|= MIPS16_EXTEND
;
18294 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18296 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18301 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18302 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18304 length
= (ext
? 4 : 2);
18305 gas_assert (mips16_opcode_length (insn
) == length
);
18306 write_compressed_insn (buf
, insn
, length
);
18307 fragp
->fr_fix
+= length
;
18311 relax_substateT subtype
= fragp
->fr_subtype
;
18312 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18313 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18317 first
= RELAX_FIRST (subtype
);
18318 second
= RELAX_SECOND (subtype
);
18319 fixp
= (fixS
*) fragp
->fr_opcode
;
18321 /* If the delay slot chosen does not match the size of the instruction,
18322 then emit a warning. */
18323 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18324 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18329 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18330 | RELAX_DELAY_SLOT_SIZE_FIRST
18331 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18332 msg
= macro_warning (s
);
18334 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18338 /* Possibly emit a warning if we've chosen the longer option. */
18339 if (use_second
== second_longer
)
18345 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18346 msg
= macro_warning (s
);
18348 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18352 /* Go through all the fixups for the first sequence. Disable them
18353 (by marking them as done) if we're going to use the second
18354 sequence instead. */
18356 && fixp
->fx_frag
== fragp
18357 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18359 if (subtype
& RELAX_USE_SECOND
)
18361 fixp
= fixp
->fx_next
;
18364 /* Go through the fixups for the second sequence. Disable them if
18365 we're going to use the first sequence, otherwise adjust their
18366 addresses to account for the relaxation. */
18367 while (fixp
&& fixp
->fx_frag
== fragp
)
18369 if (subtype
& RELAX_USE_SECOND
)
18370 fixp
->fx_where
-= first
;
18373 fixp
= fixp
->fx_next
;
18376 /* Now modify the frag contents. */
18377 if (subtype
& RELAX_USE_SECOND
)
18381 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18382 memmove (start
, start
+ first
, second
);
18383 fragp
->fr_fix
-= first
;
18386 fragp
->fr_fix
-= second
;
18390 /* This function is called after the relocs have been generated.
18391 We've been storing mips16 text labels as odd. Here we convert them
18392 back to even for the convenience of the debugger. */
18395 mips_frob_file_after_relocs (void)
18398 unsigned int count
, i
;
18400 syms
= bfd_get_outsymbols (stdoutput
);
18401 count
= bfd_get_symcount (stdoutput
);
18402 for (i
= 0; i
< count
; i
++, syms
++)
18403 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18404 && ((*syms
)->value
& 1) != 0)
18406 (*syms
)->value
&= ~1;
18407 /* If the symbol has an odd size, it was probably computed
18408 incorrectly, so adjust that as well. */
18409 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18410 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18414 /* This function is called whenever a label is defined, including fake
18415 labels instantiated off the dot special symbol. It is used when
18416 handling branch delays; if a branch has a label, we assume we cannot
18417 move it. This also bumps the value of the symbol by 1 in compressed
18421 mips_record_label (symbolS
*sym
)
18423 segment_info_type
*si
= seg_info (now_seg
);
18424 struct insn_label_list
*l
;
18426 if (free_insn_labels
== NULL
)
18427 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18430 l
= free_insn_labels
;
18431 free_insn_labels
= l
->next
;
18435 l
->next
= si
->label_list
;
18436 si
->label_list
= l
;
18439 /* This function is called as tc_frob_label() whenever a label is defined
18440 and adds a DWARF-2 record we only want for true labels. */
18443 mips_define_label (symbolS
*sym
)
18445 mips_record_label (sym
);
18446 dwarf2_emit_label (sym
);
18449 /* This function is called by tc_new_dot_label whenever a new dot symbol
18453 mips_add_dot_label (symbolS
*sym
)
18455 mips_record_label (sym
);
18456 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18457 mips_compressed_mark_label (sym
);
18460 /* Some special processing for a MIPS ELF file. */
18463 mips_elf_final_processing (void)
18465 /* Write out the register information. */
18466 if (mips_abi
!= N64_ABI
)
18470 s
.ri_gprmask
= mips_gprmask
;
18471 s
.ri_cprmask
[0] = mips_cprmask
[0];
18472 s
.ri_cprmask
[1] = mips_cprmask
[1];
18473 s
.ri_cprmask
[2] = mips_cprmask
[2];
18474 s
.ri_cprmask
[3] = mips_cprmask
[3];
18475 /* The gp_value field is set by the MIPS ELF backend. */
18477 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18478 ((Elf32_External_RegInfo
*)
18479 mips_regmask_frag
));
18483 Elf64_Internal_RegInfo s
;
18485 s
.ri_gprmask
= mips_gprmask
;
18487 s
.ri_cprmask
[0] = mips_cprmask
[0];
18488 s
.ri_cprmask
[1] = mips_cprmask
[1];
18489 s
.ri_cprmask
[2] = mips_cprmask
[2];
18490 s
.ri_cprmask
[3] = mips_cprmask
[3];
18491 /* The gp_value field is set by the MIPS ELF backend. */
18493 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18494 ((Elf64_External_RegInfo
*)
18495 mips_regmask_frag
));
18498 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18499 sort of BFD interface for this. */
18500 if (mips_any_noreorder
)
18501 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18502 if (mips_pic
!= NO_PIC
)
18504 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18505 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18508 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18510 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18511 defined at present; this might need to change in future. */
18512 if (file_ase_mips16
)
18513 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18514 if (file_ase_micromips
)
18515 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18516 if (file_ase
& ASE_MDMX
)
18517 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18519 /* Set the MIPS ELF ABI flags. */
18520 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18521 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18522 else if (mips_abi
== O64_ABI
)
18523 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18524 else if (mips_abi
== EABI_ABI
)
18526 if (!file_mips_gp32
)
18527 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18529 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18531 else if (mips_abi
== N32_ABI
)
18532 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18534 /* Nothing to do for N64_ABI. */
18536 if (mips_32bitmode
)
18537 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18539 if (mips_flag_nan2008
)
18540 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18542 #if 0 /* XXX FIXME */
18543 /* 32 bit code with 64 bit FP registers. */
18544 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18545 elf_elfheader (stdoutput
)->e_flags
|= ???;
18549 typedef struct proc
{
18551 symbolS
*func_end_sym
;
18552 unsigned long reg_mask
;
18553 unsigned long reg_offset
;
18554 unsigned long fpreg_mask
;
18555 unsigned long fpreg_offset
;
18556 unsigned long frame_offset
;
18557 unsigned long frame_reg
;
18558 unsigned long pc_reg
;
18561 static procS cur_proc
;
18562 static procS
*cur_proc_ptr
;
18563 static int numprocs
;
18565 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18566 as "2", and a normal nop as "0". */
18568 #define NOP_OPCODE_MIPS 0
18569 #define NOP_OPCODE_MIPS16 1
18570 #define NOP_OPCODE_MICROMIPS 2
18573 mips_nop_opcode (void)
18575 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18576 return NOP_OPCODE_MICROMIPS
;
18577 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18578 return NOP_OPCODE_MIPS16
;
18580 return NOP_OPCODE_MIPS
;
18583 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18584 32-bit microMIPS NOPs here (if applicable). */
18587 mips_handle_align (fragS
*fragp
)
18591 int bytes
, size
, excess
;
18594 if (fragp
->fr_type
!= rs_align_code
)
18597 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18599 switch (nop_opcode
)
18601 case NOP_OPCODE_MICROMIPS
:
18602 opcode
= micromips_nop32_insn
.insn_opcode
;
18605 case NOP_OPCODE_MIPS16
:
18606 opcode
= mips16_nop_insn
.insn_opcode
;
18609 case NOP_OPCODE_MIPS
:
18611 opcode
= nop_insn
.insn_opcode
;
18616 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18617 excess
= bytes
% size
;
18619 /* Handle the leading part if we're not inserting a whole number of
18620 instructions, and make it the end of the fixed part of the frag.
18621 Try to fit in a short microMIPS NOP if applicable and possible,
18622 and use zeroes otherwise. */
18623 gas_assert (excess
< 4);
18624 fragp
->fr_fix
+= excess
;
18629 /* Fall through. */
18631 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18633 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18637 /* Fall through. */
18640 /* Fall through. */
18645 md_number_to_chars (p
, opcode
, size
);
18646 fragp
->fr_var
= size
;
18650 md_obj_begin (void)
18657 /* Check for premature end, nesting errors, etc. */
18659 as_warn (_("missing .end at end of assembly"));
18668 if (*input_line_pointer
== '-')
18670 ++input_line_pointer
;
18673 if (!ISDIGIT (*input_line_pointer
))
18674 as_bad (_("expected simple number"));
18675 if (input_line_pointer
[0] == '0')
18677 if (input_line_pointer
[1] == 'x')
18679 input_line_pointer
+= 2;
18680 while (ISXDIGIT (*input_line_pointer
))
18683 val
|= hex_value (*input_line_pointer
++);
18685 return negative
? -val
: val
;
18689 ++input_line_pointer
;
18690 while (ISDIGIT (*input_line_pointer
))
18693 val
|= *input_line_pointer
++ - '0';
18695 return negative
? -val
: val
;
18698 if (!ISDIGIT (*input_line_pointer
))
18700 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18701 *input_line_pointer
, *input_line_pointer
);
18702 as_warn (_("invalid number"));
18705 while (ISDIGIT (*input_line_pointer
))
18708 val
+= *input_line_pointer
++ - '0';
18710 return negative
? -val
: val
;
18713 /* The .file directive; just like the usual .file directive, but there
18714 is an initial number which is the ECOFF file index. In the non-ECOFF
18715 case .file implies DWARF-2. */
18718 s_mips_file (int x ATTRIBUTE_UNUSED
)
18720 static int first_file_directive
= 0;
18722 if (ECOFF_DEBUGGING
)
18731 filename
= dwarf2_directive_file (0);
18733 /* Versions of GCC up to 3.1 start files with a ".file"
18734 directive even for stabs output. Make sure that this
18735 ".file" is handled. Note that you need a version of GCC
18736 after 3.1 in order to support DWARF-2 on MIPS. */
18737 if (filename
!= NULL
&& ! first_file_directive
)
18739 (void) new_logical_line (filename
, -1);
18740 s_app_file_string (filename
, 0);
18742 first_file_directive
= 1;
18746 /* The .loc directive, implying DWARF-2. */
18749 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18751 if (!ECOFF_DEBUGGING
)
18752 dwarf2_directive_loc (0);
18755 /* The .end directive. */
18758 s_mips_end (int x ATTRIBUTE_UNUSED
)
18762 /* Following functions need their own .frame and .cprestore directives. */
18763 mips_frame_reg_valid
= 0;
18764 mips_cprestore_valid
= 0;
18766 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18769 demand_empty_rest_of_line ();
18774 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18775 as_warn (_(".end not in text section"));
18779 as_warn (_(".end directive without a preceding .ent directive."));
18780 demand_empty_rest_of_line ();
18786 gas_assert (S_GET_NAME (p
));
18787 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18788 as_warn (_(".end symbol does not match .ent symbol."));
18790 if (debug_type
== DEBUG_STABS
)
18791 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18795 as_warn (_(".end directive missing or unknown symbol"));
18797 /* Create an expression to calculate the size of the function. */
18798 if (p
&& cur_proc_ptr
)
18800 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18801 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18804 exp
->X_op
= O_subtract
;
18805 exp
->X_add_symbol
= symbol_temp_new_now ();
18806 exp
->X_op_symbol
= p
;
18807 exp
->X_add_number
= 0;
18809 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18812 /* Generate a .pdr section. */
18813 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
18815 segT saved_seg
= now_seg
;
18816 subsegT saved_subseg
= now_subseg
;
18820 #ifdef md_flush_pending_output
18821 md_flush_pending_output ();
18824 gas_assert (pdr_seg
);
18825 subseg_set (pdr_seg
, 0);
18827 /* Write the symbol. */
18828 exp
.X_op
= O_symbol
;
18829 exp
.X_add_symbol
= p
;
18830 exp
.X_add_number
= 0;
18831 emit_expr (&exp
, 4);
18833 fragp
= frag_more (7 * 4);
18835 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18836 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18837 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18838 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18839 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18840 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18841 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18843 subseg_set (saved_seg
, saved_subseg
);
18846 cur_proc_ptr
= NULL
;
18849 /* The .aent and .ent directives. */
18852 s_mips_ent (int aent
)
18856 symbolP
= get_symbol ();
18857 if (*input_line_pointer
== ',')
18858 ++input_line_pointer
;
18859 SKIP_WHITESPACE ();
18860 if (ISDIGIT (*input_line_pointer
)
18861 || *input_line_pointer
== '-')
18864 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18865 as_warn (_(".ent or .aent not in text section."));
18867 if (!aent
&& cur_proc_ptr
)
18868 as_warn (_("missing .end"));
18872 /* This function needs its own .frame and .cprestore directives. */
18873 mips_frame_reg_valid
= 0;
18874 mips_cprestore_valid
= 0;
18876 cur_proc_ptr
= &cur_proc
;
18877 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18879 cur_proc_ptr
->func_sym
= symbolP
;
18883 if (debug_type
== DEBUG_STABS
)
18884 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18885 S_GET_NAME (symbolP
));
18888 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18890 demand_empty_rest_of_line ();
18893 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18894 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18895 s_mips_frame is used so that we can set the PDR information correctly.
18896 We can't use the ecoff routines because they make reference to the ecoff
18897 symbol table (in the mdebug section). */
18900 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18902 if (ECOFF_DEBUGGING
)
18908 if (cur_proc_ptr
== (procS
*) NULL
)
18910 as_warn (_(".frame outside of .ent"));
18911 demand_empty_rest_of_line ();
18915 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18917 SKIP_WHITESPACE ();
18918 if (*input_line_pointer
++ != ','
18919 || get_absolute_expression_and_terminator (&val
) != ',')
18921 as_warn (_("Bad .frame directive"));
18922 --input_line_pointer
;
18923 demand_empty_rest_of_line ();
18927 cur_proc_ptr
->frame_offset
= val
;
18928 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18930 demand_empty_rest_of_line ();
18934 /* The .fmask and .mask directives. If the mdebug section is present
18935 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18936 embedded targets, s_mips_mask is used so that we can set the PDR
18937 information correctly. We can't use the ecoff routines because they
18938 make reference to the ecoff symbol table (in the mdebug section). */
18941 s_mips_mask (int reg_type
)
18943 if (ECOFF_DEBUGGING
)
18944 s_ignore (reg_type
);
18949 if (cur_proc_ptr
== (procS
*) NULL
)
18951 as_warn (_(".mask/.fmask outside of .ent"));
18952 demand_empty_rest_of_line ();
18956 if (get_absolute_expression_and_terminator (&mask
) != ',')
18958 as_warn (_("Bad .mask/.fmask directive"));
18959 --input_line_pointer
;
18960 demand_empty_rest_of_line ();
18964 off
= get_absolute_expression ();
18966 if (reg_type
== 'F')
18968 cur_proc_ptr
->fpreg_mask
= mask
;
18969 cur_proc_ptr
->fpreg_offset
= off
;
18973 cur_proc_ptr
->reg_mask
= mask
;
18974 cur_proc_ptr
->reg_offset
= off
;
18977 demand_empty_rest_of_line ();
18981 /* A table describing all the processors gas knows about. Names are
18982 matched in the order listed.
18984 To ease comparison, please keep this table in the same order as
18985 gcc's mips_cpu_info_table[]. */
18986 static const struct mips_cpu_info mips_cpu_info_table
[] =
18988 /* Entries for generic ISAs */
18989 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
18990 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
18991 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
18992 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
18993 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
18994 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
18995 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18996 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
18997 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19000 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19001 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19002 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19005 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19008 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19009 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19010 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19011 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19012 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19013 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19014 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19015 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19016 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19017 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19018 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19019 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19020 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19021 /* ST Microelectronics Loongson 2E and 2F cores */
19022 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19023 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19026 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19027 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19028 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19029 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19030 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19031 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19032 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19033 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19034 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19035 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19036 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19037 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19038 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19039 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19040 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19043 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19044 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19045 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19046 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19048 /* MIPS 32 Release 2 */
19049 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19050 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19051 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19052 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19053 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19054 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19055 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19056 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19057 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19058 ISA_MIPS32R2
, CPU_MIPS32R2
},
19059 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19060 ISA_MIPS32R2
, CPU_MIPS32R2
},
19061 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19062 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19063 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19064 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19065 /* Deprecated forms of the above. */
19066 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19067 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19068 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19069 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19070 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19071 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19072 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19073 /* Deprecated forms of the above. */
19074 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19075 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19076 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19077 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19078 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19079 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19080 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19081 /* Deprecated forms of the above. */
19082 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19083 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19084 /* 34Kn is a 34kc without DSP. */
19085 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19086 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19087 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19088 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19089 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19090 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19091 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19092 /* Deprecated forms of the above. */
19093 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19094 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19095 /* 1004K cores are multiprocessor versions of the 34K. */
19096 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19097 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19098 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19099 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19102 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19103 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19104 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19105 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19107 /* Broadcom SB-1 CPU core */
19108 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19109 /* Broadcom SB-1A CPU core */
19110 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19112 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19114 /* MIPS 64 Release 2 */
19116 /* Cavium Networks Octeon CPU core */
19117 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19118 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19119 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19122 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19125 XLP is mostly like XLR, with the prominent exception that it is
19126 MIPS64R2 rather than MIPS64. */
19127 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19130 { NULL
, 0, 0, 0, 0 }
19134 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19135 with a final "000" replaced by "k". Ignore case.
19137 Note: this function is shared between GCC and GAS. */
19140 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19142 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19143 given
++, canonical
++;
19145 return ((*given
== 0 && *canonical
== 0)
19146 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19150 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19151 CPU name. We've traditionally allowed a lot of variation here.
19153 Note: this function is shared between GCC and GAS. */
19156 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19158 /* First see if the name matches exactly, or with a final "000"
19159 turned into "k". */
19160 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19163 /* If not, try comparing based on numerical designation alone.
19164 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19165 if (TOLOWER (*given
) == 'r')
19167 if (!ISDIGIT (*given
))
19170 /* Skip over some well-known prefixes in the canonical name,
19171 hoping to find a number there too. */
19172 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19174 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19176 else if (TOLOWER (canonical
[0]) == 'r')
19179 return mips_strict_matching_cpu_name_p (canonical
, given
);
19183 /* Parse an option that takes the name of a processor as its argument.
19184 OPTION is the name of the option and CPU_STRING is the argument.
19185 Return the corresponding processor enumeration if the CPU_STRING is
19186 recognized, otherwise report an error and return null.
19188 A similar function exists in GCC. */
19190 static const struct mips_cpu_info
*
19191 mips_parse_cpu (const char *option
, const char *cpu_string
)
19193 const struct mips_cpu_info
*p
;
19195 /* 'from-abi' selects the most compatible architecture for the given
19196 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19197 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19198 version. Look first at the -mgp options, if given, otherwise base
19199 the choice on MIPS_DEFAULT_64BIT.
19201 Treat NO_ABI like the EABIs. One reason to do this is that the
19202 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19203 architecture. This code picks MIPS I for 'mips' and MIPS III for
19204 'mips64', just as we did in the days before 'from-abi'. */
19205 if (strcasecmp (cpu_string
, "from-abi") == 0)
19207 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19208 return mips_cpu_info_from_isa (ISA_MIPS1
);
19210 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19211 return mips_cpu_info_from_isa (ISA_MIPS3
);
19213 if (file_mips_gp32
>= 0)
19214 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19216 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19221 /* 'default' has traditionally been a no-op. Probably not very useful. */
19222 if (strcasecmp (cpu_string
, "default") == 0)
19225 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19226 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19229 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19233 /* Return the canonical processor information for ISA (a member of the
19234 ISA_MIPS* enumeration). */
19236 static const struct mips_cpu_info
*
19237 mips_cpu_info_from_isa (int isa
)
19241 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19242 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19243 && isa
== mips_cpu_info_table
[i
].isa
)
19244 return (&mips_cpu_info_table
[i
]);
19249 static const struct mips_cpu_info
*
19250 mips_cpu_info_from_arch (int arch
)
19254 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19255 if (arch
== mips_cpu_info_table
[i
].cpu
)
19256 return (&mips_cpu_info_table
[i
]);
19262 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19266 fprintf (stream
, "%24s", "");
19271 fprintf (stream
, ", ");
19275 if (*col_p
+ strlen (string
) > 72)
19277 fprintf (stream
, "\n%24s", "");
19281 fprintf (stream
, "%s", string
);
19282 *col_p
+= strlen (string
);
19288 md_show_usage (FILE *stream
)
19293 fprintf (stream
, _("\
19295 -EB generate big endian output\n\
19296 -EL generate little endian output\n\
19297 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19298 -G NUM allow referencing objects up to NUM bytes\n\
19299 implicitly with the gp register [default 8]\n"));
19300 fprintf (stream
, _("\
19301 -mips1 generate MIPS ISA I instructions\n\
19302 -mips2 generate MIPS ISA II instructions\n\
19303 -mips3 generate MIPS ISA III instructions\n\
19304 -mips4 generate MIPS ISA IV instructions\n\
19305 -mips5 generate MIPS ISA V instructions\n\
19306 -mips32 generate MIPS32 ISA instructions\n\
19307 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19308 -mips64 generate MIPS64 ISA instructions\n\
19309 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19310 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19314 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19315 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19316 show (stream
, "from-abi", &column
, &first
);
19317 fputc ('\n', stream
);
19319 fprintf (stream
, _("\
19320 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19321 -no-mCPU don't generate code specific to CPU.\n\
19322 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19326 show (stream
, "3900", &column
, &first
);
19327 show (stream
, "4010", &column
, &first
);
19328 show (stream
, "4100", &column
, &first
);
19329 show (stream
, "4650", &column
, &first
);
19330 fputc ('\n', stream
);
19332 fprintf (stream
, _("\
19333 -mips16 generate mips16 instructions\n\
19334 -no-mips16 do not generate mips16 instructions\n"));
19335 fprintf (stream
, _("\
19336 -mmicromips generate microMIPS instructions\n\
19337 -mno-micromips do not generate microMIPS instructions\n"));
19338 fprintf (stream
, _("\
19339 -msmartmips generate smartmips instructions\n\
19340 -mno-smartmips do not generate smartmips instructions\n"));
19341 fprintf (stream
, _("\
19342 -mdsp generate DSP instructions\n\
19343 -mno-dsp do not generate DSP instructions\n"));
19344 fprintf (stream
, _("\
19345 -mdspr2 generate DSP R2 instructions\n\
19346 -mno-dspr2 do not generate DSP R2 instructions\n"));
19347 fprintf (stream
, _("\
19348 -mmt generate MT instructions\n\
19349 -mno-mt do not generate MT instructions\n"));
19350 fprintf (stream
, _("\
19351 -mmcu generate MCU instructions\n\
19352 -mno-mcu do not generate MCU instructions\n"));
19353 fprintf (stream
, _("\
19354 -mvirt generate Virtualization instructions\n\
19355 -mno-virt do not generate Virtualization instructions\n"));
19356 fprintf (stream
, _("\
19357 -minsn32 only generate 32-bit microMIPS instructions\n\
19358 -mno-insn32 generate all microMIPS instructions\n"));
19359 fprintf (stream
, _("\
19360 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19361 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19362 -mfix-vr4120 work around certain VR4120 errata\n\
19363 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19364 -mfix-24k insert a nop after ERET and DERET instructions\n\
19365 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19366 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19367 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19368 -msym32 assume all symbols have 32-bit values\n\
19369 -O0 remove unneeded NOPs, do not swap branches\n\
19370 -O remove unneeded NOPs and swap branches\n\
19371 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19372 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19373 fprintf (stream
, _("\
19374 -mhard-float allow floating-point instructions\n\
19375 -msoft-float do not allow floating-point instructions\n\
19376 -msingle-float only allow 32-bit floating-point operations\n\
19377 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19378 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19379 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19380 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19384 show (stream
, "legacy", &column
, &first
);
19385 show (stream
, "2008", &column
, &first
);
19387 fputc ('\n', stream
);
19389 fprintf (stream
, _("\
19390 -KPIC, -call_shared generate SVR4 position independent code\n\
19391 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19392 -mvxworks-pic generate VxWorks position independent code\n\
19393 -non_shared do not generate code that can operate with DSOs\n\
19394 -xgot assume a 32 bit GOT\n\
19395 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19396 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19397 position dependent (non shared) code\n\
19398 -mabi=ABI create ABI conformant object file for:\n"));
19402 show (stream
, "32", &column
, &first
);
19403 show (stream
, "o64", &column
, &first
);
19404 show (stream
, "n32", &column
, &first
);
19405 show (stream
, "64", &column
, &first
);
19406 show (stream
, "eabi", &column
, &first
);
19408 fputc ('\n', stream
);
19410 fprintf (stream
, _("\
19411 -32 create o32 ABI object file (default)\n\
19412 -n32 create n32 ABI object file\n\
19413 -64 create 64 ABI object file\n"));
19418 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19420 if (HAVE_64BIT_SYMBOLS
)
19421 return dwarf2_format_64bit_irix
;
19423 return dwarf2_format_32bit
;
19428 mips_dwarf2_addr_size (void)
19430 if (HAVE_64BIT_OBJECTS
)
19436 /* Standard calling conventions leave the CFA at SP on entry. */
19438 mips_cfi_frame_initial_instructions (void)
19440 cfi_add_CFA_def_cfa_register (SP
);
19444 tc_mips_regname_to_dw2regnum (char *regname
)
19446 unsigned int regnum
= -1;
19449 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))