1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occured in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
196 /* Whether we are assembling for the mips16 processor. 0 if we are
197 not, 1 if we are, and -1 if the value has not been initialized.
198 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
199 -nomips16 command line options, and the default CPU. */
201 /* Non-zero if we should not reorder instructions. Changed by `.set
202 reorder' and `.set noreorder'. */
204 /* Non-zero if we should not permit the $at ($1) register to be used
205 in instructions. Changed by `.set at' and `.set noat'. */
207 /* Non-zero if we should warn when a macro instruction expands into
208 more than one machine instruction. Changed by `.set nomacro' and
210 int warn_about_macros
;
211 /* Non-zero if we should not move instructions. Changed by `.set
212 move', `.set volatile', `.set nomove', and `.set novolatile'. */
214 /* Non-zero if we should not optimize branches by moving the target
215 of the branch into the delay slot. Actually, we don't perform
216 this optimization anyhow. Changed by `.set bopt' and `.set
219 /* Non-zero if we should not autoextend mips16 instructions.
220 Changed by `.set autoextend' and `.set noautoextend'. */
222 /* Restrict general purpose registers and floating point registers
223 to 32 bit. This is initially determined when -mgp32 or -mfp32
224 is passed but can changed if the assembler code uses .set mipsN. */
227 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
228 command line option, and the default CPU. */
230 /* True if ".set sym32" is in effect. */
234 /* True if -mgp32 was passed. */
235 static int file_mips_gp32
= -1;
237 /* True if -mfp32 was passed. */
238 static int file_mips_fp32
= -1;
240 /* This is the struct we use to hold the current set of options. Note
241 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
242 -1 to indicate that they have not been initialized. */
244 static struct mips_set_options mips_opts
=
246 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
249 /* These variables are filled in with the masks of registers used.
250 The object format code reads them and puts them in the appropriate
252 unsigned long mips_gprmask
;
253 unsigned long mips_cprmask
[4];
255 /* MIPS ISA we are using for this output file. */
256 static int file_mips_isa
= ISA_UNKNOWN
;
258 /* True if -mips16 was passed or implied by arguments passed on the
259 command line (e.g., by -march). */
260 static int file_ase_mips16
;
262 /* True if -mips3d was passed or implied by arguments passed on the
263 command line (e.g., by -march). */
264 static int file_ase_mips3d
;
266 /* True if -mdmx was passed or implied by arguments passed on the
267 command line (e.g., by -march). */
268 static int file_ase_mdmx
;
270 /* The argument of the -march= flag. The architecture we are assembling. */
271 static int file_mips_arch
= CPU_UNKNOWN
;
272 static const char *mips_arch_string
;
274 /* The argument of the -mtune= flag. The architecture for which we
276 static int mips_tune
= CPU_UNKNOWN
;
277 static const char *mips_tune_string
;
279 /* True when generating 32-bit code for a 64-bit processor. */
280 static int mips_32bitmode
= 0;
282 /* True if the given ABI requires 32-bit registers. */
283 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
285 /* Likewise 64-bit registers. */
286 #define ABI_NEEDS_64BIT_REGS(ABI) \
288 || (ABI) == N64_ABI \
291 /* Return true if ISA supports 64 bit gp register instructions. */
292 #define ISA_HAS_64BIT_REGS(ISA) ( \
294 || (ISA) == ISA_MIPS4 \
295 || (ISA) == ISA_MIPS5 \
296 || (ISA) == ISA_MIPS64 \
297 || (ISA) == ISA_MIPS64R2 \
300 /* Return true if ISA supports 64-bit right rotate (dror et al.)
302 #define ISA_HAS_DROR(ISA) ( \
303 (ISA) == ISA_MIPS64R2 \
306 /* Return true if ISA supports 32-bit right rotate (ror et al.)
308 #define ISA_HAS_ROR(ISA) ( \
309 (ISA) == ISA_MIPS32R2 \
310 || (ISA) == ISA_MIPS64R2 \
313 #define HAVE_32BIT_GPRS \
314 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
316 #define HAVE_32BIT_FPRS \
317 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
319 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
320 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
322 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
324 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
326 /* True if relocations are stored in-place. */
327 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
329 /* The ABI-derived address size. */
330 #define HAVE_64BIT_ADDRESSES \
331 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
332 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
334 /* The size of symbolic constants (i.e., expressions of the form
335 "SYMBOL" or "SYMBOL + OFFSET"). */
336 #define HAVE_32BIT_SYMBOLS \
337 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
338 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
340 /* Addresses are loaded in different ways, depending on the address size
341 in use. The n32 ABI Documentation also mandates the use of additions
342 with overflow checking, but existing implementations don't follow it. */
343 #define ADDRESS_ADD_INSN \
344 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
346 #define ADDRESS_ADDI_INSN \
347 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
349 #define ADDRESS_LOAD_INSN \
350 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
352 #define ADDRESS_STORE_INSN \
353 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
355 /* Return true if the given CPU supports the MIPS16 ASE. */
356 #define CPU_HAS_MIPS16(cpu) \
357 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
358 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
360 /* Return true if the given CPU supports the MIPS3D ASE. */
361 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
364 /* Return true if the given CPU supports the MDMX ASE. */
365 #define CPU_HAS_MDMX(cpu) (FALSE \
368 /* True if CPU has a dror instruction. */
369 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
371 /* True if CPU has a ror instruction. */
372 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
374 /* True if mflo and mfhi can be immediately followed by instructions
375 which write to the HI and LO registers.
377 According to MIPS specifications, MIPS ISAs I, II, and III need
378 (at least) two instructions between the reads of HI/LO and
379 instructions which write them, and later ISAs do not. Contradicting
380 the MIPS specifications, some MIPS IV processor user manuals (e.g.
381 the UM for the NEC Vr5000) document needing the instructions between
382 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
383 MIPS64 and later ISAs to have the interlocks, plus any specific
384 earlier-ISA CPUs for which CPU documentation declares that the
385 instructions are really interlocked. */
386 #define hilo_interlocks \
387 (mips_opts.isa == ISA_MIPS32 \
388 || mips_opts.isa == ISA_MIPS32R2 \
389 || mips_opts.isa == ISA_MIPS64 \
390 || mips_opts.isa == ISA_MIPS64R2 \
391 || mips_opts.arch == CPU_R4010 \
392 || mips_opts.arch == CPU_R10000 \
393 || mips_opts.arch == CPU_R12000 \
394 || mips_opts.arch == CPU_RM7000 \
395 || mips_opts.arch == CPU_VR5500 \
398 /* Whether the processor uses hardware interlocks to protect reads
399 from the GPRs after they are loaded from memory, and thus does not
400 require nops to be inserted. This applies to instructions marked
401 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
403 #define gpr_interlocks \
404 (mips_opts.isa != ISA_MIPS1 \
405 || mips_opts.arch == CPU_R3900)
407 /* Whether the processor uses hardware interlocks to avoid delays
408 required by coprocessor instructions, and thus does not require
409 nops to be inserted. This applies to instructions marked
410 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
411 between instructions marked INSN_WRITE_COND_CODE and ones marked
412 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
413 levels I, II, and III. */
414 /* Itbl support may require additional care here. */
415 #define cop_interlocks \
416 ((mips_opts.isa != ISA_MIPS1 \
417 && mips_opts.isa != ISA_MIPS2 \
418 && mips_opts.isa != ISA_MIPS3) \
419 || mips_opts.arch == CPU_R4300 \
422 /* Whether the processor uses hardware interlocks to protect reads
423 from coprocessor registers after they are loaded from memory, and
424 thus does not require nops to be inserted. This applies to
425 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
426 requires at MIPS ISA level I. */
427 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
429 /* Is this a mfhi or mflo instruction? */
430 #define MF_HILO_INSN(PINFO) \
431 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
433 /* MIPS PIC level. */
435 enum mips_pic_level mips_pic
;
437 /* 1 if we should generate 32 bit offsets from the $gp register in
438 SVR4_PIC mode. Currently has no meaning in other modes. */
439 static int mips_big_got
= 0;
441 /* 1 if trap instructions should used for overflow rather than break
443 static int mips_trap
= 0;
445 /* 1 if double width floating point constants should not be constructed
446 by assembling two single width halves into two single width floating
447 point registers which just happen to alias the double width destination
448 register. On some architectures this aliasing can be disabled by a bit
449 in the status register, and the setting of this bit cannot be determined
450 automatically at assemble time. */
451 static int mips_disable_float_construction
;
453 /* Non-zero if any .set noreorder directives were used. */
455 static int mips_any_noreorder
;
457 /* Non-zero if nops should be inserted when the register referenced in
458 an mfhi/mflo instruction is read in the next two instructions. */
459 static int mips_7000_hilo_fix
;
461 /* The size of the small data section. */
462 static unsigned int g_switch_value
= 8;
463 /* Whether the -G option was used. */
464 static int g_switch_seen
= 0;
469 /* If we can determine in advance that GP optimization won't be
470 possible, we can skip the relaxation stuff that tries to produce
471 GP-relative references. This makes delay slot optimization work
474 This function can only provide a guess, but it seems to work for
475 gcc output. It needs to guess right for gcc, otherwise gcc
476 will put what it thinks is a GP-relative instruction in a branch
479 I don't know if a fix is needed for the SVR4_PIC mode. I've only
480 fixed it for the non-PIC mode. KR 95/04/07 */
481 static int nopic_need_relax (symbolS
*, int);
483 /* handle of the OPCODE hash table */
484 static struct hash_control
*op_hash
= NULL
;
486 /* The opcode hash table we use for the mips16. */
487 static struct hash_control
*mips16_op_hash
= NULL
;
489 /* This array holds the chars that always start a comment. If the
490 pre-processor is disabled, these aren't very useful */
491 const char comment_chars
[] = "#";
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output */
496 /* Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output. */
499 /* Also note that C style comments are always supported. */
500 const char line_comment_chars
[] = "#";
502 /* This array holds machine specific line separator characters. */
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point nums */
506 const char EXP_CHARS
[] = "eE";
508 /* Chars that mean this number is a floating point constant */
511 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
513 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
514 changed in read.c . Ideally it shouldn't have to know about it at all,
515 but nothing is ideal around here.
518 static char *insn_error
;
520 static int auto_align
= 1;
522 /* When outputting SVR4 PIC code, the assembler needs to know the
523 offset in the stack frame from which to restore the $gp register.
524 This is set by the .cprestore pseudo-op, and saved in this
526 static offsetT mips_cprestore_offset
= -1;
528 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
529 more optimizations, it can use a register value instead of a memory-saved
530 offset and even an other register than $gp as global pointer. */
531 static offsetT mips_cpreturn_offset
= -1;
532 static int mips_cpreturn_register
= -1;
533 static int mips_gp_register
= GP
;
534 static int mips_gprel_offset
= 0;
536 /* Whether mips_cprestore_offset has been set in the current function
537 (or whether it has already been warned about, if not). */
538 static int mips_cprestore_valid
= 0;
540 /* This is the register which holds the stack frame, as set by the
541 .frame pseudo-op. This is needed to implement .cprestore. */
542 static int mips_frame_reg
= SP
;
544 /* Whether mips_frame_reg has been set in the current function
545 (or whether it has already been warned about, if not). */
546 static int mips_frame_reg_valid
= 0;
548 /* To output NOP instructions correctly, we need to keep information
549 about the previous two instructions. */
551 /* Whether we are optimizing. The default value of 2 means to remove
552 unneeded NOPs and swap branch instructions when possible. A value
553 of 1 means to not swap branches. A value of 0 means to always
555 static int mips_optimize
= 2;
557 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
558 equivalent to seeing no -g option at all. */
559 static int mips_debug
= 0;
561 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
562 #define MAX_VR4130_NOPS 4
564 /* The maximum number of NOPs needed to fill delay slots. */
565 #define MAX_DELAY_NOPS 2
567 /* The maximum number of NOPs needed for any purpose. */
570 /* A list of previous instructions, with index 0 being the most recent.
571 We need to look back MAX_NOPS instructions when filling delay slots
572 or working around processor errata. We need to look back one
573 instruction further if we're thinking about using history[0] to
574 fill a branch delay slot. */
575 static struct mips_cl_insn history
[1 + MAX_NOPS
];
577 /* Nop instructions used by emit_nop. */
578 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
580 /* The appropriate nop for the current mode. */
581 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
583 /* If this is set, it points to a frag holding nop instructions which
584 were inserted before the start of a noreorder section. If those
585 nops turn out to be unnecessary, the size of the frag can be
587 static fragS
*prev_nop_frag
;
589 /* The number of nop instructions we created in prev_nop_frag. */
590 static int prev_nop_frag_holds
;
592 /* The number of nop instructions that we know we need in
594 static int prev_nop_frag_required
;
596 /* The number of instructions we've seen since prev_nop_frag. */
597 static int prev_nop_frag_since
;
599 /* For ECOFF and ELF, relocations against symbols are done in two
600 parts, with a HI relocation and a LO relocation. Each relocation
601 has only 16 bits of space to store an addend. This means that in
602 order for the linker to handle carries correctly, it must be able
603 to locate both the HI and the LO relocation. This means that the
604 relocations must appear in order in the relocation table.
606 In order to implement this, we keep track of each unmatched HI
607 relocation. We then sort them so that they immediately precede the
608 corresponding LO relocation. */
613 struct mips_hi_fixup
*next
;
616 /* The section this fixup is in. */
620 /* The list of unmatched HI relocs. */
622 static struct mips_hi_fixup
*mips_hi_fixup_list
;
624 /* The frag containing the last explicit relocation operator.
625 Null if explicit relocations have not been used. */
627 static fragS
*prev_reloc_op_frag
;
629 /* Map normal MIPS register numbers to mips16 register numbers. */
631 #define X ILLEGAL_REG
632 static const int mips32_to_16_reg_map
[] =
634 X
, X
, 2, 3, 4, 5, 6, 7,
635 X
, X
, X
, X
, X
, X
, X
, X
,
636 0, 1, X
, X
, X
, X
, X
, X
,
637 X
, X
, X
, X
, X
, X
, X
, X
641 /* Map mips16 register numbers to normal MIPS register numbers. */
643 static const unsigned int mips16_to_32_reg_map
[] =
645 16, 17, 2, 3, 4, 5, 6, 7
648 /* Classifies the kind of instructions we're interested in when
649 implementing -mfix-vr4120. */
650 enum fix_vr4120_class
{
657 NUM_FIX_VR4120_CLASSES
660 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
661 there must be at least one other instruction between an instruction
662 of type X and an instruction of type Y. */
663 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
665 /* True if -mfix-vr4120 is in force. */
666 static int mips_fix_vr4120
;
668 /* ...likewise -mfix-vr4130. */
669 static int mips_fix_vr4130
;
671 /* We don't relax branches by default, since this causes us to expand
672 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
673 fail to compute the offset before expanding the macro to the most
674 efficient expansion. */
676 static int mips_relax_branch
;
678 /* The expansion of many macros depends on the type of symbol that
679 they refer to. For example, when generating position-dependent code,
680 a macro that refers to a symbol may have two different expansions,
681 one which uses GP-relative addresses and one which uses absolute
682 addresses. When generating SVR4-style PIC, a macro may have
683 different expansions for local and global symbols.
685 We handle these situations by generating both sequences and putting
686 them in variant frags. In position-dependent code, the first sequence
687 will be the GP-relative one and the second sequence will be the
688 absolute one. In SVR4 PIC, the first sequence will be for global
689 symbols and the second will be for local symbols.
691 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
692 SECOND are the lengths of the two sequences in bytes. These fields
693 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
694 the subtype has the following flags:
697 Set if it has been decided that we should use the second
698 sequence instead of the first.
701 Set in the first variant frag if the macro's second implementation
702 is longer than its first. This refers to the macro as a whole,
703 not an individual relaxation.
706 Set in the first variant frag if the macro appeared in a .set nomacro
707 block and if one alternative requires a warning but the other does not.
710 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
713 The frag's "opcode" points to the first fixup for relaxable code.
715 Relaxable macros are generated using a sequence such as:
717 relax_start (SYMBOL);
718 ... generate first expansion ...
720 ... generate second expansion ...
723 The code and fixups for the unwanted alternative are discarded
724 by md_convert_frag. */
725 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
727 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
728 #define RELAX_SECOND(X) ((X) & 0xff)
729 #define RELAX_USE_SECOND 0x10000
730 #define RELAX_SECOND_LONGER 0x20000
731 #define RELAX_NOMACRO 0x40000
732 #define RELAX_DELAY_SLOT 0x80000
734 /* Branch without likely bit. If label is out of range, we turn:
736 beq reg1, reg2, label
746 with the following opcode replacements:
753 bltzal <-> bgezal (with jal label instead of j label)
755 Even though keeping the delay slot instruction in the delay slot of
756 the branch would be more efficient, it would be very tricky to do
757 correctly, because we'd have to introduce a variable frag *after*
758 the delay slot instruction, and expand that instead. Let's do it
759 the easy way for now, even if the branch-not-taken case now costs
760 one additional instruction. Out-of-range branches are not supposed
761 to be common, anyway.
763 Branch likely. If label is out of range, we turn:
765 beql reg1, reg2, label
766 delay slot (annulled if branch not taken)
775 delay slot (executed only if branch taken)
778 It would be possible to generate a shorter sequence by losing the
779 likely bit, generating something like:
784 delay slot (executed only if branch taken)
796 bltzall -> bgezal (with jal label instead of j label)
797 bgezall -> bltzal (ditto)
800 but it's not clear that it would actually improve performance. */
801 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
804 | ((toofar) ? 1 : 0) \
806 | ((likely) ? 4 : 0) \
807 | ((uncond) ? 8 : 0)))
808 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
809 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
810 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
811 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
812 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
814 /* For mips16 code, we use an entirely different form of relaxation.
815 mips16 supports two versions of most instructions which take
816 immediate values: a small one which takes some small value, and a
817 larger one which takes a 16 bit value. Since branches also follow
818 this pattern, relaxing these values is required.
820 We can assemble both mips16 and normal MIPS code in a single
821 object. Therefore, we need to support this type of relaxation at
822 the same time that we support the relaxation described above. We
823 use the high bit of the subtype field to distinguish these cases.
825 The information we store for this type of relaxation is the
826 argument code found in the opcode file for this relocation, whether
827 the user explicitly requested a small or extended form, and whether
828 the relocation is in a jump or jal delay slot. That tells us the
829 size of the value, and how it should be stored. We also store
830 whether the fragment is considered to be extended or not. We also
831 store whether this is known to be a branch to a different section,
832 whether we have tried to relax this frag yet, and whether we have
833 ever extended a PC relative fragment because of a shift count. */
834 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
837 | ((small) ? 0x100 : 0) \
838 | ((ext) ? 0x200 : 0) \
839 | ((dslot) ? 0x400 : 0) \
840 | ((jal_dslot) ? 0x800 : 0))
841 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
842 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
843 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
844 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
845 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
846 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
847 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
848 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
849 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
850 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
851 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
852 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
854 /* Is the given value a sign-extended 32-bit value? */
855 #define IS_SEXT_32BIT_NUM(x) \
856 (((x) &~ (offsetT) 0x7fffffff) == 0 \
857 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
859 /* Is the given value a sign-extended 16-bit value? */
860 #define IS_SEXT_16BIT_NUM(x) \
861 (((x) &~ (offsetT) 0x7fff) == 0 \
862 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
864 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
865 VALUE << SHIFT. VALUE is evaluated exactly once. */
866 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
867 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
868 | (((VALUE) & (MASK)) << (SHIFT)))
870 /* Extract bits MASK << SHIFT from STRUCT and shift them right
872 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
873 (((STRUCT) >> (SHIFT)) & (MASK))
875 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
876 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
878 include/opcode/mips.h specifies operand fields using the macros
879 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
880 with "MIPS16OP" instead of "OP". */
881 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
882 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
883 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
884 INSERT_BITS ((INSN).insn_opcode, VALUE, \
885 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
887 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
888 #define EXTRACT_OPERAND(FIELD, INSN) \
889 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
890 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
891 EXTRACT_BITS ((INSN).insn_opcode, \
892 MIPS16OP_MASK_##FIELD, \
895 /* Global variables used when generating relaxable macros. See the
896 comment above RELAX_ENCODE for more details about how relaxation
899 /* 0 if we're not emitting a relaxable macro.
900 1 if we're emitting the first of the two relaxation alternatives.
901 2 if we're emitting the second alternative. */
904 /* The first relaxable fixup in the current frag. (In other words,
905 the first fixup that refers to relaxable code.) */
908 /* sizes[0] says how many bytes of the first alternative are stored in
909 the current frag. Likewise sizes[1] for the second alternative. */
910 unsigned int sizes
[2];
912 /* The symbol on which the choice of sequence depends. */
916 /* Global variables used to decide whether a macro needs a warning. */
918 /* True if the macro is in a branch delay slot. */
919 bfd_boolean delay_slot_p
;
921 /* For relaxable macros, sizes[0] is the length of the first alternative
922 in bytes and sizes[1] is the length of the second alternative.
923 For non-relaxable macros, both elements give the length of the
925 unsigned int sizes
[2];
927 /* The first variant frag for this macro. */
929 } mips_macro_warning
;
931 /* Prototypes for static functions. */
933 #define internalError() \
934 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
936 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
938 static void append_insn
939 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
940 static void mips_no_prev_insn (void);
941 static void mips16_macro_build
942 (expressionS
*, const char *, const char *, va_list);
943 static void load_register (int, expressionS
*, int);
944 static void macro_start (void);
945 static void macro_end (void);
946 static void macro (struct mips_cl_insn
* ip
);
947 static void mips16_macro (struct mips_cl_insn
* ip
);
948 #ifdef LOSING_COMPILER
949 static void macro2 (struct mips_cl_insn
* ip
);
951 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
952 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
953 static void mips16_immed
954 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
955 unsigned long *, bfd_boolean
*, unsigned short *);
956 static size_t my_getSmallExpression
957 (expressionS
*, bfd_reloc_code_real_type
*, char *);
958 static void my_getExpression (expressionS
*, char *);
959 static void s_align (int);
960 static void s_change_sec (int);
961 static void s_change_section (int);
962 static void s_cons (int);
963 static void s_float_cons (int);
964 static void s_mips_globl (int);
965 static void s_option (int);
966 static void s_mipsset (int);
967 static void s_abicalls (int);
968 static void s_cpload (int);
969 static void s_cpsetup (int);
970 static void s_cplocal (int);
971 static void s_cprestore (int);
972 static void s_cpreturn (int);
973 static void s_gpvalue (int);
974 static void s_gpword (int);
975 static void s_gpdword (int);
976 static void s_cpadd (int);
977 static void s_insn (int);
978 static void md_obj_begin (void);
979 static void md_obj_end (void);
980 static void s_mips_ent (int);
981 static void s_mips_end (int);
982 static void s_mips_frame (int);
983 static void s_mips_mask (int reg_type
);
984 static void s_mips_stab (int);
985 static void s_mips_weakext (int);
986 static void s_mips_file (int);
987 static void s_mips_loc (int);
988 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
989 static int relaxed_branch_length (fragS
*, asection
*, int);
990 static int validate_mips_insn (const struct mips_opcode
*);
992 /* Table and functions used to map between CPU/ISA names, and
993 ISA levels, and CPU numbers. */
997 const char *name
; /* CPU or ISA name. */
998 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
999 int isa
; /* ISA level. */
1000 int cpu
; /* CPU number (default CPU if ISA). */
1003 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1004 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1005 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1009 The following pseudo-ops from the Kane and Heinrich MIPS book
1010 should be defined here, but are currently unsupported: .alias,
1011 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1013 The following pseudo-ops from the Kane and Heinrich MIPS book are
1014 specific to the type of debugging information being generated, and
1015 should be defined by the object format: .aent, .begin, .bend,
1016 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1019 The following pseudo-ops from the Kane and Heinrich MIPS book are
1020 not MIPS CPU specific, but are also not specific to the object file
1021 format. This file is probably the best place to define them, but
1022 they are not currently supported: .asm0, .endr, .lab, .repeat,
1025 static const pseudo_typeS mips_pseudo_table
[] =
1027 /* MIPS specific pseudo-ops. */
1028 {"option", s_option
, 0},
1029 {"set", s_mipsset
, 0},
1030 {"rdata", s_change_sec
, 'r'},
1031 {"sdata", s_change_sec
, 's'},
1032 {"livereg", s_ignore
, 0},
1033 {"abicalls", s_abicalls
, 0},
1034 {"cpload", s_cpload
, 0},
1035 {"cpsetup", s_cpsetup
, 0},
1036 {"cplocal", s_cplocal
, 0},
1037 {"cprestore", s_cprestore
, 0},
1038 {"cpreturn", s_cpreturn
, 0},
1039 {"gpvalue", s_gpvalue
, 0},
1040 {"gpword", s_gpword
, 0},
1041 {"gpdword", s_gpdword
, 0},
1042 {"cpadd", s_cpadd
, 0},
1043 {"insn", s_insn
, 0},
1045 /* Relatively generic pseudo-ops that happen to be used on MIPS
1047 {"asciiz", stringer
, 1},
1048 {"bss", s_change_sec
, 'b'},
1050 {"half", s_cons
, 1},
1051 {"dword", s_cons
, 3},
1052 {"weakext", s_mips_weakext
, 0},
1054 /* These pseudo-ops are defined in read.c, but must be overridden
1055 here for one reason or another. */
1056 {"align", s_align
, 0},
1057 {"byte", s_cons
, 0},
1058 {"data", s_change_sec
, 'd'},
1059 {"double", s_float_cons
, 'd'},
1060 {"float", s_float_cons
, 'f'},
1061 {"globl", s_mips_globl
, 0},
1062 {"global", s_mips_globl
, 0},
1063 {"hword", s_cons
, 1},
1065 {"long", s_cons
, 2},
1066 {"octa", s_cons
, 4},
1067 {"quad", s_cons
, 3},
1068 {"section", s_change_section
, 0},
1069 {"short", s_cons
, 1},
1070 {"single", s_float_cons
, 'f'},
1071 {"stabn", s_mips_stab
, 'n'},
1072 {"text", s_change_sec
, 't'},
1073 {"word", s_cons
, 2},
1075 { "extern", ecoff_directive_extern
, 0},
1080 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1082 /* These pseudo-ops should be defined by the object file format.
1083 However, a.out doesn't support them, so we have versions here. */
1084 {"aent", s_mips_ent
, 1},
1085 {"bgnb", s_ignore
, 0},
1086 {"end", s_mips_end
, 0},
1087 {"endb", s_ignore
, 0},
1088 {"ent", s_mips_ent
, 0},
1089 {"file", s_mips_file
, 0},
1090 {"fmask", s_mips_mask
, 'F'},
1091 {"frame", s_mips_frame
, 0},
1092 {"loc", s_mips_loc
, 0},
1093 {"mask", s_mips_mask
, 'R'},
1094 {"verstamp", s_ignore
, 0},
1098 extern void pop_insert (const pseudo_typeS
*);
1101 mips_pop_insert (void)
1103 pop_insert (mips_pseudo_table
);
1104 if (! ECOFF_DEBUGGING
)
1105 pop_insert (mips_nonecoff_pseudo_table
);
1108 /* Symbols labelling the current insn. */
1110 struct insn_label_list
1112 struct insn_label_list
*next
;
1116 static struct insn_label_list
*insn_labels
;
1117 static struct insn_label_list
*free_insn_labels
;
1119 static void mips_clear_insn_labels (void);
1122 mips_clear_insn_labels (void)
1124 register struct insn_label_list
**pl
;
1126 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1132 static char *expr_end
;
1134 /* Expressions which appear in instructions. These are set by
1137 static expressionS imm_expr
;
1138 static expressionS imm2_expr
;
1139 static expressionS offset_expr
;
1141 /* Relocs associated with imm_expr and offset_expr. */
1143 static bfd_reloc_code_real_type imm_reloc
[3]
1144 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1145 static bfd_reloc_code_real_type offset_reloc
[3]
1146 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1148 /* These are set by mips16_ip if an explicit extension is used. */
1150 static bfd_boolean mips16_small
, mips16_ext
;
1153 /* The pdr segment for per procedure frame/regmask info. Not used for
1156 static segT pdr_seg
;
1159 /* The default target format to use. */
1162 mips_target_format (void)
1164 switch (OUTPUT_FLAVOR
)
1166 case bfd_target_ecoff_flavour
:
1167 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1168 case bfd_target_coff_flavour
:
1170 case bfd_target_elf_flavour
:
1172 /* This is traditional mips. */
1173 return (target_big_endian
1174 ? (HAVE_64BIT_OBJECTS
1175 ? "elf64-tradbigmips"
1177 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1178 : (HAVE_64BIT_OBJECTS
1179 ? "elf64-tradlittlemips"
1181 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1183 return (target_big_endian
1184 ? (HAVE_64BIT_OBJECTS
1187 ? "elf32-nbigmips" : "elf32-bigmips"))
1188 : (HAVE_64BIT_OBJECTS
1189 ? "elf64-littlemips"
1191 ? "elf32-nlittlemips" : "elf32-littlemips")));
1199 /* Return the length of instruction INSN. */
1201 static inline unsigned int
1202 insn_length (const struct mips_cl_insn
*insn
)
1204 if (!mips_opts
.mips16
)
1206 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1209 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1212 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1217 insn
->use_extend
= FALSE
;
1219 insn
->insn_opcode
= mo
->match
;
1222 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1223 insn
->fixp
[i
] = NULL
;
1224 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1225 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1226 insn
->mips16_absolute_jump_p
= 0;
1229 /* Install INSN at the location specified by its "frag" and "where" fields. */
1232 install_insn (const struct mips_cl_insn
*insn
)
1234 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1235 if (!mips_opts
.mips16
)
1236 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1237 else if (insn
->mips16_absolute_jump_p
)
1239 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1240 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1244 if (insn
->use_extend
)
1246 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1249 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1253 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1254 and install the opcode in the new location. */
1257 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1262 insn
->where
= where
;
1263 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1264 if (insn
->fixp
[i
] != NULL
)
1266 insn
->fixp
[i
]->fx_frag
= frag
;
1267 insn
->fixp
[i
]->fx_where
= where
;
1269 install_insn (insn
);
1272 /* Add INSN to the end of the output. */
1275 add_fixed_insn (struct mips_cl_insn
*insn
)
1277 char *f
= frag_more (insn_length (insn
));
1278 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1281 /* Start a variant frag and move INSN to the start of the variant part,
1282 marking it as fixed. The other arguments are as for frag_var. */
1285 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1286 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1288 frag_grow (max_chars
);
1289 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1291 frag_var (rs_machine_dependent
, max_chars
, var
,
1292 subtype
, symbol
, offset
, NULL
);
1295 /* Insert N copies of INSN into the history buffer, starting at
1296 position FIRST. Neither FIRST nor N need to be clipped. */
1299 insert_into_history (unsigned int first
, unsigned int n
,
1300 const struct mips_cl_insn
*insn
)
1302 if (mips_relax
.sequence
!= 2)
1306 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1308 history
[i
] = history
[i
- n
];
1314 /* Emit a nop instruction, recording it in the history buffer. */
1319 add_fixed_insn (NOP_INSN
);
1320 insert_into_history (0, 1, NOP_INSN
);
1323 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1324 the idea is to make it obvious at a glance that each errata is
1328 init_vr4120_conflicts (void)
1330 #define CONFLICT(FIRST, SECOND) \
1331 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1333 /* Errata 21 - [D]DIV[U] after [D]MACC */
1334 CONFLICT (MACC
, DIV
);
1335 CONFLICT (DMACC
, DIV
);
1337 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1338 CONFLICT (DMULT
, DMULT
);
1339 CONFLICT (DMULT
, DMACC
);
1340 CONFLICT (DMACC
, DMULT
);
1341 CONFLICT (DMACC
, DMACC
);
1343 /* Errata 24 - MT{LO,HI} after [D]MACC */
1344 CONFLICT (MACC
, MTHILO
);
1345 CONFLICT (DMACC
, MTHILO
);
1347 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1348 instruction is executed immediately after a MACC or DMACC
1349 instruction, the result of [either instruction] is incorrect." */
1350 CONFLICT (MACC
, MULT
);
1351 CONFLICT (MACC
, DMULT
);
1352 CONFLICT (DMACC
, MULT
);
1353 CONFLICT (DMACC
, DMULT
);
1355 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1356 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1357 DDIV or DDIVU instruction, the result of the MACC or
1358 DMACC instruction is incorrect.". */
1359 CONFLICT (DMULT
, MACC
);
1360 CONFLICT (DMULT
, DMACC
);
1361 CONFLICT (DIV
, MACC
);
1362 CONFLICT (DIV
, DMACC
);
1367 /* This function is called once, at assembler startup time. It should
1368 set up all the tables, etc. that the MD part of the assembler will need. */
1373 register const char *retval
= NULL
;
1377 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1378 as_warn (_("Could not set architecture and machine"));
1380 op_hash
= hash_new ();
1382 for (i
= 0; i
< NUMOPCODES
;)
1384 const char *name
= mips_opcodes
[i
].name
;
1386 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1389 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1390 mips_opcodes
[i
].name
, retval
);
1391 /* Probably a memory allocation problem? Give up now. */
1392 as_fatal (_("Broken assembler. No assembly attempted."));
1396 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1398 if (!validate_mips_insn (&mips_opcodes
[i
]))
1400 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1402 create_insn (&nop_insn
, mips_opcodes
+ i
);
1403 nop_insn
.fixed_p
= 1;
1408 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1411 mips16_op_hash
= hash_new ();
1414 while (i
< bfd_mips16_num_opcodes
)
1416 const char *name
= mips16_opcodes
[i
].name
;
1418 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1420 as_fatal (_("internal: can't hash `%s': %s"),
1421 mips16_opcodes
[i
].name
, retval
);
1424 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1425 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1426 != mips16_opcodes
[i
].match
))
1428 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1429 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1432 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1434 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1435 mips16_nop_insn
.fixed_p
= 1;
1439 while (i
< bfd_mips16_num_opcodes
1440 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1444 as_fatal (_("Broken assembler. No assembly attempted."));
1446 /* We add all the general register names to the symbol table. This
1447 helps us detect invalid uses of them. */
1448 for (i
= 0; i
< 32; i
++)
1452 sprintf (buf
, "$%d", i
);
1453 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1454 &zero_address_frag
));
1456 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1457 &zero_address_frag
));
1458 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1459 &zero_address_frag
));
1460 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1461 &zero_address_frag
));
1462 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1463 &zero_address_frag
));
1464 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1465 &zero_address_frag
));
1466 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1467 &zero_address_frag
));
1468 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1469 &zero_address_frag
));
1470 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1471 &zero_address_frag
));
1472 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1473 &zero_address_frag
));
1475 /* If we don't add these register names to the symbol table, they
1476 may end up being added as regular symbols by operand(), and then
1477 make it to the object file as undefined in case they're not
1478 regarded as local symbols. They're local in o32, since `$' is a
1479 local symbol prefix, but not in n32 or n64. */
1480 for (i
= 0; i
< 8; i
++)
1484 sprintf (buf
, "$fcc%i", i
);
1485 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1486 &zero_address_frag
));
1489 mips_no_prev_insn ();
1492 mips_cprmask
[0] = 0;
1493 mips_cprmask
[1] = 0;
1494 mips_cprmask
[2] = 0;
1495 mips_cprmask
[3] = 0;
1497 /* set the default alignment for the text section (2**2) */
1498 record_alignment (text_section
, 2);
1500 bfd_set_gp_size (stdoutput
, g_switch_value
);
1502 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1504 /* On a native system, sections must be aligned to 16 byte
1505 boundaries. When configured for an embedded ELF target, we
1507 if (strcmp (TARGET_OS
, "elf") != 0)
1509 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1510 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1511 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1514 /* Create a .reginfo section for register masks and a .mdebug
1515 section for debugging information. */
1523 subseg
= now_subseg
;
1525 /* The ABI says this section should be loaded so that the
1526 running program can access it. However, we don't load it
1527 if we are configured for an embedded target */
1528 flags
= SEC_READONLY
| SEC_DATA
;
1529 if (strcmp (TARGET_OS
, "elf") != 0)
1530 flags
|= SEC_ALLOC
| SEC_LOAD
;
1532 if (mips_abi
!= N64_ABI
)
1534 sec
= subseg_new (".reginfo", (subsegT
) 0);
1536 bfd_set_section_flags (stdoutput
, sec
, flags
);
1537 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1540 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1545 /* The 64-bit ABI uses a .MIPS.options section rather than
1546 .reginfo section. */
1547 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1548 bfd_set_section_flags (stdoutput
, sec
, flags
);
1549 bfd_set_section_alignment (stdoutput
, sec
, 3);
1552 /* Set up the option header. */
1554 Elf_Internal_Options opthdr
;
1557 opthdr
.kind
= ODK_REGINFO
;
1558 opthdr
.size
= (sizeof (Elf_External_Options
)
1559 + sizeof (Elf64_External_RegInfo
));
1562 f
= frag_more (sizeof (Elf_External_Options
));
1563 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1564 (Elf_External_Options
*) f
);
1566 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1571 if (ECOFF_DEBUGGING
)
1573 sec
= subseg_new (".mdebug", (subsegT
) 0);
1574 (void) bfd_set_section_flags (stdoutput
, sec
,
1575 SEC_HAS_CONTENTS
| SEC_READONLY
);
1576 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1579 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1581 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1582 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1583 SEC_READONLY
| SEC_RELOC
1585 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1589 subseg_set (seg
, subseg
);
1593 if (! ECOFF_DEBUGGING
)
1596 if (mips_fix_vr4120
)
1597 init_vr4120_conflicts ();
1603 if (! ECOFF_DEBUGGING
)
1608 md_assemble (char *str
)
1610 struct mips_cl_insn insn
;
1611 bfd_reloc_code_real_type unused_reloc
[3]
1612 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1614 imm_expr
.X_op
= O_absent
;
1615 imm2_expr
.X_op
= O_absent
;
1616 offset_expr
.X_op
= O_absent
;
1617 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1618 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1619 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1620 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1621 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1622 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1624 if (mips_opts
.mips16
)
1625 mips16_ip (str
, &insn
);
1628 mips_ip (str
, &insn
);
1629 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1630 str
, insn
.insn_opcode
));
1635 as_bad ("%s `%s'", insn_error
, str
);
1639 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1642 if (mips_opts
.mips16
)
1643 mips16_macro (&insn
);
1650 if (imm_expr
.X_op
!= O_absent
)
1651 append_insn (&insn
, &imm_expr
, imm_reloc
);
1652 else if (offset_expr
.X_op
!= O_absent
)
1653 append_insn (&insn
, &offset_expr
, offset_reloc
);
1655 append_insn (&insn
, NULL
, unused_reloc
);
1659 /* Return true if the given relocation might need a matching %lo().
1660 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1661 applied to local symbols. */
1663 static inline bfd_boolean
1664 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1666 return (HAVE_IN_PLACE_ADDENDS
1667 && (reloc
== BFD_RELOC_HI16_S
1668 || reloc
== BFD_RELOC_MIPS_GOT16
1669 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1672 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1675 static inline bfd_boolean
1676 fixup_has_matching_lo_p (fixS
*fixp
)
1678 return (fixp
->fx_next
!= NULL
1679 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1680 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1681 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1682 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1685 /* See whether instruction IP reads register REG. CLASS is the type
1689 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1690 enum mips_regclass
class)
1692 if (class == MIPS16_REG
)
1694 assert (mips_opts
.mips16
);
1695 reg
= mips16_to_32_reg_map
[reg
];
1696 class = MIPS_GR_REG
;
1699 /* Don't report on general register ZERO, since it never changes. */
1700 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1703 if (class == MIPS_FP_REG
)
1705 assert (! mips_opts
.mips16
);
1706 /* If we are called with either $f0 or $f1, we must check $f0.
1707 This is not optimal, because it will introduce an unnecessary
1708 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1709 need to distinguish reading both $f0 and $f1 or just one of
1710 them. Note that we don't have to check the other way,
1711 because there is no instruction that sets both $f0 and $f1
1712 and requires a delay. */
1713 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1714 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1715 == (reg
&~ (unsigned) 1)))
1717 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1718 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1719 == (reg
&~ (unsigned) 1)))
1722 else if (! mips_opts
.mips16
)
1724 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1725 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1727 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1728 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1733 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1734 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1736 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1737 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1739 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1740 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1743 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1745 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1747 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1749 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1750 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1757 /* This function returns true if modifying a register requires a
1761 reg_needs_delay (unsigned int reg
)
1763 unsigned long prev_pinfo
;
1765 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1766 if (! mips_opts
.noreorder
1767 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1768 && ! gpr_interlocks
)
1769 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1770 && ! cop_interlocks
)))
1772 /* A load from a coprocessor or from memory. All load delays
1773 delay the use of general register rt for one instruction. */
1774 /* Itbl support may require additional care here. */
1775 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1776 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1783 /* Move all labels in insn_labels to the current insertion point. */
1786 mips_move_labels (void)
1788 struct insn_label_list
*l
;
1791 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1793 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1794 symbol_set_frag (l
->label
, frag_now
);
1795 val
= (valueT
) frag_now_fix ();
1796 /* mips16 text labels are stored as odd. */
1797 if (mips_opts
.mips16
)
1799 S_SET_VALUE (l
->label
, val
);
1803 /* Mark instruction labels in mips16 mode. This permits the linker to
1804 handle them specially, such as generating jalx instructions when
1805 needed. We also make them odd for the duration of the assembly, in
1806 order to generate the right sort of code. We will make them even
1807 in the adjust_symtab routine, while leaving them marked. This is
1808 convenient for the debugger and the disassembler. The linker knows
1809 to make them odd again. */
1812 mips16_mark_labels (void)
1814 if (mips_opts
.mips16
)
1816 struct insn_label_list
*l
;
1819 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1822 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1823 S_SET_OTHER (l
->label
, STO_MIPS16
);
1825 val
= S_GET_VALUE (l
->label
);
1827 S_SET_VALUE (l
->label
, val
+ 1);
1832 /* End the current frag. Make it a variant frag and record the
1836 relax_close_frag (void)
1838 mips_macro_warning
.first_frag
= frag_now
;
1839 frag_var (rs_machine_dependent
, 0, 0,
1840 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1841 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1843 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1844 mips_relax
.first_fixup
= 0;
1847 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1848 See the comment above RELAX_ENCODE for more details. */
1851 relax_start (symbolS
*symbol
)
1853 assert (mips_relax
.sequence
== 0);
1854 mips_relax
.sequence
= 1;
1855 mips_relax
.symbol
= symbol
;
1858 /* Start generating the second version of a relaxable sequence.
1859 See the comment above RELAX_ENCODE for more details. */
1864 assert (mips_relax
.sequence
== 1);
1865 mips_relax
.sequence
= 2;
1868 /* End the current relaxable sequence. */
1873 assert (mips_relax
.sequence
== 2);
1874 relax_close_frag ();
1875 mips_relax
.sequence
= 0;
1878 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1879 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1880 by VR4120 errata. */
1883 classify_vr4120_insn (const char *name
)
1885 if (strncmp (name
, "macc", 4) == 0)
1886 return FIX_VR4120_MACC
;
1887 if (strncmp (name
, "dmacc", 5) == 0)
1888 return FIX_VR4120_DMACC
;
1889 if (strncmp (name
, "mult", 4) == 0)
1890 return FIX_VR4120_MULT
;
1891 if (strncmp (name
, "dmult", 5) == 0)
1892 return FIX_VR4120_DMULT
;
1893 if (strstr (name
, "div"))
1894 return FIX_VR4120_DIV
;
1895 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1896 return FIX_VR4120_MTHILO
;
1897 return NUM_FIX_VR4120_CLASSES
;
1900 /* Return the number of instructions that must separate INSN1 and INSN2,
1901 where INSN1 is the earlier instruction. Return the worst-case value
1902 for any INSN2 if INSN2 is null. */
1905 insns_between (const struct mips_cl_insn
*insn1
,
1906 const struct mips_cl_insn
*insn2
)
1908 unsigned long pinfo1
, pinfo2
;
1910 /* This function needs to know which pinfo flags are set for INSN2
1911 and which registers INSN2 uses. The former is stored in PINFO2 and
1912 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1913 will have every flag set and INSN2_USES_REG will always return true. */
1914 pinfo1
= insn1
->insn_mo
->pinfo
;
1915 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1917 #define INSN2_USES_REG(REG, CLASS) \
1918 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1920 /* For most targets, write-after-read dependencies on the HI and LO
1921 registers must be separated by at least two instructions. */
1922 if (!hilo_interlocks
)
1924 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1926 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1930 /* If we're working around r7000 errata, there must be two instructions
1931 between an mfhi or mflo and any instruction that uses the result. */
1932 if (mips_7000_hilo_fix
1933 && MF_HILO_INSN (pinfo1
)
1934 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1937 /* If working around VR4120 errata, check for combinations that need
1938 a single intervening instruction. */
1939 if (mips_fix_vr4120
)
1941 unsigned int class1
, class2
;
1943 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1944 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1948 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1949 if (vr4120_conflicts
[class1
] & (1 << class2
))
1954 if (!mips_opts
.mips16
)
1956 /* Check for GPR or coprocessor load delays. All such delays
1957 are on the RT register. */
1958 /* Itbl support may require additional care here. */
1959 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1960 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1962 know (pinfo1
& INSN_WRITE_GPR_T
);
1963 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1967 /* Check for generic coprocessor hazards.
1969 This case is not handled very well. There is no special
1970 knowledge of CP0 handling, and the coprocessors other than
1971 the floating point unit are not distinguished at all. */
1972 /* Itbl support may require additional care here. FIXME!
1973 Need to modify this to include knowledge about
1974 user specified delays! */
1975 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1976 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1978 /* Handle cases where INSN1 writes to a known general coprocessor
1979 register. There must be a one instruction delay before INSN2
1980 if INSN2 reads that register, otherwise no delay is needed. */
1981 if (pinfo1
& INSN_WRITE_FPR_T
)
1983 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1986 else if (pinfo1
& INSN_WRITE_FPR_S
)
1988 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1993 /* Read-after-write dependencies on the control registers
1994 require a two-instruction gap. */
1995 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1996 && (pinfo2
& INSN_READ_COND_CODE
))
1999 /* We don't know exactly what INSN1 does. If INSN2 is
2000 also a coprocessor instruction, assume there must be
2001 a one instruction gap. */
2002 if (pinfo2
& INSN_COP
)
2007 /* Check for read-after-write dependencies on the coprocessor
2008 control registers in cases where INSN1 does not need a general
2009 coprocessor delay. This means that INSN1 is a floating point
2010 comparison instruction. */
2011 /* Itbl support may require additional care here. */
2012 else if (!cop_interlocks
2013 && (pinfo1
& INSN_WRITE_COND_CODE
)
2014 && (pinfo2
& INSN_READ_COND_CODE
))
2018 #undef INSN2_USES_REG
2023 /* Return the number of nops that would be needed to work around the
2024 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2025 the MAX_VR4130_NOPS instructions described by HISTORY. */
2028 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2029 const struct mips_cl_insn
*insn
)
2033 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2034 are not affected by the errata. */
2036 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2037 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2038 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2041 /* Search for the first MFLO or MFHI. */
2042 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2043 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2045 /* Extract the destination register. */
2046 if (mips_opts
.mips16
)
2047 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2049 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2051 /* No nops are needed if INSN reads that register. */
2052 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2055 /* ...or if any of the intervening instructions do. */
2056 for (j
= 0; j
< i
; j
++)
2057 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2060 return MAX_VR4130_NOPS
- i
;
2065 /* Return the number of nops that would be needed if instruction INSN
2066 immediately followed the MAX_NOPS instructions given by HISTORY,
2067 where HISTORY[0] is the most recent instruction. If INSN is null,
2068 return the worse-case number of nops for any instruction. */
2071 nops_for_insn (const struct mips_cl_insn
*history
,
2072 const struct mips_cl_insn
*insn
)
2074 int i
, nops
, tmp_nops
;
2077 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2078 if (!history
[i
].noreorder_p
)
2080 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2081 if (tmp_nops
> nops
)
2085 if (mips_fix_vr4130
)
2087 tmp_nops
= nops_for_vr4130 (history
, insn
);
2088 if (tmp_nops
> nops
)
2095 /* The variable arguments provide NUM_INSNS extra instructions that
2096 might be added to HISTORY. Return the largest number of nops that
2097 would be needed after the extended sequence. */
2100 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2103 struct mips_cl_insn buffer
[MAX_NOPS
];
2104 struct mips_cl_insn
*cursor
;
2107 va_start (args
, history
);
2108 cursor
= buffer
+ num_insns
;
2109 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2110 while (cursor
> buffer
)
2111 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2113 nops
= nops_for_insn (buffer
, NULL
);
2118 /* Like nops_for_insn, but if INSN is a branch, take into account the
2119 worst-case delay for the branch target. */
2122 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2123 const struct mips_cl_insn
*insn
)
2127 nops
= nops_for_insn (history
, insn
);
2128 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2129 | INSN_COND_BRANCH_DELAY
2130 | INSN_COND_BRANCH_LIKELY
))
2132 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2133 if (tmp_nops
> nops
)
2136 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2138 tmp_nops
= nops_for_sequence (1, history
, insn
);
2139 if (tmp_nops
> nops
)
2145 /* Output an instruction. IP is the instruction information.
2146 ADDRESS_EXPR is an operand of the instruction to be used with
2150 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2151 bfd_reloc_code_real_type
*reloc_type
)
2153 register unsigned long prev_pinfo
, pinfo
;
2154 relax_stateT prev_insn_frag_type
= 0;
2155 bfd_boolean relaxed_branch
= FALSE
;
2157 /* Mark instruction labels in mips16 mode. */
2158 mips16_mark_labels ();
2160 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2161 pinfo
= ip
->insn_mo
->pinfo
;
2163 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2165 /* There are a lot of optimizations we could do that we don't.
2166 In particular, we do not, in general, reorder instructions.
2167 If you use gcc with optimization, it will reorder
2168 instructions and generally do much more optimization then we
2169 do here; repeating all that work in the assembler would only
2170 benefit hand written assembly code, and does not seem worth
2172 int nops
= (mips_optimize
== 0
2173 ? nops_for_insn (history
, NULL
)
2174 : nops_for_insn_or_target (history
, ip
));
2178 unsigned long old_frag_offset
;
2181 old_frag
= frag_now
;
2182 old_frag_offset
= frag_now_fix ();
2184 for (i
= 0; i
< nops
; i
++)
2189 listing_prev_line ();
2190 /* We may be at the start of a variant frag. In case we
2191 are, make sure there is enough space for the frag
2192 after the frags created by listing_prev_line. The
2193 argument to frag_grow here must be at least as large
2194 as the argument to all other calls to frag_grow in
2195 this file. We don't have to worry about being in the
2196 middle of a variant frag, because the variants insert
2197 all needed nop instructions themselves. */
2201 mips_move_labels ();
2203 #ifndef NO_ECOFF_DEBUGGING
2204 if (ECOFF_DEBUGGING
)
2205 ecoff_fix_loc (old_frag
, old_frag_offset
);
2209 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2211 /* Work out how many nops in prev_nop_frag are needed by IP. */
2212 int nops
= nops_for_insn_or_target (history
, ip
);
2213 assert (nops
<= prev_nop_frag_holds
);
2215 /* Enforce NOPS as a minimum. */
2216 if (nops
> prev_nop_frag_required
)
2217 prev_nop_frag_required
= nops
;
2219 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2221 /* Settle for the current number of nops. Update the history
2222 accordingly (for the benefit of any future .set reorder code). */
2223 prev_nop_frag
= NULL
;
2224 insert_into_history (prev_nop_frag_since
,
2225 prev_nop_frag_holds
, NOP_INSN
);
2229 /* Allow this instruction to replace one of the nops that was
2230 tentatively added to prev_nop_frag. */
2231 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2232 prev_nop_frag_holds
--;
2233 prev_nop_frag_since
++;
2238 /* The value passed to dwarf2_emit_insn is the distance between
2239 the beginning of the current instruction and the address that
2240 should be recorded in the debug tables. For MIPS16 debug info
2241 we want to use ISA-encoded addresses, so we pass -1 for an
2242 address higher by one than the current. */
2243 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2246 /* Record the frag type before frag_var. */
2247 if (history
[0].frag
)
2248 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2251 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2252 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2253 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2254 && mips_relax_branch
2255 /* Don't try branch relaxation within .set nomacro, or within
2256 .set noat if we use $at for PIC computations. If it turns
2257 out that the branch was out-of-range, we'll get an error. */
2258 && !mips_opts
.warn_about_macros
2259 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2260 && !mips_opts
.mips16
)
2262 relaxed_branch
= TRUE
;
2263 add_relaxed_insn (ip
, (relaxed_branch_length
2265 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2266 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2269 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2270 pinfo
& INSN_COND_BRANCH_LIKELY
,
2271 pinfo
& INSN_WRITE_GPR_31
,
2273 address_expr
->X_add_symbol
,
2274 address_expr
->X_add_number
);
2275 *reloc_type
= BFD_RELOC_UNUSED
;
2277 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2279 /* We need to set up a variant frag. */
2280 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2281 add_relaxed_insn (ip
, 4, 0,
2283 (*reloc_type
- BFD_RELOC_UNUSED
,
2284 mips16_small
, mips16_ext
,
2285 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2286 history
[0].mips16_absolute_jump_p
),
2287 make_expr_symbol (address_expr
), 0);
2289 else if (mips_opts
.mips16
2291 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2293 /* Make sure there is enough room to swap this instruction with
2294 a following jump instruction. */
2296 add_fixed_insn (ip
);
2300 if (mips_opts
.mips16
2301 && mips_opts
.noreorder
2302 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2303 as_warn (_("extended instruction in delay slot"));
2305 if (mips_relax
.sequence
)
2307 /* If we've reached the end of this frag, turn it into a variant
2308 frag and record the information for the instructions we've
2310 if (frag_room () < 4)
2311 relax_close_frag ();
2312 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2315 if (mips_relax
.sequence
!= 2)
2316 mips_macro_warning
.sizes
[0] += 4;
2317 if (mips_relax
.sequence
!= 1)
2318 mips_macro_warning
.sizes
[1] += 4;
2320 if (mips_opts
.mips16
)
2323 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2325 add_fixed_insn (ip
);
2328 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2330 if (address_expr
->X_op
== O_constant
)
2334 switch (*reloc_type
)
2337 ip
->insn_opcode
|= address_expr
->X_add_number
;
2340 case BFD_RELOC_MIPS_HIGHEST
:
2341 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2342 ip
->insn_opcode
|= tmp
& 0xffff;
2345 case BFD_RELOC_MIPS_HIGHER
:
2346 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2347 ip
->insn_opcode
|= tmp
& 0xffff;
2350 case BFD_RELOC_HI16_S
:
2351 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2352 ip
->insn_opcode
|= tmp
& 0xffff;
2355 case BFD_RELOC_HI16
:
2356 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2359 case BFD_RELOC_UNUSED
:
2360 case BFD_RELOC_LO16
:
2361 case BFD_RELOC_MIPS_GOT_DISP
:
2362 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2365 case BFD_RELOC_MIPS_JMP
:
2366 if ((address_expr
->X_add_number
& 3) != 0)
2367 as_bad (_("jump to misaligned address (0x%lx)"),
2368 (unsigned long) address_expr
->X_add_number
);
2369 if (address_expr
->X_add_number
& ~0xfffffff)
2370 as_bad (_("jump address range overflow (0x%lx)"),
2371 (unsigned long) address_expr
->X_add_number
);
2372 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2375 case BFD_RELOC_MIPS16_JMP
:
2376 if ((address_expr
->X_add_number
& 3) != 0)
2377 as_bad (_("jump to misaligned address (0x%lx)"),
2378 (unsigned long) address_expr
->X_add_number
);
2379 if (address_expr
->X_add_number
& ~0xfffffff)
2380 as_bad (_("jump address range overflow (0x%lx)"),
2381 (unsigned long) address_expr
->X_add_number
);
2383 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2384 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2385 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2388 case BFD_RELOC_16_PCREL_S2
:
2395 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2398 reloc_howto_type
*howto
;
2401 /* In a compound relocation, it is the final (outermost)
2402 operator that determines the relocated field. */
2403 for (i
= 1; i
< 3; i
++)
2404 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2407 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2408 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2409 bfd_get_reloc_size (howto
),
2411 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2414 /* These relocations can have an addend that won't fit in
2415 4 octets for 64bit assembly. */
2417 && ! howto
->partial_inplace
2418 && (reloc_type
[0] == BFD_RELOC_16
2419 || reloc_type
[0] == BFD_RELOC_32
2420 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2421 || reloc_type
[0] == BFD_RELOC_HI16_S
2422 || reloc_type
[0] == BFD_RELOC_LO16
2423 || reloc_type
[0] == BFD_RELOC_GPREL16
2424 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2425 || reloc_type
[0] == BFD_RELOC_GPREL32
2426 || reloc_type
[0] == BFD_RELOC_64
2427 || reloc_type
[0] == BFD_RELOC_CTOR
2428 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2429 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2430 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2431 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2432 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2433 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2434 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2435 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2436 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2437 ip
->fixp
[0]->fx_no_overflow
= 1;
2439 if (mips_relax
.sequence
)
2441 if (mips_relax
.first_fixup
== 0)
2442 mips_relax
.first_fixup
= ip
->fixp
[0];
2444 else if (reloc_needs_lo_p (*reloc_type
))
2446 struct mips_hi_fixup
*hi_fixup
;
2448 /* Reuse the last entry if it already has a matching %lo. */
2449 hi_fixup
= mips_hi_fixup_list
;
2451 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2453 hi_fixup
= ((struct mips_hi_fixup
*)
2454 xmalloc (sizeof (struct mips_hi_fixup
)));
2455 hi_fixup
->next
= mips_hi_fixup_list
;
2456 mips_hi_fixup_list
= hi_fixup
;
2458 hi_fixup
->fixp
= ip
->fixp
[0];
2459 hi_fixup
->seg
= now_seg
;
2462 /* Add fixups for the second and third relocations, if given.
2463 Note that the ABI allows the second relocation to be
2464 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2465 moment we only use RSS_UNDEF, but we could add support
2466 for the others if it ever becomes necessary. */
2467 for (i
= 1; i
< 3; i
++)
2468 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2470 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2471 ip
->fixp
[0]->fx_size
, NULL
, 0,
2472 FALSE
, reloc_type
[i
]);
2474 /* Use fx_tcbit to mark compound relocs. */
2475 ip
->fixp
[0]->fx_tcbit
= 1;
2476 ip
->fixp
[i
]->fx_tcbit
= 1;
2482 /* Update the register mask information. */
2483 if (! mips_opts
.mips16
)
2485 if (pinfo
& INSN_WRITE_GPR_D
)
2486 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2487 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2488 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2489 if (pinfo
& INSN_READ_GPR_S
)
2490 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2491 if (pinfo
& INSN_WRITE_GPR_31
)
2492 mips_gprmask
|= 1 << RA
;
2493 if (pinfo
& INSN_WRITE_FPR_D
)
2494 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2495 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2496 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2497 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2498 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2499 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2500 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2501 if (pinfo
& INSN_COP
)
2503 /* We don't keep enough information to sort these cases out.
2504 The itbl support does keep this information however, although
2505 we currently don't support itbl fprmats as part of the cop
2506 instruction. May want to add this support in the future. */
2508 /* Never set the bit for $0, which is always zero. */
2509 mips_gprmask
&= ~1 << 0;
2513 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2514 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2515 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2516 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2517 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2518 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2519 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2520 mips_gprmask
|= 1 << TREG
;
2521 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2522 mips_gprmask
|= 1 << SP
;
2523 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2524 mips_gprmask
|= 1 << RA
;
2525 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2526 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2527 if (pinfo
& MIPS16_INSN_READ_Z
)
2528 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2529 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2530 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2533 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2535 /* Filling the branch delay slot is more complex. We try to
2536 switch the branch with the previous instruction, which we can
2537 do if the previous instruction does not set up a condition
2538 that the branch tests and if the branch is not itself the
2539 target of any branch. */
2540 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2541 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2543 if (mips_optimize
< 2
2544 /* If we have seen .set volatile or .set nomove, don't
2546 || mips_opts
.nomove
!= 0
2547 /* We can't swap if the previous instruction's position
2549 || history
[0].fixed_p
2550 /* If the previous previous insn was in a .set
2551 noreorder, we can't swap. Actually, the MIPS
2552 assembler will swap in this situation. However, gcc
2553 configured -with-gnu-as will generate code like
2559 in which we can not swap the bne and INSN. If gcc is
2560 not configured -with-gnu-as, it does not output the
2562 || history
[1].noreorder_p
2563 /* If the branch is itself the target of a branch, we
2564 can not swap. We cheat on this; all we check for is
2565 whether there is a label on this instruction. If
2566 there are any branches to anything other than a
2567 label, users must use .set noreorder. */
2568 || insn_labels
!= NULL
2569 /* If the previous instruction is in a variant frag
2570 other than this branch's one, we cannot do the swap.
2571 This does not apply to the mips16, which uses variant
2572 frags for different purposes. */
2573 || (! mips_opts
.mips16
2574 && prev_insn_frag_type
== rs_machine_dependent
)
2575 /* Check for conflicts between the branch and the instructions
2576 before the candidate delay slot. */
2577 || nops_for_insn (history
+ 1, ip
) > 0
2578 /* Check for conflicts between the swapped sequence and the
2579 target of the branch. */
2580 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2581 /* We do not swap with a trap instruction, since it
2582 complicates trap handlers to have the trap
2583 instruction be in a delay slot. */
2584 || (prev_pinfo
& INSN_TRAP
)
2585 /* If the branch reads a register that the previous
2586 instruction sets, we can not swap. */
2587 || (! mips_opts
.mips16
2588 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2589 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2591 || (! mips_opts
.mips16
2592 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2593 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2595 || (mips_opts
.mips16
2596 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2598 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2600 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2602 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2604 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2606 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2608 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2609 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2610 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2611 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2612 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2613 && insn_uses_reg (ip
,
2614 MIPS16OP_EXTRACT_REG32R
2615 (history
[0].insn_opcode
),
2617 /* If the branch writes a register that the previous
2618 instruction sets, we can not swap (we know that
2619 branches write only to RD or to $31). */
2620 || (! mips_opts
.mips16
2621 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2622 && (((pinfo
& INSN_WRITE_GPR_D
)
2623 && (EXTRACT_OPERAND (RT
, history
[0])
2624 == EXTRACT_OPERAND (RD
, *ip
)))
2625 || ((pinfo
& INSN_WRITE_GPR_31
)
2626 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2627 || (! mips_opts
.mips16
2628 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2629 && (((pinfo
& INSN_WRITE_GPR_D
)
2630 && (EXTRACT_OPERAND (RD
, history
[0])
2631 == EXTRACT_OPERAND (RD
, *ip
)))
2632 || ((pinfo
& INSN_WRITE_GPR_31
)
2633 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2634 || (mips_opts
.mips16
2635 && (pinfo
& MIPS16_INSN_WRITE_31
)
2636 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2637 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2638 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2640 /* If the branch writes a register that the previous
2641 instruction reads, we can not swap (we know that
2642 branches only write to RD or to $31). */
2643 || (! mips_opts
.mips16
2644 && (pinfo
& INSN_WRITE_GPR_D
)
2645 && insn_uses_reg (&history
[0],
2646 EXTRACT_OPERAND (RD
, *ip
),
2648 || (! mips_opts
.mips16
2649 && (pinfo
& INSN_WRITE_GPR_31
)
2650 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2651 || (mips_opts
.mips16
2652 && (pinfo
& MIPS16_INSN_WRITE_31
)
2653 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2654 /* If one instruction sets a condition code and the
2655 other one uses a condition code, we can not swap. */
2656 || ((pinfo
& INSN_READ_COND_CODE
)
2657 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2658 || ((pinfo
& INSN_WRITE_COND_CODE
)
2659 && (prev_pinfo
& INSN_READ_COND_CODE
))
2660 /* If the previous instruction uses the PC, we can not
2662 || (mips_opts
.mips16
2663 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2664 /* If the previous instruction had a fixup in mips16
2665 mode, we can not swap. This normally means that the
2666 previous instruction was a 4 byte branch anyhow. */
2667 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2668 /* If the previous instruction is a sync, sync.l, or
2669 sync.p, we can not swap. */
2670 || (prev_pinfo
& INSN_SYNC
))
2672 /* We could do even better for unconditional branches to
2673 portions of this object file; we could pick up the
2674 instruction at the destination, put it in the delay
2675 slot, and bump the destination address. */
2676 insert_into_history (0, 1, ip
);
2678 if (mips_relax
.sequence
)
2679 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2683 /* It looks like we can actually do the swap. */
2684 struct mips_cl_insn delay
= history
[0];
2685 if (mips_opts
.mips16
)
2687 know (delay
.frag
== ip
->frag
);
2688 move_insn (ip
, delay
.frag
, delay
.where
);
2689 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2691 else if (relaxed_branch
)
2693 /* Add the delay slot instruction to the end of the
2694 current frag and shrink the fixed part of the
2695 original frag. If the branch occupies the tail of
2696 the latter, move it backwards to cover the gap. */
2697 delay
.frag
->fr_fix
-= 4;
2698 if (delay
.frag
== ip
->frag
)
2699 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2700 add_fixed_insn (&delay
);
2704 move_insn (&delay
, ip
->frag
, ip
->where
);
2705 move_insn (ip
, history
[0].frag
, history
[0].where
);
2709 insert_into_history (0, 1, &delay
);
2712 /* If that was an unconditional branch, forget the previous
2713 insn information. */
2714 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2715 mips_no_prev_insn ();
2717 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2719 /* We don't yet optimize a branch likely. What we should do
2720 is look at the target, copy the instruction found there
2721 into the delay slot, and increment the branch to jump to
2722 the next instruction. */
2723 insert_into_history (0, 1, ip
);
2727 insert_into_history (0, 1, ip
);
2730 insert_into_history (0, 1, ip
);
2732 /* We just output an insn, so the next one doesn't have a label. */
2733 mips_clear_insn_labels ();
2736 /* Forget that there was any previous instruction or label. */
2739 mips_no_prev_insn (void)
2741 prev_nop_frag
= NULL
;
2742 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2743 mips_clear_insn_labels ();
2746 /* This function must be called before we emit something other than
2747 instructions. It is like mips_no_prev_insn except that it inserts
2748 any NOPS that might be needed by previous instructions. */
2751 mips_emit_delays (void)
2753 if (! mips_opts
.noreorder
)
2755 int nops
= nops_for_insn (history
, NULL
);
2759 add_fixed_insn (NOP_INSN
);
2760 mips_move_labels ();
2763 mips_no_prev_insn ();
2766 /* Start a (possibly nested) noreorder block. */
2769 start_noreorder (void)
2771 if (mips_opts
.noreorder
== 0)
2776 /* None of the instructions before the .set noreorder can be moved. */
2777 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2778 history
[i
].fixed_p
= 1;
2780 /* Insert any nops that might be needed between the .set noreorder
2781 block and the previous instructions. We will later remove any
2782 nops that turn out not to be needed. */
2783 nops
= nops_for_insn (history
, NULL
);
2786 if (mips_optimize
!= 0)
2788 /* Record the frag which holds the nop instructions, so
2789 that we can remove them if we don't need them. */
2790 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2791 prev_nop_frag
= frag_now
;
2792 prev_nop_frag_holds
= nops
;
2793 prev_nop_frag_required
= 0;
2794 prev_nop_frag_since
= 0;
2797 for (; nops
> 0; --nops
)
2798 add_fixed_insn (NOP_INSN
);
2800 /* Move on to a new frag, so that it is safe to simply
2801 decrease the size of prev_nop_frag. */
2802 frag_wane (frag_now
);
2804 mips_move_labels ();
2806 mips16_mark_labels ();
2807 mips_clear_insn_labels ();
2809 mips_opts
.noreorder
++;
2810 mips_any_noreorder
= 1;
2813 /* End a nested noreorder block. */
2816 end_noreorder (void)
2818 mips_opts
.noreorder
--;
2819 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2821 /* Commit to inserting prev_nop_frag_required nops and go back to
2822 handling nop insertion the .set reorder way. */
2823 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2824 * (mips_opts
.mips16
? 2 : 4));
2825 insert_into_history (prev_nop_frag_since
,
2826 prev_nop_frag_required
, NOP_INSN
);
2827 prev_nop_frag
= NULL
;
2831 /* Set up global variables for the start of a new macro. */
2836 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2837 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2838 && (history
[0].insn_mo
->pinfo
2839 & (INSN_UNCOND_BRANCH_DELAY
2840 | INSN_COND_BRANCH_DELAY
2841 | INSN_COND_BRANCH_LIKELY
)) != 0);
2844 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2845 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2846 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2849 macro_warning (relax_substateT subtype
)
2851 if (subtype
& RELAX_DELAY_SLOT
)
2852 return _("Macro instruction expanded into multiple instructions"
2853 " in a branch delay slot");
2854 else if (subtype
& RELAX_NOMACRO
)
2855 return _("Macro instruction expanded into multiple instructions");
2860 /* Finish up a macro. Emit warnings as appropriate. */
2865 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2867 relax_substateT subtype
;
2869 /* Set up the relaxation warning flags. */
2871 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2872 subtype
|= RELAX_SECOND_LONGER
;
2873 if (mips_opts
.warn_about_macros
)
2874 subtype
|= RELAX_NOMACRO
;
2875 if (mips_macro_warning
.delay_slot_p
)
2876 subtype
|= RELAX_DELAY_SLOT
;
2878 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2880 /* Either the macro has a single implementation or both
2881 implementations are longer than 4 bytes. Emit the
2883 const char *msg
= macro_warning (subtype
);
2889 /* One implementation might need a warning but the other
2890 definitely doesn't. */
2891 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2896 /* Read a macro's relocation codes from *ARGS and store them in *R.
2897 The first argument in *ARGS will be either the code for a single
2898 relocation or -1 followed by the three codes that make up a
2899 composite relocation. */
2902 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2906 next
= va_arg (*args
, int);
2908 r
[0] = (bfd_reloc_code_real_type
) next
;
2910 for (i
= 0; i
< 3; i
++)
2911 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2914 /* Build an instruction created by a macro expansion. This is passed
2915 a pointer to the count of instructions created so far, an
2916 expression, the name of the instruction to build, an operand format
2917 string, and corresponding arguments. */
2920 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2922 const struct mips_opcode
*mo
;
2923 struct mips_cl_insn insn
;
2924 bfd_reloc_code_real_type r
[3];
2927 va_start (args
, fmt
);
2929 if (mips_opts
.mips16
)
2931 mips16_macro_build (ep
, name
, fmt
, args
);
2936 r
[0] = BFD_RELOC_UNUSED
;
2937 r
[1] = BFD_RELOC_UNUSED
;
2938 r
[2] = BFD_RELOC_UNUSED
;
2939 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2941 assert (strcmp (name
, mo
->name
) == 0);
2943 /* Search until we get a match for NAME. It is assumed here that
2944 macros will never generate MDMX or MIPS-3D instructions. */
2945 while (strcmp (fmt
, mo
->args
) != 0
2946 || mo
->pinfo
== INSN_MACRO
2947 || !OPCODE_IS_MEMBER (mo
,
2949 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2951 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2955 assert (strcmp (name
, mo
->name
) == 0);
2958 create_insn (&insn
, mo
);
2976 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2981 /* Note that in the macro case, these arguments are already
2982 in MSB form. (When handling the instruction in the
2983 non-macro case, these arguments are sizes from which
2984 MSB values must be calculated.) */
2985 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2991 /* Note that in the macro case, these arguments are already
2992 in MSBD form. (When handling the instruction in the
2993 non-macro case, these arguments are sizes from which
2994 MSBD values must be calculated.) */
2995 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3006 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3010 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3015 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3021 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3026 int tmp
= va_arg (args
, int);
3028 INSERT_OPERAND (RT
, insn
, tmp
);
3029 INSERT_OPERAND (RD
, insn
, tmp
);
3035 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3042 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3046 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3050 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3054 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3058 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3065 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3071 macro_read_relocs (&args
, r
);
3072 assert (*r
== BFD_RELOC_GPREL16
3073 || *r
== BFD_RELOC_MIPS_LITERAL
3074 || *r
== BFD_RELOC_MIPS_HIGHER
3075 || *r
== BFD_RELOC_HI16_S
3076 || *r
== BFD_RELOC_LO16
3077 || *r
== BFD_RELOC_MIPS_GOT16
3078 || *r
== BFD_RELOC_MIPS_CALL16
3079 || *r
== BFD_RELOC_MIPS_GOT_DISP
3080 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3081 || *r
== BFD_RELOC_MIPS_GOT_OFST
3082 || *r
== BFD_RELOC_MIPS_GOT_LO16
3083 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3087 macro_read_relocs (&args
, r
);
3089 && (ep
->X_op
== O_constant
3090 || (ep
->X_op
== O_symbol
3091 && (*r
== BFD_RELOC_MIPS_HIGHEST
3092 || *r
== BFD_RELOC_HI16_S
3093 || *r
== BFD_RELOC_HI16
3094 || *r
== BFD_RELOC_GPREL16
3095 || *r
== BFD_RELOC_MIPS_GOT_HI16
3096 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3100 assert (ep
!= NULL
);
3102 * This allows macro() to pass an immediate expression for
3103 * creating short branches without creating a symbol.
3104 * Note that the expression still might come from the assembly
3105 * input, in which case the value is not checked for range nor
3106 * is a relocation entry generated (yuck).
3108 if (ep
->X_op
== O_constant
)
3110 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3114 *r
= BFD_RELOC_16_PCREL_S2
;
3118 assert (ep
!= NULL
);
3119 *r
= BFD_RELOC_MIPS_JMP
;
3123 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3132 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3134 append_insn (&insn
, ep
, r
);
3138 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3141 struct mips_opcode
*mo
;
3142 struct mips_cl_insn insn
;
3143 bfd_reloc_code_real_type r
[3]
3144 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3146 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3148 assert (strcmp (name
, mo
->name
) == 0);
3150 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3154 assert (strcmp (name
, mo
->name
) == 0);
3157 create_insn (&insn
, mo
);
3175 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3180 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3184 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3188 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3198 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3205 regno
= va_arg (args
, int);
3206 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3207 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3228 assert (ep
!= NULL
);
3230 if (ep
->X_op
!= O_constant
)
3231 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3234 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3235 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3238 *r
= BFD_RELOC_UNUSED
;
3244 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3251 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3253 append_insn (&insn
, ep
, r
);
3257 * Generate a "jalr" instruction with a relocation hint to the called
3258 * function. This occurs in NewABI PIC code.
3261 macro_build_jalr (expressionS
*ep
)
3270 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3272 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3273 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3277 * Generate a "lui" instruction.
3280 macro_build_lui (expressionS
*ep
, int regnum
)
3282 expressionS high_expr
;
3283 const struct mips_opcode
*mo
;
3284 struct mips_cl_insn insn
;
3285 bfd_reloc_code_real_type r
[3]
3286 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3287 const char *name
= "lui";
3288 const char *fmt
= "t,u";
3290 assert (! mips_opts
.mips16
);
3294 if (high_expr
.X_op
== O_constant
)
3296 /* we can compute the instruction now without a relocation entry */
3297 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3299 *r
= BFD_RELOC_UNUSED
;
3303 assert (ep
->X_op
== O_symbol
);
3304 /* _gp_disp is a special case, used from s_cpload.
3305 __gnu_local_gp is used if mips_no_shared. */
3306 assert (mips_pic
== NO_PIC
3308 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3309 || (! mips_in_shared
3310 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3311 "__gnu_local_gp") == 0));
3312 *r
= BFD_RELOC_HI16_S
;
3315 mo
= hash_find (op_hash
, name
);
3316 assert (strcmp (name
, mo
->name
) == 0);
3317 assert (strcmp (fmt
, mo
->args
) == 0);
3318 create_insn (&insn
, mo
);
3320 insn
.insn_opcode
= insn
.insn_mo
->match
;
3321 INSERT_OPERAND (RT
, insn
, regnum
);
3322 if (*r
== BFD_RELOC_UNUSED
)
3324 insn
.insn_opcode
|= high_expr
.X_add_number
;
3325 append_insn (&insn
, NULL
, r
);
3328 append_insn (&insn
, &high_expr
, r
);
3331 /* Generate a sequence of instructions to do a load or store from a constant
3332 offset off of a base register (breg) into/from a target register (treg),
3333 using AT if necessary. */
3335 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3336 int treg
, int breg
, int dbl
)
3338 assert (ep
->X_op
== O_constant
);
3340 /* Sign-extending 32-bit constants makes their handling easier. */
3341 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3342 == ~((bfd_vma
) 0x7fffffff)))
3344 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3345 as_bad (_("constant too large"));
3347 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3351 /* Right now, this routine can only handle signed 32-bit constants. */
3352 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3353 as_warn (_("operand overflow"));
3355 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3357 /* Signed 16-bit offset will fit in the op. Easy! */
3358 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3362 /* 32-bit offset, need multiple instructions and AT, like:
3363 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3364 addu $tempreg,$tempreg,$breg
3365 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3366 to handle the complete offset. */
3367 macro_build_lui (ep
, AT
);
3368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3369 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3372 as_bad (_("Macro used $at after \".set noat\""));
3377 * Generates code to set the $at register to true (one)
3378 * if reg is less than the immediate expression.
3381 set_at (int reg
, int unsignedp
)
3383 if (imm_expr
.X_op
== O_constant
3384 && imm_expr
.X_add_number
>= -0x8000
3385 && imm_expr
.X_add_number
< 0x8000)
3386 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3387 AT
, reg
, BFD_RELOC_LO16
);
3390 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3391 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3396 normalize_constant_expr (expressionS
*ex
)
3398 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3399 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3403 /* Warn if an expression is not a constant. */
3406 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3408 if (ex
->X_op
== O_big
)
3409 as_bad (_("unsupported large constant"));
3410 else if (ex
->X_op
!= O_constant
)
3411 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3413 normalize_constant_expr (ex
);
3416 /* Count the leading zeroes by performing a binary chop. This is a
3417 bulky bit of source, but performance is a LOT better for the
3418 majority of values than a simple loop to count the bits:
3419 for (lcnt = 0; (lcnt < 32); lcnt++)
3420 if ((v) & (1 << (31 - lcnt)))
3422 However it is not code size friendly, and the gain will drop a bit
3423 on certain cached systems.
3425 #define COUNT_TOP_ZEROES(v) \
3426 (((v) & ~0xffff) == 0 \
3427 ? ((v) & ~0xff) == 0 \
3428 ? ((v) & ~0xf) == 0 \
3429 ? ((v) & ~0x3) == 0 \
3430 ? ((v) & ~0x1) == 0 \
3435 : ((v) & ~0x7) == 0 \
3438 : ((v) & ~0x3f) == 0 \
3439 ? ((v) & ~0x1f) == 0 \
3442 : ((v) & ~0x7f) == 0 \
3445 : ((v) & ~0xfff) == 0 \
3446 ? ((v) & ~0x3ff) == 0 \
3447 ? ((v) & ~0x1ff) == 0 \
3450 : ((v) & ~0x7ff) == 0 \
3453 : ((v) & ~0x3fff) == 0 \
3454 ? ((v) & ~0x1fff) == 0 \
3457 : ((v) & ~0x7fff) == 0 \
3460 : ((v) & ~0xffffff) == 0 \
3461 ? ((v) & ~0xfffff) == 0 \
3462 ? ((v) & ~0x3ffff) == 0 \
3463 ? ((v) & ~0x1ffff) == 0 \
3466 : ((v) & ~0x7ffff) == 0 \
3469 : ((v) & ~0x3fffff) == 0 \
3470 ? ((v) & ~0x1fffff) == 0 \
3473 : ((v) & ~0x7fffff) == 0 \
3476 : ((v) & ~0xfffffff) == 0 \
3477 ? ((v) & ~0x3ffffff) == 0 \
3478 ? ((v) & ~0x1ffffff) == 0 \
3481 : ((v) & ~0x7ffffff) == 0 \
3484 : ((v) & ~0x3fffffff) == 0 \
3485 ? ((v) & ~0x1fffffff) == 0 \
3488 : ((v) & ~0x7fffffff) == 0 \
3493 * This routine generates the least number of instructions necessary to load
3494 * an absolute expression value into a register.
3497 load_register (int reg
, expressionS
*ep
, int dbl
)
3500 expressionS hi32
, lo32
;
3502 if (ep
->X_op
!= O_big
)
3504 assert (ep
->X_op
== O_constant
);
3506 /* Sign-extending 32-bit constants makes their handling easier. */
3507 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3508 == ~((bfd_vma
) 0x7fffffff)))
3510 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3511 as_bad (_("constant too large"));
3513 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3517 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3519 /* We can handle 16 bit signed values with an addiu to
3520 $zero. No need to ever use daddiu here, since $zero and
3521 the result are always correct in 32 bit mode. */
3522 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3525 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3527 /* We can handle 16 bit unsigned values with an ori to
3529 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3532 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3534 /* 32 bit values require an lui. */
3535 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3536 if ((ep
->X_add_number
& 0xffff) != 0)
3537 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3542 /* The value is larger than 32 bits. */
3544 if (HAVE_32BIT_GPRS
)
3546 as_bad (_("Number (0x%lx) larger than 32 bits"),
3547 (unsigned long) ep
->X_add_number
);
3548 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3552 if (ep
->X_op
!= O_big
)
3555 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3556 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3557 hi32
.X_add_number
&= 0xffffffff;
3559 lo32
.X_add_number
&= 0xffffffff;
3563 assert (ep
->X_add_number
> 2);
3564 if (ep
->X_add_number
== 3)
3565 generic_bignum
[3] = 0;
3566 else if (ep
->X_add_number
> 4)
3567 as_bad (_("Number larger than 64 bits"));
3568 lo32
.X_op
= O_constant
;
3569 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3570 hi32
.X_op
= O_constant
;
3571 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3574 if (hi32
.X_add_number
== 0)
3579 unsigned long hi
, lo
;
3581 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3583 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3585 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3588 if (lo32
.X_add_number
& 0x80000000)
3590 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3591 if (lo32
.X_add_number
& 0xffff)
3592 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3597 /* Check for 16bit shifted constant. We know that hi32 is
3598 non-zero, so start the mask on the first bit of the hi32
3603 unsigned long himask
, lomask
;
3607 himask
= 0xffff >> (32 - shift
);
3608 lomask
= (0xffff << shift
) & 0xffffffff;
3612 himask
= 0xffff << (shift
- 32);
3615 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3616 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3620 tmp
.X_op
= O_constant
;
3622 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3623 | (lo32
.X_add_number
>> shift
));
3625 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3626 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3627 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3628 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3633 while (shift
<= (64 - 16));
3635 /* Find the bit number of the lowest one bit, and store the
3636 shifted value in hi/lo. */
3637 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3638 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3642 while ((lo
& 1) == 0)
3647 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3653 while ((hi
& 1) == 0)
3662 /* Optimize if the shifted value is a (power of 2) - 1. */
3663 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3664 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3666 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3671 /* This instruction will set the register to be all
3673 tmp
.X_op
= O_constant
;
3674 tmp
.X_add_number
= (offsetT
) -1;
3675 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3679 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3680 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3682 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3683 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3688 /* Sign extend hi32 before calling load_register, because we can
3689 generally get better code when we load a sign extended value. */
3690 if ((hi32
.X_add_number
& 0x80000000) != 0)
3691 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3692 load_register (reg
, &hi32
, 0);
3695 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3699 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3707 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3709 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3710 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3716 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3720 mid16
.X_add_number
>>= 16;
3721 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3722 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3725 if ((lo32
.X_add_number
& 0xffff) != 0)
3726 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3730 load_delay_nop (void)
3732 if (!gpr_interlocks
)
3733 macro_build (NULL
, "nop", "");
3736 /* Load an address into a register. */
3739 load_address (int reg
, expressionS
*ep
, int *used_at
)
3741 if (ep
->X_op
!= O_constant
3742 && ep
->X_op
!= O_symbol
)
3744 as_bad (_("expression too complex"));
3745 ep
->X_op
= O_constant
;
3748 if (ep
->X_op
== O_constant
)
3750 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3754 if (mips_pic
== NO_PIC
)
3756 /* If this is a reference to a GP relative symbol, we want
3757 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3759 lui $reg,<sym> (BFD_RELOC_HI16_S)
3760 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3761 If we have an addend, we always use the latter form.
3763 With 64bit address space and a usable $at we want
3764 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3765 lui $at,<sym> (BFD_RELOC_HI16_S)
3766 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3767 daddiu $at,<sym> (BFD_RELOC_LO16)
3771 If $at is already in use, we use a path which is suboptimal
3772 on superscalar processors.
3773 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3774 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3776 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3778 daddiu $reg,<sym> (BFD_RELOC_LO16)
3780 For GP relative symbols in 64bit address space we can use
3781 the same sequence as in 32bit address space. */
3782 if (HAVE_64BIT_SYMBOLS
)
3784 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3785 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3787 relax_start (ep
->X_add_symbol
);
3788 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3789 mips_gp_register
, BFD_RELOC_GPREL16
);
3793 if (*used_at
== 0 && !mips_opts
.noat
)
3795 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3796 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3797 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3798 BFD_RELOC_MIPS_HIGHER
);
3799 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3800 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3801 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3806 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3807 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3808 BFD_RELOC_MIPS_HIGHER
);
3809 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3810 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3811 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3812 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3815 if (mips_relax
.sequence
)
3820 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3821 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3823 relax_start (ep
->X_add_symbol
);
3824 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3825 mips_gp_register
, BFD_RELOC_GPREL16
);
3828 macro_build_lui (ep
, reg
);
3829 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3830 reg
, reg
, BFD_RELOC_LO16
);
3831 if (mips_relax
.sequence
)
3835 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3839 /* If this is a reference to an external symbol, we want
3840 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3842 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3844 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3845 If there is a constant, it must be added in after.
3847 If we have NewABI, we want
3848 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3849 unless we're referencing a global symbol with a non-zero
3850 offset, in which case cst must be added separately. */
3853 if (ep
->X_add_number
)
3855 ex
.X_add_number
= ep
->X_add_number
;
3856 ep
->X_add_number
= 0;
3857 relax_start (ep
->X_add_symbol
);
3858 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3859 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3860 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3861 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3862 ex
.X_op
= O_constant
;
3863 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3864 reg
, reg
, BFD_RELOC_LO16
);
3865 ep
->X_add_number
= ex
.X_add_number
;
3868 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3869 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3870 if (mips_relax
.sequence
)
3875 ex
.X_add_number
= ep
->X_add_number
;
3876 ep
->X_add_number
= 0;
3877 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3878 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3880 relax_start (ep
->X_add_symbol
);
3882 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3886 if (ex
.X_add_number
!= 0)
3888 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3889 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3890 ex
.X_op
= O_constant
;
3891 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3892 reg
, reg
, BFD_RELOC_LO16
);
3896 else if (mips_pic
== SVR4_PIC
)
3900 /* This is the large GOT case. If this is a reference to an
3901 external symbol, we want
3902 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3904 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3906 Otherwise, for a reference to a local symbol in old ABI, we want
3907 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3909 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3910 If there is a constant, it must be added in after.
3912 In the NewABI, for local symbols, with or without offsets, we want:
3913 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3914 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3918 ex
.X_add_number
= ep
->X_add_number
;
3919 ep
->X_add_number
= 0;
3920 relax_start (ep
->X_add_symbol
);
3921 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3922 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3923 reg
, reg
, mips_gp_register
);
3924 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3925 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3926 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3927 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3928 else if (ex
.X_add_number
)
3930 ex
.X_op
= O_constant
;
3931 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3935 ep
->X_add_number
= ex
.X_add_number
;
3937 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3938 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3939 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3940 BFD_RELOC_MIPS_GOT_OFST
);
3945 ex
.X_add_number
= ep
->X_add_number
;
3946 ep
->X_add_number
= 0;
3947 relax_start (ep
->X_add_symbol
);
3948 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3949 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3950 reg
, reg
, mips_gp_register
);
3951 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3952 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3954 if (reg_needs_delay (mips_gp_register
))
3956 /* We need a nop before loading from $gp. This special
3957 check is required because the lui which starts the main
3958 instruction stream does not refer to $gp, and so will not
3959 insert the nop which may be required. */
3960 macro_build (NULL
, "nop", "");
3962 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3963 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3965 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3969 if (ex
.X_add_number
!= 0)
3971 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3972 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3973 ex
.X_op
= O_constant
;
3974 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3982 if (mips_opts
.noat
&& *used_at
== 1)
3983 as_bad (_("Macro used $at after \".set noat\""));
3986 /* Move the contents of register SOURCE into register DEST. */
3989 move_register (int dest
, int source
)
3991 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3995 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3996 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3997 The two alternatives are:
3999 Global symbol Local sybmol
4000 ------------- ------------
4001 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4003 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4005 load_got_offset emits the first instruction and add_got_offset
4006 emits the second for a 16-bit offset or add_got_offset_hilo emits
4007 a sequence to add a 32-bit offset using a scratch register. */
4010 load_got_offset (int dest
, expressionS
*local
)
4015 global
.X_add_number
= 0;
4017 relax_start (local
->X_add_symbol
);
4018 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4019 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4021 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4022 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4027 add_got_offset (int dest
, expressionS
*local
)
4031 global
.X_op
= O_constant
;
4032 global
.X_op_symbol
= NULL
;
4033 global
.X_add_symbol
= NULL
;
4034 global
.X_add_number
= local
->X_add_number
;
4036 relax_start (local
->X_add_symbol
);
4037 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4038 dest
, dest
, BFD_RELOC_LO16
);
4040 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4045 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4048 int hold_mips_optimize
;
4050 global
.X_op
= O_constant
;
4051 global
.X_op_symbol
= NULL
;
4052 global
.X_add_symbol
= NULL
;
4053 global
.X_add_number
= local
->X_add_number
;
4055 relax_start (local
->X_add_symbol
);
4056 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4058 /* Set mips_optimize around the lui instruction to avoid
4059 inserting an unnecessary nop after the lw. */
4060 hold_mips_optimize
= mips_optimize
;
4062 macro_build_lui (&global
, tmp
);
4063 mips_optimize
= hold_mips_optimize
;
4064 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4067 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4072 * This routine implements the seemingly endless macro or synthesized
4073 * instructions and addressing modes in the mips assembly language. Many
4074 * of these macros are simple and are similar to each other. These could
4075 * probably be handled by some kind of table or grammar approach instead of
4076 * this verbose method. Others are not simple macros but are more like
4077 * optimizing code generation.
4078 * One interesting optimization is when several store macros appear
4079 * consecutively that would load AT with the upper half of the same address.
4080 * The ensuing load upper instructions are ommited. This implies some kind
4081 * of global optimization. We currently only optimize within a single macro.
4082 * For many of the load and store macros if the address is specified as a
4083 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4084 * first load register 'at' with zero and use it as the base register. The
4085 * mips assembler simply uses register $zero. Just one tiny optimization
4089 macro (struct mips_cl_insn
*ip
)
4091 register int treg
, sreg
, dreg
, breg
;
4107 bfd_reloc_code_real_type r
;
4108 int hold_mips_optimize
;
4110 assert (! mips_opts
.mips16
);
4112 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4113 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4114 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4115 mask
= ip
->insn_mo
->mask
;
4117 expr1
.X_op
= O_constant
;
4118 expr1
.X_op_symbol
= NULL
;
4119 expr1
.X_add_symbol
= NULL
;
4120 expr1
.X_add_number
= 1;
4134 expr1
.X_add_number
= 8;
4135 macro_build (&expr1
, "bgez", "s,p", sreg
);
4137 macro_build (NULL
, "nop", "", 0);
4139 move_register (dreg
, sreg
);
4140 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4163 if (imm_expr
.X_op
== O_constant
4164 && imm_expr
.X_add_number
>= -0x8000
4165 && imm_expr
.X_add_number
< 0x8000)
4167 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4171 load_register (AT
, &imm_expr
, dbl
);
4172 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4191 if (imm_expr
.X_op
== O_constant
4192 && imm_expr
.X_add_number
>= 0
4193 && imm_expr
.X_add_number
< 0x10000)
4195 if (mask
!= M_NOR_I
)
4196 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4199 macro_build (&imm_expr
, "ori", "t,r,i",
4200 treg
, sreg
, BFD_RELOC_LO16
);
4201 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4207 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4208 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4225 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4227 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4231 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4232 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4240 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4245 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4249 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4250 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4256 /* check for > max integer */
4257 maxnum
= 0x7fffffff;
4258 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4265 if (imm_expr
.X_op
== O_constant
4266 && imm_expr
.X_add_number
>= maxnum
4267 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4270 /* result is always false */
4272 macro_build (NULL
, "nop", "", 0);
4274 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4277 if (imm_expr
.X_op
!= O_constant
)
4278 as_bad (_("Unsupported large constant"));
4279 ++imm_expr
.X_add_number
;
4283 if (mask
== M_BGEL_I
)
4285 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4287 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4292 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4295 maxnum
= 0x7fffffff;
4296 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4303 maxnum
= - maxnum
- 1;
4304 if (imm_expr
.X_op
== O_constant
4305 && imm_expr
.X_add_number
<= maxnum
4306 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4309 /* result is always true */
4310 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4311 macro_build (&offset_expr
, "b", "p");
4316 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4326 macro_build (&offset_expr
, likely
? "beql" : "beq",
4331 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4332 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4340 && imm_expr
.X_op
== O_constant
4341 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4343 if (imm_expr
.X_op
!= O_constant
)
4344 as_bad (_("Unsupported large constant"));
4345 ++imm_expr
.X_add_number
;
4349 if (mask
== M_BGEUL_I
)
4351 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4353 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4355 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4361 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4369 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4374 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4378 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4379 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4387 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4394 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4395 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4403 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4408 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4412 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4413 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4419 maxnum
= 0x7fffffff;
4420 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4427 if (imm_expr
.X_op
== O_constant
4428 && imm_expr
.X_add_number
>= maxnum
4429 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4431 if (imm_expr
.X_op
!= O_constant
)
4432 as_bad (_("Unsupported large constant"));
4433 ++imm_expr
.X_add_number
;
4437 if (mask
== M_BLTL_I
)
4439 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4441 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4444 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4446 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4451 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4459 macro_build (&offset_expr
, likely
? "beql" : "beq",
4466 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4467 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4475 && imm_expr
.X_op
== O_constant
4476 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4478 if (imm_expr
.X_op
!= O_constant
)
4479 as_bad (_("Unsupported large constant"));
4480 ++imm_expr
.X_add_number
;
4484 if (mask
== M_BLTUL_I
)
4486 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4488 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4490 macro_build (&offset_expr
, likely
? "beql" : "beq",
4496 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4504 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4509 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4513 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4514 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4524 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4529 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4530 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4538 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4540 as_bad (_("Unsupported large constant"));
4545 pos
= (unsigned long) imm_expr
.X_add_number
;
4546 size
= (unsigned long) imm2_expr
.X_add_number
;
4551 as_bad (_("Improper position (%lu)"), pos
);
4554 if (size
== 0 || size
> 64
4555 || (pos
+ size
- 1) > 63)
4557 as_bad (_("Improper extract size (%lu, position %lu)"),
4562 if (size
<= 32 && pos
< 32)
4567 else if (size
<= 32)
4577 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4586 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4588 as_bad (_("Unsupported large constant"));
4593 pos
= (unsigned long) imm_expr
.X_add_number
;
4594 size
= (unsigned long) imm2_expr
.X_add_number
;
4599 as_bad (_("Improper position (%lu)"), pos
);
4602 if (size
== 0 || size
> 64
4603 || (pos
+ size
- 1) > 63)
4605 as_bad (_("Improper insert size (%lu, position %lu)"),
4610 if (pos
< 32 && (pos
+ size
- 1) < 32)
4625 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4642 as_warn (_("Divide by zero."));
4644 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4646 macro_build (NULL
, "break", "c", 7);
4653 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4654 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4658 expr1
.X_add_number
= 8;
4659 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4660 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4661 macro_build (NULL
, "break", "c", 7);
4663 expr1
.X_add_number
= -1;
4665 load_register (AT
, &expr1
, dbl
);
4666 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4667 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4670 expr1
.X_add_number
= 1;
4671 load_register (AT
, &expr1
, dbl
);
4672 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4676 expr1
.X_add_number
= 0x80000000;
4677 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4681 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4682 /* We want to close the noreorder block as soon as possible, so
4683 that later insns are available for delay slot filling. */
4688 expr1
.X_add_number
= 8;
4689 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4690 macro_build (NULL
, "nop", "", 0);
4692 /* We want to close the noreorder block as soon as possible, so
4693 that later insns are available for delay slot filling. */
4696 macro_build (NULL
, "break", "c", 6);
4698 macro_build (NULL
, s
, "d", dreg
);
4737 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4739 as_warn (_("Divide by zero."));
4741 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4743 macro_build (NULL
, "break", "c", 7);
4746 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4748 if (strcmp (s2
, "mflo") == 0)
4749 move_register (dreg
, sreg
);
4751 move_register (dreg
, 0);
4754 if (imm_expr
.X_op
== O_constant
4755 && imm_expr
.X_add_number
== -1
4756 && s
[strlen (s
) - 1] != 'u')
4758 if (strcmp (s2
, "mflo") == 0)
4760 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4763 move_register (dreg
, 0);
4768 load_register (AT
, &imm_expr
, dbl
);
4769 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4770 macro_build (NULL
, s2
, "d", dreg
);
4792 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4793 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4794 /* We want to close the noreorder block as soon as possible, so
4795 that later insns are available for delay slot filling. */
4800 expr1
.X_add_number
= 8;
4801 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4802 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4804 /* We want to close the noreorder block as soon as possible, so
4805 that later insns are available for delay slot filling. */
4807 macro_build (NULL
, "break", "c", 7);
4809 macro_build (NULL
, s2
, "d", dreg
);
4821 /* Load the address of a symbol into a register. If breg is not
4822 zero, we then add a base register to it. */
4824 if (dbl
&& HAVE_32BIT_GPRS
)
4825 as_warn (_("dla used to load 32-bit register"));
4827 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4828 as_warn (_("la used to load 64-bit address"));
4830 if (offset_expr
.X_op
== O_constant
4831 && offset_expr
.X_add_number
>= -0x8000
4832 && offset_expr
.X_add_number
< 0x8000)
4834 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4835 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4839 if (!mips_opts
.noat
&& (treg
== breg
))
4849 if (offset_expr
.X_op
!= O_symbol
4850 && offset_expr
.X_op
!= O_constant
)
4852 as_bad (_("expression too complex"));
4853 offset_expr
.X_op
= O_constant
;
4856 if (offset_expr
.X_op
== O_constant
)
4857 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4858 else if (mips_pic
== NO_PIC
)
4860 /* If this is a reference to a GP relative symbol, we want
4861 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4863 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4864 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4865 If we have a constant, we need two instructions anyhow,
4866 so we may as well always use the latter form.
4868 With 64bit address space and a usable $at we want
4869 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4870 lui $at,<sym> (BFD_RELOC_HI16_S)
4871 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4872 daddiu $at,<sym> (BFD_RELOC_LO16)
4874 daddu $tempreg,$tempreg,$at
4876 If $at is already in use, we use a path which is suboptimal
4877 on superscalar processors.
4878 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4879 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4881 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4883 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4885 For GP relative symbols in 64bit address space we can use
4886 the same sequence as in 32bit address space. */
4887 if (HAVE_64BIT_SYMBOLS
)
4889 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4890 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4892 relax_start (offset_expr
.X_add_symbol
);
4893 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4894 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4898 if (used_at
== 0 && !mips_opts
.noat
)
4900 macro_build (&offset_expr
, "lui", "t,u",
4901 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4902 macro_build (&offset_expr
, "lui", "t,u",
4903 AT
, BFD_RELOC_HI16_S
);
4904 macro_build (&offset_expr
, "daddiu", "t,r,j",
4905 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4906 macro_build (&offset_expr
, "daddiu", "t,r,j",
4907 AT
, AT
, BFD_RELOC_LO16
);
4908 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4909 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4914 macro_build (&offset_expr
, "lui", "t,u",
4915 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4916 macro_build (&offset_expr
, "daddiu", "t,r,j",
4917 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4918 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4919 macro_build (&offset_expr
, "daddiu", "t,r,j",
4920 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4921 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4922 macro_build (&offset_expr
, "daddiu", "t,r,j",
4923 tempreg
, tempreg
, BFD_RELOC_LO16
);
4926 if (mips_relax
.sequence
)
4931 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4932 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4934 relax_start (offset_expr
.X_add_symbol
);
4935 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4936 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4939 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4940 as_bad (_("offset too large"));
4941 macro_build_lui (&offset_expr
, tempreg
);
4942 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4943 tempreg
, tempreg
, BFD_RELOC_LO16
);
4944 if (mips_relax
.sequence
)
4948 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4950 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4952 /* If this is a reference to an external symbol, and there
4953 is no constant, we want
4954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4955 or for lca or if tempreg is PIC_CALL_REG
4956 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4957 For a local symbol, we want
4958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4962 If we have a small constant, and this is a reference to
4963 an external symbol, we want
4964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4966 addiu $tempreg,$tempreg,<constant>
4967 For a local symbol, we want the same instruction
4968 sequence, but we output a BFD_RELOC_LO16 reloc on the
4971 If we have a large constant, and this is a reference to
4972 an external symbol, we want
4973 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4974 lui $at,<hiconstant>
4975 addiu $at,$at,<loconstant>
4976 addu $tempreg,$tempreg,$at
4977 For a local symbol, we want the same instruction
4978 sequence, but we output a BFD_RELOC_LO16 reloc on the
4982 if (offset_expr
.X_add_number
== 0)
4984 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4985 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4987 relax_start (offset_expr
.X_add_symbol
);
4988 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4989 lw_reloc_type
, mips_gp_register
);
4992 /* We're going to put in an addu instruction using
4993 tempreg, so we may as well insert the nop right
4998 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4999 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5001 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5002 tempreg
, tempreg
, BFD_RELOC_LO16
);
5004 /* FIXME: If breg == 0, and the next instruction uses
5005 $tempreg, then if this variant case is used an extra
5006 nop will be generated. */
5008 else if (offset_expr
.X_add_number
>= -0x8000
5009 && offset_expr
.X_add_number
< 0x8000)
5011 load_got_offset (tempreg
, &offset_expr
);
5013 add_got_offset (tempreg
, &offset_expr
);
5017 expr1
.X_add_number
= offset_expr
.X_add_number
;
5018 offset_expr
.X_add_number
=
5019 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5020 load_got_offset (tempreg
, &offset_expr
);
5021 offset_expr
.X_add_number
= expr1
.X_add_number
;
5022 /* If we are going to add in a base register, and the
5023 target register and the base register are the same,
5024 then we are using AT as a temporary register. Since
5025 we want to load the constant into AT, we add our
5026 current AT (from the global offset table) and the
5027 register into the register now, and pretend we were
5028 not using a base register. */
5032 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5037 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5041 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5043 int add_breg_early
= 0;
5045 /* If this is a reference to an external, and there is no
5046 constant, or local symbol (*), with or without a
5048 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5049 or for lca or if tempreg is PIC_CALL_REG
5050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5052 If we have a small constant, and this is a reference to
5053 an external symbol, we want
5054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5055 addiu $tempreg,$tempreg,<constant>
5057 If we have a large constant, and this is a reference to
5058 an external symbol, we want
5059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5060 lui $at,<hiconstant>
5061 addiu $at,$at,<loconstant>
5062 addu $tempreg,$tempreg,$at
5064 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5065 local symbols, even though it introduces an additional
5068 if (offset_expr
.X_add_number
)
5070 expr1
.X_add_number
= offset_expr
.X_add_number
;
5071 offset_expr
.X_add_number
= 0;
5073 relax_start (offset_expr
.X_add_symbol
);
5074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5075 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5077 if (expr1
.X_add_number
>= -0x8000
5078 && expr1
.X_add_number
< 0x8000)
5080 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5081 tempreg
, tempreg
, BFD_RELOC_LO16
);
5083 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5087 /* If we are going to add in a base register, and the
5088 target register and the base register are the same,
5089 then we are using AT as a temporary register. Since
5090 we want to load the constant into AT, we add our
5091 current AT (from the global offset table) and the
5092 register into the register now, and pretend we were
5093 not using a base register. */
5098 assert (tempreg
== AT
);
5099 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5105 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5112 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5115 offset_expr
.X_add_number
= expr1
.X_add_number
;
5117 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5118 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5122 treg
, tempreg
, breg
);
5128 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5130 relax_start (offset_expr
.X_add_symbol
);
5131 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5132 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5134 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5135 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5140 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5141 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5144 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5147 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5148 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5149 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5151 /* This is the large GOT case. If this is a reference to an
5152 external symbol, and there is no constant, we want
5153 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5154 addu $tempreg,$tempreg,$gp
5155 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5156 or for lca or if tempreg is PIC_CALL_REG
5157 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5158 addu $tempreg,$tempreg,$gp
5159 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5160 For a local symbol, we want
5161 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5163 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5165 If we have a small constant, and this is a reference to
5166 an external symbol, we want
5167 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5168 addu $tempreg,$tempreg,$gp
5169 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5171 addiu $tempreg,$tempreg,<constant>
5172 For a local symbol, we want
5173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5175 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5177 If we have a large constant, and this is a reference to
5178 an external symbol, we want
5179 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5180 addu $tempreg,$tempreg,$gp
5181 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5182 lui $at,<hiconstant>
5183 addiu $at,$at,<loconstant>
5184 addu $tempreg,$tempreg,$at
5185 For a local symbol, we want
5186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5187 lui $at,<hiconstant>
5188 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5189 addu $tempreg,$tempreg,$at
5192 expr1
.X_add_number
= offset_expr
.X_add_number
;
5193 offset_expr
.X_add_number
= 0;
5194 relax_start (offset_expr
.X_add_symbol
);
5195 gpdelay
= reg_needs_delay (mips_gp_register
);
5196 if (expr1
.X_add_number
== 0 && breg
== 0
5197 && (call
|| tempreg
== PIC_CALL_REG
))
5199 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5200 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5202 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5203 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5204 tempreg
, tempreg
, mips_gp_register
);
5205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5206 tempreg
, lw_reloc_type
, tempreg
);
5207 if (expr1
.X_add_number
== 0)
5211 /* We're going to put in an addu instruction using
5212 tempreg, so we may as well insert the nop right
5217 else if (expr1
.X_add_number
>= -0x8000
5218 && expr1
.X_add_number
< 0x8000)
5221 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5222 tempreg
, tempreg
, BFD_RELOC_LO16
);
5228 /* If we are going to add in a base register, and the
5229 target register and the base register are the same,
5230 then we are using AT as a temporary register. Since
5231 we want to load the constant into AT, we add our
5232 current AT (from the global offset table) and the
5233 register into the register now, and pretend we were
5234 not using a base register. */
5239 assert (tempreg
== AT
);
5241 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5246 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5251 offset_expr
.X_add_number
=
5252 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5257 /* This is needed because this instruction uses $gp, but
5258 the first instruction on the main stream does not. */
5259 macro_build (NULL
, "nop", "");
5262 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5263 local_reloc_type
, mips_gp_register
);
5264 if (expr1
.X_add_number
>= -0x8000
5265 && expr1
.X_add_number
< 0x8000)
5268 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5269 tempreg
, tempreg
, BFD_RELOC_LO16
);
5270 /* FIXME: If add_number is 0, and there was no base
5271 register, the external symbol case ended with a load,
5272 so if the symbol turns out to not be external, and
5273 the next instruction uses tempreg, an unnecessary nop
5274 will be inserted. */
5280 /* We must add in the base register now, as in the
5281 external symbol case. */
5282 assert (tempreg
== AT
);
5284 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5287 /* We set breg to 0 because we have arranged to add
5288 it in in both cases. */
5292 macro_build_lui (&expr1
, AT
);
5293 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5294 AT
, AT
, BFD_RELOC_LO16
);
5295 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5296 tempreg
, tempreg
, AT
);
5301 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5303 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5304 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5305 int add_breg_early
= 0;
5307 /* This is the large GOT case. If this is a reference to an
5308 external symbol, and there is no constant, we want
5309 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5310 add $tempreg,$tempreg,$gp
5311 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5312 or for lca or if tempreg is PIC_CALL_REG
5313 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5314 add $tempreg,$tempreg,$gp
5315 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5317 If we have a small constant, and this is a reference to
5318 an external symbol, we want
5319 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5320 add $tempreg,$tempreg,$gp
5321 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5322 addi $tempreg,$tempreg,<constant>
5324 If we have a large constant, and this is a reference to
5325 an external symbol, we want
5326 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5327 addu $tempreg,$tempreg,$gp
5328 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5329 lui $at,<hiconstant>
5330 addi $at,$at,<loconstant>
5331 add $tempreg,$tempreg,$at
5333 If we have NewABI, and we know it's a local symbol, we want
5334 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5335 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5336 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5338 relax_start (offset_expr
.X_add_symbol
);
5340 expr1
.X_add_number
= offset_expr
.X_add_number
;
5341 offset_expr
.X_add_number
= 0;
5343 if (expr1
.X_add_number
== 0 && breg
== 0
5344 && (call
|| tempreg
== PIC_CALL_REG
))
5346 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5347 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5349 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5351 tempreg
, tempreg
, mips_gp_register
);
5352 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5353 tempreg
, lw_reloc_type
, tempreg
);
5355 if (expr1
.X_add_number
== 0)
5357 else if (expr1
.X_add_number
>= -0x8000
5358 && expr1
.X_add_number
< 0x8000)
5360 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5361 tempreg
, tempreg
, BFD_RELOC_LO16
);
5363 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5367 /* If we are going to add in a base register, and the
5368 target register and the base register are the same,
5369 then we are using AT as a temporary register. Since
5370 we want to load the constant into AT, we add our
5371 current AT (from the global offset table) and the
5372 register into the register now, and pretend we were
5373 not using a base register. */
5378 assert (tempreg
== AT
);
5379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5385 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5386 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5391 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5394 offset_expr
.X_add_number
= expr1
.X_add_number
;
5395 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5396 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5397 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5398 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5401 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5402 treg
, tempreg
, breg
);
5412 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5416 /* The j instruction may not be used in PIC code, since it
5417 requires an absolute address. We convert it to a b
5419 if (mips_pic
== NO_PIC
)
5420 macro_build (&offset_expr
, "j", "a");
5422 macro_build (&offset_expr
, "b", "p");
5425 /* The jal instructions must be handled as macros because when
5426 generating PIC code they expand to multi-instruction
5427 sequences. Normally they are simple instructions. */
5432 if (mips_pic
== NO_PIC
)
5433 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5434 else if (mips_pic
== SVR4_PIC
)
5436 if (sreg
!= PIC_CALL_REG
)
5437 as_warn (_("MIPS PIC call to register other than $25"));
5439 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5442 if (mips_cprestore_offset
< 0)
5443 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5446 if (! mips_frame_reg_valid
)
5448 as_warn (_("No .frame pseudo-op used in PIC code"));
5449 /* Quiet this warning. */
5450 mips_frame_reg_valid
= 1;
5452 if (! mips_cprestore_valid
)
5454 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5455 /* Quiet this warning. */
5456 mips_cprestore_valid
= 1;
5458 expr1
.X_add_number
= mips_cprestore_offset
;
5459 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5462 HAVE_64BIT_ADDRESSES
);
5472 if (mips_pic
== NO_PIC
)
5473 macro_build (&offset_expr
, "jal", "a");
5474 else if (mips_pic
== SVR4_PIC
)
5476 /* If this is a reference to an external symbol, and we are
5477 using a small GOT, we want
5478 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5482 lw $gp,cprestore($sp)
5483 The cprestore value is set using the .cprestore
5484 pseudo-op. If we are using a big GOT, we want
5485 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5487 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5491 lw $gp,cprestore($sp)
5492 If the symbol is not external, we want
5493 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5495 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5498 lw $gp,cprestore($sp)
5500 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5501 sequences above, minus nops, unless the symbol is local,
5502 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5508 relax_start (offset_expr
.X_add_symbol
);
5509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5510 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5513 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5514 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5520 relax_start (offset_expr
.X_add_symbol
);
5521 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5522 BFD_RELOC_MIPS_CALL_HI16
);
5523 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5524 PIC_CALL_REG
, mips_gp_register
);
5525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5526 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5529 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5530 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5532 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5533 PIC_CALL_REG
, PIC_CALL_REG
,
5534 BFD_RELOC_MIPS_GOT_OFST
);
5538 macro_build_jalr (&offset_expr
);
5542 relax_start (offset_expr
.X_add_symbol
);
5545 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5546 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5555 gpdelay
= reg_needs_delay (mips_gp_register
);
5556 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5557 BFD_RELOC_MIPS_CALL_HI16
);
5558 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5559 PIC_CALL_REG
, mips_gp_register
);
5560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5561 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5566 macro_build (NULL
, "nop", "");
5568 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5569 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5572 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5573 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5575 macro_build_jalr (&offset_expr
);
5577 if (mips_cprestore_offset
< 0)
5578 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5581 if (! mips_frame_reg_valid
)
5583 as_warn (_("No .frame pseudo-op used in PIC code"));
5584 /* Quiet this warning. */
5585 mips_frame_reg_valid
= 1;
5587 if (! mips_cprestore_valid
)
5589 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5590 /* Quiet this warning. */
5591 mips_cprestore_valid
= 1;
5593 if (mips_opts
.noreorder
)
5594 macro_build (NULL
, "nop", "");
5595 expr1
.X_add_number
= mips_cprestore_offset
;
5596 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5599 HAVE_64BIT_ADDRESSES
);
5625 /* Itbl support may require additional care here. */
5630 /* Itbl support may require additional care here. */
5635 /* Itbl support may require additional care here. */
5640 /* Itbl support may require additional care here. */
5652 if (mips_opts
.arch
== CPU_R4650
)
5654 as_bad (_("opcode not supported on this processor"));
5658 /* Itbl support may require additional care here. */
5663 /* Itbl support may require additional care here. */
5668 /* Itbl support may require additional care here. */
5688 if (breg
== treg
|| coproc
|| lr
)
5709 /* Itbl support may require additional care here. */
5714 /* Itbl support may require additional care here. */
5719 /* Itbl support may require additional care here. */
5724 /* Itbl support may require additional care here. */
5740 if (mips_opts
.arch
== CPU_R4650
)
5742 as_bad (_("opcode not supported on this processor"));
5747 /* Itbl support may require additional care here. */
5751 /* Itbl support may require additional care here. */
5756 /* Itbl support may require additional care here. */
5768 /* Itbl support may require additional care here. */
5769 if (mask
== M_LWC1_AB
5770 || mask
== M_SWC1_AB
5771 || mask
== M_LDC1_AB
5772 || mask
== M_SDC1_AB
5781 if (offset_expr
.X_op
!= O_constant
5782 && offset_expr
.X_op
!= O_symbol
)
5784 as_bad (_("expression too complex"));
5785 offset_expr
.X_op
= O_constant
;
5788 /* A constant expression in PIC code can be handled just as it
5789 is in non PIC code. */
5790 if (offset_expr
.X_op
== O_constant
)
5792 if (HAVE_32BIT_ADDRESSES
5793 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5794 as_bad (_("constant too large"));
5796 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5797 & ~(bfd_vma
) 0xffff);
5798 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5800 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5801 tempreg
, tempreg
, breg
);
5802 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5804 else if (mips_pic
== NO_PIC
)
5806 /* If this is a reference to a GP relative symbol, and there
5807 is no base register, we want
5808 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5809 Otherwise, if there is no base register, we want
5810 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5811 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5812 If we have a constant, we need two instructions anyhow,
5813 so we always use the latter form.
5815 If we have a base register, and this is a reference to a
5816 GP relative symbol, we want
5817 addu $tempreg,$breg,$gp
5818 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5820 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5821 addu $tempreg,$tempreg,$breg
5822 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5823 With a constant we always use the latter case.
5825 With 64bit address space and no base register and $at usable,
5827 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5828 lui $at,<sym> (BFD_RELOC_HI16_S)
5829 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5832 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5833 If we have a base register, we want
5834 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5835 lui $at,<sym> (BFD_RELOC_HI16_S)
5836 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5840 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5842 Without $at we can't generate the optimal path for superscalar
5843 processors here since this would require two temporary registers.
5844 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5845 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5847 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5849 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5850 If we have a base register, we want
5851 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5852 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5854 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5856 daddu $tempreg,$tempreg,$breg
5857 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5859 For GP relative symbols in 64bit address space we can use
5860 the same sequence as in 32bit address space. */
5861 if (HAVE_64BIT_SYMBOLS
)
5863 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5864 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5866 relax_start (offset_expr
.X_add_symbol
);
5869 macro_build (&offset_expr
, s
, fmt
, treg
,
5870 BFD_RELOC_GPREL16
, mips_gp_register
);
5874 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5875 tempreg
, breg
, mips_gp_register
);
5876 macro_build (&offset_expr
, s
, fmt
, treg
,
5877 BFD_RELOC_GPREL16
, tempreg
);
5882 if (used_at
== 0 && !mips_opts
.noat
)
5884 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5885 BFD_RELOC_MIPS_HIGHEST
);
5886 macro_build (&offset_expr
, "lui", "t,u", AT
,
5888 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5889 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5891 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5892 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5893 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5894 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5900 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5901 BFD_RELOC_MIPS_HIGHEST
);
5902 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5903 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5904 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5905 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5906 tempreg
, BFD_RELOC_HI16_S
);
5907 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5909 macro_build (NULL
, "daddu", "d,v,t",
5910 tempreg
, tempreg
, breg
);
5911 macro_build (&offset_expr
, s
, fmt
, treg
,
5912 BFD_RELOC_LO16
, tempreg
);
5915 if (mips_relax
.sequence
)
5922 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5923 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5925 relax_start (offset_expr
.X_add_symbol
);
5926 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5930 macro_build_lui (&offset_expr
, tempreg
);
5931 macro_build (&offset_expr
, s
, fmt
, treg
,
5932 BFD_RELOC_LO16
, tempreg
);
5933 if (mips_relax
.sequence
)
5938 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5939 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5941 relax_start (offset_expr
.X_add_symbol
);
5942 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5943 tempreg
, breg
, mips_gp_register
);
5944 macro_build (&offset_expr
, s
, fmt
, treg
,
5945 BFD_RELOC_GPREL16
, tempreg
);
5948 macro_build_lui (&offset_expr
, tempreg
);
5949 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5950 tempreg
, tempreg
, breg
);
5951 macro_build (&offset_expr
, s
, fmt
, treg
,
5952 BFD_RELOC_LO16
, tempreg
);
5953 if (mips_relax
.sequence
)
5957 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5959 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5961 /* If this is a reference to an external symbol, we want
5962 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5964 <op> $treg,0($tempreg)
5966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5968 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5969 <op> $treg,0($tempreg)
5972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5973 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5975 If there is a base register, we add it to $tempreg before
5976 the <op>. If there is a constant, we stick it in the
5977 <op> instruction. We don't handle constants larger than
5978 16 bits, because we have no way to load the upper 16 bits
5979 (actually, we could handle them for the subset of cases
5980 in which we are not using $at). */
5981 assert (offset_expr
.X_op
== O_symbol
);
5984 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5985 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5988 tempreg
, tempreg
, breg
);
5989 macro_build (&offset_expr
, s
, fmt
, treg
,
5990 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5993 expr1
.X_add_number
= offset_expr
.X_add_number
;
5994 offset_expr
.X_add_number
= 0;
5995 if (expr1
.X_add_number
< -0x8000
5996 || expr1
.X_add_number
>= 0x8000)
5997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5998 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5999 lw_reloc_type
, mips_gp_register
);
6001 relax_start (offset_expr
.X_add_symbol
);
6003 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6004 tempreg
, BFD_RELOC_LO16
);
6007 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6008 tempreg
, tempreg
, breg
);
6009 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6011 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6015 /* If this is a reference to an external symbol, we want
6016 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6017 addu $tempreg,$tempreg,$gp
6018 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6019 <op> $treg,0($tempreg)
6021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6023 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6024 <op> $treg,0($tempreg)
6025 If there is a base register, we add it to $tempreg before
6026 the <op>. If there is a constant, we stick it in the
6027 <op> instruction. We don't handle constants larger than
6028 16 bits, because we have no way to load the upper 16 bits
6029 (actually, we could handle them for the subset of cases
6030 in which we are not using $at). */
6031 assert (offset_expr
.X_op
== O_symbol
);
6032 expr1
.X_add_number
= offset_expr
.X_add_number
;
6033 offset_expr
.X_add_number
= 0;
6034 if (expr1
.X_add_number
< -0x8000
6035 || expr1
.X_add_number
>= 0x8000)
6036 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6037 gpdelay
= reg_needs_delay (mips_gp_register
);
6038 relax_start (offset_expr
.X_add_symbol
);
6039 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6040 BFD_RELOC_MIPS_GOT_HI16
);
6041 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6043 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6044 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6047 macro_build (NULL
, "nop", "");
6048 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6049 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6051 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6052 tempreg
, BFD_RELOC_LO16
);
6056 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6057 tempreg
, tempreg
, breg
);
6058 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6060 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6062 /* If this is a reference to an external symbol, we want
6063 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6064 add $tempreg,$tempreg,$gp
6065 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6066 <op> $treg,<ofst>($tempreg)
6067 Otherwise, for local symbols, we want:
6068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6069 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6070 assert (offset_expr
.X_op
== O_symbol
);
6071 expr1
.X_add_number
= offset_expr
.X_add_number
;
6072 offset_expr
.X_add_number
= 0;
6073 if (expr1
.X_add_number
< -0x8000
6074 || expr1
.X_add_number
>= 0x8000)
6075 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6076 relax_start (offset_expr
.X_add_symbol
);
6077 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6078 BFD_RELOC_MIPS_GOT_HI16
);
6079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6081 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6082 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6084 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6085 tempreg
, tempreg
, breg
);
6086 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6089 offset_expr
.X_add_number
= expr1
.X_add_number
;
6090 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6091 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6093 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6094 tempreg
, tempreg
, breg
);
6095 macro_build (&offset_expr
, s
, fmt
, treg
,
6096 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6106 load_register (treg
, &imm_expr
, 0);
6110 load_register (treg
, &imm_expr
, 1);
6114 if (imm_expr
.X_op
== O_constant
)
6117 load_register (AT
, &imm_expr
, 0);
6118 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6123 assert (offset_expr
.X_op
== O_symbol
6124 && strcmp (segment_name (S_GET_SEGMENT
6125 (offset_expr
.X_add_symbol
)),
6127 && offset_expr
.X_add_number
== 0);
6128 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6129 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6134 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6135 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6136 order 32 bits of the value and the low order 32 bits are either
6137 zero or in OFFSET_EXPR. */
6138 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6140 if (HAVE_64BIT_GPRS
)
6141 load_register (treg
, &imm_expr
, 1);
6146 if (target_big_endian
)
6158 load_register (hreg
, &imm_expr
, 0);
6161 if (offset_expr
.X_op
== O_absent
)
6162 move_register (lreg
, 0);
6165 assert (offset_expr
.X_op
== O_constant
);
6166 load_register (lreg
, &offset_expr
, 0);
6173 /* We know that sym is in the .rdata section. First we get the
6174 upper 16 bits of the address. */
6175 if (mips_pic
== NO_PIC
)
6177 macro_build_lui (&offset_expr
, AT
);
6180 else if (mips_pic
== SVR4_PIC
)
6182 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6183 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6189 /* Now we load the register(s). */
6190 if (HAVE_64BIT_GPRS
)
6193 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6198 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6201 /* FIXME: How in the world do we deal with the possible
6203 offset_expr
.X_add_number
+= 4;
6204 macro_build (&offset_expr
, "lw", "t,o(b)",
6205 treg
+ 1, BFD_RELOC_LO16
, AT
);
6211 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6212 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6213 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6214 the value and the low order 32 bits are either zero or in
6216 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6219 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6220 if (HAVE_64BIT_FPRS
)
6222 assert (HAVE_64BIT_GPRS
);
6223 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6227 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6228 if (offset_expr
.X_op
== O_absent
)
6229 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6232 assert (offset_expr
.X_op
== O_constant
);
6233 load_register (AT
, &offset_expr
, 0);
6234 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6240 assert (offset_expr
.X_op
== O_symbol
6241 && offset_expr
.X_add_number
== 0);
6242 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6243 if (strcmp (s
, ".lit8") == 0)
6245 if (mips_opts
.isa
!= ISA_MIPS1
)
6247 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6248 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6251 breg
= mips_gp_register
;
6252 r
= BFD_RELOC_MIPS_LITERAL
;
6257 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6259 if (mips_pic
== SVR4_PIC
)
6260 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6261 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6264 /* FIXME: This won't work for a 64 bit address. */
6265 macro_build_lui (&offset_expr
, AT
);
6268 if (mips_opts
.isa
!= ISA_MIPS1
)
6270 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6271 treg
, BFD_RELOC_LO16
, AT
);
6280 if (mips_opts
.arch
== CPU_R4650
)
6282 as_bad (_("opcode not supported on this processor"));
6285 /* Even on a big endian machine $fn comes before $fn+1. We have
6286 to adjust when loading from memory. */
6289 assert (mips_opts
.isa
== ISA_MIPS1
);
6290 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6291 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6292 /* FIXME: A possible overflow which I don't know how to deal
6294 offset_expr
.X_add_number
+= 4;
6295 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6296 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6301 * The MIPS assembler seems to check for X_add_number not
6302 * being double aligned and generating:
6305 * addiu at,at,%lo(foo+1)
6308 * But, the resulting address is the same after relocation so why
6309 * generate the extra instruction?
6311 if (mips_opts
.arch
== CPU_R4650
)
6313 as_bad (_("opcode not supported on this processor"));
6316 /* Itbl support may require additional care here. */
6318 if (mips_opts
.isa
!= ISA_MIPS1
)
6329 if (mips_opts
.arch
== CPU_R4650
)
6331 as_bad (_("opcode not supported on this processor"));
6335 if (mips_opts
.isa
!= ISA_MIPS1
)
6343 /* Itbl support may require additional care here. */
6348 if (HAVE_64BIT_GPRS
)
6359 if (HAVE_64BIT_GPRS
)
6369 if (offset_expr
.X_op
!= O_symbol
6370 && offset_expr
.X_op
!= O_constant
)
6372 as_bad (_("expression too complex"));
6373 offset_expr
.X_op
= O_constant
;
6376 /* Even on a big endian machine $fn comes before $fn+1. We have
6377 to adjust when loading from memory. We set coproc if we must
6378 load $fn+1 first. */
6379 /* Itbl support may require additional care here. */
6380 if (! target_big_endian
)
6383 if (mips_pic
== NO_PIC
6384 || offset_expr
.X_op
== O_constant
)
6386 /* If this is a reference to a GP relative symbol, we want
6387 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6388 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6389 If we have a base register, we use this
6391 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6392 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6393 If this is not a GP relative symbol, we want
6394 lui $at,<sym> (BFD_RELOC_HI16_S)
6395 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6396 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6397 If there is a base register, we add it to $at after the
6398 lui instruction. If there is a constant, we always use
6400 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6401 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6403 relax_start (offset_expr
.X_add_symbol
);
6406 tempreg
= mips_gp_register
;
6410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6411 AT
, breg
, mips_gp_register
);
6416 /* Itbl support may require additional care here. */
6417 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6418 BFD_RELOC_GPREL16
, tempreg
);
6419 offset_expr
.X_add_number
+= 4;
6421 /* Set mips_optimize to 2 to avoid inserting an
6423 hold_mips_optimize
= mips_optimize
;
6425 /* Itbl support may require additional care here. */
6426 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6427 BFD_RELOC_GPREL16
, tempreg
);
6428 mips_optimize
= hold_mips_optimize
;
6432 /* We just generated two relocs. When tc_gen_reloc
6433 handles this case, it will skip the first reloc and
6434 handle the second. The second reloc already has an
6435 extra addend of 4, which we added above. We must
6436 subtract it out, and then subtract another 4 to make
6437 the first reloc come out right. The second reloc
6438 will come out right because we are going to add 4 to
6439 offset_expr when we build its instruction below.
6441 If we have a symbol, then we don't want to include
6442 the offset, because it will wind up being included
6443 when we generate the reloc. */
6445 if (offset_expr
.X_op
== O_constant
)
6446 offset_expr
.X_add_number
-= 8;
6449 offset_expr
.X_add_number
= -4;
6450 offset_expr
.X_op
= O_constant
;
6454 macro_build_lui (&offset_expr
, AT
);
6456 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6457 /* Itbl support may require additional care here. */
6458 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6459 BFD_RELOC_LO16
, AT
);
6460 /* FIXME: How do we handle overflow here? */
6461 offset_expr
.X_add_number
+= 4;
6462 /* Itbl support may require additional care here. */
6463 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6464 BFD_RELOC_LO16
, AT
);
6465 if (mips_relax
.sequence
)
6468 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6470 /* If this is a reference to an external symbol, we want
6471 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6476 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6478 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6479 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6480 If there is a base register we add it to $at before the
6481 lwc1 instructions. If there is a constant we include it
6482 in the lwc1 instructions. */
6484 expr1
.X_add_number
= offset_expr
.X_add_number
;
6485 if (expr1
.X_add_number
< -0x8000
6486 || expr1
.X_add_number
>= 0x8000 - 4)
6487 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6488 load_got_offset (AT
, &offset_expr
);
6491 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6493 /* Set mips_optimize to 2 to avoid inserting an undesired
6495 hold_mips_optimize
= mips_optimize
;
6498 /* Itbl support may require additional care here. */
6499 relax_start (offset_expr
.X_add_symbol
);
6500 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6501 BFD_RELOC_LO16
, AT
);
6502 expr1
.X_add_number
+= 4;
6503 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6504 BFD_RELOC_LO16
, AT
);
6506 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6507 BFD_RELOC_LO16
, AT
);
6508 offset_expr
.X_add_number
+= 4;
6509 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6510 BFD_RELOC_LO16
, AT
);
6513 mips_optimize
= hold_mips_optimize
;
6515 else if (mips_pic
== SVR4_PIC
)
6519 /* If this is a reference to an external symbol, we want
6520 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6522 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6527 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6529 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6530 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6531 If there is a base register we add it to $at before the
6532 lwc1 instructions. If there is a constant we include it
6533 in the lwc1 instructions. */
6535 expr1
.X_add_number
= offset_expr
.X_add_number
;
6536 offset_expr
.X_add_number
= 0;
6537 if (expr1
.X_add_number
< -0x8000
6538 || expr1
.X_add_number
>= 0x8000 - 4)
6539 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6540 gpdelay
= reg_needs_delay (mips_gp_register
);
6541 relax_start (offset_expr
.X_add_symbol
);
6542 macro_build (&offset_expr
, "lui", "t,u",
6543 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6544 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6545 AT
, AT
, mips_gp_register
);
6546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6547 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6551 /* Itbl support may require additional care here. */
6552 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6553 BFD_RELOC_LO16
, AT
);
6554 expr1
.X_add_number
+= 4;
6556 /* Set mips_optimize to 2 to avoid inserting an undesired
6558 hold_mips_optimize
= mips_optimize
;
6560 /* Itbl support may require additional care here. */
6561 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6562 BFD_RELOC_LO16
, AT
);
6563 mips_optimize
= hold_mips_optimize
;
6564 expr1
.X_add_number
-= 4;
6567 offset_expr
.X_add_number
= expr1
.X_add_number
;
6569 macro_build (NULL
, "nop", "");
6570 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6571 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6574 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6575 /* Itbl support may require additional care here. */
6576 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6577 BFD_RELOC_LO16
, AT
);
6578 offset_expr
.X_add_number
+= 4;
6580 /* Set mips_optimize to 2 to avoid inserting an undesired
6582 hold_mips_optimize
= mips_optimize
;
6584 /* Itbl support may require additional care here. */
6585 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6586 BFD_RELOC_LO16
, AT
);
6587 mips_optimize
= hold_mips_optimize
;
6601 assert (HAVE_32BIT_ADDRESSES
);
6602 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6603 offset_expr
.X_add_number
+= 4;
6604 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6607 /* New code added to support COPZ instructions.
6608 This code builds table entries out of the macros in mip_opcodes.
6609 R4000 uses interlocks to handle coproc delays.
6610 Other chips (like the R3000) require nops to be inserted for delays.
6612 FIXME: Currently, we require that the user handle delays.
6613 In order to fill delay slots for non-interlocked chips,
6614 we must have a way to specify delays based on the coprocessor.
6615 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6616 What are the side-effects of the cop instruction?
6617 What cache support might we have and what are its effects?
6618 Both coprocessor & memory require delays. how long???
6619 What registers are read/set/modified?
6621 If an itbl is provided to interpret cop instructions,
6622 this knowledge can be encoded in the itbl spec. */
6636 /* For now we just do C (same as Cz). The parameter will be
6637 stored in insn_opcode by mips_ip. */
6638 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6642 move_register (dreg
, sreg
);
6645 #ifdef LOSING_COMPILER
6647 /* Try and see if this is a new itbl instruction.
6648 This code builds table entries out of the macros in mip_opcodes.
6649 FIXME: For now we just assemble the expression and pass it's
6650 value along as a 32-bit immediate.
6651 We may want to have the assembler assemble this value,
6652 so that we gain the assembler's knowledge of delay slots,
6654 Would it be more efficient to use mask (id) here? */
6655 if (itbl_have_entries
6656 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6658 s
= ip
->insn_mo
->name
;
6660 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6661 macro_build (&immed_expr
, s
, "C");
6667 if (mips_opts
.noat
&& used_at
)
6668 as_bad (_("Macro used $at after \".set noat\""));
6672 macro2 (struct mips_cl_insn
*ip
)
6674 register int treg
, sreg
, dreg
, breg
;
6689 bfd_reloc_code_real_type r
;
6691 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6692 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6693 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6694 mask
= ip
->insn_mo
->mask
;
6696 expr1
.X_op
= O_constant
;
6697 expr1
.X_op_symbol
= NULL
;
6698 expr1
.X_add_symbol
= NULL
;
6699 expr1
.X_add_number
= 1;
6703 #endif /* LOSING_COMPILER */
6708 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6709 macro_build (NULL
, "mflo", "d", dreg
);
6715 /* The MIPS assembler some times generates shifts and adds. I'm
6716 not trying to be that fancy. GCC should do this for us
6719 load_register (AT
, &imm_expr
, dbl
);
6720 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6721 macro_build (NULL
, "mflo", "d", dreg
);
6737 load_register (AT
, &imm_expr
, dbl
);
6738 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6739 macro_build (NULL
, "mflo", "d", dreg
);
6740 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6741 macro_build (NULL
, "mfhi", "d", AT
);
6743 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6746 expr1
.X_add_number
= 8;
6747 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6748 macro_build (NULL
, "nop", "", 0);
6749 macro_build (NULL
, "break", "c", 6);
6752 macro_build (NULL
, "mflo", "d", dreg
);
6768 load_register (AT
, &imm_expr
, dbl
);
6769 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6770 sreg
, imm
? AT
: treg
);
6771 macro_build (NULL
, "mfhi", "d", AT
);
6772 macro_build (NULL
, "mflo", "d", dreg
);
6774 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6777 expr1
.X_add_number
= 8;
6778 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6779 macro_build (NULL
, "nop", "", 0);
6780 macro_build (NULL
, "break", "c", 6);
6786 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6797 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6798 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6802 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6803 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6804 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6805 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6809 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6820 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6821 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6825 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6826 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6827 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6828 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6836 if (imm_expr
.X_op
!= O_constant
)
6837 as_bad (_("Improper rotate count"));
6838 rot
= imm_expr
.X_add_number
& 0x3f;
6839 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6841 rot
= (64 - rot
) & 0x3f;
6843 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6845 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6850 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6853 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6854 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6857 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6858 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6859 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6867 if (imm_expr
.X_op
!= O_constant
)
6868 as_bad (_("Improper rotate count"));
6869 rot
= imm_expr
.X_add_number
& 0x1f;
6870 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6872 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6877 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6881 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6882 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6883 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6888 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6890 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6894 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6895 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6896 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6897 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6901 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6903 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6907 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6908 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6909 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6910 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6918 if (imm_expr
.X_op
!= O_constant
)
6919 as_bad (_("Improper rotate count"));
6920 rot
= imm_expr
.X_add_number
& 0x3f;
6921 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6924 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6926 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6931 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6934 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6935 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6938 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6939 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6940 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6948 if (imm_expr
.X_op
!= O_constant
)
6949 as_bad (_("Improper rotate count"));
6950 rot
= imm_expr
.X_add_number
& 0x1f;
6951 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6953 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6958 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6962 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6963 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6964 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6969 if (mips_opts
.arch
== CPU_R4650
)
6971 as_bad (_("opcode not supported on this processor"));
6974 assert (mips_opts
.isa
== ISA_MIPS1
);
6975 /* Even on a big endian machine $fn comes before $fn+1. We have
6976 to adjust when storing to memory. */
6977 macro_build (&offset_expr
, "swc1", "T,o(b)",
6978 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6979 offset_expr
.X_add_number
+= 4;
6980 macro_build (&offset_expr
, "swc1", "T,o(b)",
6981 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6986 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6988 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6991 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6992 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6997 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6999 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7004 as_warn (_("Instruction %s: result is always false"),
7006 move_register (dreg
, 0);
7009 if (imm_expr
.X_op
== O_constant
7010 && imm_expr
.X_add_number
>= 0
7011 && imm_expr
.X_add_number
< 0x10000)
7013 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7015 else if (imm_expr
.X_op
== O_constant
7016 && imm_expr
.X_add_number
> -0x8000
7017 && imm_expr
.X_add_number
< 0)
7019 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7020 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7021 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7025 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7026 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7029 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7032 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7038 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7039 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7042 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7044 if (imm_expr
.X_op
== O_constant
7045 && imm_expr
.X_add_number
>= -0x8000
7046 && imm_expr
.X_add_number
< 0x8000)
7048 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7049 dreg
, sreg
, BFD_RELOC_LO16
);
7053 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7054 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7058 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7061 case M_SGT
: /* sreg > treg <==> treg < sreg */
7067 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7070 case M_SGT_I
: /* sreg > I <==> I < sreg */
7077 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7078 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7081 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7087 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7088 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7091 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7098 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7099 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7100 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7104 if (imm_expr
.X_op
== O_constant
7105 && imm_expr
.X_add_number
>= -0x8000
7106 && imm_expr
.X_add_number
< 0x8000)
7108 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7112 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7113 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7117 if (imm_expr
.X_op
== O_constant
7118 && imm_expr
.X_add_number
>= -0x8000
7119 && imm_expr
.X_add_number
< 0x8000)
7121 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7126 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7127 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7132 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7134 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7137 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7138 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7143 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7145 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7150 as_warn (_("Instruction %s: result is always true"),
7152 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7153 dreg
, 0, BFD_RELOC_LO16
);
7156 if (imm_expr
.X_op
== O_constant
7157 && imm_expr
.X_add_number
>= 0
7158 && imm_expr
.X_add_number
< 0x10000)
7160 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7162 else if (imm_expr
.X_op
== O_constant
7163 && imm_expr
.X_add_number
> -0x8000
7164 && imm_expr
.X_add_number
< 0)
7166 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7167 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7168 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7172 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7173 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7176 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7182 if (imm_expr
.X_op
== O_constant
7183 && imm_expr
.X_add_number
> -0x8000
7184 && imm_expr
.X_add_number
<= 0x8000)
7186 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7187 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7188 dreg
, sreg
, BFD_RELOC_LO16
);
7192 load_register (AT
, &imm_expr
, dbl
);
7193 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7199 if (imm_expr
.X_op
== O_constant
7200 && imm_expr
.X_add_number
> -0x8000
7201 && imm_expr
.X_add_number
<= 0x8000)
7203 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7204 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7205 dreg
, sreg
, BFD_RELOC_LO16
);
7209 load_register (AT
, &imm_expr
, dbl
);
7210 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7232 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7233 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7238 assert (mips_opts
.isa
== ISA_MIPS1
);
7240 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7241 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7244 * Is the double cfc1 instruction a bug in the mips assembler;
7245 * or is there a reason for it?
7248 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7249 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7250 macro_build (NULL
, "nop", "");
7251 expr1
.X_add_number
= 3;
7252 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7253 expr1
.X_add_number
= 2;
7254 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7255 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7256 macro_build (NULL
, "nop", "");
7257 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7259 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7260 macro_build (NULL
, "nop", "");
7271 if (offset_expr
.X_add_number
>= 0x7fff)
7272 as_bad (_("operand overflow"));
7273 if (! target_big_endian
)
7274 ++offset_expr
.X_add_number
;
7275 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7276 if (! target_big_endian
)
7277 --offset_expr
.X_add_number
;
7279 ++offset_expr
.X_add_number
;
7280 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7281 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7282 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7295 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7296 as_bad (_("operand overflow"));
7304 if (! target_big_endian
)
7305 offset_expr
.X_add_number
+= off
;
7306 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7307 if (! target_big_endian
)
7308 offset_expr
.X_add_number
-= off
;
7310 offset_expr
.X_add_number
+= off
;
7311 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7313 /* If necessary, move the result in tempreg the final destination. */
7314 if (treg
== tempreg
)
7316 /* Protect second load's delay slot. */
7318 move_register (treg
, tempreg
);
7332 load_address (AT
, &offset_expr
, &used_at
);
7334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7335 if (! target_big_endian
)
7336 expr1
.X_add_number
= off
;
7338 expr1
.X_add_number
= 0;
7339 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7340 if (! target_big_endian
)
7341 expr1
.X_add_number
= 0;
7343 expr1
.X_add_number
= off
;
7344 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7350 load_address (AT
, &offset_expr
, &used_at
);
7352 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7353 if (target_big_endian
)
7354 expr1
.X_add_number
= 0;
7355 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7356 treg
, BFD_RELOC_LO16
, AT
);
7357 if (target_big_endian
)
7358 expr1
.X_add_number
= 1;
7360 expr1
.X_add_number
= 0;
7361 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7362 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7363 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7368 if (offset_expr
.X_add_number
>= 0x7fff)
7369 as_bad (_("operand overflow"));
7370 if (target_big_endian
)
7371 ++offset_expr
.X_add_number
;
7372 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7373 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7374 if (target_big_endian
)
7375 --offset_expr
.X_add_number
;
7377 ++offset_expr
.X_add_number
;
7378 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7391 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7392 as_bad (_("operand overflow"));
7393 if (! target_big_endian
)
7394 offset_expr
.X_add_number
+= off
;
7395 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7396 if (! target_big_endian
)
7397 offset_expr
.X_add_number
-= off
;
7399 offset_expr
.X_add_number
+= off
;
7400 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7414 load_address (AT
, &offset_expr
, &used_at
);
7416 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7417 if (! target_big_endian
)
7418 expr1
.X_add_number
= off
;
7420 expr1
.X_add_number
= 0;
7421 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7422 if (! target_big_endian
)
7423 expr1
.X_add_number
= 0;
7425 expr1
.X_add_number
= off
;
7426 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7431 load_address (AT
, &offset_expr
, &used_at
);
7433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7434 if (! target_big_endian
)
7435 expr1
.X_add_number
= 0;
7436 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7437 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7438 if (! target_big_endian
)
7439 expr1
.X_add_number
= 1;
7441 expr1
.X_add_number
= 0;
7442 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7443 if (! target_big_endian
)
7444 expr1
.X_add_number
= 0;
7446 expr1
.X_add_number
= 1;
7447 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7448 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7449 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7453 /* FIXME: Check if this is one of the itbl macros, since they
7454 are added dynamically. */
7455 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7458 if (mips_opts
.noat
&& used_at
)
7459 as_bad (_("Macro used $at after \".set noat\""));
7462 /* Implement macros in mips16 mode. */
7465 mips16_macro (struct mips_cl_insn
*ip
)
7468 int xreg
, yreg
, zreg
, tmp
;
7471 const char *s
, *s2
, *s3
;
7473 mask
= ip
->insn_mo
->mask
;
7475 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7476 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7477 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7479 expr1
.X_op
= O_constant
;
7480 expr1
.X_op_symbol
= NULL
;
7481 expr1
.X_add_symbol
= NULL
;
7482 expr1
.X_add_number
= 1;
7502 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7503 expr1
.X_add_number
= 2;
7504 macro_build (&expr1
, "bnez", "x,p", yreg
);
7505 macro_build (NULL
, "break", "6", 7);
7507 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7508 since that causes an overflow. We should do that as well,
7509 but I don't see how to do the comparisons without a temporary
7512 macro_build (NULL
, s
, "x", zreg
);
7532 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7533 expr1
.X_add_number
= 2;
7534 macro_build (&expr1
, "bnez", "x,p", yreg
);
7535 macro_build (NULL
, "break", "6", 7);
7537 macro_build (NULL
, s2
, "x", zreg
);
7543 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7544 macro_build (NULL
, "mflo", "x", zreg
);
7552 if (imm_expr
.X_op
!= O_constant
)
7553 as_bad (_("Unsupported large constant"));
7554 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7555 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7559 if (imm_expr
.X_op
!= O_constant
)
7560 as_bad (_("Unsupported large constant"));
7561 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7562 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7566 if (imm_expr
.X_op
!= O_constant
)
7567 as_bad (_("Unsupported large constant"));
7568 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7569 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7591 goto do_reverse_branch
;
7595 goto do_reverse_branch
;
7607 goto do_reverse_branch
;
7618 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7619 macro_build (&offset_expr
, s2
, "p");
7646 goto do_addone_branch_i
;
7651 goto do_addone_branch_i
;
7666 goto do_addone_branch_i
;
7673 if (imm_expr
.X_op
!= O_constant
)
7674 as_bad (_("Unsupported large constant"));
7675 ++imm_expr
.X_add_number
;
7678 macro_build (&imm_expr
, s
, s3
, xreg
);
7679 macro_build (&offset_expr
, s2
, "p");
7683 expr1
.X_add_number
= 0;
7684 macro_build (&expr1
, "slti", "x,8", yreg
);
7686 move_register (xreg
, yreg
);
7687 expr1
.X_add_number
= 2;
7688 macro_build (&expr1
, "bteqz", "p");
7689 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7693 /* For consistency checking, verify that all bits are specified either
7694 by the match/mask part of the instruction definition, or by the
7697 validate_mips_insn (const struct mips_opcode
*opc
)
7699 const char *p
= opc
->args
;
7701 unsigned long used_bits
= opc
->mask
;
7703 if ((used_bits
& opc
->match
) != opc
->match
)
7705 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7706 opc
->name
, opc
->args
);
7709 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7719 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7720 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7721 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7722 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7723 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7724 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7725 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7726 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7727 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7730 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7731 c
, opc
->name
, opc
->args
);
7735 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7736 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7738 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7739 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7740 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7741 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7743 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7744 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7746 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7747 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7749 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7750 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7751 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7752 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7753 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7754 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7755 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7756 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7757 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7758 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7759 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7760 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7761 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7762 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7763 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7764 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7765 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7767 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7768 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7769 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7770 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7772 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7773 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7774 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7775 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7776 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7777 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7778 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7779 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7780 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7783 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7784 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7785 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7786 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7787 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7791 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7792 c
, opc
->name
, opc
->args
);
7796 if (used_bits
!= 0xffffffff)
7798 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7799 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7805 /* This routine assembles an instruction into its binary format. As a
7806 side effect, it sets one of the global variables imm_reloc or
7807 offset_reloc to the type of relocation to do if one of the operands
7808 is an address expression. */
7811 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7816 struct mips_opcode
*insn
;
7819 unsigned int lastregno
= 0;
7820 unsigned int lastpos
= 0;
7821 unsigned int limlo
, limhi
;
7827 /* If the instruction contains a '.', we first try to match an instruction
7828 including the '.'. Then we try again without the '.'. */
7830 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7833 /* If we stopped on whitespace, then replace the whitespace with null for
7834 the call to hash_find. Save the character we replaced just in case we
7835 have to re-parse the instruction. */
7842 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7844 /* If we didn't find the instruction in the opcode table, try again, but
7845 this time with just the instruction up to, but not including the
7849 /* Restore the character we overwrite above (if any). */
7853 /* Scan up to the first '.' or whitespace. */
7855 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7859 /* If we did not find a '.', then we can quit now. */
7862 insn_error
= "unrecognized opcode";
7866 /* Lookup the instruction in the hash table. */
7868 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7870 insn_error
= "unrecognized opcode";
7880 assert (strcmp (insn
->name
, str
) == 0);
7882 if (OPCODE_IS_MEMBER (insn
,
7884 | (file_ase_mips16
? INSN_MIPS16
: 0)
7885 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7886 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7892 if (insn
->pinfo
!= INSN_MACRO
)
7894 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7900 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7901 && strcmp (insn
->name
, insn
[1].name
) == 0)
7910 static char buf
[100];
7912 _("opcode not supported on this processor: %s (%s)"),
7913 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7914 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7923 create_insn (ip
, insn
);
7925 for (args
= insn
->args
;; ++args
)
7929 s
+= strspn (s
, " \t");
7933 case '\0': /* end of args */
7946 INSERT_OPERAND (RS
, *ip
, lastregno
);
7950 INSERT_OPERAND (RT
, *ip
, lastregno
);
7954 INSERT_OPERAND (FT
, *ip
, lastregno
);
7958 INSERT_OPERAND (FS
, *ip
, lastregno
);
7964 /* Handle optional base register.
7965 Either the base register is omitted or
7966 we must have a left paren. */
7967 /* This is dependent on the next operand specifier
7968 is a base register specification. */
7969 assert (args
[1] == 'b' || args
[1] == '5'
7970 || args
[1] == '-' || args
[1] == '4');
7974 case ')': /* these must match exactly */
7981 case '+': /* Opcode extension character. */
7984 case 'A': /* ins/ext position, becomes LSB. */
7993 my_getExpression (&imm_expr
, s
);
7994 check_absolute_expr (ip
, &imm_expr
);
7995 if ((unsigned long) imm_expr
.X_add_number
< limlo
7996 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7998 as_bad (_("Improper position (%lu)"),
7999 (unsigned long) imm_expr
.X_add_number
);
8000 imm_expr
.X_add_number
= limlo
;
8002 lastpos
= imm_expr
.X_add_number
;
8003 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8004 imm_expr
.X_op
= O_absent
;
8008 case 'B': /* ins size, becomes MSB. */
8017 my_getExpression (&imm_expr
, s
);
8018 check_absolute_expr (ip
, &imm_expr
);
8019 /* Check for negative input so that small negative numbers
8020 will not succeed incorrectly. The checks against
8021 (pos+size) transitively check "size" itself,
8022 assuming that "pos" is reasonable. */
8023 if ((long) imm_expr
.X_add_number
< 0
8024 || ((unsigned long) imm_expr
.X_add_number
8026 || ((unsigned long) imm_expr
.X_add_number
8029 as_bad (_("Improper insert size (%lu, position %lu)"),
8030 (unsigned long) imm_expr
.X_add_number
,
8031 (unsigned long) lastpos
);
8032 imm_expr
.X_add_number
= limlo
- lastpos
;
8034 INSERT_OPERAND (INSMSB
, *ip
,
8035 lastpos
+ imm_expr
.X_add_number
- 1);
8036 imm_expr
.X_op
= O_absent
;
8040 case 'C': /* ext size, becomes MSBD. */
8053 my_getExpression (&imm_expr
, s
);
8054 check_absolute_expr (ip
, &imm_expr
);
8055 /* Check for negative input so that small negative numbers
8056 will not succeed incorrectly. The checks against
8057 (pos+size) transitively check "size" itself,
8058 assuming that "pos" is reasonable. */
8059 if ((long) imm_expr
.X_add_number
< 0
8060 || ((unsigned long) imm_expr
.X_add_number
8062 || ((unsigned long) imm_expr
.X_add_number
8065 as_bad (_("Improper extract size (%lu, position %lu)"),
8066 (unsigned long) imm_expr
.X_add_number
,
8067 (unsigned long) lastpos
);
8068 imm_expr
.X_add_number
= limlo
- lastpos
;
8070 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8071 imm_expr
.X_op
= O_absent
;
8076 /* +D is for disassembly only; never match. */
8080 /* "+I" is like "I", except that imm2_expr is used. */
8081 my_getExpression (&imm2_expr
, s
);
8082 if (imm2_expr
.X_op
!= O_big
8083 && imm2_expr
.X_op
!= O_constant
)
8084 insn_error
= _("absolute expression required");
8085 normalize_constant_expr (&imm2_expr
);
8090 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8091 *args
, insn
->name
, insn
->args
);
8092 /* Further processing is fruitless. */
8097 case '<': /* must be at least one digit */
8099 * According to the manual, if the shift amount is greater
8100 * than 31 or less than 0, then the shift amount should be
8101 * mod 32. In reality the mips assembler issues an error.
8102 * We issue a warning and mask out all but the low 5 bits.
8104 my_getExpression (&imm_expr
, s
);
8105 check_absolute_expr (ip
, &imm_expr
);
8106 if ((unsigned long) imm_expr
.X_add_number
> 31)
8107 as_warn (_("Improper shift amount (%lu)"),
8108 (unsigned long) imm_expr
.X_add_number
);
8109 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8110 imm_expr
.X_op
= O_absent
;
8114 case '>': /* shift amount minus 32 */
8115 my_getExpression (&imm_expr
, s
);
8116 check_absolute_expr (ip
, &imm_expr
);
8117 if ((unsigned long) imm_expr
.X_add_number
< 32
8118 || (unsigned long) imm_expr
.X_add_number
> 63)
8120 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8121 imm_expr
.X_op
= O_absent
;
8125 case 'k': /* cache code */
8126 case 'h': /* prefx code */
8127 my_getExpression (&imm_expr
, s
);
8128 check_absolute_expr (ip
, &imm_expr
);
8129 if ((unsigned long) imm_expr
.X_add_number
> 31)
8130 as_warn (_("Invalid value for `%s' (%lu)"),
8132 (unsigned long) imm_expr
.X_add_number
);
8134 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8136 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8137 imm_expr
.X_op
= O_absent
;
8141 case 'c': /* break code */
8142 my_getExpression (&imm_expr
, s
);
8143 check_absolute_expr (ip
, &imm_expr
);
8144 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8145 as_warn (_("Illegal break code (%lu)"),
8146 (unsigned long) imm_expr
.X_add_number
);
8147 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8148 imm_expr
.X_op
= O_absent
;
8152 case 'q': /* lower break code */
8153 my_getExpression (&imm_expr
, s
);
8154 check_absolute_expr (ip
, &imm_expr
);
8155 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8156 as_warn (_("Illegal lower break code (%lu)"),
8157 (unsigned long) imm_expr
.X_add_number
);
8158 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8159 imm_expr
.X_op
= O_absent
;
8163 case 'B': /* 20-bit syscall/break code. */
8164 my_getExpression (&imm_expr
, s
);
8165 check_absolute_expr (ip
, &imm_expr
);
8166 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8167 as_warn (_("Illegal 20-bit code (%lu)"),
8168 (unsigned long) imm_expr
.X_add_number
);
8169 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8170 imm_expr
.X_op
= O_absent
;
8174 case 'C': /* Coprocessor code */
8175 my_getExpression (&imm_expr
, s
);
8176 check_absolute_expr (ip
, &imm_expr
);
8177 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8179 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8180 (unsigned long) imm_expr
.X_add_number
);
8181 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8183 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8184 imm_expr
.X_op
= O_absent
;
8188 case 'J': /* 19-bit wait code. */
8189 my_getExpression (&imm_expr
, s
);
8190 check_absolute_expr (ip
, &imm_expr
);
8191 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8192 as_warn (_("Illegal 19-bit code (%lu)"),
8193 (unsigned long) imm_expr
.X_add_number
);
8194 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8195 imm_expr
.X_op
= O_absent
;
8199 case 'P': /* Performance register */
8200 my_getExpression (&imm_expr
, s
);
8201 check_absolute_expr (ip
, &imm_expr
);
8202 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8203 as_warn (_("Invalid performance register (%lu)"),
8204 (unsigned long) imm_expr
.X_add_number
);
8205 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8206 imm_expr
.X_op
= O_absent
;
8210 case 'b': /* base register */
8211 case 'd': /* destination register */
8212 case 's': /* source register */
8213 case 't': /* target register */
8214 case 'r': /* both target and source */
8215 case 'v': /* both dest and source */
8216 case 'w': /* both dest and target */
8217 case 'E': /* coprocessor target register */
8218 case 'G': /* coprocessor destination register */
8219 case 'K': /* 'rdhwr' destination register */
8220 case 'x': /* ignore register name */
8221 case 'z': /* must be zero register */
8222 case 'U': /* destination register (clo/clz). */
8237 while (ISDIGIT (*s
));
8239 as_bad (_("Invalid register number (%d)"), regno
);
8241 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8245 if (s
[1] == 'r' && s
[2] == 'a')
8250 else if (s
[1] == 'f' && s
[2] == 'p')
8255 else if (s
[1] == 's' && s
[2] == 'p')
8260 else if (s
[1] == 'g' && s
[2] == 'p')
8265 else if (s
[1] == 'a' && s
[2] == 't')
8270 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8275 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8280 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8285 else if (itbl_have_entries
)
8290 p
= s
+ 1; /* advance past '$' */
8291 n
= itbl_get_field (&p
); /* n is name */
8293 /* See if this is a register defined in an
8295 if (itbl_get_reg_val (n
, &r
))
8297 /* Get_field advances to the start of
8298 the next field, so we need to back
8299 rack to the end of the last field. */
8303 s
= strchr (s
, '\0');
8317 as_warn (_("Used $at without \".set noat\""));
8323 if (c
== 'r' || c
== 'v' || c
== 'w')
8330 /* 'z' only matches $0. */
8331 if (c
== 'z' && regno
!= 0)
8334 /* Now that we have assembled one operand, we use the args string
8335 * to figure out where it goes in the instruction. */
8342 INSERT_OPERAND (RS
, *ip
, regno
);
8347 INSERT_OPERAND (RD
, *ip
, regno
);
8350 INSERT_OPERAND (RD
, *ip
, regno
);
8351 INSERT_OPERAND (RT
, *ip
, regno
);
8356 INSERT_OPERAND (RT
, *ip
, regno
);
8359 /* This case exists because on the r3000 trunc
8360 expands into a macro which requires a gp
8361 register. On the r6000 or r4000 it is
8362 assembled into a single instruction which
8363 ignores the register. Thus the insn version
8364 is MIPS_ISA2 and uses 'x', and the macro
8365 version is MIPS_ISA1 and uses 't'. */
8368 /* This case is for the div instruction, which
8369 acts differently if the destination argument
8370 is $0. This only matches $0, and is checked
8371 outside the switch. */
8374 /* Itbl operand; not yet implemented. FIXME ?? */
8376 /* What about all other operands like 'i', which
8377 can be specified in the opcode table? */
8387 INSERT_OPERAND (RS
, *ip
, lastregno
);
8390 INSERT_OPERAND (RT
, *ip
, lastregno
);
8395 case 'O': /* MDMX alignment immediate constant. */
8396 my_getExpression (&imm_expr
, s
);
8397 check_absolute_expr (ip
, &imm_expr
);
8398 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8399 as_warn ("Improper align amount (%ld), using low bits",
8400 (long) imm_expr
.X_add_number
);
8401 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8402 imm_expr
.X_op
= O_absent
;
8406 case 'Q': /* MDMX vector, element sel, or const. */
8409 /* MDMX Immediate. */
8410 my_getExpression (&imm_expr
, s
);
8411 check_absolute_expr (ip
, &imm_expr
);
8412 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8413 as_warn (_("Invalid MDMX Immediate (%ld)"),
8414 (long) imm_expr
.X_add_number
);
8415 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8416 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8417 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8419 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8420 imm_expr
.X_op
= O_absent
;
8424 /* Not MDMX Immediate. Fall through. */
8425 case 'X': /* MDMX destination register. */
8426 case 'Y': /* MDMX source register. */
8427 case 'Z': /* MDMX target register. */
8429 case 'D': /* floating point destination register */
8430 case 'S': /* floating point source register */
8431 case 'T': /* floating point target register */
8432 case 'R': /* floating point source register */
8436 /* Accept $fN for FP and MDMX register numbers, and in
8437 addition accept $vN for MDMX register numbers. */
8438 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8439 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8450 while (ISDIGIT (*s
));
8453 as_bad (_("Invalid float register number (%d)"), regno
);
8455 if ((regno
& 1) != 0
8457 && ! (strcmp (str
, "mtc1") == 0
8458 || strcmp (str
, "mfc1") == 0
8459 || strcmp (str
, "lwc1") == 0
8460 || strcmp (str
, "swc1") == 0
8461 || strcmp (str
, "l.s") == 0
8462 || strcmp (str
, "s.s") == 0))
8463 as_warn (_("Float register should be even, was %d"),
8471 if (c
== 'V' || c
== 'W')
8482 INSERT_OPERAND (FD
, *ip
, regno
);
8487 INSERT_OPERAND (FS
, *ip
, regno
);
8490 /* This is like 'Z', but also needs to fix the MDMX
8491 vector/scalar select bits. Note that the
8492 scalar immediate case is handled above. */
8495 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8496 int max_el
= (is_qh
? 3 : 7);
8498 my_getExpression(&imm_expr
, s
);
8499 check_absolute_expr (ip
, &imm_expr
);
8501 if (imm_expr
.X_add_number
> max_el
)
8502 as_bad(_("Bad element selector %ld"),
8503 (long) imm_expr
.X_add_number
);
8504 imm_expr
.X_add_number
&= max_el
;
8505 ip
->insn_opcode
|= (imm_expr
.X_add_number
8508 imm_expr
.X_op
= O_absent
;
8510 as_warn(_("Expecting ']' found '%s'"), s
);
8516 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8517 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8520 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8527 INSERT_OPERAND (FT
, *ip
, regno
);
8530 INSERT_OPERAND (FR
, *ip
, regno
);
8540 INSERT_OPERAND (FS
, *ip
, lastregno
);
8543 INSERT_OPERAND (FT
, *ip
, lastregno
);
8549 my_getExpression (&imm_expr
, s
);
8550 if (imm_expr
.X_op
!= O_big
8551 && imm_expr
.X_op
!= O_constant
)
8552 insn_error
= _("absolute expression required");
8553 normalize_constant_expr (&imm_expr
);
8558 my_getExpression (&offset_expr
, s
);
8559 *imm_reloc
= BFD_RELOC_32
;
8572 unsigned char temp
[8];
8574 unsigned int length
;
8579 /* These only appear as the last operand in an
8580 instruction, and every instruction that accepts
8581 them in any variant accepts them in all variants.
8582 This means we don't have to worry about backing out
8583 any changes if the instruction does not match.
8585 The difference between them is the size of the
8586 floating point constant and where it goes. For 'F'
8587 and 'L' the constant is 64 bits; for 'f' and 'l' it
8588 is 32 bits. Where the constant is placed is based
8589 on how the MIPS assembler does things:
8592 f -- immediate value
8595 The .lit4 and .lit8 sections are only used if
8596 permitted by the -G argument.
8598 The code below needs to know whether the target register
8599 is 32 or 64 bits wide. It relies on the fact 'f' and
8600 'F' are used with GPR-based instructions and 'l' and
8601 'L' are used with FPR-based instructions. */
8603 f64
= *args
== 'F' || *args
== 'L';
8604 using_gprs
= *args
== 'F' || *args
== 'f';
8606 save_in
= input_line_pointer
;
8607 input_line_pointer
= s
;
8608 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8610 s
= input_line_pointer
;
8611 input_line_pointer
= save_in
;
8612 if (err
!= NULL
&& *err
!= '\0')
8614 as_bad (_("Bad floating point constant: %s"), err
);
8615 memset (temp
, '\0', sizeof temp
);
8616 length
= f64
? 8 : 4;
8619 assert (length
== (unsigned) (f64
? 8 : 4));
8623 && (g_switch_value
< 4
8624 || (temp
[0] == 0 && temp
[1] == 0)
8625 || (temp
[2] == 0 && temp
[3] == 0))))
8627 imm_expr
.X_op
= O_constant
;
8628 if (! target_big_endian
)
8629 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8631 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8634 && ! mips_disable_float_construction
8635 /* Constants can only be constructed in GPRs and
8636 copied to FPRs if the GPRs are at least as wide
8637 as the FPRs. Force the constant into memory if
8638 we are using 64-bit FPRs but the GPRs are only
8641 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8642 && ((temp
[0] == 0 && temp
[1] == 0)
8643 || (temp
[2] == 0 && temp
[3] == 0))
8644 && ((temp
[4] == 0 && temp
[5] == 0)
8645 || (temp
[6] == 0 && temp
[7] == 0)))
8647 /* The value is simple enough to load with a couple of
8648 instructions. If using 32-bit registers, set
8649 imm_expr to the high order 32 bits and offset_expr to
8650 the low order 32 bits. Otherwise, set imm_expr to
8651 the entire 64 bit constant. */
8652 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8654 imm_expr
.X_op
= O_constant
;
8655 offset_expr
.X_op
= O_constant
;
8656 if (! target_big_endian
)
8658 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8659 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8663 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8664 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8666 if (offset_expr
.X_add_number
== 0)
8667 offset_expr
.X_op
= O_absent
;
8669 else if (sizeof (imm_expr
.X_add_number
) > 4)
8671 imm_expr
.X_op
= O_constant
;
8672 if (! target_big_endian
)
8673 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8675 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8679 imm_expr
.X_op
= O_big
;
8680 imm_expr
.X_add_number
= 4;
8681 if (! target_big_endian
)
8683 generic_bignum
[0] = bfd_getl16 (temp
);
8684 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8685 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8686 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8690 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8691 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8692 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8693 generic_bignum
[3] = bfd_getb16 (temp
);
8699 const char *newname
;
8702 /* Switch to the right section. */
8704 subseg
= now_subseg
;
8707 default: /* unused default case avoids warnings. */
8709 newname
= RDATA_SECTION_NAME
;
8710 if (g_switch_value
>= 8)
8714 newname
= RDATA_SECTION_NAME
;
8717 assert (g_switch_value
>= 4);
8721 new_seg
= subseg_new (newname
, (subsegT
) 0);
8722 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8723 bfd_set_section_flags (stdoutput
, new_seg
,
8728 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8729 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8730 && strcmp (TARGET_OS
, "elf") != 0)
8731 record_alignment (new_seg
, 4);
8733 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8735 as_bad (_("Can't use floating point insn in this section"));
8737 /* Set the argument to the current address in the
8739 offset_expr
.X_op
= O_symbol
;
8740 offset_expr
.X_add_symbol
=
8741 symbol_new ("L0\001", now_seg
,
8742 (valueT
) frag_now_fix (), frag_now
);
8743 offset_expr
.X_add_number
= 0;
8745 /* Put the floating point number into the section. */
8746 p
= frag_more ((int) length
);
8747 memcpy (p
, temp
, length
);
8749 /* Switch back to the original section. */
8750 subseg_set (seg
, subseg
);
8755 case 'i': /* 16 bit unsigned immediate */
8756 case 'j': /* 16 bit signed immediate */
8757 *imm_reloc
= BFD_RELOC_LO16
;
8758 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8761 offsetT minval
, maxval
;
8763 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8764 && strcmp (insn
->name
, insn
[1].name
) == 0);
8766 /* If the expression was written as an unsigned number,
8767 only treat it as signed if there are no more
8771 && sizeof (imm_expr
.X_add_number
) <= 4
8772 && imm_expr
.X_op
== O_constant
8773 && imm_expr
.X_add_number
< 0
8774 && imm_expr
.X_unsigned
8778 /* For compatibility with older assemblers, we accept
8779 0x8000-0xffff as signed 16-bit numbers when only
8780 signed numbers are allowed. */
8782 minval
= 0, maxval
= 0xffff;
8784 minval
= -0x8000, maxval
= 0x7fff;
8786 minval
= -0x8000, maxval
= 0xffff;
8788 if (imm_expr
.X_op
!= O_constant
8789 || imm_expr
.X_add_number
< minval
8790 || imm_expr
.X_add_number
> maxval
)
8794 if (imm_expr
.X_op
== O_constant
8795 || imm_expr
.X_op
== O_big
)
8796 as_bad (_("expression out of range"));
8802 case 'o': /* 16 bit offset */
8803 /* Check whether there is only a single bracketed expression
8804 left. If so, it must be the base register and the
8805 constant must be zero. */
8806 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8808 offset_expr
.X_op
= O_constant
;
8809 offset_expr
.X_add_number
= 0;
8813 /* If this value won't fit into a 16 bit offset, then go
8814 find a macro that will generate the 32 bit offset
8816 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8817 && (offset_expr
.X_op
!= O_constant
8818 || offset_expr
.X_add_number
>= 0x8000
8819 || offset_expr
.X_add_number
< -0x8000))
8825 case 'p': /* pc relative offset */
8826 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8827 my_getExpression (&offset_expr
, s
);
8831 case 'u': /* upper 16 bits */
8832 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8833 && imm_expr
.X_op
== O_constant
8834 && (imm_expr
.X_add_number
< 0
8835 || imm_expr
.X_add_number
>= 0x10000))
8836 as_bad (_("lui expression not in range 0..65535"));
8840 case 'a': /* 26 bit address */
8841 my_getExpression (&offset_expr
, s
);
8843 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8846 case 'N': /* 3 bit branch condition code */
8847 case 'M': /* 3 bit compare condition code */
8848 if (strncmp (s
, "$fcc", 4) != 0)
8858 while (ISDIGIT (*s
));
8860 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8861 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8862 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8863 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8864 && (regno
& 1) != 0)
8865 as_warn(_("Condition code register should be even for %s, was %d"),
8867 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8868 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8869 && (regno
& 3) != 0)
8870 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8873 INSERT_OPERAND (BCC
, *ip
, regno
);
8875 INSERT_OPERAND (CCC
, *ip
, regno
);
8879 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8890 while (ISDIGIT (*s
));
8893 c
= 8; /* Invalid sel value. */
8896 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8897 ip
->insn_opcode
|= c
;
8901 /* Must be at least one digit. */
8902 my_getExpression (&imm_expr
, s
);
8903 check_absolute_expr (ip
, &imm_expr
);
8905 if ((unsigned long) imm_expr
.X_add_number
8906 > (unsigned long) OP_MASK_VECBYTE
)
8908 as_bad (_("bad byte vector index (%ld)"),
8909 (long) imm_expr
.X_add_number
);
8910 imm_expr
.X_add_number
= 0;
8913 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8914 imm_expr
.X_op
= O_absent
;
8919 my_getExpression (&imm_expr
, s
);
8920 check_absolute_expr (ip
, &imm_expr
);
8922 if ((unsigned long) imm_expr
.X_add_number
8923 > (unsigned long) OP_MASK_VECALIGN
)
8925 as_bad (_("bad byte vector index (%ld)"),
8926 (long) imm_expr
.X_add_number
);
8927 imm_expr
.X_add_number
= 0;
8930 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8931 imm_expr
.X_op
= O_absent
;
8936 as_bad (_("bad char = '%c'\n"), *args
);
8941 /* Args don't match. */
8942 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8943 !strcmp (insn
->name
, insn
[1].name
))
8947 insn_error
= _("illegal operands");
8952 insn_error
= _("illegal operands");
8957 /* This routine assembles an instruction into its binary format when
8958 assembling for the mips16. As a side effect, it sets one of the
8959 global variables imm_reloc or offset_reloc to the type of
8960 relocation to do if one of the operands is an address expression.
8961 It also sets mips16_small and mips16_ext if the user explicitly
8962 requested a small or extended instruction. */
8965 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8969 struct mips_opcode
*insn
;
8972 unsigned int lastregno
= 0;
8978 mips16_small
= FALSE
;
8981 for (s
= str
; ISLOWER (*s
); ++s
)
8993 if (s
[1] == 't' && s
[2] == ' ')
8996 mips16_small
= TRUE
;
9000 else if (s
[1] == 'e' && s
[2] == ' ')
9009 insn_error
= _("unknown opcode");
9013 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9014 mips16_small
= TRUE
;
9016 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9018 insn_error
= _("unrecognized opcode");
9025 assert (strcmp (insn
->name
, str
) == 0);
9027 create_insn (ip
, insn
);
9028 imm_expr
.X_op
= O_absent
;
9029 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9030 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9031 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9032 imm2_expr
.X_op
= O_absent
;
9033 offset_expr
.X_op
= O_absent
;
9034 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9035 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9036 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9037 for (args
= insn
->args
; 1; ++args
)
9044 /* In this switch statement we call break if we did not find
9045 a match, continue if we did find a match, or return if we
9054 /* Stuff the immediate value in now, if we can. */
9055 if (imm_expr
.X_op
== O_constant
9056 && *imm_reloc
> BFD_RELOC_UNUSED
9057 && insn
->pinfo
!= INSN_MACRO
)
9061 switch (*offset_reloc
)
9063 case BFD_RELOC_MIPS16_HI16_S
:
9064 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9067 case BFD_RELOC_MIPS16_HI16
:
9068 tmp
= imm_expr
.X_add_number
>> 16;
9071 case BFD_RELOC_MIPS16_LO16
:
9072 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9076 case BFD_RELOC_UNUSED
:
9077 tmp
= imm_expr
.X_add_number
;
9083 *offset_reloc
= BFD_RELOC_UNUSED
;
9085 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9086 tmp
, TRUE
, mips16_small
,
9087 mips16_ext
, &ip
->insn_opcode
,
9088 &ip
->use_extend
, &ip
->extend
);
9089 imm_expr
.X_op
= O_absent
;
9090 *imm_reloc
= BFD_RELOC_UNUSED
;
9104 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9107 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9123 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9125 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9152 while (ISDIGIT (*s
));
9155 as_bad (_("invalid register number (%d)"), regno
);
9161 if (s
[1] == 'r' && s
[2] == 'a')
9166 else if (s
[1] == 'f' && s
[2] == 'p')
9171 else if (s
[1] == 's' && s
[2] == 'p')
9176 else if (s
[1] == 'g' && s
[2] == 'p')
9181 else if (s
[1] == 'a' && s
[2] == 't')
9186 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9191 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9196 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9209 if (c
== 'v' || c
== 'w')
9211 regno
= mips16_to_32_reg_map
[lastregno
];
9225 regno
= mips32_to_16_reg_map
[regno
];
9230 regno
= ILLEGAL_REG
;
9235 regno
= ILLEGAL_REG
;
9240 regno
= ILLEGAL_REG
;
9245 if (regno
== AT
&& ! mips_opts
.noat
)
9246 as_warn (_("used $at without \".set noat\""));
9253 if (regno
== ILLEGAL_REG
)
9260 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9264 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9267 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9270 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9276 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9279 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9280 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9290 if (strncmp (s
, "$pc", 3) == 0)
9307 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9310 if (imm_expr
.X_op
!= O_constant
)
9313 ip
->use_extend
= TRUE
;
9318 /* We need to relax this instruction. */
9319 *offset_reloc
= *imm_reloc
;
9320 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9325 *imm_reloc
= BFD_RELOC_UNUSED
;
9333 my_getExpression (&imm_expr
, s
);
9334 if (imm_expr
.X_op
== O_register
)
9336 /* What we thought was an expression turned out to
9339 if (s
[0] == '(' && args
[1] == '(')
9341 /* It looks like the expression was omitted
9342 before a register indirection, which means
9343 that the expression is implicitly zero. We
9344 still set up imm_expr, so that we handle
9345 explicit extensions correctly. */
9346 imm_expr
.X_op
= O_constant
;
9347 imm_expr
.X_add_number
= 0;
9348 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9355 /* We need to relax this instruction. */
9356 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9365 /* We use offset_reloc rather than imm_reloc for the PC
9366 relative operands. This lets macros with both
9367 immediate and address operands work correctly. */
9368 my_getExpression (&offset_expr
, s
);
9370 if (offset_expr
.X_op
== O_register
)
9373 /* We need to relax this instruction. */
9374 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9378 case '6': /* break code */
9379 my_getExpression (&imm_expr
, s
);
9380 check_absolute_expr (ip
, &imm_expr
);
9381 if ((unsigned long) imm_expr
.X_add_number
> 63)
9382 as_warn (_("Invalid value for `%s' (%lu)"),
9384 (unsigned long) imm_expr
.X_add_number
);
9385 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9386 imm_expr
.X_op
= O_absent
;
9390 case 'a': /* 26 bit address */
9391 my_getExpression (&offset_expr
, s
);
9393 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9394 ip
->insn_opcode
<<= 16;
9397 case 'l': /* register list for entry macro */
9398 case 'L': /* register list for exit macro */
9408 int freg
, reg1
, reg2
;
9410 while (*s
== ' ' || *s
== ',')
9414 as_bad (_("can't parse register list"));
9426 while (ISDIGIT (*s
))
9448 as_bad (_("invalid register list"));
9453 while (ISDIGIT (*s
))
9460 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9465 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9470 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9471 mask
|= (reg2
- 3) << 3;
9472 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9473 mask
|= (reg2
- 15) << 1;
9474 else if (reg1
== RA
&& reg2
== RA
)
9478 as_bad (_("invalid register list"));
9482 /* The mask is filled in in the opcode table for the
9483 benefit of the disassembler. We remove it before
9484 applying the actual mask. */
9485 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9486 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9490 case 'e': /* extend code */
9491 my_getExpression (&imm_expr
, s
);
9492 check_absolute_expr (ip
, &imm_expr
);
9493 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9495 as_warn (_("Invalid value for `%s' (%lu)"),
9497 (unsigned long) imm_expr
.X_add_number
);
9498 imm_expr
.X_add_number
&= 0x7ff;
9500 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9501 imm_expr
.X_op
= O_absent
;
9511 /* Args don't match. */
9512 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9513 strcmp (insn
->name
, insn
[1].name
) == 0)
9520 insn_error
= _("illegal operands");
9526 /* This structure holds information we know about a mips16 immediate
9529 struct mips16_immed_operand
9531 /* The type code used in the argument string in the opcode table. */
9533 /* The number of bits in the short form of the opcode. */
9535 /* The number of bits in the extended form of the opcode. */
9537 /* The amount by which the short form is shifted when it is used;
9538 for example, the sw instruction has a shift count of 2. */
9540 /* The amount by which the short form is shifted when it is stored
9541 into the instruction code. */
9543 /* Non-zero if the short form is unsigned. */
9545 /* Non-zero if the extended form is unsigned. */
9547 /* Non-zero if the value is PC relative. */
9551 /* The mips16 immediate operand types. */
9553 static const struct mips16_immed_operand mips16_immed_operands
[] =
9555 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9556 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9557 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9558 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9559 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9560 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9561 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9562 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9563 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9564 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9565 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9566 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9567 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9568 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9569 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9570 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9571 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9572 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9573 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9574 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9575 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9578 #define MIPS16_NUM_IMMED \
9579 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9581 /* Handle a mips16 instruction with an immediate value. This or's the
9582 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9583 whether an extended value is needed; if one is needed, it sets
9584 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9585 If SMALL is true, an unextended opcode was explicitly requested.
9586 If EXT is true, an extended opcode was explicitly requested. If
9587 WARN is true, warn if EXT does not match reality. */
9590 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9591 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9592 unsigned long *insn
, bfd_boolean
*use_extend
,
9593 unsigned short *extend
)
9595 register const struct mips16_immed_operand
*op
;
9596 int mintiny
, maxtiny
;
9597 bfd_boolean needext
;
9599 op
= mips16_immed_operands
;
9600 while (op
->type
!= type
)
9603 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9608 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9611 maxtiny
= 1 << op
->nbits
;
9616 maxtiny
= (1 << op
->nbits
) - 1;
9621 mintiny
= - (1 << (op
->nbits
- 1));
9622 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9625 /* Branch offsets have an implicit 0 in the lowest bit. */
9626 if (type
== 'p' || type
== 'q')
9629 if ((val
& ((1 << op
->shift
) - 1)) != 0
9630 || val
< (mintiny
<< op
->shift
)
9631 || val
> (maxtiny
<< op
->shift
))
9636 if (warn
&& ext
&& ! needext
)
9637 as_warn_where (file
, line
,
9638 _("extended operand requested but not required"));
9639 if (small
&& needext
)
9640 as_bad_where (file
, line
, _("invalid unextended operand value"));
9642 if (small
|| (! ext
&& ! needext
))
9646 *use_extend
= FALSE
;
9647 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9648 insnval
<<= op
->op_shift
;
9653 long minext
, maxext
;
9659 maxext
= (1 << op
->extbits
) - 1;
9663 minext
= - (1 << (op
->extbits
- 1));
9664 maxext
= (1 << (op
->extbits
- 1)) - 1;
9666 if (val
< minext
|| val
> maxext
)
9667 as_bad_where (file
, line
,
9668 _("operand value out of range for instruction"));
9671 if (op
->extbits
== 16)
9673 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9676 else if (op
->extbits
== 15)
9678 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9683 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9687 *extend
= (unsigned short) extval
;
9692 struct percent_op_match
9695 bfd_reloc_code_real_type reloc
;
9698 static const struct percent_op_match mips_percent_op
[] =
9700 {"%lo", BFD_RELOC_LO16
},
9702 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9703 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9704 {"%call16", BFD_RELOC_MIPS_CALL16
},
9705 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9706 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9707 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9708 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9709 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9710 {"%got", BFD_RELOC_MIPS_GOT16
},
9711 {"%gp_rel", BFD_RELOC_GPREL16
},
9712 {"%half", BFD_RELOC_16
},
9713 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9714 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9715 {"%neg", BFD_RELOC_MIPS_SUB
},
9716 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9717 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9718 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9719 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9720 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9721 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9722 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9724 {"%hi", BFD_RELOC_HI16_S
}
9727 static const struct percent_op_match mips16_percent_op
[] =
9729 {"%lo", BFD_RELOC_MIPS16_LO16
},
9730 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9731 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9735 /* Return true if *STR points to a relocation operator. When returning true,
9736 move *STR over the operator and store its relocation code in *RELOC.
9737 Leave both *STR and *RELOC alone when returning false. */
9740 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9742 const struct percent_op_match
*percent_op
;
9745 if (mips_opts
.mips16
)
9747 percent_op
= mips16_percent_op
;
9748 limit
= ARRAY_SIZE (mips16_percent_op
);
9752 percent_op
= mips_percent_op
;
9753 limit
= ARRAY_SIZE (mips_percent_op
);
9756 for (i
= 0; i
< limit
; i
++)
9757 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9759 int len
= strlen (percent_op
[i
].str
);
9761 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9764 *str
+= strlen (percent_op
[i
].str
);
9765 *reloc
= percent_op
[i
].reloc
;
9767 /* Check whether the output BFD supports this relocation.
9768 If not, issue an error and fall back on something safe. */
9769 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9771 as_bad ("relocation %s isn't supported by the current ABI",
9773 *reloc
= BFD_RELOC_UNUSED
;
9781 /* Parse string STR as a 16-bit relocatable operand. Store the
9782 expression in *EP and the relocations in the array starting
9783 at RELOC. Return the number of relocation operators used.
9785 On exit, EXPR_END points to the first character after the expression. */
9788 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9791 bfd_reloc_code_real_type reversed_reloc
[3];
9792 size_t reloc_index
, i
;
9793 int crux_depth
, str_depth
;
9796 /* Search for the start of the main expression, recoding relocations
9797 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9798 of the main expression and with CRUX_DEPTH containing the number
9799 of open brackets at that point. */
9806 crux_depth
= str_depth
;
9808 /* Skip over whitespace and brackets, keeping count of the number
9810 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9815 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9816 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9818 my_getExpression (ep
, crux
);
9821 /* Match every open bracket. */
9822 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9827 as_bad ("unclosed '('");
9831 if (reloc_index
!= 0)
9833 prev_reloc_op_frag
= frag_now
;
9834 for (i
= 0; i
< reloc_index
; i
++)
9835 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9842 my_getExpression (expressionS
*ep
, char *str
)
9847 save_in
= input_line_pointer
;
9848 input_line_pointer
= str
;
9850 expr_end
= input_line_pointer
;
9851 input_line_pointer
= save_in
;
9853 /* If we are in mips16 mode, and this is an expression based on `.',
9854 then we bump the value of the symbol by 1 since that is how other
9855 text symbols are handled. We don't bother to handle complex
9856 expressions, just `.' plus or minus a constant. */
9857 if (mips_opts
.mips16
9858 && ep
->X_op
== O_symbol
9859 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9860 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9861 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9862 && symbol_constant_p (ep
->X_add_symbol
)
9863 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9864 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9867 /* Turn a string in input_line_pointer into a floating point constant
9868 of type TYPE, and store the appropriate bytes in *LITP. The number
9869 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9870 returned, or NULL on OK. */
9873 md_atof (int type
, char *litP
, int *sizeP
)
9876 LITTLENUM_TYPE words
[4];
9892 return _("bad call to md_atof");
9895 t
= atof_ieee (input_line_pointer
, type
, words
);
9897 input_line_pointer
= t
;
9901 if (! target_big_endian
)
9903 for (i
= prec
- 1; i
>= 0; i
--)
9905 md_number_to_chars (litP
, words
[i
], 2);
9911 for (i
= 0; i
< prec
; i
++)
9913 md_number_to_chars (litP
, words
[i
], 2);
9922 md_number_to_chars (char *buf
, valueT val
, int n
)
9924 if (target_big_endian
)
9925 number_to_chars_bigendian (buf
, val
, n
);
9927 number_to_chars_littleendian (buf
, val
, n
);
9931 static int support_64bit_objects(void)
9933 const char **list
, **l
;
9936 list
= bfd_target_list ();
9937 for (l
= list
; *l
!= NULL
; l
++)
9939 /* This is traditional mips */
9940 if (strcmp (*l
, "elf64-tradbigmips") == 0
9941 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9943 if (strcmp (*l
, "elf64-bigmips") == 0
9944 || strcmp (*l
, "elf64-littlemips") == 0)
9951 #endif /* OBJ_ELF */
9953 const char *md_shortopts
= "O::g::G:";
9955 struct option md_longopts
[] =
9957 /* Options which specify architecture. */
9958 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9959 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9960 {"march", required_argument
, NULL
, OPTION_MARCH
},
9961 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9962 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9963 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9964 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9965 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9966 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9967 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9968 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9969 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9970 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9971 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9972 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9973 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9974 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9975 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9976 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9977 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9978 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9979 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9980 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9981 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9983 /* Options which specify Application Specific Extensions (ASEs). */
9984 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9985 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9986 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9987 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9988 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9989 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9990 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9991 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9992 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9993 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9994 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9995 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9996 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9998 /* Old-style architecture options. Don't add more of these. */
9999 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10000 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10001 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10002 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10003 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10004 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10005 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10006 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10007 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10008 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10009 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10010 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10011 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10012 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10013 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10014 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10015 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10017 /* Options which enable bug fixes. */
10018 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10019 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10020 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10021 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10022 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10023 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10024 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10025 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10026 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10027 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10028 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10029 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10030 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10031 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10033 /* Miscellaneous options. */
10034 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10035 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10036 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10037 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10038 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10039 {"break", no_argument
, NULL
, OPTION_BREAK
},
10040 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10041 #define OPTION_EB (OPTION_MISC_BASE + 2)
10042 {"EB", no_argument
, NULL
, OPTION_EB
},
10043 #define OPTION_EL (OPTION_MISC_BASE + 3)
10044 {"EL", no_argument
, NULL
, OPTION_EL
},
10045 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10046 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10047 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10048 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10049 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10050 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10051 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10052 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10053 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10054 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10055 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10056 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10057 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10058 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10059 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10060 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10061 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10062 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10063 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10064 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10065 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10066 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10067 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10068 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10070 /* ELF-specific options. */
10072 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10073 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10074 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10075 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10076 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10077 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10078 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10079 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10080 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10081 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10082 #define OPTION_32 (OPTION_ELF_BASE + 4)
10083 {"32", no_argument
, NULL
, OPTION_32
},
10084 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10085 {"n32", no_argument
, NULL
, OPTION_N32
},
10086 #define OPTION_64 (OPTION_ELF_BASE + 6)
10087 {"64", no_argument
, NULL
, OPTION_64
},
10088 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10089 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10090 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10091 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10092 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10093 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10094 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10095 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10096 #endif /* OBJ_ELF */
10098 {NULL
, no_argument
, NULL
, 0}
10100 size_t md_longopts_size
= sizeof (md_longopts
);
10102 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10103 NEW_VALUE. Warn if another value was already specified. Note:
10104 we have to defer parsing the -march and -mtune arguments in order
10105 to handle 'from-abi' correctly, since the ABI might be specified
10106 in a later argument. */
10109 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10111 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10112 as_warn (_("A different %s was already specified, is now %s"),
10113 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10116 *string_ptr
= new_value
;
10120 md_parse_option (int c
, char *arg
)
10124 case OPTION_CONSTRUCT_FLOATS
:
10125 mips_disable_float_construction
= 0;
10128 case OPTION_NO_CONSTRUCT_FLOATS
:
10129 mips_disable_float_construction
= 1;
10141 target_big_endian
= 1;
10145 target_big_endian
= 0;
10149 if (arg
&& arg
[1] == '0')
10159 mips_debug
= atoi (arg
);
10160 /* When the MIPS assembler sees -g or -g2, it does not do
10161 optimizations which limit full symbolic debugging. We take
10162 that to be equivalent to -O0. */
10163 if (mips_debug
== 2)
10168 file_mips_isa
= ISA_MIPS1
;
10172 file_mips_isa
= ISA_MIPS2
;
10176 file_mips_isa
= ISA_MIPS3
;
10180 file_mips_isa
= ISA_MIPS4
;
10184 file_mips_isa
= ISA_MIPS5
;
10187 case OPTION_MIPS32
:
10188 file_mips_isa
= ISA_MIPS32
;
10191 case OPTION_MIPS32R2
:
10192 file_mips_isa
= ISA_MIPS32R2
;
10195 case OPTION_MIPS64R2
:
10196 file_mips_isa
= ISA_MIPS64R2
;
10199 case OPTION_MIPS64
:
10200 file_mips_isa
= ISA_MIPS64
;
10204 mips_set_option_string (&mips_tune_string
, arg
);
10208 mips_set_option_string (&mips_arch_string
, arg
);
10212 mips_set_option_string (&mips_arch_string
, "4650");
10213 mips_set_option_string (&mips_tune_string
, "4650");
10216 case OPTION_NO_M4650
:
10220 mips_set_option_string (&mips_arch_string
, "4010");
10221 mips_set_option_string (&mips_tune_string
, "4010");
10224 case OPTION_NO_M4010
:
10228 mips_set_option_string (&mips_arch_string
, "4100");
10229 mips_set_option_string (&mips_tune_string
, "4100");
10232 case OPTION_NO_M4100
:
10236 mips_set_option_string (&mips_arch_string
, "3900");
10237 mips_set_option_string (&mips_tune_string
, "3900");
10240 case OPTION_NO_M3900
:
10244 mips_opts
.ase_mdmx
= 1;
10247 case OPTION_NO_MDMX
:
10248 mips_opts
.ase_mdmx
= 0;
10251 case OPTION_MIPS16
:
10252 mips_opts
.mips16
= 1;
10253 mips_no_prev_insn ();
10256 case OPTION_NO_MIPS16
:
10257 mips_opts
.mips16
= 0;
10258 mips_no_prev_insn ();
10261 case OPTION_MIPS3D
:
10262 mips_opts
.ase_mips3d
= 1;
10265 case OPTION_NO_MIPS3D
:
10266 mips_opts
.ase_mips3d
= 0;
10269 case OPTION_FIX_VR4120
:
10270 mips_fix_vr4120
= 1;
10273 case OPTION_NO_FIX_VR4120
:
10274 mips_fix_vr4120
= 0;
10277 case OPTION_FIX_VR4130
:
10278 mips_fix_vr4130
= 1;
10281 case OPTION_NO_FIX_VR4130
:
10282 mips_fix_vr4130
= 0;
10285 case OPTION_RELAX_BRANCH
:
10286 mips_relax_branch
= 1;
10289 case OPTION_NO_RELAX_BRANCH
:
10290 mips_relax_branch
= 0;
10293 case OPTION_MSHARED
:
10294 mips_in_shared
= TRUE
;
10297 case OPTION_MNO_SHARED
:
10298 mips_in_shared
= FALSE
;
10301 case OPTION_MSYM32
:
10302 mips_opts
.sym32
= TRUE
;
10305 case OPTION_MNO_SYM32
:
10306 mips_opts
.sym32
= FALSE
;
10310 /* When generating ELF code, we permit -KPIC and -call_shared to
10311 select SVR4_PIC, and -non_shared to select no PIC. This is
10312 intended to be compatible with Irix 5. */
10313 case OPTION_CALL_SHARED
:
10314 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10316 as_bad (_("-call_shared is supported only for ELF format"));
10319 mips_pic
= SVR4_PIC
;
10320 mips_abicalls
= TRUE
;
10321 if (g_switch_seen
&& g_switch_value
!= 0)
10323 as_bad (_("-G may not be used with SVR4 PIC code"));
10326 g_switch_value
= 0;
10329 case OPTION_NON_SHARED
:
10330 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10332 as_bad (_("-non_shared is supported only for ELF format"));
10336 mips_abicalls
= FALSE
;
10339 /* The -xgot option tells the assembler to use 32 offsets when
10340 accessing the got in SVR4_PIC mode. It is for Irix
10345 #endif /* OBJ_ELF */
10348 g_switch_value
= atoi (arg
);
10350 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10352 as_bad (_("-G may not be used with SVR4 PIC code"));
10358 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10361 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10363 as_bad (_("-32 is supported for ELF format only"));
10366 mips_abi
= O32_ABI
;
10370 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10372 as_bad (_("-n32 is supported for ELF format only"));
10375 mips_abi
= N32_ABI
;
10379 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10381 as_bad (_("-64 is supported for ELF format only"));
10384 mips_abi
= N64_ABI
;
10385 if (! support_64bit_objects())
10386 as_fatal (_("No compiled in support for 64 bit object file format"));
10388 #endif /* OBJ_ELF */
10391 file_mips_gp32
= 1;
10395 file_mips_gp32
= 0;
10399 file_mips_fp32
= 1;
10403 file_mips_fp32
= 0;
10408 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10410 as_bad (_("-mabi is supported for ELF format only"));
10413 if (strcmp (arg
, "32") == 0)
10414 mips_abi
= O32_ABI
;
10415 else if (strcmp (arg
, "o64") == 0)
10416 mips_abi
= O64_ABI
;
10417 else if (strcmp (arg
, "n32") == 0)
10418 mips_abi
= N32_ABI
;
10419 else if (strcmp (arg
, "64") == 0)
10421 mips_abi
= N64_ABI
;
10422 if (! support_64bit_objects())
10423 as_fatal (_("No compiled in support for 64 bit object file "
10426 else if (strcmp (arg
, "eabi") == 0)
10427 mips_abi
= EABI_ABI
;
10430 as_fatal (_("invalid abi -mabi=%s"), arg
);
10434 #endif /* OBJ_ELF */
10436 case OPTION_M7000_HILO_FIX
:
10437 mips_7000_hilo_fix
= TRUE
;
10440 case OPTION_MNO_7000_HILO_FIX
:
10441 mips_7000_hilo_fix
= FALSE
;
10445 case OPTION_MDEBUG
:
10446 mips_flag_mdebug
= TRUE
;
10449 case OPTION_NO_MDEBUG
:
10450 mips_flag_mdebug
= FALSE
;
10454 mips_flag_pdr
= TRUE
;
10457 case OPTION_NO_PDR
:
10458 mips_flag_pdr
= FALSE
;
10460 #endif /* OBJ_ELF */
10469 /* Set up globals to generate code for the ISA or processor
10470 described by INFO. */
10473 mips_set_architecture (const struct mips_cpu_info
*info
)
10477 file_mips_arch
= info
->cpu
;
10478 mips_opts
.arch
= info
->cpu
;
10479 mips_opts
.isa
= info
->isa
;
10484 /* Likewise for tuning. */
10487 mips_set_tune (const struct mips_cpu_info
*info
)
10490 mips_tune
= info
->cpu
;
10495 mips_after_parse_args (void)
10497 const struct mips_cpu_info
*arch_info
= 0;
10498 const struct mips_cpu_info
*tune_info
= 0;
10500 /* GP relative stuff not working for PE */
10501 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10503 if (g_switch_seen
&& g_switch_value
!= 0)
10504 as_bad (_("-G not supported in this configuration."));
10505 g_switch_value
= 0;
10508 if (mips_abi
== NO_ABI
)
10509 mips_abi
= MIPS_DEFAULT_ABI
;
10511 /* The following code determines the architecture and register size.
10512 Similar code was added to GCC 3.3 (see override_options() in
10513 config/mips/mips.c). The GAS and GCC code should be kept in sync
10514 as much as possible. */
10516 if (mips_arch_string
!= 0)
10517 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10519 if (file_mips_isa
!= ISA_UNKNOWN
)
10521 /* Handle -mipsN. At this point, file_mips_isa contains the
10522 ISA level specified by -mipsN, while arch_info->isa contains
10523 the -march selection (if any). */
10524 if (arch_info
!= 0)
10526 /* -march takes precedence over -mipsN, since it is more descriptive.
10527 There's no harm in specifying both as long as the ISA levels
10529 if (file_mips_isa
!= arch_info
->isa
)
10530 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10531 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10532 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10535 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10538 if (arch_info
== 0)
10539 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10541 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10542 as_bad ("-march=%s is not compatible with the selected ABI",
10545 mips_set_architecture (arch_info
);
10547 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10548 if (mips_tune_string
!= 0)
10549 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10551 if (tune_info
== 0)
10552 mips_set_tune (arch_info
);
10554 mips_set_tune (tune_info
);
10556 if (file_mips_gp32
>= 0)
10558 /* The user specified the size of the integer registers. Make sure
10559 it agrees with the ABI and ISA. */
10560 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10561 as_bad (_("-mgp64 used with a 32-bit processor"));
10562 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10563 as_bad (_("-mgp32 used with a 64-bit ABI"));
10564 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10565 as_bad (_("-mgp64 used with a 32-bit ABI"));
10569 /* Infer the integer register size from the ABI and processor.
10570 Restrict ourselves to 32-bit registers if that's all the
10571 processor has, or if the ABI cannot handle 64-bit registers. */
10572 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10573 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10576 /* ??? GAS treats single-float processors as though they had 64-bit
10577 float registers (although it complains when double-precision
10578 instructions are used). As things stand, saying they have 32-bit
10579 registers would lead to spurious "register must be even" messages.
10580 So here we assume float registers are always the same size as
10581 integer ones, unless the user says otherwise. */
10582 if (file_mips_fp32
< 0)
10583 file_mips_fp32
= file_mips_gp32
;
10585 /* End of GCC-shared inference code. */
10587 /* This flag is set when we have a 64-bit capable CPU but use only
10588 32-bit wide registers. Note that EABI does not use it. */
10589 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10590 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10591 || mips_abi
== O32_ABI
))
10592 mips_32bitmode
= 1;
10594 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10595 as_bad (_("trap exception not supported at ISA 1"));
10597 /* If the selected architecture includes support for ASEs, enable
10598 generation of code for them. */
10599 if (mips_opts
.mips16
== -1)
10600 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10601 if (mips_opts
.ase_mips3d
== -1)
10602 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10603 if (mips_opts
.ase_mdmx
== -1)
10604 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10606 file_mips_isa
= mips_opts
.isa
;
10607 file_ase_mips16
= mips_opts
.mips16
;
10608 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10609 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10610 mips_opts
.gp32
= file_mips_gp32
;
10611 mips_opts
.fp32
= file_mips_fp32
;
10613 if (mips_flag_mdebug
< 0)
10615 #ifdef OBJ_MAYBE_ECOFF
10616 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10617 mips_flag_mdebug
= 1;
10619 #endif /* OBJ_MAYBE_ECOFF */
10620 mips_flag_mdebug
= 0;
10625 mips_init_after_args (void)
10627 /* initialize opcodes */
10628 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10629 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10633 md_pcrel_from (fixS
*fixP
)
10635 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10636 switch (fixP
->fx_r_type
)
10638 case BFD_RELOC_16_PCREL_S2
:
10639 case BFD_RELOC_MIPS_JMP
:
10640 /* Return the address of the delay slot. */
10647 /* This is called before the symbol table is processed. In order to
10648 work with gcc when using mips-tfile, we must keep all local labels.
10649 However, in other cases, we want to discard them. If we were
10650 called with -g, but we didn't see any debugging information, it may
10651 mean that gcc is smuggling debugging information through to
10652 mips-tfile, in which case we must generate all local labels. */
10655 mips_frob_file_before_adjust (void)
10657 #ifndef NO_ECOFF_DEBUGGING
10658 if (ECOFF_DEBUGGING
10660 && ! ecoff_debugging_seen
)
10661 flag_keep_locals
= 1;
10665 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10666 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10667 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10668 relocation operators.
10670 For our purposes, a %lo() expression matches a %got() or %hi()
10673 (a) it refers to the same symbol; and
10674 (b) the offset applied in the %lo() expression is no lower than
10675 the offset applied in the %got() or %hi().
10677 (b) allows us to cope with code like:
10680 lh $4,%lo(foo+2)($4)
10682 ...which is legal on RELA targets, and has a well-defined behaviour
10683 if the user knows that adding 2 to "foo" will not induce a carry to
10686 When several %lo()s match a particular %got() or %hi(), we use the
10687 following rules to distinguish them:
10689 (1) %lo()s with smaller offsets are a better match than %lo()s with
10692 (2) %lo()s with no matching %got() or %hi() are better than those
10693 that already have a matching %got() or %hi().
10695 (3) later %lo()s are better than earlier %lo()s.
10697 These rules are applied in order.
10699 (1) means, among other things, that %lo()s with identical offsets are
10700 chosen if they exist.
10702 (2) means that we won't associate several high-part relocations with
10703 the same low-part relocation unless there's no alternative. Having
10704 several high parts for the same low part is a GNU extension; this rule
10705 allows careful users to avoid it.
10707 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10708 with the last high-part relocation being at the front of the list.
10709 It therefore makes sense to choose the last matching low-part
10710 relocation, all other things being equal. It's also easier
10711 to code that way. */
10714 mips_frob_file (void)
10716 struct mips_hi_fixup
*l
;
10718 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10720 segment_info_type
*seginfo
;
10721 bfd_boolean matched_lo_p
;
10722 fixS
**hi_pos
, **lo_pos
, **pos
;
10724 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10726 /* If a GOT16 relocation turns out to be against a global symbol,
10727 there isn't supposed to be a matching LO. */
10728 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10729 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10732 /* Check quickly whether the next fixup happens to be a matching %lo. */
10733 if (fixup_has_matching_lo_p (l
->fixp
))
10736 seginfo
= seg_info (l
->seg
);
10738 /* Set HI_POS to the position of this relocation in the chain.
10739 Set LO_POS to the position of the chosen low-part relocation.
10740 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10741 relocation that matches an immediately-preceding high-part
10745 matched_lo_p
= FALSE
;
10746 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10748 if (*pos
== l
->fixp
)
10751 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
10752 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
10753 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10754 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10756 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10758 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10761 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10762 && fixup_has_matching_lo_p (*pos
));
10765 /* If we found a match, remove the high-part relocation from its
10766 current position and insert it before the low-part relocation.
10767 Make the offsets match so that fixup_has_matching_lo_p()
10770 We don't warn about unmatched high-part relocations since some
10771 versions of gcc have been known to emit dead "lui ...%hi(...)"
10773 if (lo_pos
!= NULL
)
10775 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10776 if (l
->fixp
->fx_next
!= *lo_pos
)
10778 *hi_pos
= l
->fixp
->fx_next
;
10779 l
->fixp
->fx_next
= *lo_pos
;
10786 /* We may have combined relocations without symbols in the N32/N64 ABI.
10787 We have to prevent gas from dropping them. */
10790 mips_force_relocation (fixS
*fixp
)
10792 if (generic_force_reloc (fixp
))
10796 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10797 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10798 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10799 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10805 /* This hook is called before a fix is simplified. We don't really
10806 decide whether to skip a fix here. Rather, we turn global symbols
10807 used as branch targets into local symbols, such that they undergo
10808 simplification. We can only do this if the symbol is defined and
10809 it is in the same section as the branch. If this doesn't hold, we
10810 emit a better error message than just saying the relocation is not
10811 valid for the selected object format.
10813 FIXP is the fix-up we're going to try to simplify, SEG is the
10814 segment in which the fix up occurs. The return value should be
10815 non-zero to indicate the fix-up is valid for further
10816 simplifications. */
10819 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10821 /* There's a lot of discussion on whether it should be possible to
10822 use R_MIPS_PC16 to represent branch relocations. The outcome
10823 seems to be that it can, but gas/bfd are very broken in creating
10824 RELA relocations for this, so for now we only accept branches to
10825 symbols in the same section. Anything else is of dubious value,
10826 since there's no guarantee that at link time the symbol would be
10827 in range. Even for branches to local symbols this is arguably
10828 wrong, since it we assume the symbol is not going to be
10829 overridden, which should be possible per ELF library semantics,
10830 but then, there isn't a dynamic relocation that could be used to
10831 this effect, and the target would likely be out of range as well.
10833 Unfortunately, it seems that there is too much code out there
10834 that relies on branches to symbols that are global to be resolved
10835 as if they were local, like the IRIX tools do, so we do it as
10836 well, but with a warning so that people are reminded to fix their
10837 code. If we ever get back to using R_MIPS_PC16 for branch
10838 targets, this entire block should go away (and probably the
10839 whole function). */
10841 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10842 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10843 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10844 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10847 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10850 _("Cannot branch to undefined symbol."));
10851 /* Avoid any further errors about this fixup. */
10854 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10857 _("Cannot branch to symbol in another section."));
10860 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10862 symbolS
*sym
= fixP
->fx_addsy
;
10864 if (mips_pic
== SVR4_PIC
)
10865 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10866 _("Pretending global symbol used as branch target is local."));
10868 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10869 S_GET_SEGMENT (sym
),
10871 symbol_get_frag (sym
));
10872 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10873 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10874 assert (symbol_resolved_p (sym
));
10875 symbol_mark_resolved (fixP
->fx_addsy
);
10882 /* Apply a fixup to the object file. */
10885 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10889 reloc_howto_type
*howto
;
10891 /* We ignore generic BFD relocations we don't know about. */
10892 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10896 assert (fixP
->fx_size
== 4
10897 || fixP
->fx_r_type
== BFD_RELOC_16
10898 || fixP
->fx_r_type
== BFD_RELOC_64
10899 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10900 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10901 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10902 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10904 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10906 assert (! fixP
->fx_pcrel
);
10908 /* Don't treat parts of a composite relocation as done. There are two
10911 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10912 should nevertheless be emitted if the first part is.
10914 (2) In normal usage, composite relocations are never assembly-time
10915 constants. The easiest way of dealing with the pathological
10916 exceptions is to generate a relocation against STN_UNDEF and
10917 leave everything up to the linker. */
10918 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10921 switch (fixP
->fx_r_type
)
10923 case BFD_RELOC_MIPS_TLS_GD
:
10924 case BFD_RELOC_MIPS_TLS_LDM
:
10925 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10926 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10927 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10928 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10929 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10930 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10933 case BFD_RELOC_MIPS_JMP
:
10934 case BFD_RELOC_MIPS_SHIFT5
:
10935 case BFD_RELOC_MIPS_SHIFT6
:
10936 case BFD_RELOC_MIPS_GOT_DISP
:
10937 case BFD_RELOC_MIPS_GOT_PAGE
:
10938 case BFD_RELOC_MIPS_GOT_OFST
:
10939 case BFD_RELOC_MIPS_SUB
:
10940 case BFD_RELOC_MIPS_INSERT_A
:
10941 case BFD_RELOC_MIPS_INSERT_B
:
10942 case BFD_RELOC_MIPS_DELETE
:
10943 case BFD_RELOC_MIPS_HIGHEST
:
10944 case BFD_RELOC_MIPS_HIGHER
:
10945 case BFD_RELOC_MIPS_SCN_DISP
:
10946 case BFD_RELOC_MIPS_REL16
:
10947 case BFD_RELOC_MIPS_RELGOT
:
10948 case BFD_RELOC_MIPS_JALR
:
10949 case BFD_RELOC_HI16
:
10950 case BFD_RELOC_HI16_S
:
10951 case BFD_RELOC_GPREL16
:
10952 case BFD_RELOC_MIPS_LITERAL
:
10953 case BFD_RELOC_MIPS_CALL16
:
10954 case BFD_RELOC_MIPS_GOT16
:
10955 case BFD_RELOC_GPREL32
:
10956 case BFD_RELOC_MIPS_GOT_HI16
:
10957 case BFD_RELOC_MIPS_GOT_LO16
:
10958 case BFD_RELOC_MIPS_CALL_HI16
:
10959 case BFD_RELOC_MIPS_CALL_LO16
:
10960 case BFD_RELOC_MIPS16_GPREL
:
10961 case BFD_RELOC_MIPS16_HI16
:
10962 case BFD_RELOC_MIPS16_HI16_S
:
10963 assert (! fixP
->fx_pcrel
);
10964 /* Nothing needed to do. The value comes from the reloc entry */
10967 case BFD_RELOC_MIPS16_JMP
:
10968 /* We currently always generate a reloc against a symbol, which
10969 means that we don't want an addend even if the symbol is
10975 /* This is handled like BFD_RELOC_32, but we output a sign
10976 extended value if we are only 32 bits. */
10979 if (8 <= sizeof (valueT
))
10980 md_number_to_chars ((char *) buf
, *valP
, 8);
10985 if ((*valP
& 0x80000000) != 0)
10989 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
10991 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
10997 case BFD_RELOC_RVA
:
10999 /* If we are deleting this reloc entry, we must fill in the
11000 value now. This can happen if we have a .word which is not
11001 resolved when it appears but is later defined. */
11003 md_number_to_chars ((char *) buf
, *valP
, 4);
11007 /* If we are deleting this reloc entry, we must fill in the
11010 md_number_to_chars ((char *) buf
, *valP
, 2);
11013 case BFD_RELOC_LO16
:
11014 case BFD_RELOC_MIPS16_LO16
:
11015 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11016 may be safe to remove, but if so it's not obvious. */
11017 /* When handling an embedded PIC switch statement, we can wind
11018 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11021 if (*valP
+ 0x8000 > 0xffff)
11022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11023 _("relocation overflow"));
11024 if (target_big_endian
)
11026 md_number_to_chars ((char *) buf
, *valP
, 2);
11030 case BFD_RELOC_16_PCREL_S2
:
11031 if ((*valP
& 0x3) != 0)
11032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11033 _("Branch to odd address (%lx)"), (long) *valP
);
11036 * We need to save the bits in the instruction since fixup_segment()
11037 * might be deleting the relocation entry (i.e., a branch within
11038 * the current segment).
11040 if (! fixP
->fx_done
)
11043 /* update old instruction data */
11044 if (target_big_endian
)
11045 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11047 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11049 if (*valP
+ 0x20000 <= 0x3ffff)
11051 insn
|= (*valP
>> 2) & 0xffff;
11052 md_number_to_chars ((char *) buf
, insn
, 4);
11054 else if (mips_pic
== NO_PIC
11056 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11057 && (fixP
->fx_frag
->fr_address
11058 < text_section
->vma
+ bfd_get_section_size (text_section
))
11059 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11060 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11061 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11063 /* The branch offset is too large. If this is an
11064 unconditional branch, and we are not generating PIC code,
11065 we can convert it to an absolute jump instruction. */
11066 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11067 insn
= 0x0c000000; /* jal */
11069 insn
= 0x08000000; /* j */
11070 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11072 fixP
->fx_addsy
= section_symbol (text_section
);
11073 *valP
+= md_pcrel_from (fixP
);
11074 md_number_to_chars ((char *) buf
, insn
, 4);
11078 /* If we got here, we have branch-relaxation disabled,
11079 and there's nothing we can do to fix this instruction
11080 without turning it into a longer sequence. */
11081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11082 _("Branch out of range"));
11086 case BFD_RELOC_VTABLE_INHERIT
:
11089 && !S_IS_DEFINED (fixP
->fx_addsy
)
11090 && !S_IS_WEAK (fixP
->fx_addsy
))
11091 S_SET_WEAK (fixP
->fx_addsy
);
11094 case BFD_RELOC_VTABLE_ENTRY
:
11102 /* Remember value for tc_gen_reloc. */
11103 fixP
->fx_addnumber
= *valP
;
11113 name
= input_line_pointer
;
11114 c
= get_symbol_end ();
11115 p
= (symbolS
*) symbol_find_or_make (name
);
11116 *input_line_pointer
= c
;
11120 /* Align the current frag to a given power of two. The MIPS assembler
11121 also automatically adjusts any preceding label. */
11124 mips_align (int to
, int fill
, symbolS
*label
)
11126 mips_emit_delays ();
11127 frag_align (to
, fill
, 0);
11128 record_alignment (now_seg
, to
);
11131 assert (S_GET_SEGMENT (label
) == now_seg
);
11132 symbol_set_frag (label
, frag_now
);
11133 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11137 /* Align to a given power of two. .align 0 turns off the automatic
11138 alignment used by the data creating pseudo-ops. */
11141 s_align (int x ATTRIBUTE_UNUSED
)
11144 register long temp_fill
;
11145 long max_alignment
= 15;
11149 o Note that the assembler pulls down any immediately preceding label
11150 to the aligned address.
11151 o It's not documented but auto alignment is reinstated by
11152 a .align pseudo instruction.
11153 o Note also that after auto alignment is turned off the mips assembler
11154 issues an error on attempt to assemble an improperly aligned data item.
11159 temp
= get_absolute_expression ();
11160 if (temp
> max_alignment
)
11161 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11164 as_warn (_("Alignment negative: 0 assumed."));
11167 if (*input_line_pointer
== ',')
11169 ++input_line_pointer
;
11170 temp_fill
= get_absolute_expression ();
11177 mips_align (temp
, (int) temp_fill
,
11178 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11185 demand_empty_rest_of_line ();
11189 s_change_sec (int sec
)
11194 /* The ELF backend needs to know that we are changing sections, so
11195 that .previous works correctly. We could do something like check
11196 for an obj_section_change_hook macro, but that might be confusing
11197 as it would not be appropriate to use it in the section changing
11198 functions in read.c, since obj-elf.c intercepts those. FIXME:
11199 This should be cleaner, somehow. */
11200 obj_elf_section_change_hook ();
11203 mips_emit_delays ();
11213 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11214 demand_empty_rest_of_line ();
11218 seg
= subseg_new (RDATA_SECTION_NAME
,
11219 (subsegT
) get_absolute_expression ());
11220 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11222 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11223 | SEC_READONLY
| SEC_RELOC
11225 if (strcmp (TARGET_OS
, "elf") != 0)
11226 record_alignment (seg
, 4);
11228 demand_empty_rest_of_line ();
11232 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11233 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11235 bfd_set_section_flags (stdoutput
, seg
,
11236 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11237 if (strcmp (TARGET_OS
, "elf") != 0)
11238 record_alignment (seg
, 4);
11240 demand_empty_rest_of_line ();
11248 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11251 char *section_name
;
11256 int section_entry_size
;
11257 int section_alignment
;
11259 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11262 section_name
= input_line_pointer
;
11263 c
= get_symbol_end ();
11265 next_c
= *(input_line_pointer
+ 1);
11267 /* Do we have .section Name<,"flags">? */
11268 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11270 /* just after name is now '\0'. */
11271 *input_line_pointer
= c
;
11272 input_line_pointer
= section_name
;
11273 obj_elf_section (ignore
);
11276 input_line_pointer
++;
11278 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11280 section_type
= get_absolute_expression ();
11283 if (*input_line_pointer
++ == ',')
11284 section_flag
= get_absolute_expression ();
11287 if (*input_line_pointer
++ == ',')
11288 section_entry_size
= get_absolute_expression ();
11290 section_entry_size
= 0;
11291 if (*input_line_pointer
++ == ',')
11292 section_alignment
= get_absolute_expression ();
11294 section_alignment
= 0;
11296 section_name
= xstrdup (section_name
);
11298 /* When using the generic form of .section (as implemented by obj-elf.c),
11299 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11300 traditionally had to fall back on the more common @progbits instead.
11302 There's nothing really harmful in this, since bfd will correct
11303 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11304 means that, for backwards compatibiltiy, the special_section entries
11305 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11307 Even so, we shouldn't force users of the MIPS .section syntax to
11308 incorrectly label the sections as SHT_PROGBITS. The best compromise
11309 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11310 generic type-checking code. */
11311 if (section_type
== SHT_MIPS_DWARF
)
11312 section_type
= SHT_PROGBITS
;
11314 obj_elf_change_section (section_name
, section_type
, section_flag
,
11315 section_entry_size
, 0, 0, 0);
11317 if (now_seg
->name
!= section_name
)
11318 free (section_name
);
11319 #endif /* OBJ_ELF */
11323 mips_enable_auto_align (void)
11329 s_cons (int log_size
)
11333 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11334 mips_emit_delays ();
11335 if (log_size
> 0 && auto_align
)
11336 mips_align (log_size
, 0, label
);
11337 mips_clear_insn_labels ();
11338 cons (1 << log_size
);
11342 s_float_cons (int type
)
11346 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11348 mips_emit_delays ();
11353 mips_align (3, 0, label
);
11355 mips_align (2, 0, label
);
11358 mips_clear_insn_labels ();
11363 /* Handle .globl. We need to override it because on Irix 5 you are
11366 where foo is an undefined symbol, to mean that foo should be
11367 considered to be the address of a function. */
11370 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11377 name
= input_line_pointer
;
11378 c
= get_symbol_end ();
11379 symbolP
= symbol_find_or_make (name
);
11380 *input_line_pointer
= c
;
11381 SKIP_WHITESPACE ();
11383 /* On Irix 5, every global symbol that is not explicitly labelled as
11384 being a function is apparently labelled as being an object. */
11387 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11392 secname
= input_line_pointer
;
11393 c
= get_symbol_end ();
11394 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11396 as_bad (_("%s: no such section"), secname
);
11397 *input_line_pointer
= c
;
11399 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11400 flag
= BSF_FUNCTION
;
11403 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11405 S_SET_EXTERNAL (symbolP
);
11406 demand_empty_rest_of_line ();
11410 s_option (int x ATTRIBUTE_UNUSED
)
11415 opt
= input_line_pointer
;
11416 c
= get_symbol_end ();
11420 /* FIXME: What does this mean? */
11422 else if (strncmp (opt
, "pic", 3) == 0)
11426 i
= atoi (opt
+ 3);
11431 mips_pic
= SVR4_PIC
;
11432 mips_abicalls
= TRUE
;
11435 as_bad (_(".option pic%d not supported"), i
);
11437 if (mips_pic
== SVR4_PIC
)
11439 if (g_switch_seen
&& g_switch_value
!= 0)
11440 as_warn (_("-G may not be used with SVR4 PIC code"));
11441 g_switch_value
= 0;
11442 bfd_set_gp_size (stdoutput
, 0);
11446 as_warn (_("Unrecognized option \"%s\""), opt
);
11448 *input_line_pointer
= c
;
11449 demand_empty_rest_of_line ();
11452 /* This structure is used to hold a stack of .set values. */
11454 struct mips_option_stack
11456 struct mips_option_stack
*next
;
11457 struct mips_set_options options
;
11460 static struct mips_option_stack
*mips_opts_stack
;
11462 /* Handle the .set pseudo-op. */
11465 s_mipsset (int x ATTRIBUTE_UNUSED
)
11467 char *name
= input_line_pointer
, ch
;
11469 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11470 ++input_line_pointer
;
11471 ch
= *input_line_pointer
;
11472 *input_line_pointer
= '\0';
11474 if (strcmp (name
, "reorder") == 0)
11476 if (mips_opts
.noreorder
)
11479 else if (strcmp (name
, "noreorder") == 0)
11481 if (!mips_opts
.noreorder
)
11482 start_noreorder ();
11484 else if (strcmp (name
, "at") == 0)
11486 mips_opts
.noat
= 0;
11488 else if (strcmp (name
, "noat") == 0)
11490 mips_opts
.noat
= 1;
11492 else if (strcmp (name
, "macro") == 0)
11494 mips_opts
.warn_about_macros
= 0;
11496 else if (strcmp (name
, "nomacro") == 0)
11498 if (mips_opts
.noreorder
== 0)
11499 as_bad (_("`noreorder' must be set before `nomacro'"));
11500 mips_opts
.warn_about_macros
= 1;
11502 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11504 mips_opts
.nomove
= 0;
11506 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11508 mips_opts
.nomove
= 1;
11510 else if (strcmp (name
, "bopt") == 0)
11512 mips_opts
.nobopt
= 0;
11514 else if (strcmp (name
, "nobopt") == 0)
11516 mips_opts
.nobopt
= 1;
11518 else if (strcmp (name
, "mips16") == 0
11519 || strcmp (name
, "MIPS-16") == 0)
11520 mips_opts
.mips16
= 1;
11521 else if (strcmp (name
, "nomips16") == 0
11522 || strcmp (name
, "noMIPS-16") == 0)
11523 mips_opts
.mips16
= 0;
11524 else if (strcmp (name
, "mips3d") == 0)
11525 mips_opts
.ase_mips3d
= 1;
11526 else if (strcmp (name
, "nomips3d") == 0)
11527 mips_opts
.ase_mips3d
= 0;
11528 else if (strcmp (name
, "mdmx") == 0)
11529 mips_opts
.ase_mdmx
= 1;
11530 else if (strcmp (name
, "nomdmx") == 0)
11531 mips_opts
.ase_mdmx
= 0;
11532 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11536 /* Permit the user to change the ISA and architecture on the fly.
11537 Needless to say, misuse can cause serious problems. */
11538 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11541 mips_opts
.isa
= file_mips_isa
;
11542 mips_opts
.arch
= file_mips_arch
;
11544 else if (strncmp (name
, "arch=", 5) == 0)
11546 const struct mips_cpu_info
*p
;
11548 p
= mips_parse_cpu("internal use", name
+ 5);
11550 as_bad (_("unknown architecture %s"), name
+ 5);
11553 mips_opts
.arch
= p
->cpu
;
11554 mips_opts
.isa
= p
->isa
;
11557 else if (strncmp (name
, "mips", 4) == 0)
11559 const struct mips_cpu_info
*p
;
11561 p
= mips_parse_cpu("internal use", name
);
11563 as_bad (_("unknown ISA level %s"), name
+ 4);
11566 mips_opts
.arch
= p
->cpu
;
11567 mips_opts
.isa
= p
->isa
;
11571 as_bad (_("unknown ISA or architecture %s"), name
);
11573 switch (mips_opts
.isa
)
11581 mips_opts
.gp32
= 1;
11582 mips_opts
.fp32
= 1;
11589 mips_opts
.gp32
= 0;
11590 mips_opts
.fp32
= 0;
11593 as_bad (_("unknown ISA level %s"), name
+ 4);
11598 mips_opts
.gp32
= file_mips_gp32
;
11599 mips_opts
.fp32
= file_mips_fp32
;
11602 else if (strcmp (name
, "autoextend") == 0)
11603 mips_opts
.noautoextend
= 0;
11604 else if (strcmp (name
, "noautoextend") == 0)
11605 mips_opts
.noautoextend
= 1;
11606 else if (strcmp (name
, "push") == 0)
11608 struct mips_option_stack
*s
;
11610 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11611 s
->next
= mips_opts_stack
;
11612 s
->options
= mips_opts
;
11613 mips_opts_stack
= s
;
11615 else if (strcmp (name
, "pop") == 0)
11617 struct mips_option_stack
*s
;
11619 s
= mips_opts_stack
;
11621 as_bad (_(".set pop with no .set push"));
11624 /* If we're changing the reorder mode we need to handle
11625 delay slots correctly. */
11626 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11627 start_noreorder ();
11628 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11631 mips_opts
= s
->options
;
11632 mips_opts_stack
= s
->next
;
11636 else if (strcmp (name
, "sym32") == 0)
11637 mips_opts
.sym32
= TRUE
;
11638 else if (strcmp (name
, "nosym32") == 0)
11639 mips_opts
.sym32
= FALSE
;
11642 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11644 *input_line_pointer
= ch
;
11645 demand_empty_rest_of_line ();
11648 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11649 .option pic2. It means to generate SVR4 PIC calls. */
11652 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11654 mips_pic
= SVR4_PIC
;
11655 mips_abicalls
= TRUE
;
11657 if (g_switch_seen
&& g_switch_value
!= 0)
11658 as_warn (_("-G may not be used with SVR4 PIC code"));
11659 g_switch_value
= 0;
11661 bfd_set_gp_size (stdoutput
, 0);
11662 demand_empty_rest_of_line ();
11665 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11666 PIC code. It sets the $gp register for the function based on the
11667 function address, which is in the register named in the argument.
11668 This uses a relocation against _gp_disp, which is handled specially
11669 by the linker. The result is:
11670 lui $gp,%hi(_gp_disp)
11671 addiu $gp,$gp,%lo(_gp_disp)
11672 addu $gp,$gp,.cpload argument
11673 The .cpload argument is normally $25 == $t9.
11675 The -mno-shared option changes this to:
11676 lui $gp,%hi(__gnu_local_gp)
11677 addiu $gp,$gp,%lo(__gnu_local_gp)
11678 and the argument is ignored. This saves an instruction, but the
11679 resulting code is not position independent; it uses an absolute
11680 address for __gnu_local_gp. Thus code assembled with -mno-shared
11681 can go into an ordinary executable, but not into a shared library. */
11684 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11690 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11691 .cpload is ignored. */
11692 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11698 /* .cpload should be in a .set noreorder section. */
11699 if (mips_opts
.noreorder
== 0)
11700 as_warn (_(".cpload not in noreorder section"));
11702 reg
= tc_get_register (0);
11704 /* If we need to produce a 64-bit address, we are better off using
11705 the default instruction sequence. */
11706 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11708 ex
.X_op
= O_symbol
;
11709 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11711 ex
.X_op_symbol
= NULL
;
11712 ex
.X_add_number
= 0;
11714 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11715 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11718 macro_build_lui (&ex
, mips_gp_register
);
11719 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11720 mips_gp_register
, BFD_RELOC_LO16
);
11722 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11723 mips_gp_register
, reg
);
11726 demand_empty_rest_of_line ();
11729 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11730 .cpsetup $reg1, offset|$reg2, label
11732 If offset is given, this results in:
11733 sd $gp, offset($sp)
11734 lui $gp, %hi(%neg(%gp_rel(label)))
11735 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11736 daddu $gp, $gp, $reg1
11738 If $reg2 is given, this results in:
11739 daddu $reg2, $gp, $0
11740 lui $gp, %hi(%neg(%gp_rel(label)))
11741 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11742 daddu $gp, $gp, $reg1
11743 $reg1 is normally $25 == $t9.
11745 The -mno-shared option replaces the last three instructions with
11747 addiu $gp,$gp,%lo(_gp)
11751 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11753 expressionS ex_off
;
11754 expressionS ex_sym
;
11757 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11758 We also need NewABI support. */
11759 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11765 reg1
= tc_get_register (0);
11766 SKIP_WHITESPACE ();
11767 if (*input_line_pointer
!= ',')
11769 as_bad (_("missing argument separator ',' for .cpsetup"));
11773 ++input_line_pointer
;
11774 SKIP_WHITESPACE ();
11775 if (*input_line_pointer
== '$')
11777 mips_cpreturn_register
= tc_get_register (0);
11778 mips_cpreturn_offset
= -1;
11782 mips_cpreturn_offset
= get_absolute_expression ();
11783 mips_cpreturn_register
= -1;
11785 SKIP_WHITESPACE ();
11786 if (*input_line_pointer
!= ',')
11788 as_bad (_("missing argument separator ',' for .cpsetup"));
11792 ++input_line_pointer
;
11793 SKIP_WHITESPACE ();
11794 expression (&ex_sym
);
11797 if (mips_cpreturn_register
== -1)
11799 ex_off
.X_op
= O_constant
;
11800 ex_off
.X_add_symbol
= NULL
;
11801 ex_off
.X_op_symbol
= NULL
;
11802 ex_off
.X_add_number
= mips_cpreturn_offset
;
11804 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11805 BFD_RELOC_LO16
, SP
);
11808 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11809 mips_gp_register
, 0);
11811 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11813 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11814 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11817 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11818 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11819 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11822 mips_gp_register
, reg1
);
11828 ex
.X_op
= O_symbol
;
11829 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
11830 ex
.X_op_symbol
= NULL
;
11831 ex
.X_add_number
= 0;
11833 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11834 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11836 macro_build_lui (&ex
, mips_gp_register
);
11837 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11838 mips_gp_register
, BFD_RELOC_LO16
);
11843 demand_empty_rest_of_line ();
11847 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11849 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11850 .cplocal is ignored. */
11851 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11857 mips_gp_register
= tc_get_register (0);
11858 demand_empty_rest_of_line ();
11861 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11862 offset from $sp. The offset is remembered, and after making a PIC
11863 call $gp is restored from that location. */
11866 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11870 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11871 .cprestore is ignored. */
11872 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11878 mips_cprestore_offset
= get_absolute_expression ();
11879 mips_cprestore_valid
= 1;
11881 ex
.X_op
= O_constant
;
11882 ex
.X_add_symbol
= NULL
;
11883 ex
.X_op_symbol
= NULL
;
11884 ex
.X_add_number
= mips_cprestore_offset
;
11887 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11888 SP
, HAVE_64BIT_ADDRESSES
);
11891 demand_empty_rest_of_line ();
11894 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11895 was given in the preceding .cpsetup, it results in:
11896 ld $gp, offset($sp)
11898 If a register $reg2 was given there, it results in:
11899 daddu $gp, $reg2, $0
11902 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11906 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11907 We also need NewABI support. */
11908 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11915 if (mips_cpreturn_register
== -1)
11917 ex
.X_op
= O_constant
;
11918 ex
.X_add_symbol
= NULL
;
11919 ex
.X_op_symbol
= NULL
;
11920 ex
.X_add_number
= mips_cpreturn_offset
;
11922 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11925 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11926 mips_cpreturn_register
, 0);
11929 demand_empty_rest_of_line ();
11932 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11933 code. It sets the offset to use in gp_rel relocations. */
11936 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11938 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11939 We also need NewABI support. */
11940 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11946 mips_gprel_offset
= get_absolute_expression ();
11948 demand_empty_rest_of_line ();
11951 /* Handle the .gpword pseudo-op. This is used when generating PIC
11952 code. It generates a 32 bit GP relative reloc. */
11955 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11961 /* When not generating PIC code, this is treated as .word. */
11962 if (mips_pic
!= SVR4_PIC
)
11968 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11969 mips_emit_delays ();
11971 mips_align (2, 0, label
);
11972 mips_clear_insn_labels ();
11976 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11978 as_bad (_("Unsupported use of .gpword"));
11979 ignore_rest_of_line ();
11983 md_number_to_chars (p
, 0, 4);
11984 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11985 BFD_RELOC_GPREL32
);
11987 demand_empty_rest_of_line ();
11991 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11997 /* When not generating PIC code, this is treated as .dword. */
11998 if (mips_pic
!= SVR4_PIC
)
12004 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12005 mips_emit_delays ();
12007 mips_align (3, 0, label
);
12008 mips_clear_insn_labels ();
12012 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12014 as_bad (_("Unsupported use of .gpdword"));
12015 ignore_rest_of_line ();
12019 md_number_to_chars (p
, 0, 8);
12020 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12021 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12023 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12024 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12025 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12027 demand_empty_rest_of_line ();
12030 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12031 tables in SVR4 PIC code. */
12034 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12038 /* This is ignored when not generating SVR4 PIC code. */
12039 if (mips_pic
!= SVR4_PIC
)
12045 /* Add $gp to the register named as an argument. */
12047 reg
= tc_get_register (0);
12048 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12051 demand_empty_rest_of_line ();
12054 /* Handle the .insn pseudo-op. This marks instruction labels in
12055 mips16 mode. This permits the linker to handle them specially,
12056 such as generating jalx instructions when needed. We also make
12057 them odd for the duration of the assembly, in order to generate the
12058 right sort of code. We will make them even in the adjust_symtab
12059 routine, while leaving them marked. This is convenient for the
12060 debugger and the disassembler. The linker knows to make them odd
12064 s_insn (int ignore ATTRIBUTE_UNUSED
)
12066 mips16_mark_labels ();
12068 demand_empty_rest_of_line ();
12071 /* Handle a .stabn directive. We need these in order to mark a label
12072 as being a mips16 text label correctly. Sometimes the compiler
12073 will emit a label, followed by a .stabn, and then switch sections.
12074 If the label and .stabn are in mips16 mode, then the label is
12075 really a mips16 text label. */
12078 s_mips_stab (int type
)
12081 mips16_mark_labels ();
12086 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12090 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12097 name
= input_line_pointer
;
12098 c
= get_symbol_end ();
12099 symbolP
= symbol_find_or_make (name
);
12100 S_SET_WEAK (symbolP
);
12101 *input_line_pointer
= c
;
12103 SKIP_WHITESPACE ();
12105 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12107 if (S_IS_DEFINED (symbolP
))
12109 as_bad ("ignoring attempt to redefine symbol %s",
12110 S_GET_NAME (symbolP
));
12111 ignore_rest_of_line ();
12115 if (*input_line_pointer
== ',')
12117 ++input_line_pointer
;
12118 SKIP_WHITESPACE ();
12122 if (exp
.X_op
!= O_symbol
)
12124 as_bad ("bad .weakext directive");
12125 ignore_rest_of_line ();
12128 symbol_set_value_expression (symbolP
, &exp
);
12131 demand_empty_rest_of_line ();
12134 /* Parse a register string into a number. Called from the ECOFF code
12135 to parse .frame. The argument is non-zero if this is the frame
12136 register, so that we can record it in mips_frame_reg. */
12139 tc_get_register (int frame
)
12143 SKIP_WHITESPACE ();
12144 if (*input_line_pointer
++ != '$')
12146 as_warn (_("expected `$'"));
12149 else if (ISDIGIT (*input_line_pointer
))
12151 reg
= get_absolute_expression ();
12152 if (reg
< 0 || reg
>= 32)
12154 as_warn (_("Bad register number"));
12160 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12163 input_line_pointer
+= 2;
12165 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12168 input_line_pointer
+= 2;
12170 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12173 input_line_pointer
+= 2;
12175 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12178 input_line_pointer
+= 2;
12180 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12183 input_line_pointer
+= 2;
12185 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12188 input_line_pointer
+= 3;
12190 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12193 input_line_pointer
+= 3;
12195 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12198 input_line_pointer
+= 4;
12202 as_warn (_("Unrecognized register name"));
12204 while (ISALNUM(*input_line_pointer
))
12205 input_line_pointer
++;
12210 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12211 mips_frame_reg_valid
= 1;
12212 mips_cprestore_valid
= 0;
12218 md_section_align (asection
*seg
, valueT addr
)
12220 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12223 /* We don't need to align ELF sections to the full alignment.
12224 However, Irix 5 may prefer that we align them at least to a 16
12225 byte boundary. We don't bother to align the sections if we are
12226 targeted for an embedded system. */
12227 if (strcmp (TARGET_OS
, "elf") == 0)
12233 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12236 /* Utility routine, called from above as well. If called while the
12237 input file is still being read, it's only an approximation. (For
12238 example, a symbol may later become defined which appeared to be
12239 undefined earlier.) */
12242 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12247 if (g_switch_value
> 0)
12249 const char *symname
;
12252 /* Find out whether this symbol can be referenced off the $gp
12253 register. It can be if it is smaller than the -G size or if
12254 it is in the .sdata or .sbss section. Certain symbols can
12255 not be referenced off the $gp, although it appears as though
12257 symname
= S_GET_NAME (sym
);
12258 if (symname
!= (const char *) NULL
12259 && (strcmp (symname
, "eprol") == 0
12260 || strcmp (symname
, "etext") == 0
12261 || strcmp (symname
, "_gp") == 0
12262 || strcmp (symname
, "edata") == 0
12263 || strcmp (symname
, "_fbss") == 0
12264 || strcmp (symname
, "_fdata") == 0
12265 || strcmp (symname
, "_ftext") == 0
12266 || strcmp (symname
, "end") == 0
12267 || strcmp (symname
, "_gp_disp") == 0))
12269 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12271 #ifndef NO_ECOFF_DEBUGGING
12272 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12273 && (symbol_get_obj (sym
)->ecoff_extern_size
12274 <= g_switch_value
))
12276 /* We must defer this decision until after the whole
12277 file has been read, since there might be a .extern
12278 after the first use of this symbol. */
12279 || (before_relaxing
12280 #ifndef NO_ECOFF_DEBUGGING
12281 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12283 && S_GET_VALUE (sym
) == 0)
12284 || (S_GET_VALUE (sym
) != 0
12285 && S_GET_VALUE (sym
) <= g_switch_value
)))
12289 const char *segname
;
12291 segname
= segment_name (S_GET_SEGMENT (sym
));
12292 assert (strcmp (segname
, ".lit8") != 0
12293 && strcmp (segname
, ".lit4") != 0);
12294 change
= (strcmp (segname
, ".sdata") != 0
12295 && strcmp (segname
, ".sbss") != 0
12296 && strncmp (segname
, ".sdata.", 7) != 0
12297 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12302 /* We are not optimizing for the $gp register. */
12307 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12310 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12313 bfd_boolean linkonce
;
12315 /* Handle the case of a symbol equated to another symbol. */
12316 while (symbol_equated_reloc_p (sym
))
12320 /* It's possible to get a loop here in a badly written
12322 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12328 symsec
= S_GET_SEGMENT (sym
);
12330 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12332 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12334 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12338 /* The GNU toolchain uses an extension for ELF: a section
12339 beginning with the magic string .gnu.linkonce is a linkonce
12341 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12342 sizeof ".gnu.linkonce" - 1) == 0)
12346 /* This must duplicate the test in adjust_reloc_syms. */
12347 return (symsec
!= &bfd_und_section
12348 && symsec
!= &bfd_abs_section
12349 && ! bfd_is_com_section (symsec
)
12352 /* A global or weak symbol is treated as external. */
12353 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12354 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12360 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12361 extended opcode. SEC is the section the frag is in. */
12364 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12367 register const struct mips16_immed_operand
*op
;
12369 int mintiny
, maxtiny
;
12373 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12375 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12378 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12379 op
= mips16_immed_operands
;
12380 while (op
->type
!= type
)
12383 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12388 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12391 maxtiny
= 1 << op
->nbits
;
12396 maxtiny
= (1 << op
->nbits
) - 1;
12401 mintiny
= - (1 << (op
->nbits
- 1));
12402 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12405 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12406 val
= S_GET_VALUE (fragp
->fr_symbol
);
12407 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12413 /* We won't have the section when we are called from
12414 mips_relax_frag. However, we will always have been called
12415 from md_estimate_size_before_relax first. If this is a
12416 branch to a different section, we mark it as such. If SEC is
12417 NULL, and the frag is not marked, then it must be a branch to
12418 the same section. */
12421 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12426 /* Must have been called from md_estimate_size_before_relax. */
12429 fragp
->fr_subtype
=
12430 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12432 /* FIXME: We should support this, and let the linker
12433 catch branches and loads that are out of range. */
12434 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12435 _("unsupported PC relative reference to different section"));
12439 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12440 /* Assume non-extended on the first relaxation pass.
12441 The address we have calculated will be bogus if this is
12442 a forward branch to another frag, as the forward frag
12443 will have fr_address == 0. */
12447 /* In this case, we know for sure that the symbol fragment is in
12448 the same section. If the relax_marker of the symbol fragment
12449 differs from the relax_marker of this fragment, we have not
12450 yet adjusted the symbol fragment fr_address. We want to add
12451 in STRETCH in order to get a better estimate of the address.
12452 This particularly matters because of the shift bits. */
12454 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12458 /* Adjust stretch for any alignment frag. Note that if have
12459 been expanding the earlier code, the symbol may be
12460 defined in what appears to be an earlier frag. FIXME:
12461 This doesn't handle the fr_subtype field, which specifies
12462 a maximum number of bytes to skip when doing an
12464 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12466 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12469 stretch
= - ((- stretch
)
12470 & ~ ((1 << (int) f
->fr_offset
) - 1));
12472 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12481 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12483 /* The base address rules are complicated. The base address of
12484 a branch is the following instruction. The base address of a
12485 PC relative load or add is the instruction itself, but if it
12486 is in a delay slot (in which case it can not be extended) use
12487 the address of the instruction whose delay slot it is in. */
12488 if (type
== 'p' || type
== 'q')
12492 /* If we are currently assuming that this frag should be
12493 extended, then, the current address is two bytes
12495 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12498 /* Ignore the low bit in the target, since it will be set
12499 for a text label. */
12500 if ((val
& 1) != 0)
12503 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12505 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12508 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12510 /* Branch offsets have an implicit 0 in the lowest bit. */
12511 if (type
== 'p' || type
== 'q')
12514 /* If any of the shifted bits are set, we must use an extended
12515 opcode. If the address depends on the size of this
12516 instruction, this can lead to a loop, so we arrange to always
12517 use an extended opcode. We only check this when we are in
12518 the main relaxation loop, when SEC is NULL. */
12519 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12521 fragp
->fr_subtype
=
12522 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12526 /* If we are about to mark a frag as extended because the value
12527 is precisely maxtiny + 1, then there is a chance of an
12528 infinite loop as in the following code:
12533 In this case when the la is extended, foo is 0x3fc bytes
12534 away, so the la can be shrunk, but then foo is 0x400 away, so
12535 the la must be extended. To avoid this loop, we mark the
12536 frag as extended if it was small, and is about to become
12537 extended with a value of maxtiny + 1. */
12538 if (val
== ((maxtiny
+ 1) << op
->shift
)
12539 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12542 fragp
->fr_subtype
=
12543 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12547 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12548 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12550 if ((val
& ((1 << op
->shift
) - 1)) != 0
12551 || val
< (mintiny
<< op
->shift
)
12552 || val
> (maxtiny
<< op
->shift
))
12558 /* Compute the length of a branch sequence, and adjust the
12559 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12560 worst-case length is computed, with UPDATE being used to indicate
12561 whether an unconditional (-1), branch-likely (+1) or regular (0)
12562 branch is to be computed. */
12564 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12566 bfd_boolean toofar
;
12570 && S_IS_DEFINED (fragp
->fr_symbol
)
12571 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12576 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12578 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12582 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12585 /* If the symbol is not defined or it's in a different segment,
12586 assume the user knows what's going on and emit a short
12592 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12594 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12595 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12596 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12602 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12605 if (mips_pic
!= NO_PIC
)
12607 /* Additional space for PIC loading of target address. */
12609 if (mips_opts
.isa
== ISA_MIPS1
)
12610 /* Additional space for $at-stabilizing nop. */
12614 /* If branch is conditional. */
12615 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12622 /* Estimate the size of a frag before relaxing. Unless this is the
12623 mips16, we are not really relaxing here, and the final size is
12624 encoded in the subtype information. For the mips16, we have to
12625 decide whether we are using an extended opcode or not. */
12628 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12632 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12635 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12637 return fragp
->fr_var
;
12640 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12641 /* We don't want to modify the EXTENDED bit here; it might get us
12642 into infinite loops. We change it only in mips_relax_frag(). */
12643 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12645 if (mips_pic
== NO_PIC
)
12646 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12647 else if (mips_pic
== SVR4_PIC
)
12648 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12654 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12655 return -RELAX_FIRST (fragp
->fr_subtype
);
12658 return -RELAX_SECOND (fragp
->fr_subtype
);
12661 /* This is called to see whether a reloc against a defined symbol
12662 should be converted into a reloc against a section. */
12665 mips_fix_adjustable (fixS
*fixp
)
12667 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12668 about the format of the offset in the .o file. */
12669 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12672 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12673 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12676 if (fixp
->fx_addsy
== NULL
)
12679 /* If symbol SYM is in a mergeable section, relocations of the form
12680 SYM + 0 can usually be made section-relative. The mergeable data
12681 is then identified by the section offset rather than by the symbol.
12683 However, if we're generating REL LO16 relocations, the offset is split
12684 between the LO16 and parterning high part relocation. The linker will
12685 need to recalculate the complete offset in order to correctly identify
12688 The linker has traditionally not looked for the parterning high part
12689 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12690 placed anywhere. Rather than break backwards compatibility by changing
12691 this, it seems better not to force the issue, and instead keep the
12692 original symbol. This will work with either linker behavior. */
12693 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
12694 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
12695 || reloc_needs_lo_p (fixp
->fx_r_type
))
12696 && HAVE_IN_PLACE_ADDENDS
12697 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12701 /* Don't adjust relocations against mips16 symbols, so that the linker
12702 can find them if it needs to set up a stub. */
12703 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12704 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12705 && fixp
->fx_subsy
== NULL
)
12712 /* Translate internal representation of relocation info to BFD target
12716 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12718 static arelent
*retval
[4];
12720 bfd_reloc_code_real_type code
;
12722 memset (retval
, 0, sizeof(retval
));
12723 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12724 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12725 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12726 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12728 assert (! fixp
->fx_pcrel
);
12729 reloc
->addend
= fixp
->fx_addnumber
;
12731 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12732 entry to be used in the relocation's section offset. */
12733 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12735 reloc
->address
= reloc
->addend
;
12739 code
= fixp
->fx_r_type
;
12741 /* To support a PC relative reloc, we used a Cygnus extension.
12742 We check for that here to make sure that we don't let such a
12743 reloc escape normally. (FIXME: This was formerly used by
12744 embedded-PIC support, but is now used by branch handling in
12745 general. That probably should be fixed.) */
12746 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12747 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12748 && code
== BFD_RELOC_16_PCREL_S2
)
12749 reloc
->howto
= NULL
;
12751 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12753 if (reloc
->howto
== NULL
)
12755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12756 _("Can not represent %s relocation in this object file format"),
12757 bfd_get_reloc_code_name (code
));
12764 /* Relax a machine dependent frag. This returns the amount by which
12765 the current size of the frag should change. */
12768 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12770 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12772 offsetT old_var
= fragp
->fr_var
;
12774 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12776 return fragp
->fr_var
- old_var
;
12779 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12782 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12784 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12786 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12791 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12793 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12800 /* Convert a machine dependent frag. */
12803 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12805 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12808 unsigned long insn
;
12812 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12814 if (target_big_endian
)
12815 insn
= bfd_getb32 (buf
);
12817 insn
= bfd_getl32 (buf
);
12819 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12821 /* We generate a fixup instead of applying it right now
12822 because, if there are linker relaxations, we're going to
12823 need the relocations. */
12824 exp
.X_op
= O_symbol
;
12825 exp
.X_add_symbol
= fragp
->fr_symbol
;
12826 exp
.X_add_number
= fragp
->fr_offset
;
12828 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12830 BFD_RELOC_16_PCREL_S2
);
12831 fixp
->fx_file
= fragp
->fr_file
;
12832 fixp
->fx_line
= fragp
->fr_line
;
12834 md_number_to_chars ((char *) buf
, insn
, 4);
12841 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12842 _("relaxed out-of-range branch into a jump"));
12844 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12847 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12849 /* Reverse the branch. */
12850 switch ((insn
>> 28) & 0xf)
12853 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12854 have the condition reversed by tweaking a single
12855 bit, and their opcodes all have 0x4???????. */
12856 assert ((insn
& 0xf1000000) == 0x41000000);
12857 insn
^= 0x00010000;
12861 /* bltz 0x04000000 bgez 0x04010000
12862 bltzal 0x04100000 bgezal 0x04110000 */
12863 assert ((insn
& 0xfc0e0000) == 0x04000000);
12864 insn
^= 0x00010000;
12868 /* beq 0x10000000 bne 0x14000000
12869 blez 0x18000000 bgtz 0x1c000000 */
12870 insn
^= 0x04000000;
12878 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12880 /* Clear the and-link bit. */
12881 assert ((insn
& 0xfc1c0000) == 0x04100000);
12883 /* bltzal 0x04100000 bgezal 0x04110000
12884 bltzall 0x04120000 bgezall 0x04130000 */
12885 insn
&= ~0x00100000;
12888 /* Branch over the branch (if the branch was likely) or the
12889 full jump (not likely case). Compute the offset from the
12890 current instruction to branch to. */
12891 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12895 /* How many bytes in instructions we've already emitted? */
12896 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12897 /* How many bytes in instructions from here to the end? */
12898 i
= fragp
->fr_var
- i
;
12900 /* Convert to instruction count. */
12902 /* Branch counts from the next instruction. */
12905 /* Branch over the jump. */
12906 md_number_to_chars ((char *) buf
, insn
, 4);
12910 md_number_to_chars ((char *) buf
, 0, 4);
12913 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12915 /* beql $0, $0, 2f */
12917 /* Compute the PC offset from the current instruction to
12918 the end of the variable frag. */
12919 /* How many bytes in instructions we've already emitted? */
12920 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12921 /* How many bytes in instructions from here to the end? */
12922 i
= fragp
->fr_var
- i
;
12923 /* Convert to instruction count. */
12925 /* Don't decrement i, because we want to branch over the
12929 md_number_to_chars ((char *) buf
, insn
, 4);
12932 md_number_to_chars ((char *) buf
, 0, 4);
12937 if (mips_pic
== NO_PIC
)
12940 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12941 ? 0x0c000000 : 0x08000000);
12942 exp
.X_op
= O_symbol
;
12943 exp
.X_add_symbol
= fragp
->fr_symbol
;
12944 exp
.X_add_number
= fragp
->fr_offset
;
12946 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12947 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12948 fixp
->fx_file
= fragp
->fr_file
;
12949 fixp
->fx_line
= fragp
->fr_line
;
12951 md_number_to_chars ((char *) buf
, insn
, 4);
12956 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12957 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12958 exp
.X_op
= O_symbol
;
12959 exp
.X_add_symbol
= fragp
->fr_symbol
;
12960 exp
.X_add_number
= fragp
->fr_offset
;
12962 if (fragp
->fr_offset
)
12964 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12965 exp
.X_add_number
= 0;
12968 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12969 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12970 fixp
->fx_file
= fragp
->fr_file
;
12971 fixp
->fx_line
= fragp
->fr_line
;
12973 md_number_to_chars ((char *) buf
, insn
, 4);
12976 if (mips_opts
.isa
== ISA_MIPS1
)
12979 md_number_to_chars ((char *) buf
, 0, 4);
12983 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12984 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12986 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12987 4, &exp
, 0, BFD_RELOC_LO16
);
12988 fixp
->fx_file
= fragp
->fr_file
;
12989 fixp
->fx_line
= fragp
->fr_line
;
12991 md_number_to_chars ((char *) buf
, insn
, 4);
12995 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13000 md_number_to_chars ((char *) buf
, insn
, 4);
13005 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13006 + fragp
->fr_fix
+ fragp
->fr_var
);
13008 fragp
->fr_fix
+= fragp
->fr_var
;
13013 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13016 register const struct mips16_immed_operand
*op
;
13017 bfd_boolean small
, ext
;
13020 unsigned long insn
;
13021 bfd_boolean use_extend
;
13022 unsigned short extend
;
13024 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13025 op
= mips16_immed_operands
;
13026 while (op
->type
!= type
)
13029 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13040 resolve_symbol_value (fragp
->fr_symbol
);
13041 val
= S_GET_VALUE (fragp
->fr_symbol
);
13046 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13048 /* The rules for the base address of a PC relative reloc are
13049 complicated; see mips16_extended_frag. */
13050 if (type
== 'p' || type
== 'q')
13055 /* Ignore the low bit in the target, since it will be
13056 set for a text label. */
13057 if ((val
& 1) != 0)
13060 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13062 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13065 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13068 /* Make sure the section winds up with the alignment we have
13071 record_alignment (asec
, op
->shift
);
13075 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13076 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13077 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13078 _("extended instruction in delay slot"));
13080 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13082 if (target_big_endian
)
13083 insn
= bfd_getb16 (buf
);
13085 insn
= bfd_getl16 (buf
);
13087 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13088 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13089 small
, ext
, &insn
, &use_extend
, &extend
);
13093 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13094 fragp
->fr_fix
+= 2;
13098 md_number_to_chars ((char *) buf
, insn
, 2);
13099 fragp
->fr_fix
+= 2;
13107 first
= RELAX_FIRST (fragp
->fr_subtype
);
13108 second
= RELAX_SECOND (fragp
->fr_subtype
);
13109 fixp
= (fixS
*) fragp
->fr_opcode
;
13111 /* Possibly emit a warning if we've chosen the longer option. */
13112 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13113 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13115 const char *msg
= macro_warning (fragp
->fr_subtype
);
13117 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13120 /* Go through all the fixups for the first sequence. Disable them
13121 (by marking them as done) if we're going to use the second
13122 sequence instead. */
13124 && fixp
->fx_frag
== fragp
13125 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13127 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13129 fixp
= fixp
->fx_next
;
13132 /* Go through the fixups for the second sequence. Disable them if
13133 we're going to use the first sequence, otherwise adjust their
13134 addresses to account for the relaxation. */
13135 while (fixp
&& fixp
->fx_frag
== fragp
)
13137 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13138 fixp
->fx_where
-= first
;
13141 fixp
= fixp
->fx_next
;
13144 /* Now modify the frag contents. */
13145 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13149 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13150 memmove (start
, start
+ first
, second
);
13151 fragp
->fr_fix
-= first
;
13154 fragp
->fr_fix
-= second
;
13160 /* This function is called after the relocs have been generated.
13161 We've been storing mips16 text labels as odd. Here we convert them
13162 back to even for the convenience of the debugger. */
13165 mips_frob_file_after_relocs (void)
13168 unsigned int count
, i
;
13170 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13173 syms
= bfd_get_outsymbols (stdoutput
);
13174 count
= bfd_get_symcount (stdoutput
);
13175 for (i
= 0; i
< count
; i
++, syms
++)
13177 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13178 && ((*syms
)->value
& 1) != 0)
13180 (*syms
)->value
&= ~1;
13181 /* If the symbol has an odd size, it was probably computed
13182 incorrectly, so adjust that as well. */
13183 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13184 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13191 /* This function is called whenever a label is defined. It is used
13192 when handling branch delays; if a branch has a label, we assume we
13193 can not move it. */
13196 mips_define_label (symbolS
*sym
)
13198 struct insn_label_list
*l
;
13200 if (free_insn_labels
== NULL
)
13201 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13204 l
= free_insn_labels
;
13205 free_insn_labels
= l
->next
;
13209 l
->next
= insn_labels
;
13213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13215 /* Some special processing for a MIPS ELF file. */
13218 mips_elf_final_processing (void)
13220 /* Write out the register information. */
13221 if (mips_abi
!= N64_ABI
)
13225 s
.ri_gprmask
= mips_gprmask
;
13226 s
.ri_cprmask
[0] = mips_cprmask
[0];
13227 s
.ri_cprmask
[1] = mips_cprmask
[1];
13228 s
.ri_cprmask
[2] = mips_cprmask
[2];
13229 s
.ri_cprmask
[3] = mips_cprmask
[3];
13230 /* The gp_value field is set by the MIPS ELF backend. */
13232 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13233 ((Elf32_External_RegInfo
*)
13234 mips_regmask_frag
));
13238 Elf64_Internal_RegInfo s
;
13240 s
.ri_gprmask
= mips_gprmask
;
13242 s
.ri_cprmask
[0] = mips_cprmask
[0];
13243 s
.ri_cprmask
[1] = mips_cprmask
[1];
13244 s
.ri_cprmask
[2] = mips_cprmask
[2];
13245 s
.ri_cprmask
[3] = mips_cprmask
[3];
13246 /* The gp_value field is set by the MIPS ELF backend. */
13248 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13249 ((Elf64_External_RegInfo
*)
13250 mips_regmask_frag
));
13253 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13254 sort of BFD interface for this. */
13255 if (mips_any_noreorder
)
13256 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13257 if (mips_pic
!= NO_PIC
)
13259 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13260 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13263 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13265 /* Set MIPS ELF flags for ASEs. */
13266 if (file_ase_mips16
)
13267 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13268 #if 0 /* XXX FIXME */
13269 if (file_ase_mips3d
)
13270 elf_elfheader (stdoutput
)->e_flags
|= ???;
13273 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13275 /* Set the MIPS ELF ABI flags. */
13276 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13277 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13278 else if (mips_abi
== O64_ABI
)
13279 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13280 else if (mips_abi
== EABI_ABI
)
13282 if (!file_mips_gp32
)
13283 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13285 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13287 else if (mips_abi
== N32_ABI
)
13288 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13290 /* Nothing to do for N64_ABI. */
13292 if (mips_32bitmode
)
13293 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13296 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13298 typedef struct proc
{
13300 symbolS
*func_end_sym
;
13301 unsigned long reg_mask
;
13302 unsigned long reg_offset
;
13303 unsigned long fpreg_mask
;
13304 unsigned long fpreg_offset
;
13305 unsigned long frame_offset
;
13306 unsigned long frame_reg
;
13307 unsigned long pc_reg
;
13310 static procS cur_proc
;
13311 static procS
*cur_proc_ptr
;
13312 static int numprocs
;
13314 /* Fill in an rs_align_code fragment. */
13317 mips_handle_align (fragS
*fragp
)
13319 if (fragp
->fr_type
!= rs_align_code
)
13322 if (mips_opts
.mips16
)
13324 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13325 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13330 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13331 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13339 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13343 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13347 md_obj_begin (void)
13354 /* check for premature end, nesting errors, etc */
13356 as_warn (_("missing .end at end of assembly"));
13365 if (*input_line_pointer
== '-')
13367 ++input_line_pointer
;
13370 if (!ISDIGIT (*input_line_pointer
))
13371 as_bad (_("expected simple number"));
13372 if (input_line_pointer
[0] == '0')
13374 if (input_line_pointer
[1] == 'x')
13376 input_line_pointer
+= 2;
13377 while (ISXDIGIT (*input_line_pointer
))
13380 val
|= hex_value (*input_line_pointer
++);
13382 return negative
? -val
: val
;
13386 ++input_line_pointer
;
13387 while (ISDIGIT (*input_line_pointer
))
13390 val
|= *input_line_pointer
++ - '0';
13392 return negative
? -val
: val
;
13395 if (!ISDIGIT (*input_line_pointer
))
13397 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13398 *input_line_pointer
, *input_line_pointer
);
13399 as_warn (_("invalid number"));
13402 while (ISDIGIT (*input_line_pointer
))
13405 val
+= *input_line_pointer
++ - '0';
13407 return negative
? -val
: val
;
13410 /* The .file directive; just like the usual .file directive, but there
13411 is an initial number which is the ECOFF file index. In the non-ECOFF
13412 case .file implies DWARF-2. */
13415 s_mips_file (int x ATTRIBUTE_UNUSED
)
13417 static int first_file_directive
= 0;
13419 if (ECOFF_DEBUGGING
)
13428 filename
= dwarf2_directive_file (0);
13430 /* Versions of GCC up to 3.1 start files with a ".file"
13431 directive even for stabs output. Make sure that this
13432 ".file" is handled. Note that you need a version of GCC
13433 after 3.1 in order to support DWARF-2 on MIPS. */
13434 if (filename
!= NULL
&& ! first_file_directive
)
13436 (void) new_logical_line (filename
, -1);
13437 s_app_file_string (filename
, 0);
13439 first_file_directive
= 1;
13443 /* The .loc directive, implying DWARF-2. */
13446 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13448 if (!ECOFF_DEBUGGING
)
13449 dwarf2_directive_loc (0);
13452 /* The .end directive. */
13455 s_mips_end (int x ATTRIBUTE_UNUSED
)
13459 /* Following functions need their own .frame and .cprestore directives. */
13460 mips_frame_reg_valid
= 0;
13461 mips_cprestore_valid
= 0;
13463 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13466 demand_empty_rest_of_line ();
13471 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13472 as_warn (_(".end not in text section"));
13476 as_warn (_(".end directive without a preceding .ent directive."));
13477 demand_empty_rest_of_line ();
13483 assert (S_GET_NAME (p
));
13484 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13485 as_warn (_(".end symbol does not match .ent symbol."));
13487 if (debug_type
== DEBUG_STABS
)
13488 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13492 as_warn (_(".end directive missing or unknown symbol"));
13495 /* Create an expression to calculate the size of the function. */
13496 if (p
&& cur_proc_ptr
)
13498 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13499 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13502 exp
->X_op
= O_subtract
;
13503 exp
->X_add_symbol
= symbol_temp_new_now ();
13504 exp
->X_op_symbol
= p
;
13505 exp
->X_add_number
= 0;
13507 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13510 /* Generate a .pdr section. */
13511 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13514 segT saved_seg
= now_seg
;
13515 subsegT saved_subseg
= now_subseg
;
13520 dot
= frag_now_fix ();
13522 #ifdef md_flush_pending_output
13523 md_flush_pending_output ();
13527 subseg_set (pdr_seg
, 0);
13529 /* Write the symbol. */
13530 exp
.X_op
= O_symbol
;
13531 exp
.X_add_symbol
= p
;
13532 exp
.X_add_number
= 0;
13533 emit_expr (&exp
, 4);
13535 fragp
= frag_more (7 * 4);
13537 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13538 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13539 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13540 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13541 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13542 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13543 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13545 subseg_set (saved_seg
, saved_subseg
);
13547 #endif /* OBJ_ELF */
13549 cur_proc_ptr
= NULL
;
13552 /* The .aent and .ent directives. */
13555 s_mips_ent (int aent
)
13559 symbolP
= get_symbol ();
13560 if (*input_line_pointer
== ',')
13561 ++input_line_pointer
;
13562 SKIP_WHITESPACE ();
13563 if (ISDIGIT (*input_line_pointer
)
13564 || *input_line_pointer
== '-')
13567 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13568 as_warn (_(".ent or .aent not in text section."));
13570 if (!aent
&& cur_proc_ptr
)
13571 as_warn (_("missing .end"));
13575 /* This function needs its own .frame and .cprestore directives. */
13576 mips_frame_reg_valid
= 0;
13577 mips_cprestore_valid
= 0;
13579 cur_proc_ptr
= &cur_proc
;
13580 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13582 cur_proc_ptr
->func_sym
= symbolP
;
13584 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13588 if (debug_type
== DEBUG_STABS
)
13589 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13590 S_GET_NAME (symbolP
));
13593 demand_empty_rest_of_line ();
13596 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13597 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13598 s_mips_frame is used so that we can set the PDR information correctly.
13599 We can't use the ecoff routines because they make reference to the ecoff
13600 symbol table (in the mdebug section). */
13603 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13606 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13610 if (cur_proc_ptr
== (procS
*) NULL
)
13612 as_warn (_(".frame outside of .ent"));
13613 demand_empty_rest_of_line ();
13617 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13619 SKIP_WHITESPACE ();
13620 if (*input_line_pointer
++ != ','
13621 || get_absolute_expression_and_terminator (&val
) != ',')
13623 as_warn (_("Bad .frame directive"));
13624 --input_line_pointer
;
13625 demand_empty_rest_of_line ();
13629 cur_proc_ptr
->frame_offset
= val
;
13630 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13632 demand_empty_rest_of_line ();
13635 #endif /* OBJ_ELF */
13639 /* The .fmask and .mask directives. If the mdebug section is present
13640 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13641 embedded targets, s_mips_mask is used so that we can set the PDR
13642 information correctly. We can't use the ecoff routines because they
13643 make reference to the ecoff symbol table (in the mdebug section). */
13646 s_mips_mask (int reg_type
)
13649 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13653 if (cur_proc_ptr
== (procS
*) NULL
)
13655 as_warn (_(".mask/.fmask outside of .ent"));
13656 demand_empty_rest_of_line ();
13660 if (get_absolute_expression_and_terminator (&mask
) != ',')
13662 as_warn (_("Bad .mask/.fmask directive"));
13663 --input_line_pointer
;
13664 demand_empty_rest_of_line ();
13668 off
= get_absolute_expression ();
13670 if (reg_type
== 'F')
13672 cur_proc_ptr
->fpreg_mask
= mask
;
13673 cur_proc_ptr
->fpreg_offset
= off
;
13677 cur_proc_ptr
->reg_mask
= mask
;
13678 cur_proc_ptr
->reg_offset
= off
;
13681 demand_empty_rest_of_line ();
13684 #endif /* OBJ_ELF */
13685 s_ignore (reg_type
);
13688 /* A table describing all the processors gas knows about. Names are
13689 matched in the order listed.
13691 To ease comparison, please keep this table in the same order as
13692 gcc's mips_cpu_info_table[]. */
13693 static const struct mips_cpu_info mips_cpu_info_table
[] =
13695 /* Entries for generic ISAs */
13696 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13697 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13698 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13699 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13700 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13701 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13702 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13703 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13704 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13707 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13708 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13709 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13712 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13715 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13716 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13717 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13718 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13719 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13720 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13721 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13722 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13723 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13724 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13725 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13726 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13729 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13730 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13731 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13732 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13733 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13734 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13735 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13736 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13737 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13738 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13739 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13740 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13741 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13744 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13745 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13746 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13749 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13750 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13752 /* Broadcom SB-1 CPU core */
13753 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13760 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13761 with a final "000" replaced by "k". Ignore case.
13763 Note: this function is shared between GCC and GAS. */
13766 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13768 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13769 given
++, canonical
++;
13771 return ((*given
== 0 && *canonical
== 0)
13772 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13776 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13777 CPU name. We've traditionally allowed a lot of variation here.
13779 Note: this function is shared between GCC and GAS. */
13782 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13784 /* First see if the name matches exactly, or with a final "000"
13785 turned into "k". */
13786 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13789 /* If not, try comparing based on numerical designation alone.
13790 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13791 if (TOLOWER (*given
) == 'r')
13793 if (!ISDIGIT (*given
))
13796 /* Skip over some well-known prefixes in the canonical name,
13797 hoping to find a number there too. */
13798 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13800 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13802 else if (TOLOWER (canonical
[0]) == 'r')
13805 return mips_strict_matching_cpu_name_p (canonical
, given
);
13809 /* Parse an option that takes the name of a processor as its argument.
13810 OPTION is the name of the option and CPU_STRING is the argument.
13811 Return the corresponding processor enumeration if the CPU_STRING is
13812 recognized, otherwise report an error and return null.
13814 A similar function exists in GCC. */
13816 static const struct mips_cpu_info
*
13817 mips_parse_cpu (const char *option
, const char *cpu_string
)
13819 const struct mips_cpu_info
*p
;
13821 /* 'from-abi' selects the most compatible architecture for the given
13822 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13823 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13824 version. Look first at the -mgp options, if given, otherwise base
13825 the choice on MIPS_DEFAULT_64BIT.
13827 Treat NO_ABI like the EABIs. One reason to do this is that the
13828 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13829 architecture. This code picks MIPS I for 'mips' and MIPS III for
13830 'mips64', just as we did in the days before 'from-abi'. */
13831 if (strcasecmp (cpu_string
, "from-abi") == 0)
13833 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13834 return mips_cpu_info_from_isa (ISA_MIPS1
);
13836 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13837 return mips_cpu_info_from_isa (ISA_MIPS3
);
13839 if (file_mips_gp32
>= 0)
13840 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13842 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13847 /* 'default' has traditionally been a no-op. Probably not very useful. */
13848 if (strcasecmp (cpu_string
, "default") == 0)
13851 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13852 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13855 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13859 /* Return the canonical processor information for ISA (a member of the
13860 ISA_MIPS* enumeration). */
13862 static const struct mips_cpu_info
*
13863 mips_cpu_info_from_isa (int isa
)
13867 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13868 if (mips_cpu_info_table
[i
].is_isa
13869 && isa
== mips_cpu_info_table
[i
].isa
)
13870 return (&mips_cpu_info_table
[i
]);
13875 static const struct mips_cpu_info
*
13876 mips_cpu_info_from_arch (int arch
)
13880 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13881 if (arch
== mips_cpu_info_table
[i
].cpu
)
13882 return (&mips_cpu_info_table
[i
]);
13888 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13892 fprintf (stream
, "%24s", "");
13897 fprintf (stream
, ", ");
13901 if (*col_p
+ strlen (string
) > 72)
13903 fprintf (stream
, "\n%24s", "");
13907 fprintf (stream
, "%s", string
);
13908 *col_p
+= strlen (string
);
13914 md_show_usage (FILE *stream
)
13919 fprintf (stream
, _("\
13921 -EB generate big endian output\n\
13922 -EL generate little endian output\n\
13923 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13924 -G NUM allow referencing objects up to NUM bytes\n\
13925 implicitly with the gp register [default 8]\n"));
13926 fprintf (stream
, _("\
13927 -mips1 generate MIPS ISA I instructions\n\
13928 -mips2 generate MIPS ISA II instructions\n\
13929 -mips3 generate MIPS ISA III instructions\n\
13930 -mips4 generate MIPS ISA IV instructions\n\
13931 -mips5 generate MIPS ISA V instructions\n\
13932 -mips32 generate MIPS32 ISA instructions\n\
13933 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13934 -mips64 generate MIPS64 ISA instructions\n\
13935 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13936 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13940 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13941 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13942 show (stream
, "from-abi", &column
, &first
);
13943 fputc ('\n', stream
);
13945 fprintf (stream
, _("\
13946 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13947 -no-mCPU don't generate code specific to CPU.\n\
13948 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13952 show (stream
, "3900", &column
, &first
);
13953 show (stream
, "4010", &column
, &first
);
13954 show (stream
, "4100", &column
, &first
);
13955 show (stream
, "4650", &column
, &first
);
13956 fputc ('\n', stream
);
13958 fprintf (stream
, _("\
13959 -mips16 generate mips16 instructions\n\
13960 -no-mips16 do not generate mips16 instructions\n"));
13961 fprintf (stream
, _("\
13962 -mfix-vr4120 work around certain VR4120 errata\n\
13963 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
13964 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13965 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13966 -mno-shared optimize output for executables\n\
13967 -msym32 assume all symbols have 32-bit values\n\
13968 -O0 remove unneeded NOPs, do not swap branches\n\
13969 -O remove unneeded NOPs and swap branches\n\
13970 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13971 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13972 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13974 fprintf (stream
, _("\
13975 -KPIC, -call_shared generate SVR4 position independent code\n\
13976 -non_shared do not generate position independent code\n\
13977 -xgot assume a 32 bit GOT\n\
13978 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13979 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13981 -mabi=ABI create ABI conformant object file for:\n"));
13985 show (stream
, "32", &column
, &first
);
13986 show (stream
, "o64", &column
, &first
);
13987 show (stream
, "n32", &column
, &first
);
13988 show (stream
, "64", &column
, &first
);
13989 show (stream
, "eabi", &column
, &first
);
13991 fputc ('\n', stream
);
13993 fprintf (stream
, _("\
13994 -32 create o32 ABI object file (default)\n\
13995 -n32 create n32 ABI object file\n\
13996 -64 create 64 ABI object file\n"));
14001 mips_dwarf2_format (void)
14003 if (mips_abi
== N64_ABI
)
14006 return dwarf2_format_64bit_irix
;
14008 return dwarf2_format_64bit
;
14012 return dwarf2_format_32bit
;
14016 mips_dwarf2_addr_size (void)
14018 if (mips_abi
== N64_ABI
)
14024 /* Standard calling conventions leave the CFA at SP on entry. */
14026 mips_cfi_frame_initial_instructions (void)
14028 cfi_add_CFA_def_cfa_register (SP
);