1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 /* Allow override of standard little-endian ECOFF format. */
106 #ifndef ECOFF_LITTLE_FORMAT
107 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 /* Information about an instruction, including its format, operands
125 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
126 const struct mips_opcode
*insn_mo
;
128 /* True if this is a mips16 instruction and if we want the extended
130 bfd_boolean use_extend
;
132 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
133 unsigned short extend
;
135 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
136 a copy of INSN_MO->match with the operands filled in. */
137 unsigned long insn_opcode
;
139 /* The frag that contains the instruction. */
142 /* The offset into FRAG of the first instruction byte. */
145 /* The relocs associated with the instruction, if any. */
148 /* True if this entry cannot be moved from its current position. */
149 unsigned int fixed_p
: 1;
151 /* True if this instruction occurred in a .set noreorder block. */
152 unsigned int noreorder_p
: 1;
154 /* True for mips16 instructions that jump to an absolute address. */
155 unsigned int mips16_absolute_jump_p
: 1;
158 /* The ABI to use. */
169 /* MIPS ABI we are using for this output file. */
170 static enum mips_abi_level mips_abi
= NO_ABI
;
172 /* Whether or not we have code that can call pic code. */
173 int mips_abicalls
= FALSE
;
175 /* Whether or not we have code which can be put into a shared
177 static bfd_boolean mips_in_shared
= TRUE
;
179 /* This is the set of options which may be modified by the .set
180 pseudo-op. We use a struct so that .set push and .set pop are more
183 struct mips_set_options
185 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
186 if it has not been initialized. Changed by `.set mipsN', and the
187 -mipsN command line option, and the default CPU. */
189 /* Enabled Application Specific Extensions (ASEs). These are set to -1
190 if they have not been initialized. Changed by `.set <asename>', by
191 command line options, and based on the default architecture. */
198 /* Whether we are assembling for the mips16 processor. 0 if we are
199 not, 1 if we are, and -1 if the value has not been initialized.
200 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
201 -nomips16 command line options, and the default CPU. */
203 /* Non-zero if we should not reorder instructions. Changed by `.set
204 reorder' and `.set noreorder'. */
206 /* Non-zero if we should not permit the $at ($1) register to be used
207 in instructions. Changed by `.set at' and `.set noat'. */
209 /* Non-zero if we should warn when a macro instruction expands into
210 more than one machine instruction. Changed by `.set nomacro' and
212 int warn_about_macros
;
213 /* Non-zero if we should not move instructions. Changed by `.set
214 move', `.set volatile', `.set nomove', and `.set novolatile'. */
216 /* Non-zero if we should not optimize branches by moving the target
217 of the branch into the delay slot. Actually, we don't perform
218 this optimization anyhow. Changed by `.set bopt' and `.set
221 /* Non-zero if we should not autoextend mips16 instructions.
222 Changed by `.set autoextend' and `.set noautoextend'. */
224 /* Restrict general purpose registers and floating point registers
225 to 32 bit. This is initially determined when -mgp32 or -mfp32
226 is passed but can changed if the assembler code uses .set mipsN. */
229 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
230 command line option, and the default CPU. */
232 /* True if ".set sym32" is in effect. */
236 /* True if -mgp32 was passed. */
237 static int file_mips_gp32
= -1;
239 /* True if -mfp32 was passed. */
240 static int file_mips_fp32
= -1;
242 /* This is the struct we use to hold the current set of options. Note
243 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
244 -1 to indicate that they have not been initialized. */
246 static struct mips_set_options mips_opts
=
248 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
251 /* These variables are filled in with the masks of registers used.
252 The object format code reads them and puts them in the appropriate
254 unsigned long mips_gprmask
;
255 unsigned long mips_cprmask
[4];
257 /* MIPS ISA we are using for this output file. */
258 static int file_mips_isa
= ISA_UNKNOWN
;
260 /* True if -mips16 was passed or implied by arguments passed on the
261 command line (e.g., by -march). */
262 static int file_ase_mips16
;
264 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
265 || mips_opts.isa == ISA_MIPS32R2 \
266 || mips_opts.isa == ISA_MIPS64 \
267 || mips_opts.isa == ISA_MIPS64R2)
269 /* True if -mips3d was passed or implied by arguments passed on the
270 command line (e.g., by -march). */
271 static int file_ase_mips3d
;
273 /* True if -mdmx was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_mdmx
;
277 /* True if -msmartmips was passed or implied by arguments passed on the
278 command line (e.g., by -march). */
279 static int file_ase_smartmips
;
281 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
282 || mips_opts.isa == ISA_MIPS32R2)
284 /* True if -mdsp was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_dsp
;
288 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
289 || mips_opts.isa == ISA_MIPS64R2)
291 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mdspr2 was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_dspr2
;
297 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
298 || mips_opts.isa == ISA_MIPS64R2)
300 /* True if -mmt was passed or implied by arguments passed on the
301 command line (e.g., by -march). */
302 static int file_ase_mt
;
304 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
305 || mips_opts.isa == ISA_MIPS64R2)
307 /* The argument of the -march= flag. The architecture we are assembling. */
308 static int file_mips_arch
= CPU_UNKNOWN
;
309 static const char *mips_arch_string
;
311 /* The argument of the -mtune= flag. The architecture for which we
313 static int mips_tune
= CPU_UNKNOWN
;
314 static const char *mips_tune_string
;
316 /* True when generating 32-bit code for a 64-bit processor. */
317 static int mips_32bitmode
= 0;
319 /* True if the given ABI requires 32-bit registers. */
320 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
322 /* Likewise 64-bit registers. */
323 #define ABI_NEEDS_64BIT_REGS(ABI) \
325 || (ABI) == N64_ABI \
328 /* Return true if ISA supports 64 bit wide gp registers. */
329 #define ISA_HAS_64BIT_REGS(ISA) \
330 ((ISA) == ISA_MIPS3 \
331 || (ISA) == ISA_MIPS4 \
332 || (ISA) == ISA_MIPS5 \
333 || (ISA) == ISA_MIPS64 \
334 || (ISA) == ISA_MIPS64R2)
336 /* Return true if ISA supports 64 bit wide float registers. */
337 #define ISA_HAS_64BIT_FPRS(ISA) \
338 ((ISA) == ISA_MIPS3 \
339 || (ISA) == ISA_MIPS4 \
340 || (ISA) == ISA_MIPS5 \
341 || (ISA) == ISA_MIPS32R2 \
342 || (ISA) == ISA_MIPS64 \
343 || (ISA) == ISA_MIPS64R2)
345 /* Return true if ISA supports 64-bit right rotate (dror et al.)
347 #define ISA_HAS_DROR(ISA) \
348 ((ISA) == ISA_MIPS64R2)
350 /* Return true if ISA supports 32-bit right rotate (ror et al.)
352 #define ISA_HAS_ROR(ISA) \
353 ((ISA) == ISA_MIPS32R2 \
354 || (ISA) == ISA_MIPS64R2 \
355 || mips_opts.ase_smartmips)
357 /* Return true if ISA supports single-precision floats in odd registers. */
358 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
359 ((ISA) == ISA_MIPS32 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports move to/from high part of a 64-bit
365 floating-point register. */
366 #define ISA_HAS_MXHC1(ISA) \
367 ((ISA) == ISA_MIPS32R2 \
368 || (ISA) == ISA_MIPS64R2)
370 #define HAVE_32BIT_GPRS \
371 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
373 #define HAVE_32BIT_FPRS \
374 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
376 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
377 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
379 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
381 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
383 /* True if relocations are stored in-place. */
384 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
386 /* The ABI-derived address size. */
387 #define HAVE_64BIT_ADDRESSES \
388 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
389 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
391 /* The size of symbolic constants (i.e., expressions of the form
392 "SYMBOL" or "SYMBOL + OFFSET"). */
393 #define HAVE_32BIT_SYMBOLS \
394 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
395 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
397 /* Addresses are loaded in different ways, depending on the address size
398 in use. The n32 ABI Documentation also mandates the use of additions
399 with overflow checking, but existing implementations don't follow it. */
400 #define ADDRESS_ADD_INSN \
401 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
403 #define ADDRESS_ADDI_INSN \
404 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
406 #define ADDRESS_LOAD_INSN \
407 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
409 #define ADDRESS_STORE_INSN \
410 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
412 /* Return true if the given CPU supports the MIPS16 ASE. */
413 #define CPU_HAS_MIPS16(cpu) \
414 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
415 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
417 /* True if CPU has a dror instruction. */
418 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
420 /* True if CPU has a ror instruction. */
421 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
423 /* True if mflo and mfhi can be immediately followed by instructions
424 which write to the HI and LO registers.
426 According to MIPS specifications, MIPS ISAs I, II, and III need
427 (at least) two instructions between the reads of HI/LO and
428 instructions which write them, and later ISAs do not. Contradicting
429 the MIPS specifications, some MIPS IV processor user manuals (e.g.
430 the UM for the NEC Vr5000) document needing the instructions between
431 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
432 MIPS64 and later ISAs to have the interlocks, plus any specific
433 earlier-ISA CPUs for which CPU documentation declares that the
434 instructions are really interlocked. */
435 #define hilo_interlocks \
436 (mips_opts.isa == ISA_MIPS32 \
437 || mips_opts.isa == ISA_MIPS32R2 \
438 || mips_opts.isa == ISA_MIPS64 \
439 || mips_opts.isa == ISA_MIPS64R2 \
440 || mips_opts.arch == CPU_R4010 \
441 || mips_opts.arch == CPU_R10000 \
442 || mips_opts.arch == CPU_R12000 \
443 || mips_opts.arch == CPU_RM7000 \
444 || mips_opts.arch == CPU_VR5500 \
447 /* Whether the processor uses hardware interlocks to protect reads
448 from the GPRs after they are loaded from memory, and thus does not
449 require nops to be inserted. This applies to instructions marked
450 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
452 #define gpr_interlocks \
453 (mips_opts.isa != ISA_MIPS1 \
454 || mips_opts.arch == CPU_R3900)
456 /* Whether the processor uses hardware interlocks to avoid delays
457 required by coprocessor instructions, and thus does not require
458 nops to be inserted. This applies to instructions marked
459 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
460 between instructions marked INSN_WRITE_COND_CODE and ones marked
461 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
462 levels I, II, and III. */
463 /* Itbl support may require additional care here. */
464 #define cop_interlocks \
465 ((mips_opts.isa != ISA_MIPS1 \
466 && mips_opts.isa != ISA_MIPS2 \
467 && mips_opts.isa != ISA_MIPS3) \
468 || mips_opts.arch == CPU_R4300 \
471 /* Whether the processor uses hardware interlocks to protect reads
472 from coprocessor registers after they are loaded from memory, and
473 thus does not require nops to be inserted. This applies to
474 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
475 requires at MIPS ISA level I. */
476 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
478 /* Is this a mfhi or mflo instruction? */
479 #define MF_HILO_INSN(PINFO) \
480 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
482 /* MIPS PIC level. */
484 enum mips_pic_level mips_pic
;
486 /* 1 if we should generate 32 bit offsets from the $gp register in
487 SVR4_PIC mode. Currently has no meaning in other modes. */
488 static int mips_big_got
= 0;
490 /* 1 if trap instructions should used for overflow rather than break
492 static int mips_trap
= 0;
494 /* 1 if double width floating point constants should not be constructed
495 by assembling two single width halves into two single width floating
496 point registers which just happen to alias the double width destination
497 register. On some architectures this aliasing can be disabled by a bit
498 in the status register, and the setting of this bit cannot be determined
499 automatically at assemble time. */
500 static int mips_disable_float_construction
;
502 /* Non-zero if any .set noreorder directives were used. */
504 static int mips_any_noreorder
;
506 /* Non-zero if nops should be inserted when the register referenced in
507 an mfhi/mflo instruction is read in the next two instructions. */
508 static int mips_7000_hilo_fix
;
510 /* The size of objects in the small data section. */
511 static unsigned int g_switch_value
= 8;
512 /* Whether the -G option was used. */
513 static int g_switch_seen
= 0;
518 /* If we can determine in advance that GP optimization won't be
519 possible, we can skip the relaxation stuff that tries to produce
520 GP-relative references. This makes delay slot optimization work
523 This function can only provide a guess, but it seems to work for
524 gcc output. It needs to guess right for gcc, otherwise gcc
525 will put what it thinks is a GP-relative instruction in a branch
528 I don't know if a fix is needed for the SVR4_PIC mode. I've only
529 fixed it for the non-PIC mode. KR 95/04/07 */
530 static int nopic_need_relax (symbolS
*, int);
532 /* handle of the OPCODE hash table */
533 static struct hash_control
*op_hash
= NULL
;
535 /* The opcode hash table we use for the mips16. */
536 static struct hash_control
*mips16_op_hash
= NULL
;
538 /* This array holds the chars that always start a comment. If the
539 pre-processor is disabled, these aren't very useful */
540 const char comment_chars
[] = "#";
542 /* This array holds the chars that only start a comment at the beginning of
543 a line. If the line seems to have the form '# 123 filename'
544 .line and .file directives will appear in the pre-processed output */
545 /* Note that input_file.c hand checks for '#' at the beginning of the
546 first line of the input file. This is because the compiler outputs
547 #NO_APP at the beginning of its output. */
548 /* Also note that C style comments are always supported. */
549 const char line_comment_chars
[] = "#";
551 /* This array holds machine specific line separator characters. */
552 const char line_separator_chars
[] = ";";
554 /* Chars that can be used to separate mant from exp in floating point nums */
555 const char EXP_CHARS
[] = "eE";
557 /* Chars that mean this number is a floating point constant */
560 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
562 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
563 changed in read.c . Ideally it shouldn't have to know about it at all,
564 but nothing is ideal around here.
567 static char *insn_error
;
569 static int auto_align
= 1;
571 /* When outputting SVR4 PIC code, the assembler needs to know the
572 offset in the stack frame from which to restore the $gp register.
573 This is set by the .cprestore pseudo-op, and saved in this
575 static offsetT mips_cprestore_offset
= -1;
577 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
578 more optimizations, it can use a register value instead of a memory-saved
579 offset and even an other register than $gp as global pointer. */
580 static offsetT mips_cpreturn_offset
= -1;
581 static int mips_cpreturn_register
= -1;
582 static int mips_gp_register
= GP
;
583 static int mips_gprel_offset
= 0;
585 /* Whether mips_cprestore_offset has been set in the current function
586 (or whether it has already been warned about, if not). */
587 static int mips_cprestore_valid
= 0;
589 /* This is the register which holds the stack frame, as set by the
590 .frame pseudo-op. This is needed to implement .cprestore. */
591 static int mips_frame_reg
= SP
;
593 /* Whether mips_frame_reg has been set in the current function
594 (or whether it has already been warned about, if not). */
595 static int mips_frame_reg_valid
= 0;
597 /* To output NOP instructions correctly, we need to keep information
598 about the previous two instructions. */
600 /* Whether we are optimizing. The default value of 2 means to remove
601 unneeded NOPs and swap branch instructions when possible. A value
602 of 1 means to not swap branches. A value of 0 means to always
604 static int mips_optimize
= 2;
606 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
607 equivalent to seeing no -g option at all. */
608 static int mips_debug
= 0;
610 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
611 #define MAX_VR4130_NOPS 4
613 /* The maximum number of NOPs needed to fill delay slots. */
614 #define MAX_DELAY_NOPS 2
616 /* The maximum number of NOPs needed for any purpose. */
619 /* A list of previous instructions, with index 0 being the most recent.
620 We need to look back MAX_NOPS instructions when filling delay slots
621 or working around processor errata. We need to look back one
622 instruction further if we're thinking about using history[0] to
623 fill a branch delay slot. */
624 static struct mips_cl_insn history
[1 + MAX_NOPS
];
626 /* Nop instructions used by emit_nop. */
627 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
629 /* The appropriate nop for the current mode. */
630 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
632 /* If this is set, it points to a frag holding nop instructions which
633 were inserted before the start of a noreorder section. If those
634 nops turn out to be unnecessary, the size of the frag can be
636 static fragS
*prev_nop_frag
;
638 /* The number of nop instructions we created in prev_nop_frag. */
639 static int prev_nop_frag_holds
;
641 /* The number of nop instructions that we know we need in
643 static int prev_nop_frag_required
;
645 /* The number of instructions we've seen since prev_nop_frag. */
646 static int prev_nop_frag_since
;
648 /* For ECOFF and ELF, relocations against symbols are done in two
649 parts, with a HI relocation and a LO relocation. Each relocation
650 has only 16 bits of space to store an addend. This means that in
651 order for the linker to handle carries correctly, it must be able
652 to locate both the HI and the LO relocation. This means that the
653 relocations must appear in order in the relocation table.
655 In order to implement this, we keep track of each unmatched HI
656 relocation. We then sort them so that they immediately precede the
657 corresponding LO relocation. */
662 struct mips_hi_fixup
*next
;
665 /* The section this fixup is in. */
669 /* The list of unmatched HI relocs. */
671 static struct mips_hi_fixup
*mips_hi_fixup_list
;
673 /* The frag containing the last explicit relocation operator.
674 Null if explicit relocations have not been used. */
676 static fragS
*prev_reloc_op_frag
;
678 /* Map normal MIPS register numbers to mips16 register numbers. */
680 #define X ILLEGAL_REG
681 static const int mips32_to_16_reg_map
[] =
683 X
, X
, 2, 3, 4, 5, 6, 7,
684 X
, X
, X
, X
, X
, X
, X
, X
,
685 0, 1, X
, X
, X
, X
, X
, X
,
686 X
, X
, X
, X
, X
, X
, X
, X
690 /* Map mips16 register numbers to normal MIPS register numbers. */
692 static const unsigned int mips16_to_32_reg_map
[] =
694 16, 17, 2, 3, 4, 5, 6, 7
697 /* Classifies the kind of instructions we're interested in when
698 implementing -mfix-vr4120. */
699 enum fix_vr4120_class
{
706 NUM_FIX_VR4120_CLASSES
709 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
710 there must be at least one other instruction between an instruction
711 of type X and an instruction of type Y. */
712 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
714 /* True if -mfix-vr4120 is in force. */
715 static int mips_fix_vr4120
;
717 /* ...likewise -mfix-vr4130. */
718 static int mips_fix_vr4130
;
720 /* We don't relax branches by default, since this causes us to expand
721 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
722 fail to compute the offset before expanding the macro to the most
723 efficient expansion. */
725 static int mips_relax_branch
;
727 /* The expansion of many macros depends on the type of symbol that
728 they refer to. For example, when generating position-dependent code,
729 a macro that refers to a symbol may have two different expansions,
730 one which uses GP-relative addresses and one which uses absolute
731 addresses. When generating SVR4-style PIC, a macro may have
732 different expansions for local and global symbols.
734 We handle these situations by generating both sequences and putting
735 them in variant frags. In position-dependent code, the first sequence
736 will be the GP-relative one and the second sequence will be the
737 absolute one. In SVR4 PIC, the first sequence will be for global
738 symbols and the second will be for local symbols.
740 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
741 SECOND are the lengths of the two sequences in bytes. These fields
742 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
743 the subtype has the following flags:
746 Set if it has been decided that we should use the second
747 sequence instead of the first.
750 Set in the first variant frag if the macro's second implementation
751 is longer than its first. This refers to the macro as a whole,
752 not an individual relaxation.
755 Set in the first variant frag if the macro appeared in a .set nomacro
756 block and if one alternative requires a warning but the other does not.
759 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
762 The frag's "opcode" points to the first fixup for relaxable code.
764 Relaxable macros are generated using a sequence such as:
766 relax_start (SYMBOL);
767 ... generate first expansion ...
769 ... generate second expansion ...
772 The code and fixups for the unwanted alternative are discarded
773 by md_convert_frag. */
774 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
776 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
777 #define RELAX_SECOND(X) ((X) & 0xff)
778 #define RELAX_USE_SECOND 0x10000
779 #define RELAX_SECOND_LONGER 0x20000
780 #define RELAX_NOMACRO 0x40000
781 #define RELAX_DELAY_SLOT 0x80000
783 /* Branch without likely bit. If label is out of range, we turn:
785 beq reg1, reg2, label
795 with the following opcode replacements:
802 bltzal <-> bgezal (with jal label instead of j label)
804 Even though keeping the delay slot instruction in the delay slot of
805 the branch would be more efficient, it would be very tricky to do
806 correctly, because we'd have to introduce a variable frag *after*
807 the delay slot instruction, and expand that instead. Let's do it
808 the easy way for now, even if the branch-not-taken case now costs
809 one additional instruction. Out-of-range branches are not supposed
810 to be common, anyway.
812 Branch likely. If label is out of range, we turn:
814 beql reg1, reg2, label
815 delay slot (annulled if branch not taken)
824 delay slot (executed only if branch taken)
827 It would be possible to generate a shorter sequence by losing the
828 likely bit, generating something like:
833 delay slot (executed only if branch taken)
845 bltzall -> bgezal (with jal label instead of j label)
846 bgezall -> bltzal (ditto)
849 but it's not clear that it would actually improve performance. */
850 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
853 | ((toofar) ? 1 : 0) \
855 | ((likely) ? 4 : 0) \
856 | ((uncond) ? 8 : 0)))
857 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
858 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
859 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
860 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
861 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
863 /* For mips16 code, we use an entirely different form of relaxation.
864 mips16 supports two versions of most instructions which take
865 immediate values: a small one which takes some small value, and a
866 larger one which takes a 16 bit value. Since branches also follow
867 this pattern, relaxing these values is required.
869 We can assemble both mips16 and normal MIPS code in a single
870 object. Therefore, we need to support this type of relaxation at
871 the same time that we support the relaxation described above. We
872 use the high bit of the subtype field to distinguish these cases.
874 The information we store for this type of relaxation is the
875 argument code found in the opcode file for this relocation, whether
876 the user explicitly requested a small or extended form, and whether
877 the relocation is in a jump or jal delay slot. That tells us the
878 size of the value, and how it should be stored. We also store
879 whether the fragment is considered to be extended or not. We also
880 store whether this is known to be a branch to a different section,
881 whether we have tried to relax this frag yet, and whether we have
882 ever extended a PC relative fragment because of a shift count. */
883 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
886 | ((small) ? 0x100 : 0) \
887 | ((ext) ? 0x200 : 0) \
888 | ((dslot) ? 0x400 : 0) \
889 | ((jal_dslot) ? 0x800 : 0))
890 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
891 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
892 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
893 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
894 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
895 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
896 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
897 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
898 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
899 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
900 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
901 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
903 /* Is the given value a sign-extended 32-bit value? */
904 #define IS_SEXT_32BIT_NUM(x) \
905 (((x) &~ (offsetT) 0x7fffffff) == 0 \
906 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
908 /* Is the given value a sign-extended 16-bit value? */
909 #define IS_SEXT_16BIT_NUM(x) \
910 (((x) &~ (offsetT) 0x7fff) == 0 \
911 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
913 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
914 #define IS_ZEXT_32BIT_NUM(x) \
915 (((x) &~ (offsetT) 0xffffffff) == 0 \
916 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
918 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
919 VALUE << SHIFT. VALUE is evaluated exactly once. */
920 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
921 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
922 | (((VALUE) & (MASK)) << (SHIFT)))
924 /* Extract bits MASK << SHIFT from STRUCT and shift them right
926 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
927 (((STRUCT) >> (SHIFT)) & (MASK))
929 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
930 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
932 include/opcode/mips.h specifies operand fields using the macros
933 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
934 with "MIPS16OP" instead of "OP". */
935 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
936 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
937 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
938 INSERT_BITS ((INSN).insn_opcode, VALUE, \
939 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
941 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
942 #define EXTRACT_OPERAND(FIELD, INSN) \
943 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
944 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
945 EXTRACT_BITS ((INSN).insn_opcode, \
946 MIPS16OP_MASK_##FIELD, \
949 /* Global variables used when generating relaxable macros. See the
950 comment above RELAX_ENCODE for more details about how relaxation
953 /* 0 if we're not emitting a relaxable macro.
954 1 if we're emitting the first of the two relaxation alternatives.
955 2 if we're emitting the second alternative. */
958 /* The first relaxable fixup in the current frag. (In other words,
959 the first fixup that refers to relaxable code.) */
962 /* sizes[0] says how many bytes of the first alternative are stored in
963 the current frag. Likewise sizes[1] for the second alternative. */
964 unsigned int sizes
[2];
966 /* The symbol on which the choice of sequence depends. */
970 /* Global variables used to decide whether a macro needs a warning. */
972 /* True if the macro is in a branch delay slot. */
973 bfd_boolean delay_slot_p
;
975 /* For relaxable macros, sizes[0] is the length of the first alternative
976 in bytes and sizes[1] is the length of the second alternative.
977 For non-relaxable macros, both elements give the length of the
979 unsigned int sizes
[2];
981 /* The first variant frag for this macro. */
983 } mips_macro_warning
;
985 /* Prototypes for static functions. */
987 #define internalError() \
988 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
990 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
992 static void append_insn
993 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
994 static void mips_no_prev_insn (void);
995 static void mips16_macro_build
996 (expressionS
*, const char *, const char *, va_list);
997 static void load_register (int, expressionS
*, int);
998 static void macro_start (void);
999 static void macro_end (void);
1000 static void macro (struct mips_cl_insn
* ip
);
1001 static void mips16_macro (struct mips_cl_insn
* ip
);
1002 #ifdef LOSING_COMPILER
1003 static void macro2 (struct mips_cl_insn
* ip
);
1005 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1006 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1007 static void mips16_immed
1008 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1009 unsigned long *, bfd_boolean
*, unsigned short *);
1010 static size_t my_getSmallExpression
1011 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1012 static void my_getExpression (expressionS
*, char *);
1013 static void s_align (int);
1014 static void s_change_sec (int);
1015 static void s_change_section (int);
1016 static void s_cons (int);
1017 static void s_float_cons (int);
1018 static void s_mips_globl (int);
1019 static void s_option (int);
1020 static void s_mipsset (int);
1021 static void s_abicalls (int);
1022 static void s_cpload (int);
1023 static void s_cpsetup (int);
1024 static void s_cplocal (int);
1025 static void s_cprestore (int);
1026 static void s_cpreturn (int);
1027 static void s_gpvalue (int);
1028 static void s_gpword (int);
1029 static void s_gpdword (int);
1030 static void s_cpadd (int);
1031 static void s_insn (int);
1032 static void md_obj_begin (void);
1033 static void md_obj_end (void);
1034 static void s_mips_ent (int);
1035 static void s_mips_end (int);
1036 static void s_mips_frame (int);
1037 static void s_mips_mask (int reg_type
);
1038 static void s_mips_stab (int);
1039 static void s_mips_weakext (int);
1040 static void s_mips_file (int);
1041 static void s_mips_loc (int);
1042 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1043 static int relaxed_branch_length (fragS
*, asection
*, int);
1044 static int validate_mips_insn (const struct mips_opcode
*);
1046 /* Table and functions used to map between CPU/ISA names, and
1047 ISA levels, and CPU numbers. */
1049 struct mips_cpu_info
1051 const char *name
; /* CPU or ISA name. */
1052 int flags
; /* ASEs available, or ISA flag. */
1053 int isa
; /* ISA level. */
1054 int cpu
; /* CPU number (default CPU if ISA). */
1057 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1058 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1059 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1060 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1061 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1062 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1063 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1065 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1066 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1067 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1071 The following pseudo-ops from the Kane and Heinrich MIPS book
1072 should be defined here, but are currently unsupported: .alias,
1073 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1075 The following pseudo-ops from the Kane and Heinrich MIPS book are
1076 specific to the type of debugging information being generated, and
1077 should be defined by the object format: .aent, .begin, .bend,
1078 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1081 The following pseudo-ops from the Kane and Heinrich MIPS book are
1082 not MIPS CPU specific, but are also not specific to the object file
1083 format. This file is probably the best place to define them, but
1084 they are not currently supported: .asm0, .endr, .lab, .struct. */
1086 static const pseudo_typeS mips_pseudo_table
[] =
1088 /* MIPS specific pseudo-ops. */
1089 {"option", s_option
, 0},
1090 {"set", s_mipsset
, 0},
1091 {"rdata", s_change_sec
, 'r'},
1092 {"sdata", s_change_sec
, 's'},
1093 {"livereg", s_ignore
, 0},
1094 {"abicalls", s_abicalls
, 0},
1095 {"cpload", s_cpload
, 0},
1096 {"cpsetup", s_cpsetup
, 0},
1097 {"cplocal", s_cplocal
, 0},
1098 {"cprestore", s_cprestore
, 0},
1099 {"cpreturn", s_cpreturn
, 0},
1100 {"gpvalue", s_gpvalue
, 0},
1101 {"gpword", s_gpword
, 0},
1102 {"gpdword", s_gpdword
, 0},
1103 {"cpadd", s_cpadd
, 0},
1104 {"insn", s_insn
, 0},
1106 /* Relatively generic pseudo-ops that happen to be used on MIPS
1108 {"asciiz", stringer
, 1},
1109 {"bss", s_change_sec
, 'b'},
1111 {"half", s_cons
, 1},
1112 {"dword", s_cons
, 3},
1113 {"weakext", s_mips_weakext
, 0},
1114 {"origin", s_org
, 0},
1115 {"repeat", s_rept
, 0},
1117 /* These pseudo-ops are defined in read.c, but must be overridden
1118 here for one reason or another. */
1119 {"align", s_align
, 0},
1120 {"byte", s_cons
, 0},
1121 {"data", s_change_sec
, 'd'},
1122 {"double", s_float_cons
, 'd'},
1123 {"float", s_float_cons
, 'f'},
1124 {"globl", s_mips_globl
, 0},
1125 {"global", s_mips_globl
, 0},
1126 {"hword", s_cons
, 1},
1128 {"long", s_cons
, 2},
1129 {"octa", s_cons
, 4},
1130 {"quad", s_cons
, 3},
1131 {"section", s_change_section
, 0},
1132 {"short", s_cons
, 1},
1133 {"single", s_float_cons
, 'f'},
1134 {"stabn", s_mips_stab
, 'n'},
1135 {"text", s_change_sec
, 't'},
1136 {"word", s_cons
, 2},
1138 { "extern", ecoff_directive_extern
, 0},
1143 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1145 /* These pseudo-ops should be defined by the object file format.
1146 However, a.out doesn't support them, so we have versions here. */
1147 {"aent", s_mips_ent
, 1},
1148 {"bgnb", s_ignore
, 0},
1149 {"end", s_mips_end
, 0},
1150 {"endb", s_ignore
, 0},
1151 {"ent", s_mips_ent
, 0},
1152 {"file", s_mips_file
, 0},
1153 {"fmask", s_mips_mask
, 'F'},
1154 {"frame", s_mips_frame
, 0},
1155 {"loc", s_mips_loc
, 0},
1156 {"mask", s_mips_mask
, 'R'},
1157 {"verstamp", s_ignore
, 0},
1161 extern void pop_insert (const pseudo_typeS
*);
1164 mips_pop_insert (void)
1166 pop_insert (mips_pseudo_table
);
1167 if (! ECOFF_DEBUGGING
)
1168 pop_insert (mips_nonecoff_pseudo_table
);
1171 /* Symbols labelling the current insn. */
1173 struct insn_label_list
1175 struct insn_label_list
*next
;
1179 static struct insn_label_list
*free_insn_labels
;
1180 #define label_list tc_segment_info_data
1182 static void mips_clear_insn_labels (void);
1185 mips_clear_insn_labels (void)
1187 register struct insn_label_list
**pl
;
1188 segment_info_type
*si
;
1192 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1195 si
= seg_info (now_seg
);
1196 *pl
= si
->label_list
;
1197 si
->label_list
= NULL
;
1202 static char *expr_end
;
1204 /* Expressions which appear in instructions. These are set by
1207 static expressionS imm_expr
;
1208 static expressionS imm2_expr
;
1209 static expressionS offset_expr
;
1211 /* Relocs associated with imm_expr and offset_expr. */
1213 static bfd_reloc_code_real_type imm_reloc
[3]
1214 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1215 static bfd_reloc_code_real_type offset_reloc
[3]
1216 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1218 /* These are set by mips16_ip if an explicit extension is used. */
1220 static bfd_boolean mips16_small
, mips16_ext
;
1223 /* The pdr segment for per procedure frame/regmask info. Not used for
1226 static segT pdr_seg
;
1229 /* The default target format to use. */
1232 mips_target_format (void)
1234 switch (OUTPUT_FLAVOR
)
1236 case bfd_target_ecoff_flavour
:
1237 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1238 case bfd_target_coff_flavour
:
1240 case bfd_target_elf_flavour
:
1242 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1243 return (target_big_endian
1244 ? "elf32-bigmips-vxworks"
1245 : "elf32-littlemips-vxworks");
1248 /* This is traditional mips. */
1249 return (target_big_endian
1250 ? (HAVE_64BIT_OBJECTS
1251 ? "elf64-tradbigmips"
1253 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1254 : (HAVE_64BIT_OBJECTS
1255 ? "elf64-tradlittlemips"
1257 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1259 return (target_big_endian
1260 ? (HAVE_64BIT_OBJECTS
1263 ? "elf32-nbigmips" : "elf32-bigmips"))
1264 : (HAVE_64BIT_OBJECTS
1265 ? "elf64-littlemips"
1267 ? "elf32-nlittlemips" : "elf32-littlemips")));
1275 /* Return the length of instruction INSN. */
1277 static inline unsigned int
1278 insn_length (const struct mips_cl_insn
*insn
)
1280 if (!mips_opts
.mips16
)
1282 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1285 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1288 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1293 insn
->use_extend
= FALSE
;
1295 insn
->insn_opcode
= mo
->match
;
1298 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1299 insn
->fixp
[i
] = NULL
;
1300 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1301 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1302 insn
->mips16_absolute_jump_p
= 0;
1305 /* Install INSN at the location specified by its "frag" and "where" fields. */
1308 install_insn (const struct mips_cl_insn
*insn
)
1310 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1311 if (!mips_opts
.mips16
)
1312 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1313 else if (insn
->mips16_absolute_jump_p
)
1315 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1316 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1320 if (insn
->use_extend
)
1322 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1325 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1329 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1330 and install the opcode in the new location. */
1333 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1338 insn
->where
= where
;
1339 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1340 if (insn
->fixp
[i
] != NULL
)
1342 insn
->fixp
[i
]->fx_frag
= frag
;
1343 insn
->fixp
[i
]->fx_where
= where
;
1345 install_insn (insn
);
1348 /* Add INSN to the end of the output. */
1351 add_fixed_insn (struct mips_cl_insn
*insn
)
1353 char *f
= frag_more (insn_length (insn
));
1354 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1357 /* Start a variant frag and move INSN to the start of the variant part,
1358 marking it as fixed. The other arguments are as for frag_var. */
1361 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1362 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1364 frag_grow (max_chars
);
1365 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1367 frag_var (rs_machine_dependent
, max_chars
, var
,
1368 subtype
, symbol
, offset
, NULL
);
1371 /* Insert N copies of INSN into the history buffer, starting at
1372 position FIRST. Neither FIRST nor N need to be clipped. */
1375 insert_into_history (unsigned int first
, unsigned int n
,
1376 const struct mips_cl_insn
*insn
)
1378 if (mips_relax
.sequence
!= 2)
1382 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1384 history
[i
] = history
[i
- n
];
1390 /* Emit a nop instruction, recording it in the history buffer. */
1395 add_fixed_insn (NOP_INSN
);
1396 insert_into_history (0, 1, NOP_INSN
);
1399 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1400 the idea is to make it obvious at a glance that each errata is
1404 init_vr4120_conflicts (void)
1406 #define CONFLICT(FIRST, SECOND) \
1407 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1409 /* Errata 21 - [D]DIV[U] after [D]MACC */
1410 CONFLICT (MACC
, DIV
);
1411 CONFLICT (DMACC
, DIV
);
1413 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1414 CONFLICT (DMULT
, DMULT
);
1415 CONFLICT (DMULT
, DMACC
);
1416 CONFLICT (DMACC
, DMULT
);
1417 CONFLICT (DMACC
, DMACC
);
1419 /* Errata 24 - MT{LO,HI} after [D]MACC */
1420 CONFLICT (MACC
, MTHILO
);
1421 CONFLICT (DMACC
, MTHILO
);
1423 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1424 instruction is executed immediately after a MACC or DMACC
1425 instruction, the result of [either instruction] is incorrect." */
1426 CONFLICT (MACC
, MULT
);
1427 CONFLICT (MACC
, DMULT
);
1428 CONFLICT (DMACC
, MULT
);
1429 CONFLICT (DMACC
, DMULT
);
1431 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1432 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1433 DDIV or DDIVU instruction, the result of the MACC or
1434 DMACC instruction is incorrect.". */
1435 CONFLICT (DMULT
, MACC
);
1436 CONFLICT (DMULT
, DMACC
);
1437 CONFLICT (DIV
, MACC
);
1438 CONFLICT (DIV
, DMACC
);
1448 #define RTYPE_MASK 0x1ff00
1449 #define RTYPE_NUM 0x00100
1450 #define RTYPE_FPU 0x00200
1451 #define RTYPE_FCC 0x00400
1452 #define RTYPE_VEC 0x00800
1453 #define RTYPE_GP 0x01000
1454 #define RTYPE_CP0 0x02000
1455 #define RTYPE_PC 0x04000
1456 #define RTYPE_ACC 0x08000
1457 #define RTYPE_CCC 0x10000
1458 #define RNUM_MASK 0x000ff
1459 #define RWARN 0x80000
1461 #define GENERIC_REGISTER_NUMBERS \
1462 {"$0", RTYPE_NUM | 0}, \
1463 {"$1", RTYPE_NUM | 1}, \
1464 {"$2", RTYPE_NUM | 2}, \
1465 {"$3", RTYPE_NUM | 3}, \
1466 {"$4", RTYPE_NUM | 4}, \
1467 {"$5", RTYPE_NUM | 5}, \
1468 {"$6", RTYPE_NUM | 6}, \
1469 {"$7", RTYPE_NUM | 7}, \
1470 {"$8", RTYPE_NUM | 8}, \
1471 {"$9", RTYPE_NUM | 9}, \
1472 {"$10", RTYPE_NUM | 10}, \
1473 {"$11", RTYPE_NUM | 11}, \
1474 {"$12", RTYPE_NUM | 12}, \
1475 {"$13", RTYPE_NUM | 13}, \
1476 {"$14", RTYPE_NUM | 14}, \
1477 {"$15", RTYPE_NUM | 15}, \
1478 {"$16", RTYPE_NUM | 16}, \
1479 {"$17", RTYPE_NUM | 17}, \
1480 {"$18", RTYPE_NUM | 18}, \
1481 {"$19", RTYPE_NUM | 19}, \
1482 {"$20", RTYPE_NUM | 20}, \
1483 {"$21", RTYPE_NUM | 21}, \
1484 {"$22", RTYPE_NUM | 22}, \
1485 {"$23", RTYPE_NUM | 23}, \
1486 {"$24", RTYPE_NUM | 24}, \
1487 {"$25", RTYPE_NUM | 25}, \
1488 {"$26", RTYPE_NUM | 26}, \
1489 {"$27", RTYPE_NUM | 27}, \
1490 {"$28", RTYPE_NUM | 28}, \
1491 {"$29", RTYPE_NUM | 29}, \
1492 {"$30", RTYPE_NUM | 30}, \
1493 {"$31", RTYPE_NUM | 31}
1495 #define FPU_REGISTER_NAMES \
1496 {"$f0", RTYPE_FPU | 0}, \
1497 {"$f1", RTYPE_FPU | 1}, \
1498 {"$f2", RTYPE_FPU | 2}, \
1499 {"$f3", RTYPE_FPU | 3}, \
1500 {"$f4", RTYPE_FPU | 4}, \
1501 {"$f5", RTYPE_FPU | 5}, \
1502 {"$f6", RTYPE_FPU | 6}, \
1503 {"$f7", RTYPE_FPU | 7}, \
1504 {"$f8", RTYPE_FPU | 8}, \
1505 {"$f9", RTYPE_FPU | 9}, \
1506 {"$f10", RTYPE_FPU | 10}, \
1507 {"$f11", RTYPE_FPU | 11}, \
1508 {"$f12", RTYPE_FPU | 12}, \
1509 {"$f13", RTYPE_FPU | 13}, \
1510 {"$f14", RTYPE_FPU | 14}, \
1511 {"$f15", RTYPE_FPU | 15}, \
1512 {"$f16", RTYPE_FPU | 16}, \
1513 {"$f17", RTYPE_FPU | 17}, \
1514 {"$f18", RTYPE_FPU | 18}, \
1515 {"$f19", RTYPE_FPU | 19}, \
1516 {"$f20", RTYPE_FPU | 20}, \
1517 {"$f21", RTYPE_FPU | 21}, \
1518 {"$f22", RTYPE_FPU | 22}, \
1519 {"$f23", RTYPE_FPU | 23}, \
1520 {"$f24", RTYPE_FPU | 24}, \
1521 {"$f25", RTYPE_FPU | 25}, \
1522 {"$f26", RTYPE_FPU | 26}, \
1523 {"$f27", RTYPE_FPU | 27}, \
1524 {"$f28", RTYPE_FPU | 28}, \
1525 {"$f29", RTYPE_FPU | 29}, \
1526 {"$f30", RTYPE_FPU | 30}, \
1527 {"$f31", RTYPE_FPU | 31}
1529 #define FPU_CONDITION_CODE_NAMES \
1530 {"$fcc0", RTYPE_FCC | 0}, \
1531 {"$fcc1", RTYPE_FCC | 1}, \
1532 {"$fcc2", RTYPE_FCC | 2}, \
1533 {"$fcc3", RTYPE_FCC | 3}, \
1534 {"$fcc4", RTYPE_FCC | 4}, \
1535 {"$fcc5", RTYPE_FCC | 5}, \
1536 {"$fcc6", RTYPE_FCC | 6}, \
1537 {"$fcc7", RTYPE_FCC | 7}
1539 #define COPROC_CONDITION_CODE_NAMES \
1540 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1541 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1542 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1543 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1544 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1545 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1546 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1547 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1549 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1550 {"$a4", RTYPE_GP | 8}, \
1551 {"$a5", RTYPE_GP | 9}, \
1552 {"$a6", RTYPE_GP | 10}, \
1553 {"$a7", RTYPE_GP | 11}, \
1554 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1555 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1556 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1557 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1558 {"$t0", RTYPE_GP | 12}, \
1559 {"$t1", RTYPE_GP | 13}, \
1560 {"$t2", RTYPE_GP | 14}, \
1561 {"$t3", RTYPE_GP | 15}
1563 #define O32_SYMBOLIC_REGISTER_NAMES \
1564 {"$t0", RTYPE_GP | 8}, \
1565 {"$t1", RTYPE_GP | 9}, \
1566 {"$t2", RTYPE_GP | 10}, \
1567 {"$t3", RTYPE_GP | 11}, \
1568 {"$t4", RTYPE_GP | 12}, \
1569 {"$t5", RTYPE_GP | 13}, \
1570 {"$t6", RTYPE_GP | 14}, \
1571 {"$t7", RTYPE_GP | 15}, \
1572 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1573 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1574 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1575 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1577 /* Remaining symbolic register names */
1578 #define SYMBOLIC_REGISTER_NAMES \
1579 {"$zero", RTYPE_GP | 0}, \
1580 {"$at", RTYPE_GP | 1}, \
1581 {"$AT", RTYPE_GP | 1}, \
1582 {"$v0", RTYPE_GP | 2}, \
1583 {"$v1", RTYPE_GP | 3}, \
1584 {"$a0", RTYPE_GP | 4}, \
1585 {"$a1", RTYPE_GP | 5}, \
1586 {"$a2", RTYPE_GP | 6}, \
1587 {"$a3", RTYPE_GP | 7}, \
1588 {"$s0", RTYPE_GP | 16}, \
1589 {"$s1", RTYPE_GP | 17}, \
1590 {"$s2", RTYPE_GP | 18}, \
1591 {"$s3", RTYPE_GP | 19}, \
1592 {"$s4", RTYPE_GP | 20}, \
1593 {"$s5", RTYPE_GP | 21}, \
1594 {"$s6", RTYPE_GP | 22}, \
1595 {"$s7", RTYPE_GP | 23}, \
1596 {"$t8", RTYPE_GP | 24}, \
1597 {"$t9", RTYPE_GP | 25}, \
1598 {"$k0", RTYPE_GP | 26}, \
1599 {"$kt0", RTYPE_GP | 26}, \
1600 {"$k1", RTYPE_GP | 27}, \
1601 {"$kt1", RTYPE_GP | 27}, \
1602 {"$gp", RTYPE_GP | 28}, \
1603 {"$sp", RTYPE_GP | 29}, \
1604 {"$s8", RTYPE_GP | 30}, \
1605 {"$fp", RTYPE_GP | 30}, \
1606 {"$ra", RTYPE_GP | 31}
1608 #define MIPS16_SPECIAL_REGISTER_NAMES \
1609 {"$pc", RTYPE_PC | 0}
1611 #define MDMX_VECTOR_REGISTER_NAMES \
1612 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1613 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1614 {"$v2", RTYPE_VEC | 2}, \
1615 {"$v3", RTYPE_VEC | 3}, \
1616 {"$v4", RTYPE_VEC | 4}, \
1617 {"$v5", RTYPE_VEC | 5}, \
1618 {"$v6", RTYPE_VEC | 6}, \
1619 {"$v7", RTYPE_VEC | 7}, \
1620 {"$v8", RTYPE_VEC | 8}, \
1621 {"$v9", RTYPE_VEC | 9}, \
1622 {"$v10", RTYPE_VEC | 10}, \
1623 {"$v11", RTYPE_VEC | 11}, \
1624 {"$v12", RTYPE_VEC | 12}, \
1625 {"$v13", RTYPE_VEC | 13}, \
1626 {"$v14", RTYPE_VEC | 14}, \
1627 {"$v15", RTYPE_VEC | 15}, \
1628 {"$v16", RTYPE_VEC | 16}, \
1629 {"$v17", RTYPE_VEC | 17}, \
1630 {"$v18", RTYPE_VEC | 18}, \
1631 {"$v19", RTYPE_VEC | 19}, \
1632 {"$v20", RTYPE_VEC | 20}, \
1633 {"$v21", RTYPE_VEC | 21}, \
1634 {"$v22", RTYPE_VEC | 22}, \
1635 {"$v23", RTYPE_VEC | 23}, \
1636 {"$v24", RTYPE_VEC | 24}, \
1637 {"$v25", RTYPE_VEC | 25}, \
1638 {"$v26", RTYPE_VEC | 26}, \
1639 {"$v27", RTYPE_VEC | 27}, \
1640 {"$v28", RTYPE_VEC | 28}, \
1641 {"$v29", RTYPE_VEC | 29}, \
1642 {"$v30", RTYPE_VEC | 30}, \
1643 {"$v31", RTYPE_VEC | 31}
1645 #define MIPS_DSP_ACCUMULATOR_NAMES \
1646 {"$ac0", RTYPE_ACC | 0}, \
1647 {"$ac1", RTYPE_ACC | 1}, \
1648 {"$ac2", RTYPE_ACC | 2}, \
1649 {"$ac3", RTYPE_ACC | 3}
1651 static const struct regname reg_names
[] = {
1652 GENERIC_REGISTER_NUMBERS
,
1654 FPU_CONDITION_CODE_NAMES
,
1655 COPROC_CONDITION_CODE_NAMES
,
1657 /* The $txx registers depends on the abi,
1658 these will be added later into the symbol table from
1659 one of the tables below once mips_abi is set after
1660 parsing of arguments from the command line. */
1661 SYMBOLIC_REGISTER_NAMES
,
1663 MIPS16_SPECIAL_REGISTER_NAMES
,
1664 MDMX_VECTOR_REGISTER_NAMES
,
1665 MIPS_DSP_ACCUMULATOR_NAMES
,
1669 static const struct regname reg_names_o32
[] = {
1670 O32_SYMBOLIC_REGISTER_NAMES
,
1674 static const struct regname reg_names_n32n64
[] = {
1675 N32N64_SYMBOLIC_REGISTER_NAMES
,
1680 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1687 /* Find end of name. */
1689 if (is_name_beginner (*e
))
1691 while (is_part_of_name (*e
))
1694 /* Terminate name. */
1698 /* Look for a register symbol. */
1699 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1701 int r
= S_GET_VALUE (symbolP
);
1703 reg
= r
& RNUM_MASK
;
1704 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1705 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1706 reg
= (r
& RNUM_MASK
) - 2;
1708 /* Else see if this is a register defined in an itbl entry. */
1709 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1716 if (itbl_get_reg_val (n
, &r
))
1717 reg
= r
& RNUM_MASK
;
1720 /* Advance to next token if a register was recognised. */
1723 else if (types
& RWARN
)
1724 as_warn ("Unrecognized register name `%s'", *s
);
1732 /* This function is called once, at assembler startup time. It should set up
1733 all the tables, etc. that the MD part of the assembler will need. */
1738 const char *retval
= NULL
;
1742 if (mips_pic
!= NO_PIC
)
1744 if (g_switch_seen
&& g_switch_value
!= 0)
1745 as_bad (_("-G may not be used in position-independent code"));
1749 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1750 as_warn (_("Could not set architecture and machine"));
1752 op_hash
= hash_new ();
1754 for (i
= 0; i
< NUMOPCODES
;)
1756 const char *name
= mips_opcodes
[i
].name
;
1758 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1761 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1762 mips_opcodes
[i
].name
, retval
);
1763 /* Probably a memory allocation problem? Give up now. */
1764 as_fatal (_("Broken assembler. No assembly attempted."));
1768 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1770 if (!validate_mips_insn (&mips_opcodes
[i
]))
1772 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1774 create_insn (&nop_insn
, mips_opcodes
+ i
);
1775 nop_insn
.fixed_p
= 1;
1780 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1783 mips16_op_hash
= hash_new ();
1786 while (i
< bfd_mips16_num_opcodes
)
1788 const char *name
= mips16_opcodes
[i
].name
;
1790 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1792 as_fatal (_("internal: can't hash `%s': %s"),
1793 mips16_opcodes
[i
].name
, retval
);
1796 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1797 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1798 != mips16_opcodes
[i
].match
))
1800 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1801 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1804 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1806 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1807 mips16_nop_insn
.fixed_p
= 1;
1811 while (i
< bfd_mips16_num_opcodes
1812 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1816 as_fatal (_("Broken assembler. No assembly attempted."));
1818 /* We add all the general register names to the symbol table. This
1819 helps us detect invalid uses of them. */
1820 for (i
= 0; reg_names
[i
].name
; i
++)
1821 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1822 reg_names
[i
].num
, // & RNUM_MASK,
1823 &zero_address_frag
));
1825 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1826 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1827 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1828 &zero_address_frag
));
1830 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1831 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1832 reg_names_o32
[i
].num
, // & RNUM_MASK,
1833 &zero_address_frag
));
1835 mips_no_prev_insn ();
1838 mips_cprmask
[0] = 0;
1839 mips_cprmask
[1] = 0;
1840 mips_cprmask
[2] = 0;
1841 mips_cprmask
[3] = 0;
1843 /* set the default alignment for the text section (2**2) */
1844 record_alignment (text_section
, 2);
1846 bfd_set_gp_size (stdoutput
, g_switch_value
);
1851 /* On a native system other than VxWorks, sections must be aligned
1852 to 16 byte boundaries. When configured for an embedded ELF
1853 target, we don't bother. */
1854 if (strcmp (TARGET_OS
, "elf") != 0
1855 && strcmp (TARGET_OS
, "vxworks") != 0)
1857 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1858 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1859 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1862 /* Create a .reginfo section for register masks and a .mdebug
1863 section for debugging information. */
1871 subseg
= now_subseg
;
1873 /* The ABI says this section should be loaded so that the
1874 running program can access it. However, we don't load it
1875 if we are configured for an embedded target */
1876 flags
= SEC_READONLY
| SEC_DATA
;
1877 if (strcmp (TARGET_OS
, "elf") != 0)
1878 flags
|= SEC_ALLOC
| SEC_LOAD
;
1880 if (mips_abi
!= N64_ABI
)
1882 sec
= subseg_new (".reginfo", (subsegT
) 0);
1884 bfd_set_section_flags (stdoutput
, sec
, flags
);
1885 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1887 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1891 /* The 64-bit ABI uses a .MIPS.options section rather than
1892 .reginfo section. */
1893 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1894 bfd_set_section_flags (stdoutput
, sec
, flags
);
1895 bfd_set_section_alignment (stdoutput
, sec
, 3);
1897 /* Set up the option header. */
1899 Elf_Internal_Options opthdr
;
1902 opthdr
.kind
= ODK_REGINFO
;
1903 opthdr
.size
= (sizeof (Elf_External_Options
)
1904 + sizeof (Elf64_External_RegInfo
));
1907 f
= frag_more (sizeof (Elf_External_Options
));
1908 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1909 (Elf_External_Options
*) f
);
1911 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1915 if (ECOFF_DEBUGGING
)
1917 sec
= subseg_new (".mdebug", (subsegT
) 0);
1918 (void) bfd_set_section_flags (stdoutput
, sec
,
1919 SEC_HAS_CONTENTS
| SEC_READONLY
);
1920 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1922 else if (mips_flag_pdr
)
1924 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1925 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1926 SEC_READONLY
| SEC_RELOC
1928 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1931 subseg_set (seg
, subseg
);
1934 #endif /* OBJ_ELF */
1936 if (! ECOFF_DEBUGGING
)
1939 if (mips_fix_vr4120
)
1940 init_vr4120_conflicts ();
1946 if (! ECOFF_DEBUGGING
)
1951 md_assemble (char *str
)
1953 struct mips_cl_insn insn
;
1954 bfd_reloc_code_real_type unused_reloc
[3]
1955 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1957 imm_expr
.X_op
= O_absent
;
1958 imm2_expr
.X_op
= O_absent
;
1959 offset_expr
.X_op
= O_absent
;
1960 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1961 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1962 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1963 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1964 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1965 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1967 if (mips_opts
.mips16
)
1968 mips16_ip (str
, &insn
);
1971 mips_ip (str
, &insn
);
1972 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1973 str
, insn
.insn_opcode
));
1978 as_bad ("%s `%s'", insn_error
, str
);
1982 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1985 if (mips_opts
.mips16
)
1986 mips16_macro (&insn
);
1993 if (imm_expr
.X_op
!= O_absent
)
1994 append_insn (&insn
, &imm_expr
, imm_reloc
);
1995 else if (offset_expr
.X_op
!= O_absent
)
1996 append_insn (&insn
, &offset_expr
, offset_reloc
);
1998 append_insn (&insn
, NULL
, unused_reloc
);
2002 /* Return true if the given relocation might need a matching %lo().
2003 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2004 need a matching %lo() when applied to local symbols. */
2006 static inline bfd_boolean
2007 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2009 return (HAVE_IN_PLACE_ADDENDS
2010 && (reloc
== BFD_RELOC_HI16_S
2011 || reloc
== BFD_RELOC_MIPS16_HI16_S
2012 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2013 all GOT16 relocations evaluate to "G". */
2014 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
2017 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2020 static inline bfd_boolean
2021 fixup_has_matching_lo_p (fixS
*fixp
)
2023 return (fixp
->fx_next
!= NULL
2024 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2025 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2026 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2027 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2030 /* See whether instruction IP reads register REG. CLASS is the type
2034 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2035 enum mips_regclass
class)
2037 if (class == MIPS16_REG
)
2039 assert (mips_opts
.mips16
);
2040 reg
= mips16_to_32_reg_map
[reg
];
2041 class = MIPS_GR_REG
;
2044 /* Don't report on general register ZERO, since it never changes. */
2045 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2048 if (class == MIPS_FP_REG
)
2050 assert (! mips_opts
.mips16
);
2051 /* If we are called with either $f0 or $f1, we must check $f0.
2052 This is not optimal, because it will introduce an unnecessary
2053 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2054 need to distinguish reading both $f0 and $f1 or just one of
2055 them. Note that we don't have to check the other way,
2056 because there is no instruction that sets both $f0 and $f1
2057 and requires a delay. */
2058 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2059 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2060 == (reg
&~ (unsigned) 1)))
2062 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2063 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2064 == (reg
&~ (unsigned) 1)))
2067 else if (! mips_opts
.mips16
)
2069 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2070 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2072 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2073 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2078 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2079 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2081 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2082 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2084 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2085 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2088 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2090 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2092 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2094 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2095 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2102 /* This function returns true if modifying a register requires a
2106 reg_needs_delay (unsigned int reg
)
2108 unsigned long prev_pinfo
;
2110 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2111 if (! mips_opts
.noreorder
2112 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2113 && ! gpr_interlocks
)
2114 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2115 && ! cop_interlocks
)))
2117 /* A load from a coprocessor or from memory. All load delays
2118 delay the use of general register rt for one instruction. */
2119 /* Itbl support may require additional care here. */
2120 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2121 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2128 /* Move all labels in insn_labels to the current insertion point. */
2131 mips_move_labels (void)
2133 segment_info_type
*si
= seg_info (now_seg
);
2134 struct insn_label_list
*l
;
2137 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2139 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2140 symbol_set_frag (l
->label
, frag_now
);
2141 val
= (valueT
) frag_now_fix ();
2142 /* mips16 text labels are stored as odd. */
2143 if (mips_opts
.mips16
)
2145 S_SET_VALUE (l
->label
, val
);
2150 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2152 bfd_boolean linkonce
= FALSE
;
2153 segT symseg
= S_GET_SEGMENT (sym
);
2155 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2157 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2160 /* The GNU toolchain uses an extension for ELF: a section
2161 beginning with the magic string .gnu.linkonce is a
2162 linkonce section. */
2163 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2164 sizeof ".gnu.linkonce" - 1) == 0)
2171 /* Mark instruction labels in mips16 mode. This permits the linker to
2172 handle them specially, such as generating jalx instructions when
2173 needed. We also make them odd for the duration of the assembly, in
2174 order to generate the right sort of code. We will make them even
2175 in the adjust_symtab routine, while leaving them marked. This is
2176 convenient for the debugger and the disassembler. The linker knows
2177 to make them odd again. */
2180 mips16_mark_labels (void)
2182 segment_info_type
*si
= seg_info (now_seg
);
2183 struct insn_label_list
*l
;
2185 if (!mips_opts
.mips16
)
2188 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2190 symbolS
*label
= l
->label
;
2192 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2194 S_SET_OTHER (label
, STO_MIPS16
);
2196 if ((S_GET_VALUE (label
) & 1) == 0
2197 /* Don't adjust the address if the label is global or weak, or
2198 in a link-once section, since we'll be emitting symbol reloc
2199 references to it which will be patched up by the linker, and
2200 the final value of the symbol may or may not be MIPS16. */
2201 && ! S_IS_WEAK (label
)
2202 && ! S_IS_EXTERNAL (label
)
2203 && ! s_is_linkonce (label
, now_seg
))
2204 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2208 /* End the current frag. Make it a variant frag and record the
2212 relax_close_frag (void)
2214 mips_macro_warning
.first_frag
= frag_now
;
2215 frag_var (rs_machine_dependent
, 0, 0,
2216 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2217 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2219 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2220 mips_relax
.first_fixup
= 0;
2223 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2224 See the comment above RELAX_ENCODE for more details. */
2227 relax_start (symbolS
*symbol
)
2229 assert (mips_relax
.sequence
== 0);
2230 mips_relax
.sequence
= 1;
2231 mips_relax
.symbol
= symbol
;
2234 /* Start generating the second version of a relaxable sequence.
2235 See the comment above RELAX_ENCODE for more details. */
2240 assert (mips_relax
.sequence
== 1);
2241 mips_relax
.sequence
= 2;
2244 /* End the current relaxable sequence. */
2249 assert (mips_relax
.sequence
== 2);
2250 relax_close_frag ();
2251 mips_relax
.sequence
= 0;
2254 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2255 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2256 by VR4120 errata. */
2259 classify_vr4120_insn (const char *name
)
2261 if (strncmp (name
, "macc", 4) == 0)
2262 return FIX_VR4120_MACC
;
2263 if (strncmp (name
, "dmacc", 5) == 0)
2264 return FIX_VR4120_DMACC
;
2265 if (strncmp (name
, "mult", 4) == 0)
2266 return FIX_VR4120_MULT
;
2267 if (strncmp (name
, "dmult", 5) == 0)
2268 return FIX_VR4120_DMULT
;
2269 if (strstr (name
, "div"))
2270 return FIX_VR4120_DIV
;
2271 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2272 return FIX_VR4120_MTHILO
;
2273 return NUM_FIX_VR4120_CLASSES
;
2276 /* Return the number of instructions that must separate INSN1 and INSN2,
2277 where INSN1 is the earlier instruction. Return the worst-case value
2278 for any INSN2 if INSN2 is null. */
2281 insns_between (const struct mips_cl_insn
*insn1
,
2282 const struct mips_cl_insn
*insn2
)
2284 unsigned long pinfo1
, pinfo2
;
2286 /* This function needs to know which pinfo flags are set for INSN2
2287 and which registers INSN2 uses. The former is stored in PINFO2 and
2288 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2289 will have every flag set and INSN2_USES_REG will always return true. */
2290 pinfo1
= insn1
->insn_mo
->pinfo
;
2291 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2293 #define INSN2_USES_REG(REG, CLASS) \
2294 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2296 /* For most targets, write-after-read dependencies on the HI and LO
2297 registers must be separated by at least two instructions. */
2298 if (!hilo_interlocks
)
2300 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2302 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2306 /* If we're working around r7000 errata, there must be two instructions
2307 between an mfhi or mflo and any instruction that uses the result. */
2308 if (mips_7000_hilo_fix
2309 && MF_HILO_INSN (pinfo1
)
2310 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2313 /* If working around VR4120 errata, check for combinations that need
2314 a single intervening instruction. */
2315 if (mips_fix_vr4120
)
2317 unsigned int class1
, class2
;
2319 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2320 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2324 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2325 if (vr4120_conflicts
[class1
] & (1 << class2
))
2330 if (!mips_opts
.mips16
)
2332 /* Check for GPR or coprocessor load delays. All such delays
2333 are on the RT register. */
2334 /* Itbl support may require additional care here. */
2335 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2336 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2338 know (pinfo1
& INSN_WRITE_GPR_T
);
2339 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2343 /* Check for generic coprocessor hazards.
2345 This case is not handled very well. There is no special
2346 knowledge of CP0 handling, and the coprocessors other than
2347 the floating point unit are not distinguished at all. */
2348 /* Itbl support may require additional care here. FIXME!
2349 Need to modify this to include knowledge about
2350 user specified delays! */
2351 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2352 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2354 /* Handle cases where INSN1 writes to a known general coprocessor
2355 register. There must be a one instruction delay before INSN2
2356 if INSN2 reads that register, otherwise no delay is needed. */
2357 if (pinfo1
& INSN_WRITE_FPR_T
)
2359 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2362 else if (pinfo1
& INSN_WRITE_FPR_S
)
2364 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2369 /* Read-after-write dependencies on the control registers
2370 require a two-instruction gap. */
2371 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2372 && (pinfo2
& INSN_READ_COND_CODE
))
2375 /* We don't know exactly what INSN1 does. If INSN2 is
2376 also a coprocessor instruction, assume there must be
2377 a one instruction gap. */
2378 if (pinfo2
& INSN_COP
)
2383 /* Check for read-after-write dependencies on the coprocessor
2384 control registers in cases where INSN1 does not need a general
2385 coprocessor delay. This means that INSN1 is a floating point
2386 comparison instruction. */
2387 /* Itbl support may require additional care here. */
2388 else if (!cop_interlocks
2389 && (pinfo1
& INSN_WRITE_COND_CODE
)
2390 && (pinfo2
& INSN_READ_COND_CODE
))
2394 #undef INSN2_USES_REG
2399 /* Return the number of nops that would be needed to work around the
2400 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2401 the MAX_VR4130_NOPS instructions described by HISTORY. */
2404 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2405 const struct mips_cl_insn
*insn
)
2409 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2410 are not affected by the errata. */
2412 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2413 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2414 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2417 /* Search for the first MFLO or MFHI. */
2418 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2419 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2421 /* Extract the destination register. */
2422 if (mips_opts
.mips16
)
2423 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2425 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2427 /* No nops are needed if INSN reads that register. */
2428 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2431 /* ...or if any of the intervening instructions do. */
2432 for (j
= 0; j
< i
; j
++)
2433 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2436 return MAX_VR4130_NOPS
- i
;
2441 /* Return the number of nops that would be needed if instruction INSN
2442 immediately followed the MAX_NOPS instructions given by HISTORY,
2443 where HISTORY[0] is the most recent instruction. If INSN is null,
2444 return the worse-case number of nops for any instruction. */
2447 nops_for_insn (const struct mips_cl_insn
*history
,
2448 const struct mips_cl_insn
*insn
)
2450 int i
, nops
, tmp_nops
;
2453 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2454 if (!history
[i
].noreorder_p
)
2456 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2457 if (tmp_nops
> nops
)
2461 if (mips_fix_vr4130
)
2463 tmp_nops
= nops_for_vr4130 (history
, insn
);
2464 if (tmp_nops
> nops
)
2471 /* The variable arguments provide NUM_INSNS extra instructions that
2472 might be added to HISTORY. Return the largest number of nops that
2473 would be needed after the extended sequence. */
2476 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2479 struct mips_cl_insn buffer
[MAX_NOPS
];
2480 struct mips_cl_insn
*cursor
;
2483 va_start (args
, history
);
2484 cursor
= buffer
+ num_insns
;
2485 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2486 while (cursor
> buffer
)
2487 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2489 nops
= nops_for_insn (buffer
, NULL
);
2494 /* Like nops_for_insn, but if INSN is a branch, take into account the
2495 worst-case delay for the branch target. */
2498 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2499 const struct mips_cl_insn
*insn
)
2503 nops
= nops_for_insn (history
, insn
);
2504 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2505 | INSN_COND_BRANCH_DELAY
2506 | INSN_COND_BRANCH_LIKELY
))
2508 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2509 if (tmp_nops
> nops
)
2512 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2514 tmp_nops
= nops_for_sequence (1, history
, insn
);
2515 if (tmp_nops
> nops
)
2521 /* Output an instruction. IP is the instruction information.
2522 ADDRESS_EXPR is an operand of the instruction to be used with
2526 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2527 bfd_reloc_code_real_type
*reloc_type
)
2529 unsigned long prev_pinfo
, pinfo
;
2530 relax_stateT prev_insn_frag_type
= 0;
2531 bfd_boolean relaxed_branch
= FALSE
;
2532 segment_info_type
*si
= seg_info (now_seg
);
2534 /* Mark instruction labels in mips16 mode. */
2535 mips16_mark_labels ();
2537 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2538 pinfo
= ip
->insn_mo
->pinfo
;
2540 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2542 /* There are a lot of optimizations we could do that we don't.
2543 In particular, we do not, in general, reorder instructions.
2544 If you use gcc with optimization, it will reorder
2545 instructions and generally do much more optimization then we
2546 do here; repeating all that work in the assembler would only
2547 benefit hand written assembly code, and does not seem worth
2549 int nops
= (mips_optimize
== 0
2550 ? nops_for_insn (history
, NULL
)
2551 : nops_for_insn_or_target (history
, ip
));
2555 unsigned long old_frag_offset
;
2558 old_frag
= frag_now
;
2559 old_frag_offset
= frag_now_fix ();
2561 for (i
= 0; i
< nops
; i
++)
2566 listing_prev_line ();
2567 /* We may be at the start of a variant frag. In case we
2568 are, make sure there is enough space for the frag
2569 after the frags created by listing_prev_line. The
2570 argument to frag_grow here must be at least as large
2571 as the argument to all other calls to frag_grow in
2572 this file. We don't have to worry about being in the
2573 middle of a variant frag, because the variants insert
2574 all needed nop instructions themselves. */
2578 mips_move_labels ();
2580 #ifndef NO_ECOFF_DEBUGGING
2581 if (ECOFF_DEBUGGING
)
2582 ecoff_fix_loc (old_frag
, old_frag_offset
);
2586 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2588 /* Work out how many nops in prev_nop_frag are needed by IP. */
2589 int nops
= nops_for_insn_or_target (history
, ip
);
2590 assert (nops
<= prev_nop_frag_holds
);
2592 /* Enforce NOPS as a minimum. */
2593 if (nops
> prev_nop_frag_required
)
2594 prev_nop_frag_required
= nops
;
2596 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2598 /* Settle for the current number of nops. Update the history
2599 accordingly (for the benefit of any future .set reorder code). */
2600 prev_nop_frag
= NULL
;
2601 insert_into_history (prev_nop_frag_since
,
2602 prev_nop_frag_holds
, NOP_INSN
);
2606 /* Allow this instruction to replace one of the nops that was
2607 tentatively added to prev_nop_frag. */
2608 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2609 prev_nop_frag_holds
--;
2610 prev_nop_frag_since
++;
2615 /* The value passed to dwarf2_emit_insn is the distance between
2616 the beginning of the current instruction and the address that
2617 should be recorded in the debug tables. For MIPS16 debug info
2618 we want to use ISA-encoded addresses, so we pass -1 for an
2619 address higher by one than the current. */
2620 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2623 /* Record the frag type before frag_var. */
2624 if (history
[0].frag
)
2625 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2628 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2629 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2630 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2631 && mips_relax_branch
2632 /* Don't try branch relaxation within .set nomacro, or within
2633 .set noat if we use $at for PIC computations. If it turns
2634 out that the branch was out-of-range, we'll get an error. */
2635 && !mips_opts
.warn_about_macros
2636 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2637 && !mips_opts
.mips16
)
2639 relaxed_branch
= TRUE
;
2640 add_relaxed_insn (ip
, (relaxed_branch_length
2642 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2643 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2646 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2647 pinfo
& INSN_COND_BRANCH_LIKELY
,
2648 pinfo
& INSN_WRITE_GPR_31
,
2650 address_expr
->X_add_symbol
,
2651 address_expr
->X_add_number
);
2652 *reloc_type
= BFD_RELOC_UNUSED
;
2654 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2656 /* We need to set up a variant frag. */
2657 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2658 add_relaxed_insn (ip
, 4, 0,
2660 (*reloc_type
- BFD_RELOC_UNUSED
,
2661 mips16_small
, mips16_ext
,
2662 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2663 history
[0].mips16_absolute_jump_p
),
2664 make_expr_symbol (address_expr
), 0);
2666 else if (mips_opts
.mips16
2668 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2670 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2671 /* Make sure there is enough room to swap this instruction with
2672 a following jump instruction. */
2674 add_fixed_insn (ip
);
2678 if (mips_opts
.mips16
2679 && mips_opts
.noreorder
2680 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2681 as_warn (_("extended instruction in delay slot"));
2683 if (mips_relax
.sequence
)
2685 /* If we've reached the end of this frag, turn it into a variant
2686 frag and record the information for the instructions we've
2688 if (frag_room () < 4)
2689 relax_close_frag ();
2690 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2693 if (mips_relax
.sequence
!= 2)
2694 mips_macro_warning
.sizes
[0] += 4;
2695 if (mips_relax
.sequence
!= 1)
2696 mips_macro_warning
.sizes
[1] += 4;
2698 if (mips_opts
.mips16
)
2701 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2703 add_fixed_insn (ip
);
2706 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2708 if (address_expr
->X_op
== O_constant
)
2712 switch (*reloc_type
)
2715 ip
->insn_opcode
|= address_expr
->X_add_number
;
2718 case BFD_RELOC_MIPS_HIGHEST
:
2719 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2720 ip
->insn_opcode
|= tmp
& 0xffff;
2723 case BFD_RELOC_MIPS_HIGHER
:
2724 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2725 ip
->insn_opcode
|= tmp
& 0xffff;
2728 case BFD_RELOC_HI16_S
:
2729 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2730 ip
->insn_opcode
|= tmp
& 0xffff;
2733 case BFD_RELOC_HI16
:
2734 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2737 case BFD_RELOC_UNUSED
:
2738 case BFD_RELOC_LO16
:
2739 case BFD_RELOC_MIPS_GOT_DISP
:
2740 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2743 case BFD_RELOC_MIPS_JMP
:
2744 if ((address_expr
->X_add_number
& 3) != 0)
2745 as_bad (_("jump to misaligned address (0x%lx)"),
2746 (unsigned long) address_expr
->X_add_number
);
2747 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2750 case BFD_RELOC_MIPS16_JMP
:
2751 if ((address_expr
->X_add_number
& 3) != 0)
2752 as_bad (_("jump to misaligned address (0x%lx)"),
2753 (unsigned long) address_expr
->X_add_number
);
2755 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2756 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2757 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2760 case BFD_RELOC_16_PCREL_S2
:
2761 if ((address_expr
->X_add_number
& 3) != 0)
2762 as_bad (_("branch to misaligned address (0x%lx)"),
2763 (unsigned long) address_expr
->X_add_number
);
2764 if (mips_relax_branch
)
2766 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2767 as_bad (_("branch address range overflow (0x%lx)"),
2768 (unsigned long) address_expr
->X_add_number
);
2769 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2776 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2779 reloc_howto_type
*howto
;
2782 /* In a compound relocation, it is the final (outermost)
2783 operator that determines the relocated field. */
2784 for (i
= 1; i
< 3; i
++)
2785 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2788 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2789 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2790 bfd_get_reloc_size (howto
),
2792 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2795 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2796 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2797 && ip
->fixp
[0]->fx_addsy
)
2798 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2800 /* These relocations can have an addend that won't fit in
2801 4 octets for 64bit assembly. */
2803 && ! howto
->partial_inplace
2804 && (reloc_type
[0] == BFD_RELOC_16
2805 || reloc_type
[0] == BFD_RELOC_32
2806 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2807 || reloc_type
[0] == BFD_RELOC_HI16_S
2808 || reloc_type
[0] == BFD_RELOC_LO16
2809 || reloc_type
[0] == BFD_RELOC_GPREL16
2810 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2811 || reloc_type
[0] == BFD_RELOC_GPREL32
2812 || reloc_type
[0] == BFD_RELOC_64
2813 || reloc_type
[0] == BFD_RELOC_CTOR
2814 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2815 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2816 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2817 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2818 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2819 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2820 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2821 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2822 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2823 ip
->fixp
[0]->fx_no_overflow
= 1;
2825 if (mips_relax
.sequence
)
2827 if (mips_relax
.first_fixup
== 0)
2828 mips_relax
.first_fixup
= ip
->fixp
[0];
2830 else if (reloc_needs_lo_p (*reloc_type
))
2832 struct mips_hi_fixup
*hi_fixup
;
2834 /* Reuse the last entry if it already has a matching %lo. */
2835 hi_fixup
= mips_hi_fixup_list
;
2837 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2839 hi_fixup
= ((struct mips_hi_fixup
*)
2840 xmalloc (sizeof (struct mips_hi_fixup
)));
2841 hi_fixup
->next
= mips_hi_fixup_list
;
2842 mips_hi_fixup_list
= hi_fixup
;
2844 hi_fixup
->fixp
= ip
->fixp
[0];
2845 hi_fixup
->seg
= now_seg
;
2848 /* Add fixups for the second and third relocations, if given.
2849 Note that the ABI allows the second relocation to be
2850 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2851 moment we only use RSS_UNDEF, but we could add support
2852 for the others if it ever becomes necessary. */
2853 for (i
= 1; i
< 3; i
++)
2854 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2856 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2857 ip
->fixp
[0]->fx_size
, NULL
, 0,
2858 FALSE
, reloc_type
[i
]);
2860 /* Use fx_tcbit to mark compound relocs. */
2861 ip
->fixp
[0]->fx_tcbit
= 1;
2862 ip
->fixp
[i
]->fx_tcbit
= 1;
2868 /* Update the register mask information. */
2869 if (! mips_opts
.mips16
)
2871 if (pinfo
& INSN_WRITE_GPR_D
)
2872 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2873 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2874 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2875 if (pinfo
& INSN_READ_GPR_S
)
2876 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2877 if (pinfo
& INSN_WRITE_GPR_31
)
2878 mips_gprmask
|= 1 << RA
;
2879 if (pinfo
& INSN_WRITE_FPR_D
)
2880 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2881 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2882 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2883 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2884 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2885 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2886 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2887 if (pinfo
& INSN_COP
)
2889 /* We don't keep enough information to sort these cases out.
2890 The itbl support does keep this information however, although
2891 we currently don't support itbl fprmats as part of the cop
2892 instruction. May want to add this support in the future. */
2894 /* Never set the bit for $0, which is always zero. */
2895 mips_gprmask
&= ~1 << 0;
2899 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2900 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2901 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2902 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2903 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2904 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2905 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2906 mips_gprmask
|= 1 << TREG
;
2907 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2908 mips_gprmask
|= 1 << SP
;
2909 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2910 mips_gprmask
|= 1 << RA
;
2911 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2912 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2913 if (pinfo
& MIPS16_INSN_READ_Z
)
2914 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2915 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2916 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2919 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2921 /* Filling the branch delay slot is more complex. We try to
2922 switch the branch with the previous instruction, which we can
2923 do if the previous instruction does not set up a condition
2924 that the branch tests and if the branch is not itself the
2925 target of any branch. */
2926 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2927 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2929 if (mips_optimize
< 2
2930 /* If we have seen .set volatile or .set nomove, don't
2932 || mips_opts
.nomove
!= 0
2933 /* We can't swap if the previous instruction's position
2935 || history
[0].fixed_p
2936 /* If the previous previous insn was in a .set
2937 noreorder, we can't swap. Actually, the MIPS
2938 assembler will swap in this situation. However, gcc
2939 configured -with-gnu-as will generate code like
2945 in which we can not swap the bne and INSN. If gcc is
2946 not configured -with-gnu-as, it does not output the
2948 || history
[1].noreorder_p
2949 /* If the branch is itself the target of a branch, we
2950 can not swap. We cheat on this; all we check for is
2951 whether there is a label on this instruction. If
2952 there are any branches to anything other than a
2953 label, users must use .set noreorder. */
2954 || si
->label_list
!= NULL
2955 /* If the previous instruction is in a variant frag
2956 other than this branch's one, we cannot do the swap.
2957 This does not apply to the mips16, which uses variant
2958 frags for different purposes. */
2959 || (! mips_opts
.mips16
2960 && prev_insn_frag_type
== rs_machine_dependent
)
2961 /* Check for conflicts between the branch and the instructions
2962 before the candidate delay slot. */
2963 || nops_for_insn (history
+ 1, ip
) > 0
2964 /* Check for conflicts between the swapped sequence and the
2965 target of the branch. */
2966 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2967 /* We do not swap with a trap instruction, since it
2968 complicates trap handlers to have the trap
2969 instruction be in a delay slot. */
2970 || (prev_pinfo
& INSN_TRAP
)
2971 /* If the branch reads a register that the previous
2972 instruction sets, we can not swap. */
2973 || (! mips_opts
.mips16
2974 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2975 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2977 || (! mips_opts
.mips16
2978 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2979 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2981 || (mips_opts
.mips16
2982 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2984 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2986 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2988 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2990 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2992 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2994 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2995 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2996 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2997 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2998 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2999 && insn_uses_reg (ip
,
3000 MIPS16OP_EXTRACT_REG32R
3001 (history
[0].insn_opcode
),
3003 /* If the branch writes a register that the previous
3004 instruction sets, we can not swap (we know that
3005 branches write only to RD or to $31). */
3006 || (! mips_opts
.mips16
3007 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3008 && (((pinfo
& INSN_WRITE_GPR_D
)
3009 && (EXTRACT_OPERAND (RT
, history
[0])
3010 == EXTRACT_OPERAND (RD
, *ip
)))
3011 || ((pinfo
& INSN_WRITE_GPR_31
)
3012 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3013 || (! mips_opts
.mips16
3014 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3015 && (((pinfo
& INSN_WRITE_GPR_D
)
3016 && (EXTRACT_OPERAND (RD
, history
[0])
3017 == EXTRACT_OPERAND (RD
, *ip
)))
3018 || ((pinfo
& INSN_WRITE_GPR_31
)
3019 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3020 || (mips_opts
.mips16
3021 && (pinfo
& MIPS16_INSN_WRITE_31
)
3022 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3023 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3024 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3026 /* If the branch writes a register that the previous
3027 instruction reads, we can not swap (we know that
3028 branches only write to RD or to $31). */
3029 || (! mips_opts
.mips16
3030 && (pinfo
& INSN_WRITE_GPR_D
)
3031 && insn_uses_reg (&history
[0],
3032 EXTRACT_OPERAND (RD
, *ip
),
3034 || (! mips_opts
.mips16
3035 && (pinfo
& INSN_WRITE_GPR_31
)
3036 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3037 || (mips_opts
.mips16
3038 && (pinfo
& MIPS16_INSN_WRITE_31
)
3039 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3040 /* If one instruction sets a condition code and the
3041 other one uses a condition code, we can not swap. */
3042 || ((pinfo
& INSN_READ_COND_CODE
)
3043 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3044 || ((pinfo
& INSN_WRITE_COND_CODE
)
3045 && (prev_pinfo
& INSN_READ_COND_CODE
))
3046 /* If the previous instruction uses the PC, we can not
3048 || (mips_opts
.mips16
3049 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3050 /* If the previous instruction had a fixup in mips16
3051 mode, we can not swap. This normally means that the
3052 previous instruction was a 4 byte branch anyhow. */
3053 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3054 /* If the previous instruction is a sync, sync.l, or
3055 sync.p, we can not swap. */
3056 || (prev_pinfo
& INSN_SYNC
))
3058 if (mips_opts
.mips16
3059 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3060 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3061 && ISA_SUPPORTS_MIPS16E
)
3063 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3064 ip
->insn_opcode
|= 0x0080;
3066 insert_into_history (0, 1, ip
);
3070 /* We could do even better for unconditional branches to
3071 portions of this object file; we could pick up the
3072 instruction at the destination, put it in the delay
3073 slot, and bump the destination address. */
3074 insert_into_history (0, 1, ip
);
3078 if (mips_relax
.sequence
)
3079 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3083 /* It looks like we can actually do the swap. */
3084 struct mips_cl_insn delay
= history
[0];
3085 if (mips_opts
.mips16
)
3087 know (delay
.frag
== ip
->frag
);
3088 move_insn (ip
, delay
.frag
, delay
.where
);
3089 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3091 else if (relaxed_branch
)
3093 /* Add the delay slot instruction to the end of the
3094 current frag and shrink the fixed part of the
3095 original frag. If the branch occupies the tail of
3096 the latter, move it backwards to cover the gap. */
3097 delay
.frag
->fr_fix
-= 4;
3098 if (delay
.frag
== ip
->frag
)
3099 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3100 add_fixed_insn (&delay
);
3104 move_insn (&delay
, ip
->frag
, ip
->where
);
3105 move_insn (ip
, history
[0].frag
, history
[0].where
);
3109 insert_into_history (0, 1, &delay
);
3112 /* If that was an unconditional branch, forget the previous
3113 insn information. */
3114 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3115 mips_no_prev_insn ();
3117 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3119 /* We don't yet optimize a branch likely. What we should do
3120 is look at the target, copy the instruction found there
3121 into the delay slot, and increment the branch to jump to
3122 the next instruction. */
3123 insert_into_history (0, 1, ip
);
3127 insert_into_history (0, 1, ip
);
3130 insert_into_history (0, 1, ip
);
3132 /* We just output an insn, so the next one doesn't have a label. */
3133 mips_clear_insn_labels ();
3136 /* Forget that there was any previous instruction or label. */
3139 mips_no_prev_insn (void)
3141 prev_nop_frag
= NULL
;
3142 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3143 mips_clear_insn_labels ();
3146 /* This function must be called before we emit something other than
3147 instructions. It is like mips_no_prev_insn except that it inserts
3148 any NOPS that might be needed by previous instructions. */
3151 mips_emit_delays (void)
3153 if (! mips_opts
.noreorder
)
3155 int nops
= nops_for_insn (history
, NULL
);
3159 add_fixed_insn (NOP_INSN
);
3160 mips_move_labels ();
3163 mips_no_prev_insn ();
3166 /* Start a (possibly nested) noreorder block. */
3169 start_noreorder (void)
3171 if (mips_opts
.noreorder
== 0)
3176 /* None of the instructions before the .set noreorder can be moved. */
3177 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3178 history
[i
].fixed_p
= 1;
3180 /* Insert any nops that might be needed between the .set noreorder
3181 block and the previous instructions. We will later remove any
3182 nops that turn out not to be needed. */
3183 nops
= nops_for_insn (history
, NULL
);
3186 if (mips_optimize
!= 0)
3188 /* Record the frag which holds the nop instructions, so
3189 that we can remove them if we don't need them. */
3190 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3191 prev_nop_frag
= frag_now
;
3192 prev_nop_frag_holds
= nops
;
3193 prev_nop_frag_required
= 0;
3194 prev_nop_frag_since
= 0;
3197 for (; nops
> 0; --nops
)
3198 add_fixed_insn (NOP_INSN
);
3200 /* Move on to a new frag, so that it is safe to simply
3201 decrease the size of prev_nop_frag. */
3202 frag_wane (frag_now
);
3204 mips_move_labels ();
3206 mips16_mark_labels ();
3207 mips_clear_insn_labels ();
3209 mips_opts
.noreorder
++;
3210 mips_any_noreorder
= 1;
3213 /* End a nested noreorder block. */
3216 end_noreorder (void)
3218 mips_opts
.noreorder
--;
3219 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3221 /* Commit to inserting prev_nop_frag_required nops and go back to
3222 handling nop insertion the .set reorder way. */
3223 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3224 * (mips_opts
.mips16
? 2 : 4));
3225 insert_into_history (prev_nop_frag_since
,
3226 prev_nop_frag_required
, NOP_INSN
);
3227 prev_nop_frag
= NULL
;
3231 /* Set up global variables for the start of a new macro. */
3236 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3237 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3238 && (history
[0].insn_mo
->pinfo
3239 & (INSN_UNCOND_BRANCH_DELAY
3240 | INSN_COND_BRANCH_DELAY
3241 | INSN_COND_BRANCH_LIKELY
)) != 0);
3244 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3245 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3246 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3249 macro_warning (relax_substateT subtype
)
3251 if (subtype
& RELAX_DELAY_SLOT
)
3252 return _("Macro instruction expanded into multiple instructions"
3253 " in a branch delay slot");
3254 else if (subtype
& RELAX_NOMACRO
)
3255 return _("Macro instruction expanded into multiple instructions");
3260 /* Finish up a macro. Emit warnings as appropriate. */
3265 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3267 relax_substateT subtype
;
3269 /* Set up the relaxation warning flags. */
3271 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3272 subtype
|= RELAX_SECOND_LONGER
;
3273 if (mips_opts
.warn_about_macros
)
3274 subtype
|= RELAX_NOMACRO
;
3275 if (mips_macro_warning
.delay_slot_p
)
3276 subtype
|= RELAX_DELAY_SLOT
;
3278 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3280 /* Either the macro has a single implementation or both
3281 implementations are longer than 4 bytes. Emit the
3283 const char *msg
= macro_warning (subtype
);
3289 /* One implementation might need a warning but the other
3290 definitely doesn't. */
3291 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3296 /* Read a macro's relocation codes from *ARGS and store them in *R.
3297 The first argument in *ARGS will be either the code for a single
3298 relocation or -1 followed by the three codes that make up a
3299 composite relocation. */
3302 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3306 next
= va_arg (*args
, int);
3308 r
[0] = (bfd_reloc_code_real_type
) next
;
3310 for (i
= 0; i
< 3; i
++)
3311 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3314 /* Build an instruction created by a macro expansion. This is passed
3315 a pointer to the count of instructions created so far, an
3316 expression, the name of the instruction to build, an operand format
3317 string, and corresponding arguments. */
3320 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3322 const struct mips_opcode
*mo
;
3323 struct mips_cl_insn insn
;
3324 bfd_reloc_code_real_type r
[3];
3327 va_start (args
, fmt
);
3329 if (mips_opts
.mips16
)
3331 mips16_macro_build (ep
, name
, fmt
, args
);
3336 r
[0] = BFD_RELOC_UNUSED
;
3337 r
[1] = BFD_RELOC_UNUSED
;
3338 r
[2] = BFD_RELOC_UNUSED
;
3339 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3341 assert (strcmp (name
, mo
->name
) == 0);
3345 /* Search until we get a match for NAME. It is assumed here that
3346 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3347 if (strcmp (fmt
, mo
->args
) == 0
3348 && mo
->pinfo
!= INSN_MACRO
3349 && OPCODE_IS_MEMBER (mo
,
3351 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3352 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
3353 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
3355 | (mips_opts
.ase_dspr2
? INSN_DSPR2
: 0)
3356 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3358 && (mips_opts
.arch
!= CPU_R4650
|| (mo
->pinfo
& FP_D
) == 0))
3363 assert (strcmp (name
, mo
->name
) == 0);
3366 create_insn (&insn
, mo
);
3384 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3389 /* Note that in the macro case, these arguments are already
3390 in MSB form. (When handling the instruction in the
3391 non-macro case, these arguments are sizes from which
3392 MSB values must be calculated.) */
3393 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3399 /* Note that in the macro case, these arguments are already
3400 in MSBD form. (When handling the instruction in the
3401 non-macro case, these arguments are sizes from which
3402 MSBD values must be calculated.) */
3403 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3412 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3418 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3422 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3427 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3433 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3438 int tmp
= va_arg (args
, int);
3440 INSERT_OPERAND (RT
, insn
, tmp
);
3441 INSERT_OPERAND (RD
, insn
, tmp
);
3447 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3454 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3458 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3462 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3466 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3470 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3477 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3483 macro_read_relocs (&args
, r
);
3484 assert (*r
== BFD_RELOC_GPREL16
3485 || *r
== BFD_RELOC_MIPS_LITERAL
3486 || *r
== BFD_RELOC_MIPS_HIGHER
3487 || *r
== BFD_RELOC_HI16_S
3488 || *r
== BFD_RELOC_LO16
3489 || *r
== BFD_RELOC_MIPS_GOT16
3490 || *r
== BFD_RELOC_MIPS_CALL16
3491 || *r
== BFD_RELOC_MIPS_GOT_DISP
3492 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3493 || *r
== BFD_RELOC_MIPS_GOT_OFST
3494 || *r
== BFD_RELOC_MIPS_GOT_LO16
3495 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3499 macro_read_relocs (&args
, r
);
3501 && (ep
->X_op
== O_constant
3502 || (ep
->X_op
== O_symbol
3503 && (*r
== BFD_RELOC_MIPS_HIGHEST
3504 || *r
== BFD_RELOC_HI16_S
3505 || *r
== BFD_RELOC_HI16
3506 || *r
== BFD_RELOC_GPREL16
3507 || *r
== BFD_RELOC_MIPS_GOT_HI16
3508 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3512 assert (ep
!= NULL
);
3515 * This allows macro() to pass an immediate expression for
3516 * creating short branches without creating a symbol.
3518 * We don't allow branch relaxation for these branches, as
3519 * they should only appear in ".set nomacro" anyway.
3521 if (ep
->X_op
== O_constant
)
3523 if ((ep
->X_add_number
& 3) != 0)
3524 as_bad (_("branch to misaligned address (0x%lx)"),
3525 (unsigned long) ep
->X_add_number
);
3526 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3527 as_bad (_("branch address range overflow (0x%lx)"),
3528 (unsigned long) ep
->X_add_number
);
3529 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3533 *r
= BFD_RELOC_16_PCREL_S2
;
3537 assert (ep
!= NULL
);
3538 *r
= BFD_RELOC_MIPS_JMP
;
3542 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3546 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3555 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3557 append_insn (&insn
, ep
, r
);
3561 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3564 struct mips_opcode
*mo
;
3565 struct mips_cl_insn insn
;
3566 bfd_reloc_code_real_type r
[3]
3567 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3569 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3571 assert (strcmp (name
, mo
->name
) == 0);
3573 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3577 assert (strcmp (name
, mo
->name
) == 0);
3580 create_insn (&insn
, mo
);
3598 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3603 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3607 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3611 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3621 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3628 regno
= va_arg (args
, int);
3629 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3630 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3651 assert (ep
!= NULL
);
3653 if (ep
->X_op
!= O_constant
)
3654 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3657 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3658 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3661 *r
= BFD_RELOC_UNUSED
;
3667 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3674 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3676 append_insn (&insn
, ep
, r
);
3680 * Sign-extend 32-bit mode constants that have bit 31 set and all
3681 * higher bits unset.
3684 normalize_constant_expr (expressionS
*ex
)
3686 if (ex
->X_op
== O_constant
3687 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3688 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3693 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3694 * all higher bits unset.
3697 normalize_address_expr (expressionS
*ex
)
3699 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3700 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3701 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3702 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3707 * Generate a "jalr" instruction with a relocation hint to the called
3708 * function. This occurs in NewABI PIC code.
3711 macro_build_jalr (expressionS
*ep
)
3720 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3722 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3723 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3727 * Generate a "lui" instruction.
3730 macro_build_lui (expressionS
*ep
, int regnum
)
3732 expressionS high_expr
;
3733 const struct mips_opcode
*mo
;
3734 struct mips_cl_insn insn
;
3735 bfd_reloc_code_real_type r
[3]
3736 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3737 const char *name
= "lui";
3738 const char *fmt
= "t,u";
3740 assert (! mips_opts
.mips16
);
3744 if (high_expr
.X_op
== O_constant
)
3746 /* We can compute the instruction now without a relocation entry. */
3747 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3749 *r
= BFD_RELOC_UNUSED
;
3753 assert (ep
->X_op
== O_symbol
);
3754 /* _gp_disp is a special case, used from s_cpload.
3755 __gnu_local_gp is used if mips_no_shared. */
3756 assert (mips_pic
== NO_PIC
3758 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3759 || (! mips_in_shared
3760 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3761 "__gnu_local_gp") == 0));
3762 *r
= BFD_RELOC_HI16_S
;
3765 mo
= hash_find (op_hash
, name
);
3766 assert (strcmp (name
, mo
->name
) == 0);
3767 assert (strcmp (fmt
, mo
->args
) == 0);
3768 create_insn (&insn
, mo
);
3770 insn
.insn_opcode
= insn
.insn_mo
->match
;
3771 INSERT_OPERAND (RT
, insn
, regnum
);
3772 if (*r
== BFD_RELOC_UNUSED
)
3774 insn
.insn_opcode
|= high_expr
.X_add_number
;
3775 append_insn (&insn
, NULL
, r
);
3778 append_insn (&insn
, &high_expr
, r
);
3781 /* Generate a sequence of instructions to do a load or store from a constant
3782 offset off of a base register (breg) into/from a target register (treg),
3783 using AT if necessary. */
3785 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3786 int treg
, int breg
, int dbl
)
3788 assert (ep
->X_op
== O_constant
);
3790 /* Sign-extending 32-bit constants makes their handling easier. */
3792 normalize_constant_expr (ep
);
3794 /* Right now, this routine can only handle signed 32-bit constants. */
3795 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3796 as_warn (_("operand overflow"));
3798 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3800 /* Signed 16-bit offset will fit in the op. Easy! */
3801 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3805 /* 32-bit offset, need multiple instructions and AT, like:
3806 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3807 addu $tempreg,$tempreg,$breg
3808 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3809 to handle the complete offset. */
3810 macro_build_lui (ep
, AT
);
3811 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3812 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3815 as_bad (_("Macro used $at after \".set noat\""));
3820 * Generates code to set the $at register to true (one)
3821 * if reg is less than the immediate expression.
3824 set_at (int reg
, int unsignedp
)
3826 if (imm_expr
.X_op
== O_constant
3827 && imm_expr
.X_add_number
>= -0x8000
3828 && imm_expr
.X_add_number
< 0x8000)
3829 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3830 AT
, reg
, BFD_RELOC_LO16
);
3833 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3834 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3838 /* Warn if an expression is not a constant. */
3841 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3843 if (ex
->X_op
== O_big
)
3844 as_bad (_("unsupported large constant"));
3845 else if (ex
->X_op
!= O_constant
)
3846 as_bad (_("Instruction %s requires absolute expression"),
3849 if (HAVE_32BIT_GPRS
)
3850 normalize_constant_expr (ex
);
3853 /* Count the leading zeroes by performing a binary chop. This is a
3854 bulky bit of source, but performance is a LOT better for the
3855 majority of values than a simple loop to count the bits:
3856 for (lcnt = 0; (lcnt < 32); lcnt++)
3857 if ((v) & (1 << (31 - lcnt)))
3859 However it is not code size friendly, and the gain will drop a bit
3860 on certain cached systems.
3862 #define COUNT_TOP_ZEROES(v) \
3863 (((v) & ~0xffff) == 0 \
3864 ? ((v) & ~0xff) == 0 \
3865 ? ((v) & ~0xf) == 0 \
3866 ? ((v) & ~0x3) == 0 \
3867 ? ((v) & ~0x1) == 0 \
3872 : ((v) & ~0x7) == 0 \
3875 : ((v) & ~0x3f) == 0 \
3876 ? ((v) & ~0x1f) == 0 \
3879 : ((v) & ~0x7f) == 0 \
3882 : ((v) & ~0xfff) == 0 \
3883 ? ((v) & ~0x3ff) == 0 \
3884 ? ((v) & ~0x1ff) == 0 \
3887 : ((v) & ~0x7ff) == 0 \
3890 : ((v) & ~0x3fff) == 0 \
3891 ? ((v) & ~0x1fff) == 0 \
3894 : ((v) & ~0x7fff) == 0 \
3897 : ((v) & ~0xffffff) == 0 \
3898 ? ((v) & ~0xfffff) == 0 \
3899 ? ((v) & ~0x3ffff) == 0 \
3900 ? ((v) & ~0x1ffff) == 0 \
3903 : ((v) & ~0x7ffff) == 0 \
3906 : ((v) & ~0x3fffff) == 0 \
3907 ? ((v) & ~0x1fffff) == 0 \
3910 : ((v) & ~0x7fffff) == 0 \
3913 : ((v) & ~0xfffffff) == 0 \
3914 ? ((v) & ~0x3ffffff) == 0 \
3915 ? ((v) & ~0x1ffffff) == 0 \
3918 : ((v) & ~0x7ffffff) == 0 \
3921 : ((v) & ~0x3fffffff) == 0 \
3922 ? ((v) & ~0x1fffffff) == 0 \
3925 : ((v) & ~0x7fffffff) == 0 \
3930 * This routine generates the least number of instructions necessary to load
3931 * an absolute expression value into a register.
3934 load_register (int reg
, expressionS
*ep
, int dbl
)
3937 expressionS hi32
, lo32
;
3939 if (ep
->X_op
!= O_big
)
3941 assert (ep
->X_op
== O_constant
);
3943 /* Sign-extending 32-bit constants makes their handling easier. */
3945 normalize_constant_expr (ep
);
3947 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3949 /* We can handle 16 bit signed values with an addiu to
3950 $zero. No need to ever use daddiu here, since $zero and
3951 the result are always correct in 32 bit mode. */
3952 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3955 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3957 /* We can handle 16 bit unsigned values with an ori to
3959 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3962 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3964 /* 32 bit values require an lui. */
3965 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3966 if ((ep
->X_add_number
& 0xffff) != 0)
3967 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3972 /* The value is larger than 32 bits. */
3974 if (!dbl
|| HAVE_32BIT_GPRS
)
3978 sprintf_vma (value
, ep
->X_add_number
);
3979 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3980 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3984 if (ep
->X_op
!= O_big
)
3987 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3988 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3989 hi32
.X_add_number
&= 0xffffffff;
3991 lo32
.X_add_number
&= 0xffffffff;
3995 assert (ep
->X_add_number
> 2);
3996 if (ep
->X_add_number
== 3)
3997 generic_bignum
[3] = 0;
3998 else if (ep
->X_add_number
> 4)
3999 as_bad (_("Number larger than 64 bits"));
4000 lo32
.X_op
= O_constant
;
4001 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4002 hi32
.X_op
= O_constant
;
4003 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4006 if (hi32
.X_add_number
== 0)
4011 unsigned long hi
, lo
;
4013 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4015 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4017 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4020 if (lo32
.X_add_number
& 0x80000000)
4022 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4023 if (lo32
.X_add_number
& 0xffff)
4024 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4029 /* Check for 16bit shifted constant. We know that hi32 is
4030 non-zero, so start the mask on the first bit of the hi32
4035 unsigned long himask
, lomask
;
4039 himask
= 0xffff >> (32 - shift
);
4040 lomask
= (0xffff << shift
) & 0xffffffff;
4044 himask
= 0xffff << (shift
- 32);
4047 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4048 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4052 tmp
.X_op
= O_constant
;
4054 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4055 | (lo32
.X_add_number
>> shift
));
4057 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4058 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4059 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4060 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4065 while (shift
<= (64 - 16));
4067 /* Find the bit number of the lowest one bit, and store the
4068 shifted value in hi/lo. */
4069 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4070 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4074 while ((lo
& 1) == 0)
4079 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4085 while ((hi
& 1) == 0)
4094 /* Optimize if the shifted value is a (power of 2) - 1. */
4095 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4096 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4098 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4103 /* This instruction will set the register to be all
4105 tmp
.X_op
= O_constant
;
4106 tmp
.X_add_number
= (offsetT
) -1;
4107 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4111 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4112 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4114 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4115 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4120 /* Sign extend hi32 before calling load_register, because we can
4121 generally get better code when we load a sign extended value. */
4122 if ((hi32
.X_add_number
& 0x80000000) != 0)
4123 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4124 load_register (reg
, &hi32
, 0);
4127 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4131 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4139 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4141 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4142 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4148 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4152 mid16
.X_add_number
>>= 16;
4153 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4154 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4157 if ((lo32
.X_add_number
& 0xffff) != 0)
4158 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4162 load_delay_nop (void)
4164 if (!gpr_interlocks
)
4165 macro_build (NULL
, "nop", "");
4168 /* Load an address into a register. */
4171 load_address (int reg
, expressionS
*ep
, int *used_at
)
4173 if (ep
->X_op
!= O_constant
4174 && ep
->X_op
!= O_symbol
)
4176 as_bad (_("expression too complex"));
4177 ep
->X_op
= O_constant
;
4180 if (ep
->X_op
== O_constant
)
4182 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4186 if (mips_pic
== NO_PIC
)
4188 /* If this is a reference to a GP relative symbol, we want
4189 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4191 lui $reg,<sym> (BFD_RELOC_HI16_S)
4192 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4193 If we have an addend, we always use the latter form.
4195 With 64bit address space and a usable $at we want
4196 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4197 lui $at,<sym> (BFD_RELOC_HI16_S)
4198 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4199 daddiu $at,<sym> (BFD_RELOC_LO16)
4203 If $at is already in use, we use a path which is suboptimal
4204 on superscalar processors.
4205 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4206 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4208 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4210 daddiu $reg,<sym> (BFD_RELOC_LO16)
4212 For GP relative symbols in 64bit address space we can use
4213 the same sequence as in 32bit address space. */
4214 if (HAVE_64BIT_SYMBOLS
)
4216 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4217 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4219 relax_start (ep
->X_add_symbol
);
4220 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4221 mips_gp_register
, BFD_RELOC_GPREL16
);
4225 if (*used_at
== 0 && !mips_opts
.noat
)
4227 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4228 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4229 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4230 BFD_RELOC_MIPS_HIGHER
);
4231 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4232 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4233 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4238 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4239 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4240 BFD_RELOC_MIPS_HIGHER
);
4241 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4242 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4243 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4244 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4247 if (mips_relax
.sequence
)
4252 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4253 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4255 relax_start (ep
->X_add_symbol
);
4256 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4257 mips_gp_register
, BFD_RELOC_GPREL16
);
4260 macro_build_lui (ep
, reg
);
4261 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4262 reg
, reg
, BFD_RELOC_LO16
);
4263 if (mips_relax
.sequence
)
4267 else if (!mips_big_got
)
4271 /* If this is a reference to an external symbol, we want
4272 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4274 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4276 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4277 If there is a constant, it must be added in after.
4279 If we have NewABI, we want
4280 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4281 unless we're referencing a global symbol with a non-zero
4282 offset, in which case cst must be added separately. */
4285 if (ep
->X_add_number
)
4287 ex
.X_add_number
= ep
->X_add_number
;
4288 ep
->X_add_number
= 0;
4289 relax_start (ep
->X_add_symbol
);
4290 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4291 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4292 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4293 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4294 ex
.X_op
= O_constant
;
4295 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4296 reg
, reg
, BFD_RELOC_LO16
);
4297 ep
->X_add_number
= ex
.X_add_number
;
4300 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4301 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4302 if (mips_relax
.sequence
)
4307 ex
.X_add_number
= ep
->X_add_number
;
4308 ep
->X_add_number
= 0;
4309 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4310 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4312 relax_start (ep
->X_add_symbol
);
4314 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4318 if (ex
.X_add_number
!= 0)
4320 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4321 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4322 ex
.X_op
= O_constant
;
4323 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4324 reg
, reg
, BFD_RELOC_LO16
);
4328 else if (mips_big_got
)
4332 /* This is the large GOT case. If this is a reference to an
4333 external symbol, we want
4334 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4336 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4338 Otherwise, for a reference to a local symbol in old ABI, we want
4339 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4341 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4342 If there is a constant, it must be added in after.
4344 In the NewABI, for local symbols, with or without offsets, we want:
4345 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4346 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4350 ex
.X_add_number
= ep
->X_add_number
;
4351 ep
->X_add_number
= 0;
4352 relax_start (ep
->X_add_symbol
);
4353 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4355 reg
, reg
, mips_gp_register
);
4356 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4357 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4358 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4359 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4360 else if (ex
.X_add_number
)
4362 ex
.X_op
= O_constant
;
4363 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4367 ep
->X_add_number
= ex
.X_add_number
;
4369 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4370 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4371 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4372 BFD_RELOC_MIPS_GOT_OFST
);
4377 ex
.X_add_number
= ep
->X_add_number
;
4378 ep
->X_add_number
= 0;
4379 relax_start (ep
->X_add_symbol
);
4380 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4381 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4382 reg
, reg
, mips_gp_register
);
4383 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4384 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4386 if (reg_needs_delay (mips_gp_register
))
4388 /* We need a nop before loading from $gp. This special
4389 check is required because the lui which starts the main
4390 instruction stream does not refer to $gp, and so will not
4391 insert the nop which may be required. */
4392 macro_build (NULL
, "nop", "");
4394 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4395 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4397 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4401 if (ex
.X_add_number
!= 0)
4403 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4404 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4405 ex
.X_op
= O_constant
;
4406 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4414 if (mips_opts
.noat
&& *used_at
== 1)
4415 as_bad (_("Macro used $at after \".set noat\""));
4418 /* Move the contents of register SOURCE into register DEST. */
4421 move_register (int dest
, int source
)
4423 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4427 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4428 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4429 The two alternatives are:
4431 Global symbol Local sybmol
4432 ------------- ------------
4433 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4435 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4437 load_got_offset emits the first instruction and add_got_offset
4438 emits the second for a 16-bit offset or add_got_offset_hilo emits
4439 a sequence to add a 32-bit offset using a scratch register. */
4442 load_got_offset (int dest
, expressionS
*local
)
4447 global
.X_add_number
= 0;
4449 relax_start (local
->X_add_symbol
);
4450 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4451 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4453 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4454 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4459 add_got_offset (int dest
, expressionS
*local
)
4463 global
.X_op
= O_constant
;
4464 global
.X_op_symbol
= NULL
;
4465 global
.X_add_symbol
= NULL
;
4466 global
.X_add_number
= local
->X_add_number
;
4468 relax_start (local
->X_add_symbol
);
4469 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4470 dest
, dest
, BFD_RELOC_LO16
);
4472 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4477 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4480 int hold_mips_optimize
;
4482 global
.X_op
= O_constant
;
4483 global
.X_op_symbol
= NULL
;
4484 global
.X_add_symbol
= NULL
;
4485 global
.X_add_number
= local
->X_add_number
;
4487 relax_start (local
->X_add_symbol
);
4488 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4490 /* Set mips_optimize around the lui instruction to avoid
4491 inserting an unnecessary nop after the lw. */
4492 hold_mips_optimize
= mips_optimize
;
4494 macro_build_lui (&global
, tmp
);
4495 mips_optimize
= hold_mips_optimize
;
4496 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4504 * This routine implements the seemingly endless macro or synthesized
4505 * instructions and addressing modes in the mips assembly language. Many
4506 * of these macros are simple and are similar to each other. These could
4507 * probably be handled by some kind of table or grammar approach instead of
4508 * this verbose method. Others are not simple macros but are more like
4509 * optimizing code generation.
4510 * One interesting optimization is when several store macros appear
4511 * consecutively that would load AT with the upper half of the same address.
4512 * The ensuing load upper instructions are ommited. This implies some kind
4513 * of global optimization. We currently only optimize within a single macro.
4514 * For many of the load and store macros if the address is specified as a
4515 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4516 * first load register 'at' with zero and use it as the base register. The
4517 * mips assembler simply uses register $zero. Just one tiny optimization
4521 macro (struct mips_cl_insn
*ip
)
4523 int treg
, sreg
, dreg
, breg
;
4539 bfd_reloc_code_real_type r
;
4540 int hold_mips_optimize
;
4542 assert (! mips_opts
.mips16
);
4544 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4545 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4546 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4547 mask
= ip
->insn_mo
->mask
;
4549 expr1
.X_op
= O_constant
;
4550 expr1
.X_op_symbol
= NULL
;
4551 expr1
.X_add_symbol
= NULL
;
4552 expr1
.X_add_number
= 1;
4566 expr1
.X_add_number
= 8;
4567 macro_build (&expr1
, "bgez", "s,p", sreg
);
4569 macro_build (NULL
, "nop", "", 0);
4571 move_register (dreg
, sreg
);
4572 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4595 if (imm_expr
.X_op
== O_constant
4596 && imm_expr
.X_add_number
>= -0x8000
4597 && imm_expr
.X_add_number
< 0x8000)
4599 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4603 load_register (AT
, &imm_expr
, dbl
);
4604 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4623 if (imm_expr
.X_op
== O_constant
4624 && imm_expr
.X_add_number
>= 0
4625 && imm_expr
.X_add_number
< 0x10000)
4627 if (mask
!= M_NOR_I
)
4628 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4631 macro_build (&imm_expr
, "ori", "t,r,i",
4632 treg
, sreg
, BFD_RELOC_LO16
);
4633 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4639 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4640 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4644 switch (imm_expr
.X_add_number
)
4647 macro_build (NULL
, "nop", "");
4650 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4653 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4654 (int)imm_expr
.X_add_number
);
4673 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4675 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4679 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4680 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4688 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4693 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4697 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4698 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4704 /* check for > max integer */
4705 maxnum
= 0x7fffffff;
4706 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4713 if (imm_expr
.X_op
== O_constant
4714 && imm_expr
.X_add_number
>= maxnum
4715 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4718 /* result is always false */
4720 macro_build (NULL
, "nop", "", 0);
4722 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4725 if (imm_expr
.X_op
!= O_constant
)
4726 as_bad (_("Unsupported large constant"));
4727 ++imm_expr
.X_add_number
;
4731 if (mask
== M_BGEL_I
)
4733 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4735 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4738 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4740 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4743 maxnum
= 0x7fffffff;
4744 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4751 maxnum
= - maxnum
- 1;
4752 if (imm_expr
.X_op
== O_constant
4753 && imm_expr
.X_add_number
<= maxnum
4754 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4757 /* result is always true */
4758 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4759 macro_build (&offset_expr
, "b", "p");
4764 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4774 macro_build (&offset_expr
, likely
? "beql" : "beq",
4779 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4780 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4788 && imm_expr
.X_op
== O_constant
4789 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4791 if (imm_expr
.X_op
!= O_constant
)
4792 as_bad (_("Unsupported large constant"));
4793 ++imm_expr
.X_add_number
;
4797 if (mask
== M_BGEUL_I
)
4799 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4801 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4803 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4809 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4817 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4822 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4826 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4827 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4835 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4842 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4843 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4851 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4856 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4860 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4861 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4867 maxnum
= 0x7fffffff;
4868 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4875 if (imm_expr
.X_op
== O_constant
4876 && imm_expr
.X_add_number
>= maxnum
4877 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4879 if (imm_expr
.X_op
!= O_constant
)
4880 as_bad (_("Unsupported large constant"));
4881 ++imm_expr
.X_add_number
;
4885 if (mask
== M_BLTL_I
)
4887 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4889 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4892 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4894 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4899 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4907 macro_build (&offset_expr
, likely
? "beql" : "beq",
4914 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4915 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4923 && imm_expr
.X_op
== O_constant
4924 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4926 if (imm_expr
.X_op
!= O_constant
)
4927 as_bad (_("Unsupported large constant"));
4928 ++imm_expr
.X_add_number
;
4932 if (mask
== M_BLTUL_I
)
4934 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4936 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4938 macro_build (&offset_expr
, likely
? "beql" : "beq",
4944 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4952 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4957 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4961 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4962 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4972 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4977 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4978 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4986 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4988 as_bad (_("Unsupported large constant"));
4993 pos
= (unsigned long) imm_expr
.X_add_number
;
4994 size
= (unsigned long) imm2_expr
.X_add_number
;
4999 as_bad (_("Improper position (%lu)"), pos
);
5002 if (size
== 0 || size
> 64
5003 || (pos
+ size
- 1) > 63)
5005 as_bad (_("Improper extract size (%lu, position %lu)"),
5010 if (size
<= 32 && pos
< 32)
5015 else if (size
<= 32)
5025 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5034 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5036 as_bad (_("Unsupported large constant"));
5041 pos
= (unsigned long) imm_expr
.X_add_number
;
5042 size
= (unsigned long) imm2_expr
.X_add_number
;
5047 as_bad (_("Improper position (%lu)"), pos
);
5050 if (size
== 0 || size
> 64
5051 || (pos
+ size
- 1) > 63)
5053 as_bad (_("Improper insert size (%lu, position %lu)"),
5058 if (pos
< 32 && (pos
+ size
- 1) < 32)
5073 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5090 as_warn (_("Divide by zero."));
5092 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5094 macro_build (NULL
, "break", "c", 7);
5101 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5102 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5106 expr1
.X_add_number
= 8;
5107 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5108 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5109 macro_build (NULL
, "break", "c", 7);
5111 expr1
.X_add_number
= -1;
5113 load_register (AT
, &expr1
, dbl
);
5114 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5115 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5118 expr1
.X_add_number
= 1;
5119 load_register (AT
, &expr1
, dbl
);
5120 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5124 expr1
.X_add_number
= 0x80000000;
5125 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5129 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5130 /* We want to close the noreorder block as soon as possible, so
5131 that later insns are available for delay slot filling. */
5136 expr1
.X_add_number
= 8;
5137 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5138 macro_build (NULL
, "nop", "", 0);
5140 /* We want to close the noreorder block as soon as possible, so
5141 that later insns are available for delay slot filling. */
5144 macro_build (NULL
, "break", "c", 6);
5146 macro_build (NULL
, s
, "d", dreg
);
5185 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5187 as_warn (_("Divide by zero."));
5189 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5191 macro_build (NULL
, "break", "c", 7);
5194 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5196 if (strcmp (s2
, "mflo") == 0)
5197 move_register (dreg
, sreg
);
5199 move_register (dreg
, 0);
5202 if (imm_expr
.X_op
== O_constant
5203 && imm_expr
.X_add_number
== -1
5204 && s
[strlen (s
) - 1] != 'u')
5206 if (strcmp (s2
, "mflo") == 0)
5208 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5211 move_register (dreg
, 0);
5216 load_register (AT
, &imm_expr
, dbl
);
5217 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5218 macro_build (NULL
, s2
, "d", dreg
);
5240 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5241 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5242 /* We want to close the noreorder block as soon as possible, so
5243 that later insns are available for delay slot filling. */
5248 expr1
.X_add_number
= 8;
5249 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5250 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5252 /* We want to close the noreorder block as soon as possible, so
5253 that later insns are available for delay slot filling. */
5255 macro_build (NULL
, "break", "c", 7);
5257 macro_build (NULL
, s2
, "d", dreg
);
5269 /* Load the address of a symbol into a register. If breg is not
5270 zero, we then add a base register to it. */
5272 if (dbl
&& HAVE_32BIT_GPRS
)
5273 as_warn (_("dla used to load 32-bit register"));
5275 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5276 as_warn (_("la used to load 64-bit address"));
5278 if (offset_expr
.X_op
== O_constant
5279 && offset_expr
.X_add_number
>= -0x8000
5280 && offset_expr
.X_add_number
< 0x8000)
5282 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5283 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5287 if (!mips_opts
.noat
&& (treg
== breg
))
5297 if (offset_expr
.X_op
!= O_symbol
5298 && offset_expr
.X_op
!= O_constant
)
5300 as_bad (_("expression too complex"));
5301 offset_expr
.X_op
= O_constant
;
5304 if (offset_expr
.X_op
== O_constant
)
5305 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5306 else if (mips_pic
== NO_PIC
)
5308 /* If this is a reference to a GP relative symbol, we want
5309 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5311 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5312 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5313 If we have a constant, we need two instructions anyhow,
5314 so we may as well always use the latter form.
5316 With 64bit address space and a usable $at we want
5317 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5318 lui $at,<sym> (BFD_RELOC_HI16_S)
5319 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5320 daddiu $at,<sym> (BFD_RELOC_LO16)
5322 daddu $tempreg,$tempreg,$at
5324 If $at is already in use, we use a path which is suboptimal
5325 on superscalar processors.
5326 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5329 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5331 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5333 For GP relative symbols in 64bit address space we can use
5334 the same sequence as in 32bit address space. */
5335 if (HAVE_64BIT_SYMBOLS
)
5337 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5338 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5340 relax_start (offset_expr
.X_add_symbol
);
5341 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5342 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5346 if (used_at
== 0 && !mips_opts
.noat
)
5348 macro_build (&offset_expr
, "lui", "t,u",
5349 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5350 macro_build (&offset_expr
, "lui", "t,u",
5351 AT
, BFD_RELOC_HI16_S
);
5352 macro_build (&offset_expr
, "daddiu", "t,r,j",
5353 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5354 macro_build (&offset_expr
, "daddiu", "t,r,j",
5355 AT
, AT
, BFD_RELOC_LO16
);
5356 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5357 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5362 macro_build (&offset_expr
, "lui", "t,u",
5363 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5364 macro_build (&offset_expr
, "daddiu", "t,r,j",
5365 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5366 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5367 macro_build (&offset_expr
, "daddiu", "t,r,j",
5368 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5369 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5370 macro_build (&offset_expr
, "daddiu", "t,r,j",
5371 tempreg
, tempreg
, BFD_RELOC_LO16
);
5374 if (mips_relax
.sequence
)
5379 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5380 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5382 relax_start (offset_expr
.X_add_symbol
);
5383 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5384 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5387 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5388 as_bad (_("offset too large"));
5389 macro_build_lui (&offset_expr
, tempreg
);
5390 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5391 tempreg
, tempreg
, BFD_RELOC_LO16
);
5392 if (mips_relax
.sequence
)
5396 else if (!mips_big_got
&& !HAVE_NEWABI
)
5398 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5400 /* If this is a reference to an external symbol, and there
5401 is no constant, we want
5402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5403 or for lca or if tempreg is PIC_CALL_REG
5404 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5405 For a local symbol, we want
5406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5408 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5410 If we have a small constant, and this is a reference to
5411 an external symbol, we want
5412 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5414 addiu $tempreg,$tempreg,<constant>
5415 For a local symbol, we want the same instruction
5416 sequence, but we output a BFD_RELOC_LO16 reloc on the
5419 If we have a large constant, and this is a reference to
5420 an external symbol, we want
5421 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5422 lui $at,<hiconstant>
5423 addiu $at,$at,<loconstant>
5424 addu $tempreg,$tempreg,$at
5425 For a local symbol, we want the same instruction
5426 sequence, but we output a BFD_RELOC_LO16 reloc on the
5430 if (offset_expr
.X_add_number
== 0)
5432 if (mips_pic
== SVR4_PIC
5434 && (call
|| tempreg
== PIC_CALL_REG
))
5435 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5437 relax_start (offset_expr
.X_add_symbol
);
5438 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5439 lw_reloc_type
, mips_gp_register
);
5442 /* We're going to put in an addu instruction using
5443 tempreg, so we may as well insert the nop right
5448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5449 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5451 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5452 tempreg
, tempreg
, BFD_RELOC_LO16
);
5454 /* FIXME: If breg == 0, and the next instruction uses
5455 $tempreg, then if this variant case is used an extra
5456 nop will be generated. */
5458 else if (offset_expr
.X_add_number
>= -0x8000
5459 && offset_expr
.X_add_number
< 0x8000)
5461 load_got_offset (tempreg
, &offset_expr
);
5463 add_got_offset (tempreg
, &offset_expr
);
5467 expr1
.X_add_number
= offset_expr
.X_add_number
;
5468 offset_expr
.X_add_number
=
5469 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5470 load_got_offset (tempreg
, &offset_expr
);
5471 offset_expr
.X_add_number
= expr1
.X_add_number
;
5472 /* If we are going to add in a base register, and the
5473 target register and the base register are the same,
5474 then we are using AT as a temporary register. Since
5475 we want to load the constant into AT, we add our
5476 current AT (from the global offset table) and the
5477 register into the register now, and pretend we were
5478 not using a base register. */
5482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5487 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5491 else if (!mips_big_got
&& HAVE_NEWABI
)
5493 int add_breg_early
= 0;
5495 /* If this is a reference to an external, and there is no
5496 constant, or local symbol (*), with or without a
5498 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5499 or for lca or if tempreg is PIC_CALL_REG
5500 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5502 If we have a small constant, and this is a reference to
5503 an external symbol, we want
5504 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5505 addiu $tempreg,$tempreg,<constant>
5507 If we have a large constant, and this is a reference to
5508 an external symbol, we want
5509 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5510 lui $at,<hiconstant>
5511 addiu $at,$at,<loconstant>
5512 addu $tempreg,$tempreg,$at
5514 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5515 local symbols, even though it introduces an additional
5518 if (offset_expr
.X_add_number
)
5520 expr1
.X_add_number
= offset_expr
.X_add_number
;
5521 offset_expr
.X_add_number
= 0;
5523 relax_start (offset_expr
.X_add_symbol
);
5524 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5525 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5527 if (expr1
.X_add_number
>= -0x8000
5528 && expr1
.X_add_number
< 0x8000)
5530 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5531 tempreg
, tempreg
, BFD_RELOC_LO16
);
5533 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5537 /* If we are going to add in a base register, and the
5538 target register and the base register are the same,
5539 then we are using AT as a temporary register. Since
5540 we want to load the constant into AT, we add our
5541 current AT (from the global offset table) and the
5542 register into the register now, and pretend we were
5543 not using a base register. */
5548 assert (tempreg
== AT
);
5549 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5555 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5556 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5562 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5565 offset_expr
.X_add_number
= expr1
.X_add_number
;
5567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5568 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5572 treg
, tempreg
, breg
);
5578 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5580 relax_start (offset_expr
.X_add_symbol
);
5581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5582 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5584 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5585 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5591 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5594 else if (mips_big_got
&& !HAVE_NEWABI
)
5597 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5598 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5599 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5601 /* This is the large GOT case. If this is a reference to an
5602 external symbol, and there is no constant, we want
5603 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5604 addu $tempreg,$tempreg,$gp
5605 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5606 or for lca or if tempreg is PIC_CALL_REG
5607 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5608 addu $tempreg,$tempreg,$gp
5609 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5610 For a local symbol, we want
5611 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5613 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5615 If we have a small constant, and this is a reference to
5616 an external symbol, we want
5617 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5618 addu $tempreg,$tempreg,$gp
5619 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5621 addiu $tempreg,$tempreg,<constant>
5622 For a local symbol, we want
5623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5625 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5627 If we have a large constant, and this is a reference to
5628 an external symbol, we want
5629 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5630 addu $tempreg,$tempreg,$gp
5631 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5632 lui $at,<hiconstant>
5633 addiu $at,$at,<loconstant>
5634 addu $tempreg,$tempreg,$at
5635 For a local symbol, we want
5636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5637 lui $at,<hiconstant>
5638 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5639 addu $tempreg,$tempreg,$at
5642 expr1
.X_add_number
= offset_expr
.X_add_number
;
5643 offset_expr
.X_add_number
= 0;
5644 relax_start (offset_expr
.X_add_symbol
);
5645 gpdelay
= reg_needs_delay (mips_gp_register
);
5646 if (expr1
.X_add_number
== 0 && breg
== 0
5647 && (call
|| tempreg
== PIC_CALL_REG
))
5649 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5650 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5652 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5654 tempreg
, tempreg
, mips_gp_register
);
5655 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5656 tempreg
, lw_reloc_type
, tempreg
);
5657 if (expr1
.X_add_number
== 0)
5661 /* We're going to put in an addu instruction using
5662 tempreg, so we may as well insert the nop right
5667 else if (expr1
.X_add_number
>= -0x8000
5668 && expr1
.X_add_number
< 0x8000)
5671 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5672 tempreg
, tempreg
, BFD_RELOC_LO16
);
5678 /* If we are going to add in a base register, and the
5679 target register and the base register are the same,
5680 then we are using AT as a temporary register. Since
5681 we want to load the constant into AT, we add our
5682 current AT (from the global offset table) and the
5683 register into the register now, and pretend we were
5684 not using a base register. */
5689 assert (tempreg
== AT
);
5691 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5696 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5701 offset_expr
.X_add_number
=
5702 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5707 /* This is needed because this instruction uses $gp, but
5708 the first instruction on the main stream does not. */
5709 macro_build (NULL
, "nop", "");
5712 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5713 local_reloc_type
, mips_gp_register
);
5714 if (expr1
.X_add_number
>= -0x8000
5715 && expr1
.X_add_number
< 0x8000)
5718 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5719 tempreg
, tempreg
, BFD_RELOC_LO16
);
5720 /* FIXME: If add_number is 0, and there was no base
5721 register, the external symbol case ended with a load,
5722 so if the symbol turns out to not be external, and
5723 the next instruction uses tempreg, an unnecessary nop
5724 will be inserted. */
5730 /* We must add in the base register now, as in the
5731 external symbol case. */
5732 assert (tempreg
== AT
);
5734 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5737 /* We set breg to 0 because we have arranged to add
5738 it in in both cases. */
5742 macro_build_lui (&expr1
, AT
);
5743 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5744 AT
, AT
, BFD_RELOC_LO16
);
5745 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5746 tempreg
, tempreg
, AT
);
5751 else if (mips_big_got
&& HAVE_NEWABI
)
5753 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5754 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5755 int add_breg_early
= 0;
5757 /* This is the large GOT case. If this is a reference to an
5758 external symbol, and there is no constant, we want
5759 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5760 add $tempreg,$tempreg,$gp
5761 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5762 or for lca or if tempreg is PIC_CALL_REG
5763 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5764 add $tempreg,$tempreg,$gp
5765 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5767 If we have a small constant, and this is a reference to
5768 an external symbol, we want
5769 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5770 add $tempreg,$tempreg,$gp
5771 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5772 addi $tempreg,$tempreg,<constant>
5774 If we have a large constant, and this is a reference to
5775 an external symbol, we want
5776 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5777 addu $tempreg,$tempreg,$gp
5778 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5779 lui $at,<hiconstant>
5780 addi $at,$at,<loconstant>
5781 add $tempreg,$tempreg,$at
5783 If we have NewABI, and we know it's a local symbol, we want
5784 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5785 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5786 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5788 relax_start (offset_expr
.X_add_symbol
);
5790 expr1
.X_add_number
= offset_expr
.X_add_number
;
5791 offset_expr
.X_add_number
= 0;
5793 if (expr1
.X_add_number
== 0 && breg
== 0
5794 && (call
|| tempreg
== PIC_CALL_REG
))
5796 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5797 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5799 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5800 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5801 tempreg
, tempreg
, mips_gp_register
);
5802 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5803 tempreg
, lw_reloc_type
, tempreg
);
5805 if (expr1
.X_add_number
== 0)
5807 else if (expr1
.X_add_number
>= -0x8000
5808 && expr1
.X_add_number
< 0x8000)
5810 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5811 tempreg
, tempreg
, BFD_RELOC_LO16
);
5813 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5817 /* If we are going to add in a base register, and the
5818 target register and the base register are the same,
5819 then we are using AT as a temporary register. Since
5820 we want to load the constant into AT, we add our
5821 current AT (from the global offset table) and the
5822 register into the register now, and pretend we were
5823 not using a base register. */
5828 assert (tempreg
== AT
);
5829 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5835 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5836 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5841 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5844 offset_expr
.X_add_number
= expr1
.X_add_number
;
5845 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5846 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5847 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5848 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5851 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5852 treg
, tempreg
, breg
);
5862 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5866 /* The j instruction may not be used in PIC code, since it
5867 requires an absolute address. We convert it to a b
5869 if (mips_pic
== NO_PIC
)
5870 macro_build (&offset_expr
, "j", "a");
5872 macro_build (&offset_expr
, "b", "p");
5875 /* The jal instructions must be handled as macros because when
5876 generating PIC code they expand to multi-instruction
5877 sequences. Normally they are simple instructions. */
5882 if (mips_pic
== NO_PIC
)
5883 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5886 if (sreg
!= PIC_CALL_REG
)
5887 as_warn (_("MIPS PIC call to register other than $25"));
5889 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5890 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5892 if (mips_cprestore_offset
< 0)
5893 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5896 if (! mips_frame_reg_valid
)
5898 as_warn (_("No .frame pseudo-op used in PIC code"));
5899 /* Quiet this warning. */
5900 mips_frame_reg_valid
= 1;
5902 if (! mips_cprestore_valid
)
5904 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5905 /* Quiet this warning. */
5906 mips_cprestore_valid
= 1;
5908 expr1
.X_add_number
= mips_cprestore_offset
;
5909 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5912 HAVE_64BIT_ADDRESSES
);
5920 if (mips_pic
== NO_PIC
)
5921 macro_build (&offset_expr
, "jal", "a");
5922 else if (mips_pic
== SVR4_PIC
)
5924 /* If this is a reference to an external symbol, and we are
5925 using a small GOT, we want
5926 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5930 lw $gp,cprestore($sp)
5931 The cprestore value is set using the .cprestore
5932 pseudo-op. If we are using a big GOT, we want
5933 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5935 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5939 lw $gp,cprestore($sp)
5940 If the symbol is not external, we want
5941 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5943 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5946 lw $gp,cprestore($sp)
5948 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5949 sequences above, minus nops, unless the symbol is local,
5950 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5956 relax_start (offset_expr
.X_add_symbol
);
5957 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5958 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5961 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5962 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5968 relax_start (offset_expr
.X_add_symbol
);
5969 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5970 BFD_RELOC_MIPS_CALL_HI16
);
5971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5972 PIC_CALL_REG
, mips_gp_register
);
5973 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5974 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5977 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5978 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5980 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5981 PIC_CALL_REG
, PIC_CALL_REG
,
5982 BFD_RELOC_MIPS_GOT_OFST
);
5986 macro_build_jalr (&offset_expr
);
5990 relax_start (offset_expr
.X_add_symbol
);
5993 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5994 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6003 gpdelay
= reg_needs_delay (mips_gp_register
);
6004 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6005 BFD_RELOC_MIPS_CALL_HI16
);
6006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6007 PIC_CALL_REG
, mips_gp_register
);
6008 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6009 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6014 macro_build (NULL
, "nop", "");
6016 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6017 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6020 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6021 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6023 macro_build_jalr (&offset_expr
);
6025 if (mips_cprestore_offset
< 0)
6026 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6029 if (! mips_frame_reg_valid
)
6031 as_warn (_("No .frame pseudo-op used in PIC code"));
6032 /* Quiet this warning. */
6033 mips_frame_reg_valid
= 1;
6035 if (! mips_cprestore_valid
)
6037 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6038 /* Quiet this warning. */
6039 mips_cprestore_valid
= 1;
6041 if (mips_opts
.noreorder
)
6042 macro_build (NULL
, "nop", "");
6043 expr1
.X_add_number
= mips_cprestore_offset
;
6044 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6047 HAVE_64BIT_ADDRESSES
);
6051 else if (mips_pic
== VXWORKS_PIC
)
6052 as_bad (_("Non-PIC jump used in PIC library"));
6075 /* Itbl support may require additional care here. */
6080 /* Itbl support may require additional care here. */
6085 /* Itbl support may require additional care here. */
6090 /* Itbl support may require additional care here. */
6102 if (mips_opts
.arch
== CPU_R4650
)
6104 as_bad (_("opcode not supported on this processor"));
6108 /* Itbl support may require additional care here. */
6113 /* Itbl support may require additional care here. */
6118 /* Itbl support may require additional care here. */
6138 if (breg
== treg
|| coproc
|| lr
)
6159 /* Itbl support may require additional care here. */
6164 /* Itbl support may require additional care here. */
6169 /* Itbl support may require additional care here. */
6174 /* Itbl support may require additional care here. */
6193 if (mips_opts
.arch
== CPU_R4650
)
6195 as_bad (_("opcode not supported on this processor"));
6200 /* Itbl support may require additional care here. */
6204 /* Itbl support may require additional care here. */
6209 /* Itbl support may require additional care here. */
6221 /* Itbl support may require additional care here. */
6222 if (mask
== M_LWC1_AB
6223 || mask
== M_SWC1_AB
6224 || mask
== M_LDC1_AB
6225 || mask
== M_SDC1_AB
6229 else if (mask
== M_CACHE_AB
)
6236 if (offset_expr
.X_op
!= O_constant
6237 && offset_expr
.X_op
!= O_symbol
)
6239 as_bad (_("expression too complex"));
6240 offset_expr
.X_op
= O_constant
;
6243 if (HAVE_32BIT_ADDRESSES
6244 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6248 sprintf_vma (value
, offset_expr
.X_add_number
);
6249 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6252 /* A constant expression in PIC code can be handled just as it
6253 is in non PIC code. */
6254 if (offset_expr
.X_op
== O_constant
)
6256 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6257 & ~(bfd_vma
) 0xffff);
6258 normalize_address_expr (&expr1
);
6259 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6261 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6262 tempreg
, tempreg
, breg
);
6263 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6265 else if (mips_pic
== NO_PIC
)
6267 /* If this is a reference to a GP relative symbol, and there
6268 is no base register, we want
6269 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6270 Otherwise, if there is no base register, we want
6271 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6272 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6273 If we have a constant, we need two instructions anyhow,
6274 so we always use the latter form.
6276 If we have a base register, and this is a reference to a
6277 GP relative symbol, we want
6278 addu $tempreg,$breg,$gp
6279 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6281 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6282 addu $tempreg,$tempreg,$breg
6283 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6284 With a constant we always use the latter case.
6286 With 64bit address space and no base register and $at usable,
6288 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6289 lui $at,<sym> (BFD_RELOC_HI16_S)
6290 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6293 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6294 If we have a base register, we want
6295 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6296 lui $at,<sym> (BFD_RELOC_HI16_S)
6297 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6301 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6303 Without $at we can't generate the optimal path for superscalar
6304 processors here since this would require two temporary registers.
6305 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6306 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6308 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6310 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6311 If we have a base register, we want
6312 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6313 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6315 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6317 daddu $tempreg,$tempreg,$breg
6318 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6320 For GP relative symbols in 64bit address space we can use
6321 the same sequence as in 32bit address space. */
6322 if (HAVE_64BIT_SYMBOLS
)
6324 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6325 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6327 relax_start (offset_expr
.X_add_symbol
);
6330 macro_build (&offset_expr
, s
, fmt
, treg
,
6331 BFD_RELOC_GPREL16
, mips_gp_register
);
6335 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6336 tempreg
, breg
, mips_gp_register
);
6337 macro_build (&offset_expr
, s
, fmt
, treg
,
6338 BFD_RELOC_GPREL16
, tempreg
);
6343 if (used_at
== 0 && !mips_opts
.noat
)
6345 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6346 BFD_RELOC_MIPS_HIGHEST
);
6347 macro_build (&offset_expr
, "lui", "t,u", AT
,
6349 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6350 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6352 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6353 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6354 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6355 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6361 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6362 BFD_RELOC_MIPS_HIGHEST
);
6363 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6364 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6365 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6366 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6367 tempreg
, BFD_RELOC_HI16_S
);
6368 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6370 macro_build (NULL
, "daddu", "d,v,t",
6371 tempreg
, tempreg
, breg
);
6372 macro_build (&offset_expr
, s
, fmt
, treg
,
6373 BFD_RELOC_LO16
, tempreg
);
6376 if (mips_relax
.sequence
)
6383 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6384 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6386 relax_start (offset_expr
.X_add_symbol
);
6387 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6391 macro_build_lui (&offset_expr
, tempreg
);
6392 macro_build (&offset_expr
, s
, fmt
, treg
,
6393 BFD_RELOC_LO16
, tempreg
);
6394 if (mips_relax
.sequence
)
6399 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6400 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6402 relax_start (offset_expr
.X_add_symbol
);
6403 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6404 tempreg
, breg
, mips_gp_register
);
6405 macro_build (&offset_expr
, s
, fmt
, treg
,
6406 BFD_RELOC_GPREL16
, tempreg
);
6409 macro_build_lui (&offset_expr
, tempreg
);
6410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6411 tempreg
, tempreg
, breg
);
6412 macro_build (&offset_expr
, s
, fmt
, treg
,
6413 BFD_RELOC_LO16
, tempreg
);
6414 if (mips_relax
.sequence
)
6418 else if (!mips_big_got
)
6420 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6422 /* If this is a reference to an external symbol, we want
6423 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6425 <op> $treg,0($tempreg)
6427 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6429 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6430 <op> $treg,0($tempreg)
6433 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6434 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6436 If there is a base register, we add it to $tempreg before
6437 the <op>. If there is a constant, we stick it in the
6438 <op> instruction. We don't handle constants larger than
6439 16 bits, because we have no way to load the upper 16 bits
6440 (actually, we could handle them for the subset of cases
6441 in which we are not using $at). */
6442 assert (offset_expr
.X_op
== O_symbol
);
6445 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6446 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6449 tempreg
, tempreg
, breg
);
6450 macro_build (&offset_expr
, s
, fmt
, treg
,
6451 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6454 expr1
.X_add_number
= offset_expr
.X_add_number
;
6455 offset_expr
.X_add_number
= 0;
6456 if (expr1
.X_add_number
< -0x8000
6457 || expr1
.X_add_number
>= 0x8000)
6458 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6460 lw_reloc_type
, mips_gp_register
);
6462 relax_start (offset_expr
.X_add_symbol
);
6464 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6465 tempreg
, BFD_RELOC_LO16
);
6468 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6469 tempreg
, tempreg
, breg
);
6470 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6472 else if (mips_big_got
&& !HAVE_NEWABI
)
6476 /* If this is a reference to an external symbol, we want
6477 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6478 addu $tempreg,$tempreg,$gp
6479 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6480 <op> $treg,0($tempreg)
6482 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6484 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6485 <op> $treg,0($tempreg)
6486 If there is a base register, we add it to $tempreg before
6487 the <op>. If there is a constant, we stick it in the
6488 <op> instruction. We don't handle constants larger than
6489 16 bits, because we have no way to load the upper 16 bits
6490 (actually, we could handle them for the subset of cases
6491 in which we are not using $at). */
6492 assert (offset_expr
.X_op
== O_symbol
);
6493 expr1
.X_add_number
= offset_expr
.X_add_number
;
6494 offset_expr
.X_add_number
= 0;
6495 if (expr1
.X_add_number
< -0x8000
6496 || expr1
.X_add_number
>= 0x8000)
6497 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6498 gpdelay
= reg_needs_delay (mips_gp_register
);
6499 relax_start (offset_expr
.X_add_symbol
);
6500 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6501 BFD_RELOC_MIPS_GOT_HI16
);
6502 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6504 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6505 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6508 macro_build (NULL
, "nop", "");
6509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6510 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6512 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6513 tempreg
, BFD_RELOC_LO16
);
6517 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6518 tempreg
, tempreg
, breg
);
6519 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6521 else if (mips_big_got
&& HAVE_NEWABI
)
6523 /* If this is a reference to an external symbol, we want
6524 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6525 add $tempreg,$tempreg,$gp
6526 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6527 <op> $treg,<ofst>($tempreg)
6528 Otherwise, for local symbols, we want:
6529 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6530 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6531 assert (offset_expr
.X_op
== O_symbol
);
6532 expr1
.X_add_number
= offset_expr
.X_add_number
;
6533 offset_expr
.X_add_number
= 0;
6534 if (expr1
.X_add_number
< -0x8000
6535 || expr1
.X_add_number
>= 0x8000)
6536 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6537 relax_start (offset_expr
.X_add_symbol
);
6538 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6539 BFD_RELOC_MIPS_GOT_HI16
);
6540 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6543 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6546 tempreg
, tempreg
, breg
);
6547 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6550 offset_expr
.X_add_number
= expr1
.X_add_number
;
6551 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6552 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6555 tempreg
, tempreg
, breg
);
6556 macro_build (&offset_expr
, s
, fmt
, treg
,
6557 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6567 load_register (treg
, &imm_expr
, 0);
6571 load_register (treg
, &imm_expr
, 1);
6575 if (imm_expr
.X_op
== O_constant
)
6578 load_register (AT
, &imm_expr
, 0);
6579 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6584 assert (offset_expr
.X_op
== O_symbol
6585 && strcmp (segment_name (S_GET_SEGMENT
6586 (offset_expr
.X_add_symbol
)),
6588 && offset_expr
.X_add_number
== 0);
6589 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6590 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6595 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6596 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6597 order 32 bits of the value and the low order 32 bits are either
6598 zero or in OFFSET_EXPR. */
6599 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6601 if (HAVE_64BIT_GPRS
)
6602 load_register (treg
, &imm_expr
, 1);
6607 if (target_big_endian
)
6619 load_register (hreg
, &imm_expr
, 0);
6622 if (offset_expr
.X_op
== O_absent
)
6623 move_register (lreg
, 0);
6626 assert (offset_expr
.X_op
== O_constant
);
6627 load_register (lreg
, &offset_expr
, 0);
6634 /* We know that sym is in the .rdata section. First we get the
6635 upper 16 bits of the address. */
6636 if (mips_pic
== NO_PIC
)
6638 macro_build_lui (&offset_expr
, AT
);
6643 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6644 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6648 /* Now we load the register(s). */
6649 if (HAVE_64BIT_GPRS
)
6652 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6657 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6660 /* FIXME: How in the world do we deal with the possible
6662 offset_expr
.X_add_number
+= 4;
6663 macro_build (&offset_expr
, "lw", "t,o(b)",
6664 treg
+ 1, BFD_RELOC_LO16
, AT
);
6670 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6671 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6672 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6673 the value and the low order 32 bits are either zero or in
6675 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6678 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6679 if (HAVE_64BIT_FPRS
)
6681 assert (HAVE_64BIT_GPRS
);
6682 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6686 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6687 if (offset_expr
.X_op
== O_absent
)
6688 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6691 assert (offset_expr
.X_op
== O_constant
);
6692 load_register (AT
, &offset_expr
, 0);
6693 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6699 assert (offset_expr
.X_op
== O_symbol
6700 && offset_expr
.X_add_number
== 0);
6701 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6702 if (strcmp (s
, ".lit8") == 0)
6704 if (mips_opts
.isa
!= ISA_MIPS1
)
6706 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6707 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6710 breg
= mips_gp_register
;
6711 r
= BFD_RELOC_MIPS_LITERAL
;
6716 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6718 if (mips_pic
!= NO_PIC
)
6719 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6720 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6723 /* FIXME: This won't work for a 64 bit address. */
6724 macro_build_lui (&offset_expr
, AT
);
6727 if (mips_opts
.isa
!= ISA_MIPS1
)
6729 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6730 treg
, BFD_RELOC_LO16
, AT
);
6739 if (mips_opts
.arch
== CPU_R4650
)
6741 as_bad (_("opcode not supported on this processor"));
6744 /* Even on a big endian machine $fn comes before $fn+1. We have
6745 to adjust when loading from memory. */
6748 assert (mips_opts
.isa
== ISA_MIPS1
);
6749 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6750 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6751 /* FIXME: A possible overflow which I don't know how to deal
6753 offset_expr
.X_add_number
+= 4;
6754 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6755 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6760 * The MIPS assembler seems to check for X_add_number not
6761 * being double aligned and generating:
6764 * addiu at,at,%lo(foo+1)
6767 * But, the resulting address is the same after relocation so why
6768 * generate the extra instruction?
6770 if (mips_opts
.arch
== CPU_R4650
)
6772 as_bad (_("opcode not supported on this processor"));
6775 /* Itbl support may require additional care here. */
6777 if (mips_opts
.isa
!= ISA_MIPS1
)
6788 if (mips_opts
.arch
== CPU_R4650
)
6790 as_bad (_("opcode not supported on this processor"));
6794 if (mips_opts
.isa
!= ISA_MIPS1
)
6802 /* Itbl support may require additional care here. */
6807 if (HAVE_64BIT_GPRS
)
6818 if (HAVE_64BIT_GPRS
)
6828 if (offset_expr
.X_op
!= O_symbol
6829 && offset_expr
.X_op
!= O_constant
)
6831 as_bad (_("expression too complex"));
6832 offset_expr
.X_op
= O_constant
;
6835 if (HAVE_32BIT_ADDRESSES
6836 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6840 sprintf_vma (value
, offset_expr
.X_add_number
);
6841 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6844 /* Even on a big endian machine $fn comes before $fn+1. We have
6845 to adjust when loading from memory. We set coproc if we must
6846 load $fn+1 first. */
6847 /* Itbl support may require additional care here. */
6848 if (! target_big_endian
)
6851 if (mips_pic
== NO_PIC
6852 || offset_expr
.X_op
== O_constant
)
6854 /* If this is a reference to a GP relative symbol, we want
6855 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6856 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6857 If we have a base register, we use this
6859 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6860 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6861 If this is not a GP relative symbol, we want
6862 lui $at,<sym> (BFD_RELOC_HI16_S)
6863 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6864 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6865 If there is a base register, we add it to $at after the
6866 lui instruction. If there is a constant, we always use
6868 if (offset_expr
.X_op
== O_symbol
6869 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6870 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6872 relax_start (offset_expr
.X_add_symbol
);
6875 tempreg
= mips_gp_register
;
6879 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6880 AT
, breg
, mips_gp_register
);
6885 /* Itbl support may require additional care here. */
6886 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6887 BFD_RELOC_GPREL16
, tempreg
);
6888 offset_expr
.X_add_number
+= 4;
6890 /* Set mips_optimize to 2 to avoid inserting an
6892 hold_mips_optimize
= mips_optimize
;
6894 /* Itbl support may require additional care here. */
6895 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6896 BFD_RELOC_GPREL16
, tempreg
);
6897 mips_optimize
= hold_mips_optimize
;
6901 /* We just generated two relocs. When tc_gen_reloc
6902 handles this case, it will skip the first reloc and
6903 handle the second. The second reloc already has an
6904 extra addend of 4, which we added above. We must
6905 subtract it out, and then subtract another 4 to make
6906 the first reloc come out right. The second reloc
6907 will come out right because we are going to add 4 to
6908 offset_expr when we build its instruction below.
6910 If we have a symbol, then we don't want to include
6911 the offset, because it will wind up being included
6912 when we generate the reloc. */
6914 if (offset_expr
.X_op
== O_constant
)
6915 offset_expr
.X_add_number
-= 8;
6918 offset_expr
.X_add_number
= -4;
6919 offset_expr
.X_op
= O_constant
;
6923 macro_build_lui (&offset_expr
, AT
);
6925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6926 /* Itbl support may require additional care here. */
6927 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6928 BFD_RELOC_LO16
, AT
);
6929 /* FIXME: How do we handle overflow here? */
6930 offset_expr
.X_add_number
+= 4;
6931 /* Itbl support may require additional care here. */
6932 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6933 BFD_RELOC_LO16
, AT
);
6934 if (mips_relax
.sequence
)
6937 else if (!mips_big_got
)
6939 /* If this is a reference to an external symbol, we want
6940 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6945 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6947 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6948 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6949 If there is a base register we add it to $at before the
6950 lwc1 instructions. If there is a constant we include it
6951 in the lwc1 instructions. */
6953 expr1
.X_add_number
= offset_expr
.X_add_number
;
6954 if (expr1
.X_add_number
< -0x8000
6955 || expr1
.X_add_number
>= 0x8000 - 4)
6956 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6957 load_got_offset (AT
, &offset_expr
);
6960 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6962 /* Set mips_optimize to 2 to avoid inserting an undesired
6964 hold_mips_optimize
= mips_optimize
;
6967 /* Itbl support may require additional care here. */
6968 relax_start (offset_expr
.X_add_symbol
);
6969 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6970 BFD_RELOC_LO16
, AT
);
6971 expr1
.X_add_number
+= 4;
6972 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6973 BFD_RELOC_LO16
, AT
);
6975 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6976 BFD_RELOC_LO16
, AT
);
6977 offset_expr
.X_add_number
+= 4;
6978 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6979 BFD_RELOC_LO16
, AT
);
6982 mips_optimize
= hold_mips_optimize
;
6984 else if (mips_big_got
)
6988 /* If this is a reference to an external symbol, we want
6989 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6991 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6996 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6998 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6999 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7000 If there is a base register we add it to $at before the
7001 lwc1 instructions. If there is a constant we include it
7002 in the lwc1 instructions. */
7004 expr1
.X_add_number
= offset_expr
.X_add_number
;
7005 offset_expr
.X_add_number
= 0;
7006 if (expr1
.X_add_number
< -0x8000
7007 || expr1
.X_add_number
>= 0x8000 - 4)
7008 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7009 gpdelay
= reg_needs_delay (mips_gp_register
);
7010 relax_start (offset_expr
.X_add_symbol
);
7011 macro_build (&offset_expr
, "lui", "t,u",
7012 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7013 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7014 AT
, AT
, mips_gp_register
);
7015 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7016 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7020 /* Itbl support may require additional care here. */
7021 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7022 BFD_RELOC_LO16
, AT
);
7023 expr1
.X_add_number
+= 4;
7025 /* Set mips_optimize to 2 to avoid inserting an undesired
7027 hold_mips_optimize
= mips_optimize
;
7029 /* Itbl support may require additional care here. */
7030 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7031 BFD_RELOC_LO16
, AT
);
7032 mips_optimize
= hold_mips_optimize
;
7033 expr1
.X_add_number
-= 4;
7036 offset_expr
.X_add_number
= expr1
.X_add_number
;
7038 macro_build (NULL
, "nop", "");
7039 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7040 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7044 /* Itbl support may require additional care here. */
7045 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7046 BFD_RELOC_LO16
, AT
);
7047 offset_expr
.X_add_number
+= 4;
7049 /* Set mips_optimize to 2 to avoid inserting an undesired
7051 hold_mips_optimize
= mips_optimize
;
7053 /* Itbl support may require additional care here. */
7054 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7055 BFD_RELOC_LO16
, AT
);
7056 mips_optimize
= hold_mips_optimize
;
7070 assert (HAVE_32BIT_ADDRESSES
);
7071 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7072 offset_expr
.X_add_number
+= 4;
7073 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7076 /* New code added to support COPZ instructions.
7077 This code builds table entries out of the macros in mip_opcodes.
7078 R4000 uses interlocks to handle coproc delays.
7079 Other chips (like the R3000) require nops to be inserted for delays.
7081 FIXME: Currently, we require that the user handle delays.
7082 In order to fill delay slots for non-interlocked chips,
7083 we must have a way to specify delays based on the coprocessor.
7084 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7085 What are the side-effects of the cop instruction?
7086 What cache support might we have and what are its effects?
7087 Both coprocessor & memory require delays. how long???
7088 What registers are read/set/modified?
7090 If an itbl is provided to interpret cop instructions,
7091 this knowledge can be encoded in the itbl spec. */
7105 /* For now we just do C (same as Cz). The parameter will be
7106 stored in insn_opcode by mips_ip. */
7107 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7111 move_register (dreg
, sreg
);
7114 #ifdef LOSING_COMPILER
7116 /* Try and see if this is a new itbl instruction.
7117 This code builds table entries out of the macros in mip_opcodes.
7118 FIXME: For now we just assemble the expression and pass it's
7119 value along as a 32-bit immediate.
7120 We may want to have the assembler assemble this value,
7121 so that we gain the assembler's knowledge of delay slots,
7123 Would it be more efficient to use mask (id) here? */
7124 if (itbl_have_entries
7125 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7127 s
= ip
->insn_mo
->name
;
7129 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7130 macro_build (&immed_expr
, s
, "C");
7136 if (mips_opts
.noat
&& used_at
)
7137 as_bad (_("Macro used $at after \".set noat\""));
7141 macro2 (struct mips_cl_insn
*ip
)
7143 int treg
, sreg
, dreg
, breg
;
7158 bfd_reloc_code_real_type r
;
7160 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7161 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7162 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7163 mask
= ip
->insn_mo
->mask
;
7165 expr1
.X_op
= O_constant
;
7166 expr1
.X_op_symbol
= NULL
;
7167 expr1
.X_add_symbol
= NULL
;
7168 expr1
.X_add_number
= 1;
7172 #endif /* LOSING_COMPILER */
7177 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7178 macro_build (NULL
, "mflo", "d", dreg
);
7184 /* The MIPS assembler some times generates shifts and adds. I'm
7185 not trying to be that fancy. GCC should do this for us
7188 load_register (AT
, &imm_expr
, dbl
);
7189 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7190 macro_build (NULL
, "mflo", "d", dreg
);
7206 load_register (AT
, &imm_expr
, dbl
);
7207 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7208 macro_build (NULL
, "mflo", "d", dreg
);
7209 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7210 macro_build (NULL
, "mfhi", "d", AT
);
7212 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7215 expr1
.X_add_number
= 8;
7216 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7217 macro_build (NULL
, "nop", "", 0);
7218 macro_build (NULL
, "break", "c", 6);
7221 macro_build (NULL
, "mflo", "d", dreg
);
7237 load_register (AT
, &imm_expr
, dbl
);
7238 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7239 sreg
, imm
? AT
: treg
);
7240 macro_build (NULL
, "mfhi", "d", AT
);
7241 macro_build (NULL
, "mflo", "d", dreg
);
7243 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7246 expr1
.X_add_number
= 8;
7247 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7248 macro_build (NULL
, "nop", "", 0);
7249 macro_build (NULL
, "break", "c", 6);
7255 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7266 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7267 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7271 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7272 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7273 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7274 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7278 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7289 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7290 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7294 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7295 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7296 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7297 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7305 if (imm_expr
.X_op
!= O_constant
)
7306 as_bad (_("Improper rotate count"));
7307 rot
= imm_expr
.X_add_number
& 0x3f;
7308 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7310 rot
= (64 - rot
) & 0x3f;
7312 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7314 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7319 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7322 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7323 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7326 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7327 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7328 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7336 if (imm_expr
.X_op
!= O_constant
)
7337 as_bad (_("Improper rotate count"));
7338 rot
= imm_expr
.X_add_number
& 0x1f;
7339 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7341 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7346 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7350 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7351 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7352 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7357 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7359 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7363 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7364 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7365 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7366 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7370 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7372 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7376 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7377 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7378 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7379 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7387 if (imm_expr
.X_op
!= O_constant
)
7388 as_bad (_("Improper rotate count"));
7389 rot
= imm_expr
.X_add_number
& 0x3f;
7390 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7393 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7395 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7400 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7403 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7404 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7407 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7408 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7409 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7417 if (imm_expr
.X_op
!= O_constant
)
7418 as_bad (_("Improper rotate count"));
7419 rot
= imm_expr
.X_add_number
& 0x1f;
7420 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7422 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7427 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7431 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7432 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7433 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7438 if (mips_opts
.arch
== CPU_R4650
)
7440 as_bad (_("opcode not supported on this processor"));
7443 assert (mips_opts
.isa
== ISA_MIPS1
);
7444 /* Even on a big endian machine $fn comes before $fn+1. We have
7445 to adjust when storing to memory. */
7446 macro_build (&offset_expr
, "swc1", "T,o(b)",
7447 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7448 offset_expr
.X_add_number
+= 4;
7449 macro_build (&offset_expr
, "swc1", "T,o(b)",
7450 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7455 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7457 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7460 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7461 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7466 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7468 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7473 as_warn (_("Instruction %s: result is always false"),
7475 move_register (dreg
, 0);
7478 if (imm_expr
.X_op
== O_constant
7479 && imm_expr
.X_add_number
>= 0
7480 && imm_expr
.X_add_number
< 0x10000)
7482 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7484 else if (imm_expr
.X_op
== O_constant
7485 && imm_expr
.X_add_number
> -0x8000
7486 && imm_expr
.X_add_number
< 0)
7488 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7489 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7490 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7494 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7495 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7498 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7501 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7507 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7508 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7511 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7513 if (imm_expr
.X_op
== O_constant
7514 && imm_expr
.X_add_number
>= -0x8000
7515 && imm_expr
.X_add_number
< 0x8000)
7517 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7518 dreg
, sreg
, BFD_RELOC_LO16
);
7522 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7523 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7527 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7530 case M_SGT
: /* sreg > treg <==> treg < sreg */
7536 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7539 case M_SGT_I
: /* sreg > I <==> I < sreg */
7546 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7547 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7550 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7556 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7557 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7560 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7567 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7568 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7569 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7573 if (imm_expr
.X_op
== O_constant
7574 && imm_expr
.X_add_number
>= -0x8000
7575 && imm_expr
.X_add_number
< 0x8000)
7577 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7581 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7582 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7586 if (imm_expr
.X_op
== O_constant
7587 && imm_expr
.X_add_number
>= -0x8000
7588 && imm_expr
.X_add_number
< 0x8000)
7590 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7595 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7596 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7601 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7603 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7606 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7607 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7612 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7614 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7619 as_warn (_("Instruction %s: result is always true"),
7621 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7622 dreg
, 0, BFD_RELOC_LO16
);
7625 if (imm_expr
.X_op
== O_constant
7626 && imm_expr
.X_add_number
>= 0
7627 && imm_expr
.X_add_number
< 0x10000)
7629 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7631 else if (imm_expr
.X_op
== O_constant
7632 && imm_expr
.X_add_number
> -0x8000
7633 && imm_expr
.X_add_number
< 0)
7635 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7636 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7637 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7641 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7642 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7645 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7651 if (imm_expr
.X_op
== O_constant
7652 && imm_expr
.X_add_number
> -0x8000
7653 && imm_expr
.X_add_number
<= 0x8000)
7655 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7656 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7657 dreg
, sreg
, BFD_RELOC_LO16
);
7661 load_register (AT
, &imm_expr
, dbl
);
7662 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7668 if (imm_expr
.X_op
== O_constant
7669 && imm_expr
.X_add_number
> -0x8000
7670 && imm_expr
.X_add_number
<= 0x8000)
7672 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7673 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7674 dreg
, sreg
, BFD_RELOC_LO16
);
7678 load_register (AT
, &imm_expr
, dbl
);
7679 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7701 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7702 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7707 assert (mips_opts
.isa
== ISA_MIPS1
);
7709 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7710 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7713 * Is the double cfc1 instruction a bug in the mips assembler;
7714 * or is there a reason for it?
7717 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7718 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7719 macro_build (NULL
, "nop", "");
7720 expr1
.X_add_number
= 3;
7721 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7722 expr1
.X_add_number
= 2;
7723 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7724 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7725 macro_build (NULL
, "nop", "");
7726 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7728 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7729 macro_build (NULL
, "nop", "");
7740 if (offset_expr
.X_add_number
>= 0x7fff)
7741 as_bad (_("operand overflow"));
7742 if (! target_big_endian
)
7743 ++offset_expr
.X_add_number
;
7744 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7745 if (! target_big_endian
)
7746 --offset_expr
.X_add_number
;
7748 ++offset_expr
.X_add_number
;
7749 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7750 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7751 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7764 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7765 as_bad (_("operand overflow"));
7773 if (! target_big_endian
)
7774 offset_expr
.X_add_number
+= off
;
7775 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7776 if (! target_big_endian
)
7777 offset_expr
.X_add_number
-= off
;
7779 offset_expr
.X_add_number
+= off
;
7780 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7782 /* If necessary, move the result in tempreg the final destination. */
7783 if (treg
== tempreg
)
7785 /* Protect second load's delay slot. */
7787 move_register (treg
, tempreg
);
7801 load_address (AT
, &offset_expr
, &used_at
);
7803 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7804 if (! target_big_endian
)
7805 expr1
.X_add_number
= off
;
7807 expr1
.X_add_number
= 0;
7808 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7809 if (! target_big_endian
)
7810 expr1
.X_add_number
= 0;
7812 expr1
.X_add_number
= off
;
7813 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7819 load_address (AT
, &offset_expr
, &used_at
);
7821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7822 if (target_big_endian
)
7823 expr1
.X_add_number
= 0;
7824 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7825 treg
, BFD_RELOC_LO16
, AT
);
7826 if (target_big_endian
)
7827 expr1
.X_add_number
= 1;
7829 expr1
.X_add_number
= 0;
7830 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7831 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7832 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7837 if (offset_expr
.X_add_number
>= 0x7fff)
7838 as_bad (_("operand overflow"));
7839 if (target_big_endian
)
7840 ++offset_expr
.X_add_number
;
7841 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7842 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7843 if (target_big_endian
)
7844 --offset_expr
.X_add_number
;
7846 ++offset_expr
.X_add_number
;
7847 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7860 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7861 as_bad (_("operand overflow"));
7862 if (! target_big_endian
)
7863 offset_expr
.X_add_number
+= off
;
7864 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7865 if (! target_big_endian
)
7866 offset_expr
.X_add_number
-= off
;
7868 offset_expr
.X_add_number
+= off
;
7869 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7883 load_address (AT
, &offset_expr
, &used_at
);
7885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7886 if (! target_big_endian
)
7887 expr1
.X_add_number
= off
;
7889 expr1
.X_add_number
= 0;
7890 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7891 if (! target_big_endian
)
7892 expr1
.X_add_number
= 0;
7894 expr1
.X_add_number
= off
;
7895 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7900 load_address (AT
, &offset_expr
, &used_at
);
7902 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7903 if (! target_big_endian
)
7904 expr1
.X_add_number
= 0;
7905 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7906 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7907 if (! target_big_endian
)
7908 expr1
.X_add_number
= 1;
7910 expr1
.X_add_number
= 0;
7911 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7912 if (! target_big_endian
)
7913 expr1
.X_add_number
= 0;
7915 expr1
.X_add_number
= 1;
7916 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7917 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7918 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7922 /* FIXME: Check if this is one of the itbl macros, since they
7923 are added dynamically. */
7924 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7927 if (mips_opts
.noat
&& used_at
)
7928 as_bad (_("Macro used $at after \".set noat\""));
7931 /* Implement macros in mips16 mode. */
7934 mips16_macro (struct mips_cl_insn
*ip
)
7937 int xreg
, yreg
, zreg
, tmp
;
7940 const char *s
, *s2
, *s3
;
7942 mask
= ip
->insn_mo
->mask
;
7944 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7945 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7946 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7948 expr1
.X_op
= O_constant
;
7949 expr1
.X_op_symbol
= NULL
;
7950 expr1
.X_add_symbol
= NULL
;
7951 expr1
.X_add_number
= 1;
7971 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7972 expr1
.X_add_number
= 2;
7973 macro_build (&expr1
, "bnez", "x,p", yreg
);
7974 macro_build (NULL
, "break", "6", 7);
7976 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7977 since that causes an overflow. We should do that as well,
7978 but I don't see how to do the comparisons without a temporary
7981 macro_build (NULL
, s
, "x", zreg
);
8001 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8002 expr1
.X_add_number
= 2;
8003 macro_build (&expr1
, "bnez", "x,p", yreg
);
8004 macro_build (NULL
, "break", "6", 7);
8006 macro_build (NULL
, s2
, "x", zreg
);
8012 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8013 macro_build (NULL
, "mflo", "x", zreg
);
8021 if (imm_expr
.X_op
!= O_constant
)
8022 as_bad (_("Unsupported large constant"));
8023 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8024 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8028 if (imm_expr
.X_op
!= O_constant
)
8029 as_bad (_("Unsupported large constant"));
8030 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8031 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8035 if (imm_expr
.X_op
!= O_constant
)
8036 as_bad (_("Unsupported large constant"));
8037 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8038 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8060 goto do_reverse_branch
;
8064 goto do_reverse_branch
;
8076 goto do_reverse_branch
;
8087 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8088 macro_build (&offset_expr
, s2
, "p");
8115 goto do_addone_branch_i
;
8120 goto do_addone_branch_i
;
8135 goto do_addone_branch_i
;
8142 if (imm_expr
.X_op
!= O_constant
)
8143 as_bad (_("Unsupported large constant"));
8144 ++imm_expr
.X_add_number
;
8147 macro_build (&imm_expr
, s
, s3
, xreg
);
8148 macro_build (&offset_expr
, s2
, "p");
8152 expr1
.X_add_number
= 0;
8153 macro_build (&expr1
, "slti", "x,8", yreg
);
8155 move_register (xreg
, yreg
);
8156 expr1
.X_add_number
= 2;
8157 macro_build (&expr1
, "bteqz", "p");
8158 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8162 /* For consistency checking, verify that all bits are specified either
8163 by the match/mask part of the instruction definition, or by the
8166 validate_mips_insn (const struct mips_opcode
*opc
)
8168 const char *p
= opc
->args
;
8170 unsigned long used_bits
= opc
->mask
;
8172 if ((used_bits
& opc
->match
) != opc
->match
)
8174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8175 opc
->name
, opc
->args
);
8178 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8188 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8189 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8190 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8191 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8192 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8193 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8194 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8195 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8196 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8197 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8198 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8199 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8200 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8202 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8203 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8204 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8206 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8207 c
, opc
->name
, opc
->args
);
8211 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8212 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8214 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8215 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8216 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8217 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8219 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8220 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8222 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8223 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8225 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8226 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8227 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8228 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8229 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8230 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8231 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8232 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8233 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8234 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8235 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8236 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8237 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8238 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8239 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8240 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8241 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8243 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8244 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8245 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8246 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8248 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8249 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8250 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8251 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8252 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8253 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8254 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8255 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8256 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8259 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8260 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8261 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8262 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8263 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8266 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8267 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8268 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8269 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8270 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8271 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8272 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8273 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8274 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8275 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8276 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8277 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8278 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8279 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8280 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8281 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8282 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8284 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8285 c
, opc
->name
, opc
->args
);
8289 if (used_bits
!= 0xffffffff)
8291 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8292 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8298 /* UDI immediates. */
8306 static const struct mips_immed mips_immed
[] = {
8307 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8308 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8309 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8310 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8314 /* Check whether an odd floating-point register is allowed. */
8316 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8318 const char *s
= insn
->name
;
8320 if (insn
->pinfo
== INSN_MACRO
)
8321 /* Let a macro pass, we'll catch it later when it is expanded. */
8324 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8326 /* Allow odd registers for single-precision ops. */
8327 switch (insn
->pinfo
& (FP_S
| FP_D
))
8331 return 1; /* both single precision - ok */
8333 return 0; /* both double precision - fail */
8338 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8339 s
= strchr (insn
->name
, '.');
8341 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8342 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8345 /* Single-precision coprocessor loads and moves are OK too. */
8346 if ((insn
->pinfo
& FP_S
)
8347 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8348 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8354 /* This routine assembles an instruction into its binary format. As a
8355 side effect, it sets one of the global variables imm_reloc or
8356 offset_reloc to the type of relocation to do if one of the operands
8357 is an address expression. */
8360 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8365 struct mips_opcode
*insn
;
8368 unsigned int lastregno
= 0;
8369 unsigned int lastpos
= 0;
8370 unsigned int limlo
, limhi
;
8373 offsetT min_range
, max_range
;
8379 /* If the instruction contains a '.', we first try to match an instruction
8380 including the '.'. Then we try again without the '.'. */
8382 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8385 /* If we stopped on whitespace, then replace the whitespace with null for
8386 the call to hash_find. Save the character we replaced just in case we
8387 have to re-parse the instruction. */
8394 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8396 /* If we didn't find the instruction in the opcode table, try again, but
8397 this time with just the instruction up to, but not including the
8401 /* Restore the character we overwrite above (if any). */
8405 /* Scan up to the first '.' or whitespace. */
8407 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8411 /* If we did not find a '.', then we can quit now. */
8414 insn_error
= "unrecognized opcode";
8418 /* Lookup the instruction in the hash table. */
8420 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8422 insn_error
= "unrecognized opcode";
8432 assert (strcmp (insn
->name
, str
) == 0);
8434 if (OPCODE_IS_MEMBER (insn
,
8436 /* We don't check for mips_opts.mips16 here since
8437 we want to allow jalx if -mips16 was specified
8438 on the command line. */
8439 | (file_ase_mips16
? INSN_MIPS16
: 0)
8440 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8441 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8442 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
8444 | (mips_opts
.ase_dspr2
? INSN_DSPR2
: 0)
8445 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8446 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8447 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8453 if (insn
->pinfo
!= INSN_MACRO
)
8455 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8461 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8462 && strcmp (insn
->name
, insn
[1].name
) == 0)
8471 static char buf
[100];
8473 _("opcode not supported on this processor: %s (%s)"),
8474 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8475 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8484 create_insn (ip
, insn
);
8487 for (args
= insn
->args
;; ++args
)
8491 s
+= strspn (s
, " \t");
8495 case '\0': /* end of args */
8500 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8501 my_getExpression (&imm_expr
, s
);
8502 check_absolute_expr (ip
, &imm_expr
);
8503 if ((unsigned long) imm_expr
.X_add_number
!= 1
8504 && (unsigned long) imm_expr
.X_add_number
!= 3)
8506 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8507 (unsigned long) imm_expr
.X_add_number
);
8509 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8510 imm_expr
.X_op
= O_absent
;
8514 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8515 my_getExpression (&imm_expr
, s
);
8516 check_absolute_expr (ip
, &imm_expr
);
8517 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8519 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8520 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8522 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8523 imm_expr
.X_op
= O_absent
;
8527 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8528 my_getExpression (&imm_expr
, s
);
8529 check_absolute_expr (ip
, &imm_expr
);
8530 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8532 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8533 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8535 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8536 imm_expr
.X_op
= O_absent
;
8540 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8541 my_getExpression (&imm_expr
, s
);
8542 check_absolute_expr (ip
, &imm_expr
);
8543 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8545 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8546 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8548 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8549 imm_expr
.X_op
= O_absent
;
8553 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8554 my_getExpression (&imm_expr
, s
);
8555 check_absolute_expr (ip
, &imm_expr
);
8556 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8558 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8559 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8561 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8562 imm_expr
.X_op
= O_absent
;
8566 case '7': /* four dsp accumulators in bits 11,12 */
8567 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8568 s
[3] >= '0' && s
[3] <= '3')
8572 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8576 as_bad (_("Invalid dsp acc register"));
8579 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8580 my_getExpression (&imm_expr
, s
);
8581 check_absolute_expr (ip
, &imm_expr
);
8582 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8584 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8586 (unsigned long) imm_expr
.X_add_number
);
8588 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8589 imm_expr
.X_op
= O_absent
;
8593 case '9': /* four dsp accumulators in bits 21,22 */
8594 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8595 s
[3] >= '0' && s
[3] <= '3')
8599 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8603 as_bad (_("Invalid dsp acc register"));
8606 case '0': /* dsp 6-bit signed immediate in bit 20 */
8607 my_getExpression (&imm_expr
, s
);
8608 check_absolute_expr (ip
, &imm_expr
);
8609 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8610 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8611 if (imm_expr
.X_add_number
< min_range
||
8612 imm_expr
.X_add_number
> max_range
)
8614 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8615 (long) min_range
, (long) max_range
,
8616 (long) imm_expr
.X_add_number
);
8618 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8619 imm_expr
.X_op
= O_absent
;
8623 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8624 my_getExpression (&imm_expr
, s
);
8625 check_absolute_expr (ip
, &imm_expr
);
8626 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8628 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8630 (unsigned long) imm_expr
.X_add_number
);
8632 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8633 imm_expr
.X_op
= O_absent
;
8637 case ':': /* dsp 7-bit signed immediate in bit 19 */
8638 my_getExpression (&imm_expr
, s
);
8639 check_absolute_expr (ip
, &imm_expr
);
8640 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8641 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8642 if (imm_expr
.X_add_number
< min_range
||
8643 imm_expr
.X_add_number
> max_range
)
8645 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8646 (long) min_range
, (long) max_range
,
8647 (long) imm_expr
.X_add_number
);
8649 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8650 imm_expr
.X_op
= O_absent
;
8654 case '@': /* dsp 10-bit signed immediate in bit 16 */
8655 my_getExpression (&imm_expr
, s
);
8656 check_absolute_expr (ip
, &imm_expr
);
8657 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8658 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8659 if (imm_expr
.X_add_number
< min_range
||
8660 imm_expr
.X_add_number
> max_range
)
8662 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8663 (long) min_range
, (long) max_range
,
8664 (long) imm_expr
.X_add_number
);
8666 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8667 imm_expr
.X_op
= O_absent
;
8671 case '!': /* MT usermode flag bit. */
8672 my_getExpression (&imm_expr
, s
);
8673 check_absolute_expr (ip
, &imm_expr
);
8674 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8675 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8676 (unsigned long) imm_expr
.X_add_number
);
8677 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8678 imm_expr
.X_op
= O_absent
;
8682 case '$': /* MT load high flag bit. */
8683 my_getExpression (&imm_expr
, s
);
8684 check_absolute_expr (ip
, &imm_expr
);
8685 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8686 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8687 (unsigned long) imm_expr
.X_add_number
);
8688 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8689 imm_expr
.X_op
= O_absent
;
8693 case '*': /* four dsp accumulators in bits 18,19 */
8694 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8695 s
[3] >= '0' && s
[3] <= '3')
8699 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8703 as_bad (_("Invalid dsp/smartmips acc register"));
8706 case '&': /* four dsp accumulators in bits 13,14 */
8707 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8708 s
[3] >= '0' && s
[3] <= '3')
8712 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8716 as_bad (_("Invalid dsp/smartmips acc register"));
8728 INSERT_OPERAND (RS
, *ip
, lastregno
);
8732 INSERT_OPERAND (RT
, *ip
, lastregno
);
8736 INSERT_OPERAND (FT
, *ip
, lastregno
);
8740 INSERT_OPERAND (FS
, *ip
, lastregno
);
8746 /* Handle optional base register.
8747 Either the base register is omitted or
8748 we must have a left paren. */
8749 /* This is dependent on the next operand specifier
8750 is a base register specification. */
8751 assert (args
[1] == 'b' || args
[1] == '5'
8752 || args
[1] == '-' || args
[1] == '4');
8756 case ')': /* these must match exactly */
8763 case '+': /* Opcode extension character. */
8766 case '1': /* UDI immediates. */
8771 const struct mips_immed
*imm
= mips_immed
;
8773 while (imm
->type
&& imm
->type
!= *args
)
8777 my_getExpression (&imm_expr
, s
);
8778 check_absolute_expr (ip
, &imm_expr
);
8779 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8781 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8782 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8783 (unsigned long) imm_expr
.X_add_number
,
8784 (unsigned long) imm_expr
.X_add_number
);
8785 imm_expr
.X_add_number
&= imm
->mask
;
8787 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8789 imm_expr
.X_op
= O_absent
;
8794 case 'A': /* ins/ext position, becomes LSB. */
8803 my_getExpression (&imm_expr
, s
);
8804 check_absolute_expr (ip
, &imm_expr
);
8805 if ((unsigned long) imm_expr
.X_add_number
< limlo
8806 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8808 as_bad (_("Improper position (%lu)"),
8809 (unsigned long) imm_expr
.X_add_number
);
8810 imm_expr
.X_add_number
= limlo
;
8812 lastpos
= imm_expr
.X_add_number
;
8813 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8814 imm_expr
.X_op
= O_absent
;
8818 case 'B': /* ins size, becomes MSB. */
8827 my_getExpression (&imm_expr
, s
);
8828 check_absolute_expr (ip
, &imm_expr
);
8829 /* Check for negative input so that small negative numbers
8830 will not succeed incorrectly. The checks against
8831 (pos+size) transitively check "size" itself,
8832 assuming that "pos" is reasonable. */
8833 if ((long) imm_expr
.X_add_number
< 0
8834 || ((unsigned long) imm_expr
.X_add_number
8836 || ((unsigned long) imm_expr
.X_add_number
8839 as_bad (_("Improper insert size (%lu, position %lu)"),
8840 (unsigned long) imm_expr
.X_add_number
,
8841 (unsigned long) lastpos
);
8842 imm_expr
.X_add_number
= limlo
- lastpos
;
8844 INSERT_OPERAND (INSMSB
, *ip
,
8845 lastpos
+ imm_expr
.X_add_number
- 1);
8846 imm_expr
.X_op
= O_absent
;
8850 case 'C': /* ext size, becomes MSBD. */
8863 my_getExpression (&imm_expr
, s
);
8864 check_absolute_expr (ip
, &imm_expr
);
8865 /* Check for negative input so that small negative numbers
8866 will not succeed incorrectly. The checks against
8867 (pos+size) transitively check "size" itself,
8868 assuming that "pos" is reasonable. */
8869 if ((long) imm_expr
.X_add_number
< 0
8870 || ((unsigned long) imm_expr
.X_add_number
8872 || ((unsigned long) imm_expr
.X_add_number
8875 as_bad (_("Improper extract size (%lu, position %lu)"),
8876 (unsigned long) imm_expr
.X_add_number
,
8877 (unsigned long) lastpos
);
8878 imm_expr
.X_add_number
= limlo
- lastpos
;
8880 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8881 imm_expr
.X_op
= O_absent
;
8886 /* +D is for disassembly only; never match. */
8890 /* "+I" is like "I", except that imm2_expr is used. */
8891 my_getExpression (&imm2_expr
, s
);
8892 if (imm2_expr
.X_op
!= O_big
8893 && imm2_expr
.X_op
!= O_constant
)
8894 insn_error
= _("absolute expression required");
8895 if (HAVE_32BIT_GPRS
)
8896 normalize_constant_expr (&imm2_expr
);
8900 case 'T': /* Coprocessor register. */
8901 /* +T is for disassembly only; never match. */
8904 case 't': /* Coprocessor register number. */
8905 if (s
[0] == '$' && ISDIGIT (s
[1]))
8915 while (ISDIGIT (*s
));
8917 as_bad (_("Invalid register number (%d)"), regno
);
8920 INSERT_OPERAND (RT
, *ip
, regno
);
8925 as_bad (_("Invalid coprocessor 0 register number"));
8929 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8930 *args
, insn
->name
, insn
->args
);
8931 /* Further processing is fruitless. */
8936 case '<': /* must be at least one digit */
8938 * According to the manual, if the shift amount is greater
8939 * than 31 or less than 0, then the shift amount should be
8940 * mod 32. In reality the mips assembler issues an error.
8941 * We issue a warning and mask out all but the low 5 bits.
8943 my_getExpression (&imm_expr
, s
);
8944 check_absolute_expr (ip
, &imm_expr
);
8945 if ((unsigned long) imm_expr
.X_add_number
> 31)
8946 as_warn (_("Improper shift amount (%lu)"),
8947 (unsigned long) imm_expr
.X_add_number
);
8948 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8949 imm_expr
.X_op
= O_absent
;
8953 case '>': /* shift amount minus 32 */
8954 my_getExpression (&imm_expr
, s
);
8955 check_absolute_expr (ip
, &imm_expr
);
8956 if ((unsigned long) imm_expr
.X_add_number
< 32
8957 || (unsigned long) imm_expr
.X_add_number
> 63)
8959 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8960 imm_expr
.X_op
= O_absent
;
8964 case 'k': /* cache code */
8965 case 'h': /* prefx code */
8966 my_getExpression (&imm_expr
, s
);
8967 check_absolute_expr (ip
, &imm_expr
);
8968 if ((unsigned long) imm_expr
.X_add_number
> 31)
8969 as_warn (_("Invalid value for `%s' (%lu)"),
8971 (unsigned long) imm_expr
.X_add_number
);
8973 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8975 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8976 imm_expr
.X_op
= O_absent
;
8980 case 'c': /* break code */
8981 my_getExpression (&imm_expr
, s
);
8982 check_absolute_expr (ip
, &imm_expr
);
8983 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
8984 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8986 (unsigned long) imm_expr
.X_add_number
);
8987 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8988 imm_expr
.X_op
= O_absent
;
8992 case 'q': /* lower break code */
8993 my_getExpression (&imm_expr
, s
);
8994 check_absolute_expr (ip
, &imm_expr
);
8995 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
8996 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
8998 (unsigned long) imm_expr
.X_add_number
);
8999 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9000 imm_expr
.X_op
= O_absent
;
9004 case 'B': /* 20-bit syscall/break code. */
9005 my_getExpression (&imm_expr
, s
);
9006 check_absolute_expr (ip
, &imm_expr
);
9007 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9008 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9010 (unsigned long) imm_expr
.X_add_number
);
9011 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9012 imm_expr
.X_op
= O_absent
;
9016 case 'C': /* Coprocessor code */
9017 my_getExpression (&imm_expr
, s
);
9018 check_absolute_expr (ip
, &imm_expr
);
9019 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9021 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9022 (unsigned long) imm_expr
.X_add_number
);
9023 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9025 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9026 imm_expr
.X_op
= O_absent
;
9030 case 'J': /* 19-bit wait code. */
9031 my_getExpression (&imm_expr
, s
);
9032 check_absolute_expr (ip
, &imm_expr
);
9033 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9035 as_warn (_("Illegal 19-bit code (%lu)"),
9036 (unsigned long) imm_expr
.X_add_number
);
9037 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9039 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9040 imm_expr
.X_op
= O_absent
;
9044 case 'P': /* Performance register. */
9045 my_getExpression (&imm_expr
, s
);
9046 check_absolute_expr (ip
, &imm_expr
);
9047 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9048 as_warn (_("Invalid performance register (%lu)"),
9049 (unsigned long) imm_expr
.X_add_number
);
9050 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9051 imm_expr
.X_op
= O_absent
;
9055 case 'G': /* Coprocessor destination register. */
9056 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9057 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9059 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9060 INSERT_OPERAND (RD
, *ip
, regno
);
9069 case 'b': /* base register */
9070 case 'd': /* destination register */
9071 case 's': /* source register */
9072 case 't': /* target register */
9073 case 'r': /* both target and source */
9074 case 'v': /* both dest and source */
9075 case 'w': /* both dest and target */
9076 case 'E': /* coprocessor target register */
9077 case 'K': /* 'rdhwr' destination register */
9078 case 'x': /* ignore register name */
9079 case 'z': /* must be zero register */
9080 case 'U': /* destination register (clo/clz). */
9081 case 'g': /* coprocessor destination register */
9083 if (*args
== 'E' || *args
== 'K')
9084 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9087 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9088 if (regno
== AT
&& ! mips_opts
.noat
)
9089 as_warn ("Used $at without \".set noat\"");
9098 if (c
== 'r' || c
== 'v' || c
== 'w')
9105 /* 'z' only matches $0. */
9106 if (c
== 'z' && regno
!= 0)
9109 /* Now that we have assembled one operand, we use the args string
9110 * to figure out where it goes in the instruction. */
9117 INSERT_OPERAND (RS
, *ip
, regno
);
9123 INSERT_OPERAND (RD
, *ip
, regno
);
9126 INSERT_OPERAND (RD
, *ip
, regno
);
9127 INSERT_OPERAND (RT
, *ip
, regno
);
9132 INSERT_OPERAND (RT
, *ip
, regno
);
9135 /* This case exists because on the r3000 trunc
9136 expands into a macro which requires a gp
9137 register. On the r6000 or r4000 it is
9138 assembled into a single instruction which
9139 ignores the register. Thus the insn version
9140 is MIPS_ISA2 and uses 'x', and the macro
9141 version is MIPS_ISA1 and uses 't'. */
9144 /* This case is for the div instruction, which
9145 acts differently if the destination argument
9146 is $0. This only matches $0, and is checked
9147 outside the switch. */
9150 /* Itbl operand; not yet implemented. FIXME ?? */
9152 /* What about all other operands like 'i', which
9153 can be specified in the opcode table? */
9162 INSERT_OPERAND (RS
, *ip
, lastregno
);
9165 INSERT_OPERAND (RT
, *ip
, lastregno
);
9170 case 'O': /* MDMX alignment immediate constant. */
9171 my_getExpression (&imm_expr
, s
);
9172 check_absolute_expr (ip
, &imm_expr
);
9173 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9174 as_warn ("Improper align amount (%ld), using low bits",
9175 (long) imm_expr
.X_add_number
);
9176 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9177 imm_expr
.X_op
= O_absent
;
9181 case 'Q': /* MDMX vector, element sel, or const. */
9184 /* MDMX Immediate. */
9185 my_getExpression (&imm_expr
, s
);
9186 check_absolute_expr (ip
, &imm_expr
);
9187 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9188 as_warn (_("Invalid MDMX Immediate (%ld)"),
9189 (long) imm_expr
.X_add_number
);
9190 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9191 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9192 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9194 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9195 imm_expr
.X_op
= O_absent
;
9199 /* Not MDMX Immediate. Fall through. */
9200 case 'X': /* MDMX destination register. */
9201 case 'Y': /* MDMX source register. */
9202 case 'Z': /* MDMX target register. */
9204 case 'D': /* floating point destination register */
9205 case 'S': /* floating point source register */
9206 case 'T': /* floating point target register */
9207 case 'R': /* floating point source register */
9212 || (mips_opts
.ase_mdmx
9213 && (ip
->insn_mo
->pinfo
& FP_D
)
9214 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9215 | INSN_COPROC_MEMORY_DELAY
9216 | INSN_LOAD_COPROC_DELAY
9217 | INSN_LOAD_MEMORY_DELAY
9218 | INSN_STORE_MEMORY
))))
9221 if (reg_lookup (&s
, rtype
, ®no
))
9223 if ((regno
& 1) != 0
9225 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9226 as_warn (_("Float register should be even, was %d"),
9234 if (c
== 'V' || c
== 'W')
9245 INSERT_OPERAND (FD
, *ip
, regno
);
9250 INSERT_OPERAND (FS
, *ip
, regno
);
9253 /* This is like 'Z', but also needs to fix the MDMX
9254 vector/scalar select bits. Note that the
9255 scalar immediate case is handled above. */
9258 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9259 int max_el
= (is_qh
? 3 : 7);
9261 my_getExpression(&imm_expr
, s
);
9262 check_absolute_expr (ip
, &imm_expr
);
9264 if (imm_expr
.X_add_number
> max_el
)
9265 as_bad(_("Bad element selector %ld"),
9266 (long) imm_expr
.X_add_number
);
9267 imm_expr
.X_add_number
&= max_el
;
9268 ip
->insn_opcode
|= (imm_expr
.X_add_number
9271 imm_expr
.X_op
= O_absent
;
9273 as_warn(_("Expecting ']' found '%s'"), s
);
9279 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9280 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9283 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9290 INSERT_OPERAND (FT
, *ip
, regno
);
9293 INSERT_OPERAND (FR
, *ip
, regno
);
9303 INSERT_OPERAND (FS
, *ip
, lastregno
);
9306 INSERT_OPERAND (FT
, *ip
, lastregno
);
9312 my_getExpression (&imm_expr
, s
);
9313 if (imm_expr
.X_op
!= O_big
9314 && imm_expr
.X_op
!= O_constant
)
9315 insn_error
= _("absolute expression required");
9316 if (HAVE_32BIT_GPRS
)
9317 normalize_constant_expr (&imm_expr
);
9322 my_getExpression (&offset_expr
, s
);
9323 normalize_address_expr (&offset_expr
);
9324 *imm_reloc
= BFD_RELOC_32
;
9337 unsigned char temp
[8];
9339 unsigned int length
;
9344 /* These only appear as the last operand in an
9345 instruction, and every instruction that accepts
9346 them in any variant accepts them in all variants.
9347 This means we don't have to worry about backing out
9348 any changes if the instruction does not match.
9350 The difference between them is the size of the
9351 floating point constant and where it goes. For 'F'
9352 and 'L' the constant is 64 bits; for 'f' and 'l' it
9353 is 32 bits. Where the constant is placed is based
9354 on how the MIPS assembler does things:
9357 f -- immediate value
9360 The .lit4 and .lit8 sections are only used if
9361 permitted by the -G argument.
9363 The code below needs to know whether the target register
9364 is 32 or 64 bits wide. It relies on the fact 'f' and
9365 'F' are used with GPR-based instructions and 'l' and
9366 'L' are used with FPR-based instructions. */
9368 f64
= *args
== 'F' || *args
== 'L';
9369 using_gprs
= *args
== 'F' || *args
== 'f';
9371 save_in
= input_line_pointer
;
9372 input_line_pointer
= s
;
9373 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9375 s
= input_line_pointer
;
9376 input_line_pointer
= save_in
;
9377 if (err
!= NULL
&& *err
!= '\0')
9379 as_bad (_("Bad floating point constant: %s"), err
);
9380 memset (temp
, '\0', sizeof temp
);
9381 length
= f64
? 8 : 4;
9384 assert (length
== (unsigned) (f64
? 8 : 4));
9388 && (g_switch_value
< 4
9389 || (temp
[0] == 0 && temp
[1] == 0)
9390 || (temp
[2] == 0 && temp
[3] == 0))))
9392 imm_expr
.X_op
= O_constant
;
9393 if (! target_big_endian
)
9394 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9396 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9399 && ! mips_disable_float_construction
9400 /* Constants can only be constructed in GPRs and
9401 copied to FPRs if the GPRs are at least as wide
9402 as the FPRs. Force the constant into memory if
9403 we are using 64-bit FPRs but the GPRs are only
9406 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9407 && ((temp
[0] == 0 && temp
[1] == 0)
9408 || (temp
[2] == 0 && temp
[3] == 0))
9409 && ((temp
[4] == 0 && temp
[5] == 0)
9410 || (temp
[6] == 0 && temp
[7] == 0)))
9412 /* The value is simple enough to load with a couple of
9413 instructions. If using 32-bit registers, set
9414 imm_expr to the high order 32 bits and offset_expr to
9415 the low order 32 bits. Otherwise, set imm_expr to
9416 the entire 64 bit constant. */
9417 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9419 imm_expr
.X_op
= O_constant
;
9420 offset_expr
.X_op
= O_constant
;
9421 if (! target_big_endian
)
9423 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9424 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9428 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9429 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9431 if (offset_expr
.X_add_number
== 0)
9432 offset_expr
.X_op
= O_absent
;
9434 else if (sizeof (imm_expr
.X_add_number
) > 4)
9436 imm_expr
.X_op
= O_constant
;
9437 if (! target_big_endian
)
9438 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9440 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9444 imm_expr
.X_op
= O_big
;
9445 imm_expr
.X_add_number
= 4;
9446 if (! target_big_endian
)
9448 generic_bignum
[0] = bfd_getl16 (temp
);
9449 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9450 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9451 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9455 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9456 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9457 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9458 generic_bignum
[3] = bfd_getb16 (temp
);
9464 const char *newname
;
9467 /* Switch to the right section. */
9469 subseg
= now_subseg
;
9472 default: /* unused default case avoids warnings. */
9474 newname
= RDATA_SECTION_NAME
;
9475 if (g_switch_value
>= 8)
9479 newname
= RDATA_SECTION_NAME
;
9482 assert (g_switch_value
>= 4);
9486 new_seg
= subseg_new (newname
, (subsegT
) 0);
9488 bfd_set_section_flags (stdoutput
, new_seg
,
9493 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9494 if (IS_ELF
&& strcmp (TARGET_OS
, "elf") != 0)
9495 record_alignment (new_seg
, 4);
9497 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9499 as_bad (_("Can't use floating point insn in this section"));
9501 /* Set the argument to the current address in the
9503 offset_expr
.X_op
= O_symbol
;
9504 offset_expr
.X_add_symbol
=
9505 symbol_new ("L0\001", now_seg
,
9506 (valueT
) frag_now_fix (), frag_now
);
9507 offset_expr
.X_add_number
= 0;
9509 /* Put the floating point number into the section. */
9510 p
= frag_more ((int) length
);
9511 memcpy (p
, temp
, length
);
9513 /* Switch back to the original section. */
9514 subseg_set (seg
, subseg
);
9519 case 'i': /* 16 bit unsigned immediate */
9520 case 'j': /* 16 bit signed immediate */
9521 *imm_reloc
= BFD_RELOC_LO16
;
9522 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9525 offsetT minval
, maxval
;
9527 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9528 && strcmp (insn
->name
, insn
[1].name
) == 0);
9530 /* If the expression was written as an unsigned number,
9531 only treat it as signed if there are no more
9535 && sizeof (imm_expr
.X_add_number
) <= 4
9536 && imm_expr
.X_op
== O_constant
9537 && imm_expr
.X_add_number
< 0
9538 && imm_expr
.X_unsigned
9542 /* For compatibility with older assemblers, we accept
9543 0x8000-0xffff as signed 16-bit numbers when only
9544 signed numbers are allowed. */
9546 minval
= 0, maxval
= 0xffff;
9548 minval
= -0x8000, maxval
= 0x7fff;
9550 minval
= -0x8000, maxval
= 0xffff;
9552 if (imm_expr
.X_op
!= O_constant
9553 || imm_expr
.X_add_number
< minval
9554 || imm_expr
.X_add_number
> maxval
)
9558 if (imm_expr
.X_op
== O_constant
9559 || imm_expr
.X_op
== O_big
)
9560 as_bad (_("expression out of range"));
9566 case 'o': /* 16 bit offset */
9567 /* Check whether there is only a single bracketed expression
9568 left. If so, it must be the base register and the
9569 constant must be zero. */
9570 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9572 offset_expr
.X_op
= O_constant
;
9573 offset_expr
.X_add_number
= 0;
9577 /* If this value won't fit into a 16 bit offset, then go
9578 find a macro that will generate the 32 bit offset
9580 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9581 && (offset_expr
.X_op
!= O_constant
9582 || offset_expr
.X_add_number
>= 0x8000
9583 || offset_expr
.X_add_number
< -0x8000))
9589 case 'p': /* pc relative offset */
9590 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9591 my_getExpression (&offset_expr
, s
);
9595 case 'u': /* upper 16 bits */
9596 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9597 && imm_expr
.X_op
== O_constant
9598 && (imm_expr
.X_add_number
< 0
9599 || imm_expr
.X_add_number
>= 0x10000))
9600 as_bad (_("lui expression not in range 0..65535"));
9604 case 'a': /* 26 bit address */
9605 my_getExpression (&offset_expr
, s
);
9607 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9610 case 'N': /* 3 bit branch condition code */
9611 case 'M': /* 3 bit compare condition code */
9613 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9615 if (!reg_lookup (&s
, rtype
, ®no
))
9617 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9618 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9619 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9620 && (regno
& 1) != 0)
9621 as_warn(_("Condition code register should be even for %s, was %d"),
9623 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9624 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9625 && (regno
& 3) != 0)
9626 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9629 INSERT_OPERAND (BCC
, *ip
, regno
);
9631 INSERT_OPERAND (CCC
, *ip
, regno
);
9635 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9646 while (ISDIGIT (*s
));
9649 c
= 8; /* Invalid sel value. */
9652 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9653 ip
->insn_opcode
|= c
;
9657 /* Must be at least one digit. */
9658 my_getExpression (&imm_expr
, s
);
9659 check_absolute_expr (ip
, &imm_expr
);
9661 if ((unsigned long) imm_expr
.X_add_number
9662 > (unsigned long) OP_MASK_VECBYTE
)
9664 as_bad (_("bad byte vector index (%ld)"),
9665 (long) imm_expr
.X_add_number
);
9666 imm_expr
.X_add_number
= 0;
9669 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9670 imm_expr
.X_op
= O_absent
;
9675 my_getExpression (&imm_expr
, s
);
9676 check_absolute_expr (ip
, &imm_expr
);
9678 if ((unsigned long) imm_expr
.X_add_number
9679 > (unsigned long) OP_MASK_VECALIGN
)
9681 as_bad (_("bad byte vector index (%ld)"),
9682 (long) imm_expr
.X_add_number
);
9683 imm_expr
.X_add_number
= 0;
9686 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9687 imm_expr
.X_op
= O_absent
;
9692 as_bad (_("bad char = '%c'\n"), *args
);
9697 /* Args don't match. */
9698 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9699 !strcmp (insn
->name
, insn
[1].name
))
9703 insn_error
= _("illegal operands");
9708 insn_error
= _("illegal operands");
9713 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9715 /* This routine assembles an instruction into its binary format when
9716 assembling for the mips16. As a side effect, it sets one of the
9717 global variables imm_reloc or offset_reloc to the type of
9718 relocation to do if one of the operands is an address expression.
9719 It also sets mips16_small and mips16_ext if the user explicitly
9720 requested a small or extended instruction. */
9723 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9727 struct mips_opcode
*insn
;
9730 unsigned int lastregno
= 0;
9736 mips16_small
= FALSE
;
9739 for (s
= str
; ISLOWER (*s
); ++s
)
9751 if (s
[1] == 't' && s
[2] == ' ')
9754 mips16_small
= TRUE
;
9758 else if (s
[1] == 'e' && s
[2] == ' ')
9767 insn_error
= _("unknown opcode");
9771 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9772 mips16_small
= TRUE
;
9774 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9776 insn_error
= _("unrecognized opcode");
9785 assert (strcmp (insn
->name
, str
) == 0);
9787 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9794 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9795 && strcmp (insn
->name
, insn
[1].name
) == 0)
9804 static char buf
[100];
9806 _("opcode not supported on this processor: %s (%s)"),
9807 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9808 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9815 create_insn (ip
, insn
);
9816 imm_expr
.X_op
= O_absent
;
9817 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9818 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9819 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9820 imm2_expr
.X_op
= O_absent
;
9821 offset_expr
.X_op
= O_absent
;
9822 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9823 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9824 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9825 for (args
= insn
->args
; 1; ++args
)
9832 /* In this switch statement we call break if we did not find
9833 a match, continue if we did find a match, or return if we
9842 /* Stuff the immediate value in now, if we can. */
9843 if (imm_expr
.X_op
== O_constant
9844 && *imm_reloc
> BFD_RELOC_UNUSED
9845 && insn
->pinfo
!= INSN_MACRO
)
9849 switch (*offset_reloc
)
9851 case BFD_RELOC_MIPS16_HI16_S
:
9852 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9855 case BFD_RELOC_MIPS16_HI16
:
9856 tmp
= imm_expr
.X_add_number
>> 16;
9859 case BFD_RELOC_MIPS16_LO16
:
9860 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9864 case BFD_RELOC_UNUSED
:
9865 tmp
= imm_expr
.X_add_number
;
9871 *offset_reloc
= BFD_RELOC_UNUSED
;
9873 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9874 tmp
, TRUE
, mips16_small
,
9875 mips16_ext
, &ip
->insn_opcode
,
9876 &ip
->use_extend
, &ip
->extend
);
9877 imm_expr
.X_op
= O_absent
;
9878 *imm_reloc
= BFD_RELOC_UNUSED
;
9892 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9895 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9911 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9913 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9928 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9930 if (c
== 'v' || c
== 'w')
9933 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9935 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9946 if (c
== 'v' || c
== 'w')
9948 regno
= mips16_to_32_reg_map
[lastregno
];
9962 regno
= mips32_to_16_reg_map
[regno
];
9967 regno
= ILLEGAL_REG
;
9972 regno
= ILLEGAL_REG
;
9977 regno
= ILLEGAL_REG
;
9982 if (regno
== AT
&& ! mips_opts
.noat
)
9983 as_warn (_("used $at without \".set noat\""));
9990 if (regno
== ILLEGAL_REG
)
9997 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10001 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10004 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10007 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10013 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10016 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10017 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10027 if (strncmp (s
, "$pc", 3) == 0)
10044 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10047 if (imm_expr
.X_op
!= O_constant
)
10050 ip
->use_extend
= TRUE
;
10055 /* We need to relax this instruction. */
10056 *offset_reloc
= *imm_reloc
;
10057 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10062 *imm_reloc
= BFD_RELOC_UNUSED
;
10063 /* Fall through. */
10070 my_getExpression (&imm_expr
, s
);
10071 if (imm_expr
.X_op
== O_register
)
10073 /* What we thought was an expression turned out to
10076 if (s
[0] == '(' && args
[1] == '(')
10078 /* It looks like the expression was omitted
10079 before a register indirection, which means
10080 that the expression is implicitly zero. We
10081 still set up imm_expr, so that we handle
10082 explicit extensions correctly. */
10083 imm_expr
.X_op
= O_constant
;
10084 imm_expr
.X_add_number
= 0;
10085 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10092 /* We need to relax this instruction. */
10093 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10102 /* We use offset_reloc rather than imm_reloc for the PC
10103 relative operands. This lets macros with both
10104 immediate and address operands work correctly. */
10105 my_getExpression (&offset_expr
, s
);
10107 if (offset_expr
.X_op
== O_register
)
10110 /* We need to relax this instruction. */
10111 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10115 case '6': /* break code */
10116 my_getExpression (&imm_expr
, s
);
10117 check_absolute_expr (ip
, &imm_expr
);
10118 if ((unsigned long) imm_expr
.X_add_number
> 63)
10119 as_warn (_("Invalid value for `%s' (%lu)"),
10121 (unsigned long) imm_expr
.X_add_number
);
10122 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10123 imm_expr
.X_op
= O_absent
;
10127 case 'a': /* 26 bit address */
10128 my_getExpression (&offset_expr
, s
);
10130 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10131 ip
->insn_opcode
<<= 16;
10134 case 'l': /* register list for entry macro */
10135 case 'L': /* register list for exit macro */
10145 unsigned int freg
, reg1
, reg2
;
10147 while (*s
== ' ' || *s
== ',')
10149 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10151 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10155 as_bad (_("can't parse register list"));
10165 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10166 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10168 as_bad (_("invalid register list"));
10172 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10174 mask
&= ~ (7 << 3);
10177 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10179 mask
&= ~ (7 << 3);
10182 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10183 mask
|= (reg2
- 3) << 3;
10184 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10185 mask
|= (reg2
- 15) << 1;
10186 else if (reg1
== RA
&& reg2
== RA
)
10190 as_bad (_("invalid register list"));
10194 /* The mask is filled in in the opcode table for the
10195 benefit of the disassembler. We remove it before
10196 applying the actual mask. */
10197 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10198 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10202 case 'm': /* Register list for save insn. */
10203 case 'M': /* Register list for restore insn. */
10206 int framesz
= 0, seen_framesz
= 0;
10207 int args
= 0, statics
= 0, sregs
= 0;
10211 unsigned int reg1
, reg2
;
10213 SKIP_SPACE_TABS (s
);
10216 SKIP_SPACE_TABS (s
);
10218 my_getExpression (&imm_expr
, s
);
10219 if (imm_expr
.X_op
== O_constant
)
10221 /* Handle the frame size. */
10224 as_bad (_("more than one frame size in list"));
10228 framesz
= imm_expr
.X_add_number
;
10229 imm_expr
.X_op
= O_absent
;
10234 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10236 as_bad (_("can't parse register list"));
10248 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10251 as_bad (_("can't parse register list"));
10256 while (reg1
<= reg2
)
10258 if (reg1
>= 4 && reg1
<= 7)
10262 args
|= 1 << (reg1
- 4);
10264 /* statics $a0-$a3 */
10265 statics
|= 1 << (reg1
- 4);
10267 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10270 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10272 else if (reg1
== 31)
10274 /* Add $ra to insn. */
10279 as_bad (_("unexpected register in list"));
10287 /* Encode args/statics combination. */
10288 if (args
& statics
)
10289 as_bad (_("arg/static registers overlap"));
10290 else if (args
== 0xf)
10291 /* All $a0-$a3 are args. */
10292 opcode
|= MIPS16_ALL_ARGS
<< 16;
10293 else if (statics
== 0xf)
10294 /* All $a0-$a3 are statics. */
10295 opcode
|= MIPS16_ALL_STATICS
<< 16;
10298 int narg
= 0, nstat
= 0;
10300 /* Count arg registers. */
10307 as_bad (_("invalid arg register list"));
10309 /* Count static registers. */
10310 while (statics
& 0x8)
10312 statics
= (statics
<< 1) & 0xf;
10316 as_bad (_("invalid static register list"));
10318 /* Encode args/statics. */
10319 opcode
|= ((narg
<< 2) | nstat
) << 16;
10322 /* Encode $s0/$s1. */
10323 if (sregs
& (1 << 0)) /* $s0 */
10325 if (sregs
& (1 << 1)) /* $s1 */
10331 /* Count regs $s2-$s8. */
10339 as_bad (_("invalid static register list"));
10340 /* Encode $s2-$s8. */
10341 opcode
|= nsreg
<< 24;
10344 /* Encode frame size. */
10346 as_bad (_("missing frame size"));
10347 else if ((framesz
& 7) != 0 || framesz
< 0
10348 || framesz
> 0xff * 8)
10349 as_bad (_("invalid frame size"));
10350 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10353 opcode
|= (((framesz
& 0xf0) << 16)
10354 | (framesz
& 0x0f));
10357 /* Finally build the instruction. */
10358 if ((opcode
>> 16) != 0 || framesz
== 0)
10360 ip
->use_extend
= TRUE
;
10361 ip
->extend
= opcode
>> 16;
10363 ip
->insn_opcode
|= opcode
& 0x7f;
10367 case 'e': /* extend code */
10368 my_getExpression (&imm_expr
, s
);
10369 check_absolute_expr (ip
, &imm_expr
);
10370 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10372 as_warn (_("Invalid value for `%s' (%lu)"),
10374 (unsigned long) imm_expr
.X_add_number
);
10375 imm_expr
.X_add_number
&= 0x7ff;
10377 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10378 imm_expr
.X_op
= O_absent
;
10388 /* Args don't match. */
10389 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10390 strcmp (insn
->name
, insn
[1].name
) == 0)
10397 insn_error
= _("illegal operands");
10403 /* This structure holds information we know about a mips16 immediate
10406 struct mips16_immed_operand
10408 /* The type code used in the argument string in the opcode table. */
10410 /* The number of bits in the short form of the opcode. */
10412 /* The number of bits in the extended form of the opcode. */
10414 /* The amount by which the short form is shifted when it is used;
10415 for example, the sw instruction has a shift count of 2. */
10417 /* The amount by which the short form is shifted when it is stored
10418 into the instruction code. */
10420 /* Non-zero if the short form is unsigned. */
10422 /* Non-zero if the extended form is unsigned. */
10424 /* Non-zero if the value is PC relative. */
10428 /* The mips16 immediate operand types. */
10430 static const struct mips16_immed_operand mips16_immed_operands
[] =
10432 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10433 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10434 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10435 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10436 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10437 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10438 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10439 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10440 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10441 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10442 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10443 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10444 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10445 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10446 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10447 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10448 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10449 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10450 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10451 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10452 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10455 #define MIPS16_NUM_IMMED \
10456 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10458 /* Handle a mips16 instruction with an immediate value. This or's the
10459 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10460 whether an extended value is needed; if one is needed, it sets
10461 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10462 If SMALL is true, an unextended opcode was explicitly requested.
10463 If EXT is true, an extended opcode was explicitly requested. If
10464 WARN is true, warn if EXT does not match reality. */
10467 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10468 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10469 unsigned long *insn
, bfd_boolean
*use_extend
,
10470 unsigned short *extend
)
10472 const struct mips16_immed_operand
*op
;
10473 int mintiny
, maxtiny
;
10474 bfd_boolean needext
;
10476 op
= mips16_immed_operands
;
10477 while (op
->type
!= type
)
10480 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10485 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10488 maxtiny
= 1 << op
->nbits
;
10493 maxtiny
= (1 << op
->nbits
) - 1;
10498 mintiny
= - (1 << (op
->nbits
- 1));
10499 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10502 /* Branch offsets have an implicit 0 in the lowest bit. */
10503 if (type
== 'p' || type
== 'q')
10506 if ((val
& ((1 << op
->shift
) - 1)) != 0
10507 || val
< (mintiny
<< op
->shift
)
10508 || val
> (maxtiny
<< op
->shift
))
10513 if (warn
&& ext
&& ! needext
)
10514 as_warn_where (file
, line
,
10515 _("extended operand requested but not required"));
10516 if (small
&& needext
)
10517 as_bad_where (file
, line
, _("invalid unextended operand value"));
10519 if (small
|| (! ext
&& ! needext
))
10523 *use_extend
= FALSE
;
10524 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10525 insnval
<<= op
->op_shift
;
10530 long minext
, maxext
;
10536 maxext
= (1 << op
->extbits
) - 1;
10540 minext
= - (1 << (op
->extbits
- 1));
10541 maxext
= (1 << (op
->extbits
- 1)) - 1;
10543 if (val
< minext
|| val
> maxext
)
10544 as_bad_where (file
, line
,
10545 _("operand value out of range for instruction"));
10547 *use_extend
= TRUE
;
10548 if (op
->extbits
== 16)
10550 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10553 else if (op
->extbits
== 15)
10555 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10560 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10564 *extend
= (unsigned short) extval
;
10569 struct percent_op_match
10572 bfd_reloc_code_real_type reloc
;
10575 static const struct percent_op_match mips_percent_op
[] =
10577 {"%lo", BFD_RELOC_LO16
},
10579 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10580 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10581 {"%call16", BFD_RELOC_MIPS_CALL16
},
10582 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10583 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10584 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10585 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10586 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10587 {"%got", BFD_RELOC_MIPS_GOT16
},
10588 {"%gp_rel", BFD_RELOC_GPREL16
},
10589 {"%half", BFD_RELOC_16
},
10590 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10591 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10592 {"%neg", BFD_RELOC_MIPS_SUB
},
10593 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10594 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10595 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10596 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10597 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10598 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10599 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10601 {"%hi", BFD_RELOC_HI16_S
}
10604 static const struct percent_op_match mips16_percent_op
[] =
10606 {"%lo", BFD_RELOC_MIPS16_LO16
},
10607 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10608 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10612 /* Return true if *STR points to a relocation operator. When returning true,
10613 move *STR over the operator and store its relocation code in *RELOC.
10614 Leave both *STR and *RELOC alone when returning false. */
10617 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10619 const struct percent_op_match
*percent_op
;
10622 if (mips_opts
.mips16
)
10624 percent_op
= mips16_percent_op
;
10625 limit
= ARRAY_SIZE (mips16_percent_op
);
10629 percent_op
= mips_percent_op
;
10630 limit
= ARRAY_SIZE (mips_percent_op
);
10633 for (i
= 0; i
< limit
; i
++)
10634 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10636 int len
= strlen (percent_op
[i
].str
);
10638 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10641 *str
+= strlen (percent_op
[i
].str
);
10642 *reloc
= percent_op
[i
].reloc
;
10644 /* Check whether the output BFD supports this relocation.
10645 If not, issue an error and fall back on something safe. */
10646 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10648 as_bad ("relocation %s isn't supported by the current ABI",
10649 percent_op
[i
].str
);
10650 *reloc
= BFD_RELOC_UNUSED
;
10658 /* Parse string STR as a 16-bit relocatable operand. Store the
10659 expression in *EP and the relocations in the array starting
10660 at RELOC. Return the number of relocation operators used.
10662 On exit, EXPR_END points to the first character after the expression. */
10665 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10668 bfd_reloc_code_real_type reversed_reloc
[3];
10669 size_t reloc_index
, i
;
10670 int crux_depth
, str_depth
;
10673 /* Search for the start of the main expression, recoding relocations
10674 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10675 of the main expression and with CRUX_DEPTH containing the number
10676 of open brackets at that point. */
10683 crux_depth
= str_depth
;
10685 /* Skip over whitespace and brackets, keeping count of the number
10687 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10692 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10693 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10695 my_getExpression (ep
, crux
);
10698 /* Match every open bracket. */
10699 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10703 if (crux_depth
> 0)
10704 as_bad ("unclosed '('");
10708 if (reloc_index
!= 0)
10710 prev_reloc_op_frag
= frag_now
;
10711 for (i
= 0; i
< reloc_index
; i
++)
10712 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10715 return reloc_index
;
10719 my_getExpression (expressionS
*ep
, char *str
)
10724 save_in
= input_line_pointer
;
10725 input_line_pointer
= str
;
10727 expr_end
= input_line_pointer
;
10728 input_line_pointer
= save_in
;
10730 /* If we are in mips16 mode, and this is an expression based on `.',
10731 then we bump the value of the symbol by 1 since that is how other
10732 text symbols are handled. We don't bother to handle complex
10733 expressions, just `.' plus or minus a constant. */
10734 if (mips_opts
.mips16
10735 && ep
->X_op
== O_symbol
10736 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10737 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10738 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10739 && symbol_constant_p (ep
->X_add_symbol
)
10740 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10741 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10744 /* Turn a string in input_line_pointer into a floating point constant
10745 of type TYPE, and store the appropriate bytes in *LITP. The number
10746 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10747 returned, or NULL on OK. */
10750 md_atof (int type
, char *litP
, int *sizeP
)
10753 LITTLENUM_TYPE words
[4];
10769 return _("bad call to md_atof");
10772 t
= atof_ieee (input_line_pointer
, type
, words
);
10774 input_line_pointer
= t
;
10778 if (! target_big_endian
)
10780 for (i
= prec
- 1; i
>= 0; i
--)
10782 md_number_to_chars (litP
, words
[i
], 2);
10788 for (i
= 0; i
< prec
; i
++)
10790 md_number_to_chars (litP
, words
[i
], 2);
10799 md_number_to_chars (char *buf
, valueT val
, int n
)
10801 if (target_big_endian
)
10802 number_to_chars_bigendian (buf
, val
, n
);
10804 number_to_chars_littleendian (buf
, val
, n
);
10808 static int support_64bit_objects(void)
10810 const char **list
, **l
;
10813 list
= bfd_target_list ();
10814 for (l
= list
; *l
!= NULL
; l
++)
10816 /* This is traditional mips */
10817 if (strcmp (*l
, "elf64-tradbigmips") == 0
10818 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10820 if (strcmp (*l
, "elf64-bigmips") == 0
10821 || strcmp (*l
, "elf64-littlemips") == 0)
10824 yes
= (*l
!= NULL
);
10828 #endif /* OBJ_ELF */
10830 const char *md_shortopts
= "O::g::G:";
10832 struct option md_longopts
[] =
10834 /* Options which specify architecture. */
10835 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10836 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10837 {"march", required_argument
, NULL
, OPTION_MARCH
},
10838 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10839 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10840 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10841 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10842 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10843 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10844 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10845 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10846 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10847 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10848 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10849 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10850 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10851 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10852 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10853 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10854 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10855 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10856 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10857 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10858 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10860 /* Options which specify Application Specific Extensions (ASEs). */
10861 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10862 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10863 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10864 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10865 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10866 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10867 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10868 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10869 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10870 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10871 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10872 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10873 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10874 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10875 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10876 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10877 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10878 #define OPTION_MT (OPTION_ASE_BASE + 8)
10879 {"mmt", no_argument
, NULL
, OPTION_MT
},
10880 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10881 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10882 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10883 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10884 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10885 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10886 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
10887 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
10888 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
10889 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
10891 /* Old-style architecture options. Don't add more of these. */
10892 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
10893 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10894 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10895 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10896 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10897 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10898 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10899 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10900 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10901 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10902 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10903 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10904 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10905 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10906 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10907 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10908 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10910 /* Options which enable bug fixes. */
10911 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10912 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10913 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10914 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10915 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10916 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10917 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10918 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10919 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10920 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10921 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10922 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10923 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10924 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10926 /* Miscellaneous options. */
10927 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10928 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10929 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10930 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10931 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10932 {"break", no_argument
, NULL
, OPTION_BREAK
},
10933 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10934 #define OPTION_EB (OPTION_MISC_BASE + 2)
10935 {"EB", no_argument
, NULL
, OPTION_EB
},
10936 #define OPTION_EL (OPTION_MISC_BASE + 3)
10937 {"EL", no_argument
, NULL
, OPTION_EL
},
10938 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10939 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10940 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10941 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10942 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10943 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10944 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10945 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10946 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10947 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10948 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10949 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10950 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10951 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10952 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10953 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10954 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10955 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10956 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10957 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10958 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10959 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10960 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10961 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10963 /* ELF-specific options. */
10965 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10966 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10967 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10968 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10969 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10970 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10971 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10972 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10973 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10974 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10975 #define OPTION_32 (OPTION_ELF_BASE + 4)
10976 {"32", no_argument
, NULL
, OPTION_32
},
10977 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10978 {"n32", no_argument
, NULL
, OPTION_N32
},
10979 #define OPTION_64 (OPTION_ELF_BASE + 6)
10980 {"64", no_argument
, NULL
, OPTION_64
},
10981 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10982 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10983 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10984 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10985 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10986 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10987 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10988 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10989 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10990 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10991 #endif /* OBJ_ELF */
10993 {NULL
, no_argument
, NULL
, 0}
10995 size_t md_longopts_size
= sizeof (md_longopts
);
10997 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10998 NEW_VALUE. Warn if another value was already specified. Note:
10999 we have to defer parsing the -march and -mtune arguments in order
11000 to handle 'from-abi' correctly, since the ABI might be specified
11001 in a later argument. */
11004 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11006 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11007 as_warn (_("A different %s was already specified, is now %s"),
11008 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11011 *string_ptr
= new_value
;
11015 md_parse_option (int c
, char *arg
)
11019 case OPTION_CONSTRUCT_FLOATS
:
11020 mips_disable_float_construction
= 0;
11023 case OPTION_NO_CONSTRUCT_FLOATS
:
11024 mips_disable_float_construction
= 1;
11036 target_big_endian
= 1;
11040 target_big_endian
= 0;
11044 if (arg
&& arg
[0] == '0')
11054 mips_debug
= atoi (arg
);
11058 file_mips_isa
= ISA_MIPS1
;
11062 file_mips_isa
= ISA_MIPS2
;
11066 file_mips_isa
= ISA_MIPS3
;
11070 file_mips_isa
= ISA_MIPS4
;
11074 file_mips_isa
= ISA_MIPS5
;
11077 case OPTION_MIPS32
:
11078 file_mips_isa
= ISA_MIPS32
;
11081 case OPTION_MIPS32R2
:
11082 file_mips_isa
= ISA_MIPS32R2
;
11085 case OPTION_MIPS64R2
:
11086 file_mips_isa
= ISA_MIPS64R2
;
11089 case OPTION_MIPS64
:
11090 file_mips_isa
= ISA_MIPS64
;
11094 mips_set_option_string (&mips_tune_string
, arg
);
11098 mips_set_option_string (&mips_arch_string
, arg
);
11102 mips_set_option_string (&mips_arch_string
, "4650");
11103 mips_set_option_string (&mips_tune_string
, "4650");
11106 case OPTION_NO_M4650
:
11110 mips_set_option_string (&mips_arch_string
, "4010");
11111 mips_set_option_string (&mips_tune_string
, "4010");
11114 case OPTION_NO_M4010
:
11118 mips_set_option_string (&mips_arch_string
, "4100");
11119 mips_set_option_string (&mips_tune_string
, "4100");
11122 case OPTION_NO_M4100
:
11126 mips_set_option_string (&mips_arch_string
, "3900");
11127 mips_set_option_string (&mips_tune_string
, "3900");
11130 case OPTION_NO_M3900
:
11134 mips_opts
.ase_mdmx
= 1;
11137 case OPTION_NO_MDMX
:
11138 mips_opts
.ase_mdmx
= 0;
11142 mips_opts
.ase_dsp
= 1;
11143 mips_opts
.ase_dspr2
= 0;
11146 case OPTION_NO_DSP
:
11147 mips_opts
.ase_dsp
= 0;
11148 mips_opts
.ase_dspr2
= 0;
11152 mips_opts
.ase_dspr2
= 1;
11153 mips_opts
.ase_dsp
= 1;
11156 case OPTION_NO_DSPR2
:
11157 mips_opts
.ase_dspr2
= 0;
11158 mips_opts
.ase_dsp
= 0;
11162 mips_opts
.ase_mt
= 1;
11166 mips_opts
.ase_mt
= 0;
11169 case OPTION_MIPS16
:
11170 mips_opts
.mips16
= 1;
11171 mips_no_prev_insn ();
11174 case OPTION_NO_MIPS16
:
11175 mips_opts
.mips16
= 0;
11176 mips_no_prev_insn ();
11179 case OPTION_MIPS3D
:
11180 mips_opts
.ase_mips3d
= 1;
11183 case OPTION_NO_MIPS3D
:
11184 mips_opts
.ase_mips3d
= 0;
11187 case OPTION_SMARTMIPS
:
11188 mips_opts
.ase_smartmips
= 1;
11191 case OPTION_NO_SMARTMIPS
:
11192 mips_opts
.ase_smartmips
= 0;
11195 case OPTION_FIX_VR4120
:
11196 mips_fix_vr4120
= 1;
11199 case OPTION_NO_FIX_VR4120
:
11200 mips_fix_vr4120
= 0;
11203 case OPTION_FIX_VR4130
:
11204 mips_fix_vr4130
= 1;
11207 case OPTION_NO_FIX_VR4130
:
11208 mips_fix_vr4130
= 0;
11211 case OPTION_RELAX_BRANCH
:
11212 mips_relax_branch
= 1;
11215 case OPTION_NO_RELAX_BRANCH
:
11216 mips_relax_branch
= 0;
11219 case OPTION_MSHARED
:
11220 mips_in_shared
= TRUE
;
11223 case OPTION_MNO_SHARED
:
11224 mips_in_shared
= FALSE
;
11227 case OPTION_MSYM32
:
11228 mips_opts
.sym32
= TRUE
;
11231 case OPTION_MNO_SYM32
:
11232 mips_opts
.sym32
= FALSE
;
11236 /* When generating ELF code, we permit -KPIC and -call_shared to
11237 select SVR4_PIC, and -non_shared to select no PIC. This is
11238 intended to be compatible with Irix 5. */
11239 case OPTION_CALL_SHARED
:
11242 as_bad (_("-call_shared is supported only for ELF format"));
11245 mips_pic
= SVR4_PIC
;
11246 mips_abicalls
= TRUE
;
11249 case OPTION_NON_SHARED
:
11252 as_bad (_("-non_shared is supported only for ELF format"));
11256 mips_abicalls
= FALSE
;
11259 /* The -xgot option tells the assembler to use 32 bit offsets
11260 when accessing the got in SVR4_PIC mode. It is for Irix
11265 #endif /* OBJ_ELF */
11268 g_switch_value
= atoi (arg
);
11273 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11278 as_bad (_("-32 is supported for ELF format only"));
11281 mips_abi
= O32_ABI
;
11287 as_bad (_("-n32 is supported for ELF format only"));
11290 mips_abi
= N32_ABI
;
11296 as_bad (_("-64 is supported for ELF format only"));
11299 mips_abi
= N64_ABI
;
11300 if (!support_64bit_objects())
11301 as_fatal (_("No compiled in support for 64 bit object file format"));
11303 #endif /* OBJ_ELF */
11306 file_mips_gp32
= 1;
11310 file_mips_gp32
= 0;
11314 file_mips_fp32
= 1;
11318 file_mips_fp32
= 0;
11325 as_bad (_("-mabi is supported for ELF format only"));
11328 if (strcmp (arg
, "32") == 0)
11329 mips_abi
= O32_ABI
;
11330 else if (strcmp (arg
, "o64") == 0)
11331 mips_abi
= O64_ABI
;
11332 else if (strcmp (arg
, "n32") == 0)
11333 mips_abi
= N32_ABI
;
11334 else if (strcmp (arg
, "64") == 0)
11336 mips_abi
= N64_ABI
;
11337 if (! support_64bit_objects())
11338 as_fatal (_("No compiled in support for 64 bit object file "
11341 else if (strcmp (arg
, "eabi") == 0)
11342 mips_abi
= EABI_ABI
;
11345 as_fatal (_("invalid abi -mabi=%s"), arg
);
11349 #endif /* OBJ_ELF */
11351 case OPTION_M7000_HILO_FIX
:
11352 mips_7000_hilo_fix
= TRUE
;
11355 case OPTION_MNO_7000_HILO_FIX
:
11356 mips_7000_hilo_fix
= FALSE
;
11360 case OPTION_MDEBUG
:
11361 mips_flag_mdebug
= TRUE
;
11364 case OPTION_NO_MDEBUG
:
11365 mips_flag_mdebug
= FALSE
;
11369 mips_flag_pdr
= TRUE
;
11372 case OPTION_NO_PDR
:
11373 mips_flag_pdr
= FALSE
;
11376 case OPTION_MVXWORKS_PIC
:
11377 mips_pic
= VXWORKS_PIC
;
11379 #endif /* OBJ_ELF */
11388 /* Set up globals to generate code for the ISA or processor
11389 described by INFO. */
11392 mips_set_architecture (const struct mips_cpu_info
*info
)
11396 file_mips_arch
= info
->cpu
;
11397 mips_opts
.arch
= info
->cpu
;
11398 mips_opts
.isa
= info
->isa
;
11403 /* Likewise for tuning. */
11406 mips_set_tune (const struct mips_cpu_info
*info
)
11409 mips_tune
= info
->cpu
;
11414 mips_after_parse_args (void)
11416 const struct mips_cpu_info
*arch_info
= 0;
11417 const struct mips_cpu_info
*tune_info
= 0;
11419 /* GP relative stuff not working for PE */
11420 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11422 if (g_switch_seen
&& g_switch_value
!= 0)
11423 as_bad (_("-G not supported in this configuration."));
11424 g_switch_value
= 0;
11427 if (mips_abi
== NO_ABI
)
11428 mips_abi
= MIPS_DEFAULT_ABI
;
11430 /* The following code determines the architecture and register size.
11431 Similar code was added to GCC 3.3 (see override_options() in
11432 config/mips/mips.c). The GAS and GCC code should be kept in sync
11433 as much as possible. */
11435 if (mips_arch_string
!= 0)
11436 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11438 if (file_mips_isa
!= ISA_UNKNOWN
)
11440 /* Handle -mipsN. At this point, file_mips_isa contains the
11441 ISA level specified by -mipsN, while arch_info->isa contains
11442 the -march selection (if any). */
11443 if (arch_info
!= 0)
11445 /* -march takes precedence over -mipsN, since it is more descriptive.
11446 There's no harm in specifying both as long as the ISA levels
11448 if (file_mips_isa
!= arch_info
->isa
)
11449 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11450 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11451 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11454 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11457 if (arch_info
== 0)
11458 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11460 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11461 as_bad ("-march=%s is not compatible with the selected ABI",
11464 mips_set_architecture (arch_info
);
11466 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11467 if (mips_tune_string
!= 0)
11468 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11470 if (tune_info
== 0)
11471 mips_set_tune (arch_info
);
11473 mips_set_tune (tune_info
);
11475 if (file_mips_gp32
>= 0)
11477 /* The user specified the size of the integer registers. Make sure
11478 it agrees with the ABI and ISA. */
11479 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11480 as_bad (_("-mgp64 used with a 32-bit processor"));
11481 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11482 as_bad (_("-mgp32 used with a 64-bit ABI"));
11483 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11484 as_bad (_("-mgp64 used with a 32-bit ABI"));
11488 /* Infer the integer register size from the ABI and processor.
11489 Restrict ourselves to 32-bit registers if that's all the
11490 processor has, or if the ABI cannot handle 64-bit registers. */
11491 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11492 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11495 switch (file_mips_fp32
)
11499 /* No user specified float register size.
11500 ??? GAS treats single-float processors as though they had 64-bit
11501 float registers (although it complains when double-precision
11502 instructions are used). As things stand, saying they have 32-bit
11503 registers would lead to spurious "register must be even" messages.
11504 So here we assume float registers are never smaller than the
11506 if (file_mips_gp32
== 0)
11507 /* 64-bit integer registers implies 64-bit float registers. */
11508 file_mips_fp32
= 0;
11509 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11510 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11511 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11512 file_mips_fp32
= 0;
11514 /* 32-bit float registers. */
11515 file_mips_fp32
= 1;
11518 /* The user specified the size of the float registers. Check if it
11519 agrees with the ABI and ISA. */
11521 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11522 as_bad (_("-mfp64 used with a 32-bit fpu"));
11523 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11524 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11525 as_warn (_("-mfp64 used with a 32-bit ABI"));
11528 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11529 as_warn (_("-mfp32 used with a 64-bit ABI"));
11533 /* End of GCC-shared inference code. */
11535 /* This flag is set when we have a 64-bit capable CPU but use only
11536 32-bit wide registers. Note that EABI does not use it. */
11537 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11538 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11539 || mips_abi
== O32_ABI
))
11540 mips_32bitmode
= 1;
11542 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11543 as_bad (_("trap exception not supported at ISA 1"));
11545 /* If the selected architecture includes support for ASEs, enable
11546 generation of code for them. */
11547 if (mips_opts
.mips16
== -1)
11548 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11549 if (mips_opts
.ase_mips3d
== -1)
11550 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11551 && file_mips_fp32
== 0) ? 1 : 0;
11552 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11553 as_bad (_("-mfp32 used with -mips3d"));
11555 if (mips_opts
.ase_mdmx
== -1)
11556 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11557 && file_mips_fp32
== 0) ? 1 : 0;
11558 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11559 as_bad (_("-mfp32 used with -mdmx"));
11561 if (mips_opts
.ase_smartmips
== -1)
11562 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11563 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11564 as_warn ("%s ISA does not support SmartMIPS",
11565 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11567 if (mips_opts
.ase_dsp
== -1)
11568 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11569 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11570 as_warn ("%s ISA does not support DSP ASE",
11571 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11573 if (mips_opts
.ase_dspr2
== -1)
11575 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11576 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11578 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11579 as_warn ("%s ISA does not support DSP R2 ASE",
11580 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11582 if (mips_opts
.ase_mt
== -1)
11583 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11584 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11585 as_warn ("%s ISA does not support MT ASE",
11586 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11588 file_mips_isa
= mips_opts
.isa
;
11589 file_ase_mips16
= mips_opts
.mips16
;
11590 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11591 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11592 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11593 file_ase_dsp
= mips_opts
.ase_dsp
;
11594 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11595 file_ase_mt
= mips_opts
.ase_mt
;
11596 mips_opts
.gp32
= file_mips_gp32
;
11597 mips_opts
.fp32
= file_mips_fp32
;
11599 if (mips_flag_mdebug
< 0)
11601 #ifdef OBJ_MAYBE_ECOFF
11602 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11603 mips_flag_mdebug
= 1;
11605 #endif /* OBJ_MAYBE_ECOFF */
11606 mips_flag_mdebug
= 0;
11611 mips_init_after_args (void)
11613 /* initialize opcodes */
11614 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11615 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11619 md_pcrel_from (fixS
*fixP
)
11621 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11622 switch (fixP
->fx_r_type
)
11624 case BFD_RELOC_16_PCREL_S2
:
11625 case BFD_RELOC_MIPS_JMP
:
11626 /* Return the address of the delay slot. */
11629 /* We have no relocation type for PC relative MIPS16 instructions. */
11630 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11632 _("PC relative MIPS16 instruction references a different section"));
11637 /* This is called before the symbol table is processed. In order to
11638 work with gcc when using mips-tfile, we must keep all local labels.
11639 However, in other cases, we want to discard them. If we were
11640 called with -g, but we didn't see any debugging information, it may
11641 mean that gcc is smuggling debugging information through to
11642 mips-tfile, in which case we must generate all local labels. */
11645 mips_frob_file_before_adjust (void)
11647 #ifndef NO_ECOFF_DEBUGGING
11648 if (ECOFF_DEBUGGING
11650 && ! ecoff_debugging_seen
)
11651 flag_keep_locals
= 1;
11655 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11656 the corresponding LO16 reloc. This is called before md_apply_fix and
11657 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11658 relocation operators.
11660 For our purposes, a %lo() expression matches a %got() or %hi()
11663 (a) it refers to the same symbol; and
11664 (b) the offset applied in the %lo() expression is no lower than
11665 the offset applied in the %got() or %hi().
11667 (b) allows us to cope with code like:
11670 lh $4,%lo(foo+2)($4)
11672 ...which is legal on RELA targets, and has a well-defined behaviour
11673 if the user knows that adding 2 to "foo" will not induce a carry to
11676 When several %lo()s match a particular %got() or %hi(), we use the
11677 following rules to distinguish them:
11679 (1) %lo()s with smaller offsets are a better match than %lo()s with
11682 (2) %lo()s with no matching %got() or %hi() are better than those
11683 that already have a matching %got() or %hi().
11685 (3) later %lo()s are better than earlier %lo()s.
11687 These rules are applied in order.
11689 (1) means, among other things, that %lo()s with identical offsets are
11690 chosen if they exist.
11692 (2) means that we won't associate several high-part relocations with
11693 the same low-part relocation unless there's no alternative. Having
11694 several high parts for the same low part is a GNU extension; this rule
11695 allows careful users to avoid it.
11697 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11698 with the last high-part relocation being at the front of the list.
11699 It therefore makes sense to choose the last matching low-part
11700 relocation, all other things being equal. It's also easier
11701 to code that way. */
11704 mips_frob_file (void)
11706 struct mips_hi_fixup
*l
;
11708 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11710 segment_info_type
*seginfo
;
11711 bfd_boolean matched_lo_p
;
11712 fixS
**hi_pos
, **lo_pos
, **pos
;
11714 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11716 /* If a GOT16 relocation turns out to be against a global symbol,
11717 there isn't supposed to be a matching LO. */
11718 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11719 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11722 /* Check quickly whether the next fixup happens to be a matching %lo. */
11723 if (fixup_has_matching_lo_p (l
->fixp
))
11726 seginfo
= seg_info (l
->seg
);
11728 /* Set HI_POS to the position of this relocation in the chain.
11729 Set LO_POS to the position of the chosen low-part relocation.
11730 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11731 relocation that matches an immediately-preceding high-part
11735 matched_lo_p
= FALSE
;
11736 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11738 if (*pos
== l
->fixp
)
11741 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11742 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11743 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11744 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11746 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11748 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11751 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11752 && fixup_has_matching_lo_p (*pos
));
11755 /* If we found a match, remove the high-part relocation from its
11756 current position and insert it before the low-part relocation.
11757 Make the offsets match so that fixup_has_matching_lo_p()
11760 We don't warn about unmatched high-part relocations since some
11761 versions of gcc have been known to emit dead "lui ...%hi(...)"
11763 if (lo_pos
!= NULL
)
11765 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11766 if (l
->fixp
->fx_next
!= *lo_pos
)
11768 *hi_pos
= l
->fixp
->fx_next
;
11769 l
->fixp
->fx_next
= *lo_pos
;
11776 /* We may have combined relocations without symbols in the N32/N64 ABI.
11777 We have to prevent gas from dropping them. */
11780 mips_force_relocation (fixS
*fixp
)
11782 if (generic_force_reloc (fixp
))
11786 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11787 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11788 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11789 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11795 /* Apply a fixup to the object file. */
11798 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11802 reloc_howto_type
*howto
;
11804 /* We ignore generic BFD relocations we don't know about. */
11805 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11809 assert (fixP
->fx_size
== 4
11810 || fixP
->fx_r_type
== BFD_RELOC_16
11811 || fixP
->fx_r_type
== BFD_RELOC_64
11812 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11813 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11814 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11815 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11817 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11819 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11821 /* Don't treat parts of a composite relocation as done. There are two
11824 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11825 should nevertheless be emitted if the first part is.
11827 (2) In normal usage, composite relocations are never assembly-time
11828 constants. The easiest way of dealing with the pathological
11829 exceptions is to generate a relocation against STN_UNDEF and
11830 leave everything up to the linker. */
11831 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11834 switch (fixP
->fx_r_type
)
11836 case BFD_RELOC_MIPS_TLS_GD
:
11837 case BFD_RELOC_MIPS_TLS_LDM
:
11838 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11839 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11840 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11841 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11842 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11843 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11846 case BFD_RELOC_MIPS_JMP
:
11847 case BFD_RELOC_MIPS_SHIFT5
:
11848 case BFD_RELOC_MIPS_SHIFT6
:
11849 case BFD_RELOC_MIPS_GOT_DISP
:
11850 case BFD_RELOC_MIPS_GOT_PAGE
:
11851 case BFD_RELOC_MIPS_GOT_OFST
:
11852 case BFD_RELOC_MIPS_SUB
:
11853 case BFD_RELOC_MIPS_INSERT_A
:
11854 case BFD_RELOC_MIPS_INSERT_B
:
11855 case BFD_RELOC_MIPS_DELETE
:
11856 case BFD_RELOC_MIPS_HIGHEST
:
11857 case BFD_RELOC_MIPS_HIGHER
:
11858 case BFD_RELOC_MIPS_SCN_DISP
:
11859 case BFD_RELOC_MIPS_REL16
:
11860 case BFD_RELOC_MIPS_RELGOT
:
11861 case BFD_RELOC_MIPS_JALR
:
11862 case BFD_RELOC_HI16
:
11863 case BFD_RELOC_HI16_S
:
11864 case BFD_RELOC_GPREL16
:
11865 case BFD_RELOC_MIPS_LITERAL
:
11866 case BFD_RELOC_MIPS_CALL16
:
11867 case BFD_RELOC_MIPS_GOT16
:
11868 case BFD_RELOC_GPREL32
:
11869 case BFD_RELOC_MIPS_GOT_HI16
:
11870 case BFD_RELOC_MIPS_GOT_LO16
:
11871 case BFD_RELOC_MIPS_CALL_HI16
:
11872 case BFD_RELOC_MIPS_CALL_LO16
:
11873 case BFD_RELOC_MIPS16_GPREL
:
11874 case BFD_RELOC_MIPS16_HI16
:
11875 case BFD_RELOC_MIPS16_HI16_S
:
11876 case BFD_RELOC_MIPS16_JMP
:
11877 /* Nothing needed to do. The value comes from the reloc entry. */
11881 /* This is handled like BFD_RELOC_32, but we output a sign
11882 extended value if we are only 32 bits. */
11885 if (8 <= sizeof (valueT
))
11886 md_number_to_chars ((char *) buf
, *valP
, 8);
11891 if ((*valP
& 0x80000000) != 0)
11895 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11897 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11903 case BFD_RELOC_RVA
:
11906 /* If we are deleting this reloc entry, we must fill in the
11907 value now. This can happen if we have a .word which is not
11908 resolved when it appears but is later defined. */
11910 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
11913 case BFD_RELOC_LO16
:
11914 case BFD_RELOC_MIPS16_LO16
:
11915 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11916 may be safe to remove, but if so it's not obvious. */
11917 /* When handling an embedded PIC switch statement, we can wind
11918 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11921 if (*valP
+ 0x8000 > 0xffff)
11922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11923 _("relocation overflow"));
11924 if (target_big_endian
)
11926 md_number_to_chars ((char *) buf
, *valP
, 2);
11930 case BFD_RELOC_16_PCREL_S2
:
11931 if ((*valP
& 0x3) != 0)
11932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11933 _("Branch to misaligned address (%lx)"), (long) *valP
);
11935 /* We need to save the bits in the instruction since fixup_segment()
11936 might be deleting the relocation entry (i.e., a branch within
11937 the current segment). */
11938 if (! fixP
->fx_done
)
11941 /* Update old instruction data. */
11942 if (target_big_endian
)
11943 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11945 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11947 if (*valP
+ 0x20000 <= 0x3ffff)
11949 insn
|= (*valP
>> 2) & 0xffff;
11950 md_number_to_chars ((char *) buf
, insn
, 4);
11952 else if (mips_pic
== NO_PIC
11954 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11955 && (fixP
->fx_frag
->fr_address
11956 < text_section
->vma
+ bfd_get_section_size (text_section
))
11957 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11958 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11959 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11961 /* The branch offset is too large. If this is an
11962 unconditional branch, and we are not generating PIC code,
11963 we can convert it to an absolute jump instruction. */
11964 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11965 insn
= 0x0c000000; /* jal */
11967 insn
= 0x08000000; /* j */
11968 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11970 fixP
->fx_addsy
= section_symbol (text_section
);
11971 *valP
+= md_pcrel_from (fixP
);
11972 md_number_to_chars ((char *) buf
, insn
, 4);
11976 /* If we got here, we have branch-relaxation disabled,
11977 and there's nothing we can do to fix this instruction
11978 without turning it into a longer sequence. */
11979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11980 _("Branch out of range"));
11984 case BFD_RELOC_VTABLE_INHERIT
:
11987 && !S_IS_DEFINED (fixP
->fx_addsy
)
11988 && !S_IS_WEAK (fixP
->fx_addsy
))
11989 S_SET_WEAK (fixP
->fx_addsy
);
11992 case BFD_RELOC_VTABLE_ENTRY
:
12000 /* Remember value for tc_gen_reloc. */
12001 fixP
->fx_addnumber
= *valP
;
12011 name
= input_line_pointer
;
12012 c
= get_symbol_end ();
12013 p
= (symbolS
*) symbol_find_or_make (name
);
12014 *input_line_pointer
= c
;
12018 /* Align the current frag to a given power of two. The MIPS assembler
12019 also automatically adjusts any preceding label. */
12022 mips_align (int to
, int fill
, symbolS
*label
)
12024 mips_emit_delays ();
12025 frag_align (to
, fill
, 0);
12026 record_alignment (now_seg
, to
);
12029 assert (S_GET_SEGMENT (label
) == now_seg
);
12030 symbol_set_frag (label
, frag_now
);
12031 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12035 /* Align to a given power of two. .align 0 turns off the automatic
12036 alignment used by the data creating pseudo-ops. */
12039 s_align (int x ATTRIBUTE_UNUSED
)
12043 long max_alignment
= 15;
12045 /* o Note that the assembler pulls down any immediately preceding label
12046 to the aligned address.
12047 o It's not documented but auto alignment is reinstated by
12048 a .align pseudo instruction.
12049 o Note also that after auto alignment is turned off the mips assembler
12050 issues an error on attempt to assemble an improperly aligned data item.
12053 temp
= get_absolute_expression ();
12054 if (temp
> max_alignment
)
12055 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12058 as_warn (_("Alignment negative: 0 assumed."));
12061 if (*input_line_pointer
== ',')
12063 ++input_line_pointer
;
12064 temp_fill
= get_absolute_expression ();
12070 segment_info_type
*si
= seg_info (now_seg
);
12071 struct insn_label_list
*l
= si
->label_list
;
12072 /* Auto alignment should be switched on by next section change. */
12074 mips_align (temp
, (int) temp_fill
, l
!= NULL
? l
->label
: NULL
);
12081 demand_empty_rest_of_line ();
12085 s_change_sec (int sec
)
12090 /* The ELF backend needs to know that we are changing sections, so
12091 that .previous works correctly. We could do something like check
12092 for an obj_section_change_hook macro, but that might be confusing
12093 as it would not be appropriate to use it in the section changing
12094 functions in read.c, since obj-elf.c intercepts those. FIXME:
12095 This should be cleaner, somehow. */
12097 obj_elf_section_change_hook ();
12100 mips_emit_delays ();
12110 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12111 demand_empty_rest_of_line ();
12115 seg
= subseg_new (RDATA_SECTION_NAME
,
12116 (subsegT
) get_absolute_expression ());
12119 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12120 | SEC_READONLY
| SEC_RELOC
12122 if (strcmp (TARGET_OS
, "elf") != 0)
12123 record_alignment (seg
, 4);
12125 demand_empty_rest_of_line ();
12129 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12132 bfd_set_section_flags (stdoutput
, seg
,
12133 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12134 if (strcmp (TARGET_OS
, "elf") != 0)
12135 record_alignment (seg
, 4);
12137 demand_empty_rest_of_line ();
12145 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12148 char *section_name
;
12153 int section_entry_size
;
12154 int section_alignment
;
12159 section_name
= input_line_pointer
;
12160 c
= get_symbol_end ();
12162 next_c
= *(input_line_pointer
+ 1);
12164 /* Do we have .section Name<,"flags">? */
12165 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12167 /* just after name is now '\0'. */
12168 *input_line_pointer
= c
;
12169 input_line_pointer
= section_name
;
12170 obj_elf_section (ignore
);
12173 input_line_pointer
++;
12175 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12177 section_type
= get_absolute_expression ();
12180 if (*input_line_pointer
++ == ',')
12181 section_flag
= get_absolute_expression ();
12184 if (*input_line_pointer
++ == ',')
12185 section_entry_size
= get_absolute_expression ();
12187 section_entry_size
= 0;
12188 if (*input_line_pointer
++ == ',')
12189 section_alignment
= get_absolute_expression ();
12191 section_alignment
= 0;
12193 section_name
= xstrdup (section_name
);
12195 /* When using the generic form of .section (as implemented by obj-elf.c),
12196 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12197 traditionally had to fall back on the more common @progbits instead.
12199 There's nothing really harmful in this, since bfd will correct
12200 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12201 means that, for backwards compatibility, the special_section entries
12202 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12204 Even so, we shouldn't force users of the MIPS .section syntax to
12205 incorrectly label the sections as SHT_PROGBITS. The best compromise
12206 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12207 generic type-checking code. */
12208 if (section_type
== SHT_MIPS_DWARF
)
12209 section_type
= SHT_PROGBITS
;
12211 obj_elf_change_section (section_name
, section_type
, section_flag
,
12212 section_entry_size
, 0, 0, 0);
12214 if (now_seg
->name
!= section_name
)
12215 free (section_name
);
12216 #endif /* OBJ_ELF */
12220 mips_enable_auto_align (void)
12226 s_cons (int log_size
)
12228 segment_info_type
*si
= seg_info (now_seg
);
12229 struct insn_label_list
*l
= si
->label_list
;
12232 label
= l
!= NULL
? l
->label
: NULL
;
12233 mips_emit_delays ();
12234 if (log_size
> 0 && auto_align
)
12235 mips_align (log_size
, 0, label
);
12236 mips_clear_insn_labels ();
12237 cons (1 << log_size
);
12241 s_float_cons (int type
)
12243 segment_info_type
*si
= seg_info (now_seg
);
12244 struct insn_label_list
*l
= si
->label_list
;
12247 label
= l
!= NULL
? l
->label
: NULL
;
12249 mips_emit_delays ();
12254 mips_align (3, 0, label
);
12256 mips_align (2, 0, label
);
12259 mips_clear_insn_labels ();
12264 /* Handle .globl. We need to override it because on Irix 5 you are
12267 where foo is an undefined symbol, to mean that foo should be
12268 considered to be the address of a function. */
12271 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12280 name
= input_line_pointer
;
12281 c
= get_symbol_end ();
12282 symbolP
= symbol_find_or_make (name
);
12283 S_SET_EXTERNAL (symbolP
);
12285 *input_line_pointer
= c
;
12286 SKIP_WHITESPACE ();
12288 /* On Irix 5, every global symbol that is not explicitly labelled as
12289 being a function is apparently labelled as being an object. */
12292 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12293 && (*input_line_pointer
!= ','))
12298 secname
= input_line_pointer
;
12299 c
= get_symbol_end ();
12300 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12302 as_bad (_("%s: no such section"), secname
);
12303 *input_line_pointer
= c
;
12305 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12306 flag
= BSF_FUNCTION
;
12309 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12311 c
= *input_line_pointer
;
12314 input_line_pointer
++;
12315 SKIP_WHITESPACE ();
12316 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12322 demand_empty_rest_of_line ();
12326 s_option (int x ATTRIBUTE_UNUSED
)
12331 opt
= input_line_pointer
;
12332 c
= get_symbol_end ();
12336 /* FIXME: What does this mean? */
12338 else if (strncmp (opt
, "pic", 3) == 0)
12342 i
= atoi (opt
+ 3);
12347 mips_pic
= SVR4_PIC
;
12348 mips_abicalls
= TRUE
;
12351 as_bad (_(".option pic%d not supported"), i
);
12353 if (mips_pic
== SVR4_PIC
)
12355 if (g_switch_seen
&& g_switch_value
!= 0)
12356 as_warn (_("-G may not be used with SVR4 PIC code"));
12357 g_switch_value
= 0;
12358 bfd_set_gp_size (stdoutput
, 0);
12362 as_warn (_("Unrecognized option \"%s\""), opt
);
12364 *input_line_pointer
= c
;
12365 demand_empty_rest_of_line ();
12368 /* This structure is used to hold a stack of .set values. */
12370 struct mips_option_stack
12372 struct mips_option_stack
*next
;
12373 struct mips_set_options options
;
12376 static struct mips_option_stack
*mips_opts_stack
;
12378 /* Handle the .set pseudo-op. */
12381 s_mipsset (int x ATTRIBUTE_UNUSED
)
12383 char *name
= input_line_pointer
, ch
;
12385 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12386 ++input_line_pointer
;
12387 ch
= *input_line_pointer
;
12388 *input_line_pointer
= '\0';
12390 if (strcmp (name
, "reorder") == 0)
12392 if (mips_opts
.noreorder
)
12395 else if (strcmp (name
, "noreorder") == 0)
12397 if (!mips_opts
.noreorder
)
12398 start_noreorder ();
12400 else if (strcmp (name
, "at") == 0)
12402 mips_opts
.noat
= 0;
12404 else if (strcmp (name
, "noat") == 0)
12406 mips_opts
.noat
= 1;
12408 else if (strcmp (name
, "macro") == 0)
12410 mips_opts
.warn_about_macros
= 0;
12412 else if (strcmp (name
, "nomacro") == 0)
12414 if (mips_opts
.noreorder
== 0)
12415 as_bad (_("`noreorder' must be set before `nomacro'"));
12416 mips_opts
.warn_about_macros
= 1;
12418 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12420 mips_opts
.nomove
= 0;
12422 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12424 mips_opts
.nomove
= 1;
12426 else if (strcmp (name
, "bopt") == 0)
12428 mips_opts
.nobopt
= 0;
12430 else if (strcmp (name
, "nobopt") == 0)
12432 mips_opts
.nobopt
= 1;
12434 else if (strcmp (name
, "gp=default") == 0)
12435 mips_opts
.gp32
= file_mips_gp32
;
12436 else if (strcmp (name
, "gp=32") == 0)
12437 mips_opts
.gp32
= 1;
12438 else if (strcmp (name
, "gp=64") == 0)
12440 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12441 as_warn ("%s isa does not support 64-bit registers",
12442 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12443 mips_opts
.gp32
= 0;
12445 else if (strcmp (name
, "fp=default") == 0)
12446 mips_opts
.fp32
= file_mips_fp32
;
12447 else if (strcmp (name
, "fp=32") == 0)
12448 mips_opts
.fp32
= 1;
12449 else if (strcmp (name
, "fp=64") == 0)
12451 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12452 as_warn ("%s isa does not support 64-bit floating point registers",
12453 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12454 mips_opts
.fp32
= 0;
12456 else if (strcmp (name
, "mips16") == 0
12457 || strcmp (name
, "MIPS-16") == 0)
12458 mips_opts
.mips16
= 1;
12459 else if (strcmp (name
, "nomips16") == 0
12460 || strcmp (name
, "noMIPS-16") == 0)
12461 mips_opts
.mips16
= 0;
12462 else if (strcmp (name
, "smartmips") == 0)
12464 if (!ISA_SUPPORTS_SMARTMIPS
)
12465 as_warn ("%s ISA does not support SmartMIPS ASE",
12466 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12467 mips_opts
.ase_smartmips
= 1;
12469 else if (strcmp (name
, "nosmartmips") == 0)
12470 mips_opts
.ase_smartmips
= 0;
12471 else if (strcmp (name
, "mips3d") == 0)
12472 mips_opts
.ase_mips3d
= 1;
12473 else if (strcmp (name
, "nomips3d") == 0)
12474 mips_opts
.ase_mips3d
= 0;
12475 else if (strcmp (name
, "mdmx") == 0)
12476 mips_opts
.ase_mdmx
= 1;
12477 else if (strcmp (name
, "nomdmx") == 0)
12478 mips_opts
.ase_mdmx
= 0;
12479 else if (strcmp (name
, "dsp") == 0)
12481 if (!ISA_SUPPORTS_DSP_ASE
)
12482 as_warn ("%s ISA does not support DSP ASE",
12483 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12484 mips_opts
.ase_dsp
= 1;
12485 mips_opts
.ase_dspr2
= 0;
12487 else if (strcmp (name
, "nodsp") == 0)
12489 mips_opts
.ase_dsp
= 0;
12490 mips_opts
.ase_dspr2
= 0;
12492 else if (strcmp (name
, "dspr2") == 0)
12494 if (!ISA_SUPPORTS_DSPR2_ASE
)
12495 as_warn ("%s ISA does not support DSP R2 ASE",
12496 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12497 mips_opts
.ase_dspr2
= 1;
12498 mips_opts
.ase_dsp
= 1;
12500 else if (strcmp (name
, "nodspr2") == 0)
12502 mips_opts
.ase_dspr2
= 0;
12503 mips_opts
.ase_dsp
= 0;
12505 else if (strcmp (name
, "mt") == 0)
12507 if (!ISA_SUPPORTS_MT_ASE
)
12508 as_warn ("%s ISA does not support MT ASE",
12509 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12510 mips_opts
.ase_mt
= 1;
12512 else if (strcmp (name
, "nomt") == 0)
12513 mips_opts
.ase_mt
= 0;
12514 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12518 /* Permit the user to change the ISA and architecture on the fly.
12519 Needless to say, misuse can cause serious problems. */
12520 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12523 mips_opts
.isa
= file_mips_isa
;
12524 mips_opts
.arch
= file_mips_arch
;
12526 else if (strncmp (name
, "arch=", 5) == 0)
12528 const struct mips_cpu_info
*p
;
12530 p
= mips_parse_cpu("internal use", name
+ 5);
12532 as_bad (_("unknown architecture %s"), name
+ 5);
12535 mips_opts
.arch
= p
->cpu
;
12536 mips_opts
.isa
= p
->isa
;
12539 else if (strncmp (name
, "mips", 4) == 0)
12541 const struct mips_cpu_info
*p
;
12543 p
= mips_parse_cpu("internal use", name
);
12545 as_bad (_("unknown ISA level %s"), name
+ 4);
12548 mips_opts
.arch
= p
->cpu
;
12549 mips_opts
.isa
= p
->isa
;
12553 as_bad (_("unknown ISA or architecture %s"), name
);
12555 switch (mips_opts
.isa
)
12563 mips_opts
.gp32
= 1;
12564 mips_opts
.fp32
= 1;
12571 mips_opts
.gp32
= 0;
12572 mips_opts
.fp32
= 0;
12575 as_bad (_("unknown ISA level %s"), name
+ 4);
12580 mips_opts
.gp32
= file_mips_gp32
;
12581 mips_opts
.fp32
= file_mips_fp32
;
12584 else if (strcmp (name
, "autoextend") == 0)
12585 mips_opts
.noautoextend
= 0;
12586 else if (strcmp (name
, "noautoextend") == 0)
12587 mips_opts
.noautoextend
= 1;
12588 else if (strcmp (name
, "push") == 0)
12590 struct mips_option_stack
*s
;
12592 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12593 s
->next
= mips_opts_stack
;
12594 s
->options
= mips_opts
;
12595 mips_opts_stack
= s
;
12597 else if (strcmp (name
, "pop") == 0)
12599 struct mips_option_stack
*s
;
12601 s
= mips_opts_stack
;
12603 as_bad (_(".set pop with no .set push"));
12606 /* If we're changing the reorder mode we need to handle
12607 delay slots correctly. */
12608 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12609 start_noreorder ();
12610 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12613 mips_opts
= s
->options
;
12614 mips_opts_stack
= s
->next
;
12618 else if (strcmp (name
, "sym32") == 0)
12619 mips_opts
.sym32
= TRUE
;
12620 else if (strcmp (name
, "nosym32") == 0)
12621 mips_opts
.sym32
= FALSE
;
12622 else if (strchr (name
, ','))
12624 /* Generic ".set" directive; use the generic handler. */
12625 *input_line_pointer
= ch
;
12626 input_line_pointer
= name
;
12632 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12634 *input_line_pointer
= ch
;
12635 demand_empty_rest_of_line ();
12638 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12639 .option pic2. It means to generate SVR4 PIC calls. */
12642 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12644 mips_pic
= SVR4_PIC
;
12645 mips_abicalls
= TRUE
;
12647 if (g_switch_seen
&& g_switch_value
!= 0)
12648 as_warn (_("-G may not be used with SVR4 PIC code"));
12649 g_switch_value
= 0;
12651 bfd_set_gp_size (stdoutput
, 0);
12652 demand_empty_rest_of_line ();
12655 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12656 PIC code. It sets the $gp register for the function based on the
12657 function address, which is in the register named in the argument.
12658 This uses a relocation against _gp_disp, which is handled specially
12659 by the linker. The result is:
12660 lui $gp,%hi(_gp_disp)
12661 addiu $gp,$gp,%lo(_gp_disp)
12662 addu $gp,$gp,.cpload argument
12663 The .cpload argument is normally $25 == $t9.
12665 The -mno-shared option changes this to:
12666 lui $gp,%hi(__gnu_local_gp)
12667 addiu $gp,$gp,%lo(__gnu_local_gp)
12668 and the argument is ignored. This saves an instruction, but the
12669 resulting code is not position independent; it uses an absolute
12670 address for __gnu_local_gp. Thus code assembled with -mno-shared
12671 can go into an ordinary executable, but not into a shared library. */
12674 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12680 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12681 .cpload is ignored. */
12682 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12688 /* .cpload should be in a .set noreorder section. */
12689 if (mips_opts
.noreorder
== 0)
12690 as_warn (_(".cpload not in noreorder section"));
12692 reg
= tc_get_register (0);
12694 /* If we need to produce a 64-bit address, we are better off using
12695 the default instruction sequence. */
12696 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12698 ex
.X_op
= O_symbol
;
12699 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12701 ex
.X_op_symbol
= NULL
;
12702 ex
.X_add_number
= 0;
12704 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12705 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12708 macro_build_lui (&ex
, mips_gp_register
);
12709 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12710 mips_gp_register
, BFD_RELOC_LO16
);
12712 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12713 mips_gp_register
, reg
);
12716 demand_empty_rest_of_line ();
12719 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12720 .cpsetup $reg1, offset|$reg2, label
12722 If offset is given, this results in:
12723 sd $gp, offset($sp)
12724 lui $gp, %hi(%neg(%gp_rel(label)))
12725 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12726 daddu $gp, $gp, $reg1
12728 If $reg2 is given, this results in:
12729 daddu $reg2, $gp, $0
12730 lui $gp, %hi(%neg(%gp_rel(label)))
12731 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12732 daddu $gp, $gp, $reg1
12733 $reg1 is normally $25 == $t9.
12735 The -mno-shared option replaces the last three instructions with
12737 addiu $gp,$gp,%lo(_gp) */
12740 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12742 expressionS ex_off
;
12743 expressionS ex_sym
;
12746 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12747 We also need NewABI support. */
12748 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12754 reg1
= tc_get_register (0);
12755 SKIP_WHITESPACE ();
12756 if (*input_line_pointer
!= ',')
12758 as_bad (_("missing argument separator ',' for .cpsetup"));
12762 ++input_line_pointer
;
12763 SKIP_WHITESPACE ();
12764 if (*input_line_pointer
== '$')
12766 mips_cpreturn_register
= tc_get_register (0);
12767 mips_cpreturn_offset
= -1;
12771 mips_cpreturn_offset
= get_absolute_expression ();
12772 mips_cpreturn_register
= -1;
12774 SKIP_WHITESPACE ();
12775 if (*input_line_pointer
!= ',')
12777 as_bad (_("missing argument separator ',' for .cpsetup"));
12781 ++input_line_pointer
;
12782 SKIP_WHITESPACE ();
12783 expression (&ex_sym
);
12786 if (mips_cpreturn_register
== -1)
12788 ex_off
.X_op
= O_constant
;
12789 ex_off
.X_add_symbol
= NULL
;
12790 ex_off
.X_op_symbol
= NULL
;
12791 ex_off
.X_add_number
= mips_cpreturn_offset
;
12793 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12794 BFD_RELOC_LO16
, SP
);
12797 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12798 mips_gp_register
, 0);
12800 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12802 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12803 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12806 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12807 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12808 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12810 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12811 mips_gp_register
, reg1
);
12817 ex
.X_op
= O_symbol
;
12818 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12819 ex
.X_op_symbol
= NULL
;
12820 ex
.X_add_number
= 0;
12822 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12823 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12825 macro_build_lui (&ex
, mips_gp_register
);
12826 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12827 mips_gp_register
, BFD_RELOC_LO16
);
12832 demand_empty_rest_of_line ();
12836 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12838 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12839 .cplocal is ignored. */
12840 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12846 mips_gp_register
= tc_get_register (0);
12847 demand_empty_rest_of_line ();
12850 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12851 offset from $sp. The offset is remembered, and after making a PIC
12852 call $gp is restored from that location. */
12855 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12859 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12860 .cprestore is ignored. */
12861 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12867 mips_cprestore_offset
= get_absolute_expression ();
12868 mips_cprestore_valid
= 1;
12870 ex
.X_op
= O_constant
;
12871 ex
.X_add_symbol
= NULL
;
12872 ex
.X_op_symbol
= NULL
;
12873 ex
.X_add_number
= mips_cprestore_offset
;
12876 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12877 SP
, HAVE_64BIT_ADDRESSES
);
12880 demand_empty_rest_of_line ();
12883 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12884 was given in the preceding .cpsetup, it results in:
12885 ld $gp, offset($sp)
12887 If a register $reg2 was given there, it results in:
12888 daddu $gp, $reg2, $0 */
12891 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12895 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12896 We also need NewABI support. */
12897 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12904 if (mips_cpreturn_register
== -1)
12906 ex
.X_op
= O_constant
;
12907 ex
.X_add_symbol
= NULL
;
12908 ex
.X_op_symbol
= NULL
;
12909 ex
.X_add_number
= mips_cpreturn_offset
;
12911 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12914 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12915 mips_cpreturn_register
, 0);
12918 demand_empty_rest_of_line ();
12921 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12922 code. It sets the offset to use in gp_rel relocations. */
12925 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12927 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12928 We also need NewABI support. */
12929 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12935 mips_gprel_offset
= get_absolute_expression ();
12937 demand_empty_rest_of_line ();
12940 /* Handle the .gpword pseudo-op. This is used when generating PIC
12941 code. It generates a 32 bit GP relative reloc. */
12944 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12946 segment_info_type
*si
;
12947 struct insn_label_list
*l
;
12952 /* When not generating PIC code, this is treated as .word. */
12953 if (mips_pic
!= SVR4_PIC
)
12959 si
= seg_info (now_seg
);
12960 l
= si
->label_list
;
12961 label
= l
!= NULL
? l
->label
: NULL
;
12962 mips_emit_delays ();
12964 mips_align (2, 0, label
);
12965 mips_clear_insn_labels ();
12969 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12971 as_bad (_("Unsupported use of .gpword"));
12972 ignore_rest_of_line ();
12976 md_number_to_chars (p
, 0, 4);
12977 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12978 BFD_RELOC_GPREL32
);
12980 demand_empty_rest_of_line ();
12984 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12986 segment_info_type
*si
;
12987 struct insn_label_list
*l
;
12992 /* When not generating PIC code, this is treated as .dword. */
12993 if (mips_pic
!= SVR4_PIC
)
12999 si
= seg_info (now_seg
);
13000 l
= si
->label_list
;
13001 label
= l
!= NULL
? l
->label
: NULL
;
13002 mips_emit_delays ();
13004 mips_align (3, 0, label
);
13005 mips_clear_insn_labels ();
13009 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13011 as_bad (_("Unsupported use of .gpdword"));
13012 ignore_rest_of_line ();
13016 md_number_to_chars (p
, 0, 8);
13017 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13018 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13020 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13021 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13022 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13024 demand_empty_rest_of_line ();
13027 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13028 tables in SVR4 PIC code. */
13031 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13035 /* This is ignored when not generating SVR4 PIC code. */
13036 if (mips_pic
!= SVR4_PIC
)
13042 /* Add $gp to the register named as an argument. */
13044 reg
= tc_get_register (0);
13045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13048 demand_empty_rest_of_line ();
13051 /* Handle the .insn pseudo-op. This marks instruction labels in
13052 mips16 mode. This permits the linker to handle them specially,
13053 such as generating jalx instructions when needed. We also make
13054 them odd for the duration of the assembly, in order to generate the
13055 right sort of code. We will make them even in the adjust_symtab
13056 routine, while leaving them marked. This is convenient for the
13057 debugger and the disassembler. The linker knows to make them odd
13061 s_insn (int ignore ATTRIBUTE_UNUSED
)
13063 mips16_mark_labels ();
13065 demand_empty_rest_of_line ();
13068 /* Handle a .stabn directive. We need these in order to mark a label
13069 as being a mips16 text label correctly. Sometimes the compiler
13070 will emit a label, followed by a .stabn, and then switch sections.
13071 If the label and .stabn are in mips16 mode, then the label is
13072 really a mips16 text label. */
13075 s_mips_stab (int type
)
13078 mips16_mark_labels ();
13083 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13086 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13093 name
= input_line_pointer
;
13094 c
= get_symbol_end ();
13095 symbolP
= symbol_find_or_make (name
);
13096 S_SET_WEAK (symbolP
);
13097 *input_line_pointer
= c
;
13099 SKIP_WHITESPACE ();
13101 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13103 if (S_IS_DEFINED (symbolP
))
13105 as_bad ("ignoring attempt to redefine symbol %s",
13106 S_GET_NAME (symbolP
));
13107 ignore_rest_of_line ();
13111 if (*input_line_pointer
== ',')
13113 ++input_line_pointer
;
13114 SKIP_WHITESPACE ();
13118 if (exp
.X_op
!= O_symbol
)
13120 as_bad ("bad .weakext directive");
13121 ignore_rest_of_line ();
13124 symbol_set_value_expression (symbolP
, &exp
);
13127 demand_empty_rest_of_line ();
13130 /* Parse a register string into a number. Called from the ECOFF code
13131 to parse .frame. The argument is non-zero if this is the frame
13132 register, so that we can record it in mips_frame_reg. */
13135 tc_get_register (int frame
)
13139 SKIP_WHITESPACE ();
13140 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13144 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13145 mips_frame_reg_valid
= 1;
13146 mips_cprestore_valid
= 0;
13152 md_section_align (asection
*seg
, valueT addr
)
13154 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13158 /* We don't need to align ELF sections to the full alignment.
13159 However, Irix 5 may prefer that we align them at least to a 16
13160 byte boundary. We don't bother to align the sections if we
13161 are targeted for an embedded system. */
13162 if (strcmp (TARGET_OS
, "elf") == 0)
13168 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13171 /* Utility routine, called from above as well. If called while the
13172 input file is still being read, it's only an approximation. (For
13173 example, a symbol may later become defined which appeared to be
13174 undefined earlier.) */
13177 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13182 if (g_switch_value
> 0)
13184 const char *symname
;
13187 /* Find out whether this symbol can be referenced off the $gp
13188 register. It can be if it is smaller than the -G size or if
13189 it is in the .sdata or .sbss section. Certain symbols can
13190 not be referenced off the $gp, although it appears as though
13192 symname
= S_GET_NAME (sym
);
13193 if (symname
!= (const char *) NULL
13194 && (strcmp (symname
, "eprol") == 0
13195 || strcmp (symname
, "etext") == 0
13196 || strcmp (symname
, "_gp") == 0
13197 || strcmp (symname
, "edata") == 0
13198 || strcmp (symname
, "_fbss") == 0
13199 || strcmp (symname
, "_fdata") == 0
13200 || strcmp (symname
, "_ftext") == 0
13201 || strcmp (symname
, "end") == 0
13202 || strcmp (symname
, "_gp_disp") == 0))
13204 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13206 #ifndef NO_ECOFF_DEBUGGING
13207 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13208 && (symbol_get_obj (sym
)->ecoff_extern_size
13209 <= g_switch_value
))
13211 /* We must defer this decision until after the whole
13212 file has been read, since there might be a .extern
13213 after the first use of this symbol. */
13214 || (before_relaxing
13215 #ifndef NO_ECOFF_DEBUGGING
13216 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13218 && S_GET_VALUE (sym
) == 0)
13219 || (S_GET_VALUE (sym
) != 0
13220 && S_GET_VALUE (sym
) <= g_switch_value
)))
13224 const char *segname
;
13226 segname
= segment_name (S_GET_SEGMENT (sym
));
13227 assert (strcmp (segname
, ".lit8") != 0
13228 && strcmp (segname
, ".lit4") != 0);
13229 change
= (strcmp (segname
, ".sdata") != 0
13230 && strcmp (segname
, ".sbss") != 0
13231 && strncmp (segname
, ".sdata.", 7) != 0
13232 && strncmp (segname
, ".sbss.", 6) != 0
13233 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13234 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13239 /* We are not optimizing for the $gp register. */
13244 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13247 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13251 /* Handle the case of a symbol equated to another symbol. */
13252 while (symbol_equated_reloc_p (sym
))
13256 /* It's possible to get a loop here in a badly written program. */
13257 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13263 if (symbol_section_p (sym
))
13266 symsec
= S_GET_SEGMENT (sym
);
13268 /* This must duplicate the test in adjust_reloc_syms. */
13269 return (symsec
!= &bfd_und_section
13270 && symsec
!= &bfd_abs_section
13271 && !bfd_is_com_section (symsec
)
13272 && !s_is_linkonce (sym
, segtype
)
13274 /* A global or weak symbol is treated as external. */
13275 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13281 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13282 extended opcode. SEC is the section the frag is in. */
13285 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13288 const struct mips16_immed_operand
*op
;
13290 int mintiny
, maxtiny
;
13294 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13296 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13299 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13300 op
= mips16_immed_operands
;
13301 while (op
->type
!= type
)
13304 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13309 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13312 maxtiny
= 1 << op
->nbits
;
13317 maxtiny
= (1 << op
->nbits
) - 1;
13322 mintiny
= - (1 << (op
->nbits
- 1));
13323 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13326 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13327 val
= S_GET_VALUE (fragp
->fr_symbol
);
13328 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13334 /* We won't have the section when we are called from
13335 mips_relax_frag. However, we will always have been called
13336 from md_estimate_size_before_relax first. If this is a
13337 branch to a different section, we mark it as such. If SEC is
13338 NULL, and the frag is not marked, then it must be a branch to
13339 the same section. */
13342 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13347 /* Must have been called from md_estimate_size_before_relax. */
13350 fragp
->fr_subtype
=
13351 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13353 /* FIXME: We should support this, and let the linker
13354 catch branches and loads that are out of range. */
13355 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13356 _("unsupported PC relative reference to different section"));
13360 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13361 /* Assume non-extended on the first relaxation pass.
13362 The address we have calculated will be bogus if this is
13363 a forward branch to another frag, as the forward frag
13364 will have fr_address == 0. */
13368 /* In this case, we know for sure that the symbol fragment is in
13369 the same section. If the relax_marker of the symbol fragment
13370 differs from the relax_marker of this fragment, we have not
13371 yet adjusted the symbol fragment fr_address. We want to add
13372 in STRETCH in order to get a better estimate of the address.
13373 This particularly matters because of the shift bits. */
13375 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13379 /* Adjust stretch for any alignment frag. Note that if have
13380 been expanding the earlier code, the symbol may be
13381 defined in what appears to be an earlier frag. FIXME:
13382 This doesn't handle the fr_subtype field, which specifies
13383 a maximum number of bytes to skip when doing an
13385 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13387 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13390 stretch
= - ((- stretch
)
13391 & ~ ((1 << (int) f
->fr_offset
) - 1));
13393 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13402 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13404 /* The base address rules are complicated. The base address of
13405 a branch is the following instruction. The base address of a
13406 PC relative load or add is the instruction itself, but if it
13407 is in a delay slot (in which case it can not be extended) use
13408 the address of the instruction whose delay slot it is in. */
13409 if (type
== 'p' || type
== 'q')
13413 /* If we are currently assuming that this frag should be
13414 extended, then, the current address is two bytes
13416 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13419 /* Ignore the low bit in the target, since it will be set
13420 for a text label. */
13421 if ((val
& 1) != 0)
13424 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13426 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13429 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13431 /* Branch offsets have an implicit 0 in the lowest bit. */
13432 if (type
== 'p' || type
== 'q')
13435 /* If any of the shifted bits are set, we must use an extended
13436 opcode. If the address depends on the size of this
13437 instruction, this can lead to a loop, so we arrange to always
13438 use an extended opcode. We only check this when we are in
13439 the main relaxation loop, when SEC is NULL. */
13440 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13442 fragp
->fr_subtype
=
13443 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13447 /* If we are about to mark a frag as extended because the value
13448 is precisely maxtiny + 1, then there is a chance of an
13449 infinite loop as in the following code:
13454 In this case when the la is extended, foo is 0x3fc bytes
13455 away, so the la can be shrunk, but then foo is 0x400 away, so
13456 the la must be extended. To avoid this loop, we mark the
13457 frag as extended if it was small, and is about to become
13458 extended with a value of maxtiny + 1. */
13459 if (val
== ((maxtiny
+ 1) << op
->shift
)
13460 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13463 fragp
->fr_subtype
=
13464 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13468 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13469 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13471 if ((val
& ((1 << op
->shift
) - 1)) != 0
13472 || val
< (mintiny
<< op
->shift
)
13473 || val
> (maxtiny
<< op
->shift
))
13479 /* Compute the length of a branch sequence, and adjust the
13480 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13481 worst-case length is computed, with UPDATE being used to indicate
13482 whether an unconditional (-1), branch-likely (+1) or regular (0)
13483 branch is to be computed. */
13485 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13487 bfd_boolean toofar
;
13491 && S_IS_DEFINED (fragp
->fr_symbol
)
13492 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13497 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13499 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13503 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13506 /* If the symbol is not defined or it's in a different segment,
13507 assume the user knows what's going on and emit a short
13513 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13515 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13516 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13517 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13523 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13526 if (mips_pic
!= NO_PIC
)
13528 /* Additional space for PIC loading of target address. */
13530 if (mips_opts
.isa
== ISA_MIPS1
)
13531 /* Additional space for $at-stabilizing nop. */
13535 /* If branch is conditional. */
13536 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13543 /* Estimate the size of a frag before relaxing. Unless this is the
13544 mips16, we are not really relaxing here, and the final size is
13545 encoded in the subtype information. For the mips16, we have to
13546 decide whether we are using an extended opcode or not. */
13549 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13553 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13556 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13558 return fragp
->fr_var
;
13561 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13562 /* We don't want to modify the EXTENDED bit here; it might get us
13563 into infinite loops. We change it only in mips_relax_frag(). */
13564 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13566 if (mips_pic
== NO_PIC
)
13567 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13568 else if (mips_pic
== SVR4_PIC
)
13569 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13570 else if (mips_pic
== VXWORKS_PIC
)
13571 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13578 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13579 return -RELAX_FIRST (fragp
->fr_subtype
);
13582 return -RELAX_SECOND (fragp
->fr_subtype
);
13585 /* This is called to see whether a reloc against a defined symbol
13586 should be converted into a reloc against a section. */
13589 mips_fix_adjustable (fixS
*fixp
)
13591 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13592 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13595 if (fixp
->fx_addsy
== NULL
)
13598 /* If symbol SYM is in a mergeable section, relocations of the form
13599 SYM + 0 can usually be made section-relative. The mergeable data
13600 is then identified by the section offset rather than by the symbol.
13602 However, if we're generating REL LO16 relocations, the offset is split
13603 between the LO16 and parterning high part relocation. The linker will
13604 need to recalculate the complete offset in order to correctly identify
13607 The linker has traditionally not looked for the parterning high part
13608 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13609 placed anywhere. Rather than break backwards compatibility by changing
13610 this, it seems better not to force the issue, and instead keep the
13611 original symbol. This will work with either linker behavior. */
13612 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13613 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13614 || reloc_needs_lo_p (fixp
->fx_r_type
))
13615 && HAVE_IN_PLACE_ADDENDS
13616 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13620 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13621 to a floating-point stub. The same is true for non-R_MIPS16_26
13622 relocations against MIPS16 functions; in this case, the stub becomes
13623 the function's canonical address.
13625 Floating-point stubs are stored in unique .mips16.call.* or
13626 .mips16.fn.* sections. If a stub T for function F is in section S,
13627 the first relocation in section S must be against F; this is how the
13628 linker determines the target function. All relocations that might
13629 resolve to T must also be against F. We therefore have the following
13630 restrictions, which are given in an intentionally-redundant way:
13632 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
13635 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
13636 if that stub might be used.
13638 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
13641 4. We cannot reduce a stub's relocations against MIPS16 symbols if
13642 that stub might be used.
13644 There is a further restriction:
13646 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
13647 on targets with in-place addends; the relocation field cannot
13648 encode the low bit.
13650 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
13651 against a MIPS16 symbol.
13653 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
13654 relocation against some symbol R, no relocation against R may be
13655 reduced. (Note that this deals with (2) as well as (1) because
13656 relocations against global symbols will never be reduced on ELF
13657 targets.) This approach is a little simpler than trying to detect
13658 stub sections, and gives the "all or nothing" per-symbol consistency
13659 that we have for MIPS16 symbols. */
13661 && fixp
->fx_subsy
== NULL
13662 && (S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13663 || *symbol_get_tc (fixp
->fx_addsy
)))
13670 /* Translate internal representation of relocation info to BFD target
13674 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13676 static arelent
*retval
[4];
13678 bfd_reloc_code_real_type code
;
13680 memset (retval
, 0, sizeof(retval
));
13681 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13682 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13683 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13684 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13686 if (fixp
->fx_pcrel
)
13688 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13690 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13691 Relocations want only the symbol offset. */
13692 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13695 /* A gruesome hack which is a result of the gruesome gas
13696 reloc handling. What's worse, for COFF (as opposed to
13697 ECOFF), we might need yet another copy of reloc->address.
13698 See bfd_install_relocation. */
13699 reloc
->addend
+= reloc
->address
;
13703 reloc
->addend
= fixp
->fx_addnumber
;
13705 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13706 entry to be used in the relocation's section offset. */
13707 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13709 reloc
->address
= reloc
->addend
;
13713 code
= fixp
->fx_r_type
;
13715 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13716 if (reloc
->howto
== NULL
)
13718 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13719 _("Can not represent %s relocation in this object file format"),
13720 bfd_get_reloc_code_name (code
));
13727 /* Relax a machine dependent frag. This returns the amount by which
13728 the current size of the frag should change. */
13731 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13733 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13735 offsetT old_var
= fragp
->fr_var
;
13737 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13739 return fragp
->fr_var
- old_var
;
13742 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13745 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13747 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13749 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13754 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13756 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13763 /* Convert a machine dependent frag. */
13766 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13768 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13771 unsigned long insn
;
13775 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13777 if (target_big_endian
)
13778 insn
= bfd_getb32 (buf
);
13780 insn
= bfd_getl32 (buf
);
13782 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13784 /* We generate a fixup instead of applying it right now
13785 because, if there are linker relaxations, we're going to
13786 need the relocations. */
13787 exp
.X_op
= O_symbol
;
13788 exp
.X_add_symbol
= fragp
->fr_symbol
;
13789 exp
.X_add_number
= fragp
->fr_offset
;
13791 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13792 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
13793 fixp
->fx_file
= fragp
->fr_file
;
13794 fixp
->fx_line
= fragp
->fr_line
;
13796 md_number_to_chars ((char *) buf
, insn
, 4);
13803 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13804 _("relaxed out-of-range branch into a jump"));
13806 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13809 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13811 /* Reverse the branch. */
13812 switch ((insn
>> 28) & 0xf)
13815 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13816 have the condition reversed by tweaking a single
13817 bit, and their opcodes all have 0x4???????. */
13818 assert ((insn
& 0xf1000000) == 0x41000000);
13819 insn
^= 0x00010000;
13823 /* bltz 0x04000000 bgez 0x04010000
13824 bltzal 0x04100000 bgezal 0x04110000 */
13825 assert ((insn
& 0xfc0e0000) == 0x04000000);
13826 insn
^= 0x00010000;
13830 /* beq 0x10000000 bne 0x14000000
13831 blez 0x18000000 bgtz 0x1c000000 */
13832 insn
^= 0x04000000;
13840 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13842 /* Clear the and-link bit. */
13843 assert ((insn
& 0xfc1c0000) == 0x04100000);
13845 /* bltzal 0x04100000 bgezal 0x04110000
13846 bltzall 0x04120000 bgezall 0x04130000 */
13847 insn
&= ~0x00100000;
13850 /* Branch over the branch (if the branch was likely) or the
13851 full jump (not likely case). Compute the offset from the
13852 current instruction to branch to. */
13853 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13857 /* How many bytes in instructions we've already emitted? */
13858 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13859 /* How many bytes in instructions from here to the end? */
13860 i
= fragp
->fr_var
- i
;
13862 /* Convert to instruction count. */
13864 /* Branch counts from the next instruction. */
13867 /* Branch over the jump. */
13868 md_number_to_chars ((char *) buf
, insn
, 4);
13872 md_number_to_chars ((char *) buf
, 0, 4);
13875 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13877 /* beql $0, $0, 2f */
13879 /* Compute the PC offset from the current instruction to
13880 the end of the variable frag. */
13881 /* How many bytes in instructions we've already emitted? */
13882 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13883 /* How many bytes in instructions from here to the end? */
13884 i
= fragp
->fr_var
- i
;
13885 /* Convert to instruction count. */
13887 /* Don't decrement i, because we want to branch over the
13891 md_number_to_chars ((char *) buf
, insn
, 4);
13894 md_number_to_chars ((char *) buf
, 0, 4);
13899 if (mips_pic
== NO_PIC
)
13902 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13903 ? 0x0c000000 : 0x08000000);
13904 exp
.X_op
= O_symbol
;
13905 exp
.X_add_symbol
= fragp
->fr_symbol
;
13906 exp
.X_add_number
= fragp
->fr_offset
;
13908 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13909 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
13910 fixp
->fx_file
= fragp
->fr_file
;
13911 fixp
->fx_line
= fragp
->fr_line
;
13913 md_number_to_chars ((char *) buf
, insn
, 4);
13918 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13919 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13920 exp
.X_op
= O_symbol
;
13921 exp
.X_add_symbol
= fragp
->fr_symbol
;
13922 exp
.X_add_number
= fragp
->fr_offset
;
13924 if (fragp
->fr_offset
)
13926 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13927 exp
.X_add_number
= 0;
13930 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13931 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
13932 fixp
->fx_file
= fragp
->fr_file
;
13933 fixp
->fx_line
= fragp
->fr_line
;
13935 md_number_to_chars ((char *) buf
, insn
, 4);
13938 if (mips_opts
.isa
== ISA_MIPS1
)
13941 md_number_to_chars ((char *) buf
, 0, 4);
13945 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13946 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13948 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13949 4, &exp
, FALSE
, BFD_RELOC_LO16
);
13950 fixp
->fx_file
= fragp
->fr_file
;
13951 fixp
->fx_line
= fragp
->fr_line
;
13953 md_number_to_chars ((char *) buf
, insn
, 4);
13957 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13962 md_number_to_chars ((char *) buf
, insn
, 4);
13967 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13968 + fragp
->fr_fix
+ fragp
->fr_var
);
13970 fragp
->fr_fix
+= fragp
->fr_var
;
13975 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13978 const struct mips16_immed_operand
*op
;
13979 bfd_boolean small
, ext
;
13982 unsigned long insn
;
13983 bfd_boolean use_extend
;
13984 unsigned short extend
;
13986 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13987 op
= mips16_immed_operands
;
13988 while (op
->type
!= type
)
13991 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14002 resolve_symbol_value (fragp
->fr_symbol
);
14003 val
= S_GET_VALUE (fragp
->fr_symbol
);
14008 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14010 /* The rules for the base address of a PC relative reloc are
14011 complicated; see mips16_extended_frag. */
14012 if (type
== 'p' || type
== 'q')
14017 /* Ignore the low bit in the target, since it will be
14018 set for a text label. */
14019 if ((val
& 1) != 0)
14022 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14024 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14027 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14030 /* Make sure the section winds up with the alignment we have
14033 record_alignment (asec
, op
->shift
);
14037 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14038 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14039 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14040 _("extended instruction in delay slot"));
14042 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14044 if (target_big_endian
)
14045 insn
= bfd_getb16 (buf
);
14047 insn
= bfd_getl16 (buf
);
14049 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14050 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14051 small
, ext
, &insn
, &use_extend
, &extend
);
14055 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14056 fragp
->fr_fix
+= 2;
14060 md_number_to_chars ((char *) buf
, insn
, 2);
14061 fragp
->fr_fix
+= 2;
14069 first
= RELAX_FIRST (fragp
->fr_subtype
);
14070 second
= RELAX_SECOND (fragp
->fr_subtype
);
14071 fixp
= (fixS
*) fragp
->fr_opcode
;
14073 /* Possibly emit a warning if we've chosen the longer option. */
14074 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14075 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14077 const char *msg
= macro_warning (fragp
->fr_subtype
);
14079 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14082 /* Go through all the fixups for the first sequence. Disable them
14083 (by marking them as done) if we're going to use the second
14084 sequence instead. */
14086 && fixp
->fx_frag
== fragp
14087 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14089 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14091 fixp
= fixp
->fx_next
;
14094 /* Go through the fixups for the second sequence. Disable them if
14095 we're going to use the first sequence, otherwise adjust their
14096 addresses to account for the relaxation. */
14097 while (fixp
&& fixp
->fx_frag
== fragp
)
14099 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14100 fixp
->fx_where
-= first
;
14103 fixp
= fixp
->fx_next
;
14106 /* Now modify the frag contents. */
14107 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14111 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14112 memmove (start
, start
+ first
, second
);
14113 fragp
->fr_fix
-= first
;
14116 fragp
->fr_fix
-= second
;
14122 /* This function is called after the relocs have been generated.
14123 We've been storing mips16 text labels as odd. Here we convert them
14124 back to even for the convenience of the debugger. */
14127 mips_frob_file_after_relocs (void)
14130 unsigned int count
, i
;
14135 syms
= bfd_get_outsymbols (stdoutput
);
14136 count
= bfd_get_symcount (stdoutput
);
14137 for (i
= 0; i
< count
; i
++, syms
++)
14139 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14140 && ((*syms
)->value
& 1) != 0)
14142 (*syms
)->value
&= ~1;
14143 /* If the symbol has an odd size, it was probably computed
14144 incorrectly, so adjust that as well. */
14145 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14146 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14153 /* This function is called whenever a label is defined. It is used
14154 when handling branch delays; if a branch has a label, we assume we
14155 can not move it. */
14158 mips_define_label (symbolS
*sym
)
14160 segment_info_type
*si
= seg_info (now_seg
);
14161 struct insn_label_list
*l
;
14163 if (free_insn_labels
== NULL
)
14164 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14167 l
= free_insn_labels
;
14168 free_insn_labels
= l
->next
;
14172 l
->next
= si
->label_list
;
14173 si
->label_list
= l
;
14176 dwarf2_emit_label (sym
);
14180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14182 /* Some special processing for a MIPS ELF file. */
14185 mips_elf_final_processing (void)
14187 /* Write out the register information. */
14188 if (mips_abi
!= N64_ABI
)
14192 s
.ri_gprmask
= mips_gprmask
;
14193 s
.ri_cprmask
[0] = mips_cprmask
[0];
14194 s
.ri_cprmask
[1] = mips_cprmask
[1];
14195 s
.ri_cprmask
[2] = mips_cprmask
[2];
14196 s
.ri_cprmask
[3] = mips_cprmask
[3];
14197 /* The gp_value field is set by the MIPS ELF backend. */
14199 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14200 ((Elf32_External_RegInfo
*)
14201 mips_regmask_frag
));
14205 Elf64_Internal_RegInfo s
;
14207 s
.ri_gprmask
= mips_gprmask
;
14209 s
.ri_cprmask
[0] = mips_cprmask
[0];
14210 s
.ri_cprmask
[1] = mips_cprmask
[1];
14211 s
.ri_cprmask
[2] = mips_cprmask
[2];
14212 s
.ri_cprmask
[3] = mips_cprmask
[3];
14213 /* The gp_value field is set by the MIPS ELF backend. */
14215 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14216 ((Elf64_External_RegInfo
*)
14217 mips_regmask_frag
));
14220 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14221 sort of BFD interface for this. */
14222 if (mips_any_noreorder
)
14223 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14224 if (mips_pic
!= NO_PIC
)
14226 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14227 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14230 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14232 /* Set MIPS ELF flags for ASEs. */
14233 /* We may need to define a new flag for DSP ASE, and set this flag when
14234 file_ase_dsp is true. */
14235 /* Same for DSP R2. */
14236 /* We may need to define a new flag for MT ASE, and set this flag when
14237 file_ase_mt is true. */
14238 if (file_ase_mips16
)
14239 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14240 #if 0 /* XXX FIXME */
14241 if (file_ase_mips3d
)
14242 elf_elfheader (stdoutput
)->e_flags
|= ???;
14245 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14247 /* Set the MIPS ELF ABI flags. */
14248 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14249 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14250 else if (mips_abi
== O64_ABI
)
14251 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14252 else if (mips_abi
== EABI_ABI
)
14254 if (!file_mips_gp32
)
14255 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14257 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14259 else if (mips_abi
== N32_ABI
)
14260 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14262 /* Nothing to do for N64_ABI. */
14264 if (mips_32bitmode
)
14265 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14267 #if 0 /* XXX FIXME */
14268 /* 32 bit code with 64 bit FP registers. */
14269 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14270 elf_elfheader (stdoutput
)->e_flags
|= ???;
14274 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14276 typedef struct proc
{
14278 symbolS
*func_end_sym
;
14279 unsigned long reg_mask
;
14280 unsigned long reg_offset
;
14281 unsigned long fpreg_mask
;
14282 unsigned long fpreg_offset
;
14283 unsigned long frame_offset
;
14284 unsigned long frame_reg
;
14285 unsigned long pc_reg
;
14288 static procS cur_proc
;
14289 static procS
*cur_proc_ptr
;
14290 static int numprocs
;
14292 /* Fill in an rs_align_code fragment. */
14295 mips_handle_align (fragS
*fragp
)
14297 if (fragp
->fr_type
!= rs_align_code
)
14300 if (mips_opts
.mips16
)
14302 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14303 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14308 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14309 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14317 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14321 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14325 md_obj_begin (void)
14332 /* Check for premature end, nesting errors, etc. */
14334 as_warn (_("missing .end at end of assembly"));
14343 if (*input_line_pointer
== '-')
14345 ++input_line_pointer
;
14348 if (!ISDIGIT (*input_line_pointer
))
14349 as_bad (_("expected simple number"));
14350 if (input_line_pointer
[0] == '0')
14352 if (input_line_pointer
[1] == 'x')
14354 input_line_pointer
+= 2;
14355 while (ISXDIGIT (*input_line_pointer
))
14358 val
|= hex_value (*input_line_pointer
++);
14360 return negative
? -val
: val
;
14364 ++input_line_pointer
;
14365 while (ISDIGIT (*input_line_pointer
))
14368 val
|= *input_line_pointer
++ - '0';
14370 return negative
? -val
: val
;
14373 if (!ISDIGIT (*input_line_pointer
))
14375 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14376 *input_line_pointer
, *input_line_pointer
);
14377 as_warn (_("invalid number"));
14380 while (ISDIGIT (*input_line_pointer
))
14383 val
+= *input_line_pointer
++ - '0';
14385 return negative
? -val
: val
;
14388 /* The .file directive; just like the usual .file directive, but there
14389 is an initial number which is the ECOFF file index. In the non-ECOFF
14390 case .file implies DWARF-2. */
14393 s_mips_file (int x ATTRIBUTE_UNUSED
)
14395 static int first_file_directive
= 0;
14397 if (ECOFF_DEBUGGING
)
14406 filename
= dwarf2_directive_file (0);
14408 /* Versions of GCC up to 3.1 start files with a ".file"
14409 directive even for stabs output. Make sure that this
14410 ".file" is handled. Note that you need a version of GCC
14411 after 3.1 in order to support DWARF-2 on MIPS. */
14412 if (filename
!= NULL
&& ! first_file_directive
)
14414 (void) new_logical_line (filename
, -1);
14415 s_app_file_string (filename
, 0);
14417 first_file_directive
= 1;
14421 /* The .loc directive, implying DWARF-2. */
14424 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14426 if (!ECOFF_DEBUGGING
)
14427 dwarf2_directive_loc (0);
14430 /* The .end directive. */
14433 s_mips_end (int x ATTRIBUTE_UNUSED
)
14437 /* Following functions need their own .frame and .cprestore directives. */
14438 mips_frame_reg_valid
= 0;
14439 mips_cprestore_valid
= 0;
14441 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14444 demand_empty_rest_of_line ();
14449 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14450 as_warn (_(".end not in text section"));
14454 as_warn (_(".end directive without a preceding .ent directive."));
14455 demand_empty_rest_of_line ();
14461 assert (S_GET_NAME (p
));
14462 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14463 as_warn (_(".end symbol does not match .ent symbol."));
14465 if (debug_type
== DEBUG_STABS
)
14466 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14470 as_warn (_(".end directive missing or unknown symbol"));
14473 /* Create an expression to calculate the size of the function. */
14474 if (p
&& cur_proc_ptr
)
14476 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14477 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14480 exp
->X_op
= O_subtract
;
14481 exp
->X_add_symbol
= symbol_temp_new_now ();
14482 exp
->X_op_symbol
= p
;
14483 exp
->X_add_number
= 0;
14485 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14488 /* Generate a .pdr section. */
14489 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14491 segT saved_seg
= now_seg
;
14492 subsegT saved_subseg
= now_subseg
;
14497 dot
= frag_now_fix ();
14499 #ifdef md_flush_pending_output
14500 md_flush_pending_output ();
14504 subseg_set (pdr_seg
, 0);
14506 /* Write the symbol. */
14507 exp
.X_op
= O_symbol
;
14508 exp
.X_add_symbol
= p
;
14509 exp
.X_add_number
= 0;
14510 emit_expr (&exp
, 4);
14512 fragp
= frag_more (7 * 4);
14514 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14515 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14516 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14517 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14518 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14519 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14520 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14522 subseg_set (saved_seg
, saved_subseg
);
14524 #endif /* OBJ_ELF */
14526 cur_proc_ptr
= NULL
;
14529 /* The .aent and .ent directives. */
14532 s_mips_ent (int aent
)
14536 symbolP
= get_symbol ();
14537 if (*input_line_pointer
== ',')
14538 ++input_line_pointer
;
14539 SKIP_WHITESPACE ();
14540 if (ISDIGIT (*input_line_pointer
)
14541 || *input_line_pointer
== '-')
14544 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14545 as_warn (_(".ent or .aent not in text section."));
14547 if (!aent
&& cur_proc_ptr
)
14548 as_warn (_("missing .end"));
14552 /* This function needs its own .frame and .cprestore directives. */
14553 mips_frame_reg_valid
= 0;
14554 mips_cprestore_valid
= 0;
14556 cur_proc_ptr
= &cur_proc
;
14557 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14559 cur_proc_ptr
->func_sym
= symbolP
;
14561 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14565 if (debug_type
== DEBUG_STABS
)
14566 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14567 S_GET_NAME (symbolP
));
14570 demand_empty_rest_of_line ();
14573 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14574 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14575 s_mips_frame is used so that we can set the PDR information correctly.
14576 We can't use the ecoff routines because they make reference to the ecoff
14577 symbol table (in the mdebug section). */
14580 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14583 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14587 if (cur_proc_ptr
== (procS
*) NULL
)
14589 as_warn (_(".frame outside of .ent"));
14590 demand_empty_rest_of_line ();
14594 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14596 SKIP_WHITESPACE ();
14597 if (*input_line_pointer
++ != ','
14598 || get_absolute_expression_and_terminator (&val
) != ',')
14600 as_warn (_("Bad .frame directive"));
14601 --input_line_pointer
;
14602 demand_empty_rest_of_line ();
14606 cur_proc_ptr
->frame_offset
= val
;
14607 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14609 demand_empty_rest_of_line ();
14612 #endif /* OBJ_ELF */
14616 /* The .fmask and .mask directives. If the mdebug section is present
14617 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14618 embedded targets, s_mips_mask is used so that we can set the PDR
14619 information correctly. We can't use the ecoff routines because they
14620 make reference to the ecoff symbol table (in the mdebug section). */
14623 s_mips_mask (int reg_type
)
14626 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14630 if (cur_proc_ptr
== (procS
*) NULL
)
14632 as_warn (_(".mask/.fmask outside of .ent"));
14633 demand_empty_rest_of_line ();
14637 if (get_absolute_expression_and_terminator (&mask
) != ',')
14639 as_warn (_("Bad .mask/.fmask directive"));
14640 --input_line_pointer
;
14641 demand_empty_rest_of_line ();
14645 off
= get_absolute_expression ();
14647 if (reg_type
== 'F')
14649 cur_proc_ptr
->fpreg_mask
= mask
;
14650 cur_proc_ptr
->fpreg_offset
= off
;
14654 cur_proc_ptr
->reg_mask
= mask
;
14655 cur_proc_ptr
->reg_offset
= off
;
14658 demand_empty_rest_of_line ();
14661 #endif /* OBJ_ELF */
14662 s_ignore (reg_type
);
14665 /* A table describing all the processors gas knows about. Names are
14666 matched in the order listed.
14668 To ease comparison, please keep this table in the same order as
14669 gcc's mips_cpu_info_table[]. */
14670 static const struct mips_cpu_info mips_cpu_info_table
[] =
14672 /* Entries for generic ISAs */
14673 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14674 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14675 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14676 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14677 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14678 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14679 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14680 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14681 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14684 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14685 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14686 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14689 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14692 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14693 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14694 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14695 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14696 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14697 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14698 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14699 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14700 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14701 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14702 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14703 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14706 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14707 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14708 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14709 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14710 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14711 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14712 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14713 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14714 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14715 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14716 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14717 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14718 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14721 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14722 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14723 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14724 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
14726 /* MIPS 32 Release 2 */
14727 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14728 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14729 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14730 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14731 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14732 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14733 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14734 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14735 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14736 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
14737 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14738 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14739 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14740 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
14741 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14742 ISA_MIPS32R2
, CPU_MIPS32R2
},
14743 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14744 ISA_MIPS32R2
, CPU_MIPS32R2
},
14745 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14746 ISA_MIPS32R2
, CPU_MIPS32R2
},
14747 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
14748 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14749 ISA_MIPS32R2
, CPU_MIPS32R2
},
14750 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14751 ISA_MIPS32R2
, CPU_MIPS32R2
},
14752 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14753 ISA_MIPS32R2
, CPU_MIPS32R2
},
14756 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14757 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14758 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14759 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14761 /* MIPS 64 Release 2 */
14763 /* Broadcom SB-1 CPU core */
14764 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14765 ISA_MIPS64
, CPU_SB1
},
14766 /* Broadcom SB-1A CPU core */
14767 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14768 ISA_MIPS64
, CPU_SB1
},
14775 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14776 with a final "000" replaced by "k". Ignore case.
14778 Note: this function is shared between GCC and GAS. */
14781 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14783 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14784 given
++, canonical
++;
14786 return ((*given
== 0 && *canonical
== 0)
14787 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14791 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14792 CPU name. We've traditionally allowed a lot of variation here.
14794 Note: this function is shared between GCC and GAS. */
14797 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14799 /* First see if the name matches exactly, or with a final "000"
14800 turned into "k". */
14801 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14804 /* If not, try comparing based on numerical designation alone.
14805 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14806 if (TOLOWER (*given
) == 'r')
14808 if (!ISDIGIT (*given
))
14811 /* Skip over some well-known prefixes in the canonical name,
14812 hoping to find a number there too. */
14813 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14815 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14817 else if (TOLOWER (canonical
[0]) == 'r')
14820 return mips_strict_matching_cpu_name_p (canonical
, given
);
14824 /* Parse an option that takes the name of a processor as its argument.
14825 OPTION is the name of the option and CPU_STRING is the argument.
14826 Return the corresponding processor enumeration if the CPU_STRING is
14827 recognized, otherwise report an error and return null.
14829 A similar function exists in GCC. */
14831 static const struct mips_cpu_info
*
14832 mips_parse_cpu (const char *option
, const char *cpu_string
)
14834 const struct mips_cpu_info
*p
;
14836 /* 'from-abi' selects the most compatible architecture for the given
14837 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14838 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14839 version. Look first at the -mgp options, if given, otherwise base
14840 the choice on MIPS_DEFAULT_64BIT.
14842 Treat NO_ABI like the EABIs. One reason to do this is that the
14843 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14844 architecture. This code picks MIPS I for 'mips' and MIPS III for
14845 'mips64', just as we did in the days before 'from-abi'. */
14846 if (strcasecmp (cpu_string
, "from-abi") == 0)
14848 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14849 return mips_cpu_info_from_isa (ISA_MIPS1
);
14851 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14852 return mips_cpu_info_from_isa (ISA_MIPS3
);
14854 if (file_mips_gp32
>= 0)
14855 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14857 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14862 /* 'default' has traditionally been a no-op. Probably not very useful. */
14863 if (strcasecmp (cpu_string
, "default") == 0)
14866 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14867 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14870 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14874 /* Return the canonical processor information for ISA (a member of the
14875 ISA_MIPS* enumeration). */
14877 static const struct mips_cpu_info
*
14878 mips_cpu_info_from_isa (int isa
)
14882 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14883 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
14884 && isa
== mips_cpu_info_table
[i
].isa
)
14885 return (&mips_cpu_info_table
[i
]);
14890 static const struct mips_cpu_info
*
14891 mips_cpu_info_from_arch (int arch
)
14895 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14896 if (arch
== mips_cpu_info_table
[i
].cpu
)
14897 return (&mips_cpu_info_table
[i
]);
14903 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14907 fprintf (stream
, "%24s", "");
14912 fprintf (stream
, ", ");
14916 if (*col_p
+ strlen (string
) > 72)
14918 fprintf (stream
, "\n%24s", "");
14922 fprintf (stream
, "%s", string
);
14923 *col_p
+= strlen (string
);
14929 md_show_usage (FILE *stream
)
14934 fprintf (stream
, _("\
14936 -EB generate big endian output\n\
14937 -EL generate little endian output\n\
14938 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14939 -G NUM allow referencing objects up to NUM bytes\n\
14940 implicitly with the gp register [default 8]\n"));
14941 fprintf (stream
, _("\
14942 -mips1 generate MIPS ISA I instructions\n\
14943 -mips2 generate MIPS ISA II instructions\n\
14944 -mips3 generate MIPS ISA III instructions\n\
14945 -mips4 generate MIPS ISA IV instructions\n\
14946 -mips5 generate MIPS ISA V instructions\n\
14947 -mips32 generate MIPS32 ISA instructions\n\
14948 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14949 -mips64 generate MIPS64 ISA instructions\n\
14950 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14951 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14955 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14956 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14957 show (stream
, "from-abi", &column
, &first
);
14958 fputc ('\n', stream
);
14960 fprintf (stream
, _("\
14961 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14962 -no-mCPU don't generate code specific to CPU.\n\
14963 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14967 show (stream
, "3900", &column
, &first
);
14968 show (stream
, "4010", &column
, &first
);
14969 show (stream
, "4100", &column
, &first
);
14970 show (stream
, "4650", &column
, &first
);
14971 fputc ('\n', stream
);
14973 fprintf (stream
, _("\
14974 -mips16 generate mips16 instructions\n\
14975 -no-mips16 do not generate mips16 instructions\n"));
14976 fprintf (stream
, _("\
14977 -msmartmips generate smartmips instructions\n\
14978 -mno-smartmips do not generate smartmips instructions\n"));
14979 fprintf (stream
, _("\
14980 -mdsp generate DSP instructions\n\
14981 -mno-dsp do not generate DSP instructions\n"));
14982 fprintf (stream
, _("\
14983 -mdspr2 generate DSP R2 instructions\n\
14984 -mno-dspr2 do not generate DSP R2 instructions\n"));
14985 fprintf (stream
, _("\
14986 -mmt generate MT instructions\n\
14987 -mno-mt do not generate MT instructions\n"));
14988 fprintf (stream
, _("\
14989 -mfix-vr4120 work around certain VR4120 errata\n\
14990 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14991 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14992 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14993 -msym32 assume all symbols have 32-bit values\n\
14994 -O0 remove unneeded NOPs, do not swap branches\n\
14995 -O remove unneeded NOPs and swap branches\n\
14996 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14997 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14998 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15000 fprintf (stream
, _("\
15001 -KPIC, -call_shared generate SVR4 position independent code\n\
15002 -mvxworks-pic generate VxWorks position independent code\n\
15003 -non_shared do not generate position independent code\n\
15004 -xgot assume a 32 bit GOT\n\
15005 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15006 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15007 position dependent (non shared) code\n\
15008 -mabi=ABI create ABI conformant object file for:\n"));
15012 show (stream
, "32", &column
, &first
);
15013 show (stream
, "o64", &column
, &first
);
15014 show (stream
, "n32", &column
, &first
);
15015 show (stream
, "64", &column
, &first
);
15016 show (stream
, "eabi", &column
, &first
);
15018 fputc ('\n', stream
);
15020 fprintf (stream
, _("\
15021 -32 create o32 ABI object file (default)\n\
15022 -n32 create n32 ABI object file\n\
15023 -64 create 64 ABI object file\n"));
15028 mips_dwarf2_format (void)
15030 if (mips_abi
== N64_ABI
)
15033 return dwarf2_format_64bit_irix
;
15035 return dwarf2_format_64bit
;
15039 return dwarf2_format_32bit
;
15043 mips_dwarf2_addr_size (void)
15045 if (mips_abi
== N64_ABI
)
15051 /* Standard calling conventions leave the CFA at SP on entry. */
15053 mips_cfi_frame_initial_instructions (void)
15055 cfi_add_CFA_def_cfa_register (SP
);
15059 tc_mips_regname_to_dw2regnum (char *regname
)
15061 unsigned int regnum
= -1;
15064 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))