1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format
{
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error
{
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format
;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error
;
671 static int auto_align
= 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset
= -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset
= -1;
683 static int mips_cpreturn_register
= -1;
684 static int mips_gp_register
= GP
;
685 static int mips_gprel_offset
= 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid
= 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg
= SP
;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid
= 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize
= 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug
= 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history
[1 + MAX_NOPS
];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array
{
731 const struct mips_operand
*operand
[MAX_OPERANDS
];
733 static struct mips_operand_array
*mips_operands
;
734 static struct mips_operand_array
*mips16_operands
;
735 static struct mips_operand_array
*micromips_operands
;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn
;
739 static struct mips_cl_insn mips16_nop_insn
;
740 static struct mips_cl_insn micromips_nop16_insn
;
741 static struct mips_cl_insn micromips_nop32_insn
;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS
*prev_nop_frag
;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds
;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required
;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since
;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup
*next
;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup
*mips_hi_fixup_list
;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS
*prev_reloc_op_frag
;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map
[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1
[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2
[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map
[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump
;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop
;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f
;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120
;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130
;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k
;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1
;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch
;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes
[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p
;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length
;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes
[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes
[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns
[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning
;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1226 static void append_insn
1227 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1228 bfd_boolean expansionp
);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS
*, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS
*, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS
*, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn
*ip
, char *str
);
1237 static void mips16_macro (struct mips_cl_insn
* ip
);
1238 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1239 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1245 static void my_getExpression (expressionS
*, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type
);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1282 static int relaxed_branch_length (fragS
*, asection
*, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name
; /* CPU or ISA name. */
1292 int flags
; /* MIPS_CPU_* flags. */
1293 int ase
; /* Set of ASEs implemented by the CPU. */
1294 int isa
; /* ISA level. */
1295 int cpu
; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts
= "O::g::G:";
1309 OPTION_MARCH
= OPTION_MD_BASE
,
1333 OPTION_NO_SMARTMIPS
,
1339 OPTION_NO_MICROMIPS
,
1342 OPTION_COMPAT_ARCH_BASE
,
1351 OPTION_M7000_HILO_FIX
,
1352 OPTION_MNO_7000_HILO_FIX
,
1355 OPTION_FIX_LOONGSON2F_JUMP
,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1357 OPTION_FIX_LOONGSON2F_NOP
,
1358 OPTION_NO_FIX_LOONGSON2F_NOP
,
1360 OPTION_NO_FIX_VR4120
,
1362 OPTION_NO_FIX_VR4130
,
1363 OPTION_FIX_CN63XXP1
,
1364 OPTION_NO_FIX_CN63XXP1
,
1371 OPTION_CONSTRUCT_FLOATS
,
1372 OPTION_NO_CONSTRUCT_FLOATS
,
1375 OPTION_RELAX_BRANCH
,
1376 OPTION_NO_RELAX_BRANCH
,
1385 OPTION_SINGLE_FLOAT
,
1386 OPTION_DOUBLE_FLOAT
,
1399 OPTION_MVXWORKS_PIC
,
1404 struct option md_longopts
[] =
1406 /* Options which specify architecture. */
1407 {"march", required_argument
, NULL
, OPTION_MARCH
},
1408 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1409 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1410 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1411 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1412 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1413 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1414 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1415 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1416 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1417 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1418 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1422 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1423 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1424 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1425 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1426 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1427 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1428 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1429 {"mmt", no_argument
, NULL
, OPTION_MT
},
1430 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1431 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1432 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1433 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1434 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1435 {"meva", no_argument
, NULL
, OPTION_EVA
},
1436 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1437 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1438 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1439 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1440 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1441 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1442 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1446 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1447 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1448 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1449 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1450 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1451 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1452 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1456 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1457 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1458 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1459 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1460 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1461 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1462 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1463 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1464 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1465 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1466 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1467 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1468 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1469 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1471 /* Miscellaneous options. */
1472 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1473 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1474 {"break", no_argument
, NULL
, OPTION_BREAK
},
1475 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1476 {"EB", no_argument
, NULL
, OPTION_EB
},
1477 {"EL", no_argument
, NULL
, OPTION_EL
},
1478 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1479 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1480 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1481 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1482 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1483 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1484 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1485 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1486 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1487 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1488 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1489 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1490 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1491 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1492 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1493 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1494 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1495 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument
, NULL
, OPTION_32
},
1502 /* ELF-specific options. */
1503 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1504 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1505 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1506 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1507 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1508 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1509 {"n32", no_argument
, NULL
, OPTION_N32
},
1510 {"64", no_argument
, NULL
, OPTION_64
},
1511 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1512 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1513 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1514 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1515 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1516 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1518 {NULL
, no_argument
, NULL
, 0}
1520 size_t md_longopts_size
= sizeof (md_longopts
);
1522 /* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1527 /* The name of the ASE, used in both the command-line and .set options. */
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64
;
1539 /* The command-line options that turn the ASE on and off. */
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1547 int micromips32_rev
;
1548 int micromips64_rev
;
1551 /* A table of all supported ASEs. */
1552 static const struct mips_ase mips_ases
[] = {
1553 { "dsp", ASE_DSP
, ASE_DSP64
,
1554 OPTION_DSP
, OPTION_NO_DSP
,
1557 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1558 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1561 { "eva", ASE_EVA
, 0,
1562 OPTION_EVA
, OPTION_NO_EVA
,
1565 { "mcu", ASE_MCU
, 0,
1566 OPTION_MCU
, OPTION_NO_MCU
,
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX
, 0,
1571 OPTION_MDMX
, OPTION_NO_MDMX
,
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D
, 0,
1576 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1580 OPTION_MT
, OPTION_NO_MT
,
1583 { "smartmips", ASE_SMARTMIPS
, 0,
1584 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1587 { "virt", ASE_VIRT
, ASE_VIRT64
,
1588 OPTION_VIRT
, OPTION_NO_VIRT
,
1592 /* The set of ASEs that require -mfp64. */
1593 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1595 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1596 static const unsigned int mips_ase_groups
[] = {
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
1617 static const pseudo_typeS mips_pseudo_table
[] =
1619 /* MIPS specific pseudo-ops. */
1620 {"option", s_option
, 0},
1621 {"set", s_mipsset
, 0},
1622 {"rdata", s_change_sec
, 'r'},
1623 {"sdata", s_change_sec
, 's'},
1624 {"livereg", s_ignore
, 0},
1625 {"abicalls", s_abicalls
, 0},
1626 {"cpload", s_cpload
, 0},
1627 {"cpsetup", s_cpsetup
, 0},
1628 {"cplocal", s_cplocal
, 0},
1629 {"cprestore", s_cprestore
, 0},
1630 {"cpreturn", s_cpreturn
, 0},
1631 {"dtprelword", s_dtprelword
, 0},
1632 {"dtpreldword", s_dtpreldword
, 0},
1633 {"tprelword", s_tprelword
, 0},
1634 {"tpreldword", s_tpreldword
, 0},
1635 {"gpvalue", s_gpvalue
, 0},
1636 {"gpword", s_gpword
, 0},
1637 {"gpdword", s_gpdword
, 0},
1638 {"ehword", s_ehword
, 0},
1639 {"cpadd", s_cpadd
, 0},
1640 {"insn", s_insn
, 0},
1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
1645 {"asciiz", stringer
, 8 + 1},
1646 {"bss", s_change_sec
, 'b'},
1648 {"half", s_cons
, 1},
1649 {"dword", s_cons
, 3},
1650 {"weakext", s_mips_weakext
, 0},
1651 {"origin", s_org
, 0},
1652 {"repeat", s_rept
, 0},
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec
, 'B'},
1657 /* These pseudo-ops are defined in read.c, but must be overridden
1658 here for one reason or another. */
1659 {"align", s_align
, 0},
1660 {"byte", s_cons
, 0},
1661 {"data", s_change_sec
, 'd'},
1662 {"double", s_float_cons
, 'd'},
1663 {"float", s_float_cons
, 'f'},
1664 {"globl", s_mips_globl
, 0},
1665 {"global", s_mips_globl
, 0},
1666 {"hword", s_cons
, 1},
1668 {"long", s_cons
, 2},
1669 {"octa", s_cons
, 4},
1670 {"quad", s_cons
, 3},
1671 {"section", s_change_section
, 0},
1672 {"short", s_cons
, 1},
1673 {"single", s_float_cons
, 'f'},
1674 {"stabd", s_mips_stab
, 'd'},
1675 {"stabn", s_mips_stab
, 'n'},
1676 {"stabs", s_mips_stab
, 's'},
1677 {"text", s_change_sec
, 't'},
1678 {"word", s_cons
, 2},
1680 { "extern", ecoff_directive_extern
, 0},
1685 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
1689 {"aent", s_mips_ent
, 1},
1690 {"bgnb", s_ignore
, 0},
1691 {"end", s_mips_end
, 0},
1692 {"endb", s_ignore
, 0},
1693 {"ent", s_mips_ent
, 0},
1694 {"file", s_mips_file
, 0},
1695 {"fmask", s_mips_mask
, 'F'},
1696 {"frame", s_mips_frame
, 0},
1697 {"loc", s_mips_loc
, 0},
1698 {"mask", s_mips_mask
, 'R'},
1699 {"verstamp", s_ignore
, 0},
1703 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1707 mips_address_bytes (void)
1709 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1712 extern void pop_insert (const pseudo_typeS
*);
1715 mips_pop_insert (void)
1717 pop_insert (mips_pseudo_table
);
1718 if (! ECOFF_DEBUGGING
)
1719 pop_insert (mips_nonecoff_pseudo_table
);
1722 /* Symbols labelling the current insn. */
1724 struct insn_label_list
1726 struct insn_label_list
*next
;
1730 static struct insn_label_list
*free_insn_labels
;
1731 #define label_list tc_segment_info_data.labels
1733 static void mips_clear_insn_labels (void);
1734 static void mips_mark_labels (void);
1735 static void mips_compressed_mark_labels (void);
1738 mips_clear_insn_labels (void)
1740 register struct insn_label_list
**pl
;
1741 segment_info_type
*si
;
1745 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1748 si
= seg_info (now_seg
);
1749 *pl
= si
->label_list
;
1750 si
->label_list
= NULL
;
1754 /* Mark instruction labels in MIPS16/microMIPS mode. */
1757 mips_mark_labels (void)
1759 if (HAVE_CODE_COMPRESSION
)
1760 mips_compressed_mark_labels ();
1763 static char *expr_end
;
1765 /* Expressions which appear in macro instructions. These are set by
1766 mips_ip and read by macro. */
1768 static expressionS imm_expr
;
1769 static expressionS imm2_expr
;
1771 /* The relocatable field in an instruction and the relocs associated
1772 with it. These variables are used for instructions like LUI and
1773 JAL as well as true offsets. They are also used for address
1774 operands in macros. */
1776 static expressionS offset_expr
;
1777 static bfd_reloc_code_real_type offset_reloc
[3]
1778 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1780 /* This is set to the resulting size of the instruction to be produced
1781 by mips16_ip if an explicit extension is used or by mips_ip if an
1782 explicit size is supplied. */
1784 static unsigned int forced_insn_length
;
1786 /* True if we are assembling an instruction. All dot symbols defined during
1787 this time should be treated as code labels. */
1789 static bfd_boolean mips_assembling_insn
;
1791 /* The pdr segment for per procedure frame/regmask info. Not used for
1794 static segT pdr_seg
;
1796 /* The default target format to use. */
1798 #if defined (TE_FreeBSD)
1799 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1800 #elif defined (TE_TMIPS)
1801 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1803 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1807 mips_target_format (void)
1809 switch (OUTPUT_FLAVOR
)
1811 case bfd_target_elf_flavour
:
1813 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1814 return (target_big_endian
1815 ? "elf32-bigmips-vxworks"
1816 : "elf32-littlemips-vxworks");
1818 return (target_big_endian
1819 ? (HAVE_64BIT_OBJECTS
1820 ? ELF_TARGET ("elf64-", "big")
1822 ? ELF_TARGET ("elf32-n", "big")
1823 : ELF_TARGET ("elf32-", "big")))
1824 : (HAVE_64BIT_OBJECTS
1825 ? ELF_TARGET ("elf64-", "little")
1827 ? ELF_TARGET ("elf32-n", "little")
1828 : ELF_TARGET ("elf32-", "little"))));
1835 /* Return the ISA revision that is currently in use, or 0 if we are
1836 generating code for MIPS V or below. */
1841 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1844 /* microMIPS implies revision 2 or above. */
1845 if (mips_opts
.micromips
)
1848 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1854 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1857 mips_ase_mask (unsigned int flags
)
1861 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1862 if (flags
& mips_ase_groups
[i
])
1863 flags
|= mips_ase_groups
[i
];
1867 /* Check whether the current ISA supports ASE. Issue a warning if
1871 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1875 static unsigned int warned_isa
;
1876 static unsigned int warned_fp32
;
1878 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1879 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1881 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1882 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1883 && (warned_isa
& ase
->flags
) != ase
->flags
)
1885 warned_isa
|= ase
->flags
;
1886 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1887 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1889 as_warn (_("The %d-bit %s architecture does not support the"
1890 " `%s' extension"), size
, base
, ase
->name
);
1892 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1893 ase
->name
, base
, size
, min_rev
);
1895 if ((ase
->flags
& FP64_ASES
)
1897 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1899 warned_fp32
|= ase
->flags
;
1900 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1904 /* Check all enabled ASEs to see whether they are supported by the
1905 chosen architecture. */
1908 mips_check_isa_supports_ases (void)
1910 unsigned int i
, mask
;
1912 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1914 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1915 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1916 mips_check_isa_supports_ase (&mips_ases
[i
]);
1920 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1921 that were affected. */
1924 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1928 mask
= mips_ase_mask (ase
->flags
);
1929 mips_opts
.ase
&= ~mask
;
1931 mips_opts
.ase
|= ase
->flags
;
1935 /* Return the ASE called NAME, or null if none. */
1937 static const struct mips_ase
*
1938 mips_lookup_ase (const char *name
)
1942 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1943 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1944 return &mips_ases
[i
];
1948 /* Return the length of a microMIPS instruction in bytes. If bits of
1949 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1950 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1951 major opcode) will require further modifications to the opcode
1954 static inline unsigned int
1955 micromips_insn_length (const struct mips_opcode
*mo
)
1957 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1960 /* Return the length of MIPS16 instruction OPCODE. */
1962 static inline unsigned int
1963 mips16_opcode_length (unsigned long opcode
)
1965 return (opcode
>> 16) == 0 ? 2 : 4;
1968 /* Return the length of instruction INSN. */
1970 static inline unsigned int
1971 insn_length (const struct mips_cl_insn
*insn
)
1973 if (mips_opts
.micromips
)
1974 return micromips_insn_length (insn
->insn_mo
);
1975 else if (mips_opts
.mips16
)
1976 return mips16_opcode_length (insn
->insn_opcode
);
1981 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1984 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1989 insn
->insn_opcode
= mo
->match
;
1992 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1993 insn
->fixp
[i
] = NULL
;
1994 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1995 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1996 insn
->mips16_absolute_jump_p
= 0;
1997 insn
->complete_p
= 0;
1998 insn
->cleared_p
= 0;
2001 /* Get a list of all the operands in INSN. */
2003 static const struct mips_operand_array
*
2004 insn_operands (const struct mips_cl_insn
*insn
)
2006 if (insn
->insn_mo
>= &mips_opcodes
[0]
2007 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2008 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2010 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2011 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2012 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2014 if (insn
->insn_mo
>= µmips_opcodes
[0]
2015 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2016 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2021 /* Get a description of operand OPNO of INSN. */
2023 static const struct mips_operand
*
2024 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2026 const struct mips_operand_array
*operands
;
2028 operands
= insn_operands (insn
);
2029 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2031 return operands
->operand
[opno
];
2034 /* Install UVAL as the value of OPERAND in INSN. */
2037 insn_insert_operand (struct mips_cl_insn
*insn
,
2038 const struct mips_operand
*operand
, unsigned int uval
)
2040 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2043 /* Extract the value of OPERAND from INSN. */
2045 static inline unsigned
2046 insn_extract_operand (const struct mips_cl_insn
*insn
,
2047 const struct mips_operand
*operand
)
2049 return mips_extract_operand (operand
, insn
->insn_opcode
);
2052 /* Record the current MIPS16/microMIPS mode in now_seg. */
2055 mips_record_compressed_mode (void)
2057 segment_info_type
*si
;
2059 si
= seg_info (now_seg
);
2060 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2061 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2062 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2063 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2066 /* Read a standard MIPS instruction from BUF. */
2068 static unsigned long
2069 read_insn (char *buf
)
2071 if (target_big_endian
)
2072 return bfd_getb32 ((bfd_byte
*) buf
);
2074 return bfd_getl32 ((bfd_byte
*) buf
);
2077 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2081 write_insn (char *buf
, unsigned int insn
)
2083 md_number_to_chars (buf
, insn
, 4);
2087 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2090 static unsigned long
2091 read_compressed_insn (char *buf
, unsigned int length
)
2097 for (i
= 0; i
< length
; i
+= 2)
2100 if (target_big_endian
)
2101 insn
|= bfd_getb16 ((char *) buf
);
2103 insn
|= bfd_getl16 ((char *) buf
);
2109 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2113 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2117 for (i
= 0; i
< length
; i
+= 2)
2118 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2119 return buf
+ length
;
2122 /* Install INSN at the location specified by its "frag" and "where" fields. */
2125 install_insn (const struct mips_cl_insn
*insn
)
2127 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2128 if (HAVE_CODE_COMPRESSION
)
2129 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2131 write_insn (f
, insn
->insn_opcode
);
2132 mips_record_compressed_mode ();
2135 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2139 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2144 insn
->where
= where
;
2145 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2146 if (insn
->fixp
[i
] != NULL
)
2148 insn
->fixp
[i
]->fx_frag
= frag
;
2149 insn
->fixp
[i
]->fx_where
= where
;
2151 install_insn (insn
);
2154 /* Add INSN to the end of the output. */
2157 add_fixed_insn (struct mips_cl_insn
*insn
)
2159 char *f
= frag_more (insn_length (insn
));
2160 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2163 /* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2167 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2168 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2170 frag_grow (max_chars
);
2171 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2173 frag_var (rs_machine_dependent
, max_chars
, var
,
2174 subtype
, symbol
, offset
, NULL
);
2177 /* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2181 insert_into_history (unsigned int first
, unsigned int n
,
2182 const struct mips_cl_insn
*insn
)
2184 if (mips_relax
.sequence
!= 2)
2188 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2190 history
[i
] = history
[i
- n
];
2196 /* Clear the error in insn_error. */
2199 clear_insn_error (void)
2201 memset (&insn_error
, 0, sizeof (insn_error
));
2204 /* Possibly record error message MSG for the current instruction.
2205 If the error is about a particular argument, ARGNUM is the 1-based
2206 number of that argument, otherwise it is 0. FORMAT is the format
2207 of MSG. Return true if MSG was used, false if the current message
2211 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2216 /* Give priority to errors against specific arguments, and to
2217 the first whole-instruction message. */
2223 /* Keep insn_error if it is against a later argument. */
2224 if (argnum
< insn_error
.min_argnum
)
2227 /* If both errors are against the same argument but are different,
2228 give up on reporting a specific error for this argument.
2229 See the comment about mips_insn_error for details. */
2230 if (argnum
== insn_error
.min_argnum
2232 && strcmp (insn_error
.msg
, msg
) != 0)
2235 insn_error
.min_argnum
+= 1;
2239 insn_error
.min_argnum
= argnum
;
2240 insn_error
.format
= format
;
2241 insn_error
.msg
= msg
;
2245 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2246 as for set_insn_error_format. */
2249 set_insn_error (int argnum
, const char *msg
)
2251 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2254 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2255 as for set_insn_error_format. */
2258 set_insn_error_i (int argnum
, const char *msg
, int i
)
2260 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2264 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2265 are as for set_insn_error_format. */
2268 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2270 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2272 insn_error
.u
.ss
[0] = s1
;
2273 insn_error
.u
.ss
[1] = s2
;
2277 /* Report the error in insn_error, which is against assembly code STR. */
2280 report_insn_error (const char *str
)
2284 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2285 switch (insn_error
.format
)
2292 as_bad (msg
, insn_error
.u
.i
, str
);
2296 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2301 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2302 the idea is to make it obvious at a glance that each errata is
2306 init_vr4120_conflicts (void)
2308 #define CONFLICT(FIRST, SECOND) \
2309 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2311 /* Errata 21 - [D]DIV[U] after [D]MACC */
2312 CONFLICT (MACC
, DIV
);
2313 CONFLICT (DMACC
, DIV
);
2315 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2316 CONFLICT (DMULT
, DMULT
);
2317 CONFLICT (DMULT
, DMACC
);
2318 CONFLICT (DMACC
, DMULT
);
2319 CONFLICT (DMACC
, DMACC
);
2321 /* Errata 24 - MT{LO,HI} after [D]MACC */
2322 CONFLICT (MACC
, MTHILO
);
2323 CONFLICT (DMACC
, MTHILO
);
2325 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2326 instruction is executed immediately after a MACC or DMACC
2327 instruction, the result of [either instruction] is incorrect." */
2328 CONFLICT (MACC
, MULT
);
2329 CONFLICT (MACC
, DMULT
);
2330 CONFLICT (DMACC
, MULT
);
2331 CONFLICT (DMACC
, DMULT
);
2333 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2334 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2335 DDIV or DDIVU instruction, the result of the MACC or
2336 DMACC instruction is incorrect.". */
2337 CONFLICT (DMULT
, MACC
);
2338 CONFLICT (DMULT
, DMACC
);
2339 CONFLICT (DIV
, MACC
);
2340 CONFLICT (DIV
, DMACC
);
2350 #define RNUM_MASK 0x00000ff
2351 #define RTYPE_MASK 0x0efff00
2352 #define RTYPE_NUM 0x0000100
2353 #define RTYPE_FPU 0x0000200
2354 #define RTYPE_FCC 0x0000400
2355 #define RTYPE_VEC 0x0000800
2356 #define RTYPE_GP 0x0001000
2357 #define RTYPE_CP0 0x0002000
2358 #define RTYPE_PC 0x0004000
2359 #define RTYPE_ACC 0x0008000
2360 #define RTYPE_CCC 0x0010000
2361 #define RTYPE_VI 0x0020000
2362 #define RTYPE_VF 0x0040000
2363 #define RTYPE_R5900_I 0x0080000
2364 #define RTYPE_R5900_Q 0x0100000
2365 #define RTYPE_R5900_R 0x0200000
2366 #define RTYPE_R5900_ACC 0x0400000
2367 #define RWARN 0x8000000
2369 #define GENERIC_REGISTER_NUMBERS \
2370 {"$0", RTYPE_NUM | 0}, \
2371 {"$1", RTYPE_NUM | 1}, \
2372 {"$2", RTYPE_NUM | 2}, \
2373 {"$3", RTYPE_NUM | 3}, \
2374 {"$4", RTYPE_NUM | 4}, \
2375 {"$5", RTYPE_NUM | 5}, \
2376 {"$6", RTYPE_NUM | 6}, \
2377 {"$7", RTYPE_NUM | 7}, \
2378 {"$8", RTYPE_NUM | 8}, \
2379 {"$9", RTYPE_NUM | 9}, \
2380 {"$10", RTYPE_NUM | 10}, \
2381 {"$11", RTYPE_NUM | 11}, \
2382 {"$12", RTYPE_NUM | 12}, \
2383 {"$13", RTYPE_NUM | 13}, \
2384 {"$14", RTYPE_NUM | 14}, \
2385 {"$15", RTYPE_NUM | 15}, \
2386 {"$16", RTYPE_NUM | 16}, \
2387 {"$17", RTYPE_NUM | 17}, \
2388 {"$18", RTYPE_NUM | 18}, \
2389 {"$19", RTYPE_NUM | 19}, \
2390 {"$20", RTYPE_NUM | 20}, \
2391 {"$21", RTYPE_NUM | 21}, \
2392 {"$22", RTYPE_NUM | 22}, \
2393 {"$23", RTYPE_NUM | 23}, \
2394 {"$24", RTYPE_NUM | 24}, \
2395 {"$25", RTYPE_NUM | 25}, \
2396 {"$26", RTYPE_NUM | 26}, \
2397 {"$27", RTYPE_NUM | 27}, \
2398 {"$28", RTYPE_NUM | 28}, \
2399 {"$29", RTYPE_NUM | 29}, \
2400 {"$30", RTYPE_NUM | 30}, \
2401 {"$31", RTYPE_NUM | 31}
2403 #define FPU_REGISTER_NAMES \
2404 {"$f0", RTYPE_FPU | 0}, \
2405 {"$f1", RTYPE_FPU | 1}, \
2406 {"$f2", RTYPE_FPU | 2}, \
2407 {"$f3", RTYPE_FPU | 3}, \
2408 {"$f4", RTYPE_FPU | 4}, \
2409 {"$f5", RTYPE_FPU | 5}, \
2410 {"$f6", RTYPE_FPU | 6}, \
2411 {"$f7", RTYPE_FPU | 7}, \
2412 {"$f8", RTYPE_FPU | 8}, \
2413 {"$f9", RTYPE_FPU | 9}, \
2414 {"$f10", RTYPE_FPU | 10}, \
2415 {"$f11", RTYPE_FPU | 11}, \
2416 {"$f12", RTYPE_FPU | 12}, \
2417 {"$f13", RTYPE_FPU | 13}, \
2418 {"$f14", RTYPE_FPU | 14}, \
2419 {"$f15", RTYPE_FPU | 15}, \
2420 {"$f16", RTYPE_FPU | 16}, \
2421 {"$f17", RTYPE_FPU | 17}, \
2422 {"$f18", RTYPE_FPU | 18}, \
2423 {"$f19", RTYPE_FPU | 19}, \
2424 {"$f20", RTYPE_FPU | 20}, \
2425 {"$f21", RTYPE_FPU | 21}, \
2426 {"$f22", RTYPE_FPU | 22}, \
2427 {"$f23", RTYPE_FPU | 23}, \
2428 {"$f24", RTYPE_FPU | 24}, \
2429 {"$f25", RTYPE_FPU | 25}, \
2430 {"$f26", RTYPE_FPU | 26}, \
2431 {"$f27", RTYPE_FPU | 27}, \
2432 {"$f28", RTYPE_FPU | 28}, \
2433 {"$f29", RTYPE_FPU | 29}, \
2434 {"$f30", RTYPE_FPU | 30}, \
2435 {"$f31", RTYPE_FPU | 31}
2437 #define FPU_CONDITION_CODE_NAMES \
2438 {"$fcc0", RTYPE_FCC | 0}, \
2439 {"$fcc1", RTYPE_FCC | 1}, \
2440 {"$fcc2", RTYPE_FCC | 2}, \
2441 {"$fcc3", RTYPE_FCC | 3}, \
2442 {"$fcc4", RTYPE_FCC | 4}, \
2443 {"$fcc5", RTYPE_FCC | 5}, \
2444 {"$fcc6", RTYPE_FCC | 6}, \
2445 {"$fcc7", RTYPE_FCC | 7}
2447 #define COPROC_CONDITION_CODE_NAMES \
2448 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2449 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2450 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2451 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2452 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2453 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2454 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2455 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2457 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2458 {"$a4", RTYPE_GP | 8}, \
2459 {"$a5", RTYPE_GP | 9}, \
2460 {"$a6", RTYPE_GP | 10}, \
2461 {"$a7", RTYPE_GP | 11}, \
2462 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2463 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2464 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2465 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2466 {"$t0", RTYPE_GP | 12}, \
2467 {"$t1", RTYPE_GP | 13}, \
2468 {"$t2", RTYPE_GP | 14}, \
2469 {"$t3", RTYPE_GP | 15}
2471 #define O32_SYMBOLIC_REGISTER_NAMES \
2472 {"$t0", RTYPE_GP | 8}, \
2473 {"$t1", RTYPE_GP | 9}, \
2474 {"$t2", RTYPE_GP | 10}, \
2475 {"$t3", RTYPE_GP | 11}, \
2476 {"$t4", RTYPE_GP | 12}, \
2477 {"$t5", RTYPE_GP | 13}, \
2478 {"$t6", RTYPE_GP | 14}, \
2479 {"$t7", RTYPE_GP | 15}, \
2480 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2481 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2482 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2483 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2485 /* Remaining symbolic register names */
2486 #define SYMBOLIC_REGISTER_NAMES \
2487 {"$zero", RTYPE_GP | 0}, \
2488 {"$at", RTYPE_GP | 1}, \
2489 {"$AT", RTYPE_GP | 1}, \
2490 {"$v0", RTYPE_GP | 2}, \
2491 {"$v1", RTYPE_GP | 3}, \
2492 {"$a0", RTYPE_GP | 4}, \
2493 {"$a1", RTYPE_GP | 5}, \
2494 {"$a2", RTYPE_GP | 6}, \
2495 {"$a3", RTYPE_GP | 7}, \
2496 {"$s0", RTYPE_GP | 16}, \
2497 {"$s1", RTYPE_GP | 17}, \
2498 {"$s2", RTYPE_GP | 18}, \
2499 {"$s3", RTYPE_GP | 19}, \
2500 {"$s4", RTYPE_GP | 20}, \
2501 {"$s5", RTYPE_GP | 21}, \
2502 {"$s6", RTYPE_GP | 22}, \
2503 {"$s7", RTYPE_GP | 23}, \
2504 {"$t8", RTYPE_GP | 24}, \
2505 {"$t9", RTYPE_GP | 25}, \
2506 {"$k0", RTYPE_GP | 26}, \
2507 {"$kt0", RTYPE_GP | 26}, \
2508 {"$k1", RTYPE_GP | 27}, \
2509 {"$kt1", RTYPE_GP | 27}, \
2510 {"$gp", RTYPE_GP | 28}, \
2511 {"$sp", RTYPE_GP | 29}, \
2512 {"$s8", RTYPE_GP | 30}, \
2513 {"$fp", RTYPE_GP | 30}, \
2514 {"$ra", RTYPE_GP | 31}
2516 #define MIPS16_SPECIAL_REGISTER_NAMES \
2517 {"$pc", RTYPE_PC | 0}
2519 #define MDMX_VECTOR_REGISTER_NAMES \
2520 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2521 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2522 {"$v2", RTYPE_VEC | 2}, \
2523 {"$v3", RTYPE_VEC | 3}, \
2524 {"$v4", RTYPE_VEC | 4}, \
2525 {"$v5", RTYPE_VEC | 5}, \
2526 {"$v6", RTYPE_VEC | 6}, \
2527 {"$v7", RTYPE_VEC | 7}, \
2528 {"$v8", RTYPE_VEC | 8}, \
2529 {"$v9", RTYPE_VEC | 9}, \
2530 {"$v10", RTYPE_VEC | 10}, \
2531 {"$v11", RTYPE_VEC | 11}, \
2532 {"$v12", RTYPE_VEC | 12}, \
2533 {"$v13", RTYPE_VEC | 13}, \
2534 {"$v14", RTYPE_VEC | 14}, \
2535 {"$v15", RTYPE_VEC | 15}, \
2536 {"$v16", RTYPE_VEC | 16}, \
2537 {"$v17", RTYPE_VEC | 17}, \
2538 {"$v18", RTYPE_VEC | 18}, \
2539 {"$v19", RTYPE_VEC | 19}, \
2540 {"$v20", RTYPE_VEC | 20}, \
2541 {"$v21", RTYPE_VEC | 21}, \
2542 {"$v22", RTYPE_VEC | 22}, \
2543 {"$v23", RTYPE_VEC | 23}, \
2544 {"$v24", RTYPE_VEC | 24}, \
2545 {"$v25", RTYPE_VEC | 25}, \
2546 {"$v26", RTYPE_VEC | 26}, \
2547 {"$v27", RTYPE_VEC | 27}, \
2548 {"$v28", RTYPE_VEC | 28}, \
2549 {"$v29", RTYPE_VEC | 29}, \
2550 {"$v30", RTYPE_VEC | 30}, \
2551 {"$v31", RTYPE_VEC | 31}
2553 #define R5900_I_NAMES \
2554 {"$I", RTYPE_R5900_I | 0}
2556 #define R5900_Q_NAMES \
2557 {"$Q", RTYPE_R5900_Q | 0}
2559 #define R5900_R_NAMES \
2560 {"$R", RTYPE_R5900_R | 0}
2562 #define R5900_ACC_NAMES \
2563 {"$ACC", RTYPE_R5900_ACC | 0 }
2565 #define MIPS_DSP_ACCUMULATOR_NAMES \
2566 {"$ac0", RTYPE_ACC | 0}, \
2567 {"$ac1", RTYPE_ACC | 1}, \
2568 {"$ac2", RTYPE_ACC | 2}, \
2569 {"$ac3", RTYPE_ACC | 3}
2571 static const struct regname reg_names
[] = {
2572 GENERIC_REGISTER_NUMBERS
,
2574 FPU_CONDITION_CODE_NAMES
,
2575 COPROC_CONDITION_CODE_NAMES
,
2577 /* The $txx registers depends on the abi,
2578 these will be added later into the symbol table from
2579 one of the tables below once mips_abi is set after
2580 parsing of arguments from the command line. */
2581 SYMBOLIC_REGISTER_NAMES
,
2583 MIPS16_SPECIAL_REGISTER_NAMES
,
2584 MDMX_VECTOR_REGISTER_NAMES
,
2589 MIPS_DSP_ACCUMULATOR_NAMES
,
2593 static const struct regname reg_names_o32
[] = {
2594 O32_SYMBOLIC_REGISTER_NAMES
,
2598 static const struct regname reg_names_n32n64
[] = {
2599 N32N64_SYMBOLIC_REGISTER_NAMES
,
2603 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2604 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2605 of these register symbols, return the associated vector register,
2606 otherwise return SYMVAL itself. */
2609 mips_prefer_vec_regno (unsigned int symval
)
2611 if ((symval
& -2) == (RTYPE_GP
| 2))
2612 return RTYPE_VEC
| (symval
& 1);
2616 /* Return true if string [S, E) is a valid register name, storing its
2617 symbol value in *SYMVAL_PTR if so. */
2620 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2625 /* Terminate name. */
2629 /* Look up the name. */
2630 symbol
= symbol_find (s
);
2633 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2636 *symval_ptr
= S_GET_VALUE (symbol
);
2640 /* Return true if the string at *SPTR is a valid register name. Allow it
2641 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2644 When returning true, move *SPTR past the register, store the
2645 register's symbol value in *SYMVAL_PTR and the channel mask in
2646 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2647 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2648 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2651 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2652 unsigned int *channels_ptr
)
2656 unsigned int channels
, symval
, bit
;
2658 /* Find end of name. */
2660 if (is_name_beginner (*e
))
2662 while (is_part_of_name (*e
))
2666 if (!mips_parse_register_1 (s
, e
, &symval
))
2671 /* Eat characters from the end of the string that are valid
2672 channel suffixes. The preceding register must be $ACC or
2673 end with a digit, so there is no ambiguity. */
2676 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2677 if (m
> s
&& m
[-1] == *q
)
2684 || !mips_parse_register_1 (s
, m
, &symval
)
2685 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2690 *symval_ptr
= symval
;
2692 *channels_ptr
= channels
;
2696 /* Check if SPTR points at a valid register specifier according to TYPES.
2697 If so, then return 1, advance S to consume the specifier and store
2698 the register's number in REGNOP, otherwise return 0. */
2701 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2705 if (mips_parse_register (s
, ®no
, NULL
))
2707 if (types
& RTYPE_VEC
)
2708 regno
= mips_prefer_vec_regno (regno
);
2717 as_warn (_("Unrecognized register name `%s'"), *s
);
2722 return regno
<= RNUM_MASK
;
2725 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2726 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2729 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2734 for (i
= 0; i
< 4; i
++)
2735 if (*s
== "xyzw"[i
])
2737 *channels
|= 1 << (3 - i
);
2743 /* Token types for parsed operand lists. */
2744 enum mips_operand_token_type
{
2745 /* A plain register, e.g. $f2. */
2748 /* A 4-bit XYZW channel mask. */
2751 /* An element of a vector, e.g. $v0[1]. */
2754 /* A continuous range of registers, e.g. $s0-$s4. */
2757 /* A (possibly relocated) expression. */
2760 /* A floating-point value. */
2763 /* A single character. This can be '(', ')' or ',', but '(' only appears
2767 /* A doubled character, either "--" or "++". */
2770 /* The end of the operand list. */
2774 /* A parsed operand token. */
2775 struct mips_operand_token
2777 /* The type of token. */
2778 enum mips_operand_token_type type
;
2781 /* The register symbol value for an OT_REG. */
2784 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2785 unsigned int channels
;
2787 /* The register symbol value and index for an OT_REG_ELEMENT. */
2793 /* The two register symbol values involved in an OT_REG_RANGE. */
2795 unsigned int regno1
;
2796 unsigned int regno2
;
2799 /* The value of an OT_INTEGER. The value is represented as an
2800 expression and the relocation operators that were applied to
2801 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2802 relocation operators were used. */
2805 bfd_reloc_code_real_type relocs
[3];
2808 /* The binary data for an OT_FLOAT constant, and the number of bytes
2811 unsigned char data
[8];
2815 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2820 /* An obstack used to construct lists of mips_operand_tokens. */
2821 static struct obstack mips_operand_tokens
;
2823 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2826 mips_add_token (struct mips_operand_token
*token
,
2827 enum mips_operand_token_type type
)
2830 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2833 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2834 and OT_REG tokens for them if so, and return a pointer to the first
2835 unconsumed character. Return null otherwise. */
2838 mips_parse_base_start (char *s
)
2840 struct mips_operand_token token
;
2841 unsigned int regno
, channels
;
2842 bfd_boolean decrement_p
;
2848 SKIP_SPACE_TABS (s
);
2850 /* Only match "--" as part of a base expression. In other contexts "--X"
2851 is a double negative. */
2852 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2856 SKIP_SPACE_TABS (s
);
2859 /* Allow a channel specifier because that leads to better error messages
2860 than treating something like "$vf0x++" as an expression. */
2861 if (!mips_parse_register (&s
, ®no
, &channels
))
2865 mips_add_token (&token
, OT_CHAR
);
2870 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2873 token
.u
.regno
= regno
;
2874 mips_add_token (&token
, OT_REG
);
2878 token
.u
.channels
= channels
;
2879 mips_add_token (&token
, OT_CHANNELS
);
2882 /* For consistency, only match "++" as part of base expressions too. */
2883 SKIP_SPACE_TABS (s
);
2884 if (s
[0] == '+' && s
[1] == '+')
2888 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2894 /* Parse one or more tokens from S. Return a pointer to the first
2895 unconsumed character on success. Return null if an error was found
2896 and store the error text in insn_error. FLOAT_FORMAT is as for
2897 mips_parse_arguments. */
2900 mips_parse_argument_token (char *s
, char float_format
)
2902 char *end
, *save_in
, *err
;
2903 unsigned int regno1
, regno2
, channels
;
2904 struct mips_operand_token token
;
2906 /* First look for "($reg", since we want to treat that as an
2907 OT_CHAR and OT_REG rather than an expression. */
2908 end
= mips_parse_base_start (s
);
2912 /* Handle other characters that end up as OT_CHARs. */
2913 if (*s
== ')' || *s
== ',')
2916 mips_add_token (&token
, OT_CHAR
);
2921 /* Handle tokens that start with a register. */
2922 if (mips_parse_register (&s
, ®no1
, &channels
))
2926 /* A register and a VU0 channel suffix. */
2927 token
.u
.regno
= regno1
;
2928 mips_add_token (&token
, OT_REG
);
2930 token
.u
.channels
= channels
;
2931 mips_add_token (&token
, OT_CHANNELS
);
2935 SKIP_SPACE_TABS (s
);
2938 /* A register range. */
2940 SKIP_SPACE_TABS (s
);
2941 if (!mips_parse_register (&s
, ®no2
, NULL
))
2943 set_insn_error (0, _("Invalid register range"));
2947 token
.u
.reg_range
.regno1
= regno1
;
2948 token
.u
.reg_range
.regno2
= regno2
;
2949 mips_add_token (&token
, OT_REG_RANGE
);
2954 /* A vector element. */
2955 expressionS element
;
2958 SKIP_SPACE_TABS (s
);
2959 my_getExpression (&element
, s
);
2960 if (element
.X_op
!= O_constant
)
2962 set_insn_error (0, _("Vector element must be constant"));
2966 SKIP_SPACE_TABS (s
);
2969 set_insn_error (0, _("Missing `]'"));
2974 token
.u
.reg_element
.regno
= regno1
;
2975 token
.u
.reg_element
.index
= element
.X_add_number
;
2976 mips_add_token (&token
, OT_REG_ELEMENT
);
2980 /* Looks like just a plain register. */
2981 token
.u
.regno
= regno1
;
2982 mips_add_token (&token
, OT_REG
);
2988 /* First try to treat expressions as floats. */
2989 save_in
= input_line_pointer
;
2990 input_line_pointer
= s
;
2991 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2992 &token
.u
.flt
.length
);
2993 end
= input_line_pointer
;
2994 input_line_pointer
= save_in
;
2997 set_insn_error (0, err
);
3002 mips_add_token (&token
, OT_FLOAT
);
3007 /* Treat everything else as an integer expression. */
3008 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3009 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3010 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3011 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3013 mips_add_token (&token
, OT_INTEGER
);
3017 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3018 if expressions should be treated as 32-bit floating-point constants,
3019 'd' if they should be treated as 64-bit floating-point constants,
3020 or 0 if they should be treated as integer expressions (the usual case).
3022 Return a list of tokens on success, otherwise return 0. The caller
3023 must obstack_free the list after use. */
3025 static struct mips_operand_token
*
3026 mips_parse_arguments (char *s
, char float_format
)
3028 struct mips_operand_token token
;
3030 SKIP_SPACE_TABS (s
);
3033 s
= mips_parse_argument_token (s
, float_format
);
3036 obstack_free (&mips_operand_tokens
,
3037 obstack_finish (&mips_operand_tokens
));
3040 SKIP_SPACE_TABS (s
);
3042 mips_add_token (&token
, OT_END
);
3043 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3046 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3047 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3050 is_opcode_valid (const struct mips_opcode
*mo
)
3052 int isa
= mips_opts
.isa
;
3053 int ase
= mips_opts
.ase
;
3057 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3058 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3059 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3060 ase
|= mips_ases
[i
].flags64
;
3062 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3065 /* Check whether the instruction or macro requires single-precision or
3066 double-precision floating-point support. Note that this information is
3067 stored differently in the opcode table for insns and macros. */
3068 if (mo
->pinfo
== INSN_MACRO
)
3070 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3071 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3075 fp_s
= mo
->pinfo
& FP_S
;
3076 fp_d
= mo
->pinfo
& FP_D
;
3079 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3082 if (fp_s
&& mips_opts
.soft_float
)
3088 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3089 selected ISA and architecture. */
3092 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3094 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3097 /* Return TRUE if the size of the microMIPS opcode MO matches one
3098 explicitly requested. Always TRUE in the standard MIPS mode. */
3101 is_size_valid (const struct mips_opcode
*mo
)
3103 if (!mips_opts
.micromips
)
3106 if (mips_opts
.insn32
)
3108 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3110 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3113 if (!forced_insn_length
)
3115 if (mo
->pinfo
== INSN_MACRO
)
3117 return forced_insn_length
== micromips_insn_length (mo
);
3120 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3121 of the preceding instruction. Always TRUE in the standard MIPS mode.
3123 We don't accept macros in 16-bit delay slots to avoid a case where
3124 a macro expansion fails because it relies on a preceding 32-bit real
3125 instruction to have matched and does not handle the operands correctly.
3126 The only macros that may expand to 16-bit instructions are JAL that
3127 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3128 and BGT (that likewise cannot be placed in a delay slot) that decay to
3129 a NOP. In all these cases the macros precede any corresponding real
3130 instruction definitions in the opcode table, so they will match in the
3131 second pass where the size of the delay slot is ignored and therefore
3132 produce correct code. */
3135 is_delay_slot_valid (const struct mips_opcode
*mo
)
3137 if (!mips_opts
.micromips
)
3140 if (mo
->pinfo
== INSN_MACRO
)
3141 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3142 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3143 && micromips_insn_length (mo
) != 4)
3145 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3146 && micromips_insn_length (mo
) != 2)
3152 /* For consistency checking, verify that all bits of OPCODE are specified
3153 either by the match/mask part of the instruction definition, or by the
3154 operand list. Also build up a list of operands in OPERANDS.
3156 INSN_BITS says which bits of the instruction are significant.
3157 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3158 provides the mips_operand description of each operand. DECODE_OPERAND
3159 is null for MIPS16 instructions. */
3162 validate_mips_insn (const struct mips_opcode
*opcode
,
3163 unsigned long insn_bits
,
3164 const struct mips_operand
*(*decode_operand
) (const char *),
3165 struct mips_operand_array
*operands
)
3168 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3169 const struct mips_operand
*operand
;
3171 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3172 if ((mask
& opcode
->match
) != opcode
->match
)
3174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3175 opcode
->name
, opcode
->args
);
3180 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3181 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3182 for (s
= opcode
->args
; *s
; ++s
)
3195 if (!decode_operand
)
3196 operand
= decode_mips16_operand (*s
, FALSE
);
3198 operand
= decode_operand (s
);
3199 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3201 as_bad (_("internal: unknown operand type: %s %s"),
3202 opcode
->name
, opcode
->args
);
3205 gas_assert (opno
< MAX_OPERANDS
);
3206 operands
->operand
[opno
] = operand
;
3207 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3209 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3210 if (operand
->type
== OP_MDMX_IMM_REG
)
3211 /* Bit 5 is the format selector (OB vs QH). The opcode table
3212 has separate entries for each format. */
3213 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3214 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3215 used_bits
&= ~(mask
& 0x700);
3217 /* Skip prefix characters. */
3218 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3223 doubled
= used_bits
& mask
& insn_bits
;
3226 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3227 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3231 undefined
= ~used_bits
& insn_bits
;
3232 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3234 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3235 undefined
, opcode
->name
, opcode
->args
);
3238 used_bits
&= ~insn_bits
;
3241 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3242 used_bits
, opcode
->name
, opcode
->args
);
3248 /* The MIPS16 version of validate_mips_insn. */
3251 validate_mips16_insn (const struct mips_opcode
*opcode
,
3252 struct mips_operand_array
*operands
)
3254 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3256 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3257 instruction. Use TMP to describe the full instruction. */
3258 struct mips_opcode tmp
;
3263 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3265 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3268 /* The microMIPS version of validate_mips_insn. */
3271 validate_micromips_insn (const struct mips_opcode
*opc
,
3272 struct mips_operand_array
*operands
)
3274 unsigned long insn_bits
;
3275 unsigned long major
;
3276 unsigned int length
;
3278 if (opc
->pinfo
== INSN_MACRO
)
3279 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3282 length
= micromips_insn_length (opc
);
3283 if (length
!= 2 && length
!= 4)
3285 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3286 "%s %s"), length
, opc
->name
, opc
->args
);
3289 major
= opc
->match
>> (10 + 8 * (length
- 2));
3290 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3291 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3293 as_bad (_("Internal error: bad microMIPS opcode "
3294 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3298 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3299 insn_bits
= 1 << 4 * length
;
3300 insn_bits
<<= 4 * length
;
3302 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3306 /* This function is called once, at assembler startup time. It should set up
3307 all the tables, etc. that the MD part of the assembler will need. */
3312 const char *retval
= NULL
;
3316 if (mips_pic
!= NO_PIC
)
3318 if (g_switch_seen
&& g_switch_value
!= 0)
3319 as_bad (_("-G may not be used in position-independent code"));
3323 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3324 as_warn (_("Could not set architecture and machine"));
3326 op_hash
= hash_new ();
3328 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3329 for (i
= 0; i
< NUMOPCODES
;)
3331 const char *name
= mips_opcodes
[i
].name
;
3333 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3336 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3337 mips_opcodes
[i
].name
, retval
);
3338 /* Probably a memory allocation problem? Give up now. */
3339 as_fatal (_("Broken assembler. No assembly attempted."));
3343 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3344 decode_mips_operand
, &mips_operands
[i
]))
3346 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3348 create_insn (&nop_insn
, mips_opcodes
+ i
);
3349 if (mips_fix_loongson2f_nop
)
3350 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3351 nop_insn
.fixed_p
= 1;
3355 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3358 mips16_op_hash
= hash_new ();
3359 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3360 bfd_mips16_num_opcodes
);
3363 while (i
< bfd_mips16_num_opcodes
)
3365 const char *name
= mips16_opcodes
[i
].name
;
3367 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3369 as_fatal (_("internal: can't hash `%s': %s"),
3370 mips16_opcodes
[i
].name
, retval
);
3373 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3375 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3377 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3378 mips16_nop_insn
.fixed_p
= 1;
3382 while (i
< bfd_mips16_num_opcodes
3383 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3386 micromips_op_hash
= hash_new ();
3387 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3388 bfd_micromips_num_opcodes
);
3391 while (i
< bfd_micromips_num_opcodes
)
3393 const char *name
= micromips_opcodes
[i
].name
;
3395 retval
= hash_insert (micromips_op_hash
, name
,
3396 (void *) µmips_opcodes
[i
]);
3398 as_fatal (_("internal: can't hash `%s': %s"),
3399 micromips_opcodes
[i
].name
, retval
);
3402 struct mips_cl_insn
*micromips_nop_insn
;
3404 if (!validate_micromips_insn (µmips_opcodes
[i
],
3405 µmips_operands
[i
]))
3408 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3410 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3411 micromips_nop_insn
= µmips_nop16_insn
;
3412 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3413 micromips_nop_insn
= µmips_nop32_insn
;
3417 if (micromips_nop_insn
->insn_mo
== NULL
3418 && strcmp (name
, "nop") == 0)
3420 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3421 micromips_nop_insn
->fixed_p
= 1;
3425 while (++i
< bfd_micromips_num_opcodes
3426 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3430 as_fatal (_("Broken assembler. No assembly attempted."));
3432 /* We add all the general register names to the symbol table. This
3433 helps us detect invalid uses of them. */
3434 for (i
= 0; reg_names
[i
].name
; i
++)
3435 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3436 reg_names
[i
].num
, /* & RNUM_MASK, */
3437 &zero_address_frag
));
3439 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3440 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3441 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3442 &zero_address_frag
));
3444 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3445 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3446 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3447 &zero_address_frag
));
3449 for (i
= 0; i
< 32; i
++)
3453 /* R5900 VU0 floating-point register. */
3454 regname
[sizeof (rename
) - 1] = 0;
3455 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3456 symbol_table_insert (symbol_new (regname
, reg_section
,
3457 RTYPE_VF
| i
, &zero_address_frag
));
3459 /* R5900 VU0 integer register. */
3460 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3461 symbol_table_insert (symbol_new (regname
, reg_section
,
3462 RTYPE_VI
| i
, &zero_address_frag
));
3466 obstack_init (&mips_operand_tokens
);
3468 mips_no_prev_insn ();
3471 mips_cprmask
[0] = 0;
3472 mips_cprmask
[1] = 0;
3473 mips_cprmask
[2] = 0;
3474 mips_cprmask
[3] = 0;
3476 /* set the default alignment for the text section (2**2) */
3477 record_alignment (text_section
, 2);
3479 bfd_set_gp_size (stdoutput
, g_switch_value
);
3481 /* On a native system other than VxWorks, sections must be aligned
3482 to 16 byte boundaries. When configured for an embedded ELF
3483 target, we don't bother. */
3484 if (strncmp (TARGET_OS
, "elf", 3) != 0
3485 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3487 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3488 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3489 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3492 /* Create a .reginfo section for register masks and a .mdebug
3493 section for debugging information. */
3501 subseg
= now_subseg
;
3503 /* The ABI says this section should be loaded so that the
3504 running program can access it. However, we don't load it
3505 if we are configured for an embedded target */
3506 flags
= SEC_READONLY
| SEC_DATA
;
3507 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3508 flags
|= SEC_ALLOC
| SEC_LOAD
;
3510 if (mips_abi
!= N64_ABI
)
3512 sec
= subseg_new (".reginfo", (subsegT
) 0);
3514 bfd_set_section_flags (stdoutput
, sec
, flags
);
3515 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3517 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3521 /* The 64-bit ABI uses a .MIPS.options section rather than
3522 .reginfo section. */
3523 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3524 bfd_set_section_flags (stdoutput
, sec
, flags
);
3525 bfd_set_section_alignment (stdoutput
, sec
, 3);
3527 /* Set up the option header. */
3529 Elf_Internal_Options opthdr
;
3532 opthdr
.kind
= ODK_REGINFO
;
3533 opthdr
.size
= (sizeof (Elf_External_Options
)
3534 + sizeof (Elf64_External_RegInfo
));
3537 f
= frag_more (sizeof (Elf_External_Options
));
3538 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3539 (Elf_External_Options
*) f
);
3541 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3545 if (ECOFF_DEBUGGING
)
3547 sec
= subseg_new (".mdebug", (subsegT
) 0);
3548 (void) bfd_set_section_flags (stdoutput
, sec
,
3549 SEC_HAS_CONTENTS
| SEC_READONLY
);
3550 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3552 else if (mips_flag_pdr
)
3554 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3555 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3556 SEC_READONLY
| SEC_RELOC
3558 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3561 subseg_set (seg
, subseg
);
3564 if (! ECOFF_DEBUGGING
)
3567 if (mips_fix_vr4120
)
3568 init_vr4120_conflicts ();
3574 mips_emit_delays ();
3575 if (! ECOFF_DEBUGGING
)
3580 md_assemble (char *str
)
3582 struct mips_cl_insn insn
;
3583 bfd_reloc_code_real_type unused_reloc
[3]
3584 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3586 imm_expr
.X_op
= O_absent
;
3587 imm2_expr
.X_op
= O_absent
;
3588 offset_expr
.X_op
= O_absent
;
3589 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3590 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3591 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3593 mips_mark_labels ();
3594 mips_assembling_insn
= TRUE
;
3595 clear_insn_error ();
3597 if (mips_opts
.mips16
)
3598 mips16_ip (str
, &insn
);
3601 mips_ip (str
, &insn
);
3602 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3603 str
, insn
.insn_opcode
));
3607 report_insn_error (str
);
3608 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3611 if (mips_opts
.mips16
)
3612 mips16_macro (&insn
);
3619 if (offset_expr
.X_op
!= O_absent
)
3620 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3622 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3625 mips_assembling_insn
= FALSE
;
3628 /* Convenience functions for abstracting away the differences between
3629 MIPS16 and non-MIPS16 relocations. */
3631 static inline bfd_boolean
3632 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3636 case BFD_RELOC_MIPS16_JMP
:
3637 case BFD_RELOC_MIPS16_GPREL
:
3638 case BFD_RELOC_MIPS16_GOT16
:
3639 case BFD_RELOC_MIPS16_CALL16
:
3640 case BFD_RELOC_MIPS16_HI16_S
:
3641 case BFD_RELOC_MIPS16_HI16
:
3642 case BFD_RELOC_MIPS16_LO16
:
3650 static inline bfd_boolean
3651 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3655 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3656 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3657 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3658 case BFD_RELOC_MICROMIPS_GPREL16
:
3659 case BFD_RELOC_MICROMIPS_JMP
:
3660 case BFD_RELOC_MICROMIPS_HI16
:
3661 case BFD_RELOC_MICROMIPS_HI16_S
:
3662 case BFD_RELOC_MICROMIPS_LO16
:
3663 case BFD_RELOC_MICROMIPS_LITERAL
:
3664 case BFD_RELOC_MICROMIPS_GOT16
:
3665 case BFD_RELOC_MICROMIPS_CALL16
:
3666 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3667 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3668 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3669 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3670 case BFD_RELOC_MICROMIPS_SUB
:
3671 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3672 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3673 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3674 case BFD_RELOC_MICROMIPS_HIGHEST
:
3675 case BFD_RELOC_MICROMIPS_HIGHER
:
3676 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3677 case BFD_RELOC_MICROMIPS_JALR
:
3685 static inline bfd_boolean
3686 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3688 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3691 static inline bfd_boolean
3692 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3694 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3695 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3698 static inline bfd_boolean
3699 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3701 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3702 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3705 static inline bfd_boolean
3706 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3708 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3709 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3712 static inline bfd_boolean
3713 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3715 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3718 static inline bfd_boolean
3719 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3721 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3722 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3725 /* Return true if RELOC is a PC-relative relocation that does not have
3726 full address range. */
3728 static inline bfd_boolean
3729 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3733 case BFD_RELOC_16_PCREL_S2
:
3734 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3735 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3736 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3739 case BFD_RELOC_32_PCREL
:
3740 return HAVE_64BIT_ADDRESSES
;
3747 /* Return true if the given relocation might need a matching %lo().
3748 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3749 need a matching %lo() when applied to local symbols. */
3751 static inline bfd_boolean
3752 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3754 return (HAVE_IN_PLACE_ADDENDS
3755 && (hi16_reloc_p (reloc
)
3756 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3757 all GOT16 relocations evaluate to "G". */
3758 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3761 /* Return the type of %lo() reloc needed by RELOC, given that
3762 reloc_needs_lo_p. */
3764 static inline bfd_reloc_code_real_type
3765 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3767 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3768 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3772 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3775 static inline bfd_boolean
3776 fixup_has_matching_lo_p (fixS
*fixp
)
3778 return (fixp
->fx_next
!= NULL
3779 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3780 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3781 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3784 /* Move all labels in LABELS to the current insertion point. TEXT_P
3785 says whether the labels refer to text or data. */
3788 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3790 struct insn_label_list
*l
;
3793 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3795 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3796 symbol_set_frag (l
->label
, frag_now
);
3797 val
= (valueT
) frag_now_fix ();
3798 /* MIPS16/microMIPS text labels are stored as odd. */
3799 if (text_p
&& HAVE_CODE_COMPRESSION
)
3801 S_SET_VALUE (l
->label
, val
);
3805 /* Move all labels in insn_labels to the current insertion point
3806 and treat them as text labels. */
3809 mips_move_text_labels (void)
3811 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3815 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3817 bfd_boolean linkonce
= FALSE
;
3818 segT symseg
= S_GET_SEGMENT (sym
);
3820 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3822 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3824 /* The GNU toolchain uses an extension for ELF: a section
3825 beginning with the magic string .gnu.linkonce is a
3826 linkonce section. */
3827 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3828 sizeof ".gnu.linkonce" - 1) == 0)
3834 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3835 linker to handle them specially, such as generating jalx instructions
3836 when needed. We also make them odd for the duration of the assembly,
3837 in order to generate the right sort of code. We will make them even
3838 in the adjust_symtab routine, while leaving them marked. This is
3839 convenient for the debugger and the disassembler. The linker knows
3840 to make them odd again. */
3843 mips_compressed_mark_label (symbolS
*label
)
3845 gas_assert (HAVE_CODE_COMPRESSION
);
3847 if (mips_opts
.mips16
)
3848 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3850 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3851 if ((S_GET_VALUE (label
) & 1) == 0
3852 /* Don't adjust the address if the label is global or weak, or
3853 in a link-once section, since we'll be emitting symbol reloc
3854 references to it which will be patched up by the linker, and
3855 the final value of the symbol may or may not be MIPS16/microMIPS. */
3856 && !S_IS_WEAK (label
)
3857 && !S_IS_EXTERNAL (label
)
3858 && !s_is_linkonce (label
, now_seg
))
3859 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3862 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3865 mips_compressed_mark_labels (void)
3867 struct insn_label_list
*l
;
3869 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3870 mips_compressed_mark_label (l
->label
);
3873 /* End the current frag. Make it a variant frag and record the
3877 relax_close_frag (void)
3879 mips_macro_warning
.first_frag
= frag_now
;
3880 frag_var (rs_machine_dependent
, 0, 0,
3881 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3882 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3884 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3885 mips_relax
.first_fixup
= 0;
3888 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3889 See the comment above RELAX_ENCODE for more details. */
3892 relax_start (symbolS
*symbol
)
3894 gas_assert (mips_relax
.sequence
== 0);
3895 mips_relax
.sequence
= 1;
3896 mips_relax
.symbol
= symbol
;
3899 /* Start generating the second version of a relaxable sequence.
3900 See the comment above RELAX_ENCODE for more details. */
3905 gas_assert (mips_relax
.sequence
== 1);
3906 mips_relax
.sequence
= 2;
3909 /* End the current relaxable sequence. */
3914 gas_assert (mips_relax
.sequence
== 2);
3915 relax_close_frag ();
3916 mips_relax
.sequence
= 0;
3919 /* Return true if IP is a delayed branch or jump. */
3921 static inline bfd_boolean
3922 delayed_branch_p (const struct mips_cl_insn
*ip
)
3924 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3925 | INSN_COND_BRANCH_DELAY
3926 | INSN_COND_BRANCH_LIKELY
)) != 0;
3929 /* Return true if IP is a compact branch or jump. */
3931 static inline bfd_boolean
3932 compact_branch_p (const struct mips_cl_insn
*ip
)
3934 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3935 | INSN2_COND_BRANCH
)) != 0;
3938 /* Return true if IP is an unconditional branch or jump. */
3940 static inline bfd_boolean
3941 uncond_branch_p (const struct mips_cl_insn
*ip
)
3943 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3944 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3947 /* Return true if IP is a branch-likely instruction. */
3949 static inline bfd_boolean
3950 branch_likely_p (const struct mips_cl_insn
*ip
)
3952 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3955 /* Return the type of nop that should be used to fill the delay slot
3956 of delayed branch IP. */
3958 static struct mips_cl_insn
*
3959 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3961 if (mips_opts
.micromips
3962 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3963 return µmips_nop32_insn
;
3967 /* Return a mask that has bit N set if OPCODE reads the register(s)
3971 insn_read_mask (const struct mips_opcode
*opcode
)
3973 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3976 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3980 insn_write_mask (const struct mips_opcode
*opcode
)
3982 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3985 /* Return a mask of the registers specified by operand OPERAND of INSN.
3986 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3990 operand_reg_mask (const struct mips_cl_insn
*insn
,
3991 const struct mips_operand
*operand
,
3992 unsigned int type_mask
)
3994 unsigned int uval
, vsel
;
3996 switch (operand
->type
)
4003 case OP_ADDIUSP_INT
:
4004 case OP_ENTRY_EXIT_LIST
:
4005 case OP_REPEAT_DEST_REG
:
4006 case OP_REPEAT_PREV_REG
:
4009 case OP_VU0_MATCH_SUFFIX
:
4013 case OP_OPTIONAL_REG
:
4015 const struct mips_reg_operand
*reg_op
;
4017 reg_op
= (const struct mips_reg_operand
*) operand
;
4018 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4020 uval
= insn_extract_operand (insn
, operand
);
4021 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4026 const struct mips_reg_pair_operand
*pair_op
;
4028 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4029 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4031 uval
= insn_extract_operand (insn
, operand
);
4032 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4035 case OP_CLO_CLZ_DEST
:
4036 if (!(type_mask
& (1 << OP_REG_GP
)))
4038 uval
= insn_extract_operand (insn
, operand
);
4039 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4041 case OP_LWM_SWM_LIST
:
4044 case OP_SAVE_RESTORE_LIST
:
4047 case OP_MDMX_IMM_REG
:
4048 if (!(type_mask
& (1 << OP_REG_VEC
)))
4050 uval
= insn_extract_operand (insn
, operand
);
4052 if ((vsel
& 0x18) == 0x18)
4054 return 1 << (uval
& 31);
4059 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4060 where bit N of OPNO_MASK is set if operand N should be included.
4061 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4065 insn_reg_mask (const struct mips_cl_insn
*insn
,
4066 unsigned int type_mask
, unsigned int opno_mask
)
4068 unsigned int opno
, reg_mask
;
4072 while (opno_mask
!= 0)
4075 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4082 /* Return the mask of core registers that IP reads. */
4085 gpr_read_mask (const struct mips_cl_insn
*ip
)
4087 unsigned long pinfo
, pinfo2
;
4090 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4091 pinfo
= ip
->insn_mo
->pinfo
;
4092 pinfo2
= ip
->insn_mo
->pinfo2
;
4093 if (pinfo
& INSN_UDI
)
4095 /* UDI instructions have traditionally been assumed to read RS
4097 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4098 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4100 if (pinfo
& INSN_READ_GPR_24
)
4102 if (pinfo2
& INSN2_READ_GPR_16
)
4104 if (pinfo2
& INSN2_READ_SP
)
4106 if (pinfo2
& INSN2_READ_GPR_31
)
4108 /* Don't include register 0. */
4112 /* Return the mask of core registers that IP writes. */
4115 gpr_write_mask (const struct mips_cl_insn
*ip
)
4117 unsigned long pinfo
, pinfo2
;
4120 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4121 pinfo
= ip
->insn_mo
->pinfo
;
4122 pinfo2
= ip
->insn_mo
->pinfo2
;
4123 if (pinfo
& INSN_WRITE_GPR_24
)
4125 if (pinfo
& INSN_WRITE_GPR_31
)
4127 if (pinfo
& INSN_UDI
)
4128 /* UDI instructions have traditionally been assumed to write to RD. */
4129 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4130 if (pinfo2
& INSN2_WRITE_SP
)
4132 /* Don't include register 0. */
4136 /* Return the mask of floating-point registers that IP reads. */
4139 fpr_read_mask (const struct mips_cl_insn
*ip
)
4141 unsigned long pinfo
;
4144 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4145 insn_read_mask (ip
->insn_mo
));
4146 pinfo
= ip
->insn_mo
->pinfo
;
4147 /* Conservatively treat all operands to an FP_D instruction are doubles.
4148 (This is overly pessimistic for things like cvt.d.s.) */
4149 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4154 /* Return the mask of floating-point registers that IP writes. */
4157 fpr_write_mask (const struct mips_cl_insn
*ip
)
4159 unsigned long pinfo
;
4162 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4163 insn_write_mask (ip
->insn_mo
));
4164 pinfo
= ip
->insn_mo
->pinfo
;
4165 /* Conservatively treat all operands to an FP_D instruction are doubles.
4166 (This is overly pessimistic for things like cvt.s.d.) */
4167 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4172 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4173 Check whether that is allowed. */
4176 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4178 const char *s
= insn
->name
;
4180 if (insn
->pinfo
== INSN_MACRO
)
4181 /* Let a macro pass, we'll catch it later when it is expanded. */
4184 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4186 /* Allow odd registers for single-precision ops. */
4187 switch (insn
->pinfo
& (FP_S
| FP_D
))
4198 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4199 s
= strchr (insn
->name
, '.');
4200 if (s
!= NULL
&& opnum
== 2)
4201 s
= strchr (s
+ 1, '.');
4202 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4205 /* Single-precision coprocessor loads and moves are OK too. */
4206 if ((insn
->pinfo
& FP_S
)
4207 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4208 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4214 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4215 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4216 this operand is normally printed in hex or decimal. */
4219 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
4220 offsetT val
, int min_val
, int max_val
,
4221 bfd_boolean print_hex
)
4223 if (print_hex
&& val
>= 0)
4224 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4226 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4228 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4230 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4232 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4234 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4237 /* Report an invalid combination of position and size operands for a bitfield
4238 operation. POS and SIZE are the values that were given. */
4241 report_bad_field (offsetT pos
, offsetT size
)
4243 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4244 (unsigned long) pos
, (unsigned long) size
);
4247 /* Information about an instruction argument that we're trying to match. */
4248 struct mips_arg_info
4250 /* The instruction so far. */
4251 struct mips_cl_insn
*insn
;
4253 /* The first unconsumed operand token. */
4254 struct mips_operand_token
*token
;
4256 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4259 /* The 1-based argument number, for error reporting. This does not
4260 count elided optional registers, etc.. */
4263 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4264 unsigned int last_regno
;
4266 /* If the first operand was an OP_REG, this is the register that it
4267 specified, otherwise it is ILLEGAL_REG. */
4268 unsigned int dest_regno
;
4270 /* The value of the last OP_INT operand. Only used for OP_MSB,
4271 where it gives the lsb position. */
4272 unsigned int last_op_int
;
4274 /* If true, match routines should silently reject invalid arguments.
4275 If false, match routines can accept invalid arguments as long as
4276 they report an appropriate error. They still have the option of
4277 silently rejecting arguments, in which case a generic "Invalid operands"
4278 style of error will be used instead. */
4279 bfd_boolean soft_match
;
4281 /* If true, the OP_INT match routine should treat plain symbolic operands
4282 as if a relocation operator like %lo(...) had been used. This is only
4283 ever true if the operand can be relocated. */
4284 bfd_boolean allow_nonconst
;
4286 /* When true, the OP_INT match routine should allow unsigned N-bit
4287 arguments to be used where a signed N-bit operand is expected. */
4288 bfd_boolean lax_max
;
4290 /* True if a reference to the current AT register was seen. */
4291 bfd_boolean seen_at
;
4294 /* Try to match an OT_CHAR token for character CH. Consume the token
4295 and return true on success, otherwise return false. */
4298 match_char (struct mips_arg_info
*arg
, char ch
)
4300 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4310 /* Try to get an expression from the next tokens in ARG. Consume the
4311 tokens and return true on success, storing the expression value in
4312 VALUE and relocation types in R. */
4315 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4316 bfd_reloc_code_real_type
*r
)
4318 if (arg
->token
->type
== OT_INTEGER
)
4320 *value
= arg
->token
->u
.integer
.value
;
4321 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4326 /* Error-reporting is more consistent if we treat registers as O_register
4327 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4328 then handled in the same way. */
4329 if (arg
->token
->type
== OT_REG
)
4331 value
->X_add_number
= arg
->token
->u
.regno
;
4334 else if (arg
->token
[0].type
== OT_CHAR
4335 && arg
->token
[0].u
.ch
== '('
4336 && arg
->token
[1].type
== OT_REG
4337 && arg
->token
[2].type
== OT_CHAR
4338 && arg
->token
[2].u
.ch
== ')')
4340 value
->X_add_number
= arg
->token
[1].u
.regno
;
4346 value
->X_op
= O_register
;
4347 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4351 /* Try to get a constant expression from the next tokens in ARG. Consume
4352 the tokens and return return true on success, storing the constant value
4353 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4357 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
, offsetT fallback
)
4360 bfd_reloc_code_real_type r
[3];
4362 if (!match_expression (arg
, &ex
, r
))
4365 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4366 *value
= ex
.X_add_number
;
4369 if (arg
->soft_match
)
4371 as_bad (_("Operand %d of `%s' must be constant"),
4372 arg
->argnum
, arg
->insn
->insn_mo
->name
);
4378 /* Return the RTYPE_* flags for a register operand of type TYPE that
4379 appears in instruction OPCODE. */
4382 convert_reg_type (const struct mips_opcode
*opcode
,
4383 enum mips_reg_operand_type type
)
4388 return RTYPE_NUM
| RTYPE_GP
;
4391 /* Allow vector register names for MDMX if the instruction is a 64-bit
4392 FPR load, store or move (including moves to and from GPRs). */
4393 if ((mips_opts
.ase
& ASE_MDMX
)
4394 && (opcode
->pinfo
& FP_D
)
4395 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4396 | INSN_COPROC_MEMORY_DELAY
4397 | INSN_LOAD_COPROC_DELAY
4398 | INSN_LOAD_MEMORY_DELAY
4399 | INSN_STORE_MEMORY
)))
4400 return RTYPE_FPU
| RTYPE_VEC
;
4404 if (opcode
->pinfo
& (FP_D
| FP_S
))
4405 return RTYPE_CCC
| RTYPE_FCC
;
4409 if (opcode
->membership
& INSN_5400
)
4411 return RTYPE_FPU
| RTYPE_VEC
;
4417 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4418 return RTYPE_NUM
| RTYPE_CP0
;
4425 return RTYPE_NUM
| RTYPE_VI
;
4428 return RTYPE_NUM
| RTYPE_VF
;
4430 case OP_REG_R5900_I
:
4431 return RTYPE_R5900_I
;
4433 case OP_REG_R5900_Q
:
4434 return RTYPE_R5900_Q
;
4436 case OP_REG_R5900_R
:
4437 return RTYPE_R5900_R
;
4439 case OP_REG_R5900_ACC
:
4440 return RTYPE_R5900_ACC
;
4445 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4448 check_regno (struct mips_arg_info
*arg
,
4449 enum mips_reg_operand_type type
, unsigned int regno
)
4451 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4452 arg
->seen_at
= TRUE
;
4454 if (type
== OP_REG_FP
4457 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4458 as_warn (_("Float register should be even, was %d"), regno
);
4460 if (type
== OP_REG_CCC
)
4465 name
= arg
->insn
->insn_mo
->name
;
4466 length
= strlen (name
);
4467 if ((regno
& 1) != 0
4468 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4469 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4470 as_warn (_("Condition code register should be even for %s, was %d"),
4473 if ((regno
& 3) != 0
4474 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4475 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4480 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4481 a register of type TYPE. Return true on success, storing the register
4482 number in *REGNO and warning about any dubious uses. */
4485 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4486 unsigned int symval
, unsigned int *regno
)
4488 if (type
== OP_REG_VEC
)
4489 symval
= mips_prefer_vec_regno (symval
);
4490 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4493 *regno
= symval
& RNUM_MASK
;
4494 check_regno (arg
, type
, *regno
);
4498 /* Try to interpret the next token in ARG as a register of type TYPE.
4499 Consume the token and return true on success, storing the register
4500 number in *REGNO. Return false on failure. */
4503 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4504 unsigned int *regno
)
4506 if (arg
->token
->type
== OT_REG
4507 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4515 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4516 Consume the token and return true on success, storing the register numbers
4517 in *REGNO1 and *REGNO2. Return false on failure. */
4520 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4521 unsigned int *regno1
, unsigned int *regno2
)
4523 if (match_reg (arg
, type
, regno1
))
4528 if (arg
->token
->type
== OT_REG_RANGE
4529 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4530 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4531 && *regno1
<= *regno2
)
4539 /* OP_INT matcher. */
4542 match_int_operand (struct mips_arg_info
*arg
,
4543 const struct mips_operand
*operand_base
)
4545 const struct mips_int_operand
*operand
;
4547 int min_val
, max_val
, factor
;
4549 bfd_boolean print_hex
;
4551 operand
= (const struct mips_int_operand
*) operand_base
;
4552 factor
= 1 << operand
->shift
;
4553 min_val
= mips_int_operand_min (operand
);
4554 max_val
= mips_int_operand_max (operand
);
4556 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4558 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4559 /* Assume we have an elided offset. The later match will fail
4560 if this turns out to be wrong. */
4562 else if (operand_base
->lsb
== 0
4563 && operand_base
->size
== 16
4564 && operand
->shift
== 0
4565 && operand
->bias
== 0
4566 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4568 /* The operand can be relocated. */
4569 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4572 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4573 /* Relocation operators were used. Accept the arguent and
4574 leave the relocation value in offset_expr and offset_relocs
4575 for the caller to process. */
4578 if (offset_expr
.X_op
!= O_constant
)
4580 /* If non-constant operands are allowed then leave them for
4581 the caller to process, otherwise fail the match. */
4582 if (!arg
->allow_nonconst
)
4584 offset_reloc
[0] = BFD_RELOC_LO16
;
4588 /* Clear the global state; we're going to install the operand
4590 sval
= offset_expr
.X_add_number
;
4591 offset_expr
.X_op
= O_absent
;
4595 if (!match_const_int (arg
, &sval
, min_val
))
4599 arg
->last_op_int
= sval
;
4601 /* Check the range. If there's a problem, record the lowest acceptable
4602 value in arg->last_op_int in order to prevent an unhelpful error
4605 Bit counts have traditionally been printed in hex by the disassembler
4606 but printed as decimal in error messages. Only resort to hex if
4607 the operand is bigger than 6 bits. */
4608 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4609 if (sval
< min_val
|| sval
> max_val
)
4611 if (arg
->soft_match
)
4613 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4615 arg
->last_op_int
= min_val
;
4617 else if (sval
% factor
)
4619 if (arg
->soft_match
)
4621 as_bad (print_hex
&& sval
>= 0
4622 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4623 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4624 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4625 (unsigned long) sval
);
4626 arg
->last_op_int
= min_val
;
4629 uval
= (unsigned int) sval
>> operand
->shift
;
4630 uval
-= operand
->bias
;
4632 /* Handle -mfix-cn63xxp1. */
4634 && mips_fix_cn63xxp1
4635 && !mips_opts
.micromips
4636 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4651 /* The rest must be changed to 28. */
4656 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4660 /* OP_MAPPED_INT matcher. */
4663 match_mapped_int_operand (struct mips_arg_info
*arg
,
4664 const struct mips_operand
*operand_base
)
4666 const struct mips_mapped_int_operand
*operand
;
4667 unsigned int uval
, num_vals
;
4670 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4671 if (!match_const_int (arg
, &sval
, operand
->int_map
[0]))
4674 num_vals
= 1 << operand_base
->size
;
4675 for (uval
= 0; uval
< num_vals
; uval
++)
4676 if (operand
->int_map
[uval
] == sval
)
4678 if (uval
== num_vals
)
4681 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4685 /* OP_MSB matcher. */
4688 match_msb_operand (struct mips_arg_info
*arg
,
4689 const struct mips_operand
*operand_base
)
4691 const struct mips_msb_operand
*operand
;
4692 int min_val
, max_val
, max_high
;
4693 offsetT size
, sval
, high
;
4695 operand
= (const struct mips_msb_operand
*) operand_base
;
4696 min_val
= operand
->bias
;
4697 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4698 max_high
= operand
->opsize
;
4700 if (!match_const_int (arg
, &size
, 1))
4703 high
= size
+ arg
->last_op_int
;
4704 sval
= operand
->add_lsb
? high
: size
;
4706 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4708 if (arg
->soft_match
)
4710 report_bad_field (arg
->last_op_int
, size
);
4713 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4717 /* OP_REG matcher. */
4720 match_reg_operand (struct mips_arg_info
*arg
,
4721 const struct mips_operand
*operand_base
)
4723 const struct mips_reg_operand
*operand
;
4724 unsigned int regno
, uval
, num_vals
;
4726 operand
= (const struct mips_reg_operand
*) operand_base
;
4727 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4730 if (operand
->reg_map
)
4732 num_vals
= 1 << operand
->root
.size
;
4733 for (uval
= 0; uval
< num_vals
; uval
++)
4734 if (operand
->reg_map
[uval
] == regno
)
4736 if (num_vals
== uval
)
4742 arg
->last_regno
= regno
;
4743 if (arg
->opnum
== 1)
4744 arg
->dest_regno
= regno
;
4745 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4749 /* OP_REG_PAIR matcher. */
4752 match_reg_pair_operand (struct mips_arg_info
*arg
,
4753 const struct mips_operand
*operand_base
)
4755 const struct mips_reg_pair_operand
*operand
;
4756 unsigned int regno1
, regno2
, uval
, num_vals
;
4758 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4759 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4760 || !match_char (arg
, ',')
4761 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4764 num_vals
= 1 << operand_base
->size
;
4765 for (uval
= 0; uval
< num_vals
; uval
++)
4766 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4768 if (uval
== num_vals
)
4771 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4775 /* OP_PCREL matcher. The caller chooses the relocation type. */
4778 match_pcrel_operand (struct mips_arg_info
*arg
)
4780 bfd_reloc_code_real_type r
[3];
4782 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4785 /* OP_PERF_REG matcher. */
4788 match_perf_reg_operand (struct mips_arg_info
*arg
,
4789 const struct mips_operand
*operand
)
4793 if (!match_const_int (arg
, &sval
, 0))
4798 || (mips_opts
.arch
== CPU_R5900
4799 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4800 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4802 if (arg
->soft_match
)
4804 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4807 insn_insert_operand (arg
->insn
, operand
, sval
);
4811 /* OP_ADDIUSP matcher. */
4814 match_addiusp_operand (struct mips_arg_info
*arg
,
4815 const struct mips_operand
*operand
)
4820 if (!match_const_int (arg
, &sval
, -256))
4827 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4830 uval
= (unsigned int) sval
;
4831 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4832 insn_insert_operand (arg
->insn
, operand
, uval
);
4836 /* OP_CLO_CLZ_DEST matcher. */
4839 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4840 const struct mips_operand
*operand
)
4844 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4847 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4851 /* OP_LWM_SWM_LIST matcher. */
4854 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4855 const struct mips_operand
*operand
)
4857 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4858 struct mips_arg_info reset
;
4861 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4865 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4870 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4873 while (match_char (arg
, ',')
4874 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4877 if (operand
->size
== 2)
4879 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4885 and any permutations of these. */
4886 if ((reglist
& 0xfff1ffff) != 0x80010000)
4889 sregs
= (reglist
>> 17) & 7;
4894 /* The list must include at least one of ra and s0-sN,
4895 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4896 which are $23 and $30 respectively.) E.g.:
4904 and any permutations of these. */
4905 if ((reglist
& 0x3f00ffff) != 0)
4908 ra
= (reglist
>> 27) & 0x10;
4909 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4912 if ((sregs
& -sregs
) != sregs
)
4915 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4919 /* OP_ENTRY_EXIT_LIST matcher. */
4922 match_entry_exit_operand (struct mips_arg_info
*arg
,
4923 const struct mips_operand
*operand
)
4926 bfd_boolean is_exit
;
4928 /* The format is the same for both ENTRY and EXIT, but the constraints
4930 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4931 mask
= (is_exit
? 7 << 3 : 0);
4934 unsigned int regno1
, regno2
;
4935 bfd_boolean is_freg
;
4937 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4939 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4944 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4947 mask
|= (5 + regno2
) << 3;
4949 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4950 mask
|= (regno2
- 3) << 3;
4951 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4952 mask
|= (regno2
- 15) << 1;
4953 else if (regno1
== RA
&& regno2
== RA
)
4958 while (match_char (arg
, ','));
4960 insn_insert_operand (arg
->insn
, operand
, mask
);
4964 /* OP_SAVE_RESTORE_LIST matcher. */
4967 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4969 unsigned int opcode
, args
, statics
, sregs
;
4970 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4975 opcode
= arg
->insn
->insn_opcode
;
4977 num_frame_sizes
= 0;
4983 unsigned int regno1
, regno2
;
4985 if (arg
->token
->type
== OT_INTEGER
)
4987 /* Handle the frame size. */
4988 if (!match_const_int (arg
, &frame_size
, 0))
4990 num_frame_sizes
+= 1;
4994 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4997 while (regno1
<= regno2
)
4999 if (regno1
>= 4 && regno1
<= 7)
5001 if (num_frame_sizes
== 0)
5003 args
|= 1 << (regno1
- 4);
5005 /* statics $a0-$a3 */
5006 statics
|= 1 << (regno1
- 4);
5008 else if (regno1
>= 16 && regno1
<= 23)
5010 sregs
|= 1 << (regno1
- 16);
5011 else if (regno1
== 30)
5014 else if (regno1
== 31)
5015 /* Add $ra to insn. */
5025 while (match_char (arg
, ','));
5027 /* Encode args/statics combination. */
5030 else if (args
== 0xf)
5031 /* All $a0-$a3 are args. */
5032 opcode
|= MIPS16_ALL_ARGS
<< 16;
5033 else if (statics
== 0xf)
5034 /* All $a0-$a3 are statics. */
5035 opcode
|= MIPS16_ALL_STATICS
<< 16;
5038 /* Count arg registers. */
5048 /* Count static registers. */
5050 while (statics
& 0x8)
5052 statics
= (statics
<< 1) & 0xf;
5058 /* Encode args/statics. */
5059 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5062 /* Encode $s0/$s1. */
5063 if (sregs
& (1 << 0)) /* $s0 */
5065 if (sregs
& (1 << 1)) /* $s1 */
5069 /* Encode $s2-$s8. */
5078 opcode
|= num_sregs
<< 24;
5080 /* Encode frame size. */
5081 if (num_frame_sizes
== 0)
5082 error
= _("Missing frame size");
5083 else if (num_frame_sizes
> 1)
5084 error
= _("Frame size specified twice");
5085 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5086 error
= _("Invalid frame size");
5087 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
5090 opcode
|= (((frame_size
& 0xf0) << 16)
5091 | (frame_size
& 0x0f));
5096 if (arg
->soft_match
)
5098 as_bad ("%s", error
);
5101 /* Finally build the instruction. */
5102 if ((opcode
>> 16) != 0 || frame_size
== 0)
5103 opcode
|= MIPS16_EXTEND
;
5104 arg
->insn
->insn_opcode
= opcode
;
5108 /* OP_MDMX_IMM_REG matcher. */
5111 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5112 const struct mips_operand
*operand
)
5114 unsigned int regno
, uval
;
5116 const struct mips_opcode
*opcode
;
5118 /* The mips_opcode records whether this is an octobyte or quadhalf
5119 instruction. Start out with that bit in place. */
5120 opcode
= arg
->insn
->insn_mo
;
5121 uval
= mips_extract_operand (operand
, opcode
->match
);
5122 is_qh
= (uval
!= 0);
5124 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
5126 if ((opcode
->membership
& INSN_5400
)
5127 && strcmp (opcode
->name
, "rzu.ob") == 0)
5129 if (arg
->soft_match
)
5131 as_bad (_("Operand %d of `%s' must be an immediate"),
5132 arg
->argnum
, opcode
->name
);
5135 /* Check whether this is a vector register or a broadcast of
5136 a single element. */
5137 if (arg
->token
->type
== OT_REG_ELEMENT
)
5139 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
5142 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
5144 if (arg
->soft_match
)
5146 as_bad (_("Invalid element selector"));
5149 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
5153 /* A full vector. */
5154 if ((opcode
->membership
& INSN_5400
)
5155 && (strcmp (opcode
->name
, "sll.ob") == 0
5156 || strcmp (opcode
->name
, "srl.ob") == 0))
5158 if (arg
->soft_match
)
5160 as_bad (_("Operand %d of `%s' must be scalar"),
5161 arg
->argnum
, opcode
->name
);
5164 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5167 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5169 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5178 if (!match_const_int (arg
, &sval
, 0))
5180 if (sval
< 0 || sval
> 31)
5182 if (arg
->soft_match
)
5184 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
5186 uval
|= (sval
& 31);
5188 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5190 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5192 insn_insert_operand (arg
->insn
, operand
, uval
);
5196 /* OP_PC matcher. */
5199 match_pc_operand (struct mips_arg_info
*arg
)
5201 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5209 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5210 register that we need to match. */
5213 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5217 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5220 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5221 the length of the value in bytes (4 for float, 8 for double) and
5222 USING_GPRS says whether the destination is a GPR rather than an FPR.
5224 Return the constant in IMM and OFFSET as follows:
5226 - If the constant should be loaded via memory, set IMM to O_absent and
5227 OFFSET to the memory address.
5229 - Otherwise, if the constant should be loaded into two 32-bit registers,
5230 set IMM to the O_constant to load into the high register and OFFSET
5231 to the corresponding value for the low register.
5233 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5235 These constants only appear as the last operand in an instruction,
5236 and every instruction that accepts them in any variant accepts them
5237 in all variants. This means we don't have to worry about backing out
5238 any changes if the instruction does not match. We just match
5239 unconditionally and report an error if the constant is invalid. */
5242 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5243 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5248 const char *newname
;
5249 unsigned char *data
;
5251 /* Where the constant is placed is based on how the MIPS assembler
5254 length == 4 && using_gprs -- immediate value only
5255 length == 8 && using_gprs -- .rdata or immediate value
5256 length == 4 && !using_gprs -- .lit4 or immediate value
5257 length == 8 && !using_gprs -- .lit8 or immediate value
5259 The .lit4 and .lit8 sections are only used if permitted by the
5261 if (arg
->token
->type
!= OT_FLOAT
)
5264 gas_assert (arg
->token
->u
.flt
.length
== length
);
5265 data
= arg
->token
->u
.flt
.data
;
5268 /* Handle 32-bit constants for which an immediate value is best. */
5271 || g_switch_value
< 4
5272 || (data
[0] == 0 && data
[1] == 0)
5273 || (data
[2] == 0 && data
[3] == 0)))
5275 imm
->X_op
= O_constant
;
5276 if (!target_big_endian
)
5277 imm
->X_add_number
= bfd_getl32 (data
);
5279 imm
->X_add_number
= bfd_getb32 (data
);
5280 offset
->X_op
= O_absent
;
5284 /* Handle 64-bit constants for which an immediate value is best. */
5286 && !mips_disable_float_construction
5287 /* Constants can only be constructed in GPRs and copied
5288 to FPRs if the GPRs are at least as wide as the FPRs.
5289 Force the constant into memory if we are using 64-bit FPRs
5290 but the GPRs are only 32 bits wide. */
5291 /* ??? No longer true with the addition of MTHC1, but this
5292 is legacy code... */
5293 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5294 && ((data
[0] == 0 && data
[1] == 0)
5295 || (data
[2] == 0 && data
[3] == 0))
5296 && ((data
[4] == 0 && data
[5] == 0)
5297 || (data
[6] == 0 && data
[7] == 0)))
5299 /* The value is simple enough to load with a couple of instructions.
5300 If using 32-bit registers, set IMM to the high order 32 bits and
5301 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5303 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5305 imm
->X_op
= O_constant
;
5306 offset
->X_op
= O_constant
;
5307 if (!target_big_endian
)
5309 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5310 offset
->X_add_number
= bfd_getl32 (data
);
5314 imm
->X_add_number
= bfd_getb32 (data
);
5315 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5317 if (offset
->X_add_number
== 0)
5318 offset
->X_op
= O_absent
;
5322 imm
->X_op
= O_constant
;
5323 if (!target_big_endian
)
5324 imm
->X_add_number
= bfd_getl64 (data
);
5326 imm
->X_add_number
= bfd_getb64 (data
);
5327 offset
->X_op
= O_absent
;
5332 /* Switch to the right section. */
5334 subseg
= now_subseg
;
5337 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5342 if (using_gprs
|| g_switch_value
< 8)
5343 newname
= RDATA_SECTION_NAME
;
5348 new_seg
= subseg_new (newname
, (subsegT
) 0);
5349 bfd_set_section_flags (stdoutput
, new_seg
,
5350 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5351 frag_align (length
== 4 ? 2 : 3, 0, 0);
5352 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5353 record_alignment (new_seg
, 4);
5355 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5357 as_bad (_("Can't use floating point insn in this section"));
5359 /* Set the argument to the current address in the section. */
5360 imm
->X_op
= O_absent
;
5361 offset
->X_op
= O_symbol
;
5362 offset
->X_add_symbol
= symbol_temp_new_now ();
5363 offset
->X_add_number
= 0;
5365 /* Put the floating point number into the section. */
5366 p
= frag_more (length
);
5367 memcpy (p
, data
, length
);
5369 /* Switch back to the original section. */
5370 subseg_set (seg
, subseg
);
5374 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5378 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5379 const struct mips_operand
*operand
,
5380 bfd_boolean match_p
)
5384 /* The operand can be an XYZW mask or a single 2-bit channel index
5385 (with X being 0). */
5386 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5388 /* The suffix can be omitted when it is already part of the opcode. */
5389 if (arg
->token
->type
!= OT_CHANNELS
)
5392 uval
= arg
->token
->u
.channels
;
5393 if (operand
->size
== 2)
5395 /* Check that a single bit is set and convert it into a 2-bit index. */
5396 if ((uval
& -uval
) != uval
)
5398 uval
= 4 - ffs (uval
);
5401 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5406 insn_insert_operand (arg
->insn
, operand
, uval
);
5410 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5411 of the argument text if the match is successful, otherwise return null. */
5414 match_operand (struct mips_arg_info
*arg
,
5415 const struct mips_operand
*operand
)
5417 switch (operand
->type
)
5420 return match_int_operand (arg
, operand
);
5423 return match_mapped_int_operand (arg
, operand
);
5426 return match_msb_operand (arg
, operand
);
5429 case OP_OPTIONAL_REG
:
5430 return match_reg_operand (arg
, operand
);
5433 return match_reg_pair_operand (arg
, operand
);
5436 return match_pcrel_operand (arg
);
5439 return match_perf_reg_operand (arg
, operand
);
5441 case OP_ADDIUSP_INT
:
5442 return match_addiusp_operand (arg
, operand
);
5444 case OP_CLO_CLZ_DEST
:
5445 return match_clo_clz_dest_operand (arg
, operand
);
5447 case OP_LWM_SWM_LIST
:
5448 return match_lwm_swm_list_operand (arg
, operand
);
5450 case OP_ENTRY_EXIT_LIST
:
5451 return match_entry_exit_operand (arg
, operand
);
5453 case OP_SAVE_RESTORE_LIST
:
5454 return match_save_restore_list_operand (arg
);
5456 case OP_MDMX_IMM_REG
:
5457 return match_mdmx_imm_reg_operand (arg
, operand
);
5459 case OP_REPEAT_DEST_REG
:
5460 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5462 case OP_REPEAT_PREV_REG
:
5463 return match_tied_reg_operand (arg
, arg
->last_regno
);
5466 return match_pc_operand (arg
);
5469 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5471 case OP_VU0_MATCH_SUFFIX
:
5472 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5477 /* ARG is the state after successfully matching an instruction.
5478 Issue any queued-up warnings. */
5481 check_completed_insn (struct mips_arg_info
*arg
)
5486 as_warn (_("Used $at without \".set noat\""));
5488 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5492 /* Return true if modifying general-purpose register REG needs a delay. */
5495 reg_needs_delay (unsigned int reg
)
5497 unsigned long prev_pinfo
;
5499 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5500 if (!mips_opts
.noreorder
5501 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5502 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5503 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5509 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5510 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5511 by VR4120 errata. */
5514 classify_vr4120_insn (const char *name
)
5516 if (strncmp (name
, "macc", 4) == 0)
5517 return FIX_VR4120_MACC
;
5518 if (strncmp (name
, "dmacc", 5) == 0)
5519 return FIX_VR4120_DMACC
;
5520 if (strncmp (name
, "mult", 4) == 0)
5521 return FIX_VR4120_MULT
;
5522 if (strncmp (name
, "dmult", 5) == 0)
5523 return FIX_VR4120_DMULT
;
5524 if (strstr (name
, "div"))
5525 return FIX_VR4120_DIV
;
5526 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5527 return FIX_VR4120_MTHILO
;
5528 return NUM_FIX_VR4120_CLASSES
;
5531 #define INSN_ERET 0x42000018
5532 #define INSN_DERET 0x4200001f
5534 /* Return the number of instructions that must separate INSN1 and INSN2,
5535 where INSN1 is the earlier instruction. Return the worst-case value
5536 for any INSN2 if INSN2 is null. */
5539 insns_between (const struct mips_cl_insn
*insn1
,
5540 const struct mips_cl_insn
*insn2
)
5542 unsigned long pinfo1
, pinfo2
;
5545 /* If INFO2 is null, pessimistically assume that all flags are set for
5546 the second instruction. */
5547 pinfo1
= insn1
->insn_mo
->pinfo
;
5548 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5550 /* For most targets, write-after-read dependencies on the HI and LO
5551 registers must be separated by at least two instructions. */
5552 if (!hilo_interlocks
)
5554 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5556 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5560 /* If we're working around r7000 errata, there must be two instructions
5561 between an mfhi or mflo and any instruction that uses the result. */
5562 if (mips_7000_hilo_fix
5563 && !mips_opts
.micromips
5564 && MF_HILO_INSN (pinfo1
)
5565 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5568 /* If we're working around 24K errata, one instruction is required
5569 if an ERET or DERET is followed by a branch instruction. */
5570 if (mips_fix_24k
&& !mips_opts
.micromips
)
5572 if (insn1
->insn_opcode
== INSN_ERET
5573 || insn1
->insn_opcode
== INSN_DERET
)
5576 || insn2
->insn_opcode
== INSN_ERET
5577 || insn2
->insn_opcode
== INSN_DERET
5578 || delayed_branch_p (insn2
))
5583 /* If working around VR4120 errata, check for combinations that need
5584 a single intervening instruction. */
5585 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5587 unsigned int class1
, class2
;
5589 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5590 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5594 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5595 if (vr4120_conflicts
[class1
] & (1 << class2
))
5600 if (!HAVE_CODE_COMPRESSION
)
5602 /* Check for GPR or coprocessor load delays. All such delays
5603 are on the RT register. */
5604 /* Itbl support may require additional care here. */
5605 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5606 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5608 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5612 /* Check for generic coprocessor hazards.
5614 This case is not handled very well. There is no special
5615 knowledge of CP0 handling, and the coprocessors other than
5616 the floating point unit are not distinguished at all. */
5617 /* Itbl support may require additional care here. FIXME!
5618 Need to modify this to include knowledge about
5619 user specified delays! */
5620 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5621 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5623 /* Handle cases where INSN1 writes to a known general coprocessor
5624 register. There must be a one instruction delay before INSN2
5625 if INSN2 reads that register, otherwise no delay is needed. */
5626 mask
= fpr_write_mask (insn1
);
5629 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5634 /* Read-after-write dependencies on the control registers
5635 require a two-instruction gap. */
5636 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5637 && (pinfo2
& INSN_READ_COND_CODE
))
5640 /* We don't know exactly what INSN1 does. If INSN2 is
5641 also a coprocessor instruction, assume there must be
5642 a one instruction gap. */
5643 if (pinfo2
& INSN_COP
)
5648 /* Check for read-after-write dependencies on the coprocessor
5649 control registers in cases where INSN1 does not need a general
5650 coprocessor delay. This means that INSN1 is a floating point
5651 comparison instruction. */
5652 /* Itbl support may require additional care here. */
5653 else if (!cop_interlocks
5654 && (pinfo1
& INSN_WRITE_COND_CODE
)
5655 && (pinfo2
& INSN_READ_COND_CODE
))
5662 /* Return the number of nops that would be needed to work around the
5663 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5664 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5665 that are contained within the first IGNORE instructions of HIST. */
5668 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5669 const struct mips_cl_insn
*insn
)
5674 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5675 are not affected by the errata. */
5677 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5678 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5679 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5682 /* Search for the first MFLO or MFHI. */
5683 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5684 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5686 /* Extract the destination register. */
5687 mask
= gpr_write_mask (&hist
[i
]);
5689 /* No nops are needed if INSN reads that register. */
5690 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5693 /* ...or if any of the intervening instructions do. */
5694 for (j
= 0; j
< i
; j
++)
5695 if (gpr_read_mask (&hist
[j
]) & mask
)
5699 return MAX_VR4130_NOPS
- i
;
5704 #define BASE_REG_EQ(INSN1, INSN2) \
5705 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5706 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5708 /* Return the minimum alignment for this store instruction. */
5711 fix_24k_align_to (const struct mips_opcode
*mo
)
5713 if (strcmp (mo
->name
, "sh") == 0)
5716 if (strcmp (mo
->name
, "swc1") == 0
5717 || strcmp (mo
->name
, "swc2") == 0
5718 || strcmp (mo
->name
, "sw") == 0
5719 || strcmp (mo
->name
, "sc") == 0
5720 || strcmp (mo
->name
, "s.s") == 0)
5723 if (strcmp (mo
->name
, "sdc1") == 0
5724 || strcmp (mo
->name
, "sdc2") == 0
5725 || strcmp (mo
->name
, "s.d") == 0)
5732 struct fix_24k_store_info
5734 /* Immediate offset, if any, for this store instruction. */
5736 /* Alignment required by this store instruction. */
5738 /* True for register offsets. */
5739 int register_offset
;
5742 /* Comparison function used by qsort. */
5745 fix_24k_sort (const void *a
, const void *b
)
5747 const struct fix_24k_store_info
*pos1
= a
;
5748 const struct fix_24k_store_info
*pos2
= b
;
5750 return (pos1
->off
- pos2
->off
);
5753 /* INSN is a store instruction. Try to record the store information
5754 in STINFO. Return false if the information isn't known. */
5757 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5758 const struct mips_cl_insn
*insn
)
5760 /* The instruction must have a known offset. */
5761 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5764 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5765 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5769 /* Return the number of nops that would be needed to work around the 24k
5770 "lost data on stores during refill" errata if instruction INSN
5771 immediately followed the 2 instructions described by HIST.
5772 Ignore hazards that are contained within the first IGNORE
5773 instructions of HIST.
5775 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5776 for the data cache refills and store data. The following describes
5777 the scenario where the store data could be lost.
5779 * A data cache miss, due to either a load or a store, causing fill
5780 data to be supplied by the memory subsystem
5781 * The first three doublewords of fill data are returned and written
5783 * A sequence of four stores occurs in consecutive cycles around the
5784 final doubleword of the fill:
5788 * Zero, One or more instructions
5791 The four stores A-D must be to different doublewords of the line that
5792 is being filled. The fourth instruction in the sequence above permits
5793 the fill of the final doubleword to be transferred from the FSB into
5794 the cache. In the sequence above, the stores may be either integer
5795 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5796 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5797 different doublewords on the line. If the floating point unit is
5798 running in 1:2 mode, it is not possible to create the sequence above
5799 using only floating point store instructions.
5801 In this case, the cache line being filled is incorrectly marked
5802 invalid, thereby losing the data from any store to the line that
5803 occurs between the original miss and the completion of the five
5804 cycle sequence shown above.
5806 The workarounds are:
5808 * Run the data cache in write-through mode.
5809 * Insert a non-store instruction between
5810 Store A and Store B or Store B and Store C. */
5813 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5814 const struct mips_cl_insn
*insn
)
5816 struct fix_24k_store_info pos
[3];
5817 int align
, i
, base_offset
;
5822 /* If the previous instruction wasn't a store, there's nothing to
5824 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5827 /* If the instructions after the previous one are unknown, we have
5828 to assume the worst. */
5832 /* Check whether we are dealing with three consecutive stores. */
5833 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5834 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5837 /* If we don't know the relationship between the store addresses,
5838 assume the worst. */
5839 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5840 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5843 if (!fix_24k_record_store_info (&pos
[0], insn
)
5844 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5845 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5848 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5850 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5851 X bytes and such that the base register + X is known to be aligned
5854 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5858 align
= pos
[0].align_to
;
5859 base_offset
= pos
[0].off
;
5860 for (i
= 1; i
< 3; i
++)
5861 if (align
< pos
[i
].align_to
)
5863 align
= pos
[i
].align_to
;
5864 base_offset
= pos
[i
].off
;
5866 for (i
= 0; i
< 3; i
++)
5867 pos
[i
].off
-= base_offset
;
5870 pos
[0].off
&= ~align
+ 1;
5871 pos
[1].off
&= ~align
+ 1;
5872 pos
[2].off
&= ~align
+ 1;
5874 /* If any two stores write to the same chunk, they also write to the
5875 same doubleword. The offsets are still sorted at this point. */
5876 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5879 /* A range of at least 9 bytes is needed for the stores to be in
5880 non-overlapping doublewords. */
5881 if (pos
[2].off
- pos
[0].off
<= 8)
5884 if (pos
[2].off
- pos
[1].off
>= 24
5885 || pos
[1].off
- pos
[0].off
>= 24
5886 || pos
[2].off
- pos
[0].off
>= 32)
5892 /* Return the number of nops that would be needed if instruction INSN
5893 immediately followed the MAX_NOPS instructions given by HIST,
5894 where HIST[0] is the most recent instruction. Ignore hazards
5895 between INSN and the first IGNORE instructions in HIST.
5897 If INSN is null, return the worse-case number of nops for any
5901 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5902 const struct mips_cl_insn
*insn
)
5904 int i
, nops
, tmp_nops
;
5907 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5909 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5910 if (tmp_nops
> nops
)
5914 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5916 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5917 if (tmp_nops
> nops
)
5921 if (mips_fix_24k
&& !mips_opts
.micromips
)
5923 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5924 if (tmp_nops
> nops
)
5931 /* The variable arguments provide NUM_INSNS extra instructions that
5932 might be added to HIST. Return the largest number of nops that
5933 would be needed after the extended sequence, ignoring hazards
5934 in the first IGNORE instructions. */
5937 nops_for_sequence (int num_insns
, int ignore
,
5938 const struct mips_cl_insn
*hist
, ...)
5941 struct mips_cl_insn buffer
[MAX_NOPS
];
5942 struct mips_cl_insn
*cursor
;
5945 va_start (args
, hist
);
5946 cursor
= buffer
+ num_insns
;
5947 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5948 while (cursor
> buffer
)
5949 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5951 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5956 /* Like nops_for_insn, but if INSN is a branch, take into account the
5957 worst-case delay for the branch target. */
5960 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5961 const struct mips_cl_insn
*insn
)
5965 nops
= nops_for_insn (ignore
, hist
, insn
);
5966 if (delayed_branch_p (insn
))
5968 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5969 hist
, insn
, get_delay_slot_nop (insn
));
5970 if (tmp_nops
> nops
)
5973 else if (compact_branch_p (insn
))
5975 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5976 if (tmp_nops
> nops
)
5982 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5985 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5987 gas_assert (!HAVE_CODE_COMPRESSION
);
5988 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5989 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5992 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5993 jr target pc &= 'hffff_ffff_cfff_ffff. */
5996 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5998 gas_assert (!HAVE_CODE_COMPRESSION
);
5999 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6000 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6001 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6009 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6010 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6013 ep
.X_op
= O_constant
;
6014 ep
.X_add_number
= 0xcfff0000;
6015 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6016 ep
.X_add_number
= 0xffff;
6017 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6018 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6023 fix_loongson2f (struct mips_cl_insn
* ip
)
6025 if (mips_fix_loongson2f_nop
)
6026 fix_loongson2f_nop (ip
);
6028 if (mips_fix_loongson2f_jump
)
6029 fix_loongson2f_jump (ip
);
6032 /* IP is a branch that has a delay slot, and we need to fill it
6033 automatically. Return true if we can do that by swapping IP
6034 with the previous instruction.
6035 ADDRESS_EXPR is an operand of the instruction to be used with
6039 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6040 bfd_reloc_code_real_type
*reloc_type
)
6042 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6043 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6045 /* -O2 and above is required for this optimization. */
6046 if (mips_optimize
< 2)
6049 /* If we have seen .set volatile or .set nomove, don't optimize. */
6050 if (mips_opts
.nomove
)
6053 /* We can't swap if the previous instruction's position is fixed. */
6054 if (history
[0].fixed_p
)
6057 /* If the previous previous insn was in a .set noreorder, we can't
6058 swap. Actually, the MIPS assembler will swap in this situation.
6059 However, gcc configured -with-gnu-as will generate code like
6067 in which we can not swap the bne and INSN. If gcc is not configured
6068 -with-gnu-as, it does not output the .set pseudo-ops. */
6069 if (history
[1].noreorder_p
)
6072 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6073 This means that the previous instruction was a 4-byte one anyhow. */
6074 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6077 /* If the branch is itself the target of a branch, we can not swap.
6078 We cheat on this; all we check for is whether there is a label on
6079 this instruction. If there are any branches to anything other than
6080 a label, users must use .set noreorder. */
6081 if (seg_info (now_seg
)->label_list
)
6084 /* If the previous instruction is in a variant frag other than this
6085 branch's one, we cannot do the swap. This does not apply to
6086 MIPS16 code, which uses variant frags for different purposes. */
6087 if (!mips_opts
.mips16
6089 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6092 /* We do not swap with instructions that cannot architecturally
6093 be placed in a branch delay slot, such as SYNC or ERET. We
6094 also refrain from swapping with a trap instruction, since it
6095 complicates trap handlers to have the trap instruction be in
6097 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6098 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6101 /* Check for conflicts between the branch and the instructions
6102 before the candidate delay slot. */
6103 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6106 /* Check for conflicts between the swapped sequence and the
6107 target of the branch. */
6108 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6111 /* If the branch reads a register that the previous
6112 instruction sets, we can not swap. */
6113 gpr_read
= gpr_read_mask (ip
);
6114 prev_gpr_write
= gpr_write_mask (&history
[0]);
6115 if (gpr_read
& prev_gpr_write
)
6118 /* If the branch writes a register that the previous
6119 instruction sets, we can not swap. */
6120 gpr_write
= gpr_write_mask (ip
);
6121 if (gpr_write
& prev_gpr_write
)
6124 /* If the branch writes a register that the previous
6125 instruction reads, we can not swap. */
6126 prev_gpr_read
= gpr_read_mask (&history
[0]);
6127 if (gpr_write
& prev_gpr_read
)
6130 /* If one instruction sets a condition code and the
6131 other one uses a condition code, we can not swap. */
6132 pinfo
= ip
->insn_mo
->pinfo
;
6133 if ((pinfo
& INSN_READ_COND_CODE
)
6134 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6136 if ((pinfo
& INSN_WRITE_COND_CODE
)
6137 && (prev_pinfo
& INSN_READ_COND_CODE
))
6140 /* If the previous instruction uses the PC, we can not swap. */
6141 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6142 if (prev_pinfo2
& INSN2_READ_PC
)
6145 /* If the previous instruction has an incorrect size for a fixed
6146 branch delay slot in microMIPS mode, we cannot swap. */
6147 pinfo2
= ip
->insn_mo
->pinfo2
;
6148 if (mips_opts
.micromips
6149 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6150 && insn_length (history
) != 2)
6152 if (mips_opts
.micromips
6153 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6154 && insn_length (history
) != 4)
6157 /* On R5900 short loops need to be fixed by inserting a nop in
6158 the branch delay slots.
6159 A short loop can be terminated too early. */
6160 if (mips_opts
.arch
== CPU_R5900
6161 /* Check if instruction has a parameter, ignore "j $31". */
6162 && (address_expr
!= NULL
)
6163 /* Parameter must be 16 bit. */
6164 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6165 /* Branch to same segment. */
6166 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6167 /* Branch to same code fragment. */
6168 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6169 /* Can only calculate branch offset if value is known. */
6170 && symbol_constant_p(address_expr
->X_add_symbol
)
6171 /* Check if branch is really conditional. */
6172 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6173 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6174 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6177 /* Check if loop is shorter than 6 instructions including
6178 branch and delay slot. */
6179 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6186 /* When the loop includes branches or jumps,
6187 it is not a short loop. */
6188 for (i
= 0; i
< (distance
/ 4); i
++)
6190 if ((history
[i
].cleared_p
)
6191 || delayed_branch_p(&history
[i
]))
6199 /* Insert nop after branch to fix short loop. */
6208 /* Decide how we should add IP to the instruction stream.
6209 ADDRESS_EXPR is an operand of the instruction to be used with
6212 static enum append_method
6213 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6214 bfd_reloc_code_real_type
*reloc_type
)
6216 /* The relaxed version of a macro sequence must be inherently
6218 if (mips_relax
.sequence
== 2)
6221 /* We must not dabble with instructions in a ".set norerorder" block. */
6222 if (mips_opts
.noreorder
)
6225 /* Otherwise, it's our responsibility to fill branch delay slots. */
6226 if (delayed_branch_p (ip
))
6228 if (!branch_likely_p (ip
)
6229 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6232 if (mips_opts
.mips16
6233 && ISA_SUPPORTS_MIPS16E
6234 && gpr_read_mask (ip
) != 0)
6235 return APPEND_ADD_COMPACT
;
6237 return APPEND_ADD_WITH_NOP
;
6243 /* IP is a MIPS16 instruction whose opcode we have just changed.
6244 Point IP->insn_mo to the new opcode's definition. */
6247 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6249 const struct mips_opcode
*mo
, *end
;
6251 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6252 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6253 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6261 /* For microMIPS macros, we need to generate a local number label
6262 as the target of branches. */
6263 #define MICROMIPS_LABEL_CHAR '\037'
6264 static unsigned long micromips_target_label
;
6265 static char micromips_target_name
[32];
6268 micromips_label_name (void)
6270 char *p
= micromips_target_name
;
6271 char symbol_name_temporary
[24];
6279 l
= micromips_target_label
;
6280 #ifdef LOCAL_LABEL_PREFIX
6281 *p
++ = LOCAL_LABEL_PREFIX
;
6284 *p
++ = MICROMIPS_LABEL_CHAR
;
6287 symbol_name_temporary
[i
++] = l
% 10 + '0';
6292 *p
++ = symbol_name_temporary
[--i
];
6295 return micromips_target_name
;
6299 micromips_label_expr (expressionS
*label_expr
)
6301 label_expr
->X_op
= O_symbol
;
6302 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6303 label_expr
->X_add_number
= 0;
6307 micromips_label_inc (void)
6309 micromips_target_label
++;
6310 *micromips_target_name
= '\0';
6314 micromips_add_label (void)
6318 s
= colon (micromips_label_name ());
6319 micromips_label_inc ();
6320 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6323 /* If assembling microMIPS code, then return the microMIPS reloc
6324 corresponding to the requested one if any. Otherwise return
6325 the reloc unchanged. */
6327 static bfd_reloc_code_real_type
6328 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6330 static const bfd_reloc_code_real_type relocs
[][2] =
6332 /* Keep sorted incrementally by the left-hand key. */
6333 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6334 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6335 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6336 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6337 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6338 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6339 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6340 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6341 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6342 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6343 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6344 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6345 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6346 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6347 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6348 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6349 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6350 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6351 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6352 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6353 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6354 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6355 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6356 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6357 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6358 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6359 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6361 bfd_reloc_code_real_type r
;
6364 if (!mips_opts
.micromips
)
6366 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6372 return relocs
[i
][1];
6377 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6378 Return true on success, storing the resolved value in RESULT. */
6381 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6386 case BFD_RELOC_MIPS_HIGHEST
:
6387 case BFD_RELOC_MICROMIPS_HIGHEST
:
6388 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6391 case BFD_RELOC_MIPS_HIGHER
:
6392 case BFD_RELOC_MICROMIPS_HIGHER
:
6393 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6396 case BFD_RELOC_HI16_S
:
6397 case BFD_RELOC_MICROMIPS_HI16_S
:
6398 case BFD_RELOC_MIPS16_HI16_S
:
6399 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6402 case BFD_RELOC_HI16
:
6403 case BFD_RELOC_MICROMIPS_HI16
:
6404 case BFD_RELOC_MIPS16_HI16
:
6405 *result
= (operand
>> 16) & 0xffff;
6408 case BFD_RELOC_LO16
:
6409 case BFD_RELOC_MICROMIPS_LO16
:
6410 case BFD_RELOC_MIPS16_LO16
:
6411 *result
= operand
& 0xffff;
6414 case BFD_RELOC_UNUSED
:
6423 /* Output an instruction. IP is the instruction information.
6424 ADDRESS_EXPR is an operand of the instruction to be used with
6425 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6426 a macro expansion. */
6429 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6430 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6432 unsigned long prev_pinfo2
, pinfo
;
6433 bfd_boolean relaxed_branch
= FALSE
;
6434 enum append_method method
;
6435 bfd_boolean relax32
;
6438 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6439 fix_loongson2f (ip
);
6441 file_ase_mips16
|= mips_opts
.mips16
;
6442 file_ase_micromips
|= mips_opts
.micromips
;
6444 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6445 pinfo
= ip
->insn_mo
->pinfo
;
6447 if (mips_opts
.micromips
6449 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6450 && micromips_insn_length (ip
->insn_mo
) != 2)
6451 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6452 && micromips_insn_length (ip
->insn_mo
) != 4)))
6453 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6454 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6456 if (address_expr
== NULL
)
6458 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6459 && reloc_type
[1] == BFD_RELOC_UNUSED
6460 && reloc_type
[2] == BFD_RELOC_UNUSED
6461 && address_expr
->X_op
== O_constant
)
6463 switch (*reloc_type
)
6465 case BFD_RELOC_MIPS_JMP
:
6469 shift
= mips_opts
.micromips
? 1 : 2;
6470 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6471 as_bad (_("jump to misaligned address (0x%lx)"),
6472 (unsigned long) address_expr
->X_add_number
);
6473 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6479 case BFD_RELOC_MIPS16_JMP
:
6480 if ((address_expr
->X_add_number
& 3) != 0)
6481 as_bad (_("jump to misaligned address (0x%lx)"),
6482 (unsigned long) address_expr
->X_add_number
);
6484 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6485 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6486 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6490 case BFD_RELOC_16_PCREL_S2
:
6494 shift
= mips_opts
.micromips
? 1 : 2;
6495 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6496 as_bad (_("branch to misaligned address (0x%lx)"),
6497 (unsigned long) address_expr
->X_add_number
);
6498 if (!mips_relax_branch
)
6500 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6501 & ~((1 << (shift
+ 16)) - 1))
6502 as_bad (_("branch address range overflow (0x%lx)"),
6503 (unsigned long) address_expr
->X_add_number
);
6504 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6514 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6517 ip
->insn_opcode
|= value
& 0xffff;
6525 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6527 /* There are a lot of optimizations we could do that we don't.
6528 In particular, we do not, in general, reorder instructions.
6529 If you use gcc with optimization, it will reorder
6530 instructions and generally do much more optimization then we
6531 do here; repeating all that work in the assembler would only
6532 benefit hand written assembly code, and does not seem worth
6534 int nops
= (mips_optimize
== 0
6535 ? nops_for_insn (0, history
, NULL
)
6536 : nops_for_insn_or_target (0, history
, ip
));
6540 unsigned long old_frag_offset
;
6543 old_frag
= frag_now
;
6544 old_frag_offset
= frag_now_fix ();
6546 for (i
= 0; i
< nops
; i
++)
6547 add_fixed_insn (NOP_INSN
);
6548 insert_into_history (0, nops
, NOP_INSN
);
6552 listing_prev_line ();
6553 /* We may be at the start of a variant frag. In case we
6554 are, make sure there is enough space for the frag
6555 after the frags created by listing_prev_line. The
6556 argument to frag_grow here must be at least as large
6557 as the argument to all other calls to frag_grow in
6558 this file. We don't have to worry about being in the
6559 middle of a variant frag, because the variants insert
6560 all needed nop instructions themselves. */
6564 mips_move_text_labels ();
6566 #ifndef NO_ECOFF_DEBUGGING
6567 if (ECOFF_DEBUGGING
)
6568 ecoff_fix_loc (old_frag
, old_frag_offset
);
6572 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6576 /* Work out how many nops in prev_nop_frag are needed by IP,
6577 ignoring hazards generated by the first prev_nop_frag_since
6579 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6580 gas_assert (nops
<= prev_nop_frag_holds
);
6582 /* Enforce NOPS as a minimum. */
6583 if (nops
> prev_nop_frag_required
)
6584 prev_nop_frag_required
= nops
;
6586 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6588 /* Settle for the current number of nops. Update the history
6589 accordingly (for the benefit of any future .set reorder code). */
6590 prev_nop_frag
= NULL
;
6591 insert_into_history (prev_nop_frag_since
,
6592 prev_nop_frag_holds
, NOP_INSN
);
6596 /* Allow this instruction to replace one of the nops that was
6597 tentatively added to prev_nop_frag. */
6598 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6599 prev_nop_frag_holds
--;
6600 prev_nop_frag_since
++;
6604 method
= get_append_method (ip
, address_expr
, reloc_type
);
6605 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6607 dwarf2_emit_insn (0);
6608 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6609 so "move" the instruction address accordingly.
6611 Also, it doesn't seem appropriate for the assembler to reorder .loc
6612 entries. If this instruction is a branch that we are going to swap
6613 with the previous instruction, the two instructions should be
6614 treated as a unit, and the debug information for both instructions
6615 should refer to the start of the branch sequence. Using the
6616 current position is certainly wrong when swapping a 32-bit branch
6617 and a 16-bit delay slot, since the current position would then be
6618 in the middle of a branch. */
6619 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6621 relax32
= (mips_relax_branch
6622 /* Don't try branch relaxation within .set nomacro, or within
6623 .set noat if we use $at for PIC computations. If it turns
6624 out that the branch was out-of-range, we'll get an error. */
6625 && !mips_opts
.warn_about_macros
6626 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6627 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6628 as they have no complementing branches. */
6629 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6631 if (!HAVE_CODE_COMPRESSION
6634 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6635 && delayed_branch_p (ip
))
6637 relaxed_branch
= TRUE
;
6638 add_relaxed_insn (ip
, (relaxed_branch_length
6640 uncond_branch_p (ip
) ? -1
6641 : branch_likely_p (ip
) ? 1
6645 uncond_branch_p (ip
),
6646 branch_likely_p (ip
),
6647 pinfo
& INSN_WRITE_GPR_31
,
6649 address_expr
->X_add_symbol
,
6650 address_expr
->X_add_number
);
6651 *reloc_type
= BFD_RELOC_UNUSED
;
6653 else if (mips_opts
.micromips
6655 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6656 || *reloc_type
> BFD_RELOC_UNUSED
)
6657 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6658 /* Don't try branch relaxation when users specify
6659 16-bit/32-bit instructions. */
6660 && !forced_insn_length
)
6662 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6663 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6664 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6665 int compact
= compact_branch_p (ip
);
6666 int al
= pinfo
& INSN_WRITE_GPR_31
;
6669 gas_assert (address_expr
!= NULL
);
6670 gas_assert (!mips_relax
.sequence
);
6672 relaxed_branch
= TRUE
;
6673 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6674 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6675 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6677 address_expr
->X_add_symbol
,
6678 address_expr
->X_add_number
);
6679 *reloc_type
= BFD_RELOC_UNUSED
;
6681 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6683 /* We need to set up a variant frag. */
6684 gas_assert (address_expr
!= NULL
);
6685 add_relaxed_insn (ip
, 4, 0,
6687 (*reloc_type
- BFD_RELOC_UNUSED
,
6688 forced_insn_length
== 2, forced_insn_length
== 4,
6689 delayed_branch_p (&history
[0]),
6690 history
[0].mips16_absolute_jump_p
),
6691 make_expr_symbol (address_expr
), 0);
6693 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6695 if (!delayed_branch_p (ip
))
6696 /* Make sure there is enough room to swap this instruction with
6697 a following jump instruction. */
6699 add_fixed_insn (ip
);
6703 if (mips_opts
.mips16
6704 && mips_opts
.noreorder
6705 && delayed_branch_p (&history
[0]))
6706 as_warn (_("extended instruction in delay slot"));
6708 if (mips_relax
.sequence
)
6710 /* If we've reached the end of this frag, turn it into a variant
6711 frag and record the information for the instructions we've
6713 if (frag_room () < 4)
6714 relax_close_frag ();
6715 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6718 if (mips_relax
.sequence
!= 2)
6720 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6721 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6722 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6723 mips_macro_warning
.insns
[0]++;
6725 if (mips_relax
.sequence
!= 1)
6727 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6728 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6729 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6730 mips_macro_warning
.insns
[1]++;
6733 if (mips_opts
.mips16
)
6736 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6738 add_fixed_insn (ip
);
6741 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6743 bfd_reloc_code_real_type final_type
[3];
6744 reloc_howto_type
*howto0
;
6745 reloc_howto_type
*howto
;
6748 /* Perform any necessary conversion to microMIPS relocations
6749 and find out how many relocations there actually are. */
6750 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6751 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6753 /* In a compound relocation, it is the final (outermost)
6754 operator that determines the relocated field. */
6755 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6760 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6761 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6762 bfd_get_reloc_size (howto
),
6764 howto0
&& howto0
->pc_relative
,
6767 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6768 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6769 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6771 /* These relocations can have an addend that won't fit in
6772 4 octets for 64bit assembly. */
6774 && ! howto
->partial_inplace
6775 && (reloc_type
[0] == BFD_RELOC_16
6776 || reloc_type
[0] == BFD_RELOC_32
6777 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6778 || reloc_type
[0] == BFD_RELOC_GPREL16
6779 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6780 || reloc_type
[0] == BFD_RELOC_GPREL32
6781 || reloc_type
[0] == BFD_RELOC_64
6782 || reloc_type
[0] == BFD_RELOC_CTOR
6783 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6784 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6785 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6786 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6787 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6788 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6789 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6790 || hi16_reloc_p (reloc_type
[0])
6791 || lo16_reloc_p (reloc_type
[0])))
6792 ip
->fixp
[0]->fx_no_overflow
= 1;
6794 /* These relocations can have an addend that won't fit in 2 octets. */
6795 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6796 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6797 ip
->fixp
[0]->fx_no_overflow
= 1;
6799 if (mips_relax
.sequence
)
6801 if (mips_relax
.first_fixup
== 0)
6802 mips_relax
.first_fixup
= ip
->fixp
[0];
6804 else if (reloc_needs_lo_p (*reloc_type
))
6806 struct mips_hi_fixup
*hi_fixup
;
6808 /* Reuse the last entry if it already has a matching %lo. */
6809 hi_fixup
= mips_hi_fixup_list
;
6811 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6813 hi_fixup
= ((struct mips_hi_fixup
*)
6814 xmalloc (sizeof (struct mips_hi_fixup
)));
6815 hi_fixup
->next
= mips_hi_fixup_list
;
6816 mips_hi_fixup_list
= hi_fixup
;
6818 hi_fixup
->fixp
= ip
->fixp
[0];
6819 hi_fixup
->seg
= now_seg
;
6822 /* Add fixups for the second and third relocations, if given.
6823 Note that the ABI allows the second relocation to be
6824 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6825 moment we only use RSS_UNDEF, but we could add support
6826 for the others if it ever becomes necessary. */
6827 for (i
= 1; i
< 3; i
++)
6828 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6830 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6831 ip
->fixp
[0]->fx_size
, NULL
, 0,
6832 FALSE
, final_type
[i
]);
6834 /* Use fx_tcbit to mark compound relocs. */
6835 ip
->fixp
[0]->fx_tcbit
= 1;
6836 ip
->fixp
[i
]->fx_tcbit
= 1;
6841 /* Update the register mask information. */
6842 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6843 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6848 insert_into_history (0, 1, ip
);
6851 case APPEND_ADD_WITH_NOP
:
6853 struct mips_cl_insn
*nop
;
6855 insert_into_history (0, 1, ip
);
6856 nop
= get_delay_slot_nop (ip
);
6857 add_fixed_insn (nop
);
6858 insert_into_history (0, 1, nop
);
6859 if (mips_relax
.sequence
)
6860 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6864 case APPEND_ADD_COMPACT
:
6865 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6866 gas_assert (mips_opts
.mips16
);
6867 ip
->insn_opcode
|= 0x0080;
6868 find_altered_mips16_opcode (ip
);
6870 insert_into_history (0, 1, ip
);
6875 struct mips_cl_insn delay
= history
[0];
6876 if (mips_opts
.mips16
)
6878 know (delay
.frag
== ip
->frag
);
6879 move_insn (ip
, delay
.frag
, delay
.where
);
6880 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6882 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6884 /* Add the delay slot instruction to the end of the
6885 current frag and shrink the fixed part of the
6886 original frag. If the branch occupies the tail of
6887 the latter, move it backwards to cover the gap. */
6888 delay
.frag
->fr_fix
-= branch_disp
;
6889 if (delay
.frag
== ip
->frag
)
6890 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6891 add_fixed_insn (&delay
);
6895 move_insn (&delay
, ip
->frag
,
6896 ip
->where
- branch_disp
+ insn_length (ip
));
6897 move_insn (ip
, history
[0].frag
, history
[0].where
);
6901 insert_into_history (0, 1, &delay
);
6906 /* If we have just completed an unconditional branch, clear the history. */
6907 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6908 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6912 mips_no_prev_insn ();
6914 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6915 history
[i
].cleared_p
= 1;
6918 /* We need to emit a label at the end of branch-likely macros. */
6919 if (emit_branch_likely_macro
)
6921 emit_branch_likely_macro
= FALSE
;
6922 micromips_add_label ();
6925 /* We just output an insn, so the next one doesn't have a label. */
6926 mips_clear_insn_labels ();
6929 /* Forget that there was any previous instruction or label.
6930 When BRANCH is true, the branch history is also flushed. */
6933 mips_no_prev_insn (void)
6935 prev_nop_frag
= NULL
;
6936 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6937 mips_clear_insn_labels ();
6940 /* This function must be called before we emit something other than
6941 instructions. It is like mips_no_prev_insn except that it inserts
6942 any NOPS that might be needed by previous instructions. */
6945 mips_emit_delays (void)
6947 if (! mips_opts
.noreorder
)
6949 int nops
= nops_for_insn (0, history
, NULL
);
6953 add_fixed_insn (NOP_INSN
);
6954 mips_move_text_labels ();
6957 mips_no_prev_insn ();
6960 /* Start a (possibly nested) noreorder block. */
6963 start_noreorder (void)
6965 if (mips_opts
.noreorder
== 0)
6970 /* None of the instructions before the .set noreorder can be moved. */
6971 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6972 history
[i
].fixed_p
= 1;
6974 /* Insert any nops that might be needed between the .set noreorder
6975 block and the previous instructions. We will later remove any
6976 nops that turn out not to be needed. */
6977 nops
= nops_for_insn (0, history
, NULL
);
6980 if (mips_optimize
!= 0)
6982 /* Record the frag which holds the nop instructions, so
6983 that we can remove them if we don't need them. */
6984 frag_grow (nops
* NOP_INSN_SIZE
);
6985 prev_nop_frag
= frag_now
;
6986 prev_nop_frag_holds
= nops
;
6987 prev_nop_frag_required
= 0;
6988 prev_nop_frag_since
= 0;
6991 for (; nops
> 0; --nops
)
6992 add_fixed_insn (NOP_INSN
);
6994 /* Move on to a new frag, so that it is safe to simply
6995 decrease the size of prev_nop_frag. */
6996 frag_wane (frag_now
);
6998 mips_move_text_labels ();
7000 mips_mark_labels ();
7001 mips_clear_insn_labels ();
7003 mips_opts
.noreorder
++;
7004 mips_any_noreorder
= 1;
7007 /* End a nested noreorder block. */
7010 end_noreorder (void)
7012 mips_opts
.noreorder
--;
7013 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7015 /* Commit to inserting prev_nop_frag_required nops and go back to
7016 handling nop insertion the .set reorder way. */
7017 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7019 insert_into_history (prev_nop_frag_since
,
7020 prev_nop_frag_required
, NOP_INSN
);
7021 prev_nop_frag
= NULL
;
7025 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7026 higher bits unset. */
7029 normalize_constant_expr (expressionS
*ex
)
7031 if (ex
->X_op
== O_constant
7032 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7033 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7037 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7038 all higher bits unset. */
7041 normalize_address_expr (expressionS
*ex
)
7043 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7044 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7045 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7046 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7050 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7051 Return true if the match was successful.
7053 OPCODE_EXTRA is a value that should be ORed into the opcode
7054 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7055 there are more alternatives after OPCODE and SOFT_MATCH is
7056 as for mips_arg_info. */
7059 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7060 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7061 bfd_boolean more_alts
, bfd_boolean soft_match
)
7064 struct mips_arg_info arg
;
7065 const struct mips_operand
*operand
;
7068 imm_expr
.X_op
= O_absent
;
7069 imm2_expr
.X_op
= O_absent
;
7070 offset_expr
.X_op
= O_absent
;
7071 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7072 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7073 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7075 create_insn (insn
, opcode
);
7076 insn
->insn_opcode
|= opcode_extra
;
7077 memset (&arg
, 0, sizeof (arg
));
7081 arg
.last_regno
= ILLEGAL_REG
;
7082 arg
.dest_regno
= ILLEGAL_REG
;
7083 arg
.soft_match
= soft_match
;
7084 for (args
= opcode
->args
;; ++args
)
7086 if (arg
.token
->type
== OT_END
)
7088 /* Handle unary instructions in which only one operand is given.
7089 The source is then the same as the destination. */
7090 if (arg
.opnum
== 1 && *args
== ',')
7092 operand
= (mips_opts
.micromips
7093 ? decode_micromips_operand (args
+ 1)
7094 : decode_mips_operand (args
+ 1));
7095 if (operand
&& mips_optional_operand_p (operand
))
7103 /* Treat elided base registers as $0. */
7104 if (strcmp (args
, "(b)") == 0)
7112 /* The register suffix is optional. */
7117 /* Fail the match if there were too few operands. */
7121 /* Successful match. */
7122 clear_insn_error ();
7123 if (arg
.dest_regno
== arg
.last_regno
7124 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7128 (0, _("Source and destination must be different"));
7129 else if (arg
.last_regno
== 31)
7131 (0, _("A destination register must be supplied"));
7133 check_completed_insn (&arg
);
7137 /* Fail the match if the line has too many operands. */
7141 /* Handle characters that need to match exactly. */
7142 if (*args
== '(' || *args
== ')' || *args
== ',')
7144 if (match_char (&arg
, *args
))
7151 if (arg
.token
->type
== OT_DOUBLE_CHAR
7152 && arg
.token
->u
.ch
== *args
)
7160 /* Handle special macro operands. Work out the properties of
7163 arg
.lax_max
= FALSE
;
7182 /* If these integer forms come last, there is no other
7183 form of the instruction that could match. Prefer to
7184 give detailed error messages where possible. */
7186 arg
.soft_match
= FALSE
;
7190 /* "+I" is like "I", except that imm2_expr is used. */
7191 if (match_const_int (&arg
, &imm2_expr
.X_add_number
, 0))
7192 imm2_expr
.X_op
= O_constant
;
7194 set_insn_error (arg
.argnum
, _("absolute expression required"));
7195 if (HAVE_32BIT_GPRS
)
7196 normalize_constant_expr (&imm2_expr
);
7201 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7231 /* If these integer forms come last, there is no other
7232 form of the instruction that could match. Prefer to
7233 give detailed error messages where possible. */
7235 arg
.soft_match
= FALSE
;
7239 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
7240 imm_expr
.X_op
= O_constant
;
7242 set_insn_error (arg
.argnum
, _("absolute expression required"));
7243 if (HAVE_32BIT_GPRS
)
7244 normalize_constant_expr (&imm_expr
);
7248 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7250 /* Assume that the offset has been elided and that what
7251 we saw was a base register. The match will fail later
7252 if that assumption turns out to be wrong. */
7253 offset_expr
.X_op
= O_constant
;
7254 offset_expr
.X_add_number
= 0;
7256 else if (match_expression (&arg
, &offset_expr
, offset_reloc
))
7257 normalize_address_expr (&offset_expr
);
7259 set_insn_error (arg
.argnum
, _("absolute expression required"));
7263 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7265 set_insn_error (arg
.argnum
,
7266 _("floating-point expression required"));
7270 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7272 set_insn_error (arg
.argnum
,
7273 _("floating-point expression required"));
7277 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7279 set_insn_error (arg
.argnum
,
7280 _("floating-point expression required"));
7284 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7286 set_insn_error (arg
.argnum
,
7287 _("floating-point expression required"));
7290 /* ??? This is the traditional behavior, but is flaky if
7291 there are alternative versions of the same instruction
7292 for different subarchitectures. The next alternative
7293 might not be suitable. */
7295 /* For compatibility with older assemblers, we accept
7296 0x8000-0xffff as signed 16-bit numbers when only
7297 signed numbers are allowed. */
7298 arg
.lax_max
= !more_alts
;
7300 /* Only accept non-constant operands if this is the
7301 final alternative. Later alternatives might include
7302 a macro implementation. */
7303 arg
.allow_nonconst
= !more_alts
;
7307 /* There are no macro implementations for out-of-range values. */
7308 arg
.allow_nonconst
= TRUE
;
7312 /* There should always be a macro implementation. */
7313 arg
.allow_nonconst
= FALSE
;
7317 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7321 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7325 gas_assert (mips_opts
.micromips
);
7331 if (!forced_insn_length
)
7332 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7334 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7336 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7342 operand
= (mips_opts
.micromips
7343 ? decode_micromips_operand (args
)
7344 : decode_mips_operand (args
));
7348 /* Skip prefixes. */
7349 if (*args
== '+' || *args
== 'm')
7352 if (mips_optional_operand_p (operand
)
7354 && (arg
.token
[0].type
!= OT_REG
7355 || arg
.token
[1].type
== OT_END
))
7357 /* Assume that the register has been elided and is the
7358 same as the first operand. */
7363 if (!match_operand (&arg
, operand
))
7368 /* Like match_insn, but for MIPS16. */
7371 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7372 struct mips_operand_token
*tokens
, bfd_boolean soft_match
)
7375 const struct mips_operand
*operand
;
7376 const struct mips_operand
*ext_operand
;
7377 struct mips_arg_info arg
;
7380 create_insn (insn
, opcode
);
7381 imm_expr
.X_op
= O_absent
;
7382 imm2_expr
.X_op
= O_absent
;
7383 offset_expr
.X_op
= O_absent
;
7384 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7385 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7386 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7389 memset (&arg
, 0, sizeof (arg
));
7393 arg
.last_regno
= ILLEGAL_REG
;
7394 arg
.dest_regno
= ILLEGAL_REG
;
7395 arg
.soft_match
= soft_match
;
7397 for (args
= opcode
->args
;; ++args
)
7401 if (arg
.token
->type
== OT_END
)
7405 /* Handle unary instructions in which only one operand is given.
7406 The source is then the same as the destination. */
7407 if (arg
.opnum
== 1 && *args
== ',')
7409 operand
= decode_mips16_operand (args
[1], FALSE
);
7410 if (operand
&& mips_optional_operand_p (operand
))
7418 /* Fail the match if there were too few operands. */
7422 /* Successful match. Stuff the immediate value in now, if
7424 clear_insn_error ();
7425 if (opcode
->pinfo
== INSN_MACRO
)
7427 gas_assert (relax_char
== 0 || relax_char
== 'p');
7428 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7431 && offset_expr
.X_op
== O_constant
7432 && calculate_reloc (*offset_reloc
,
7433 offset_expr
.X_add_number
,
7436 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7437 forced_insn_length
, &insn
->insn_opcode
);
7438 offset_expr
.X_op
= O_absent
;
7439 *offset_reloc
= BFD_RELOC_UNUSED
;
7441 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7443 if (forced_insn_length
== 2)
7444 set_insn_error (0, _("invalid unextended operand value"));
7445 forced_insn_length
= 4;
7446 insn
->insn_opcode
|= MIPS16_EXTEND
;
7448 else if (relax_char
)
7449 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7451 check_completed_insn (&arg
);
7455 /* Fail the match if the line has too many operands. */
7459 /* Handle characters that need to match exactly. */
7460 if (*args
== '(' || *args
== ')' || *args
== ',')
7462 if (match_char (&arg
, *args
))
7480 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
7481 imm_expr
.X_op
= O_constant
;
7483 set_insn_error (arg
.argnum
, _("absolute expression required"));
7484 if (HAVE_32BIT_GPRS
)
7485 normalize_constant_expr (&imm_expr
);
7490 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7491 insn
->insn_opcode
<<= 16;
7495 operand
= decode_mips16_operand (c
, FALSE
);
7499 /* '6' is a special case. It is used for BREAK and SDBBP,
7500 whose operands are only meaningful to the software that decodes
7501 them. This means that there is no architectural reason why
7502 they cannot be prefixed by EXTEND, but in practice,
7503 exception handlers will only look at the instruction
7504 itself. We therefore allow '6' to be extended when
7505 disassembling but not when assembling. */
7506 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7508 ext_operand
= decode_mips16_operand (c
, TRUE
);
7509 if (operand
!= ext_operand
)
7511 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7513 offset_expr
.X_op
= O_constant
;
7514 offset_expr
.X_add_number
= 0;
7519 /* We need the OT_INTEGER check because some MIPS16
7520 immediate variants are listed before the register ones. */
7521 if (arg
.token
->type
!= OT_INTEGER
7522 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7525 /* '8' is used for SLTI(U) and has traditionally not
7526 been allowed to take relocation operators. */
7527 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7528 && (ext_operand
->size
!= 16 || c
== '8'))
7536 if (mips_optional_operand_p (operand
)
7538 && (arg
.token
[0].type
!= OT_REG
7539 || arg
.token
[1].type
== OT_END
))
7541 /* Assume that the register has been elided and is the
7542 same as the first operand. */
7547 if (!match_operand (&arg
, operand
))
7552 /* Set up global variables for the start of a new macro. */
7557 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7558 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7559 sizeof (mips_macro_warning
.first_insn_sizes
));
7560 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7561 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7562 && delayed_branch_p (&history
[0]));
7563 switch (history
[0].insn_mo
->pinfo2
7564 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7566 case INSN2_BRANCH_DELAY_32BIT
:
7567 mips_macro_warning
.delay_slot_length
= 4;
7569 case INSN2_BRANCH_DELAY_16BIT
:
7570 mips_macro_warning
.delay_slot_length
= 2;
7573 mips_macro_warning
.delay_slot_length
= 0;
7576 mips_macro_warning
.first_frag
= NULL
;
7579 /* Given that a macro is longer than one instruction or of the wrong size,
7580 return the appropriate warning for it. Return null if no warning is
7581 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7582 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7583 and RELAX_NOMACRO. */
7586 macro_warning (relax_substateT subtype
)
7588 if (subtype
& RELAX_DELAY_SLOT
)
7589 return _("Macro instruction expanded into multiple instructions"
7590 " in a branch delay slot");
7591 else if (subtype
& RELAX_NOMACRO
)
7592 return _("Macro instruction expanded into multiple instructions");
7593 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7594 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7595 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7596 ? _("Macro instruction expanded into a wrong size instruction"
7597 " in a 16-bit branch delay slot")
7598 : _("Macro instruction expanded into a wrong size instruction"
7599 " in a 32-bit branch delay slot"));
7604 /* Finish up a macro. Emit warnings as appropriate. */
7609 /* Relaxation warning flags. */
7610 relax_substateT subtype
= 0;
7612 /* Check delay slot size requirements. */
7613 if (mips_macro_warning
.delay_slot_length
== 2)
7614 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7615 if (mips_macro_warning
.delay_slot_length
!= 0)
7617 if (mips_macro_warning
.delay_slot_length
7618 != mips_macro_warning
.first_insn_sizes
[0])
7619 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7620 if (mips_macro_warning
.delay_slot_length
7621 != mips_macro_warning
.first_insn_sizes
[1])
7622 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7625 /* Check instruction count requirements. */
7626 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7628 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7629 subtype
|= RELAX_SECOND_LONGER
;
7630 if (mips_opts
.warn_about_macros
)
7631 subtype
|= RELAX_NOMACRO
;
7632 if (mips_macro_warning
.delay_slot_p
)
7633 subtype
|= RELAX_DELAY_SLOT
;
7636 /* If both alternatives fail to fill a delay slot correctly,
7637 emit the warning now. */
7638 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7639 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7644 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7645 | RELAX_DELAY_SLOT_SIZE_FIRST
7646 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7647 msg
= macro_warning (s
);
7649 as_warn ("%s", msg
);
7653 /* If both implementations are longer than 1 instruction, then emit the
7655 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7660 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7661 msg
= macro_warning (s
);
7663 as_warn ("%s", msg
);
7667 /* If any flags still set, then one implementation might need a warning
7668 and the other either will need one of a different kind or none at all.
7669 Pass any remaining flags over to relaxation. */
7670 if (mips_macro_warning
.first_frag
!= NULL
)
7671 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7674 /* Instruction operand formats used in macros that vary between
7675 standard MIPS and microMIPS code. */
7677 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7678 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7679 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7680 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7681 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7682 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7683 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7684 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7686 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7687 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7688 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7689 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7690 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7691 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7692 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7693 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7695 /* Read a macro's relocation codes from *ARGS and store them in *R.
7696 The first argument in *ARGS will be either the code for a single
7697 relocation or -1 followed by the three codes that make up a
7698 composite relocation. */
7701 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7705 next
= va_arg (*args
, int);
7707 r
[0] = (bfd_reloc_code_real_type
) next
;
7710 for (i
= 0; i
< 3; i
++)
7711 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7712 /* This function is only used for 16-bit relocation fields.
7713 To make the macro code simpler, treat an unrelocated value
7714 in the same way as BFD_RELOC_LO16. */
7715 if (r
[0] == BFD_RELOC_UNUSED
)
7716 r
[0] = BFD_RELOC_LO16
;
7720 /* Build an instruction created by a macro expansion. This is passed
7721 a pointer to the count of instructions created so far, an
7722 expression, the name of the instruction to build, an operand format
7723 string, and corresponding arguments. */
7726 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7728 const struct mips_opcode
*mo
= NULL
;
7729 bfd_reloc_code_real_type r
[3];
7730 const struct mips_opcode
*amo
;
7731 const struct mips_operand
*operand
;
7732 struct hash_control
*hash
;
7733 struct mips_cl_insn insn
;
7737 va_start (args
, fmt
);
7739 if (mips_opts
.mips16
)
7741 mips16_macro_build (ep
, name
, fmt
, &args
);
7746 r
[0] = BFD_RELOC_UNUSED
;
7747 r
[1] = BFD_RELOC_UNUSED
;
7748 r
[2] = BFD_RELOC_UNUSED
;
7749 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7750 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7752 gas_assert (strcmp (name
, amo
->name
) == 0);
7756 /* Search until we get a match for NAME. It is assumed here that
7757 macros will never generate MDMX, MIPS-3D, or MT instructions.
7758 We try to match an instruction that fulfils the branch delay
7759 slot instruction length requirement (if any) of the previous
7760 instruction. While doing this we record the first instruction
7761 seen that matches all the other conditions and use it anyway
7762 if the requirement cannot be met; we will issue an appropriate
7763 warning later on. */
7764 if (strcmp (fmt
, amo
->args
) == 0
7765 && amo
->pinfo
!= INSN_MACRO
7766 && is_opcode_valid (amo
)
7767 && is_size_valid (amo
))
7769 if (is_delay_slot_valid (amo
))
7779 gas_assert (amo
->name
);
7781 while (strcmp (name
, amo
->name
) == 0);
7784 create_insn (&insn
, mo
);
7797 macro_read_relocs (&args
, r
);
7798 gas_assert (*r
== BFD_RELOC_GPREL16
7799 || *r
== BFD_RELOC_MIPS_HIGHER
7800 || *r
== BFD_RELOC_HI16_S
7801 || *r
== BFD_RELOC_LO16
7802 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7806 macro_read_relocs (&args
, r
);
7810 macro_read_relocs (&args
, r
);
7811 gas_assert (ep
!= NULL
7812 && (ep
->X_op
== O_constant
7813 || (ep
->X_op
== O_symbol
7814 && (*r
== BFD_RELOC_MIPS_HIGHEST
7815 || *r
== BFD_RELOC_HI16_S
7816 || *r
== BFD_RELOC_HI16
7817 || *r
== BFD_RELOC_GPREL16
7818 || *r
== BFD_RELOC_MIPS_GOT_HI16
7819 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7823 gas_assert (ep
!= NULL
);
7826 * This allows macro() to pass an immediate expression for
7827 * creating short branches without creating a symbol.
7829 * We don't allow branch relaxation for these branches, as
7830 * they should only appear in ".set nomacro" anyway.
7832 if (ep
->X_op
== O_constant
)
7834 /* For microMIPS we always use relocations for branches.
7835 So we should not resolve immediate values. */
7836 gas_assert (!mips_opts
.micromips
);
7838 if ((ep
->X_add_number
& 3) != 0)
7839 as_bad (_("branch to misaligned address (0x%lx)"),
7840 (unsigned long) ep
->X_add_number
);
7841 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7842 as_bad (_("branch address range overflow (0x%lx)"),
7843 (unsigned long) ep
->X_add_number
);
7844 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7848 *r
= BFD_RELOC_16_PCREL_S2
;
7852 gas_assert (ep
!= NULL
);
7853 *r
= BFD_RELOC_MIPS_JMP
;
7857 operand
= (mips_opts
.micromips
7858 ? decode_micromips_operand (fmt
)
7859 : decode_mips_operand (fmt
));
7863 uval
= va_arg (args
, int);
7864 if (operand
->type
== OP_CLO_CLZ_DEST
)
7865 uval
|= (uval
<< 5);
7866 insn_insert_operand (&insn
, operand
, uval
);
7868 if (*fmt
== '+' || *fmt
== 'm')
7874 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7876 append_insn (&insn
, ep
, r
, TRUE
);
7880 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7883 struct mips_opcode
*mo
;
7884 struct mips_cl_insn insn
;
7885 const struct mips_operand
*operand
;
7886 bfd_reloc_code_real_type r
[3]
7887 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7889 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7891 gas_assert (strcmp (name
, mo
->name
) == 0);
7893 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7896 gas_assert (mo
->name
);
7897 gas_assert (strcmp (name
, mo
->name
) == 0);
7900 create_insn (&insn
, mo
);
7938 gas_assert (ep
!= NULL
);
7940 if (ep
->X_op
!= O_constant
)
7941 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7942 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7944 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7946 *r
= BFD_RELOC_UNUSED
;
7952 operand
= decode_mips16_operand (c
, FALSE
);
7956 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7961 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7963 append_insn (&insn
, ep
, r
, TRUE
);
7967 * Generate a "jalr" instruction with a relocation hint to the called
7968 * function. This occurs in NewABI PIC code.
7971 macro_build_jalr (expressionS
*ep
, int cprestore
)
7973 static const bfd_reloc_code_real_type jalr_relocs
[2]
7974 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7975 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7979 if (MIPS_JALR_HINT_P (ep
))
7984 if (mips_opts
.micromips
)
7986 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7987 ? "jalr" : "jalrs");
7988 if (MIPS_JALR_HINT_P (ep
)
7990 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7991 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7993 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7996 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7997 if (MIPS_JALR_HINT_P (ep
))
7998 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8002 * Generate a "lui" instruction.
8005 macro_build_lui (expressionS
*ep
, int regnum
)
8007 gas_assert (! mips_opts
.mips16
);
8009 if (ep
->X_op
!= O_constant
)
8011 gas_assert (ep
->X_op
== O_symbol
);
8012 /* _gp_disp is a special case, used from s_cpload.
8013 __gnu_local_gp is used if mips_no_shared. */
8014 gas_assert (mips_pic
== NO_PIC
8016 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8017 || (! mips_in_shared
8018 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8019 "__gnu_local_gp") == 0));
8022 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8025 /* Generate a sequence of instructions to do a load or store from a constant
8026 offset off of a base register (breg) into/from a target register (treg),
8027 using AT if necessary. */
8029 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8030 int treg
, int breg
, int dbl
)
8032 gas_assert (ep
->X_op
== O_constant
);
8034 /* Sign-extending 32-bit constants makes their handling easier. */
8036 normalize_constant_expr (ep
);
8038 /* Right now, this routine can only handle signed 32-bit constants. */
8039 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8040 as_warn (_("operand overflow"));
8042 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8044 /* Signed 16-bit offset will fit in the op. Easy! */
8045 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8049 /* 32-bit offset, need multiple instructions and AT, like:
8050 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8051 addu $tempreg,$tempreg,$breg
8052 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8053 to handle the complete offset. */
8054 macro_build_lui (ep
, AT
);
8055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8056 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8059 as_bad (_("Macro used $at after \".set noat\""));
8064 * Generates code to set the $at register to true (one)
8065 * if reg is less than the immediate expression.
8068 set_at (int reg
, int unsignedp
)
8070 if (imm_expr
.X_op
== O_constant
8071 && imm_expr
.X_add_number
>= -0x8000
8072 && imm_expr
.X_add_number
< 0x8000)
8073 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8074 AT
, reg
, BFD_RELOC_LO16
);
8077 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8078 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8082 /* Count the leading zeroes by performing a binary chop. This is a
8083 bulky bit of source, but performance is a LOT better for the
8084 majority of values than a simple loop to count the bits:
8085 for (lcnt = 0; (lcnt < 32); lcnt++)
8086 if ((v) & (1 << (31 - lcnt)))
8088 However it is not code size friendly, and the gain will drop a bit
8089 on certain cached systems.
8091 #define COUNT_TOP_ZEROES(v) \
8092 (((v) & ~0xffff) == 0 \
8093 ? ((v) & ~0xff) == 0 \
8094 ? ((v) & ~0xf) == 0 \
8095 ? ((v) & ~0x3) == 0 \
8096 ? ((v) & ~0x1) == 0 \
8101 : ((v) & ~0x7) == 0 \
8104 : ((v) & ~0x3f) == 0 \
8105 ? ((v) & ~0x1f) == 0 \
8108 : ((v) & ~0x7f) == 0 \
8111 : ((v) & ~0xfff) == 0 \
8112 ? ((v) & ~0x3ff) == 0 \
8113 ? ((v) & ~0x1ff) == 0 \
8116 : ((v) & ~0x7ff) == 0 \
8119 : ((v) & ~0x3fff) == 0 \
8120 ? ((v) & ~0x1fff) == 0 \
8123 : ((v) & ~0x7fff) == 0 \
8126 : ((v) & ~0xffffff) == 0 \
8127 ? ((v) & ~0xfffff) == 0 \
8128 ? ((v) & ~0x3ffff) == 0 \
8129 ? ((v) & ~0x1ffff) == 0 \
8132 : ((v) & ~0x7ffff) == 0 \
8135 : ((v) & ~0x3fffff) == 0 \
8136 ? ((v) & ~0x1fffff) == 0 \
8139 : ((v) & ~0x7fffff) == 0 \
8142 : ((v) & ~0xfffffff) == 0 \
8143 ? ((v) & ~0x3ffffff) == 0 \
8144 ? ((v) & ~0x1ffffff) == 0 \
8147 : ((v) & ~0x7ffffff) == 0 \
8150 : ((v) & ~0x3fffffff) == 0 \
8151 ? ((v) & ~0x1fffffff) == 0 \
8154 : ((v) & ~0x7fffffff) == 0 \
8159 * This routine generates the least number of instructions necessary to load
8160 * an absolute expression value into a register.
8163 load_register (int reg
, expressionS
*ep
, int dbl
)
8166 expressionS hi32
, lo32
;
8168 if (ep
->X_op
!= O_big
)
8170 gas_assert (ep
->X_op
== O_constant
);
8172 /* Sign-extending 32-bit constants makes their handling easier. */
8174 normalize_constant_expr (ep
);
8176 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8178 /* We can handle 16 bit signed values with an addiu to
8179 $zero. No need to ever use daddiu here, since $zero and
8180 the result are always correct in 32 bit mode. */
8181 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8184 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8186 /* We can handle 16 bit unsigned values with an ori to
8188 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8191 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8193 /* 32 bit values require an lui. */
8194 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8195 if ((ep
->X_add_number
& 0xffff) != 0)
8196 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8201 /* The value is larger than 32 bits. */
8203 if (!dbl
|| HAVE_32BIT_GPRS
)
8207 sprintf_vma (value
, ep
->X_add_number
);
8208 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8209 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8213 if (ep
->X_op
!= O_big
)
8216 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8217 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8218 hi32
.X_add_number
&= 0xffffffff;
8220 lo32
.X_add_number
&= 0xffffffff;
8224 gas_assert (ep
->X_add_number
> 2);
8225 if (ep
->X_add_number
== 3)
8226 generic_bignum
[3] = 0;
8227 else if (ep
->X_add_number
> 4)
8228 as_bad (_("Number larger than 64 bits"));
8229 lo32
.X_op
= O_constant
;
8230 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8231 hi32
.X_op
= O_constant
;
8232 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8235 if (hi32
.X_add_number
== 0)
8240 unsigned long hi
, lo
;
8242 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8244 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8246 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8249 if (lo32
.X_add_number
& 0x80000000)
8251 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8252 if (lo32
.X_add_number
& 0xffff)
8253 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8258 /* Check for 16bit shifted constant. We know that hi32 is
8259 non-zero, so start the mask on the first bit of the hi32
8264 unsigned long himask
, lomask
;
8268 himask
= 0xffff >> (32 - shift
);
8269 lomask
= (0xffff << shift
) & 0xffffffff;
8273 himask
= 0xffff << (shift
- 32);
8276 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8277 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8281 tmp
.X_op
= O_constant
;
8283 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8284 | (lo32
.X_add_number
>> shift
));
8286 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8287 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8288 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8289 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8294 while (shift
<= (64 - 16));
8296 /* Find the bit number of the lowest one bit, and store the
8297 shifted value in hi/lo. */
8298 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8299 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8303 while ((lo
& 1) == 0)
8308 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8314 while ((hi
& 1) == 0)
8323 /* Optimize if the shifted value is a (power of 2) - 1. */
8324 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8325 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8327 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8332 /* This instruction will set the register to be all
8334 tmp
.X_op
= O_constant
;
8335 tmp
.X_add_number
= (offsetT
) -1;
8336 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8340 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8341 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8343 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8344 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8349 /* Sign extend hi32 before calling load_register, because we can
8350 generally get better code when we load a sign extended value. */
8351 if ((hi32
.X_add_number
& 0x80000000) != 0)
8352 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8353 load_register (reg
, &hi32
, 0);
8356 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8360 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8368 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8370 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8371 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8377 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8381 mid16
.X_add_number
>>= 16;
8382 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8383 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8386 if ((lo32
.X_add_number
& 0xffff) != 0)
8387 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8391 load_delay_nop (void)
8393 if (!gpr_interlocks
)
8394 macro_build (NULL
, "nop", "");
8397 /* Load an address into a register. */
8400 load_address (int reg
, expressionS
*ep
, int *used_at
)
8402 if (ep
->X_op
!= O_constant
8403 && ep
->X_op
!= O_symbol
)
8405 as_bad (_("expression too complex"));
8406 ep
->X_op
= O_constant
;
8409 if (ep
->X_op
== O_constant
)
8411 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8415 if (mips_pic
== NO_PIC
)
8417 /* If this is a reference to a GP relative symbol, we want
8418 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8420 lui $reg,<sym> (BFD_RELOC_HI16_S)
8421 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8422 If we have an addend, we always use the latter form.
8424 With 64bit address space and a usable $at we want
8425 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8426 lui $at,<sym> (BFD_RELOC_HI16_S)
8427 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8428 daddiu $at,<sym> (BFD_RELOC_LO16)
8432 If $at is already in use, we use a path which is suboptimal
8433 on superscalar processors.
8434 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8435 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8437 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8439 daddiu $reg,<sym> (BFD_RELOC_LO16)
8441 For GP relative symbols in 64bit address space we can use
8442 the same sequence as in 32bit address space. */
8443 if (HAVE_64BIT_SYMBOLS
)
8445 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8446 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8448 relax_start (ep
->X_add_symbol
);
8449 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8450 mips_gp_register
, BFD_RELOC_GPREL16
);
8454 if (*used_at
== 0 && mips_opts
.at
)
8456 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8457 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8458 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8459 BFD_RELOC_MIPS_HIGHER
);
8460 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8461 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8462 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8467 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8468 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8469 BFD_RELOC_MIPS_HIGHER
);
8470 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8471 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8472 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8473 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8476 if (mips_relax
.sequence
)
8481 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8482 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8484 relax_start (ep
->X_add_symbol
);
8485 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8486 mips_gp_register
, BFD_RELOC_GPREL16
);
8489 macro_build_lui (ep
, reg
);
8490 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8491 reg
, reg
, BFD_RELOC_LO16
);
8492 if (mips_relax
.sequence
)
8496 else if (!mips_big_got
)
8500 /* If this is a reference to an external symbol, we want
8501 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8503 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8505 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8506 If there is a constant, it must be added in after.
8508 If we have NewABI, we want
8509 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8510 unless we're referencing a global symbol with a non-zero
8511 offset, in which case cst must be added separately. */
8514 if (ep
->X_add_number
)
8516 ex
.X_add_number
= ep
->X_add_number
;
8517 ep
->X_add_number
= 0;
8518 relax_start (ep
->X_add_symbol
);
8519 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8520 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8521 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8522 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8523 ex
.X_op
= O_constant
;
8524 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8525 reg
, reg
, BFD_RELOC_LO16
);
8526 ep
->X_add_number
= ex
.X_add_number
;
8529 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8530 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8531 if (mips_relax
.sequence
)
8536 ex
.X_add_number
= ep
->X_add_number
;
8537 ep
->X_add_number
= 0;
8538 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8539 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8541 relax_start (ep
->X_add_symbol
);
8543 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8547 if (ex
.X_add_number
!= 0)
8549 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8550 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8551 ex
.X_op
= O_constant
;
8552 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8553 reg
, reg
, BFD_RELOC_LO16
);
8557 else if (mips_big_got
)
8561 /* This is the large GOT case. If this is a reference to an
8562 external symbol, we want
8563 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8565 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8567 Otherwise, for a reference to a local symbol in old ABI, we want
8568 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8570 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8571 If there is a constant, it must be added in after.
8573 In the NewABI, for local symbols, with or without offsets, we want:
8574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8575 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8579 ex
.X_add_number
= ep
->X_add_number
;
8580 ep
->X_add_number
= 0;
8581 relax_start (ep
->X_add_symbol
);
8582 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8583 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8584 reg
, reg
, mips_gp_register
);
8585 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8586 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8587 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8588 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8589 else if (ex
.X_add_number
)
8591 ex
.X_op
= O_constant
;
8592 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8596 ep
->X_add_number
= ex
.X_add_number
;
8598 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8599 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8600 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8601 BFD_RELOC_MIPS_GOT_OFST
);
8606 ex
.X_add_number
= ep
->X_add_number
;
8607 ep
->X_add_number
= 0;
8608 relax_start (ep
->X_add_symbol
);
8609 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8611 reg
, reg
, mips_gp_register
);
8612 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8613 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8615 if (reg_needs_delay (mips_gp_register
))
8617 /* We need a nop before loading from $gp. This special
8618 check is required because the lui which starts the main
8619 instruction stream does not refer to $gp, and so will not
8620 insert the nop which may be required. */
8621 macro_build (NULL
, "nop", "");
8623 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8624 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8626 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8630 if (ex
.X_add_number
!= 0)
8632 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8633 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8634 ex
.X_op
= O_constant
;
8635 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8643 if (!mips_opts
.at
&& *used_at
== 1)
8644 as_bad (_("Macro used $at after \".set noat\""));
8647 /* Move the contents of register SOURCE into register DEST. */
8650 move_register (int dest
, int source
)
8652 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8653 instruction specifically requires a 32-bit one. */
8654 if (mips_opts
.micromips
8655 && !mips_opts
.insn32
8656 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8657 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8659 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8663 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8664 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8665 The two alternatives are:
8667 Global symbol Local sybmol
8668 ------------- ------------
8669 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8671 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8673 load_got_offset emits the first instruction and add_got_offset
8674 emits the second for a 16-bit offset or add_got_offset_hilo emits
8675 a sequence to add a 32-bit offset using a scratch register. */
8678 load_got_offset (int dest
, expressionS
*local
)
8683 global
.X_add_number
= 0;
8685 relax_start (local
->X_add_symbol
);
8686 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8687 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8689 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8690 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8695 add_got_offset (int dest
, expressionS
*local
)
8699 global
.X_op
= O_constant
;
8700 global
.X_op_symbol
= NULL
;
8701 global
.X_add_symbol
= NULL
;
8702 global
.X_add_number
= local
->X_add_number
;
8704 relax_start (local
->X_add_symbol
);
8705 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8706 dest
, dest
, BFD_RELOC_LO16
);
8708 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8713 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8716 int hold_mips_optimize
;
8718 global
.X_op
= O_constant
;
8719 global
.X_op_symbol
= NULL
;
8720 global
.X_add_symbol
= NULL
;
8721 global
.X_add_number
= local
->X_add_number
;
8723 relax_start (local
->X_add_symbol
);
8724 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8726 /* Set mips_optimize around the lui instruction to avoid
8727 inserting an unnecessary nop after the lw. */
8728 hold_mips_optimize
= mips_optimize
;
8730 macro_build_lui (&global
, tmp
);
8731 mips_optimize
= hold_mips_optimize
;
8732 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8735 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8738 /* Emit a sequence of instructions to emulate a branch likely operation.
8739 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8740 is its complementing branch with the original condition negated.
8741 CALL is set if the original branch specified the link operation.
8742 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8744 Code like this is produced in the noreorder mode:
8749 delay slot (executed only if branch taken)
8757 delay slot (executed only if branch taken)
8760 In the reorder mode the delay slot would be filled with a nop anyway,
8761 so code produced is simply:
8766 This function is used when producing code for the microMIPS ASE that
8767 does not implement branch likely instructions in hardware. */
8770 macro_build_branch_likely (const char *br
, const char *brneg
,
8771 int call
, expressionS
*ep
, const char *fmt
,
8772 unsigned int sreg
, unsigned int treg
)
8774 int noreorder
= mips_opts
.noreorder
;
8777 gas_assert (mips_opts
.micromips
);
8781 micromips_label_expr (&expr1
);
8782 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8783 macro_build (NULL
, "nop", "");
8784 macro_build (ep
, call
? "bal" : "b", "p");
8786 /* Set to true so that append_insn adds a label. */
8787 emit_branch_likely_macro
= TRUE
;
8791 macro_build (ep
, br
, fmt
, sreg
, treg
);
8792 macro_build (NULL
, "nop", "");
8797 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8798 the condition code tested. EP specifies the branch target. */
8801 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8828 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8831 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8832 the register tested. EP specifies the branch target. */
8835 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8837 const char *brneg
= NULL
;
8847 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8851 gas_assert (mips_opts
.micromips
);
8852 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8860 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8867 br
= mips_opts
.micromips
? "blez" : "blezl";
8874 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8878 gas_assert (mips_opts
.micromips
);
8879 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8886 if (mips_opts
.micromips
&& brneg
)
8887 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8889 macro_build (ep
, br
, "s,p", sreg
);
8892 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8893 TREG as the registers tested. EP specifies the branch target. */
8896 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8897 unsigned int sreg
, unsigned int treg
)
8899 const char *brneg
= NULL
;
8911 br
= mips_opts
.micromips
? "beq" : "beql";
8920 br
= mips_opts
.micromips
? "bne" : "bnel";
8926 if (mips_opts
.micromips
&& brneg
)
8927 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8929 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8932 /* Return the high part that should be loaded in order to make the low
8933 part of VALUE accessible using an offset of OFFBITS bits. */
8936 offset_high_part (offsetT value
, unsigned int offbits
)
8943 bias
= 1 << (offbits
- 1);
8944 low_mask
= bias
* 2 - 1;
8945 return (value
+ bias
) & ~low_mask
;
8948 /* Return true if the value stored in offset_expr and offset_reloc
8949 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8950 amount that the caller wants to add without inducing overflow
8951 and ALIGN is the known alignment of the value in bytes. */
8954 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8958 /* Accept any relocation operator if overflow isn't a concern. */
8959 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8962 /* These relocations are guaranteed not to overflow in correct links. */
8963 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8964 || gprel16_reloc_p (*offset_reloc
))
8967 if (offset_expr
.X_op
== O_constant
8968 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8969 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8976 * This routine implements the seemingly endless macro or synthesized
8977 * instructions and addressing modes in the mips assembly language. Many
8978 * of these macros are simple and are similar to each other. These could
8979 * probably be handled by some kind of table or grammar approach instead of
8980 * this verbose method. Others are not simple macros but are more like
8981 * optimizing code generation.
8982 * One interesting optimization is when several store macros appear
8983 * consecutively that would load AT with the upper half of the same address.
8984 * The ensuing load upper instructions are ommited. This implies some kind
8985 * of global optimization. We currently only optimize within a single macro.
8986 * For many of the load and store macros if the address is specified as a
8987 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8988 * first load register 'at' with zero and use it as the base register. The
8989 * mips assembler simply uses register $zero. Just one tiny optimization
8993 macro (struct mips_cl_insn
*ip
, char *str
)
8995 const struct mips_operand_array
*operands
;
8996 unsigned int breg
, i
;
8997 unsigned int tempreg
;
9000 expressionS label_expr
;
9015 bfd_boolean large_offset
;
9017 int hold_mips_optimize
;
9019 unsigned int op
[MAX_OPERANDS
];
9021 gas_assert (! mips_opts
.mips16
);
9023 operands
= insn_operands (ip
);
9024 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9025 if (operands
->operand
[i
])
9026 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9030 mask
= ip
->insn_mo
->mask
;
9032 label_expr
.X_op
= O_constant
;
9033 label_expr
.X_op_symbol
= NULL
;
9034 label_expr
.X_add_symbol
= NULL
;
9035 label_expr
.X_add_number
= 0;
9037 expr1
.X_op
= O_constant
;
9038 expr1
.X_op_symbol
= NULL
;
9039 expr1
.X_add_symbol
= NULL
;
9040 expr1
.X_add_number
= 1;
9056 if (mips_opts
.micromips
)
9057 micromips_label_expr (&label_expr
);
9059 label_expr
.X_add_number
= 8;
9060 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9062 macro_build (NULL
, "nop", "");
9064 move_register (op
[0], op
[1]);
9065 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9066 if (mips_opts
.micromips
)
9067 micromips_add_label ();
9084 if (!mips_opts
.micromips
)
9086 if (imm_expr
.X_op
== O_constant
9087 && imm_expr
.X_add_number
>= -0x200
9088 && imm_expr
.X_add_number
< 0x200)
9090 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], imm_expr
.X_add_number
);
9099 if (imm_expr
.X_op
== O_constant
9100 && imm_expr
.X_add_number
>= -0x8000
9101 && imm_expr
.X_add_number
< 0x8000)
9103 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9108 load_register (AT
, &imm_expr
, dbl
);
9109 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9128 if (imm_expr
.X_op
== O_constant
9129 && imm_expr
.X_add_number
>= 0
9130 && imm_expr
.X_add_number
< 0x10000)
9132 if (mask
!= M_NOR_I
)
9133 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9136 macro_build (&imm_expr
, "ori", "t,r,i",
9137 op
[0], op
[1], BFD_RELOC_LO16
);
9138 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9144 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9145 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9149 switch (imm_expr
.X_add_number
)
9152 macro_build (NULL
, "nop", "");
9155 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9159 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9160 (int) imm_expr
.X_add_number
);
9163 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9164 (unsigned long) imm_expr
.X_add_number
);
9173 gas_assert (mips_opts
.micromips
);
9174 macro_build_branch_ccl (mask
, &offset_expr
,
9175 EXTRACT_OPERAND (1, BCC
, *ip
));
9182 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9188 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9193 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9200 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9201 else if (op
[0] == 0)
9202 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9206 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9207 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9208 &offset_expr
, AT
, ZERO
);
9218 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9224 /* Check for > max integer. */
9225 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9228 /* Result is always false. */
9230 macro_build (NULL
, "nop", "");
9232 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9235 if (imm_expr
.X_op
!= O_constant
)
9236 as_bad (_("Unsupported large constant"));
9237 ++imm_expr
.X_add_number
;
9241 if (mask
== M_BGEL_I
)
9243 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9245 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9246 &offset_expr
, op
[0]);
9249 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9251 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9252 &offset_expr
, op
[0]);
9255 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
9258 /* result is always true */
9259 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
9260 macro_build (&offset_expr
, "b", "p");
9265 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9266 &offset_expr
, AT
, ZERO
);
9274 else if (op
[0] == 0)
9275 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9276 &offset_expr
, ZERO
, op
[1]);
9280 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9281 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9282 &offset_expr
, AT
, ZERO
);
9291 && imm_expr
.X_op
== O_constant
9292 && imm_expr
.X_add_number
== -1))
9294 if (imm_expr
.X_op
!= O_constant
)
9295 as_bad (_("Unsupported large constant"));
9296 ++imm_expr
.X_add_number
;
9300 if (mask
== M_BGEUL_I
)
9302 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9304 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9305 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9306 &offset_expr
, op
[0], ZERO
);
9311 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9312 &offset_expr
, AT
, ZERO
);
9320 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9321 else if (op
[0] == 0)
9322 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9326 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9327 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9328 &offset_expr
, AT
, ZERO
);
9336 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9337 &offset_expr
, op
[0], ZERO
);
9338 else if (op
[0] == 0)
9343 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9344 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9345 &offset_expr
, AT
, ZERO
);
9353 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9354 else if (op
[0] == 0)
9355 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9359 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9360 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9361 &offset_expr
, AT
, ZERO
);
9368 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9370 if (imm_expr
.X_op
!= O_constant
)
9371 as_bad (_("Unsupported large constant"));
9372 ++imm_expr
.X_add_number
;
9376 if (mask
== M_BLTL_I
)
9378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9379 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9380 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9381 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9386 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9387 &offset_expr
, AT
, ZERO
);
9395 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9396 &offset_expr
, op
[0], ZERO
);
9397 else if (op
[0] == 0)
9402 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9403 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9404 &offset_expr
, AT
, ZERO
);
9413 && imm_expr
.X_op
== O_constant
9414 && imm_expr
.X_add_number
== -1))
9416 if (imm_expr
.X_op
!= O_constant
)
9417 as_bad (_("Unsupported large constant"));
9418 ++imm_expr
.X_add_number
;
9422 if (mask
== M_BLTUL_I
)
9424 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9426 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9427 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9428 &offset_expr
, op
[0], ZERO
);
9433 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9434 &offset_expr
, AT
, ZERO
);
9442 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9443 else if (op
[0] == 0)
9444 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9448 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9449 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9450 &offset_expr
, AT
, ZERO
);
9459 else if (op
[0] == 0)
9460 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9461 &offset_expr
, ZERO
, op
[1]);
9465 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9466 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9467 &offset_expr
, AT
, ZERO
);
9473 /* Use unsigned arithmetic. */
9477 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
9479 as_bad (_("Unsupported large constant"));
9484 pos
= imm_expr
.X_add_number
;
9485 size
= imm2_expr
.X_add_number
;
9490 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
9493 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
9495 report_bad_field (pos
, size
);
9499 if (size
<= 32 && pos
< 32)
9504 else if (size
<= 32)
9514 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
9521 /* Use unsigned arithmetic. */
9525 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
9527 as_bad (_("Unsupported large constant"));
9532 pos
= imm_expr
.X_add_number
;
9533 size
= imm2_expr
.X_add_number
;
9538 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
9541 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
9543 report_bad_field (pos
, size
);
9547 if (pos
< 32 && (pos
+ size
- 1) < 32)
9562 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
9563 (int) (pos
+ size
- 1));
9579 as_warn (_("Divide by zero."));
9581 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9583 macro_build (NULL
, "break", BRK_FMT
, 7);
9590 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9591 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9595 if (mips_opts
.micromips
)
9596 micromips_label_expr (&label_expr
);
9598 label_expr
.X_add_number
= 8;
9599 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9600 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9601 macro_build (NULL
, "break", BRK_FMT
, 7);
9602 if (mips_opts
.micromips
)
9603 micromips_add_label ();
9605 expr1
.X_add_number
= -1;
9607 load_register (AT
, &expr1
, dbl
);
9608 if (mips_opts
.micromips
)
9609 micromips_label_expr (&label_expr
);
9611 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9612 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9615 expr1
.X_add_number
= 1;
9616 load_register (AT
, &expr1
, dbl
);
9617 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9621 expr1
.X_add_number
= 0x80000000;
9622 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9626 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9627 /* We want to close the noreorder block as soon as possible, so
9628 that later insns are available for delay slot filling. */
9633 if (mips_opts
.micromips
)
9634 micromips_label_expr (&label_expr
);
9636 label_expr
.X_add_number
= 8;
9637 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9638 macro_build (NULL
, "nop", "");
9640 /* We want to close the noreorder block as soon as possible, so
9641 that later insns are available for delay slot filling. */
9644 macro_build (NULL
, "break", BRK_FMT
, 6);
9646 if (mips_opts
.micromips
)
9647 micromips_add_label ();
9648 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9687 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9689 as_warn (_("Divide by zero."));
9691 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9693 macro_build (NULL
, "break", BRK_FMT
, 7);
9696 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9698 if (strcmp (s2
, "mflo") == 0)
9699 move_register (op
[0], op
[1]);
9701 move_register (op
[0], ZERO
);
9704 if (imm_expr
.X_op
== O_constant
9705 && imm_expr
.X_add_number
== -1
9706 && s
[strlen (s
) - 1] != 'u')
9708 if (strcmp (s2
, "mflo") == 0)
9709 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9711 move_register (op
[0], ZERO
);
9716 load_register (AT
, &imm_expr
, dbl
);
9717 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9718 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9740 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9741 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9742 /* We want to close the noreorder block as soon as possible, so
9743 that later insns are available for delay slot filling. */
9748 if (mips_opts
.micromips
)
9749 micromips_label_expr (&label_expr
);
9751 label_expr
.X_add_number
= 8;
9752 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9753 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9755 /* We want to close the noreorder block as soon as possible, so
9756 that later insns are available for delay slot filling. */
9758 macro_build (NULL
, "break", BRK_FMT
, 7);
9759 if (mips_opts
.micromips
)
9760 micromips_add_label ();
9762 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9774 /* Load the address of a symbol into a register. If breg is not
9775 zero, we then add a base register to it. */
9778 if (dbl
&& HAVE_32BIT_GPRS
)
9779 as_warn (_("dla used to load 32-bit register"));
9781 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9782 as_warn (_("la used to load 64-bit address"));
9784 if (small_offset_p (0, align
, 16))
9786 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9787 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9791 if (mips_opts
.at
&& (op
[0] == breg
))
9799 if (offset_expr
.X_op
!= O_symbol
9800 && offset_expr
.X_op
!= O_constant
)
9802 as_bad (_("Expression too complex"));
9803 offset_expr
.X_op
= O_constant
;
9806 if (offset_expr
.X_op
== O_constant
)
9807 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9808 else if (mips_pic
== NO_PIC
)
9810 /* If this is a reference to a GP relative symbol, we want
9811 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9813 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9814 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9815 If we have a constant, we need two instructions anyhow,
9816 so we may as well always use the latter form.
9818 With 64bit address space and a usable $at we want
9819 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9820 lui $at,<sym> (BFD_RELOC_HI16_S)
9821 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9822 daddiu $at,<sym> (BFD_RELOC_LO16)
9824 daddu $tempreg,$tempreg,$at
9826 If $at is already in use, we use a path which is suboptimal
9827 on superscalar processors.
9828 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9829 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9831 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9833 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9835 For GP relative symbols in 64bit address space we can use
9836 the same sequence as in 32bit address space. */
9837 if (HAVE_64BIT_SYMBOLS
)
9839 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9840 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9842 relax_start (offset_expr
.X_add_symbol
);
9843 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9844 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9848 if (used_at
== 0 && mips_opts
.at
)
9850 macro_build (&offset_expr
, "lui", LUI_FMT
,
9851 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9852 macro_build (&offset_expr
, "lui", LUI_FMT
,
9853 AT
, BFD_RELOC_HI16_S
);
9854 macro_build (&offset_expr
, "daddiu", "t,r,j",
9855 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9856 macro_build (&offset_expr
, "daddiu", "t,r,j",
9857 AT
, AT
, BFD_RELOC_LO16
);
9858 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9859 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9864 macro_build (&offset_expr
, "lui", LUI_FMT
,
9865 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9866 macro_build (&offset_expr
, "daddiu", "t,r,j",
9867 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9868 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9869 macro_build (&offset_expr
, "daddiu", "t,r,j",
9870 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9871 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9872 macro_build (&offset_expr
, "daddiu", "t,r,j",
9873 tempreg
, tempreg
, BFD_RELOC_LO16
);
9876 if (mips_relax
.sequence
)
9881 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9882 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9884 relax_start (offset_expr
.X_add_symbol
);
9885 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9886 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9889 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9890 as_bad (_("Offset too large"));
9891 macro_build_lui (&offset_expr
, tempreg
);
9892 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9893 tempreg
, tempreg
, BFD_RELOC_LO16
);
9894 if (mips_relax
.sequence
)
9898 else if (!mips_big_got
&& !HAVE_NEWABI
)
9900 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9902 /* If this is a reference to an external symbol, and there
9903 is no constant, we want
9904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9905 or for lca or if tempreg is PIC_CALL_REG
9906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9907 For a local symbol, we want
9908 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9910 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9912 If we have a small constant, and this is a reference to
9913 an external symbol, we want
9914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9916 addiu $tempreg,$tempreg,<constant>
9917 For a local symbol, we want the same instruction
9918 sequence, but we output a BFD_RELOC_LO16 reloc on the
9921 If we have a large constant, and this is a reference to
9922 an external symbol, we want
9923 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9924 lui $at,<hiconstant>
9925 addiu $at,$at,<loconstant>
9926 addu $tempreg,$tempreg,$at
9927 For a local symbol, we want the same instruction
9928 sequence, but we output a BFD_RELOC_LO16 reloc on the
9932 if (offset_expr
.X_add_number
== 0)
9934 if (mips_pic
== SVR4_PIC
9936 && (call
|| tempreg
== PIC_CALL_REG
))
9937 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9939 relax_start (offset_expr
.X_add_symbol
);
9940 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9941 lw_reloc_type
, mips_gp_register
);
9944 /* We're going to put in an addu instruction using
9945 tempreg, so we may as well insert the nop right
9950 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9951 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9953 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9954 tempreg
, tempreg
, BFD_RELOC_LO16
);
9956 /* FIXME: If breg == 0, and the next instruction uses
9957 $tempreg, then if this variant case is used an extra
9958 nop will be generated. */
9960 else if (offset_expr
.X_add_number
>= -0x8000
9961 && offset_expr
.X_add_number
< 0x8000)
9963 load_got_offset (tempreg
, &offset_expr
);
9965 add_got_offset (tempreg
, &offset_expr
);
9969 expr1
.X_add_number
= offset_expr
.X_add_number
;
9970 offset_expr
.X_add_number
=
9971 SEXT_16BIT (offset_expr
.X_add_number
);
9972 load_got_offset (tempreg
, &offset_expr
);
9973 offset_expr
.X_add_number
= expr1
.X_add_number
;
9974 /* If we are going to add in a base register, and the
9975 target register and the base register are the same,
9976 then we are using AT as a temporary register. Since
9977 we want to load the constant into AT, we add our
9978 current AT (from the global offset table) and the
9979 register into the register now, and pretend we were
9980 not using a base register. */
9984 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9989 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9993 else if (!mips_big_got
&& HAVE_NEWABI
)
9995 int add_breg_early
= 0;
9997 /* If this is a reference to an external, and there is no
9998 constant, or local symbol (*), with or without a
10000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10001 or for lca or if tempreg is PIC_CALL_REG
10002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10004 If we have a small constant, and this is a reference to
10005 an external symbol, we want
10006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10007 addiu $tempreg,$tempreg,<constant>
10009 If we have a large constant, and this is a reference to
10010 an external symbol, we want
10011 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10012 lui $at,<hiconstant>
10013 addiu $at,$at,<loconstant>
10014 addu $tempreg,$tempreg,$at
10016 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10017 local symbols, even though it introduces an additional
10020 if (offset_expr
.X_add_number
)
10022 expr1
.X_add_number
= offset_expr
.X_add_number
;
10023 offset_expr
.X_add_number
= 0;
10025 relax_start (offset_expr
.X_add_symbol
);
10026 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10027 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10029 if (expr1
.X_add_number
>= -0x8000
10030 && expr1
.X_add_number
< 0x8000)
10032 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10033 tempreg
, tempreg
, BFD_RELOC_LO16
);
10035 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10039 /* If we are going to add in a base register, and the
10040 target register and the base register are the same,
10041 then we are using AT as a temporary register. Since
10042 we want to load the constant into AT, we add our
10043 current AT (from the global offset table) and the
10044 register into the register now, and pretend we were
10045 not using a base register. */
10050 gas_assert (tempreg
== AT
);
10051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10054 add_breg_early
= 1;
10057 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10064 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10067 offset_expr
.X_add_number
= expr1
.X_add_number
;
10069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10070 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10071 if (add_breg_early
)
10073 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10074 op
[0], tempreg
, breg
);
10080 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10082 relax_start (offset_expr
.X_add_symbol
);
10083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10084 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10086 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10087 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10092 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10093 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10096 else if (mips_big_got
&& !HAVE_NEWABI
)
10099 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10100 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10101 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10103 /* This is the large GOT case. If this is a reference to an
10104 external symbol, and there is no constant, we want
10105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10106 addu $tempreg,$tempreg,$gp
10107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10108 or for lca or if tempreg is PIC_CALL_REG
10109 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10110 addu $tempreg,$tempreg,$gp
10111 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10112 For a local symbol, we want
10113 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10115 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10117 If we have a small constant, and this is a reference to
10118 an external symbol, we want
10119 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10120 addu $tempreg,$tempreg,$gp
10121 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10123 addiu $tempreg,$tempreg,<constant>
10124 For a local symbol, we want
10125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10127 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10129 If we have a large constant, and this is a reference to
10130 an external symbol, we want
10131 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10132 addu $tempreg,$tempreg,$gp
10133 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10134 lui $at,<hiconstant>
10135 addiu $at,$at,<loconstant>
10136 addu $tempreg,$tempreg,$at
10137 For a local symbol, we want
10138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10139 lui $at,<hiconstant>
10140 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10141 addu $tempreg,$tempreg,$at
10144 expr1
.X_add_number
= offset_expr
.X_add_number
;
10145 offset_expr
.X_add_number
= 0;
10146 relax_start (offset_expr
.X_add_symbol
);
10147 gpdelay
= reg_needs_delay (mips_gp_register
);
10148 if (expr1
.X_add_number
== 0 && breg
== 0
10149 && (call
|| tempreg
== PIC_CALL_REG
))
10151 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10152 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10154 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10155 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10156 tempreg
, tempreg
, mips_gp_register
);
10157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10158 tempreg
, lw_reloc_type
, tempreg
);
10159 if (expr1
.X_add_number
== 0)
10163 /* We're going to put in an addu instruction using
10164 tempreg, so we may as well insert the nop right
10169 else if (expr1
.X_add_number
>= -0x8000
10170 && expr1
.X_add_number
< 0x8000)
10173 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10174 tempreg
, tempreg
, BFD_RELOC_LO16
);
10180 /* If we are going to add in a base register, and the
10181 target register and the base register are the same,
10182 then we are using AT as a temporary register. Since
10183 we want to load the constant into AT, we add our
10184 current AT (from the global offset table) and the
10185 register into the register now, and pretend we were
10186 not using a base register. */
10191 gas_assert (tempreg
== AT
);
10193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10198 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10199 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10203 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10208 /* This is needed because this instruction uses $gp, but
10209 the first instruction on the main stream does not. */
10210 macro_build (NULL
, "nop", "");
10213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10214 local_reloc_type
, mips_gp_register
);
10215 if (expr1
.X_add_number
>= -0x8000
10216 && expr1
.X_add_number
< 0x8000)
10219 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10220 tempreg
, tempreg
, BFD_RELOC_LO16
);
10221 /* FIXME: If add_number is 0, and there was no base
10222 register, the external symbol case ended with a load,
10223 so if the symbol turns out to not be external, and
10224 the next instruction uses tempreg, an unnecessary nop
10225 will be inserted. */
10231 /* We must add in the base register now, as in the
10232 external symbol case. */
10233 gas_assert (tempreg
== AT
);
10235 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10238 /* We set breg to 0 because we have arranged to add
10239 it in in both cases. */
10243 macro_build_lui (&expr1
, AT
);
10244 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10245 AT
, AT
, BFD_RELOC_LO16
);
10246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10247 tempreg
, tempreg
, AT
);
10252 else if (mips_big_got
&& HAVE_NEWABI
)
10254 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10255 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10256 int add_breg_early
= 0;
10258 /* This is the large GOT case. If this is a reference to an
10259 external symbol, and there is no constant, we want
10260 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10261 add $tempreg,$tempreg,$gp
10262 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10263 or for lca or if tempreg is PIC_CALL_REG
10264 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10265 add $tempreg,$tempreg,$gp
10266 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10268 If we have a small constant, and this is a reference to
10269 an external symbol, we want
10270 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10271 add $tempreg,$tempreg,$gp
10272 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10273 addi $tempreg,$tempreg,<constant>
10275 If we have a large constant, and this is a reference to
10276 an external symbol, we want
10277 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10278 addu $tempreg,$tempreg,$gp
10279 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10280 lui $at,<hiconstant>
10281 addi $at,$at,<loconstant>
10282 add $tempreg,$tempreg,$at
10284 If we have NewABI, and we know it's a local symbol, we want
10285 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10286 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10287 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10289 relax_start (offset_expr
.X_add_symbol
);
10291 expr1
.X_add_number
= offset_expr
.X_add_number
;
10292 offset_expr
.X_add_number
= 0;
10294 if (expr1
.X_add_number
== 0 && breg
== 0
10295 && (call
|| tempreg
== PIC_CALL_REG
))
10297 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10298 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10300 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10302 tempreg
, tempreg
, mips_gp_register
);
10303 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10304 tempreg
, lw_reloc_type
, tempreg
);
10306 if (expr1
.X_add_number
== 0)
10308 else if (expr1
.X_add_number
>= -0x8000
10309 && expr1
.X_add_number
< 0x8000)
10311 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10312 tempreg
, tempreg
, BFD_RELOC_LO16
);
10314 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10318 /* If we are going to add in a base register, and the
10319 target register and the base register are the same,
10320 then we are using AT as a temporary register. Since
10321 we want to load the constant into AT, we add our
10322 current AT (from the global offset table) and the
10323 register into the register now, and pretend we were
10324 not using a base register. */
10329 gas_assert (tempreg
== AT
);
10330 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10333 add_breg_early
= 1;
10336 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10342 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10345 offset_expr
.X_add_number
= expr1
.X_add_number
;
10346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10347 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10348 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10349 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10350 if (add_breg_early
)
10352 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10353 op
[0], tempreg
, breg
);
10363 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10367 gas_assert (!mips_opts
.micromips
);
10368 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10372 gas_assert (!mips_opts
.micromips
);
10373 macro_build (NULL
, "c2", "C", 0x02);
10377 gas_assert (!mips_opts
.micromips
);
10378 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10382 gas_assert (!mips_opts
.micromips
);
10383 macro_build (NULL
, "c2", "C", 3);
10387 gas_assert (!mips_opts
.micromips
);
10388 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10392 /* The j instruction may not be used in PIC code, since it
10393 requires an absolute address. We convert it to a b
10395 if (mips_pic
== NO_PIC
)
10396 macro_build (&offset_expr
, "j", "a");
10398 macro_build (&offset_expr
, "b", "p");
10401 /* The jal instructions must be handled as macros because when
10402 generating PIC code they expand to multi-instruction
10403 sequences. Normally they are simple instructions. */
10407 /* Fall through. */
10409 gas_assert (mips_opts
.micromips
);
10410 if (mips_opts
.insn32
)
10412 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10420 /* Fall through. */
10423 if (mips_pic
== NO_PIC
)
10425 s
= jals
? "jalrs" : "jalr";
10426 if (mips_opts
.micromips
10427 && !mips_opts
.insn32
10429 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10430 macro_build (NULL
, s
, "mj", op
[1]);
10432 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10436 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10437 && mips_cprestore_offset
>= 0);
10439 if (op
[1] != PIC_CALL_REG
)
10440 as_warn (_("MIPS PIC call to register other than $25"));
10442 s
= ((mips_opts
.micromips
10443 && !mips_opts
.insn32
10444 && (!mips_opts
.noreorder
|| cprestore
))
10445 ? "jalrs" : "jalr");
10446 if (mips_opts
.micromips
10447 && !mips_opts
.insn32
10449 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10450 macro_build (NULL
, s
, "mj", op
[1]);
10452 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10453 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10455 if (mips_cprestore_offset
< 0)
10456 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10459 if (!mips_frame_reg_valid
)
10461 as_warn (_("No .frame pseudo-op used in PIC code"));
10462 /* Quiet this warning. */
10463 mips_frame_reg_valid
= 1;
10465 if (!mips_cprestore_valid
)
10467 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10468 /* Quiet this warning. */
10469 mips_cprestore_valid
= 1;
10471 if (mips_opts
.noreorder
)
10472 macro_build (NULL
, "nop", "");
10473 expr1
.X_add_number
= mips_cprestore_offset
;
10474 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10477 HAVE_64BIT_ADDRESSES
);
10485 gas_assert (mips_opts
.micromips
);
10486 if (mips_opts
.insn32
)
10488 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10492 /* Fall through. */
10494 if (mips_pic
== NO_PIC
)
10495 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10496 else if (mips_pic
== SVR4_PIC
)
10498 /* If this is a reference to an external symbol, and we are
10499 using a small GOT, we want
10500 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10504 lw $gp,cprestore($sp)
10505 The cprestore value is set using the .cprestore
10506 pseudo-op. If we are using a big GOT, we want
10507 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10509 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10513 lw $gp,cprestore($sp)
10514 If the symbol is not external, we want
10515 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10517 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10520 lw $gp,cprestore($sp)
10522 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10523 sequences above, minus nops, unless the symbol is local,
10524 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10530 relax_start (offset_expr
.X_add_symbol
);
10531 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10532 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10535 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10536 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10542 relax_start (offset_expr
.X_add_symbol
);
10543 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10544 BFD_RELOC_MIPS_CALL_HI16
);
10545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10546 PIC_CALL_REG
, mips_gp_register
);
10547 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10548 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10551 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10552 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10554 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10555 PIC_CALL_REG
, PIC_CALL_REG
,
10556 BFD_RELOC_MIPS_GOT_OFST
);
10560 macro_build_jalr (&offset_expr
, 0);
10564 relax_start (offset_expr
.X_add_symbol
);
10567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10568 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10577 gpdelay
= reg_needs_delay (mips_gp_register
);
10578 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10579 BFD_RELOC_MIPS_CALL_HI16
);
10580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10581 PIC_CALL_REG
, mips_gp_register
);
10582 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10583 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10588 macro_build (NULL
, "nop", "");
10590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10591 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10594 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10595 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10597 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10599 if (mips_cprestore_offset
< 0)
10600 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10603 if (!mips_frame_reg_valid
)
10605 as_warn (_("No .frame pseudo-op used in PIC code"));
10606 /* Quiet this warning. */
10607 mips_frame_reg_valid
= 1;
10609 if (!mips_cprestore_valid
)
10611 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10612 /* Quiet this warning. */
10613 mips_cprestore_valid
= 1;
10615 if (mips_opts
.noreorder
)
10616 macro_build (NULL
, "nop", "");
10617 expr1
.X_add_number
= mips_cprestore_offset
;
10618 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10621 HAVE_64BIT_ADDRESSES
);
10625 else if (mips_pic
== VXWORKS_PIC
)
10626 as_bad (_("Non-PIC jump used in PIC library"));
10733 gas_assert (!mips_opts
.micromips
);
10736 /* Itbl support may require additional care here. */
10742 /* Itbl support may require additional care here. */
10748 offbits
= (mips_opts
.micromips
? 12 : 16);
10749 /* Itbl support may require additional care here. */
10753 gas_assert (!mips_opts
.micromips
);
10756 /* Itbl support may require additional care here. */
10762 offbits
= (mips_opts
.micromips
? 12 : 16);
10767 offbits
= (mips_opts
.micromips
? 12 : 16);
10772 /* Itbl support may require additional care here. */
10778 offbits
= (mips_opts
.micromips
? 12 : 16);
10779 /* Itbl support may require additional care here. */
10785 /* Itbl support may require additional care here. */
10791 /* Itbl support may require additional care here. */
10797 offbits
= (mips_opts
.micromips
? 12 : 16);
10802 offbits
= (mips_opts
.micromips
? 12 : 16);
10807 offbits
= (mips_opts
.micromips
? 12 : 16);
10812 offbits
= (mips_opts
.micromips
? 12 : 16);
10817 offbits
= (mips_opts
.micromips
? 12 : 16);
10820 gas_assert (mips_opts
.micromips
);
10827 gas_assert (mips_opts
.micromips
);
10834 gas_assert (mips_opts
.micromips
);
10840 gas_assert (mips_opts
.micromips
);
10847 /* We don't want to use $0 as tempreg. */
10848 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10851 tempreg
= op
[0] + lp
;
10867 gas_assert (!mips_opts
.micromips
);
10870 /* Itbl support may require additional care here. */
10876 /* Itbl support may require additional care here. */
10882 offbits
= (mips_opts
.micromips
? 12 : 16);
10883 /* Itbl support may require additional care here. */
10887 gas_assert (!mips_opts
.micromips
);
10890 /* Itbl support may require additional care here. */
10896 offbits
= (mips_opts
.micromips
? 12 : 16);
10901 offbits
= (mips_opts
.micromips
? 12 : 16);
10906 offbits
= (mips_opts
.micromips
? 12 : 16);
10911 offbits
= (mips_opts
.micromips
? 12 : 16);
10915 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10916 offbits
= (mips_opts
.micromips
? 12 : 16);
10925 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10926 offbits
= (mips_opts
.micromips
? 12 : 16);
10937 /* Itbl support may require additional care here. */
10942 offbits
= (mips_opts
.micromips
? 12 : 16);
10943 /* Itbl support may require additional care here. */
10949 /* Itbl support may require additional care here. */
10953 gas_assert (!mips_opts
.micromips
);
10956 /* Itbl support may require additional care here. */
10962 offbits
= (mips_opts
.micromips
? 12 : 16);
10967 offbits
= (mips_opts
.micromips
? 12 : 16);
10970 gas_assert (mips_opts
.micromips
);
10976 gas_assert (mips_opts
.micromips
);
10982 gas_assert (mips_opts
.micromips
);
10988 gas_assert (mips_opts
.micromips
);
10997 if (small_offset_p (0, align
, 16))
10999 /* The first case exists for M_LD_AB and M_SD_AB, which are
11000 macros for o32 but which should act like normal instructions
11003 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11004 offset_reloc
[1], offset_reloc
[2], breg
);
11005 else if (small_offset_p (0, align
, offbits
))
11008 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11010 macro_build (NULL
, s
, fmt
, op
[0],
11011 (int) offset_expr
.X_add_number
, breg
);
11017 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11018 tempreg
, breg
, -1, offset_reloc
[0],
11019 offset_reloc
[1], offset_reloc
[2]);
11021 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11023 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11031 if (offset_expr
.X_op
!= O_constant
11032 && offset_expr
.X_op
!= O_symbol
)
11034 as_bad (_("Expression too complex"));
11035 offset_expr
.X_op
= O_constant
;
11038 if (HAVE_32BIT_ADDRESSES
11039 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11043 sprintf_vma (value
, offset_expr
.X_add_number
);
11044 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11047 /* A constant expression in PIC code can be handled just as it
11048 is in non PIC code. */
11049 if (offset_expr
.X_op
== O_constant
)
11051 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11052 offbits
== 0 ? 16 : offbits
);
11053 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11055 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11058 tempreg
, tempreg
, breg
);
11061 if (offset_expr
.X_add_number
!= 0)
11062 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11063 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11064 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11066 else if (offbits
== 16)
11067 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11069 macro_build (NULL
, s
, fmt
, op
[0],
11070 (int) offset_expr
.X_add_number
, tempreg
);
11072 else if (offbits
!= 16)
11074 /* The offset field is too narrow to be used for a low-part
11075 relocation, so load the whole address into the auxillary
11077 load_address (tempreg
, &offset_expr
, &used_at
);
11079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11080 tempreg
, tempreg
, breg
);
11082 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11084 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11086 else if (mips_pic
== NO_PIC
)
11088 /* If this is a reference to a GP relative symbol, and there
11089 is no base register, we want
11090 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11091 Otherwise, if there is no base register, we want
11092 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11093 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11094 If we have a constant, we need two instructions anyhow,
11095 so we always use the latter form.
11097 If we have a base register, and this is a reference to a
11098 GP relative symbol, we want
11099 addu $tempreg,$breg,$gp
11100 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11102 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11103 addu $tempreg,$tempreg,$breg
11104 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11105 With a constant we always use the latter case.
11107 With 64bit address space and no base register and $at usable,
11109 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11110 lui $at,<sym> (BFD_RELOC_HI16_S)
11111 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11114 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11115 If we have a base register, we want
11116 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11117 lui $at,<sym> (BFD_RELOC_HI16_S)
11118 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11122 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11124 Without $at we can't generate the optimal path for superscalar
11125 processors here since this would require two temporary registers.
11126 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11127 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11129 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11131 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11132 If we have a base register, we want
11133 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11134 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11136 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11138 daddu $tempreg,$tempreg,$breg
11139 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11141 For GP relative symbols in 64bit address space we can use
11142 the same sequence as in 32bit address space. */
11143 if (HAVE_64BIT_SYMBOLS
)
11145 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11146 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11148 relax_start (offset_expr
.X_add_symbol
);
11151 macro_build (&offset_expr
, s
, fmt
, op
[0],
11152 BFD_RELOC_GPREL16
, mips_gp_register
);
11156 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11157 tempreg
, breg
, mips_gp_register
);
11158 macro_build (&offset_expr
, s
, fmt
, op
[0],
11159 BFD_RELOC_GPREL16
, tempreg
);
11164 if (used_at
== 0 && mips_opts
.at
)
11166 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11167 BFD_RELOC_MIPS_HIGHEST
);
11168 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11170 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11171 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11173 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11174 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11175 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11176 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11182 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11183 BFD_RELOC_MIPS_HIGHEST
);
11184 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11185 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11186 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11187 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11188 tempreg
, BFD_RELOC_HI16_S
);
11189 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11191 macro_build (NULL
, "daddu", "d,v,t",
11192 tempreg
, tempreg
, breg
);
11193 macro_build (&offset_expr
, s
, fmt
, op
[0],
11194 BFD_RELOC_LO16
, tempreg
);
11197 if (mips_relax
.sequence
)
11204 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11205 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11207 relax_start (offset_expr
.X_add_symbol
);
11208 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11212 macro_build_lui (&offset_expr
, tempreg
);
11213 macro_build (&offset_expr
, s
, fmt
, op
[0],
11214 BFD_RELOC_LO16
, tempreg
);
11215 if (mips_relax
.sequence
)
11220 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11221 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11223 relax_start (offset_expr
.X_add_symbol
);
11224 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11225 tempreg
, breg
, mips_gp_register
);
11226 macro_build (&offset_expr
, s
, fmt
, op
[0],
11227 BFD_RELOC_GPREL16
, tempreg
);
11230 macro_build_lui (&offset_expr
, tempreg
);
11231 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11232 tempreg
, tempreg
, breg
);
11233 macro_build (&offset_expr
, s
, fmt
, op
[0],
11234 BFD_RELOC_LO16
, tempreg
);
11235 if (mips_relax
.sequence
)
11239 else if (!mips_big_got
)
11241 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11243 /* If this is a reference to an external symbol, we want
11244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11246 <op> op[0],0($tempreg)
11248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11250 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11251 <op> op[0],0($tempreg)
11253 For NewABI, we want
11254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11255 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11257 If there is a base register, we add it to $tempreg before
11258 the <op>. If there is a constant, we stick it in the
11259 <op> instruction. We don't handle constants larger than
11260 16 bits, because we have no way to load the upper 16 bits
11261 (actually, we could handle them for the subset of cases
11262 in which we are not using $at). */
11263 gas_assert (offset_expr
.X_op
== O_symbol
);
11266 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11267 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11269 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11270 tempreg
, tempreg
, breg
);
11271 macro_build (&offset_expr
, s
, fmt
, op
[0],
11272 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11275 expr1
.X_add_number
= offset_expr
.X_add_number
;
11276 offset_expr
.X_add_number
= 0;
11277 if (expr1
.X_add_number
< -0x8000
11278 || expr1
.X_add_number
>= 0x8000)
11279 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11280 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11281 lw_reloc_type
, mips_gp_register
);
11283 relax_start (offset_expr
.X_add_symbol
);
11285 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11286 tempreg
, BFD_RELOC_LO16
);
11289 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11290 tempreg
, tempreg
, breg
);
11291 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11293 else if (mips_big_got
&& !HAVE_NEWABI
)
11297 /* If this is a reference to an external symbol, we want
11298 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11299 addu $tempreg,$tempreg,$gp
11300 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11301 <op> op[0],0($tempreg)
11303 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11305 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11306 <op> op[0],0($tempreg)
11307 If there is a base register, we add it to $tempreg before
11308 the <op>. If there is a constant, we stick it in the
11309 <op> instruction. We don't handle constants larger than
11310 16 bits, because we have no way to load the upper 16 bits
11311 (actually, we could handle them for the subset of cases
11312 in which we are not using $at). */
11313 gas_assert (offset_expr
.X_op
== O_symbol
);
11314 expr1
.X_add_number
= offset_expr
.X_add_number
;
11315 offset_expr
.X_add_number
= 0;
11316 if (expr1
.X_add_number
< -0x8000
11317 || expr1
.X_add_number
>= 0x8000)
11318 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11319 gpdelay
= reg_needs_delay (mips_gp_register
);
11320 relax_start (offset_expr
.X_add_symbol
);
11321 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11322 BFD_RELOC_MIPS_GOT_HI16
);
11323 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11325 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11326 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11329 macro_build (NULL
, "nop", "");
11330 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11331 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11333 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11334 tempreg
, BFD_RELOC_LO16
);
11338 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11339 tempreg
, tempreg
, breg
);
11340 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11342 else if (mips_big_got
&& HAVE_NEWABI
)
11344 /* If this is a reference to an external symbol, we want
11345 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11346 add $tempreg,$tempreg,$gp
11347 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11348 <op> op[0],<ofst>($tempreg)
11349 Otherwise, for local symbols, we want:
11350 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11351 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11352 gas_assert (offset_expr
.X_op
== O_symbol
);
11353 expr1
.X_add_number
= offset_expr
.X_add_number
;
11354 offset_expr
.X_add_number
= 0;
11355 if (expr1
.X_add_number
< -0x8000
11356 || expr1
.X_add_number
>= 0x8000)
11357 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11358 relax_start (offset_expr
.X_add_symbol
);
11359 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11360 BFD_RELOC_MIPS_GOT_HI16
);
11361 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11363 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11364 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11366 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11367 tempreg
, tempreg
, breg
);
11368 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11371 offset_expr
.X_add_number
= expr1
.X_add_number
;
11372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11373 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11376 tempreg
, tempreg
, breg
);
11377 macro_build (&offset_expr
, s
, fmt
, op
[0],
11378 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11387 gas_assert (mips_opts
.micromips
);
11388 gas_assert (mips_opts
.insn32
);
11389 start_noreorder ();
11390 macro_build (NULL
, "jr", "s", RA
);
11391 expr1
.X_add_number
= op
[0] << 2;
11392 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11397 gas_assert (mips_opts
.micromips
);
11398 gas_assert (mips_opts
.insn32
);
11399 macro_build (NULL
, "jr", "s", op
[0]);
11400 if (mips_opts
.noreorder
)
11401 macro_build (NULL
, "nop", "");
11406 load_register (op
[0], &imm_expr
, 0);
11410 load_register (op
[0], &imm_expr
, 1);
11414 if (imm_expr
.X_op
== O_constant
)
11417 load_register (AT
, &imm_expr
, 0);
11418 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11423 gas_assert (offset_expr
.X_op
== O_symbol
11424 && strcmp (segment_name (S_GET_SEGMENT
11425 (offset_expr
.X_add_symbol
)),
11427 && offset_expr
.X_add_number
== 0);
11428 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11429 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11434 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11435 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11436 order 32 bits of the value and the low order 32 bits are either
11437 zero or in OFFSET_EXPR. */
11438 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11440 if (HAVE_64BIT_GPRS
)
11441 load_register (op
[0], &imm_expr
, 1);
11446 if (target_big_endian
)
11458 load_register (hreg
, &imm_expr
, 0);
11461 if (offset_expr
.X_op
== O_absent
)
11462 move_register (lreg
, 0);
11465 gas_assert (offset_expr
.X_op
== O_constant
);
11466 load_register (lreg
, &offset_expr
, 0);
11473 /* We know that sym is in the .rdata section. First we get the
11474 upper 16 bits of the address. */
11475 if (mips_pic
== NO_PIC
)
11477 macro_build_lui (&offset_expr
, AT
);
11482 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11483 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11487 /* Now we load the register(s). */
11488 if (HAVE_64BIT_GPRS
)
11491 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11492 BFD_RELOC_LO16
, AT
);
11497 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11498 BFD_RELOC_LO16
, AT
);
11501 /* FIXME: How in the world do we deal with the possible
11503 offset_expr
.X_add_number
+= 4;
11504 macro_build (&offset_expr
, "lw", "t,o(b)",
11505 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11511 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11512 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11513 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11514 the value and the low order 32 bits are either zero or in
11516 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11519 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11520 if (HAVE_64BIT_FPRS
)
11522 gas_assert (HAVE_64BIT_GPRS
);
11523 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11527 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11528 if (offset_expr
.X_op
== O_absent
)
11529 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11532 gas_assert (offset_expr
.X_op
== O_constant
);
11533 load_register (AT
, &offset_expr
, 0);
11534 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11540 gas_assert (offset_expr
.X_op
== O_symbol
11541 && offset_expr
.X_add_number
== 0);
11542 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11543 if (strcmp (s
, ".lit8") == 0)
11545 op
[2] = mips_gp_register
;
11546 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11547 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11548 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11552 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11554 if (mips_pic
!= NO_PIC
)
11555 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11556 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11559 /* FIXME: This won't work for a 64 bit address. */
11560 macro_build_lui (&offset_expr
, AT
);
11564 offset_reloc
[0] = BFD_RELOC_LO16
;
11565 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11566 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11573 * The MIPS assembler seems to check for X_add_number not
11574 * being double aligned and generating:
11575 * lui at,%hi(foo+1)
11577 * addiu at,at,%lo(foo+1)
11580 * But, the resulting address is the same after relocation so why
11581 * generate the extra instruction?
11583 /* Itbl support may require additional care here. */
11586 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11595 gas_assert (!mips_opts
.micromips
);
11596 /* Itbl support may require additional care here. */
11599 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11619 if (HAVE_64BIT_GPRS
)
11629 if (HAVE_64BIT_GPRS
)
11637 /* Even on a big endian machine $fn comes before $fn+1. We have
11638 to adjust when loading from memory. We set coproc if we must
11639 load $fn+1 first. */
11640 /* Itbl support may require additional care here. */
11641 if (!target_big_endian
)
11645 if (small_offset_p (0, align
, 16))
11648 if (!small_offset_p (4, align
, 16))
11650 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11651 -1, offset_reloc
[0], offset_reloc
[1],
11653 expr1
.X_add_number
= 0;
11657 offset_reloc
[0] = BFD_RELOC_LO16
;
11658 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11659 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11661 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11663 ep
->X_add_number
+= 4;
11664 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11665 offset_reloc
[1], offset_reloc
[2], breg
);
11666 ep
->X_add_number
-= 4;
11667 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11668 offset_reloc
[1], offset_reloc
[2], breg
);
11672 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11673 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11675 ep
->X_add_number
+= 4;
11676 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11677 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11683 if (offset_expr
.X_op
!= O_symbol
11684 && offset_expr
.X_op
!= O_constant
)
11686 as_bad (_("Expression too complex"));
11687 offset_expr
.X_op
= O_constant
;
11690 if (HAVE_32BIT_ADDRESSES
11691 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11695 sprintf_vma (value
, offset_expr
.X_add_number
);
11696 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11699 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11701 /* If this is a reference to a GP relative symbol, we want
11702 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11703 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11704 If we have a base register, we use this
11706 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11707 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11708 If this is not a GP relative symbol, we want
11709 lui $at,<sym> (BFD_RELOC_HI16_S)
11710 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11711 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11712 If there is a base register, we add it to $at after the
11713 lui instruction. If there is a constant, we always use
11715 if (offset_expr
.X_op
== O_symbol
11716 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11717 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11719 relax_start (offset_expr
.X_add_symbol
);
11722 tempreg
= mips_gp_register
;
11726 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11727 AT
, breg
, mips_gp_register
);
11732 /* Itbl support may require additional care here. */
11733 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11734 BFD_RELOC_GPREL16
, tempreg
);
11735 offset_expr
.X_add_number
+= 4;
11737 /* Set mips_optimize to 2 to avoid inserting an
11739 hold_mips_optimize
= mips_optimize
;
11741 /* Itbl support may require additional care here. */
11742 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11743 BFD_RELOC_GPREL16
, tempreg
);
11744 mips_optimize
= hold_mips_optimize
;
11748 offset_expr
.X_add_number
-= 4;
11751 if (offset_high_part (offset_expr
.X_add_number
, 16)
11752 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11754 load_address (AT
, &offset_expr
, &used_at
);
11755 offset_expr
.X_op
= O_constant
;
11756 offset_expr
.X_add_number
= 0;
11759 macro_build_lui (&offset_expr
, AT
);
11761 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11762 /* Itbl support may require additional care here. */
11763 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11764 BFD_RELOC_LO16
, AT
);
11765 /* FIXME: How do we handle overflow here? */
11766 offset_expr
.X_add_number
+= 4;
11767 /* Itbl support may require additional care here. */
11768 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11769 BFD_RELOC_LO16
, AT
);
11770 if (mips_relax
.sequence
)
11773 else if (!mips_big_got
)
11775 /* If this is a reference to an external symbol, we want
11776 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11779 <op> op[0]+1,4($at)
11781 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11783 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11784 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11785 If there is a base register we add it to $at before the
11786 lwc1 instructions. If there is a constant we include it
11787 in the lwc1 instructions. */
11789 expr1
.X_add_number
= offset_expr
.X_add_number
;
11790 if (expr1
.X_add_number
< -0x8000
11791 || expr1
.X_add_number
>= 0x8000 - 4)
11792 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11793 load_got_offset (AT
, &offset_expr
);
11796 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11798 /* Set mips_optimize to 2 to avoid inserting an undesired
11800 hold_mips_optimize
= mips_optimize
;
11803 /* Itbl support may require additional care here. */
11804 relax_start (offset_expr
.X_add_symbol
);
11805 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11806 BFD_RELOC_LO16
, AT
);
11807 expr1
.X_add_number
+= 4;
11808 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11809 BFD_RELOC_LO16
, AT
);
11811 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11812 BFD_RELOC_LO16
, AT
);
11813 offset_expr
.X_add_number
+= 4;
11814 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11815 BFD_RELOC_LO16
, AT
);
11818 mips_optimize
= hold_mips_optimize
;
11820 else if (mips_big_got
)
11824 /* If this is a reference to an external symbol, we want
11825 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11827 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11830 <op> op[0]+1,4($at)
11832 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11834 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11835 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11836 If there is a base register we add it to $at before the
11837 lwc1 instructions. If there is a constant we include it
11838 in the lwc1 instructions. */
11840 expr1
.X_add_number
= offset_expr
.X_add_number
;
11841 offset_expr
.X_add_number
= 0;
11842 if (expr1
.X_add_number
< -0x8000
11843 || expr1
.X_add_number
>= 0x8000 - 4)
11844 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11845 gpdelay
= reg_needs_delay (mips_gp_register
);
11846 relax_start (offset_expr
.X_add_symbol
);
11847 macro_build (&offset_expr
, "lui", LUI_FMT
,
11848 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11849 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11850 AT
, AT
, mips_gp_register
);
11851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11852 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11856 /* Itbl support may require additional care here. */
11857 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11858 BFD_RELOC_LO16
, AT
);
11859 expr1
.X_add_number
+= 4;
11861 /* Set mips_optimize to 2 to avoid inserting an undesired
11863 hold_mips_optimize
= mips_optimize
;
11865 /* Itbl support may require additional care here. */
11866 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11867 BFD_RELOC_LO16
, AT
);
11868 mips_optimize
= hold_mips_optimize
;
11869 expr1
.X_add_number
-= 4;
11872 offset_expr
.X_add_number
= expr1
.X_add_number
;
11874 macro_build (NULL
, "nop", "");
11875 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11876 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11879 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11880 /* Itbl support may require additional care here. */
11881 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11882 BFD_RELOC_LO16
, AT
);
11883 offset_expr
.X_add_number
+= 4;
11885 /* Set mips_optimize to 2 to avoid inserting an undesired
11887 hold_mips_optimize
= mips_optimize
;
11889 /* Itbl support may require additional care here. */
11890 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11891 BFD_RELOC_LO16
, AT
);
11892 mips_optimize
= hold_mips_optimize
;
11911 /* New code added to support COPZ instructions.
11912 This code builds table entries out of the macros in mip_opcodes.
11913 R4000 uses interlocks to handle coproc delays.
11914 Other chips (like the R3000) require nops to be inserted for delays.
11916 FIXME: Currently, we require that the user handle delays.
11917 In order to fill delay slots for non-interlocked chips,
11918 we must have a way to specify delays based on the coprocessor.
11919 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11920 What are the side-effects of the cop instruction?
11921 What cache support might we have and what are its effects?
11922 Both coprocessor & memory require delays. how long???
11923 What registers are read/set/modified?
11925 If an itbl is provided to interpret cop instructions,
11926 this knowledge can be encoded in the itbl spec. */
11940 gas_assert (!mips_opts
.micromips
);
11941 /* For now we just do C (same as Cz). The parameter will be
11942 stored in insn_opcode by mips_ip. */
11943 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11947 move_register (op
[0], op
[1]);
11951 gas_assert (mips_opts
.micromips
);
11952 gas_assert (mips_opts
.insn32
);
11953 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11954 micromips_to_32_reg_m_map
[op
[1]]);
11955 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11956 micromips_to_32_reg_n_map
[op
[2]]);
11962 if (mips_opts
.arch
== CPU_R5900
)
11963 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
11967 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
11968 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11975 /* The MIPS assembler some times generates shifts and adds. I'm
11976 not trying to be that fancy. GCC should do this for us
11979 load_register (AT
, &imm_expr
, dbl
);
11980 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
11981 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11994 start_noreorder ();
11997 load_register (AT
, &imm_expr
, dbl
);
11998 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
11999 op
[1], imm
? AT
: op
[2]);
12000 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12001 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12002 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12004 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12007 if (mips_opts
.micromips
)
12008 micromips_label_expr (&label_expr
);
12010 label_expr
.X_add_number
= 8;
12011 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12012 macro_build (NULL
, "nop", "");
12013 macro_build (NULL
, "break", BRK_FMT
, 6);
12014 if (mips_opts
.micromips
)
12015 micromips_add_label ();
12018 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12031 start_noreorder ();
12034 load_register (AT
, &imm_expr
, dbl
);
12035 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12036 op
[1], imm
? AT
: op
[2]);
12037 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12038 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12040 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12043 if (mips_opts
.micromips
)
12044 micromips_label_expr (&label_expr
);
12046 label_expr
.X_add_number
= 8;
12047 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12048 macro_build (NULL
, "nop", "");
12049 macro_build (NULL
, "break", BRK_FMT
, 6);
12050 if (mips_opts
.micromips
)
12051 micromips_add_label ();
12057 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12059 if (op
[0] == op
[1])
12066 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12067 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12071 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12072 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12073 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12074 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12078 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12080 if (op
[0] == op
[1])
12087 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12088 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12092 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12093 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12094 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12095 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12104 if (imm_expr
.X_op
!= O_constant
)
12105 as_bad (_("Improper rotate count"));
12106 rot
= imm_expr
.X_add_number
& 0x3f;
12107 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12109 rot
= (64 - rot
) & 0x3f;
12111 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12113 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12118 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12121 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12122 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12125 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12126 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12127 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12135 if (imm_expr
.X_op
!= O_constant
)
12136 as_bad (_("Improper rotate count"));
12137 rot
= imm_expr
.X_add_number
& 0x1f;
12138 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12140 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12141 (32 - rot
) & 0x1f);
12146 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12150 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12151 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12152 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12157 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12159 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12163 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12164 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12165 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12166 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12170 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12172 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12176 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12177 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12178 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12179 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12188 if (imm_expr
.X_op
!= O_constant
)
12189 as_bad (_("Improper rotate count"));
12190 rot
= imm_expr
.X_add_number
& 0x3f;
12191 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12194 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12196 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12201 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12204 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12205 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12208 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12209 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12210 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12218 if (imm_expr
.X_op
!= O_constant
)
12219 as_bad (_("Improper rotate count"));
12220 rot
= imm_expr
.X_add_number
& 0x1f;
12221 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12223 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12228 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12232 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12233 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12234 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12240 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12241 else if (op
[2] == 0)
12242 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12245 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12246 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12251 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12253 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12258 as_warn (_("Instruction %s: result is always false"),
12259 ip
->insn_mo
->name
);
12260 move_register (op
[0], 0);
12263 if (CPU_HAS_SEQ (mips_opts
.arch
)
12264 && -512 <= imm_expr
.X_add_number
12265 && imm_expr
.X_add_number
< 512)
12267 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12268 (int) imm_expr
.X_add_number
);
12271 if (imm_expr
.X_op
== O_constant
12272 && imm_expr
.X_add_number
>= 0
12273 && imm_expr
.X_add_number
< 0x10000)
12274 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12275 else if (imm_expr
.X_op
== O_constant
12276 && imm_expr
.X_add_number
> -0x8000
12277 && imm_expr
.X_add_number
< 0)
12279 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12280 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12281 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12283 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12286 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12287 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12292 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12293 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12296 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12299 case M_SGE
: /* X >= Y <==> not (X < Y) */
12305 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12306 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12309 case M_SGE_I
: /* X >= I <==> not (X < I) */
12311 if (imm_expr
.X_op
== O_constant
12312 && imm_expr
.X_add_number
>= -0x8000
12313 && imm_expr
.X_add_number
< 0x8000)
12314 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12315 op
[0], op
[1], BFD_RELOC_LO16
);
12318 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12319 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12323 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12326 case M_SGT
: /* X > Y <==> Y < X */
12332 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12335 case M_SGT_I
: /* X > I <==> I < X */
12342 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12343 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12346 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12352 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12353 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12356 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12363 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12364 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12365 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12369 if (imm_expr
.X_op
== O_constant
12370 && imm_expr
.X_add_number
>= -0x8000
12371 && imm_expr
.X_add_number
< 0x8000)
12373 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12378 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12379 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12383 if (imm_expr
.X_op
== O_constant
12384 && imm_expr
.X_add_number
>= -0x8000
12385 && imm_expr
.X_add_number
< 0x8000)
12387 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12392 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12393 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12398 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12399 else if (op
[2] == 0)
12400 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12403 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12404 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12409 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12411 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12416 as_warn (_("Instruction %s: result is always true"),
12417 ip
->insn_mo
->name
);
12418 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12419 op
[0], 0, BFD_RELOC_LO16
);
12422 if (CPU_HAS_SEQ (mips_opts
.arch
)
12423 && -512 <= imm_expr
.X_add_number
12424 && imm_expr
.X_add_number
< 512)
12426 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12427 (int) imm_expr
.X_add_number
);
12430 if (imm_expr
.X_op
== O_constant
12431 && imm_expr
.X_add_number
>= 0
12432 && imm_expr
.X_add_number
< 0x10000)
12434 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12437 else if (imm_expr
.X_op
== O_constant
12438 && imm_expr
.X_add_number
> -0x8000
12439 && imm_expr
.X_add_number
< 0)
12441 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12442 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12443 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12445 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12448 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12449 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12454 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12455 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12458 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12473 if (!mips_opts
.micromips
)
12475 if (imm_expr
.X_op
== O_constant
12476 && imm_expr
.X_add_number
> -0x200
12477 && imm_expr
.X_add_number
<= 0x200)
12479 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], -imm_expr
.X_add_number
);
12488 if (imm_expr
.X_op
== O_constant
12489 && imm_expr
.X_add_number
> -0x8000
12490 && imm_expr
.X_add_number
<= 0x8000)
12492 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12493 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12498 load_register (AT
, &imm_expr
, dbl
);
12499 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12521 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12522 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12527 gas_assert (!mips_opts
.micromips
);
12528 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12532 * Is the double cfc1 instruction a bug in the mips assembler;
12533 * or is there a reason for it?
12535 start_noreorder ();
12536 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12537 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12538 macro_build (NULL
, "nop", "");
12539 expr1
.X_add_number
= 3;
12540 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12541 expr1
.X_add_number
= 2;
12542 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12543 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12544 macro_build (NULL
, "nop", "");
12545 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12547 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12548 macro_build (NULL
, "nop", "");
12565 offbits
= (mips_opts
.micromips
? 12 : 16);
12571 offbits
= (mips_opts
.micromips
? 12 : 16);
12583 offbits
= (mips_opts
.micromips
? 12 : 16);
12590 offbits
= (mips_opts
.micromips
? 12 : 16);
12596 large_offset
= !small_offset_p (off
, align
, offbits
);
12598 expr1
.X_add_number
= 0;
12603 if (small_offset_p (0, align
, 16))
12604 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12605 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12608 load_address (tempreg
, ep
, &used_at
);
12610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12611 tempreg
, tempreg
, breg
);
12613 offset_reloc
[0] = BFD_RELOC_LO16
;
12614 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12615 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12620 else if (!ust
&& op
[0] == breg
)
12631 if (!target_big_endian
)
12632 ep
->X_add_number
+= off
;
12634 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12636 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12637 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12639 if (!target_big_endian
)
12640 ep
->X_add_number
-= off
;
12642 ep
->X_add_number
+= off
;
12644 macro_build (NULL
, s2
, "t,~(b)",
12645 tempreg
, (int) ep
->X_add_number
, breg
);
12647 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12648 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12650 /* If necessary, move the result in tempreg to the final destination. */
12651 if (!ust
&& op
[0] != tempreg
)
12653 /* Protect second load's delay slot. */
12655 move_register (op
[0], tempreg
);
12661 if (target_big_endian
== ust
)
12662 ep
->X_add_number
+= off
;
12663 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12664 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12665 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12667 /* For halfword transfers we need a temporary register to shuffle
12668 bytes. Unfortunately for M_USH_A we have none available before
12669 the next store as AT holds the base address. We deal with this
12670 case by clobbering TREG and then restoring it as with ULH. */
12671 tempreg
= ust
== large_offset
? op
[0] : AT
;
12673 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12675 if (target_big_endian
== ust
)
12676 ep
->X_add_number
-= off
;
12678 ep
->X_add_number
+= off
;
12679 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12680 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12682 /* For M_USH_A re-retrieve the LSB. */
12683 if (ust
&& large_offset
)
12685 if (target_big_endian
)
12686 ep
->X_add_number
+= off
;
12688 ep
->X_add_number
-= off
;
12689 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12690 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12692 /* For ULH and M_USH_A OR the LSB in. */
12693 if (!ust
|| large_offset
)
12695 tempreg
= !large_offset
? AT
: op
[0];
12696 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12697 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12702 /* FIXME: Check if this is one of the itbl macros, since they
12703 are added dynamically. */
12704 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
12707 if (!mips_opts
.at
&& used_at
)
12708 as_bad (_("Macro used $at after \".set noat\""));
12711 /* Implement macros in mips16 mode. */
12714 mips16_macro (struct mips_cl_insn
*ip
)
12716 const struct mips_operand_array
*operands
;
12721 const char *s
, *s2
, *s3
;
12722 unsigned int op
[MAX_OPERANDS
];
12725 mask
= ip
->insn_mo
->mask
;
12727 operands
= insn_operands (ip
);
12728 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12729 if (operands
->operand
[i
])
12730 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12734 expr1
.X_op
= O_constant
;
12735 expr1
.X_op_symbol
= NULL
;
12736 expr1
.X_add_symbol
= NULL
;
12737 expr1
.X_add_number
= 1;
12756 start_noreorder ();
12757 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12758 expr1
.X_add_number
= 2;
12759 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12760 macro_build (NULL
, "break", "6", 7);
12762 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12763 since that causes an overflow. We should do that as well,
12764 but I don't see how to do the comparisons without a temporary
12767 macro_build (NULL
, s
, "x", op
[0]);
12786 start_noreorder ();
12787 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12788 expr1
.X_add_number
= 2;
12789 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12790 macro_build (NULL
, "break", "6", 7);
12792 macro_build (NULL
, s2
, "x", op
[0]);
12798 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12799 macro_build (NULL
, "mflo", "x", op
[0]);
12807 if (imm_expr
.X_op
!= O_constant
)
12808 as_bad (_("Unsupported large constant"));
12809 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12810 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12814 if (imm_expr
.X_op
!= O_constant
)
12815 as_bad (_("Unsupported large constant"));
12816 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12817 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12821 if (imm_expr
.X_op
!= O_constant
)
12822 as_bad (_("Unsupported large constant"));
12823 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12824 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12846 goto do_reverse_branch
;
12850 goto do_reverse_branch
;
12862 goto do_reverse_branch
;
12873 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12874 macro_build (&offset_expr
, s2
, "p");
12901 goto do_addone_branch_i
;
12906 goto do_addone_branch_i
;
12921 goto do_addone_branch_i
;
12927 do_addone_branch_i
:
12928 if (imm_expr
.X_op
!= O_constant
)
12929 as_bad (_("Unsupported large constant"));
12930 ++imm_expr
.X_add_number
;
12933 macro_build (&imm_expr
, s
, s3
, op
[0]);
12934 macro_build (&offset_expr
, s2
, "p");
12938 expr1
.X_add_number
= 0;
12939 macro_build (&expr1
, "slti", "x,8", op
[1]);
12940 if (op
[0] != op
[1])
12941 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12942 expr1
.X_add_number
= 2;
12943 macro_build (&expr1
, "bteqz", "p");
12944 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12949 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12950 opcode bits in *OPCODE_EXTRA. */
12952 static struct mips_opcode
*
12953 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12954 ssize_t length
, unsigned int *opcode_extra
)
12956 char *name
, *dot
, *p
;
12957 unsigned int mask
, suffix
;
12959 struct mips_opcode
*insn
;
12961 /* Make a copy of the instruction so that we can fiddle with it. */
12962 name
= alloca (length
+ 1);
12963 memcpy (name
, start
, length
);
12964 name
[length
] = '\0';
12966 /* Look up the instruction as-is. */
12967 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12971 dot
= strchr (name
, '.');
12974 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12975 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12976 if (*p
== 0 && mask
!= 0)
12979 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12981 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
12983 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
12989 if (mips_opts
.micromips
)
12991 /* See if there's an instruction size override suffix,
12992 either `16' or `32', at the end of the mnemonic proper,
12993 that defines the operation, i.e. before the first `.'
12994 character if any. Strip it and retry. */
12995 opend
= dot
!= NULL
? dot
- name
: length
;
12996 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12998 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13004 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13005 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13008 forced_insn_length
= suffix
;
13017 /* Assemble an instruction into its binary format. If the instruction
13018 is a macro, set imm_expr, imm2_expr and offset_expr to the values
13019 associated with "I", "+I" and "A" operands respectively. Otherwise
13020 store the value of the relocatable field (if any) in offset_expr.
13021 In both cases set offset_reloc to the relocation operators applied
13025 mips_ip (char *str
, struct mips_cl_insn
*ip
)
13027 bfd_boolean wrong_delay_slot_insns
= FALSE
;
13028 bfd_boolean need_delay_slot_ok
= TRUE
;
13029 struct mips_opcode
*firstinsn
= NULL
;
13030 const struct mips_opcode
*past
;
13031 struct hash_control
*hash
;
13032 struct mips_opcode
*first
, *insn
;
13035 struct mips_operand_token
*tokens
;
13036 unsigned int opcode_extra
;
13038 if (mips_opts
.micromips
)
13040 hash
= micromips_op_hash
;
13041 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13046 past
= &mips_opcodes
[NUMOPCODES
];
13048 forced_insn_length
= 0;
13052 /* We first try to match an instruction up to a space or to the end. */
13053 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13056 first
= insn
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13059 set_insn_error (0, _("Unrecognized opcode"));
13062 /* When no opcode suffix is specified, assume ".xyzw". */
13063 if ((insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
13064 opcode_extra
= 0xf << mips_vu0_channel_mask
.lsb
;
13066 if (strcmp (insn
->name
, "li.s") == 0)
13068 else if (strcmp (insn
->name
, "li.d") == 0)
13072 tokens
= mips_parse_arguments (str
+ end
, format
);
13076 /* For microMIPS instructions placed in a fixed-length branch delay slot
13077 we make up to two passes over the relevant fragment of the opcode
13078 table. First we try instructions that meet the delay slot's length
13079 requirement. If none matched, then we retry with the remaining ones
13080 and if one matches, then we use it and then issue an appropriate
13081 warning later on. */
13084 bfd_boolean delay_slot_ok
;
13085 bfd_boolean size_ok
;
13087 bfd_boolean more_alts
;
13089 gas_assert (strcmp (insn
->name
, first
->name
) == 0);
13091 ok
= is_opcode_valid (insn
);
13092 size_ok
= is_size_valid (insn
);
13093 delay_slot_ok
= is_delay_slot_valid (insn
);
13094 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
13097 wrong_delay_slot_insns
= TRUE
;
13099 more_alts
= (insn
+ 1 < past
13100 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
13101 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
13108 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13110 gas_assert (firstinsn
);
13111 need_delay_slot_ok
= FALSE
;
13119 (0, _("Opcode not supported on this processor: %s (%s)"),
13120 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13121 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13122 else if (mips_opts
.insn32
)
13124 (0, _("Opcode not supported in the `insn32' mode"));
13127 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
13128 8 * forced_insn_length
);
13132 if (match_insn (ip
, insn
, tokens
, opcode_extra
, more_alts
,
13133 more_alts
|| (wrong_delay_slot_insns
13134 && need_delay_slot_ok
)))
13137 /* Args don't match. */
13138 set_insn_error (0, _("Illegal operands"));
13144 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13146 gas_assert (firstinsn
);
13147 need_delay_slot_ok
= FALSE
;
13154 obstack_free (&mips_operand_tokens
, tokens
);
13157 /* As for mips_ip, but used when assembling MIPS16 code.
13158 Also set forced_insn_length to the resulting instruction size in
13159 bytes if the user explicitly requested a small or extended instruction. */
13162 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13165 struct mips_opcode
*insn
;
13166 struct mips_operand_token
*tokens
;
13168 forced_insn_length
= 0;
13170 for (s
= str
; ISLOWER (*s
); ++s
)
13182 if (s
[1] == 't' && s
[2] == ' ')
13185 forced_insn_length
= 2;
13189 else if (s
[1] == 'e' && s
[2] == ' ')
13192 forced_insn_length
= 4;
13196 /* Fall through. */
13198 set_insn_error (0, _("Unrecognized opcode"));
13202 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13203 forced_insn_length
= 2;
13205 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13207 set_insn_error (0, _("Unrecognized opcode"));
13211 tokens
= mips_parse_arguments (s
, 0);
13218 bfd_boolean more_alts
;
13220 gas_assert (strcmp (insn
->name
, str
) == 0);
13222 ok
= is_opcode_valid_16 (insn
);
13223 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13224 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
13235 (0, _("Opcode not supported on this processor: %s (%s)"),
13236 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13237 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13242 if (match_mips16_insn (ip
, insn
, tokens
, more_alts
))
13245 /* Args don't match. */
13246 set_insn_error (0, _("Illegal operands"));
13254 obstack_free (&mips_operand_tokens
, tokens
);
13257 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13258 NBITS is the number of significant bits in VAL. */
13260 static unsigned long
13261 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13266 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13269 else if (nbits
== 15)
13271 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13276 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13279 return (extval
<< 16) | val
;
13282 /* Like decode_mips16_operand, but require the operand to be defined and
13283 require it to be an integer. */
13285 static const struct mips_int_operand
*
13286 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13288 const struct mips_operand
*operand
;
13290 operand
= decode_mips16_operand (type
, extended_p
);
13291 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13293 return (const struct mips_int_operand
*) operand
;
13296 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13299 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13300 bfd_reloc_code_real_type reloc
, offsetT sval
)
13302 int min_val
, max_val
;
13304 min_val
= mips_int_operand_min (operand
);
13305 max_val
= mips_int_operand_max (operand
);
13306 if (reloc
!= BFD_RELOC_UNUSED
)
13309 sval
= SEXT_16BIT (sval
);
13314 return (sval
>= min_val
13316 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13319 /* Install immediate value VAL into MIPS16 instruction *INSN,
13320 extending it if necessary. The instruction in *INSN may
13321 already be extended.
13323 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13324 if none. In the former case, VAL is a 16-bit number with no
13325 defined signedness.
13327 TYPE is the type of the immediate field. USER_INSN_LENGTH
13328 is the length that the user requested, or 0 if none. */
13331 mips16_immed (char *file
, unsigned int line
, int type
,
13332 bfd_reloc_code_real_type reloc
, offsetT val
,
13333 unsigned int user_insn_length
, unsigned long *insn
)
13335 const struct mips_int_operand
*operand
;
13336 unsigned int uval
, length
;
13338 operand
= mips16_immed_operand (type
, FALSE
);
13339 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13341 /* We need an extended instruction. */
13342 if (user_insn_length
== 2)
13343 as_bad_where (file
, line
, _("invalid unextended operand value"));
13345 *insn
|= MIPS16_EXTEND
;
13347 else if (user_insn_length
== 4)
13349 /* The operand doesn't force an unextended instruction to be extended.
13350 Warn if the user wanted an extended instruction anyway. */
13351 *insn
|= MIPS16_EXTEND
;
13352 as_warn_where (file
, line
,
13353 _("extended operand requested but not required"));
13356 length
= mips16_opcode_length (*insn
);
13359 operand
= mips16_immed_operand (type
, TRUE
);
13360 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13361 as_bad_where (file
, line
,
13362 _("operand value out of range for instruction"));
13364 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13366 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13368 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13371 struct percent_op_match
13374 bfd_reloc_code_real_type reloc
;
13377 static const struct percent_op_match mips_percent_op
[] =
13379 {"%lo", BFD_RELOC_LO16
},
13380 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13381 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13382 {"%call16", BFD_RELOC_MIPS_CALL16
},
13383 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13384 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13385 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13386 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13387 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13388 {"%got", BFD_RELOC_MIPS_GOT16
},
13389 {"%gp_rel", BFD_RELOC_GPREL16
},
13390 {"%half", BFD_RELOC_16
},
13391 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13392 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13393 {"%neg", BFD_RELOC_MIPS_SUB
},
13394 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13395 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13396 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13397 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13398 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13399 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13400 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13401 {"%hi", BFD_RELOC_HI16_S
}
13404 static const struct percent_op_match mips16_percent_op
[] =
13406 {"%lo", BFD_RELOC_MIPS16_LO16
},
13407 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13408 {"%got", BFD_RELOC_MIPS16_GOT16
},
13409 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13410 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13411 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13412 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13413 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13414 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13415 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13416 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13417 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13421 /* Return true if *STR points to a relocation operator. When returning true,
13422 move *STR over the operator and store its relocation code in *RELOC.
13423 Leave both *STR and *RELOC alone when returning false. */
13426 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13428 const struct percent_op_match
*percent_op
;
13431 if (mips_opts
.mips16
)
13433 percent_op
= mips16_percent_op
;
13434 limit
= ARRAY_SIZE (mips16_percent_op
);
13438 percent_op
= mips_percent_op
;
13439 limit
= ARRAY_SIZE (mips_percent_op
);
13442 for (i
= 0; i
< limit
; i
++)
13443 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13445 int len
= strlen (percent_op
[i
].str
);
13447 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13450 *str
+= strlen (percent_op
[i
].str
);
13451 *reloc
= percent_op
[i
].reloc
;
13453 /* Check whether the output BFD supports this relocation.
13454 If not, issue an error and fall back on something safe. */
13455 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13457 as_bad (_("relocation %s isn't supported by the current ABI"),
13458 percent_op
[i
].str
);
13459 *reloc
= BFD_RELOC_UNUSED
;
13467 /* Parse string STR as a 16-bit relocatable operand. Store the
13468 expression in *EP and the relocations in the array starting
13469 at RELOC. Return the number of relocation operators used.
13471 On exit, EXPR_END points to the first character after the expression. */
13474 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13477 bfd_reloc_code_real_type reversed_reloc
[3];
13478 size_t reloc_index
, i
;
13479 int crux_depth
, str_depth
;
13482 /* Search for the start of the main expression, recoding relocations
13483 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13484 of the main expression and with CRUX_DEPTH containing the number
13485 of open brackets at that point. */
13492 crux_depth
= str_depth
;
13494 /* Skip over whitespace and brackets, keeping count of the number
13496 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13501 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13502 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13504 my_getExpression (ep
, crux
);
13507 /* Match every open bracket. */
13508 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13512 if (crux_depth
> 0)
13513 as_bad (_("unclosed '('"));
13517 if (reloc_index
!= 0)
13519 prev_reloc_op_frag
= frag_now
;
13520 for (i
= 0; i
< reloc_index
; i
++)
13521 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13524 return reloc_index
;
13528 my_getExpression (expressionS
*ep
, char *str
)
13532 save_in
= input_line_pointer
;
13533 input_line_pointer
= str
;
13535 expr_end
= input_line_pointer
;
13536 input_line_pointer
= save_in
;
13540 md_atof (int type
, char *litP
, int *sizeP
)
13542 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13546 md_number_to_chars (char *buf
, valueT val
, int n
)
13548 if (target_big_endian
)
13549 number_to_chars_bigendian (buf
, val
, n
);
13551 number_to_chars_littleendian (buf
, val
, n
);
13554 static int support_64bit_objects(void)
13556 const char **list
, **l
;
13559 list
= bfd_target_list ();
13560 for (l
= list
; *l
!= NULL
; l
++)
13561 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13562 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13564 yes
= (*l
!= NULL
);
13569 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13570 NEW_VALUE. Warn if another value was already specified. Note:
13571 we have to defer parsing the -march and -mtune arguments in order
13572 to handle 'from-abi' correctly, since the ABI might be specified
13573 in a later argument. */
13576 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13578 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13579 as_warn (_("A different %s was already specified, is now %s"),
13580 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13583 *string_ptr
= new_value
;
13587 md_parse_option (int c
, char *arg
)
13591 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13592 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13594 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13595 c
== mips_ases
[i
].option_on
);
13601 case OPTION_CONSTRUCT_FLOATS
:
13602 mips_disable_float_construction
= 0;
13605 case OPTION_NO_CONSTRUCT_FLOATS
:
13606 mips_disable_float_construction
= 1;
13618 target_big_endian
= 1;
13622 target_big_endian
= 0;
13628 else if (arg
[0] == '0')
13630 else if (arg
[0] == '1')
13640 mips_debug
= atoi (arg
);
13644 file_mips_isa
= ISA_MIPS1
;
13648 file_mips_isa
= ISA_MIPS2
;
13652 file_mips_isa
= ISA_MIPS3
;
13656 file_mips_isa
= ISA_MIPS4
;
13660 file_mips_isa
= ISA_MIPS5
;
13663 case OPTION_MIPS32
:
13664 file_mips_isa
= ISA_MIPS32
;
13667 case OPTION_MIPS32R2
:
13668 file_mips_isa
= ISA_MIPS32R2
;
13671 case OPTION_MIPS64R2
:
13672 file_mips_isa
= ISA_MIPS64R2
;
13675 case OPTION_MIPS64
:
13676 file_mips_isa
= ISA_MIPS64
;
13680 mips_set_option_string (&mips_tune_string
, arg
);
13684 mips_set_option_string (&mips_arch_string
, arg
);
13688 mips_set_option_string (&mips_arch_string
, "4650");
13689 mips_set_option_string (&mips_tune_string
, "4650");
13692 case OPTION_NO_M4650
:
13696 mips_set_option_string (&mips_arch_string
, "4010");
13697 mips_set_option_string (&mips_tune_string
, "4010");
13700 case OPTION_NO_M4010
:
13704 mips_set_option_string (&mips_arch_string
, "4100");
13705 mips_set_option_string (&mips_tune_string
, "4100");
13708 case OPTION_NO_M4100
:
13712 mips_set_option_string (&mips_arch_string
, "3900");
13713 mips_set_option_string (&mips_tune_string
, "3900");
13716 case OPTION_NO_M3900
:
13719 case OPTION_MICROMIPS
:
13720 if (mips_opts
.mips16
== 1)
13722 as_bad (_("-mmicromips cannot be used with -mips16"));
13725 mips_opts
.micromips
= 1;
13726 mips_no_prev_insn ();
13729 case OPTION_NO_MICROMIPS
:
13730 mips_opts
.micromips
= 0;
13731 mips_no_prev_insn ();
13734 case OPTION_MIPS16
:
13735 if (mips_opts
.micromips
== 1)
13737 as_bad (_("-mips16 cannot be used with -micromips"));
13740 mips_opts
.mips16
= 1;
13741 mips_no_prev_insn ();
13744 case OPTION_NO_MIPS16
:
13745 mips_opts
.mips16
= 0;
13746 mips_no_prev_insn ();
13749 case OPTION_FIX_24K
:
13753 case OPTION_NO_FIX_24K
:
13757 case OPTION_FIX_LOONGSON2F_JUMP
:
13758 mips_fix_loongson2f_jump
= TRUE
;
13761 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13762 mips_fix_loongson2f_jump
= FALSE
;
13765 case OPTION_FIX_LOONGSON2F_NOP
:
13766 mips_fix_loongson2f_nop
= TRUE
;
13769 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13770 mips_fix_loongson2f_nop
= FALSE
;
13773 case OPTION_FIX_VR4120
:
13774 mips_fix_vr4120
= 1;
13777 case OPTION_NO_FIX_VR4120
:
13778 mips_fix_vr4120
= 0;
13781 case OPTION_FIX_VR4130
:
13782 mips_fix_vr4130
= 1;
13785 case OPTION_NO_FIX_VR4130
:
13786 mips_fix_vr4130
= 0;
13789 case OPTION_FIX_CN63XXP1
:
13790 mips_fix_cn63xxp1
= TRUE
;
13793 case OPTION_NO_FIX_CN63XXP1
:
13794 mips_fix_cn63xxp1
= FALSE
;
13797 case OPTION_RELAX_BRANCH
:
13798 mips_relax_branch
= 1;
13801 case OPTION_NO_RELAX_BRANCH
:
13802 mips_relax_branch
= 0;
13805 case OPTION_INSN32
:
13806 mips_opts
.insn32
= TRUE
;
13809 case OPTION_NO_INSN32
:
13810 mips_opts
.insn32
= FALSE
;
13813 case OPTION_MSHARED
:
13814 mips_in_shared
= TRUE
;
13817 case OPTION_MNO_SHARED
:
13818 mips_in_shared
= FALSE
;
13821 case OPTION_MSYM32
:
13822 mips_opts
.sym32
= TRUE
;
13825 case OPTION_MNO_SYM32
:
13826 mips_opts
.sym32
= FALSE
;
13829 /* When generating ELF code, we permit -KPIC and -call_shared to
13830 select SVR4_PIC, and -non_shared to select no PIC. This is
13831 intended to be compatible with Irix 5. */
13832 case OPTION_CALL_SHARED
:
13833 mips_pic
= SVR4_PIC
;
13834 mips_abicalls
= TRUE
;
13837 case OPTION_CALL_NONPIC
:
13839 mips_abicalls
= TRUE
;
13842 case OPTION_NON_SHARED
:
13844 mips_abicalls
= FALSE
;
13847 /* The -xgot option tells the assembler to use 32 bit offsets
13848 when accessing the got in SVR4_PIC mode. It is for Irix
13855 g_switch_value
= atoi (arg
);
13859 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13862 mips_abi
= O32_ABI
;
13866 mips_abi
= N32_ABI
;
13870 mips_abi
= N64_ABI
;
13871 if (!support_64bit_objects())
13872 as_fatal (_("No compiled in support for 64 bit object file format"));
13876 file_mips_gp32
= 1;
13880 file_mips_gp32
= 0;
13884 file_mips_fp32
= 1;
13888 file_mips_fp32
= 0;
13891 case OPTION_SINGLE_FLOAT
:
13892 file_mips_single_float
= 1;
13895 case OPTION_DOUBLE_FLOAT
:
13896 file_mips_single_float
= 0;
13899 case OPTION_SOFT_FLOAT
:
13900 file_mips_soft_float
= 1;
13903 case OPTION_HARD_FLOAT
:
13904 file_mips_soft_float
= 0;
13908 if (strcmp (arg
, "32") == 0)
13909 mips_abi
= O32_ABI
;
13910 else if (strcmp (arg
, "o64") == 0)
13911 mips_abi
= O64_ABI
;
13912 else if (strcmp (arg
, "n32") == 0)
13913 mips_abi
= N32_ABI
;
13914 else if (strcmp (arg
, "64") == 0)
13916 mips_abi
= N64_ABI
;
13917 if (! support_64bit_objects())
13918 as_fatal (_("No compiled in support for 64 bit object file "
13921 else if (strcmp (arg
, "eabi") == 0)
13922 mips_abi
= EABI_ABI
;
13925 as_fatal (_("invalid abi -mabi=%s"), arg
);
13930 case OPTION_M7000_HILO_FIX
:
13931 mips_7000_hilo_fix
= TRUE
;
13934 case OPTION_MNO_7000_HILO_FIX
:
13935 mips_7000_hilo_fix
= FALSE
;
13938 case OPTION_MDEBUG
:
13939 mips_flag_mdebug
= TRUE
;
13942 case OPTION_NO_MDEBUG
:
13943 mips_flag_mdebug
= FALSE
;
13947 mips_flag_pdr
= TRUE
;
13950 case OPTION_NO_PDR
:
13951 mips_flag_pdr
= FALSE
;
13954 case OPTION_MVXWORKS_PIC
:
13955 mips_pic
= VXWORKS_PIC
;
13959 if (strcmp (arg
, "2008") == 0)
13960 mips_flag_nan2008
= TRUE
;
13961 else if (strcmp (arg
, "legacy") == 0)
13962 mips_flag_nan2008
= FALSE
;
13965 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13974 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13979 /* Set up globals to generate code for the ISA or processor
13980 described by INFO. */
13983 mips_set_architecture (const struct mips_cpu_info
*info
)
13987 file_mips_arch
= info
->cpu
;
13988 mips_opts
.arch
= info
->cpu
;
13989 mips_opts
.isa
= info
->isa
;
13994 /* Likewise for tuning. */
13997 mips_set_tune (const struct mips_cpu_info
*info
)
14000 mips_tune
= info
->cpu
;
14005 mips_after_parse_args (void)
14007 const struct mips_cpu_info
*arch_info
= 0;
14008 const struct mips_cpu_info
*tune_info
= 0;
14010 /* GP relative stuff not working for PE */
14011 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14013 if (g_switch_seen
&& g_switch_value
!= 0)
14014 as_bad (_("-G not supported in this configuration."));
14015 g_switch_value
= 0;
14018 if (mips_abi
== NO_ABI
)
14019 mips_abi
= MIPS_DEFAULT_ABI
;
14021 /* The following code determines the architecture and register size.
14022 Similar code was added to GCC 3.3 (see override_options() in
14023 config/mips/mips.c). The GAS and GCC code should be kept in sync
14024 as much as possible. */
14026 if (mips_arch_string
!= 0)
14027 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14029 if (file_mips_isa
!= ISA_UNKNOWN
)
14031 /* Handle -mipsN. At this point, file_mips_isa contains the
14032 ISA level specified by -mipsN, while arch_info->isa contains
14033 the -march selection (if any). */
14034 if (arch_info
!= 0)
14036 /* -march takes precedence over -mipsN, since it is more descriptive.
14037 There's no harm in specifying both as long as the ISA levels
14039 if (file_mips_isa
!= arch_info
->isa
)
14040 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14041 mips_cpu_info_from_isa (file_mips_isa
)->name
,
14042 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14045 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
14048 if (arch_info
== 0)
14050 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14051 gas_assert (arch_info
);
14054 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14055 as_bad (_("-march=%s is not compatible with the selected ABI"),
14058 mips_set_architecture (arch_info
);
14060 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14061 if (mips_tune_string
!= 0)
14062 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14064 if (tune_info
== 0)
14065 mips_set_tune (arch_info
);
14067 mips_set_tune (tune_info
);
14069 if (file_mips_gp32
>= 0)
14071 /* The user specified the size of the integer registers. Make sure
14072 it agrees with the ABI and ISA. */
14073 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14074 as_bad (_("-mgp64 used with a 32-bit processor"));
14075 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14076 as_bad (_("-mgp32 used with a 64-bit ABI"));
14077 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14078 as_bad (_("-mgp64 used with a 32-bit ABI"));
14082 /* Infer the integer register size from the ABI and processor.
14083 Restrict ourselves to 32-bit registers if that's all the
14084 processor has, or if the ABI cannot handle 64-bit registers. */
14085 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14086 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14089 switch (file_mips_fp32
)
14093 /* No user specified float register size.
14094 ??? GAS treats single-float processors as though they had 64-bit
14095 float registers (although it complains when double-precision
14096 instructions are used). As things stand, saying they have 32-bit
14097 registers would lead to spurious "register must be even" messages.
14098 So here we assume float registers are never smaller than the
14100 if (file_mips_gp32
== 0)
14101 /* 64-bit integer registers implies 64-bit float registers. */
14102 file_mips_fp32
= 0;
14103 else if ((mips_opts
.ase
& FP64_ASES
)
14104 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14105 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14106 file_mips_fp32
= 0;
14108 /* 32-bit float registers. */
14109 file_mips_fp32
= 1;
14112 /* The user specified the size of the float registers. Check if it
14113 agrees with the ABI and ISA. */
14115 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14116 as_bad (_("-mfp64 used with a 32-bit fpu"));
14117 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14118 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14119 as_warn (_("-mfp64 used with a 32-bit ABI"));
14122 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14123 as_warn (_("-mfp32 used with a 64-bit ABI"));
14127 /* End of GCC-shared inference code. */
14129 /* This flag is set when we have a 64-bit capable CPU but use only
14130 32-bit wide registers. Note that EABI does not use it. */
14131 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14132 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14133 || mips_abi
== O32_ABI
))
14134 mips_32bitmode
= 1;
14136 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14137 as_bad (_("trap exception not supported at ISA 1"));
14139 /* If the selected architecture includes support for ASEs, enable
14140 generation of code for them. */
14141 if (mips_opts
.mips16
== -1)
14142 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14143 if (mips_opts
.micromips
== -1)
14144 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14146 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14147 ASEs from being selected implicitly. */
14148 if (file_mips_fp32
== 1)
14149 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14151 /* If the user didn't explicitly select or deselect a particular ASE,
14152 use the default setting for the CPU. */
14153 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14155 file_mips_isa
= mips_opts
.isa
;
14156 file_ase
= mips_opts
.ase
;
14157 mips_opts
.gp32
= file_mips_gp32
;
14158 mips_opts
.fp32
= file_mips_fp32
;
14159 mips_opts
.soft_float
= file_mips_soft_float
;
14160 mips_opts
.single_float
= file_mips_single_float
;
14162 mips_check_isa_supports_ases ();
14164 if (mips_flag_mdebug
< 0)
14165 mips_flag_mdebug
= 0;
14169 mips_init_after_args (void)
14171 /* initialize opcodes */
14172 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14173 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14177 md_pcrel_from (fixS
*fixP
)
14179 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14180 switch (fixP
->fx_r_type
)
14182 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14183 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14184 /* Return the address of the delay slot. */
14187 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14188 case BFD_RELOC_MICROMIPS_JMP
:
14189 case BFD_RELOC_16_PCREL_S2
:
14190 case BFD_RELOC_MIPS_JMP
:
14191 /* Return the address of the delay slot. */
14194 case BFD_RELOC_32_PCREL
:
14198 /* We have no relocation type for PC relative MIPS16 instructions. */
14199 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
14200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14201 _("PC relative MIPS16 instruction references a different section"));
14206 /* This is called before the symbol table is processed. In order to
14207 work with gcc when using mips-tfile, we must keep all local labels.
14208 However, in other cases, we want to discard them. If we were
14209 called with -g, but we didn't see any debugging information, it may
14210 mean that gcc is smuggling debugging information through to
14211 mips-tfile, in which case we must generate all local labels. */
14214 mips_frob_file_before_adjust (void)
14216 #ifndef NO_ECOFF_DEBUGGING
14217 if (ECOFF_DEBUGGING
14219 && ! ecoff_debugging_seen
)
14220 flag_keep_locals
= 1;
14224 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14225 the corresponding LO16 reloc. This is called before md_apply_fix and
14226 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14227 relocation operators.
14229 For our purposes, a %lo() expression matches a %got() or %hi()
14232 (a) it refers to the same symbol; and
14233 (b) the offset applied in the %lo() expression is no lower than
14234 the offset applied in the %got() or %hi().
14236 (b) allows us to cope with code like:
14239 lh $4,%lo(foo+2)($4)
14241 ...which is legal on RELA targets, and has a well-defined behaviour
14242 if the user knows that adding 2 to "foo" will not induce a carry to
14245 When several %lo()s match a particular %got() or %hi(), we use the
14246 following rules to distinguish them:
14248 (1) %lo()s with smaller offsets are a better match than %lo()s with
14251 (2) %lo()s with no matching %got() or %hi() are better than those
14252 that already have a matching %got() or %hi().
14254 (3) later %lo()s are better than earlier %lo()s.
14256 These rules are applied in order.
14258 (1) means, among other things, that %lo()s with identical offsets are
14259 chosen if they exist.
14261 (2) means that we won't associate several high-part relocations with
14262 the same low-part relocation unless there's no alternative. Having
14263 several high parts for the same low part is a GNU extension; this rule
14264 allows careful users to avoid it.
14266 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14267 with the last high-part relocation being at the front of the list.
14268 It therefore makes sense to choose the last matching low-part
14269 relocation, all other things being equal. It's also easier
14270 to code that way. */
14273 mips_frob_file (void)
14275 struct mips_hi_fixup
*l
;
14276 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14278 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14280 segment_info_type
*seginfo
;
14281 bfd_boolean matched_lo_p
;
14282 fixS
**hi_pos
, **lo_pos
, **pos
;
14284 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14286 /* If a GOT16 relocation turns out to be against a global symbol,
14287 there isn't supposed to be a matching LO. Ignore %gots against
14288 constants; we'll report an error for those later. */
14289 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14290 && !(l
->fixp
->fx_addsy
14291 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14294 /* Check quickly whether the next fixup happens to be a matching %lo. */
14295 if (fixup_has_matching_lo_p (l
->fixp
))
14298 seginfo
= seg_info (l
->seg
);
14300 /* Set HI_POS to the position of this relocation in the chain.
14301 Set LO_POS to the position of the chosen low-part relocation.
14302 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14303 relocation that matches an immediately-preceding high-part
14307 matched_lo_p
= FALSE
;
14308 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14310 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14312 if (*pos
== l
->fixp
)
14315 if ((*pos
)->fx_r_type
== looking_for_rtype
14316 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14317 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14319 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14321 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14324 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14325 && fixup_has_matching_lo_p (*pos
));
14328 /* If we found a match, remove the high-part relocation from its
14329 current position and insert it before the low-part relocation.
14330 Make the offsets match so that fixup_has_matching_lo_p()
14333 We don't warn about unmatched high-part relocations since some
14334 versions of gcc have been known to emit dead "lui ...%hi(...)"
14336 if (lo_pos
!= NULL
)
14338 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14339 if (l
->fixp
->fx_next
!= *lo_pos
)
14341 *hi_pos
= l
->fixp
->fx_next
;
14342 l
->fixp
->fx_next
= *lo_pos
;
14350 mips_force_relocation (fixS
*fixp
)
14352 if (generic_force_reloc (fixp
))
14355 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14356 so that the linker relaxation can update targets. */
14357 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14358 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14359 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14365 /* Read the instruction associated with RELOC from BUF. */
14367 static unsigned int
14368 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14370 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14371 return read_compressed_insn (buf
, 4);
14373 return read_insn (buf
);
14376 /* Write instruction INSN to BUF, given that it has been relocated
14380 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14381 unsigned long insn
)
14383 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14384 write_compressed_insn (buf
, insn
, 4);
14386 write_insn (buf
, insn
);
14389 /* Apply a fixup to the object file. */
14392 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14395 unsigned long insn
;
14396 reloc_howto_type
*howto
;
14398 /* We ignore generic BFD relocations we don't know about. */
14399 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14403 gas_assert (fixP
->fx_size
== 2
14404 || fixP
->fx_size
== 4
14405 || fixP
->fx_r_type
== BFD_RELOC_16
14406 || fixP
->fx_r_type
== BFD_RELOC_64
14407 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14408 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14409 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14410 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14411 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14412 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14414 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14416 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14417 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14418 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14419 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14420 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14422 /* Don't treat parts of a composite relocation as done. There are two
14425 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14426 should nevertheless be emitted if the first part is.
14428 (2) In normal usage, composite relocations are never assembly-time
14429 constants. The easiest way of dealing with the pathological
14430 exceptions is to generate a relocation against STN_UNDEF and
14431 leave everything up to the linker. */
14432 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14435 switch (fixP
->fx_r_type
)
14437 case BFD_RELOC_MIPS_TLS_GD
:
14438 case BFD_RELOC_MIPS_TLS_LDM
:
14439 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14440 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14441 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14442 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14443 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14444 case BFD_RELOC_MIPS_TLS_TPREL32
:
14445 case BFD_RELOC_MIPS_TLS_TPREL64
:
14446 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14447 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14448 case BFD_RELOC_MICROMIPS_TLS_GD
:
14449 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14450 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14451 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14452 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14453 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14454 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14455 case BFD_RELOC_MIPS16_TLS_GD
:
14456 case BFD_RELOC_MIPS16_TLS_LDM
:
14457 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14458 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14459 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14460 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14461 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14462 if (!fixP
->fx_addsy
)
14464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14465 _("TLS relocation against a constant"));
14468 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14471 case BFD_RELOC_MIPS_JMP
:
14472 case BFD_RELOC_MIPS_SHIFT5
:
14473 case BFD_RELOC_MIPS_SHIFT6
:
14474 case BFD_RELOC_MIPS_GOT_DISP
:
14475 case BFD_RELOC_MIPS_GOT_PAGE
:
14476 case BFD_RELOC_MIPS_GOT_OFST
:
14477 case BFD_RELOC_MIPS_SUB
:
14478 case BFD_RELOC_MIPS_INSERT_A
:
14479 case BFD_RELOC_MIPS_INSERT_B
:
14480 case BFD_RELOC_MIPS_DELETE
:
14481 case BFD_RELOC_MIPS_HIGHEST
:
14482 case BFD_RELOC_MIPS_HIGHER
:
14483 case BFD_RELOC_MIPS_SCN_DISP
:
14484 case BFD_RELOC_MIPS_REL16
:
14485 case BFD_RELOC_MIPS_RELGOT
:
14486 case BFD_RELOC_MIPS_JALR
:
14487 case BFD_RELOC_HI16
:
14488 case BFD_RELOC_HI16_S
:
14489 case BFD_RELOC_LO16
:
14490 case BFD_RELOC_GPREL16
:
14491 case BFD_RELOC_MIPS_LITERAL
:
14492 case BFD_RELOC_MIPS_CALL16
:
14493 case BFD_RELOC_MIPS_GOT16
:
14494 case BFD_RELOC_GPREL32
:
14495 case BFD_RELOC_MIPS_GOT_HI16
:
14496 case BFD_RELOC_MIPS_GOT_LO16
:
14497 case BFD_RELOC_MIPS_CALL_HI16
:
14498 case BFD_RELOC_MIPS_CALL_LO16
:
14499 case BFD_RELOC_MIPS16_GPREL
:
14500 case BFD_RELOC_MIPS16_GOT16
:
14501 case BFD_RELOC_MIPS16_CALL16
:
14502 case BFD_RELOC_MIPS16_HI16
:
14503 case BFD_RELOC_MIPS16_HI16_S
:
14504 case BFD_RELOC_MIPS16_LO16
:
14505 case BFD_RELOC_MIPS16_JMP
:
14506 case BFD_RELOC_MICROMIPS_JMP
:
14507 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14508 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14509 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14510 case BFD_RELOC_MICROMIPS_SUB
:
14511 case BFD_RELOC_MICROMIPS_HIGHEST
:
14512 case BFD_RELOC_MICROMIPS_HIGHER
:
14513 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14514 case BFD_RELOC_MICROMIPS_JALR
:
14515 case BFD_RELOC_MICROMIPS_HI16
:
14516 case BFD_RELOC_MICROMIPS_HI16_S
:
14517 case BFD_RELOC_MICROMIPS_LO16
:
14518 case BFD_RELOC_MICROMIPS_GPREL16
:
14519 case BFD_RELOC_MICROMIPS_LITERAL
:
14520 case BFD_RELOC_MICROMIPS_CALL16
:
14521 case BFD_RELOC_MICROMIPS_GOT16
:
14522 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14523 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14524 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14525 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14526 case BFD_RELOC_MIPS_EH
:
14531 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14533 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14534 if (mips16_reloc_p (fixP
->fx_r_type
))
14535 insn
|= mips16_immed_extend (value
, 16);
14537 insn
|= (value
& 0xffff);
14538 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14542 _("Unsupported constant in relocation"));
14547 /* This is handled like BFD_RELOC_32, but we output a sign
14548 extended value if we are only 32 bits. */
14551 if (8 <= sizeof (valueT
))
14552 md_number_to_chars (buf
, *valP
, 8);
14557 if ((*valP
& 0x80000000) != 0)
14561 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14562 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14567 case BFD_RELOC_RVA
:
14569 case BFD_RELOC_32_PCREL
:
14571 /* If we are deleting this reloc entry, we must fill in the
14572 value now. This can happen if we have a .word which is not
14573 resolved when it appears but is later defined. */
14575 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14578 case BFD_RELOC_16_PCREL_S2
:
14579 if ((*valP
& 0x3) != 0)
14580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14581 _("Branch to misaligned address (%lx)"), (long) *valP
);
14583 /* We need to save the bits in the instruction since fixup_segment()
14584 might be deleting the relocation entry (i.e., a branch within
14585 the current segment). */
14586 if (! fixP
->fx_done
)
14589 /* Update old instruction data. */
14590 insn
= read_insn (buf
);
14592 if (*valP
+ 0x20000 <= 0x3ffff)
14594 insn
|= (*valP
>> 2) & 0xffff;
14595 write_insn (buf
, insn
);
14597 else if (mips_pic
== NO_PIC
14599 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14600 && (fixP
->fx_frag
->fr_address
14601 < text_section
->vma
+ bfd_get_section_size (text_section
))
14602 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14603 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14604 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14606 /* The branch offset is too large. If this is an
14607 unconditional branch, and we are not generating PIC code,
14608 we can convert it to an absolute jump instruction. */
14609 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14610 insn
= 0x0c000000; /* jal */
14612 insn
= 0x08000000; /* j */
14613 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14615 fixP
->fx_addsy
= section_symbol (text_section
);
14616 *valP
+= md_pcrel_from (fixP
);
14617 write_insn (buf
, insn
);
14621 /* If we got here, we have branch-relaxation disabled,
14622 and there's nothing we can do to fix this instruction
14623 without turning it into a longer sequence. */
14624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14625 _("Branch out of range"));
14629 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14630 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14631 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14632 /* We adjust the offset back to even. */
14633 if ((*valP
& 0x1) != 0)
14636 if (! fixP
->fx_done
)
14639 /* Should never visit here, because we keep the relocation. */
14643 case BFD_RELOC_VTABLE_INHERIT
:
14646 && !S_IS_DEFINED (fixP
->fx_addsy
)
14647 && !S_IS_WEAK (fixP
->fx_addsy
))
14648 S_SET_WEAK (fixP
->fx_addsy
);
14651 case BFD_RELOC_VTABLE_ENTRY
:
14659 /* Remember value for tc_gen_reloc. */
14660 fixP
->fx_addnumber
= *valP
;
14670 name
= input_line_pointer
;
14671 c
= get_symbol_end ();
14672 p
= (symbolS
*) symbol_find_or_make (name
);
14673 *input_line_pointer
= c
;
14677 /* Align the current frag to a given power of two. If a particular
14678 fill byte should be used, FILL points to an integer that contains
14679 that byte, otherwise FILL is null.
14681 This function used to have the comment:
14683 The MIPS assembler also automatically adjusts any preceding label.
14685 The implementation therefore applied the adjustment to a maximum of
14686 one label. However, other label adjustments are applied to batches
14687 of labels, and adjusting just one caused problems when new labels
14688 were added for the sake of debugging or unwind information.
14689 We therefore adjust all preceding labels (given as LABELS) instead. */
14692 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14694 mips_emit_delays ();
14695 mips_record_compressed_mode ();
14696 if (fill
== NULL
&& subseg_text_p (now_seg
))
14697 frag_align_code (to
, 0);
14699 frag_align (to
, fill
? *fill
: 0, 0);
14700 record_alignment (now_seg
, to
);
14701 mips_move_labels (labels
, FALSE
);
14704 /* Align to a given power of two. .align 0 turns off the automatic
14705 alignment used by the data creating pseudo-ops. */
14708 s_align (int x ATTRIBUTE_UNUSED
)
14710 int temp
, fill_value
, *fill_ptr
;
14711 long max_alignment
= 28;
14713 /* o Note that the assembler pulls down any immediately preceding label
14714 to the aligned address.
14715 o It's not documented but auto alignment is reinstated by
14716 a .align pseudo instruction.
14717 o Note also that after auto alignment is turned off the mips assembler
14718 issues an error on attempt to assemble an improperly aligned data item.
14721 temp
= get_absolute_expression ();
14722 if (temp
> max_alignment
)
14723 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14726 as_warn (_("Alignment negative: 0 assumed."));
14729 if (*input_line_pointer
== ',')
14731 ++input_line_pointer
;
14732 fill_value
= get_absolute_expression ();
14733 fill_ptr
= &fill_value
;
14739 segment_info_type
*si
= seg_info (now_seg
);
14740 struct insn_label_list
*l
= si
->label_list
;
14741 /* Auto alignment should be switched on by next section change. */
14743 mips_align (temp
, fill_ptr
, l
);
14750 demand_empty_rest_of_line ();
14754 s_change_sec (int sec
)
14758 /* The ELF backend needs to know that we are changing sections, so
14759 that .previous works correctly. We could do something like check
14760 for an obj_section_change_hook macro, but that might be confusing
14761 as it would not be appropriate to use it in the section changing
14762 functions in read.c, since obj-elf.c intercepts those. FIXME:
14763 This should be cleaner, somehow. */
14764 obj_elf_section_change_hook ();
14766 mips_emit_delays ();
14777 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14778 demand_empty_rest_of_line ();
14782 seg
= subseg_new (RDATA_SECTION_NAME
,
14783 (subsegT
) get_absolute_expression ());
14784 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14785 | SEC_READONLY
| SEC_RELOC
14787 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14788 record_alignment (seg
, 4);
14789 demand_empty_rest_of_line ();
14793 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14794 bfd_set_section_flags (stdoutput
, seg
,
14795 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14796 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14797 record_alignment (seg
, 4);
14798 demand_empty_rest_of_line ();
14802 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14803 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14804 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14805 record_alignment (seg
, 4);
14806 demand_empty_rest_of_line ();
14814 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14816 char *section_name
;
14821 int section_entry_size
;
14822 int section_alignment
;
14824 section_name
= input_line_pointer
;
14825 c
= get_symbol_end ();
14827 next_c
= *(input_line_pointer
+ 1);
14829 /* Do we have .section Name<,"flags">? */
14830 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14832 /* just after name is now '\0'. */
14833 *input_line_pointer
= c
;
14834 input_line_pointer
= section_name
;
14835 obj_elf_section (ignore
);
14838 input_line_pointer
++;
14840 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14842 section_type
= get_absolute_expression ();
14845 if (*input_line_pointer
++ == ',')
14846 section_flag
= get_absolute_expression ();
14849 if (*input_line_pointer
++ == ',')
14850 section_entry_size
= get_absolute_expression ();
14852 section_entry_size
= 0;
14853 if (*input_line_pointer
++ == ',')
14854 section_alignment
= get_absolute_expression ();
14856 section_alignment
= 0;
14857 /* FIXME: really ignore? */
14858 (void) section_alignment
;
14860 section_name
= xstrdup (section_name
);
14862 /* When using the generic form of .section (as implemented by obj-elf.c),
14863 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14864 traditionally had to fall back on the more common @progbits instead.
14866 There's nothing really harmful in this, since bfd will correct
14867 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14868 means that, for backwards compatibility, the special_section entries
14869 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14871 Even so, we shouldn't force users of the MIPS .section syntax to
14872 incorrectly label the sections as SHT_PROGBITS. The best compromise
14873 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14874 generic type-checking code. */
14875 if (section_type
== SHT_MIPS_DWARF
)
14876 section_type
= SHT_PROGBITS
;
14878 obj_elf_change_section (section_name
, section_type
, section_flag
,
14879 section_entry_size
, 0, 0, 0);
14881 if (now_seg
->name
!= section_name
)
14882 free (section_name
);
14886 mips_enable_auto_align (void)
14892 s_cons (int log_size
)
14894 segment_info_type
*si
= seg_info (now_seg
);
14895 struct insn_label_list
*l
= si
->label_list
;
14897 mips_emit_delays ();
14898 if (log_size
> 0 && auto_align
)
14899 mips_align (log_size
, 0, l
);
14900 cons (1 << log_size
);
14901 mips_clear_insn_labels ();
14905 s_float_cons (int type
)
14907 segment_info_type
*si
= seg_info (now_seg
);
14908 struct insn_label_list
*l
= si
->label_list
;
14910 mips_emit_delays ();
14915 mips_align (3, 0, l
);
14917 mips_align (2, 0, l
);
14921 mips_clear_insn_labels ();
14924 /* Handle .globl. We need to override it because on Irix 5 you are
14927 where foo is an undefined symbol, to mean that foo should be
14928 considered to be the address of a function. */
14931 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14940 name
= input_line_pointer
;
14941 c
= get_symbol_end ();
14942 symbolP
= symbol_find_or_make (name
);
14943 S_SET_EXTERNAL (symbolP
);
14945 *input_line_pointer
= c
;
14946 SKIP_WHITESPACE ();
14948 /* On Irix 5, every global symbol that is not explicitly labelled as
14949 being a function is apparently labelled as being an object. */
14952 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14953 && (*input_line_pointer
!= ','))
14958 secname
= input_line_pointer
;
14959 c
= get_symbol_end ();
14960 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14962 as_bad (_("%s: no such section"), secname
);
14963 *input_line_pointer
= c
;
14965 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14966 flag
= BSF_FUNCTION
;
14969 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14971 c
= *input_line_pointer
;
14974 input_line_pointer
++;
14975 SKIP_WHITESPACE ();
14976 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14982 demand_empty_rest_of_line ();
14986 s_option (int x ATTRIBUTE_UNUSED
)
14991 opt
= input_line_pointer
;
14992 c
= get_symbol_end ();
14996 /* FIXME: What does this mean? */
14998 else if (strncmp (opt
, "pic", 3) == 0)
15002 i
= atoi (opt
+ 3);
15007 mips_pic
= SVR4_PIC
;
15008 mips_abicalls
= TRUE
;
15011 as_bad (_(".option pic%d not supported"), i
);
15013 if (mips_pic
== SVR4_PIC
)
15015 if (g_switch_seen
&& g_switch_value
!= 0)
15016 as_warn (_("-G may not be used with SVR4 PIC code"));
15017 g_switch_value
= 0;
15018 bfd_set_gp_size (stdoutput
, 0);
15022 as_warn (_("Unrecognized option \"%s\""), opt
);
15024 *input_line_pointer
= c
;
15025 demand_empty_rest_of_line ();
15028 /* This structure is used to hold a stack of .set values. */
15030 struct mips_option_stack
15032 struct mips_option_stack
*next
;
15033 struct mips_set_options options
;
15036 static struct mips_option_stack
*mips_opts_stack
;
15038 /* Handle the .set pseudo-op. */
15041 s_mipsset (int x ATTRIBUTE_UNUSED
)
15043 char *name
= input_line_pointer
, ch
;
15044 const struct mips_ase
*ase
;
15046 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15047 ++input_line_pointer
;
15048 ch
= *input_line_pointer
;
15049 *input_line_pointer
= '\0';
15051 if (strcmp (name
, "reorder") == 0)
15053 if (mips_opts
.noreorder
)
15056 else if (strcmp (name
, "noreorder") == 0)
15058 if (!mips_opts
.noreorder
)
15059 start_noreorder ();
15061 else if (strncmp (name
, "at=", 3) == 0)
15063 char *s
= name
+ 3;
15065 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15066 as_bad (_("Unrecognized register name `%s'"), s
);
15068 else if (strcmp (name
, "at") == 0)
15070 mips_opts
.at
= ATREG
;
15072 else if (strcmp (name
, "noat") == 0)
15074 mips_opts
.at
= ZERO
;
15076 else if (strcmp (name
, "macro") == 0)
15078 mips_opts
.warn_about_macros
= 0;
15080 else if (strcmp (name
, "nomacro") == 0)
15082 if (mips_opts
.noreorder
== 0)
15083 as_bad (_("`noreorder' must be set before `nomacro'"));
15084 mips_opts
.warn_about_macros
= 1;
15086 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15088 mips_opts
.nomove
= 0;
15090 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15092 mips_opts
.nomove
= 1;
15094 else if (strcmp (name
, "bopt") == 0)
15096 mips_opts
.nobopt
= 0;
15098 else if (strcmp (name
, "nobopt") == 0)
15100 mips_opts
.nobopt
= 1;
15102 else if (strcmp (name
, "gp=default") == 0)
15103 mips_opts
.gp32
= file_mips_gp32
;
15104 else if (strcmp (name
, "gp=32") == 0)
15105 mips_opts
.gp32
= 1;
15106 else if (strcmp (name
, "gp=64") == 0)
15108 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15109 as_warn (_("%s isa does not support 64-bit registers"),
15110 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15111 mips_opts
.gp32
= 0;
15113 else if (strcmp (name
, "fp=default") == 0)
15114 mips_opts
.fp32
= file_mips_fp32
;
15115 else if (strcmp (name
, "fp=32") == 0)
15116 mips_opts
.fp32
= 1;
15117 else if (strcmp (name
, "fp=64") == 0)
15119 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15120 as_warn (_("%s isa does not support 64-bit floating point registers"),
15121 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15122 mips_opts
.fp32
= 0;
15124 else if (strcmp (name
, "softfloat") == 0)
15125 mips_opts
.soft_float
= 1;
15126 else if (strcmp (name
, "hardfloat") == 0)
15127 mips_opts
.soft_float
= 0;
15128 else if (strcmp (name
, "singlefloat") == 0)
15129 mips_opts
.single_float
= 1;
15130 else if (strcmp (name
, "doublefloat") == 0)
15131 mips_opts
.single_float
= 0;
15132 else if (strcmp (name
, "mips16") == 0
15133 || strcmp (name
, "MIPS-16") == 0)
15135 if (mips_opts
.micromips
== 1)
15136 as_fatal (_("`mips16' cannot be used with `micromips'"));
15137 mips_opts
.mips16
= 1;
15139 else if (strcmp (name
, "nomips16") == 0
15140 || strcmp (name
, "noMIPS-16") == 0)
15141 mips_opts
.mips16
= 0;
15142 else if (strcmp (name
, "micromips") == 0)
15144 if (mips_opts
.mips16
== 1)
15145 as_fatal (_("`micromips' cannot be used with `mips16'"));
15146 mips_opts
.micromips
= 1;
15148 else if (strcmp (name
, "nomicromips") == 0)
15149 mips_opts
.micromips
= 0;
15150 else if (name
[0] == 'n'
15152 && (ase
= mips_lookup_ase (name
+ 2)))
15153 mips_set_ase (ase
, FALSE
);
15154 else if ((ase
= mips_lookup_ase (name
)))
15155 mips_set_ase (ase
, TRUE
);
15156 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15160 /* Permit the user to change the ISA and architecture on the fly.
15161 Needless to say, misuse can cause serious problems. */
15162 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15165 mips_opts
.isa
= file_mips_isa
;
15166 mips_opts
.arch
= file_mips_arch
;
15168 else if (strncmp (name
, "arch=", 5) == 0)
15170 const struct mips_cpu_info
*p
;
15172 p
= mips_parse_cpu("internal use", name
+ 5);
15174 as_bad (_("unknown architecture %s"), name
+ 5);
15177 mips_opts
.arch
= p
->cpu
;
15178 mips_opts
.isa
= p
->isa
;
15181 else if (strncmp (name
, "mips", 4) == 0)
15183 const struct mips_cpu_info
*p
;
15185 p
= mips_parse_cpu("internal use", name
);
15187 as_bad (_("unknown ISA level %s"), name
+ 4);
15190 mips_opts
.arch
= p
->cpu
;
15191 mips_opts
.isa
= p
->isa
;
15195 as_bad (_("unknown ISA or architecture %s"), name
);
15197 switch (mips_opts
.isa
)
15205 mips_opts
.gp32
= 1;
15206 mips_opts
.fp32
= 1;
15213 mips_opts
.gp32
= 0;
15214 if (mips_opts
.arch
== CPU_R5900
)
15216 mips_opts
.fp32
= 1;
15220 mips_opts
.fp32
= 0;
15224 as_bad (_("unknown ISA level %s"), name
+ 4);
15229 mips_opts
.gp32
= file_mips_gp32
;
15230 mips_opts
.fp32
= file_mips_fp32
;
15233 else if (strcmp (name
, "autoextend") == 0)
15234 mips_opts
.noautoextend
= 0;
15235 else if (strcmp (name
, "noautoextend") == 0)
15236 mips_opts
.noautoextend
= 1;
15237 else if (strcmp (name
, "insn32") == 0)
15238 mips_opts
.insn32
= TRUE
;
15239 else if (strcmp (name
, "noinsn32") == 0)
15240 mips_opts
.insn32
= FALSE
;
15241 else if (strcmp (name
, "push") == 0)
15243 struct mips_option_stack
*s
;
15245 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15246 s
->next
= mips_opts_stack
;
15247 s
->options
= mips_opts
;
15248 mips_opts_stack
= s
;
15250 else if (strcmp (name
, "pop") == 0)
15252 struct mips_option_stack
*s
;
15254 s
= mips_opts_stack
;
15256 as_bad (_(".set pop with no .set push"));
15259 /* If we're changing the reorder mode we need to handle
15260 delay slots correctly. */
15261 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15262 start_noreorder ();
15263 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15266 mips_opts
= s
->options
;
15267 mips_opts_stack
= s
->next
;
15271 else if (strcmp (name
, "sym32") == 0)
15272 mips_opts
.sym32
= TRUE
;
15273 else if (strcmp (name
, "nosym32") == 0)
15274 mips_opts
.sym32
= FALSE
;
15275 else if (strchr (name
, ','))
15277 /* Generic ".set" directive; use the generic handler. */
15278 *input_line_pointer
= ch
;
15279 input_line_pointer
= name
;
15285 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
15287 mips_check_isa_supports_ases ();
15288 *input_line_pointer
= ch
;
15289 demand_empty_rest_of_line ();
15292 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15293 .option pic2. It means to generate SVR4 PIC calls. */
15296 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15298 mips_pic
= SVR4_PIC
;
15299 mips_abicalls
= TRUE
;
15301 if (g_switch_seen
&& g_switch_value
!= 0)
15302 as_warn (_("-G may not be used with SVR4 PIC code"));
15303 g_switch_value
= 0;
15305 bfd_set_gp_size (stdoutput
, 0);
15306 demand_empty_rest_of_line ();
15309 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15310 PIC code. It sets the $gp register for the function based on the
15311 function address, which is in the register named in the argument.
15312 This uses a relocation against _gp_disp, which is handled specially
15313 by the linker. The result is:
15314 lui $gp,%hi(_gp_disp)
15315 addiu $gp,$gp,%lo(_gp_disp)
15316 addu $gp,$gp,.cpload argument
15317 The .cpload argument is normally $25 == $t9.
15319 The -mno-shared option changes this to:
15320 lui $gp,%hi(__gnu_local_gp)
15321 addiu $gp,$gp,%lo(__gnu_local_gp)
15322 and the argument is ignored. This saves an instruction, but the
15323 resulting code is not position independent; it uses an absolute
15324 address for __gnu_local_gp. Thus code assembled with -mno-shared
15325 can go into an ordinary executable, but not into a shared library. */
15328 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15334 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15335 .cpload is ignored. */
15336 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15342 if (mips_opts
.mips16
)
15344 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15345 ignore_rest_of_line ();
15349 /* .cpload should be in a .set noreorder section. */
15350 if (mips_opts
.noreorder
== 0)
15351 as_warn (_(".cpload not in noreorder section"));
15353 reg
= tc_get_register (0);
15355 /* If we need to produce a 64-bit address, we are better off using
15356 the default instruction sequence. */
15357 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15359 ex
.X_op
= O_symbol
;
15360 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15362 ex
.X_op_symbol
= NULL
;
15363 ex
.X_add_number
= 0;
15365 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15366 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15368 mips_mark_labels ();
15369 mips_assembling_insn
= TRUE
;
15372 macro_build_lui (&ex
, mips_gp_register
);
15373 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15374 mips_gp_register
, BFD_RELOC_LO16
);
15376 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15377 mips_gp_register
, reg
);
15380 mips_assembling_insn
= FALSE
;
15381 demand_empty_rest_of_line ();
15384 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15385 .cpsetup $reg1, offset|$reg2, label
15387 If offset is given, this results in:
15388 sd $gp, offset($sp)
15389 lui $gp, %hi(%neg(%gp_rel(label)))
15390 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15391 daddu $gp, $gp, $reg1
15393 If $reg2 is given, this results in:
15394 daddu $reg2, $gp, $0
15395 lui $gp, %hi(%neg(%gp_rel(label)))
15396 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15397 daddu $gp, $gp, $reg1
15398 $reg1 is normally $25 == $t9.
15400 The -mno-shared option replaces the last three instructions with
15402 addiu $gp,$gp,%lo(_gp) */
15405 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15407 expressionS ex_off
;
15408 expressionS ex_sym
;
15411 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15412 We also need NewABI support. */
15413 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15419 if (mips_opts
.mips16
)
15421 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15422 ignore_rest_of_line ();
15426 reg1
= tc_get_register (0);
15427 SKIP_WHITESPACE ();
15428 if (*input_line_pointer
!= ',')
15430 as_bad (_("missing argument separator ',' for .cpsetup"));
15434 ++input_line_pointer
;
15435 SKIP_WHITESPACE ();
15436 if (*input_line_pointer
== '$')
15438 mips_cpreturn_register
= tc_get_register (0);
15439 mips_cpreturn_offset
= -1;
15443 mips_cpreturn_offset
= get_absolute_expression ();
15444 mips_cpreturn_register
= -1;
15446 SKIP_WHITESPACE ();
15447 if (*input_line_pointer
!= ',')
15449 as_bad (_("missing argument separator ',' for .cpsetup"));
15453 ++input_line_pointer
;
15454 SKIP_WHITESPACE ();
15455 expression (&ex_sym
);
15457 mips_mark_labels ();
15458 mips_assembling_insn
= TRUE
;
15461 if (mips_cpreturn_register
== -1)
15463 ex_off
.X_op
= O_constant
;
15464 ex_off
.X_add_symbol
= NULL
;
15465 ex_off
.X_op_symbol
= NULL
;
15466 ex_off
.X_add_number
= mips_cpreturn_offset
;
15468 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15469 BFD_RELOC_LO16
, SP
);
15472 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15473 mips_gp_register
, 0);
15475 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15477 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15478 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15481 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15482 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15483 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15486 mips_gp_register
, reg1
);
15492 ex
.X_op
= O_symbol
;
15493 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15494 ex
.X_op_symbol
= NULL
;
15495 ex
.X_add_number
= 0;
15497 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15498 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15500 macro_build_lui (&ex
, mips_gp_register
);
15501 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15502 mips_gp_register
, BFD_RELOC_LO16
);
15507 mips_assembling_insn
= FALSE
;
15508 demand_empty_rest_of_line ();
15512 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15514 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15515 .cplocal is ignored. */
15516 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15522 if (mips_opts
.mips16
)
15524 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15525 ignore_rest_of_line ();
15529 mips_gp_register
= tc_get_register (0);
15530 demand_empty_rest_of_line ();
15533 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15534 offset from $sp. The offset is remembered, and after making a PIC
15535 call $gp is restored from that location. */
15538 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15542 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15543 .cprestore is ignored. */
15544 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15550 if (mips_opts
.mips16
)
15552 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15553 ignore_rest_of_line ();
15557 mips_cprestore_offset
= get_absolute_expression ();
15558 mips_cprestore_valid
= 1;
15560 ex
.X_op
= O_constant
;
15561 ex
.X_add_symbol
= NULL
;
15562 ex
.X_op_symbol
= NULL
;
15563 ex
.X_add_number
= mips_cprestore_offset
;
15565 mips_mark_labels ();
15566 mips_assembling_insn
= TRUE
;
15569 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15570 SP
, HAVE_64BIT_ADDRESSES
);
15573 mips_assembling_insn
= FALSE
;
15574 demand_empty_rest_of_line ();
15577 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15578 was given in the preceding .cpsetup, it results in:
15579 ld $gp, offset($sp)
15581 If a register $reg2 was given there, it results in:
15582 daddu $gp, $reg2, $0 */
15585 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15589 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15590 We also need NewABI support. */
15591 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15597 if (mips_opts
.mips16
)
15599 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15600 ignore_rest_of_line ();
15604 mips_mark_labels ();
15605 mips_assembling_insn
= TRUE
;
15608 if (mips_cpreturn_register
== -1)
15610 ex
.X_op
= O_constant
;
15611 ex
.X_add_symbol
= NULL
;
15612 ex
.X_op_symbol
= NULL
;
15613 ex
.X_add_number
= mips_cpreturn_offset
;
15615 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15618 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15619 mips_cpreturn_register
, 0);
15622 mips_assembling_insn
= FALSE
;
15623 demand_empty_rest_of_line ();
15626 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15627 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15628 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15629 debug information or MIPS16 TLS. */
15632 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15633 bfd_reloc_code_real_type rtype
)
15640 if (ex
.X_op
!= O_symbol
)
15642 as_bad (_("Unsupported use of %s"), dirstr
);
15643 ignore_rest_of_line ();
15646 p
= frag_more (bytes
);
15647 md_number_to_chars (p
, 0, bytes
);
15648 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15649 demand_empty_rest_of_line ();
15650 mips_clear_insn_labels ();
15653 /* Handle .dtprelword. */
15656 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15658 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15661 /* Handle .dtpreldword. */
15664 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15666 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15669 /* Handle .tprelword. */
15672 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15674 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15677 /* Handle .tpreldword. */
15680 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15682 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15685 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15686 code. It sets the offset to use in gp_rel relocations. */
15689 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15691 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15692 We also need NewABI support. */
15693 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15699 mips_gprel_offset
= get_absolute_expression ();
15701 demand_empty_rest_of_line ();
15704 /* Handle the .gpword pseudo-op. This is used when generating PIC
15705 code. It generates a 32 bit GP relative reloc. */
15708 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15710 segment_info_type
*si
;
15711 struct insn_label_list
*l
;
15715 /* When not generating PIC code, this is treated as .word. */
15716 if (mips_pic
!= SVR4_PIC
)
15722 si
= seg_info (now_seg
);
15723 l
= si
->label_list
;
15724 mips_emit_delays ();
15726 mips_align (2, 0, l
);
15729 mips_clear_insn_labels ();
15731 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15733 as_bad (_("Unsupported use of .gpword"));
15734 ignore_rest_of_line ();
15738 md_number_to_chars (p
, 0, 4);
15739 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15740 BFD_RELOC_GPREL32
);
15742 demand_empty_rest_of_line ();
15746 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15748 segment_info_type
*si
;
15749 struct insn_label_list
*l
;
15753 /* When not generating PIC code, this is treated as .dword. */
15754 if (mips_pic
!= SVR4_PIC
)
15760 si
= seg_info (now_seg
);
15761 l
= si
->label_list
;
15762 mips_emit_delays ();
15764 mips_align (3, 0, l
);
15767 mips_clear_insn_labels ();
15769 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15771 as_bad (_("Unsupported use of .gpdword"));
15772 ignore_rest_of_line ();
15776 md_number_to_chars (p
, 0, 8);
15777 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15778 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15780 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15781 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15782 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15784 demand_empty_rest_of_line ();
15787 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15788 tables. It generates a R_MIPS_EH reloc. */
15791 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15796 mips_emit_delays ();
15799 mips_clear_insn_labels ();
15801 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15803 as_bad (_("Unsupported use of .ehword"));
15804 ignore_rest_of_line ();
15808 md_number_to_chars (p
, 0, 4);
15809 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15810 BFD_RELOC_MIPS_EH
);
15812 demand_empty_rest_of_line ();
15815 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15816 tables in SVR4 PIC code. */
15819 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15823 /* This is ignored when not generating SVR4 PIC code. */
15824 if (mips_pic
!= SVR4_PIC
)
15830 mips_mark_labels ();
15831 mips_assembling_insn
= TRUE
;
15833 /* Add $gp to the register named as an argument. */
15835 reg
= tc_get_register (0);
15836 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15839 mips_assembling_insn
= FALSE
;
15840 demand_empty_rest_of_line ();
15843 /* Handle the .insn pseudo-op. This marks instruction labels in
15844 mips16/micromips mode. This permits the linker to handle them specially,
15845 such as generating jalx instructions when needed. We also make
15846 them odd for the duration of the assembly, in order to generate the
15847 right sort of code. We will make them even in the adjust_symtab
15848 routine, while leaving them marked. This is convenient for the
15849 debugger and the disassembler. The linker knows to make them odd
15853 s_insn (int ignore ATTRIBUTE_UNUSED
)
15855 mips_mark_labels ();
15857 demand_empty_rest_of_line ();
15860 /* Handle the .nan pseudo-op. */
15863 s_nan (int ignore ATTRIBUTE_UNUSED
)
15865 static const char str_legacy
[] = "legacy";
15866 static const char str_2008
[] = "2008";
15869 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15871 if (i
== sizeof (str_2008
) - 1
15872 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15873 mips_flag_nan2008
= TRUE
;
15874 else if (i
== sizeof (str_legacy
) - 1
15875 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15876 mips_flag_nan2008
= FALSE
;
15878 as_bad (_("Bad .nan directive"));
15880 input_line_pointer
+= i
;
15881 demand_empty_rest_of_line ();
15884 /* Handle a .stab[snd] directive. Ideally these directives would be
15885 implemented in a transparent way, so that removing them would not
15886 have any effect on the generated instructions. However, s_stab
15887 internally changes the section, so in practice we need to decide
15888 now whether the preceding label marks compressed code. We do not
15889 support changing the compression mode of a label after a .stab*
15890 directive, such as in:
15896 so the current mode wins. */
15899 s_mips_stab (int type
)
15901 mips_mark_labels ();
15905 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15908 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15915 name
= input_line_pointer
;
15916 c
= get_symbol_end ();
15917 symbolP
= symbol_find_or_make (name
);
15918 S_SET_WEAK (symbolP
);
15919 *input_line_pointer
= c
;
15921 SKIP_WHITESPACE ();
15923 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15925 if (S_IS_DEFINED (symbolP
))
15927 as_bad (_("ignoring attempt to redefine symbol %s"),
15928 S_GET_NAME (symbolP
));
15929 ignore_rest_of_line ();
15933 if (*input_line_pointer
== ',')
15935 ++input_line_pointer
;
15936 SKIP_WHITESPACE ();
15940 if (exp
.X_op
!= O_symbol
)
15942 as_bad (_("bad .weakext directive"));
15943 ignore_rest_of_line ();
15946 symbol_set_value_expression (symbolP
, &exp
);
15949 demand_empty_rest_of_line ();
15952 /* Parse a register string into a number. Called from the ECOFF code
15953 to parse .frame. The argument is non-zero if this is the frame
15954 register, so that we can record it in mips_frame_reg. */
15957 tc_get_register (int frame
)
15961 SKIP_WHITESPACE ();
15962 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15966 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15967 mips_frame_reg_valid
= 1;
15968 mips_cprestore_valid
= 0;
15974 md_section_align (asection
*seg
, valueT addr
)
15976 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15978 /* We don't need to align ELF sections to the full alignment.
15979 However, Irix 5 may prefer that we align them at least to a 16
15980 byte boundary. We don't bother to align the sections if we
15981 are targeted for an embedded system. */
15982 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15987 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15990 /* Utility routine, called from above as well. If called while the
15991 input file is still being read, it's only an approximation. (For
15992 example, a symbol may later become defined which appeared to be
15993 undefined earlier.) */
15996 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16001 if (g_switch_value
> 0)
16003 const char *symname
;
16006 /* Find out whether this symbol can be referenced off the $gp
16007 register. It can be if it is smaller than the -G size or if
16008 it is in the .sdata or .sbss section. Certain symbols can
16009 not be referenced off the $gp, although it appears as though
16011 symname
= S_GET_NAME (sym
);
16012 if (symname
!= (const char *) NULL
16013 && (strcmp (symname
, "eprol") == 0
16014 || strcmp (symname
, "etext") == 0
16015 || strcmp (symname
, "_gp") == 0
16016 || strcmp (symname
, "edata") == 0
16017 || strcmp (symname
, "_fbss") == 0
16018 || strcmp (symname
, "_fdata") == 0
16019 || strcmp (symname
, "_ftext") == 0
16020 || strcmp (symname
, "end") == 0
16021 || strcmp (symname
, "_gp_disp") == 0))
16023 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16025 #ifndef NO_ECOFF_DEBUGGING
16026 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16027 && (symbol_get_obj (sym
)->ecoff_extern_size
16028 <= g_switch_value
))
16030 /* We must defer this decision until after the whole
16031 file has been read, since there might be a .extern
16032 after the first use of this symbol. */
16033 || (before_relaxing
16034 #ifndef NO_ECOFF_DEBUGGING
16035 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16037 && S_GET_VALUE (sym
) == 0)
16038 || (S_GET_VALUE (sym
) != 0
16039 && S_GET_VALUE (sym
) <= g_switch_value
)))
16043 const char *segname
;
16045 segname
= segment_name (S_GET_SEGMENT (sym
));
16046 gas_assert (strcmp (segname
, ".lit8") != 0
16047 && strcmp (segname
, ".lit4") != 0);
16048 change
= (strcmp (segname
, ".sdata") != 0
16049 && strcmp (segname
, ".sbss") != 0
16050 && strncmp (segname
, ".sdata.", 7) != 0
16051 && strncmp (segname
, ".sbss.", 6) != 0
16052 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16053 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16058 /* We are not optimizing for the $gp register. */
16063 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16066 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16070 /* Handle the case of a symbol equated to another symbol. */
16071 while (symbol_equated_reloc_p (sym
))
16075 /* It's possible to get a loop here in a badly written program. */
16076 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16082 if (symbol_section_p (sym
))
16085 symsec
= S_GET_SEGMENT (sym
);
16087 /* This must duplicate the test in adjust_reloc_syms. */
16088 return (!bfd_is_und_section (symsec
)
16089 && !bfd_is_abs_section (symsec
)
16090 && !bfd_is_com_section (symsec
)
16091 && !s_is_linkonce (sym
, segtype
)
16092 /* A global or weak symbol is treated as external. */
16093 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16097 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16098 extended opcode. SEC is the section the frag is in. */
16101 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16104 const struct mips_int_operand
*operand
;
16109 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16111 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16114 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16115 operand
= mips16_immed_operand (type
, FALSE
);
16117 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16118 val
= S_GET_VALUE (fragp
->fr_symbol
);
16119 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16121 if (operand
->root
.type
== OP_PCREL
)
16123 const struct mips_pcrel_operand
*pcrel_op
;
16127 /* We won't have the section when we are called from
16128 mips_relax_frag. However, we will always have been called
16129 from md_estimate_size_before_relax first. If this is a
16130 branch to a different section, we mark it as such. If SEC is
16131 NULL, and the frag is not marked, then it must be a branch to
16132 the same section. */
16133 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16136 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16141 /* Must have been called from md_estimate_size_before_relax. */
16144 fragp
->fr_subtype
=
16145 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16147 /* FIXME: We should support this, and let the linker
16148 catch branches and loads that are out of range. */
16149 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16150 _("unsupported PC relative reference to different section"));
16154 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16155 /* Assume non-extended on the first relaxation pass.
16156 The address we have calculated will be bogus if this is
16157 a forward branch to another frag, as the forward frag
16158 will have fr_address == 0. */
16162 /* In this case, we know for sure that the symbol fragment is in
16163 the same section. If the relax_marker of the symbol fragment
16164 differs from the relax_marker of this fragment, we have not
16165 yet adjusted the symbol fragment fr_address. We want to add
16166 in STRETCH in order to get a better estimate of the address.
16167 This particularly matters because of the shift bits. */
16169 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16173 /* Adjust stretch for any alignment frag. Note that if have
16174 been expanding the earlier code, the symbol may be
16175 defined in what appears to be an earlier frag. FIXME:
16176 This doesn't handle the fr_subtype field, which specifies
16177 a maximum number of bytes to skip when doing an
16179 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16181 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16184 stretch
= - ((- stretch
)
16185 & ~ ((1 << (int) f
->fr_offset
) - 1));
16187 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16196 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16198 /* The base address rules are complicated. The base address of
16199 a branch is the following instruction. The base address of a
16200 PC relative load or add is the instruction itself, but if it
16201 is in a delay slot (in which case it can not be extended) use
16202 the address of the instruction whose delay slot it is in. */
16203 if (pcrel_op
->include_isa_bit
)
16207 /* If we are currently assuming that this frag should be
16208 extended, then, the current address is two bytes
16210 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16213 /* Ignore the low bit in the target, since it will be set
16214 for a text label. */
16217 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16219 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16222 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16224 /* If any of the shifted bits are set, we must use an extended
16225 opcode. If the address depends on the size of this
16226 instruction, this can lead to a loop, so we arrange to always
16227 use an extended opcode. We only check this when we are in
16228 the main relaxation loop, when SEC is NULL. */
16229 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16231 fragp
->fr_subtype
=
16232 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16236 /* If we are about to mark a frag as extended because the value
16237 is precisely the next value above maxtiny, then there is a
16238 chance of an infinite loop as in the following code:
16243 In this case when the la is extended, foo is 0x3fc bytes
16244 away, so the la can be shrunk, but then foo is 0x400 away, so
16245 the la must be extended. To avoid this loop, we mark the
16246 frag as extended if it was small, and is about to become
16247 extended with the next value above maxtiny. */
16248 maxtiny
= mips_int_operand_max (operand
);
16249 if (val
== maxtiny
+ (1 << operand
->shift
)
16250 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16253 fragp
->fr_subtype
=
16254 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16258 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16259 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16261 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16264 /* Compute the length of a branch sequence, and adjust the
16265 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16266 worst-case length is computed, with UPDATE being used to indicate
16267 whether an unconditional (-1), branch-likely (+1) or regular (0)
16268 branch is to be computed. */
16270 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16272 bfd_boolean toofar
;
16276 && S_IS_DEFINED (fragp
->fr_symbol
)
16277 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16282 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16284 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16288 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16291 /* If the symbol is not defined or it's in a different segment,
16292 assume the user knows what's going on and emit a short
16298 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16300 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16301 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16302 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16303 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16309 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16312 if (mips_pic
!= NO_PIC
)
16314 /* Additional space for PIC loading of target address. */
16316 if (mips_opts
.isa
== ISA_MIPS1
)
16317 /* Additional space for $at-stabilizing nop. */
16321 /* If branch is conditional. */
16322 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16329 /* Compute the length of a branch sequence, and adjust the
16330 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16331 worst-case length is computed, with UPDATE being used to indicate
16332 whether an unconditional (-1), or regular (0) branch is to be
16336 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16338 bfd_boolean toofar
;
16342 && S_IS_DEFINED (fragp
->fr_symbol
)
16343 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16348 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16349 /* Ignore the low bit in the target, since it will be set
16350 for a text label. */
16351 if ((val
& 1) != 0)
16354 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16358 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16361 /* If the symbol is not defined or it's in a different segment,
16362 assume the user knows what's going on and emit a short
16368 if (fragp
&& update
16369 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16370 fragp
->fr_subtype
= (toofar
16371 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16372 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16377 bfd_boolean compact_known
= fragp
!= NULL
;
16378 bfd_boolean compact
= FALSE
;
16379 bfd_boolean uncond
;
16382 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16384 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16386 uncond
= update
< 0;
16388 /* If label is out of range, we turn branch <br>:
16390 <br> label # 4 bytes
16396 nop # 2 bytes if compact && !PIC
16399 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16402 /* If assembling PIC code, we further turn:
16408 lw/ld at, %got(label)(gp) # 4 bytes
16409 d/addiu at, %lo(label) # 4 bytes
16412 if (mips_pic
!= NO_PIC
)
16415 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16417 <brneg> 0f # 4 bytes
16418 nop # 2 bytes if !compact
16421 length
+= (compact_known
&& compact
) ? 4 : 6;
16427 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16428 bit accordingly. */
16431 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16433 bfd_boolean toofar
;
16436 && S_IS_DEFINED (fragp
->fr_symbol
)
16437 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16443 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16444 /* Ignore the low bit in the target, since it will be set
16445 for a text label. */
16446 if ((val
& 1) != 0)
16449 /* Assume this is a 2-byte branch. */
16450 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16452 /* We try to avoid the infinite loop by not adding 2 more bytes for
16457 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16459 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16460 else if (type
== 'E')
16461 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16466 /* If the symbol is not defined or it's in a different segment,
16467 we emit a normal 32-bit branch. */
16470 if (fragp
&& update
16471 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16473 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16474 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16482 /* Estimate the size of a frag before relaxing. Unless this is the
16483 mips16, we are not really relaxing here, and the final size is
16484 encoded in the subtype information. For the mips16, we have to
16485 decide whether we are using an extended opcode or not. */
16488 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16492 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16495 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16497 return fragp
->fr_var
;
16500 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16501 /* We don't want to modify the EXTENDED bit here; it might get us
16502 into infinite loops. We change it only in mips_relax_frag(). */
16503 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16505 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16509 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16510 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16511 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16512 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16513 fragp
->fr_var
= length
;
16518 if (mips_pic
== NO_PIC
)
16519 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16520 else if (mips_pic
== SVR4_PIC
)
16521 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16522 else if (mips_pic
== VXWORKS_PIC
)
16523 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16530 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16531 return -RELAX_FIRST (fragp
->fr_subtype
);
16534 return -RELAX_SECOND (fragp
->fr_subtype
);
16537 /* This is called to see whether a reloc against a defined symbol
16538 should be converted into a reloc against a section. */
16541 mips_fix_adjustable (fixS
*fixp
)
16543 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16544 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16547 if (fixp
->fx_addsy
== NULL
)
16550 /* If symbol SYM is in a mergeable section, relocations of the form
16551 SYM + 0 can usually be made section-relative. The mergeable data
16552 is then identified by the section offset rather than by the symbol.
16554 However, if we're generating REL LO16 relocations, the offset is split
16555 between the LO16 and parterning high part relocation. The linker will
16556 need to recalculate the complete offset in order to correctly identify
16559 The linker has traditionally not looked for the parterning high part
16560 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16561 placed anywhere. Rather than break backwards compatibility by changing
16562 this, it seems better not to force the issue, and instead keep the
16563 original symbol. This will work with either linker behavior. */
16564 if ((lo16_reloc_p (fixp
->fx_r_type
)
16565 || reloc_needs_lo_p (fixp
->fx_r_type
))
16566 && HAVE_IN_PLACE_ADDENDS
16567 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16570 /* There is no place to store an in-place offset for JALR relocations.
16571 Likewise an in-range offset of limited PC-relative relocations may
16572 overflow the in-place relocatable field if recalculated against the
16573 start address of the symbol's containing section. */
16574 if (HAVE_IN_PLACE_ADDENDS
16575 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16576 || jalr_reloc_p (fixp
->fx_r_type
)))
16579 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16580 to a floating-point stub. The same is true for non-R_MIPS16_26
16581 relocations against MIPS16 functions; in this case, the stub becomes
16582 the function's canonical address.
16584 Floating-point stubs are stored in unique .mips16.call.* or
16585 .mips16.fn.* sections. If a stub T for function F is in section S,
16586 the first relocation in section S must be against F; this is how the
16587 linker determines the target function. All relocations that might
16588 resolve to T must also be against F. We therefore have the following
16589 restrictions, which are given in an intentionally-redundant way:
16591 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16594 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16595 if that stub might be used.
16597 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16600 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16601 that stub might be used.
16603 There is a further restriction:
16605 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16606 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16607 targets with in-place addends; the relocation field cannot
16608 encode the low bit.
16610 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16611 against a MIPS16 symbol. We deal with (5) by by not reducing any
16612 such relocations on REL targets.
16614 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16615 relocation against some symbol R, no relocation against R may be
16616 reduced. (Note that this deals with (2) as well as (1) because
16617 relocations against global symbols will never be reduced on ELF
16618 targets.) This approach is a little simpler than trying to detect
16619 stub sections, and gives the "all or nothing" per-symbol consistency
16620 that we have for MIPS16 symbols. */
16621 if (fixp
->fx_subsy
== NULL
16622 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16623 || *symbol_get_tc (fixp
->fx_addsy
)
16624 || (HAVE_IN_PLACE_ADDENDS
16625 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16626 && jmp_reloc_p (fixp
->fx_r_type
))))
16632 /* Translate internal representation of relocation info to BFD target
16636 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16638 static arelent
*retval
[4];
16640 bfd_reloc_code_real_type code
;
16642 memset (retval
, 0, sizeof(retval
));
16643 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16644 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16645 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16646 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16648 if (fixp
->fx_pcrel
)
16650 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16651 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16652 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16653 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16654 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16656 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16657 Relocations want only the symbol offset. */
16658 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16661 reloc
->addend
= fixp
->fx_addnumber
;
16663 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16664 entry to be used in the relocation's section offset. */
16665 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16667 reloc
->address
= reloc
->addend
;
16671 code
= fixp
->fx_r_type
;
16673 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16674 if (reloc
->howto
== NULL
)
16676 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16677 _("Can not represent %s relocation in this object file format"),
16678 bfd_get_reloc_code_name (code
));
16685 /* Relax a machine dependent frag. This returns the amount by which
16686 the current size of the frag should change. */
16689 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16691 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16693 offsetT old_var
= fragp
->fr_var
;
16695 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16697 return fragp
->fr_var
- old_var
;
16700 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16702 offsetT old_var
= fragp
->fr_var
;
16703 offsetT new_var
= 4;
16705 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16706 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16707 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16708 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16709 fragp
->fr_var
= new_var
;
16711 return new_var
- old_var
;
16714 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16717 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16719 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16721 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16726 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16728 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16735 /* Convert a machine dependent frag. */
16738 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16740 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16743 unsigned long insn
;
16747 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16748 insn
= read_insn (buf
);
16750 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16752 /* We generate a fixup instead of applying it right now
16753 because, if there are linker relaxations, we're going to
16754 need the relocations. */
16755 exp
.X_op
= O_symbol
;
16756 exp
.X_add_symbol
= fragp
->fr_symbol
;
16757 exp
.X_add_number
= fragp
->fr_offset
;
16759 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16760 BFD_RELOC_16_PCREL_S2
);
16761 fixp
->fx_file
= fragp
->fr_file
;
16762 fixp
->fx_line
= fragp
->fr_line
;
16764 buf
= write_insn (buf
, insn
);
16770 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16771 _("Relaxed out-of-range branch into a jump"));
16773 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16776 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16778 /* Reverse the branch. */
16779 switch ((insn
>> 28) & 0xf)
16782 /* bc[0-3][tf]l? instructions can have the condition
16783 reversed by tweaking a single TF bit, and their
16784 opcodes all have 0x4???????. */
16785 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16786 insn
^= 0x00010000;
16790 /* bltz 0x04000000 bgez 0x04010000
16791 bltzal 0x04100000 bgezal 0x04110000 */
16792 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16793 insn
^= 0x00010000;
16797 /* beq 0x10000000 bne 0x14000000
16798 blez 0x18000000 bgtz 0x1c000000 */
16799 insn
^= 0x04000000;
16807 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16809 /* Clear the and-link bit. */
16810 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16812 /* bltzal 0x04100000 bgezal 0x04110000
16813 bltzall 0x04120000 bgezall 0x04130000 */
16814 insn
&= ~0x00100000;
16817 /* Branch over the branch (if the branch was likely) or the
16818 full jump (not likely case). Compute the offset from the
16819 current instruction to branch to. */
16820 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16824 /* How many bytes in instructions we've already emitted? */
16825 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16826 /* How many bytes in instructions from here to the end? */
16827 i
= fragp
->fr_var
- i
;
16829 /* Convert to instruction count. */
16831 /* Branch counts from the next instruction. */
16834 /* Branch over the jump. */
16835 buf
= write_insn (buf
, insn
);
16838 buf
= write_insn (buf
, 0);
16840 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16842 /* beql $0, $0, 2f */
16844 /* Compute the PC offset from the current instruction to
16845 the end of the variable frag. */
16846 /* How many bytes in instructions we've already emitted? */
16847 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16848 /* How many bytes in instructions from here to the end? */
16849 i
= fragp
->fr_var
- i
;
16850 /* Convert to instruction count. */
16852 /* Don't decrement i, because we want to branch over the
16856 buf
= write_insn (buf
, insn
);
16857 buf
= write_insn (buf
, 0);
16861 if (mips_pic
== NO_PIC
)
16864 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16865 ? 0x0c000000 : 0x08000000);
16866 exp
.X_op
= O_symbol
;
16867 exp
.X_add_symbol
= fragp
->fr_symbol
;
16868 exp
.X_add_number
= fragp
->fr_offset
;
16870 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16871 FALSE
, BFD_RELOC_MIPS_JMP
);
16872 fixp
->fx_file
= fragp
->fr_file
;
16873 fixp
->fx_line
= fragp
->fr_line
;
16875 buf
= write_insn (buf
, insn
);
16879 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16881 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16882 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16883 insn
|= at
<< OP_SH_RT
;
16884 exp
.X_op
= O_symbol
;
16885 exp
.X_add_symbol
= fragp
->fr_symbol
;
16886 exp
.X_add_number
= fragp
->fr_offset
;
16888 if (fragp
->fr_offset
)
16890 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16891 exp
.X_add_number
= 0;
16894 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16895 FALSE
, BFD_RELOC_MIPS_GOT16
);
16896 fixp
->fx_file
= fragp
->fr_file
;
16897 fixp
->fx_line
= fragp
->fr_line
;
16899 buf
= write_insn (buf
, insn
);
16901 if (mips_opts
.isa
== ISA_MIPS1
)
16903 buf
= write_insn (buf
, 0);
16905 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16906 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16907 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16909 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16910 FALSE
, BFD_RELOC_LO16
);
16911 fixp
->fx_file
= fragp
->fr_file
;
16912 fixp
->fx_line
= fragp
->fr_line
;
16914 buf
= write_insn (buf
, insn
);
16917 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16921 insn
|= at
<< OP_SH_RS
;
16923 buf
= write_insn (buf
, insn
);
16927 fragp
->fr_fix
+= fragp
->fr_var
;
16928 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16932 /* Relax microMIPS branches. */
16933 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16935 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16936 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16937 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16938 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16939 bfd_boolean short_ds
;
16940 unsigned long insn
;
16944 exp
.X_op
= O_symbol
;
16945 exp
.X_add_symbol
= fragp
->fr_symbol
;
16946 exp
.X_add_number
= fragp
->fr_offset
;
16948 fragp
->fr_fix
+= fragp
->fr_var
;
16950 /* Handle 16-bit branches that fit or are forced to fit. */
16951 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16953 /* We generate a fixup instead of applying it right now,
16954 because if there is linker relaxation, we're going to
16955 need the relocations. */
16957 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16958 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16959 else if (type
== 'E')
16960 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16961 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16965 fixp
->fx_file
= fragp
->fr_file
;
16966 fixp
->fx_line
= fragp
->fr_line
;
16968 /* These relocations can have an addend that won't fit in
16970 fixp
->fx_no_overflow
= 1;
16975 /* Handle 32-bit branches that fit or are forced to fit. */
16976 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16977 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16979 /* We generate a fixup instead of applying it right now,
16980 because if there is linker relaxation, we're going to
16981 need the relocations. */
16982 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16983 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16984 fixp
->fx_file
= fragp
->fr_file
;
16985 fixp
->fx_line
= fragp
->fr_line
;
16991 /* Relax 16-bit branches to 32-bit branches. */
16994 insn
= read_compressed_insn (buf
, 2);
16996 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16997 insn
= 0x94000000; /* beq */
16998 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17000 unsigned long regno
;
17002 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17003 regno
= micromips_to_32_reg_d_map
[regno
];
17004 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17005 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17010 /* Nothing else to do, just write it out. */
17011 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17012 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17014 buf
= write_compressed_insn (buf
, insn
, 4);
17015 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17020 insn
= read_compressed_insn (buf
, 4);
17022 /* Relax 32-bit branches to a sequence of instructions. */
17023 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17024 _("Relaxed out-of-range branch into a jump"));
17026 /* Set the short-delay-slot bit. */
17027 short_ds
= al
&& (insn
& 0x02000000) != 0;
17029 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17033 /* Reverse the branch. */
17034 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17035 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17036 insn
^= 0x20000000;
17037 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17038 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17039 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17040 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17041 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17042 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17043 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17044 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17045 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17046 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17047 insn
^= 0x00400000;
17048 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17049 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17050 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17051 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17052 insn
^= 0x00200000;
17058 /* Clear the and-link and short-delay-slot bits. */
17059 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17061 /* bltzal 0x40200000 bgezal 0x40600000 */
17062 /* bltzals 0x42200000 bgezals 0x42600000 */
17063 insn
&= ~0x02200000;
17066 /* Make a label at the end for use with the branch. */
17067 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17068 micromips_label_inc ();
17069 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17072 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17073 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17074 fixp
->fx_file
= fragp
->fr_file
;
17075 fixp
->fx_line
= fragp
->fr_line
;
17077 /* Branch over the jump. */
17078 buf
= write_compressed_insn (buf
, insn
, 4);
17081 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17084 if (mips_pic
== NO_PIC
)
17086 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17088 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17089 insn
= al
? jal
: 0xd4000000;
17091 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17092 BFD_RELOC_MICROMIPS_JMP
);
17093 fixp
->fx_file
= fragp
->fr_file
;
17094 fixp
->fx_line
= fragp
->fr_line
;
17096 buf
= write_compressed_insn (buf
, insn
, 4);
17099 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17103 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17104 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17105 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17107 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17108 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17109 insn
|= at
<< MICROMIPSOP_SH_RT
;
17111 if (exp
.X_add_number
)
17113 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17114 exp
.X_add_number
= 0;
17117 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17118 BFD_RELOC_MICROMIPS_GOT16
);
17119 fixp
->fx_file
= fragp
->fr_file
;
17120 fixp
->fx_line
= fragp
->fr_line
;
17122 buf
= write_compressed_insn (buf
, insn
, 4);
17124 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17125 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17126 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17128 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17129 BFD_RELOC_MICROMIPS_LO16
);
17130 fixp
->fx_file
= fragp
->fr_file
;
17131 fixp
->fx_line
= fragp
->fr_line
;
17133 buf
= write_compressed_insn (buf
, insn
, 4);
17135 /* jr/jrc/jalr/jalrs $at */
17136 insn
= al
? jalr
: jr
;
17137 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17139 buf
= write_compressed_insn (buf
, insn
, 2);
17142 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17146 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17149 const struct mips_int_operand
*operand
;
17152 unsigned int user_length
, length
;
17153 unsigned long insn
;
17156 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17157 operand
= mips16_immed_operand (type
, FALSE
);
17159 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17160 val
= resolve_symbol_value (fragp
->fr_symbol
);
17161 if (operand
->root
.type
== OP_PCREL
)
17163 const struct mips_pcrel_operand
*pcrel_op
;
17166 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17167 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17169 /* The rules for the base address of a PC relative reloc are
17170 complicated; see mips16_extended_frag. */
17171 if (pcrel_op
->include_isa_bit
)
17176 /* Ignore the low bit in the target, since it will be
17177 set for a text label. */
17180 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17182 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17185 addr
&= -(1 << pcrel_op
->align_log2
);
17188 /* Make sure the section winds up with the alignment we have
17190 if (operand
->shift
> 0)
17191 record_alignment (asec
, operand
->shift
);
17195 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17196 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17197 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17198 _("extended instruction in delay slot"));
17200 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17202 insn
= read_compressed_insn (buf
, 2);
17204 insn
|= MIPS16_EXTEND
;
17206 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17208 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17213 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17214 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17216 length
= (ext
? 4 : 2);
17217 gas_assert (mips16_opcode_length (insn
) == length
);
17218 write_compressed_insn (buf
, insn
, length
);
17219 fragp
->fr_fix
+= length
;
17223 relax_substateT subtype
= fragp
->fr_subtype
;
17224 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17225 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17229 first
= RELAX_FIRST (subtype
);
17230 second
= RELAX_SECOND (subtype
);
17231 fixp
= (fixS
*) fragp
->fr_opcode
;
17233 /* If the delay slot chosen does not match the size of the instruction,
17234 then emit a warning. */
17235 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17236 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17241 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17242 | RELAX_DELAY_SLOT_SIZE_FIRST
17243 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17244 msg
= macro_warning (s
);
17246 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17250 /* Possibly emit a warning if we've chosen the longer option. */
17251 if (use_second
== second_longer
)
17257 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17258 msg
= macro_warning (s
);
17260 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17264 /* Go through all the fixups for the first sequence. Disable them
17265 (by marking them as done) if we're going to use the second
17266 sequence instead. */
17268 && fixp
->fx_frag
== fragp
17269 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17271 if (subtype
& RELAX_USE_SECOND
)
17273 fixp
= fixp
->fx_next
;
17276 /* Go through the fixups for the second sequence. Disable them if
17277 we're going to use the first sequence, otherwise adjust their
17278 addresses to account for the relaxation. */
17279 while (fixp
&& fixp
->fx_frag
== fragp
)
17281 if (subtype
& RELAX_USE_SECOND
)
17282 fixp
->fx_where
-= first
;
17285 fixp
= fixp
->fx_next
;
17288 /* Now modify the frag contents. */
17289 if (subtype
& RELAX_USE_SECOND
)
17293 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17294 memmove (start
, start
+ first
, second
);
17295 fragp
->fr_fix
-= first
;
17298 fragp
->fr_fix
-= second
;
17302 /* This function is called after the relocs have been generated.
17303 We've been storing mips16 text labels as odd. Here we convert them
17304 back to even for the convenience of the debugger. */
17307 mips_frob_file_after_relocs (void)
17310 unsigned int count
, i
;
17312 syms
= bfd_get_outsymbols (stdoutput
);
17313 count
= bfd_get_symcount (stdoutput
);
17314 for (i
= 0; i
< count
; i
++, syms
++)
17315 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17316 && ((*syms
)->value
& 1) != 0)
17318 (*syms
)->value
&= ~1;
17319 /* If the symbol has an odd size, it was probably computed
17320 incorrectly, so adjust that as well. */
17321 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17322 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17326 /* This function is called whenever a label is defined, including fake
17327 labels instantiated off the dot special symbol. It is used when
17328 handling branch delays; if a branch has a label, we assume we cannot
17329 move it. This also bumps the value of the symbol by 1 in compressed
17333 mips_record_label (symbolS
*sym
)
17335 segment_info_type
*si
= seg_info (now_seg
);
17336 struct insn_label_list
*l
;
17338 if (free_insn_labels
== NULL
)
17339 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17342 l
= free_insn_labels
;
17343 free_insn_labels
= l
->next
;
17347 l
->next
= si
->label_list
;
17348 si
->label_list
= l
;
17351 /* This function is called as tc_frob_label() whenever a label is defined
17352 and adds a DWARF-2 record we only want for true labels. */
17355 mips_define_label (symbolS
*sym
)
17357 mips_record_label (sym
);
17358 dwarf2_emit_label (sym
);
17361 /* This function is called by tc_new_dot_label whenever a new dot symbol
17365 mips_add_dot_label (symbolS
*sym
)
17367 mips_record_label (sym
);
17368 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17369 mips_compressed_mark_label (sym
);
17372 /* Some special processing for a MIPS ELF file. */
17375 mips_elf_final_processing (void)
17377 /* Write out the register information. */
17378 if (mips_abi
!= N64_ABI
)
17382 s
.ri_gprmask
= mips_gprmask
;
17383 s
.ri_cprmask
[0] = mips_cprmask
[0];
17384 s
.ri_cprmask
[1] = mips_cprmask
[1];
17385 s
.ri_cprmask
[2] = mips_cprmask
[2];
17386 s
.ri_cprmask
[3] = mips_cprmask
[3];
17387 /* The gp_value field is set by the MIPS ELF backend. */
17389 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17390 ((Elf32_External_RegInfo
*)
17391 mips_regmask_frag
));
17395 Elf64_Internal_RegInfo s
;
17397 s
.ri_gprmask
= mips_gprmask
;
17399 s
.ri_cprmask
[0] = mips_cprmask
[0];
17400 s
.ri_cprmask
[1] = mips_cprmask
[1];
17401 s
.ri_cprmask
[2] = mips_cprmask
[2];
17402 s
.ri_cprmask
[3] = mips_cprmask
[3];
17403 /* The gp_value field is set by the MIPS ELF backend. */
17405 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17406 ((Elf64_External_RegInfo
*)
17407 mips_regmask_frag
));
17410 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17411 sort of BFD interface for this. */
17412 if (mips_any_noreorder
)
17413 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17414 if (mips_pic
!= NO_PIC
)
17416 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17420 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17422 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17423 defined at present; this might need to change in future. */
17424 if (file_ase_mips16
)
17425 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17426 if (file_ase_micromips
)
17427 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17428 if (file_ase
& ASE_MDMX
)
17429 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17431 /* Set the MIPS ELF ABI flags. */
17432 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17433 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17434 else if (mips_abi
== O64_ABI
)
17435 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17436 else if (mips_abi
== EABI_ABI
)
17438 if (!file_mips_gp32
)
17439 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17441 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17443 else if (mips_abi
== N32_ABI
)
17444 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17446 /* Nothing to do for N64_ABI. */
17448 if (mips_32bitmode
)
17449 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17451 if (mips_flag_nan2008
)
17452 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17454 #if 0 /* XXX FIXME */
17455 /* 32 bit code with 64 bit FP registers. */
17456 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17457 elf_elfheader (stdoutput
)->e_flags
|= ???;
17461 typedef struct proc
{
17463 symbolS
*func_end_sym
;
17464 unsigned long reg_mask
;
17465 unsigned long reg_offset
;
17466 unsigned long fpreg_mask
;
17467 unsigned long fpreg_offset
;
17468 unsigned long frame_offset
;
17469 unsigned long frame_reg
;
17470 unsigned long pc_reg
;
17473 static procS cur_proc
;
17474 static procS
*cur_proc_ptr
;
17475 static int numprocs
;
17477 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17478 as "2", and a normal nop as "0". */
17480 #define NOP_OPCODE_MIPS 0
17481 #define NOP_OPCODE_MIPS16 1
17482 #define NOP_OPCODE_MICROMIPS 2
17485 mips_nop_opcode (void)
17487 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17488 return NOP_OPCODE_MICROMIPS
;
17489 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17490 return NOP_OPCODE_MIPS16
;
17492 return NOP_OPCODE_MIPS
;
17495 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17496 32-bit microMIPS NOPs here (if applicable). */
17499 mips_handle_align (fragS
*fragp
)
17503 int bytes
, size
, excess
;
17506 if (fragp
->fr_type
!= rs_align_code
)
17509 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17511 switch (nop_opcode
)
17513 case NOP_OPCODE_MICROMIPS
:
17514 opcode
= micromips_nop32_insn
.insn_opcode
;
17517 case NOP_OPCODE_MIPS16
:
17518 opcode
= mips16_nop_insn
.insn_opcode
;
17521 case NOP_OPCODE_MIPS
:
17523 opcode
= nop_insn
.insn_opcode
;
17528 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17529 excess
= bytes
% size
;
17531 /* Handle the leading part if we're not inserting a whole number of
17532 instructions, and make it the end of the fixed part of the frag.
17533 Try to fit in a short microMIPS NOP if applicable and possible,
17534 and use zeroes otherwise. */
17535 gas_assert (excess
< 4);
17536 fragp
->fr_fix
+= excess
;
17541 /* Fall through. */
17543 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17545 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17549 /* Fall through. */
17552 /* Fall through. */
17557 md_number_to_chars (p
, opcode
, size
);
17558 fragp
->fr_var
= size
;
17562 md_obj_begin (void)
17569 /* Check for premature end, nesting errors, etc. */
17571 as_warn (_("missing .end at end of assembly"));
17580 if (*input_line_pointer
== '-')
17582 ++input_line_pointer
;
17585 if (!ISDIGIT (*input_line_pointer
))
17586 as_bad (_("expected simple number"));
17587 if (input_line_pointer
[0] == '0')
17589 if (input_line_pointer
[1] == 'x')
17591 input_line_pointer
+= 2;
17592 while (ISXDIGIT (*input_line_pointer
))
17595 val
|= hex_value (*input_line_pointer
++);
17597 return negative
? -val
: val
;
17601 ++input_line_pointer
;
17602 while (ISDIGIT (*input_line_pointer
))
17605 val
|= *input_line_pointer
++ - '0';
17607 return negative
? -val
: val
;
17610 if (!ISDIGIT (*input_line_pointer
))
17612 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17613 *input_line_pointer
, *input_line_pointer
);
17614 as_warn (_("invalid number"));
17617 while (ISDIGIT (*input_line_pointer
))
17620 val
+= *input_line_pointer
++ - '0';
17622 return negative
? -val
: val
;
17625 /* The .file directive; just like the usual .file directive, but there
17626 is an initial number which is the ECOFF file index. In the non-ECOFF
17627 case .file implies DWARF-2. */
17630 s_mips_file (int x ATTRIBUTE_UNUSED
)
17632 static int first_file_directive
= 0;
17634 if (ECOFF_DEBUGGING
)
17643 filename
= dwarf2_directive_file (0);
17645 /* Versions of GCC up to 3.1 start files with a ".file"
17646 directive even for stabs output. Make sure that this
17647 ".file" is handled. Note that you need a version of GCC
17648 after 3.1 in order to support DWARF-2 on MIPS. */
17649 if (filename
!= NULL
&& ! first_file_directive
)
17651 (void) new_logical_line (filename
, -1);
17652 s_app_file_string (filename
, 0);
17654 first_file_directive
= 1;
17658 /* The .loc directive, implying DWARF-2. */
17661 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17663 if (!ECOFF_DEBUGGING
)
17664 dwarf2_directive_loc (0);
17667 /* The .end directive. */
17670 s_mips_end (int x ATTRIBUTE_UNUSED
)
17674 /* Following functions need their own .frame and .cprestore directives. */
17675 mips_frame_reg_valid
= 0;
17676 mips_cprestore_valid
= 0;
17678 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17681 demand_empty_rest_of_line ();
17686 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17687 as_warn (_(".end not in text section"));
17691 as_warn (_(".end directive without a preceding .ent directive."));
17692 demand_empty_rest_of_line ();
17698 gas_assert (S_GET_NAME (p
));
17699 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17700 as_warn (_(".end symbol does not match .ent symbol."));
17702 if (debug_type
== DEBUG_STABS
)
17703 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17707 as_warn (_(".end directive missing or unknown symbol"));
17709 /* Create an expression to calculate the size of the function. */
17710 if (p
&& cur_proc_ptr
)
17712 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17713 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17716 exp
->X_op
= O_subtract
;
17717 exp
->X_add_symbol
= symbol_temp_new_now ();
17718 exp
->X_op_symbol
= p
;
17719 exp
->X_add_number
= 0;
17721 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17724 /* Generate a .pdr section. */
17725 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17727 segT saved_seg
= now_seg
;
17728 subsegT saved_subseg
= now_subseg
;
17732 #ifdef md_flush_pending_output
17733 md_flush_pending_output ();
17736 gas_assert (pdr_seg
);
17737 subseg_set (pdr_seg
, 0);
17739 /* Write the symbol. */
17740 exp
.X_op
= O_symbol
;
17741 exp
.X_add_symbol
= p
;
17742 exp
.X_add_number
= 0;
17743 emit_expr (&exp
, 4);
17745 fragp
= frag_more (7 * 4);
17747 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17748 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17749 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17750 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17751 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17752 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17753 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17755 subseg_set (saved_seg
, saved_subseg
);
17758 cur_proc_ptr
= NULL
;
17761 /* The .aent and .ent directives. */
17764 s_mips_ent (int aent
)
17768 symbolP
= get_symbol ();
17769 if (*input_line_pointer
== ',')
17770 ++input_line_pointer
;
17771 SKIP_WHITESPACE ();
17772 if (ISDIGIT (*input_line_pointer
)
17773 || *input_line_pointer
== '-')
17776 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17777 as_warn (_(".ent or .aent not in text section."));
17779 if (!aent
&& cur_proc_ptr
)
17780 as_warn (_("missing .end"));
17784 /* This function needs its own .frame and .cprestore directives. */
17785 mips_frame_reg_valid
= 0;
17786 mips_cprestore_valid
= 0;
17788 cur_proc_ptr
= &cur_proc
;
17789 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17791 cur_proc_ptr
->func_sym
= symbolP
;
17795 if (debug_type
== DEBUG_STABS
)
17796 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17797 S_GET_NAME (symbolP
));
17800 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17802 demand_empty_rest_of_line ();
17805 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17806 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17807 s_mips_frame is used so that we can set the PDR information correctly.
17808 We can't use the ecoff routines because they make reference to the ecoff
17809 symbol table (in the mdebug section). */
17812 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17814 if (ECOFF_DEBUGGING
)
17820 if (cur_proc_ptr
== (procS
*) NULL
)
17822 as_warn (_(".frame outside of .ent"));
17823 demand_empty_rest_of_line ();
17827 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17829 SKIP_WHITESPACE ();
17830 if (*input_line_pointer
++ != ','
17831 || get_absolute_expression_and_terminator (&val
) != ',')
17833 as_warn (_("Bad .frame directive"));
17834 --input_line_pointer
;
17835 demand_empty_rest_of_line ();
17839 cur_proc_ptr
->frame_offset
= val
;
17840 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17842 demand_empty_rest_of_line ();
17846 /* The .fmask and .mask directives. If the mdebug section is present
17847 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17848 embedded targets, s_mips_mask is used so that we can set the PDR
17849 information correctly. We can't use the ecoff routines because they
17850 make reference to the ecoff symbol table (in the mdebug section). */
17853 s_mips_mask (int reg_type
)
17855 if (ECOFF_DEBUGGING
)
17856 s_ignore (reg_type
);
17861 if (cur_proc_ptr
== (procS
*) NULL
)
17863 as_warn (_(".mask/.fmask outside of .ent"));
17864 demand_empty_rest_of_line ();
17868 if (get_absolute_expression_and_terminator (&mask
) != ',')
17870 as_warn (_("Bad .mask/.fmask directive"));
17871 --input_line_pointer
;
17872 demand_empty_rest_of_line ();
17876 off
= get_absolute_expression ();
17878 if (reg_type
== 'F')
17880 cur_proc_ptr
->fpreg_mask
= mask
;
17881 cur_proc_ptr
->fpreg_offset
= off
;
17885 cur_proc_ptr
->reg_mask
= mask
;
17886 cur_proc_ptr
->reg_offset
= off
;
17889 demand_empty_rest_of_line ();
17893 /* A table describing all the processors gas knows about. Names are
17894 matched in the order listed.
17896 To ease comparison, please keep this table in the same order as
17897 gcc's mips_cpu_info_table[]. */
17898 static const struct mips_cpu_info mips_cpu_info_table
[] =
17900 /* Entries for generic ISAs */
17901 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17902 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17903 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17904 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17905 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17906 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17907 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17908 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17909 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17912 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17913 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17914 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17917 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17920 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17921 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17922 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17923 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17924 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17925 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17926 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17927 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17928 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17929 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17930 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17931 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17932 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17933 /* ST Microelectronics Loongson 2E and 2F cores */
17934 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17935 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17938 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17939 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17940 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17941 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17942 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17943 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17944 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17945 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17946 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17947 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17948 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17949 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17950 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17951 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17952 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17955 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17956 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17957 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17958 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17960 /* MIPS 32 Release 2 */
17961 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17962 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17963 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17964 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17965 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17966 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17967 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17968 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17969 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17970 ISA_MIPS32R2
, CPU_MIPS32R2
},
17971 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17972 ISA_MIPS32R2
, CPU_MIPS32R2
},
17973 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17974 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17975 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17976 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17977 /* Deprecated forms of the above. */
17978 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17979 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17980 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17981 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17982 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17983 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17984 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17985 /* Deprecated forms of the above. */
17986 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17987 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17988 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17989 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17990 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17991 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17992 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17993 /* Deprecated forms of the above. */
17994 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17995 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17996 /* 34Kn is a 34kc without DSP. */
17997 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17998 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17999 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18000 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18001 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18002 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18003 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18004 /* Deprecated forms of the above. */
18005 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18006 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18007 /* 1004K cores are multiprocessor versions of the 34K. */
18008 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18009 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18010 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18011 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18014 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18015 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18016 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18017 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18019 /* Broadcom SB-1 CPU core */
18020 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18021 /* Broadcom SB-1A CPU core */
18022 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18024 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
18026 /* MIPS 64 Release 2 */
18028 /* Cavium Networks Octeon CPU core */
18029 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18030 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18031 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18034 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18037 XLP is mostly like XLR, with the prominent exception that it is
18038 MIPS64R2 rather than MIPS64. */
18039 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18042 { NULL
, 0, 0, 0, 0 }
18046 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18047 with a final "000" replaced by "k". Ignore case.
18049 Note: this function is shared between GCC and GAS. */
18052 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18054 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18055 given
++, canonical
++;
18057 return ((*given
== 0 && *canonical
== 0)
18058 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18062 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18063 CPU name. We've traditionally allowed a lot of variation here.
18065 Note: this function is shared between GCC and GAS. */
18068 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18070 /* First see if the name matches exactly, or with a final "000"
18071 turned into "k". */
18072 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18075 /* If not, try comparing based on numerical designation alone.
18076 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18077 if (TOLOWER (*given
) == 'r')
18079 if (!ISDIGIT (*given
))
18082 /* Skip over some well-known prefixes in the canonical name,
18083 hoping to find a number there too. */
18084 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18086 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18088 else if (TOLOWER (canonical
[0]) == 'r')
18091 return mips_strict_matching_cpu_name_p (canonical
, given
);
18095 /* Parse an option that takes the name of a processor as its argument.
18096 OPTION is the name of the option and CPU_STRING is the argument.
18097 Return the corresponding processor enumeration if the CPU_STRING is
18098 recognized, otherwise report an error and return null.
18100 A similar function exists in GCC. */
18102 static const struct mips_cpu_info
*
18103 mips_parse_cpu (const char *option
, const char *cpu_string
)
18105 const struct mips_cpu_info
*p
;
18107 /* 'from-abi' selects the most compatible architecture for the given
18108 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18109 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18110 version. Look first at the -mgp options, if given, otherwise base
18111 the choice on MIPS_DEFAULT_64BIT.
18113 Treat NO_ABI like the EABIs. One reason to do this is that the
18114 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18115 architecture. This code picks MIPS I for 'mips' and MIPS III for
18116 'mips64', just as we did in the days before 'from-abi'. */
18117 if (strcasecmp (cpu_string
, "from-abi") == 0)
18119 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18120 return mips_cpu_info_from_isa (ISA_MIPS1
);
18122 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18123 return mips_cpu_info_from_isa (ISA_MIPS3
);
18125 if (file_mips_gp32
>= 0)
18126 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
18128 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18133 /* 'default' has traditionally been a no-op. Probably not very useful. */
18134 if (strcasecmp (cpu_string
, "default") == 0)
18137 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18138 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18141 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
18145 /* Return the canonical processor information for ISA (a member of the
18146 ISA_MIPS* enumeration). */
18148 static const struct mips_cpu_info
*
18149 mips_cpu_info_from_isa (int isa
)
18153 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18154 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18155 && isa
== mips_cpu_info_table
[i
].isa
)
18156 return (&mips_cpu_info_table
[i
]);
18161 static const struct mips_cpu_info
*
18162 mips_cpu_info_from_arch (int arch
)
18166 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18167 if (arch
== mips_cpu_info_table
[i
].cpu
)
18168 return (&mips_cpu_info_table
[i
]);
18174 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18178 fprintf (stream
, "%24s", "");
18183 fprintf (stream
, ", ");
18187 if (*col_p
+ strlen (string
) > 72)
18189 fprintf (stream
, "\n%24s", "");
18193 fprintf (stream
, "%s", string
);
18194 *col_p
+= strlen (string
);
18200 md_show_usage (FILE *stream
)
18205 fprintf (stream
, _("\
18207 -EB generate big endian output\n\
18208 -EL generate little endian output\n\
18209 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18210 -G NUM allow referencing objects up to NUM bytes\n\
18211 implicitly with the gp register [default 8]\n"));
18212 fprintf (stream
, _("\
18213 -mips1 generate MIPS ISA I instructions\n\
18214 -mips2 generate MIPS ISA II instructions\n\
18215 -mips3 generate MIPS ISA III instructions\n\
18216 -mips4 generate MIPS ISA IV instructions\n\
18217 -mips5 generate MIPS ISA V instructions\n\
18218 -mips32 generate MIPS32 ISA instructions\n\
18219 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18220 -mips64 generate MIPS64 ISA instructions\n\
18221 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18222 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18226 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18227 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18228 show (stream
, "from-abi", &column
, &first
);
18229 fputc ('\n', stream
);
18231 fprintf (stream
, _("\
18232 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18233 -no-mCPU don't generate code specific to CPU.\n\
18234 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18238 show (stream
, "3900", &column
, &first
);
18239 show (stream
, "4010", &column
, &first
);
18240 show (stream
, "4100", &column
, &first
);
18241 show (stream
, "4650", &column
, &first
);
18242 fputc ('\n', stream
);
18244 fprintf (stream
, _("\
18245 -mips16 generate mips16 instructions\n\
18246 -no-mips16 do not generate mips16 instructions\n"));
18247 fprintf (stream
, _("\
18248 -mmicromips generate microMIPS instructions\n\
18249 -mno-micromips do not generate microMIPS instructions\n"));
18250 fprintf (stream
, _("\
18251 -msmartmips generate smartmips instructions\n\
18252 -mno-smartmips do not generate smartmips instructions\n"));
18253 fprintf (stream
, _("\
18254 -mdsp generate DSP instructions\n\
18255 -mno-dsp do not generate DSP instructions\n"));
18256 fprintf (stream
, _("\
18257 -mdspr2 generate DSP R2 instructions\n\
18258 -mno-dspr2 do not generate DSP R2 instructions\n"));
18259 fprintf (stream
, _("\
18260 -mmt generate MT instructions\n\
18261 -mno-mt do not generate MT instructions\n"));
18262 fprintf (stream
, _("\
18263 -mmcu generate MCU instructions\n\
18264 -mno-mcu do not generate MCU instructions\n"));
18265 fprintf (stream
, _("\
18266 -mvirt generate Virtualization instructions\n\
18267 -mno-virt do not generate Virtualization instructions\n"));
18268 fprintf (stream
, _("\
18269 -minsn32 only generate 32-bit microMIPS instructions\n\
18270 -mno-insn32 generate all microMIPS instructions\n"));
18271 fprintf (stream
, _("\
18272 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18273 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18274 -mfix-vr4120 work around certain VR4120 errata\n\
18275 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18276 -mfix-24k insert a nop after ERET and DERET instructions\n\
18277 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18278 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18279 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18280 -msym32 assume all symbols have 32-bit values\n\
18281 -O0 remove unneeded NOPs, do not swap branches\n\
18282 -O remove unneeded NOPs and swap branches\n\
18283 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18284 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18285 fprintf (stream
, _("\
18286 -mhard-float allow floating-point instructions\n\
18287 -msoft-float do not allow floating-point instructions\n\
18288 -msingle-float only allow 32-bit floating-point operations\n\
18289 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18290 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18291 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18292 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18296 show (stream
, "legacy", &column
, &first
);
18297 show (stream
, "2008", &column
, &first
);
18299 fputc ('\n', stream
);
18301 fprintf (stream
, _("\
18302 -KPIC, -call_shared generate SVR4 position independent code\n\
18303 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18304 -mvxworks-pic generate VxWorks position independent code\n\
18305 -non_shared do not generate code that can operate with DSOs\n\
18306 -xgot assume a 32 bit GOT\n\
18307 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18308 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18309 position dependent (non shared) code\n\
18310 -mabi=ABI create ABI conformant object file for:\n"));
18314 show (stream
, "32", &column
, &first
);
18315 show (stream
, "o64", &column
, &first
);
18316 show (stream
, "n32", &column
, &first
);
18317 show (stream
, "64", &column
, &first
);
18318 show (stream
, "eabi", &column
, &first
);
18320 fputc ('\n', stream
);
18322 fprintf (stream
, _("\
18323 -32 create o32 ABI object file (default)\n\
18324 -n32 create n32 ABI object file\n\
18325 -64 create 64 ABI object file\n"));
18330 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18332 if (HAVE_64BIT_SYMBOLS
)
18333 return dwarf2_format_64bit_irix
;
18335 return dwarf2_format_32bit
;
18340 mips_dwarf2_addr_size (void)
18342 if (HAVE_64BIT_OBJECTS
)
18348 /* Standard calling conventions leave the CFA at SP on entry. */
18350 mips_cfi_frame_initial_instructions (void)
18352 cfi_add_CFA_def_cfa_register (SP
);
18356 tc_mips_regname_to_dw2regnum (char *regname
)
18358 unsigned int regnum
= -1;
18361 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))