1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 /* Allow override of standard little-endian ECOFF format. */
106 #ifndef ECOFF_LITTLE_FORMAT
107 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 /* Information about an instruction, including its format, operands
125 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
126 const struct mips_opcode
*insn_mo
;
128 /* True if this is a mips16 instruction and if we want the extended
130 bfd_boolean use_extend
;
132 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
133 unsigned short extend
;
135 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
136 a copy of INSN_MO->match with the operands filled in. */
137 unsigned long insn_opcode
;
139 /* The frag that contains the instruction. */
142 /* The offset into FRAG of the first instruction byte. */
145 /* The relocs associated with the instruction, if any. */
148 /* True if this entry cannot be moved from its current position. */
149 unsigned int fixed_p
: 1;
151 /* True if this instruction occurred in a .set noreorder block. */
152 unsigned int noreorder_p
: 1;
154 /* True for mips16 instructions that jump to an absolute address. */
155 unsigned int mips16_absolute_jump_p
: 1;
158 /* The ABI to use. */
169 /* MIPS ABI we are using for this output file. */
170 static enum mips_abi_level mips_abi
= NO_ABI
;
172 /* Whether or not we have code that can call pic code. */
173 int mips_abicalls
= FALSE
;
175 /* Whether or not we have code which can be put into a shared
177 static bfd_boolean mips_in_shared
= TRUE
;
179 /* This is the set of options which may be modified by the .set
180 pseudo-op. We use a struct so that .set push and .set pop are more
183 struct mips_set_options
185 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
186 if it has not been initialized. Changed by `.set mipsN', and the
187 -mipsN command line option, and the default CPU. */
189 /* Enabled Application Specific Extensions (ASEs). These are set to -1
190 if they have not been initialized. Changed by `.set <asename>', by
191 command line options, and based on the default architecture. */
197 /* Whether we are assembling for the mips16 processor. 0 if we are
198 not, 1 if we are, and -1 if the value has not been initialized.
199 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
200 -nomips16 command line options, and the default CPU. */
202 /* Non-zero if we should not reorder instructions. Changed by `.set
203 reorder' and `.set noreorder'. */
205 /* Non-zero if we should not permit the $at ($1) register to be used
206 in instructions. Changed by `.set at' and `.set noat'. */
208 /* Non-zero if we should warn when a macro instruction expands into
209 more than one machine instruction. Changed by `.set nomacro' and
211 int warn_about_macros
;
212 /* Non-zero if we should not move instructions. Changed by `.set
213 move', `.set volatile', `.set nomove', and `.set novolatile'. */
215 /* Non-zero if we should not optimize branches by moving the target
216 of the branch into the delay slot. Actually, we don't perform
217 this optimization anyhow. Changed by `.set bopt' and `.set
220 /* Non-zero if we should not autoextend mips16 instructions.
221 Changed by `.set autoextend' and `.set noautoextend'. */
223 /* Restrict general purpose registers and floating point registers
224 to 32 bit. This is initially determined when -mgp32 or -mfp32
225 is passed but can changed if the assembler code uses .set mipsN. */
228 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
229 command line option, and the default CPU. */
231 /* True if ".set sym32" is in effect. */
235 /* True if -mgp32 was passed. */
236 static int file_mips_gp32
= -1;
238 /* True if -mfp32 was passed. */
239 static int file_mips_fp32
= -1;
241 /* This is the struct we use to hold the current set of options. Note
242 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
243 -1 to indicate that they have not been initialized. */
245 static struct mips_set_options mips_opts
=
247 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
250 /* These variables are filled in with the masks of registers used.
251 The object format code reads them and puts them in the appropriate
253 unsigned long mips_gprmask
;
254 unsigned long mips_cprmask
[4];
256 /* MIPS ISA we are using for this output file. */
257 static int file_mips_isa
= ISA_UNKNOWN
;
259 /* True if -mips16 was passed or implied by arguments passed on the
260 command line (e.g., by -march). */
261 static int file_ase_mips16
;
263 /* True if -mips3d was passed or implied by arguments passed on the
264 command line (e.g., by -march). */
265 static int file_ase_mips3d
;
267 /* True if -mdmx was passed or implied by arguments passed on the
268 command line (e.g., by -march). */
269 static int file_ase_mdmx
;
271 /* True if -msmartmips was passed or implied by arguments passed on the
272 command line (e.g., by -march). */
273 static int file_ase_smartmips
;
275 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
276 || mips_opts.isa == ISA_MIPS32R2)
278 /* True if -mdsp was passed or implied by arguments passed on the
279 command line (e.g., by -march). */
280 static int file_ase_dsp
;
282 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
283 || mips_opts.isa == ISA_MIPS64R2)
285 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
287 /* True if -mmt was passed or implied by arguments passed on the
288 command line (e.g., by -march). */
289 static int file_ase_mt
;
291 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* The argument of the -march= flag. The architecture we are assembling. */
295 static int file_mips_arch
= CPU_UNKNOWN
;
296 static const char *mips_arch_string
;
298 /* The argument of the -mtune= flag. The architecture for which we
300 static int mips_tune
= CPU_UNKNOWN
;
301 static const char *mips_tune_string
;
303 /* True when generating 32-bit code for a 64-bit processor. */
304 static int mips_32bitmode
= 0;
306 /* True if the given ABI requires 32-bit registers. */
307 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
309 /* Likewise 64-bit registers. */
310 #define ABI_NEEDS_64BIT_REGS(ABI) \
312 || (ABI) == N64_ABI \
315 /* Return true if ISA supports 64 bit wide gp registers. */
316 #define ISA_HAS_64BIT_REGS(ISA) \
317 ((ISA) == ISA_MIPS3 \
318 || (ISA) == ISA_MIPS4 \
319 || (ISA) == ISA_MIPS5 \
320 || (ISA) == ISA_MIPS64 \
321 || (ISA) == ISA_MIPS64R2)
323 /* Return true if ISA supports 64 bit wide float registers. */
324 #define ISA_HAS_64BIT_FPRS(ISA) \
325 ((ISA) == ISA_MIPS3 \
326 || (ISA) == ISA_MIPS4 \
327 || (ISA) == ISA_MIPS5 \
328 || (ISA) == ISA_MIPS32R2 \
329 || (ISA) == ISA_MIPS64 \
330 || (ISA) == ISA_MIPS64R2)
332 /* Return true if ISA supports 64-bit right rotate (dror et al.)
334 #define ISA_HAS_DROR(ISA) \
335 ((ISA) == ISA_MIPS64R2)
337 /* Return true if ISA supports 32-bit right rotate (ror et al.)
339 #define ISA_HAS_ROR(ISA) \
340 ((ISA) == ISA_MIPS32R2 \
341 || (ISA) == ISA_MIPS64R2 \
342 || mips_opts.ase_smartmips)
344 /* Return true if ISA supports single-precision floats in odd registers. */
345 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
346 ((ISA) == ISA_MIPS32 \
347 || (ISA) == ISA_MIPS32R2 \
348 || (ISA) == ISA_MIPS64 \
349 || (ISA) == ISA_MIPS64R2)
351 /* Return true if ISA supports move to/from high part of a 64-bit
352 floating-point register. */
353 #define ISA_HAS_MXHC1(ISA) \
354 ((ISA) == ISA_MIPS32R2 \
355 || (ISA) == ISA_MIPS64R2)
357 #define HAVE_32BIT_GPRS \
358 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
360 #define HAVE_32BIT_FPRS \
361 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
363 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
364 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
366 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
368 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
370 /* True if relocations are stored in-place. */
371 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
373 /* The ABI-derived address size. */
374 #define HAVE_64BIT_ADDRESSES \
375 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
376 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
378 /* The size of symbolic constants (i.e., expressions of the form
379 "SYMBOL" or "SYMBOL + OFFSET"). */
380 #define HAVE_32BIT_SYMBOLS \
381 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
382 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
384 /* Addresses are loaded in different ways, depending on the address size
385 in use. The n32 ABI Documentation also mandates the use of additions
386 with overflow checking, but existing implementations don't follow it. */
387 #define ADDRESS_ADD_INSN \
388 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
390 #define ADDRESS_ADDI_INSN \
391 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
393 #define ADDRESS_LOAD_INSN \
394 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
396 #define ADDRESS_STORE_INSN \
397 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
399 /* Return true if the given CPU supports the MIPS16 ASE. */
400 #define CPU_HAS_MIPS16(cpu) \
401 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
402 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
404 /* True if CPU has a dror instruction. */
405 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
407 /* True if CPU has a ror instruction. */
408 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
410 /* True if mflo and mfhi can be immediately followed by instructions
411 which write to the HI and LO registers.
413 According to MIPS specifications, MIPS ISAs I, II, and III need
414 (at least) two instructions between the reads of HI/LO and
415 instructions which write them, and later ISAs do not. Contradicting
416 the MIPS specifications, some MIPS IV processor user manuals (e.g.
417 the UM for the NEC Vr5000) document needing the instructions between
418 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
419 MIPS64 and later ISAs to have the interlocks, plus any specific
420 earlier-ISA CPUs for which CPU documentation declares that the
421 instructions are really interlocked. */
422 #define hilo_interlocks \
423 (mips_opts.isa == ISA_MIPS32 \
424 || mips_opts.isa == ISA_MIPS32R2 \
425 || mips_opts.isa == ISA_MIPS64 \
426 || mips_opts.isa == ISA_MIPS64R2 \
427 || mips_opts.arch == CPU_R4010 \
428 || mips_opts.arch == CPU_R10000 \
429 || mips_opts.arch == CPU_R12000 \
430 || mips_opts.arch == CPU_RM7000 \
431 || mips_opts.arch == CPU_VR5500 \
434 /* Whether the processor uses hardware interlocks to protect reads
435 from the GPRs after they are loaded from memory, and thus does not
436 require nops to be inserted. This applies to instructions marked
437 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
439 #define gpr_interlocks \
440 (mips_opts.isa != ISA_MIPS1 \
441 || mips_opts.arch == CPU_R3900)
443 /* Whether the processor uses hardware interlocks to avoid delays
444 required by coprocessor instructions, and thus does not require
445 nops to be inserted. This applies to instructions marked
446 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
447 between instructions marked INSN_WRITE_COND_CODE and ones marked
448 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
449 levels I, II, and III. */
450 /* Itbl support may require additional care here. */
451 #define cop_interlocks \
452 ((mips_opts.isa != ISA_MIPS1 \
453 && mips_opts.isa != ISA_MIPS2 \
454 && mips_opts.isa != ISA_MIPS3) \
455 || mips_opts.arch == CPU_R4300 \
458 /* Whether the processor uses hardware interlocks to protect reads
459 from coprocessor registers after they are loaded from memory, and
460 thus does not require nops to be inserted. This applies to
461 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
462 requires at MIPS ISA level I. */
463 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
465 /* Is this a mfhi or mflo instruction? */
466 #define MF_HILO_INSN(PINFO) \
467 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
469 /* MIPS PIC level. */
471 enum mips_pic_level mips_pic
;
473 /* 1 if we should generate 32 bit offsets from the $gp register in
474 SVR4_PIC mode. Currently has no meaning in other modes. */
475 static int mips_big_got
= 0;
477 /* 1 if trap instructions should used for overflow rather than break
479 static int mips_trap
= 0;
481 /* 1 if double width floating point constants should not be constructed
482 by assembling two single width halves into two single width floating
483 point registers which just happen to alias the double width destination
484 register. On some architectures this aliasing can be disabled by a bit
485 in the status register, and the setting of this bit cannot be determined
486 automatically at assemble time. */
487 static int mips_disable_float_construction
;
489 /* Non-zero if any .set noreorder directives were used. */
491 static int mips_any_noreorder
;
493 /* Non-zero if nops should be inserted when the register referenced in
494 an mfhi/mflo instruction is read in the next two instructions. */
495 static int mips_7000_hilo_fix
;
497 /* The size of the small data section. */
498 static unsigned int g_switch_value
= 8;
499 /* Whether the -G option was used. */
500 static int g_switch_seen
= 0;
505 /* If we can determine in advance that GP optimization won't be
506 possible, we can skip the relaxation stuff that tries to produce
507 GP-relative references. This makes delay slot optimization work
510 This function can only provide a guess, but it seems to work for
511 gcc output. It needs to guess right for gcc, otherwise gcc
512 will put what it thinks is a GP-relative instruction in a branch
515 I don't know if a fix is needed for the SVR4_PIC mode. I've only
516 fixed it for the non-PIC mode. KR 95/04/07 */
517 static int nopic_need_relax (symbolS
*, int);
519 /* handle of the OPCODE hash table */
520 static struct hash_control
*op_hash
= NULL
;
522 /* The opcode hash table we use for the mips16. */
523 static struct hash_control
*mips16_op_hash
= NULL
;
525 /* This array holds the chars that always start a comment. If the
526 pre-processor is disabled, these aren't very useful */
527 const char comment_chars
[] = "#";
529 /* This array holds the chars that only start a comment at the beginning of
530 a line. If the line seems to have the form '# 123 filename'
531 .line and .file directives will appear in the pre-processed output */
532 /* Note that input_file.c hand checks for '#' at the beginning of the
533 first line of the input file. This is because the compiler outputs
534 #NO_APP at the beginning of its output. */
535 /* Also note that C style comments are always supported. */
536 const char line_comment_chars
[] = "#";
538 /* This array holds machine specific line separator characters. */
539 const char line_separator_chars
[] = ";";
541 /* Chars that can be used to separate mant from exp in floating point nums */
542 const char EXP_CHARS
[] = "eE";
544 /* Chars that mean this number is a floating point constant */
547 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
549 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
550 changed in read.c . Ideally it shouldn't have to know about it at all,
551 but nothing is ideal around here.
554 static char *insn_error
;
556 static int auto_align
= 1;
558 /* When outputting SVR4 PIC code, the assembler needs to know the
559 offset in the stack frame from which to restore the $gp register.
560 This is set by the .cprestore pseudo-op, and saved in this
562 static offsetT mips_cprestore_offset
= -1;
564 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
565 more optimizations, it can use a register value instead of a memory-saved
566 offset and even an other register than $gp as global pointer. */
567 static offsetT mips_cpreturn_offset
= -1;
568 static int mips_cpreturn_register
= -1;
569 static int mips_gp_register
= GP
;
570 static int mips_gprel_offset
= 0;
572 /* Whether mips_cprestore_offset has been set in the current function
573 (or whether it has already been warned about, if not). */
574 static int mips_cprestore_valid
= 0;
576 /* This is the register which holds the stack frame, as set by the
577 .frame pseudo-op. This is needed to implement .cprestore. */
578 static int mips_frame_reg
= SP
;
580 /* Whether mips_frame_reg has been set in the current function
581 (or whether it has already been warned about, if not). */
582 static int mips_frame_reg_valid
= 0;
584 /* To output NOP instructions correctly, we need to keep information
585 about the previous two instructions. */
587 /* Whether we are optimizing. The default value of 2 means to remove
588 unneeded NOPs and swap branch instructions when possible. A value
589 of 1 means to not swap branches. A value of 0 means to always
591 static int mips_optimize
= 2;
593 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
594 equivalent to seeing no -g option at all. */
595 static int mips_debug
= 0;
597 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
598 #define MAX_VR4130_NOPS 4
600 /* The maximum number of NOPs needed to fill delay slots. */
601 #define MAX_DELAY_NOPS 2
603 /* The maximum number of NOPs needed for any purpose. */
606 /* A list of previous instructions, with index 0 being the most recent.
607 We need to look back MAX_NOPS instructions when filling delay slots
608 or working around processor errata. We need to look back one
609 instruction further if we're thinking about using history[0] to
610 fill a branch delay slot. */
611 static struct mips_cl_insn history
[1 + MAX_NOPS
];
613 /* Nop instructions used by emit_nop. */
614 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
616 /* The appropriate nop for the current mode. */
617 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
619 /* If this is set, it points to a frag holding nop instructions which
620 were inserted before the start of a noreorder section. If those
621 nops turn out to be unnecessary, the size of the frag can be
623 static fragS
*prev_nop_frag
;
625 /* The number of nop instructions we created in prev_nop_frag. */
626 static int prev_nop_frag_holds
;
628 /* The number of nop instructions that we know we need in
630 static int prev_nop_frag_required
;
632 /* The number of instructions we've seen since prev_nop_frag. */
633 static int prev_nop_frag_since
;
635 /* For ECOFF and ELF, relocations against symbols are done in two
636 parts, with a HI relocation and a LO relocation. Each relocation
637 has only 16 bits of space to store an addend. This means that in
638 order for the linker to handle carries correctly, it must be able
639 to locate both the HI and the LO relocation. This means that the
640 relocations must appear in order in the relocation table.
642 In order to implement this, we keep track of each unmatched HI
643 relocation. We then sort them so that they immediately precede the
644 corresponding LO relocation. */
649 struct mips_hi_fixup
*next
;
652 /* The section this fixup is in. */
656 /* The list of unmatched HI relocs. */
658 static struct mips_hi_fixup
*mips_hi_fixup_list
;
660 /* The frag containing the last explicit relocation operator.
661 Null if explicit relocations have not been used. */
663 static fragS
*prev_reloc_op_frag
;
665 /* Map normal MIPS register numbers to mips16 register numbers. */
667 #define X ILLEGAL_REG
668 static const int mips32_to_16_reg_map
[] =
670 X
, X
, 2, 3, 4, 5, 6, 7,
671 X
, X
, X
, X
, X
, X
, X
, X
,
672 0, 1, X
, X
, X
, X
, X
, X
,
673 X
, X
, X
, X
, X
, X
, X
, X
677 /* Map mips16 register numbers to normal MIPS register numbers. */
679 static const unsigned int mips16_to_32_reg_map
[] =
681 16, 17, 2, 3, 4, 5, 6, 7
684 /* Classifies the kind of instructions we're interested in when
685 implementing -mfix-vr4120. */
686 enum fix_vr4120_class
{
693 NUM_FIX_VR4120_CLASSES
696 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
697 there must be at least one other instruction between an instruction
698 of type X and an instruction of type Y. */
699 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
701 /* True if -mfix-vr4120 is in force. */
702 static int mips_fix_vr4120
;
704 /* ...likewise -mfix-vr4130. */
705 static int mips_fix_vr4130
;
707 /* We don't relax branches by default, since this causes us to expand
708 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
709 fail to compute the offset before expanding the macro to the most
710 efficient expansion. */
712 static int mips_relax_branch
;
714 /* The expansion of many macros depends on the type of symbol that
715 they refer to. For example, when generating position-dependent code,
716 a macro that refers to a symbol may have two different expansions,
717 one which uses GP-relative addresses and one which uses absolute
718 addresses. When generating SVR4-style PIC, a macro may have
719 different expansions for local and global symbols.
721 We handle these situations by generating both sequences and putting
722 them in variant frags. In position-dependent code, the first sequence
723 will be the GP-relative one and the second sequence will be the
724 absolute one. In SVR4 PIC, the first sequence will be for global
725 symbols and the second will be for local symbols.
727 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
728 SECOND are the lengths of the two sequences in bytes. These fields
729 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
730 the subtype has the following flags:
733 Set if it has been decided that we should use the second
734 sequence instead of the first.
737 Set in the first variant frag if the macro's second implementation
738 is longer than its first. This refers to the macro as a whole,
739 not an individual relaxation.
742 Set in the first variant frag if the macro appeared in a .set nomacro
743 block and if one alternative requires a warning but the other does not.
746 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
749 The frag's "opcode" points to the first fixup for relaxable code.
751 Relaxable macros are generated using a sequence such as:
753 relax_start (SYMBOL);
754 ... generate first expansion ...
756 ... generate second expansion ...
759 The code and fixups for the unwanted alternative are discarded
760 by md_convert_frag. */
761 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
763 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
764 #define RELAX_SECOND(X) ((X) & 0xff)
765 #define RELAX_USE_SECOND 0x10000
766 #define RELAX_SECOND_LONGER 0x20000
767 #define RELAX_NOMACRO 0x40000
768 #define RELAX_DELAY_SLOT 0x80000
770 /* Branch without likely bit. If label is out of range, we turn:
772 beq reg1, reg2, label
782 with the following opcode replacements:
789 bltzal <-> bgezal (with jal label instead of j label)
791 Even though keeping the delay slot instruction in the delay slot of
792 the branch would be more efficient, it would be very tricky to do
793 correctly, because we'd have to introduce a variable frag *after*
794 the delay slot instruction, and expand that instead. Let's do it
795 the easy way for now, even if the branch-not-taken case now costs
796 one additional instruction. Out-of-range branches are not supposed
797 to be common, anyway.
799 Branch likely. If label is out of range, we turn:
801 beql reg1, reg2, label
802 delay slot (annulled if branch not taken)
811 delay slot (executed only if branch taken)
814 It would be possible to generate a shorter sequence by losing the
815 likely bit, generating something like:
820 delay slot (executed only if branch taken)
832 bltzall -> bgezal (with jal label instead of j label)
833 bgezall -> bltzal (ditto)
836 but it's not clear that it would actually improve performance. */
837 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
840 | ((toofar) ? 1 : 0) \
842 | ((likely) ? 4 : 0) \
843 | ((uncond) ? 8 : 0)))
844 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
845 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
846 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
847 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
848 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
850 /* For mips16 code, we use an entirely different form of relaxation.
851 mips16 supports two versions of most instructions which take
852 immediate values: a small one which takes some small value, and a
853 larger one which takes a 16 bit value. Since branches also follow
854 this pattern, relaxing these values is required.
856 We can assemble both mips16 and normal MIPS code in a single
857 object. Therefore, we need to support this type of relaxation at
858 the same time that we support the relaxation described above. We
859 use the high bit of the subtype field to distinguish these cases.
861 The information we store for this type of relaxation is the
862 argument code found in the opcode file for this relocation, whether
863 the user explicitly requested a small or extended form, and whether
864 the relocation is in a jump or jal delay slot. That tells us the
865 size of the value, and how it should be stored. We also store
866 whether the fragment is considered to be extended or not. We also
867 store whether this is known to be a branch to a different section,
868 whether we have tried to relax this frag yet, and whether we have
869 ever extended a PC relative fragment because of a shift count. */
870 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
873 | ((small) ? 0x100 : 0) \
874 | ((ext) ? 0x200 : 0) \
875 | ((dslot) ? 0x400 : 0) \
876 | ((jal_dslot) ? 0x800 : 0))
877 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
878 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
879 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
880 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
881 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
882 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
883 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
884 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
885 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
886 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
887 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
888 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
890 /* Is the given value a sign-extended 32-bit value? */
891 #define IS_SEXT_32BIT_NUM(x) \
892 (((x) &~ (offsetT) 0x7fffffff) == 0 \
893 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
895 /* Is the given value a sign-extended 16-bit value? */
896 #define IS_SEXT_16BIT_NUM(x) \
897 (((x) &~ (offsetT) 0x7fff) == 0 \
898 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
900 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
901 #define IS_ZEXT_32BIT_NUM(x) \
902 (((x) &~ (offsetT) 0xffffffff) == 0 \
903 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
905 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
906 VALUE << SHIFT. VALUE is evaluated exactly once. */
907 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
908 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
909 | (((VALUE) & (MASK)) << (SHIFT)))
911 /* Extract bits MASK << SHIFT from STRUCT and shift them right
913 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
914 (((STRUCT) >> (SHIFT)) & (MASK))
916 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
917 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
919 include/opcode/mips.h specifies operand fields using the macros
920 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
921 with "MIPS16OP" instead of "OP". */
922 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
923 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
924 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
925 INSERT_BITS ((INSN).insn_opcode, VALUE, \
926 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
928 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
929 #define EXTRACT_OPERAND(FIELD, INSN) \
930 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
931 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
932 EXTRACT_BITS ((INSN).insn_opcode, \
933 MIPS16OP_MASK_##FIELD, \
936 /* Global variables used when generating relaxable macros. See the
937 comment above RELAX_ENCODE for more details about how relaxation
940 /* 0 if we're not emitting a relaxable macro.
941 1 if we're emitting the first of the two relaxation alternatives.
942 2 if we're emitting the second alternative. */
945 /* The first relaxable fixup in the current frag. (In other words,
946 the first fixup that refers to relaxable code.) */
949 /* sizes[0] says how many bytes of the first alternative are stored in
950 the current frag. Likewise sizes[1] for the second alternative. */
951 unsigned int sizes
[2];
953 /* The symbol on which the choice of sequence depends. */
957 /* Global variables used to decide whether a macro needs a warning. */
959 /* True if the macro is in a branch delay slot. */
960 bfd_boolean delay_slot_p
;
962 /* For relaxable macros, sizes[0] is the length of the first alternative
963 in bytes and sizes[1] is the length of the second alternative.
964 For non-relaxable macros, both elements give the length of the
966 unsigned int sizes
[2];
968 /* The first variant frag for this macro. */
970 } mips_macro_warning
;
972 /* Prototypes for static functions. */
974 #define internalError() \
975 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
977 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
979 static void append_insn
980 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
981 static void mips_no_prev_insn (void);
982 static void mips16_macro_build
983 (expressionS
*, const char *, const char *, va_list);
984 static void load_register (int, expressionS
*, int);
985 static void macro_start (void);
986 static void macro_end (void);
987 static void macro (struct mips_cl_insn
* ip
);
988 static void mips16_macro (struct mips_cl_insn
* ip
);
989 #ifdef LOSING_COMPILER
990 static void macro2 (struct mips_cl_insn
* ip
);
992 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
993 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
994 static void mips16_immed
995 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
996 unsigned long *, bfd_boolean
*, unsigned short *);
997 static size_t my_getSmallExpression
998 (expressionS
*, bfd_reloc_code_real_type
*, char *);
999 static void my_getExpression (expressionS
*, char *);
1000 static void s_align (int);
1001 static void s_change_sec (int);
1002 static void s_change_section (int);
1003 static void s_cons (int);
1004 static void s_float_cons (int);
1005 static void s_mips_globl (int);
1006 static void s_option (int);
1007 static void s_mipsset (int);
1008 static void s_abicalls (int);
1009 static void s_cpload (int);
1010 static void s_cpsetup (int);
1011 static void s_cplocal (int);
1012 static void s_cprestore (int);
1013 static void s_cpreturn (int);
1014 static void s_gpvalue (int);
1015 static void s_gpword (int);
1016 static void s_gpdword (int);
1017 static void s_cpadd (int);
1018 static void s_insn (int);
1019 static void md_obj_begin (void);
1020 static void md_obj_end (void);
1021 static void s_mips_ent (int);
1022 static void s_mips_end (int);
1023 static void s_mips_frame (int);
1024 static void s_mips_mask (int reg_type
);
1025 static void s_mips_stab (int);
1026 static void s_mips_weakext (int);
1027 static void s_mips_file (int);
1028 static void s_mips_loc (int);
1029 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1030 static int relaxed_branch_length (fragS
*, asection
*, int);
1031 static int validate_mips_insn (const struct mips_opcode
*);
1033 /* Table and functions used to map between CPU/ISA names, and
1034 ISA levels, and CPU numbers. */
1036 struct mips_cpu_info
1038 const char *name
; /* CPU or ISA name. */
1039 int flags
; /* ASEs available, or ISA flag. */
1040 int isa
; /* ISA level. */
1041 int cpu
; /* CPU number (default CPU if ISA). */
1044 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1045 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1046 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1047 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1048 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1049 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1051 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1052 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1053 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1057 The following pseudo-ops from the Kane and Heinrich MIPS book
1058 should be defined here, but are currently unsupported: .alias,
1059 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1061 The following pseudo-ops from the Kane and Heinrich MIPS book are
1062 specific to the type of debugging information being generated, and
1063 should be defined by the object format: .aent, .begin, .bend,
1064 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1067 The following pseudo-ops from the Kane and Heinrich MIPS book are
1068 not MIPS CPU specific, but are also not specific to the object file
1069 format. This file is probably the best place to define them, but
1070 they are not currently supported: .asm0, .endr, .lab, .repeat,
1073 static const pseudo_typeS mips_pseudo_table
[] =
1075 /* MIPS specific pseudo-ops. */
1076 {"option", s_option
, 0},
1077 {"set", s_mipsset
, 0},
1078 {"rdata", s_change_sec
, 'r'},
1079 {"sdata", s_change_sec
, 's'},
1080 {"livereg", s_ignore
, 0},
1081 {"abicalls", s_abicalls
, 0},
1082 {"cpload", s_cpload
, 0},
1083 {"cpsetup", s_cpsetup
, 0},
1084 {"cplocal", s_cplocal
, 0},
1085 {"cprestore", s_cprestore
, 0},
1086 {"cpreturn", s_cpreturn
, 0},
1087 {"gpvalue", s_gpvalue
, 0},
1088 {"gpword", s_gpword
, 0},
1089 {"gpdword", s_gpdword
, 0},
1090 {"cpadd", s_cpadd
, 0},
1091 {"insn", s_insn
, 0},
1093 /* Relatively generic pseudo-ops that happen to be used on MIPS
1095 {"asciiz", stringer
, 1},
1096 {"bss", s_change_sec
, 'b'},
1098 {"half", s_cons
, 1},
1099 {"dword", s_cons
, 3},
1100 {"weakext", s_mips_weakext
, 0},
1102 /* These pseudo-ops are defined in read.c, but must be overridden
1103 here for one reason or another. */
1104 {"align", s_align
, 0},
1105 {"byte", s_cons
, 0},
1106 {"data", s_change_sec
, 'd'},
1107 {"double", s_float_cons
, 'd'},
1108 {"float", s_float_cons
, 'f'},
1109 {"globl", s_mips_globl
, 0},
1110 {"global", s_mips_globl
, 0},
1111 {"hword", s_cons
, 1},
1113 {"long", s_cons
, 2},
1114 {"octa", s_cons
, 4},
1115 {"quad", s_cons
, 3},
1116 {"section", s_change_section
, 0},
1117 {"short", s_cons
, 1},
1118 {"single", s_float_cons
, 'f'},
1119 {"stabn", s_mips_stab
, 'n'},
1120 {"text", s_change_sec
, 't'},
1121 {"word", s_cons
, 2},
1123 { "extern", ecoff_directive_extern
, 0},
1128 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1130 /* These pseudo-ops should be defined by the object file format.
1131 However, a.out doesn't support them, so we have versions here. */
1132 {"aent", s_mips_ent
, 1},
1133 {"bgnb", s_ignore
, 0},
1134 {"end", s_mips_end
, 0},
1135 {"endb", s_ignore
, 0},
1136 {"ent", s_mips_ent
, 0},
1137 {"file", s_mips_file
, 0},
1138 {"fmask", s_mips_mask
, 'F'},
1139 {"frame", s_mips_frame
, 0},
1140 {"loc", s_mips_loc
, 0},
1141 {"mask", s_mips_mask
, 'R'},
1142 {"verstamp", s_ignore
, 0},
1146 extern void pop_insert (const pseudo_typeS
*);
1149 mips_pop_insert (void)
1151 pop_insert (mips_pseudo_table
);
1152 if (! ECOFF_DEBUGGING
)
1153 pop_insert (mips_nonecoff_pseudo_table
);
1156 /* Symbols labelling the current insn. */
1158 struct insn_label_list
1160 struct insn_label_list
*next
;
1164 static struct insn_label_list
*insn_labels
;
1165 static struct insn_label_list
*free_insn_labels
;
1167 static void mips_clear_insn_labels (void);
1170 mips_clear_insn_labels (void)
1172 register struct insn_label_list
**pl
;
1174 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1180 static char *expr_end
;
1182 /* Expressions which appear in instructions. These are set by
1185 static expressionS imm_expr
;
1186 static expressionS imm2_expr
;
1187 static expressionS offset_expr
;
1189 /* Relocs associated with imm_expr and offset_expr. */
1191 static bfd_reloc_code_real_type imm_reloc
[3]
1192 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1193 static bfd_reloc_code_real_type offset_reloc
[3]
1194 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1196 /* These are set by mips16_ip if an explicit extension is used. */
1198 static bfd_boolean mips16_small
, mips16_ext
;
1201 /* The pdr segment for per procedure frame/regmask info. Not used for
1204 static segT pdr_seg
;
1207 /* The default target format to use. */
1210 mips_target_format (void)
1212 switch (OUTPUT_FLAVOR
)
1214 case bfd_target_ecoff_flavour
:
1215 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1216 case bfd_target_coff_flavour
:
1218 case bfd_target_elf_flavour
:
1220 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1221 return (target_big_endian
1222 ? "elf32-bigmips-vxworks"
1223 : "elf32-littlemips-vxworks");
1226 /* This is traditional mips. */
1227 return (target_big_endian
1228 ? (HAVE_64BIT_OBJECTS
1229 ? "elf64-tradbigmips"
1231 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1232 : (HAVE_64BIT_OBJECTS
1233 ? "elf64-tradlittlemips"
1235 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1237 return (target_big_endian
1238 ? (HAVE_64BIT_OBJECTS
1241 ? "elf32-nbigmips" : "elf32-bigmips"))
1242 : (HAVE_64BIT_OBJECTS
1243 ? "elf64-littlemips"
1245 ? "elf32-nlittlemips" : "elf32-littlemips")));
1253 /* Return the length of instruction INSN. */
1255 static inline unsigned int
1256 insn_length (const struct mips_cl_insn
*insn
)
1258 if (!mips_opts
.mips16
)
1260 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1263 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1266 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1271 insn
->use_extend
= FALSE
;
1273 insn
->insn_opcode
= mo
->match
;
1276 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1277 insn
->fixp
[i
] = NULL
;
1278 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1279 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1280 insn
->mips16_absolute_jump_p
= 0;
1283 /* Install INSN at the location specified by its "frag" and "where" fields. */
1286 install_insn (const struct mips_cl_insn
*insn
)
1288 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1289 if (!mips_opts
.mips16
)
1290 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1291 else if (insn
->mips16_absolute_jump_p
)
1293 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1294 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1298 if (insn
->use_extend
)
1300 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1303 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1307 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1308 and install the opcode in the new location. */
1311 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1316 insn
->where
= where
;
1317 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1318 if (insn
->fixp
[i
] != NULL
)
1320 insn
->fixp
[i
]->fx_frag
= frag
;
1321 insn
->fixp
[i
]->fx_where
= where
;
1323 install_insn (insn
);
1326 /* Add INSN to the end of the output. */
1329 add_fixed_insn (struct mips_cl_insn
*insn
)
1331 char *f
= frag_more (insn_length (insn
));
1332 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1335 /* Start a variant frag and move INSN to the start of the variant part,
1336 marking it as fixed. The other arguments are as for frag_var. */
1339 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1340 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1342 frag_grow (max_chars
);
1343 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1345 frag_var (rs_machine_dependent
, max_chars
, var
,
1346 subtype
, symbol
, offset
, NULL
);
1349 /* Insert N copies of INSN into the history buffer, starting at
1350 position FIRST. Neither FIRST nor N need to be clipped. */
1353 insert_into_history (unsigned int first
, unsigned int n
,
1354 const struct mips_cl_insn
*insn
)
1356 if (mips_relax
.sequence
!= 2)
1360 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1362 history
[i
] = history
[i
- n
];
1368 /* Emit a nop instruction, recording it in the history buffer. */
1373 add_fixed_insn (NOP_INSN
);
1374 insert_into_history (0, 1, NOP_INSN
);
1377 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1378 the idea is to make it obvious at a glance that each errata is
1382 init_vr4120_conflicts (void)
1384 #define CONFLICT(FIRST, SECOND) \
1385 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1387 /* Errata 21 - [D]DIV[U] after [D]MACC */
1388 CONFLICT (MACC
, DIV
);
1389 CONFLICT (DMACC
, DIV
);
1391 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1392 CONFLICT (DMULT
, DMULT
);
1393 CONFLICT (DMULT
, DMACC
);
1394 CONFLICT (DMACC
, DMULT
);
1395 CONFLICT (DMACC
, DMACC
);
1397 /* Errata 24 - MT{LO,HI} after [D]MACC */
1398 CONFLICT (MACC
, MTHILO
);
1399 CONFLICT (DMACC
, MTHILO
);
1401 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1402 instruction is executed immediately after a MACC or DMACC
1403 instruction, the result of [either instruction] is incorrect." */
1404 CONFLICT (MACC
, MULT
);
1405 CONFLICT (MACC
, DMULT
);
1406 CONFLICT (DMACC
, MULT
);
1407 CONFLICT (DMACC
, DMULT
);
1409 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1410 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1411 DDIV or DDIVU instruction, the result of the MACC or
1412 DMACC instruction is incorrect.". */
1413 CONFLICT (DMULT
, MACC
);
1414 CONFLICT (DMULT
, DMACC
);
1415 CONFLICT (DIV
, MACC
);
1416 CONFLICT (DIV
, DMACC
);
1426 #define RTYPE_MASK 0x1ff00
1427 #define RTYPE_NUM 0x00100
1428 #define RTYPE_FPU 0x00200
1429 #define RTYPE_FCC 0x00400
1430 #define RTYPE_VEC 0x00800
1431 #define RTYPE_GP 0x01000
1432 #define RTYPE_CP0 0x02000
1433 #define RTYPE_PC 0x04000
1434 #define RTYPE_ACC 0x08000
1435 #define RTYPE_CCC 0x10000
1436 #define RNUM_MASK 0x000ff
1437 #define RWARN 0x80000
1439 #define GENERIC_REGISTER_NUMBERS \
1440 {"$0", RTYPE_NUM | 0}, \
1441 {"$1", RTYPE_NUM | 1}, \
1442 {"$2", RTYPE_NUM | 2}, \
1443 {"$3", RTYPE_NUM | 3}, \
1444 {"$4", RTYPE_NUM | 4}, \
1445 {"$5", RTYPE_NUM | 5}, \
1446 {"$6", RTYPE_NUM | 6}, \
1447 {"$7", RTYPE_NUM | 7}, \
1448 {"$8", RTYPE_NUM | 8}, \
1449 {"$9", RTYPE_NUM | 9}, \
1450 {"$10", RTYPE_NUM | 10}, \
1451 {"$11", RTYPE_NUM | 11}, \
1452 {"$12", RTYPE_NUM | 12}, \
1453 {"$13", RTYPE_NUM | 13}, \
1454 {"$14", RTYPE_NUM | 14}, \
1455 {"$15", RTYPE_NUM | 15}, \
1456 {"$16", RTYPE_NUM | 16}, \
1457 {"$17", RTYPE_NUM | 17}, \
1458 {"$18", RTYPE_NUM | 18}, \
1459 {"$19", RTYPE_NUM | 19}, \
1460 {"$20", RTYPE_NUM | 20}, \
1461 {"$21", RTYPE_NUM | 21}, \
1462 {"$22", RTYPE_NUM | 22}, \
1463 {"$23", RTYPE_NUM | 23}, \
1464 {"$24", RTYPE_NUM | 24}, \
1465 {"$25", RTYPE_NUM | 25}, \
1466 {"$26", RTYPE_NUM | 26}, \
1467 {"$27", RTYPE_NUM | 27}, \
1468 {"$28", RTYPE_NUM | 28}, \
1469 {"$29", RTYPE_NUM | 29}, \
1470 {"$30", RTYPE_NUM | 30}, \
1471 {"$31", RTYPE_NUM | 31}
1473 #define FPU_REGISTER_NAMES \
1474 {"$f0", RTYPE_FPU | 0}, \
1475 {"$f1", RTYPE_FPU | 1}, \
1476 {"$f2", RTYPE_FPU | 2}, \
1477 {"$f3", RTYPE_FPU | 3}, \
1478 {"$f4", RTYPE_FPU | 4}, \
1479 {"$f5", RTYPE_FPU | 5}, \
1480 {"$f6", RTYPE_FPU | 6}, \
1481 {"$f7", RTYPE_FPU | 7}, \
1482 {"$f8", RTYPE_FPU | 8}, \
1483 {"$f9", RTYPE_FPU | 9}, \
1484 {"$f10", RTYPE_FPU | 10}, \
1485 {"$f11", RTYPE_FPU | 11}, \
1486 {"$f12", RTYPE_FPU | 12}, \
1487 {"$f13", RTYPE_FPU | 13}, \
1488 {"$f14", RTYPE_FPU | 14}, \
1489 {"$f15", RTYPE_FPU | 15}, \
1490 {"$f16", RTYPE_FPU | 16}, \
1491 {"$f17", RTYPE_FPU | 17}, \
1492 {"$f18", RTYPE_FPU | 18}, \
1493 {"$f19", RTYPE_FPU | 19}, \
1494 {"$f20", RTYPE_FPU | 20}, \
1495 {"$f21", RTYPE_FPU | 21}, \
1496 {"$f22", RTYPE_FPU | 22}, \
1497 {"$f23", RTYPE_FPU | 23}, \
1498 {"$f24", RTYPE_FPU | 24}, \
1499 {"$f25", RTYPE_FPU | 25}, \
1500 {"$f26", RTYPE_FPU | 26}, \
1501 {"$f27", RTYPE_FPU | 27}, \
1502 {"$f28", RTYPE_FPU | 28}, \
1503 {"$f29", RTYPE_FPU | 29}, \
1504 {"$f30", RTYPE_FPU | 30}, \
1505 {"$f31", RTYPE_FPU | 31}
1507 #define FPU_CONDITION_CODE_NAMES \
1508 {"$fcc0", RTYPE_FCC | 0}, \
1509 {"$fcc1", RTYPE_FCC | 1}, \
1510 {"$fcc2", RTYPE_FCC | 2}, \
1511 {"$fcc3", RTYPE_FCC | 3}, \
1512 {"$fcc4", RTYPE_FCC | 4}, \
1513 {"$fcc5", RTYPE_FCC | 5}, \
1514 {"$fcc6", RTYPE_FCC | 6}, \
1515 {"$fcc7", RTYPE_FCC | 7}
1517 #define COPROC_CONDITION_CODE_NAMES \
1518 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1519 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1520 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1521 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1522 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1523 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1524 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1525 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1527 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1528 {"$a4", RTYPE_GP | 8}, \
1529 {"$a5", RTYPE_GP | 9}, \
1530 {"$a6", RTYPE_GP | 10}, \
1531 {"$a7", RTYPE_GP | 11}, \
1532 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1533 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1534 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1535 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1536 {"$t0", RTYPE_GP | 12}, \
1537 {"$t1", RTYPE_GP | 13}, \
1538 {"$t2", RTYPE_GP | 14}, \
1539 {"$t3", RTYPE_GP | 15}
1541 #define O32_SYMBOLIC_REGISTER_NAMES \
1542 {"$t0", RTYPE_GP | 8}, \
1543 {"$t1", RTYPE_GP | 9}, \
1544 {"$t2", RTYPE_GP | 10}, \
1545 {"$t3", RTYPE_GP | 11}, \
1546 {"$t4", RTYPE_GP | 12}, \
1547 {"$t5", RTYPE_GP | 13}, \
1548 {"$t6", RTYPE_GP | 14}, \
1549 {"$t7", RTYPE_GP | 15}, \
1550 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1551 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1552 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1553 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1555 /* Remaining symbolic register names */
1556 #define SYMBOLIC_REGISTER_NAMES \
1557 {"$zero", RTYPE_GP | 0}, \
1558 {"$at", RTYPE_GP | 1}, \
1559 {"$AT", RTYPE_GP | 1}, \
1560 {"$v0", RTYPE_GP | 2}, \
1561 {"$v1", RTYPE_GP | 3}, \
1562 {"$a0", RTYPE_GP | 4}, \
1563 {"$a1", RTYPE_GP | 5}, \
1564 {"$a2", RTYPE_GP | 6}, \
1565 {"$a3", RTYPE_GP | 7}, \
1566 {"$s0", RTYPE_GP | 16}, \
1567 {"$s1", RTYPE_GP | 17}, \
1568 {"$s2", RTYPE_GP | 18}, \
1569 {"$s3", RTYPE_GP | 19}, \
1570 {"$s4", RTYPE_GP | 20}, \
1571 {"$s5", RTYPE_GP | 21}, \
1572 {"$s6", RTYPE_GP | 22}, \
1573 {"$s7", RTYPE_GP | 23}, \
1574 {"$t8", RTYPE_GP | 24}, \
1575 {"$t9", RTYPE_GP | 25}, \
1576 {"$k0", RTYPE_GP | 26}, \
1577 {"$kt0", RTYPE_GP | 26}, \
1578 {"$k1", RTYPE_GP | 27}, \
1579 {"$kt1", RTYPE_GP | 27}, \
1580 {"$gp", RTYPE_GP | 28}, \
1581 {"$sp", RTYPE_GP | 29}, \
1582 {"$s8", RTYPE_GP | 30}, \
1583 {"$fp", RTYPE_GP | 30}, \
1584 {"$ra", RTYPE_GP | 31}
1586 #define MIPS16_SPECIAL_REGISTER_NAMES \
1587 {"$pc", RTYPE_PC | 0}
1589 #define MDMX_VECTOR_REGISTER_NAMES \
1590 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1591 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1592 {"$v2", RTYPE_VEC | 2}, \
1593 {"$v3", RTYPE_VEC | 3}, \
1594 {"$v4", RTYPE_VEC | 4}, \
1595 {"$v5", RTYPE_VEC | 5}, \
1596 {"$v6", RTYPE_VEC | 6}, \
1597 {"$v7", RTYPE_VEC | 7}, \
1598 {"$v8", RTYPE_VEC | 8}, \
1599 {"$v9", RTYPE_VEC | 9}, \
1600 {"$v10", RTYPE_VEC | 10}, \
1601 {"$v11", RTYPE_VEC | 11}, \
1602 {"$v12", RTYPE_VEC | 12}, \
1603 {"$v13", RTYPE_VEC | 13}, \
1604 {"$v14", RTYPE_VEC | 14}, \
1605 {"$v15", RTYPE_VEC | 15}, \
1606 {"$v16", RTYPE_VEC | 16}, \
1607 {"$v17", RTYPE_VEC | 17}, \
1608 {"$v18", RTYPE_VEC | 18}, \
1609 {"$v19", RTYPE_VEC | 19}, \
1610 {"$v20", RTYPE_VEC | 20}, \
1611 {"$v21", RTYPE_VEC | 21}, \
1612 {"$v22", RTYPE_VEC | 22}, \
1613 {"$v23", RTYPE_VEC | 23}, \
1614 {"$v24", RTYPE_VEC | 24}, \
1615 {"$v25", RTYPE_VEC | 25}, \
1616 {"$v26", RTYPE_VEC | 26}, \
1617 {"$v27", RTYPE_VEC | 27}, \
1618 {"$v28", RTYPE_VEC | 28}, \
1619 {"$v29", RTYPE_VEC | 29}, \
1620 {"$v30", RTYPE_VEC | 30}, \
1621 {"$v31", RTYPE_VEC | 31}
1623 #define MIPS_DSP_ACCUMULATOR_NAMES \
1624 {"$ac0", RTYPE_ACC | 0}, \
1625 {"$ac1", RTYPE_ACC | 1}, \
1626 {"$ac2", RTYPE_ACC | 2}, \
1627 {"$ac3", RTYPE_ACC | 3}
1629 static const struct regname reg_names
[] = {
1630 GENERIC_REGISTER_NUMBERS
,
1632 FPU_CONDITION_CODE_NAMES
,
1633 COPROC_CONDITION_CODE_NAMES
,
1635 /* The $txx registers depends on the abi,
1636 these will be added later into the symbol table from
1637 one of the tables below once mips_abi is set after
1638 parsing of arguments from the command line. */
1639 SYMBOLIC_REGISTER_NAMES
,
1641 MIPS16_SPECIAL_REGISTER_NAMES
,
1642 MDMX_VECTOR_REGISTER_NAMES
,
1643 MIPS_DSP_ACCUMULATOR_NAMES
,
1647 static const struct regname reg_names_o32
[] = {
1648 O32_SYMBOLIC_REGISTER_NAMES
,
1652 static const struct regname reg_names_n32n64
[] = {
1653 N32N64_SYMBOLIC_REGISTER_NAMES
,
1658 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1665 /* Find end of name. */
1667 if (is_name_beginner (*e
))
1669 while (is_part_of_name (*e
))
1672 /* Terminate name. */
1676 /* Look for a register symbol. */
1677 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1679 int r
= S_GET_VALUE (symbolP
);
1681 reg
= r
& RNUM_MASK
;
1682 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1683 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1684 reg
= (r
& RNUM_MASK
) - 2;
1686 /* Else see if this is a register defined in an itbl entry. */
1687 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1694 if (itbl_get_reg_val (n
, &r
))
1695 reg
= r
& RNUM_MASK
;
1698 /* Advance to next token if a register was recognised. */
1701 else if (types
& RWARN
)
1702 as_warn ("Unrecognized register name `%s'", *s
);
1710 /* This function is called once, at assembler startup time. It should set up
1711 all the tables, etc. that the MD part of the assembler will need. */
1716 register const char *retval
= NULL
;
1720 if (mips_pic
!= NO_PIC
)
1722 if (g_switch_seen
&& g_switch_value
!= 0)
1723 as_bad (_("-G may not be used in position-independent code"));
1727 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1728 as_warn (_("Could not set architecture and machine"));
1730 op_hash
= hash_new ();
1732 for (i
= 0; i
< NUMOPCODES
;)
1734 const char *name
= mips_opcodes
[i
].name
;
1736 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1739 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1740 mips_opcodes
[i
].name
, retval
);
1741 /* Probably a memory allocation problem? Give up now. */
1742 as_fatal (_("Broken assembler. No assembly attempted."));
1746 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1748 if (!validate_mips_insn (&mips_opcodes
[i
]))
1750 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1752 create_insn (&nop_insn
, mips_opcodes
+ i
);
1753 nop_insn
.fixed_p
= 1;
1758 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1761 mips16_op_hash
= hash_new ();
1764 while (i
< bfd_mips16_num_opcodes
)
1766 const char *name
= mips16_opcodes
[i
].name
;
1768 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1770 as_fatal (_("internal: can't hash `%s': %s"),
1771 mips16_opcodes
[i
].name
, retval
);
1774 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1775 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1776 != mips16_opcodes
[i
].match
))
1778 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1779 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1782 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1784 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1785 mips16_nop_insn
.fixed_p
= 1;
1789 while (i
< bfd_mips16_num_opcodes
1790 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1794 as_fatal (_("Broken assembler. No assembly attempted."));
1796 /* We add all the general register names to the symbol table. This
1797 helps us detect invalid uses of them. */
1798 for (i
= 0; reg_names
[i
].name
; i
++)
1799 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1800 reg_names
[i
].num
, // & RNUM_MASK,
1801 &zero_address_frag
));
1803 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1804 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1805 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1806 &zero_address_frag
));
1808 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1809 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1810 reg_names_o32
[i
].num
, // & RNUM_MASK,
1811 &zero_address_frag
));
1813 mips_no_prev_insn ();
1816 mips_cprmask
[0] = 0;
1817 mips_cprmask
[1] = 0;
1818 mips_cprmask
[2] = 0;
1819 mips_cprmask
[3] = 0;
1821 /* set the default alignment for the text section (2**2) */
1822 record_alignment (text_section
, 2);
1824 bfd_set_gp_size (stdoutput
, g_switch_value
);
1827 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1829 /* On a native system other than VxWorks, sections must be aligned
1830 to 16 byte boundaries. When configured for an embedded ELF
1831 target, we don't bother. */
1832 if (strcmp (TARGET_OS
, "elf") != 0
1833 && strcmp (TARGET_OS
, "vxworks") != 0)
1835 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1836 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1837 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1840 /* Create a .reginfo section for register masks and a .mdebug
1841 section for debugging information. */
1849 subseg
= now_subseg
;
1851 /* The ABI says this section should be loaded so that the
1852 running program can access it. However, we don't load it
1853 if we are configured for an embedded target */
1854 flags
= SEC_READONLY
| SEC_DATA
;
1855 if (strcmp (TARGET_OS
, "elf") != 0)
1856 flags
|= SEC_ALLOC
| SEC_LOAD
;
1858 if (mips_abi
!= N64_ABI
)
1860 sec
= subseg_new (".reginfo", (subsegT
) 0);
1862 bfd_set_section_flags (stdoutput
, sec
, flags
);
1863 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1865 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1869 /* The 64-bit ABI uses a .MIPS.options section rather than
1870 .reginfo section. */
1871 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1872 bfd_set_section_flags (stdoutput
, sec
, flags
);
1873 bfd_set_section_alignment (stdoutput
, sec
, 3);
1875 /* Set up the option header. */
1877 Elf_Internal_Options opthdr
;
1880 opthdr
.kind
= ODK_REGINFO
;
1881 opthdr
.size
= (sizeof (Elf_External_Options
)
1882 + sizeof (Elf64_External_RegInfo
));
1885 f
= frag_more (sizeof (Elf_External_Options
));
1886 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1887 (Elf_External_Options
*) f
);
1889 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1893 if (ECOFF_DEBUGGING
)
1895 sec
= subseg_new (".mdebug", (subsegT
) 0);
1896 (void) bfd_set_section_flags (stdoutput
, sec
,
1897 SEC_HAS_CONTENTS
| SEC_READONLY
);
1898 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1900 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1902 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1903 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1904 SEC_READONLY
| SEC_RELOC
1906 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1909 subseg_set (seg
, subseg
);
1912 #endif /* OBJ_ELF */
1914 if (! ECOFF_DEBUGGING
)
1917 if (mips_fix_vr4120
)
1918 init_vr4120_conflicts ();
1924 if (! ECOFF_DEBUGGING
)
1929 md_assemble (char *str
)
1931 struct mips_cl_insn insn
;
1932 bfd_reloc_code_real_type unused_reloc
[3]
1933 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1935 imm_expr
.X_op
= O_absent
;
1936 imm2_expr
.X_op
= O_absent
;
1937 offset_expr
.X_op
= O_absent
;
1938 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1939 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1940 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1941 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1942 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1943 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1945 if (mips_opts
.mips16
)
1946 mips16_ip (str
, &insn
);
1949 mips_ip (str
, &insn
);
1950 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1951 str
, insn
.insn_opcode
));
1956 as_bad ("%s `%s'", insn_error
, str
);
1960 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1963 if (mips_opts
.mips16
)
1964 mips16_macro (&insn
);
1971 if (imm_expr
.X_op
!= O_absent
)
1972 append_insn (&insn
, &imm_expr
, imm_reloc
);
1973 else if (offset_expr
.X_op
!= O_absent
)
1974 append_insn (&insn
, &offset_expr
, offset_reloc
);
1976 append_insn (&insn
, NULL
, unused_reloc
);
1980 /* Return true if the given relocation might need a matching %lo().
1981 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1982 need a matching %lo() when applied to local symbols. */
1984 static inline bfd_boolean
1985 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1987 return (HAVE_IN_PLACE_ADDENDS
1988 && (reloc
== BFD_RELOC_HI16_S
1989 || reloc
== BFD_RELOC_MIPS16_HI16_S
1990 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
1991 all GOT16 relocations evaluate to "G". */
1992 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
1995 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1998 static inline bfd_boolean
1999 fixup_has_matching_lo_p (fixS
*fixp
)
2001 return (fixp
->fx_next
!= NULL
2002 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2003 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2004 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2005 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2008 /* See whether instruction IP reads register REG. CLASS is the type
2012 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2013 enum mips_regclass
class)
2015 if (class == MIPS16_REG
)
2017 assert (mips_opts
.mips16
);
2018 reg
= mips16_to_32_reg_map
[reg
];
2019 class = MIPS_GR_REG
;
2022 /* Don't report on general register ZERO, since it never changes. */
2023 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2026 if (class == MIPS_FP_REG
)
2028 assert (! mips_opts
.mips16
);
2029 /* If we are called with either $f0 or $f1, we must check $f0.
2030 This is not optimal, because it will introduce an unnecessary
2031 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2032 need to distinguish reading both $f0 and $f1 or just one of
2033 them. Note that we don't have to check the other way,
2034 because there is no instruction that sets both $f0 and $f1
2035 and requires a delay. */
2036 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2037 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2038 == (reg
&~ (unsigned) 1)))
2040 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2041 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2042 == (reg
&~ (unsigned) 1)))
2045 else if (! mips_opts
.mips16
)
2047 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2048 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2050 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2051 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2056 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2057 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2059 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2060 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2062 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2063 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2066 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2068 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2070 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2072 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2073 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2080 /* This function returns true if modifying a register requires a
2084 reg_needs_delay (unsigned int reg
)
2086 unsigned long prev_pinfo
;
2088 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2089 if (! mips_opts
.noreorder
2090 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2091 && ! gpr_interlocks
)
2092 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2093 && ! cop_interlocks
)))
2095 /* A load from a coprocessor or from memory. All load delays
2096 delay the use of general register rt for one instruction. */
2097 /* Itbl support may require additional care here. */
2098 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2099 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2106 /* Move all labels in insn_labels to the current insertion point. */
2109 mips_move_labels (void)
2111 struct insn_label_list
*l
;
2114 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2116 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2117 symbol_set_frag (l
->label
, frag_now
);
2118 val
= (valueT
) frag_now_fix ();
2119 /* mips16 text labels are stored as odd. */
2120 if (mips_opts
.mips16
)
2122 S_SET_VALUE (l
->label
, val
);
2126 /* Mark instruction labels in mips16 mode. This permits the linker to
2127 handle them specially, such as generating jalx instructions when
2128 needed. We also make them odd for the duration of the assembly, in
2129 order to generate the right sort of code. We will make them even
2130 in the adjust_symtab routine, while leaving them marked. This is
2131 convenient for the debugger and the disassembler. The linker knows
2132 to make them odd again. */
2135 mips16_mark_labels (void)
2137 if (mips_opts
.mips16
)
2139 struct insn_label_list
*l
;
2142 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2145 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2146 S_SET_OTHER (l
->label
, STO_MIPS16
);
2148 val
= S_GET_VALUE (l
->label
);
2150 S_SET_VALUE (l
->label
, val
+ 1);
2155 /* End the current frag. Make it a variant frag and record the
2159 relax_close_frag (void)
2161 mips_macro_warning
.first_frag
= frag_now
;
2162 frag_var (rs_machine_dependent
, 0, 0,
2163 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2164 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2166 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2167 mips_relax
.first_fixup
= 0;
2170 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2171 See the comment above RELAX_ENCODE for more details. */
2174 relax_start (symbolS
*symbol
)
2176 assert (mips_relax
.sequence
== 0);
2177 mips_relax
.sequence
= 1;
2178 mips_relax
.symbol
= symbol
;
2181 /* Start generating the second version of a relaxable sequence.
2182 See the comment above RELAX_ENCODE for more details. */
2187 assert (mips_relax
.sequence
== 1);
2188 mips_relax
.sequence
= 2;
2191 /* End the current relaxable sequence. */
2196 assert (mips_relax
.sequence
== 2);
2197 relax_close_frag ();
2198 mips_relax
.sequence
= 0;
2201 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2202 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2203 by VR4120 errata. */
2206 classify_vr4120_insn (const char *name
)
2208 if (strncmp (name
, "macc", 4) == 0)
2209 return FIX_VR4120_MACC
;
2210 if (strncmp (name
, "dmacc", 5) == 0)
2211 return FIX_VR4120_DMACC
;
2212 if (strncmp (name
, "mult", 4) == 0)
2213 return FIX_VR4120_MULT
;
2214 if (strncmp (name
, "dmult", 5) == 0)
2215 return FIX_VR4120_DMULT
;
2216 if (strstr (name
, "div"))
2217 return FIX_VR4120_DIV
;
2218 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2219 return FIX_VR4120_MTHILO
;
2220 return NUM_FIX_VR4120_CLASSES
;
2223 /* Return the number of instructions that must separate INSN1 and INSN2,
2224 where INSN1 is the earlier instruction. Return the worst-case value
2225 for any INSN2 if INSN2 is null. */
2228 insns_between (const struct mips_cl_insn
*insn1
,
2229 const struct mips_cl_insn
*insn2
)
2231 unsigned long pinfo1
, pinfo2
;
2233 /* This function needs to know which pinfo flags are set for INSN2
2234 and which registers INSN2 uses. The former is stored in PINFO2 and
2235 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2236 will have every flag set and INSN2_USES_REG will always return true. */
2237 pinfo1
= insn1
->insn_mo
->pinfo
;
2238 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2240 #define INSN2_USES_REG(REG, CLASS) \
2241 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2243 /* For most targets, write-after-read dependencies on the HI and LO
2244 registers must be separated by at least two instructions. */
2245 if (!hilo_interlocks
)
2247 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2249 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2253 /* If we're working around r7000 errata, there must be two instructions
2254 between an mfhi or mflo and any instruction that uses the result. */
2255 if (mips_7000_hilo_fix
2256 && MF_HILO_INSN (pinfo1
)
2257 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2260 /* If working around VR4120 errata, check for combinations that need
2261 a single intervening instruction. */
2262 if (mips_fix_vr4120
)
2264 unsigned int class1
, class2
;
2266 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2267 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2271 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2272 if (vr4120_conflicts
[class1
] & (1 << class2
))
2277 if (!mips_opts
.mips16
)
2279 /* Check for GPR or coprocessor load delays. All such delays
2280 are on the RT register. */
2281 /* Itbl support may require additional care here. */
2282 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2283 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2285 know (pinfo1
& INSN_WRITE_GPR_T
);
2286 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2290 /* Check for generic coprocessor hazards.
2292 This case is not handled very well. There is no special
2293 knowledge of CP0 handling, and the coprocessors other than
2294 the floating point unit are not distinguished at all. */
2295 /* Itbl support may require additional care here. FIXME!
2296 Need to modify this to include knowledge about
2297 user specified delays! */
2298 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2299 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2301 /* Handle cases where INSN1 writes to a known general coprocessor
2302 register. There must be a one instruction delay before INSN2
2303 if INSN2 reads that register, otherwise no delay is needed. */
2304 if (pinfo1
& INSN_WRITE_FPR_T
)
2306 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2309 else if (pinfo1
& INSN_WRITE_FPR_S
)
2311 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2316 /* Read-after-write dependencies on the control registers
2317 require a two-instruction gap. */
2318 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2319 && (pinfo2
& INSN_READ_COND_CODE
))
2322 /* We don't know exactly what INSN1 does. If INSN2 is
2323 also a coprocessor instruction, assume there must be
2324 a one instruction gap. */
2325 if (pinfo2
& INSN_COP
)
2330 /* Check for read-after-write dependencies on the coprocessor
2331 control registers in cases where INSN1 does not need a general
2332 coprocessor delay. This means that INSN1 is a floating point
2333 comparison instruction. */
2334 /* Itbl support may require additional care here. */
2335 else if (!cop_interlocks
2336 && (pinfo1
& INSN_WRITE_COND_CODE
)
2337 && (pinfo2
& INSN_READ_COND_CODE
))
2341 #undef INSN2_USES_REG
2346 /* Return the number of nops that would be needed to work around the
2347 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2348 the MAX_VR4130_NOPS instructions described by HISTORY. */
2351 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2352 const struct mips_cl_insn
*insn
)
2356 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2357 are not affected by the errata. */
2359 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2360 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2361 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2364 /* Search for the first MFLO or MFHI. */
2365 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2366 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2368 /* Extract the destination register. */
2369 if (mips_opts
.mips16
)
2370 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2372 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2374 /* No nops are needed if INSN reads that register. */
2375 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2378 /* ...or if any of the intervening instructions do. */
2379 for (j
= 0; j
< i
; j
++)
2380 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2383 return MAX_VR4130_NOPS
- i
;
2388 /* Return the number of nops that would be needed if instruction INSN
2389 immediately followed the MAX_NOPS instructions given by HISTORY,
2390 where HISTORY[0] is the most recent instruction. If INSN is null,
2391 return the worse-case number of nops for any instruction. */
2394 nops_for_insn (const struct mips_cl_insn
*history
,
2395 const struct mips_cl_insn
*insn
)
2397 int i
, nops
, tmp_nops
;
2400 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2401 if (!history
[i
].noreorder_p
)
2403 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2404 if (tmp_nops
> nops
)
2408 if (mips_fix_vr4130
)
2410 tmp_nops
= nops_for_vr4130 (history
, insn
);
2411 if (tmp_nops
> nops
)
2418 /* The variable arguments provide NUM_INSNS extra instructions that
2419 might be added to HISTORY. Return the largest number of nops that
2420 would be needed after the extended sequence. */
2423 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2426 struct mips_cl_insn buffer
[MAX_NOPS
];
2427 struct mips_cl_insn
*cursor
;
2430 va_start (args
, history
);
2431 cursor
= buffer
+ num_insns
;
2432 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2433 while (cursor
> buffer
)
2434 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2436 nops
= nops_for_insn (buffer
, NULL
);
2441 /* Like nops_for_insn, but if INSN is a branch, take into account the
2442 worst-case delay for the branch target. */
2445 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2446 const struct mips_cl_insn
*insn
)
2450 nops
= nops_for_insn (history
, insn
);
2451 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2452 | INSN_COND_BRANCH_DELAY
2453 | INSN_COND_BRANCH_LIKELY
))
2455 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2456 if (tmp_nops
> nops
)
2459 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2461 tmp_nops
= nops_for_sequence (1, history
, insn
);
2462 if (tmp_nops
> nops
)
2468 /* Output an instruction. IP is the instruction information.
2469 ADDRESS_EXPR is an operand of the instruction to be used with
2473 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2474 bfd_reloc_code_real_type
*reloc_type
)
2476 register unsigned long prev_pinfo
, pinfo
;
2477 relax_stateT prev_insn_frag_type
= 0;
2478 bfd_boolean relaxed_branch
= FALSE
;
2480 /* Mark instruction labels in mips16 mode. */
2481 mips16_mark_labels ();
2483 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2484 pinfo
= ip
->insn_mo
->pinfo
;
2486 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2488 /* There are a lot of optimizations we could do that we don't.
2489 In particular, we do not, in general, reorder instructions.
2490 If you use gcc with optimization, it will reorder
2491 instructions and generally do much more optimization then we
2492 do here; repeating all that work in the assembler would only
2493 benefit hand written assembly code, and does not seem worth
2495 int nops
= (mips_optimize
== 0
2496 ? nops_for_insn (history
, NULL
)
2497 : nops_for_insn_or_target (history
, ip
));
2501 unsigned long old_frag_offset
;
2504 old_frag
= frag_now
;
2505 old_frag_offset
= frag_now_fix ();
2507 for (i
= 0; i
< nops
; i
++)
2512 listing_prev_line ();
2513 /* We may be at the start of a variant frag. In case we
2514 are, make sure there is enough space for the frag
2515 after the frags created by listing_prev_line. The
2516 argument to frag_grow here must be at least as large
2517 as the argument to all other calls to frag_grow in
2518 this file. We don't have to worry about being in the
2519 middle of a variant frag, because the variants insert
2520 all needed nop instructions themselves. */
2524 mips_move_labels ();
2526 #ifndef NO_ECOFF_DEBUGGING
2527 if (ECOFF_DEBUGGING
)
2528 ecoff_fix_loc (old_frag
, old_frag_offset
);
2532 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2534 /* Work out how many nops in prev_nop_frag are needed by IP. */
2535 int nops
= nops_for_insn_or_target (history
, ip
);
2536 assert (nops
<= prev_nop_frag_holds
);
2538 /* Enforce NOPS as a minimum. */
2539 if (nops
> prev_nop_frag_required
)
2540 prev_nop_frag_required
= nops
;
2542 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2544 /* Settle for the current number of nops. Update the history
2545 accordingly (for the benefit of any future .set reorder code). */
2546 prev_nop_frag
= NULL
;
2547 insert_into_history (prev_nop_frag_since
,
2548 prev_nop_frag_holds
, NOP_INSN
);
2552 /* Allow this instruction to replace one of the nops that was
2553 tentatively added to prev_nop_frag. */
2554 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2555 prev_nop_frag_holds
--;
2556 prev_nop_frag_since
++;
2561 /* The value passed to dwarf2_emit_insn is the distance between
2562 the beginning of the current instruction and the address that
2563 should be recorded in the debug tables. For MIPS16 debug info
2564 we want to use ISA-encoded addresses, so we pass -1 for an
2565 address higher by one than the current. */
2566 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2569 /* Record the frag type before frag_var. */
2570 if (history
[0].frag
)
2571 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2574 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2575 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2576 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2577 && mips_relax_branch
2578 /* Don't try branch relaxation within .set nomacro, or within
2579 .set noat if we use $at for PIC computations. If it turns
2580 out that the branch was out-of-range, we'll get an error. */
2581 && !mips_opts
.warn_about_macros
2582 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2583 && !mips_opts
.mips16
)
2585 relaxed_branch
= TRUE
;
2586 add_relaxed_insn (ip
, (relaxed_branch_length
2588 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2589 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2592 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2593 pinfo
& INSN_COND_BRANCH_LIKELY
,
2594 pinfo
& INSN_WRITE_GPR_31
,
2596 address_expr
->X_add_symbol
,
2597 address_expr
->X_add_number
);
2598 *reloc_type
= BFD_RELOC_UNUSED
;
2600 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2602 /* We need to set up a variant frag. */
2603 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2604 add_relaxed_insn (ip
, 4, 0,
2606 (*reloc_type
- BFD_RELOC_UNUSED
,
2607 mips16_small
, mips16_ext
,
2608 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2609 history
[0].mips16_absolute_jump_p
),
2610 make_expr_symbol (address_expr
), 0);
2612 else if (mips_opts
.mips16
2614 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2616 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2617 /* Make sure there is enough room to swap this instruction with
2618 a following jump instruction. */
2620 add_fixed_insn (ip
);
2624 if (mips_opts
.mips16
2625 && mips_opts
.noreorder
2626 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2627 as_warn (_("extended instruction in delay slot"));
2629 if (mips_relax
.sequence
)
2631 /* If we've reached the end of this frag, turn it into a variant
2632 frag and record the information for the instructions we've
2634 if (frag_room () < 4)
2635 relax_close_frag ();
2636 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2639 if (mips_relax
.sequence
!= 2)
2640 mips_macro_warning
.sizes
[0] += 4;
2641 if (mips_relax
.sequence
!= 1)
2642 mips_macro_warning
.sizes
[1] += 4;
2644 if (mips_opts
.mips16
)
2647 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2649 add_fixed_insn (ip
);
2652 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2654 if (address_expr
->X_op
== O_constant
)
2658 switch (*reloc_type
)
2661 ip
->insn_opcode
|= address_expr
->X_add_number
;
2664 case BFD_RELOC_MIPS_HIGHEST
:
2665 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2666 ip
->insn_opcode
|= tmp
& 0xffff;
2669 case BFD_RELOC_MIPS_HIGHER
:
2670 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2671 ip
->insn_opcode
|= tmp
& 0xffff;
2674 case BFD_RELOC_HI16_S
:
2675 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2676 ip
->insn_opcode
|= tmp
& 0xffff;
2679 case BFD_RELOC_HI16
:
2680 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2683 case BFD_RELOC_UNUSED
:
2684 case BFD_RELOC_LO16
:
2685 case BFD_RELOC_MIPS_GOT_DISP
:
2686 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2689 case BFD_RELOC_MIPS_JMP
:
2690 if ((address_expr
->X_add_number
& 3) != 0)
2691 as_bad (_("jump to misaligned address (0x%lx)"),
2692 (unsigned long) address_expr
->X_add_number
);
2693 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2696 case BFD_RELOC_MIPS16_JMP
:
2697 if ((address_expr
->X_add_number
& 3) != 0)
2698 as_bad (_("jump to misaligned address (0x%lx)"),
2699 (unsigned long) address_expr
->X_add_number
);
2701 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2702 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2703 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2706 case BFD_RELOC_16_PCREL_S2
:
2707 if ((address_expr
->X_add_number
& 3) != 0)
2708 as_bad (_("branch to misaligned address (0x%lx)"),
2709 (unsigned long) address_expr
->X_add_number
);
2710 if (mips_relax_branch
)
2712 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2713 as_bad (_("branch address range overflow (0x%lx)"),
2714 (unsigned long) address_expr
->X_add_number
);
2715 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2722 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2725 reloc_howto_type
*howto
;
2728 /* In a compound relocation, it is the final (outermost)
2729 operator that determines the relocated field. */
2730 for (i
= 1; i
< 3; i
++)
2731 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2734 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2735 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2736 bfd_get_reloc_size (howto
),
2738 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2741 /* These relocations can have an addend that won't fit in
2742 4 octets for 64bit assembly. */
2744 && ! howto
->partial_inplace
2745 && (reloc_type
[0] == BFD_RELOC_16
2746 || reloc_type
[0] == BFD_RELOC_32
2747 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2748 || reloc_type
[0] == BFD_RELOC_HI16_S
2749 || reloc_type
[0] == BFD_RELOC_LO16
2750 || reloc_type
[0] == BFD_RELOC_GPREL16
2751 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2752 || reloc_type
[0] == BFD_RELOC_GPREL32
2753 || reloc_type
[0] == BFD_RELOC_64
2754 || reloc_type
[0] == BFD_RELOC_CTOR
2755 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2756 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2757 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2758 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2759 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2760 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2761 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2762 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2763 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2764 ip
->fixp
[0]->fx_no_overflow
= 1;
2766 if (mips_relax
.sequence
)
2768 if (mips_relax
.first_fixup
== 0)
2769 mips_relax
.first_fixup
= ip
->fixp
[0];
2771 else if (reloc_needs_lo_p (*reloc_type
))
2773 struct mips_hi_fixup
*hi_fixup
;
2775 /* Reuse the last entry if it already has a matching %lo. */
2776 hi_fixup
= mips_hi_fixup_list
;
2778 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2780 hi_fixup
= ((struct mips_hi_fixup
*)
2781 xmalloc (sizeof (struct mips_hi_fixup
)));
2782 hi_fixup
->next
= mips_hi_fixup_list
;
2783 mips_hi_fixup_list
= hi_fixup
;
2785 hi_fixup
->fixp
= ip
->fixp
[0];
2786 hi_fixup
->seg
= now_seg
;
2789 /* Add fixups for the second and third relocations, if given.
2790 Note that the ABI allows the second relocation to be
2791 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2792 moment we only use RSS_UNDEF, but we could add support
2793 for the others if it ever becomes necessary. */
2794 for (i
= 1; i
< 3; i
++)
2795 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2797 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2798 ip
->fixp
[0]->fx_size
, NULL
, 0,
2799 FALSE
, reloc_type
[i
]);
2801 /* Use fx_tcbit to mark compound relocs. */
2802 ip
->fixp
[0]->fx_tcbit
= 1;
2803 ip
->fixp
[i
]->fx_tcbit
= 1;
2809 /* Update the register mask information. */
2810 if (! mips_opts
.mips16
)
2812 if (pinfo
& INSN_WRITE_GPR_D
)
2813 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2814 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2815 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2816 if (pinfo
& INSN_READ_GPR_S
)
2817 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2818 if (pinfo
& INSN_WRITE_GPR_31
)
2819 mips_gprmask
|= 1 << RA
;
2820 if (pinfo
& INSN_WRITE_FPR_D
)
2821 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2822 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2823 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2824 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2825 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2826 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2827 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2828 if (pinfo
& INSN_COP
)
2830 /* We don't keep enough information to sort these cases out.
2831 The itbl support does keep this information however, although
2832 we currently don't support itbl fprmats as part of the cop
2833 instruction. May want to add this support in the future. */
2835 /* Never set the bit for $0, which is always zero. */
2836 mips_gprmask
&= ~1 << 0;
2840 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2841 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2842 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2843 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2844 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2845 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2846 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2847 mips_gprmask
|= 1 << TREG
;
2848 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2849 mips_gprmask
|= 1 << SP
;
2850 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2851 mips_gprmask
|= 1 << RA
;
2852 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2853 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2854 if (pinfo
& MIPS16_INSN_READ_Z
)
2855 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2856 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2857 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2860 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2862 /* Filling the branch delay slot is more complex. We try to
2863 switch the branch with the previous instruction, which we can
2864 do if the previous instruction does not set up a condition
2865 that the branch tests and if the branch is not itself the
2866 target of any branch. */
2867 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2868 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2870 if (mips_optimize
< 2
2871 /* If we have seen .set volatile or .set nomove, don't
2873 || mips_opts
.nomove
!= 0
2874 /* We can't swap if the previous instruction's position
2876 || history
[0].fixed_p
2877 /* If the previous previous insn was in a .set
2878 noreorder, we can't swap. Actually, the MIPS
2879 assembler will swap in this situation. However, gcc
2880 configured -with-gnu-as will generate code like
2886 in which we can not swap the bne and INSN. If gcc is
2887 not configured -with-gnu-as, it does not output the
2889 || history
[1].noreorder_p
2890 /* If the branch is itself the target of a branch, we
2891 can not swap. We cheat on this; all we check for is
2892 whether there is a label on this instruction. If
2893 there are any branches to anything other than a
2894 label, users must use .set noreorder. */
2895 || insn_labels
!= NULL
2896 /* If the previous instruction is in a variant frag
2897 other than this branch's one, we cannot do the swap.
2898 This does not apply to the mips16, which uses variant
2899 frags for different purposes. */
2900 || (! mips_opts
.mips16
2901 && prev_insn_frag_type
== rs_machine_dependent
)
2902 /* Check for conflicts between the branch and the instructions
2903 before the candidate delay slot. */
2904 || nops_for_insn (history
+ 1, ip
) > 0
2905 /* Check for conflicts between the swapped sequence and the
2906 target of the branch. */
2907 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2908 /* We do not swap with a trap instruction, since it
2909 complicates trap handlers to have the trap
2910 instruction be in a delay slot. */
2911 || (prev_pinfo
& INSN_TRAP
)
2912 /* If the branch reads a register that the previous
2913 instruction sets, we can not swap. */
2914 || (! mips_opts
.mips16
2915 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2916 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2918 || (! mips_opts
.mips16
2919 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2920 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2922 || (mips_opts
.mips16
2923 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2925 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2927 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2929 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2931 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2933 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2935 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2936 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2937 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2938 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2939 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2940 && insn_uses_reg (ip
,
2941 MIPS16OP_EXTRACT_REG32R
2942 (history
[0].insn_opcode
),
2944 /* If the branch writes a register that the previous
2945 instruction sets, we can not swap (we know that
2946 branches write only to RD or to $31). */
2947 || (! mips_opts
.mips16
2948 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2949 && (((pinfo
& INSN_WRITE_GPR_D
)
2950 && (EXTRACT_OPERAND (RT
, history
[0])
2951 == EXTRACT_OPERAND (RD
, *ip
)))
2952 || ((pinfo
& INSN_WRITE_GPR_31
)
2953 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2954 || (! mips_opts
.mips16
2955 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2956 && (((pinfo
& INSN_WRITE_GPR_D
)
2957 && (EXTRACT_OPERAND (RD
, history
[0])
2958 == EXTRACT_OPERAND (RD
, *ip
)))
2959 || ((pinfo
& INSN_WRITE_GPR_31
)
2960 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2961 || (mips_opts
.mips16
2962 && (pinfo
& MIPS16_INSN_WRITE_31
)
2963 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2964 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2965 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2967 /* If the branch writes a register that the previous
2968 instruction reads, we can not swap (we know that
2969 branches only write to RD or to $31). */
2970 || (! mips_opts
.mips16
2971 && (pinfo
& INSN_WRITE_GPR_D
)
2972 && insn_uses_reg (&history
[0],
2973 EXTRACT_OPERAND (RD
, *ip
),
2975 || (! mips_opts
.mips16
2976 && (pinfo
& INSN_WRITE_GPR_31
)
2977 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2978 || (mips_opts
.mips16
2979 && (pinfo
& MIPS16_INSN_WRITE_31
)
2980 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2981 /* If one instruction sets a condition code and the
2982 other one uses a condition code, we can not swap. */
2983 || ((pinfo
& INSN_READ_COND_CODE
)
2984 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2985 || ((pinfo
& INSN_WRITE_COND_CODE
)
2986 && (prev_pinfo
& INSN_READ_COND_CODE
))
2987 /* If the previous instruction uses the PC, we can not
2989 || (mips_opts
.mips16
2990 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2991 /* If the previous instruction had a fixup in mips16
2992 mode, we can not swap. This normally means that the
2993 previous instruction was a 4 byte branch anyhow. */
2994 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2995 /* If the previous instruction is a sync, sync.l, or
2996 sync.p, we can not swap. */
2997 || (prev_pinfo
& INSN_SYNC
))
2999 if (mips_opts
.mips16
3000 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3001 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3002 && (mips_opts
.isa
== ISA_MIPS32
3003 || mips_opts
.isa
== ISA_MIPS32R2
3004 || mips_opts
.isa
== ISA_MIPS64
3005 || mips_opts
.isa
== ISA_MIPS64R2
))
3007 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3008 ip
->insn_opcode
|= 0x0080;
3010 insert_into_history (0, 1, ip
);
3014 /* We could do even better for unconditional branches to
3015 portions of this object file; we could pick up the
3016 instruction at the destination, put it in the delay
3017 slot, and bump the destination address. */
3018 insert_into_history (0, 1, ip
);
3022 if (mips_relax
.sequence
)
3023 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3027 /* It looks like we can actually do the swap. */
3028 struct mips_cl_insn delay
= history
[0];
3029 if (mips_opts
.mips16
)
3031 know (delay
.frag
== ip
->frag
);
3032 move_insn (ip
, delay
.frag
, delay
.where
);
3033 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3035 else if (relaxed_branch
)
3037 /* Add the delay slot instruction to the end of the
3038 current frag and shrink the fixed part of the
3039 original frag. If the branch occupies the tail of
3040 the latter, move it backwards to cover the gap. */
3041 delay
.frag
->fr_fix
-= 4;
3042 if (delay
.frag
== ip
->frag
)
3043 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3044 add_fixed_insn (&delay
);
3048 move_insn (&delay
, ip
->frag
, ip
->where
);
3049 move_insn (ip
, history
[0].frag
, history
[0].where
);
3053 insert_into_history (0, 1, &delay
);
3056 /* If that was an unconditional branch, forget the previous
3057 insn information. */
3058 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3059 mips_no_prev_insn ();
3061 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3063 /* We don't yet optimize a branch likely. What we should do
3064 is look at the target, copy the instruction found there
3065 into the delay slot, and increment the branch to jump to
3066 the next instruction. */
3067 insert_into_history (0, 1, ip
);
3071 insert_into_history (0, 1, ip
);
3074 insert_into_history (0, 1, ip
);
3076 /* We just output an insn, so the next one doesn't have a label. */
3077 mips_clear_insn_labels ();
3080 /* Forget that there was any previous instruction or label. */
3083 mips_no_prev_insn (void)
3085 prev_nop_frag
= NULL
;
3086 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3087 mips_clear_insn_labels ();
3090 /* This function must be called before we emit something other than
3091 instructions. It is like mips_no_prev_insn except that it inserts
3092 any NOPS that might be needed by previous instructions. */
3095 mips_emit_delays (void)
3097 if (! mips_opts
.noreorder
)
3099 int nops
= nops_for_insn (history
, NULL
);
3103 add_fixed_insn (NOP_INSN
);
3104 mips_move_labels ();
3107 mips_no_prev_insn ();
3110 /* Start a (possibly nested) noreorder block. */
3113 start_noreorder (void)
3115 if (mips_opts
.noreorder
== 0)
3120 /* None of the instructions before the .set noreorder can be moved. */
3121 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3122 history
[i
].fixed_p
= 1;
3124 /* Insert any nops that might be needed between the .set noreorder
3125 block and the previous instructions. We will later remove any
3126 nops that turn out not to be needed. */
3127 nops
= nops_for_insn (history
, NULL
);
3130 if (mips_optimize
!= 0)
3132 /* Record the frag which holds the nop instructions, so
3133 that we can remove them if we don't need them. */
3134 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3135 prev_nop_frag
= frag_now
;
3136 prev_nop_frag_holds
= nops
;
3137 prev_nop_frag_required
= 0;
3138 prev_nop_frag_since
= 0;
3141 for (; nops
> 0; --nops
)
3142 add_fixed_insn (NOP_INSN
);
3144 /* Move on to a new frag, so that it is safe to simply
3145 decrease the size of prev_nop_frag. */
3146 frag_wane (frag_now
);
3148 mips_move_labels ();
3150 mips16_mark_labels ();
3151 mips_clear_insn_labels ();
3153 mips_opts
.noreorder
++;
3154 mips_any_noreorder
= 1;
3157 /* End a nested noreorder block. */
3160 end_noreorder (void)
3162 mips_opts
.noreorder
--;
3163 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3165 /* Commit to inserting prev_nop_frag_required nops and go back to
3166 handling nop insertion the .set reorder way. */
3167 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3168 * (mips_opts
.mips16
? 2 : 4));
3169 insert_into_history (prev_nop_frag_since
,
3170 prev_nop_frag_required
, NOP_INSN
);
3171 prev_nop_frag
= NULL
;
3175 /* Set up global variables for the start of a new macro. */
3180 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3181 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3182 && (history
[0].insn_mo
->pinfo
3183 & (INSN_UNCOND_BRANCH_DELAY
3184 | INSN_COND_BRANCH_DELAY
3185 | INSN_COND_BRANCH_LIKELY
)) != 0);
3188 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3189 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3190 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3193 macro_warning (relax_substateT subtype
)
3195 if (subtype
& RELAX_DELAY_SLOT
)
3196 return _("Macro instruction expanded into multiple instructions"
3197 " in a branch delay slot");
3198 else if (subtype
& RELAX_NOMACRO
)
3199 return _("Macro instruction expanded into multiple instructions");
3204 /* Finish up a macro. Emit warnings as appropriate. */
3209 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3211 relax_substateT subtype
;
3213 /* Set up the relaxation warning flags. */
3215 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3216 subtype
|= RELAX_SECOND_LONGER
;
3217 if (mips_opts
.warn_about_macros
)
3218 subtype
|= RELAX_NOMACRO
;
3219 if (mips_macro_warning
.delay_slot_p
)
3220 subtype
|= RELAX_DELAY_SLOT
;
3222 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3224 /* Either the macro has a single implementation or both
3225 implementations are longer than 4 bytes. Emit the
3227 const char *msg
= macro_warning (subtype
);
3233 /* One implementation might need a warning but the other
3234 definitely doesn't. */
3235 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3240 /* Read a macro's relocation codes from *ARGS and store them in *R.
3241 The first argument in *ARGS will be either the code for a single
3242 relocation or -1 followed by the three codes that make up a
3243 composite relocation. */
3246 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3250 next
= va_arg (*args
, int);
3252 r
[0] = (bfd_reloc_code_real_type
) next
;
3254 for (i
= 0; i
< 3; i
++)
3255 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3258 /* Build an instruction created by a macro expansion. This is passed
3259 a pointer to the count of instructions created so far, an
3260 expression, the name of the instruction to build, an operand format
3261 string, and corresponding arguments. */
3264 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3266 const struct mips_opcode
*mo
;
3267 struct mips_cl_insn insn
;
3268 bfd_reloc_code_real_type r
[3];
3271 va_start (args
, fmt
);
3273 if (mips_opts
.mips16
)
3275 mips16_macro_build (ep
, name
, fmt
, args
);
3280 r
[0] = BFD_RELOC_UNUSED
;
3281 r
[1] = BFD_RELOC_UNUSED
;
3282 r
[2] = BFD_RELOC_UNUSED
;
3283 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3285 assert (strcmp (name
, mo
->name
) == 0);
3287 /* Search until we get a match for NAME. It is assumed here that
3288 macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */
3289 while (strcmp (fmt
, mo
->args
) != 0
3290 || mo
->pinfo
== INSN_MACRO
3291 || !OPCODE_IS_MEMBER (mo
,
3293 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3294 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3296 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3300 assert (strcmp (name
, mo
->name
) == 0);
3303 create_insn (&insn
, mo
);
3321 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3326 /* Note that in the macro case, these arguments are already
3327 in MSB form. (When handling the instruction in the
3328 non-macro case, these arguments are sizes from which
3329 MSB values must be calculated.) */
3330 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3336 /* Note that in the macro case, these arguments are already
3337 in MSBD form. (When handling the instruction in the
3338 non-macro case, these arguments are sizes from which
3339 MSBD values must be calculated.) */
3340 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3351 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3355 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3360 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3366 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3371 int tmp
= va_arg (args
, int);
3373 INSERT_OPERAND (RT
, insn
, tmp
);
3374 INSERT_OPERAND (RD
, insn
, tmp
);
3380 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3387 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3391 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3395 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3399 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3403 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3410 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3416 macro_read_relocs (&args
, r
);
3417 assert (*r
== BFD_RELOC_GPREL16
3418 || *r
== BFD_RELOC_MIPS_LITERAL
3419 || *r
== BFD_RELOC_MIPS_HIGHER
3420 || *r
== BFD_RELOC_HI16_S
3421 || *r
== BFD_RELOC_LO16
3422 || *r
== BFD_RELOC_MIPS_GOT16
3423 || *r
== BFD_RELOC_MIPS_CALL16
3424 || *r
== BFD_RELOC_MIPS_GOT_DISP
3425 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3426 || *r
== BFD_RELOC_MIPS_GOT_OFST
3427 || *r
== BFD_RELOC_MIPS_GOT_LO16
3428 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3432 macro_read_relocs (&args
, r
);
3434 && (ep
->X_op
== O_constant
3435 || (ep
->X_op
== O_symbol
3436 && (*r
== BFD_RELOC_MIPS_HIGHEST
3437 || *r
== BFD_RELOC_HI16_S
3438 || *r
== BFD_RELOC_HI16
3439 || *r
== BFD_RELOC_GPREL16
3440 || *r
== BFD_RELOC_MIPS_GOT_HI16
3441 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3445 assert (ep
!= NULL
);
3448 * This allows macro() to pass an immediate expression for
3449 * creating short branches without creating a symbol.
3451 * We don't allow branch relaxation for these branches, as
3452 * they should only appear in ".set nomacro" anyway.
3454 if (ep
->X_op
== O_constant
)
3456 if ((ep
->X_add_number
& 3) != 0)
3457 as_bad (_("branch to misaligned address (0x%lx)"),
3458 (unsigned long) ep
->X_add_number
);
3459 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3460 as_bad (_("branch address range overflow (0x%lx)"),
3461 (unsigned long) ep
->X_add_number
);
3462 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3466 *r
= BFD_RELOC_16_PCREL_S2
;
3470 assert (ep
!= NULL
);
3471 *r
= BFD_RELOC_MIPS_JMP
;
3475 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3479 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3488 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3490 append_insn (&insn
, ep
, r
);
3494 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3497 struct mips_opcode
*mo
;
3498 struct mips_cl_insn insn
;
3499 bfd_reloc_code_real_type r
[3]
3500 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3502 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3504 assert (strcmp (name
, mo
->name
) == 0);
3506 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3510 assert (strcmp (name
, mo
->name
) == 0);
3513 create_insn (&insn
, mo
);
3531 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3536 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3540 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3544 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3554 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3561 regno
= va_arg (args
, int);
3562 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3563 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3584 assert (ep
!= NULL
);
3586 if (ep
->X_op
!= O_constant
)
3587 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3590 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3591 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3594 *r
= BFD_RELOC_UNUSED
;
3600 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3607 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3609 append_insn (&insn
, ep
, r
);
3613 * Sign-extend 32-bit mode constants that have bit 31 set and all
3614 * higher bits unset.
3617 normalize_constant_expr (expressionS
*ex
)
3619 if (ex
->X_op
== O_constant
3620 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3621 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3626 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3627 * all higher bits unset.
3630 normalize_address_expr (expressionS
*ex
)
3632 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3633 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3634 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3635 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3640 * Generate a "jalr" instruction with a relocation hint to the called
3641 * function. This occurs in NewABI PIC code.
3644 macro_build_jalr (expressionS
*ep
)
3653 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3655 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3656 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3660 * Generate a "lui" instruction.
3663 macro_build_lui (expressionS
*ep
, int regnum
)
3665 expressionS high_expr
;
3666 const struct mips_opcode
*mo
;
3667 struct mips_cl_insn insn
;
3668 bfd_reloc_code_real_type r
[3]
3669 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3670 const char *name
= "lui";
3671 const char *fmt
= "t,u";
3673 assert (! mips_opts
.mips16
);
3677 if (high_expr
.X_op
== O_constant
)
3679 /* we can compute the instruction now without a relocation entry */
3680 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3682 *r
= BFD_RELOC_UNUSED
;
3686 assert (ep
->X_op
== O_symbol
);
3687 /* _gp_disp is a special case, used from s_cpload.
3688 __gnu_local_gp is used if mips_no_shared. */
3689 assert (mips_pic
== NO_PIC
3691 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3692 || (! mips_in_shared
3693 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3694 "__gnu_local_gp") == 0));
3695 *r
= BFD_RELOC_HI16_S
;
3698 mo
= hash_find (op_hash
, name
);
3699 assert (strcmp (name
, mo
->name
) == 0);
3700 assert (strcmp (fmt
, mo
->args
) == 0);
3701 create_insn (&insn
, mo
);
3703 insn
.insn_opcode
= insn
.insn_mo
->match
;
3704 INSERT_OPERAND (RT
, insn
, regnum
);
3705 if (*r
== BFD_RELOC_UNUSED
)
3707 insn
.insn_opcode
|= high_expr
.X_add_number
;
3708 append_insn (&insn
, NULL
, r
);
3711 append_insn (&insn
, &high_expr
, r
);
3714 /* Generate a sequence of instructions to do a load or store from a constant
3715 offset off of a base register (breg) into/from a target register (treg),
3716 using AT if necessary. */
3718 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3719 int treg
, int breg
, int dbl
)
3721 assert (ep
->X_op
== O_constant
);
3723 /* Sign-extending 32-bit constants makes their handling easier. */
3725 normalize_constant_expr (ep
);
3727 /* Right now, this routine can only handle signed 32-bit constants. */
3728 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3729 as_warn (_("operand overflow"));
3731 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3733 /* Signed 16-bit offset will fit in the op. Easy! */
3734 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3738 /* 32-bit offset, need multiple instructions and AT, like:
3739 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3740 addu $tempreg,$tempreg,$breg
3741 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3742 to handle the complete offset. */
3743 macro_build_lui (ep
, AT
);
3744 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3745 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3748 as_bad (_("Macro used $at after \".set noat\""));
3753 * Generates code to set the $at register to true (one)
3754 * if reg is less than the immediate expression.
3757 set_at (int reg
, int unsignedp
)
3759 if (imm_expr
.X_op
== O_constant
3760 && imm_expr
.X_add_number
>= -0x8000
3761 && imm_expr
.X_add_number
< 0x8000)
3762 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3763 AT
, reg
, BFD_RELOC_LO16
);
3766 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3767 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3771 /* Warn if an expression is not a constant. */
3774 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3776 if (ex
->X_op
== O_big
)
3777 as_bad (_("unsupported large constant"));
3778 else if (ex
->X_op
!= O_constant
)
3779 as_bad (_("Instruction %s requires absolute expression"),
3782 if (HAVE_32BIT_GPRS
)
3783 normalize_constant_expr (ex
);
3786 /* Count the leading zeroes by performing a binary chop. This is a
3787 bulky bit of source, but performance is a LOT better for the
3788 majority of values than a simple loop to count the bits:
3789 for (lcnt = 0; (lcnt < 32); lcnt++)
3790 if ((v) & (1 << (31 - lcnt)))
3792 However it is not code size friendly, and the gain will drop a bit
3793 on certain cached systems.
3795 #define COUNT_TOP_ZEROES(v) \
3796 (((v) & ~0xffff) == 0 \
3797 ? ((v) & ~0xff) == 0 \
3798 ? ((v) & ~0xf) == 0 \
3799 ? ((v) & ~0x3) == 0 \
3800 ? ((v) & ~0x1) == 0 \
3805 : ((v) & ~0x7) == 0 \
3808 : ((v) & ~0x3f) == 0 \
3809 ? ((v) & ~0x1f) == 0 \
3812 : ((v) & ~0x7f) == 0 \
3815 : ((v) & ~0xfff) == 0 \
3816 ? ((v) & ~0x3ff) == 0 \
3817 ? ((v) & ~0x1ff) == 0 \
3820 : ((v) & ~0x7ff) == 0 \
3823 : ((v) & ~0x3fff) == 0 \
3824 ? ((v) & ~0x1fff) == 0 \
3827 : ((v) & ~0x7fff) == 0 \
3830 : ((v) & ~0xffffff) == 0 \
3831 ? ((v) & ~0xfffff) == 0 \
3832 ? ((v) & ~0x3ffff) == 0 \
3833 ? ((v) & ~0x1ffff) == 0 \
3836 : ((v) & ~0x7ffff) == 0 \
3839 : ((v) & ~0x3fffff) == 0 \
3840 ? ((v) & ~0x1fffff) == 0 \
3843 : ((v) & ~0x7fffff) == 0 \
3846 : ((v) & ~0xfffffff) == 0 \
3847 ? ((v) & ~0x3ffffff) == 0 \
3848 ? ((v) & ~0x1ffffff) == 0 \
3851 : ((v) & ~0x7ffffff) == 0 \
3854 : ((v) & ~0x3fffffff) == 0 \
3855 ? ((v) & ~0x1fffffff) == 0 \
3858 : ((v) & ~0x7fffffff) == 0 \
3863 * This routine generates the least number of instructions necessary to load
3864 * an absolute expression value into a register.
3867 load_register (int reg
, expressionS
*ep
, int dbl
)
3870 expressionS hi32
, lo32
;
3872 if (ep
->X_op
!= O_big
)
3874 assert (ep
->X_op
== O_constant
);
3876 /* Sign-extending 32-bit constants makes their handling easier. */
3878 normalize_constant_expr (ep
);
3880 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3882 /* We can handle 16 bit signed values with an addiu to
3883 $zero. No need to ever use daddiu here, since $zero and
3884 the result are always correct in 32 bit mode. */
3885 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3888 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3890 /* We can handle 16 bit unsigned values with an ori to
3892 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3895 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3897 /* 32 bit values require an lui. */
3898 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3899 if ((ep
->X_add_number
& 0xffff) != 0)
3900 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3905 /* The value is larger than 32 bits. */
3907 if (!dbl
|| HAVE_32BIT_GPRS
)
3911 sprintf_vma (value
, ep
->X_add_number
);
3912 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3913 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3917 if (ep
->X_op
!= O_big
)
3920 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3921 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3922 hi32
.X_add_number
&= 0xffffffff;
3924 lo32
.X_add_number
&= 0xffffffff;
3928 assert (ep
->X_add_number
> 2);
3929 if (ep
->X_add_number
== 3)
3930 generic_bignum
[3] = 0;
3931 else if (ep
->X_add_number
> 4)
3932 as_bad (_("Number larger than 64 bits"));
3933 lo32
.X_op
= O_constant
;
3934 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3935 hi32
.X_op
= O_constant
;
3936 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3939 if (hi32
.X_add_number
== 0)
3944 unsigned long hi
, lo
;
3946 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3948 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3950 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3953 if (lo32
.X_add_number
& 0x80000000)
3955 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3956 if (lo32
.X_add_number
& 0xffff)
3957 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3962 /* Check for 16bit shifted constant. We know that hi32 is
3963 non-zero, so start the mask on the first bit of the hi32
3968 unsigned long himask
, lomask
;
3972 himask
= 0xffff >> (32 - shift
);
3973 lomask
= (0xffff << shift
) & 0xffffffff;
3977 himask
= 0xffff << (shift
- 32);
3980 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3981 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3985 tmp
.X_op
= O_constant
;
3987 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3988 | (lo32
.X_add_number
>> shift
));
3990 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3991 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3992 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3993 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3998 while (shift
<= (64 - 16));
4000 /* Find the bit number of the lowest one bit, and store the
4001 shifted value in hi/lo. */
4002 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4003 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4007 while ((lo
& 1) == 0)
4012 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4018 while ((hi
& 1) == 0)
4027 /* Optimize if the shifted value is a (power of 2) - 1. */
4028 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4029 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4031 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4036 /* This instruction will set the register to be all
4038 tmp
.X_op
= O_constant
;
4039 tmp
.X_add_number
= (offsetT
) -1;
4040 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4044 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4045 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4047 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4048 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4053 /* Sign extend hi32 before calling load_register, because we can
4054 generally get better code when we load a sign extended value. */
4055 if ((hi32
.X_add_number
& 0x80000000) != 0)
4056 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4057 load_register (reg
, &hi32
, 0);
4060 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4064 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4072 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4074 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4075 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4081 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4085 mid16
.X_add_number
>>= 16;
4086 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4087 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4090 if ((lo32
.X_add_number
& 0xffff) != 0)
4091 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4095 load_delay_nop (void)
4097 if (!gpr_interlocks
)
4098 macro_build (NULL
, "nop", "");
4101 /* Load an address into a register. */
4104 load_address (int reg
, expressionS
*ep
, int *used_at
)
4106 if (ep
->X_op
!= O_constant
4107 && ep
->X_op
!= O_symbol
)
4109 as_bad (_("expression too complex"));
4110 ep
->X_op
= O_constant
;
4113 if (ep
->X_op
== O_constant
)
4115 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4119 if (mips_pic
== NO_PIC
)
4121 /* If this is a reference to a GP relative symbol, we want
4122 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4124 lui $reg,<sym> (BFD_RELOC_HI16_S)
4125 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4126 If we have an addend, we always use the latter form.
4128 With 64bit address space and a usable $at we want
4129 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4130 lui $at,<sym> (BFD_RELOC_HI16_S)
4131 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4132 daddiu $at,<sym> (BFD_RELOC_LO16)
4136 If $at is already in use, we use a path which is suboptimal
4137 on superscalar processors.
4138 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4139 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4141 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4143 daddiu $reg,<sym> (BFD_RELOC_LO16)
4145 For GP relative symbols in 64bit address space we can use
4146 the same sequence as in 32bit address space. */
4147 if (HAVE_64BIT_SYMBOLS
)
4149 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4150 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4152 relax_start (ep
->X_add_symbol
);
4153 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4154 mips_gp_register
, BFD_RELOC_GPREL16
);
4158 if (*used_at
== 0 && !mips_opts
.noat
)
4160 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4161 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4162 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4163 BFD_RELOC_MIPS_HIGHER
);
4164 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4165 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4166 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4171 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4172 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4173 BFD_RELOC_MIPS_HIGHER
);
4174 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4175 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4176 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4177 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4180 if (mips_relax
.sequence
)
4185 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4186 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4188 relax_start (ep
->X_add_symbol
);
4189 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4190 mips_gp_register
, BFD_RELOC_GPREL16
);
4193 macro_build_lui (ep
, reg
);
4194 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4195 reg
, reg
, BFD_RELOC_LO16
);
4196 if (mips_relax
.sequence
)
4200 else if (!mips_big_got
)
4204 /* If this is a reference to an external symbol, we want
4205 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4207 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4209 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4210 If there is a constant, it must be added in after.
4212 If we have NewABI, we want
4213 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4214 unless we're referencing a global symbol with a non-zero
4215 offset, in which case cst must be added separately. */
4218 if (ep
->X_add_number
)
4220 ex
.X_add_number
= ep
->X_add_number
;
4221 ep
->X_add_number
= 0;
4222 relax_start (ep
->X_add_symbol
);
4223 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4224 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4225 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4226 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4227 ex
.X_op
= O_constant
;
4228 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4229 reg
, reg
, BFD_RELOC_LO16
);
4230 ep
->X_add_number
= ex
.X_add_number
;
4233 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4234 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4235 if (mips_relax
.sequence
)
4240 ex
.X_add_number
= ep
->X_add_number
;
4241 ep
->X_add_number
= 0;
4242 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4243 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4245 relax_start (ep
->X_add_symbol
);
4247 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4251 if (ex
.X_add_number
!= 0)
4253 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4254 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4255 ex
.X_op
= O_constant
;
4256 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4257 reg
, reg
, BFD_RELOC_LO16
);
4261 else if (mips_big_got
)
4265 /* This is the large GOT case. If this is a reference to an
4266 external symbol, we want
4267 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4269 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4271 Otherwise, for a reference to a local symbol in old ABI, we want
4272 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4274 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4275 If there is a constant, it must be added in after.
4277 In the NewABI, for local symbols, with or without offsets, we want:
4278 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4279 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4283 ex
.X_add_number
= ep
->X_add_number
;
4284 ep
->X_add_number
= 0;
4285 relax_start (ep
->X_add_symbol
);
4286 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4287 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4288 reg
, reg
, mips_gp_register
);
4289 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4290 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4291 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4292 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4293 else if (ex
.X_add_number
)
4295 ex
.X_op
= O_constant
;
4296 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4300 ep
->X_add_number
= ex
.X_add_number
;
4302 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4303 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4304 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4305 BFD_RELOC_MIPS_GOT_OFST
);
4310 ex
.X_add_number
= ep
->X_add_number
;
4311 ep
->X_add_number
= 0;
4312 relax_start (ep
->X_add_symbol
);
4313 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4314 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4315 reg
, reg
, mips_gp_register
);
4316 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4317 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4319 if (reg_needs_delay (mips_gp_register
))
4321 /* We need a nop before loading from $gp. This special
4322 check is required because the lui which starts the main
4323 instruction stream does not refer to $gp, and so will not
4324 insert the nop which may be required. */
4325 macro_build (NULL
, "nop", "");
4327 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4328 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4330 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4334 if (ex
.X_add_number
!= 0)
4336 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4337 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4338 ex
.X_op
= O_constant
;
4339 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4347 if (mips_opts
.noat
&& *used_at
== 1)
4348 as_bad (_("Macro used $at after \".set noat\""));
4351 /* Move the contents of register SOURCE into register DEST. */
4354 move_register (int dest
, int source
)
4356 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4360 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4361 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4362 The two alternatives are:
4364 Global symbol Local sybmol
4365 ------------- ------------
4366 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4368 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4370 load_got_offset emits the first instruction and add_got_offset
4371 emits the second for a 16-bit offset or add_got_offset_hilo emits
4372 a sequence to add a 32-bit offset using a scratch register. */
4375 load_got_offset (int dest
, expressionS
*local
)
4380 global
.X_add_number
= 0;
4382 relax_start (local
->X_add_symbol
);
4383 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4384 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4386 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4387 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4392 add_got_offset (int dest
, expressionS
*local
)
4396 global
.X_op
= O_constant
;
4397 global
.X_op_symbol
= NULL
;
4398 global
.X_add_symbol
= NULL
;
4399 global
.X_add_number
= local
->X_add_number
;
4401 relax_start (local
->X_add_symbol
);
4402 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4403 dest
, dest
, BFD_RELOC_LO16
);
4405 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4410 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4413 int hold_mips_optimize
;
4415 global
.X_op
= O_constant
;
4416 global
.X_op_symbol
= NULL
;
4417 global
.X_add_symbol
= NULL
;
4418 global
.X_add_number
= local
->X_add_number
;
4420 relax_start (local
->X_add_symbol
);
4421 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4423 /* Set mips_optimize around the lui instruction to avoid
4424 inserting an unnecessary nop after the lw. */
4425 hold_mips_optimize
= mips_optimize
;
4427 macro_build_lui (&global
, tmp
);
4428 mips_optimize
= hold_mips_optimize
;
4429 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4437 * This routine implements the seemingly endless macro or synthesized
4438 * instructions and addressing modes in the mips assembly language. Many
4439 * of these macros are simple and are similar to each other. These could
4440 * probably be handled by some kind of table or grammar approach instead of
4441 * this verbose method. Others are not simple macros but are more like
4442 * optimizing code generation.
4443 * One interesting optimization is when several store macros appear
4444 * consecutively that would load AT with the upper half of the same address.
4445 * The ensuing load upper instructions are ommited. This implies some kind
4446 * of global optimization. We currently only optimize within a single macro.
4447 * For many of the load and store macros if the address is specified as a
4448 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4449 * first load register 'at' with zero and use it as the base register. The
4450 * mips assembler simply uses register $zero. Just one tiny optimization
4454 macro (struct mips_cl_insn
*ip
)
4456 register int treg
, sreg
, dreg
, breg
;
4472 bfd_reloc_code_real_type r
;
4473 int hold_mips_optimize
;
4475 assert (! mips_opts
.mips16
);
4477 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4478 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4479 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4480 mask
= ip
->insn_mo
->mask
;
4482 expr1
.X_op
= O_constant
;
4483 expr1
.X_op_symbol
= NULL
;
4484 expr1
.X_add_symbol
= NULL
;
4485 expr1
.X_add_number
= 1;
4499 expr1
.X_add_number
= 8;
4500 macro_build (&expr1
, "bgez", "s,p", sreg
);
4502 macro_build (NULL
, "nop", "", 0);
4504 move_register (dreg
, sreg
);
4505 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4528 if (imm_expr
.X_op
== O_constant
4529 && imm_expr
.X_add_number
>= -0x8000
4530 && imm_expr
.X_add_number
< 0x8000)
4532 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4536 load_register (AT
, &imm_expr
, dbl
);
4537 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4556 if (imm_expr
.X_op
== O_constant
4557 && imm_expr
.X_add_number
>= 0
4558 && imm_expr
.X_add_number
< 0x10000)
4560 if (mask
!= M_NOR_I
)
4561 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4564 macro_build (&imm_expr
, "ori", "t,r,i",
4565 treg
, sreg
, BFD_RELOC_LO16
);
4566 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4572 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4573 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4590 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4592 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4596 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4597 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4605 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4610 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4614 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4615 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4621 /* check for > max integer */
4622 maxnum
= 0x7fffffff;
4623 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4630 if (imm_expr
.X_op
== O_constant
4631 && imm_expr
.X_add_number
>= maxnum
4632 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4635 /* result is always false */
4637 macro_build (NULL
, "nop", "", 0);
4639 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4642 if (imm_expr
.X_op
!= O_constant
)
4643 as_bad (_("Unsupported large constant"));
4644 ++imm_expr
.X_add_number
;
4648 if (mask
== M_BGEL_I
)
4650 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4652 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4655 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4657 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4660 maxnum
= 0x7fffffff;
4661 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4668 maxnum
= - maxnum
- 1;
4669 if (imm_expr
.X_op
== O_constant
4670 && imm_expr
.X_add_number
<= maxnum
4671 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4674 /* result is always true */
4675 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4676 macro_build (&offset_expr
, "b", "p");
4681 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4691 macro_build (&offset_expr
, likely
? "beql" : "beq",
4696 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4697 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4705 && imm_expr
.X_op
== O_constant
4706 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4708 if (imm_expr
.X_op
!= O_constant
)
4709 as_bad (_("Unsupported large constant"));
4710 ++imm_expr
.X_add_number
;
4714 if (mask
== M_BGEUL_I
)
4716 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4718 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4720 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4726 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4734 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4739 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4743 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4744 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4752 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4759 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4760 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4768 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4773 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4777 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4778 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4784 maxnum
= 0x7fffffff;
4785 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4792 if (imm_expr
.X_op
== O_constant
4793 && imm_expr
.X_add_number
>= maxnum
4794 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4796 if (imm_expr
.X_op
!= O_constant
)
4797 as_bad (_("Unsupported large constant"));
4798 ++imm_expr
.X_add_number
;
4802 if (mask
== M_BLTL_I
)
4804 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4806 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4809 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4811 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4816 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4824 macro_build (&offset_expr
, likely
? "beql" : "beq",
4831 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4832 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4840 && imm_expr
.X_op
== O_constant
4841 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4843 if (imm_expr
.X_op
!= O_constant
)
4844 as_bad (_("Unsupported large constant"));
4845 ++imm_expr
.X_add_number
;
4849 if (mask
== M_BLTUL_I
)
4851 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4853 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4855 macro_build (&offset_expr
, likely
? "beql" : "beq",
4861 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4869 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4874 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4878 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4879 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4889 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4894 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4895 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4903 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4905 as_bad (_("Unsupported large constant"));
4910 pos
= (unsigned long) imm_expr
.X_add_number
;
4911 size
= (unsigned long) imm2_expr
.X_add_number
;
4916 as_bad (_("Improper position (%lu)"), pos
);
4919 if (size
== 0 || size
> 64
4920 || (pos
+ size
- 1) > 63)
4922 as_bad (_("Improper extract size (%lu, position %lu)"),
4927 if (size
<= 32 && pos
< 32)
4932 else if (size
<= 32)
4942 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4951 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4953 as_bad (_("Unsupported large constant"));
4958 pos
= (unsigned long) imm_expr
.X_add_number
;
4959 size
= (unsigned long) imm2_expr
.X_add_number
;
4964 as_bad (_("Improper position (%lu)"), pos
);
4967 if (size
== 0 || size
> 64
4968 || (pos
+ size
- 1) > 63)
4970 as_bad (_("Improper insert size (%lu, position %lu)"),
4975 if (pos
< 32 && (pos
+ size
- 1) < 32)
4990 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5007 as_warn (_("Divide by zero."));
5009 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5011 macro_build (NULL
, "break", "c", 7);
5018 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5019 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5023 expr1
.X_add_number
= 8;
5024 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5025 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5026 macro_build (NULL
, "break", "c", 7);
5028 expr1
.X_add_number
= -1;
5030 load_register (AT
, &expr1
, dbl
);
5031 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5032 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5035 expr1
.X_add_number
= 1;
5036 load_register (AT
, &expr1
, dbl
);
5037 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5041 expr1
.X_add_number
= 0x80000000;
5042 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5046 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5047 /* We want to close the noreorder block as soon as possible, so
5048 that later insns are available for delay slot filling. */
5053 expr1
.X_add_number
= 8;
5054 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5055 macro_build (NULL
, "nop", "", 0);
5057 /* We want to close the noreorder block as soon as possible, so
5058 that later insns are available for delay slot filling. */
5061 macro_build (NULL
, "break", "c", 6);
5063 macro_build (NULL
, s
, "d", dreg
);
5102 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5104 as_warn (_("Divide by zero."));
5106 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5108 macro_build (NULL
, "break", "c", 7);
5111 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5113 if (strcmp (s2
, "mflo") == 0)
5114 move_register (dreg
, sreg
);
5116 move_register (dreg
, 0);
5119 if (imm_expr
.X_op
== O_constant
5120 && imm_expr
.X_add_number
== -1
5121 && s
[strlen (s
) - 1] != 'u')
5123 if (strcmp (s2
, "mflo") == 0)
5125 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5128 move_register (dreg
, 0);
5133 load_register (AT
, &imm_expr
, dbl
);
5134 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5135 macro_build (NULL
, s2
, "d", dreg
);
5157 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5158 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5159 /* We want to close the noreorder block as soon as possible, so
5160 that later insns are available for delay slot filling. */
5165 expr1
.X_add_number
= 8;
5166 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5167 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5169 /* We want to close the noreorder block as soon as possible, so
5170 that later insns are available for delay slot filling. */
5172 macro_build (NULL
, "break", "c", 7);
5174 macro_build (NULL
, s2
, "d", dreg
);
5186 /* Load the address of a symbol into a register. If breg is not
5187 zero, we then add a base register to it. */
5189 if (dbl
&& HAVE_32BIT_GPRS
)
5190 as_warn (_("dla used to load 32-bit register"));
5192 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5193 as_warn (_("la used to load 64-bit address"));
5195 if (offset_expr
.X_op
== O_constant
5196 && offset_expr
.X_add_number
>= -0x8000
5197 && offset_expr
.X_add_number
< 0x8000)
5199 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5200 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5204 if (!mips_opts
.noat
&& (treg
== breg
))
5214 if (offset_expr
.X_op
!= O_symbol
5215 && offset_expr
.X_op
!= O_constant
)
5217 as_bad (_("expression too complex"));
5218 offset_expr
.X_op
= O_constant
;
5221 if (offset_expr
.X_op
== O_constant
)
5222 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5223 else if (mips_pic
== NO_PIC
)
5225 /* If this is a reference to a GP relative symbol, we want
5226 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5228 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5229 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5230 If we have a constant, we need two instructions anyhow,
5231 so we may as well always use the latter form.
5233 With 64bit address space and a usable $at we want
5234 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5235 lui $at,<sym> (BFD_RELOC_HI16_S)
5236 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5237 daddiu $at,<sym> (BFD_RELOC_LO16)
5239 daddu $tempreg,$tempreg,$at
5241 If $at is already in use, we use a path which is suboptimal
5242 on superscalar processors.
5243 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5244 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5246 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5248 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5250 For GP relative symbols in 64bit address space we can use
5251 the same sequence as in 32bit address space. */
5252 if (HAVE_64BIT_SYMBOLS
)
5254 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5255 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5257 relax_start (offset_expr
.X_add_symbol
);
5258 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5259 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5263 if (used_at
== 0 && !mips_opts
.noat
)
5265 macro_build (&offset_expr
, "lui", "t,u",
5266 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5267 macro_build (&offset_expr
, "lui", "t,u",
5268 AT
, BFD_RELOC_HI16_S
);
5269 macro_build (&offset_expr
, "daddiu", "t,r,j",
5270 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5271 macro_build (&offset_expr
, "daddiu", "t,r,j",
5272 AT
, AT
, BFD_RELOC_LO16
);
5273 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5274 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5279 macro_build (&offset_expr
, "lui", "t,u",
5280 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5281 macro_build (&offset_expr
, "daddiu", "t,r,j",
5282 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5283 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5284 macro_build (&offset_expr
, "daddiu", "t,r,j",
5285 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5286 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5287 macro_build (&offset_expr
, "daddiu", "t,r,j",
5288 tempreg
, tempreg
, BFD_RELOC_LO16
);
5291 if (mips_relax
.sequence
)
5296 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5297 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5299 relax_start (offset_expr
.X_add_symbol
);
5300 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5301 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5304 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5305 as_bad (_("offset too large"));
5306 macro_build_lui (&offset_expr
, tempreg
);
5307 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5308 tempreg
, tempreg
, BFD_RELOC_LO16
);
5309 if (mips_relax
.sequence
)
5313 else if (!mips_big_got
&& !HAVE_NEWABI
)
5315 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5317 /* If this is a reference to an external symbol, and there
5318 is no constant, we want
5319 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5320 or for lca or if tempreg is PIC_CALL_REG
5321 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5322 For a local symbol, we want
5323 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5325 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5327 If we have a small constant, and this is a reference to
5328 an external symbol, we want
5329 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5331 addiu $tempreg,$tempreg,<constant>
5332 For a local symbol, we want the same instruction
5333 sequence, but we output a BFD_RELOC_LO16 reloc on the
5336 If we have a large constant, and this is a reference to
5337 an external symbol, we want
5338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5339 lui $at,<hiconstant>
5340 addiu $at,$at,<loconstant>
5341 addu $tempreg,$tempreg,$at
5342 For a local symbol, we want the same instruction
5343 sequence, but we output a BFD_RELOC_LO16 reloc on the
5347 if (offset_expr
.X_add_number
== 0)
5349 if (mips_pic
== SVR4_PIC
5351 && (call
|| tempreg
== PIC_CALL_REG
))
5352 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5354 relax_start (offset_expr
.X_add_symbol
);
5355 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5356 lw_reloc_type
, mips_gp_register
);
5359 /* We're going to put in an addu instruction using
5360 tempreg, so we may as well insert the nop right
5365 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5366 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5368 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5369 tempreg
, tempreg
, BFD_RELOC_LO16
);
5371 /* FIXME: If breg == 0, and the next instruction uses
5372 $tempreg, then if this variant case is used an extra
5373 nop will be generated. */
5375 else if (offset_expr
.X_add_number
>= -0x8000
5376 && offset_expr
.X_add_number
< 0x8000)
5378 load_got_offset (tempreg
, &offset_expr
);
5380 add_got_offset (tempreg
, &offset_expr
);
5384 expr1
.X_add_number
= offset_expr
.X_add_number
;
5385 offset_expr
.X_add_number
=
5386 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5387 load_got_offset (tempreg
, &offset_expr
);
5388 offset_expr
.X_add_number
= expr1
.X_add_number
;
5389 /* If we are going to add in a base register, and the
5390 target register and the base register are the same,
5391 then we are using AT as a temporary register. Since
5392 we want to load the constant into AT, we add our
5393 current AT (from the global offset table) and the
5394 register into the register now, and pretend we were
5395 not using a base register. */
5399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5404 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5408 else if (!mips_big_got
&& HAVE_NEWABI
)
5410 int add_breg_early
= 0;
5412 /* If this is a reference to an external, and there is no
5413 constant, or local symbol (*), with or without a
5415 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5416 or for lca or if tempreg is PIC_CALL_REG
5417 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5419 If we have a small constant, and this is a reference to
5420 an external symbol, we want
5421 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5422 addiu $tempreg,$tempreg,<constant>
5424 If we have a large constant, and this is a reference to
5425 an external symbol, we want
5426 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5427 lui $at,<hiconstant>
5428 addiu $at,$at,<loconstant>
5429 addu $tempreg,$tempreg,$at
5431 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5432 local symbols, even though it introduces an additional
5435 if (offset_expr
.X_add_number
)
5437 expr1
.X_add_number
= offset_expr
.X_add_number
;
5438 offset_expr
.X_add_number
= 0;
5440 relax_start (offset_expr
.X_add_symbol
);
5441 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5442 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5444 if (expr1
.X_add_number
>= -0x8000
5445 && expr1
.X_add_number
< 0x8000)
5447 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5448 tempreg
, tempreg
, BFD_RELOC_LO16
);
5450 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5454 /* If we are going to add in a base register, and the
5455 target register and the base register are the same,
5456 then we are using AT as a temporary register. Since
5457 we want to load the constant into AT, we add our
5458 current AT (from the global offset table) and the
5459 register into the register now, and pretend we were
5460 not using a base register. */
5465 assert (tempreg
== AT
);
5466 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5472 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5479 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5482 offset_expr
.X_add_number
= expr1
.X_add_number
;
5484 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5485 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5488 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5489 treg
, tempreg
, breg
);
5495 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5497 relax_start (offset_expr
.X_add_symbol
);
5498 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5499 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5501 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5502 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5507 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5508 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5511 else if (mips_big_got
&& !HAVE_NEWABI
)
5514 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5515 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5516 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5518 /* This is the large GOT case. If this is a reference to an
5519 external symbol, and there is no constant, we want
5520 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5521 addu $tempreg,$tempreg,$gp
5522 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5523 or for lca or if tempreg is PIC_CALL_REG
5524 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5525 addu $tempreg,$tempreg,$gp
5526 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5527 For a local symbol, we want
5528 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5530 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5532 If we have a small constant, and this is a reference to
5533 an external symbol, we want
5534 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5535 addu $tempreg,$tempreg,$gp
5536 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5538 addiu $tempreg,$tempreg,<constant>
5539 For a local symbol, we want
5540 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5542 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5544 If we have a large constant, and this is a reference to
5545 an external symbol, we want
5546 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5547 addu $tempreg,$tempreg,$gp
5548 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5549 lui $at,<hiconstant>
5550 addiu $at,$at,<loconstant>
5551 addu $tempreg,$tempreg,$at
5552 For a local symbol, we want
5553 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5554 lui $at,<hiconstant>
5555 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5556 addu $tempreg,$tempreg,$at
5559 expr1
.X_add_number
= offset_expr
.X_add_number
;
5560 offset_expr
.X_add_number
= 0;
5561 relax_start (offset_expr
.X_add_symbol
);
5562 gpdelay
= reg_needs_delay (mips_gp_register
);
5563 if (expr1
.X_add_number
== 0 && breg
== 0
5564 && (call
|| tempreg
== PIC_CALL_REG
))
5566 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5567 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5569 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5570 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5571 tempreg
, tempreg
, mips_gp_register
);
5572 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5573 tempreg
, lw_reloc_type
, tempreg
);
5574 if (expr1
.X_add_number
== 0)
5578 /* We're going to put in an addu instruction using
5579 tempreg, so we may as well insert the nop right
5584 else if (expr1
.X_add_number
>= -0x8000
5585 && expr1
.X_add_number
< 0x8000)
5588 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5589 tempreg
, tempreg
, BFD_RELOC_LO16
);
5595 /* If we are going to add in a base register, and the
5596 target register and the base register are the same,
5597 then we are using AT as a temporary register. Since
5598 we want to load the constant into AT, we add our
5599 current AT (from the global offset table) and the
5600 register into the register now, and pretend we were
5601 not using a base register. */
5606 assert (tempreg
== AT
);
5608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5613 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5614 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5618 offset_expr
.X_add_number
=
5619 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5624 /* This is needed because this instruction uses $gp, but
5625 the first instruction on the main stream does not. */
5626 macro_build (NULL
, "nop", "");
5629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5630 local_reloc_type
, mips_gp_register
);
5631 if (expr1
.X_add_number
>= -0x8000
5632 && expr1
.X_add_number
< 0x8000)
5635 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5636 tempreg
, tempreg
, BFD_RELOC_LO16
);
5637 /* FIXME: If add_number is 0, and there was no base
5638 register, the external symbol case ended with a load,
5639 so if the symbol turns out to not be external, and
5640 the next instruction uses tempreg, an unnecessary nop
5641 will be inserted. */
5647 /* We must add in the base register now, as in the
5648 external symbol case. */
5649 assert (tempreg
== AT
);
5651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5654 /* We set breg to 0 because we have arranged to add
5655 it in in both cases. */
5659 macro_build_lui (&expr1
, AT
);
5660 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5661 AT
, AT
, BFD_RELOC_LO16
);
5662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5663 tempreg
, tempreg
, AT
);
5668 else if (mips_big_got
&& HAVE_NEWABI
)
5670 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5671 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5672 int add_breg_early
= 0;
5674 /* This is the large GOT case. If this is a reference to an
5675 external symbol, and there is no constant, we want
5676 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5677 add $tempreg,$tempreg,$gp
5678 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5679 or for lca or if tempreg is PIC_CALL_REG
5680 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5681 add $tempreg,$tempreg,$gp
5682 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5684 If we have a small constant, and this is a reference to
5685 an external symbol, we want
5686 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5687 add $tempreg,$tempreg,$gp
5688 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5689 addi $tempreg,$tempreg,<constant>
5691 If we have a large constant, and this is a reference to
5692 an external symbol, we want
5693 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5694 addu $tempreg,$tempreg,$gp
5695 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5696 lui $at,<hiconstant>
5697 addi $at,$at,<loconstant>
5698 add $tempreg,$tempreg,$at
5700 If we have NewABI, and we know it's a local symbol, we want
5701 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5702 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5703 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5705 relax_start (offset_expr
.X_add_symbol
);
5707 expr1
.X_add_number
= offset_expr
.X_add_number
;
5708 offset_expr
.X_add_number
= 0;
5710 if (expr1
.X_add_number
== 0 && breg
== 0
5711 && (call
|| tempreg
== PIC_CALL_REG
))
5713 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5714 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5716 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5717 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5718 tempreg
, tempreg
, mips_gp_register
);
5719 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5720 tempreg
, lw_reloc_type
, tempreg
);
5722 if (expr1
.X_add_number
== 0)
5724 else if (expr1
.X_add_number
>= -0x8000
5725 && expr1
.X_add_number
< 0x8000)
5727 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5728 tempreg
, tempreg
, BFD_RELOC_LO16
);
5730 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5734 /* If we are going to add in a base register, and the
5735 target register and the base register are the same,
5736 then we are using AT as a temporary register. Since
5737 we want to load the constant into AT, we add our
5738 current AT (from the global offset table) and the
5739 register into the register now, and pretend we were
5740 not using a base register. */
5745 assert (tempreg
== AT
);
5746 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5752 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5753 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5758 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5761 offset_expr
.X_add_number
= expr1
.X_add_number
;
5762 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5763 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5764 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5765 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5768 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5769 treg
, tempreg
, breg
);
5779 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5783 /* The j instruction may not be used in PIC code, since it
5784 requires an absolute address. We convert it to a b
5786 if (mips_pic
== NO_PIC
)
5787 macro_build (&offset_expr
, "j", "a");
5789 macro_build (&offset_expr
, "b", "p");
5792 /* The jal instructions must be handled as macros because when
5793 generating PIC code they expand to multi-instruction
5794 sequences. Normally they are simple instructions. */
5799 if (mips_pic
== NO_PIC
)
5800 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5803 if (sreg
!= PIC_CALL_REG
)
5804 as_warn (_("MIPS PIC call to register other than $25"));
5806 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5807 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5809 if (mips_cprestore_offset
< 0)
5810 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5813 if (! mips_frame_reg_valid
)
5815 as_warn (_("No .frame pseudo-op used in PIC code"));
5816 /* Quiet this warning. */
5817 mips_frame_reg_valid
= 1;
5819 if (! mips_cprestore_valid
)
5821 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5822 /* Quiet this warning. */
5823 mips_cprestore_valid
= 1;
5825 expr1
.X_add_number
= mips_cprestore_offset
;
5826 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5829 HAVE_64BIT_ADDRESSES
);
5837 if (mips_pic
== NO_PIC
)
5838 macro_build (&offset_expr
, "jal", "a");
5839 else if (mips_pic
== SVR4_PIC
)
5841 /* If this is a reference to an external symbol, and we are
5842 using a small GOT, we want
5843 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5847 lw $gp,cprestore($sp)
5848 The cprestore value is set using the .cprestore
5849 pseudo-op. If we are using a big GOT, we want
5850 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5852 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5856 lw $gp,cprestore($sp)
5857 If the symbol is not external, we want
5858 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5860 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5863 lw $gp,cprestore($sp)
5865 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5866 sequences above, minus nops, unless the symbol is local,
5867 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5873 relax_start (offset_expr
.X_add_symbol
);
5874 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5875 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5878 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5879 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5885 relax_start (offset_expr
.X_add_symbol
);
5886 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5887 BFD_RELOC_MIPS_CALL_HI16
);
5888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5889 PIC_CALL_REG
, mips_gp_register
);
5890 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5891 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5894 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5895 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5897 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5898 PIC_CALL_REG
, PIC_CALL_REG
,
5899 BFD_RELOC_MIPS_GOT_OFST
);
5903 macro_build_jalr (&offset_expr
);
5907 relax_start (offset_expr
.X_add_symbol
);
5910 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5911 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5920 gpdelay
= reg_needs_delay (mips_gp_register
);
5921 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5922 BFD_RELOC_MIPS_CALL_HI16
);
5923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5924 PIC_CALL_REG
, mips_gp_register
);
5925 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5926 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5931 macro_build (NULL
, "nop", "");
5933 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5934 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5937 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5938 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5940 macro_build_jalr (&offset_expr
);
5942 if (mips_cprestore_offset
< 0)
5943 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5946 if (! mips_frame_reg_valid
)
5948 as_warn (_("No .frame pseudo-op used in PIC code"));
5949 /* Quiet this warning. */
5950 mips_frame_reg_valid
= 1;
5952 if (! mips_cprestore_valid
)
5954 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5955 /* Quiet this warning. */
5956 mips_cprestore_valid
= 1;
5958 if (mips_opts
.noreorder
)
5959 macro_build (NULL
, "nop", "");
5960 expr1
.X_add_number
= mips_cprestore_offset
;
5961 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5964 HAVE_64BIT_ADDRESSES
);
5968 else if (mips_pic
== VXWORKS_PIC
)
5969 as_bad (_("Non-PIC jump used in PIC library"));
5992 /* Itbl support may require additional care here. */
5997 /* Itbl support may require additional care here. */
6002 /* Itbl support may require additional care here. */
6007 /* Itbl support may require additional care here. */
6019 if (mips_opts
.arch
== CPU_R4650
)
6021 as_bad (_("opcode not supported on this processor"));
6025 /* Itbl support may require additional care here. */
6030 /* Itbl support may require additional care here. */
6035 /* Itbl support may require additional care here. */
6055 if (breg
== treg
|| coproc
|| lr
)
6076 /* Itbl support may require additional care here. */
6081 /* Itbl support may require additional care here. */
6086 /* Itbl support may require additional care here. */
6091 /* Itbl support may require additional care here. */
6110 if (mips_opts
.arch
== CPU_R4650
)
6112 as_bad (_("opcode not supported on this processor"));
6117 /* Itbl support may require additional care here. */
6121 /* Itbl support may require additional care here. */
6126 /* Itbl support may require additional care here. */
6138 /* Itbl support may require additional care here. */
6139 if (mask
== M_LWC1_AB
6140 || mask
== M_SWC1_AB
6141 || mask
== M_LDC1_AB
6142 || mask
== M_SDC1_AB
6146 else if (mask
== M_CACHE_AB
)
6153 if (offset_expr
.X_op
!= O_constant
6154 && offset_expr
.X_op
!= O_symbol
)
6156 as_bad (_("expression too complex"));
6157 offset_expr
.X_op
= O_constant
;
6160 if (HAVE_32BIT_ADDRESSES
6161 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6165 sprintf_vma (value
, offset_expr
.X_add_number
);
6166 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6169 /* A constant expression in PIC code can be handled just as it
6170 is in non PIC code. */
6171 if (offset_expr
.X_op
== O_constant
)
6173 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6174 & ~(bfd_vma
) 0xffff);
6175 normalize_address_expr (&expr1
);
6176 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6178 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6179 tempreg
, tempreg
, breg
);
6180 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6182 else if (mips_pic
== NO_PIC
)
6184 /* If this is a reference to a GP relative symbol, and there
6185 is no base register, we want
6186 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6187 Otherwise, if there is no base register, we want
6188 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6189 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6190 If we have a constant, we need two instructions anyhow,
6191 so we always use the latter form.
6193 If we have a base register, and this is a reference to a
6194 GP relative symbol, we want
6195 addu $tempreg,$breg,$gp
6196 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6198 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6199 addu $tempreg,$tempreg,$breg
6200 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6201 With a constant we always use the latter case.
6203 With 64bit address space and no base register and $at usable,
6205 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6206 lui $at,<sym> (BFD_RELOC_HI16_S)
6207 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6210 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6211 If we have a base register, we want
6212 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6213 lui $at,<sym> (BFD_RELOC_HI16_S)
6214 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6218 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6220 Without $at we can't generate the optimal path for superscalar
6221 processors here since this would require two temporary registers.
6222 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6223 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6225 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6227 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6228 If we have a base register, we want
6229 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6230 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6232 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6234 daddu $tempreg,$tempreg,$breg
6235 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6237 For GP relative symbols in 64bit address space we can use
6238 the same sequence as in 32bit address space. */
6239 if (HAVE_64BIT_SYMBOLS
)
6241 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6242 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6244 relax_start (offset_expr
.X_add_symbol
);
6247 macro_build (&offset_expr
, s
, fmt
, treg
,
6248 BFD_RELOC_GPREL16
, mips_gp_register
);
6252 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6253 tempreg
, breg
, mips_gp_register
);
6254 macro_build (&offset_expr
, s
, fmt
, treg
,
6255 BFD_RELOC_GPREL16
, tempreg
);
6260 if (used_at
== 0 && !mips_opts
.noat
)
6262 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6263 BFD_RELOC_MIPS_HIGHEST
);
6264 macro_build (&offset_expr
, "lui", "t,u", AT
,
6266 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6267 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6269 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6270 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6271 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6272 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6278 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6279 BFD_RELOC_MIPS_HIGHEST
);
6280 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6281 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6282 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6283 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6284 tempreg
, BFD_RELOC_HI16_S
);
6285 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6287 macro_build (NULL
, "daddu", "d,v,t",
6288 tempreg
, tempreg
, breg
);
6289 macro_build (&offset_expr
, s
, fmt
, treg
,
6290 BFD_RELOC_LO16
, tempreg
);
6293 if (mips_relax
.sequence
)
6300 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6301 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6303 relax_start (offset_expr
.X_add_symbol
);
6304 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6308 macro_build_lui (&offset_expr
, tempreg
);
6309 macro_build (&offset_expr
, s
, fmt
, treg
,
6310 BFD_RELOC_LO16
, tempreg
);
6311 if (mips_relax
.sequence
)
6316 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6317 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6319 relax_start (offset_expr
.X_add_symbol
);
6320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6321 tempreg
, breg
, mips_gp_register
);
6322 macro_build (&offset_expr
, s
, fmt
, treg
,
6323 BFD_RELOC_GPREL16
, tempreg
);
6326 macro_build_lui (&offset_expr
, tempreg
);
6327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6328 tempreg
, tempreg
, breg
);
6329 macro_build (&offset_expr
, s
, fmt
, treg
,
6330 BFD_RELOC_LO16
, tempreg
);
6331 if (mips_relax
.sequence
)
6335 else if (!mips_big_got
)
6337 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6339 /* If this is a reference to an external symbol, we want
6340 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6342 <op> $treg,0($tempreg)
6344 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6346 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6347 <op> $treg,0($tempreg)
6350 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6351 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6353 If there is a base register, we add it to $tempreg before
6354 the <op>. If there is a constant, we stick it in the
6355 <op> instruction. We don't handle constants larger than
6356 16 bits, because we have no way to load the upper 16 bits
6357 (actually, we could handle them for the subset of cases
6358 in which we are not using $at). */
6359 assert (offset_expr
.X_op
== O_symbol
);
6362 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6363 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6366 tempreg
, tempreg
, breg
);
6367 macro_build (&offset_expr
, s
, fmt
, treg
,
6368 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6371 expr1
.X_add_number
= offset_expr
.X_add_number
;
6372 offset_expr
.X_add_number
= 0;
6373 if (expr1
.X_add_number
< -0x8000
6374 || expr1
.X_add_number
>= 0x8000)
6375 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6376 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6377 lw_reloc_type
, mips_gp_register
);
6379 relax_start (offset_expr
.X_add_symbol
);
6381 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6382 tempreg
, BFD_RELOC_LO16
);
6385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6386 tempreg
, tempreg
, breg
);
6387 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6389 else if (mips_big_got
&& !HAVE_NEWABI
)
6393 /* If this is a reference to an external symbol, we want
6394 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6395 addu $tempreg,$tempreg,$gp
6396 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6397 <op> $treg,0($tempreg)
6399 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6401 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6402 <op> $treg,0($tempreg)
6403 If there is a base register, we add it to $tempreg before
6404 the <op>. If there is a constant, we stick it in the
6405 <op> instruction. We don't handle constants larger than
6406 16 bits, because we have no way to load the upper 16 bits
6407 (actually, we could handle them for the subset of cases
6408 in which we are not using $at). */
6409 assert (offset_expr
.X_op
== O_symbol
);
6410 expr1
.X_add_number
= offset_expr
.X_add_number
;
6411 offset_expr
.X_add_number
= 0;
6412 if (expr1
.X_add_number
< -0x8000
6413 || expr1
.X_add_number
>= 0x8000)
6414 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6415 gpdelay
= reg_needs_delay (mips_gp_register
);
6416 relax_start (offset_expr
.X_add_symbol
);
6417 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6418 BFD_RELOC_MIPS_GOT_HI16
);
6419 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6421 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6422 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6425 macro_build (NULL
, "nop", "");
6426 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6427 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6429 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6430 tempreg
, BFD_RELOC_LO16
);
6434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6435 tempreg
, tempreg
, breg
);
6436 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6438 else if (mips_big_got
&& HAVE_NEWABI
)
6440 /* If this is a reference to an external symbol, we want
6441 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6442 add $tempreg,$tempreg,$gp
6443 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6444 <op> $treg,<ofst>($tempreg)
6445 Otherwise, for local symbols, we want:
6446 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6447 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6448 assert (offset_expr
.X_op
== O_symbol
);
6449 expr1
.X_add_number
= offset_expr
.X_add_number
;
6450 offset_expr
.X_add_number
= 0;
6451 if (expr1
.X_add_number
< -0x8000
6452 || expr1
.X_add_number
>= 0x8000)
6453 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6454 relax_start (offset_expr
.X_add_symbol
);
6455 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6456 BFD_RELOC_MIPS_GOT_HI16
);
6457 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6460 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6463 tempreg
, tempreg
, breg
);
6464 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6467 offset_expr
.X_add_number
= expr1
.X_add_number
;
6468 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6469 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6472 tempreg
, tempreg
, breg
);
6473 macro_build (&offset_expr
, s
, fmt
, treg
,
6474 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6484 load_register (treg
, &imm_expr
, 0);
6488 load_register (treg
, &imm_expr
, 1);
6492 if (imm_expr
.X_op
== O_constant
)
6495 load_register (AT
, &imm_expr
, 0);
6496 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6501 assert (offset_expr
.X_op
== O_symbol
6502 && strcmp (segment_name (S_GET_SEGMENT
6503 (offset_expr
.X_add_symbol
)),
6505 && offset_expr
.X_add_number
== 0);
6506 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6507 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6512 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6513 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6514 order 32 bits of the value and the low order 32 bits are either
6515 zero or in OFFSET_EXPR. */
6516 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6518 if (HAVE_64BIT_GPRS
)
6519 load_register (treg
, &imm_expr
, 1);
6524 if (target_big_endian
)
6536 load_register (hreg
, &imm_expr
, 0);
6539 if (offset_expr
.X_op
== O_absent
)
6540 move_register (lreg
, 0);
6543 assert (offset_expr
.X_op
== O_constant
);
6544 load_register (lreg
, &offset_expr
, 0);
6551 /* We know that sym is in the .rdata section. First we get the
6552 upper 16 bits of the address. */
6553 if (mips_pic
== NO_PIC
)
6555 macro_build_lui (&offset_expr
, AT
);
6560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6561 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6565 /* Now we load the register(s). */
6566 if (HAVE_64BIT_GPRS
)
6569 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6574 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6577 /* FIXME: How in the world do we deal with the possible
6579 offset_expr
.X_add_number
+= 4;
6580 macro_build (&offset_expr
, "lw", "t,o(b)",
6581 treg
+ 1, BFD_RELOC_LO16
, AT
);
6587 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6588 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6589 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6590 the value and the low order 32 bits are either zero or in
6592 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6595 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6596 if (HAVE_64BIT_FPRS
)
6598 assert (HAVE_64BIT_GPRS
);
6599 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6603 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6604 if (offset_expr
.X_op
== O_absent
)
6605 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6608 assert (offset_expr
.X_op
== O_constant
);
6609 load_register (AT
, &offset_expr
, 0);
6610 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6616 assert (offset_expr
.X_op
== O_symbol
6617 && offset_expr
.X_add_number
== 0);
6618 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6619 if (strcmp (s
, ".lit8") == 0)
6621 if (mips_opts
.isa
!= ISA_MIPS1
)
6623 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6624 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6627 breg
= mips_gp_register
;
6628 r
= BFD_RELOC_MIPS_LITERAL
;
6633 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6635 if (mips_pic
!= NO_PIC
)
6636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6637 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6640 /* FIXME: This won't work for a 64 bit address. */
6641 macro_build_lui (&offset_expr
, AT
);
6644 if (mips_opts
.isa
!= ISA_MIPS1
)
6646 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6647 treg
, BFD_RELOC_LO16
, AT
);
6656 if (mips_opts
.arch
== CPU_R4650
)
6658 as_bad (_("opcode not supported on this processor"));
6661 /* Even on a big endian machine $fn comes before $fn+1. We have
6662 to adjust when loading from memory. */
6665 assert (mips_opts
.isa
== ISA_MIPS1
);
6666 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6667 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6668 /* FIXME: A possible overflow which I don't know how to deal
6670 offset_expr
.X_add_number
+= 4;
6671 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6672 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6677 * The MIPS assembler seems to check for X_add_number not
6678 * being double aligned and generating:
6681 * addiu at,at,%lo(foo+1)
6684 * But, the resulting address is the same after relocation so why
6685 * generate the extra instruction?
6687 if (mips_opts
.arch
== CPU_R4650
)
6689 as_bad (_("opcode not supported on this processor"));
6692 /* Itbl support may require additional care here. */
6694 if (mips_opts
.isa
!= ISA_MIPS1
)
6705 if (mips_opts
.arch
== CPU_R4650
)
6707 as_bad (_("opcode not supported on this processor"));
6711 if (mips_opts
.isa
!= ISA_MIPS1
)
6719 /* Itbl support may require additional care here. */
6724 if (HAVE_64BIT_GPRS
)
6735 if (HAVE_64BIT_GPRS
)
6745 if (offset_expr
.X_op
!= O_symbol
6746 && offset_expr
.X_op
!= O_constant
)
6748 as_bad (_("expression too complex"));
6749 offset_expr
.X_op
= O_constant
;
6752 if (HAVE_32BIT_ADDRESSES
6753 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6757 sprintf_vma (value
, offset_expr
.X_add_number
);
6758 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6761 /* Even on a big endian machine $fn comes before $fn+1. We have
6762 to adjust when loading from memory. We set coproc if we must
6763 load $fn+1 first. */
6764 /* Itbl support may require additional care here. */
6765 if (! target_big_endian
)
6768 if (mips_pic
== NO_PIC
6769 || offset_expr
.X_op
== O_constant
)
6771 /* If this is a reference to a GP relative symbol, we want
6772 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6773 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6774 If we have a base register, we use this
6776 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6777 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6778 If this is not a GP relative symbol, we want
6779 lui $at,<sym> (BFD_RELOC_HI16_S)
6780 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6781 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6782 If there is a base register, we add it to $at after the
6783 lui instruction. If there is a constant, we always use
6785 if (offset_expr
.X_op
== O_symbol
6786 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6787 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6789 relax_start (offset_expr
.X_add_symbol
);
6792 tempreg
= mips_gp_register
;
6796 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6797 AT
, breg
, mips_gp_register
);
6802 /* Itbl support may require additional care here. */
6803 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6804 BFD_RELOC_GPREL16
, tempreg
);
6805 offset_expr
.X_add_number
+= 4;
6807 /* Set mips_optimize to 2 to avoid inserting an
6809 hold_mips_optimize
= mips_optimize
;
6811 /* Itbl support may require additional care here. */
6812 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6813 BFD_RELOC_GPREL16
, tempreg
);
6814 mips_optimize
= hold_mips_optimize
;
6818 /* We just generated two relocs. When tc_gen_reloc
6819 handles this case, it will skip the first reloc and
6820 handle the second. The second reloc already has an
6821 extra addend of 4, which we added above. We must
6822 subtract it out, and then subtract another 4 to make
6823 the first reloc come out right. The second reloc
6824 will come out right because we are going to add 4 to
6825 offset_expr when we build its instruction below.
6827 If we have a symbol, then we don't want to include
6828 the offset, because it will wind up being included
6829 when we generate the reloc. */
6831 if (offset_expr
.X_op
== O_constant
)
6832 offset_expr
.X_add_number
-= 8;
6835 offset_expr
.X_add_number
= -4;
6836 offset_expr
.X_op
= O_constant
;
6840 macro_build_lui (&offset_expr
, AT
);
6842 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6843 /* Itbl support may require additional care here. */
6844 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6845 BFD_RELOC_LO16
, AT
);
6846 /* FIXME: How do we handle overflow here? */
6847 offset_expr
.X_add_number
+= 4;
6848 /* Itbl support may require additional care here. */
6849 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6850 BFD_RELOC_LO16
, AT
);
6851 if (mips_relax
.sequence
)
6854 else if (!mips_big_got
)
6856 /* If this is a reference to an external symbol, we want
6857 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6862 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6864 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6865 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6866 If there is a base register we add it to $at before the
6867 lwc1 instructions. If there is a constant we include it
6868 in the lwc1 instructions. */
6870 expr1
.X_add_number
= offset_expr
.X_add_number
;
6871 if (expr1
.X_add_number
< -0x8000
6872 || expr1
.X_add_number
>= 0x8000 - 4)
6873 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6874 load_got_offset (AT
, &offset_expr
);
6877 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6879 /* Set mips_optimize to 2 to avoid inserting an undesired
6881 hold_mips_optimize
= mips_optimize
;
6884 /* Itbl support may require additional care here. */
6885 relax_start (offset_expr
.X_add_symbol
);
6886 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6887 BFD_RELOC_LO16
, AT
);
6888 expr1
.X_add_number
+= 4;
6889 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6890 BFD_RELOC_LO16
, AT
);
6892 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6893 BFD_RELOC_LO16
, AT
);
6894 offset_expr
.X_add_number
+= 4;
6895 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6896 BFD_RELOC_LO16
, AT
);
6899 mips_optimize
= hold_mips_optimize
;
6901 else if (mips_big_got
)
6905 /* If this is a reference to an external symbol, we want
6906 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6908 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6913 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6915 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6916 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6917 If there is a base register we add it to $at before the
6918 lwc1 instructions. If there is a constant we include it
6919 in the lwc1 instructions. */
6921 expr1
.X_add_number
= offset_expr
.X_add_number
;
6922 offset_expr
.X_add_number
= 0;
6923 if (expr1
.X_add_number
< -0x8000
6924 || expr1
.X_add_number
>= 0x8000 - 4)
6925 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6926 gpdelay
= reg_needs_delay (mips_gp_register
);
6927 relax_start (offset_expr
.X_add_symbol
);
6928 macro_build (&offset_expr
, "lui", "t,u",
6929 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6930 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6931 AT
, AT
, mips_gp_register
);
6932 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6933 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6936 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6937 /* Itbl support may require additional care here. */
6938 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6939 BFD_RELOC_LO16
, AT
);
6940 expr1
.X_add_number
+= 4;
6942 /* Set mips_optimize to 2 to avoid inserting an undesired
6944 hold_mips_optimize
= mips_optimize
;
6946 /* Itbl support may require additional care here. */
6947 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6948 BFD_RELOC_LO16
, AT
);
6949 mips_optimize
= hold_mips_optimize
;
6950 expr1
.X_add_number
-= 4;
6953 offset_expr
.X_add_number
= expr1
.X_add_number
;
6955 macro_build (NULL
, "nop", "");
6956 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6957 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6960 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6961 /* Itbl support may require additional care here. */
6962 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6963 BFD_RELOC_LO16
, AT
);
6964 offset_expr
.X_add_number
+= 4;
6966 /* Set mips_optimize to 2 to avoid inserting an undesired
6968 hold_mips_optimize
= mips_optimize
;
6970 /* Itbl support may require additional care here. */
6971 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6972 BFD_RELOC_LO16
, AT
);
6973 mips_optimize
= hold_mips_optimize
;
6987 assert (HAVE_32BIT_ADDRESSES
);
6988 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6989 offset_expr
.X_add_number
+= 4;
6990 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6993 /* New code added to support COPZ instructions.
6994 This code builds table entries out of the macros in mip_opcodes.
6995 R4000 uses interlocks to handle coproc delays.
6996 Other chips (like the R3000) require nops to be inserted for delays.
6998 FIXME: Currently, we require that the user handle delays.
6999 In order to fill delay slots for non-interlocked chips,
7000 we must have a way to specify delays based on the coprocessor.
7001 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7002 What are the side-effects of the cop instruction?
7003 What cache support might we have and what are its effects?
7004 Both coprocessor & memory require delays. how long???
7005 What registers are read/set/modified?
7007 If an itbl is provided to interpret cop instructions,
7008 this knowledge can be encoded in the itbl spec. */
7022 /* For now we just do C (same as Cz). The parameter will be
7023 stored in insn_opcode by mips_ip. */
7024 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7028 move_register (dreg
, sreg
);
7031 #ifdef LOSING_COMPILER
7033 /* Try and see if this is a new itbl instruction.
7034 This code builds table entries out of the macros in mip_opcodes.
7035 FIXME: For now we just assemble the expression and pass it's
7036 value along as a 32-bit immediate.
7037 We may want to have the assembler assemble this value,
7038 so that we gain the assembler's knowledge of delay slots,
7040 Would it be more efficient to use mask (id) here? */
7041 if (itbl_have_entries
7042 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7044 s
= ip
->insn_mo
->name
;
7046 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7047 macro_build (&immed_expr
, s
, "C");
7053 if (mips_opts
.noat
&& used_at
)
7054 as_bad (_("Macro used $at after \".set noat\""));
7058 macro2 (struct mips_cl_insn
*ip
)
7060 register int treg
, sreg
, dreg
, breg
;
7075 bfd_reloc_code_real_type r
;
7077 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7078 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7079 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7080 mask
= ip
->insn_mo
->mask
;
7082 expr1
.X_op
= O_constant
;
7083 expr1
.X_op_symbol
= NULL
;
7084 expr1
.X_add_symbol
= NULL
;
7085 expr1
.X_add_number
= 1;
7089 #endif /* LOSING_COMPILER */
7094 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7095 macro_build (NULL
, "mflo", "d", dreg
);
7101 /* The MIPS assembler some times generates shifts and adds. I'm
7102 not trying to be that fancy. GCC should do this for us
7105 load_register (AT
, &imm_expr
, dbl
);
7106 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7107 macro_build (NULL
, "mflo", "d", dreg
);
7123 load_register (AT
, &imm_expr
, dbl
);
7124 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7125 macro_build (NULL
, "mflo", "d", dreg
);
7126 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7127 macro_build (NULL
, "mfhi", "d", AT
);
7129 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7132 expr1
.X_add_number
= 8;
7133 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7134 macro_build (NULL
, "nop", "", 0);
7135 macro_build (NULL
, "break", "c", 6);
7138 macro_build (NULL
, "mflo", "d", dreg
);
7154 load_register (AT
, &imm_expr
, dbl
);
7155 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7156 sreg
, imm
? AT
: treg
);
7157 macro_build (NULL
, "mfhi", "d", AT
);
7158 macro_build (NULL
, "mflo", "d", dreg
);
7160 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7163 expr1
.X_add_number
= 8;
7164 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7165 macro_build (NULL
, "nop", "", 0);
7166 macro_build (NULL
, "break", "c", 6);
7172 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7183 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7184 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7188 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7189 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7190 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7191 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7195 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7206 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7207 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7211 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7212 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7213 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7214 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7222 if (imm_expr
.X_op
!= O_constant
)
7223 as_bad (_("Improper rotate count"));
7224 rot
= imm_expr
.X_add_number
& 0x3f;
7225 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7227 rot
= (64 - rot
) & 0x3f;
7229 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7231 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7236 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7239 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7240 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7243 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7244 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7245 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7253 if (imm_expr
.X_op
!= O_constant
)
7254 as_bad (_("Improper rotate count"));
7255 rot
= imm_expr
.X_add_number
& 0x1f;
7256 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7258 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7263 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7267 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7268 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7269 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7274 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7276 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7280 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7281 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7282 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7283 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7287 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7289 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7293 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7294 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7295 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7296 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7304 if (imm_expr
.X_op
!= O_constant
)
7305 as_bad (_("Improper rotate count"));
7306 rot
= imm_expr
.X_add_number
& 0x3f;
7307 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7310 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7312 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7317 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7320 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7321 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7324 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7325 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7326 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7334 if (imm_expr
.X_op
!= O_constant
)
7335 as_bad (_("Improper rotate count"));
7336 rot
= imm_expr
.X_add_number
& 0x1f;
7337 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7339 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7344 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7348 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7349 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7350 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7355 if (mips_opts
.arch
== CPU_R4650
)
7357 as_bad (_("opcode not supported on this processor"));
7360 assert (mips_opts
.isa
== ISA_MIPS1
);
7361 /* Even on a big endian machine $fn comes before $fn+1. We have
7362 to adjust when storing to memory. */
7363 macro_build (&offset_expr
, "swc1", "T,o(b)",
7364 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7365 offset_expr
.X_add_number
+= 4;
7366 macro_build (&offset_expr
, "swc1", "T,o(b)",
7367 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7372 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7374 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7377 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7378 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7383 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7385 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7390 as_warn (_("Instruction %s: result is always false"),
7392 move_register (dreg
, 0);
7395 if (imm_expr
.X_op
== O_constant
7396 && imm_expr
.X_add_number
>= 0
7397 && imm_expr
.X_add_number
< 0x10000)
7399 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7401 else if (imm_expr
.X_op
== O_constant
7402 && imm_expr
.X_add_number
> -0x8000
7403 && imm_expr
.X_add_number
< 0)
7405 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7406 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7407 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7411 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7412 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7415 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7418 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7424 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7425 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7428 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7430 if (imm_expr
.X_op
== O_constant
7431 && imm_expr
.X_add_number
>= -0x8000
7432 && imm_expr
.X_add_number
< 0x8000)
7434 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7435 dreg
, sreg
, BFD_RELOC_LO16
);
7439 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7440 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7444 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7447 case M_SGT
: /* sreg > treg <==> treg < sreg */
7453 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7456 case M_SGT_I
: /* sreg > I <==> I < sreg */
7463 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7464 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7467 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7473 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7474 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7477 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7484 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7485 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7486 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7490 if (imm_expr
.X_op
== O_constant
7491 && imm_expr
.X_add_number
>= -0x8000
7492 && imm_expr
.X_add_number
< 0x8000)
7494 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7498 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7499 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7503 if (imm_expr
.X_op
== O_constant
7504 && imm_expr
.X_add_number
>= -0x8000
7505 && imm_expr
.X_add_number
< 0x8000)
7507 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7512 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7513 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7518 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7520 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7523 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7524 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7529 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7531 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7536 as_warn (_("Instruction %s: result is always true"),
7538 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7539 dreg
, 0, BFD_RELOC_LO16
);
7542 if (imm_expr
.X_op
== O_constant
7543 && imm_expr
.X_add_number
>= 0
7544 && imm_expr
.X_add_number
< 0x10000)
7546 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7548 else if (imm_expr
.X_op
== O_constant
7549 && imm_expr
.X_add_number
> -0x8000
7550 && imm_expr
.X_add_number
< 0)
7552 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7553 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7554 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7558 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7559 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7562 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7568 if (imm_expr
.X_op
== O_constant
7569 && imm_expr
.X_add_number
> -0x8000
7570 && imm_expr
.X_add_number
<= 0x8000)
7572 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7573 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7574 dreg
, sreg
, BFD_RELOC_LO16
);
7578 load_register (AT
, &imm_expr
, dbl
);
7579 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7585 if (imm_expr
.X_op
== O_constant
7586 && imm_expr
.X_add_number
> -0x8000
7587 && imm_expr
.X_add_number
<= 0x8000)
7589 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7590 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7591 dreg
, sreg
, BFD_RELOC_LO16
);
7595 load_register (AT
, &imm_expr
, dbl
);
7596 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7618 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7619 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7624 assert (mips_opts
.isa
== ISA_MIPS1
);
7626 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7627 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7630 * Is the double cfc1 instruction a bug in the mips assembler;
7631 * or is there a reason for it?
7634 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7635 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7636 macro_build (NULL
, "nop", "");
7637 expr1
.X_add_number
= 3;
7638 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7639 expr1
.X_add_number
= 2;
7640 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7641 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7642 macro_build (NULL
, "nop", "");
7643 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7645 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7646 macro_build (NULL
, "nop", "");
7657 if (offset_expr
.X_add_number
>= 0x7fff)
7658 as_bad (_("operand overflow"));
7659 if (! target_big_endian
)
7660 ++offset_expr
.X_add_number
;
7661 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7662 if (! target_big_endian
)
7663 --offset_expr
.X_add_number
;
7665 ++offset_expr
.X_add_number
;
7666 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7667 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7668 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7681 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7682 as_bad (_("operand overflow"));
7690 if (! target_big_endian
)
7691 offset_expr
.X_add_number
+= off
;
7692 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7693 if (! target_big_endian
)
7694 offset_expr
.X_add_number
-= off
;
7696 offset_expr
.X_add_number
+= off
;
7697 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7699 /* If necessary, move the result in tempreg the final destination. */
7700 if (treg
== tempreg
)
7702 /* Protect second load's delay slot. */
7704 move_register (treg
, tempreg
);
7718 load_address (AT
, &offset_expr
, &used_at
);
7720 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7721 if (! target_big_endian
)
7722 expr1
.X_add_number
= off
;
7724 expr1
.X_add_number
= 0;
7725 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7726 if (! target_big_endian
)
7727 expr1
.X_add_number
= 0;
7729 expr1
.X_add_number
= off
;
7730 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7736 load_address (AT
, &offset_expr
, &used_at
);
7738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7739 if (target_big_endian
)
7740 expr1
.X_add_number
= 0;
7741 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7742 treg
, BFD_RELOC_LO16
, AT
);
7743 if (target_big_endian
)
7744 expr1
.X_add_number
= 1;
7746 expr1
.X_add_number
= 0;
7747 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7748 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7749 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7754 if (offset_expr
.X_add_number
>= 0x7fff)
7755 as_bad (_("operand overflow"));
7756 if (target_big_endian
)
7757 ++offset_expr
.X_add_number
;
7758 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7759 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7760 if (target_big_endian
)
7761 --offset_expr
.X_add_number
;
7763 ++offset_expr
.X_add_number
;
7764 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7777 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7778 as_bad (_("operand overflow"));
7779 if (! target_big_endian
)
7780 offset_expr
.X_add_number
+= off
;
7781 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7782 if (! target_big_endian
)
7783 offset_expr
.X_add_number
-= off
;
7785 offset_expr
.X_add_number
+= off
;
7786 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7800 load_address (AT
, &offset_expr
, &used_at
);
7802 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7803 if (! target_big_endian
)
7804 expr1
.X_add_number
= off
;
7806 expr1
.X_add_number
= 0;
7807 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7808 if (! target_big_endian
)
7809 expr1
.X_add_number
= 0;
7811 expr1
.X_add_number
= off
;
7812 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7817 load_address (AT
, &offset_expr
, &used_at
);
7819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7820 if (! target_big_endian
)
7821 expr1
.X_add_number
= 0;
7822 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7823 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7824 if (! target_big_endian
)
7825 expr1
.X_add_number
= 1;
7827 expr1
.X_add_number
= 0;
7828 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7829 if (! target_big_endian
)
7830 expr1
.X_add_number
= 0;
7832 expr1
.X_add_number
= 1;
7833 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7834 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7835 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7839 /* FIXME: Check if this is one of the itbl macros, since they
7840 are added dynamically. */
7841 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7844 if (mips_opts
.noat
&& used_at
)
7845 as_bad (_("Macro used $at after \".set noat\""));
7848 /* Implement macros in mips16 mode. */
7851 mips16_macro (struct mips_cl_insn
*ip
)
7854 int xreg
, yreg
, zreg
, tmp
;
7857 const char *s
, *s2
, *s3
;
7859 mask
= ip
->insn_mo
->mask
;
7861 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7862 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7863 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7865 expr1
.X_op
= O_constant
;
7866 expr1
.X_op_symbol
= NULL
;
7867 expr1
.X_add_symbol
= NULL
;
7868 expr1
.X_add_number
= 1;
7888 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7889 expr1
.X_add_number
= 2;
7890 macro_build (&expr1
, "bnez", "x,p", yreg
);
7891 macro_build (NULL
, "break", "6", 7);
7893 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7894 since that causes an overflow. We should do that as well,
7895 but I don't see how to do the comparisons without a temporary
7898 macro_build (NULL
, s
, "x", zreg
);
7918 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7919 expr1
.X_add_number
= 2;
7920 macro_build (&expr1
, "bnez", "x,p", yreg
);
7921 macro_build (NULL
, "break", "6", 7);
7923 macro_build (NULL
, s2
, "x", zreg
);
7929 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7930 macro_build (NULL
, "mflo", "x", zreg
);
7938 if (imm_expr
.X_op
!= O_constant
)
7939 as_bad (_("Unsupported large constant"));
7940 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7941 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7945 if (imm_expr
.X_op
!= O_constant
)
7946 as_bad (_("Unsupported large constant"));
7947 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7948 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7952 if (imm_expr
.X_op
!= O_constant
)
7953 as_bad (_("Unsupported large constant"));
7954 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7955 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7977 goto do_reverse_branch
;
7981 goto do_reverse_branch
;
7993 goto do_reverse_branch
;
8004 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8005 macro_build (&offset_expr
, s2
, "p");
8032 goto do_addone_branch_i
;
8037 goto do_addone_branch_i
;
8052 goto do_addone_branch_i
;
8059 if (imm_expr
.X_op
!= O_constant
)
8060 as_bad (_("Unsupported large constant"));
8061 ++imm_expr
.X_add_number
;
8064 macro_build (&imm_expr
, s
, s3
, xreg
);
8065 macro_build (&offset_expr
, s2
, "p");
8069 expr1
.X_add_number
= 0;
8070 macro_build (&expr1
, "slti", "x,8", yreg
);
8072 move_register (xreg
, yreg
);
8073 expr1
.X_add_number
= 2;
8074 macro_build (&expr1
, "bteqz", "p");
8075 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8079 /* For consistency checking, verify that all bits are specified either
8080 by the match/mask part of the instruction definition, or by the
8083 validate_mips_insn (const struct mips_opcode
*opc
)
8085 const char *p
= opc
->args
;
8087 unsigned long used_bits
= opc
->mask
;
8089 if ((used_bits
& opc
->match
) != opc
->match
)
8091 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8092 opc
->name
, opc
->args
);
8095 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8105 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8106 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8107 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8108 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8109 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8110 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8111 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8112 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8113 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8114 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8115 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8116 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8117 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8119 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8120 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8121 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8123 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8124 c
, opc
->name
, opc
->args
);
8128 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8129 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8131 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8132 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8133 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8134 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8136 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8137 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8139 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8140 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8142 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8143 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8144 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8145 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8146 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8147 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8148 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8149 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8150 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8151 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8152 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8153 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8154 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8155 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8156 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8157 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8158 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8160 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8161 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8162 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8163 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8165 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8166 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8167 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8168 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8169 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8170 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8171 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8172 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8173 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8176 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8177 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8178 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8179 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8180 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8183 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8184 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8185 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8186 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8187 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8188 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8189 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8190 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8191 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8192 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8193 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8194 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8195 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8196 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8197 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8198 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8200 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8201 c
, opc
->name
, opc
->args
);
8205 if (used_bits
!= 0xffffffff)
8207 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8208 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8214 /* UDI immediates. */
8222 static const struct mips_immed mips_immed
[] = {
8223 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8224 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8225 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8226 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8230 /* Check whether an odd floating-point register is allowed. */
8232 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8234 const char *s
= insn
->name
;
8236 if (insn
->pinfo
== INSN_MACRO
)
8237 /* Let a macro pass, we'll catch it later when it is expanded. */
8240 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8242 /* Allow odd registers for single-precision ops. */
8243 switch (insn
->pinfo
& (FP_S
| FP_D
))
8247 return 1; /* both single precision - ok */
8249 return 0; /* both double precision - fail */
8254 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8255 s
= strchr (insn
->name
, '.');
8257 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8258 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8261 /* Single-precision coprocessor loads and moves are OK too. */
8262 if ((insn
->pinfo
& FP_S
)
8263 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8264 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8270 /* This routine assembles an instruction into its binary format. As a
8271 side effect, it sets one of the global variables imm_reloc or
8272 offset_reloc to the type of relocation to do if one of the operands
8273 is an address expression. */
8276 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8281 struct mips_opcode
*insn
;
8284 unsigned int lastregno
= 0;
8285 unsigned int lastpos
= 0;
8286 unsigned int limlo
, limhi
;
8289 offsetT min_range
, max_range
;
8295 /* If the instruction contains a '.', we first try to match an instruction
8296 including the '.'. Then we try again without the '.'. */
8298 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8301 /* If we stopped on whitespace, then replace the whitespace with null for
8302 the call to hash_find. Save the character we replaced just in case we
8303 have to re-parse the instruction. */
8310 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8312 /* If we didn't find the instruction in the opcode table, try again, but
8313 this time with just the instruction up to, but not including the
8317 /* Restore the character we overwrite above (if any). */
8321 /* Scan up to the first '.' or whitespace. */
8323 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8327 /* If we did not find a '.', then we can quit now. */
8330 insn_error
= "unrecognized opcode";
8334 /* Lookup the instruction in the hash table. */
8336 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8338 insn_error
= "unrecognized opcode";
8348 assert (strcmp (insn
->name
, str
) == 0);
8350 if (OPCODE_IS_MEMBER (insn
,
8352 /* We don't check for mips_opts.mips16 here since
8353 we want to allow jalx if -mips16 was specified
8354 on the command line. */
8355 | (file_ase_mips16
? INSN_MIPS16
: 0)
8356 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8357 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8358 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
8360 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8361 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8362 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8368 if (insn
->pinfo
!= INSN_MACRO
)
8370 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8376 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8377 && strcmp (insn
->name
, insn
[1].name
) == 0)
8386 static char buf
[100];
8388 _("opcode not supported on this processor: %s (%s)"),
8389 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8390 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8399 create_insn (ip
, insn
);
8402 for (args
= insn
->args
;; ++args
)
8406 s
+= strspn (s
, " \t");
8410 case '\0': /* end of args */
8415 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8416 my_getExpression (&imm_expr
, s
);
8417 check_absolute_expr (ip
, &imm_expr
);
8418 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8420 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8421 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8423 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8424 imm_expr
.X_op
= O_absent
;
8428 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8429 my_getExpression (&imm_expr
, s
);
8430 check_absolute_expr (ip
, &imm_expr
);
8431 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8433 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8434 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8436 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8437 imm_expr
.X_op
= O_absent
;
8441 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8442 my_getExpression (&imm_expr
, s
);
8443 check_absolute_expr (ip
, &imm_expr
);
8444 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8446 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8447 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8449 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8450 imm_expr
.X_op
= O_absent
;
8454 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8455 my_getExpression (&imm_expr
, s
);
8456 check_absolute_expr (ip
, &imm_expr
);
8457 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8459 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8460 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8462 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8463 imm_expr
.X_op
= O_absent
;
8467 case '7': /* four dsp accumulators in bits 11,12 */
8468 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8469 s
[3] >= '0' && s
[3] <= '3')
8473 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8477 as_bad (_("Invalid dsp acc register"));
8480 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8481 my_getExpression (&imm_expr
, s
);
8482 check_absolute_expr (ip
, &imm_expr
);
8483 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8485 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8487 (unsigned long) imm_expr
.X_add_number
);
8489 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8490 imm_expr
.X_op
= O_absent
;
8494 case '9': /* four dsp accumulators in bits 21,22 */
8495 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8496 s
[3] >= '0' && s
[3] <= '3')
8500 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8504 as_bad (_("Invalid dsp acc register"));
8507 case '0': /* dsp 6-bit signed immediate in bit 20 */
8508 my_getExpression (&imm_expr
, s
);
8509 check_absolute_expr (ip
, &imm_expr
);
8510 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8511 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8512 if (imm_expr
.X_add_number
< min_range
||
8513 imm_expr
.X_add_number
> max_range
)
8515 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8516 (long) min_range
, (long) max_range
,
8517 (long) imm_expr
.X_add_number
);
8519 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8520 imm_expr
.X_op
= O_absent
;
8524 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8525 my_getExpression (&imm_expr
, s
);
8526 check_absolute_expr (ip
, &imm_expr
);
8527 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8529 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8531 (unsigned long) imm_expr
.X_add_number
);
8533 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8534 imm_expr
.X_op
= O_absent
;
8538 case ':': /* dsp 7-bit signed immediate in bit 19 */
8539 my_getExpression (&imm_expr
, s
);
8540 check_absolute_expr (ip
, &imm_expr
);
8541 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8542 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8543 if (imm_expr
.X_add_number
< min_range
||
8544 imm_expr
.X_add_number
> max_range
)
8546 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8547 (long) min_range
, (long) max_range
,
8548 (long) imm_expr
.X_add_number
);
8550 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8551 imm_expr
.X_op
= O_absent
;
8555 case '@': /* dsp 10-bit signed immediate in bit 16 */
8556 my_getExpression (&imm_expr
, s
);
8557 check_absolute_expr (ip
, &imm_expr
);
8558 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8559 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8560 if (imm_expr
.X_add_number
< min_range
||
8561 imm_expr
.X_add_number
> max_range
)
8563 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8564 (long) min_range
, (long) max_range
,
8565 (long) imm_expr
.X_add_number
);
8567 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8568 imm_expr
.X_op
= O_absent
;
8572 case '!': /* MT usermode flag bit. */
8573 my_getExpression (&imm_expr
, s
);
8574 check_absolute_expr (ip
, &imm_expr
);
8575 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8576 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8577 (unsigned long) imm_expr
.X_add_number
);
8578 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8579 imm_expr
.X_op
= O_absent
;
8583 case '$': /* MT load high flag bit. */
8584 my_getExpression (&imm_expr
, s
);
8585 check_absolute_expr (ip
, &imm_expr
);
8586 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8587 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8588 (unsigned long) imm_expr
.X_add_number
);
8589 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8590 imm_expr
.X_op
= O_absent
;
8594 case '*': /* four dsp accumulators in bits 18,19 */
8595 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8596 s
[3] >= '0' && s
[3] <= '3')
8600 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8604 as_bad (_("Invalid dsp/smartmips acc register"));
8607 case '&': /* four dsp accumulators in bits 13,14 */
8608 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8609 s
[3] >= '0' && s
[3] <= '3')
8613 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8617 as_bad (_("Invalid dsp/smartmips acc register"));
8628 INSERT_OPERAND (RS
, *ip
, lastregno
);
8632 INSERT_OPERAND (RT
, *ip
, lastregno
);
8636 INSERT_OPERAND (FT
, *ip
, lastregno
);
8640 INSERT_OPERAND (FS
, *ip
, lastregno
);
8646 /* Handle optional base register.
8647 Either the base register is omitted or
8648 we must have a left paren. */
8649 /* This is dependent on the next operand specifier
8650 is a base register specification. */
8651 assert (args
[1] == 'b' || args
[1] == '5'
8652 || args
[1] == '-' || args
[1] == '4');
8656 case ')': /* these must match exactly */
8663 case '+': /* Opcode extension character. */
8666 case '1': /* UDI immediates. */
8671 const struct mips_immed
*imm
= mips_immed
;
8673 while (imm
->type
&& imm
->type
!= *args
)
8677 my_getExpression (&imm_expr
, s
);
8678 check_absolute_expr (ip
, &imm_expr
);
8679 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8681 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8682 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8683 (unsigned long) imm_expr
.X_add_number
,
8684 (unsigned long) imm_expr
.X_add_number
);
8685 imm_expr
.X_add_number
&= imm
->mask
;
8687 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8689 imm_expr
.X_op
= O_absent
;
8694 case 'A': /* ins/ext position, becomes LSB. */
8703 my_getExpression (&imm_expr
, s
);
8704 check_absolute_expr (ip
, &imm_expr
);
8705 if ((unsigned long) imm_expr
.X_add_number
< limlo
8706 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8708 as_bad (_("Improper position (%lu)"),
8709 (unsigned long) imm_expr
.X_add_number
);
8710 imm_expr
.X_add_number
= limlo
;
8712 lastpos
= imm_expr
.X_add_number
;
8713 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8714 imm_expr
.X_op
= O_absent
;
8718 case 'B': /* ins size, becomes MSB. */
8727 my_getExpression (&imm_expr
, s
);
8728 check_absolute_expr (ip
, &imm_expr
);
8729 /* Check for negative input so that small negative numbers
8730 will not succeed incorrectly. The checks against
8731 (pos+size) transitively check "size" itself,
8732 assuming that "pos" is reasonable. */
8733 if ((long) imm_expr
.X_add_number
< 0
8734 || ((unsigned long) imm_expr
.X_add_number
8736 || ((unsigned long) imm_expr
.X_add_number
8739 as_bad (_("Improper insert size (%lu, position %lu)"),
8740 (unsigned long) imm_expr
.X_add_number
,
8741 (unsigned long) lastpos
);
8742 imm_expr
.X_add_number
= limlo
- lastpos
;
8744 INSERT_OPERAND (INSMSB
, *ip
,
8745 lastpos
+ imm_expr
.X_add_number
- 1);
8746 imm_expr
.X_op
= O_absent
;
8750 case 'C': /* ext size, becomes MSBD. */
8763 my_getExpression (&imm_expr
, s
);
8764 check_absolute_expr (ip
, &imm_expr
);
8765 /* Check for negative input so that small negative numbers
8766 will not succeed incorrectly. The checks against
8767 (pos+size) transitively check "size" itself,
8768 assuming that "pos" is reasonable. */
8769 if ((long) imm_expr
.X_add_number
< 0
8770 || ((unsigned long) imm_expr
.X_add_number
8772 || ((unsigned long) imm_expr
.X_add_number
8775 as_bad (_("Improper extract size (%lu, position %lu)"),
8776 (unsigned long) imm_expr
.X_add_number
,
8777 (unsigned long) lastpos
);
8778 imm_expr
.X_add_number
= limlo
- lastpos
;
8780 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8781 imm_expr
.X_op
= O_absent
;
8786 /* +D is for disassembly only; never match. */
8790 /* "+I" is like "I", except that imm2_expr is used. */
8791 my_getExpression (&imm2_expr
, s
);
8792 if (imm2_expr
.X_op
!= O_big
8793 && imm2_expr
.X_op
!= O_constant
)
8794 insn_error
= _("absolute expression required");
8795 if (HAVE_32BIT_GPRS
)
8796 normalize_constant_expr (&imm2_expr
);
8800 case 'T': /* Coprocessor register. */
8801 /* +T is for disassembly only; never match. */
8804 case 't': /* Coprocessor register number. */
8805 if (s
[0] == '$' && ISDIGIT (s
[1]))
8815 while (ISDIGIT (*s
));
8817 as_bad (_("Invalid register number (%d)"), regno
);
8820 INSERT_OPERAND (RT
, *ip
, regno
);
8825 as_bad (_("Invalid coprocessor 0 register number"));
8829 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8830 *args
, insn
->name
, insn
->args
);
8831 /* Further processing is fruitless. */
8836 case '<': /* must be at least one digit */
8838 * According to the manual, if the shift amount is greater
8839 * than 31 or less than 0, then the shift amount should be
8840 * mod 32. In reality the mips assembler issues an error.
8841 * We issue a warning and mask out all but the low 5 bits.
8843 my_getExpression (&imm_expr
, s
);
8844 check_absolute_expr (ip
, &imm_expr
);
8845 if ((unsigned long) imm_expr
.X_add_number
> 31)
8846 as_warn (_("Improper shift amount (%lu)"),
8847 (unsigned long) imm_expr
.X_add_number
);
8848 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8849 imm_expr
.X_op
= O_absent
;
8853 case '>': /* shift amount minus 32 */
8854 my_getExpression (&imm_expr
, s
);
8855 check_absolute_expr (ip
, &imm_expr
);
8856 if ((unsigned long) imm_expr
.X_add_number
< 32
8857 || (unsigned long) imm_expr
.X_add_number
> 63)
8859 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8860 imm_expr
.X_op
= O_absent
;
8864 case 'k': /* cache code */
8865 case 'h': /* prefx code */
8866 my_getExpression (&imm_expr
, s
);
8867 check_absolute_expr (ip
, &imm_expr
);
8868 if ((unsigned long) imm_expr
.X_add_number
> 31)
8869 as_warn (_("Invalid value for `%s' (%lu)"),
8871 (unsigned long) imm_expr
.X_add_number
);
8873 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8875 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8876 imm_expr
.X_op
= O_absent
;
8880 case 'c': /* break code */
8881 my_getExpression (&imm_expr
, s
);
8882 check_absolute_expr (ip
, &imm_expr
);
8883 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
8884 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8886 (unsigned long) imm_expr
.X_add_number
);
8887 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8888 imm_expr
.X_op
= O_absent
;
8892 case 'q': /* lower break code */
8893 my_getExpression (&imm_expr
, s
);
8894 check_absolute_expr (ip
, &imm_expr
);
8895 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
8896 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
8898 (unsigned long) imm_expr
.X_add_number
);
8899 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8900 imm_expr
.X_op
= O_absent
;
8904 case 'B': /* 20-bit syscall/break code. */
8905 my_getExpression (&imm_expr
, s
);
8906 check_absolute_expr (ip
, &imm_expr
);
8907 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8908 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
8910 (unsigned long) imm_expr
.X_add_number
);
8911 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8912 imm_expr
.X_op
= O_absent
;
8916 case 'C': /* Coprocessor code */
8917 my_getExpression (&imm_expr
, s
);
8918 check_absolute_expr (ip
, &imm_expr
);
8919 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
8921 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8922 (unsigned long) imm_expr
.X_add_number
);
8923 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
8925 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
8926 imm_expr
.X_op
= O_absent
;
8930 case 'J': /* 19-bit wait code. */
8931 my_getExpression (&imm_expr
, s
);
8932 check_absolute_expr (ip
, &imm_expr
);
8933 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8935 as_warn (_("Illegal 19-bit code (%lu)"),
8936 (unsigned long) imm_expr
.X_add_number
);
8937 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
8939 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8940 imm_expr
.X_op
= O_absent
;
8944 case 'P': /* Performance register. */
8945 my_getExpression (&imm_expr
, s
);
8946 check_absolute_expr (ip
, &imm_expr
);
8947 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8948 as_warn (_("Invalid performance register (%lu)"),
8949 (unsigned long) imm_expr
.X_add_number
);
8950 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8951 imm_expr
.X_op
= O_absent
;
8955 case 'G': /* Coprocessor destination register. */
8956 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
8957 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
8959 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
8960 INSERT_OPERAND (RD
, *ip
, regno
);
8969 case 'b': /* base register */
8970 case 'd': /* destination register */
8971 case 's': /* source register */
8972 case 't': /* target register */
8973 case 'r': /* both target and source */
8974 case 'v': /* both dest and source */
8975 case 'w': /* both dest and target */
8976 case 'E': /* coprocessor target register */
8977 case 'K': /* 'rdhwr' destination register */
8978 case 'x': /* ignore register name */
8979 case 'z': /* must be zero register */
8980 case 'U': /* destination register (clo/clz). */
8981 case 'g': /* coprocessor destination register */
8983 if (*args
== 'E' || *args
== 'K')
8984 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
8987 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
8988 if (regno
== AT
&& ! mips_opts
.noat
)
8989 as_warn ("Used $at without \".set noat\"");
8998 if (c
== 'r' || c
== 'v' || c
== 'w')
9005 /* 'z' only matches $0. */
9006 if (c
== 'z' && regno
!= 0)
9009 /* Now that we have assembled one operand, we use the args string
9010 * to figure out where it goes in the instruction. */
9017 INSERT_OPERAND (RS
, *ip
, regno
);
9023 INSERT_OPERAND (RD
, *ip
, regno
);
9026 INSERT_OPERAND (RD
, *ip
, regno
);
9027 INSERT_OPERAND (RT
, *ip
, regno
);
9032 INSERT_OPERAND (RT
, *ip
, regno
);
9035 /* This case exists because on the r3000 trunc
9036 expands into a macro which requires a gp
9037 register. On the r6000 or r4000 it is
9038 assembled into a single instruction which
9039 ignores the register. Thus the insn version
9040 is MIPS_ISA2 and uses 'x', and the macro
9041 version is MIPS_ISA1 and uses 't'. */
9044 /* This case is for the div instruction, which
9045 acts differently if the destination argument
9046 is $0. This only matches $0, and is checked
9047 outside the switch. */
9050 /* Itbl operand; not yet implemented. FIXME ?? */
9052 /* What about all other operands like 'i', which
9053 can be specified in the opcode table? */
9062 INSERT_OPERAND (RS
, *ip
, lastregno
);
9065 INSERT_OPERAND (RT
, *ip
, lastregno
);
9070 case 'O': /* MDMX alignment immediate constant. */
9071 my_getExpression (&imm_expr
, s
);
9072 check_absolute_expr (ip
, &imm_expr
);
9073 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9074 as_warn ("Improper align amount (%ld), using low bits",
9075 (long) imm_expr
.X_add_number
);
9076 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9077 imm_expr
.X_op
= O_absent
;
9081 case 'Q': /* MDMX vector, element sel, or const. */
9084 /* MDMX Immediate. */
9085 my_getExpression (&imm_expr
, s
);
9086 check_absolute_expr (ip
, &imm_expr
);
9087 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9088 as_warn (_("Invalid MDMX Immediate (%ld)"),
9089 (long) imm_expr
.X_add_number
);
9090 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9091 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9092 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9094 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9095 imm_expr
.X_op
= O_absent
;
9099 /* Not MDMX Immediate. Fall through. */
9100 case 'X': /* MDMX destination register. */
9101 case 'Y': /* MDMX source register. */
9102 case 'Z': /* MDMX target register. */
9104 case 'D': /* floating point destination register */
9105 case 'S': /* floating point source register */
9106 case 'T': /* floating point target register */
9107 case 'R': /* floating point source register */
9112 || (mips_opts
.ase_mdmx
9113 && (ip
->insn_mo
->pinfo
& FP_D
)
9114 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9115 | INSN_COPROC_MEMORY_DELAY
9116 | INSN_LOAD_COPROC_DELAY
9117 | INSN_LOAD_MEMORY_DELAY
9118 | INSN_STORE_MEMORY
))))
9121 if (reg_lookup (&s
, rtype
, ®no
))
9123 if ((regno
& 1) != 0
9125 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9126 as_warn (_("Float register should be even, was %d"),
9134 if (c
== 'V' || c
== 'W')
9145 INSERT_OPERAND (FD
, *ip
, regno
);
9150 INSERT_OPERAND (FS
, *ip
, regno
);
9153 /* This is like 'Z', but also needs to fix the MDMX
9154 vector/scalar select bits. Note that the
9155 scalar immediate case is handled above. */
9158 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9159 int max_el
= (is_qh
? 3 : 7);
9161 my_getExpression(&imm_expr
, s
);
9162 check_absolute_expr (ip
, &imm_expr
);
9164 if (imm_expr
.X_add_number
> max_el
)
9165 as_bad(_("Bad element selector %ld"),
9166 (long) imm_expr
.X_add_number
);
9167 imm_expr
.X_add_number
&= max_el
;
9168 ip
->insn_opcode
|= (imm_expr
.X_add_number
9171 imm_expr
.X_op
= O_absent
;
9173 as_warn(_("Expecting ']' found '%s'"), s
);
9179 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9180 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9183 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9190 INSERT_OPERAND (FT
, *ip
, regno
);
9193 INSERT_OPERAND (FR
, *ip
, regno
);
9203 INSERT_OPERAND (FS
, *ip
, lastregno
);
9206 INSERT_OPERAND (FT
, *ip
, lastregno
);
9212 my_getExpression (&imm_expr
, s
);
9213 if (imm_expr
.X_op
!= O_big
9214 && imm_expr
.X_op
!= O_constant
)
9215 insn_error
= _("absolute expression required");
9216 if (HAVE_32BIT_GPRS
)
9217 normalize_constant_expr (&imm_expr
);
9222 my_getExpression (&offset_expr
, s
);
9223 normalize_address_expr (&offset_expr
);
9224 *imm_reloc
= BFD_RELOC_32
;
9237 unsigned char temp
[8];
9239 unsigned int length
;
9244 /* These only appear as the last operand in an
9245 instruction, and every instruction that accepts
9246 them in any variant accepts them in all variants.
9247 This means we don't have to worry about backing out
9248 any changes if the instruction does not match.
9250 The difference between them is the size of the
9251 floating point constant and where it goes. For 'F'
9252 and 'L' the constant is 64 bits; for 'f' and 'l' it
9253 is 32 bits. Where the constant is placed is based
9254 on how the MIPS assembler does things:
9257 f -- immediate value
9260 The .lit4 and .lit8 sections are only used if
9261 permitted by the -G argument.
9263 The code below needs to know whether the target register
9264 is 32 or 64 bits wide. It relies on the fact 'f' and
9265 'F' are used with GPR-based instructions and 'l' and
9266 'L' are used with FPR-based instructions. */
9268 f64
= *args
== 'F' || *args
== 'L';
9269 using_gprs
= *args
== 'F' || *args
== 'f';
9271 save_in
= input_line_pointer
;
9272 input_line_pointer
= s
;
9273 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9275 s
= input_line_pointer
;
9276 input_line_pointer
= save_in
;
9277 if (err
!= NULL
&& *err
!= '\0')
9279 as_bad (_("Bad floating point constant: %s"), err
);
9280 memset (temp
, '\0', sizeof temp
);
9281 length
= f64
? 8 : 4;
9284 assert (length
== (unsigned) (f64
? 8 : 4));
9288 && (g_switch_value
< 4
9289 || (temp
[0] == 0 && temp
[1] == 0)
9290 || (temp
[2] == 0 && temp
[3] == 0))))
9292 imm_expr
.X_op
= O_constant
;
9293 if (! target_big_endian
)
9294 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9296 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9299 && ! mips_disable_float_construction
9300 /* Constants can only be constructed in GPRs and
9301 copied to FPRs if the GPRs are at least as wide
9302 as the FPRs. Force the constant into memory if
9303 we are using 64-bit FPRs but the GPRs are only
9306 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9307 && ((temp
[0] == 0 && temp
[1] == 0)
9308 || (temp
[2] == 0 && temp
[3] == 0))
9309 && ((temp
[4] == 0 && temp
[5] == 0)
9310 || (temp
[6] == 0 && temp
[7] == 0)))
9312 /* The value is simple enough to load with a couple of
9313 instructions. If using 32-bit registers, set
9314 imm_expr to the high order 32 bits and offset_expr to
9315 the low order 32 bits. Otherwise, set imm_expr to
9316 the entire 64 bit constant. */
9317 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9319 imm_expr
.X_op
= O_constant
;
9320 offset_expr
.X_op
= O_constant
;
9321 if (! target_big_endian
)
9323 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9324 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9328 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9329 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9331 if (offset_expr
.X_add_number
== 0)
9332 offset_expr
.X_op
= O_absent
;
9334 else if (sizeof (imm_expr
.X_add_number
) > 4)
9336 imm_expr
.X_op
= O_constant
;
9337 if (! target_big_endian
)
9338 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9340 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9344 imm_expr
.X_op
= O_big
;
9345 imm_expr
.X_add_number
= 4;
9346 if (! target_big_endian
)
9348 generic_bignum
[0] = bfd_getl16 (temp
);
9349 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9350 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9351 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9355 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9356 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9357 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9358 generic_bignum
[3] = bfd_getb16 (temp
);
9364 const char *newname
;
9367 /* Switch to the right section. */
9369 subseg
= now_subseg
;
9372 default: /* unused default case avoids warnings. */
9374 newname
= RDATA_SECTION_NAME
;
9375 if (g_switch_value
>= 8)
9379 newname
= RDATA_SECTION_NAME
;
9382 assert (g_switch_value
>= 4);
9386 new_seg
= subseg_new (newname
, (subsegT
) 0);
9387 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9388 bfd_set_section_flags (stdoutput
, new_seg
,
9393 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9394 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9395 && strcmp (TARGET_OS
, "elf") != 0)
9396 record_alignment (new_seg
, 4);
9398 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9400 as_bad (_("Can't use floating point insn in this section"));
9402 /* Set the argument to the current address in the
9404 offset_expr
.X_op
= O_symbol
;
9405 offset_expr
.X_add_symbol
=
9406 symbol_new ("L0\001", now_seg
,
9407 (valueT
) frag_now_fix (), frag_now
);
9408 offset_expr
.X_add_number
= 0;
9410 /* Put the floating point number into the section. */
9411 p
= frag_more ((int) length
);
9412 memcpy (p
, temp
, length
);
9414 /* Switch back to the original section. */
9415 subseg_set (seg
, subseg
);
9420 case 'i': /* 16 bit unsigned immediate */
9421 case 'j': /* 16 bit signed immediate */
9422 *imm_reloc
= BFD_RELOC_LO16
;
9423 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9426 offsetT minval
, maxval
;
9428 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9429 && strcmp (insn
->name
, insn
[1].name
) == 0);
9431 /* If the expression was written as an unsigned number,
9432 only treat it as signed if there are no more
9436 && sizeof (imm_expr
.X_add_number
) <= 4
9437 && imm_expr
.X_op
== O_constant
9438 && imm_expr
.X_add_number
< 0
9439 && imm_expr
.X_unsigned
9443 /* For compatibility with older assemblers, we accept
9444 0x8000-0xffff as signed 16-bit numbers when only
9445 signed numbers are allowed. */
9447 minval
= 0, maxval
= 0xffff;
9449 minval
= -0x8000, maxval
= 0x7fff;
9451 minval
= -0x8000, maxval
= 0xffff;
9453 if (imm_expr
.X_op
!= O_constant
9454 || imm_expr
.X_add_number
< minval
9455 || imm_expr
.X_add_number
> maxval
)
9459 if (imm_expr
.X_op
== O_constant
9460 || imm_expr
.X_op
== O_big
)
9461 as_bad (_("expression out of range"));
9467 case 'o': /* 16 bit offset */
9468 /* Check whether there is only a single bracketed expression
9469 left. If so, it must be the base register and the
9470 constant must be zero. */
9471 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9473 offset_expr
.X_op
= O_constant
;
9474 offset_expr
.X_add_number
= 0;
9478 /* If this value won't fit into a 16 bit offset, then go
9479 find a macro that will generate the 32 bit offset
9481 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9482 && (offset_expr
.X_op
!= O_constant
9483 || offset_expr
.X_add_number
>= 0x8000
9484 || offset_expr
.X_add_number
< -0x8000))
9490 case 'p': /* pc relative offset */
9491 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9492 my_getExpression (&offset_expr
, s
);
9496 case 'u': /* upper 16 bits */
9497 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9498 && imm_expr
.X_op
== O_constant
9499 && (imm_expr
.X_add_number
< 0
9500 || imm_expr
.X_add_number
>= 0x10000))
9501 as_bad (_("lui expression not in range 0..65535"));
9505 case 'a': /* 26 bit address */
9506 my_getExpression (&offset_expr
, s
);
9508 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9511 case 'N': /* 3 bit branch condition code */
9512 case 'M': /* 3 bit compare condition code */
9514 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9516 if (!reg_lookup (&s
, rtype
, ®no
))
9518 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9519 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9520 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9521 && (regno
& 1) != 0)
9522 as_warn(_("Condition code register should be even for %s, was %d"),
9524 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9525 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9526 && (regno
& 3) != 0)
9527 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9530 INSERT_OPERAND (BCC
, *ip
, regno
);
9532 INSERT_OPERAND (CCC
, *ip
, regno
);
9536 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9547 while (ISDIGIT (*s
));
9550 c
= 8; /* Invalid sel value. */
9553 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9554 ip
->insn_opcode
|= c
;
9558 /* Must be at least one digit. */
9559 my_getExpression (&imm_expr
, s
);
9560 check_absolute_expr (ip
, &imm_expr
);
9562 if ((unsigned long) imm_expr
.X_add_number
9563 > (unsigned long) OP_MASK_VECBYTE
)
9565 as_bad (_("bad byte vector index (%ld)"),
9566 (long) imm_expr
.X_add_number
);
9567 imm_expr
.X_add_number
= 0;
9570 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9571 imm_expr
.X_op
= O_absent
;
9576 my_getExpression (&imm_expr
, s
);
9577 check_absolute_expr (ip
, &imm_expr
);
9579 if ((unsigned long) imm_expr
.X_add_number
9580 > (unsigned long) OP_MASK_VECALIGN
)
9582 as_bad (_("bad byte vector index (%ld)"),
9583 (long) imm_expr
.X_add_number
);
9584 imm_expr
.X_add_number
= 0;
9587 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9588 imm_expr
.X_op
= O_absent
;
9593 as_bad (_("bad char = '%c'\n"), *args
);
9598 /* Args don't match. */
9599 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9600 !strcmp (insn
->name
, insn
[1].name
))
9604 insn_error
= _("illegal operands");
9609 insn_error
= _("illegal operands");
9614 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9616 /* This routine assembles an instruction into its binary format when
9617 assembling for the mips16. As a side effect, it sets one of the
9618 global variables imm_reloc or offset_reloc to the type of
9619 relocation to do if one of the operands is an address expression.
9620 It also sets mips16_small and mips16_ext if the user explicitly
9621 requested a small or extended instruction. */
9624 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9628 struct mips_opcode
*insn
;
9631 unsigned int lastregno
= 0;
9637 mips16_small
= FALSE
;
9640 for (s
= str
; ISLOWER (*s
); ++s
)
9652 if (s
[1] == 't' && s
[2] == ' ')
9655 mips16_small
= TRUE
;
9659 else if (s
[1] == 'e' && s
[2] == ' ')
9668 insn_error
= _("unknown opcode");
9672 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9673 mips16_small
= TRUE
;
9675 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9677 insn_error
= _("unrecognized opcode");
9686 assert (strcmp (insn
->name
, str
) == 0);
9688 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9695 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9696 && strcmp (insn
->name
, insn
[1].name
) == 0)
9705 static char buf
[100];
9707 _("opcode not supported on this processor: %s (%s)"),
9708 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9709 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9716 create_insn (ip
, insn
);
9717 imm_expr
.X_op
= O_absent
;
9718 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9719 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9720 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9721 imm2_expr
.X_op
= O_absent
;
9722 offset_expr
.X_op
= O_absent
;
9723 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9724 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9725 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9726 for (args
= insn
->args
; 1; ++args
)
9733 /* In this switch statement we call break if we did not find
9734 a match, continue if we did find a match, or return if we
9743 /* Stuff the immediate value in now, if we can. */
9744 if (imm_expr
.X_op
== O_constant
9745 && *imm_reloc
> BFD_RELOC_UNUSED
9746 && insn
->pinfo
!= INSN_MACRO
)
9750 switch (*offset_reloc
)
9752 case BFD_RELOC_MIPS16_HI16_S
:
9753 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9756 case BFD_RELOC_MIPS16_HI16
:
9757 tmp
= imm_expr
.X_add_number
>> 16;
9760 case BFD_RELOC_MIPS16_LO16
:
9761 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9765 case BFD_RELOC_UNUSED
:
9766 tmp
= imm_expr
.X_add_number
;
9772 *offset_reloc
= BFD_RELOC_UNUSED
;
9774 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9775 tmp
, TRUE
, mips16_small
,
9776 mips16_ext
, &ip
->insn_opcode
,
9777 &ip
->use_extend
, &ip
->extend
);
9778 imm_expr
.X_op
= O_absent
;
9779 *imm_reloc
= BFD_RELOC_UNUSED
;
9793 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9796 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9812 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9814 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9829 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9831 if (c
== 'v' || c
== 'w')
9834 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9836 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9847 if (c
== 'v' || c
== 'w')
9849 regno
= mips16_to_32_reg_map
[lastregno
];
9863 regno
= mips32_to_16_reg_map
[regno
];
9868 regno
= ILLEGAL_REG
;
9873 regno
= ILLEGAL_REG
;
9878 regno
= ILLEGAL_REG
;
9883 if (regno
== AT
&& ! mips_opts
.noat
)
9884 as_warn (_("used $at without \".set noat\""));
9891 if (regno
== ILLEGAL_REG
)
9898 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9902 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9905 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9908 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9914 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9917 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9918 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9928 if (strncmp (s
, "$pc", 3) == 0)
9945 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9948 if (imm_expr
.X_op
!= O_constant
)
9951 ip
->use_extend
= TRUE
;
9956 /* We need to relax this instruction. */
9957 *offset_reloc
= *imm_reloc
;
9958 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9963 *imm_reloc
= BFD_RELOC_UNUSED
;
9971 my_getExpression (&imm_expr
, s
);
9972 if (imm_expr
.X_op
== O_register
)
9974 /* What we thought was an expression turned out to
9977 if (s
[0] == '(' && args
[1] == '(')
9979 /* It looks like the expression was omitted
9980 before a register indirection, which means
9981 that the expression is implicitly zero. We
9982 still set up imm_expr, so that we handle
9983 explicit extensions correctly. */
9984 imm_expr
.X_op
= O_constant
;
9985 imm_expr
.X_add_number
= 0;
9986 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9993 /* We need to relax this instruction. */
9994 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10003 /* We use offset_reloc rather than imm_reloc for the PC
10004 relative operands. This lets macros with both
10005 immediate and address operands work correctly. */
10006 my_getExpression (&offset_expr
, s
);
10008 if (offset_expr
.X_op
== O_register
)
10011 /* We need to relax this instruction. */
10012 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10016 case '6': /* break code */
10017 my_getExpression (&imm_expr
, s
);
10018 check_absolute_expr (ip
, &imm_expr
);
10019 if ((unsigned long) imm_expr
.X_add_number
> 63)
10020 as_warn (_("Invalid value for `%s' (%lu)"),
10022 (unsigned long) imm_expr
.X_add_number
);
10023 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10024 imm_expr
.X_op
= O_absent
;
10028 case 'a': /* 26 bit address */
10029 my_getExpression (&offset_expr
, s
);
10031 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10032 ip
->insn_opcode
<<= 16;
10035 case 'l': /* register list for entry macro */
10036 case 'L': /* register list for exit macro */
10046 unsigned int freg
, reg1
, reg2
;
10048 while (*s
== ' ' || *s
== ',')
10050 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10052 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10056 as_bad (_("can't parse register list"));
10066 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10067 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10069 as_bad (_("invalid register list"));
10073 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10075 mask
&= ~ (7 << 3);
10078 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10080 mask
&= ~ (7 << 3);
10083 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10084 mask
|= (reg2
- 3) << 3;
10085 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10086 mask
|= (reg2
- 15) << 1;
10087 else if (reg1
== RA
&& reg2
== RA
)
10091 as_bad (_("invalid register list"));
10095 /* The mask is filled in in the opcode table for the
10096 benefit of the disassembler. We remove it before
10097 applying the actual mask. */
10098 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10099 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10103 case 'm': /* Register list for save insn. */
10104 case 'M': /* Register list for restore insn. */
10107 int framesz
= 0, seen_framesz
= 0;
10108 int args
= 0, statics
= 0, sregs
= 0;
10112 unsigned int reg1
, reg2
;
10114 SKIP_SPACE_TABS (s
);
10117 SKIP_SPACE_TABS (s
);
10119 my_getExpression (&imm_expr
, s
);
10120 if (imm_expr
.X_op
== O_constant
)
10122 /* Handle the frame size. */
10125 as_bad (_("more than one frame size in list"));
10129 framesz
= imm_expr
.X_add_number
;
10130 imm_expr
.X_op
= O_absent
;
10135 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10137 as_bad (_("can't parse register list"));
10149 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10152 as_bad (_("can't parse register list"));
10157 while (reg1
<= reg2
)
10159 if (reg1
>= 4 && reg1
<= 7)
10161 if (c
== 'm' && !seen_framesz
)
10163 args
|= 1 << (reg1
- 4);
10165 /* statics $a0-$a3 */
10166 statics
|= 1 << (reg1
- 4);
10168 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10171 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10173 else if (reg1
== 31)
10175 /* Add $ra to insn. */
10180 as_bad (_("unexpected register in list"));
10188 /* Encode args/statics combination. */
10189 if (args
& statics
)
10190 as_bad (_("arg/static registers overlap"));
10191 else if (args
== 0xf)
10192 /* All $a0-$a3 are args. */
10193 opcode
|= MIPS16_ALL_ARGS
<< 16;
10194 else if (statics
== 0xf)
10195 /* All $a0-$a3 are statics. */
10196 opcode
|= MIPS16_ALL_STATICS
<< 16;
10199 int narg
= 0, nstat
= 0;
10201 /* Count arg registers. */
10208 as_bad (_("invalid arg register list"));
10210 /* Count static registers. */
10211 while (statics
& 0x8)
10213 statics
= (statics
<< 1) & 0xf;
10217 as_bad (_("invalid static register list"));
10219 /* Encode args/statics. */
10220 opcode
|= ((narg
<< 2) | nstat
) << 16;
10223 /* Encode $s0/$s1. */
10224 if (sregs
& (1 << 0)) /* $s0 */
10226 if (sregs
& (1 << 1)) /* $s1 */
10232 /* Count regs $s2-$s8. */
10240 as_bad (_("invalid static register list"));
10241 /* Encode $s2-$s8. */
10242 opcode
|= nsreg
<< 24;
10245 /* Encode frame size. */
10247 as_bad (_("missing frame size"));
10248 else if ((framesz
& 7) != 0 || framesz
< 0
10249 || framesz
> 0xff * 8)
10250 as_bad (_("invalid frame size"));
10251 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10254 opcode
|= (((framesz
& 0xf0) << 16)
10255 | (framesz
& 0x0f));
10258 /* Finally build the instruction. */
10259 if ((opcode
>> 16) != 0 || framesz
== 0)
10261 ip
->use_extend
= TRUE
;
10262 ip
->extend
= opcode
>> 16;
10264 ip
->insn_opcode
|= opcode
& 0x7f;
10268 case 'e': /* extend code */
10269 my_getExpression (&imm_expr
, s
);
10270 check_absolute_expr (ip
, &imm_expr
);
10271 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10273 as_warn (_("Invalid value for `%s' (%lu)"),
10275 (unsigned long) imm_expr
.X_add_number
);
10276 imm_expr
.X_add_number
&= 0x7ff;
10278 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10279 imm_expr
.X_op
= O_absent
;
10289 /* Args don't match. */
10290 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10291 strcmp (insn
->name
, insn
[1].name
) == 0)
10298 insn_error
= _("illegal operands");
10304 /* This structure holds information we know about a mips16 immediate
10307 struct mips16_immed_operand
10309 /* The type code used in the argument string in the opcode table. */
10311 /* The number of bits in the short form of the opcode. */
10313 /* The number of bits in the extended form of the opcode. */
10315 /* The amount by which the short form is shifted when it is used;
10316 for example, the sw instruction has a shift count of 2. */
10318 /* The amount by which the short form is shifted when it is stored
10319 into the instruction code. */
10321 /* Non-zero if the short form is unsigned. */
10323 /* Non-zero if the extended form is unsigned. */
10325 /* Non-zero if the value is PC relative. */
10329 /* The mips16 immediate operand types. */
10331 static const struct mips16_immed_operand mips16_immed_operands
[] =
10333 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10334 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10335 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10336 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10337 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10338 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10339 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10340 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10341 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10342 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10343 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10344 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10345 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10346 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10347 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10348 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10349 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10350 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10351 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10352 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10353 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10356 #define MIPS16_NUM_IMMED \
10357 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10359 /* Handle a mips16 instruction with an immediate value. This or's the
10360 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10361 whether an extended value is needed; if one is needed, it sets
10362 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10363 If SMALL is true, an unextended opcode was explicitly requested.
10364 If EXT is true, an extended opcode was explicitly requested. If
10365 WARN is true, warn if EXT does not match reality. */
10368 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10369 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10370 unsigned long *insn
, bfd_boolean
*use_extend
,
10371 unsigned short *extend
)
10373 register const struct mips16_immed_operand
*op
;
10374 int mintiny
, maxtiny
;
10375 bfd_boolean needext
;
10377 op
= mips16_immed_operands
;
10378 while (op
->type
!= type
)
10381 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10386 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10389 maxtiny
= 1 << op
->nbits
;
10394 maxtiny
= (1 << op
->nbits
) - 1;
10399 mintiny
= - (1 << (op
->nbits
- 1));
10400 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10403 /* Branch offsets have an implicit 0 in the lowest bit. */
10404 if (type
== 'p' || type
== 'q')
10407 if ((val
& ((1 << op
->shift
) - 1)) != 0
10408 || val
< (mintiny
<< op
->shift
)
10409 || val
> (maxtiny
<< op
->shift
))
10414 if (warn
&& ext
&& ! needext
)
10415 as_warn_where (file
, line
,
10416 _("extended operand requested but not required"));
10417 if (small
&& needext
)
10418 as_bad_where (file
, line
, _("invalid unextended operand value"));
10420 if (small
|| (! ext
&& ! needext
))
10424 *use_extend
= FALSE
;
10425 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10426 insnval
<<= op
->op_shift
;
10431 long minext
, maxext
;
10437 maxext
= (1 << op
->extbits
) - 1;
10441 minext
= - (1 << (op
->extbits
- 1));
10442 maxext
= (1 << (op
->extbits
- 1)) - 1;
10444 if (val
< minext
|| val
> maxext
)
10445 as_bad_where (file
, line
,
10446 _("operand value out of range for instruction"));
10448 *use_extend
= TRUE
;
10449 if (op
->extbits
== 16)
10451 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10454 else if (op
->extbits
== 15)
10456 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10461 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10465 *extend
= (unsigned short) extval
;
10470 struct percent_op_match
10473 bfd_reloc_code_real_type reloc
;
10476 static const struct percent_op_match mips_percent_op
[] =
10478 {"%lo", BFD_RELOC_LO16
},
10480 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10481 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10482 {"%call16", BFD_RELOC_MIPS_CALL16
},
10483 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10484 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10485 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10486 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10487 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10488 {"%got", BFD_RELOC_MIPS_GOT16
},
10489 {"%gp_rel", BFD_RELOC_GPREL16
},
10490 {"%half", BFD_RELOC_16
},
10491 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10492 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10493 {"%neg", BFD_RELOC_MIPS_SUB
},
10494 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10495 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10496 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10497 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10498 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10499 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10500 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10502 {"%hi", BFD_RELOC_HI16_S
}
10505 static const struct percent_op_match mips16_percent_op
[] =
10507 {"%lo", BFD_RELOC_MIPS16_LO16
},
10508 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10509 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10513 /* Return true if *STR points to a relocation operator. When returning true,
10514 move *STR over the operator and store its relocation code in *RELOC.
10515 Leave both *STR and *RELOC alone when returning false. */
10518 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10520 const struct percent_op_match
*percent_op
;
10523 if (mips_opts
.mips16
)
10525 percent_op
= mips16_percent_op
;
10526 limit
= ARRAY_SIZE (mips16_percent_op
);
10530 percent_op
= mips_percent_op
;
10531 limit
= ARRAY_SIZE (mips_percent_op
);
10534 for (i
= 0; i
< limit
; i
++)
10535 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10537 int len
= strlen (percent_op
[i
].str
);
10539 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10542 *str
+= strlen (percent_op
[i
].str
);
10543 *reloc
= percent_op
[i
].reloc
;
10545 /* Check whether the output BFD supports this relocation.
10546 If not, issue an error and fall back on something safe. */
10547 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10549 as_bad ("relocation %s isn't supported by the current ABI",
10550 percent_op
[i
].str
);
10551 *reloc
= BFD_RELOC_UNUSED
;
10559 /* Parse string STR as a 16-bit relocatable operand. Store the
10560 expression in *EP and the relocations in the array starting
10561 at RELOC. Return the number of relocation operators used.
10563 On exit, EXPR_END points to the first character after the expression. */
10566 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10569 bfd_reloc_code_real_type reversed_reloc
[3];
10570 size_t reloc_index
, i
;
10571 int crux_depth
, str_depth
;
10574 /* Search for the start of the main expression, recoding relocations
10575 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10576 of the main expression and with CRUX_DEPTH containing the number
10577 of open brackets at that point. */
10584 crux_depth
= str_depth
;
10586 /* Skip over whitespace and brackets, keeping count of the number
10588 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10593 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10594 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10596 my_getExpression (ep
, crux
);
10599 /* Match every open bracket. */
10600 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10604 if (crux_depth
> 0)
10605 as_bad ("unclosed '('");
10609 if (reloc_index
!= 0)
10611 prev_reloc_op_frag
= frag_now
;
10612 for (i
= 0; i
< reloc_index
; i
++)
10613 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10616 return reloc_index
;
10620 my_getExpression (expressionS
*ep
, char *str
)
10625 save_in
= input_line_pointer
;
10626 input_line_pointer
= str
;
10628 expr_end
= input_line_pointer
;
10629 input_line_pointer
= save_in
;
10631 /* If we are in mips16 mode, and this is an expression based on `.',
10632 then we bump the value of the symbol by 1 since that is how other
10633 text symbols are handled. We don't bother to handle complex
10634 expressions, just `.' plus or minus a constant. */
10635 if (mips_opts
.mips16
10636 && ep
->X_op
== O_symbol
10637 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10638 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10639 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10640 && symbol_constant_p (ep
->X_add_symbol
)
10641 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10642 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10645 /* Turn a string in input_line_pointer into a floating point constant
10646 of type TYPE, and store the appropriate bytes in *LITP. The number
10647 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10648 returned, or NULL on OK. */
10651 md_atof (int type
, char *litP
, int *sizeP
)
10654 LITTLENUM_TYPE words
[4];
10670 return _("bad call to md_atof");
10673 t
= atof_ieee (input_line_pointer
, type
, words
);
10675 input_line_pointer
= t
;
10679 if (! target_big_endian
)
10681 for (i
= prec
- 1; i
>= 0; i
--)
10683 md_number_to_chars (litP
, words
[i
], 2);
10689 for (i
= 0; i
< prec
; i
++)
10691 md_number_to_chars (litP
, words
[i
], 2);
10700 md_number_to_chars (char *buf
, valueT val
, int n
)
10702 if (target_big_endian
)
10703 number_to_chars_bigendian (buf
, val
, n
);
10705 number_to_chars_littleendian (buf
, val
, n
);
10709 static int support_64bit_objects(void)
10711 const char **list
, **l
;
10714 list
= bfd_target_list ();
10715 for (l
= list
; *l
!= NULL
; l
++)
10717 /* This is traditional mips */
10718 if (strcmp (*l
, "elf64-tradbigmips") == 0
10719 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10721 if (strcmp (*l
, "elf64-bigmips") == 0
10722 || strcmp (*l
, "elf64-littlemips") == 0)
10725 yes
= (*l
!= NULL
);
10729 #endif /* OBJ_ELF */
10731 const char *md_shortopts
= "O::g::G:";
10733 struct option md_longopts
[] =
10735 /* Options which specify architecture. */
10736 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10737 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10738 {"march", required_argument
, NULL
, OPTION_MARCH
},
10739 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10740 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10741 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10742 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10743 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10744 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10745 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10746 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10747 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10748 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10749 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10750 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10751 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10752 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10753 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10754 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10755 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10756 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10757 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10758 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10759 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10761 /* Options which specify Application Specific Extensions (ASEs). */
10762 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10763 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10764 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10765 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10766 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10767 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10768 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10769 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10770 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10771 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10772 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10773 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10774 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10775 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10776 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10777 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10778 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10779 #define OPTION_MT (OPTION_ASE_BASE + 8)
10780 {"mmt", no_argument
, NULL
, OPTION_MT
},
10781 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10782 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10783 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10784 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10785 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10786 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10788 /* Old-style architecture options. Don't add more of these. */
10789 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10790 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10791 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10792 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10793 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10794 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10795 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10796 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10797 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10798 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10799 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10800 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10801 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10802 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10803 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10804 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10805 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10807 /* Options which enable bug fixes. */
10808 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10809 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10810 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10811 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10812 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10813 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10814 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10815 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10816 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10817 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10818 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10819 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10820 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10821 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10823 /* Miscellaneous options. */
10824 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10825 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10826 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10827 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10828 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10829 {"break", no_argument
, NULL
, OPTION_BREAK
},
10830 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10831 #define OPTION_EB (OPTION_MISC_BASE + 2)
10832 {"EB", no_argument
, NULL
, OPTION_EB
},
10833 #define OPTION_EL (OPTION_MISC_BASE + 3)
10834 {"EL", no_argument
, NULL
, OPTION_EL
},
10835 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10836 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10837 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10838 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10839 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10840 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10841 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10842 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10843 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10844 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10845 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10846 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10847 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10848 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10849 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10850 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10851 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10852 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10853 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10854 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10855 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10856 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10857 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10858 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10860 /* ELF-specific options. */
10862 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10863 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10864 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10865 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10866 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10867 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10868 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10869 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10870 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10871 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10872 #define OPTION_32 (OPTION_ELF_BASE + 4)
10873 {"32", no_argument
, NULL
, OPTION_32
},
10874 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10875 {"n32", no_argument
, NULL
, OPTION_N32
},
10876 #define OPTION_64 (OPTION_ELF_BASE + 6)
10877 {"64", no_argument
, NULL
, OPTION_64
},
10878 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10879 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10880 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10881 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10882 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10883 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10884 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10885 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10886 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10887 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10888 #endif /* OBJ_ELF */
10890 {NULL
, no_argument
, NULL
, 0}
10892 size_t md_longopts_size
= sizeof (md_longopts
);
10894 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10895 NEW_VALUE. Warn if another value was already specified. Note:
10896 we have to defer parsing the -march and -mtune arguments in order
10897 to handle 'from-abi' correctly, since the ABI might be specified
10898 in a later argument. */
10901 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10903 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10904 as_warn (_("A different %s was already specified, is now %s"),
10905 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10908 *string_ptr
= new_value
;
10912 md_parse_option (int c
, char *arg
)
10916 case OPTION_CONSTRUCT_FLOATS
:
10917 mips_disable_float_construction
= 0;
10920 case OPTION_NO_CONSTRUCT_FLOATS
:
10921 mips_disable_float_construction
= 1;
10933 target_big_endian
= 1;
10937 target_big_endian
= 0;
10941 if (arg
&& arg
[1] == '0')
10951 mips_debug
= atoi (arg
);
10952 /* When the MIPS assembler sees -g or -g2, it does not do
10953 optimizations which limit full symbolic debugging. We take
10954 that to be equivalent to -O0. */
10955 if (mips_debug
== 2)
10960 file_mips_isa
= ISA_MIPS1
;
10964 file_mips_isa
= ISA_MIPS2
;
10968 file_mips_isa
= ISA_MIPS3
;
10972 file_mips_isa
= ISA_MIPS4
;
10976 file_mips_isa
= ISA_MIPS5
;
10979 case OPTION_MIPS32
:
10980 file_mips_isa
= ISA_MIPS32
;
10983 case OPTION_MIPS32R2
:
10984 file_mips_isa
= ISA_MIPS32R2
;
10987 case OPTION_MIPS64R2
:
10988 file_mips_isa
= ISA_MIPS64R2
;
10991 case OPTION_MIPS64
:
10992 file_mips_isa
= ISA_MIPS64
;
10996 mips_set_option_string (&mips_tune_string
, arg
);
11000 mips_set_option_string (&mips_arch_string
, arg
);
11004 mips_set_option_string (&mips_arch_string
, "4650");
11005 mips_set_option_string (&mips_tune_string
, "4650");
11008 case OPTION_NO_M4650
:
11012 mips_set_option_string (&mips_arch_string
, "4010");
11013 mips_set_option_string (&mips_tune_string
, "4010");
11016 case OPTION_NO_M4010
:
11020 mips_set_option_string (&mips_arch_string
, "4100");
11021 mips_set_option_string (&mips_tune_string
, "4100");
11024 case OPTION_NO_M4100
:
11028 mips_set_option_string (&mips_arch_string
, "3900");
11029 mips_set_option_string (&mips_tune_string
, "3900");
11032 case OPTION_NO_M3900
:
11036 mips_opts
.ase_mdmx
= 1;
11039 case OPTION_NO_MDMX
:
11040 mips_opts
.ase_mdmx
= 0;
11044 mips_opts
.ase_dsp
= 1;
11047 case OPTION_NO_DSP
:
11048 mips_opts
.ase_dsp
= 0;
11052 mips_opts
.ase_mt
= 1;
11056 mips_opts
.ase_mt
= 0;
11059 case OPTION_MIPS16
:
11060 mips_opts
.mips16
= 1;
11061 mips_no_prev_insn ();
11064 case OPTION_NO_MIPS16
:
11065 mips_opts
.mips16
= 0;
11066 mips_no_prev_insn ();
11069 case OPTION_MIPS3D
:
11070 mips_opts
.ase_mips3d
= 1;
11073 case OPTION_NO_MIPS3D
:
11074 mips_opts
.ase_mips3d
= 0;
11077 case OPTION_SMARTMIPS
:
11078 mips_opts
.ase_smartmips
= 1;
11081 case OPTION_NO_SMARTMIPS
:
11082 mips_opts
.ase_smartmips
= 0;
11085 case OPTION_FIX_VR4120
:
11086 mips_fix_vr4120
= 1;
11089 case OPTION_NO_FIX_VR4120
:
11090 mips_fix_vr4120
= 0;
11093 case OPTION_FIX_VR4130
:
11094 mips_fix_vr4130
= 1;
11097 case OPTION_NO_FIX_VR4130
:
11098 mips_fix_vr4130
= 0;
11101 case OPTION_RELAX_BRANCH
:
11102 mips_relax_branch
= 1;
11105 case OPTION_NO_RELAX_BRANCH
:
11106 mips_relax_branch
= 0;
11109 case OPTION_MSHARED
:
11110 mips_in_shared
= TRUE
;
11113 case OPTION_MNO_SHARED
:
11114 mips_in_shared
= FALSE
;
11117 case OPTION_MSYM32
:
11118 mips_opts
.sym32
= TRUE
;
11121 case OPTION_MNO_SYM32
:
11122 mips_opts
.sym32
= FALSE
;
11126 /* When generating ELF code, we permit -KPIC and -call_shared to
11127 select SVR4_PIC, and -non_shared to select no PIC. This is
11128 intended to be compatible with Irix 5. */
11129 case OPTION_CALL_SHARED
:
11130 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11132 as_bad (_("-call_shared is supported only for ELF format"));
11135 mips_pic
= SVR4_PIC
;
11136 mips_abicalls
= TRUE
;
11139 case OPTION_NON_SHARED
:
11140 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11142 as_bad (_("-non_shared is supported only for ELF format"));
11146 mips_abicalls
= FALSE
;
11149 /* The -xgot option tells the assembler to use 32 bit offsets
11150 when accessing the got in SVR4_PIC mode. It is for Irix
11155 #endif /* OBJ_ELF */
11158 g_switch_value
= atoi (arg
);
11163 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11166 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11168 as_bad (_("-32 is supported for ELF format only"));
11171 mips_abi
= O32_ABI
;
11175 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11177 as_bad (_("-n32 is supported for ELF format only"));
11180 mips_abi
= N32_ABI
;
11184 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11186 as_bad (_("-64 is supported for ELF format only"));
11189 mips_abi
= N64_ABI
;
11190 if (! support_64bit_objects())
11191 as_fatal (_("No compiled in support for 64 bit object file format"));
11193 #endif /* OBJ_ELF */
11196 file_mips_gp32
= 1;
11200 file_mips_gp32
= 0;
11204 file_mips_fp32
= 1;
11208 file_mips_fp32
= 0;
11213 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11215 as_bad (_("-mabi is supported for ELF format only"));
11218 if (strcmp (arg
, "32") == 0)
11219 mips_abi
= O32_ABI
;
11220 else if (strcmp (arg
, "o64") == 0)
11221 mips_abi
= O64_ABI
;
11222 else if (strcmp (arg
, "n32") == 0)
11223 mips_abi
= N32_ABI
;
11224 else if (strcmp (arg
, "64") == 0)
11226 mips_abi
= N64_ABI
;
11227 if (! support_64bit_objects())
11228 as_fatal (_("No compiled in support for 64 bit object file "
11231 else if (strcmp (arg
, "eabi") == 0)
11232 mips_abi
= EABI_ABI
;
11235 as_fatal (_("invalid abi -mabi=%s"), arg
);
11239 #endif /* OBJ_ELF */
11241 case OPTION_M7000_HILO_FIX
:
11242 mips_7000_hilo_fix
= TRUE
;
11245 case OPTION_MNO_7000_HILO_FIX
:
11246 mips_7000_hilo_fix
= FALSE
;
11250 case OPTION_MDEBUG
:
11251 mips_flag_mdebug
= TRUE
;
11254 case OPTION_NO_MDEBUG
:
11255 mips_flag_mdebug
= FALSE
;
11259 mips_flag_pdr
= TRUE
;
11262 case OPTION_NO_PDR
:
11263 mips_flag_pdr
= FALSE
;
11266 case OPTION_MVXWORKS_PIC
:
11267 mips_pic
= VXWORKS_PIC
;
11269 #endif /* OBJ_ELF */
11278 /* Set up globals to generate code for the ISA or processor
11279 described by INFO. */
11282 mips_set_architecture (const struct mips_cpu_info
*info
)
11286 file_mips_arch
= info
->cpu
;
11287 mips_opts
.arch
= info
->cpu
;
11288 mips_opts
.isa
= info
->isa
;
11293 /* Likewise for tuning. */
11296 mips_set_tune (const struct mips_cpu_info
*info
)
11299 mips_tune
= info
->cpu
;
11304 mips_after_parse_args (void)
11306 const struct mips_cpu_info
*arch_info
= 0;
11307 const struct mips_cpu_info
*tune_info
= 0;
11309 /* GP relative stuff not working for PE */
11310 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11312 if (g_switch_seen
&& g_switch_value
!= 0)
11313 as_bad (_("-G not supported in this configuration."));
11314 g_switch_value
= 0;
11317 if (mips_abi
== NO_ABI
)
11318 mips_abi
= MIPS_DEFAULT_ABI
;
11320 /* The following code determines the architecture and register size.
11321 Similar code was added to GCC 3.3 (see override_options() in
11322 config/mips/mips.c). The GAS and GCC code should be kept in sync
11323 as much as possible. */
11325 if (mips_arch_string
!= 0)
11326 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11328 if (file_mips_isa
!= ISA_UNKNOWN
)
11330 /* Handle -mipsN. At this point, file_mips_isa contains the
11331 ISA level specified by -mipsN, while arch_info->isa contains
11332 the -march selection (if any). */
11333 if (arch_info
!= 0)
11335 /* -march takes precedence over -mipsN, since it is more descriptive.
11336 There's no harm in specifying both as long as the ISA levels
11338 if (file_mips_isa
!= arch_info
->isa
)
11339 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11340 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11341 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11344 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11347 if (arch_info
== 0)
11348 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11350 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11351 as_bad ("-march=%s is not compatible with the selected ABI",
11354 mips_set_architecture (arch_info
);
11356 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11357 if (mips_tune_string
!= 0)
11358 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11360 if (tune_info
== 0)
11361 mips_set_tune (arch_info
);
11363 mips_set_tune (tune_info
);
11365 if (file_mips_gp32
>= 0)
11367 /* The user specified the size of the integer registers. Make sure
11368 it agrees with the ABI and ISA. */
11369 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11370 as_bad (_("-mgp64 used with a 32-bit processor"));
11371 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11372 as_bad (_("-mgp32 used with a 64-bit ABI"));
11373 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11374 as_bad (_("-mgp64 used with a 32-bit ABI"));
11378 /* Infer the integer register size from the ABI and processor.
11379 Restrict ourselves to 32-bit registers if that's all the
11380 processor has, or if the ABI cannot handle 64-bit registers. */
11381 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11382 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11385 switch (file_mips_fp32
)
11389 /* No user specified float register size.
11390 ??? GAS treats single-float processors as though they had 64-bit
11391 float registers (although it complains when double-precision
11392 instructions are used). As things stand, saying they have 32-bit
11393 registers would lead to spurious "register must be even" messages.
11394 So here we assume float registers are never smaller than the
11396 if (file_mips_gp32
== 0)
11397 /* 64-bit integer registers implies 64-bit float registers. */
11398 file_mips_fp32
= 0;
11399 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11400 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11401 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11402 file_mips_fp32
= 0;
11404 /* 32-bit float registers. */
11405 file_mips_fp32
= 1;
11408 /* The user specified the size of the float registers. Check if it
11409 agrees with the ABI and ISA. */
11411 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11412 as_bad (_("-mfp64 used with a 32-bit fpu"));
11413 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11414 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11415 as_warn (_("-mfp64 used with a 32-bit ABI"));
11418 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11419 as_warn (_("-mfp32 used with a 64-bit ABI"));
11423 /* End of GCC-shared inference code. */
11425 /* This flag is set when we have a 64-bit capable CPU but use only
11426 32-bit wide registers. Note that EABI does not use it. */
11427 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11428 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11429 || mips_abi
== O32_ABI
))
11430 mips_32bitmode
= 1;
11432 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11433 as_bad (_("trap exception not supported at ISA 1"));
11435 /* If the selected architecture includes support for ASEs, enable
11436 generation of code for them. */
11437 if (mips_opts
.mips16
== -1)
11438 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11439 if (mips_opts
.ase_mips3d
== -1)
11440 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11441 && file_mips_fp32
== 0) ? 1 : 0;
11442 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11443 as_bad (_("-mfp32 used with -mips3d"));
11445 if (mips_opts
.ase_mdmx
== -1)
11446 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11447 && file_mips_fp32
== 0) ? 1 : 0;
11448 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11449 as_bad (_("-mfp32 used with -mdmx"));
11451 if (mips_opts
.ase_smartmips
== -1)
11452 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11453 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11454 as_warn ("%s ISA does not support SmartMIPS",
11455 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11457 if (mips_opts
.ase_dsp
== -1)
11458 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11459 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11460 as_warn ("%s ISA does not support DSP ASE",
11461 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11463 if (mips_opts
.ase_mt
== -1)
11464 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11465 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11466 as_warn ("%s ISA does not support MT ASE",
11467 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11469 file_mips_isa
= mips_opts
.isa
;
11470 file_ase_mips16
= mips_opts
.mips16
;
11471 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11472 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11473 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11474 file_ase_dsp
= mips_opts
.ase_dsp
;
11475 file_ase_mt
= mips_opts
.ase_mt
;
11476 mips_opts
.gp32
= file_mips_gp32
;
11477 mips_opts
.fp32
= file_mips_fp32
;
11479 if (mips_flag_mdebug
< 0)
11481 #ifdef OBJ_MAYBE_ECOFF
11482 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11483 mips_flag_mdebug
= 1;
11485 #endif /* OBJ_MAYBE_ECOFF */
11486 mips_flag_mdebug
= 0;
11491 mips_init_after_args (void)
11493 /* initialize opcodes */
11494 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11495 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11499 md_pcrel_from (fixS
*fixP
)
11501 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11502 switch (fixP
->fx_r_type
)
11504 case BFD_RELOC_16_PCREL_S2
:
11505 case BFD_RELOC_MIPS_JMP
:
11506 /* Return the address of the delay slot. */
11513 /* This is called before the symbol table is processed. In order to
11514 work with gcc when using mips-tfile, we must keep all local labels.
11515 However, in other cases, we want to discard them. If we were
11516 called with -g, but we didn't see any debugging information, it may
11517 mean that gcc is smuggling debugging information through to
11518 mips-tfile, in which case we must generate all local labels. */
11521 mips_frob_file_before_adjust (void)
11523 #ifndef NO_ECOFF_DEBUGGING
11524 if (ECOFF_DEBUGGING
11526 && ! ecoff_debugging_seen
)
11527 flag_keep_locals
= 1;
11531 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11532 the corresponding LO16 reloc. This is called before md_apply_fix and
11533 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11534 relocation operators.
11536 For our purposes, a %lo() expression matches a %got() or %hi()
11539 (a) it refers to the same symbol; and
11540 (b) the offset applied in the %lo() expression is no lower than
11541 the offset applied in the %got() or %hi().
11543 (b) allows us to cope with code like:
11546 lh $4,%lo(foo+2)($4)
11548 ...which is legal on RELA targets, and has a well-defined behaviour
11549 if the user knows that adding 2 to "foo" will not induce a carry to
11552 When several %lo()s match a particular %got() or %hi(), we use the
11553 following rules to distinguish them:
11555 (1) %lo()s with smaller offsets are a better match than %lo()s with
11558 (2) %lo()s with no matching %got() or %hi() are better than those
11559 that already have a matching %got() or %hi().
11561 (3) later %lo()s are better than earlier %lo()s.
11563 These rules are applied in order.
11565 (1) means, among other things, that %lo()s with identical offsets are
11566 chosen if they exist.
11568 (2) means that we won't associate several high-part relocations with
11569 the same low-part relocation unless there's no alternative. Having
11570 several high parts for the same low part is a GNU extension; this rule
11571 allows careful users to avoid it.
11573 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11574 with the last high-part relocation being at the front of the list.
11575 It therefore makes sense to choose the last matching low-part
11576 relocation, all other things being equal. It's also easier
11577 to code that way. */
11580 mips_frob_file (void)
11582 struct mips_hi_fixup
*l
;
11584 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11586 segment_info_type
*seginfo
;
11587 bfd_boolean matched_lo_p
;
11588 fixS
**hi_pos
, **lo_pos
, **pos
;
11590 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11592 /* If a GOT16 relocation turns out to be against a global symbol,
11593 there isn't supposed to be a matching LO. */
11594 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11595 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11598 /* Check quickly whether the next fixup happens to be a matching %lo. */
11599 if (fixup_has_matching_lo_p (l
->fixp
))
11602 seginfo
= seg_info (l
->seg
);
11604 /* Set HI_POS to the position of this relocation in the chain.
11605 Set LO_POS to the position of the chosen low-part relocation.
11606 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11607 relocation that matches an immediately-preceding high-part
11611 matched_lo_p
= FALSE
;
11612 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11614 if (*pos
== l
->fixp
)
11617 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11618 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11619 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11620 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11622 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11624 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11627 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11628 && fixup_has_matching_lo_p (*pos
));
11631 /* If we found a match, remove the high-part relocation from its
11632 current position and insert it before the low-part relocation.
11633 Make the offsets match so that fixup_has_matching_lo_p()
11636 We don't warn about unmatched high-part relocations since some
11637 versions of gcc have been known to emit dead "lui ...%hi(...)"
11639 if (lo_pos
!= NULL
)
11641 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11642 if (l
->fixp
->fx_next
!= *lo_pos
)
11644 *hi_pos
= l
->fixp
->fx_next
;
11645 l
->fixp
->fx_next
= *lo_pos
;
11652 /* We may have combined relocations without symbols in the N32/N64 ABI.
11653 We have to prevent gas from dropping them. */
11656 mips_force_relocation (fixS
*fixp
)
11658 if (generic_force_reloc (fixp
))
11662 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11663 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11664 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11665 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11671 /* Apply a fixup to the object file. */
11674 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11678 reloc_howto_type
*howto
;
11680 /* We ignore generic BFD relocations we don't know about. */
11681 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11685 assert (fixP
->fx_size
== 4
11686 || fixP
->fx_r_type
== BFD_RELOC_16
11687 || fixP
->fx_r_type
== BFD_RELOC_64
11688 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11689 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11690 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11691 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11693 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11695 assert (! fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11697 /* Don't treat parts of a composite relocation as done. There are two
11700 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11701 should nevertheless be emitted if the first part is.
11703 (2) In normal usage, composite relocations are never assembly-time
11704 constants. The easiest way of dealing with the pathological
11705 exceptions is to generate a relocation against STN_UNDEF and
11706 leave everything up to the linker. */
11707 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11710 switch (fixP
->fx_r_type
)
11712 case BFD_RELOC_MIPS_TLS_GD
:
11713 case BFD_RELOC_MIPS_TLS_LDM
:
11714 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11715 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11716 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11717 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11718 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11719 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11722 case BFD_RELOC_MIPS_JMP
:
11723 case BFD_RELOC_MIPS_SHIFT5
:
11724 case BFD_RELOC_MIPS_SHIFT6
:
11725 case BFD_RELOC_MIPS_GOT_DISP
:
11726 case BFD_RELOC_MIPS_GOT_PAGE
:
11727 case BFD_RELOC_MIPS_GOT_OFST
:
11728 case BFD_RELOC_MIPS_SUB
:
11729 case BFD_RELOC_MIPS_INSERT_A
:
11730 case BFD_RELOC_MIPS_INSERT_B
:
11731 case BFD_RELOC_MIPS_DELETE
:
11732 case BFD_RELOC_MIPS_HIGHEST
:
11733 case BFD_RELOC_MIPS_HIGHER
:
11734 case BFD_RELOC_MIPS_SCN_DISP
:
11735 case BFD_RELOC_MIPS_REL16
:
11736 case BFD_RELOC_MIPS_RELGOT
:
11737 case BFD_RELOC_MIPS_JALR
:
11738 case BFD_RELOC_HI16
:
11739 case BFD_RELOC_HI16_S
:
11740 case BFD_RELOC_GPREL16
:
11741 case BFD_RELOC_MIPS_LITERAL
:
11742 case BFD_RELOC_MIPS_CALL16
:
11743 case BFD_RELOC_MIPS_GOT16
:
11744 case BFD_RELOC_GPREL32
:
11745 case BFD_RELOC_MIPS_GOT_HI16
:
11746 case BFD_RELOC_MIPS_GOT_LO16
:
11747 case BFD_RELOC_MIPS_CALL_HI16
:
11748 case BFD_RELOC_MIPS_CALL_LO16
:
11749 case BFD_RELOC_MIPS16_GPREL
:
11750 case BFD_RELOC_MIPS16_HI16
:
11751 case BFD_RELOC_MIPS16_HI16_S
:
11752 /* Nothing needed to do. The value comes from the reloc entry */
11755 case BFD_RELOC_MIPS16_JMP
:
11756 /* We currently always generate a reloc against a symbol, which
11757 means that we don't want an addend even if the symbol is
11763 /* This is handled like BFD_RELOC_32, but we output a sign
11764 extended value if we are only 32 bits. */
11767 if (8 <= sizeof (valueT
))
11768 md_number_to_chars ((char *) buf
, *valP
, 8);
11773 if ((*valP
& 0x80000000) != 0)
11777 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11779 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11785 case BFD_RELOC_RVA
:
11787 /* If we are deleting this reloc entry, we must fill in the
11788 value now. This can happen if we have a .word which is not
11789 resolved when it appears but is later defined. */
11791 md_number_to_chars ((char *) buf
, *valP
, 4);
11795 /* If we are deleting this reloc entry, we must fill in the
11798 md_number_to_chars ((char *) buf
, *valP
, 2);
11801 case BFD_RELOC_LO16
:
11802 case BFD_RELOC_MIPS16_LO16
:
11803 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11804 may be safe to remove, but if so it's not obvious. */
11805 /* When handling an embedded PIC switch statement, we can wind
11806 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11809 if (*valP
+ 0x8000 > 0xffff)
11810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11811 _("relocation overflow"));
11812 if (target_big_endian
)
11814 md_number_to_chars ((char *) buf
, *valP
, 2);
11818 case BFD_RELOC_16_PCREL_S2
:
11819 if ((*valP
& 0x3) != 0)
11820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11821 _("Branch to misaligned address (%lx)"), (long) *valP
);
11824 * We need to save the bits in the instruction since fixup_segment()
11825 * might be deleting the relocation entry (i.e., a branch within
11826 * the current segment).
11828 if (! fixP
->fx_done
)
11831 /* update old instruction data */
11832 if (target_big_endian
)
11833 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11835 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11837 if (*valP
+ 0x20000 <= 0x3ffff)
11839 insn
|= (*valP
>> 2) & 0xffff;
11840 md_number_to_chars ((char *) buf
, insn
, 4);
11842 else if (mips_pic
== NO_PIC
11844 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11845 && (fixP
->fx_frag
->fr_address
11846 < text_section
->vma
+ bfd_get_section_size (text_section
))
11847 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11848 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11849 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11851 /* The branch offset is too large. If this is an
11852 unconditional branch, and we are not generating PIC code,
11853 we can convert it to an absolute jump instruction. */
11854 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11855 insn
= 0x0c000000; /* jal */
11857 insn
= 0x08000000; /* j */
11858 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11860 fixP
->fx_addsy
= section_symbol (text_section
);
11861 *valP
+= md_pcrel_from (fixP
);
11862 md_number_to_chars ((char *) buf
, insn
, 4);
11866 /* If we got here, we have branch-relaxation disabled,
11867 and there's nothing we can do to fix this instruction
11868 without turning it into a longer sequence. */
11869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11870 _("Branch out of range"));
11874 case BFD_RELOC_VTABLE_INHERIT
:
11877 && !S_IS_DEFINED (fixP
->fx_addsy
)
11878 && !S_IS_WEAK (fixP
->fx_addsy
))
11879 S_SET_WEAK (fixP
->fx_addsy
);
11882 case BFD_RELOC_VTABLE_ENTRY
:
11890 /* Remember value for tc_gen_reloc. */
11891 fixP
->fx_addnumber
= *valP
;
11901 name
= input_line_pointer
;
11902 c
= get_symbol_end ();
11903 p
= (symbolS
*) symbol_find_or_make (name
);
11904 *input_line_pointer
= c
;
11908 /* Align the current frag to a given power of two. The MIPS assembler
11909 also automatically adjusts any preceding label. */
11912 mips_align (int to
, int fill
, symbolS
*label
)
11914 mips_emit_delays ();
11915 frag_align (to
, fill
, 0);
11916 record_alignment (now_seg
, to
);
11919 assert (S_GET_SEGMENT (label
) == now_seg
);
11920 symbol_set_frag (label
, frag_now
);
11921 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11925 /* Align to a given power of two. .align 0 turns off the automatic
11926 alignment used by the data creating pseudo-ops. */
11929 s_align (int x ATTRIBUTE_UNUSED
)
11932 register long temp_fill
;
11933 long max_alignment
= 15;
11937 o Note that the assembler pulls down any immediately preceding label
11938 to the aligned address.
11939 o It's not documented but auto alignment is reinstated by
11940 a .align pseudo instruction.
11941 o Note also that after auto alignment is turned off the mips assembler
11942 issues an error on attempt to assemble an improperly aligned data item.
11947 temp
= get_absolute_expression ();
11948 if (temp
> max_alignment
)
11949 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11952 as_warn (_("Alignment negative: 0 assumed."));
11955 if (*input_line_pointer
== ',')
11957 ++input_line_pointer
;
11958 temp_fill
= get_absolute_expression ();
11965 mips_align (temp
, (int) temp_fill
,
11966 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11973 demand_empty_rest_of_line ();
11977 s_change_sec (int sec
)
11982 /* The ELF backend needs to know that we are changing sections, so
11983 that .previous works correctly. We could do something like check
11984 for an obj_section_change_hook macro, but that might be confusing
11985 as it would not be appropriate to use it in the section changing
11986 functions in read.c, since obj-elf.c intercepts those. FIXME:
11987 This should be cleaner, somehow. */
11988 obj_elf_section_change_hook ();
11991 mips_emit_delays ();
12001 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12002 demand_empty_rest_of_line ();
12006 seg
= subseg_new (RDATA_SECTION_NAME
,
12007 (subsegT
) get_absolute_expression ());
12008 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12010 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12011 | SEC_READONLY
| SEC_RELOC
12013 if (strcmp (TARGET_OS
, "elf") != 0)
12014 record_alignment (seg
, 4);
12016 demand_empty_rest_of_line ();
12020 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12021 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12023 bfd_set_section_flags (stdoutput
, seg
,
12024 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12025 if (strcmp (TARGET_OS
, "elf") != 0)
12026 record_alignment (seg
, 4);
12028 demand_empty_rest_of_line ();
12036 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12039 char *section_name
;
12044 int section_entry_size
;
12045 int section_alignment
;
12047 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12050 section_name
= input_line_pointer
;
12051 c
= get_symbol_end ();
12053 next_c
= *(input_line_pointer
+ 1);
12055 /* Do we have .section Name<,"flags">? */
12056 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12058 /* just after name is now '\0'. */
12059 *input_line_pointer
= c
;
12060 input_line_pointer
= section_name
;
12061 obj_elf_section (ignore
);
12064 input_line_pointer
++;
12066 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12068 section_type
= get_absolute_expression ();
12071 if (*input_line_pointer
++ == ',')
12072 section_flag
= get_absolute_expression ();
12075 if (*input_line_pointer
++ == ',')
12076 section_entry_size
= get_absolute_expression ();
12078 section_entry_size
= 0;
12079 if (*input_line_pointer
++ == ',')
12080 section_alignment
= get_absolute_expression ();
12082 section_alignment
= 0;
12084 section_name
= xstrdup (section_name
);
12086 /* When using the generic form of .section (as implemented by obj-elf.c),
12087 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12088 traditionally had to fall back on the more common @progbits instead.
12090 There's nothing really harmful in this, since bfd will correct
12091 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12092 means that, for backwards compatibility, the special_section entries
12093 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12095 Even so, we shouldn't force users of the MIPS .section syntax to
12096 incorrectly label the sections as SHT_PROGBITS. The best compromise
12097 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12098 generic type-checking code. */
12099 if (section_type
== SHT_MIPS_DWARF
)
12100 section_type
= SHT_PROGBITS
;
12102 obj_elf_change_section (section_name
, section_type
, section_flag
,
12103 section_entry_size
, 0, 0, 0);
12105 if (now_seg
->name
!= section_name
)
12106 free (section_name
);
12107 #endif /* OBJ_ELF */
12111 mips_enable_auto_align (void)
12117 s_cons (int log_size
)
12121 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12122 mips_emit_delays ();
12123 if (log_size
> 0 && auto_align
)
12124 mips_align (log_size
, 0, label
);
12125 mips_clear_insn_labels ();
12126 cons (1 << log_size
);
12130 s_float_cons (int type
)
12134 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12136 mips_emit_delays ();
12141 mips_align (3, 0, label
);
12143 mips_align (2, 0, label
);
12146 mips_clear_insn_labels ();
12151 /* Handle .globl. We need to override it because on Irix 5 you are
12154 where foo is an undefined symbol, to mean that foo should be
12155 considered to be the address of a function. */
12158 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12167 name
= input_line_pointer
;
12168 c
= get_symbol_end ();
12169 symbolP
= symbol_find_or_make (name
);
12170 S_SET_EXTERNAL (symbolP
);
12172 *input_line_pointer
= c
;
12173 SKIP_WHITESPACE ();
12175 /* On Irix 5, every global symbol that is not explicitly labelled as
12176 being a function is apparently labelled as being an object. */
12179 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12180 && (*input_line_pointer
!= ','))
12185 secname
= input_line_pointer
;
12186 c
= get_symbol_end ();
12187 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12189 as_bad (_("%s: no such section"), secname
);
12190 *input_line_pointer
= c
;
12192 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12193 flag
= BSF_FUNCTION
;
12196 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12198 c
= *input_line_pointer
;
12201 input_line_pointer
++;
12202 SKIP_WHITESPACE ();
12203 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12209 demand_empty_rest_of_line ();
12213 s_option (int x ATTRIBUTE_UNUSED
)
12218 opt
= input_line_pointer
;
12219 c
= get_symbol_end ();
12223 /* FIXME: What does this mean? */
12225 else if (strncmp (opt
, "pic", 3) == 0)
12229 i
= atoi (opt
+ 3);
12234 mips_pic
= SVR4_PIC
;
12235 mips_abicalls
= TRUE
;
12238 as_bad (_(".option pic%d not supported"), i
);
12240 if (mips_pic
== SVR4_PIC
)
12242 if (g_switch_seen
&& g_switch_value
!= 0)
12243 as_warn (_("-G may not be used with SVR4 PIC code"));
12244 g_switch_value
= 0;
12245 bfd_set_gp_size (stdoutput
, 0);
12249 as_warn (_("Unrecognized option \"%s\""), opt
);
12251 *input_line_pointer
= c
;
12252 demand_empty_rest_of_line ();
12255 /* This structure is used to hold a stack of .set values. */
12257 struct mips_option_stack
12259 struct mips_option_stack
*next
;
12260 struct mips_set_options options
;
12263 static struct mips_option_stack
*mips_opts_stack
;
12265 /* Handle the .set pseudo-op. */
12268 s_mipsset (int x ATTRIBUTE_UNUSED
)
12270 char *name
= input_line_pointer
, ch
;
12272 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12273 ++input_line_pointer
;
12274 ch
= *input_line_pointer
;
12275 *input_line_pointer
= '\0';
12277 if (strcmp (name
, "reorder") == 0)
12279 if (mips_opts
.noreorder
)
12282 else if (strcmp (name
, "noreorder") == 0)
12284 if (!mips_opts
.noreorder
)
12285 start_noreorder ();
12287 else if (strcmp (name
, "at") == 0)
12289 mips_opts
.noat
= 0;
12291 else if (strcmp (name
, "noat") == 0)
12293 mips_opts
.noat
= 1;
12295 else if (strcmp (name
, "macro") == 0)
12297 mips_opts
.warn_about_macros
= 0;
12299 else if (strcmp (name
, "nomacro") == 0)
12301 if (mips_opts
.noreorder
== 0)
12302 as_bad (_("`noreorder' must be set before `nomacro'"));
12303 mips_opts
.warn_about_macros
= 1;
12305 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12307 mips_opts
.nomove
= 0;
12309 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12311 mips_opts
.nomove
= 1;
12313 else if (strcmp (name
, "bopt") == 0)
12315 mips_opts
.nobopt
= 0;
12317 else if (strcmp (name
, "nobopt") == 0)
12319 mips_opts
.nobopt
= 1;
12321 else if (strcmp (name
, "gp=default") == 0)
12322 mips_opts
.gp32
= file_mips_gp32
;
12323 else if (strcmp (name
, "gp=32") == 0)
12324 mips_opts
.gp32
= 1;
12325 else if (strcmp (name
, "gp=64") == 0)
12327 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12328 as_warn ("%s isa does not support 64-bit registers",
12329 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12330 mips_opts
.gp32
= 0;
12332 else if (strcmp (name
, "fp=default") == 0)
12333 mips_opts
.fp32
= file_mips_fp32
;
12334 else if (strcmp (name
, "fp=32") == 0)
12335 mips_opts
.fp32
= 1;
12336 else if (strcmp (name
, "fp=64") == 0)
12338 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12339 as_warn ("%s isa does not support 64-bit floating point registers",
12340 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12341 mips_opts
.fp32
= 0;
12343 else if (strcmp (name
, "mips16") == 0
12344 || strcmp (name
, "MIPS-16") == 0)
12345 mips_opts
.mips16
= 1;
12346 else if (strcmp (name
, "nomips16") == 0
12347 || strcmp (name
, "noMIPS-16") == 0)
12348 mips_opts
.mips16
= 0;
12349 else if (strcmp (name
, "smartmips") == 0)
12351 if (!ISA_SUPPORTS_SMARTMIPS
)
12352 as_warn ("%s ISA does not support SmartMIPS ASE",
12353 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12354 mips_opts
.ase_smartmips
= 1;
12356 else if (strcmp (name
, "nosmartmips") == 0)
12357 mips_opts
.ase_smartmips
= 0;
12358 else if (strcmp (name
, "mips3d") == 0)
12359 mips_opts
.ase_mips3d
= 1;
12360 else if (strcmp (name
, "nomips3d") == 0)
12361 mips_opts
.ase_mips3d
= 0;
12362 else if (strcmp (name
, "mdmx") == 0)
12363 mips_opts
.ase_mdmx
= 1;
12364 else if (strcmp (name
, "nomdmx") == 0)
12365 mips_opts
.ase_mdmx
= 0;
12366 else if (strcmp (name
, "dsp") == 0)
12368 if (!ISA_SUPPORTS_DSP_ASE
)
12369 as_warn ("%s ISA does not support DSP ASE",
12370 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12371 mips_opts
.ase_dsp
= 1;
12373 else if (strcmp (name
, "nodsp") == 0)
12374 mips_opts
.ase_dsp
= 0;
12375 else if (strcmp (name
, "mt") == 0)
12377 if (!ISA_SUPPORTS_MT_ASE
)
12378 as_warn ("%s ISA does not support MT ASE",
12379 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12380 mips_opts
.ase_mt
= 1;
12382 else if (strcmp (name
, "nomt") == 0)
12383 mips_opts
.ase_mt
= 0;
12384 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12388 /* Permit the user to change the ISA and architecture on the fly.
12389 Needless to say, misuse can cause serious problems. */
12390 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12393 mips_opts
.isa
= file_mips_isa
;
12394 mips_opts
.arch
= file_mips_arch
;
12396 else if (strncmp (name
, "arch=", 5) == 0)
12398 const struct mips_cpu_info
*p
;
12400 p
= mips_parse_cpu("internal use", name
+ 5);
12402 as_bad (_("unknown architecture %s"), name
+ 5);
12405 mips_opts
.arch
= p
->cpu
;
12406 mips_opts
.isa
= p
->isa
;
12409 else if (strncmp (name
, "mips", 4) == 0)
12411 const struct mips_cpu_info
*p
;
12413 p
= mips_parse_cpu("internal use", name
);
12415 as_bad (_("unknown ISA level %s"), name
+ 4);
12418 mips_opts
.arch
= p
->cpu
;
12419 mips_opts
.isa
= p
->isa
;
12423 as_bad (_("unknown ISA or architecture %s"), name
);
12425 switch (mips_opts
.isa
)
12433 mips_opts
.gp32
= 1;
12434 mips_opts
.fp32
= 1;
12441 mips_opts
.gp32
= 0;
12442 mips_opts
.fp32
= 0;
12445 as_bad (_("unknown ISA level %s"), name
+ 4);
12450 mips_opts
.gp32
= file_mips_gp32
;
12451 mips_opts
.fp32
= file_mips_fp32
;
12454 else if (strcmp (name
, "autoextend") == 0)
12455 mips_opts
.noautoextend
= 0;
12456 else if (strcmp (name
, "noautoextend") == 0)
12457 mips_opts
.noautoextend
= 1;
12458 else if (strcmp (name
, "push") == 0)
12460 struct mips_option_stack
*s
;
12462 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12463 s
->next
= mips_opts_stack
;
12464 s
->options
= mips_opts
;
12465 mips_opts_stack
= s
;
12467 else if (strcmp (name
, "pop") == 0)
12469 struct mips_option_stack
*s
;
12471 s
= mips_opts_stack
;
12473 as_bad (_(".set pop with no .set push"));
12476 /* If we're changing the reorder mode we need to handle
12477 delay slots correctly. */
12478 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12479 start_noreorder ();
12480 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12483 mips_opts
= s
->options
;
12484 mips_opts_stack
= s
->next
;
12488 else if (strcmp (name
, "sym32") == 0)
12489 mips_opts
.sym32
= TRUE
;
12490 else if (strcmp (name
, "nosym32") == 0)
12491 mips_opts
.sym32
= FALSE
;
12494 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12496 *input_line_pointer
= ch
;
12497 demand_empty_rest_of_line ();
12500 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12501 .option pic2. It means to generate SVR4 PIC calls. */
12504 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12506 mips_pic
= SVR4_PIC
;
12507 mips_abicalls
= TRUE
;
12509 if (g_switch_seen
&& g_switch_value
!= 0)
12510 as_warn (_("-G may not be used with SVR4 PIC code"));
12511 g_switch_value
= 0;
12513 bfd_set_gp_size (stdoutput
, 0);
12514 demand_empty_rest_of_line ();
12517 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12518 PIC code. It sets the $gp register for the function based on the
12519 function address, which is in the register named in the argument.
12520 This uses a relocation against _gp_disp, which is handled specially
12521 by the linker. The result is:
12522 lui $gp,%hi(_gp_disp)
12523 addiu $gp,$gp,%lo(_gp_disp)
12524 addu $gp,$gp,.cpload argument
12525 The .cpload argument is normally $25 == $t9.
12527 The -mno-shared option changes this to:
12528 lui $gp,%hi(__gnu_local_gp)
12529 addiu $gp,$gp,%lo(__gnu_local_gp)
12530 and the argument is ignored. This saves an instruction, but the
12531 resulting code is not position independent; it uses an absolute
12532 address for __gnu_local_gp. Thus code assembled with -mno-shared
12533 can go into an ordinary executable, but not into a shared library. */
12536 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12542 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12543 .cpload is ignored. */
12544 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12550 /* .cpload should be in a .set noreorder section. */
12551 if (mips_opts
.noreorder
== 0)
12552 as_warn (_(".cpload not in noreorder section"));
12554 reg
= tc_get_register (0);
12556 /* If we need to produce a 64-bit address, we are better off using
12557 the default instruction sequence. */
12558 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12560 ex
.X_op
= O_symbol
;
12561 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12563 ex
.X_op_symbol
= NULL
;
12564 ex
.X_add_number
= 0;
12566 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12567 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12570 macro_build_lui (&ex
, mips_gp_register
);
12571 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12572 mips_gp_register
, BFD_RELOC_LO16
);
12574 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12575 mips_gp_register
, reg
);
12578 demand_empty_rest_of_line ();
12581 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12582 .cpsetup $reg1, offset|$reg2, label
12584 If offset is given, this results in:
12585 sd $gp, offset($sp)
12586 lui $gp, %hi(%neg(%gp_rel(label)))
12587 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12588 daddu $gp, $gp, $reg1
12590 If $reg2 is given, this results in:
12591 daddu $reg2, $gp, $0
12592 lui $gp, %hi(%neg(%gp_rel(label)))
12593 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12594 daddu $gp, $gp, $reg1
12595 $reg1 is normally $25 == $t9.
12597 The -mno-shared option replaces the last three instructions with
12599 addiu $gp,$gp,%lo(_gp)
12603 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12605 expressionS ex_off
;
12606 expressionS ex_sym
;
12609 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12610 We also need NewABI support. */
12611 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12617 reg1
= tc_get_register (0);
12618 SKIP_WHITESPACE ();
12619 if (*input_line_pointer
!= ',')
12621 as_bad (_("missing argument separator ',' for .cpsetup"));
12625 ++input_line_pointer
;
12626 SKIP_WHITESPACE ();
12627 if (*input_line_pointer
== '$')
12629 mips_cpreturn_register
= tc_get_register (0);
12630 mips_cpreturn_offset
= -1;
12634 mips_cpreturn_offset
= get_absolute_expression ();
12635 mips_cpreturn_register
= -1;
12637 SKIP_WHITESPACE ();
12638 if (*input_line_pointer
!= ',')
12640 as_bad (_("missing argument separator ',' for .cpsetup"));
12644 ++input_line_pointer
;
12645 SKIP_WHITESPACE ();
12646 expression (&ex_sym
);
12649 if (mips_cpreturn_register
== -1)
12651 ex_off
.X_op
= O_constant
;
12652 ex_off
.X_add_symbol
= NULL
;
12653 ex_off
.X_op_symbol
= NULL
;
12654 ex_off
.X_add_number
= mips_cpreturn_offset
;
12656 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12657 BFD_RELOC_LO16
, SP
);
12660 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12661 mips_gp_register
, 0);
12663 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12665 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12666 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12669 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12670 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12671 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12673 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12674 mips_gp_register
, reg1
);
12680 ex
.X_op
= O_symbol
;
12681 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12682 ex
.X_op_symbol
= NULL
;
12683 ex
.X_add_number
= 0;
12685 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12686 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12688 macro_build_lui (&ex
, mips_gp_register
);
12689 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12690 mips_gp_register
, BFD_RELOC_LO16
);
12695 demand_empty_rest_of_line ();
12699 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12701 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12702 .cplocal is ignored. */
12703 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12709 mips_gp_register
= tc_get_register (0);
12710 demand_empty_rest_of_line ();
12713 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12714 offset from $sp. The offset is remembered, and after making a PIC
12715 call $gp is restored from that location. */
12718 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12722 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12723 .cprestore is ignored. */
12724 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12730 mips_cprestore_offset
= get_absolute_expression ();
12731 mips_cprestore_valid
= 1;
12733 ex
.X_op
= O_constant
;
12734 ex
.X_add_symbol
= NULL
;
12735 ex
.X_op_symbol
= NULL
;
12736 ex
.X_add_number
= mips_cprestore_offset
;
12739 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12740 SP
, HAVE_64BIT_ADDRESSES
);
12743 demand_empty_rest_of_line ();
12746 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12747 was given in the preceding .cpsetup, it results in:
12748 ld $gp, offset($sp)
12750 If a register $reg2 was given there, it results in:
12751 daddu $gp, $reg2, $0
12754 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12758 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12759 We also need NewABI support. */
12760 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12767 if (mips_cpreturn_register
== -1)
12769 ex
.X_op
= O_constant
;
12770 ex
.X_add_symbol
= NULL
;
12771 ex
.X_op_symbol
= NULL
;
12772 ex
.X_add_number
= mips_cpreturn_offset
;
12774 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12777 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12778 mips_cpreturn_register
, 0);
12781 demand_empty_rest_of_line ();
12784 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12785 code. It sets the offset to use in gp_rel relocations. */
12788 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12790 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12791 We also need NewABI support. */
12792 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12798 mips_gprel_offset
= get_absolute_expression ();
12800 demand_empty_rest_of_line ();
12803 /* Handle the .gpword pseudo-op. This is used when generating PIC
12804 code. It generates a 32 bit GP relative reloc. */
12807 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12813 /* When not generating PIC code, this is treated as .word. */
12814 if (mips_pic
!= SVR4_PIC
)
12820 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12821 mips_emit_delays ();
12823 mips_align (2, 0, label
);
12824 mips_clear_insn_labels ();
12828 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12830 as_bad (_("Unsupported use of .gpword"));
12831 ignore_rest_of_line ();
12835 md_number_to_chars (p
, 0, 4);
12836 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12837 BFD_RELOC_GPREL32
);
12839 demand_empty_rest_of_line ();
12843 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12849 /* When not generating PIC code, this is treated as .dword. */
12850 if (mips_pic
!= SVR4_PIC
)
12856 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12857 mips_emit_delays ();
12859 mips_align (3, 0, label
);
12860 mips_clear_insn_labels ();
12864 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12866 as_bad (_("Unsupported use of .gpdword"));
12867 ignore_rest_of_line ();
12871 md_number_to_chars (p
, 0, 8);
12872 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12873 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12875 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12876 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12877 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12879 demand_empty_rest_of_line ();
12882 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12883 tables in SVR4 PIC code. */
12886 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12890 /* This is ignored when not generating SVR4 PIC code. */
12891 if (mips_pic
!= SVR4_PIC
)
12897 /* Add $gp to the register named as an argument. */
12899 reg
= tc_get_register (0);
12900 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12903 demand_empty_rest_of_line ();
12906 /* Handle the .insn pseudo-op. This marks instruction labels in
12907 mips16 mode. This permits the linker to handle them specially,
12908 such as generating jalx instructions when needed. We also make
12909 them odd for the duration of the assembly, in order to generate the
12910 right sort of code. We will make them even in the adjust_symtab
12911 routine, while leaving them marked. This is convenient for the
12912 debugger and the disassembler. The linker knows to make them odd
12916 s_insn (int ignore ATTRIBUTE_UNUSED
)
12918 mips16_mark_labels ();
12920 demand_empty_rest_of_line ();
12923 /* Handle a .stabn directive. We need these in order to mark a label
12924 as being a mips16 text label correctly. Sometimes the compiler
12925 will emit a label, followed by a .stabn, and then switch sections.
12926 If the label and .stabn are in mips16 mode, then the label is
12927 really a mips16 text label. */
12930 s_mips_stab (int type
)
12933 mips16_mark_labels ();
12938 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12942 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12949 name
= input_line_pointer
;
12950 c
= get_symbol_end ();
12951 symbolP
= symbol_find_or_make (name
);
12952 S_SET_WEAK (symbolP
);
12953 *input_line_pointer
= c
;
12955 SKIP_WHITESPACE ();
12957 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12959 if (S_IS_DEFINED (symbolP
))
12961 as_bad ("ignoring attempt to redefine symbol %s",
12962 S_GET_NAME (symbolP
));
12963 ignore_rest_of_line ();
12967 if (*input_line_pointer
== ',')
12969 ++input_line_pointer
;
12970 SKIP_WHITESPACE ();
12974 if (exp
.X_op
!= O_symbol
)
12976 as_bad ("bad .weakext directive");
12977 ignore_rest_of_line ();
12980 symbol_set_value_expression (symbolP
, &exp
);
12983 demand_empty_rest_of_line ();
12986 /* Parse a register string into a number. Called from the ECOFF code
12987 to parse .frame. The argument is non-zero if this is the frame
12988 register, so that we can record it in mips_frame_reg. */
12991 tc_get_register (int frame
)
12995 SKIP_WHITESPACE ();
12996 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13000 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13001 mips_frame_reg_valid
= 1;
13002 mips_cprestore_valid
= 0;
13008 md_section_align (asection
*seg
, valueT addr
)
13010 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13013 /* We don't need to align ELF sections to the full alignment.
13014 However, Irix 5 may prefer that we align them at least to a 16
13015 byte boundary. We don't bother to align the sections if we are
13016 targeted for an embedded system. */
13017 if (strcmp (TARGET_OS
, "elf") == 0)
13023 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13026 /* Utility routine, called from above as well. If called while the
13027 input file is still being read, it's only an approximation. (For
13028 example, a symbol may later become defined which appeared to be
13029 undefined earlier.) */
13032 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13037 if (g_switch_value
> 0)
13039 const char *symname
;
13042 /* Find out whether this symbol can be referenced off the $gp
13043 register. It can be if it is smaller than the -G size or if
13044 it is in the .sdata or .sbss section. Certain symbols can
13045 not be referenced off the $gp, although it appears as though
13047 symname
= S_GET_NAME (sym
);
13048 if (symname
!= (const char *) NULL
13049 && (strcmp (symname
, "eprol") == 0
13050 || strcmp (symname
, "etext") == 0
13051 || strcmp (symname
, "_gp") == 0
13052 || strcmp (symname
, "edata") == 0
13053 || strcmp (symname
, "_fbss") == 0
13054 || strcmp (symname
, "_fdata") == 0
13055 || strcmp (symname
, "_ftext") == 0
13056 || strcmp (symname
, "end") == 0
13057 || strcmp (symname
, "_gp_disp") == 0))
13059 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13061 #ifndef NO_ECOFF_DEBUGGING
13062 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13063 && (symbol_get_obj (sym
)->ecoff_extern_size
13064 <= g_switch_value
))
13066 /* We must defer this decision until after the whole
13067 file has been read, since there might be a .extern
13068 after the first use of this symbol. */
13069 || (before_relaxing
13070 #ifndef NO_ECOFF_DEBUGGING
13071 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13073 && S_GET_VALUE (sym
) == 0)
13074 || (S_GET_VALUE (sym
) != 0
13075 && S_GET_VALUE (sym
) <= g_switch_value
)))
13079 const char *segname
;
13081 segname
= segment_name (S_GET_SEGMENT (sym
));
13082 assert (strcmp (segname
, ".lit8") != 0
13083 && strcmp (segname
, ".lit4") != 0);
13084 change
= (strcmp (segname
, ".sdata") != 0
13085 && strcmp (segname
, ".sbss") != 0
13086 && strncmp (segname
, ".sdata.", 7) != 0
13087 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13092 /* We are not optimizing for the $gp register. */
13097 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13100 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13103 bfd_boolean linkonce
;
13105 /* Handle the case of a symbol equated to another symbol. */
13106 while (symbol_equated_reloc_p (sym
))
13110 /* It's possible to get a loop here in a badly written
13112 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13118 symsec
= S_GET_SEGMENT (sym
);
13120 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13122 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13124 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13128 /* The GNU toolchain uses an extension for ELF: a section
13129 beginning with the magic string .gnu.linkonce is a linkonce
13131 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13132 sizeof ".gnu.linkonce" - 1) == 0)
13136 /* This must duplicate the test in adjust_reloc_syms. */
13137 return (symsec
!= &bfd_und_section
13138 && symsec
!= &bfd_abs_section
13139 && ! bfd_is_com_section (symsec
)
13142 /* A global or weak symbol is treated as external. */
13143 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13144 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13150 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13151 extended opcode. SEC is the section the frag is in. */
13154 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13157 register const struct mips16_immed_operand
*op
;
13159 int mintiny
, maxtiny
;
13163 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13165 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13168 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13169 op
= mips16_immed_operands
;
13170 while (op
->type
!= type
)
13173 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13178 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13181 maxtiny
= 1 << op
->nbits
;
13186 maxtiny
= (1 << op
->nbits
) - 1;
13191 mintiny
= - (1 << (op
->nbits
- 1));
13192 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13195 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13196 val
= S_GET_VALUE (fragp
->fr_symbol
);
13197 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13203 /* We won't have the section when we are called from
13204 mips_relax_frag. However, we will always have been called
13205 from md_estimate_size_before_relax first. If this is a
13206 branch to a different section, we mark it as such. If SEC is
13207 NULL, and the frag is not marked, then it must be a branch to
13208 the same section. */
13211 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13216 /* Must have been called from md_estimate_size_before_relax. */
13219 fragp
->fr_subtype
=
13220 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13222 /* FIXME: We should support this, and let the linker
13223 catch branches and loads that are out of range. */
13224 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13225 _("unsupported PC relative reference to different section"));
13229 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13230 /* Assume non-extended on the first relaxation pass.
13231 The address we have calculated will be bogus if this is
13232 a forward branch to another frag, as the forward frag
13233 will have fr_address == 0. */
13237 /* In this case, we know for sure that the symbol fragment is in
13238 the same section. If the relax_marker of the symbol fragment
13239 differs from the relax_marker of this fragment, we have not
13240 yet adjusted the symbol fragment fr_address. We want to add
13241 in STRETCH in order to get a better estimate of the address.
13242 This particularly matters because of the shift bits. */
13244 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13248 /* Adjust stretch for any alignment frag. Note that if have
13249 been expanding the earlier code, the symbol may be
13250 defined in what appears to be an earlier frag. FIXME:
13251 This doesn't handle the fr_subtype field, which specifies
13252 a maximum number of bytes to skip when doing an
13254 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13256 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13259 stretch
= - ((- stretch
)
13260 & ~ ((1 << (int) f
->fr_offset
) - 1));
13262 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13271 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13273 /* The base address rules are complicated. The base address of
13274 a branch is the following instruction. The base address of a
13275 PC relative load or add is the instruction itself, but if it
13276 is in a delay slot (in which case it can not be extended) use
13277 the address of the instruction whose delay slot it is in. */
13278 if (type
== 'p' || type
== 'q')
13282 /* If we are currently assuming that this frag should be
13283 extended, then, the current address is two bytes
13285 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13288 /* Ignore the low bit in the target, since it will be set
13289 for a text label. */
13290 if ((val
& 1) != 0)
13293 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13295 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13298 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13300 /* Branch offsets have an implicit 0 in the lowest bit. */
13301 if (type
== 'p' || type
== 'q')
13304 /* If any of the shifted bits are set, we must use an extended
13305 opcode. If the address depends on the size of this
13306 instruction, this can lead to a loop, so we arrange to always
13307 use an extended opcode. We only check this when we are in
13308 the main relaxation loop, when SEC is NULL. */
13309 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13311 fragp
->fr_subtype
=
13312 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13316 /* If we are about to mark a frag as extended because the value
13317 is precisely maxtiny + 1, then there is a chance of an
13318 infinite loop as in the following code:
13323 In this case when the la is extended, foo is 0x3fc bytes
13324 away, so the la can be shrunk, but then foo is 0x400 away, so
13325 the la must be extended. To avoid this loop, we mark the
13326 frag as extended if it was small, and is about to become
13327 extended with a value of maxtiny + 1. */
13328 if (val
== ((maxtiny
+ 1) << op
->shift
)
13329 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13332 fragp
->fr_subtype
=
13333 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13337 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13338 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13340 if ((val
& ((1 << op
->shift
) - 1)) != 0
13341 || val
< (mintiny
<< op
->shift
)
13342 || val
> (maxtiny
<< op
->shift
))
13348 /* Compute the length of a branch sequence, and adjust the
13349 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13350 worst-case length is computed, with UPDATE being used to indicate
13351 whether an unconditional (-1), branch-likely (+1) or regular (0)
13352 branch is to be computed. */
13354 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13356 bfd_boolean toofar
;
13360 && S_IS_DEFINED (fragp
->fr_symbol
)
13361 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13366 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13368 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13372 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13375 /* If the symbol is not defined or it's in a different segment,
13376 assume the user knows what's going on and emit a short
13382 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13384 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13385 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13386 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13392 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13395 if (mips_pic
!= NO_PIC
)
13397 /* Additional space for PIC loading of target address. */
13399 if (mips_opts
.isa
== ISA_MIPS1
)
13400 /* Additional space for $at-stabilizing nop. */
13404 /* If branch is conditional. */
13405 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13412 /* Estimate the size of a frag before relaxing. Unless this is the
13413 mips16, we are not really relaxing here, and the final size is
13414 encoded in the subtype information. For the mips16, we have to
13415 decide whether we are using an extended opcode or not. */
13418 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13422 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13425 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13427 return fragp
->fr_var
;
13430 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13431 /* We don't want to modify the EXTENDED bit here; it might get us
13432 into infinite loops. We change it only in mips_relax_frag(). */
13433 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13435 if (mips_pic
== NO_PIC
)
13436 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13437 else if (mips_pic
== SVR4_PIC
)
13438 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13439 else if (mips_pic
== VXWORKS_PIC
)
13440 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13447 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13448 return -RELAX_FIRST (fragp
->fr_subtype
);
13451 return -RELAX_SECOND (fragp
->fr_subtype
);
13454 /* This is called to see whether a reloc against a defined symbol
13455 should be converted into a reloc against a section. */
13458 mips_fix_adjustable (fixS
*fixp
)
13460 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13461 about the format of the offset in the .o file. */
13462 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13465 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13466 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13469 if (fixp
->fx_addsy
== NULL
)
13472 /* If symbol SYM is in a mergeable section, relocations of the form
13473 SYM + 0 can usually be made section-relative. The mergeable data
13474 is then identified by the section offset rather than by the symbol.
13476 However, if we're generating REL LO16 relocations, the offset is split
13477 between the LO16 and parterning high part relocation. The linker will
13478 need to recalculate the complete offset in order to correctly identify
13481 The linker has traditionally not looked for the parterning high part
13482 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13483 placed anywhere. Rather than break backwards compatibility by changing
13484 this, it seems better not to force the issue, and instead keep the
13485 original symbol. This will work with either linker behavior. */
13486 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13487 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13488 || reloc_needs_lo_p (fixp
->fx_r_type
))
13489 && HAVE_IN_PLACE_ADDENDS
13490 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13494 /* Don't adjust relocations against mips16 symbols, so that the linker
13495 can find them if it needs to set up a stub. */
13496 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13497 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13498 && fixp
->fx_subsy
== NULL
)
13505 /* Translate internal representation of relocation info to BFD target
13509 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13511 static arelent
*retval
[4];
13513 bfd_reloc_code_real_type code
;
13515 memset (retval
, 0, sizeof(retval
));
13516 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13517 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13518 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13519 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13521 if (fixp
->fx_pcrel
)
13523 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13525 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13526 Relocations want only the symbol offset. */
13527 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13528 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13530 /* A gruesome hack which is a result of the gruesome gas
13531 reloc handling. What's worse, for COFF (as opposed to
13532 ECOFF), we might need yet another copy of reloc->address.
13533 See bfd_install_relocation. */
13534 reloc
->addend
+= reloc
->address
;
13538 reloc
->addend
= fixp
->fx_addnumber
;
13540 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13541 entry to be used in the relocation's section offset. */
13542 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13544 reloc
->address
= reloc
->addend
;
13548 code
= fixp
->fx_r_type
;
13550 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13551 if (reloc
->howto
== NULL
)
13553 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13554 _("Can not represent %s relocation in this object file format"),
13555 bfd_get_reloc_code_name (code
));
13562 /* Relax a machine dependent frag. This returns the amount by which
13563 the current size of the frag should change. */
13566 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13568 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13570 offsetT old_var
= fragp
->fr_var
;
13572 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13574 return fragp
->fr_var
- old_var
;
13577 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13580 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13582 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13584 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13589 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13591 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13598 /* Convert a machine dependent frag. */
13601 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13603 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13606 unsigned long insn
;
13610 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13612 if (target_big_endian
)
13613 insn
= bfd_getb32 (buf
);
13615 insn
= bfd_getl32 (buf
);
13617 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13619 /* We generate a fixup instead of applying it right now
13620 because, if there are linker relaxations, we're going to
13621 need the relocations. */
13622 exp
.X_op
= O_symbol
;
13623 exp
.X_add_symbol
= fragp
->fr_symbol
;
13624 exp
.X_add_number
= fragp
->fr_offset
;
13626 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13627 4, &exp
, 1, BFD_RELOC_16_PCREL_S2
);
13628 fixp
->fx_file
= fragp
->fr_file
;
13629 fixp
->fx_line
= fragp
->fr_line
;
13631 md_number_to_chars ((char *) buf
, insn
, 4);
13638 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13639 _("relaxed out-of-range branch into a jump"));
13641 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13644 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13646 /* Reverse the branch. */
13647 switch ((insn
>> 28) & 0xf)
13650 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13651 have the condition reversed by tweaking a single
13652 bit, and their opcodes all have 0x4???????. */
13653 assert ((insn
& 0xf1000000) == 0x41000000);
13654 insn
^= 0x00010000;
13658 /* bltz 0x04000000 bgez 0x04010000
13659 bltzal 0x04100000 bgezal 0x04110000 */
13660 assert ((insn
& 0xfc0e0000) == 0x04000000);
13661 insn
^= 0x00010000;
13665 /* beq 0x10000000 bne 0x14000000
13666 blez 0x18000000 bgtz 0x1c000000 */
13667 insn
^= 0x04000000;
13675 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13677 /* Clear the and-link bit. */
13678 assert ((insn
& 0xfc1c0000) == 0x04100000);
13680 /* bltzal 0x04100000 bgezal 0x04110000
13681 bltzall 0x04120000 bgezall 0x04130000 */
13682 insn
&= ~0x00100000;
13685 /* Branch over the branch (if the branch was likely) or the
13686 full jump (not likely case). Compute the offset from the
13687 current instruction to branch to. */
13688 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13692 /* How many bytes in instructions we've already emitted? */
13693 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13694 /* How many bytes in instructions from here to the end? */
13695 i
= fragp
->fr_var
- i
;
13697 /* Convert to instruction count. */
13699 /* Branch counts from the next instruction. */
13702 /* Branch over the jump. */
13703 md_number_to_chars ((char *) buf
, insn
, 4);
13707 md_number_to_chars ((char *) buf
, 0, 4);
13710 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13712 /* beql $0, $0, 2f */
13714 /* Compute the PC offset from the current instruction to
13715 the end of the variable frag. */
13716 /* How many bytes in instructions we've already emitted? */
13717 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13718 /* How many bytes in instructions from here to the end? */
13719 i
= fragp
->fr_var
- i
;
13720 /* Convert to instruction count. */
13722 /* Don't decrement i, because we want to branch over the
13726 md_number_to_chars ((char *) buf
, insn
, 4);
13729 md_number_to_chars ((char *) buf
, 0, 4);
13734 if (mips_pic
== NO_PIC
)
13737 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13738 ? 0x0c000000 : 0x08000000);
13739 exp
.X_op
= O_symbol
;
13740 exp
.X_add_symbol
= fragp
->fr_symbol
;
13741 exp
.X_add_number
= fragp
->fr_offset
;
13743 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13744 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13745 fixp
->fx_file
= fragp
->fr_file
;
13746 fixp
->fx_line
= fragp
->fr_line
;
13748 md_number_to_chars ((char *) buf
, insn
, 4);
13753 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13754 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13755 exp
.X_op
= O_symbol
;
13756 exp
.X_add_symbol
= fragp
->fr_symbol
;
13757 exp
.X_add_number
= fragp
->fr_offset
;
13759 if (fragp
->fr_offset
)
13761 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13762 exp
.X_add_number
= 0;
13765 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13766 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13767 fixp
->fx_file
= fragp
->fr_file
;
13768 fixp
->fx_line
= fragp
->fr_line
;
13770 md_number_to_chars ((char *) buf
, insn
, 4);
13773 if (mips_opts
.isa
== ISA_MIPS1
)
13776 md_number_to_chars ((char *) buf
, 0, 4);
13780 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13781 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13783 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13784 4, &exp
, 0, BFD_RELOC_LO16
);
13785 fixp
->fx_file
= fragp
->fr_file
;
13786 fixp
->fx_line
= fragp
->fr_line
;
13788 md_number_to_chars ((char *) buf
, insn
, 4);
13792 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13797 md_number_to_chars ((char *) buf
, insn
, 4);
13802 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13803 + fragp
->fr_fix
+ fragp
->fr_var
);
13805 fragp
->fr_fix
+= fragp
->fr_var
;
13810 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13813 register const struct mips16_immed_operand
*op
;
13814 bfd_boolean small
, ext
;
13817 unsigned long insn
;
13818 bfd_boolean use_extend
;
13819 unsigned short extend
;
13821 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13822 op
= mips16_immed_operands
;
13823 while (op
->type
!= type
)
13826 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13837 resolve_symbol_value (fragp
->fr_symbol
);
13838 val
= S_GET_VALUE (fragp
->fr_symbol
);
13843 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13845 /* The rules for the base address of a PC relative reloc are
13846 complicated; see mips16_extended_frag. */
13847 if (type
== 'p' || type
== 'q')
13852 /* Ignore the low bit in the target, since it will be
13853 set for a text label. */
13854 if ((val
& 1) != 0)
13857 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13859 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13862 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13865 /* Make sure the section winds up with the alignment we have
13868 record_alignment (asec
, op
->shift
);
13872 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13873 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13874 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13875 _("extended instruction in delay slot"));
13877 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13879 if (target_big_endian
)
13880 insn
= bfd_getb16 (buf
);
13882 insn
= bfd_getl16 (buf
);
13884 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13885 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13886 small
, ext
, &insn
, &use_extend
, &extend
);
13890 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13891 fragp
->fr_fix
+= 2;
13895 md_number_to_chars ((char *) buf
, insn
, 2);
13896 fragp
->fr_fix
+= 2;
13904 first
= RELAX_FIRST (fragp
->fr_subtype
);
13905 second
= RELAX_SECOND (fragp
->fr_subtype
);
13906 fixp
= (fixS
*) fragp
->fr_opcode
;
13908 /* Possibly emit a warning if we've chosen the longer option. */
13909 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13910 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13912 const char *msg
= macro_warning (fragp
->fr_subtype
);
13914 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13917 /* Go through all the fixups for the first sequence. Disable them
13918 (by marking them as done) if we're going to use the second
13919 sequence instead. */
13921 && fixp
->fx_frag
== fragp
13922 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13924 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13926 fixp
= fixp
->fx_next
;
13929 /* Go through the fixups for the second sequence. Disable them if
13930 we're going to use the first sequence, otherwise adjust their
13931 addresses to account for the relaxation. */
13932 while (fixp
&& fixp
->fx_frag
== fragp
)
13934 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13935 fixp
->fx_where
-= first
;
13938 fixp
= fixp
->fx_next
;
13941 /* Now modify the frag contents. */
13942 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13946 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13947 memmove (start
, start
+ first
, second
);
13948 fragp
->fr_fix
-= first
;
13951 fragp
->fr_fix
-= second
;
13957 /* This function is called after the relocs have been generated.
13958 We've been storing mips16 text labels as odd. Here we convert them
13959 back to even for the convenience of the debugger. */
13962 mips_frob_file_after_relocs (void)
13965 unsigned int count
, i
;
13967 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13970 syms
= bfd_get_outsymbols (stdoutput
);
13971 count
= bfd_get_symcount (stdoutput
);
13972 for (i
= 0; i
< count
; i
++, syms
++)
13974 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13975 && ((*syms
)->value
& 1) != 0)
13977 (*syms
)->value
&= ~1;
13978 /* If the symbol has an odd size, it was probably computed
13979 incorrectly, so adjust that as well. */
13980 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13981 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13988 /* This function is called whenever a label is defined. It is used
13989 when handling branch delays; if a branch has a label, we assume we
13990 can not move it. */
13993 mips_define_label (symbolS
*sym
)
13995 struct insn_label_list
*l
;
13997 if (free_insn_labels
== NULL
)
13998 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14001 l
= free_insn_labels
;
14002 free_insn_labels
= l
->next
;
14006 l
->next
= insn_labels
;
14010 dwarf2_emit_label (sym
);
14014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14016 /* Some special processing for a MIPS ELF file. */
14019 mips_elf_final_processing (void)
14021 /* Write out the register information. */
14022 if (mips_abi
!= N64_ABI
)
14026 s
.ri_gprmask
= mips_gprmask
;
14027 s
.ri_cprmask
[0] = mips_cprmask
[0];
14028 s
.ri_cprmask
[1] = mips_cprmask
[1];
14029 s
.ri_cprmask
[2] = mips_cprmask
[2];
14030 s
.ri_cprmask
[3] = mips_cprmask
[3];
14031 /* The gp_value field is set by the MIPS ELF backend. */
14033 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14034 ((Elf32_External_RegInfo
*)
14035 mips_regmask_frag
));
14039 Elf64_Internal_RegInfo s
;
14041 s
.ri_gprmask
= mips_gprmask
;
14043 s
.ri_cprmask
[0] = mips_cprmask
[0];
14044 s
.ri_cprmask
[1] = mips_cprmask
[1];
14045 s
.ri_cprmask
[2] = mips_cprmask
[2];
14046 s
.ri_cprmask
[3] = mips_cprmask
[3];
14047 /* The gp_value field is set by the MIPS ELF backend. */
14049 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14050 ((Elf64_External_RegInfo
*)
14051 mips_regmask_frag
));
14054 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14055 sort of BFD interface for this. */
14056 if (mips_any_noreorder
)
14057 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14058 if (mips_pic
!= NO_PIC
)
14060 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14061 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14064 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14066 /* Set MIPS ELF flags for ASEs. */
14067 /* We may need to define a new flag for DSP ASE, and set this flag when
14068 file_ase_dsp is true. */
14069 /* We may need to define a new flag for MT ASE, and set this flag when
14070 file_ase_mt is true. */
14071 if (file_ase_mips16
)
14072 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14073 #if 0 /* XXX FIXME */
14074 if (file_ase_mips3d
)
14075 elf_elfheader (stdoutput
)->e_flags
|= ???;
14078 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14080 /* Set the MIPS ELF ABI flags. */
14081 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14082 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14083 else if (mips_abi
== O64_ABI
)
14084 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14085 else if (mips_abi
== EABI_ABI
)
14087 if (!file_mips_gp32
)
14088 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14090 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14092 else if (mips_abi
== N32_ABI
)
14093 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14095 /* Nothing to do for N64_ABI. */
14097 if (mips_32bitmode
)
14098 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14100 #if 0 /* XXX FIXME */
14101 /* 32 bit code with 64 bit FP registers. */
14102 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14103 elf_elfheader (stdoutput
)->e_flags
|= ???;
14107 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14109 typedef struct proc
{
14111 symbolS
*func_end_sym
;
14112 unsigned long reg_mask
;
14113 unsigned long reg_offset
;
14114 unsigned long fpreg_mask
;
14115 unsigned long fpreg_offset
;
14116 unsigned long frame_offset
;
14117 unsigned long frame_reg
;
14118 unsigned long pc_reg
;
14121 static procS cur_proc
;
14122 static procS
*cur_proc_ptr
;
14123 static int numprocs
;
14125 /* Fill in an rs_align_code fragment. */
14128 mips_handle_align (fragS
*fragp
)
14130 if (fragp
->fr_type
!= rs_align_code
)
14133 if (mips_opts
.mips16
)
14135 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14136 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14141 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14142 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14150 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14154 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14158 md_obj_begin (void)
14165 /* check for premature end, nesting errors, etc */
14167 as_warn (_("missing .end at end of assembly"));
14176 if (*input_line_pointer
== '-')
14178 ++input_line_pointer
;
14181 if (!ISDIGIT (*input_line_pointer
))
14182 as_bad (_("expected simple number"));
14183 if (input_line_pointer
[0] == '0')
14185 if (input_line_pointer
[1] == 'x')
14187 input_line_pointer
+= 2;
14188 while (ISXDIGIT (*input_line_pointer
))
14191 val
|= hex_value (*input_line_pointer
++);
14193 return negative
? -val
: val
;
14197 ++input_line_pointer
;
14198 while (ISDIGIT (*input_line_pointer
))
14201 val
|= *input_line_pointer
++ - '0';
14203 return negative
? -val
: val
;
14206 if (!ISDIGIT (*input_line_pointer
))
14208 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14209 *input_line_pointer
, *input_line_pointer
);
14210 as_warn (_("invalid number"));
14213 while (ISDIGIT (*input_line_pointer
))
14216 val
+= *input_line_pointer
++ - '0';
14218 return negative
? -val
: val
;
14221 /* The .file directive; just like the usual .file directive, but there
14222 is an initial number which is the ECOFF file index. In the non-ECOFF
14223 case .file implies DWARF-2. */
14226 s_mips_file (int x ATTRIBUTE_UNUSED
)
14228 static int first_file_directive
= 0;
14230 if (ECOFF_DEBUGGING
)
14239 filename
= dwarf2_directive_file (0);
14241 /* Versions of GCC up to 3.1 start files with a ".file"
14242 directive even for stabs output. Make sure that this
14243 ".file" is handled. Note that you need a version of GCC
14244 after 3.1 in order to support DWARF-2 on MIPS. */
14245 if (filename
!= NULL
&& ! first_file_directive
)
14247 (void) new_logical_line (filename
, -1);
14248 s_app_file_string (filename
, 0);
14250 first_file_directive
= 1;
14254 /* The .loc directive, implying DWARF-2. */
14257 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14259 if (!ECOFF_DEBUGGING
)
14260 dwarf2_directive_loc (0);
14263 /* The .end directive. */
14266 s_mips_end (int x ATTRIBUTE_UNUSED
)
14270 /* Following functions need their own .frame and .cprestore directives. */
14271 mips_frame_reg_valid
= 0;
14272 mips_cprestore_valid
= 0;
14274 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14277 demand_empty_rest_of_line ();
14282 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14283 as_warn (_(".end not in text section"));
14287 as_warn (_(".end directive without a preceding .ent directive."));
14288 demand_empty_rest_of_line ();
14294 assert (S_GET_NAME (p
));
14295 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14296 as_warn (_(".end symbol does not match .ent symbol."));
14298 if (debug_type
== DEBUG_STABS
)
14299 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14303 as_warn (_(".end directive missing or unknown symbol"));
14306 /* Create an expression to calculate the size of the function. */
14307 if (p
&& cur_proc_ptr
)
14309 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14310 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14313 exp
->X_op
= O_subtract
;
14314 exp
->X_add_symbol
= symbol_temp_new_now ();
14315 exp
->X_op_symbol
= p
;
14316 exp
->X_add_number
= 0;
14318 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14321 /* Generate a .pdr section. */
14322 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14325 segT saved_seg
= now_seg
;
14326 subsegT saved_subseg
= now_subseg
;
14331 dot
= frag_now_fix ();
14333 #ifdef md_flush_pending_output
14334 md_flush_pending_output ();
14338 subseg_set (pdr_seg
, 0);
14340 /* Write the symbol. */
14341 exp
.X_op
= O_symbol
;
14342 exp
.X_add_symbol
= p
;
14343 exp
.X_add_number
= 0;
14344 emit_expr (&exp
, 4);
14346 fragp
= frag_more (7 * 4);
14348 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14349 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14350 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14351 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14352 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14353 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14354 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14356 subseg_set (saved_seg
, saved_subseg
);
14358 #endif /* OBJ_ELF */
14360 cur_proc_ptr
= NULL
;
14363 /* The .aent and .ent directives. */
14366 s_mips_ent (int aent
)
14370 symbolP
= get_symbol ();
14371 if (*input_line_pointer
== ',')
14372 ++input_line_pointer
;
14373 SKIP_WHITESPACE ();
14374 if (ISDIGIT (*input_line_pointer
)
14375 || *input_line_pointer
== '-')
14378 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14379 as_warn (_(".ent or .aent not in text section."));
14381 if (!aent
&& cur_proc_ptr
)
14382 as_warn (_("missing .end"));
14386 /* This function needs its own .frame and .cprestore directives. */
14387 mips_frame_reg_valid
= 0;
14388 mips_cprestore_valid
= 0;
14390 cur_proc_ptr
= &cur_proc
;
14391 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14393 cur_proc_ptr
->func_sym
= symbolP
;
14395 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14399 if (debug_type
== DEBUG_STABS
)
14400 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14401 S_GET_NAME (symbolP
));
14404 demand_empty_rest_of_line ();
14407 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14408 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14409 s_mips_frame is used so that we can set the PDR information correctly.
14410 We can't use the ecoff routines because they make reference to the ecoff
14411 symbol table (in the mdebug section). */
14414 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14417 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14421 if (cur_proc_ptr
== (procS
*) NULL
)
14423 as_warn (_(".frame outside of .ent"));
14424 demand_empty_rest_of_line ();
14428 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14430 SKIP_WHITESPACE ();
14431 if (*input_line_pointer
++ != ','
14432 || get_absolute_expression_and_terminator (&val
) != ',')
14434 as_warn (_("Bad .frame directive"));
14435 --input_line_pointer
;
14436 demand_empty_rest_of_line ();
14440 cur_proc_ptr
->frame_offset
= val
;
14441 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14443 demand_empty_rest_of_line ();
14446 #endif /* OBJ_ELF */
14450 /* The .fmask and .mask directives. If the mdebug section is present
14451 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14452 embedded targets, s_mips_mask is used so that we can set the PDR
14453 information correctly. We can't use the ecoff routines because they
14454 make reference to the ecoff symbol table (in the mdebug section). */
14457 s_mips_mask (int reg_type
)
14460 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14464 if (cur_proc_ptr
== (procS
*) NULL
)
14466 as_warn (_(".mask/.fmask outside of .ent"));
14467 demand_empty_rest_of_line ();
14471 if (get_absolute_expression_and_terminator (&mask
) != ',')
14473 as_warn (_("Bad .mask/.fmask directive"));
14474 --input_line_pointer
;
14475 demand_empty_rest_of_line ();
14479 off
= get_absolute_expression ();
14481 if (reg_type
== 'F')
14483 cur_proc_ptr
->fpreg_mask
= mask
;
14484 cur_proc_ptr
->fpreg_offset
= off
;
14488 cur_proc_ptr
->reg_mask
= mask
;
14489 cur_proc_ptr
->reg_offset
= off
;
14492 demand_empty_rest_of_line ();
14495 #endif /* OBJ_ELF */
14496 s_ignore (reg_type
);
14499 /* A table describing all the processors gas knows about. Names are
14500 matched in the order listed.
14502 To ease comparison, please keep this table in the same order as
14503 gcc's mips_cpu_info_table[]. */
14504 static const struct mips_cpu_info mips_cpu_info_table
[] =
14506 /* Entries for generic ISAs */
14507 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14508 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14509 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14510 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14511 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14512 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14513 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14514 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14515 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14518 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14519 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14520 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14523 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14526 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14527 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14528 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14529 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14530 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14531 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14532 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14533 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14534 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14535 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14536 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14537 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14540 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14541 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14542 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14543 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14544 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14545 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14546 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14547 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14548 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14549 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14550 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14551 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14552 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14555 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14556 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14557 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14558 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
14560 /* MIPS 32 Release 2 */
14561 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14562 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14563 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14564 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14565 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14566 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14567 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14568 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14569 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14570 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14571 /* 24ke is a 24k with DSP ASE, other ASEs are optional. */
14572 { "24ke", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14573 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14574 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14575 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14576 /* 34k is a 24k with MT ASE, other ASEs are optional. */
14577 { "34kc", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14578 { "34kf", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14579 { "34kx", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14582 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14583 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14584 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14586 /* MIPS 64 Release 2 */
14587 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14589 /* Broadcom SB-1 CPU core */
14590 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14591 ISA_MIPS64
, CPU_SB1
},
14598 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14599 with a final "000" replaced by "k". Ignore case.
14601 Note: this function is shared between GCC and GAS. */
14604 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14606 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14607 given
++, canonical
++;
14609 return ((*given
== 0 && *canonical
== 0)
14610 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14614 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14615 CPU name. We've traditionally allowed a lot of variation here.
14617 Note: this function is shared between GCC and GAS. */
14620 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14622 /* First see if the name matches exactly, or with a final "000"
14623 turned into "k". */
14624 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14627 /* If not, try comparing based on numerical designation alone.
14628 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14629 if (TOLOWER (*given
) == 'r')
14631 if (!ISDIGIT (*given
))
14634 /* Skip over some well-known prefixes in the canonical name,
14635 hoping to find a number there too. */
14636 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14638 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14640 else if (TOLOWER (canonical
[0]) == 'r')
14643 return mips_strict_matching_cpu_name_p (canonical
, given
);
14647 /* Parse an option that takes the name of a processor as its argument.
14648 OPTION is the name of the option and CPU_STRING is the argument.
14649 Return the corresponding processor enumeration if the CPU_STRING is
14650 recognized, otherwise report an error and return null.
14652 A similar function exists in GCC. */
14654 static const struct mips_cpu_info
*
14655 mips_parse_cpu (const char *option
, const char *cpu_string
)
14657 const struct mips_cpu_info
*p
;
14659 /* 'from-abi' selects the most compatible architecture for the given
14660 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14661 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14662 version. Look first at the -mgp options, if given, otherwise base
14663 the choice on MIPS_DEFAULT_64BIT.
14665 Treat NO_ABI like the EABIs. One reason to do this is that the
14666 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14667 architecture. This code picks MIPS I for 'mips' and MIPS III for
14668 'mips64', just as we did in the days before 'from-abi'. */
14669 if (strcasecmp (cpu_string
, "from-abi") == 0)
14671 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14672 return mips_cpu_info_from_isa (ISA_MIPS1
);
14674 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14675 return mips_cpu_info_from_isa (ISA_MIPS3
);
14677 if (file_mips_gp32
>= 0)
14678 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14680 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14685 /* 'default' has traditionally been a no-op. Probably not very useful. */
14686 if (strcasecmp (cpu_string
, "default") == 0)
14689 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14690 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14693 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14697 /* Return the canonical processor information for ISA (a member of the
14698 ISA_MIPS* enumeration). */
14700 static const struct mips_cpu_info
*
14701 mips_cpu_info_from_isa (int isa
)
14705 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14706 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
14707 && isa
== mips_cpu_info_table
[i
].isa
)
14708 return (&mips_cpu_info_table
[i
]);
14713 static const struct mips_cpu_info
*
14714 mips_cpu_info_from_arch (int arch
)
14718 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14719 if (arch
== mips_cpu_info_table
[i
].cpu
)
14720 return (&mips_cpu_info_table
[i
]);
14726 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14730 fprintf (stream
, "%24s", "");
14735 fprintf (stream
, ", ");
14739 if (*col_p
+ strlen (string
) > 72)
14741 fprintf (stream
, "\n%24s", "");
14745 fprintf (stream
, "%s", string
);
14746 *col_p
+= strlen (string
);
14752 md_show_usage (FILE *stream
)
14757 fprintf (stream
, _("\
14759 -EB generate big endian output\n\
14760 -EL generate little endian output\n\
14761 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14762 -G NUM allow referencing objects up to NUM bytes\n\
14763 implicitly with the gp register [default 8]\n"));
14764 fprintf (stream
, _("\
14765 -mips1 generate MIPS ISA I instructions\n\
14766 -mips2 generate MIPS ISA II instructions\n\
14767 -mips3 generate MIPS ISA III instructions\n\
14768 -mips4 generate MIPS ISA IV instructions\n\
14769 -mips5 generate MIPS ISA V instructions\n\
14770 -mips32 generate MIPS32 ISA instructions\n\
14771 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14772 -mips64 generate MIPS64 ISA instructions\n\
14773 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14774 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14778 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14779 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14780 show (stream
, "from-abi", &column
, &first
);
14781 fputc ('\n', stream
);
14783 fprintf (stream
, _("\
14784 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14785 -no-mCPU don't generate code specific to CPU.\n\
14786 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14790 show (stream
, "3900", &column
, &first
);
14791 show (stream
, "4010", &column
, &first
);
14792 show (stream
, "4100", &column
, &first
);
14793 show (stream
, "4650", &column
, &first
);
14794 fputc ('\n', stream
);
14796 fprintf (stream
, _("\
14797 -mips16 generate mips16 instructions\n\
14798 -no-mips16 do not generate mips16 instructions\n"));
14799 fprintf (stream
, _("\
14800 -msmartmips generate smartmips instructions\n\
14801 -mno-smartmips do not generate smartmips instructions\n"));
14802 fprintf (stream
, _("\
14803 -mdsp generate DSP instructions\n\
14804 -mno-dsp do not generate DSP instructions\n"));
14805 fprintf (stream
, _("\
14806 -mmt generate MT instructions\n\
14807 -mno-mt do not generate MT instructions\n"));
14808 fprintf (stream
, _("\
14809 -mfix-vr4120 work around certain VR4120 errata\n\
14810 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14811 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14812 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14813 -mno-shared optimize output for executables\n\
14814 -msym32 assume all symbols have 32-bit values\n\
14815 -O0 remove unneeded NOPs, do not swap branches\n\
14816 -O remove unneeded NOPs and swap branches\n\
14817 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14818 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14819 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14821 fprintf (stream
, _("\
14822 -KPIC, -call_shared generate SVR4 position independent code\n\
14823 -non_shared do not generate position independent code\n\
14824 -xgot assume a 32 bit GOT\n\
14825 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14826 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14828 -mabi=ABI create ABI conformant object file for:\n"));
14832 show (stream
, "32", &column
, &first
);
14833 show (stream
, "o64", &column
, &first
);
14834 show (stream
, "n32", &column
, &first
);
14835 show (stream
, "64", &column
, &first
);
14836 show (stream
, "eabi", &column
, &first
);
14838 fputc ('\n', stream
);
14840 fprintf (stream
, _("\
14841 -32 create o32 ABI object file (default)\n\
14842 -n32 create n32 ABI object file\n\
14843 -64 create 64 ABI object file\n"));
14848 mips_dwarf2_format (void)
14850 if (mips_abi
== N64_ABI
)
14853 return dwarf2_format_64bit_irix
;
14855 return dwarf2_format_64bit
;
14859 return dwarf2_format_32bit
;
14863 mips_dwarf2_addr_size (void)
14865 if (mips_abi
== N64_ABI
)
14871 /* Standard calling conventions leave the CFA at SP on entry. */
14873 mips_cfi_frame_initial_instructions (void)
14875 cfi_add_CFA_def_cfa_register (SP
);
14879 tc_mips_regname_to_dw2regnum (char *regname
)
14881 unsigned int regnum
= -1;
14884 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))