1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* Whether or not we have code that can call pic code. */
135 int mips_abicalls
= FALSE
;
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Enabled Application Specific Extensions (ASEs). These are set to -1
148 if they have not been initialized. Changed by `.set <asename>', by
149 command line options, and based on the default architecture. */
152 /* Whether we are assembling for the mips16 processor. 0 if we are
153 not, 1 if we are, and -1 if the value has not been initialized.
154 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
155 -nomips16 command line options, and the default CPU. */
157 /* Non-zero if we should not reorder instructions. Changed by `.set
158 reorder' and `.set noreorder'. */
160 /* Non-zero if we should not permit the $at ($1) register to be used
161 in instructions. Changed by `.set at' and `.set noat'. */
163 /* Non-zero if we should warn when a macro instruction expands into
164 more than one machine instruction. Changed by `.set nomacro' and
166 int warn_about_macros
;
167 /* Non-zero if we should not move instructions. Changed by `.set
168 move', `.set volatile', `.set nomove', and `.set novolatile'. */
170 /* Non-zero if we should not optimize branches by moving the target
171 of the branch into the delay slot. Actually, we don't perform
172 this optimization anyhow. Changed by `.set bopt' and `.set
175 /* Non-zero if we should not autoextend mips16 instructions.
176 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* Restrict general purpose registers and floating point registers
179 to 32 bit. This is initially determined when -mgp32 or -mfp32
180 is passed but can changed if the assembler code uses .set mipsN. */
183 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
184 command line option, and the default CPU. */
188 /* True if -mgp32 was passed. */
189 static int file_mips_gp32
= -1;
191 /* True if -mfp32 was passed. */
192 static int file_mips_fp32
= -1;
194 /* This is the struct we use to hold the current set of options. Note
195 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
196 -1 to indicate that they have not been initialized. */
198 static struct mips_set_options mips_opts
=
200 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
203 /* These variables are filled in with the masks of registers used.
204 The object format code reads them and puts them in the appropriate
206 unsigned long mips_gprmask
;
207 unsigned long mips_cprmask
[4];
209 /* MIPS ISA we are using for this output file. */
210 static int file_mips_isa
= ISA_UNKNOWN
;
212 /* True if -mips16 was passed or implied by arguments passed on the
213 command line (e.g., by -march). */
214 static int file_ase_mips16
;
216 /* True if -mips3d was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips3d
;
220 /* True if -mdmx was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mdmx
;
224 /* The argument of the -march= flag. The architecture we are assembling. */
225 static int file_mips_arch
= CPU_UNKNOWN
;
226 static const char *mips_arch_string
;
228 /* The argument of the -mtune= flag. The architecture for which we
230 static int mips_tune
= CPU_UNKNOWN
;
231 static const char *mips_tune_string
;
233 /* True when generating 32-bit code for a 64-bit processor. */
234 static int mips_32bitmode
= 0;
236 /* Some ISA's have delay slots for instructions which read or write
237 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
238 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
239 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
240 delay slot in this ISA. The uses of this macro assume that any
241 ISA that has delay slots for one of these, has them for all. They
242 also assume that ISAs which don't have delays for these insns, don't
243 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
244 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
246 || (ISA) == ISA_MIPS2 \
247 || (ISA) == ISA_MIPS3 \
250 /* True if the given ABI requires 32-bit registers. */
251 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
253 /* Likewise 64-bit registers. */
254 #define ABI_NEEDS_64BIT_REGS(ABI) \
256 || (ABI) == N64_ABI \
259 /* Return true if ISA supports 64 bit gp register instructions. */
260 #define ISA_HAS_64BIT_REGS(ISA) ( \
262 || (ISA) == ISA_MIPS4 \
263 || (ISA) == ISA_MIPS5 \
264 || (ISA) == ISA_MIPS64 \
267 /* Return true if ISA supports 64-bit right rotate (dror et al.)
269 #define ISA_HAS_DROR(ISA) ( \
273 /* Return true if ISA supports 32-bit right rotate (ror et al.)
275 #define ISA_HAS_ROR(ISA) ( \
276 (ISA) == ISA_MIPS32R2 \
279 #define HAVE_32BIT_GPRS \
280 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
282 #define HAVE_32BIT_FPRS \
283 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
285 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
286 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
288 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
290 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
292 /* We can only have 64bit addresses if the object file format
294 #define HAVE_32BIT_ADDRESSES \
296 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
297 || ! HAVE_64BIT_OBJECTS) \
298 && mips_pic != EMBEDDED_PIC))
300 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
301 #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
304 /* Addresses are loaded in different ways, depending on the address size
305 in use. The n32 ABI Documentation also mandates the use of additions
306 with overflow checking, but existing implementations don't follow it. */
307 #define ADDRESS_ADD_INSN \
308 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
310 #define ADDRESS_ADDI_INSN \
311 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
313 #define ADDRESS_LOAD_INSN \
314 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
316 #define ADDRESS_STORE_INSN \
317 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
319 /* Return true if the given CPU supports the MIPS16 ASE. */
320 #define CPU_HAS_MIPS16(cpu) \
321 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
322 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
324 /* Return true if the given CPU supports the MIPS3D ASE. */
325 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
328 /* Return true if the given CPU supports the MDMX ASE. */
329 #define CPU_HAS_MDMX(cpu) (FALSE \
332 /* True if CPU has a dror instruction. */
333 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
335 /* True if CPU has a ror instruction. */
336 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
338 /* Whether the processor uses hardware interlocks to protect
339 reads from the HI and LO registers, and thus does not
340 require nops to be inserted. */
342 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
343 || mips_opts.arch == CPU_VR5500 \
344 || mips_opts.arch == CPU_SB1 \
347 /* Whether the processor uses hardware interlocks to protect reads
348 from the GPRs, and thus does not require nops to be inserted. */
349 #define gpr_interlocks \
350 (mips_opts.isa != ISA_MIPS1 \
351 || mips_opts.arch == CPU_VR5400 \
352 || mips_opts.arch == CPU_VR5500 \
353 || mips_opts.arch == CPU_R3900)
355 /* As with other "interlocks" this is used by hardware that has FP
356 (co-processor) interlocks. */
357 /* Itbl support may require additional care here. */
358 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
359 || mips_opts.arch == CPU_VR5400 \
360 || mips_opts.arch == CPU_VR5500 \
361 || mips_opts.arch == CPU_SB1 \
364 /* Is this a mfhi or mflo instruction? */
365 #define MF_HILO_INSN(PINFO) \
366 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
368 /* MIPS PIC level. */
370 enum mips_pic_level mips_pic
;
372 /* Warn about all NOPS that the assembler generates. */
373 static int warn_nops
= 0;
375 /* 1 if we should generate 32 bit offsets from the $gp register in
376 SVR4_PIC mode. Currently has no meaning in other modes. */
377 static int mips_big_got
= 0;
379 /* 1 if trap instructions should used for overflow rather than break
381 static int mips_trap
= 0;
383 /* 1 if double width floating point constants should not be constructed
384 by assembling two single width halves into two single width floating
385 point registers which just happen to alias the double width destination
386 register. On some architectures this aliasing can be disabled by a bit
387 in the status register, and the setting of this bit cannot be determined
388 automatically at assemble time. */
389 static int mips_disable_float_construction
;
391 /* Non-zero if any .set noreorder directives were used. */
393 static int mips_any_noreorder
;
395 /* Non-zero if nops should be inserted when the register referenced in
396 an mfhi/mflo instruction is read in the next two instructions. */
397 static int mips_7000_hilo_fix
;
399 /* The size of the small data section. */
400 static unsigned int g_switch_value
= 8;
401 /* Whether the -G option was used. */
402 static int g_switch_seen
= 0;
407 /* If we can determine in advance that GP optimization won't be
408 possible, we can skip the relaxation stuff that tries to produce
409 GP-relative references. This makes delay slot optimization work
412 This function can only provide a guess, but it seems to work for
413 gcc output. It needs to guess right for gcc, otherwise gcc
414 will put what it thinks is a GP-relative instruction in a branch
417 I don't know if a fix is needed for the SVR4_PIC mode. I've only
418 fixed it for the non-PIC mode. KR 95/04/07 */
419 static int nopic_need_relax
PARAMS ((symbolS
*, int));
421 /* handle of the OPCODE hash table */
422 static struct hash_control
*op_hash
= NULL
;
424 /* The opcode hash table we use for the mips16. */
425 static struct hash_control
*mips16_op_hash
= NULL
;
427 /* This array holds the chars that always start a comment. If the
428 pre-processor is disabled, these aren't very useful */
429 const char comment_chars
[] = "#";
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output */
434 /* Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output. */
437 /* Also note that C style comments are always supported. */
438 const char line_comment_chars
[] = "#";
440 /* This array holds machine specific line separator characters. */
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point nums */
444 const char EXP_CHARS
[] = "eE";
446 /* Chars that mean this number is a floating point constant */
449 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
451 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
452 changed in read.c . Ideally it shouldn't have to know about it at all,
453 but nothing is ideal around here.
456 static char *insn_error
;
458 static int auto_align
= 1;
460 /* When outputting SVR4 PIC code, the assembler needs to know the
461 offset in the stack frame from which to restore the $gp register.
462 This is set by the .cprestore pseudo-op, and saved in this
464 static offsetT mips_cprestore_offset
= -1;
466 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
467 more optimizations, it can use a register value instead of a memory-saved
468 offset and even an other register than $gp as global pointer. */
469 static offsetT mips_cpreturn_offset
= -1;
470 static int mips_cpreturn_register
= -1;
471 static int mips_gp_register
= GP
;
472 static int mips_gprel_offset
= 0;
474 /* Whether mips_cprestore_offset has been set in the current function
475 (or whether it has already been warned about, if not). */
476 static int mips_cprestore_valid
= 0;
478 /* This is the register which holds the stack frame, as set by the
479 .frame pseudo-op. This is needed to implement .cprestore. */
480 static int mips_frame_reg
= SP
;
482 /* Whether mips_frame_reg has been set in the current function
483 (or whether it has already been warned about, if not). */
484 static int mips_frame_reg_valid
= 0;
486 /* To output NOP instructions correctly, we need to keep information
487 about the previous two instructions. */
489 /* Whether we are optimizing. The default value of 2 means to remove
490 unneeded NOPs and swap branch instructions when possible. A value
491 of 1 means to not swap branches. A value of 0 means to always
493 static int mips_optimize
= 2;
495 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
496 equivalent to seeing no -g option at all. */
497 static int mips_debug
= 0;
499 /* The previous instruction. */
500 static struct mips_cl_insn prev_insn
;
502 /* The instruction before prev_insn. */
503 static struct mips_cl_insn prev_prev_insn
;
505 /* If we don't want information for prev_insn or prev_prev_insn, we
506 point the insn_mo field at this dummy integer. */
507 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
509 /* Non-zero if prev_insn is valid. */
510 static int prev_insn_valid
;
512 /* The frag for the previous instruction. */
513 static struct frag
*prev_insn_frag
;
515 /* The offset into prev_insn_frag for the previous instruction. */
516 static long prev_insn_where
;
518 /* The reloc type for the previous instruction, if any. */
519 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
521 /* The reloc for the previous instruction, if any. */
522 static fixS
*prev_insn_fixp
[3];
524 /* Non-zero if the previous instruction was in a delay slot. */
525 static int prev_insn_is_delay_slot
;
527 /* Non-zero if the previous instruction was in a .set noreorder. */
528 static int prev_insn_unreordered
;
530 /* Non-zero if the previous instruction uses an extend opcode (if
532 static int prev_insn_extended
;
534 /* Non-zero if the previous previous instruction was in a .set
536 static int prev_prev_insn_unreordered
;
538 /* If this is set, it points to a frag holding nop instructions which
539 were inserted before the start of a noreorder section. If those
540 nops turn out to be unnecessary, the size of the frag can be
542 static fragS
*prev_nop_frag
;
544 /* The number of nop instructions we created in prev_nop_frag. */
545 static int prev_nop_frag_holds
;
547 /* The number of nop instructions that we know we need in
549 static int prev_nop_frag_required
;
551 /* The number of instructions we've seen since prev_nop_frag. */
552 static int prev_nop_frag_since
;
554 /* For ECOFF and ELF, relocations against symbols are done in two
555 parts, with a HI relocation and a LO relocation. Each relocation
556 has only 16 bits of space to store an addend. This means that in
557 order for the linker to handle carries correctly, it must be able
558 to locate both the HI and the LO relocation. This means that the
559 relocations must appear in order in the relocation table.
561 In order to implement this, we keep track of each unmatched HI
562 relocation. We then sort them so that they immediately precede the
563 corresponding LO relocation. */
568 struct mips_hi_fixup
*next
;
571 /* The section this fixup is in. */
575 /* The list of unmatched HI relocs. */
577 static struct mips_hi_fixup
*mips_hi_fixup_list
;
579 /* The frag containing the last explicit relocation operator.
580 Null if explicit relocations have not been used. */
582 static fragS
*prev_reloc_op_frag
;
584 /* Map normal MIPS register numbers to mips16 register numbers. */
586 #define X ILLEGAL_REG
587 static const int mips32_to_16_reg_map
[] =
589 X
, X
, 2, 3, 4, 5, 6, 7,
590 X
, X
, X
, X
, X
, X
, X
, X
,
591 0, 1, X
, X
, X
, X
, X
, X
,
592 X
, X
, X
, X
, X
, X
, X
, X
596 /* Map mips16 register numbers to normal MIPS register numbers. */
598 static const unsigned int mips16_to_32_reg_map
[] =
600 16, 17, 2, 3, 4, 5, 6, 7
603 static int mips_fix_4122_bugs
;
605 /* We don't relax branches by default, since this causes us to expand
606 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
607 fail to compute the offset before expanding the macro to the most
608 efficient expansion. */
610 static int mips_relax_branch
;
612 /* Since the MIPS does not have multiple forms of PC relative
613 instructions, we do not have to do relaxing as is done on other
614 platforms. However, we do have to handle GP relative addressing
615 correctly, which turns out to be a similar problem.
617 Every macro that refers to a symbol can occur in (at least) two
618 forms, one with GP relative addressing and one without. For
619 example, loading a global variable into a register generally uses
620 a macro instruction like this:
622 If i can be addressed off the GP register (this is true if it is in
623 the .sbss or .sdata section, or if it is known to be smaller than
624 the -G argument) this will generate the following instruction:
626 This instruction will use a GPREL reloc. If i can not be addressed
627 off the GP register, the following instruction sequence will be used:
630 In this case the first instruction will have a HI16 reloc, and the
631 second reloc will have a LO16 reloc. Both relocs will be against
634 The issue here is that we may not know whether i is GP addressable
635 until after we see the instruction that uses it. Therefore, we
636 want to be able to choose the final instruction sequence only at
637 the end of the assembly. This is similar to the way other
638 platforms choose the size of a PC relative instruction only at the
641 When generating position independent code we do not use GP
642 addressing in quite the same way, but the issue still arises as
643 external symbols and local symbols must be handled differently.
645 We handle these issues by actually generating both possible
646 instruction sequences. The longer one is put in a frag_var with
647 type rs_machine_dependent. We encode what to do with the frag in
648 the subtype field. We encode (1) the number of existing bytes to
649 replace, (2) the number of new bytes to use, (3) the offset from
650 the start of the existing bytes to the first reloc we must generate
651 (that is, the offset is applied from the start of the existing
652 bytes after they are replaced by the new bytes, if any), (4) the
653 offset from the start of the existing bytes to the second reloc,
654 (5) whether a third reloc is needed (the third reloc is always four
655 bytes after the second reloc), and (6) whether to warn if this
656 variant is used (this is sometimes needed if .set nomacro or .set
657 noat is in effect). All these numbers are reasonably small.
659 Generating two instruction sequences must be handled carefully to
660 ensure that delay slots are handled correctly. Fortunately, there
661 are a limited number of cases. When the second instruction
662 sequence is generated, append_insn is directed to maintain the
663 existing delay slot information, so it continues to apply to any
664 code after the second instruction sequence. This means that the
665 second instruction sequence must not impose any requirements not
666 required by the first instruction sequence.
668 These variant frags are then handled in functions called by the
669 machine independent code. md_estimate_size_before_relax returns
670 the final size of the frag. md_convert_frag sets up the final form
671 of the frag. tc_gen_reloc adjust the first reloc and adds a second
673 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
677 | (((reloc1) + 64) << 9) \
678 | (((reloc2) + 64) << 2) \
679 | ((reloc3) ? (1 << 1) : 0) \
681 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
682 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
683 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
684 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
685 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
686 #define RELAX_WARN(i) ((i) & 1)
688 /* Branch without likely bit. If label is out of range, we turn:
690 beq reg1, reg2, label
700 with the following opcode replacements:
707 bltzal <-> bgezal (with jal label instead of j label)
709 Even though keeping the delay slot instruction in the delay slot of
710 the branch would be more efficient, it would be very tricky to do
711 correctly, because we'd have to introduce a variable frag *after*
712 the delay slot instruction, and expand that instead. Let's do it
713 the easy way for now, even if the branch-not-taken case now costs
714 one additional instruction. Out-of-range branches are not supposed
715 to be common, anyway.
717 Branch likely. If label is out of range, we turn:
719 beql reg1, reg2, label
720 delay slot (annulled if branch not taken)
729 delay slot (executed only if branch taken)
732 It would be possible to generate a shorter sequence by losing the
733 likely bit, generating something like:
738 delay slot (executed only if branch taken)
750 bltzall -> bgezal (with jal label instead of j label)
751 bgezall -> bltzal (ditto)
754 but it's not clear that it would actually improve performance. */
755 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
758 | ((toofar) ? 1 : 0) \
760 | ((likely) ? 4 : 0) \
761 | ((uncond) ? 8 : 0)))
762 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
763 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
764 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
765 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
766 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
768 /* For mips16 code, we use an entirely different form of relaxation.
769 mips16 supports two versions of most instructions which take
770 immediate values: a small one which takes some small value, and a
771 larger one which takes a 16 bit value. Since branches also follow
772 this pattern, relaxing these values is required.
774 We can assemble both mips16 and normal MIPS code in a single
775 object. Therefore, we need to support this type of relaxation at
776 the same time that we support the relaxation described above. We
777 use the high bit of the subtype field to distinguish these cases.
779 The information we store for this type of relaxation is the
780 argument code found in the opcode file for this relocation, whether
781 the user explicitly requested a small or extended form, and whether
782 the relocation is in a jump or jal delay slot. That tells us the
783 size of the value, and how it should be stored. We also store
784 whether the fragment is considered to be extended or not. We also
785 store whether this is known to be a branch to a different section,
786 whether we have tried to relax this frag yet, and whether we have
787 ever extended a PC relative fragment because of a shift count. */
788 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
791 | ((small) ? 0x100 : 0) \
792 | ((ext) ? 0x200 : 0) \
793 | ((dslot) ? 0x400 : 0) \
794 | ((jal_dslot) ? 0x800 : 0))
795 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
796 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
797 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
798 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
799 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
800 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
801 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
802 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
803 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
804 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
805 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
806 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
808 /* Is the given value a sign-extended 32-bit value? */
809 #define IS_SEXT_32BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fffffff) == 0 \
811 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
813 /* Is the given value a sign-extended 16-bit value? */
814 #define IS_SEXT_16BIT_NUM(x) \
815 (((x) &~ (offsetT) 0x7fff) == 0 \
816 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
819 /* Prototypes for static functions. */
822 #define internalError() \
823 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
825 #define internalError() as_fatal (_("MIPS internal Error"));
828 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
830 static inline bfd_boolean reloc_needs_lo_p
831 PARAMS ((bfd_reloc_code_real_type
));
832 static inline bfd_boolean fixup_has_matching_lo_p
834 static int insn_uses_reg
835 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
836 enum mips_regclass
class));
837 static int reg_needs_delay
838 PARAMS ((unsigned int));
839 static void mips16_mark_labels
841 static void append_insn
842 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
843 bfd_reloc_code_real_type
*r
));
844 static void mips_no_prev_insn
846 static void mips_emit_delays
847 PARAMS ((bfd_boolean
));
849 static void macro_build
850 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
851 const char *fmt
, ...));
853 static void macro_build ();
855 static void mips16_macro_build
856 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
857 static void macro_build_jalr
858 PARAMS ((int, expressionS
*));
859 static void macro_build_lui
860 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
861 static void macro_build_ldst_constoffset
862 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
863 int valreg
, int breg
));
865 PARAMS ((int *counter
, int reg
, int unsignedp
));
866 static void check_absolute_expr
867 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
868 static void load_register
869 PARAMS ((int *, int, expressionS
*, int));
870 static void load_address
871 PARAMS ((int *, int, expressionS
*, int *));
872 static void move_register
873 PARAMS ((int *, int, int));
875 PARAMS ((struct mips_cl_insn
* ip
));
876 static void mips16_macro
877 PARAMS ((struct mips_cl_insn
* ip
));
878 #ifdef LOSING_COMPILER
880 PARAMS ((struct mips_cl_insn
* ip
));
883 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
884 static void mips16_ip
885 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
886 static void mips16_immed
887 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
888 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
889 static bfd_boolean parse_relocation
890 PARAMS ((char **, bfd_reloc_code_real_type
*));
891 static size_t my_getSmallExpression
892 PARAMS ((expressionS
*, bfd_reloc_code_real_type
*, char *));
893 static void my_getExpression
894 PARAMS ((expressionS
*, char *));
896 static int support_64bit_objects
899 static void mips_set_option_string
900 PARAMS ((const char **, const char *));
901 static symbolS
*get_symbol
903 static void mips_align
904 PARAMS ((int to
, int fill
, symbolS
*label
));
907 static void s_change_sec
909 static void s_change_section
913 static void s_float_cons
915 static void s_mips_globl
919 static void s_mipsset
921 static void s_abicalls
925 static void s_cpsetup
927 static void s_cplocal
929 static void s_cprestore
931 static void s_cpreturn
933 static void s_gpvalue
937 static void s_gpdword
943 static void md_obj_begin
945 static void md_obj_end
947 static long get_number
949 static void s_mips_ent
951 static void s_mips_end
953 static void s_mips_frame
955 static void s_mips_mask
957 static void s_mips_stab
959 static void s_mips_weakext
961 static void s_mips_file
963 static void s_mips_loc
965 static bfd_boolean pic_need_relax
966 PARAMS ((symbolS
*, asection
*));
967 static int mips16_extended_frag
968 PARAMS ((fragS
*, asection
*, long));
969 static int relaxed_branch_length (fragS
*, asection
*, int);
970 static int validate_mips_insn
971 PARAMS ((const struct mips_opcode
*));
973 PARAMS ((FILE *, const char *, int *, int *));
975 static int mips_need_elf_addend_fixup
979 /* Table and functions used to map between CPU/ISA names, and
980 ISA levels, and CPU numbers. */
984 const char *name
; /* CPU or ISA name. */
985 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
986 int isa
; /* ISA level. */
987 int cpu
; /* CPU number (default CPU if ISA). */
990 static void mips_set_architecture
991 PARAMS ((const struct mips_cpu_info
*));
992 static void mips_set_tune
993 PARAMS ((const struct mips_cpu_info
*));
994 static bfd_boolean mips_strict_matching_cpu_name_p
995 PARAMS ((const char *, const char *));
996 static bfd_boolean mips_matching_cpu_name_p
997 PARAMS ((const char *, const char *));
998 static const struct mips_cpu_info
*mips_parse_cpu
999 PARAMS ((const char *, const char *));
1000 static const struct mips_cpu_info
*mips_cpu_info_from_isa
1002 static const struct mips_cpu_info
*mips_cpu_info_from_arch
1007 The following pseudo-ops from the Kane and Heinrich MIPS book
1008 should be defined here, but are currently unsupported: .alias,
1009 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1011 The following pseudo-ops from the Kane and Heinrich MIPS book are
1012 specific to the type of debugging information being generated, and
1013 should be defined by the object format: .aent, .begin, .bend,
1014 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1017 The following pseudo-ops from the Kane and Heinrich MIPS book are
1018 not MIPS CPU specific, but are also not specific to the object file
1019 format. This file is probably the best place to define them, but
1020 they are not currently supported: .asm0, .endr, .lab, .repeat,
1023 static const pseudo_typeS mips_pseudo_table
[] =
1025 /* MIPS specific pseudo-ops. */
1026 {"option", s_option
, 0},
1027 {"set", s_mipsset
, 0},
1028 {"rdata", s_change_sec
, 'r'},
1029 {"sdata", s_change_sec
, 's'},
1030 {"livereg", s_ignore
, 0},
1031 {"abicalls", s_abicalls
, 0},
1032 {"cpload", s_cpload
, 0},
1033 {"cpsetup", s_cpsetup
, 0},
1034 {"cplocal", s_cplocal
, 0},
1035 {"cprestore", s_cprestore
, 0},
1036 {"cpreturn", s_cpreturn
, 0},
1037 {"gpvalue", s_gpvalue
, 0},
1038 {"gpword", s_gpword
, 0},
1039 {"gpdword", s_gpdword
, 0},
1040 {"cpadd", s_cpadd
, 0},
1041 {"insn", s_insn
, 0},
1043 /* Relatively generic pseudo-ops that happen to be used on MIPS
1045 {"asciiz", stringer
, 1},
1046 {"bss", s_change_sec
, 'b'},
1048 {"half", s_cons
, 1},
1049 {"dword", s_cons
, 3},
1050 {"weakext", s_mips_weakext
, 0},
1052 /* These pseudo-ops are defined in read.c, but must be overridden
1053 here for one reason or another. */
1054 {"align", s_align
, 0},
1055 {"byte", s_cons
, 0},
1056 {"data", s_change_sec
, 'd'},
1057 {"double", s_float_cons
, 'd'},
1058 {"float", s_float_cons
, 'f'},
1059 {"globl", s_mips_globl
, 0},
1060 {"global", s_mips_globl
, 0},
1061 {"hword", s_cons
, 1},
1063 {"long", s_cons
, 2},
1064 {"octa", s_cons
, 4},
1065 {"quad", s_cons
, 3},
1066 {"section", s_change_section
, 0},
1067 {"short", s_cons
, 1},
1068 {"single", s_float_cons
, 'f'},
1069 {"stabn", s_mips_stab
, 'n'},
1070 {"text", s_change_sec
, 't'},
1071 {"word", s_cons
, 2},
1073 { "extern", ecoff_directive_extern
, 0},
1078 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1080 /* These pseudo-ops should be defined by the object file format.
1081 However, a.out doesn't support them, so we have versions here. */
1082 {"aent", s_mips_ent
, 1},
1083 {"bgnb", s_ignore
, 0},
1084 {"end", s_mips_end
, 0},
1085 {"endb", s_ignore
, 0},
1086 {"ent", s_mips_ent
, 0},
1087 {"file", s_mips_file
, 0},
1088 {"fmask", s_mips_mask
, 'F'},
1089 {"frame", s_mips_frame
, 0},
1090 {"loc", s_mips_loc
, 0},
1091 {"mask", s_mips_mask
, 'R'},
1092 {"verstamp", s_ignore
, 0},
1096 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1101 pop_insert (mips_pseudo_table
);
1102 if (! ECOFF_DEBUGGING
)
1103 pop_insert (mips_nonecoff_pseudo_table
);
1106 /* Symbols labelling the current insn. */
1108 struct insn_label_list
1110 struct insn_label_list
*next
;
1114 static struct insn_label_list
*insn_labels
;
1115 static struct insn_label_list
*free_insn_labels
;
1117 static void mips_clear_insn_labels
PARAMS ((void));
1120 mips_clear_insn_labels ()
1122 register struct insn_label_list
**pl
;
1124 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1130 static char *expr_end
;
1132 /* Expressions which appear in instructions. These are set by
1135 static expressionS imm_expr
;
1136 static expressionS offset_expr
;
1138 /* Relocs associated with imm_expr and offset_expr. */
1140 static bfd_reloc_code_real_type imm_reloc
[3]
1141 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1142 static bfd_reloc_code_real_type offset_reloc
[3]
1143 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1145 /* These are set by mips16_ip if an explicit extension is used. */
1147 static bfd_boolean mips16_small
, mips16_ext
;
1150 /* The pdr segment for per procedure frame/regmask info. Not used for
1153 static segT pdr_seg
;
1156 /* The default target format to use. */
1159 mips_target_format ()
1161 switch (OUTPUT_FLAVOR
)
1163 case bfd_target_aout_flavour
:
1164 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1165 case bfd_target_ecoff_flavour
:
1166 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1167 case bfd_target_coff_flavour
:
1169 case bfd_target_elf_flavour
:
1171 /* This is traditional mips. */
1172 return (target_big_endian
1173 ? (HAVE_64BIT_OBJECTS
1174 ? "elf64-tradbigmips"
1176 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1177 : (HAVE_64BIT_OBJECTS
1178 ? "elf64-tradlittlemips"
1180 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1182 return (target_big_endian
1183 ? (HAVE_64BIT_OBJECTS
1186 ? "elf32-nbigmips" : "elf32-bigmips"))
1187 : (HAVE_64BIT_OBJECTS
1188 ? "elf64-littlemips"
1190 ? "elf32-nlittlemips" : "elf32-littlemips")));
1198 /* This function is called once, at assembler startup time. It should
1199 set up all the tables, etc. that the MD part of the assembler will need. */
1204 register const char *retval
= NULL
;
1208 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1209 as_warn (_("Could not set architecture and machine"));
1211 op_hash
= hash_new ();
1213 for (i
= 0; i
< NUMOPCODES
;)
1215 const char *name
= mips_opcodes
[i
].name
;
1217 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1220 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1221 mips_opcodes
[i
].name
, retval
);
1222 /* Probably a memory allocation problem? Give up now. */
1223 as_fatal (_("Broken assembler. No assembly attempted."));
1227 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1229 if (!validate_mips_insn (&mips_opcodes
[i
]))
1234 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1237 mips16_op_hash
= hash_new ();
1240 while (i
< bfd_mips16_num_opcodes
)
1242 const char *name
= mips16_opcodes
[i
].name
;
1244 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1246 as_fatal (_("internal: can't hash `%s': %s"),
1247 mips16_opcodes
[i
].name
, retval
);
1250 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1251 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1252 != mips16_opcodes
[i
].match
))
1254 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1255 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1260 while (i
< bfd_mips16_num_opcodes
1261 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1265 as_fatal (_("Broken assembler. No assembly attempted."));
1267 /* We add all the general register names to the symbol table. This
1268 helps us detect invalid uses of them. */
1269 for (i
= 0; i
< 32; i
++)
1273 sprintf (buf
, "$%d", i
);
1274 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1275 &zero_address_frag
));
1277 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1278 &zero_address_frag
));
1279 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1280 &zero_address_frag
));
1281 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1282 &zero_address_frag
));
1283 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1284 &zero_address_frag
));
1285 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1286 &zero_address_frag
));
1287 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1288 &zero_address_frag
));
1289 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1290 &zero_address_frag
));
1291 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1292 &zero_address_frag
));
1293 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1294 &zero_address_frag
));
1296 /* If we don't add these register names to the symbol table, they
1297 may end up being added as regular symbols by operand(), and then
1298 make it to the object file as undefined in case they're not
1299 regarded as local symbols. They're local in o32, since `$' is a
1300 local symbol prefix, but not in n32 or n64. */
1301 for (i
= 0; i
< 8; i
++)
1305 sprintf (buf
, "$fcc%i", i
);
1306 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1307 &zero_address_frag
));
1310 mips_no_prev_insn (FALSE
);
1313 mips_cprmask
[0] = 0;
1314 mips_cprmask
[1] = 0;
1315 mips_cprmask
[2] = 0;
1316 mips_cprmask
[3] = 0;
1318 /* set the default alignment for the text section (2**2) */
1319 record_alignment (text_section
, 2);
1321 if (USE_GLOBAL_POINTER_OPT
)
1322 bfd_set_gp_size (stdoutput
, g_switch_value
);
1324 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1326 /* On a native system, sections must be aligned to 16 byte
1327 boundaries. When configured for an embedded ELF target, we
1329 if (strcmp (TARGET_OS
, "elf") != 0)
1331 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1332 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1333 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1336 /* Create a .reginfo section for register masks and a .mdebug
1337 section for debugging information. */
1345 subseg
= now_subseg
;
1347 /* The ABI says this section should be loaded so that the
1348 running program can access it. However, we don't load it
1349 if we are configured for an embedded target */
1350 flags
= SEC_READONLY
| SEC_DATA
;
1351 if (strcmp (TARGET_OS
, "elf") != 0)
1352 flags
|= SEC_ALLOC
| SEC_LOAD
;
1354 if (mips_abi
!= N64_ABI
)
1356 sec
= subseg_new (".reginfo", (subsegT
) 0);
1358 bfd_set_section_flags (stdoutput
, sec
, flags
);
1359 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1362 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1367 /* The 64-bit ABI uses a .MIPS.options section rather than
1368 .reginfo section. */
1369 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1370 bfd_set_section_flags (stdoutput
, sec
, flags
);
1371 bfd_set_section_alignment (stdoutput
, sec
, 3);
1374 /* Set up the option header. */
1376 Elf_Internal_Options opthdr
;
1379 opthdr
.kind
= ODK_REGINFO
;
1380 opthdr
.size
= (sizeof (Elf_External_Options
)
1381 + sizeof (Elf64_External_RegInfo
));
1384 f
= frag_more (sizeof (Elf_External_Options
));
1385 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1386 (Elf_External_Options
*) f
);
1388 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1393 if (ECOFF_DEBUGGING
)
1395 sec
= subseg_new (".mdebug", (subsegT
) 0);
1396 (void) bfd_set_section_flags (stdoutput
, sec
,
1397 SEC_HAS_CONTENTS
| SEC_READONLY
);
1398 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1401 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1403 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1404 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1405 SEC_READONLY
| SEC_RELOC
1407 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1411 subseg_set (seg
, subseg
);
1415 if (! ECOFF_DEBUGGING
)
1422 if (! ECOFF_DEBUGGING
)
1430 struct mips_cl_insn insn
;
1431 bfd_reloc_code_real_type unused_reloc
[3]
1432 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1434 imm_expr
.X_op
= O_absent
;
1435 offset_expr
.X_op
= O_absent
;
1436 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1437 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1438 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1439 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1440 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1441 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1443 if (mips_opts
.mips16
)
1444 mips16_ip (str
, &insn
);
1447 mips_ip (str
, &insn
);
1448 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1449 str
, insn
.insn_opcode
));
1454 as_bad ("%s `%s'", insn_error
, str
);
1458 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1460 if (mips_opts
.mips16
)
1461 mips16_macro (&insn
);
1467 if (imm_expr
.X_op
!= O_absent
)
1468 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1469 else if (offset_expr
.X_op
!= O_absent
)
1470 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1472 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1476 /* Return true if the given relocation might need a matching %lo().
1477 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1478 applied to local symbols. */
1480 static inline bfd_boolean
1481 reloc_needs_lo_p (reloc
)
1482 bfd_reloc_code_real_type reloc
;
1484 return (reloc
== BFD_RELOC_HI16_S
1485 || reloc
== BFD_RELOC_MIPS_GOT16
);
1488 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1491 static inline bfd_boolean
1492 fixup_has_matching_lo_p (fixp
)
1495 return (fixp
->fx_next
!= NULL
1496 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1497 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1498 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1501 /* See whether instruction IP reads register REG. CLASS is the type
1505 insn_uses_reg (ip
, reg
, class)
1506 struct mips_cl_insn
*ip
;
1508 enum mips_regclass
class;
1510 if (class == MIPS16_REG
)
1512 assert (mips_opts
.mips16
);
1513 reg
= mips16_to_32_reg_map
[reg
];
1514 class = MIPS_GR_REG
;
1517 /* Don't report on general register ZERO, since it never changes. */
1518 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1521 if (class == MIPS_FP_REG
)
1523 assert (! mips_opts
.mips16
);
1524 /* If we are called with either $f0 or $f1, we must check $f0.
1525 This is not optimal, because it will introduce an unnecessary
1526 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1527 need to distinguish reading both $f0 and $f1 or just one of
1528 them. Note that we don't have to check the other way,
1529 because there is no instruction that sets both $f0 and $f1
1530 and requires a delay. */
1531 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1532 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1533 == (reg
&~ (unsigned) 1)))
1535 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1536 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1537 == (reg
&~ (unsigned) 1)))
1540 else if (! mips_opts
.mips16
)
1542 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1543 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1545 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1546 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1551 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1552 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1553 & MIPS16OP_MASK_RX
)]
1556 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1557 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1558 & MIPS16OP_MASK_RY
)]
1561 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1562 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1563 & MIPS16OP_MASK_MOVE32Z
)]
1566 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1568 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1570 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1572 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1573 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1574 & MIPS16OP_MASK_REGR32
) == reg
)
1581 /* This function returns true if modifying a register requires a
1585 reg_needs_delay (reg
)
1588 unsigned long prev_pinfo
;
1590 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1591 if (! mips_opts
.noreorder
1592 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1593 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1594 || (! gpr_interlocks
1595 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1597 /* A load from a coprocessor or from memory. All load
1598 delays delay the use of general register rt for one
1599 instruction on the r3000. The r6000 and r4000 use
1601 /* Itbl support may require additional care here. */
1602 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1603 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1610 /* Mark instruction labels in mips16 mode. This permits the linker to
1611 handle them specially, such as generating jalx instructions when
1612 needed. We also make them odd for the duration of the assembly, in
1613 order to generate the right sort of code. We will make them even
1614 in the adjust_symtab routine, while leaving them marked. This is
1615 convenient for the debugger and the disassembler. The linker knows
1616 to make them odd again. */
1619 mips16_mark_labels ()
1621 if (mips_opts
.mips16
)
1623 struct insn_label_list
*l
;
1626 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1629 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1630 S_SET_OTHER (l
->label
, STO_MIPS16
);
1632 val
= S_GET_VALUE (l
->label
);
1634 S_SET_VALUE (l
->label
, val
+ 1);
1639 /* Output an instruction. PLACE is where to put the instruction; if
1640 it is NULL, this uses frag_more to get room. IP is the instruction
1641 information. ADDRESS_EXPR is an operand of the instruction to be
1642 used with RELOC_TYPE. */
1645 append_insn (place
, ip
, address_expr
, reloc_type
)
1647 struct mips_cl_insn
*ip
;
1648 expressionS
*address_expr
;
1649 bfd_reloc_code_real_type
*reloc_type
;
1651 register unsigned long prev_pinfo
, pinfo
;
1655 bfd_boolean force_new_frag
= FALSE
;
1657 /* Mark instruction labels in mips16 mode. */
1658 mips16_mark_labels ();
1660 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1661 pinfo
= ip
->insn_mo
->pinfo
;
1663 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1667 /* If the previous insn required any delay slots, see if we need
1668 to insert a NOP or two. There are eight kinds of possible
1669 hazards, of which an instruction can have at most one type.
1670 (1) a load from memory delay
1671 (2) a load from a coprocessor delay
1672 (3) an unconditional branch delay
1673 (4) a conditional branch delay
1674 (5) a move to coprocessor register delay
1675 (6) a load coprocessor register from memory delay
1676 (7) a coprocessor condition code delay
1677 (8) a HI/LO special register delay
1679 There are a lot of optimizations we could do that we don't.
1680 In particular, we do not, in general, reorder instructions.
1681 If you use gcc with optimization, it will reorder
1682 instructions and generally do much more optimization then we
1683 do here; repeating all that work in the assembler would only
1684 benefit hand written assembly code, and does not seem worth
1687 /* This is how a NOP is emitted. */
1688 #define emit_nop() \
1690 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1691 : md_number_to_chars (frag_more (4), 0, 4))
1693 /* The previous insn might require a delay slot, depending upon
1694 the contents of the current insn. */
1695 if (! mips_opts
.mips16
1696 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1697 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1698 && ! cop_interlocks
)
1699 || (! gpr_interlocks
1700 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1702 /* A load from a coprocessor or from memory. All load
1703 delays delay the use of general register rt for one
1704 instruction on the r3000. The r6000 and r4000 use
1706 /* Itbl support may require additional care here. */
1707 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1708 if (mips_optimize
== 0
1709 || insn_uses_reg (ip
,
1710 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1715 else if (! mips_opts
.mips16
1716 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1717 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1718 && ! cop_interlocks
)
1719 || (mips_opts
.isa
== ISA_MIPS1
1720 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1722 /* A generic coprocessor delay. The previous instruction
1723 modified a coprocessor general or control register. If
1724 it modified a control register, we need to avoid any
1725 coprocessor instruction (this is probably not always
1726 required, but it sometimes is). If it modified a general
1727 register, we avoid using that register.
1729 On the r6000 and r4000 loading a coprocessor register
1730 from memory is interlocked, and does not require a delay.
1732 This case is not handled very well. There is no special
1733 knowledge of CP0 handling, and the coprocessors other
1734 than the floating point unit are not distinguished at
1736 /* Itbl support may require additional care here. FIXME!
1737 Need to modify this to include knowledge about
1738 user specified delays! */
1739 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1741 if (mips_optimize
== 0
1742 || insn_uses_reg (ip
,
1743 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1748 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1750 if (mips_optimize
== 0
1751 || insn_uses_reg (ip
,
1752 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1759 /* We don't know exactly what the previous instruction
1760 does. If the current instruction uses a coprocessor
1761 register, we must insert a NOP. If previous
1762 instruction may set the condition codes, and the
1763 current instruction uses them, we must insert two
1765 /* Itbl support may require additional care here. */
1766 if (mips_optimize
== 0
1767 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1768 && (pinfo
& INSN_READ_COND_CODE
)))
1770 else if (pinfo
& INSN_COP
)
1774 else if (! mips_opts
.mips16
1775 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1776 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1777 && ! cop_interlocks
)
1779 /* The previous instruction sets the coprocessor condition
1780 codes, but does not require a general coprocessor delay
1781 (this means it is a floating point comparison
1782 instruction). If this instruction uses the condition
1783 codes, we need to insert a single NOP. */
1784 /* Itbl support may require additional care here. */
1785 if (mips_optimize
== 0
1786 || (pinfo
& INSN_READ_COND_CODE
))
1790 /* If we're fixing up mfhi/mflo for the r7000 and the
1791 previous insn was an mfhi/mflo and the current insn
1792 reads the register that the mfhi/mflo wrote to, then
1795 else if (mips_7000_hilo_fix
1796 && MF_HILO_INSN (prev_pinfo
)
1797 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1804 /* If we're fixing up mfhi/mflo for the r7000 and the
1805 2nd previous insn was an mfhi/mflo and the current insn
1806 reads the register that the mfhi/mflo wrote to, then
1809 else if (mips_7000_hilo_fix
1810 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1811 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1819 else if (prev_pinfo
& INSN_READ_LO
)
1821 /* The previous instruction reads the LO register; if the
1822 current instruction writes to the LO register, we must
1823 insert two NOPS. Some newer processors have interlocks.
1824 Also the tx39's multiply instructions can be exectuted
1825 immediatly after a read from HI/LO (without the delay),
1826 though the tx39's divide insns still do require the
1828 if (! (hilo_interlocks
1829 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1830 && (mips_optimize
== 0
1831 || (pinfo
& INSN_WRITE_LO
)))
1833 /* Most mips16 branch insns don't have a delay slot.
1834 If a read from LO is immediately followed by a branch
1835 to a write to LO we have a read followed by a write
1836 less than 2 insns away. We assume the target of
1837 a branch might be a write to LO, and insert a nop
1838 between a read and an immediately following branch. */
1839 else if (mips_opts
.mips16
1840 && (mips_optimize
== 0
1841 || (pinfo
& MIPS16_INSN_BRANCH
)))
1844 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1846 /* The previous instruction reads the HI register; if the
1847 current instruction writes to the HI register, we must
1848 insert a NOP. Some newer processors have interlocks.
1849 Also the note tx39's multiply above. */
1850 if (! (hilo_interlocks
1851 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1852 && (mips_optimize
== 0
1853 || (pinfo
& INSN_WRITE_HI
)))
1855 /* Most mips16 branch insns don't have a delay slot.
1856 If a read from HI is immediately followed by a branch
1857 to a write to HI we have a read followed by a write
1858 less than 2 insns away. We assume the target of
1859 a branch might be a write to HI, and insert a nop
1860 between a read and an immediately following branch. */
1861 else if (mips_opts
.mips16
1862 && (mips_optimize
== 0
1863 || (pinfo
& MIPS16_INSN_BRANCH
)))
1867 /* If the previous instruction was in a noreorder section, then
1868 we don't want to insert the nop after all. */
1869 /* Itbl support may require additional care here. */
1870 if (prev_insn_unreordered
)
1873 /* There are two cases which require two intervening
1874 instructions: 1) setting the condition codes using a move to
1875 coprocessor instruction which requires a general coprocessor
1876 delay and then reading the condition codes 2) reading the HI
1877 or LO register and then writing to it (except on processors
1878 which have interlocks). If we are not already emitting a NOP
1879 instruction, we must check for these cases compared to the
1880 instruction previous to the previous instruction. */
1881 if ((! mips_opts
.mips16
1882 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1883 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1884 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1885 && (pinfo
& INSN_READ_COND_CODE
)
1886 && ! cop_interlocks
)
1887 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1888 && (pinfo
& INSN_WRITE_LO
)
1889 && ! (hilo_interlocks
1890 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1891 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1892 && (pinfo
& INSN_WRITE_HI
)
1893 && ! (hilo_interlocks
1894 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1899 if (prev_prev_insn_unreordered
)
1902 if (prev_prev_nop
&& nops
== 0)
1905 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1907 /* We're out of bits in pinfo, so we must resort to string
1908 ops here. Shortcuts are selected based on opcodes being
1909 limited to the VR4122 instruction set. */
1911 const char *pn
= prev_insn
.insn_mo
->name
;
1912 const char *tn
= ip
->insn_mo
->name
;
1913 if (strncmp(pn
, "macc", 4) == 0
1914 || strncmp(pn
, "dmacc", 5) == 0)
1916 /* Errata 21 - [D]DIV[U] after [D]MACC */
1917 if (strstr (tn
, "div"))
1922 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1923 if (pn
[0] == 'd' /* dmacc */
1924 && (strncmp(tn
, "dmult", 5) == 0
1925 || strncmp(tn
, "dmacc", 5) == 0))
1930 /* Errata 24 - MT{LO,HI} after [D]MACC */
1931 if (strcmp (tn
, "mtlo") == 0
1932 || strcmp (tn
, "mthi") == 0)
1938 else if (strncmp(pn
, "dmult", 5) == 0
1939 && (strncmp(tn
, "dmult", 5) == 0
1940 || strncmp(tn
, "dmacc", 5) == 0))
1942 /* Here is the rest of errata 23. */
1945 if (nops
< min_nops
)
1949 /* If we are being given a nop instruction, don't bother with
1950 one of the nops we would otherwise output. This will only
1951 happen when a nop instruction is used with mips_optimize set
1954 && ! mips_opts
.noreorder
1955 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1958 /* Now emit the right number of NOP instructions. */
1959 if (nops
> 0 && ! mips_opts
.noreorder
)
1962 unsigned long old_frag_offset
;
1964 struct insn_label_list
*l
;
1966 old_frag
= frag_now
;
1967 old_frag_offset
= frag_now_fix ();
1969 for (i
= 0; i
< nops
; i
++)
1974 listing_prev_line ();
1975 /* We may be at the start of a variant frag. In case we
1976 are, make sure there is enough space for the frag
1977 after the frags created by listing_prev_line. The
1978 argument to frag_grow here must be at least as large
1979 as the argument to all other calls to frag_grow in
1980 this file. We don't have to worry about being in the
1981 middle of a variant frag, because the variants insert
1982 all needed nop instructions themselves. */
1986 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1990 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1991 symbol_set_frag (l
->label
, frag_now
);
1992 val
= (valueT
) frag_now_fix ();
1993 /* mips16 text labels are stored as odd. */
1994 if (mips_opts
.mips16
)
1996 S_SET_VALUE (l
->label
, val
);
1999 #ifndef NO_ECOFF_DEBUGGING
2000 if (ECOFF_DEBUGGING
)
2001 ecoff_fix_loc (old_frag
, old_frag_offset
);
2004 else if (prev_nop_frag
!= NULL
)
2006 /* We have a frag holding nops we may be able to remove. If
2007 we don't need any nops, we can decrease the size of
2008 prev_nop_frag by the size of one instruction. If we do
2009 need some nops, we count them in prev_nops_required. */
2010 if (prev_nop_frag_since
== 0)
2014 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2015 --prev_nop_frag_holds
;
2018 prev_nop_frag_required
+= nops
;
2022 if (prev_prev_nop
== 0)
2024 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2025 --prev_nop_frag_holds
;
2028 ++prev_nop_frag_required
;
2031 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2032 prev_nop_frag
= NULL
;
2034 ++prev_nop_frag_since
;
2036 /* Sanity check: by the time we reach the second instruction
2037 after prev_nop_frag, we should have used up all the nops
2038 one way or another. */
2039 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2045 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2046 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2047 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2048 && mips_relax_branch
2049 /* Don't try branch relaxation within .set nomacro, or within
2050 .set noat if we use $at for PIC computations. If it turns
2051 out that the branch was out-of-range, we'll get an error. */
2052 && !mips_opts
.warn_about_macros
2053 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2054 && !mips_opts
.mips16
)
2056 f
= frag_var (rs_machine_dependent
,
2057 relaxed_branch_length
2059 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2060 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2062 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2063 pinfo
& INSN_COND_BRANCH_LIKELY
,
2064 pinfo
& INSN_WRITE_GPR_31
,
2066 address_expr
->X_add_symbol
,
2067 address_expr
->X_add_number
,
2069 *reloc_type
= BFD_RELOC_UNUSED
;
2071 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2073 /* We need to set up a variant frag. */
2074 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2075 f
= frag_var (rs_machine_dependent
, 4, 0,
2076 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2077 mips16_small
, mips16_ext
,
2079 & INSN_UNCOND_BRANCH_DELAY
),
2080 (*prev_insn_reloc_type
2081 == BFD_RELOC_MIPS16_JMP
)),
2082 make_expr_symbol (address_expr
), 0, NULL
);
2084 else if (place
!= NULL
)
2086 else if (mips_opts
.mips16
2088 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2090 /* Make sure there is enough room to swap this instruction with
2091 a following jump instruction. */
2097 if (mips_opts
.mips16
2098 && mips_opts
.noreorder
2099 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2100 as_warn (_("extended instruction in delay slot"));
2105 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2106 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2108 if (address_expr
->X_op
== O_constant
)
2112 switch (*reloc_type
)
2115 ip
->insn_opcode
|= address_expr
->X_add_number
;
2118 case BFD_RELOC_MIPS_HIGHEST
:
2119 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2121 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2124 case BFD_RELOC_MIPS_HIGHER
:
2125 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2126 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2129 case BFD_RELOC_HI16_S
:
2130 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2134 case BFD_RELOC_HI16
:
2135 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2138 case BFD_RELOC_LO16
:
2139 case BFD_RELOC_MIPS_GOT_DISP
:
2140 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2143 case BFD_RELOC_MIPS_JMP
:
2144 if ((address_expr
->X_add_number
& 3) != 0)
2145 as_bad (_("jump to misaligned address (0x%lx)"),
2146 (unsigned long) address_expr
->X_add_number
);
2147 if (address_expr
->X_add_number
& ~0xfffffff)
2148 as_bad (_("jump address range overflow (0x%lx)"),
2149 (unsigned long) address_expr
->X_add_number
);
2150 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2153 case BFD_RELOC_MIPS16_JMP
:
2154 if ((address_expr
->X_add_number
& 3) != 0)
2155 as_bad (_("jump to misaligned address (0x%lx)"),
2156 (unsigned long) address_expr
->X_add_number
);
2157 if (address_expr
->X_add_number
& ~0xfffffff)
2158 as_bad (_("jump address range overflow (0x%lx)"),
2159 (unsigned long) address_expr
->X_add_number
);
2161 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2162 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2163 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2166 case BFD_RELOC_16_PCREL_S2
:
2176 /* Don't generate a reloc if we are writing into a variant frag. */
2179 reloc_howto_type
*howto
;
2182 /* In a compound relocation, it is the final (outermost)
2183 operator that determines the relocated field. */
2184 for (i
= 1; i
< 3; i
++)
2185 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2188 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2189 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2190 bfd_get_reloc_size(howto
),
2192 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2195 /* These relocations can have an addend that won't fit in
2196 4 octets for 64bit assembly. */
2198 && ! howto
->partial_inplace
2199 && (reloc_type
[0] == BFD_RELOC_16
2200 || reloc_type
[0] == BFD_RELOC_32
2201 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2202 || reloc_type
[0] == BFD_RELOC_HI16_S
2203 || reloc_type
[0] == BFD_RELOC_LO16
2204 || reloc_type
[0] == BFD_RELOC_GPREL16
2205 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2206 || reloc_type
[0] == BFD_RELOC_GPREL32
2207 || reloc_type
[0] == BFD_RELOC_64
2208 || reloc_type
[0] == BFD_RELOC_CTOR
2209 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2210 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2211 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2212 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2213 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2214 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2215 fixp
[0]->fx_no_overflow
= 1;
2217 if (reloc_needs_lo_p (*reloc_type
))
2219 struct mips_hi_fixup
*hi_fixup
;
2221 /* Reuse the last entry if it already has a matching %lo. */
2222 hi_fixup
= mips_hi_fixup_list
;
2224 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2226 hi_fixup
= ((struct mips_hi_fixup
*)
2227 xmalloc (sizeof (struct mips_hi_fixup
)));
2228 hi_fixup
->next
= mips_hi_fixup_list
;
2229 mips_hi_fixup_list
= hi_fixup
;
2231 hi_fixup
->fixp
= fixp
[0];
2232 hi_fixup
->seg
= now_seg
;
2235 /* Add fixups for the second and third relocations, if given.
2236 Note that the ABI allows the second relocation to be
2237 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2238 moment we only use RSS_UNDEF, but we could add support
2239 for the others if it ever becomes necessary. */
2240 for (i
= 1; i
< 3; i
++)
2241 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2243 address_expr
->X_op
= O_absent
;
2244 address_expr
->X_add_symbol
= 0;
2245 address_expr
->X_add_number
= 0;
2247 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2248 fixp
[0]->fx_size
, address_expr
,
2249 FALSE
, reloc_type
[i
]);
2255 if (! mips_opts
.mips16
)
2257 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2259 dwarf2_emit_insn (4);
2262 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2264 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2265 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2267 dwarf2_emit_insn (4);
2274 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2277 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2279 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2283 /* Update the register mask information. */
2284 if (! mips_opts
.mips16
)
2286 if (pinfo
& INSN_WRITE_GPR_D
)
2287 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2288 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2289 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2290 if (pinfo
& INSN_READ_GPR_S
)
2291 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2292 if (pinfo
& INSN_WRITE_GPR_31
)
2293 mips_gprmask
|= 1 << RA
;
2294 if (pinfo
& INSN_WRITE_FPR_D
)
2295 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2296 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2297 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2298 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2299 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2300 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2301 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2302 if (pinfo
& INSN_COP
)
2304 /* We don't keep enough information to sort these cases out.
2305 The itbl support does keep this information however, although
2306 we currently don't support itbl fprmats as part of the cop
2307 instruction. May want to add this support in the future. */
2309 /* Never set the bit for $0, which is always zero. */
2310 mips_gprmask
&= ~1 << 0;
2314 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2315 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2316 & MIPS16OP_MASK_RX
);
2317 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2318 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2319 & MIPS16OP_MASK_RY
);
2320 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2321 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2322 & MIPS16OP_MASK_RZ
);
2323 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2324 mips_gprmask
|= 1 << TREG
;
2325 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2326 mips_gprmask
|= 1 << SP
;
2327 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2328 mips_gprmask
|= 1 << RA
;
2329 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2330 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2331 if (pinfo
& MIPS16_INSN_READ_Z
)
2332 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2333 & MIPS16OP_MASK_MOVE32Z
);
2334 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2335 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2336 & MIPS16OP_MASK_REGR32
);
2339 if (place
== NULL
&& ! mips_opts
.noreorder
)
2341 /* Filling the branch delay slot is more complex. We try to
2342 switch the branch with the previous instruction, which we can
2343 do if the previous instruction does not set up a condition
2344 that the branch tests and if the branch is not itself the
2345 target of any branch. */
2346 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2347 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2349 if (mips_optimize
< 2
2350 /* If we have seen .set volatile or .set nomove, don't
2352 || mips_opts
.nomove
!= 0
2353 /* If we had to emit any NOP instructions, then we
2354 already know we can not swap. */
2356 /* If we don't even know the previous insn, we can not
2358 || ! prev_insn_valid
2359 /* If the previous insn is already in a branch delay
2360 slot, then we can not swap. */
2361 || prev_insn_is_delay_slot
2362 /* If the previous previous insn was in a .set
2363 noreorder, we can't swap. Actually, the MIPS
2364 assembler will swap in this situation. However, gcc
2365 configured -with-gnu-as will generate code like
2371 in which we can not swap the bne and INSN. If gcc is
2372 not configured -with-gnu-as, it does not output the
2373 .set pseudo-ops. We don't have to check
2374 prev_insn_unreordered, because prev_insn_valid will
2375 be 0 in that case. We don't want to use
2376 prev_prev_insn_valid, because we do want to be able
2377 to swap at the start of a function. */
2378 || prev_prev_insn_unreordered
2379 /* If the branch is itself the target of a branch, we
2380 can not swap. We cheat on this; all we check for is
2381 whether there is a label on this instruction. If
2382 there are any branches to anything other than a
2383 label, users must use .set noreorder. */
2384 || insn_labels
!= NULL
2385 /* If the previous instruction is in a variant frag, we
2386 can not do the swap. This does not apply to the
2387 mips16, which uses variant frags for different
2389 || (! mips_opts
.mips16
2390 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2391 /* If the branch reads the condition codes, we don't
2392 even try to swap, because in the sequence
2397 we can not swap, and I don't feel like handling that
2399 || (! mips_opts
.mips16
2400 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2401 && (pinfo
& INSN_READ_COND_CODE
))
2402 /* We can not swap with an instruction that requires a
2403 delay slot, becase the target of the branch might
2404 interfere with that instruction. */
2405 || (! mips_opts
.mips16
2406 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2408 /* Itbl support may require additional care here. */
2409 & (INSN_LOAD_COPROC_DELAY
2410 | INSN_COPROC_MOVE_DELAY
2411 | INSN_WRITE_COND_CODE
)))
2412 || (! (hilo_interlocks
2413 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2417 || (! mips_opts
.mips16
2419 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2420 || (! mips_opts
.mips16
2421 && mips_opts
.isa
== ISA_MIPS1
2422 /* Itbl support may require additional care here. */
2423 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2424 /* We can not swap with a branch instruction. */
2426 & (INSN_UNCOND_BRANCH_DELAY
2427 | INSN_COND_BRANCH_DELAY
2428 | INSN_COND_BRANCH_LIKELY
))
2429 /* We do not swap with a trap instruction, since it
2430 complicates trap handlers to have the trap
2431 instruction be in a delay slot. */
2432 || (prev_pinfo
& INSN_TRAP
)
2433 /* If the branch reads a register that the previous
2434 instruction sets, we can not swap. */
2435 || (! mips_opts
.mips16
2436 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2437 && insn_uses_reg (ip
,
2438 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2441 || (! mips_opts
.mips16
2442 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2443 && insn_uses_reg (ip
,
2444 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2447 || (mips_opts
.mips16
2448 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2449 && insn_uses_reg (ip
,
2450 ((prev_insn
.insn_opcode
2452 & MIPS16OP_MASK_RX
),
2454 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2455 && insn_uses_reg (ip
,
2456 ((prev_insn
.insn_opcode
2458 & MIPS16OP_MASK_RY
),
2460 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2461 && insn_uses_reg (ip
,
2462 ((prev_insn
.insn_opcode
2464 & MIPS16OP_MASK_RZ
),
2466 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2467 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2468 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2469 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2470 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2471 && insn_uses_reg (ip
,
2472 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2475 /* If the branch writes a register that the previous
2476 instruction sets, we can not swap (we know that
2477 branches write only to RD or to $31). */
2478 || (! mips_opts
.mips16
2479 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2480 && (((pinfo
& INSN_WRITE_GPR_D
)
2481 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2482 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2483 || ((pinfo
& INSN_WRITE_GPR_31
)
2484 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2487 || (! mips_opts
.mips16
2488 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2489 && (((pinfo
& INSN_WRITE_GPR_D
)
2490 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2491 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2492 || ((pinfo
& INSN_WRITE_GPR_31
)
2493 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2496 || (mips_opts
.mips16
2497 && (pinfo
& MIPS16_INSN_WRITE_31
)
2498 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2499 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2500 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2502 /* If the branch writes a register that the previous
2503 instruction reads, we can not swap (we know that
2504 branches only write to RD or to $31). */
2505 || (! mips_opts
.mips16
2506 && (pinfo
& INSN_WRITE_GPR_D
)
2507 && insn_uses_reg (&prev_insn
,
2508 ((ip
->insn_opcode
>> OP_SH_RD
)
2511 || (! mips_opts
.mips16
2512 && (pinfo
& INSN_WRITE_GPR_31
)
2513 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2514 || (mips_opts
.mips16
2515 && (pinfo
& MIPS16_INSN_WRITE_31
)
2516 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2517 /* If we are generating embedded PIC code, the branch
2518 might be expanded into a sequence which uses $at, so
2519 we can't swap with an instruction which reads it. */
2520 || (mips_pic
== EMBEDDED_PIC
2521 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2522 /* If the previous previous instruction has a load
2523 delay, and sets a register that the branch reads, we
2525 || (! mips_opts
.mips16
2526 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2527 /* Itbl support may require additional care here. */
2528 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2529 || (! gpr_interlocks
2530 && (prev_prev_insn
.insn_mo
->pinfo
2531 & INSN_LOAD_MEMORY_DELAY
)))
2532 && insn_uses_reg (ip
,
2533 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2536 /* If one instruction sets a condition code and the
2537 other one uses a condition code, we can not swap. */
2538 || ((pinfo
& INSN_READ_COND_CODE
)
2539 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2540 || ((pinfo
& INSN_WRITE_COND_CODE
)
2541 && (prev_pinfo
& INSN_READ_COND_CODE
))
2542 /* If the previous instruction uses the PC, we can not
2544 || (mips_opts
.mips16
2545 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2546 /* If the previous instruction was extended, we can not
2548 || (mips_opts
.mips16
&& prev_insn_extended
)
2549 /* If the previous instruction had a fixup in mips16
2550 mode, we can not swap. This normally means that the
2551 previous instruction was a 4 byte branch anyhow. */
2552 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2553 /* If the previous instruction is a sync, sync.l, or
2554 sync.p, we can not swap. */
2555 || (prev_pinfo
& INSN_SYNC
))
2557 /* We could do even better for unconditional branches to
2558 portions of this object file; we could pick up the
2559 instruction at the destination, put it in the delay
2560 slot, and bump the destination address. */
2562 /* Update the previous insn information. */
2563 prev_prev_insn
= *ip
;
2564 prev_insn
.insn_mo
= &dummy_opcode
;
2568 /* It looks like we can actually do the swap. */
2569 if (! mips_opts
.mips16
)
2574 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2575 memcpy (temp
, prev_f
, 4);
2576 memcpy (prev_f
, f
, 4);
2577 memcpy (f
, temp
, 4);
2578 if (prev_insn_fixp
[0])
2580 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2581 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2583 if (prev_insn_fixp
[1])
2585 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2586 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2588 if (prev_insn_fixp
[2])
2590 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2591 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2593 if (prev_insn_fixp
[0] && HAVE_NEWABI
2594 && prev_insn_frag
!= frag_now
2595 && (prev_insn_fixp
[0]->fx_r_type
2596 == BFD_RELOC_MIPS_GOT_DISP
2597 || (prev_insn_fixp
[0]->fx_r_type
2598 == BFD_RELOC_MIPS_CALL16
)))
2600 /* To avoid confusion in tc_gen_reloc, we must
2601 ensure that this does not become a variant
2603 force_new_frag
= TRUE
;
2607 fixp
[0]->fx_frag
= prev_insn_frag
;
2608 fixp
[0]->fx_where
= prev_insn_where
;
2612 fixp
[1]->fx_frag
= prev_insn_frag
;
2613 fixp
[1]->fx_where
= prev_insn_where
;
2617 fixp
[2]->fx_frag
= prev_insn_frag
;
2618 fixp
[2]->fx_where
= prev_insn_where
;
2626 assert (prev_insn_fixp
[0] == NULL
);
2627 assert (prev_insn_fixp
[1] == NULL
);
2628 assert (prev_insn_fixp
[2] == NULL
);
2629 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2630 memcpy (temp
, prev_f
, 2);
2631 memcpy (prev_f
, f
, 2);
2632 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2634 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2635 memcpy (f
, temp
, 2);
2639 memcpy (f
, f
+ 2, 2);
2640 memcpy (f
+ 2, temp
, 2);
2644 fixp
[0]->fx_frag
= prev_insn_frag
;
2645 fixp
[0]->fx_where
= prev_insn_where
;
2649 fixp
[1]->fx_frag
= prev_insn_frag
;
2650 fixp
[1]->fx_where
= prev_insn_where
;
2654 fixp
[2]->fx_frag
= prev_insn_frag
;
2655 fixp
[2]->fx_where
= prev_insn_where
;
2659 /* Update the previous insn information; leave prev_insn
2661 prev_prev_insn
= *ip
;
2663 prev_insn_is_delay_slot
= 1;
2665 /* If that was an unconditional branch, forget the previous
2666 insn information. */
2667 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2669 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2670 prev_insn
.insn_mo
= &dummy_opcode
;
2673 prev_insn_fixp
[0] = NULL
;
2674 prev_insn_fixp
[1] = NULL
;
2675 prev_insn_fixp
[2] = NULL
;
2676 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2677 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2678 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2679 prev_insn_extended
= 0;
2681 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2683 /* We don't yet optimize a branch likely. What we should do
2684 is look at the target, copy the instruction found there
2685 into the delay slot, and increment the branch to jump to
2686 the next instruction. */
2688 /* Update the previous insn information. */
2689 prev_prev_insn
= *ip
;
2690 prev_insn
.insn_mo
= &dummy_opcode
;
2691 prev_insn_fixp
[0] = NULL
;
2692 prev_insn_fixp
[1] = NULL
;
2693 prev_insn_fixp
[2] = NULL
;
2694 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2695 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2696 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2697 prev_insn_extended
= 0;
2701 /* Update the previous insn information. */
2703 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2705 prev_prev_insn
= prev_insn
;
2708 /* Any time we see a branch, we always fill the delay slot
2709 immediately; since this insn is not a branch, we know it
2710 is not in a delay slot. */
2711 prev_insn_is_delay_slot
= 0;
2713 prev_insn_fixp
[0] = fixp
[0];
2714 prev_insn_fixp
[1] = fixp
[1];
2715 prev_insn_fixp
[2] = fixp
[2];
2716 prev_insn_reloc_type
[0] = reloc_type
[0];
2717 prev_insn_reloc_type
[1] = reloc_type
[1];
2718 prev_insn_reloc_type
[2] = reloc_type
[2];
2719 if (mips_opts
.mips16
)
2720 prev_insn_extended
= (ip
->use_extend
2721 || *reloc_type
> BFD_RELOC_UNUSED
);
2724 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2725 prev_insn_unreordered
= 0;
2726 prev_insn_frag
= frag_now
;
2727 prev_insn_where
= f
- frag_now
->fr_literal
;
2728 prev_insn_valid
= 1;
2730 else if (place
== NULL
)
2732 /* We need to record a bit of information even when we are not
2733 reordering, in order to determine the base address for mips16
2734 PC relative relocs. */
2735 prev_prev_insn
= prev_insn
;
2737 prev_insn_reloc_type
[0] = reloc_type
[0];
2738 prev_insn_reloc_type
[1] = reloc_type
[1];
2739 prev_insn_reloc_type
[2] = reloc_type
[2];
2740 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2741 prev_insn_unreordered
= 1;
2744 /* We just output an insn, so the next one doesn't have a label. */
2745 mips_clear_insn_labels ();
2747 /* We must ensure that the frag to which an instruction that was
2748 moved from a non-variant frag doesn't become a variant frag,
2749 otherwise tc_gen_reloc may get confused. */
2752 frag_wane (frag_now
);
2757 /* This function forgets that there was any previous instruction or
2758 label. If PRESERVE is non-zero, it remembers enough information to
2759 know whether nops are needed before a noreorder section. */
2762 mips_no_prev_insn (preserve
)
2767 prev_insn
.insn_mo
= &dummy_opcode
;
2768 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2769 prev_nop_frag
= NULL
;
2770 prev_nop_frag_holds
= 0;
2771 prev_nop_frag_required
= 0;
2772 prev_nop_frag_since
= 0;
2774 prev_insn_valid
= 0;
2775 prev_insn_is_delay_slot
= 0;
2776 prev_insn_unreordered
= 0;
2777 prev_insn_extended
= 0;
2778 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2779 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2780 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2781 prev_prev_insn_unreordered
= 0;
2782 mips_clear_insn_labels ();
2785 /* This function must be called whenever we turn on noreorder or emit
2786 something other than instructions. It inserts any NOPS which might
2787 be needed by the previous instruction, and clears the information
2788 kept for the previous instructions. The INSNS parameter is true if
2789 instructions are to follow. */
2792 mips_emit_delays (insns
)
2795 if (! mips_opts
.noreorder
)
2800 if ((! mips_opts
.mips16
2801 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2802 && (! cop_interlocks
2803 && (prev_insn
.insn_mo
->pinfo
2804 & (INSN_LOAD_COPROC_DELAY
2805 | INSN_COPROC_MOVE_DELAY
2806 | INSN_WRITE_COND_CODE
))))
2807 || (! hilo_interlocks
2808 && (prev_insn
.insn_mo
->pinfo
2811 || (! mips_opts
.mips16
2813 && (prev_insn
.insn_mo
->pinfo
2814 & INSN_LOAD_MEMORY_DELAY
))
2815 || (! mips_opts
.mips16
2816 && mips_opts
.isa
== ISA_MIPS1
2817 && (prev_insn
.insn_mo
->pinfo
2818 & INSN_COPROC_MEMORY_DELAY
)))
2820 /* Itbl support may require additional care here. */
2822 if ((! mips_opts
.mips16
2823 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2824 && (! cop_interlocks
2825 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2826 || (! hilo_interlocks
2827 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2828 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2831 if (prev_insn_unreordered
)
2834 else if ((! mips_opts
.mips16
2835 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2836 && (! cop_interlocks
2837 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2838 || (! hilo_interlocks
2839 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2840 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2842 /* Itbl support may require additional care here. */
2843 if (! prev_prev_insn_unreordered
)
2847 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2850 const char *pn
= prev_insn
.insn_mo
->name
;
2851 if (strncmp(pn
, "macc", 4) == 0
2852 || strncmp(pn
, "dmacc", 5) == 0
2853 || strncmp(pn
, "dmult", 5) == 0)
2857 if (nops
< min_nops
)
2863 struct insn_label_list
*l
;
2867 /* Record the frag which holds the nop instructions, so
2868 that we can remove them if we don't need them. */
2869 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2870 prev_nop_frag
= frag_now
;
2871 prev_nop_frag_holds
= nops
;
2872 prev_nop_frag_required
= 0;
2873 prev_nop_frag_since
= 0;
2876 for (; nops
> 0; --nops
)
2881 /* Move on to a new frag, so that it is safe to simply
2882 decrease the size of prev_nop_frag. */
2883 frag_wane (frag_now
);
2887 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2891 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2892 symbol_set_frag (l
->label
, frag_now
);
2893 val
= (valueT
) frag_now_fix ();
2894 /* mips16 text labels are stored as odd. */
2895 if (mips_opts
.mips16
)
2897 S_SET_VALUE (l
->label
, val
);
2902 /* Mark instruction labels in mips16 mode. */
2904 mips16_mark_labels ();
2906 mips_no_prev_insn (insns
);
2909 /* Build an instruction created by a macro expansion. This is passed
2910 a pointer to the count of instructions created so far, an
2911 expression, the name of the instruction to build, an operand format
2912 string, and corresponding arguments. */
2916 macro_build (char *place
,
2924 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2933 struct mips_cl_insn insn
;
2934 bfd_reloc_code_real_type r
[3];
2938 va_start (args
, fmt
);
2944 * If the macro is about to expand into a second instruction,
2945 * print a warning if needed. We need to pass ip as a parameter
2946 * to generate a better warning message here...
2948 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2949 as_warn (_("Macro instruction expanded into multiple instructions"));
2952 * If the macro is about to expand into a second instruction,
2953 * and it is in a delay slot, print a warning.
2957 && mips_opts
.noreorder
2958 && (prev_prev_insn
.insn_mo
->pinfo
2959 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2960 | INSN_COND_BRANCH_LIKELY
)) != 0)
2961 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2964 ++*counter
; /* bump instruction counter */
2966 if (mips_opts
.mips16
)
2968 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2973 r
[0] = BFD_RELOC_UNUSED
;
2974 r
[1] = BFD_RELOC_UNUSED
;
2975 r
[2] = BFD_RELOC_UNUSED
;
2976 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2977 assert (insn
.insn_mo
);
2978 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2980 /* Search until we get a match for NAME. */
2983 /* It is assumed here that macros will never generate
2984 MDMX or MIPS-3D instructions. */
2985 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2986 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2987 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2989 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2991 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2995 assert (insn
.insn_mo
->name
);
2996 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2999 insn
.insn_opcode
= insn
.insn_mo
->match
;
3015 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3019 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3024 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3030 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3035 int tmp
= va_arg (args
, int);
3037 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3038 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3044 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3051 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3055 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3059 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3063 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3067 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3074 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3080 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3081 assert (*r
== BFD_RELOC_GPREL16
3082 || *r
== BFD_RELOC_MIPS_LITERAL
3083 || *r
== BFD_RELOC_MIPS_HIGHER
3084 || *r
== BFD_RELOC_HI16_S
3085 || *r
== BFD_RELOC_LO16
3086 || *r
== BFD_RELOC_MIPS_GOT16
3087 || *r
== BFD_RELOC_MIPS_CALL16
3088 || *r
== BFD_RELOC_MIPS_GOT_DISP
3089 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3090 || *r
== BFD_RELOC_MIPS_GOT_OFST
3091 || *r
== BFD_RELOC_MIPS_GOT_LO16
3092 || *r
== BFD_RELOC_MIPS_CALL_LO16
3093 || (ep
->X_op
== O_subtract
3094 && *r
== BFD_RELOC_PCREL_LO16
));
3098 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3100 && (ep
->X_op
== O_constant
3101 || (ep
->X_op
== O_symbol
3102 && (*r
== BFD_RELOC_MIPS_HIGHEST
3103 || *r
== BFD_RELOC_HI16_S
3104 || *r
== BFD_RELOC_HI16
3105 || *r
== BFD_RELOC_GPREL16
3106 || *r
== BFD_RELOC_MIPS_GOT_HI16
3107 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3108 || (ep
->X_op
== O_subtract
3109 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3113 assert (ep
!= NULL
);
3115 * This allows macro() to pass an immediate expression for
3116 * creating short branches without creating a symbol.
3117 * Note that the expression still might come from the assembly
3118 * input, in which case the value is not checked for range nor
3119 * is a relocation entry generated (yuck).
3121 if (ep
->X_op
== O_constant
)
3123 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3127 *r
= BFD_RELOC_16_PCREL_S2
;
3131 assert (ep
!= NULL
);
3132 *r
= BFD_RELOC_MIPS_JMP
;
3136 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3145 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3147 append_insn (place
, &insn
, ep
, r
);
3151 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3153 int *counter ATTRIBUTE_UNUSED
;
3159 struct mips_cl_insn insn
;
3160 bfd_reloc_code_real_type r
[3]
3161 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3163 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3164 assert (insn
.insn_mo
);
3165 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3167 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3168 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3171 assert (insn
.insn_mo
->name
);
3172 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3175 insn
.insn_opcode
= insn
.insn_mo
->match
;
3176 insn
.use_extend
= FALSE
;
3195 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3200 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3204 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3208 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3218 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3225 regno
= va_arg (args
, int);
3226 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3227 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3248 assert (ep
!= NULL
);
3250 if (ep
->X_op
!= O_constant
)
3251 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3254 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3255 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3258 *r
= BFD_RELOC_UNUSED
;
3264 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3271 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3273 append_insn (place
, &insn
, ep
, r
);
3277 * Generate a "jalr" instruction with a relocation hint to the called
3278 * function. This occurs in NewABI PIC code.
3281 macro_build_jalr (icnt
, ep
)
3292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3295 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3296 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3300 * Generate a "lui" instruction.
3303 macro_build_lui (place
, counter
, ep
, regnum
)
3309 expressionS high_expr
;
3310 struct mips_cl_insn insn
;
3311 bfd_reloc_code_real_type r
[3]
3312 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3313 const char *name
= "lui";
3314 const char *fmt
= "t,u";
3316 assert (! mips_opts
.mips16
);
3322 high_expr
.X_op
= O_constant
;
3323 high_expr
.X_add_number
= ep
->X_add_number
;
3326 if (high_expr
.X_op
== O_constant
)
3328 /* we can compute the instruction now without a relocation entry */
3329 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3331 *r
= BFD_RELOC_UNUSED
;
3335 assert (ep
->X_op
== O_symbol
);
3336 /* _gp_disp is a special case, used from s_cpload. */
3337 assert (mips_pic
== NO_PIC
3339 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3340 *r
= BFD_RELOC_HI16_S
;
3344 * If the macro is about to expand into a second instruction,
3345 * print a warning if needed. We need to pass ip as a parameter
3346 * to generate a better warning message here...
3348 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3349 as_warn (_("Macro instruction expanded into multiple instructions"));
3352 ++*counter
; /* bump instruction counter */
3354 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3355 assert (insn
.insn_mo
);
3356 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3357 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3359 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3360 if (*r
== BFD_RELOC_UNUSED
)
3362 insn
.insn_opcode
|= high_expr
.X_add_number
;
3363 append_insn (place
, &insn
, NULL
, r
);
3366 append_insn (place
, &insn
, &high_expr
, r
);
3369 /* Generate a sequence of instructions to do a load or store from a constant
3370 offset off of a base register (breg) into/from a target register (treg),
3371 using AT if necessary. */
3373 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3380 assert (ep
->X_op
== O_constant
);
3382 /* Right now, this routine can only handle signed 32-bit contants. */
3383 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3384 as_warn (_("operand overflow"));
3386 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3388 /* Signed 16-bit offset will fit in the op. Easy! */
3389 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3390 (int) BFD_RELOC_LO16
, breg
);
3394 /* 32-bit offset, need multiple instructions and AT, like:
3395 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3396 addu $tempreg,$tempreg,$breg
3397 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3398 to handle the complete offset. */
3399 macro_build_lui (place
, counter
, ep
, AT
);
3402 macro_build (place
, counter
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
3403 "d,v,t", AT
, AT
, breg
);
3406 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3407 (int) BFD_RELOC_LO16
, AT
);
3410 as_warn (_("Macro used $at after \".set noat\""));
3415 * Generates code to set the $at register to true (one)
3416 * if reg is less than the immediate expression.
3419 set_at (counter
, reg
, unsignedp
)
3424 if (imm_expr
.X_op
== O_constant
3425 && imm_expr
.X_add_number
>= -0x8000
3426 && imm_expr
.X_add_number
< 0x8000)
3427 macro_build ((char *) NULL
, counter
, &imm_expr
,
3428 unsignedp
? "sltiu" : "slti",
3429 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3432 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3433 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3434 unsignedp
? "sltu" : "slt",
3435 "d,v,t", AT
, reg
, AT
);
3439 /* Warn if an expression is not a constant. */
3442 check_absolute_expr (ip
, ex
)
3443 struct mips_cl_insn
*ip
;
3446 if (ex
->X_op
== O_big
)
3447 as_bad (_("unsupported large constant"));
3448 else if (ex
->X_op
!= O_constant
)
3449 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3452 /* Count the leading zeroes by performing a binary chop. This is a
3453 bulky bit of source, but performance is a LOT better for the
3454 majority of values than a simple loop to count the bits:
3455 for (lcnt = 0; (lcnt < 32); lcnt++)
3456 if ((v) & (1 << (31 - lcnt)))
3458 However it is not code size friendly, and the gain will drop a bit
3459 on certain cached systems.
3461 #define COUNT_TOP_ZEROES(v) \
3462 (((v) & ~0xffff) == 0 \
3463 ? ((v) & ~0xff) == 0 \
3464 ? ((v) & ~0xf) == 0 \
3465 ? ((v) & ~0x3) == 0 \
3466 ? ((v) & ~0x1) == 0 \
3471 : ((v) & ~0x7) == 0 \
3474 : ((v) & ~0x3f) == 0 \
3475 ? ((v) & ~0x1f) == 0 \
3478 : ((v) & ~0x7f) == 0 \
3481 : ((v) & ~0xfff) == 0 \
3482 ? ((v) & ~0x3ff) == 0 \
3483 ? ((v) & ~0x1ff) == 0 \
3486 : ((v) & ~0x7ff) == 0 \
3489 : ((v) & ~0x3fff) == 0 \
3490 ? ((v) & ~0x1fff) == 0 \
3493 : ((v) & ~0x7fff) == 0 \
3496 : ((v) & ~0xffffff) == 0 \
3497 ? ((v) & ~0xfffff) == 0 \
3498 ? ((v) & ~0x3ffff) == 0 \
3499 ? ((v) & ~0x1ffff) == 0 \
3502 : ((v) & ~0x7ffff) == 0 \
3505 : ((v) & ~0x3fffff) == 0 \
3506 ? ((v) & ~0x1fffff) == 0 \
3509 : ((v) & ~0x7fffff) == 0 \
3512 : ((v) & ~0xfffffff) == 0 \
3513 ? ((v) & ~0x3ffffff) == 0 \
3514 ? ((v) & ~0x1ffffff) == 0 \
3517 : ((v) & ~0x7ffffff) == 0 \
3520 : ((v) & ~0x3fffffff) == 0 \
3521 ? ((v) & ~0x1fffffff) == 0 \
3524 : ((v) & ~0x7fffffff) == 0 \
3529 * This routine generates the least number of instructions neccessary to load
3530 * an absolute expression value into a register.
3533 load_register (counter
, reg
, ep
, dbl
)
3540 expressionS hi32
, lo32
;
3542 if (ep
->X_op
!= O_big
)
3544 assert (ep
->X_op
== O_constant
);
3545 if (ep
->X_add_number
< 0x8000
3546 && (ep
->X_add_number
>= 0
3547 || (ep
->X_add_number
>= -0x8000
3550 || sizeof (ep
->X_add_number
) > 4))))
3552 /* We can handle 16 bit signed values with an addiu to
3553 $zero. No need to ever use daddiu here, since $zero and
3554 the result are always correct in 32 bit mode. */
3555 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3556 (int) BFD_RELOC_LO16
);
3559 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3561 /* We can handle 16 bit unsigned values with an ori to
3563 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3564 (int) BFD_RELOC_LO16
);
3567 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3570 || sizeof (ep
->X_add_number
) > 4
3571 || (ep
->X_add_number
& 0x80000000) == 0))
3572 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3573 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3576 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3577 == ~ (offsetT
) 0xffffffff)))
3579 /* 32 bit values require an lui. */
3580 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3581 (int) BFD_RELOC_HI16
);
3582 if ((ep
->X_add_number
& 0xffff) != 0)
3583 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3584 (int) BFD_RELOC_LO16
);
3589 /* The value is larger than 32 bits. */
3591 if (HAVE_32BIT_GPRS
)
3593 as_bad (_("Number (0x%lx) larger than 32 bits"),
3594 (unsigned long) ep
->X_add_number
);
3595 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3596 (int) BFD_RELOC_LO16
);
3600 if (ep
->X_op
!= O_big
)
3603 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3604 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3605 hi32
.X_add_number
&= 0xffffffff;
3607 lo32
.X_add_number
&= 0xffffffff;
3611 assert (ep
->X_add_number
> 2);
3612 if (ep
->X_add_number
== 3)
3613 generic_bignum
[3] = 0;
3614 else if (ep
->X_add_number
> 4)
3615 as_bad (_("Number larger than 64 bits"));
3616 lo32
.X_op
= O_constant
;
3617 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3618 hi32
.X_op
= O_constant
;
3619 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3622 if (hi32
.X_add_number
== 0)
3627 unsigned long hi
, lo
;
3629 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3631 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3633 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3634 reg
, 0, (int) BFD_RELOC_LO16
);
3637 if (lo32
.X_add_number
& 0x80000000)
3639 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3640 (int) BFD_RELOC_HI16
);
3641 if (lo32
.X_add_number
& 0xffff)
3642 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3643 reg
, reg
, (int) BFD_RELOC_LO16
);
3648 /* Check for 16bit shifted constant. We know that hi32 is
3649 non-zero, so start the mask on the first bit of the hi32
3654 unsigned long himask
, lomask
;
3658 himask
= 0xffff >> (32 - shift
);
3659 lomask
= (0xffff << shift
) & 0xffffffff;
3663 himask
= 0xffff << (shift
- 32);
3666 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3667 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3671 tmp
.X_op
= O_constant
;
3673 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3674 | (lo32
.X_add_number
>> shift
));
3676 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3677 macro_build ((char *) NULL
, counter
, &tmp
,
3678 "ori", "t,r,i", reg
, 0,
3679 (int) BFD_RELOC_LO16
);
3680 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3681 (shift
>= 32) ? "dsll32" : "dsll",
3683 (shift
>= 32) ? shift
- 32 : shift
);
3688 while (shift
<= (64 - 16));
3690 /* Find the bit number of the lowest one bit, and store the
3691 shifted value in hi/lo. */
3692 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3693 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3697 while ((lo
& 1) == 0)
3702 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3708 while ((hi
& 1) == 0)
3717 /* Optimize if the shifted value is a (power of 2) - 1. */
3718 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3719 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3721 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3726 /* This instruction will set the register to be all
3728 tmp
.X_op
= O_constant
;
3729 tmp
.X_add_number
= (offsetT
) -1;
3730 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3731 reg
, 0, (int) BFD_RELOC_LO16
);
3735 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3736 (bit
>= 32) ? "dsll32" : "dsll",
3738 (bit
>= 32) ? bit
- 32 : bit
);
3740 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3741 (shift
>= 32) ? "dsrl32" : "dsrl",
3743 (shift
>= 32) ? shift
- 32 : shift
);
3748 /* Sign extend hi32 before calling load_register, because we can
3749 generally get better code when we load a sign extended value. */
3750 if ((hi32
.X_add_number
& 0x80000000) != 0)
3751 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3752 load_register (counter
, reg
, &hi32
, 0);
3755 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3759 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3760 "dsll32", "d,w,<", reg
, freg
, 0);
3768 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3770 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3771 (int) BFD_RELOC_HI16
);
3772 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3773 "dsrl32", "d,w,<", reg
, reg
, 0);
3779 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3780 "d,w,<", reg
, freg
, 16);
3784 mid16
.X_add_number
>>= 16;
3785 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3786 freg
, (int) BFD_RELOC_LO16
);
3787 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3788 "d,w,<", reg
, reg
, 16);
3791 if ((lo32
.X_add_number
& 0xffff) != 0)
3792 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3793 (int) BFD_RELOC_LO16
);
3796 /* Load an address into a register. */
3799 load_address (counter
, reg
, ep
, used_at
)
3807 if (ep
->X_op
!= O_constant
3808 && ep
->X_op
!= O_symbol
)
3810 as_bad (_("expression too complex"));
3811 ep
->X_op
= O_constant
;
3814 if (ep
->X_op
== O_constant
)
3816 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3820 if (mips_pic
== NO_PIC
)
3822 /* If this is a reference to a GP relative symbol, we want
3823 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3825 lui $reg,<sym> (BFD_RELOC_HI16_S)
3826 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3827 If we have an addend, we always use the latter form.
3829 With 64bit address space and a usable $at we want
3830 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3831 lui $at,<sym> (BFD_RELOC_HI16_S)
3832 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3833 daddiu $at,<sym> (BFD_RELOC_LO16)
3837 If $at is already in use, we use a path which is suboptimal
3838 on superscalar processors.
3839 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3840 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3842 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3844 daddiu $reg,<sym> (BFD_RELOC_LO16)
3846 if (HAVE_64BIT_ADDRESSES
)
3848 /* We don't do GP optimization for now because RELAX_ENCODE can't
3849 hold the data for such large chunks. */
3851 if (*used_at
== 0 && ! mips_opts
.noat
)
3853 macro_build (p
, counter
, ep
, "lui", "t,u",
3854 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3855 macro_build (p
, counter
, ep
, "lui", "t,u",
3856 AT
, (int) BFD_RELOC_HI16_S
);
3857 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3858 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3859 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3860 AT
, AT
, (int) BFD_RELOC_LO16
);
3861 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3862 "d,w,<", reg
, reg
, 0);
3863 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3864 "d,v,t", reg
, reg
, AT
);
3869 macro_build (p
, counter
, ep
, "lui", "t,u",
3870 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3871 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3872 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3873 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3874 "d,w,<", reg
, reg
, 16);
3875 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3876 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3877 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3878 "d,w,<", reg
, reg
, 16);
3879 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3880 reg
, reg
, (int) BFD_RELOC_LO16
);
3885 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3886 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3889 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_ADDI_INSN
,
3890 "t,r,j", reg
, mips_gp_register
,
3891 (int) BFD_RELOC_GPREL16
);
3892 p
= frag_var (rs_machine_dependent
, 8, 0,
3893 RELAX_ENCODE (4, 8, 0, 4, 0,
3894 mips_opts
.warn_about_macros
),
3895 ep
->X_add_symbol
, 0, NULL
);
3897 macro_build_lui (p
, counter
, ep
, reg
);
3900 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
,
3901 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3904 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3908 /* If this is a reference to an external symbol, we want
3909 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3911 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3913 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3914 If there is a constant, it must be added in after.
3916 If we have NewABI, we want
3917 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3918 unless we're referencing a global symbol with a non-zero
3919 offset, in which case cst must be added separately. */
3924 if (ep
->X_add_number
)
3926 frag_now
->tc_frag_data
.tc_fr_offset
=
3927 ex
.X_add_number
= ep
->X_add_number
;
3928 ep
->X_add_number
= 0;
3929 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_LOAD_INSN
,
3930 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_DISP
,
3932 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3933 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3934 ex
.X_op
= O_constant
;
3935 macro_build ((char *) NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
,
3936 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3937 p
= frag_var (rs_machine_dependent
, 8, 0,
3938 RELAX_ENCODE (8, 4, 0, 0, 0,
3939 mips_opts
.warn_about_macros
),
3940 ep
->X_add_symbol
, 0, (char *) NULL
);
3941 ep
->X_add_number
= ex
.X_add_number
;
3944 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3945 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3949 /* To avoid confusion in tc_gen_reloc, we must ensure
3950 that this does not become a variant frag. */
3951 frag_wane (frag_now
);
3957 ex
.X_add_number
= ep
->X_add_number
;
3958 ep
->X_add_number
= 0;
3960 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_LOAD_INSN
,
3961 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
,
3963 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3964 p
= frag_var (rs_machine_dependent
, 4, 0,
3965 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3966 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3967 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
,
3968 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3970 if (ex
.X_add_number
!= 0)
3972 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3973 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3974 ex
.X_op
= O_constant
;
3975 macro_build ((char *) NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
,
3976 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3980 else if (mips_pic
== SVR4_PIC
)
3985 /* This is the large GOT case. If this is a reference to an
3986 external symbol, we want
3987 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3989 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3991 Otherwise, for a reference to a local symbol in old ABI, we want
3992 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3995 If there is a constant, it must be added in after.
3997 In the NewABI, for local symbols, with or without offsets, we want:
3998 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3999 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4005 frag_now
->tc_frag_data
.tc_fr_offset
=
4006 ex
.X_add_number
= ep
->X_add_number
;
4007 ep
->X_add_number
= 0;
4008 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4009 (int) BFD_RELOC_MIPS_GOT_HI16
);
4010 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4011 ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
4012 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_LOAD_INSN
,
4013 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4014 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4015 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4016 else if (ex
.X_add_number
)
4018 ex
.X_op
= O_constant
;
4019 macro_build ((char *) NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
,
4020 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4023 ep
->X_add_number
= ex
.X_add_number
;
4024 p
= frag_var (rs_machine_dependent
, 8, 0,
4025 RELAX_ENCODE (ex
.X_add_number
? 16 : 12, 8, 0, 4, 0,
4026 mips_opts
.warn_about_macros
),
4027 ep
->X_add_symbol
, 0, (char *) NULL
);
4028 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4029 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4030 macro_build (p
+ 4, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4031 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
4035 ex
.X_add_number
= ep
->X_add_number
;
4036 ep
->X_add_number
= 0;
4037 if (reg_needs_delay (mips_gp_register
))
4042 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4043 (int) BFD_RELOC_MIPS_GOT_HI16
);
4044 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4045 ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
4046 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_LOAD_INSN
,
4047 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4048 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4049 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
4050 mips_opts
.warn_about_macros
),
4051 ep
->X_add_symbol
, 0, NULL
);
4054 /* We need a nop before loading from $gp. This special
4055 check is required because the lui which starts the main
4056 instruction stream does not refer to $gp, and so will not
4057 insert the nop which may be required. */
4058 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4061 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4062 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4064 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4066 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
,
4067 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4069 if (ex
.X_add_number
!= 0)
4071 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4073 ex
.X_op
= O_constant
;
4074 macro_build ((char *) NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
,
4075 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4079 else if (mips_pic
== EMBEDDED_PIC
)
4082 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4084 macro_build ((char *) NULL
, counter
, ep
, ADDRESS_ADDI_INSN
,
4085 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4091 /* Move the contents of register SOURCE into register DEST. */
4094 move_register (counter
, dest
, source
)
4099 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4100 HAVE_32BIT_GPRS
? "addu" : "daddu",
4101 "d,v,t", dest
, source
, 0);
4106 * This routine implements the seemingly endless macro or synthesized
4107 * instructions and addressing modes in the mips assembly language. Many
4108 * of these macros are simple and are similar to each other. These could
4109 * probably be handled by some kind of table or grammer aproach instead of
4110 * this verbose method. Others are not simple macros but are more like
4111 * optimizing code generation.
4112 * One interesting optimization is when several store macros appear
4113 * consecutivly that would load AT with the upper half of the same address.
4114 * The ensuing load upper instructions are ommited. This implies some kind
4115 * of global optimization. We currently only optimize within a single macro.
4116 * For many of the load and store macros if the address is specified as a
4117 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4118 * first load register 'at' with zero and use it as the base register. The
4119 * mips assembler simply uses register $zero. Just one tiny optimization
4124 struct mips_cl_insn
*ip
;
4126 register int treg
, sreg
, dreg
, breg
;
4142 bfd_reloc_code_real_type r
;
4143 int hold_mips_optimize
;
4145 assert (! mips_opts
.mips16
);
4147 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4148 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4149 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4150 mask
= ip
->insn_mo
->mask
;
4152 expr1
.X_op
= O_constant
;
4153 expr1
.X_op_symbol
= NULL
;
4154 expr1
.X_add_symbol
= NULL
;
4155 expr1
.X_add_number
= 1;
4157 /* Umatched fixups should not be put in the same frag as a relaxable
4158 macro. For example, suppose we have:
4162 addiu $4,$4,%lo(l1) # 3
4164 If instructions 1 and 2 were put in the same frag, md_frob_file would
4165 move the fixup for #1 after the fixups for the "unrelaxed" version of
4166 #2. This would confuse tc_gen_reloc, which expects the relocations
4167 for #2 to be the last for that frag.
4169 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4170 it assumes that they belong to a relaxable macro. We mustn't put
4171 other uses of such relocations into a variant frag.
4173 To avoid both problems, finish the current frag it contains a
4174 %reloc() operator. The macro then goes into a new frag. */
4175 if (prev_reloc_op_frag
== frag_now
)
4177 frag_wane (frag_now
);
4191 mips_emit_delays (TRUE
);
4192 ++mips_opts
.noreorder
;
4193 mips_any_noreorder
= 1;
4195 expr1
.X_add_number
= 8;
4196 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4198 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4201 move_register (&icnt
, dreg
, sreg
);
4202 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4203 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4205 --mips_opts
.noreorder
;
4226 if (imm_expr
.X_op
== O_constant
4227 && imm_expr
.X_add_number
>= -0x8000
4228 && imm_expr
.X_add_number
< 0x8000)
4230 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4231 (int) BFD_RELOC_LO16
);
4234 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4235 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4255 if (imm_expr
.X_op
== O_constant
4256 && imm_expr
.X_add_number
>= 0
4257 && imm_expr
.X_add_number
< 0x10000)
4259 if (mask
!= M_NOR_I
)
4260 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4261 sreg
, (int) BFD_RELOC_LO16
);
4264 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4265 treg
, sreg
, (int) BFD_RELOC_LO16
);
4266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4267 "d,v,t", treg
, treg
, 0);
4272 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4291 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4297 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4298 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4306 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4307 likely
? "bgezl" : "bgez", "s,p", sreg
);
4312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4313 likely
? "blezl" : "blez", "s,p", treg
);
4316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4319 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4325 /* check for > max integer */
4326 maxnum
= 0x7fffffff;
4327 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4334 if (imm_expr
.X_op
== O_constant
4335 && imm_expr
.X_add_number
>= maxnum
4336 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4339 /* result is always false */
4343 as_warn (_("Branch %s is always false (nop)"),
4345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4351 as_warn (_("Branch likely %s is always false"),
4353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4358 if (imm_expr
.X_op
!= O_constant
)
4359 as_bad (_("Unsupported large constant"));
4360 ++imm_expr
.X_add_number
;
4364 if (mask
== M_BGEL_I
)
4366 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4369 likely
? "bgezl" : "bgez", "s,p", sreg
);
4372 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4374 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4375 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4378 maxnum
= 0x7fffffff;
4379 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4386 maxnum
= - maxnum
- 1;
4387 if (imm_expr
.X_op
== O_constant
4388 && imm_expr
.X_add_number
<= maxnum
4389 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4392 /* result is always true */
4393 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4394 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4397 set_at (&icnt
, sreg
, 0);
4398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4399 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4410 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4413 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4414 "d,v,t", AT
, sreg
, treg
);
4415 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4416 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4424 && imm_expr
.X_op
== O_constant
4425 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4427 if (imm_expr
.X_op
!= O_constant
)
4428 as_bad (_("Unsupported large constant"));
4429 ++imm_expr
.X_add_number
;
4433 if (mask
== M_BGEUL_I
)
4435 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4437 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4439 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4440 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4443 set_at (&icnt
, sreg
, 1);
4444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4445 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4454 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4460 likely
? "bltzl" : "bltz", "s,p", treg
);
4463 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4465 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4466 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4474 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4475 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4481 "d,v,t", AT
, treg
, sreg
);
4482 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4483 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4492 likely
? "blezl" : "blez", "s,p", sreg
);
4497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4498 likely
? "bgezl" : "bgez", "s,p", treg
);
4501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4504 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4510 maxnum
= 0x7fffffff;
4511 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4518 if (imm_expr
.X_op
== O_constant
4519 && imm_expr
.X_add_number
>= maxnum
4520 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4522 if (imm_expr
.X_op
!= O_constant
)
4523 as_bad (_("Unsupported large constant"));
4524 ++imm_expr
.X_add_number
;
4528 if (mask
== M_BLTL_I
)
4530 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4532 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4533 likely
? "bltzl" : "bltz", "s,p", sreg
);
4536 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4539 likely
? "blezl" : "blez", "s,p", sreg
);
4542 set_at (&icnt
, sreg
, 0);
4543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4544 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4553 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4559 "d,v,t", AT
, treg
, sreg
);
4560 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4561 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4569 && imm_expr
.X_op
== O_constant
4570 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4572 if (imm_expr
.X_op
!= O_constant
)
4573 as_bad (_("Unsupported large constant"));
4574 ++imm_expr
.X_add_number
;
4578 if (mask
== M_BLTUL_I
)
4580 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4582 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4585 likely
? "beql" : "beq",
4589 set_at (&icnt
, sreg
, 1);
4590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4591 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4600 likely
? "bltzl" : "bltz", "s,p", sreg
);
4605 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4606 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4609 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4612 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4622 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4623 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4630 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4645 as_warn (_("Divide by zero."));
4647 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4655 mips_emit_delays (TRUE
);
4656 ++mips_opts
.noreorder
;
4657 mips_any_noreorder
= 1;
4660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4661 "s,t,q", treg
, 0, 7);
4662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4663 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4667 expr1
.X_add_number
= 8;
4668 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4670 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4674 expr1
.X_add_number
= -1;
4675 macro_build ((char *) NULL
, &icnt
, &expr1
,
4676 dbl
? "daddiu" : "addiu",
4677 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4678 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4679 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4682 expr1
.X_add_number
= 1;
4683 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4684 (int) BFD_RELOC_LO16
);
4685 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4686 "d,w,<", AT
, AT
, 31);
4690 expr1
.X_add_number
= 0x80000000;
4691 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4692 (int) BFD_RELOC_HI16
);
4696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4697 "s,t,q", sreg
, AT
, 6);
4698 /* We want to close the noreorder block as soon as possible, so
4699 that later insns are available for delay slot filling. */
4700 --mips_opts
.noreorder
;
4704 expr1
.X_add_number
= 8;
4705 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4709 /* We want to close the noreorder block as soon as possible, so
4710 that later insns are available for delay slot filling. */
4711 --mips_opts
.noreorder
;
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4755 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4757 as_warn (_("Divide by zero."));
4759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4766 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4768 if (strcmp (s2
, "mflo") == 0)
4769 move_register (&icnt
, dreg
, sreg
);
4771 move_register (&icnt
, dreg
, 0);
4774 if (imm_expr
.X_op
== O_constant
4775 && imm_expr
.X_add_number
== -1
4776 && s
[strlen (s
) - 1] != 'u')
4778 if (strcmp (s2
, "mflo") == 0)
4780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4781 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4784 move_register (&icnt
, dreg
, 0);
4788 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4810 mips_emit_delays (TRUE
);
4811 ++mips_opts
.noreorder
;
4812 mips_any_noreorder
= 1;
4815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4816 "s,t,q", treg
, 0, 7);
4817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4819 /* We want to close the noreorder block as soon as possible, so
4820 that later insns are available for delay slot filling. */
4821 --mips_opts
.noreorder
;
4825 expr1
.X_add_number
= 8;
4826 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4830 /* We want to close the noreorder block as soon as possible, so
4831 that later insns are available for delay slot filling. */
4832 --mips_opts
.noreorder
;
4833 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4836 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4842 /* Load the address of a symbol into a register. If breg is not
4843 zero, we then add a base register to it. */
4845 if (dbl
&& HAVE_32BIT_GPRS
)
4846 as_warn (_("dla used to load 32-bit register"));
4848 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4849 as_warn (_("la used to load 64-bit address"));
4851 if (offset_expr
.X_op
== O_constant
4852 && offset_expr
.X_add_number
>= -0x8000
4853 && offset_expr
.X_add_number
< 0x8000)
4855 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4856 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4857 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4872 /* When generating embedded PIC code, we permit expressions of
4875 la $treg,foo-bar($breg)
4876 where bar is an address in the current section. These are used
4877 when getting the addresses of functions. We don't permit
4878 X_add_number to be non-zero, because if the symbol is
4879 external the relaxing code needs to know that any addend is
4880 purely the offset to X_op_symbol. */
4881 if (mips_pic
== EMBEDDED_PIC
4882 && offset_expr
.X_op
== O_subtract
4883 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4884 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4885 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4887 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4890 && (offset_expr
.X_add_number
== 0
4891 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4898 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4902 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4903 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4905 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4906 "d,v,t", tempreg
, tempreg
, breg
);
4908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4909 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4910 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4916 if (offset_expr
.X_op
!= O_symbol
4917 && offset_expr
.X_op
!= O_constant
)
4919 as_bad (_("expression too complex"));
4920 offset_expr
.X_op
= O_constant
;
4923 if (offset_expr
.X_op
== O_constant
)
4924 load_register (&icnt
, tempreg
, &offset_expr
,
4925 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4926 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4927 : HAVE_64BIT_ADDRESSES
));
4928 else if (mips_pic
== NO_PIC
)
4930 /* If this is a reference to a GP relative symbol, we want
4931 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4933 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4935 If we have a constant, we need two instructions anyhow,
4936 so we may as well always use the latter form.
4938 With 64bit address space and a usable $at we want
4939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4940 lui $at,<sym> (BFD_RELOC_HI16_S)
4941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4942 daddiu $at,<sym> (BFD_RELOC_LO16)
4944 daddu $tempreg,$tempreg,$at
4946 If $at is already in use, we use a path which is suboptimal
4947 on superscalar processors.
4948 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4949 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4951 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4953 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4956 if (HAVE_64BIT_ADDRESSES
)
4958 /* We don't do GP optimization for now because RELAX_ENCODE can't
4959 hold the data for such large chunks. */
4961 if (used_at
== 0 && ! mips_opts
.noat
)
4963 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4964 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4965 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4966 AT
, (int) BFD_RELOC_HI16_S
);
4967 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4968 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4969 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4970 AT
, AT
, (int) BFD_RELOC_LO16
);
4971 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4972 "d,w,<", tempreg
, tempreg
, 0);
4973 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4974 "d,v,t", tempreg
, tempreg
, AT
);
4979 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4980 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4981 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4982 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4983 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4984 tempreg
, tempreg
, 16);
4985 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4986 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4987 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4988 tempreg
, tempreg
, 16);
4989 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4990 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4995 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4996 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5000 ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5001 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5002 p
= frag_var (rs_machine_dependent
, 8, 0,
5003 RELAX_ENCODE (4, 8, 0, 4, 0,
5004 mips_opts
.warn_about_macros
),
5005 offset_expr
.X_add_symbol
, 0, NULL
);
5007 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5010 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5011 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5014 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5016 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5018 /* If this is a reference to an external symbol, and there
5019 is no constant, we want
5020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5021 or if tempreg is PIC_CALL_REG
5022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5023 For a local symbol, we want
5024 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5026 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5028 If we have a small constant, and this is a reference to
5029 an external symbol, we want
5030 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5032 addiu $tempreg,$tempreg,<constant>
5033 For a local symbol, we want the same instruction
5034 sequence, but we output a BFD_RELOC_LO16 reloc on the
5037 If we have a large constant, and this is a reference to
5038 an external symbol, we want
5039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5040 lui $at,<hiconstant>
5041 addiu $at,$at,<loconstant>
5042 addu $tempreg,$tempreg,$at
5043 For a local symbol, we want the same instruction
5044 sequence, but we output a BFD_RELOC_LO16 reloc on the
5048 expr1
.X_add_number
= offset_expr
.X_add_number
;
5049 offset_expr
.X_add_number
= 0;
5051 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5052 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5053 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5054 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
5055 if (expr1
.X_add_number
== 0)
5064 /* We're going to put in an addu instruction using
5065 tempreg, so we may as well insert the nop right
5067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5071 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5072 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5074 ? mips_opts
.warn_about_macros
5076 offset_expr
.X_add_symbol
, 0, NULL
);
5079 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5082 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5083 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5084 /* FIXME: If breg == 0, and the next instruction uses
5085 $tempreg, then if this variant case is used an extra
5086 nop will be generated. */
5088 else if (expr1
.X_add_number
>= -0x8000
5089 && expr1
.X_add_number
< 0x8000)
5091 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5093 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5094 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5095 frag_var (rs_machine_dependent
, 0, 0,
5096 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5097 offset_expr
.X_add_symbol
, 0, NULL
);
5103 /* If we are going to add in a base register, and the
5104 target register and the base register are the same,
5105 then we are using AT as a temporary register. Since
5106 we want to load the constant into AT, we add our
5107 current AT (from the global offset table) and the
5108 register into the register now, and pretend we were
5109 not using a base register. */
5114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5117 ADDRESS_ADD_INSN
, "d,v,t", treg
, AT
, breg
);
5123 /* Set mips_optimize around the lui instruction to avoid
5124 inserting an unnecessary nop after the lw. */
5125 hold_mips_optimize
= mips_optimize
;
5127 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5128 mips_optimize
= hold_mips_optimize
;
5130 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5131 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5133 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
, AT
);
5134 frag_var (rs_machine_dependent
, 0, 0,
5135 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5136 offset_expr
.X_add_symbol
, 0, NULL
);
5140 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5143 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5146 /* If this is a reference to an external, and there is no
5147 constant, or local symbol (*), with or without a
5149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5150 or if tempreg is PIC_CALL_REG
5151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5153 If we have a small constant, and this is a reference to
5154 an external symbol, we want
5155 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5156 addiu $tempreg,$tempreg,<constant>
5158 If we have a large constant, and this is a reference to
5159 an external symbol, we want
5160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5161 lui $at,<hiconstant>
5162 addiu $at,$at,<loconstant>
5163 addu $tempreg,$tempreg,$at
5165 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5166 local symbols, even though it introduces an additional
5170 if (offset_expr
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5171 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5172 if (offset_expr
.X_add_number
)
5174 frag_now
->tc_frag_data
.tc_fr_offset
=
5175 expr1
.X_add_number
= offset_expr
.X_add_number
;
5176 offset_expr
.X_add_number
= 0;
5178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5179 ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5180 lw_reloc_type
, mips_gp_register
);
5182 if (expr1
.X_add_number
>= -0x8000
5183 && expr1
.X_add_number
< 0x8000)
5185 macro_build ((char *) NULL
, &icnt
, &expr1
,
5186 ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, tempreg
,
5187 (int) BFD_RELOC_LO16
);
5188 p
= frag_var (rs_machine_dependent
, 4, 0,
5189 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5190 offset_expr
.X_add_symbol
, 0, NULL
);
5192 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5196 /* If we are going to add in a base register, and the
5197 target register and the base register are the same,
5198 then we are using AT as a temporary register. Since
5199 we want to load the constant into AT, we add our
5200 current AT (from the global offset table) and the
5201 register into the register now, and pretend we were
5202 not using a base register. */
5207 assert (tempreg
== AT
);
5208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5209 ADDRESS_ADD_INSN
, "d,v,t", treg
, AT
, breg
);
5214 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5215 macro_build ((char *) NULL
, &icnt
, &expr1
,
5216 ADDRESS_ADDI_INSN
, "t,r,j", AT
, AT
,
5217 (int) BFD_RELOC_LO16
);
5218 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5219 ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5221 p
= frag_var (rs_machine_dependent
, 4 + adj
, 0,
5222 RELAX_ENCODE (16 + adj
, 4 + adj
,
5224 offset_expr
.X_add_symbol
, 0, NULL
);
5229 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5231 offset_expr
.X_add_number
= expr1
.X_add_number
;
5233 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5234 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_DISP
,
5238 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
5239 ADDRESS_ADD_INSN
, "d,v,t",
5240 treg
, tempreg
, breg
);
5247 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5248 ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5249 lw_reloc_type
, mips_gp_register
);
5250 if (lw_reloc_type
!= BFD_RELOC_MIPS_GOT_DISP
)
5251 p
= frag_var (rs_machine_dependent
, 0, 0,
5252 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5253 offset_expr
.X_add_symbol
, 0, NULL
);
5258 /* To avoid confusion in tc_gen_reloc, we must ensure
5259 that this does not become a variant frag. */
5260 frag_wane (frag_now
);
5264 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5268 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5269 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5270 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5272 /* This is the large GOT case. If this is a reference to an
5273 external symbol, and there is no constant, we want
5274 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5275 addu $tempreg,$tempreg,$gp
5276 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5277 or if tempreg is PIC_CALL_REG
5278 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5279 addu $tempreg,$tempreg,$gp
5280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5281 For a local symbol, we want
5282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5284 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5286 If we have a small constant, and this is a reference to
5287 an external symbol, we want
5288 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5289 addu $tempreg,$tempreg,$gp
5290 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5292 addiu $tempreg,$tempreg,<constant>
5293 For a local symbol, we want
5294 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5296 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5298 If we have a large constant, and this is a reference to
5299 an external symbol, we want
5300 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5301 addu $tempreg,$tempreg,$gp
5302 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5303 lui $at,<hiconstant>
5304 addiu $at,$at,<loconstant>
5305 addu $tempreg,$tempreg,$at
5306 For a local symbol, we want
5307 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5308 lui $at,<hiconstant>
5309 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5310 addu $tempreg,$tempreg,$at
5313 expr1
.X_add_number
= offset_expr
.X_add_number
;
5314 offset_expr
.X_add_number
= 0;
5316 if (reg_needs_delay (mips_gp_register
))
5320 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5322 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5323 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5325 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5326 tempreg
, lui_reloc_type
);
5327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5328 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5330 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5331 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5332 if (expr1
.X_add_number
== 0)
5340 /* We're going to put in an addu instruction using
5341 tempreg, so we may as well insert the nop right
5343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5348 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5349 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5352 ? mips_opts
.warn_about_macros
5354 offset_expr
.X_add_symbol
, 0, NULL
);
5356 else if (expr1
.X_add_number
>= -0x8000
5357 && expr1
.X_add_number
< 0x8000)
5359 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5361 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5362 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5364 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5365 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5367 ? mips_opts
.warn_about_macros
5369 offset_expr
.X_add_symbol
, 0, NULL
);
5375 /* If we are going to add in a base register, and the
5376 target register and the base register are the same,
5377 then we are using AT as a temporary register. Since
5378 we want to load the constant into AT, we add our
5379 current AT (from the global offset table) and the
5380 register into the register now, and pretend we were
5381 not using a base register. */
5389 assert (tempreg
== AT
);
5390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5393 ADDRESS_ADD_INSN
, "d,v,t", treg
, AT
, breg
);
5398 /* Set mips_optimize around the lui instruction to avoid
5399 inserting an unnecessary nop after the lw. */
5400 hold_mips_optimize
= mips_optimize
;
5402 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5403 mips_optimize
= hold_mips_optimize
;
5405 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5406 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5408 ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5410 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5411 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5414 ? mips_opts
.warn_about_macros
5416 offset_expr
.X_add_symbol
, 0, NULL
);
5423 /* This is needed because this instruction uses $gp, but
5424 the first instruction on the main stream does not. */
5425 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5429 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5430 tempreg
, local_reloc_type
, mips_gp_register
);
5432 if (expr1
.X_add_number
>= -0x8000
5433 && expr1
.X_add_number
< 0x8000)
5435 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5437 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5438 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5439 /* FIXME: If add_number is 0, and there was no base
5440 register, the external symbol case ended with a load,
5441 so if the symbol turns out to not be external, and
5442 the next instruction uses tempreg, an unnecessary nop
5443 will be inserted. */
5449 /* We must add in the base register now, as in the
5450 external symbol case. */
5451 assert (tempreg
== AT
);
5452 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5454 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5455 ADDRESS_ADD_INSN
, "d,v,t", treg
, AT
, breg
);
5458 /* We set breg to 0 because we have arranged to add
5459 it in in both cases. */
5463 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5465 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5466 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5468 macro_build (p
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
5469 "d,v,t", tempreg
, tempreg
, AT
);
5473 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5476 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5477 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5480 /* This is the large GOT case. If this is a reference to an
5481 external symbol, and there is no constant, we want
5482 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5483 add $tempreg,$tempreg,$gp
5484 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5485 or if tempreg is PIC_CALL_REG
5486 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5487 add $tempreg,$tempreg,$gp
5488 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5490 If we have a small constant, and this is a reference to
5491 an external symbol, we want
5492 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5493 add $tempreg,$tempreg,$gp
5494 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5495 addi $tempreg,$tempreg,<constant>
5497 If we have a large constant, and this is a reference to
5498 an external symbol, we want
5499 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5500 addu $tempreg,$tempreg,$gp
5501 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5502 lui $at,<hiconstant>
5503 addi $at,$at,<loconstant>
5504 add $tempreg,$tempreg,$at
5506 If we have NewABI, and we know it's a local symbol, we want
5507 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5508 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5509 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5513 frag_now
->tc_frag_data
.tc_fr_offset
=
5514 expr1
.X_add_number
= offset_expr
.X_add_number
;
5515 offset_expr
.X_add_number
= 0;
5517 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5519 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5520 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5523 tempreg
, lui_reloc_type
);
5524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5525 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5528 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5530 if (expr1
.X_add_number
== 0)
5532 p
= frag_var (rs_machine_dependent
, 8, 0,
5533 RELAX_ENCODE (12, 8, 0, 4, 0,
5534 mips_opts
.warn_about_macros
),
5535 offset_expr
.X_add_symbol
, 0, NULL
);
5537 else if (expr1
.X_add_number
>= -0x8000
5538 && expr1
.X_add_number
< 0x8000)
5540 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5541 "t,r,j", tempreg
, tempreg
,
5542 (int) BFD_RELOC_LO16
);
5543 p
= frag_var (rs_machine_dependent
, 8, 0,
5544 RELAX_ENCODE (16, 8, 0, 4, 0,
5545 mips_opts
.warn_about_macros
),
5546 offset_expr
.X_add_symbol
, 0, NULL
);
5548 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5552 /* If we are going to add in a base register, and the
5553 target register and the base register are the same,
5554 then we are using AT as a temporary register. Since
5555 we want to load the constant into AT, we add our
5556 current AT (from the global offset table) and the
5557 register into the register now, and pretend we were
5558 not using a base register. */
5563 assert (tempreg
== AT
);
5564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5565 ADDRESS_ADD_INSN
, "d,v,t", treg
, AT
, breg
);
5570 /* Set mips_optimize around the lui instruction to avoid
5571 inserting an unnecessary nop after the lw. */
5572 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5573 macro_build ((char *) NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5574 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5576 ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5578 p
= frag_var (rs_machine_dependent
, 8 + adj
, 0,
5579 RELAX_ENCODE (24 + adj
, 8 + adj
,
5582 ? mips_opts
.warn_about_macros
5584 offset_expr
.X_add_symbol
, 0, NULL
);
5589 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5591 offset_expr
.X_add_number
= expr1
.X_add_number
;
5592 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5593 tempreg
, (int) BFD_RELOC_MIPS_GOT_PAGE
,
5595 macro_build (p
+ 4, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5596 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
5599 macro_build (p
+ 8, &icnt
, (expressionS
*) NULL
,
5600 ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5605 else if (mips_pic
== EMBEDDED_PIC
)
5608 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5610 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5611 "t,r,j", tempreg
, mips_gp_register
,
5612 (int) BFD_RELOC_GPREL16
);
5621 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5622 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5624 s
= ADDRESS_ADD_INSN
;
5626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5627 "d,v,t", treg
, tempreg
, breg
);
5636 /* The j instruction may not be used in PIC code, since it
5637 requires an absolute address. We convert it to a b
5639 if (mips_pic
== NO_PIC
)
5640 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5642 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5645 /* The jal instructions must be handled as macros because when
5646 generating PIC code they expand to multi-instruction
5647 sequences. Normally they are simple instructions. */
5652 if (mips_pic
== NO_PIC
5653 || mips_pic
== EMBEDDED_PIC
)
5654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5656 else if (mips_pic
== SVR4_PIC
)
5658 if (sreg
!= PIC_CALL_REG
)
5659 as_warn (_("MIPS PIC call to register other than $25"));
5661 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5665 if (mips_cprestore_offset
< 0)
5666 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5669 if (! mips_frame_reg_valid
)
5671 as_warn (_("No .frame pseudo-op used in PIC code"));
5672 /* Quiet this warning. */
5673 mips_frame_reg_valid
= 1;
5675 if (! mips_cprestore_valid
)
5677 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5678 /* Quiet this warning. */
5679 mips_cprestore_valid
= 1;
5681 expr1
.X_add_number
= mips_cprestore_offset
;
5682 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5695 if (mips_pic
== NO_PIC
)
5696 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5697 else if (mips_pic
== SVR4_PIC
)
5701 /* If this is a reference to an external symbol, and we are
5702 using a small GOT, we want
5703 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5707 lw $gp,cprestore($sp)
5708 The cprestore value is set using the .cprestore
5709 pseudo-op. If we are using a big GOT, we want
5710 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5712 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5716 lw $gp,cprestore($sp)
5717 If the symbol is not external, we want
5718 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5720 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5723 lw $gp,cprestore($sp)
5725 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5726 sequences above, minus nops, unless the symbol is local,
5727 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5734 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5735 ADDRESS_LOAD_INSN
, "t,o(b)", PIC_CALL_REG
,
5736 (int) BFD_RELOC_MIPS_CALL16
,
5738 frag_var (rs_machine_dependent
, 0, 0,
5739 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5740 offset_expr
.X_add_symbol
, 0, NULL
);
5745 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5746 "t,u", PIC_CALL_REG
,
5747 (int) BFD_RELOC_MIPS_CALL_HI16
);
5748 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5749 ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5750 PIC_CALL_REG
, mips_gp_register
);
5751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5752 ADDRESS_LOAD_INSN
, "t,o(b)", PIC_CALL_REG
,
5753 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5754 p
= frag_var (rs_machine_dependent
, 8, 0,
5755 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5756 offset_expr
.X_add_symbol
, 0, NULL
);
5757 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5758 "t,o(b)", PIC_CALL_REG
,
5759 (int) BFD_RELOC_MIPS_GOT_PAGE
,
5761 macro_build (p
+ 4, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5762 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5763 (int) BFD_RELOC_MIPS_GOT_OFST
);
5766 macro_build_jalr (icnt
, &offset_expr
);
5773 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5774 ADDRESS_LOAD_INSN
, "t,o(b)", PIC_CALL_REG
,
5775 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5778 p
= frag_var (rs_machine_dependent
, 4, 0,
5779 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5780 offset_expr
.X_add_symbol
, 0, NULL
);
5786 if (reg_needs_delay (mips_gp_register
))
5790 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5791 "t,u", PIC_CALL_REG
,
5792 (int) BFD_RELOC_MIPS_CALL_HI16
);
5793 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5794 ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5795 PIC_CALL_REG
, mips_gp_register
);
5796 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5797 ADDRESS_LOAD_INSN
, "t,o(b)", PIC_CALL_REG
,
5798 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5801 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5802 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5804 offset_expr
.X_add_symbol
, 0, NULL
);
5807 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5810 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5811 "t,o(b)", PIC_CALL_REG
,
5812 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5814 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5817 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5818 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5819 (int) BFD_RELOC_LO16
);
5820 macro_build_jalr (icnt
, &offset_expr
);
5822 if (mips_cprestore_offset
< 0)
5823 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5826 if (! mips_frame_reg_valid
)
5828 as_warn (_("No .frame pseudo-op used in PIC code"));
5829 /* Quiet this warning. */
5830 mips_frame_reg_valid
= 1;
5832 if (! mips_cprestore_valid
)
5834 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5835 /* Quiet this warning. */
5836 mips_cprestore_valid
= 1;
5838 if (mips_opts
.noreorder
)
5839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5841 expr1
.X_add_number
= mips_cprestore_offset
;
5842 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5849 else if (mips_pic
== EMBEDDED_PIC
)
5851 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5852 /* The linker may expand the call to a longer sequence which
5853 uses $at, so we must break rather than return. */
5878 /* Itbl support may require additional care here. */
5883 /* Itbl support may require additional care here. */
5888 /* Itbl support may require additional care here. */
5893 /* Itbl support may require additional care here. */
5905 if (mips_opts
.arch
== CPU_R4650
)
5907 as_bad (_("opcode not supported on this processor"));
5911 /* Itbl support may require additional care here. */
5916 /* Itbl support may require additional care here. */
5921 /* Itbl support may require additional care here. */
5941 if (breg
== treg
|| coproc
|| lr
)
5963 /* Itbl support may require additional care here. */
5968 /* Itbl support may require additional care here. */
5973 /* Itbl support may require additional care here. */
5978 /* Itbl support may require additional care here. */
5994 if (mips_opts
.arch
== CPU_R4650
)
5996 as_bad (_("opcode not supported on this processor"));
6001 /* Itbl support may require additional care here. */
6005 /* Itbl support may require additional care here. */
6010 /* Itbl support may require additional care here. */
6022 /* Itbl support may require additional care here. */
6023 if (mask
== M_LWC1_AB
6024 || mask
== M_SWC1_AB
6025 || mask
== M_LDC1_AB
6026 || mask
== M_SDC1_AB
6035 /* For embedded PIC, we allow loads where the offset is calculated
6036 by subtracting a symbol in the current segment from an unknown
6037 symbol, relative to a base register, e.g.:
6038 <op> $treg, <sym>-<localsym>($breg)
6039 This is used by the compiler for switch statements. */
6040 if (mips_pic
== EMBEDDED_PIC
6041 && offset_expr
.X_op
== O_subtract
6042 && (symbol_constant_p (offset_expr
.X_op_symbol
)
6043 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
6044 : (symbol_equated_p (offset_expr
.X_op_symbol
)
6046 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
6050 && (offset_expr
.X_add_number
== 0
6051 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
6053 /* For this case, we output the instructions:
6054 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6055 addiu $tempreg,$tempreg,$breg
6056 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6057 If the relocation would fit entirely in 16 bits, it would be
6059 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6060 instead, but that seems quite difficult. */
6061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6062 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
6063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6064 ((bfd_arch_bits_per_address (stdoutput
) == 32
6065 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6066 ? "addu" : "daddu"),
6067 "d,v,t", tempreg
, tempreg
, breg
);
6068 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6069 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
6075 if (offset_expr
.X_op
!= O_constant
6076 && offset_expr
.X_op
!= O_symbol
)
6078 as_bad (_("expression too complex"));
6079 offset_expr
.X_op
= O_constant
;
6082 /* A constant expression in PIC code can be handled just as it
6083 is in non PIC code. */
6084 if (mips_pic
== NO_PIC
6085 || offset_expr
.X_op
== O_constant
)
6089 /* If this is a reference to a GP relative symbol, and there
6090 is no base register, we want
6091 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6092 Otherwise, if there is no base register, we want
6093 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6094 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6095 If we have a constant, we need two instructions anyhow,
6096 so we always use the latter form.
6098 If we have a base register, and this is a reference to a
6099 GP relative symbol, we want
6100 addu $tempreg,$breg,$gp
6101 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6103 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6104 addu $tempreg,$tempreg,$breg
6105 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6106 With a constant we always use the latter case.
6108 With 64bit address space and no base register and $at usable,
6110 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6111 lui $at,<sym> (BFD_RELOC_HI16_S)
6112 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6115 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6116 If we have a base register, we want
6117 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6118 lui $at,<sym> (BFD_RELOC_HI16_S)
6119 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6123 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6125 Without $at we can't generate the optimal path for superscalar
6126 processors here since this would require two temporary registers.
6127 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6128 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6130 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6132 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6133 If we have a base register, we want
6134 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6135 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6137 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6139 daddu $tempreg,$tempreg,$breg
6140 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6142 If we have 64-bit addresses, as an optimization, for
6143 addresses which are 32-bit constants (e.g. kseg0/kseg1
6144 addresses) we fall back to the 32-bit address generation
6145 mechanism since it is more efficient. Note that due to
6146 the signed offset used by memory operations, the 32-bit
6147 range is shifted down by 32768 here. This code should
6148 probably attempt to generate 64-bit constants more
6149 efficiently in general.
6151 As an extension for architectures with 64-bit registers,
6152 we don't truncate 64-bit addresses given as literal
6153 constants down to 32 bits, to support existing practice
6154 in the mips64 Linux (the kernel), that compiles source
6155 files with -mabi=64, assembling them as o32 or n32 (with
6156 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6157 the whole kernel is loaded into a memory region that is
6158 addressible with sign-extended 32-bit addresses, it is
6159 wasteful to compute the upper 32 bits of every
6160 non-literal address, that takes more space and time.
6161 Some day this should probably be implemented as an
6162 assembler option, such that the kernel doesn't have to
6163 use such ugly hacks, even though it will still have to
6164 end up converting the binary to ELF32 for a number of
6165 platforms whose boot loaders don't support ELF64
6167 if ((offset_expr
.X_op
!= O_constant
&& HAVE_64BIT_ADDRESSES
)
6168 || (offset_expr
.X_op
== O_constant
6169 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)
6170 && HAVE_64BIT_ADDRESS_CONSTANTS
))
6174 /* We don't do GP optimization for now because RELAX_ENCODE can't
6175 hold the data for such large chunks. */
6177 if (used_at
== 0 && ! mips_opts
.noat
)
6179 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6180 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6181 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6182 AT
, (int) BFD_RELOC_HI16_S
);
6183 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6184 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6186 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6187 "d,v,t", AT
, AT
, breg
);
6188 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
6189 "d,w,<", tempreg
, tempreg
, 0);
6190 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6191 "d,v,t", tempreg
, tempreg
, AT
);
6192 macro_build (p
, &icnt
, &offset_expr
, s
,
6193 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6198 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6199 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6200 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6201 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6202 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6203 "d,w,<", tempreg
, tempreg
, 16);
6204 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6205 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
6206 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6207 "d,w,<", tempreg
, tempreg
, 16);
6209 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6210 "d,v,t", tempreg
, tempreg
, breg
);
6211 macro_build (p
, &icnt
, &offset_expr
, s
,
6212 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6217 else if (offset_expr
.X_op
== O_constant
6218 && !HAVE_64BIT_ADDRESS_CONSTANTS
6219 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6220 as_bad (_("load/store address overflow (max 32 bits)"));
6224 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6225 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6230 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6231 treg
, (int) BFD_RELOC_GPREL16
,
6233 p
= frag_var (rs_machine_dependent
, 8, 0,
6234 RELAX_ENCODE (4, 8, 0, 4, 0,
6235 (mips_opts
.warn_about_macros
6237 && mips_opts
.noat
))),
6238 offset_expr
.X_add_symbol
, 0, NULL
);
6241 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6244 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6245 (int) BFD_RELOC_LO16
, tempreg
);
6249 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6250 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6256 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, breg
,
6258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6259 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6260 p
= frag_var (rs_machine_dependent
, 12, 0,
6261 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6262 offset_expr
.X_add_symbol
, 0, NULL
);
6264 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6267 macro_build (p
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
6268 "d,v,t", tempreg
, tempreg
, breg
);
6271 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6272 (int) BFD_RELOC_LO16
, tempreg
);
6275 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6278 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6280 /* If this is a reference to an external symbol, we want
6281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6283 <op> $treg,0($tempreg)
6285 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6287 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6288 <op> $treg,0($tempreg)
6291 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6292 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6294 If there is a base register, we add it to $tempreg before
6295 the <op>. If there is a constant, we stick it in the
6296 <op> instruction. We don't handle constants larger than
6297 16 bits, because we have no way to load the upper 16 bits
6298 (actually, we could handle them for the subset of cases
6299 in which we are not using $at). */
6300 assert (offset_expr
.X_op
== O_symbol
);
6303 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6304 ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6305 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6308 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6310 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6311 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6318 expr1
.X_add_number
= offset_expr
.X_add_number
;
6319 offset_expr
.X_add_number
= 0;
6320 if (expr1
.X_add_number
< -0x8000
6321 || expr1
.X_add_number
>= 0x8000)
6322 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6325 "t,o(b)", tempreg
, (int) lw_reloc_type
,
6327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6328 p
= frag_var (rs_machine_dependent
, 4, 0,
6329 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6330 offset_expr
.X_add_symbol
, 0, NULL
);
6331 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
6332 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6335 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
, breg
);
6336 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6337 (int) BFD_RELOC_LO16
, tempreg
);
6339 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6344 /* If this is a reference to an external symbol, we want
6345 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6346 addu $tempreg,$tempreg,$gp
6347 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6348 <op> $treg,0($tempreg)
6350 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6352 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6353 <op> $treg,0($tempreg)
6354 If there is a base register, we add it to $tempreg before
6355 the <op>. If there is a constant, we stick it in the
6356 <op> instruction. We don't handle constants larger than
6357 16 bits, because we have no way to load the upper 16 bits
6358 (actually, we could handle them for the subset of cases
6359 in which we are not using $at). */
6360 assert (offset_expr
.X_op
== O_symbol
);
6361 expr1
.X_add_number
= offset_expr
.X_add_number
;
6362 offset_expr
.X_add_number
= 0;
6363 if (expr1
.X_add_number
< -0x8000
6364 || expr1
.X_add_number
>= 0x8000)
6365 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6366 if (reg_needs_delay (mips_gp_register
))
6371 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6372 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6374 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6376 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6377 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6379 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6380 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6381 offset_expr
.X_add_symbol
, 0, NULL
);
6384 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6387 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6388 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6391 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6393 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
6394 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6397 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
, breg
);
6398 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6399 (int) BFD_RELOC_LO16
, tempreg
);
6401 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6404 int bregsz
= breg
!= 0 ? 4 : 0;
6406 /* If this is a reference to an external symbol, we want
6407 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6408 add $tempreg,$tempreg,$gp
6409 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6410 <op> $treg,<ofst>($tempreg)
6411 Otherwise, for local symbols, we want:
6412 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6413 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6414 assert (offset_expr
.X_op
== O_symbol
);
6415 frag_now
->tc_frag_data
.tc_fr_offset
=
6416 expr1
.X_add_number
= offset_expr
.X_add_number
;
6417 offset_expr
.X_add_number
= 0;
6418 if (expr1
.X_add_number
< -0x8000
6419 || expr1
.X_add_number
>= 0x8000)
6420 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6422 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6423 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6425 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6428 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6431 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6432 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
, breg
);
6433 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6434 (int) BFD_RELOC_LO16
, tempreg
);
6436 offset_expr
.X_add_number
= expr1
.X_add_number
;
6437 p
= frag_var (rs_machine_dependent
, 12 + bregsz
, 0,
6438 RELAX_ENCODE (16 + bregsz
, 8 + bregsz
,
6439 0, 4 + bregsz
, 0, 0),
6440 offset_expr
.X_add_symbol
, 0, NULL
);
6441 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6442 tempreg
, (int) BFD_RELOC_MIPS_GOT_PAGE
,
6445 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
6446 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
, breg
);
6447 macro_build (p
+ 4 + bregsz
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6448 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6450 else if (mips_pic
== EMBEDDED_PIC
)
6452 /* If there is no base register, we want
6453 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6454 If there is a base register, we want
6455 addu $tempreg,$breg,$gp
6456 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6458 assert (offset_expr
.X_op
== O_symbol
);
6461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6462 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6467 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6468 ADDRESS_ADD_INSN
, "d,v,t", tempreg
, breg
,
6470 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6471 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6484 load_register (&icnt
, treg
, &imm_expr
, 0);
6488 load_register (&icnt
, treg
, &imm_expr
, 1);
6492 if (imm_expr
.X_op
== O_constant
)
6494 load_register (&icnt
, AT
, &imm_expr
, 0);
6495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6496 "mtc1", "t,G", AT
, treg
);
6501 assert (offset_expr
.X_op
== O_symbol
6502 && strcmp (segment_name (S_GET_SEGMENT
6503 (offset_expr
.X_add_symbol
)),
6505 && offset_expr
.X_add_number
== 0);
6506 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6507 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6512 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6513 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6514 order 32 bits of the value and the low order 32 bits are either
6515 zero or in OFFSET_EXPR. */
6516 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6518 if (HAVE_64BIT_GPRS
)
6519 load_register (&icnt
, treg
, &imm_expr
, 1);
6524 if (target_big_endian
)
6536 load_register (&icnt
, hreg
, &imm_expr
, 0);
6539 if (offset_expr
.X_op
== O_absent
)
6540 move_register (&icnt
, lreg
, 0);
6543 assert (offset_expr
.X_op
== O_constant
);
6544 load_register (&icnt
, lreg
, &offset_expr
, 0);
6551 /* We know that sym is in the .rdata section. First we get the
6552 upper 16 bits of the address. */
6553 if (mips_pic
== NO_PIC
)
6555 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6557 else if (mips_pic
== SVR4_PIC
)
6559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6560 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6563 else if (mips_pic
== EMBEDDED_PIC
)
6565 /* For embedded PIC we pick up the entire address off $gp in
6566 a single instruction. */
6567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
6568 "t,r,j", AT
, mips_gp_register
,
6569 (int) BFD_RELOC_GPREL16
);
6570 offset_expr
.X_op
= O_constant
;
6571 offset_expr
.X_add_number
= 0;
6576 /* Now we load the register(s). */
6577 if (HAVE_64BIT_GPRS
)
6578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6579 treg
, (int) BFD_RELOC_LO16
, AT
);
6582 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6583 treg
, (int) BFD_RELOC_LO16
, AT
);
6586 /* FIXME: How in the world do we deal with the possible
6588 offset_expr
.X_add_number
+= 4;
6589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6590 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6594 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6595 does not become a variant frag. */
6596 frag_wane (frag_now
);
6602 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6603 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6604 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6605 the value and the low order 32 bits are either zero or in
6607 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6609 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6610 if (HAVE_64BIT_FPRS
)
6612 assert (HAVE_64BIT_GPRS
);
6613 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6614 "dmtc1", "t,S", AT
, treg
);
6618 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6619 "mtc1", "t,G", AT
, treg
+ 1);
6620 if (offset_expr
.X_op
== O_absent
)
6621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6622 "mtc1", "t,G", 0, treg
);
6625 assert (offset_expr
.X_op
== O_constant
);
6626 load_register (&icnt
, AT
, &offset_expr
, 0);
6627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6628 "mtc1", "t,G", AT
, treg
);
6634 assert (offset_expr
.X_op
== O_symbol
6635 && offset_expr
.X_add_number
== 0);
6636 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6637 if (strcmp (s
, ".lit8") == 0)
6639 if (mips_opts
.isa
!= ISA_MIPS1
)
6641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6642 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6646 breg
= mips_gp_register
;
6647 r
= BFD_RELOC_MIPS_LITERAL
;
6652 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6653 if (mips_pic
== SVR4_PIC
)
6654 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6655 ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6656 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6659 /* FIXME: This won't work for a 64 bit address. */
6660 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6663 if (mips_opts
.isa
!= ISA_MIPS1
)
6665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6666 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6668 /* To avoid confusion in tc_gen_reloc, we must ensure
6669 that this does not become a variant frag. */
6670 frag_wane (frag_now
);
6681 if (mips_opts
.arch
== CPU_R4650
)
6683 as_bad (_("opcode not supported on this processor"));
6686 /* Even on a big endian machine $fn comes before $fn+1. We have
6687 to adjust when loading from memory. */
6690 assert (mips_opts
.isa
== ISA_MIPS1
);
6691 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6692 target_big_endian
? treg
+ 1 : treg
,
6694 /* FIXME: A possible overflow which I don't know how to deal
6696 offset_expr
.X_add_number
+= 4;
6697 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6698 target_big_endian
? treg
: treg
+ 1,
6701 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6702 does not become a variant frag. */
6703 frag_wane (frag_now
);
6712 * The MIPS assembler seems to check for X_add_number not
6713 * being double aligned and generating:
6716 * addiu at,at,%lo(foo+1)
6719 * But, the resulting address is the same after relocation so why
6720 * generate the extra instruction?
6722 if (mips_opts
.arch
== CPU_R4650
)
6724 as_bad (_("opcode not supported on this processor"));
6727 /* Itbl support may require additional care here. */
6729 if (mips_opts
.isa
!= ISA_MIPS1
)
6740 if (mips_opts
.arch
== CPU_R4650
)
6742 as_bad (_("opcode not supported on this processor"));
6746 if (mips_opts
.isa
!= ISA_MIPS1
)
6754 /* Itbl support may require additional care here. */
6759 if (HAVE_64BIT_GPRS
)
6770 if (HAVE_64BIT_GPRS
)
6780 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6781 loads for the case of doing a pair of loads to simulate an 'ld'.
6782 This is not currently done by the compiler, and assembly coders
6783 writing embedded-pic code can cope. */
6785 if (offset_expr
.X_op
!= O_symbol
6786 && offset_expr
.X_op
!= O_constant
)
6788 as_bad (_("expression too complex"));
6789 offset_expr
.X_op
= O_constant
;
6792 /* Even on a big endian machine $fn comes before $fn+1. We have
6793 to adjust when loading from memory. We set coproc if we must
6794 load $fn+1 first. */
6795 /* Itbl support may require additional care here. */
6796 if (! target_big_endian
)
6799 if (mips_pic
== NO_PIC
6800 || offset_expr
.X_op
== O_constant
)
6804 /* If this is a reference to a GP relative symbol, we want
6805 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6806 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6807 If we have a base register, we use this
6809 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6810 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6811 If this is not a GP relative symbol, we want
6812 lui $at,<sym> (BFD_RELOC_HI16_S)
6813 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6814 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6815 If there is a base register, we add it to $at after the
6816 lui instruction. If there is a constant, we always use
6818 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6819 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6831 tempreg
= mips_gp_register
;
6838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6839 ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
,
6846 /* Itbl support may require additional care here. */
6847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6848 coproc
? treg
+ 1 : treg
,
6849 (int) BFD_RELOC_GPREL16
, tempreg
);
6850 offset_expr
.X_add_number
+= 4;
6852 /* Set mips_optimize to 2 to avoid inserting an
6854 hold_mips_optimize
= mips_optimize
;
6856 /* Itbl support may require additional care here. */
6857 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6858 coproc
? treg
: treg
+ 1,
6859 (int) BFD_RELOC_GPREL16
, tempreg
);
6860 mips_optimize
= hold_mips_optimize
;
6862 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6863 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6864 used_at
&& mips_opts
.noat
),
6865 offset_expr
.X_add_symbol
, 0, NULL
);
6867 /* We just generated two relocs. When tc_gen_reloc
6868 handles this case, it will skip the first reloc and
6869 handle the second. The second reloc already has an
6870 extra addend of 4, which we added above. We must
6871 subtract it out, and then subtract another 4 to make
6872 the first reloc come out right. The second reloc
6873 will come out right because we are going to add 4 to
6874 offset_expr when we build its instruction below.
6876 If we have a symbol, then we don't want to include
6877 the offset, because it will wind up being included
6878 when we generate the reloc. */
6880 if (offset_expr
.X_op
== O_constant
)
6881 offset_expr
.X_add_number
-= 8;
6884 offset_expr
.X_add_number
= -4;
6885 offset_expr
.X_op
= O_constant
;
6888 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6893 macro_build (p
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
6894 "d,v,t", AT
, breg
, AT
);
6898 /* Itbl support may require additional care here. */
6899 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6900 coproc
? treg
+ 1 : treg
,
6901 (int) BFD_RELOC_LO16
, AT
);
6904 /* FIXME: How do we handle overflow here? */
6905 offset_expr
.X_add_number
+= 4;
6906 /* Itbl support may require additional care here. */
6907 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6908 coproc
? treg
: treg
+ 1,
6909 (int) BFD_RELOC_LO16
, AT
);
6911 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6915 /* If this is a reference to an external symbol, we want
6916 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6921 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6923 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6924 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6925 If there is a base register we add it to $at before the
6926 lwc1 instructions. If there is a constant we include it
6927 in the lwc1 instructions. */
6929 expr1
.X_add_number
= offset_expr
.X_add_number
;
6930 offset_expr
.X_add_number
= 0;
6931 if (expr1
.X_add_number
< -0x8000
6932 || expr1
.X_add_number
>= 0x8000 - 4)
6933 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6938 frag_grow (24 + off
);
6939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6940 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6942 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6944 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6945 ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6946 /* Itbl support may require additional care here. */
6947 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6948 coproc
? treg
+ 1 : treg
,
6949 (int) BFD_RELOC_LO16
, AT
);
6950 expr1
.X_add_number
+= 4;
6952 /* Set mips_optimize to 2 to avoid inserting an undesired
6954 hold_mips_optimize
= mips_optimize
;
6956 /* Itbl support may require additional care here. */
6957 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6958 coproc
? treg
: treg
+ 1,
6959 (int) BFD_RELOC_LO16
, AT
);
6960 mips_optimize
= hold_mips_optimize
;
6962 (void) frag_var (rs_machine_dependent
, 0, 0,
6963 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6964 offset_expr
.X_add_symbol
, 0, NULL
);
6966 else if (mips_pic
== SVR4_PIC
)
6971 /* If this is a reference to an external symbol, we want
6972 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6974 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6979 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6981 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6982 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6983 If there is a base register we add it to $at before the
6984 lwc1 instructions. If there is a constant we include it
6985 in the lwc1 instructions. */
6987 expr1
.X_add_number
= offset_expr
.X_add_number
;
6988 offset_expr
.X_add_number
= 0;
6989 if (expr1
.X_add_number
< -0x8000
6990 || expr1
.X_add_number
>= 0x8000 - 4)
6991 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6992 if (reg_needs_delay (mips_gp_register
))
7001 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
7002 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
7003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7004 ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, mips_gp_register
);
7005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
7006 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
7007 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7010 ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7011 /* Itbl support may require additional care here. */
7012 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7013 coproc
? treg
+ 1 : treg
,
7014 (int) BFD_RELOC_LO16
, AT
);
7015 expr1
.X_add_number
+= 4;
7017 /* Set mips_optimize to 2 to avoid inserting an undesired
7019 hold_mips_optimize
= mips_optimize
;
7021 /* Itbl support may require additional care here. */
7022 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7023 coproc
? treg
: treg
+ 1,
7024 (int) BFD_RELOC_LO16
, AT
);
7025 mips_optimize
= hold_mips_optimize
;
7026 expr1
.X_add_number
-= 4;
7028 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
7029 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
7030 8 + gpdel
+ off
, 1, 0),
7031 offset_expr
.X_add_symbol
, 0, NULL
);
7034 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7037 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
7038 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
7041 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7045 macro_build (p
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
7046 "d,v,t", AT
, breg
, AT
);
7049 /* Itbl support may require additional care here. */
7050 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7051 coproc
? treg
+ 1 : treg
,
7052 (int) BFD_RELOC_LO16
, AT
);
7054 expr1
.X_add_number
+= 4;
7056 /* Set mips_optimize to 2 to avoid inserting an undesired
7058 hold_mips_optimize
= mips_optimize
;
7060 /* Itbl support may require additional care here. */
7061 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7062 coproc
? treg
: treg
+ 1,
7063 (int) BFD_RELOC_LO16
, AT
);
7064 mips_optimize
= hold_mips_optimize
;
7066 else if (mips_pic
== EMBEDDED_PIC
)
7068 /* If there is no base register, we use
7069 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7070 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7071 If we have a base register, we use
7073 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7074 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7078 tempreg
= mips_gp_register
;
7083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7084 ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
,
7090 /* Itbl support may require additional care here. */
7091 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7092 coproc
? treg
+ 1 : treg
,
7093 (int) BFD_RELOC_GPREL16
, tempreg
);
7094 offset_expr
.X_add_number
+= 4;
7095 /* Itbl support may require additional care here. */
7096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7097 coproc
? treg
: treg
+ 1,
7098 (int) BFD_RELOC_GPREL16
, tempreg
);
7114 assert (HAVE_32BIT_ADDRESSES
);
7115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7116 (int) BFD_RELOC_LO16
, breg
);
7117 offset_expr
.X_add_number
+= 4;
7118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
7119 (int) BFD_RELOC_LO16
, breg
);
7122 /* New code added to support COPZ instructions.
7123 This code builds table entries out of the macros in mip_opcodes.
7124 R4000 uses interlocks to handle coproc delays.
7125 Other chips (like the R3000) require nops to be inserted for delays.
7127 FIXME: Currently, we require that the user handle delays.
7128 In order to fill delay slots for non-interlocked chips,
7129 we must have a way to specify delays based on the coprocessor.
7130 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7131 What are the side-effects of the cop instruction?
7132 What cache support might we have and what are its effects?
7133 Both coprocessor & memory require delays. how long???
7134 What registers are read/set/modified?
7136 If an itbl is provided to interpret cop instructions,
7137 this knowledge can be encoded in the itbl spec. */
7151 /* For now we just do C (same as Cz). The parameter will be
7152 stored in insn_opcode by mips_ip. */
7153 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
7158 move_register (&icnt
, dreg
, sreg
);
7161 #ifdef LOSING_COMPILER
7163 /* Try and see if this is a new itbl instruction.
7164 This code builds table entries out of the macros in mip_opcodes.
7165 FIXME: For now we just assemble the expression and pass it's
7166 value along as a 32-bit immediate.
7167 We may want to have the assembler assemble this value,
7168 so that we gain the assembler's knowledge of delay slots,
7170 Would it be more efficient to use mask (id) here? */
7171 if (itbl_have_entries
7172 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7174 s
= ip
->insn_mo
->name
;
7176 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7177 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
7184 as_warn (_("Macro used $at after \".set noat\""));
7189 struct mips_cl_insn
*ip
;
7191 register int treg
, sreg
, dreg
, breg
;
7207 bfd_reloc_code_real_type r
;
7210 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7211 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7212 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7213 mask
= ip
->insn_mo
->mask
;
7215 expr1
.X_op
= O_constant
;
7216 expr1
.X_op_symbol
= NULL
;
7217 expr1
.X_add_symbol
= NULL
;
7218 expr1
.X_add_number
= 1;
7222 #endif /* LOSING_COMPILER */
7227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7228 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7236 /* The MIPS assembler some times generates shifts and adds. I'm
7237 not trying to be that fancy. GCC should do this for us
7239 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7240 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7241 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7256 mips_emit_delays (TRUE
);
7257 ++mips_opts
.noreorder
;
7258 mips_any_noreorder
= 1;
7260 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7261 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7262 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7266 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7271 "s,t,q", dreg
, AT
, 6);
7274 expr1
.X_add_number
= 8;
7275 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
7277 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7282 --mips_opts
.noreorder
;
7283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
7296 mips_emit_delays (TRUE
);
7297 ++mips_opts
.noreorder
;
7298 mips_any_noreorder
= 1;
7300 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7302 dbl
? "dmultu" : "multu",
7303 "s,t", sreg
, imm
? AT
: treg
);
7304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7313 expr1
.X_add_number
= 8;
7314 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
7315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7320 --mips_opts
.noreorder
;
7324 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7336 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
7337 "d,w", tempreg
, treg
);
7338 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7339 "d,t,s", dreg
, sreg
, tempreg
);
7344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7345 "d,v,t", AT
, 0, treg
);
7346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7347 "d,t,s", AT
, sreg
, AT
);
7348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7349 "d,t,s", dreg
, sreg
, treg
);
7350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7351 "d,v,t", dreg
, dreg
, AT
);
7355 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7367 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
7368 "d,w", tempreg
, treg
);
7369 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7370 "d,t,s", dreg
, sreg
, tempreg
);
7375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7376 "d,v,t", AT
, 0, treg
);
7377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7378 "d,t,s", AT
, sreg
, AT
);
7379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7380 "d,t,s", dreg
, sreg
, treg
);
7381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7382 "d,v,t", dreg
, dreg
, AT
);
7390 if (imm_expr
.X_op
!= O_constant
)
7391 as_bad (_("Improper rotate count"));
7392 rot
= imm_expr
.X_add_number
& 0x3f;
7393 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7395 rot
= (64 - rot
) & 0x3f;
7397 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7398 "d,w,<", dreg
, sreg
, rot
- 32);
7400 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7401 "d,w,<", dreg
, sreg
, rot
);
7406 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7407 "d,w,<", dreg
, sreg
, 0);
7410 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7411 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7413 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7414 "d,w,<", AT
, sreg
, rot
);
7415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7416 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7418 "d,v,t", dreg
, dreg
, AT
);
7426 if (imm_expr
.X_op
!= O_constant
)
7427 as_bad (_("Improper rotate count"));
7428 rot
= imm_expr
.X_add_number
& 0x1f;
7429 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7431 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7432 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7438 "d,w,<", dreg
, sreg
, 0);
7441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7442 "d,w,<", AT
, sreg
, rot
);
7443 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7444 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7446 "d,v,t", dreg
, dreg
, AT
);
7451 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7453 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7454 "d,t,s", dreg
, sreg
, treg
);
7457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7458 "d,v,t", AT
, 0, treg
);
7459 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7460 "d,t,s", AT
, sreg
, AT
);
7461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7462 "d,t,s", dreg
, sreg
, treg
);
7463 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7464 "d,v,t", dreg
, dreg
, AT
);
7468 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7470 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7471 "d,t,s", dreg
, sreg
, treg
);
7474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7475 "d,v,t", AT
, 0, treg
);
7476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7477 "d,t,s", AT
, sreg
, AT
);
7478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7479 "d,t,s", dreg
, sreg
, treg
);
7480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7481 "d,v,t", dreg
, dreg
, AT
);
7489 if (imm_expr
.X_op
!= O_constant
)
7490 as_bad (_("Improper rotate count"));
7491 rot
= imm_expr
.X_add_number
& 0x3f;
7492 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7495 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7496 "d,w,<", dreg
, sreg
, rot
- 32);
7498 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7499 "d,w,<", dreg
, sreg
, rot
);
7504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7505 "d,w,<", dreg
, sreg
, 0);
7508 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7509 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7511 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7512 "d,w,<", AT
, sreg
, rot
);
7513 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7514 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7516 "d,v,t", dreg
, dreg
, AT
);
7524 if (imm_expr
.X_op
!= O_constant
)
7525 as_bad (_("Improper rotate count"));
7526 rot
= imm_expr
.X_add_number
& 0x1f;
7527 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7529 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7530 "d,w,<", dreg
, sreg
, rot
);
7535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7536 "d,w,<", dreg
, sreg
, 0);
7539 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7540 "d,w,<", AT
, sreg
, rot
);
7541 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7542 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7544 "d,v,t", dreg
, dreg
, AT
);
7549 if (mips_opts
.arch
== CPU_R4650
)
7551 as_bad (_("opcode not supported on this processor"));
7554 assert (mips_opts
.isa
== ISA_MIPS1
);
7555 /* Even on a big endian machine $fn comes before $fn+1. We have
7556 to adjust when storing to memory. */
7557 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7558 target_big_endian
? treg
+ 1 : treg
,
7559 (int) BFD_RELOC_LO16
, breg
);
7560 offset_expr
.X_add_number
+= 4;
7561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7562 target_big_endian
? treg
: treg
+ 1,
7563 (int) BFD_RELOC_LO16
, breg
);
7568 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7569 treg
, (int) BFD_RELOC_LO16
);
7571 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7572 sreg
, (int) BFD_RELOC_LO16
);
7575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7576 "d,v,t", dreg
, sreg
, treg
);
7577 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7578 dreg
, (int) BFD_RELOC_LO16
);
7583 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7585 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7586 sreg
, (int) BFD_RELOC_LO16
);
7591 as_warn (_("Instruction %s: result is always false"),
7593 move_register (&icnt
, dreg
, 0);
7596 if (imm_expr
.X_op
== O_constant
7597 && imm_expr
.X_add_number
>= 0
7598 && imm_expr
.X_add_number
< 0x10000)
7600 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7601 sreg
, (int) BFD_RELOC_LO16
);
7604 else if (imm_expr
.X_op
== O_constant
7605 && imm_expr
.X_add_number
> -0x8000
7606 && imm_expr
.X_add_number
< 0)
7608 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7609 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7610 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7611 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7616 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7618 "d,v,t", dreg
, sreg
, AT
);
7621 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7622 (int) BFD_RELOC_LO16
);
7627 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7635 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7636 (int) BFD_RELOC_LO16
);
7639 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7641 if (imm_expr
.X_op
== O_constant
7642 && imm_expr
.X_add_number
>= -0x8000
7643 && imm_expr
.X_add_number
< 0x8000)
7645 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7646 mask
== M_SGE_I
? "slti" : "sltiu",
7647 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7652 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7654 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7658 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7659 (int) BFD_RELOC_LO16
);
7664 case M_SGT
: /* sreg > treg <==> treg < sreg */
7670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7674 case M_SGT_I
: /* sreg > I <==> I < sreg */
7680 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7685 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7693 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7694 (int) BFD_RELOC_LO16
);
7697 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7703 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7706 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7707 (int) BFD_RELOC_LO16
);
7711 if (imm_expr
.X_op
== O_constant
7712 && imm_expr
.X_add_number
>= -0x8000
7713 && imm_expr
.X_add_number
< 0x8000)
7715 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7716 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7719 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7725 if (imm_expr
.X_op
== O_constant
7726 && imm_expr
.X_add_number
>= -0x8000
7727 && imm_expr
.X_add_number
< 0x8000)
7729 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7730 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7733 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7735 "d,v,t", dreg
, sreg
, AT
);
7740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7741 "d,v,t", dreg
, 0, treg
);
7743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7744 "d,v,t", dreg
, 0, sreg
);
7747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7748 "d,v,t", dreg
, sreg
, treg
);
7749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7750 "d,v,t", dreg
, 0, dreg
);
7755 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7758 "d,v,t", dreg
, 0, sreg
);
7763 as_warn (_("Instruction %s: result is always true"),
7765 macro_build ((char *) NULL
, &icnt
, &expr1
,
7766 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7767 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7770 if (imm_expr
.X_op
== O_constant
7771 && imm_expr
.X_add_number
>= 0
7772 && imm_expr
.X_add_number
< 0x10000)
7774 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7775 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7778 else if (imm_expr
.X_op
== O_constant
7779 && imm_expr
.X_add_number
> -0x8000
7780 && imm_expr
.X_add_number
< 0)
7782 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7783 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7784 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7785 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7790 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7792 "d,v,t", dreg
, sreg
, AT
);
7795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7796 "d,v,t", dreg
, 0, dreg
);
7804 if (imm_expr
.X_op
== O_constant
7805 && imm_expr
.X_add_number
> -0x8000
7806 && imm_expr
.X_add_number
<= 0x8000)
7808 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7809 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7810 dbl
? "daddi" : "addi",
7811 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7814 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7816 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7822 if (imm_expr
.X_op
== O_constant
7823 && imm_expr
.X_add_number
> -0x8000
7824 && imm_expr
.X_add_number
<= 0x8000)
7826 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7827 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7828 dbl
? "daddiu" : "addiu",
7829 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7832 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7833 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7834 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7855 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7862 assert (mips_opts
.isa
== ISA_MIPS1
);
7863 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7864 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7867 * Is the double cfc1 instruction a bug in the mips assembler;
7868 * or is there a reason for it?
7870 mips_emit_delays (TRUE
);
7871 ++mips_opts
.noreorder
;
7872 mips_any_noreorder
= 1;
7873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7878 expr1
.X_add_number
= 3;
7879 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7880 (int) BFD_RELOC_LO16
);
7881 expr1
.X_add_number
= 2;
7882 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7883 (int) BFD_RELOC_LO16
);
7884 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7888 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7892 --mips_opts
.noreorder
;
7901 if (offset_expr
.X_add_number
>= 0x7fff)
7902 as_bad (_("operand overflow"));
7903 if (! target_big_endian
)
7904 ++offset_expr
.X_add_number
;
7905 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", AT
,
7906 (int) BFD_RELOC_LO16
, breg
);
7907 if (! target_big_endian
)
7908 --offset_expr
.X_add_number
;
7910 ++offset_expr
.X_add_number
;
7911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", treg
,
7912 (int) BFD_RELOC_LO16
, breg
);
7913 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7929 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7930 as_bad (_("operand overflow"));
7935 if (! target_big_endian
)
7936 offset_expr
.X_add_number
+= off
;
7937 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", tempreg
,
7938 (int) BFD_RELOC_LO16
, breg
);
7939 if (! target_big_endian
)
7940 offset_expr
.X_add_number
-= off
;
7942 offset_expr
.X_add_number
+= off
;
7943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", tempreg
,
7944 (int) BFD_RELOC_LO16
, breg
);
7946 /* If necessary, move the result in tempreg the final destination. */
7947 if (treg
== tempreg
)
7949 /* Protect second load's delay slot. */
7950 if (!gpr_interlocks
)
7951 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7952 move_register (&icnt
, treg
, tempreg
);
7966 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7968 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7969 ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7970 if (! target_big_endian
)
7971 expr1
.X_add_number
= off
;
7973 expr1
.X_add_number
= 0;
7974 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7975 (int) BFD_RELOC_LO16
, AT
);
7976 if (! target_big_endian
)
7977 expr1
.X_add_number
= 0;
7979 expr1
.X_add_number
= off
;
7980 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7981 (int) BFD_RELOC_LO16
, AT
);
7987 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7990 ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7991 if (target_big_endian
)
7992 expr1
.X_add_number
= 0;
7993 macro_build ((char *) NULL
, &icnt
, &expr1
,
7994 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7995 (int) BFD_RELOC_LO16
, AT
);
7996 if (target_big_endian
)
7997 expr1
.X_add_number
= 1;
7999 expr1
.X_add_number
= 0;
8000 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8001 (int) BFD_RELOC_LO16
, AT
);
8002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8009 if (offset_expr
.X_add_number
>= 0x7fff)
8010 as_bad (_("operand overflow"));
8011 if (target_big_endian
)
8012 ++offset_expr
.X_add_number
;
8013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
8014 (int) BFD_RELOC_LO16
, breg
);
8015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8017 if (target_big_endian
)
8018 --offset_expr
.X_add_number
;
8020 ++offset_expr
.X_add_number
;
8021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
8022 (int) BFD_RELOC_LO16
, breg
);
8035 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8036 as_bad (_("operand overflow"));
8037 if (! target_big_endian
)
8038 offset_expr
.X_add_number
+= off
;
8039 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
8040 (int) BFD_RELOC_LO16
, breg
);
8041 if (! target_big_endian
)
8042 offset_expr
.X_add_number
-= off
;
8044 offset_expr
.X_add_number
+= off
;
8045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
8046 (int) BFD_RELOC_LO16
, breg
);
8060 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8063 ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8064 if (! target_big_endian
)
8065 expr1
.X_add_number
= off
;
8067 expr1
.X_add_number
= 0;
8068 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
8069 (int) BFD_RELOC_LO16
, AT
);
8070 if (! target_big_endian
)
8071 expr1
.X_add_number
= 0;
8073 expr1
.X_add_number
= off
;
8074 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
8075 (int) BFD_RELOC_LO16
, AT
);
8080 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8083 ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8084 if (! target_big_endian
)
8085 expr1
.X_add_number
= 0;
8086 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8087 (int) BFD_RELOC_LO16
, AT
);
8088 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8090 if (! target_big_endian
)
8091 expr1
.X_add_number
= 1;
8093 expr1
.X_add_number
= 0;
8094 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8095 (int) BFD_RELOC_LO16
, AT
);
8096 if (! target_big_endian
)
8097 expr1
.X_add_number
= 0;
8099 expr1
.X_add_number
= 1;
8100 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8101 (int) BFD_RELOC_LO16
, AT
);
8102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8109 /* FIXME: Check if this is one of the itbl macros, since they
8110 are added dynamically. */
8111 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8115 as_warn (_("Macro used $at after \".set noat\""));
8118 /* Implement macros in mips16 mode. */
8122 struct mips_cl_insn
*ip
;
8125 int xreg
, yreg
, zreg
, tmp
;
8129 const char *s
, *s2
, *s3
;
8131 mask
= ip
->insn_mo
->mask
;
8133 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
8134 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
8135 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
8139 expr1
.X_op
= O_constant
;
8140 expr1
.X_op_symbol
= NULL
;
8141 expr1
.X_add_symbol
= NULL
;
8142 expr1
.X_add_number
= 1;
8161 mips_emit_delays (TRUE
);
8162 ++mips_opts
.noreorder
;
8163 mips_any_noreorder
= 1;
8164 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8165 dbl
? "ddiv" : "div",
8166 "0,x,y", xreg
, yreg
);
8167 expr1
.X_add_number
= 2;
8168 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
8172 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8173 since that causes an overflow. We should do that as well,
8174 but I don't see how to do the comparisons without a temporary
8176 --mips_opts
.noreorder
;
8177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
8196 mips_emit_delays (TRUE
);
8197 ++mips_opts
.noreorder
;
8198 mips_any_noreorder
= 1;
8199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
8201 expr1
.X_add_number
= 2;
8202 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8203 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
8205 --mips_opts
.noreorder
;
8206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
8212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8213 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8214 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
8223 if (imm_expr
.X_op
!= O_constant
)
8224 as_bad (_("Unsupported large constant"));
8225 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8226 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
8227 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8231 if (imm_expr
.X_op
!= O_constant
)
8232 as_bad (_("Unsupported large constant"));
8233 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8234 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
8239 if (imm_expr
.X_op
!= O_constant
)
8240 as_bad (_("Unsupported large constant"));
8241 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8242 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
8265 goto do_reverse_branch
;
8269 goto do_reverse_branch
;
8281 goto do_reverse_branch
;
8292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
8294 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8321 goto do_addone_branch_i
;
8326 goto do_addone_branch_i
;
8341 goto do_addone_branch_i
;
8348 if (imm_expr
.X_op
!= O_constant
)
8349 as_bad (_("Unsupported large constant"));
8350 ++imm_expr
.X_add_number
;
8353 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
8354 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8358 expr1
.X_add_number
= 0;
8359 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
8361 move_register (&icnt
, xreg
, yreg
);
8362 expr1
.X_add_number
= 2;
8363 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
8364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8365 "neg", "x,w", xreg
, xreg
);
8369 /* For consistency checking, verify that all bits are specified either
8370 by the match/mask part of the instruction definition, or by the
8373 validate_mips_insn (opc
)
8374 const struct mips_opcode
*opc
;
8376 const char *p
= opc
->args
;
8378 unsigned long used_bits
= opc
->mask
;
8380 if ((used_bits
& opc
->match
) != opc
->match
)
8382 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8383 opc
->name
, opc
->args
);
8386 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8396 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8397 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8398 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8399 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8400 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8402 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8403 c
, opc
->name
, opc
->args
);
8407 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8408 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8410 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8411 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8412 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8413 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8415 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8416 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8418 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8419 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8421 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8422 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8423 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8424 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8425 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8426 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8427 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8428 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8429 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8430 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8431 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8432 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8433 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8434 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8435 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8436 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8437 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8439 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8440 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8441 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8442 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8444 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8445 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8446 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8447 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8448 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8449 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8450 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8451 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8452 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8455 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8456 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8457 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8458 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8459 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8463 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8464 c
, opc
->name
, opc
->args
);
8468 if (used_bits
!= 0xffffffff)
8470 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8471 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8477 /* This routine assembles an instruction into its binary format. As a
8478 side effect, it sets one of the global variables imm_reloc or
8479 offset_reloc to the type of relocation to do if one of the operands
8480 is an address expression. */
8485 struct mips_cl_insn
*ip
;
8490 struct mips_opcode
*insn
;
8493 unsigned int lastregno
= 0;
8494 unsigned int lastpos
= 0;
8495 unsigned int limlo
, limhi
;
8501 /* If the instruction contains a '.', we first try to match an instruction
8502 including the '.'. Then we try again without the '.'. */
8504 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8507 /* If we stopped on whitespace, then replace the whitespace with null for
8508 the call to hash_find. Save the character we replaced just in case we
8509 have to re-parse the instruction. */
8516 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8518 /* If we didn't find the instruction in the opcode table, try again, but
8519 this time with just the instruction up to, but not including the
8523 /* Restore the character we overwrite above (if any). */
8527 /* Scan up to the first '.' or whitespace. */
8529 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8533 /* If we did not find a '.', then we can quit now. */
8536 insn_error
= "unrecognized opcode";
8540 /* Lookup the instruction in the hash table. */
8542 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8544 insn_error
= "unrecognized opcode";
8554 assert (strcmp (insn
->name
, str
) == 0);
8556 if (OPCODE_IS_MEMBER (insn
,
8558 | (file_ase_mips16
? INSN_MIPS16
: 0)
8559 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8560 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8566 if (insn
->pinfo
!= INSN_MACRO
)
8568 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8574 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8575 && strcmp (insn
->name
, insn
[1].name
) == 0)
8584 static char buf
[100];
8586 _("opcode not supported on this processor: %s (%s)"),
8587 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8588 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8598 ip
->insn_opcode
= insn
->match
;
8600 for (args
= insn
->args
;; ++args
)
8604 s
+= strspn (s
, " \t");
8608 case '\0': /* end of args */
8621 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8625 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8629 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8633 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8639 /* Handle optional base register.
8640 Either the base register is omitted or
8641 we must have a left paren. */
8642 /* This is dependent on the next operand specifier
8643 is a base register specification. */
8644 assert (args
[1] == 'b' || args
[1] == '5'
8645 || args
[1] == '-' || args
[1] == '4');
8649 case ')': /* these must match exactly */
8656 case '+': /* Opcode extension character. */
8659 case 'A': /* ins/ext position, becomes LSB. */
8662 my_getExpression (&imm_expr
, s
);
8663 check_absolute_expr (ip
, &imm_expr
);
8664 if ((unsigned long) imm_expr
.X_add_number
< limlo
8665 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8667 as_bad (_("Improper position (%lu)"),
8668 (unsigned long) imm_expr
.X_add_number
);
8669 imm_expr
.X_add_number
= limlo
;
8671 lastpos
= imm_expr
.X_add_number
;
8672 ip
->insn_opcode
|= (imm_expr
.X_add_number
8673 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8674 imm_expr
.X_op
= O_absent
;
8678 case 'B': /* ins size, becomes MSB. */
8681 my_getExpression (&imm_expr
, s
);
8682 check_absolute_expr (ip
, &imm_expr
);
8683 /* Check for negative input so that small negative numbers
8684 will not succeed incorrectly. The checks against
8685 (pos+size) transitively check "size" itself,
8686 assuming that "pos" is reasonable. */
8687 if ((long) imm_expr
.X_add_number
< 0
8688 || ((unsigned long) imm_expr
.X_add_number
8690 || ((unsigned long) imm_expr
.X_add_number
8693 as_bad (_("Improper insert size (%lu, position %lu)"),
8694 (unsigned long) imm_expr
.X_add_number
,
8695 (unsigned long) lastpos
);
8696 imm_expr
.X_add_number
= limlo
- lastpos
;
8698 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8699 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8700 imm_expr
.X_op
= O_absent
;
8704 case 'C': /* ext size, becomes MSBD. */
8707 my_getExpression (&imm_expr
, s
);
8708 check_absolute_expr (ip
, &imm_expr
);
8709 /* Check for negative input so that small negative numbers
8710 will not succeed incorrectly. The checks against
8711 (pos+size) transitively check "size" itself,
8712 assuming that "pos" is reasonable. */
8713 if ((long) imm_expr
.X_add_number
< 0
8714 || ((unsigned long) imm_expr
.X_add_number
8716 || ((unsigned long) imm_expr
.X_add_number
8719 as_bad (_("Improper extract size (%lu, position %lu)"),
8720 (unsigned long) imm_expr
.X_add_number
,
8721 (unsigned long) lastpos
);
8722 imm_expr
.X_add_number
= limlo
- lastpos
;
8724 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8725 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8726 imm_expr
.X_op
= O_absent
;
8731 /* +D is for disassembly only; never match. */
8735 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8736 *args
, insn
->name
, insn
->args
);
8737 /* Further processing is fruitless. */
8742 case '<': /* must be at least one digit */
8744 * According to the manual, if the shift amount is greater
8745 * than 31 or less than 0, then the shift amount should be
8746 * mod 32. In reality the mips assembler issues an error.
8747 * We issue a warning and mask out all but the low 5 bits.
8749 my_getExpression (&imm_expr
, s
);
8750 check_absolute_expr (ip
, &imm_expr
);
8751 if ((unsigned long) imm_expr
.X_add_number
> 31)
8753 as_warn (_("Improper shift amount (%lu)"),
8754 (unsigned long) imm_expr
.X_add_number
);
8755 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8757 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8758 imm_expr
.X_op
= O_absent
;
8762 case '>': /* shift amount minus 32 */
8763 my_getExpression (&imm_expr
, s
);
8764 check_absolute_expr (ip
, &imm_expr
);
8765 if ((unsigned long) imm_expr
.X_add_number
< 32
8766 || (unsigned long) imm_expr
.X_add_number
> 63)
8768 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8769 imm_expr
.X_op
= O_absent
;
8773 case 'k': /* cache code */
8774 case 'h': /* prefx code */
8775 my_getExpression (&imm_expr
, s
);
8776 check_absolute_expr (ip
, &imm_expr
);
8777 if ((unsigned long) imm_expr
.X_add_number
> 31)
8779 as_warn (_("Invalid value for `%s' (%lu)"),
8781 (unsigned long) imm_expr
.X_add_number
);
8782 imm_expr
.X_add_number
&= 0x1f;
8785 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8787 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8788 imm_expr
.X_op
= O_absent
;
8792 case 'c': /* break code */
8793 my_getExpression (&imm_expr
, s
);
8794 check_absolute_expr (ip
, &imm_expr
);
8795 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8797 as_warn (_("Illegal break code (%lu)"),
8798 (unsigned long) imm_expr
.X_add_number
);
8799 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8801 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8802 imm_expr
.X_op
= O_absent
;
8806 case 'q': /* lower break code */
8807 my_getExpression (&imm_expr
, s
);
8808 check_absolute_expr (ip
, &imm_expr
);
8809 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8811 as_warn (_("Illegal lower break code (%lu)"),
8812 (unsigned long) imm_expr
.X_add_number
);
8813 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8815 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8816 imm_expr
.X_op
= O_absent
;
8820 case 'B': /* 20-bit syscall/break code. */
8821 my_getExpression (&imm_expr
, s
);
8822 check_absolute_expr (ip
, &imm_expr
);
8823 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8824 as_warn (_("Illegal 20-bit code (%lu)"),
8825 (unsigned long) imm_expr
.X_add_number
);
8826 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8827 imm_expr
.X_op
= O_absent
;
8831 case 'C': /* Coprocessor code */
8832 my_getExpression (&imm_expr
, s
);
8833 check_absolute_expr (ip
, &imm_expr
);
8834 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8836 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8837 (unsigned long) imm_expr
.X_add_number
);
8838 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8840 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8841 imm_expr
.X_op
= O_absent
;
8845 case 'J': /* 19-bit wait code. */
8846 my_getExpression (&imm_expr
, s
);
8847 check_absolute_expr (ip
, &imm_expr
);
8848 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8849 as_warn (_("Illegal 19-bit code (%lu)"),
8850 (unsigned long) imm_expr
.X_add_number
);
8851 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8852 imm_expr
.X_op
= O_absent
;
8856 case 'P': /* Performance register */
8857 my_getExpression (&imm_expr
, s
);
8858 check_absolute_expr (ip
, &imm_expr
);
8859 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8861 as_warn (_("Invalid performance register (%lu)"),
8862 (unsigned long) imm_expr
.X_add_number
);
8863 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8865 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8866 imm_expr
.X_op
= O_absent
;
8870 case 'b': /* base register */
8871 case 'd': /* destination register */
8872 case 's': /* source register */
8873 case 't': /* target register */
8874 case 'r': /* both target and source */
8875 case 'v': /* both dest and source */
8876 case 'w': /* both dest and target */
8877 case 'E': /* coprocessor target register */
8878 case 'G': /* coprocessor destination register */
8879 case 'K': /* 'rdhwr' destination register */
8880 case 'x': /* ignore register name */
8881 case 'z': /* must be zero register */
8882 case 'U': /* destination register (clo/clz). */
8897 while (ISDIGIT (*s
));
8899 as_bad (_("Invalid register number (%d)"), regno
);
8901 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8905 if (s
[1] == 'r' && s
[2] == 'a')
8910 else if (s
[1] == 'f' && s
[2] == 'p')
8915 else if (s
[1] == 's' && s
[2] == 'p')
8920 else if (s
[1] == 'g' && s
[2] == 'p')
8925 else if (s
[1] == 'a' && s
[2] == 't')
8930 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8935 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8940 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8945 else if (itbl_have_entries
)
8950 p
= s
+ 1; /* advance past '$' */
8951 n
= itbl_get_field (&p
); /* n is name */
8953 /* See if this is a register defined in an
8955 if (itbl_get_reg_val (n
, &r
))
8957 /* Get_field advances to the start of
8958 the next field, so we need to back
8959 rack to the end of the last field. */
8963 s
= strchr (s
, '\0');
8977 as_warn (_("Used $at without \".set noat\""));
8983 if (c
== 'r' || c
== 'v' || c
== 'w')
8990 /* 'z' only matches $0. */
8991 if (c
== 'z' && regno
!= 0)
8994 /* Now that we have assembled one operand, we use the args string
8995 * to figure out where it goes in the instruction. */
9002 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
9007 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9010 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9011 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9016 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9019 /* This case exists because on the r3000 trunc
9020 expands into a macro which requires a gp
9021 register. On the r6000 or r4000 it is
9022 assembled into a single instruction which
9023 ignores the register. Thus the insn version
9024 is MIPS_ISA2 and uses 'x', and the macro
9025 version is MIPS_ISA1 and uses 't'. */
9028 /* This case is for the div instruction, which
9029 acts differently if the destination argument
9030 is $0. This only matches $0, and is checked
9031 outside the switch. */
9034 /* Itbl operand; not yet implemented. FIXME ?? */
9036 /* What about all other operands like 'i', which
9037 can be specified in the opcode table? */
9047 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
9050 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
9055 case 'O': /* MDMX alignment immediate constant. */
9056 my_getExpression (&imm_expr
, s
);
9057 check_absolute_expr (ip
, &imm_expr
);
9058 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9060 as_warn ("Improper align amount (%ld), using low bits",
9061 (long) imm_expr
.X_add_number
);
9062 imm_expr
.X_add_number
&= OP_MASK_ALN
;
9064 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
9065 imm_expr
.X_op
= O_absent
;
9069 case 'Q': /* MDMX vector, element sel, or const. */
9072 /* MDMX Immediate. */
9073 my_getExpression (&imm_expr
, s
);
9074 check_absolute_expr (ip
, &imm_expr
);
9075 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9077 as_warn (_("Invalid MDMX Immediate (%ld)"),
9078 (long) imm_expr
.X_add_number
);
9079 imm_expr
.X_add_number
&= OP_MASK_FT
;
9081 imm_expr
.X_add_number
&= OP_MASK_FT
;
9082 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9083 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9085 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9086 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
9087 imm_expr
.X_op
= O_absent
;
9091 /* Not MDMX Immediate. Fall through. */
9092 case 'X': /* MDMX destination register. */
9093 case 'Y': /* MDMX source register. */
9094 case 'Z': /* MDMX target register. */
9096 case 'D': /* floating point destination register */
9097 case 'S': /* floating point source register */
9098 case 'T': /* floating point target register */
9099 case 'R': /* floating point source register */
9103 /* Accept $fN for FP and MDMX register numbers, and in
9104 addition accept $vN for MDMX register numbers. */
9105 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
9106 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
9117 while (ISDIGIT (*s
));
9120 as_bad (_("Invalid float register number (%d)"), regno
);
9122 if ((regno
& 1) != 0
9124 && ! (strcmp (str
, "mtc1") == 0
9125 || strcmp (str
, "mfc1") == 0
9126 || strcmp (str
, "lwc1") == 0
9127 || strcmp (str
, "swc1") == 0
9128 || strcmp (str
, "l.s") == 0
9129 || strcmp (str
, "s.s") == 0))
9130 as_warn (_("Float register should be even, was %d"),
9138 if (c
== 'V' || c
== 'W')
9149 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
9154 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
9157 /* This is like 'Z', but also needs to fix the MDMX
9158 vector/scalar select bits. Note that the
9159 scalar immediate case is handled above. */
9162 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9163 int max_el
= (is_qh
? 3 : 7);
9165 my_getExpression(&imm_expr
, s
);
9166 check_absolute_expr (ip
, &imm_expr
);
9168 if (imm_expr
.X_add_number
> max_el
)
9169 as_bad(_("Bad element selector %ld"),
9170 (long) imm_expr
.X_add_number
);
9171 imm_expr
.X_add_number
&= max_el
;
9172 ip
->insn_opcode
|= (imm_expr
.X_add_number
9176 as_warn(_("Expecting ']' found '%s'"), s
);
9182 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9183 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9186 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9193 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
9196 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
9206 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
9209 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
9215 my_getExpression (&imm_expr
, s
);
9216 if (imm_expr
.X_op
!= O_big
9217 && imm_expr
.X_op
!= O_constant
)
9218 insn_error
= _("absolute expression required");
9223 my_getExpression (&offset_expr
, s
);
9224 *imm_reloc
= BFD_RELOC_32
;
9237 unsigned char temp
[8];
9239 unsigned int length
;
9244 /* These only appear as the last operand in an
9245 instruction, and every instruction that accepts
9246 them in any variant accepts them in all variants.
9247 This means we don't have to worry about backing out
9248 any changes if the instruction does not match.
9250 The difference between them is the size of the
9251 floating point constant and where it goes. For 'F'
9252 and 'L' the constant is 64 bits; for 'f' and 'l' it
9253 is 32 bits. Where the constant is placed is based
9254 on how the MIPS assembler does things:
9257 f -- immediate value
9260 The .lit4 and .lit8 sections are only used if
9261 permitted by the -G argument.
9263 When generating embedded PIC code, we use the
9264 .lit8 section but not the .lit4 section (we can do
9265 .lit4 inline easily; we need to put .lit8
9266 somewhere in the data segment, and using .lit8
9267 permits the linker to eventually combine identical
9270 The code below needs to know whether the target register
9271 is 32 or 64 bits wide. It relies on the fact 'f' and
9272 'F' are used with GPR-based instructions and 'l' and
9273 'L' are used with FPR-based instructions. */
9275 f64
= *args
== 'F' || *args
== 'L';
9276 using_gprs
= *args
== 'F' || *args
== 'f';
9278 save_in
= input_line_pointer
;
9279 input_line_pointer
= s
;
9280 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9282 s
= input_line_pointer
;
9283 input_line_pointer
= save_in
;
9284 if (err
!= NULL
&& *err
!= '\0')
9286 as_bad (_("Bad floating point constant: %s"), err
);
9287 memset (temp
, '\0', sizeof temp
);
9288 length
= f64
? 8 : 4;
9291 assert (length
== (unsigned) (f64
? 8 : 4));
9295 && (! USE_GLOBAL_POINTER_OPT
9296 || mips_pic
== EMBEDDED_PIC
9297 || g_switch_value
< 4
9298 || (temp
[0] == 0 && temp
[1] == 0)
9299 || (temp
[2] == 0 && temp
[3] == 0))))
9301 imm_expr
.X_op
= O_constant
;
9302 if (! target_big_endian
)
9303 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9305 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9308 && ! mips_disable_float_construction
9309 /* Constants can only be constructed in GPRs and
9310 copied to FPRs if the GPRs are at least as wide
9311 as the FPRs. Force the constant into memory if
9312 we are using 64-bit FPRs but the GPRs are only
9315 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9316 && ((temp
[0] == 0 && temp
[1] == 0)
9317 || (temp
[2] == 0 && temp
[3] == 0))
9318 && ((temp
[4] == 0 && temp
[5] == 0)
9319 || (temp
[6] == 0 && temp
[7] == 0)))
9321 /* The value is simple enough to load with a couple of
9322 instructions. If using 32-bit registers, set
9323 imm_expr to the high order 32 bits and offset_expr to
9324 the low order 32 bits. Otherwise, set imm_expr to
9325 the entire 64 bit constant. */
9326 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9328 imm_expr
.X_op
= O_constant
;
9329 offset_expr
.X_op
= O_constant
;
9330 if (! target_big_endian
)
9332 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9333 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9337 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9338 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9340 if (offset_expr
.X_add_number
== 0)
9341 offset_expr
.X_op
= O_absent
;
9343 else if (sizeof (imm_expr
.X_add_number
) > 4)
9345 imm_expr
.X_op
= O_constant
;
9346 if (! target_big_endian
)
9347 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9349 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9353 imm_expr
.X_op
= O_big
;
9354 imm_expr
.X_add_number
= 4;
9355 if (! target_big_endian
)
9357 generic_bignum
[0] = bfd_getl16 (temp
);
9358 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9359 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9360 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9364 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9365 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9366 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9367 generic_bignum
[3] = bfd_getb16 (temp
);
9373 const char *newname
;
9376 /* Switch to the right section. */
9378 subseg
= now_subseg
;
9381 default: /* unused default case avoids warnings. */
9383 newname
= RDATA_SECTION_NAME
;
9384 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
9385 || mips_pic
== EMBEDDED_PIC
)
9389 if (mips_pic
== EMBEDDED_PIC
)
9392 newname
= RDATA_SECTION_NAME
;
9395 assert (!USE_GLOBAL_POINTER_OPT
9396 || g_switch_value
>= 4);
9400 new_seg
= subseg_new (newname
, (subsegT
) 0);
9401 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9402 bfd_set_section_flags (stdoutput
, new_seg
,
9407 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9408 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9409 && strcmp (TARGET_OS
, "elf") != 0)
9410 record_alignment (new_seg
, 4);
9412 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9414 as_bad (_("Can't use floating point insn in this section"));
9416 /* Set the argument to the current address in the
9418 offset_expr
.X_op
= O_symbol
;
9419 offset_expr
.X_add_symbol
=
9420 symbol_new ("L0\001", now_seg
,
9421 (valueT
) frag_now_fix (), frag_now
);
9422 offset_expr
.X_add_number
= 0;
9424 /* Put the floating point number into the section. */
9425 p
= frag_more ((int) length
);
9426 memcpy (p
, temp
, length
);
9428 /* Switch back to the original section. */
9429 subseg_set (seg
, subseg
);
9434 case 'i': /* 16 bit unsigned immediate */
9435 case 'j': /* 16 bit signed immediate */
9436 *imm_reloc
= BFD_RELOC_LO16
;
9437 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9440 offsetT minval
, maxval
;
9442 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9443 && strcmp (insn
->name
, insn
[1].name
) == 0);
9445 /* If the expression was written as an unsigned number,
9446 only treat it as signed if there are no more
9450 && sizeof (imm_expr
.X_add_number
) <= 4
9451 && imm_expr
.X_op
== O_constant
9452 && imm_expr
.X_add_number
< 0
9453 && imm_expr
.X_unsigned
9457 /* For compatibility with older assemblers, we accept
9458 0x8000-0xffff as signed 16-bit numbers when only
9459 signed numbers are allowed. */
9461 minval
= 0, maxval
= 0xffff;
9463 minval
= -0x8000, maxval
= 0x7fff;
9465 minval
= -0x8000, maxval
= 0xffff;
9467 if (imm_expr
.X_op
!= O_constant
9468 || imm_expr
.X_add_number
< minval
9469 || imm_expr
.X_add_number
> maxval
)
9473 if (imm_expr
.X_op
== O_constant
9474 || imm_expr
.X_op
== O_big
)
9475 as_bad (_("expression out of range"));
9481 case 'o': /* 16 bit offset */
9482 /* Check whether there is only a single bracketed expression
9483 left. If so, it must be the base register and the
9484 constant must be zero. */
9485 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9487 offset_expr
.X_op
= O_constant
;
9488 offset_expr
.X_add_number
= 0;
9492 /* If this value won't fit into a 16 bit offset, then go
9493 find a macro that will generate the 32 bit offset
9495 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9496 && (offset_expr
.X_op
!= O_constant
9497 || offset_expr
.X_add_number
>= 0x8000
9498 || offset_expr
.X_add_number
< -0x8000))
9504 case 'p': /* pc relative offset */
9505 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9506 my_getExpression (&offset_expr
, s
);
9510 case 'u': /* upper 16 bits */
9511 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9512 && imm_expr
.X_op
== O_constant
9513 && (imm_expr
.X_add_number
< 0
9514 || imm_expr
.X_add_number
>= 0x10000))
9515 as_bad (_("lui expression not in range 0..65535"));
9519 case 'a': /* 26 bit address */
9520 my_getExpression (&offset_expr
, s
);
9522 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9525 case 'N': /* 3 bit branch condition code */
9526 case 'M': /* 3 bit compare condition code */
9527 if (strncmp (s
, "$fcc", 4) != 0)
9537 while (ISDIGIT (*s
));
9539 as_bad (_("invalid condition code register $fcc%d"), regno
);
9541 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9543 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9547 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9558 while (ISDIGIT (*s
));
9561 c
= 8; /* Invalid sel value. */
9564 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9565 ip
->insn_opcode
|= c
;
9569 /* Must be at least one digit. */
9570 my_getExpression (&imm_expr
, s
);
9571 check_absolute_expr (ip
, &imm_expr
);
9573 if ((unsigned long) imm_expr
.X_add_number
9574 > (unsigned long) OP_MASK_VECBYTE
)
9576 as_bad (_("bad byte vector index (%ld)"),
9577 (long) imm_expr
.X_add_number
);
9578 imm_expr
.X_add_number
= 0;
9581 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9582 imm_expr
.X_op
= O_absent
;
9587 my_getExpression (&imm_expr
, s
);
9588 check_absolute_expr (ip
, &imm_expr
);
9590 if ((unsigned long) imm_expr
.X_add_number
9591 > (unsigned long) OP_MASK_VECALIGN
)
9593 as_bad (_("bad byte vector index (%ld)"),
9594 (long) imm_expr
.X_add_number
);
9595 imm_expr
.X_add_number
= 0;
9598 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9599 imm_expr
.X_op
= O_absent
;
9604 as_bad (_("bad char = '%c'\n"), *args
);
9609 /* Args don't match. */
9610 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9611 !strcmp (insn
->name
, insn
[1].name
))
9615 insn_error
= _("illegal operands");
9620 insn_error
= _("illegal operands");
9625 /* This routine assembles an instruction into its binary format when
9626 assembling for the mips16. As a side effect, it sets one of the
9627 global variables imm_reloc or offset_reloc to the type of
9628 relocation to do if one of the operands is an address expression.
9629 It also sets mips16_small and mips16_ext if the user explicitly
9630 requested a small or extended instruction. */
9635 struct mips_cl_insn
*ip
;
9639 struct mips_opcode
*insn
;
9642 unsigned int lastregno
= 0;
9647 mips16_small
= FALSE
;
9650 for (s
= str
; ISLOWER (*s
); ++s
)
9662 if (s
[1] == 't' && s
[2] == ' ')
9665 mips16_small
= TRUE
;
9669 else if (s
[1] == 'e' && s
[2] == ' ')
9678 insn_error
= _("unknown opcode");
9682 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9683 mips16_small
= TRUE
;
9685 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9687 insn_error
= _("unrecognized opcode");
9694 assert (strcmp (insn
->name
, str
) == 0);
9697 ip
->insn_opcode
= insn
->match
;
9698 ip
->use_extend
= FALSE
;
9699 imm_expr
.X_op
= O_absent
;
9700 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9701 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9702 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9703 offset_expr
.X_op
= O_absent
;
9704 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9705 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9706 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9707 for (args
= insn
->args
; 1; ++args
)
9714 /* In this switch statement we call break if we did not find
9715 a match, continue if we did find a match, or return if we
9724 /* Stuff the immediate value in now, if we can. */
9725 if (imm_expr
.X_op
== O_constant
9726 && *imm_reloc
> BFD_RELOC_UNUSED
9727 && insn
->pinfo
!= INSN_MACRO
)
9729 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9730 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9731 mips16_ext
, &ip
->insn_opcode
,
9732 &ip
->use_extend
, &ip
->extend
);
9733 imm_expr
.X_op
= O_absent
;
9734 *imm_reloc
= BFD_RELOC_UNUSED
;
9748 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9751 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9767 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9769 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9796 while (ISDIGIT (*s
));
9799 as_bad (_("invalid register number (%d)"), regno
);
9805 if (s
[1] == 'r' && s
[2] == 'a')
9810 else if (s
[1] == 'f' && s
[2] == 'p')
9815 else if (s
[1] == 's' && s
[2] == 'p')
9820 else if (s
[1] == 'g' && s
[2] == 'p')
9825 else if (s
[1] == 'a' && s
[2] == 't')
9830 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9835 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9840 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9853 if (c
== 'v' || c
== 'w')
9855 regno
= mips16_to_32_reg_map
[lastregno
];
9869 regno
= mips32_to_16_reg_map
[regno
];
9874 regno
= ILLEGAL_REG
;
9879 regno
= ILLEGAL_REG
;
9884 regno
= ILLEGAL_REG
;
9889 if (regno
== AT
&& ! mips_opts
.noat
)
9890 as_warn (_("used $at without \".set noat\""));
9897 if (regno
== ILLEGAL_REG
)
9904 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9908 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9911 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9914 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9920 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9923 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9924 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9934 if (strncmp (s
, "$pc", 3) == 0)
9958 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9960 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9961 and generate the appropriate reloc. If the text
9962 inside %gprel is not a symbol name with an
9963 optional offset, then we generate a normal reloc
9964 and will probably fail later. */
9965 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9966 if (imm_expr
.X_op
== O_symbol
)
9969 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9971 ip
->use_extend
= TRUE
;
9978 /* Just pick up a normal expression. */
9979 my_getExpression (&imm_expr
, s
);
9982 if (imm_expr
.X_op
== O_register
)
9984 /* What we thought was an expression turned out to
9987 if (s
[0] == '(' && args
[1] == '(')
9989 /* It looks like the expression was omitted
9990 before a register indirection, which means
9991 that the expression is implicitly zero. We
9992 still set up imm_expr, so that we handle
9993 explicit extensions correctly. */
9994 imm_expr
.X_op
= O_constant
;
9995 imm_expr
.X_add_number
= 0;
9996 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10003 /* We need to relax this instruction. */
10004 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10013 /* We use offset_reloc rather than imm_reloc for the PC
10014 relative operands. This lets macros with both
10015 immediate and address operands work correctly. */
10016 my_getExpression (&offset_expr
, s
);
10018 if (offset_expr
.X_op
== O_register
)
10021 /* We need to relax this instruction. */
10022 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10026 case '6': /* break code */
10027 my_getExpression (&imm_expr
, s
);
10028 check_absolute_expr (ip
, &imm_expr
);
10029 if ((unsigned long) imm_expr
.X_add_number
> 63)
10031 as_warn (_("Invalid value for `%s' (%lu)"),
10033 (unsigned long) imm_expr
.X_add_number
);
10034 imm_expr
.X_add_number
&= 0x3f;
10036 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
10037 imm_expr
.X_op
= O_absent
;
10041 case 'a': /* 26 bit address */
10042 my_getExpression (&offset_expr
, s
);
10044 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10045 ip
->insn_opcode
<<= 16;
10048 case 'l': /* register list for entry macro */
10049 case 'L': /* register list for exit macro */
10059 int freg
, reg1
, reg2
;
10061 while (*s
== ' ' || *s
== ',')
10065 as_bad (_("can't parse register list"));
10077 while (ISDIGIT (*s
))
10099 as_bad (_("invalid register list"));
10104 while (ISDIGIT (*s
))
10111 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10113 mask
&= ~ (7 << 3);
10116 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10118 mask
&= ~ (7 << 3);
10121 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10122 mask
|= (reg2
- 3) << 3;
10123 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10124 mask
|= (reg2
- 15) << 1;
10125 else if (reg1
== RA
&& reg2
== RA
)
10129 as_bad (_("invalid register list"));
10133 /* The mask is filled in in the opcode table for the
10134 benefit of the disassembler. We remove it before
10135 applying the actual mask. */
10136 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10137 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10141 case 'e': /* extend code */
10142 my_getExpression (&imm_expr
, s
);
10143 check_absolute_expr (ip
, &imm_expr
);
10144 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10146 as_warn (_("Invalid value for `%s' (%lu)"),
10148 (unsigned long) imm_expr
.X_add_number
);
10149 imm_expr
.X_add_number
&= 0x7ff;
10151 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10152 imm_expr
.X_op
= O_absent
;
10162 /* Args don't match. */
10163 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10164 strcmp (insn
->name
, insn
[1].name
) == 0)
10171 insn_error
= _("illegal operands");
10177 /* This structure holds information we know about a mips16 immediate
10180 struct mips16_immed_operand
10182 /* The type code used in the argument string in the opcode table. */
10184 /* The number of bits in the short form of the opcode. */
10186 /* The number of bits in the extended form of the opcode. */
10188 /* The amount by which the short form is shifted when it is used;
10189 for example, the sw instruction has a shift count of 2. */
10191 /* The amount by which the short form is shifted when it is stored
10192 into the instruction code. */
10194 /* Non-zero if the short form is unsigned. */
10196 /* Non-zero if the extended form is unsigned. */
10198 /* Non-zero if the value is PC relative. */
10202 /* The mips16 immediate operand types. */
10204 static const struct mips16_immed_operand mips16_immed_operands
[] =
10206 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10207 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10208 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10209 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10210 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10211 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10212 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10213 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10214 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10215 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10216 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10217 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10218 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10219 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10220 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10221 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10222 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10223 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10224 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10225 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10226 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10229 #define MIPS16_NUM_IMMED \
10230 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10232 /* Handle a mips16 instruction with an immediate value. This or's the
10233 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10234 whether an extended value is needed; if one is needed, it sets
10235 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10236 If SMALL is true, an unextended opcode was explicitly requested.
10237 If EXT is true, an extended opcode was explicitly requested. If
10238 WARN is true, warn if EXT does not match reality. */
10241 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
10250 unsigned long *insn
;
10251 bfd_boolean
*use_extend
;
10252 unsigned short *extend
;
10254 register const struct mips16_immed_operand
*op
;
10255 int mintiny
, maxtiny
;
10256 bfd_boolean needext
;
10258 op
= mips16_immed_operands
;
10259 while (op
->type
!= type
)
10262 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10267 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10270 maxtiny
= 1 << op
->nbits
;
10275 maxtiny
= (1 << op
->nbits
) - 1;
10280 mintiny
= - (1 << (op
->nbits
- 1));
10281 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10284 /* Branch offsets have an implicit 0 in the lowest bit. */
10285 if (type
== 'p' || type
== 'q')
10288 if ((val
& ((1 << op
->shift
) - 1)) != 0
10289 || val
< (mintiny
<< op
->shift
)
10290 || val
> (maxtiny
<< op
->shift
))
10295 if (warn
&& ext
&& ! needext
)
10296 as_warn_where (file
, line
,
10297 _("extended operand requested but not required"));
10298 if (small
&& needext
)
10299 as_bad_where (file
, line
, _("invalid unextended operand value"));
10301 if (small
|| (! ext
&& ! needext
))
10305 *use_extend
= FALSE
;
10306 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10307 insnval
<<= op
->op_shift
;
10312 long minext
, maxext
;
10318 maxext
= (1 << op
->extbits
) - 1;
10322 minext
= - (1 << (op
->extbits
- 1));
10323 maxext
= (1 << (op
->extbits
- 1)) - 1;
10325 if (val
< minext
|| val
> maxext
)
10326 as_bad_where (file
, line
,
10327 _("operand value out of range for instruction"));
10329 *use_extend
= TRUE
;
10330 if (op
->extbits
== 16)
10332 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10335 else if (op
->extbits
== 15)
10337 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10342 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10346 *extend
= (unsigned short) extval
;
10351 static const struct percent_op_match
10354 bfd_reloc_code_real_type reloc
;
10357 {"%lo", BFD_RELOC_LO16
},
10359 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10360 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10361 {"%call16", BFD_RELOC_MIPS_CALL16
},
10362 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10363 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10364 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10365 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10366 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10367 {"%got", BFD_RELOC_MIPS_GOT16
},
10368 {"%gp_rel", BFD_RELOC_GPREL16
},
10369 {"%half", BFD_RELOC_16
},
10370 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10371 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10372 {"%neg", BFD_RELOC_MIPS_SUB
},
10374 {"%hi", BFD_RELOC_HI16_S
}
10378 /* Return true if *STR points to a relocation operator. When returning true,
10379 move *STR over the operator and store its relocation code in *RELOC.
10380 Leave both *STR and *RELOC alone when returning false. */
10383 parse_relocation (str
, reloc
)
10385 bfd_reloc_code_real_type
*reloc
;
10389 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
10390 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10392 *str
+= strlen (percent_op
[i
].str
);
10393 *reloc
= percent_op
[i
].reloc
;
10395 /* Check whether the output BFD supports this relocation.
10396 If not, issue an error and fall back on something safe. */
10397 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10399 as_bad ("relocation %s isn't supported by the current ABI",
10400 percent_op
[i
].str
);
10401 *reloc
= BFD_RELOC_LO16
;
10409 /* Parse string STR as a 16-bit relocatable operand. Store the
10410 expression in *EP and the relocations in the array starting
10411 at RELOC. Return the number of relocation operators used.
10413 On exit, EXPR_END points to the first character after the expression.
10414 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10417 my_getSmallExpression (ep
, reloc
, str
)
10419 bfd_reloc_code_real_type
*reloc
;
10422 bfd_reloc_code_real_type reversed_reloc
[3];
10423 size_t reloc_index
, i
;
10424 int crux_depth
, str_depth
;
10427 /* Search for the start of the main expression, recoding relocations
10428 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10429 of the main expression and with CRUX_DEPTH containing the number
10430 of open brackets at that point. */
10437 crux_depth
= str_depth
;
10439 /* Skip over whitespace and brackets, keeping count of the number
10441 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10446 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10447 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10449 my_getExpression (ep
, crux
);
10452 /* Match every open bracket. */
10453 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10457 if (crux_depth
> 0)
10458 as_bad ("unclosed '('");
10462 if (reloc_index
== 0)
10463 reloc
[0] = BFD_RELOC_LO16
;
10466 prev_reloc_op_frag
= frag_now
;
10467 for (i
= 0; i
< reloc_index
; i
++)
10468 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10471 return reloc_index
;
10475 my_getExpression (ep
, str
)
10482 save_in
= input_line_pointer
;
10483 input_line_pointer
= str
;
10485 expr_end
= input_line_pointer
;
10486 input_line_pointer
= save_in
;
10488 /* If we are in mips16 mode, and this is an expression based on `.',
10489 then we bump the value of the symbol by 1 since that is how other
10490 text symbols are handled. We don't bother to handle complex
10491 expressions, just `.' plus or minus a constant. */
10492 if (mips_opts
.mips16
10493 && ep
->X_op
== O_symbol
10494 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10495 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10496 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10497 && symbol_constant_p (ep
->X_add_symbol
)
10498 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10499 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10502 /* Turn a string in input_line_pointer into a floating point constant
10503 of type TYPE, and store the appropriate bytes in *LITP. The number
10504 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10505 returned, or NULL on OK. */
10508 md_atof (type
, litP
, sizeP
)
10514 LITTLENUM_TYPE words
[4];
10530 return _("bad call to md_atof");
10533 t
= atof_ieee (input_line_pointer
, type
, words
);
10535 input_line_pointer
= t
;
10539 if (! target_big_endian
)
10541 for (i
= prec
- 1; i
>= 0; i
--)
10543 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10549 for (i
= 0; i
< prec
; i
++)
10551 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10560 md_number_to_chars (buf
, val
, n
)
10565 if (target_big_endian
)
10566 number_to_chars_bigendian (buf
, val
, n
);
10568 number_to_chars_littleendian (buf
, val
, n
);
10572 static int support_64bit_objects(void)
10574 const char **list
, **l
;
10577 list
= bfd_target_list ();
10578 for (l
= list
; *l
!= NULL
; l
++)
10580 /* This is traditional mips */
10581 if (strcmp (*l
, "elf64-tradbigmips") == 0
10582 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10584 if (strcmp (*l
, "elf64-bigmips") == 0
10585 || strcmp (*l
, "elf64-littlemips") == 0)
10588 yes
= (*l
!= NULL
);
10592 #endif /* OBJ_ELF */
10594 const char *md_shortopts
= "nO::g::G:";
10596 struct option md_longopts
[] =
10598 /* Options which specify architecture. */
10599 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10600 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10601 {"march", required_argument
, NULL
, OPTION_MARCH
},
10602 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10603 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10604 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10605 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10606 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10607 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10608 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10609 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10610 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10611 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10612 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10613 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10614 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10615 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10616 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10617 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10618 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10619 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10620 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10622 /* Options which specify Application Specific Extensions (ASEs). */
10623 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10624 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10625 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10626 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10627 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10628 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10629 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10630 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10631 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10632 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10633 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10634 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10635 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10637 /* Old-style architecture options. Don't add more of these. */
10638 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10639 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10640 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10641 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10642 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10643 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10644 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10645 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10646 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10647 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10648 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10649 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10650 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10651 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10653 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10654 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10656 /* Options which enable bug fixes. */
10657 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10658 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10659 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10660 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10661 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10662 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10663 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10664 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10665 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10666 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10668 /* Miscellaneous options. */
10669 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10670 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10671 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10672 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10673 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10674 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10675 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10676 {"break", no_argument
, NULL
, OPTION_BREAK
},
10677 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10678 #define OPTION_EB (OPTION_MISC_BASE + 3)
10679 {"EB", no_argument
, NULL
, OPTION_EB
},
10680 #define OPTION_EL (OPTION_MISC_BASE + 4)
10681 {"EL", no_argument
, NULL
, OPTION_EL
},
10682 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10683 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10684 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10685 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10686 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10688 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10689 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10690 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10691 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10692 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10693 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10694 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10695 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10696 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10697 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10699 /* ELF-specific options. */
10701 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10702 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10703 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10704 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10705 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10706 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10707 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10708 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10709 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10710 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10711 #define OPTION_32 (OPTION_ELF_BASE + 4)
10712 {"32", no_argument
, NULL
, OPTION_32
},
10713 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10714 {"n32", no_argument
, NULL
, OPTION_N32
},
10715 #define OPTION_64 (OPTION_ELF_BASE + 6)
10716 {"64", no_argument
, NULL
, OPTION_64
},
10717 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10718 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10719 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10720 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10721 #endif /* OBJ_ELF */
10723 {NULL
, no_argument
, NULL
, 0}
10725 size_t md_longopts_size
= sizeof (md_longopts
);
10727 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10728 NEW_VALUE. Warn if another value was already specified. Note:
10729 we have to defer parsing the -march and -mtune arguments in order
10730 to handle 'from-abi' correctly, since the ABI might be specified
10731 in a later argument. */
10734 mips_set_option_string (string_ptr
, new_value
)
10735 const char **string_ptr
, *new_value
;
10737 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10738 as_warn (_("A different %s was already specified, is now %s"),
10739 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10742 *string_ptr
= new_value
;
10746 md_parse_option (c
, arg
)
10752 case OPTION_CONSTRUCT_FLOATS
:
10753 mips_disable_float_construction
= 0;
10756 case OPTION_NO_CONSTRUCT_FLOATS
:
10757 mips_disable_float_construction
= 1;
10769 target_big_endian
= 1;
10773 target_big_endian
= 0;
10781 if (arg
&& arg
[1] == '0')
10791 mips_debug
= atoi (arg
);
10792 /* When the MIPS assembler sees -g or -g2, it does not do
10793 optimizations which limit full symbolic debugging. We take
10794 that to be equivalent to -O0. */
10795 if (mips_debug
== 2)
10800 file_mips_isa
= ISA_MIPS1
;
10804 file_mips_isa
= ISA_MIPS2
;
10808 file_mips_isa
= ISA_MIPS3
;
10812 file_mips_isa
= ISA_MIPS4
;
10816 file_mips_isa
= ISA_MIPS5
;
10819 case OPTION_MIPS32
:
10820 file_mips_isa
= ISA_MIPS32
;
10823 case OPTION_MIPS32R2
:
10824 file_mips_isa
= ISA_MIPS32R2
;
10827 case OPTION_MIPS64
:
10828 file_mips_isa
= ISA_MIPS64
;
10832 mips_set_option_string (&mips_tune_string
, arg
);
10836 mips_set_option_string (&mips_arch_string
, arg
);
10840 mips_set_option_string (&mips_arch_string
, "4650");
10841 mips_set_option_string (&mips_tune_string
, "4650");
10844 case OPTION_NO_M4650
:
10848 mips_set_option_string (&mips_arch_string
, "4010");
10849 mips_set_option_string (&mips_tune_string
, "4010");
10852 case OPTION_NO_M4010
:
10856 mips_set_option_string (&mips_arch_string
, "4100");
10857 mips_set_option_string (&mips_tune_string
, "4100");
10860 case OPTION_NO_M4100
:
10864 mips_set_option_string (&mips_arch_string
, "3900");
10865 mips_set_option_string (&mips_tune_string
, "3900");
10868 case OPTION_NO_M3900
:
10872 mips_opts
.ase_mdmx
= 1;
10875 case OPTION_NO_MDMX
:
10876 mips_opts
.ase_mdmx
= 0;
10879 case OPTION_MIPS16
:
10880 mips_opts
.mips16
= 1;
10881 mips_no_prev_insn (FALSE
);
10884 case OPTION_NO_MIPS16
:
10885 mips_opts
.mips16
= 0;
10886 mips_no_prev_insn (FALSE
);
10889 case OPTION_MIPS3D
:
10890 mips_opts
.ase_mips3d
= 1;
10893 case OPTION_NO_MIPS3D
:
10894 mips_opts
.ase_mips3d
= 0;
10897 case OPTION_MEMBEDDED_PIC
:
10898 mips_pic
= EMBEDDED_PIC
;
10899 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10901 as_bad (_("-G may not be used with embedded PIC code"));
10904 g_switch_value
= 0x7fffffff;
10907 case OPTION_FIX_VR4122
:
10908 mips_fix_4122_bugs
= 1;
10911 case OPTION_NO_FIX_VR4122
:
10912 mips_fix_4122_bugs
= 0;
10915 case OPTION_RELAX_BRANCH
:
10916 mips_relax_branch
= 1;
10919 case OPTION_NO_RELAX_BRANCH
:
10920 mips_relax_branch
= 0;
10924 /* When generating ELF code, we permit -KPIC and -call_shared to
10925 select SVR4_PIC, and -non_shared to select no PIC. This is
10926 intended to be compatible with Irix 5. */
10927 case OPTION_CALL_SHARED
:
10928 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10930 as_bad (_("-call_shared is supported only for ELF format"));
10933 mips_pic
= SVR4_PIC
;
10934 mips_abicalls
= TRUE
;
10935 if (g_switch_seen
&& g_switch_value
!= 0)
10937 as_bad (_("-G may not be used with SVR4 PIC code"));
10940 g_switch_value
= 0;
10943 case OPTION_NON_SHARED
:
10944 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10946 as_bad (_("-non_shared is supported only for ELF format"));
10950 mips_abicalls
= FALSE
;
10953 /* The -xgot option tells the assembler to use 32 offsets when
10954 accessing the got in SVR4_PIC mode. It is for Irix
10959 #endif /* OBJ_ELF */
10962 if (! USE_GLOBAL_POINTER_OPT
)
10964 as_bad (_("-G is not supported for this configuration"));
10967 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10969 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10973 g_switch_value
= atoi (arg
);
10978 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10981 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10983 as_bad (_("-32 is supported for ELF format only"));
10986 mips_abi
= O32_ABI
;
10990 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10992 as_bad (_("-n32 is supported for ELF format only"));
10995 mips_abi
= N32_ABI
;
10999 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11001 as_bad (_("-64 is supported for ELF format only"));
11004 mips_abi
= N64_ABI
;
11005 if (! support_64bit_objects())
11006 as_fatal (_("No compiled in support for 64 bit object file format"));
11008 #endif /* OBJ_ELF */
11011 file_mips_gp32
= 1;
11015 file_mips_gp32
= 0;
11019 file_mips_fp32
= 1;
11023 file_mips_fp32
= 0;
11028 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11030 as_bad (_("-mabi is supported for ELF format only"));
11033 if (strcmp (arg
, "32") == 0)
11034 mips_abi
= O32_ABI
;
11035 else if (strcmp (arg
, "o64") == 0)
11036 mips_abi
= O64_ABI
;
11037 else if (strcmp (arg
, "n32") == 0)
11038 mips_abi
= N32_ABI
;
11039 else if (strcmp (arg
, "64") == 0)
11041 mips_abi
= N64_ABI
;
11042 if (! support_64bit_objects())
11043 as_fatal (_("No compiled in support for 64 bit object file "
11046 else if (strcmp (arg
, "eabi") == 0)
11047 mips_abi
= EABI_ABI
;
11050 as_fatal (_("invalid abi -mabi=%s"), arg
);
11054 #endif /* OBJ_ELF */
11056 case OPTION_M7000_HILO_FIX
:
11057 mips_7000_hilo_fix
= TRUE
;
11060 case OPTION_MNO_7000_HILO_FIX
:
11061 mips_7000_hilo_fix
= FALSE
;
11065 case OPTION_MDEBUG
:
11066 mips_flag_mdebug
= TRUE
;
11069 case OPTION_NO_MDEBUG
:
11070 mips_flag_mdebug
= FALSE
;
11072 #endif /* OBJ_ELF */
11081 /* Set up globals to generate code for the ISA or processor
11082 described by INFO. */
11085 mips_set_architecture (info
)
11086 const struct mips_cpu_info
*info
;
11090 file_mips_arch
= info
->cpu
;
11091 mips_opts
.arch
= info
->cpu
;
11092 mips_opts
.isa
= info
->isa
;
11097 /* Likewise for tuning. */
11100 mips_set_tune (info
)
11101 const struct mips_cpu_info
*info
;
11104 mips_tune
= info
->cpu
;
11109 mips_after_parse_args ()
11111 const struct mips_cpu_info
*arch_info
= 0;
11112 const struct mips_cpu_info
*tune_info
= 0;
11114 /* GP relative stuff not working for PE */
11115 if (strncmp (TARGET_OS
, "pe", 2) == 0
11116 && g_switch_value
!= 0)
11119 as_bad (_("-G not supported in this configuration."));
11120 g_switch_value
= 0;
11123 if (mips_abi
== NO_ABI
)
11124 mips_abi
= MIPS_DEFAULT_ABI
;
11126 /* The following code determines the architecture and register size.
11127 Similar code was added to GCC 3.3 (see override_options() in
11128 config/mips/mips.c). The GAS and GCC code should be kept in sync
11129 as much as possible. */
11131 if (mips_arch_string
!= 0)
11132 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11134 if (file_mips_isa
!= ISA_UNKNOWN
)
11136 /* Handle -mipsN. At this point, file_mips_isa contains the
11137 ISA level specified by -mipsN, while arch_info->isa contains
11138 the -march selection (if any). */
11139 if (arch_info
!= 0)
11141 /* -march takes precedence over -mipsN, since it is more descriptive.
11142 There's no harm in specifying both as long as the ISA levels
11144 if (file_mips_isa
!= arch_info
->isa
)
11145 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11146 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11147 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11150 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11153 if (arch_info
== 0)
11154 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11156 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11157 as_bad ("-march=%s is not compatible with the selected ABI",
11160 mips_set_architecture (arch_info
);
11162 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11163 if (mips_tune_string
!= 0)
11164 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11166 if (tune_info
== 0)
11167 mips_set_tune (arch_info
);
11169 mips_set_tune (tune_info
);
11171 if (file_mips_gp32
>= 0)
11173 /* The user specified the size of the integer registers. Make sure
11174 it agrees with the ABI and ISA. */
11175 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11176 as_bad (_("-mgp64 used with a 32-bit processor"));
11177 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11178 as_bad (_("-mgp32 used with a 64-bit ABI"));
11179 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11180 as_bad (_("-mgp64 used with a 32-bit ABI"));
11184 /* Infer the integer register size from the ABI and processor.
11185 Restrict ourselves to 32-bit registers if that's all the
11186 processor has, or if the ABI cannot handle 64-bit registers. */
11187 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11188 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11191 /* ??? GAS treats single-float processors as though they had 64-bit
11192 float registers (although it complains when double-precision
11193 instructions are used). As things stand, saying they have 32-bit
11194 registers would lead to spurious "register must be even" messages.
11195 So here we assume float registers are always the same size as
11196 integer ones, unless the user says otherwise. */
11197 if (file_mips_fp32
< 0)
11198 file_mips_fp32
= file_mips_gp32
;
11200 /* End of GCC-shared inference code. */
11202 /* ??? When do we want this flag to be set? Who uses it? */
11203 if (file_mips_gp32
== 1
11204 && mips_abi
== NO_ABI
11205 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11206 mips_32bitmode
= 1;
11208 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11209 as_bad (_("trap exception not supported at ISA 1"));
11211 /* If the selected architecture includes support for ASEs, enable
11212 generation of code for them. */
11213 if (mips_opts
.mips16
== -1)
11214 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11215 if (mips_opts
.ase_mips3d
== -1)
11216 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
11217 if (mips_opts
.ase_mdmx
== -1)
11218 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
11220 file_mips_isa
= mips_opts
.isa
;
11221 file_ase_mips16
= mips_opts
.mips16
;
11222 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11223 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11224 mips_opts
.gp32
= file_mips_gp32
;
11225 mips_opts
.fp32
= file_mips_fp32
;
11227 if (mips_flag_mdebug
< 0)
11229 #ifdef OBJ_MAYBE_ECOFF
11230 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11231 mips_flag_mdebug
= 1;
11233 #endif /* OBJ_MAYBE_ECOFF */
11234 mips_flag_mdebug
= 0;
11239 mips_init_after_args ()
11241 /* initialize opcodes */
11242 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11243 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11247 md_pcrel_from (fixP
)
11250 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11251 switch (fixP
->fx_r_type
)
11253 case BFD_RELOC_16_PCREL_S2
:
11254 case BFD_RELOC_MIPS_JMP
:
11255 /* Return the address of the delay slot. */
11262 /* This is called before the symbol table is processed. In order to
11263 work with gcc when using mips-tfile, we must keep all local labels.
11264 However, in other cases, we want to discard them. If we were
11265 called with -g, but we didn't see any debugging information, it may
11266 mean that gcc is smuggling debugging information through to
11267 mips-tfile, in which case we must generate all local labels. */
11270 mips_frob_file_before_adjust ()
11272 #ifndef NO_ECOFF_DEBUGGING
11273 if (ECOFF_DEBUGGING
11275 && ! ecoff_debugging_seen
)
11276 flag_keep_locals
= 1;
11280 /* Sort any unmatched HI16_S relocs so that they immediately precede
11281 the corresponding LO reloc. This is called before md_apply_fix3 and
11282 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11283 explicit use of the %hi modifier. */
11288 struct mips_hi_fixup
*l
;
11290 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11292 segment_info_type
*seginfo
;
11295 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11297 /* If a GOT16 relocation turns out to be against a global symbol,
11298 there isn't supposed to be a matching LO. */
11299 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11300 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11303 /* Check quickly whether the next fixup happens to be a matching %lo. */
11304 if (fixup_has_matching_lo_p (l
->fixp
))
11307 /* Look through the fixups for this segment for a matching %lo.
11308 When we find one, move the %hi just in front of it. We do
11309 this in two passes. In the first pass, we try to find a
11310 unique %lo. In the second pass, we permit multiple %hi
11311 relocs for a single %lo (this is a GNU extension). */
11312 seginfo
= seg_info (l
->seg
);
11313 for (pass
= 0; pass
< 2; pass
++)
11318 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
11320 /* Check whether this is a %lo fixup which matches l->fixp. */
11321 if (f
->fx_r_type
== BFD_RELOC_LO16
11322 && f
->fx_addsy
== l
->fixp
->fx_addsy
11323 && f
->fx_offset
== l
->fixp
->fx_offset
11326 || !reloc_needs_lo_p (prev
->fx_r_type
)
11327 || !fixup_has_matching_lo_p (prev
)))
11331 /* Move l->fixp before f. */
11332 for (pf
= &seginfo
->fix_root
;
11334 pf
= &(*pf
)->fx_next
)
11335 assert (*pf
!= NULL
);
11337 *pf
= l
->fixp
->fx_next
;
11339 l
->fixp
->fx_next
= f
;
11341 seginfo
->fix_root
= l
->fixp
;
11343 prev
->fx_next
= l
->fixp
;
11354 #if 0 /* GCC code motion plus incomplete dead code elimination
11355 can leave a %hi without a %lo. */
11357 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
11358 _("Unmatched %%hi reloc"));
11364 /* When generating embedded PIC code we need to use a special
11365 relocation to represent the difference of two symbols in the .text
11366 section (switch tables use a difference of this sort). See
11367 include/coff/mips.h for details. This macro checks whether this
11368 fixup requires the special reloc. */
11369 #define SWITCH_TABLE(fixp) \
11370 ((fixp)->fx_r_type == BFD_RELOC_32 \
11371 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11372 && (fixp)->fx_addsy != NULL \
11373 && (fixp)->fx_subsy != NULL \
11374 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11375 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11377 /* When generating embedded PIC code we must keep all PC relative
11378 relocations, in case the linker has to relax a call. We also need
11379 to keep relocations for switch table entries.
11381 We may have combined relocations without symbols in the N32/N64 ABI.
11382 We have to prevent gas from dropping them. */
11385 mips_force_relocation (fixp
)
11388 if (generic_force_reloc (fixp
))
11392 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11393 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11394 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11395 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11398 return (mips_pic
== EMBEDDED_PIC
11400 || SWITCH_TABLE (fixp
)
11401 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11402 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11405 /* This hook is called before a fix is simplified. We don't really
11406 decide whether to skip a fix here. Rather, we turn global symbols
11407 used as branch targets into local symbols, such that they undergo
11408 simplification. We can only do this if the symbol is defined and
11409 it is in the same section as the branch. If this doesn't hold, we
11410 emit a better error message than just saying the relocation is not
11411 valid for the selected object format.
11413 FIXP is the fix-up we're going to try to simplify, SEG is the
11414 segment in which the fix up occurs. The return value should be
11415 non-zero to indicate the fix-up is valid for further
11416 simplifications. */
11419 mips_validate_fix (fixP
, seg
)
11423 /* There's a lot of discussion on whether it should be possible to
11424 use R_MIPS_PC16 to represent branch relocations. The outcome
11425 seems to be that it can, but gas/bfd are very broken in creating
11426 RELA relocations for this, so for now we only accept branches to
11427 symbols in the same section. Anything else is of dubious value,
11428 since there's no guarantee that at link time the symbol would be
11429 in range. Even for branches to local symbols this is arguably
11430 wrong, since it we assume the symbol is not going to be
11431 overridden, which should be possible per ELF library semantics,
11432 but then, there isn't a dynamic relocation that could be used to
11433 this effect, and the target would likely be out of range as well.
11435 Unfortunately, it seems that there is too much code out there
11436 that relies on branches to symbols that are global to be resolved
11437 as if they were local, like the IRIX tools do, so we do it as
11438 well, but with a warning so that people are reminded to fix their
11439 code. If we ever get back to using R_MIPS_PC16 for branch
11440 targets, this entire block should go away (and probably the
11441 whole function). */
11443 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11444 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11445 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11446 && mips_pic
!= EMBEDDED_PIC
)
11447 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11450 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11453 _("Cannot branch to undefined symbol."));
11454 /* Avoid any further errors about this fixup. */
11457 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11460 _("Cannot branch to symbol in another section."));
11463 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11465 symbolS
*sym
= fixP
->fx_addsy
;
11467 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11468 _("Pretending global symbol used as branch target is local."));
11470 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11471 S_GET_SEGMENT (sym
),
11473 symbol_get_frag (sym
));
11474 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11475 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11476 assert (symbol_resolved_p (sym
));
11477 symbol_mark_resolved (fixP
->fx_addsy
);
11486 mips_need_elf_addend_fixup (fixP
)
11489 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11491 if (mips_pic
== EMBEDDED_PIC
11492 && S_IS_WEAK (fixP
->fx_addsy
))
11494 if (mips_pic
!= EMBEDDED_PIC
11495 && (S_IS_WEAK (fixP
->fx_addsy
)
11496 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11497 && !S_IS_COMMON (fixP
->fx_addsy
))
11499 if (((bfd_get_section_flags (stdoutput
,
11500 S_GET_SEGMENT (fixP
->fx_addsy
))
11501 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11502 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11504 sizeof (".gnu.linkonce") - 1))
11510 /* Apply a fixup to the object file. */
11513 md_apply_fix3 (fixP
, valP
, seg
)
11516 segT seg ATTRIBUTE_UNUSED
;
11520 static int previous_fx_r_type
= 0;
11521 reloc_howto_type
*howto
;
11523 /* We ignore generic BFD relocations we don't know about. */
11524 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11528 assert (fixP
->fx_size
== 4
11529 || fixP
->fx_r_type
== BFD_RELOC_16
11530 || fixP
->fx_r_type
== BFD_RELOC_64
11531 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11532 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11533 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11534 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11536 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11538 /* If we aren't adjusting this fixup to be against the section
11539 symbol, we need to adjust the value. */
11541 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11543 if (mips_need_elf_addend_fixup (fixP
)
11544 && howto
->partial_inplace
11545 && fixP
->fx_r_type
!= BFD_RELOC_GPREL16
11546 && fixP
->fx_r_type
!= BFD_RELOC_GPREL32
11547 && fixP
->fx_r_type
!= BFD_RELOC_MIPS16_GPREL
)
11549 /* In this case, the bfd_install_relocation routine will
11550 incorrectly add the symbol value back in. We just want
11551 the addend to appear in the object file.
11553 The condition above used to include
11554 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11556 However, howto can't be trusted here, because we
11557 might change the reloc type in tc_gen_reloc. We can
11558 check howto->partial_inplace because that conversion
11559 happens to preserve howto->partial_inplace; but it
11560 does not preserve howto->pcrel_offset. I've just
11561 eliminated the check, because all MIPS PC-relative
11562 relocations are marked howto->pcrel_offset.
11564 howto->pcrel_offset was originally added for
11565 R_MIPS_PC16, which is generated for code like
11574 *valP
-= S_GET_VALUE (fixP
->fx_addsy
);
11577 /* This code was generated using trial and error and so is
11578 fragile and not trustworthy. If you change it, you should
11579 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11580 they still pass. */
11581 if (fixP
->fx_pcrel
)
11583 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11585 /* BFD's REL handling, for MIPS, is _very_ weird.
11586 This gives the right results, but it can't possibly
11587 be the way things are supposed to work. */
11588 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11593 /* We are not done if this is a composite relocation to set up gp. */
11594 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11595 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11596 || (fixP
->fx_r_type
== BFD_RELOC_64
11597 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11598 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11599 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11600 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11601 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11603 previous_fx_r_type
= fixP
->fx_r_type
;
11605 switch (fixP
->fx_r_type
)
11607 case BFD_RELOC_MIPS_JMP
:
11608 case BFD_RELOC_MIPS_SHIFT5
:
11609 case BFD_RELOC_MIPS_SHIFT6
:
11610 case BFD_RELOC_MIPS_GOT_DISP
:
11611 case BFD_RELOC_MIPS_GOT_PAGE
:
11612 case BFD_RELOC_MIPS_GOT_OFST
:
11613 case BFD_RELOC_MIPS_SUB
:
11614 case BFD_RELOC_MIPS_INSERT_A
:
11615 case BFD_RELOC_MIPS_INSERT_B
:
11616 case BFD_RELOC_MIPS_DELETE
:
11617 case BFD_RELOC_MIPS_HIGHEST
:
11618 case BFD_RELOC_MIPS_HIGHER
:
11619 case BFD_RELOC_MIPS_SCN_DISP
:
11620 case BFD_RELOC_MIPS_REL16
:
11621 case BFD_RELOC_MIPS_RELGOT
:
11622 case BFD_RELOC_MIPS_JALR
:
11623 case BFD_RELOC_HI16
:
11624 case BFD_RELOC_HI16_S
:
11625 case BFD_RELOC_GPREL16
:
11626 case BFD_RELOC_MIPS_LITERAL
:
11627 case BFD_RELOC_MIPS_CALL16
:
11628 case BFD_RELOC_MIPS_GOT16
:
11629 case BFD_RELOC_GPREL32
:
11630 case BFD_RELOC_MIPS_GOT_HI16
:
11631 case BFD_RELOC_MIPS_GOT_LO16
:
11632 case BFD_RELOC_MIPS_CALL_HI16
:
11633 case BFD_RELOC_MIPS_CALL_LO16
:
11634 case BFD_RELOC_MIPS16_GPREL
:
11635 if (fixP
->fx_pcrel
)
11636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11637 _("Invalid PC relative reloc"));
11638 /* Nothing needed to do. The value comes from the reloc entry */
11641 case BFD_RELOC_MIPS16_JMP
:
11642 /* We currently always generate a reloc against a symbol, which
11643 means that we don't want an addend even if the symbol is
11648 case BFD_RELOC_PCREL_HI16_S
:
11649 /* The addend for this is tricky if it is internal, so we just
11650 do everything here rather than in bfd_install_relocation. */
11651 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11654 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11656 /* For an external symbol adjust by the address to make it
11657 pcrel_offset. We use the address of the RELLO reloc
11658 which follows this one. */
11659 *valP
+= (fixP
->fx_next
->fx_frag
->fr_address
11660 + fixP
->fx_next
->fx_where
);
11662 *valP
= ((*valP
+ 0x8000) >> 16) & 0xffff;
11663 if (target_big_endian
)
11665 md_number_to_chars ((char *) buf
, *valP
, 2);
11668 case BFD_RELOC_PCREL_LO16
:
11669 /* The addend for this is tricky if it is internal, so we just
11670 do everything here rather than in bfd_install_relocation. */
11671 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11674 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11675 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11676 if (target_big_endian
)
11678 md_number_to_chars ((char *) buf
, *valP
, 2);
11682 /* This is handled like BFD_RELOC_32, but we output a sign
11683 extended value if we are only 32 bits. */
11685 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11687 if (8 <= sizeof (valueT
))
11688 md_number_to_chars (buf
, *valP
, 8);
11693 if ((*valP
& 0x80000000) != 0)
11697 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11699 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11705 case BFD_RELOC_RVA
:
11707 /* If we are deleting this reloc entry, we must fill in the
11708 value now. This can happen if we have a .word which is not
11709 resolved when it appears but is later defined. We also need
11710 to fill in the value if this is an embedded PIC switch table
11713 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11714 md_number_to_chars (buf
, *valP
, 4);
11718 /* If we are deleting this reloc entry, we must fill in the
11720 assert (fixP
->fx_size
== 2);
11722 md_number_to_chars (buf
, *valP
, 2);
11725 case BFD_RELOC_LO16
:
11726 /* When handling an embedded PIC switch statement, we can wind
11727 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11730 if (*valP
+ 0x8000 > 0xffff)
11731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11732 _("relocation overflow"));
11733 if (target_big_endian
)
11735 md_number_to_chars ((char *) buf
, *valP
, 2);
11739 case BFD_RELOC_16_PCREL_S2
:
11740 if ((*valP
& 0x3) != 0)
11741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11742 _("Branch to odd address (%lx)"), (long) *valP
);
11745 * We need to save the bits in the instruction since fixup_segment()
11746 * might be deleting the relocation entry (i.e., a branch within
11747 * the current segment).
11749 if (! fixP
->fx_done
)
11752 /* update old instruction data */
11753 if (target_big_endian
)
11754 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11756 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11758 if (*valP
+ 0x20000 <= 0x3ffff)
11760 insn
|= (*valP
>> 2) & 0xffff;
11761 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11763 else if (mips_pic
== NO_PIC
11765 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11766 && (fixP
->fx_frag
->fr_address
11767 < text_section
->vma
+ text_section
->_raw_size
)
11768 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11769 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11770 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11772 /* The branch offset is too large. If this is an
11773 unconditional branch, and we are not generating PIC code,
11774 we can convert it to an absolute jump instruction. */
11775 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11776 insn
= 0x0c000000; /* jal */
11778 insn
= 0x08000000; /* j */
11779 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11781 fixP
->fx_addsy
= section_symbol (text_section
);
11782 *valP
+= md_pcrel_from (fixP
);
11783 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11787 /* If we got here, we have branch-relaxation disabled,
11788 and there's nothing we can do to fix this instruction
11789 without turning it into a longer sequence. */
11790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11791 _("Branch out of range"));
11795 case BFD_RELOC_VTABLE_INHERIT
:
11798 && !S_IS_DEFINED (fixP
->fx_addsy
)
11799 && !S_IS_WEAK (fixP
->fx_addsy
))
11800 S_SET_WEAK (fixP
->fx_addsy
);
11803 case BFD_RELOC_VTABLE_ENTRY
:
11811 /* Remember value for tc_gen_reloc. */
11812 fixP
->fx_addnumber
= *valP
;
11820 const struct mips_opcode
*p
;
11821 int treg
, sreg
, dreg
, shamt
;
11826 for (i
= 0; i
< NUMOPCODES
; ++i
)
11828 p
= &mips_opcodes
[i
];
11829 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11831 printf ("%08lx %s\t", oc
, p
->name
);
11832 treg
= (oc
>> 16) & 0x1f;
11833 sreg
= (oc
>> 21) & 0x1f;
11834 dreg
= (oc
>> 11) & 0x1f;
11835 shamt
= (oc
>> 6) & 0x1f;
11837 for (args
= p
->args
;; ++args
)
11848 printf ("%c", *args
);
11852 assert (treg
== sreg
);
11853 printf ("$%d,$%d", treg
, sreg
);
11858 printf ("$%d", dreg
);
11863 printf ("$%d", treg
);
11867 printf ("0x%x", treg
);
11872 printf ("$%d", sreg
);
11876 printf ("0x%08lx", oc
& 0x1ffffff);
11883 printf ("%d", imm
);
11888 printf ("$%d", shamt
);
11899 printf (_("%08lx UNDEFINED\n"), oc
);
11910 name
= input_line_pointer
;
11911 c
= get_symbol_end ();
11912 p
= (symbolS
*) symbol_find_or_make (name
);
11913 *input_line_pointer
= c
;
11917 /* Align the current frag to a given power of two. The MIPS assembler
11918 also automatically adjusts any preceding label. */
11921 mips_align (to
, fill
, label
)
11926 mips_emit_delays (FALSE
);
11927 frag_align (to
, fill
, 0);
11928 record_alignment (now_seg
, to
);
11931 assert (S_GET_SEGMENT (label
) == now_seg
);
11932 symbol_set_frag (label
, frag_now
);
11933 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11937 /* Align to a given power of two. .align 0 turns off the automatic
11938 alignment used by the data creating pseudo-ops. */
11942 int x ATTRIBUTE_UNUSED
;
11945 register long temp_fill
;
11946 long max_alignment
= 15;
11950 o Note that the assembler pulls down any immediately preceeding label
11951 to the aligned address.
11952 o It's not documented but auto alignment is reinstated by
11953 a .align pseudo instruction.
11954 o Note also that after auto alignment is turned off the mips assembler
11955 issues an error on attempt to assemble an improperly aligned data item.
11960 temp
= get_absolute_expression ();
11961 if (temp
> max_alignment
)
11962 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11965 as_warn (_("Alignment negative: 0 assumed."));
11968 if (*input_line_pointer
== ',')
11970 ++input_line_pointer
;
11971 temp_fill
= get_absolute_expression ();
11978 mips_align (temp
, (int) temp_fill
,
11979 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11986 demand_empty_rest_of_line ();
11990 mips_flush_pending_output ()
11992 mips_emit_delays (FALSE
);
11993 mips_clear_insn_labels ();
12002 /* When generating embedded PIC code, we only use the .text, .lit8,
12003 .sdata and .sbss sections. We change the .data and .rdata
12004 pseudo-ops to use .sdata. */
12005 if (mips_pic
== EMBEDDED_PIC
12006 && (sec
== 'd' || sec
== 'r'))
12010 /* The ELF backend needs to know that we are changing sections, so
12011 that .previous works correctly. We could do something like check
12012 for an obj_section_change_hook macro, but that might be confusing
12013 as it would not be appropriate to use it in the section changing
12014 functions in read.c, since obj-elf.c intercepts those. FIXME:
12015 This should be cleaner, somehow. */
12016 obj_elf_section_change_hook ();
12019 mips_emit_delays (FALSE
);
12029 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12030 demand_empty_rest_of_line ();
12034 if (USE_GLOBAL_POINTER_OPT
)
12036 seg
= subseg_new (RDATA_SECTION_NAME
,
12037 (subsegT
) get_absolute_expression ());
12038 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12040 bfd_set_section_flags (stdoutput
, seg
,
12046 if (strcmp (TARGET_OS
, "elf") != 0)
12047 record_alignment (seg
, 4);
12049 demand_empty_rest_of_line ();
12053 as_bad (_("No read only data section in this object file format"));
12054 demand_empty_rest_of_line ();
12060 if (USE_GLOBAL_POINTER_OPT
)
12062 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12063 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12065 bfd_set_section_flags (stdoutput
, seg
,
12066 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
12068 if (strcmp (TARGET_OS
, "elf") != 0)
12069 record_alignment (seg
, 4);
12071 demand_empty_rest_of_line ();
12076 as_bad (_("Global pointers not supported; recompile -G 0"));
12077 demand_empty_rest_of_line ();
12086 s_change_section (ignore
)
12087 int ignore ATTRIBUTE_UNUSED
;
12090 char *section_name
;
12095 int section_entry_size
;
12096 int section_alignment
;
12098 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12101 section_name
= input_line_pointer
;
12102 c
= get_symbol_end ();
12104 next_c
= *(input_line_pointer
+ 1);
12106 /* Do we have .section Name<,"flags">? */
12107 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12109 /* just after name is now '\0'. */
12110 *input_line_pointer
= c
;
12111 input_line_pointer
= section_name
;
12112 obj_elf_section (ignore
);
12115 input_line_pointer
++;
12117 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12119 section_type
= get_absolute_expression ();
12122 if (*input_line_pointer
++ == ',')
12123 section_flag
= get_absolute_expression ();
12126 if (*input_line_pointer
++ == ',')
12127 section_entry_size
= get_absolute_expression ();
12129 section_entry_size
= 0;
12130 if (*input_line_pointer
++ == ',')
12131 section_alignment
= get_absolute_expression ();
12133 section_alignment
= 0;
12135 section_name
= xstrdup (section_name
);
12137 obj_elf_change_section (section_name
, section_type
, section_flag
,
12138 section_entry_size
, 0, 0, 0);
12140 if (now_seg
->name
!= section_name
)
12141 free (section_name
);
12142 #endif /* OBJ_ELF */
12146 mips_enable_auto_align ()
12157 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12158 mips_emit_delays (FALSE
);
12159 if (log_size
> 0 && auto_align
)
12160 mips_align (log_size
, 0, label
);
12161 mips_clear_insn_labels ();
12162 cons (1 << log_size
);
12166 s_float_cons (type
)
12171 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12173 mips_emit_delays (FALSE
);
12178 mips_align (3, 0, label
);
12180 mips_align (2, 0, label
);
12183 mips_clear_insn_labels ();
12188 /* Handle .globl. We need to override it because on Irix 5 you are
12191 where foo is an undefined symbol, to mean that foo should be
12192 considered to be the address of a function. */
12196 int x ATTRIBUTE_UNUSED
;
12203 name
= input_line_pointer
;
12204 c
= get_symbol_end ();
12205 symbolP
= symbol_find_or_make (name
);
12206 *input_line_pointer
= c
;
12207 SKIP_WHITESPACE ();
12209 /* On Irix 5, every global symbol that is not explicitly labelled as
12210 being a function is apparently labelled as being an object. */
12213 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12218 secname
= input_line_pointer
;
12219 c
= get_symbol_end ();
12220 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12222 as_bad (_("%s: no such section"), secname
);
12223 *input_line_pointer
= c
;
12225 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12226 flag
= BSF_FUNCTION
;
12229 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12231 S_SET_EXTERNAL (symbolP
);
12232 demand_empty_rest_of_line ();
12237 int x ATTRIBUTE_UNUSED
;
12242 opt
= input_line_pointer
;
12243 c
= get_symbol_end ();
12247 /* FIXME: What does this mean? */
12249 else if (strncmp (opt
, "pic", 3) == 0)
12253 i
= atoi (opt
+ 3);
12258 mips_pic
= SVR4_PIC
;
12259 mips_abicalls
= TRUE
;
12262 as_bad (_(".option pic%d not supported"), i
);
12264 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
12266 if (g_switch_seen
&& g_switch_value
!= 0)
12267 as_warn (_("-G may not be used with SVR4 PIC code"));
12268 g_switch_value
= 0;
12269 bfd_set_gp_size (stdoutput
, 0);
12273 as_warn (_("Unrecognized option \"%s\""), opt
);
12275 *input_line_pointer
= c
;
12276 demand_empty_rest_of_line ();
12279 /* This structure is used to hold a stack of .set values. */
12281 struct mips_option_stack
12283 struct mips_option_stack
*next
;
12284 struct mips_set_options options
;
12287 static struct mips_option_stack
*mips_opts_stack
;
12289 /* Handle the .set pseudo-op. */
12293 int x ATTRIBUTE_UNUSED
;
12295 char *name
= input_line_pointer
, ch
;
12297 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12298 ++input_line_pointer
;
12299 ch
= *input_line_pointer
;
12300 *input_line_pointer
= '\0';
12302 if (strcmp (name
, "reorder") == 0)
12304 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
12306 /* If we still have pending nops, we can discard them. The
12307 usual nop handling will insert any that are still
12309 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12310 * (mips_opts
.mips16
? 2 : 4));
12311 prev_nop_frag
= NULL
;
12313 mips_opts
.noreorder
= 0;
12315 else if (strcmp (name
, "noreorder") == 0)
12317 mips_emit_delays (TRUE
);
12318 mips_opts
.noreorder
= 1;
12319 mips_any_noreorder
= 1;
12321 else if (strcmp (name
, "at") == 0)
12323 mips_opts
.noat
= 0;
12325 else if (strcmp (name
, "noat") == 0)
12327 mips_opts
.noat
= 1;
12329 else if (strcmp (name
, "macro") == 0)
12331 mips_opts
.warn_about_macros
= 0;
12333 else if (strcmp (name
, "nomacro") == 0)
12335 if (mips_opts
.noreorder
== 0)
12336 as_bad (_("`noreorder' must be set before `nomacro'"));
12337 mips_opts
.warn_about_macros
= 1;
12339 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12341 mips_opts
.nomove
= 0;
12343 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12345 mips_opts
.nomove
= 1;
12347 else if (strcmp (name
, "bopt") == 0)
12349 mips_opts
.nobopt
= 0;
12351 else if (strcmp (name
, "nobopt") == 0)
12353 mips_opts
.nobopt
= 1;
12355 else if (strcmp (name
, "mips16") == 0
12356 || strcmp (name
, "MIPS-16") == 0)
12357 mips_opts
.mips16
= 1;
12358 else if (strcmp (name
, "nomips16") == 0
12359 || strcmp (name
, "noMIPS-16") == 0)
12360 mips_opts
.mips16
= 0;
12361 else if (strcmp (name
, "mips3d") == 0)
12362 mips_opts
.ase_mips3d
= 1;
12363 else if (strcmp (name
, "nomips3d") == 0)
12364 mips_opts
.ase_mips3d
= 0;
12365 else if (strcmp (name
, "mdmx") == 0)
12366 mips_opts
.ase_mdmx
= 1;
12367 else if (strcmp (name
, "nomdmx") == 0)
12368 mips_opts
.ase_mdmx
= 0;
12369 else if (strncmp (name
, "mips", 4) == 0)
12373 /* Permit the user to change the ISA on the fly. Needless to
12374 say, misuse can cause serious problems. */
12375 if (strcmp (name
, "mips0") == 0)
12378 mips_opts
.isa
= file_mips_isa
;
12380 else if (strcmp (name
, "mips1") == 0)
12381 mips_opts
.isa
= ISA_MIPS1
;
12382 else if (strcmp (name
, "mips2") == 0)
12383 mips_opts
.isa
= ISA_MIPS2
;
12384 else if (strcmp (name
, "mips3") == 0)
12385 mips_opts
.isa
= ISA_MIPS3
;
12386 else if (strcmp (name
, "mips4") == 0)
12387 mips_opts
.isa
= ISA_MIPS4
;
12388 else if (strcmp (name
, "mips5") == 0)
12389 mips_opts
.isa
= ISA_MIPS5
;
12390 else if (strcmp (name
, "mips32") == 0)
12391 mips_opts
.isa
= ISA_MIPS32
;
12392 else if (strcmp (name
, "mips32r2") == 0)
12393 mips_opts
.isa
= ISA_MIPS32R2
;
12394 else if (strcmp (name
, "mips64") == 0)
12395 mips_opts
.isa
= ISA_MIPS64
;
12397 as_bad (_("unknown ISA level %s"), name
+ 4);
12399 switch (mips_opts
.isa
)
12407 mips_opts
.gp32
= 1;
12408 mips_opts
.fp32
= 1;
12414 mips_opts
.gp32
= 0;
12415 mips_opts
.fp32
= 0;
12418 as_bad (_("unknown ISA level %s"), name
+ 4);
12423 mips_opts
.gp32
= file_mips_gp32
;
12424 mips_opts
.fp32
= file_mips_fp32
;
12427 else if (strcmp (name
, "autoextend") == 0)
12428 mips_opts
.noautoextend
= 0;
12429 else if (strcmp (name
, "noautoextend") == 0)
12430 mips_opts
.noautoextend
= 1;
12431 else if (strcmp (name
, "push") == 0)
12433 struct mips_option_stack
*s
;
12435 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12436 s
->next
= mips_opts_stack
;
12437 s
->options
= mips_opts
;
12438 mips_opts_stack
= s
;
12440 else if (strcmp (name
, "pop") == 0)
12442 struct mips_option_stack
*s
;
12444 s
= mips_opts_stack
;
12446 as_bad (_(".set pop with no .set push"));
12449 /* If we're changing the reorder mode we need to handle
12450 delay slots correctly. */
12451 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12452 mips_emit_delays (TRUE
);
12453 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12455 if (prev_nop_frag
!= NULL
)
12457 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12458 * (mips_opts
.mips16
? 2 : 4));
12459 prev_nop_frag
= NULL
;
12463 mips_opts
= s
->options
;
12464 mips_opts_stack
= s
->next
;
12468 else if (strncmp (name
, "arch=", 5) == 0)
12470 /* Permit the user to change the architecture on the fly. Needless
12471 to say, misuse can cause serious problems. */
12472 if (strcmp (name
+ 5, "default") == 0)
12474 mips_opts
.arch
= file_mips_arch
;
12475 mips_opts
.isa
= file_mips_isa
;
12476 mips_opts
.gp32
= file_mips_gp32
;
12477 mips_opts
.fp32
= file_mips_fp32
;
12481 const struct mips_cpu_info
*p
;
12483 p
= mips_parse_cpu("internal use", name
+ 5);
12485 as_bad (_("unknown architecture %s"), name
+ 5);
12488 mips_opts
.arch
= p
->cpu
;
12489 mips_opts
.isa
= p
->isa
;
12492 switch (mips_opts
.arch
)
12499 mips_opts
.gp32
= 1;
12500 mips_opts
.fp32
= 1;
12503 mips_opts
.gp32
= 0;
12504 mips_opts
.fp32
= 0;
12511 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12513 *input_line_pointer
= ch
;
12514 demand_empty_rest_of_line ();
12517 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12518 .option pic2. It means to generate SVR4 PIC calls. */
12521 s_abicalls (ignore
)
12522 int ignore ATTRIBUTE_UNUSED
;
12524 mips_pic
= SVR4_PIC
;
12525 mips_abicalls
= TRUE
;
12526 if (USE_GLOBAL_POINTER_OPT
)
12528 if (g_switch_seen
&& g_switch_value
!= 0)
12529 as_warn (_("-G may not be used with SVR4 PIC code"));
12530 g_switch_value
= 0;
12532 bfd_set_gp_size (stdoutput
, 0);
12533 demand_empty_rest_of_line ();
12536 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12537 PIC code. It sets the $gp register for the function based on the
12538 function address, which is in the register named in the argument.
12539 This uses a relocation against _gp_disp, which is handled specially
12540 by the linker. The result is:
12541 lui $gp,%hi(_gp_disp)
12542 addiu $gp,$gp,%lo(_gp_disp)
12543 addu $gp,$gp,.cpload argument
12544 The .cpload argument is normally $25 == $t9. */
12548 int ignore ATTRIBUTE_UNUSED
;
12553 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12554 .cpload is ignored. */
12555 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12561 /* .cpload should be in a .set noreorder section. */
12562 if (mips_opts
.noreorder
== 0)
12563 as_warn (_(".cpload not in noreorder section"));
12565 ex
.X_op
= O_symbol
;
12566 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12567 ex
.X_op_symbol
= NULL
;
12568 ex
.X_add_number
= 0;
12570 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12571 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12573 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12574 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12575 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12578 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12580 demand_empty_rest_of_line ();
12583 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12584 .cpsetup $reg1, offset|$reg2, label
12586 If offset is given, this results in:
12587 sd $gp, offset($sp)
12588 lui $gp, %hi(%neg(%gp_rel(label)))
12589 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12590 daddu $gp, $gp, $reg1
12592 If $reg2 is given, this results in:
12593 daddu $reg2, $gp, $0
12594 lui $gp, %hi(%neg(%gp_rel(label)))
12595 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12596 daddu $gp, $gp, $reg1
12597 $reg1 is normally $25 == $t9. */
12600 int ignore ATTRIBUTE_UNUSED
;
12602 expressionS ex_off
;
12603 expressionS ex_sym
;
12608 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12609 We also need NewABI support. */
12610 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12616 reg1
= tc_get_register (0);
12617 SKIP_WHITESPACE ();
12618 if (*input_line_pointer
!= ',')
12620 as_bad (_("missing argument separator ',' for .cpsetup"));
12624 ++input_line_pointer
;
12625 SKIP_WHITESPACE ();
12626 if (*input_line_pointer
== '$')
12628 mips_cpreturn_register
= tc_get_register (0);
12629 mips_cpreturn_offset
= -1;
12633 mips_cpreturn_offset
= get_absolute_expression ();
12634 mips_cpreturn_register
= -1;
12636 SKIP_WHITESPACE ();
12637 if (*input_line_pointer
!= ',')
12639 as_bad (_("missing argument separator ',' for .cpsetup"));
12643 ++input_line_pointer
;
12644 SKIP_WHITESPACE ();
12645 expression (&ex_sym
);
12647 if (mips_cpreturn_register
== -1)
12649 ex_off
.X_op
= O_constant
;
12650 ex_off
.X_add_symbol
= NULL
;
12651 ex_off
.X_op_symbol
= NULL
;
12652 ex_off
.X_add_number
= mips_cpreturn_offset
;
12654 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12655 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12659 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12661 /* Ensure there's room for the next two instructions, so that `f'
12662 doesn't end up with an address in the wrong frag. */
12665 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12666 (int) BFD_RELOC_GPREL16
);
12667 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12668 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12669 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12670 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12673 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12674 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12675 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12676 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12677 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12678 4, NULL
, 0, 0, BFD_RELOC_LO16
);
12680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
12681 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
12683 demand_empty_rest_of_line ();
12688 int ignore ATTRIBUTE_UNUSED
;
12690 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12691 .cplocal is ignored. */
12692 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12698 mips_gp_register
= tc_get_register (0);
12699 demand_empty_rest_of_line ();
12702 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12703 offset from $sp. The offset is remembered, and after making a PIC
12704 call $gp is restored from that location. */
12707 s_cprestore (ignore
)
12708 int ignore ATTRIBUTE_UNUSED
;
12713 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12714 .cprestore is ignored. */
12715 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12721 mips_cprestore_offset
= get_absolute_expression ();
12722 mips_cprestore_valid
= 1;
12724 ex
.X_op
= O_constant
;
12725 ex
.X_add_symbol
= NULL
;
12726 ex
.X_op_symbol
= NULL
;
12727 ex
.X_add_number
= mips_cprestore_offset
;
12729 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
, ADDRESS_STORE_INSN
,
12730 mips_gp_register
, SP
);
12732 demand_empty_rest_of_line ();
12735 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12736 was given in the preceeding .gpsetup, it results in:
12737 ld $gp, offset($sp)
12739 If a register $reg2 was given there, it results in:
12740 daddiu $gp, $gp, $reg2
12743 s_cpreturn (ignore
)
12744 int ignore ATTRIBUTE_UNUSED
;
12749 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12750 We also need NewABI support. */
12751 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12757 if (mips_cpreturn_register
== -1)
12759 ex
.X_op
= O_constant
;
12760 ex
.X_add_symbol
= NULL
;
12761 ex
.X_op_symbol
= NULL
;
12762 ex
.X_add_number
= mips_cpreturn_offset
;
12764 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12765 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12769 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12771 demand_empty_rest_of_line ();
12774 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12775 code. It sets the offset to use in gp_rel relocations. */
12779 int ignore ATTRIBUTE_UNUSED
;
12781 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12782 We also need NewABI support. */
12783 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12789 mips_gprel_offset
= get_absolute_expression ();
12791 demand_empty_rest_of_line ();
12794 /* Handle the .gpword pseudo-op. This is used when generating PIC
12795 code. It generates a 32 bit GP relative reloc. */
12799 int ignore ATTRIBUTE_UNUSED
;
12805 /* When not generating PIC code, this is treated as .word. */
12806 if (mips_pic
!= SVR4_PIC
)
12812 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12813 mips_emit_delays (TRUE
);
12815 mips_align (2, 0, label
);
12816 mips_clear_insn_labels ();
12820 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12822 as_bad (_("Unsupported use of .gpword"));
12823 ignore_rest_of_line ();
12827 md_number_to_chars (p
, (valueT
) 0, 4);
12828 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12829 BFD_RELOC_GPREL32
);
12831 demand_empty_rest_of_line ();
12836 int ignore ATTRIBUTE_UNUSED
;
12842 /* When not generating PIC code, this is treated as .dword. */
12843 if (mips_pic
!= SVR4_PIC
)
12849 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12850 mips_emit_delays (TRUE
);
12852 mips_align (3, 0, label
);
12853 mips_clear_insn_labels ();
12857 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12859 as_bad (_("Unsupported use of .gpdword"));
12860 ignore_rest_of_line ();
12864 md_number_to_chars (p
, (valueT
) 0, 8);
12865 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12866 BFD_RELOC_GPREL32
);
12868 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12869 ex
.X_op
= O_absent
;
12870 ex
.X_add_symbol
= 0;
12871 ex
.X_add_number
= 0;
12872 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12875 demand_empty_rest_of_line ();
12878 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12879 tables in SVR4 PIC code. */
12883 int ignore ATTRIBUTE_UNUSED
;
12888 /* This is ignored when not generating SVR4 PIC code. */
12889 if (mips_pic
!= SVR4_PIC
)
12895 /* Add $gp to the register named as an argument. */
12896 reg
= tc_get_register (0);
12897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, ADDRESS_ADD_INSN
,
12898 "d,v,t", reg
, reg
, mips_gp_register
);
12900 demand_empty_rest_of_line ();
12903 /* Handle the .insn pseudo-op. This marks instruction labels in
12904 mips16 mode. This permits the linker to handle them specially,
12905 such as generating jalx instructions when needed. We also make
12906 them odd for the duration of the assembly, in order to generate the
12907 right sort of code. We will make them even in the adjust_symtab
12908 routine, while leaving them marked. This is convenient for the
12909 debugger and the disassembler. The linker knows to make them odd
12914 int ignore ATTRIBUTE_UNUSED
;
12916 mips16_mark_labels ();
12918 demand_empty_rest_of_line ();
12921 /* Handle a .stabn directive. We need these in order to mark a label
12922 as being a mips16 text label correctly. Sometimes the compiler
12923 will emit a label, followed by a .stabn, and then switch sections.
12924 If the label and .stabn are in mips16 mode, then the label is
12925 really a mips16 text label. */
12932 mips16_mark_labels ();
12937 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12941 s_mips_weakext (ignore
)
12942 int ignore ATTRIBUTE_UNUSED
;
12949 name
= input_line_pointer
;
12950 c
= get_symbol_end ();
12951 symbolP
= symbol_find_or_make (name
);
12952 S_SET_WEAK (symbolP
);
12953 *input_line_pointer
= c
;
12955 SKIP_WHITESPACE ();
12957 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12959 if (S_IS_DEFINED (symbolP
))
12961 as_bad ("ignoring attempt to redefine symbol %s",
12962 S_GET_NAME (symbolP
));
12963 ignore_rest_of_line ();
12967 if (*input_line_pointer
== ',')
12969 ++input_line_pointer
;
12970 SKIP_WHITESPACE ();
12974 if (exp
.X_op
!= O_symbol
)
12976 as_bad ("bad .weakext directive");
12977 ignore_rest_of_line ();
12980 symbol_set_value_expression (symbolP
, &exp
);
12983 demand_empty_rest_of_line ();
12986 /* Parse a register string into a number. Called from the ECOFF code
12987 to parse .frame. The argument is non-zero if this is the frame
12988 register, so that we can record it in mips_frame_reg. */
12991 tc_get_register (frame
)
12996 SKIP_WHITESPACE ();
12997 if (*input_line_pointer
++ != '$')
12999 as_warn (_("expected `$'"));
13002 else if (ISDIGIT (*input_line_pointer
))
13004 reg
= get_absolute_expression ();
13005 if (reg
< 0 || reg
>= 32)
13007 as_warn (_("Bad register number"));
13013 if (strncmp (input_line_pointer
, "ra", 2) == 0)
13016 input_line_pointer
+= 2;
13018 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
13021 input_line_pointer
+= 2;
13023 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
13026 input_line_pointer
+= 2;
13028 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
13031 input_line_pointer
+= 2;
13033 else if (strncmp (input_line_pointer
, "at", 2) == 0)
13036 input_line_pointer
+= 2;
13038 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
13041 input_line_pointer
+= 3;
13043 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
13046 input_line_pointer
+= 3;
13048 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
13051 input_line_pointer
+= 4;
13055 as_warn (_("Unrecognized register name"));
13057 while (ISALNUM(*input_line_pointer
))
13058 input_line_pointer
++;
13063 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13064 mips_frame_reg_valid
= 1;
13065 mips_cprestore_valid
= 0;
13071 md_section_align (seg
, addr
)
13075 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13078 /* We don't need to align ELF sections to the full alignment.
13079 However, Irix 5 may prefer that we align them at least to a 16
13080 byte boundary. We don't bother to align the sections if we are
13081 targeted for an embedded system. */
13082 if (strcmp (TARGET_OS
, "elf") == 0)
13088 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13091 /* Utility routine, called from above as well. If called while the
13092 input file is still being read, it's only an approximation. (For
13093 example, a symbol may later become defined which appeared to be
13094 undefined earlier.) */
13097 nopic_need_relax (sym
, before_relaxing
)
13099 int before_relaxing
;
13104 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
13106 const char *symname
;
13109 /* Find out whether this symbol can be referenced off the $gp
13110 register. It can be if it is smaller than the -G size or if
13111 it is in the .sdata or .sbss section. Certain symbols can
13112 not be referenced off the $gp, although it appears as though
13114 symname
= S_GET_NAME (sym
);
13115 if (symname
!= (const char *) NULL
13116 && (strcmp (symname
, "eprol") == 0
13117 || strcmp (symname
, "etext") == 0
13118 || strcmp (symname
, "_gp") == 0
13119 || strcmp (symname
, "edata") == 0
13120 || strcmp (symname
, "_fbss") == 0
13121 || strcmp (symname
, "_fdata") == 0
13122 || strcmp (symname
, "_ftext") == 0
13123 || strcmp (symname
, "end") == 0
13124 || strcmp (symname
, "_gp_disp") == 0))
13126 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13128 #ifndef NO_ECOFF_DEBUGGING
13129 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13130 && (symbol_get_obj (sym
)->ecoff_extern_size
13131 <= g_switch_value
))
13133 /* We must defer this decision until after the whole
13134 file has been read, since there might be a .extern
13135 after the first use of this symbol. */
13136 || (before_relaxing
13137 #ifndef NO_ECOFF_DEBUGGING
13138 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13140 && S_GET_VALUE (sym
) == 0)
13141 || (S_GET_VALUE (sym
) != 0
13142 && S_GET_VALUE (sym
) <= g_switch_value
)))
13146 const char *segname
;
13148 segname
= segment_name (S_GET_SEGMENT (sym
));
13149 assert (strcmp (segname
, ".lit8") != 0
13150 && strcmp (segname
, ".lit4") != 0);
13151 change
= (strcmp (segname
, ".sdata") != 0
13152 && strcmp (segname
, ".sbss") != 0
13153 && strncmp (segname
, ".sdata.", 7) != 0
13154 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13159 /* We are not optimizing for the $gp register. */
13164 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13167 pic_need_relax (sym
, segtype
)
13172 bfd_boolean linkonce
;
13174 /* Handle the case of a symbol equated to another symbol. */
13175 while (symbol_equated_reloc_p (sym
))
13179 /* It's possible to get a loop here in a badly written
13181 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13187 symsec
= S_GET_SEGMENT (sym
);
13189 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13191 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13193 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13197 /* The GNU toolchain uses an extension for ELF: a section
13198 beginning with the magic string .gnu.linkonce is a linkonce
13200 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13201 sizeof ".gnu.linkonce" - 1) == 0)
13205 /* This must duplicate the test in adjust_reloc_syms. */
13206 return (symsec
!= &bfd_und_section
13207 && symsec
!= &bfd_abs_section
13208 && ! bfd_is_com_section (symsec
)
13211 /* A global or weak symbol is treated as external. */
13212 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13213 || (! S_IS_WEAK (sym
)
13214 && (! S_IS_EXTERNAL (sym
)
13215 || mips_pic
== EMBEDDED_PIC
)))
13221 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13222 extended opcode. SEC is the section the frag is in. */
13225 mips16_extended_frag (fragp
, sec
, stretch
)
13231 register const struct mips16_immed_operand
*op
;
13233 int mintiny
, maxtiny
;
13237 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13239 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13242 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13243 op
= mips16_immed_operands
;
13244 while (op
->type
!= type
)
13247 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13252 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13255 maxtiny
= 1 << op
->nbits
;
13260 maxtiny
= (1 << op
->nbits
) - 1;
13265 mintiny
= - (1 << (op
->nbits
- 1));
13266 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13269 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13270 val
= S_GET_VALUE (fragp
->fr_symbol
);
13271 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13277 /* We won't have the section when we are called from
13278 mips_relax_frag. However, we will always have been called
13279 from md_estimate_size_before_relax first. If this is a
13280 branch to a different section, we mark it as such. If SEC is
13281 NULL, and the frag is not marked, then it must be a branch to
13282 the same section. */
13285 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13290 /* Must have been called from md_estimate_size_before_relax. */
13293 fragp
->fr_subtype
=
13294 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13296 /* FIXME: We should support this, and let the linker
13297 catch branches and loads that are out of range. */
13298 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13299 _("unsupported PC relative reference to different section"));
13303 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13304 /* Assume non-extended on the first relaxation pass.
13305 The address we have calculated will be bogus if this is
13306 a forward branch to another frag, as the forward frag
13307 will have fr_address == 0. */
13311 /* In this case, we know for sure that the symbol fragment is in
13312 the same section. If the relax_marker of the symbol fragment
13313 differs from the relax_marker of this fragment, we have not
13314 yet adjusted the symbol fragment fr_address. We want to add
13315 in STRETCH in order to get a better estimate of the address.
13316 This particularly matters because of the shift bits. */
13318 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13322 /* Adjust stretch for any alignment frag. Note that if have
13323 been expanding the earlier code, the symbol may be
13324 defined in what appears to be an earlier frag. FIXME:
13325 This doesn't handle the fr_subtype field, which specifies
13326 a maximum number of bytes to skip when doing an
13328 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13330 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13333 stretch
= - ((- stretch
)
13334 & ~ ((1 << (int) f
->fr_offset
) - 1));
13336 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13345 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13347 /* The base address rules are complicated. The base address of
13348 a branch is the following instruction. The base address of a
13349 PC relative load or add is the instruction itself, but if it
13350 is in a delay slot (in which case it can not be extended) use
13351 the address of the instruction whose delay slot it is in. */
13352 if (type
== 'p' || type
== 'q')
13356 /* If we are currently assuming that this frag should be
13357 extended, then, the current address is two bytes
13359 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13362 /* Ignore the low bit in the target, since it will be set
13363 for a text label. */
13364 if ((val
& 1) != 0)
13367 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13369 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13372 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13374 /* Branch offsets have an implicit 0 in the lowest bit. */
13375 if (type
== 'p' || type
== 'q')
13378 /* If any of the shifted bits are set, we must use an extended
13379 opcode. If the address depends on the size of this
13380 instruction, this can lead to a loop, so we arrange to always
13381 use an extended opcode. We only check this when we are in
13382 the main relaxation loop, when SEC is NULL. */
13383 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13385 fragp
->fr_subtype
=
13386 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13390 /* If we are about to mark a frag as extended because the value
13391 is precisely maxtiny + 1, then there is a chance of an
13392 infinite loop as in the following code:
13397 In this case when the la is extended, foo is 0x3fc bytes
13398 away, so the la can be shrunk, but then foo is 0x400 away, so
13399 the la must be extended. To avoid this loop, we mark the
13400 frag as extended if it was small, and is about to become
13401 extended with a value of maxtiny + 1. */
13402 if (val
== ((maxtiny
+ 1) << op
->shift
)
13403 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13406 fragp
->fr_subtype
=
13407 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13411 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13412 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13414 if ((val
& ((1 << op
->shift
) - 1)) != 0
13415 || val
< (mintiny
<< op
->shift
)
13416 || val
> (maxtiny
<< op
->shift
))
13422 /* Compute the length of a branch sequence, and adjust the
13423 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13424 worst-case length is computed, with UPDATE being used to indicate
13425 whether an unconditional (-1), branch-likely (+1) or regular (0)
13426 branch is to be computed. */
13428 relaxed_branch_length (fragp
, sec
, update
)
13433 bfd_boolean toofar
;
13437 && S_IS_DEFINED (fragp
->fr_symbol
)
13438 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13443 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13445 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13449 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13452 /* If the symbol is not defined or it's in a different segment,
13453 assume the user knows what's going on and emit a short
13459 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13461 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13462 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13463 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13469 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13472 if (mips_pic
!= NO_PIC
)
13474 /* Additional space for PIC loading of target address. */
13476 if (mips_opts
.isa
== ISA_MIPS1
)
13477 /* Additional space for $at-stabilizing nop. */
13481 /* If branch is conditional. */
13482 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13489 /* Estimate the size of a frag before relaxing. Unless this is the
13490 mips16, we are not really relaxing here, and the final size is
13491 encoded in the subtype information. For the mips16, we have to
13492 decide whether we are using an extended opcode or not. */
13495 md_estimate_size_before_relax (fragp
, segtype
)
13501 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13504 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13506 return fragp
->fr_var
;
13509 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13510 /* We don't want to modify the EXTENDED bit here; it might get us
13511 into infinite loops. We change it only in mips_relax_frag(). */
13512 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13514 if (mips_pic
== NO_PIC
)
13515 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13516 else if (mips_pic
== SVR4_PIC
)
13517 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13523 /* Record the offset to the first reloc in the fr_opcode field.
13524 This lets md_convert_frag and tc_gen_reloc know that the code
13525 must be expanded. */
13526 fragp
->fr_opcode
= (fragp
->fr_literal
13528 - RELAX_OLD (fragp
->fr_subtype
)
13529 + RELAX_RELOC1 (fragp
->fr_subtype
));
13530 /* FIXME: This really needs as_warn_where. */
13531 if (RELAX_WARN (fragp
->fr_subtype
))
13532 as_warn (_("AT used after \".set noat\" or macro used after "
13533 "\".set nomacro\""));
13535 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13541 /* This is called to see whether a reloc against a defined symbol
13542 should be converted into a reloc against a section. Don't adjust
13543 MIPS16 jump relocations, so we don't have to worry about the format
13544 of the offset in the .o file. Don't adjust relocations against
13545 mips16 symbols, so that the linker can find them if it needs to set
13549 mips_fix_adjustable (fixp
)
13552 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13555 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13556 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13559 if (fixp
->fx_addsy
== NULL
)
13563 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13564 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13565 && fixp
->fx_subsy
== NULL
)
13572 /* Translate internal representation of relocation info to BFD target
13576 tc_gen_reloc (section
, fixp
)
13577 asection
*section ATTRIBUTE_UNUSED
;
13580 static arelent
*retval
[4];
13582 bfd_reloc_code_real_type code
;
13584 memset (retval
, 0, sizeof(retval
));
13585 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13586 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13587 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13588 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13590 if (mips_pic
== EMBEDDED_PIC
13591 && SWITCH_TABLE (fixp
))
13593 /* For a switch table entry we use a special reloc. The addend
13594 is actually the difference between the reloc address and the
13596 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13597 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13598 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13599 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13601 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13603 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13604 reloc
->addend
= fixp
->fx_addnumber
;
13607 /* We use a special addend for an internal RELLO reloc. */
13608 if (symbol_section_p (fixp
->fx_addsy
))
13609 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13611 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13614 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13616 assert (fixp
->fx_next
!= NULL
13617 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13619 /* The reloc is relative to the RELLO; adjust the addend
13621 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13622 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13625 /* We use a special addend for an internal RELHI reloc. */
13626 if (symbol_section_p (fixp
->fx_addsy
))
13627 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13628 + fixp
->fx_next
->fx_where
13629 - S_GET_VALUE (fixp
->fx_subsy
));
13631 reloc
->addend
= (fixp
->fx_addnumber
13632 + fixp
->fx_next
->fx_frag
->fr_address
13633 + fixp
->fx_next
->fx_where
);
13636 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13637 reloc
->addend
= fixp
->fx_addnumber
;
13640 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13641 /* A gruesome hack which is a result of the gruesome gas reloc
13643 reloc
->addend
= reloc
->address
;
13645 reloc
->addend
= -reloc
->address
;
13648 /* If this is a variant frag, we may need to adjust the existing
13649 reloc and generate a new one. */
13650 if (fixp
->fx_frag
->fr_opcode
!= NULL
13651 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13653 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_DISP
13655 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13656 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13657 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13658 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13659 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13660 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13665 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13667 /* If this is not the last reloc in this frag, then we have two
13668 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13669 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13670 the second one handle all of them. */
13671 if (fixp
->fx_next
!= NULL
13672 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13674 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13675 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13676 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13677 && (fixp
->fx_next
->fx_r_type
13678 == BFD_RELOC_MIPS_GOT_LO16
))
13679 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13680 && (fixp
->fx_next
->fx_r_type
13681 == BFD_RELOC_MIPS_CALL_LO16
)));
13686 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13687 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13688 reloc
->addend
+= fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13689 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13690 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13691 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13692 reloc2
->address
= (reloc
->address
13693 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13694 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13695 reloc2
->addend
= fixp
->fx_addnumber
- S_GET_VALUE (fixp
->fx_addsy
)
13696 + fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13697 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13698 assert (reloc2
->howto
!= NULL
);
13700 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13704 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13706 reloc3
->address
+= 4;
13709 if (mips_pic
== NO_PIC
)
13711 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13712 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13714 else if (mips_pic
== SVR4_PIC
)
13716 switch (fixp
->fx_r_type
)
13720 case BFD_RELOC_MIPS_GOT16
:
13722 case BFD_RELOC_MIPS_GOT_LO16
:
13723 case BFD_RELOC_MIPS_CALL_LO16
:
13726 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13727 reloc2
->howto
= bfd_reloc_type_lookup
13728 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13731 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13733 case BFD_RELOC_MIPS_CALL16
:
13734 case BFD_RELOC_MIPS_GOT_OFST
:
13735 case BFD_RELOC_MIPS_GOT_DISP
:
13738 /* It may seem nonsensical to relax GOT_DISP to
13739 GOT_DISP, but we're actually turning a GOT_DISP
13740 without offset into a GOT_DISP with an offset,
13741 getting rid of the separate addition, which we can
13742 do when the symbol is found to be local. */
13743 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13747 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13755 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13756 entry to be used in the relocation's section offset. */
13757 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13759 reloc
->address
= reloc
->addend
;
13763 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13764 fixup_segment converted a non-PC relative reloc into a PC
13765 relative reloc. In such a case, we need to convert the reloc
13767 code
= fixp
->fx_r_type
;
13768 if (fixp
->fx_pcrel
)
13773 code
= BFD_RELOC_8_PCREL
;
13776 code
= BFD_RELOC_16_PCREL
;
13779 code
= BFD_RELOC_32_PCREL
;
13782 code
= BFD_RELOC_64_PCREL
;
13784 case BFD_RELOC_8_PCREL
:
13785 case BFD_RELOC_16_PCREL
:
13786 case BFD_RELOC_32_PCREL
:
13787 case BFD_RELOC_64_PCREL
:
13788 case BFD_RELOC_16_PCREL_S2
:
13789 case BFD_RELOC_PCREL_HI16_S
:
13790 case BFD_RELOC_PCREL_LO16
:
13793 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13794 _("Cannot make %s relocation PC relative"),
13795 bfd_get_reloc_code_name (code
));
13799 /* To support a PC relative reloc when generating embedded PIC code
13800 for ECOFF, we use a Cygnus extension. We check for that here to
13801 make sure that we don't let such a reloc escape normally. */
13802 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13803 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13804 && code
== BFD_RELOC_16_PCREL_S2
13805 && mips_pic
!= EMBEDDED_PIC
)
13806 reloc
->howto
= NULL
;
13808 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13810 if (reloc
->howto
== NULL
)
13812 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13813 _("Can not represent %s relocation in this object file format"),
13814 bfd_get_reloc_code_name (code
));
13821 /* Relax a machine dependent frag. This returns the amount by which
13822 the current size of the frag should change. */
13825 mips_relax_frag (sec
, fragp
, stretch
)
13830 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13832 offsetT old_var
= fragp
->fr_var
;
13834 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13836 return fragp
->fr_var
- old_var
;
13839 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13842 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13844 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13846 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13851 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13853 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13860 /* Convert a machine dependent frag. */
13863 md_convert_frag (abfd
, asec
, fragp
)
13864 bfd
*abfd ATTRIBUTE_UNUSED
;
13871 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13874 unsigned long insn
;
13878 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13880 if (target_big_endian
)
13881 insn
= bfd_getb32 (buf
);
13883 insn
= bfd_getl32 (buf
);
13885 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13887 /* We generate a fixup instead of applying it right now
13888 because, if there are linker relaxations, we're going to
13889 need the relocations. */
13890 exp
.X_op
= O_symbol
;
13891 exp
.X_add_symbol
= fragp
->fr_symbol
;
13892 exp
.X_add_number
= fragp
->fr_offset
;
13894 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13896 BFD_RELOC_16_PCREL_S2
);
13897 fixp
->fx_file
= fragp
->fr_file
;
13898 fixp
->fx_line
= fragp
->fr_line
;
13900 md_number_to_chars ((char *)buf
, insn
, 4);
13907 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13908 _("relaxed out-of-range branch into a jump"));
13910 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13913 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13915 /* Reverse the branch. */
13916 switch ((insn
>> 28) & 0xf)
13919 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13920 have the condition reversed by tweaking a single
13921 bit, and their opcodes all have 0x4???????. */
13922 assert ((insn
& 0xf1000000) == 0x41000000);
13923 insn
^= 0x00010000;
13927 /* bltz 0x04000000 bgez 0x04010000
13928 bltzal 0x04100000 bgezal 0x04110000 */
13929 assert ((insn
& 0xfc0e0000) == 0x04000000);
13930 insn
^= 0x00010000;
13934 /* beq 0x10000000 bne 0x14000000
13935 blez 0x18000000 bgtz 0x1c000000 */
13936 insn
^= 0x04000000;
13944 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13946 /* Clear the and-link bit. */
13947 assert ((insn
& 0xfc1c0000) == 0x04100000);
13949 /* bltzal 0x04100000 bgezal 0x04110000
13950 bltzall 0x04120000 bgezall 0x04130000 */
13951 insn
&= ~0x00100000;
13954 /* Branch over the branch (if the branch was likely) or the
13955 full jump (not likely case). Compute the offset from the
13956 current instruction to branch to. */
13957 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13961 /* How many bytes in instructions we've already emitted? */
13962 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13963 /* How many bytes in instructions from here to the end? */
13964 i
= fragp
->fr_var
- i
;
13966 /* Convert to instruction count. */
13968 /* Branch counts from the next instruction. */
13971 /* Branch over the jump. */
13972 md_number_to_chars ((char *)buf
, insn
, 4);
13976 md_number_to_chars ((char*)buf
, 0, 4);
13979 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13981 /* beql $0, $0, 2f */
13983 /* Compute the PC offset from the current instruction to
13984 the end of the variable frag. */
13985 /* How many bytes in instructions we've already emitted? */
13986 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13987 /* How many bytes in instructions from here to the end? */
13988 i
= fragp
->fr_var
- i
;
13989 /* Convert to instruction count. */
13991 /* Don't decrement i, because we want to branch over the
13995 md_number_to_chars ((char *)buf
, insn
, 4);
13998 md_number_to_chars ((char *)buf
, 0, 4);
14003 if (mips_pic
== NO_PIC
)
14006 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14007 ? 0x0c000000 : 0x08000000);
14008 exp
.X_op
= O_symbol
;
14009 exp
.X_add_symbol
= fragp
->fr_symbol
;
14010 exp
.X_add_number
= fragp
->fr_offset
;
14012 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14013 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
14014 fixp
->fx_file
= fragp
->fr_file
;
14015 fixp
->fx_line
= fragp
->fr_line
;
14017 md_number_to_chars ((char*)buf
, insn
, 4);
14022 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14023 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14024 exp
.X_op
= O_symbol
;
14025 exp
.X_add_symbol
= fragp
->fr_symbol
;
14026 exp
.X_add_number
= fragp
->fr_offset
;
14028 if (fragp
->fr_offset
)
14030 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14031 exp
.X_add_number
= 0;
14034 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14035 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
14036 fixp
->fx_file
= fragp
->fr_file
;
14037 fixp
->fx_line
= fragp
->fr_line
;
14039 md_number_to_chars ((char*)buf
, insn
, 4);
14042 if (mips_opts
.isa
== ISA_MIPS1
)
14045 md_number_to_chars ((char*)buf
, 0, 4);
14049 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14050 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14052 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14053 4, &exp
, 0, BFD_RELOC_LO16
);
14054 fixp
->fx_file
= fragp
->fr_file
;
14055 fixp
->fx_line
= fragp
->fr_line
;
14057 md_number_to_chars ((char*)buf
, insn
, 4);
14061 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14066 md_number_to_chars ((char*)buf
, insn
, 4);
14071 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14072 + fragp
->fr_fix
+ fragp
->fr_var
);
14074 fragp
->fr_fix
+= fragp
->fr_var
;
14079 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14082 register const struct mips16_immed_operand
*op
;
14083 bfd_boolean small
, ext
;
14086 unsigned long insn
;
14087 bfd_boolean use_extend
;
14088 unsigned short extend
;
14090 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14091 op
= mips16_immed_operands
;
14092 while (op
->type
!= type
)
14095 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14106 resolve_symbol_value (fragp
->fr_symbol
);
14107 val
= S_GET_VALUE (fragp
->fr_symbol
);
14112 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14114 /* The rules for the base address of a PC relative reloc are
14115 complicated; see mips16_extended_frag. */
14116 if (type
== 'p' || type
== 'q')
14121 /* Ignore the low bit in the target, since it will be
14122 set for a text label. */
14123 if ((val
& 1) != 0)
14126 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14128 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14131 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14134 /* Make sure the section winds up with the alignment we have
14137 record_alignment (asec
, op
->shift
);
14141 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14142 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14143 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14144 _("extended instruction in delay slot"));
14146 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14148 if (target_big_endian
)
14149 insn
= bfd_getb16 (buf
);
14151 insn
= bfd_getl16 (buf
);
14153 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14154 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14155 small
, ext
, &insn
, &use_extend
, &extend
);
14159 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14160 fragp
->fr_fix
+= 2;
14164 md_number_to_chars ((char *) buf
, insn
, 2);
14165 fragp
->fr_fix
+= 2;
14170 if (fragp
->fr_opcode
== NULL
)
14173 old
= RELAX_OLD (fragp
->fr_subtype
);
14174 new = RELAX_NEW (fragp
->fr_subtype
);
14175 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
14178 memmove (fixptr
- old
, fixptr
, new);
14180 fragp
->fr_fix
+= new - old
;
14186 /* This function is called after the relocs have been generated.
14187 We've been storing mips16 text labels as odd. Here we convert them
14188 back to even for the convenience of the debugger. */
14191 mips_frob_file_after_relocs ()
14194 unsigned int count
, i
;
14196 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
14199 syms
= bfd_get_outsymbols (stdoutput
);
14200 count
= bfd_get_symcount (stdoutput
);
14201 for (i
= 0; i
< count
; i
++, syms
++)
14203 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14204 && ((*syms
)->value
& 1) != 0)
14206 (*syms
)->value
&= ~1;
14207 /* If the symbol has an odd size, it was probably computed
14208 incorrectly, so adjust that as well. */
14209 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14210 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14217 /* This function is called whenever a label is defined. It is used
14218 when handling branch delays; if a branch has a label, we assume we
14219 can not move it. */
14222 mips_define_label (sym
)
14225 struct insn_label_list
*l
;
14227 if (free_insn_labels
== NULL
)
14228 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14231 l
= free_insn_labels
;
14232 free_insn_labels
= l
->next
;
14236 l
->next
= insn_labels
;
14240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14242 /* Some special processing for a MIPS ELF file. */
14245 mips_elf_final_processing ()
14247 /* Write out the register information. */
14248 if (mips_abi
!= N64_ABI
)
14252 s
.ri_gprmask
= mips_gprmask
;
14253 s
.ri_cprmask
[0] = mips_cprmask
[0];
14254 s
.ri_cprmask
[1] = mips_cprmask
[1];
14255 s
.ri_cprmask
[2] = mips_cprmask
[2];
14256 s
.ri_cprmask
[3] = mips_cprmask
[3];
14257 /* The gp_value field is set by the MIPS ELF backend. */
14259 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14260 ((Elf32_External_RegInfo
*)
14261 mips_regmask_frag
));
14265 Elf64_Internal_RegInfo s
;
14267 s
.ri_gprmask
= mips_gprmask
;
14269 s
.ri_cprmask
[0] = mips_cprmask
[0];
14270 s
.ri_cprmask
[1] = mips_cprmask
[1];
14271 s
.ri_cprmask
[2] = mips_cprmask
[2];
14272 s
.ri_cprmask
[3] = mips_cprmask
[3];
14273 /* The gp_value field is set by the MIPS ELF backend. */
14275 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14276 ((Elf64_External_RegInfo
*)
14277 mips_regmask_frag
));
14280 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14281 sort of BFD interface for this. */
14282 if (mips_any_noreorder
)
14283 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14284 if (mips_pic
!= NO_PIC
)
14286 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14287 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14290 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14292 /* Set MIPS ELF flags for ASEs. */
14293 if (file_ase_mips16
)
14294 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14295 #if 0 /* XXX FIXME */
14296 if (file_ase_mips3d
)
14297 elf_elfheader (stdoutput
)->e_flags
|= ???;
14300 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14302 /* Set the MIPS ELF ABI flags. */
14303 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14304 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14305 else if (mips_abi
== O64_ABI
)
14306 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14307 else if (mips_abi
== EABI_ABI
)
14309 if (!file_mips_gp32
)
14310 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14312 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14314 else if (mips_abi
== N32_ABI
)
14315 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14317 /* Nothing to do for N64_ABI. */
14319 if (mips_32bitmode
)
14320 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14323 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14325 typedef struct proc
{
14327 unsigned long reg_mask
;
14328 unsigned long reg_offset
;
14329 unsigned long fpreg_mask
;
14330 unsigned long fpreg_offset
;
14331 unsigned long frame_offset
;
14332 unsigned long frame_reg
;
14333 unsigned long pc_reg
;
14336 static procS cur_proc
;
14337 static procS
*cur_proc_ptr
;
14338 static int numprocs
;
14340 /* Fill in an rs_align_code fragment. */
14343 mips_handle_align (fragp
)
14346 if (fragp
->fr_type
!= rs_align_code
)
14349 if (mips_opts
.mips16
)
14351 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14352 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14357 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14358 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14366 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14370 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14381 /* check for premature end, nesting errors, etc */
14383 as_warn (_("missing .end at end of assembly"));
14392 if (*input_line_pointer
== '-')
14394 ++input_line_pointer
;
14397 if (!ISDIGIT (*input_line_pointer
))
14398 as_bad (_("expected simple number"));
14399 if (input_line_pointer
[0] == '0')
14401 if (input_line_pointer
[1] == 'x')
14403 input_line_pointer
+= 2;
14404 while (ISXDIGIT (*input_line_pointer
))
14407 val
|= hex_value (*input_line_pointer
++);
14409 return negative
? -val
: val
;
14413 ++input_line_pointer
;
14414 while (ISDIGIT (*input_line_pointer
))
14417 val
|= *input_line_pointer
++ - '0';
14419 return negative
? -val
: val
;
14422 if (!ISDIGIT (*input_line_pointer
))
14424 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14425 *input_line_pointer
, *input_line_pointer
);
14426 as_warn (_("invalid number"));
14429 while (ISDIGIT (*input_line_pointer
))
14432 val
+= *input_line_pointer
++ - '0';
14434 return negative
? -val
: val
;
14437 /* The .file directive; just like the usual .file directive, but there
14438 is an initial number which is the ECOFF file index. In the non-ECOFF
14439 case .file implies DWARF-2. */
14443 int x ATTRIBUTE_UNUSED
;
14445 static int first_file_directive
= 0;
14447 if (ECOFF_DEBUGGING
)
14456 filename
= dwarf2_directive_file (0);
14458 /* Versions of GCC up to 3.1 start files with a ".file"
14459 directive even for stabs output. Make sure that this
14460 ".file" is handled. Note that you need a version of GCC
14461 after 3.1 in order to support DWARF-2 on MIPS. */
14462 if (filename
!= NULL
&& ! first_file_directive
)
14464 (void) new_logical_line (filename
, -1);
14465 s_app_file_string (filename
);
14467 first_file_directive
= 1;
14471 /* The .loc directive, implying DWARF-2. */
14475 int x ATTRIBUTE_UNUSED
;
14477 if (!ECOFF_DEBUGGING
)
14478 dwarf2_directive_loc (0);
14481 /* The .end directive. */
14485 int x ATTRIBUTE_UNUSED
;
14489 /* Following functions need their own .frame and .cprestore directives. */
14490 mips_frame_reg_valid
= 0;
14491 mips_cprestore_valid
= 0;
14493 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14496 demand_empty_rest_of_line ();
14501 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14502 as_warn (_(".end not in text section"));
14506 as_warn (_(".end directive without a preceding .ent directive."));
14507 demand_empty_rest_of_line ();
14513 assert (S_GET_NAME (p
));
14514 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14515 as_warn (_(".end symbol does not match .ent symbol."));
14517 if (debug_type
== DEBUG_STABS
)
14518 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14522 as_warn (_(".end directive missing or unknown symbol"));
14525 /* Generate a .pdr section. */
14526 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14528 segT saved_seg
= now_seg
;
14529 subsegT saved_subseg
= now_subseg
;
14534 dot
= frag_now_fix ();
14536 #ifdef md_flush_pending_output
14537 md_flush_pending_output ();
14541 subseg_set (pdr_seg
, 0);
14543 /* Write the symbol. */
14544 exp
.X_op
= O_symbol
;
14545 exp
.X_add_symbol
= p
;
14546 exp
.X_add_number
= 0;
14547 emit_expr (&exp
, 4);
14549 fragp
= frag_more (7 * 4);
14551 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14552 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14553 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14554 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14555 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14556 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14557 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14559 subseg_set (saved_seg
, saved_subseg
);
14561 #endif /* OBJ_ELF */
14563 cur_proc_ptr
= NULL
;
14566 /* The .aent and .ent directives. */
14574 symbolP
= get_symbol ();
14575 if (*input_line_pointer
== ',')
14576 ++input_line_pointer
;
14577 SKIP_WHITESPACE ();
14578 if (ISDIGIT (*input_line_pointer
)
14579 || *input_line_pointer
== '-')
14582 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14583 as_warn (_(".ent or .aent not in text section."));
14585 if (!aent
&& cur_proc_ptr
)
14586 as_warn (_("missing .end"));
14590 /* This function needs its own .frame and .cprestore directives. */
14591 mips_frame_reg_valid
= 0;
14592 mips_cprestore_valid
= 0;
14594 cur_proc_ptr
= &cur_proc
;
14595 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14597 cur_proc_ptr
->isym
= symbolP
;
14599 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14603 if (debug_type
== DEBUG_STABS
)
14604 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14605 S_GET_NAME (symbolP
));
14608 demand_empty_rest_of_line ();
14611 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14612 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14613 s_mips_frame is used so that we can set the PDR information correctly.
14614 We can't use the ecoff routines because they make reference to the ecoff
14615 symbol table (in the mdebug section). */
14618 s_mips_frame (ignore
)
14619 int ignore ATTRIBUTE_UNUSED
;
14622 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14626 if (cur_proc_ptr
== (procS
*) NULL
)
14628 as_warn (_(".frame outside of .ent"));
14629 demand_empty_rest_of_line ();
14633 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14635 SKIP_WHITESPACE ();
14636 if (*input_line_pointer
++ != ','
14637 || get_absolute_expression_and_terminator (&val
) != ',')
14639 as_warn (_("Bad .frame directive"));
14640 --input_line_pointer
;
14641 demand_empty_rest_of_line ();
14645 cur_proc_ptr
->frame_offset
= val
;
14646 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14648 demand_empty_rest_of_line ();
14651 #endif /* OBJ_ELF */
14655 /* The .fmask and .mask directives. If the mdebug section is present
14656 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14657 embedded targets, s_mips_mask is used so that we can set the PDR
14658 information correctly. We can't use the ecoff routines because they
14659 make reference to the ecoff symbol table (in the mdebug section). */
14662 s_mips_mask (reg_type
)
14666 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14670 if (cur_proc_ptr
== (procS
*) NULL
)
14672 as_warn (_(".mask/.fmask outside of .ent"));
14673 demand_empty_rest_of_line ();
14677 if (get_absolute_expression_and_terminator (&mask
) != ',')
14679 as_warn (_("Bad .mask/.fmask directive"));
14680 --input_line_pointer
;
14681 demand_empty_rest_of_line ();
14685 off
= get_absolute_expression ();
14687 if (reg_type
== 'F')
14689 cur_proc_ptr
->fpreg_mask
= mask
;
14690 cur_proc_ptr
->fpreg_offset
= off
;
14694 cur_proc_ptr
->reg_mask
= mask
;
14695 cur_proc_ptr
->reg_offset
= off
;
14698 demand_empty_rest_of_line ();
14701 #endif /* OBJ_ELF */
14702 s_ignore (reg_type
);
14705 /* The .loc directive. */
14716 assert (now_seg
== text_section
);
14718 lineno
= get_number ();
14719 addroff
= frag_now_fix ();
14721 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14722 S_SET_TYPE (symbolP
, N_SLINE
);
14723 S_SET_OTHER (symbolP
, 0);
14724 S_SET_DESC (symbolP
, lineno
);
14725 symbolP
->sy_segment
= now_seg
;
14729 /* A table describing all the processors gas knows about. Names are
14730 matched in the order listed.
14732 To ease comparison, please keep this table in the same order as
14733 gcc's mips_cpu_info_table[]. */
14734 static const struct mips_cpu_info mips_cpu_info_table
[] =
14736 /* Entries for generic ISAs */
14737 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14738 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14739 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14740 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14741 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14742 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14743 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14744 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14747 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14748 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14749 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14752 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14755 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14756 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14757 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14758 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14759 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14760 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14761 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14762 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14763 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14764 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14765 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14766 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14769 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14770 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14771 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14772 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14773 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14774 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14775 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14776 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14777 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14778 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14779 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14780 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14783 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14784 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14785 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14788 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14789 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14791 /* Broadcom SB-1 CPU core */
14792 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14799 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14800 with a final "000" replaced by "k". Ignore case.
14802 Note: this function is shared between GCC and GAS. */
14805 mips_strict_matching_cpu_name_p (canonical
, given
)
14806 const char *canonical
, *given
;
14808 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14809 given
++, canonical
++;
14811 return ((*given
== 0 && *canonical
== 0)
14812 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14816 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14817 CPU name. We've traditionally allowed a lot of variation here.
14819 Note: this function is shared between GCC and GAS. */
14822 mips_matching_cpu_name_p (canonical
, given
)
14823 const char *canonical
, *given
;
14825 /* First see if the name matches exactly, or with a final "000"
14826 turned into "k". */
14827 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14830 /* If not, try comparing based on numerical designation alone.
14831 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14832 if (TOLOWER (*given
) == 'r')
14834 if (!ISDIGIT (*given
))
14837 /* Skip over some well-known prefixes in the canonical name,
14838 hoping to find a number there too. */
14839 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14841 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14843 else if (TOLOWER (canonical
[0]) == 'r')
14846 return mips_strict_matching_cpu_name_p (canonical
, given
);
14850 /* Parse an option that takes the name of a processor as its argument.
14851 OPTION is the name of the option and CPU_STRING is the argument.
14852 Return the corresponding processor enumeration if the CPU_STRING is
14853 recognized, otherwise report an error and return null.
14855 A similar function exists in GCC. */
14857 static const struct mips_cpu_info
*
14858 mips_parse_cpu (option
, cpu_string
)
14859 const char *option
, *cpu_string
;
14861 const struct mips_cpu_info
*p
;
14863 /* 'from-abi' selects the most compatible architecture for the given
14864 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14865 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14866 version. Look first at the -mgp options, if given, otherwise base
14867 the choice on MIPS_DEFAULT_64BIT.
14869 Treat NO_ABI like the EABIs. One reason to do this is that the
14870 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14871 architecture. This code picks MIPS I for 'mips' and MIPS III for
14872 'mips64', just as we did in the days before 'from-abi'. */
14873 if (strcasecmp (cpu_string
, "from-abi") == 0)
14875 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14876 return mips_cpu_info_from_isa (ISA_MIPS1
);
14878 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14879 return mips_cpu_info_from_isa (ISA_MIPS3
);
14881 if (file_mips_gp32
>= 0)
14882 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14884 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14889 /* 'default' has traditionally been a no-op. Probably not very useful. */
14890 if (strcasecmp (cpu_string
, "default") == 0)
14893 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14894 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14897 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14901 /* Return the canonical processor information for ISA (a member of the
14902 ISA_MIPS* enumeration). */
14904 static const struct mips_cpu_info
*
14905 mips_cpu_info_from_isa (isa
)
14910 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14911 if (mips_cpu_info_table
[i
].is_isa
14912 && isa
== mips_cpu_info_table
[i
].isa
)
14913 return (&mips_cpu_info_table
[i
]);
14918 static const struct mips_cpu_info
*
14919 mips_cpu_info_from_arch (arch
)
14924 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14925 if (arch
== mips_cpu_info_table
[i
].cpu
)
14926 return (&mips_cpu_info_table
[i
]);
14932 show (stream
, string
, col_p
, first_p
)
14934 const char *string
;
14940 fprintf (stream
, "%24s", "");
14945 fprintf (stream
, ", ");
14949 if (*col_p
+ strlen (string
) > 72)
14951 fprintf (stream
, "\n%24s", "");
14955 fprintf (stream
, "%s", string
);
14956 *col_p
+= strlen (string
);
14962 md_show_usage (stream
)
14968 fprintf (stream
, _("\
14970 -membedded-pic generate embedded position independent code\n\
14971 -EB generate big endian output\n\
14972 -EL generate little endian output\n\
14973 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14974 -G NUM allow referencing objects up to NUM bytes\n\
14975 implicitly with the gp register [default 8]\n"));
14976 fprintf (stream
, _("\
14977 -mips1 generate MIPS ISA I instructions\n\
14978 -mips2 generate MIPS ISA II instructions\n\
14979 -mips3 generate MIPS ISA III instructions\n\
14980 -mips4 generate MIPS ISA IV instructions\n\
14981 -mips5 generate MIPS ISA V instructions\n\
14982 -mips32 generate MIPS32 ISA instructions\n\
14983 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14984 -mips64 generate MIPS64 ISA instructions\n\
14985 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14989 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14990 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14991 show (stream
, "from-abi", &column
, &first
);
14992 fputc ('\n', stream
);
14994 fprintf (stream
, _("\
14995 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14996 -no-mCPU don't generate code specific to CPU.\n\
14997 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15001 show (stream
, "3900", &column
, &first
);
15002 show (stream
, "4010", &column
, &first
);
15003 show (stream
, "4100", &column
, &first
);
15004 show (stream
, "4650", &column
, &first
);
15005 fputc ('\n', stream
);
15007 fprintf (stream
, _("\
15008 -mips16 generate mips16 instructions\n\
15009 -no-mips16 do not generate mips16 instructions\n"));
15010 fprintf (stream
, _("\
15011 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15012 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15013 -O0 remove unneeded NOPs, do not swap branches\n\
15014 -O remove unneeded NOPs and swap branches\n\
15015 -n warn about NOPs generated from macros\n\
15016 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15017 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15018 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15020 fprintf (stream
, _("\
15021 -KPIC, -call_shared generate SVR4 position independent code\n\
15022 -non_shared do not generate position independent code\n\
15023 -xgot assume a 32 bit GOT\n\
15024 -mabi=ABI create ABI conformant object file for:\n"));
15028 show (stream
, "32", &column
, &first
);
15029 show (stream
, "o64", &column
, &first
);
15030 show (stream
, "n32", &column
, &first
);
15031 show (stream
, "64", &column
, &first
);
15032 show (stream
, "eabi", &column
, &first
);
15034 fputc ('\n', stream
);
15036 fprintf (stream
, _("\
15037 -32 create o32 ABI object file (default)\n\
15038 -n32 create n32 ABI object file\n\
15039 -64 create 64 ABI object file\n"));
15044 mips_dwarf2_format ()
15046 if (mips_abi
== N64_ABI
)
15049 return dwarf2_format_64bit_irix
;
15051 return dwarf2_format_64bit
;
15055 return dwarf2_format_32bit
;