1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r8000") == 0
665 || strcmp (cpu
, "mips4") == 0)
671 else if (strcmp (cpu
, "r10000") == 0)
697 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
702 if (mips_cpu
== 4300)
707 if (mips_isa
< 2 && mips_trap
)
708 as_bad ("trap exception not supported at ISA 1");
713 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
716 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
719 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
722 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
726 as_warn ("Could not set architecture and machine");
728 file_mips_isa
= mips_isa
;
730 op_hash
= hash_new ();
732 for (i
= 0; i
< NUMOPCODES
;)
734 const char *name
= mips_opcodes
[i
].name
;
736 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
739 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
740 mips_opcodes
[i
].name
, retval
);
741 as_fatal ("Broken assembler. No assembly attempted.");
745 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
746 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
747 != mips_opcodes
[i
].match
))
749 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
750 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
751 as_fatal ("Broken assembler. No assembly attempted.");
755 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
758 mips_no_prev_insn ();
766 /* set the default alignment for the text section (2**2) */
767 record_alignment (text_section
, 2);
769 if (USE_GLOBAL_POINTER_OPT
)
770 bfd_set_gp_size (stdoutput
, g_switch_value
);
772 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
774 /* Sections must be aligned to 16 byte boundaries. */
775 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
776 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
777 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
779 /* Create a .reginfo section for register masks and a .mdebug
780 section for debugging information. */
791 sec
= subseg_new (".reginfo", (subsegT
) 0);
793 /* The ABI says this section should be loaded so that the
794 running program can access it. */
795 (void) bfd_set_section_flags (stdoutput
, sec
,
796 (SEC_ALLOC
| SEC_LOAD
797 | SEC_READONLY
| SEC_DATA
));
798 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
801 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
806 /* The 64-bit ABI uses a .MIPS.options section rather than
808 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
809 (void) bfd_set_section_flags (stdoutput
, sec
,
810 (SEC_ALLOC
| SEC_LOAD
811 | SEC_READONLY
| SEC_DATA
));
812 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
815 /* Set up the option header. */
817 Elf_Internal_Options opthdr
;
820 opthdr
.kind
= ODK_REGINFO
;
821 opthdr
.size
= (sizeof (Elf_External_Options
)
822 + sizeof (Elf64_External_RegInfo
));
825 f
= frag_more (sizeof (Elf_External_Options
));
826 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
827 (Elf_External_Options
*) f
);
829 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
836 sec
= subseg_new (".mdebug", (subsegT
) 0);
837 (void) bfd_set_section_flags (stdoutput
, sec
,
838 SEC_HAS_CONTENTS
| SEC_READONLY
);
839 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
842 subseg_set (seg
, subseg
);
846 if (! ECOFF_DEBUGGING
)
853 if (! ECOFF_DEBUGGING
)
861 struct mips_cl_insn insn
;
863 imm_expr
.X_op
= O_absent
;
864 imm_reloc
= BFD_RELOC_UNUSED
;
865 imm_unmatched_hi
= false;
866 offset_expr
.X_op
= O_absent
;
867 offset_reloc
= BFD_RELOC_UNUSED
;
869 mips_ip (str
, &insn
);
872 as_bad ("%s `%s'", insn_error
, str
);
875 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
881 if (imm_expr
.X_op
!= O_absent
)
882 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
884 else if (offset_expr
.X_op
!= O_absent
)
885 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
887 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
891 /* See whether instruction IP reads register REG. If FPR is non-zero,
892 REG is a floating point register. */
895 insn_uses_reg (ip
, reg
, fpr
)
896 struct mips_cl_insn
*ip
;
900 /* Don't report on general register 0, since it never changes. */
901 if (! fpr
&& reg
== 0)
906 /* If we are called with either $f0 or $f1, we must check $f0.
907 This is not optimal, because it will introduce an unnecessary
908 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
909 need to distinguish reading both $f0 and $f1 or just one of
910 them. Note that we don't have to check the other way,
911 because there is no instruction that sets both $f0 and $f1
912 and requires a delay. */
913 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
914 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
915 == (reg
&~ (unsigned) 1)))
917 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
918 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
919 == (reg
&~ (unsigned) 1)))
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
925 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
927 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
928 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
935 /* This function returns true if modifying a register requires a
939 reg_needs_delay (reg
)
942 unsigned long prev_pinfo
;
944 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
947 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
949 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
951 /* A load from a coprocessor or from memory. All load
952 delays delay the use of general register rt for one
953 instruction on the r3000. The r6000 and r4000 use
955 know (prev_pinfo
& INSN_WRITE_GPR_T
);
956 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
963 /* Output an instruction. PLACE is where to put the instruction; if
964 it is NULL, this uses frag_more to get room. IP is the instruction
965 information. ADDRESS_EXPR is an operand of the instruction to be
966 used with RELOC_TYPE. */
969 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
971 struct mips_cl_insn
*ip
;
972 expressionS
*address_expr
;
973 bfd_reloc_code_real_type reloc_type
;
974 boolean unmatched_hi
;
976 register unsigned long prev_pinfo
, pinfo
;
981 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
982 pinfo
= ip
->insn_mo
->pinfo
;
984 if (place
== NULL
&& ! mips_noreorder
)
986 /* If the previous insn required any delay slots, see if we need
987 to insert a NOP or two. There are eight kinds of possible
988 hazards, of which an instruction can have at most one type.
989 (1) a load from memory delay
990 (2) a load from a coprocessor delay
991 (3) an unconditional branch delay
992 (4) a conditional branch delay
993 (5) a move to coprocessor register delay
994 (6) a load coprocessor register from memory delay
995 (7) a coprocessor condition code delay
996 (8) a HI/LO special register delay
998 There are a lot of optimizations we could do that we don't.
999 In particular, we do not, in general, reorder instructions.
1000 If you use gcc with optimization, it will reorder
1001 instructions and generally do much more optimization then we
1002 do here; repeating all that work in the assembler would only
1003 benefit hand written assembly code, and does not seem worth
1006 /* This is how a NOP is emitted. */
1007 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1009 /* The previous insn might require a delay slot, depending upon
1010 the contents of the current insn. */
1012 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1013 && ! cop_interlocks
)
1015 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1017 /* A load from a coprocessor or from memory. All load
1018 delays delay the use of general register rt for one
1019 instruction on the r3000. The r6000 and r4000 use
1021 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1022 if (mips_optimize
== 0
1023 || insn_uses_reg (ip
,
1024 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1029 else if (mips_isa
< 4
1030 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1031 && ! cop_interlocks
)
1033 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1035 /* A generic coprocessor delay. The previous instruction
1036 modified a coprocessor general or control register. If
1037 it modified a control register, we need to avoid any
1038 coprocessor instruction (this is probably not always
1039 required, but it sometimes is). If it modified a general
1040 register, we avoid using that register.
1042 On the r6000 and r4000 loading a coprocessor register
1043 from memory is interlocked, and does not require a delay.
1045 This case is not handled very well. There is no special
1046 knowledge of CP0 handling, and the coprocessors other
1047 than the floating point unit are not distinguished at
1049 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1051 if (mips_optimize
== 0
1052 || insn_uses_reg (ip
,
1053 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1058 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1060 if (mips_optimize
== 0
1061 || insn_uses_reg (ip
,
1062 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1069 /* We don't know exactly what the previous instruction
1070 does. If the current instruction uses a coprocessor
1071 register, we must insert a NOP. If previous
1072 instruction may set the condition codes, and the
1073 current instruction uses them, we must insert two
1075 if (mips_optimize
== 0
1076 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1077 && (pinfo
& INSN_READ_COND_CODE
)))
1079 else if (pinfo
& INSN_COP
)
1083 else if (mips_isa
< 4
1084 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1085 && ! cop_interlocks
)
1087 /* The previous instruction sets the coprocessor condition
1088 codes, but does not require a general coprocessor delay
1089 (this means it is a floating point comparison
1090 instruction). If this instruction uses the condition
1091 codes, we need to insert a single NOP. */
1092 if (mips_optimize
== 0
1093 || (pinfo
& INSN_READ_COND_CODE
))
1096 else if (prev_pinfo
& INSN_READ_LO
)
1098 /* The previous instruction reads the LO register; if the
1099 current instruction writes to the LO register, we must
1100 insert two NOPS. The R4650, VR4100 and VR4300 have
1103 && (mips_optimize
== 0
1104 || (pinfo
& INSN_WRITE_LO
)))
1107 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1109 /* The previous instruction reads the HI register; if the
1110 current instruction writes to the HI register, we must
1111 insert a NOP. The R4650, VR4100 and VR4300 have
1114 && (mips_optimize
== 0
1115 || (pinfo
& INSN_WRITE_HI
)))
1119 /* There are two cases which require two intervening
1120 instructions: 1) setting the condition codes using a move to
1121 coprocessor instruction which requires a general coprocessor
1122 delay and then reading the condition codes 2) reading the HI
1123 or LO register and then writing to it (except on the R4650,
1124 VR4100, and VR4300 which have interlocks). If we are not
1125 already emitting a NOP instruction, we must check for these
1126 cases compared to the instruction previous to the previous
1130 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1131 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1132 && (pinfo
& INSN_READ_COND_CODE
)
1133 && ! cop_interlocks
)
1134 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1135 && (pinfo
& INSN_WRITE_LO
)
1137 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1138 && (pinfo
& INSN_WRITE_HI
)
1142 /* If we are being given a nop instruction, don't bother with
1143 one of the nops we would otherwise output. This will only
1144 happen when a nop instruction is used with mips_optimize set
1146 if (nops
> 0 && ip
->insn_opcode
== 0)
1149 /* Now emit the right number of NOP instructions. */
1153 unsigned long old_frag_offset
;
1156 old_frag
= frag_now
;
1157 old_frag_offset
= frag_now_fix ();
1159 for (i
= 0; i
< nops
; i
++)
1164 listing_prev_line ();
1165 /* We may be at the start of a variant frag. In case we
1166 are, make sure there is enough space for the frag
1167 after the frags created by listing_prev_line. The
1168 argument to frag_grow here must be at least as large
1169 as the argument to all other calls to frag_grow in
1170 this file. We don't have to worry about being in the
1171 middle of a variant frag, because the variants insert
1172 all needed nop instructions themselves. */
1176 if (insn_label
!= NULL
)
1178 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1179 insn_label
->sy_frag
= frag_now
;
1180 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1183 #ifndef NO_ECOFF_DEBUGGING
1184 if (ECOFF_DEBUGGING
)
1185 ecoff_fix_loc (old_frag
, old_frag_offset
);
1195 if (address_expr
!= NULL
)
1197 if (address_expr
->X_op
== O_constant
)
1202 ip
->insn_opcode
|= address_expr
->X_add_number
;
1205 case BFD_RELOC_LO16
:
1206 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1209 case BFD_RELOC_MIPS_JMP
:
1210 case BFD_RELOC_16_PCREL_S2
:
1219 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1221 /* Don't generate a reloc if we are writing into a variant
1225 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1227 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1231 struct mips_hi_fixup
*hi_fixup
;
1233 assert (reloc_type
== BFD_RELOC_HI16_S
);
1234 hi_fixup
= ((struct mips_hi_fixup
*)
1235 xmalloc (sizeof (struct mips_hi_fixup
)));
1236 hi_fixup
->fixp
= fixp
;
1237 hi_fixup
->seg
= now_seg
;
1238 hi_fixup
->next
= mips_hi_fixup_list
;
1239 mips_hi_fixup_list
= hi_fixup
;
1245 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1247 /* Update the register mask information. */
1248 if (pinfo
& INSN_WRITE_GPR_D
)
1249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1250 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1251 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1252 if (pinfo
& INSN_READ_GPR_S
)
1253 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1254 if (pinfo
& INSN_WRITE_GPR_31
)
1255 mips_gprmask
|= 1 << 31;
1256 if (pinfo
& INSN_WRITE_FPR_D
)
1257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1258 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1260 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1262 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1264 if (pinfo
& INSN_COP
)
1266 /* We don't keep enough information to sort these cases out. */
1268 /* Never set the bit for $0, which is always zero. */
1269 mips_gprmask
&=~ 1 << 0;
1271 if (place
== NULL
&& ! mips_noreorder
)
1273 /* Filling the branch delay slot is more complex. We try to
1274 switch the branch with the previous instruction, which we can
1275 do if the previous instruction does not set up a condition
1276 that the branch tests and if the branch is not itself the
1277 target of any branch. */
1278 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1279 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1281 if (mips_optimize
< 2
1282 /* If we have seen .set volatile or .set nomove, don't
1285 /* If we had to emit any NOP instructions, then we
1286 already know we can not swap. */
1288 /* If we don't even know the previous insn, we can not
1290 || ! prev_insn_valid
1291 /* If the previous insn is already in a branch delay
1292 slot, then we can not swap. */
1293 || prev_insn_is_delay_slot
1294 /* If the previous previous insn was in a .set
1295 noreorder, we can't swap. Actually, the MIPS
1296 assembler will swap in this situation. However, gcc
1297 configured -with-gnu-as will generate code like
1303 in which we can not swap the bne and INSN. If gcc is
1304 not configured -with-gnu-as, it does not output the
1305 .set pseudo-ops. We don't have to check
1306 prev_insn_unreordered, because prev_insn_valid will
1307 be 0 in that case. We don't want to use
1308 prev_prev_insn_valid, because we do want to be able
1309 to swap at the start of a function. */
1310 || prev_prev_insn_unreordered
1311 /* If the branch is itself the target of a branch, we
1312 can not swap. We cheat on this; all we check for is
1313 whether there is a label on this instruction. If
1314 there are any branches to anything other than a
1315 label, users must use .set noreorder. */
1316 || insn_label
!= NULL
1317 /* If the previous instruction is in a variant frag, we
1318 can not do the swap. */
1319 || prev_insn_frag
->fr_type
== rs_machine_dependent
1320 /* If the branch reads the condition codes, we don't
1321 even try to swap, because in the sequence
1326 we can not swap, and I don't feel like handling that
1329 && (pinfo
& INSN_READ_COND_CODE
))
1330 /* We can not swap with an instruction that requires a
1331 delay slot, becase the target of the branch might
1332 interfere with that instruction. */
1335 & (INSN_LOAD_COPROC_DELAY
1336 | INSN_COPROC_MOVE_DELAY
1337 | INSN_WRITE_COND_CODE
)))
1344 & (INSN_LOAD_MEMORY_DELAY
1345 | INSN_COPROC_MEMORY_DELAY
)))
1346 /* We can not swap with a branch instruction. */
1348 & (INSN_UNCOND_BRANCH_DELAY
1349 | INSN_COND_BRANCH_DELAY
1350 | INSN_COND_BRANCH_LIKELY
))
1351 /* We do not swap with a trap instruction, since it
1352 complicates trap handlers to have the trap
1353 instruction be in a delay slot. */
1354 || (prev_pinfo
& INSN_TRAP
)
1355 /* If the branch reads a register that the previous
1356 instruction sets, we can not swap. */
1357 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1358 && insn_uses_reg (ip
,
1359 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1362 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1363 && insn_uses_reg (ip
,
1364 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1367 /* If the branch writes a register that the previous
1368 instruction sets, we can not swap (we know that
1369 branches write only to RD or to $31). */
1370 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1371 && (((pinfo
& INSN_WRITE_GPR_D
)
1372 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1373 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1374 || ((pinfo
& INSN_WRITE_GPR_31
)
1375 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1378 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1379 && (((pinfo
& INSN_WRITE_GPR_D
)
1380 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1381 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1382 || ((pinfo
& INSN_WRITE_GPR_31
)
1383 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1386 /* If the branch writes a register that the previous
1387 instruction reads, we can not swap (we know that
1388 branches only write to RD or to $31). */
1389 || ((pinfo
& INSN_WRITE_GPR_D
)
1390 && insn_uses_reg (&prev_insn
,
1391 ((ip
->insn_opcode
>> OP_SH_RD
)
1394 || ((pinfo
& INSN_WRITE_GPR_31
)
1395 && insn_uses_reg (&prev_insn
, 31, 0))
1396 /* If we are generating embedded PIC code, the branch
1397 might be expanded into a sequence which uses $at, so
1398 we can't swap with an instruction which reads it. */
1399 || (mips_pic
== EMBEDDED_PIC
1400 && insn_uses_reg (&prev_insn
, AT
, 0))
1401 /* If the previous previous instruction has a load
1402 delay, and sets a register that the branch reads, we
1405 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1407 && (prev_prev_insn
.insn_mo
->pinfo
1408 & INSN_LOAD_MEMORY_DELAY
)))
1409 && insn_uses_reg (ip
,
1410 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1414 /* We could do even better for unconditional branches to
1415 portions of this object file; we could pick up the
1416 instruction at the destination, put it in the delay
1417 slot, and bump the destination address. */
1419 /* Update the previous insn information. */
1420 prev_prev_insn
= *ip
;
1421 prev_insn
.insn_mo
= &dummy_opcode
;
1428 /* It looks like we can actually do the swap. */
1429 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1430 memcpy (temp
, prev_f
, 4);
1431 memcpy (prev_f
, f
, 4);
1432 memcpy (f
, temp
, 4);
1435 prev_insn_fixp
->fx_frag
= frag_now
;
1436 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1440 fixp
->fx_frag
= prev_insn_frag
;
1441 fixp
->fx_where
= prev_insn_where
;
1443 /* Update the previous insn information; leave prev_insn
1445 prev_prev_insn
= *ip
;
1447 prev_insn_is_delay_slot
= 1;
1449 /* If that was an unconditional branch, forget the previous
1450 insn information. */
1451 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1453 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1454 prev_insn
.insn_mo
= &dummy_opcode
;
1457 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1459 /* We don't yet optimize a branch likely. What we should do
1460 is look at the target, copy the instruction found there
1461 into the delay slot, and increment the branch to jump to
1462 the next instruction. */
1464 /* Update the previous insn information. */
1465 prev_prev_insn
= *ip
;
1466 prev_insn
.insn_mo
= &dummy_opcode
;
1470 /* Update the previous insn information. */
1472 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1474 prev_prev_insn
= prev_insn
;
1477 /* Any time we see a branch, we always fill the delay slot
1478 immediately; since this insn is not a branch, we know it
1479 is not in a delay slot. */
1480 prev_insn_is_delay_slot
= 0;
1483 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1484 prev_insn_unreordered
= 0;
1485 prev_insn_frag
= frag_now
;
1486 prev_insn_where
= f
- frag_now
->fr_literal
;
1487 prev_insn_fixp
= fixp
;
1488 prev_insn_valid
= 1;
1491 /* We just output an insn, so the next one doesn't have a label. */
1495 /* This function forgets that there was any previous instruction or
1499 mips_no_prev_insn ()
1501 prev_insn
.insn_mo
= &dummy_opcode
;
1502 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1503 prev_insn_valid
= 0;
1504 prev_insn_is_delay_slot
= 0;
1505 prev_insn_unreordered
= 0;
1506 prev_prev_insn_unreordered
= 0;
1510 /* This function must be called whenever we turn on noreorder or emit
1511 something other than instructions. It inserts any NOPS which might
1512 be needed by the previous instruction, and clears the information
1513 kept for the previous instructions. */
1518 if (! mips_noreorder
)
1524 && (! cop_interlocks
1525 && (prev_insn
.insn_mo
->pinfo
1526 & (INSN_LOAD_COPROC_DELAY
1527 | INSN_COPROC_MOVE_DELAY
1528 | INSN_WRITE_COND_CODE
))))
1530 && (prev_insn
.insn_mo
->pinfo
1534 && (prev_insn
.insn_mo
->pinfo
1535 & (INSN_LOAD_MEMORY_DELAY
1536 | INSN_COPROC_MEMORY_DELAY
))))
1540 && (! cop_interlocks
1541 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1543 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1544 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1547 else if ((mips_isa
< 4
1548 && (! cop_interlocks
1549 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1551 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1552 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1557 if (insn_label
!= NULL
)
1559 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1560 insn_label
->sy_frag
= frag_now
;
1561 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1566 mips_no_prev_insn ();
1569 /* Build an instruction created by a macro expansion. This is passed
1570 a pointer to the count of instructions created so far, an
1571 expression, the name of the instruction to build, an operand format
1572 string, and corresponding arguments. */
1576 macro_build (char *place
,
1584 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1593 struct mips_cl_insn insn
;
1594 bfd_reloc_code_real_type r
;
1598 va_start (args
, fmt
);
1604 * If the macro is about to expand into a second instruction,
1605 * print a warning if needed. We need to pass ip as a parameter
1606 * to generate a better warning message here...
1608 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1609 as_warn ("Macro instruction expanded into multiple instructions");
1612 *counter
+= 1; /* bump instruction counter */
1614 r
= BFD_RELOC_UNUSED
;
1615 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1616 assert (insn
.insn_mo
);
1617 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1619 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1620 || insn
.insn_mo
->pinfo
== INSN_MACRO
1621 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1623 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1625 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1627 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1629 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1631 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1635 assert (insn
.insn_mo
->name
);
1636 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1638 insn
.insn_opcode
= insn
.insn_mo
->match
;
1654 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1660 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1665 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1670 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1677 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1681 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1685 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1692 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1698 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1699 assert (r
== BFD_RELOC_MIPS_GPREL
1700 || r
== BFD_RELOC_MIPS_LITERAL
1701 || r
== BFD_RELOC_LO16
1702 || r
== BFD_RELOC_MIPS_GOT16
1703 || r
== BFD_RELOC_MIPS_CALL16
1704 || r
== BFD_RELOC_MIPS_GOT_LO16
1705 || r
== BFD_RELOC_MIPS_CALL_LO16
1706 || (ep
->X_op
== O_subtract
1707 && now_seg
== text_section
1708 && r
== BFD_RELOC_PCREL_LO16
));
1712 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1714 && (ep
->X_op
== O_constant
1715 || (ep
->X_op
== O_symbol
1716 && (r
== BFD_RELOC_HI16_S
1717 || r
== BFD_RELOC_HI16
1718 || r
== BFD_RELOC_MIPS_GOT_HI16
1719 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1720 || (ep
->X_op
== O_subtract
1721 && now_seg
== text_section
1722 && r
== BFD_RELOC_PCREL_HI16_S
)));
1723 if (ep
->X_op
== O_constant
)
1725 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1727 r
= BFD_RELOC_UNUSED
;
1732 assert (ep
!= NULL
);
1734 * This allows macro() to pass an immediate expression for
1735 * creating short branches without creating a symbol.
1736 * Note that the expression still might come from the assembly
1737 * input, in which case the value is not checked for range nor
1738 * is a relocation entry generated (yuck).
1740 if (ep
->X_op
== O_constant
)
1742 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1746 r
= BFD_RELOC_16_PCREL_S2
;
1750 assert (ep
!= NULL
);
1751 r
= BFD_RELOC_MIPS_JMP
;
1760 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1762 append_insn (place
, &insn
, ep
, r
, false);
1766 * Generate a "lui" instruction.
1769 macro_build_lui (place
, counter
, ep
, regnum
)
1775 expressionS high_expr
;
1776 struct mips_cl_insn insn
;
1777 bfd_reloc_code_real_type r
;
1778 CONST
char *name
= "lui";
1779 CONST
char *fmt
= "t,u";
1785 high_expr
.X_op
= O_constant
;
1786 high_expr
.X_add_number
= ep
->X_add_number
;
1789 if (high_expr
.X_op
== O_constant
)
1791 /* we can compute the instruction now without a relocation entry */
1792 if (high_expr
.X_add_number
& 0x8000)
1793 high_expr
.X_add_number
+= 0x10000;
1794 high_expr
.X_add_number
=
1795 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1796 r
= BFD_RELOC_UNUSED
;
1800 assert (ep
->X_op
== O_symbol
);
1801 /* _gp_disp is a special case, used from s_cpload. */
1802 assert (mips_pic
== NO_PIC
1803 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1804 r
= BFD_RELOC_HI16_S
;
1808 * If the macro is about to expand into a second instruction,
1809 * print a warning if needed. We need to pass ip as a parameter
1810 * to generate a better warning message here...
1812 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1813 as_warn ("Macro instruction expanded into multiple instructions");
1816 *counter
+= 1; /* bump instruction counter */
1818 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1819 assert (insn
.insn_mo
);
1820 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1821 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1823 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1824 if (r
== BFD_RELOC_UNUSED
)
1826 insn
.insn_opcode
|= high_expr
.X_add_number
;
1827 append_insn (place
, &insn
, NULL
, r
, false);
1830 append_insn (place
, &insn
, &high_expr
, r
, false);
1834 * Generates code to set the $at register to true (one)
1835 * if reg is less than the immediate expression.
1838 set_at (counter
, reg
, unsignedp
)
1843 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1844 macro_build ((char *) NULL
, counter
, &imm_expr
,
1845 unsignedp
? "sltiu" : "slti",
1846 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1849 load_register (counter
, AT
, &imm_expr
, 0);
1850 macro_build ((char *) NULL
, counter
, NULL
,
1851 unsignedp
? "sltu" : "slt",
1852 "d,v,t", AT
, reg
, AT
);
1856 /* Warn if an expression is not a constant. */
1859 check_absolute_expr (ip
, ex
)
1860 struct mips_cl_insn
*ip
;
1863 if (ex
->X_op
!= O_constant
)
1864 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1867 /* Count the leading zeroes by performing a binary chop. This is a
1868 bulky bit of source, but performance is a LOT better for the
1869 majority of values than a simple loop to count the bits:
1870 for (lcnt = 0; (lcnt < 32); lcnt++)
1871 if ((v) & (1 << (31 - lcnt)))
1873 However it is not code size friendly, and the gain will drop a bit
1874 on certain cached systems.
1876 #define COUNT_TOP_ZEROES(v) \
1877 (((v) & ~0xffff) == 0 \
1878 ? ((v) & ~0xff) == 0 \
1879 ? ((v) & ~0xf) == 0 \
1880 ? ((v) & ~0x3) == 0 \
1881 ? ((v) & ~0x1) == 0 \
1886 : ((v) & ~0x7) == 0 \
1889 : ((v) & ~0x3f) == 0 \
1890 ? ((v) & ~0x1f) == 0 \
1893 : ((v) & ~0x7f) == 0 \
1896 : ((v) & ~0xfff) == 0 \
1897 ? ((v) & ~0x3ff) == 0 \
1898 ? ((v) & ~0x1ff) == 0 \
1901 : ((v) & ~0x7ff) == 0 \
1904 : ((v) & ~0x3fff) == 0 \
1905 ? ((v) & ~0x1fff) == 0 \
1908 : ((v) & ~0x7fff) == 0 \
1911 : ((v) & ~0xffffff) == 0 \
1912 ? ((v) & ~0xfffff) == 0 \
1913 ? ((v) & ~0x3ffff) == 0 \
1914 ? ((v) & ~0x1ffff) == 0 \
1917 : ((v) & ~0x7ffff) == 0 \
1920 : ((v) & ~0x3fffff) == 0 \
1921 ? ((v) & ~0x1fffff) == 0 \
1924 : ((v) & ~0x7fffff) == 0 \
1927 : ((v) & ~0xfffffff) == 0 \
1928 ? ((v) & ~0x3ffffff) == 0 \
1929 ? ((v) & ~0x1ffffff) == 0 \
1932 : ((v) & ~0x7ffffff) == 0 \
1935 : ((v) & ~0x3fffffff) == 0 \
1936 ? ((v) & ~0x1fffffff) == 0 \
1939 : ((v) & ~0x7fffffff) == 0 \
1944 * This routine generates the least number of instructions neccessary to load
1945 * an absolute expression value into a register.
1948 load_register (counter
, reg
, ep
, dbl
)
1955 expressionS hi32
, lo32
, tmp
;
1957 if (ep
->X_op
!= O_big
)
1959 assert (ep
->X_op
== O_constant
);
1960 if (ep
->X_add_number
< 0x8000
1961 && (ep
->X_add_number
>= 0
1962 || (ep
->X_add_number
>= -0x8000
1965 || sizeof (ep
->X_add_number
) > 4))))
1967 /* We can handle 16 bit signed values with an addiu to
1968 $zero. No need to ever use daddiu here, since $zero and
1969 the result are always correct in 32 bit mode. */
1970 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1971 (int) BFD_RELOC_LO16
);
1974 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1976 /* We can handle 16 bit unsigned values with an ori to
1978 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1979 (int) BFD_RELOC_LO16
);
1982 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1983 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1984 == ~ (offsetT
) 0x7fffffff))
1987 || sizeof (ep
->X_add_number
) > 4
1988 || (ep
->X_add_number
& 0x80000000) == 0))
1989 || ((mips_isa
< 3 || !dbl
)
1990 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1992 /* 32 bit values require an lui. */
1993 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1994 (int) BFD_RELOC_HI16
);
1995 if ((ep
->X_add_number
& 0xffff) != 0)
1996 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1997 (int) BFD_RELOC_LO16
);
2002 /* The value is larger than 32 bits. */
2006 as_bad ("Number larger than 32 bits");
2007 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2008 (int) BFD_RELOC_LO16
);
2012 if (ep
->X_op
!= O_big
)
2016 hi32
.X_add_number
>>= shift
;
2017 hi32
.X_add_number
&= 0xffffffff;
2018 if ((hi32
.X_add_number
& 0x80000000) != 0)
2019 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2021 lo32
.X_add_number
&= 0xffffffff;
2025 assert (ep
->X_add_number
> 2);
2026 if (ep
->X_add_number
== 3)
2027 generic_bignum
[3] = 0;
2028 else if (ep
->X_add_number
> 4)
2029 as_bad ("Number larger than 64 bits");
2030 lo32
.X_op
= O_constant
;
2031 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2032 hi32
.X_op
= O_constant
;
2033 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2036 if (hi32
.X_add_number
== 0)
2040 if (hi32
.X_add_number
== 0xffffffff)
2042 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2044 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2045 (int) BFD_RELOC_LO16
);
2048 if (lo32
.X_add_number
& 0x80000000)
2050 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2051 (int) BFD_RELOC_HI16
);
2052 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2053 (int) BFD_RELOC_LO16
);
2058 /* Check for 16bit shifted constant: */
2060 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2061 /* We know that hi32 is non-zero, so start the mask on the first
2062 bit of the hi32 value: */
2066 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2068 tmp
.X_op
= O_constant
;
2069 tmp
.X_add_number
>>= shift
;
2070 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2071 (int) BFD_RELOC_LO16
);
2072 macro_build ((char *) NULL
, counter
, NULL
,
2073 (shift
>= 32) ? "dsll32" : "dsll",
2074 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2078 } while (shift
<= (64 - 16));
2082 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2083 while ((tmp
.X_add_number
& 1) == 0)
2085 tmp
.X_add_number
>>= 1;
2088 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2090 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2093 tmp
.X_op
= O_constant
;
2094 tmp
.X_add_number
= (offsetT
)-1;
2095 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2096 (int) BFD_RELOC_LO16
); /* set all ones */
2100 macro_build ((char *) NULL
, counter
, NULL
,
2101 (freg
>= 32) ? "dsll32" : "dsll",
2103 (freg
>= 32) ? freg
- 32 : freg
);
2105 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2106 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2110 load_register (counter
, reg
, &hi32
, 0);
2113 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2117 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2126 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2128 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2129 (int) BFD_RELOC_HI16
);
2130 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2137 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2142 mid16
.X_add_number
>>= 16;
2143 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2144 freg
, (int) BFD_RELOC_LO16
);
2145 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2149 if ((lo32
.X_add_number
& 0xffff) != 0)
2150 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2151 (int) BFD_RELOC_LO16
);
2154 /* Load an address into a register. */
2157 load_address (counter
, reg
, ep
)
2164 if (ep
->X_op
!= O_constant
2165 && ep
->X_op
!= O_symbol
)
2167 as_bad ("expression too complex");
2168 ep
->X_op
= O_constant
;
2171 if (ep
->X_op
== O_constant
)
2173 load_register (counter
, reg
, ep
, 0);
2177 if (mips_pic
== NO_PIC
)
2179 /* If this is a reference to a GP relative symbol, we want
2180 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2182 lui $reg,<sym> (BFD_RELOC_HI16_S)
2183 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2184 If we have an addend, we always use the latter form. */
2185 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2186 || nopic_need_relax (ep
->X_add_symbol
))
2191 macro_build ((char *) NULL
, counter
, ep
,
2192 mips_isa
< 3 ? "addiu" : "daddiu",
2193 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2194 p
= frag_var (rs_machine_dependent
, 8, 0,
2195 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2196 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2198 macro_build_lui (p
, counter
, ep
, reg
);
2201 macro_build (p
, counter
, ep
,
2202 mips_isa
< 3 ? "addiu" : "daddiu",
2203 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2205 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2209 /* If this is a reference to an external symbol, we want
2210 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2212 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2214 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2215 If there is a constant, it must be added in after. */
2216 ex
.X_add_number
= ep
->X_add_number
;
2217 ep
->X_add_number
= 0;
2219 macro_build ((char *) NULL
, counter
, ep
,
2220 mips_isa
< 3 ? "lw" : "ld",
2221 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2222 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2223 p
= frag_var (rs_machine_dependent
, 4, 0,
2224 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2225 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2226 macro_build (p
, counter
, ep
,
2227 mips_isa
< 3 ? "addiu" : "daddiu",
2228 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2229 if (ex
.X_add_number
!= 0)
2231 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2232 as_bad ("PIC code offset overflow (max 16 signed bits)");
2233 ex
.X_op
= O_constant
;
2234 macro_build ((char *) NULL
, counter
, &ex
,
2235 mips_isa
< 3 ? "addiu" : "daddiu",
2236 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2239 else if (mips_pic
== SVR4_PIC
)
2244 /* This is the large GOT case. If this is a reference to an
2245 external symbol, we want
2246 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2248 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2249 Otherwise, for a reference to a local symbol, we want
2250 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2252 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2253 If there is a constant, it must be added in after. */
2254 ex
.X_add_number
= ep
->X_add_number
;
2255 ep
->X_add_number
= 0;
2256 if (reg_needs_delay (GP
))
2261 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2262 (int) BFD_RELOC_MIPS_GOT_HI16
);
2263 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2264 mips_isa
< 3 ? "addu" : "daddu",
2265 "d,v,t", reg
, reg
, GP
);
2266 macro_build ((char *) NULL
, counter
, ep
,
2267 mips_isa
< 3 ? "lw" : "ld",
2268 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2269 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2270 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2271 mips_warn_about_macros
),
2272 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2275 /* We need a nop before loading from $gp. This special
2276 check is required because the lui which starts the main
2277 instruction stream does not refer to $gp, and so will not
2278 insert the nop which may be required. */
2279 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2282 macro_build (p
, counter
, ep
,
2283 mips_isa
< 3 ? "lw" : "ld",
2284 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2286 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2288 macro_build (p
, counter
, ep
,
2289 mips_isa
< 3 ? "addiu" : "daddiu",
2290 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2291 if (ex
.X_add_number
!= 0)
2293 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2294 as_bad ("PIC code offset overflow (max 16 signed bits)");
2295 ex
.X_op
= O_constant
;
2296 macro_build ((char *) NULL
, counter
, &ex
,
2297 mips_isa
< 3 ? "addiu" : "daddiu",
2298 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2301 else if (mips_pic
== EMBEDDED_PIC
)
2304 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2306 macro_build ((char *) NULL
, counter
, ep
,
2307 mips_isa
< 3 ? "addiu" : "daddiu",
2308 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2316 * This routine implements the seemingly endless macro or synthesized
2317 * instructions and addressing modes in the mips assembly language. Many
2318 * of these macros are simple and are similar to each other. These could
2319 * probably be handled by some kind of table or grammer aproach instead of
2320 * this verbose method. Others are not simple macros but are more like
2321 * optimizing code generation.
2322 * One interesting optimization is when several store macros appear
2323 * consecutivly that would load AT with the upper half of the same address.
2324 * The ensuing load upper instructions are ommited. This implies some kind
2325 * of global optimization. We currently only optimize within a single macro.
2326 * For many of the load and store macros if the address is specified as a
2327 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2328 * first load register 'at' with zero and use it as the base register. The
2329 * mips assembler simply uses register $zero. Just one tiny optimization
2334 struct mips_cl_insn
*ip
;
2336 register int treg
, sreg
, dreg
, breg
;
2351 bfd_reloc_code_real_type r
;
2353 int hold_mips_optimize
;
2355 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2356 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2357 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2358 mask
= ip
->insn_mo
->mask
;
2360 expr1
.X_op
= O_constant
;
2361 expr1
.X_op_symbol
= NULL
;
2362 expr1
.X_add_symbol
= NULL
;
2363 expr1
.X_add_number
= 1;
2375 mips_emit_delays ();
2377 mips_any_noreorder
= 1;
2379 expr1
.X_add_number
= 8;
2380 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2382 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2384 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2385 macro_build ((char *) NULL
, &icnt
, NULL
,
2386 dbl
? "dsub" : "sub",
2387 "d,v,t", dreg
, 0, sreg
);
2410 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2412 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2413 (int) BFD_RELOC_LO16
);
2416 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2417 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2436 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2438 if (mask
!= M_NOR_I
)
2439 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2440 sreg
, (int) BFD_RELOC_LO16
);
2443 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2444 treg
, sreg
, (int) BFD_RELOC_LO16
);
2445 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2451 load_register (&icnt
, AT
, &imm_expr
, 0);
2452 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2469 if (imm_expr
.X_add_number
== 0)
2471 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2475 load_register (&icnt
, AT
, &imm_expr
, 0);
2476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2484 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2485 likely
? "bgezl" : "bgez",
2491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2492 likely
? "blezl" : "blez",
2496 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2498 likely
? "beql" : "beq",
2505 /* check for > max integer */
2506 maxnum
= 0x7fffffff;
2514 if (imm_expr
.X_add_number
>= maxnum
2515 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2518 /* result is always false */
2521 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2522 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2526 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2532 imm_expr
.X_add_number
++;
2536 if (mask
== M_BGEL_I
)
2538 if (imm_expr
.X_add_number
== 0)
2540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2541 likely
? "bgezl" : "bgez",
2545 if (imm_expr
.X_add_number
== 1)
2547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2548 likely
? "bgtzl" : "bgtz",
2552 maxnum
= 0x7fffffff;
2560 maxnum
= - maxnum
- 1;
2561 if (imm_expr
.X_add_number
<= maxnum
2562 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2565 /* result is always true */
2566 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2570 set_at (&icnt
, sreg
, 0);
2571 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2572 likely
? "beql" : "beq",
2583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2584 likely
? "beql" : "beq",
2588 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2591 likely
? "beql" : "beq",
2598 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2600 imm_expr
.X_add_number
++;
2604 if (mask
== M_BGEUL_I
)
2606 if (imm_expr
.X_add_number
== 0)
2608 if (imm_expr
.X_add_number
== 1)
2610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2611 likely
? "bnel" : "bne",
2615 set_at (&icnt
, sreg
, 1);
2616 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2617 likely
? "beql" : "beq",
2626 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2627 likely
? "bgtzl" : "bgtz",
2633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2634 likely
? "bltzl" : "bltz",
2638 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2640 likely
? "bnel" : "bne",
2649 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2650 likely
? "bnel" : "bne",
2656 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2659 likely
? "bnel" : "bne",
2668 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2669 likely
? "blezl" : "blez",
2675 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2676 likely
? "bgezl" : "bgez",
2680 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2681 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2682 likely
? "beql" : "beq",
2689 maxnum
= 0x7fffffff;
2697 if (imm_expr
.X_add_number
>= maxnum
2698 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2700 imm_expr
.X_add_number
++;
2704 if (mask
== M_BLTL_I
)
2706 if (imm_expr
.X_add_number
== 0)
2708 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2709 likely
? "bltzl" : "bltz",
2713 if (imm_expr
.X_add_number
== 1)
2715 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2716 likely
? "blezl" : "blez",
2720 set_at (&icnt
, sreg
, 0);
2721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2722 likely
? "bnel" : "bne",
2731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2732 likely
? "beql" : "beq",
2738 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2741 likely
? "beql" : "beq",
2748 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2750 imm_expr
.X_add_number
++;
2754 if (mask
== M_BLTUL_I
)
2756 if (imm_expr
.X_add_number
== 0)
2758 if (imm_expr
.X_add_number
== 1)
2760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2761 likely
? "beql" : "beq",
2765 set_at (&icnt
, sreg
, 1);
2766 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2767 likely
? "bnel" : "bne",
2776 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2777 likely
? "bltzl" : "bltz",
2783 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2784 likely
? "bgtzl" : "bgtz",
2788 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2789 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2790 likely
? "bnel" : "bne",
2801 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2802 likely
? "bnel" : "bne",
2806 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2808 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2809 likely
? "bnel" : "bne",
2825 as_warn ("Divide by zero.");
2827 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2829 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2833 mips_emit_delays ();
2835 mips_any_noreorder
= 1;
2836 macro_build ((char *) NULL
, &icnt
, NULL
,
2837 dbl
? "ddiv" : "div",
2838 "z,s,t", sreg
, treg
);
2840 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2843 expr1
.X_add_number
= 8;
2844 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2845 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2846 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2848 expr1
.X_add_number
= -1;
2849 macro_build ((char *) NULL
, &icnt
, &expr1
,
2850 dbl
? "daddiu" : "addiu",
2851 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2852 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2853 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2856 expr1
.X_add_number
= 1;
2857 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2858 (int) BFD_RELOC_LO16
);
2859 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2864 expr1
.X_add_number
= 0x80000000;
2865 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2866 (int) BFD_RELOC_HI16
);
2869 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2872 expr1
.X_add_number
= 8;
2873 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2874 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2875 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2878 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2917 if (imm_expr
.X_add_number
== 0)
2919 as_warn ("Divide by zero.");
2921 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2923 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2926 if (imm_expr
.X_add_number
== 1)
2928 if (strcmp (s2
, "mflo") == 0)
2929 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2932 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2935 if (imm_expr
.X_add_number
== -1
2936 && s
[strlen (s
) - 1] != 'u')
2938 if (strcmp (s2
, "mflo") == 0)
2941 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2944 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2948 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2952 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2953 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2954 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2973 mips_emit_delays ();
2975 mips_any_noreorder
= 1;
2976 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2978 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2981 expr1
.X_add_number
= 8;
2982 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2983 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2984 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2987 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2993 /* Load the address of a symbol into a register. If breg is not
2994 zero, we then add a base register to it. */
2996 /* When generating embedded PIC code, we permit expressions of
2999 where bar is an address in the .text section. These are used
3000 when getting the addresses of functions. We don't permit
3001 X_add_number to be non-zero, because if the symbol is
3002 external the relaxing code needs to know that any addend is
3003 purely the offset to X_op_symbol. */
3004 if (mips_pic
== EMBEDDED_PIC
3005 && offset_expr
.X_op
== O_subtract
3006 && now_seg
== text_section
3007 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3008 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3009 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3010 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3011 ->sy_value
.X_add_symbol
)
3014 && offset_expr
.X_add_number
== 0)
3016 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3017 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3018 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3019 mips_isa
< 3 ? "addiu" : "daddiu",
3020 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3024 if (offset_expr
.X_op
!= O_symbol
3025 && offset_expr
.X_op
!= O_constant
)
3027 as_bad ("expression too complex");
3028 offset_expr
.X_op
= O_constant
;
3042 if (offset_expr
.X_op
== O_constant
)
3043 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3044 else if (mips_pic
== NO_PIC
)
3046 /* If this is a reference to an GP relative symbol, we want
3047 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3049 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3050 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3051 If we have a constant, we need two instructions anyhow,
3052 so we may as well always use the latter form. */
3053 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3054 || nopic_need_relax (offset_expr
.X_add_symbol
))
3059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3060 mips_isa
< 3 ? "addiu" : "daddiu",
3061 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3062 p
= frag_var (rs_machine_dependent
, 8, 0,
3063 RELAX_ENCODE (4, 8, 0, 4, 0,
3064 mips_warn_about_macros
),
3065 offset_expr
.X_add_symbol
, (long) 0,
3068 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3071 macro_build (p
, &icnt
, &offset_expr
,
3072 mips_isa
< 3 ? "addiu" : "daddiu",
3073 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3075 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3077 /* If this is a reference to an external symbol, and there
3078 is no constant, we want
3079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3080 For a local symbol, we want
3081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3083 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3085 If we have a small constant, and this is a reference to
3086 an external symbol, we want
3087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3089 addiu $tempreg,$tempreg,<constant>
3090 For a local symbol, we want the same instruction
3091 sequence, but we output a BFD_RELOC_LO16 reloc on the
3094 If we have a large constant, and this is a reference to
3095 an external symbol, we want
3096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3097 lui $at,<hiconstant>
3098 addiu $at,$at,<loconstant>
3099 addu $tempreg,$tempreg,$at
3100 For a local symbol, we want the same instruction
3101 sequence, but we output a BFD_RELOC_LO16 reloc on the
3102 addiu instruction. */
3103 expr1
.X_add_number
= offset_expr
.X_add_number
;
3104 offset_expr
.X_add_number
= 0;
3106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3108 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3109 if (expr1
.X_add_number
== 0)
3117 /* We're going to put in an addu instruction using
3118 tempreg, so we may as well insert the nop right
3120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3124 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3125 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3127 ? mips_warn_about_macros
3129 offset_expr
.X_add_symbol
, (long) 0,
3133 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3136 macro_build (p
, &icnt
, &expr1
,
3137 mips_isa
< 3 ? "addiu" : "daddiu",
3138 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3139 /* FIXME: If breg == 0, and the next instruction uses
3140 $tempreg, then if this variant case is used an extra
3141 nop will be generated. */
3143 else if (expr1
.X_add_number
>= -0x8000
3144 && expr1
.X_add_number
< 0x8000)
3146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3148 macro_build ((char *) NULL
, &icnt
, &expr1
,
3149 mips_isa
< 3 ? "addiu" : "daddiu",
3150 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3151 (void) frag_var (rs_machine_dependent
, 0, 0,
3152 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3153 offset_expr
.X_add_symbol
, (long) 0,
3160 /* If we are going to add in a base register, and the
3161 target register and the base register are the same,
3162 then we are using AT as a temporary register. Since
3163 we want to load the constant into AT, we add our
3164 current AT (from the global offset table) and the
3165 register into the register now, and pretend we were
3166 not using a base register. */
3171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3174 mips_isa
< 3 ? "addu" : "daddu",
3175 "d,v,t", treg
, AT
, breg
);
3181 /* Set mips_optimize around the lui instruction to avoid
3182 inserting an unnecessary nop after the lw. */
3183 hold_mips_optimize
= mips_optimize
;
3185 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3186 mips_optimize
= hold_mips_optimize
;
3188 macro_build ((char *) NULL
, &icnt
, &expr1
,
3189 mips_isa
< 3 ? "addiu" : "daddiu",
3190 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3192 mips_isa
< 3 ? "addu" : "daddu",
3193 "d,v,t", tempreg
, tempreg
, AT
);
3194 (void) frag_var (rs_machine_dependent
, 0, 0,
3195 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3196 offset_expr
.X_add_symbol
, (long) 0,
3201 else if (mips_pic
== SVR4_PIC
)
3205 /* This is the large GOT case. If this is a reference to an
3206 external symbol, and there is no constant, we want
3207 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3208 addu $tempreg,$tempreg,$gp
3209 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3210 For a local symbol, we want
3211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3213 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3215 If we have a small constant, and this is a reference to
3216 an external symbol, we want
3217 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3218 addu $tempreg,$tempreg,$gp
3219 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3221 addiu $tempreg,$tempreg,<constant>
3222 For a local symbol, we want
3223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3225 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3227 If we have a large constant, and this is a reference to
3228 an external symbol, we want
3229 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3230 addu $tempreg,$tempreg,$gp
3231 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3232 lui $at,<hiconstant>
3233 addiu $at,$at,<loconstant>
3234 addu $tempreg,$tempreg,$at
3235 For a local symbol, we want
3236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3237 lui $at,<hiconstant>
3238 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3239 addu $tempreg,$tempreg,$at
3241 expr1
.X_add_number
= offset_expr
.X_add_number
;
3242 offset_expr
.X_add_number
= 0;
3244 if (reg_needs_delay (GP
))
3248 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3249 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3251 mips_isa
< 3 ? "addu" : "daddu",
3252 "d,v,t", tempreg
, tempreg
, GP
);
3253 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3255 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3257 if (expr1
.X_add_number
== 0)
3265 /* We're going to put in an addu instruction using
3266 tempreg, so we may as well insert the nop right
3268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3273 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3274 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3277 ? mips_warn_about_macros
3279 offset_expr
.X_add_symbol
, (long) 0,
3282 else if (expr1
.X_add_number
>= -0x8000
3283 && expr1
.X_add_number
< 0x8000)
3285 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3287 macro_build ((char *) NULL
, &icnt
, &expr1
,
3288 mips_isa
< 3 ? "addiu" : "daddiu",
3289 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3291 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3292 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3294 ? mips_warn_about_macros
3296 offset_expr
.X_add_symbol
, (long) 0,
3303 /* If we are going to add in a base register, and the
3304 target register and the base register are the same,
3305 then we are using AT as a temporary register. Since
3306 we want to load the constant into AT, we add our
3307 current AT (from the global offset table) and the
3308 register into the register now, and pretend we were
3309 not using a base register. */
3317 assert (tempreg
== AT
);
3318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3321 mips_isa
< 3 ? "addu" : "daddu",
3322 "d,v,t", treg
, AT
, breg
);
3327 /* Set mips_optimize around the lui instruction to avoid
3328 inserting an unnecessary nop after the lw. */
3329 hold_mips_optimize
= mips_optimize
;
3331 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3332 mips_optimize
= hold_mips_optimize
;
3334 macro_build ((char *) NULL
, &icnt
, &expr1
,
3335 mips_isa
< 3 ? "addiu" : "daddiu",
3336 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3338 mips_isa
< 3 ? "addu" : "daddu",
3339 "d,v,t", dreg
, dreg
, AT
);
3341 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3342 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3345 ? mips_warn_about_macros
3347 offset_expr
.X_add_symbol
, (long) 0,
3355 /* This is needed because this instruction uses $gp, but
3356 the first instruction on the main stream does not. */
3357 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3360 macro_build (p
, &icnt
, &offset_expr
,
3362 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3364 if (expr1
.X_add_number
>= -0x8000
3365 && expr1
.X_add_number
< 0x8000)
3367 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3369 macro_build (p
, &icnt
, &expr1
,
3370 mips_isa
< 3 ? "addiu" : "daddiu",
3371 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3372 /* FIXME: If add_number is 0, and there was no base
3373 register, the external symbol case ended with a load,
3374 so if the symbol turns out to not be external, and
3375 the next instruction uses tempreg, an unnecessary nop
3376 will be inserted. */
3382 /* We must add in the base register now, as in the
3383 external symbol case. */
3384 assert (tempreg
== AT
);
3385 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3387 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3388 mips_isa
< 3 ? "addu" : "daddu",
3389 "d,v,t", treg
, AT
, breg
);
3392 /* We set breg to 0 because we have arranged to add
3393 it in in both cases. */
3397 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3399 macro_build (p
, &icnt
, &expr1
,
3400 mips_isa
< 3 ? "addiu" : "daddiu",
3401 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3403 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3404 mips_isa
< 3 ? "addu" : "daddu",
3405 "d,v,t", tempreg
, tempreg
, AT
);
3409 else if (mips_pic
== EMBEDDED_PIC
)
3412 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3414 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3415 mips_isa
< 3 ? "addiu" : "daddiu",
3416 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3423 mips_isa
< 3 ? "addu" : "daddu",
3424 "d,v,t", treg
, tempreg
, breg
);
3432 /* The j instruction may not be used in PIC code, since it
3433 requires an absolute address. We convert it to a b
3435 if (mips_pic
== NO_PIC
)
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3441 /* The jal instructions must be handled as macros because when
3442 generating PIC code they expand to multi-instruction
3443 sequences. Normally they are simple instructions. */
3448 if (mips_pic
== NO_PIC
3449 || mips_pic
== EMBEDDED_PIC
)
3450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3452 else if (mips_pic
== SVR4_PIC
)
3454 if (sreg
!= PIC_CALL_REG
)
3455 as_warn ("MIPS PIC call to register other than $25");
3457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3459 if (mips_cprestore_offset
< 0)
3460 as_warn ("No .cprestore pseudo-op used in PIC code");
3463 expr1
.X_add_number
= mips_cprestore_offset
;
3464 macro_build ((char *) NULL
, &icnt
, &expr1
,
3465 mips_isa
< 3 ? "lw" : "ld",
3466 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3475 if (mips_pic
== NO_PIC
)
3476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3477 else if (mips_pic
== SVR4_PIC
)
3479 /* If this is a reference to an external symbol, and we are
3480 using a small GOT, we want
3481 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3485 lw $gp,cprestore($sp)
3486 The cprestore value is set using the .cprestore
3487 pseudo-op. If we are using a big GOT, we want
3488 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3490 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3494 lw $gp,cprestore($sp)
3495 If the symbol is not external, we want
3496 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3498 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3501 lw $gp,cprestore($sp) */
3505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3506 mips_isa
< 3 ? "lw" : "ld",
3507 "t,o(b)", PIC_CALL_REG
,
3508 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3509 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3511 p
= frag_var (rs_machine_dependent
, 4, 0,
3512 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3513 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3519 if (reg_needs_delay (GP
))
3523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3524 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3526 mips_isa
< 3 ? "addu" : "daddu",
3527 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3529 mips_isa
< 3 ? "lw" : "ld",
3530 "t,o(b)", PIC_CALL_REG
,
3531 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3534 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3535 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3537 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3540 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3543 macro_build (p
, &icnt
, &offset_expr
,
3544 mips_isa
< 3 ? "lw" : "ld",
3545 "t,o(b)", PIC_CALL_REG
,
3546 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3548 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3551 macro_build (p
, &icnt
, &offset_expr
,
3552 mips_isa
< 3 ? "addiu" : "daddiu",
3553 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3554 (int) BFD_RELOC_LO16
);
3555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3556 "jalr", "s", PIC_CALL_REG
);
3557 if (mips_cprestore_offset
< 0)
3558 as_warn ("No .cprestore pseudo-op used in PIC code");
3562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3564 expr1
.X_add_number
= mips_cprestore_offset
;
3565 macro_build ((char *) NULL
, &icnt
, &expr1
,
3566 mips_isa
< 3 ? "lw" : "ld",
3567 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3571 else if (mips_pic
== EMBEDDED_PIC
)
3573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3574 /* The linker may expand the call to a longer sequence which
3575 uses $at, so we must break rather than return. */
3651 if (breg
== treg
|| coproc
|| lr
)
3720 if (mask
== M_LWC1_AB
3721 || mask
== M_SWC1_AB
3722 || mask
== M_LDC1_AB
3723 || mask
== M_SDC1_AB
3732 if (offset_expr
.X_op
!= O_constant
3733 && offset_expr
.X_op
!= O_symbol
)
3735 as_bad ("expression too complex");
3736 offset_expr
.X_op
= O_constant
;
3739 /* A constant expression in PIC code can be handled just as it
3740 is in non PIC code. */
3741 if (mips_pic
== NO_PIC
3742 || offset_expr
.X_op
== O_constant
)
3744 /* If this is a reference to a GP relative symbol, and there
3745 is no base register, we want
3746 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3747 Otherwise, if there is no base register, we want
3748 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3749 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3750 If we have a constant, we need two instructions anyhow,
3751 so we always use the latter form.
3753 If we have a base register, and this is a reference to a
3754 GP relative symbol, we want
3755 addu $tempreg,$breg,$gp
3756 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3758 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3759 addu $tempreg,$tempreg,$breg
3760 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3761 With a constant we always use the latter case. */
3764 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3765 || nopic_need_relax (offset_expr
.X_add_symbol
))
3770 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3771 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3772 p
= frag_var (rs_machine_dependent
, 8, 0,
3773 RELAX_ENCODE (4, 8, 0, 4, 0,
3774 (mips_warn_about_macros
3775 || (used_at
&& mips_noat
))),
3776 offset_expr
.X_add_symbol
, (long) 0,
3780 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3783 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3784 (int) BFD_RELOC_LO16
, tempreg
);
3788 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3789 || nopic_need_relax (offset_expr
.X_add_symbol
))
3794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3795 mips_isa
< 3 ? "addu" : "daddu",
3796 "d,v,t", tempreg
, breg
, GP
);
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3798 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3799 p
= frag_var (rs_machine_dependent
, 12, 0,
3800 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3801 offset_expr
.X_add_symbol
, (long) 0,
3804 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3807 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3808 mips_isa
< 3 ? "addu" : "daddu",
3809 "d,v,t", tempreg
, tempreg
, breg
);
3812 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3813 (int) BFD_RELOC_LO16
, tempreg
);
3816 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3818 /* If this is a reference to an external symbol, we want
3819 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3821 <op> $treg,0($tempreg)
3823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3825 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3826 <op> $treg,0($tempreg)
3827 If there is a base register, we add it to $tempreg before
3828 the <op>. If there is a constant, we stick it in the
3829 <op> instruction. We don't handle constants larger than
3830 16 bits, because we have no way to load the upper 16 bits
3831 (actually, we could handle them for the subset of cases
3832 in which we are not using $at). */
3833 assert (offset_expr
.X_op
== O_symbol
);
3834 expr1
.X_add_number
= offset_expr
.X_add_number
;
3835 offset_expr
.X_add_number
= 0;
3836 if (expr1
.X_add_number
< -0x8000
3837 || expr1
.X_add_number
>= 0x8000)
3838 as_bad ("PIC code offset overflow (max 16 signed bits)");
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3841 mips_isa
< 3 ? "lw" : "ld",
3842 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3844 p
= frag_var (rs_machine_dependent
, 4, 0,
3845 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3846 offset_expr
.X_add_symbol
, (long) 0,
3848 macro_build (p
, &icnt
, &offset_expr
,
3849 mips_isa
< 3 ? "addiu" : "daddiu",
3850 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3853 mips_isa
< 3 ? "addu" : "daddu",
3854 "d,v,t", tempreg
, tempreg
, breg
);
3855 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3856 (int) BFD_RELOC_LO16
, tempreg
);
3858 else if (mips_pic
== SVR4_PIC
)
3862 /* If this is a reference to an external symbol, we want
3863 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3864 addu $tempreg,$tempreg,$gp
3865 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3866 <op> $treg,0($tempreg)
3868 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3870 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3871 <op> $treg,0($tempreg)
3872 If there is a base register, we add it to $tempreg before
3873 the <op>. If there is a constant, we stick it in the
3874 <op> instruction. We don't handle constants larger than
3875 16 bits, because we have no way to load the upper 16 bits
3876 (actually, we could handle them for the subset of cases
3877 in which we are not using $at). */
3878 assert (offset_expr
.X_op
== O_symbol
);
3879 expr1
.X_add_number
= offset_expr
.X_add_number
;
3880 offset_expr
.X_add_number
= 0;
3881 if (expr1
.X_add_number
< -0x8000
3882 || expr1
.X_add_number
>= 0x8000)
3883 as_bad ("PIC code offset overflow (max 16 signed bits)");
3884 if (reg_needs_delay (GP
))
3889 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3890 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3892 mips_isa
< 3 ? "addu" : "daddu",
3893 "d,v,t", tempreg
, tempreg
, GP
);
3894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3895 mips_isa
< 3 ? "lw" : "ld",
3896 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3898 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3899 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3900 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3903 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3906 macro_build (p
, &icnt
, &offset_expr
,
3907 mips_isa
< 3 ? "lw" : "ld",
3908 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3910 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3912 macro_build (p
, &icnt
, &offset_expr
,
3913 mips_isa
< 3 ? "addiu" : "daddiu",
3914 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3916 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3917 mips_isa
< 3 ? "addu" : "daddu",
3918 "d,v,t", tempreg
, tempreg
, breg
);
3919 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3920 (int) BFD_RELOC_LO16
, tempreg
);
3922 else if (mips_pic
== EMBEDDED_PIC
)
3924 /* If there is no base register, we want
3925 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3926 If there is a base register, we want
3927 addu $tempreg,$breg,$gp
3928 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3930 assert (offset_expr
.X_op
== O_symbol
);
3933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3934 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3939 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3940 mips_isa
< 3 ? "addu" : "daddu",
3941 "d,v,t", tempreg
, breg
, GP
);
3942 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3943 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3956 load_register (&icnt
, treg
, &imm_expr
, 0);
3960 load_register (&icnt
, treg
, &imm_expr
, 1);
3964 if (imm_expr
.X_op
== O_constant
)
3966 load_register (&icnt
, AT
, &imm_expr
, 0);
3967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3968 "mtc1", "t,G", AT
, treg
);
3973 assert (offset_expr
.X_op
== O_symbol
3974 && strcmp (segment_name (S_GET_SEGMENT
3975 (offset_expr
.X_add_symbol
)),
3977 && offset_expr
.X_add_number
== 0);
3978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3979 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3984 /* We know that sym is in the .rdata section. First we get the
3985 upper 16 bits of the address. */
3986 if (mips_pic
== NO_PIC
)
3988 /* FIXME: This won't work for a 64 bit address. */
3989 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3991 else if (mips_pic
== SVR4_PIC
)
3993 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3994 mips_isa
< 3 ? "lw" : "ld",
3995 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3997 else if (mips_pic
== EMBEDDED_PIC
)
3999 /* For embedded PIC we pick up the entire address off $gp in
4000 a single instruction. */
4001 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4002 mips_isa
< 3 ? "addiu" : "daddiu",
4003 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4004 offset_expr
.X_op
= O_constant
;
4005 offset_expr
.X_add_number
= 0;
4010 /* Now we load the register(s). */
4012 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4013 treg
, (int) BFD_RELOC_LO16
, AT
);
4016 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4017 treg
, (int) BFD_RELOC_LO16
, AT
);
4020 /* FIXME: How in the world do we deal with the possible
4022 offset_expr
.X_add_number
+= 4;
4023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4024 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4028 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4029 does not become a variant frag. */
4030 frag_wane (frag_now
);
4036 assert (offset_expr
.X_op
== O_symbol
4037 && offset_expr
.X_add_number
== 0);
4038 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4039 if (strcmp (s
, ".lit8") == 0)
4043 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4044 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4048 r
= BFD_RELOC_MIPS_LITERAL
;
4053 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4054 if (mips_pic
== SVR4_PIC
)
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4056 mips_isa
< 3 ? "lw" : "ld",
4057 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4060 /* FIXME: This won't work for a 64 bit address. */
4061 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4066 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4067 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4069 /* To avoid confusion in tc_gen_reloc, we must ensure
4070 that this does not become a variant frag. */
4071 frag_wane (frag_now
);
4082 /* Even on a big endian machine $fn comes before $fn+1. We have
4083 to adjust when loading from memory. */
4086 assert (mips_isa
< 2);
4087 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4088 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4090 /* FIXME: A possible overflow which I don't know how to deal
4092 offset_expr
.X_add_number
+= 4;
4093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4094 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4097 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4098 does not become a variant frag. */
4099 frag_wane (frag_now
);
4108 * The MIPS assembler seems to check for X_add_number not
4109 * being double aligned and generating:
4112 * addiu at,at,%lo(foo+1)
4115 * But, the resulting address is the same after relocation so why
4116 * generate the extra instruction?
4163 if (offset_expr
.X_op
!= O_symbol
4164 && offset_expr
.X_op
!= O_constant
)
4166 as_bad ("expression too complex");
4167 offset_expr
.X_op
= O_constant
;
4170 /* Even on a big endian machine $fn comes before $fn+1. We have
4171 to adjust when loading from memory. We set coproc if we must
4172 load $fn+1 first. */
4173 if (byte_order
== LITTLE_ENDIAN
)
4176 if (mips_pic
== NO_PIC
4177 || offset_expr
.X_op
== O_constant
)
4179 /* If this is a reference to a GP relative symbol, we want
4180 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4181 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4182 If we have a base register, we use this
4184 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4185 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4186 If this is not a GP relative symbol, we want
4187 lui $at,<sym> (BFD_RELOC_HI16_S)
4188 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4189 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4190 If there is a base register, we add it to $at after the
4191 lui instruction. If there is a constant, we always use
4193 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4194 || nopic_need_relax (offset_expr
.X_add_symbol
))
4213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4214 mips_isa
< 3 ? "addu" : "daddu",
4215 "d,v,t", AT
, breg
, GP
);
4221 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4222 coproc
? treg
+ 1 : treg
,
4223 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4224 offset_expr
.X_add_number
+= 4;
4226 /* Set mips_optimize to 2 to avoid inserting an
4228 hold_mips_optimize
= mips_optimize
;
4230 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4231 coproc
? treg
: treg
+ 1,
4232 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4233 mips_optimize
= hold_mips_optimize
;
4235 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4236 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4237 used_at
&& mips_noat
),
4238 offset_expr
.X_add_symbol
, (long) 0,
4241 /* We just generated two relocs. When tc_gen_reloc
4242 handles this case, it will skip the first reloc and
4243 handle the second. The second reloc already has an
4244 extra addend of 4, which we added above. We must
4245 subtract it out, and then subtract another 4 to make
4246 the first reloc come out right. The second reloc
4247 will come out right because we are going to add 4 to
4248 offset_expr when we build its instruction below. */
4249 offset_expr
.X_add_number
-= 8;
4250 offset_expr
.X_op
= O_constant
;
4252 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4257 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4258 mips_isa
< 3 ? "addu" : "daddu",
4259 "d,v,t", AT
, breg
, AT
);
4263 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4264 coproc
? treg
+ 1 : treg
,
4265 (int) BFD_RELOC_LO16
, AT
);
4268 /* FIXME: How do we handle overflow here? */
4269 offset_expr
.X_add_number
+= 4;
4270 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4271 coproc
? treg
: treg
+ 1,
4272 (int) BFD_RELOC_LO16
, AT
);
4274 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4278 /* If this is a reference to an external symbol, we want
4279 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4284 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4286 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4287 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4288 If there is a base register we add it to $at before the
4289 lwc1 instructions. If there is a constant we include it
4290 in the lwc1 instructions. */
4292 expr1
.X_add_number
= offset_expr
.X_add_number
;
4293 offset_expr
.X_add_number
= 0;
4294 if (expr1
.X_add_number
< -0x8000
4295 || expr1
.X_add_number
>= 0x8000 - 4)
4296 as_bad ("PIC code offset overflow (max 16 signed bits)");
4301 frag_grow (24 + off
);
4302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4303 mips_isa
< 3 ? "lw" : "ld",
4304 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4308 mips_isa
< 3 ? "addu" : "daddu",
4309 "d,v,t", AT
, breg
, AT
);
4310 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4311 coproc
? treg
+ 1 : treg
,
4312 (int) BFD_RELOC_LO16
, AT
);
4313 expr1
.X_add_number
+= 4;
4315 /* Set mips_optimize to 2 to avoid inserting an undesired
4317 hold_mips_optimize
= mips_optimize
;
4319 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4320 coproc
? treg
: treg
+ 1,
4321 (int) BFD_RELOC_LO16
, AT
);
4322 mips_optimize
= hold_mips_optimize
;
4324 (void) frag_var (rs_machine_dependent
, 0, 0,
4325 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4326 offset_expr
.X_add_symbol
, (long) 0,
4329 else if (mips_pic
== SVR4_PIC
)
4333 /* If this is a reference to an external symbol, we want
4334 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4336 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4341 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4343 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4344 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4345 If there is a base register we add it to $at before the
4346 lwc1 instructions. If there is a constant we include it
4347 in the lwc1 instructions. */
4349 expr1
.X_add_number
= offset_expr
.X_add_number
;
4350 offset_expr
.X_add_number
= 0;
4351 if (expr1
.X_add_number
< -0x8000
4352 || expr1
.X_add_number
>= 0x8000 - 4)
4353 as_bad ("PIC code offset overflow (max 16 signed bits)");
4354 if (reg_needs_delay (GP
))
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4364 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4366 mips_isa
< 3 ? "addu" : "daddu",
4367 "d,v,t", AT
, AT
, GP
);
4368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4369 mips_isa
< 3 ? "lw" : "ld",
4370 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4374 mips_isa
< 3 ? "addu" : "daddu",
4375 "d,v,t", AT
, breg
, AT
);
4376 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4377 coproc
? treg
+ 1 : treg
,
4378 (int) BFD_RELOC_LO16
, AT
);
4379 expr1
.X_add_number
+= 4;
4381 /* Set mips_optimize to 2 to avoid inserting an undesired
4383 hold_mips_optimize
= mips_optimize
;
4385 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4386 coproc
? treg
: treg
+ 1,
4387 (int) BFD_RELOC_LO16
, AT
);
4388 mips_optimize
= hold_mips_optimize
;
4389 expr1
.X_add_number
-= 4;
4391 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4392 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4393 8 + gpdel
+ off
, 1, 0),
4394 offset_expr
.X_add_symbol
, (long) 0,
4398 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4401 macro_build (p
, &icnt
, &offset_expr
,
4402 mips_isa
< 3 ? "lw" : "ld",
4403 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4405 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4409 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4410 mips_isa
< 3 ? "addu" : "daddu",
4411 "d,v,t", AT
, breg
, AT
);
4414 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4415 coproc
? treg
+ 1 : treg
,
4416 (int) BFD_RELOC_LO16
, AT
);
4418 expr1
.X_add_number
+= 4;
4420 /* Set mips_optimize to 2 to avoid inserting an undesired
4422 hold_mips_optimize
= mips_optimize
;
4424 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4425 coproc
? treg
: treg
+ 1,
4426 (int) BFD_RELOC_LO16
, AT
);
4427 mips_optimize
= hold_mips_optimize
;
4429 else if (mips_pic
== EMBEDDED_PIC
)
4431 /* If there is no base register, we use
4432 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4433 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4434 If we have a base register, we use
4436 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4437 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4447 mips_isa
< 3 ? "addu" : "daddu",
4448 "d,v,t", AT
, breg
, GP
);
4453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4454 coproc
? treg
+ 1 : treg
,
4455 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4456 offset_expr
.X_add_number
+= 4;
4457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4458 coproc
? treg
: treg
+ 1,
4459 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4475 assert (mips_isa
< 3);
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4477 (int) BFD_RELOC_LO16
, breg
);
4478 offset_expr
.X_add_number
+= 4;
4479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4480 (int) BFD_RELOC_LO16
, breg
);
4482 #ifdef LOSING_COMPILER
4488 as_warn ("Macro used $at after \".set noat\"");
4493 struct mips_cl_insn
*ip
;
4495 register int treg
, sreg
, dreg
, breg
;
4510 bfd_reloc_code_real_type r
;
4513 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4514 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4515 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4516 mask
= ip
->insn_mo
->mask
;
4518 expr1
.X_op
= O_constant
;
4519 expr1
.X_op_symbol
= NULL
;
4520 expr1
.X_add_symbol
= NULL
;
4521 expr1
.X_add_number
= 1;
4525 #endif /* LOSING_COMPILER */
4530 macro_build ((char *) NULL
, &icnt
, NULL
,
4531 dbl
? "dmultu" : "multu",
4533 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4539 /* The MIPS assembler some times generates shifts and adds. I'm
4540 not trying to be that fancy. GCC should do this for us
4542 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4543 macro_build ((char *) NULL
, &icnt
, NULL
,
4544 dbl
? "dmult" : "mult",
4546 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4552 mips_emit_delays ();
4554 mips_any_noreorder
= 1;
4555 macro_build ((char *) NULL
, &icnt
, NULL
,
4556 dbl
? "dmult" : "mult",
4558 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4559 macro_build ((char *) NULL
, &icnt
, NULL
,
4560 dbl
? "dsra32" : "sra",
4561 "d,w,<", dreg
, dreg
, 31);
4562 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4564 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4567 expr1
.X_add_number
= 8;
4568 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4569 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4570 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4573 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4579 mips_emit_delays ();
4581 mips_any_noreorder
= 1;
4582 macro_build ((char *) NULL
, &icnt
, NULL
,
4583 dbl
? "dmultu" : "multu",
4585 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4586 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4588 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4591 expr1
.X_add_number
= 8;
4592 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4593 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4594 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4600 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4601 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4602 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4604 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4608 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4609 (int) (imm_expr
.X_add_number
& 0x1f));
4610 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4611 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4612 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4617 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4618 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4624 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4625 (int) (imm_expr
.X_add_number
& 0x1f));
4626 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4627 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4628 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4632 assert (mips_isa
< 2);
4633 /* Even on a big endian machine $fn comes before $fn+1. We have
4634 to adjust when storing to memory. */
4635 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4636 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4637 (int) BFD_RELOC_LO16
, breg
);
4638 offset_expr
.X_add_number
+= 4;
4639 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4640 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4641 (int) BFD_RELOC_LO16
, breg
);
4646 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4647 treg
, (int) BFD_RELOC_LO16
);
4649 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4650 sreg
, (int) BFD_RELOC_LO16
);
4653 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4655 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4656 dreg
, (int) BFD_RELOC_LO16
);
4661 if (imm_expr
.X_add_number
== 0)
4663 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4664 sreg
, (int) BFD_RELOC_LO16
);
4669 as_warn ("Instruction %s: result is always false",
4671 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4674 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4676 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4677 sreg
, (int) BFD_RELOC_LO16
);
4680 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4682 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4683 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4684 mips_isa
< 3 ? "addiu" : "daddiu",
4685 "t,r,j", dreg
, sreg
,
4686 (int) BFD_RELOC_LO16
);
4691 load_register (&icnt
, AT
, &imm_expr
, 0);
4692 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4696 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4697 (int) BFD_RELOC_LO16
);
4702 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4708 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4709 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4710 (int) BFD_RELOC_LO16
);
4713 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4715 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4717 macro_build ((char *) NULL
, &icnt
, &expr1
,
4718 mask
== M_SGE_I
? "slti" : "sltiu",
4719 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4724 load_register (&icnt
, AT
, &imm_expr
, 0);
4725 macro_build ((char *) NULL
, &icnt
, NULL
,
4726 mask
== M_SGE_I
? "slt" : "sltu",
4727 "d,v,t", dreg
, sreg
, AT
);
4730 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4731 (int) BFD_RELOC_LO16
);
4736 case M_SGT
: /* sreg > treg <==> treg < sreg */
4742 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4745 case M_SGT_I
: /* sreg > I <==> I < sreg */
4751 load_register (&icnt
, AT
, &imm_expr
, 0);
4752 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4755 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4761 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4762 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4763 (int) BFD_RELOC_LO16
);
4766 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4772 load_register (&icnt
, AT
, &imm_expr
, 0);
4773 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4774 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4775 (int) BFD_RELOC_LO16
);
4779 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4781 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4782 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4785 load_register (&icnt
, AT
, &imm_expr
, 0);
4786 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4790 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4792 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4793 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4796 load_register (&icnt
, AT
, &imm_expr
, 0);
4797 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4803 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4806 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4810 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4812 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4818 if (imm_expr
.X_add_number
== 0)
4820 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4826 as_warn ("Instruction %s: result is always true",
4828 macro_build ((char *) NULL
, &icnt
, &expr1
,
4829 mips_isa
< 3 ? "addiu" : "daddiu",
4830 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4833 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4835 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4836 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4839 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4841 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4842 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4843 mips_isa
< 3 ? "addiu" : "daddiu",
4844 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4849 load_register (&icnt
, AT
, &imm_expr
, 0);
4850 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4854 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4862 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4864 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4865 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4866 dbl
? "daddi" : "addi",
4867 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4870 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4871 macro_build ((char *) NULL
, &icnt
, NULL
,
4872 dbl
? "dsub" : "sub",
4873 "d,v,t", dreg
, sreg
, AT
);
4879 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4881 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4882 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4883 dbl
? "daddiu" : "addiu",
4884 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4887 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4888 macro_build ((char *) NULL
, &icnt
, NULL
,
4889 dbl
? "dsubu" : "subu",
4890 "d,v,t", dreg
, sreg
, AT
);
4911 load_register (&icnt
, AT
, &imm_expr
, 0);
4912 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4917 assert (mips_isa
< 2);
4918 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4919 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4922 * Is the double cfc1 instruction a bug in the mips assembler;
4923 * or is there a reason for it?
4925 mips_emit_delays ();
4927 mips_any_noreorder
= 1;
4928 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4929 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4930 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4931 expr1
.X_add_number
= 3;
4932 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4933 (int) BFD_RELOC_LO16
);
4934 expr1
.X_add_number
= 2;
4935 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4936 (int) BFD_RELOC_LO16
);
4937 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4938 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4939 macro_build ((char *) NULL
, &icnt
, NULL
,
4940 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4941 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4942 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4952 if (offset_expr
.X_add_number
>= 0x7fff)
4953 as_bad ("operand overflow");
4954 /* avoid load delay */
4955 if (byte_order
== LITTLE_ENDIAN
)
4956 offset_expr
.X_add_number
+= 1;
4957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4958 (int) BFD_RELOC_LO16
, breg
);
4959 if (byte_order
== LITTLE_ENDIAN
)
4960 offset_expr
.X_add_number
-= 1;
4962 offset_expr
.X_add_number
+= 1;
4963 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4964 (int) BFD_RELOC_LO16
, breg
);
4965 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4966 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4979 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4980 as_bad ("operand overflow");
4981 if (byte_order
== LITTLE_ENDIAN
)
4982 offset_expr
.X_add_number
+= off
;
4983 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4984 (int) BFD_RELOC_LO16
, breg
);
4985 if (byte_order
== LITTLE_ENDIAN
)
4986 offset_expr
.X_add_number
-= off
;
4988 offset_expr
.X_add_number
+= off
;
4989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4990 (int) BFD_RELOC_LO16
, breg
);
5003 load_address (&icnt
, AT
, &offset_expr
);
5005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5006 mips_isa
< 3 ? "addu" : "daddu",
5007 "d,v,t", AT
, AT
, breg
);
5008 if (byte_order
== LITTLE_ENDIAN
)
5009 expr1
.X_add_number
= off
;
5011 expr1
.X_add_number
= 0;
5012 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5013 (int) BFD_RELOC_LO16
, AT
);
5014 if (byte_order
== LITTLE_ENDIAN
)
5015 expr1
.X_add_number
= 0;
5017 expr1
.X_add_number
= off
;
5018 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5019 (int) BFD_RELOC_LO16
, AT
);
5024 load_address (&icnt
, AT
, &offset_expr
);
5026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5027 mips_isa
< 3 ? "addu" : "daddu",
5028 "d,v,t", AT
, AT
, breg
);
5029 if (byte_order
== BIG_ENDIAN
)
5030 expr1
.X_add_number
= 0;
5031 macro_build ((char *) NULL
, &icnt
, &expr1
,
5032 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5033 (int) BFD_RELOC_LO16
, AT
);
5034 if (byte_order
== BIG_ENDIAN
)
5035 expr1
.X_add_number
= 1;
5037 expr1
.X_add_number
= 0;
5038 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5039 (int) BFD_RELOC_LO16
, AT
);
5040 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5042 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5047 if (offset_expr
.X_add_number
>= 0x7fff)
5048 as_bad ("operand overflow");
5049 if (byte_order
== BIG_ENDIAN
)
5050 offset_expr
.X_add_number
+= 1;
5051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5052 (int) BFD_RELOC_LO16
, breg
);
5053 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5054 if (byte_order
== BIG_ENDIAN
)
5055 offset_expr
.X_add_number
-= 1;
5057 offset_expr
.X_add_number
+= 1;
5058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5059 (int) BFD_RELOC_LO16
, breg
);
5072 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5073 as_bad ("operand overflow");
5074 if (byte_order
== LITTLE_ENDIAN
)
5075 offset_expr
.X_add_number
+= off
;
5076 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5077 (int) BFD_RELOC_LO16
, breg
);
5078 if (byte_order
== LITTLE_ENDIAN
)
5079 offset_expr
.X_add_number
-= off
;
5081 offset_expr
.X_add_number
+= off
;
5082 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5083 (int) BFD_RELOC_LO16
, breg
);
5096 load_address (&icnt
, AT
, &offset_expr
);
5098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5099 mips_isa
< 3 ? "addu" : "daddu",
5100 "d,v,t", AT
, AT
, breg
);
5101 if (byte_order
== LITTLE_ENDIAN
)
5102 expr1
.X_add_number
= off
;
5104 expr1
.X_add_number
= 0;
5105 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5106 (int) BFD_RELOC_LO16
, AT
);
5107 if (byte_order
== LITTLE_ENDIAN
)
5108 expr1
.X_add_number
= 0;
5110 expr1
.X_add_number
= off
;
5111 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5112 (int) BFD_RELOC_LO16
, AT
);
5116 load_address (&icnt
, AT
, &offset_expr
);
5118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5119 mips_isa
< 3 ? "addu" : "daddu",
5120 "d,v,t", AT
, AT
, breg
);
5121 if (byte_order
== LITTLE_ENDIAN
)
5122 expr1
.X_add_number
= 0;
5123 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5124 (int) BFD_RELOC_LO16
, AT
);
5125 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5127 if (byte_order
== LITTLE_ENDIAN
)
5128 expr1
.X_add_number
= 1;
5130 expr1
.X_add_number
= 0;
5131 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5132 (int) BFD_RELOC_LO16
, AT
);
5133 if (byte_order
== LITTLE_ENDIAN
)
5134 expr1
.X_add_number
= 0;
5136 expr1
.X_add_number
= 1;
5137 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5138 (int) BFD_RELOC_LO16
, AT
);
5139 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5141 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5146 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5150 as_warn ("Macro used $at after \".set noat\"");
5153 /* This routine assembles an instruction into its binary format. As a
5154 side effect, it sets one of the global variables imm_reloc or
5155 offset_reloc to the type of relocation to do if one of the operands
5156 is an address expression. */
5161 struct mips_cl_insn
*ip
;
5166 struct mips_opcode
*insn
;
5169 unsigned int lastregno
= 0;
5174 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5186 as_fatal ("Unknown opcode: `%s'", str
);
5188 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5190 insn_error
= "unrecognized opcode";
5198 assert (strcmp (insn
->name
, str
) == 0);
5200 if (insn
->pinfo
== INSN_MACRO
)
5201 insn_isa
= insn
->match
;
5202 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5204 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5206 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5211 if (insn_isa
> mips_isa
5212 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5214 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5216 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5219 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5220 && strcmp (insn
->name
, insn
[1].name
) == 0)
5225 insn_error
= "opcode not supported on this processor";
5230 ip
->insn_opcode
= insn
->match
;
5231 for (args
= insn
->args
;; ++args
)
5237 case '\0': /* end of args */
5250 ip
->insn_opcode
|= lastregno
<< 21;
5255 ip
->insn_opcode
|= lastregno
<< 16;
5259 ip
->insn_opcode
|= lastregno
<< 11;
5265 /* handle optional base register.
5266 Either the base register is omitted or
5267 we must have a left paren. */
5268 /* this is dependent on the next operand specifier
5269 is a 'b' for base register */
5270 assert (args
[1] == 'b');
5274 case ')': /* these must match exactly */
5279 case '<': /* must be at least one digit */
5281 * According to the manual, if the shift amount is greater
5282 * than 31 or less than 0 the the shift amount should be
5283 * mod 32. In reality the mips assembler issues an error.
5284 * We issue a warning and mask out all but the low 5 bits.
5286 my_getExpression (&imm_expr
, s
);
5287 check_absolute_expr (ip
, &imm_expr
);
5288 if ((unsigned long) imm_expr
.X_add_number
> 31)
5290 as_warn ("Improper shift amount (%ld)",
5291 (long) imm_expr
.X_add_number
);
5292 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5294 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5295 imm_expr
.X_op
= O_absent
;
5299 case '>': /* shift amount minus 32 */
5300 my_getExpression (&imm_expr
, s
);
5301 check_absolute_expr (ip
, &imm_expr
);
5302 if ((unsigned long) imm_expr
.X_add_number
< 32
5303 || (unsigned long) imm_expr
.X_add_number
> 63)
5305 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5306 imm_expr
.X_op
= O_absent
;
5310 case 'k': /* cache code */
5311 case 'h': /* prefx code */
5312 my_getExpression (&imm_expr
, s
);
5313 check_absolute_expr (ip
, &imm_expr
);
5314 if ((unsigned long) imm_expr
.X_add_number
> 31)
5316 as_warn ("Invalid value for `%s' (%lu)",
5318 (unsigned long) imm_expr
.X_add_number
);
5319 imm_expr
.X_add_number
&= 0x1f;
5322 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5324 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5325 imm_expr
.X_op
= O_absent
;
5329 case 'c': /* break code */
5330 my_getExpression (&imm_expr
, s
);
5331 check_absolute_expr (ip
, &imm_expr
);
5332 if ((unsigned) imm_expr
.X_add_number
> 1023)
5333 as_warn ("Illegal break code (%ld)",
5334 (long) imm_expr
.X_add_number
);
5335 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5336 imm_expr
.X_op
= O_absent
;
5340 case 'B': /* syscall code */
5341 my_getExpression (&imm_expr
, s
);
5342 check_absolute_expr (ip
, &imm_expr
);
5343 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5344 as_warn ("Illegal syscall code (%ld)",
5345 (long) imm_expr
.X_add_number
);
5346 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5347 imm_expr
.X_op
= O_absent
;
5351 case 'C': /* Coprocessor code */
5352 my_getExpression (&imm_expr
, s
);
5353 check_absolute_expr (ip
, &imm_expr
);
5354 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5356 as_warn ("Coproccesor code > 25 bits (%ld)",
5357 (long) imm_expr
.X_add_number
);
5358 imm_expr
.X_add_number
&= ((1<<25) - 1);
5360 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5361 imm_expr
.X_op
= O_absent
;
5365 case 'b': /* base register */
5366 case 'd': /* destination register */
5367 case 's': /* source register */
5368 case 't': /* target register */
5369 case 'r': /* both target and source */
5370 case 'v': /* both dest and source */
5371 case 'w': /* both dest and target */
5372 case 'E': /* coprocessor target register */
5373 case 'G': /* coprocessor destination register */
5374 case 'x': /* ignore register name */
5375 case 'z': /* must be zero register */
5389 while (isdigit (*s
));
5391 as_bad ("Invalid register number (%d)", regno
);
5393 else if (*args
== 'E' || *args
== 'G')
5397 if (s
[1] == 'f' && s
[2] == 'p')
5402 else if (s
[1] == 's' && s
[2] == 'p')
5407 else if (s
[1] == 'g' && s
[2] == 'p')
5412 else if (s
[1] == 'a' && s
[2] == 't')
5417 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5422 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5434 as_warn ("Used $at without \".set noat\"");
5440 if (c
== 'r' || c
== 'v' || c
== 'w')
5447 /* 'z' only matches $0. */
5448 if (c
== 'z' && regno
!= 0)
5456 ip
->insn_opcode
|= regno
<< 21;
5460 ip
->insn_opcode
|= regno
<< 11;
5465 ip
->insn_opcode
|= regno
<< 16;
5468 /* This case exists because on the r3000 trunc
5469 expands into a macro which requires a gp
5470 register. On the r6000 or r4000 it is
5471 assembled into a single instruction which
5472 ignores the register. Thus the insn version
5473 is MIPS_ISA2 and uses 'x', and the macro
5474 version is MIPS_ISA1 and uses 't'. */
5477 /* This case is for the div instruction, which
5478 acts differently if the destination argument
5479 is $0. This only matches $0, and is checked
5480 outside the switch. */
5491 ip
->insn_opcode
|= lastregno
<< 21;
5494 ip
->insn_opcode
|= lastregno
<< 16;
5499 case 'D': /* floating point destination register */
5500 case 'S': /* floating point source register */
5501 case 'T': /* floating point target register */
5502 case 'R': /* floating point source register */
5506 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5516 while (isdigit (*s
));
5519 as_bad ("Invalid float register number (%d)", regno
);
5521 if ((regno
& 1) != 0
5523 && ! (strcmp (str
, "mtc1") == 0 ||
5524 strcmp (str
, "mfc1") == 0 ||
5525 strcmp (str
, "lwc1") == 0 ||
5526 strcmp (str
, "swc1") == 0))
5527 as_warn ("Float register should be even, was %d",
5535 if (c
== 'V' || c
== 'W')
5545 ip
->insn_opcode
|= regno
<< 6;
5549 ip
->insn_opcode
|= regno
<< 11;
5553 ip
->insn_opcode
|= regno
<< 16;
5556 ip
->insn_opcode
|= regno
<< 21;
5565 ip
->insn_opcode
|= lastregno
<< 11;
5568 ip
->insn_opcode
|= lastregno
<< 16;
5574 my_getExpression (&imm_expr
, s
);
5575 if (imm_expr
.X_op
!= O_big
5576 && imm_expr
.X_op
!= O_constant
)
5577 insn_error
= "absolute expression required";
5582 my_getExpression (&offset_expr
, s
);
5583 imm_reloc
= BFD_RELOC_32
;
5595 unsigned char temp
[8];
5597 unsigned int length
;
5602 /* These only appear as the last operand in an
5603 instruction, and every instruction that accepts
5604 them in any variant accepts them in all variants.
5605 This means we don't have to worry about backing out
5606 any changes if the instruction does not match.
5608 The difference between them is the size of the
5609 floating point constant and where it goes. For 'F'
5610 and 'L' the constant is 64 bits; for 'f' and 'l' it
5611 is 32 bits. Where the constant is placed is based
5612 on how the MIPS assembler does things:
5615 f -- immediate value
5618 The .lit4 and .lit8 sections are only used if
5619 permitted by the -G argument.
5621 When generating embedded PIC code, we use the
5622 .lit8 section but not the .lit4 section (we can do
5623 .lit4 inline easily; we need to put .lit8
5624 somewhere in the data segment, and using .lit8
5625 permits the linker to eventually combine identical
5628 f64
= *args
== 'F' || *args
== 'L';
5630 save_in
= input_line_pointer
;
5631 input_line_pointer
= s
;
5632 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5634 s
= input_line_pointer
;
5635 input_line_pointer
= save_in
;
5636 if (err
!= NULL
&& *err
!= '\0')
5638 as_bad ("Bad floating point constant: %s", err
);
5639 memset (temp
, '\0', sizeof temp
);
5640 length
= f64
? 8 : 4;
5643 assert (length
== (f64
? 8 : 4));
5647 && (! USE_GLOBAL_POINTER_OPT
5648 || mips_pic
== EMBEDDED_PIC
5649 || g_switch_value
< 4)
5652 imm_expr
.X_op
= O_constant
;
5653 if (byte_order
== LITTLE_ENDIAN
)
5654 imm_expr
.X_add_number
=
5655 (((((((int) temp
[3] << 8)
5660 imm_expr
.X_add_number
=
5661 (((((((int) temp
[0] << 8)
5668 const char *newname
;
5671 /* Switch to the right section. */
5673 subseg
= now_subseg
;
5676 default: /* unused default case avoids warnings. */
5678 newname
= RDATA_SECTION_NAME
;
5679 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5683 newname
= RDATA_SECTION_NAME
;
5686 assert (!USE_GLOBAL_POINTER_OPT
5687 || g_switch_value
>= 4);
5691 new_seg
= subseg_new (newname
, (subsegT
) 0);
5692 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5693 bfd_set_section_flags (stdoutput
, new_seg
,
5698 frag_align (*args
== 'l' ? 2 : 3, 0);
5699 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5700 record_alignment (new_seg
, 4);
5702 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5704 as_bad ("Can't use floating point insn in this section");
5706 /* Set the argument to the current address in the
5708 offset_expr
.X_op
= O_symbol
;
5709 offset_expr
.X_add_symbol
=
5710 symbol_new ("L0\001", now_seg
,
5711 (valueT
) frag_now_fix (), frag_now
);
5712 offset_expr
.X_add_number
= 0;
5714 /* Put the floating point number into the section. */
5715 p
= frag_more ((int) length
);
5716 memcpy (p
, temp
, length
);
5718 /* Switch back to the original section. */
5719 subseg_set (seg
, subseg
);
5724 case 'i': /* 16 bit unsigned immediate */
5725 case 'j': /* 16 bit signed immediate */
5726 imm_reloc
= BFD_RELOC_LO16
;
5727 c
= my_getSmallExpression (&imm_expr
, s
);
5732 if (imm_expr
.X_op
== O_constant
)
5733 imm_expr
.X_add_number
=
5734 (imm_expr
.X_add_number
>> 16) & 0xffff;
5737 imm_reloc
= BFD_RELOC_HI16_S
;
5738 imm_unmatched_hi
= true;
5741 imm_reloc
= BFD_RELOC_HI16
;
5746 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5747 || ((imm_expr
.X_add_number
< 0
5748 || imm_expr
.X_add_number
>= 0x10000)
5749 && imm_expr
.X_op
== O_constant
))
5751 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5752 !strcmp (insn
->name
, insn
[1].name
))
5754 if (imm_expr
.X_op
!= O_constant
5755 && imm_expr
.X_op
!= O_big
)
5756 insn_error
= "absolute expression required";
5758 as_bad ("16 bit expression not in range 0..65535");
5766 /* The upper bound should be 0x8000, but
5767 unfortunately the MIPS assembler accepts numbers
5768 from 0x8000 to 0xffff and sign extends them, and
5769 we want to be compatible. We only permit this
5770 extended range for an instruction which does not
5771 provide any further alternates, since those
5772 alternates may handle other cases. People should
5773 use the numbers they mean, rather than relying on
5774 a mysterious sign extension. */
5775 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5776 strcmp (insn
->name
, insn
[1].name
) == 0);
5781 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5782 || ((imm_expr
.X_add_number
< -0x8000
5783 || imm_expr
.X_add_number
>= max
)
5784 && imm_expr
.X_op
== O_constant
)
5786 && imm_expr
.X_add_number
< 0
5788 && imm_expr
.X_unsigned
5789 && sizeof (imm_expr
.X_add_number
) <= 4))
5793 if (imm_expr
.X_op
!= O_constant
5794 && imm_expr
.X_op
!= O_big
)
5795 insn_error
= "absolute expression required";
5797 as_bad ("16 bit expression not in range -32768..32767");
5803 case 'o': /* 16 bit offset */
5804 c
= my_getSmallExpression (&offset_expr
, s
);
5806 /* If this value won't fit into a 16 bit offset, then go
5807 find a macro that will generate the 32 bit offset
5808 code pattern. As a special hack, we accept the
5809 difference of two local symbols as a constant. This
5810 is required to suppose embedded PIC switches, which
5811 use an instruction which looks like
5812 lw $4,$L12-$LS12($4)
5813 The problem with handling this in a more general
5814 fashion is that the macro function doesn't expect to
5815 see anything which can be handled in a single
5816 constant instruction. */
5818 && (offset_expr
.X_op
!= O_constant
5819 || offset_expr
.X_add_number
>= 0x8000
5820 || offset_expr
.X_add_number
< -0x8000)
5821 && (mips_pic
!= EMBEDDED_PIC
5822 || offset_expr
.X_op
!= O_subtract
5823 || now_seg
!= text_section
5824 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5828 offset_reloc
= BFD_RELOC_LO16
;
5829 if (c
== 'h' || c
== 'H')
5831 assert (offset_expr
.X_op
== O_constant
);
5832 offset_expr
.X_add_number
=
5833 (offset_expr
.X_add_number
>> 16) & 0xffff;
5838 case 'p': /* pc relative offset */
5839 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5840 my_getExpression (&offset_expr
, s
);
5844 case 'u': /* upper 16 bits */
5845 c
= my_getSmallExpression (&imm_expr
, s
);
5846 if (imm_expr
.X_op
== O_constant
5847 && (imm_expr
.X_add_number
< 0
5848 || imm_expr
.X_add_number
>= 0x10000))
5849 as_bad ("lui expression not in range 0..65535");
5850 imm_reloc
= BFD_RELOC_LO16
;
5855 if (imm_expr
.X_op
== O_constant
)
5856 imm_expr
.X_add_number
=
5857 (imm_expr
.X_add_number
>> 16) & 0xffff;
5860 imm_reloc
= BFD_RELOC_HI16_S
;
5861 imm_unmatched_hi
= true;
5864 imm_reloc
= BFD_RELOC_HI16
;
5870 case 'a': /* 26 bit address */
5871 my_getExpression (&offset_expr
, s
);
5873 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5876 case 'N': /* 3 bit branch condition code */
5877 case 'M': /* 3 bit compare condition code */
5878 my_getExpression (&imm_expr
, s
);
5879 check_absolute_expr (ip
, &imm_expr
);
5880 if ((unsigned long) imm_expr
.X_add_number
> 7)
5882 as_warn ("Condition code > 7 (%ld)",
5883 (long) imm_expr
.X_add_number
);
5884 imm_expr
.X_add_number
&= 7;
5887 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5889 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5890 imm_expr
.X_op
= O_absent
;
5895 fprintf (stderr
, "bad char = '%c'\n", *args
);
5900 /* Args don't match. */
5901 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5902 !strcmp (insn
->name
, insn
[1].name
))
5908 insn_error
= "illegal operands";
5917 my_getSmallExpression (ep
, str
)
5928 ((str
[1] == 'h' && str
[2] == 'i')
5929 || (str
[1] == 'H' && str
[2] == 'I')
5930 || (str
[1] == 'l' && str
[2] == 'o'))
5942 * A small expression may be followed by a base register.
5943 * Scan to the end of this operand, and then back over a possible
5944 * base register. Then scan the small expression up to that
5945 * point. (Based on code in sparc.c...)
5947 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5949 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5951 if (isdigit (sp
[-2]))
5953 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5955 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5961 else if (sp
- 5 >= str
5964 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5965 || (sp
[-3] == 's' && sp
[-2] == 'p')
5966 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5967 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5973 /* no expression means zero offset */
5976 /* %xx(reg) is an error */
5977 ep
->X_op
= O_absent
;
5982 ep
->X_op
= O_constant
;
5985 ep
->X_add_symbol
= NULL
;
5986 ep
->X_op_symbol
= NULL
;
5987 ep
->X_add_number
= 0;
5992 my_getExpression (ep
, str
);
5999 my_getExpression (ep
, str
);
6000 return c
; /* => %hi or %lo encountered */
6004 my_getExpression (ep
, str
)
6010 save_in
= input_line_pointer
;
6011 input_line_pointer
= str
;
6013 expr_end
= input_line_pointer
;
6014 input_line_pointer
= save_in
;
6017 /* Turn a string in input_line_pointer into a floating point constant
6018 of type type, and store the appropriate bytes in *litP. The number
6019 of LITTLENUMS emitted is stored in *sizeP . An error message is
6020 returned, or NULL on OK. */
6023 md_atof (type
, litP
, sizeP
)
6029 LITTLENUM_TYPE words
[4];
6045 return "bad call to md_atof";
6048 t
= atof_ieee (input_line_pointer
, type
, words
);
6050 input_line_pointer
= t
;
6054 if (byte_order
== LITTLE_ENDIAN
)
6056 for (i
= prec
- 1; i
>= 0; i
--)
6058 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6064 for (i
= 0; i
< prec
; i
++)
6066 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6075 md_number_to_chars (buf
, val
, n
)
6083 number_to_chars_littleendian (buf
, val
, n
);
6087 number_to_chars_bigendian (buf
, val
, n
);
6095 CONST
char *md_shortopts
= "O::g::G:";
6097 struct option md_longopts
[] = {
6098 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
6099 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
6100 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
6101 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
6102 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
6103 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
6104 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
6105 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
6106 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
6107 #define OPTION_MCPU (OPTION_MD_BASE + 5)
6108 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
6109 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
6110 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
6111 #define OPTION_TRAP (OPTION_MD_BASE + 9)
6112 {"trap", no_argument
, NULL
, OPTION_TRAP
},
6113 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
6114 #define OPTION_BREAK (OPTION_MD_BASE + 10)
6115 {"break", no_argument
, NULL
, OPTION_BREAK
},
6116 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6117 #define OPTION_EB (OPTION_MD_BASE + 11)
6118 {"EB", no_argument
, NULL
, OPTION_EB
},
6119 #define OPTION_EL (OPTION_MD_BASE + 12)
6120 {"EL", no_argument
, NULL
, OPTION_EL
},
6121 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6122 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6123 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6124 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6125 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6126 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6127 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6128 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6129 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6130 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6131 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6132 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6134 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6135 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6136 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6137 #define OPTION_32 (OPTION_MD_BASE + 20)
6138 #define OPTION_64 (OPTION_MD_BASE + 21)
6140 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6141 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6142 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6143 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6144 {"32", no_argument
, NULL
, OPTION_32
},
6145 {"64", no_argument
, NULL
, OPTION_64
},
6148 {NULL
, no_argument
, NULL
, 0}
6150 size_t md_longopts_size
= sizeof(md_longopts
);
6153 md_parse_option (c
, arg
)
6168 target_big_endian
= 1;
6172 target_big_endian
= 0;
6176 if (arg
&& arg
[1] == '0')
6186 mips_debug
= atoi (arg
);
6187 /* When the MIPS assembler sees -g or -g2, it does not do
6188 optimizations which limit full symbolic debugging. We take
6189 that to be equivalent to -O0. */
6190 if (mips_debug
== 2)
6222 /* Identify the processor type */
6224 if (strcmp (p
, "default") == 0
6225 || strcmp (p
, "DEFAULT") == 0)
6231 /* We need to cope with the various "vr" prefixes for the 4300
6233 if (*p
== 'v' || *p
== 'V')
6239 if (*p
== 'r' || *p
== 'R')
6246 if (strcmp (p
, "10000") == 0
6247 || strcmp (p
, "10k") == 0
6248 || strcmp (p
, "10K") == 0)
6253 if (strcmp (p
, "2000") == 0
6254 || strcmp (p
, "2k") == 0
6255 || strcmp (p
, "2K") == 0)
6260 if (strcmp (p
, "3000") == 0
6261 || strcmp (p
, "3k") == 0
6262 || strcmp (p
, "3K") == 0)
6267 if (strcmp (p
, "4000") == 0
6268 || strcmp (p
, "4k") == 0
6269 || strcmp (p
, "4K") == 0)
6271 else if (strcmp (p
, "4100") == 0)
6277 else if (strcmp (p
, "4300") == 0)
6279 else if (strcmp (p
, "4400") == 0)
6281 else if (strcmp (p
, "4600") == 0)
6283 else if (strcmp (p
, "4650") == 0)
6289 else if (strcmp (p
, "4010") == 0)
6298 if (strcmp (p
, "6000") == 0
6299 || strcmp (p
, "6k") == 0
6300 || strcmp (p
, "6K") == 0)
6305 if (strcmp (p
, "8000") == 0
6306 || strcmp (p
, "8k") == 0
6307 || strcmp (p
, "8K") == 0)
6312 if (strcmp (p
, "orion") == 0)
6317 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6319 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6325 as_bad ("invalid architecture -mcpu=%s", arg
);
6336 case OPTION_NO_M4650
:
6344 case OPTION_NO_M4010
:
6352 case OPTION_NO_M4100
:
6356 case OPTION_MEMBEDDED_PIC
:
6357 mips_pic
= EMBEDDED_PIC
;
6358 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6360 as_bad ("-G may not be used with embedded PIC code");
6363 g_switch_value
= 0x7fffffff;
6366 /* When generating ELF code, we permit -KPIC and -call_shared to
6367 select SVR4_PIC, and -non_shared to select no PIC. This is
6368 intended to be compatible with Irix 5. */
6369 case OPTION_CALL_SHARED
:
6370 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6372 as_bad ("-call_shared is supported only for ELF format");
6375 mips_pic
= SVR4_PIC
;
6376 if (g_switch_seen
&& g_switch_value
!= 0)
6378 as_bad ("-G may not be used with SVR4 PIC code");
6384 case OPTION_NON_SHARED
:
6385 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6387 as_bad ("-non_shared is supported only for ELF format");
6393 /* The -xgot option tells the assembler to use 32 offsets when
6394 accessing the got in SVR4_PIC mode. It is for Irix
6401 if (! USE_GLOBAL_POINTER_OPT
)
6403 as_bad ("-G is not supported for this configuration");
6406 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6408 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6412 g_switch_value
= atoi (arg
);
6416 /* The -32 and -64 options tell the assembler to output the 32
6417 bit or the 64 bit MIPS ELF format. */
6424 const char **list
, **l
;
6426 list
= bfd_target_list ();
6427 for (l
= list
; *l
!= NULL
; l
++)
6428 if (strcmp (*l
, "elf64-bigmips") == 0
6429 || strcmp (*l
, "elf64-littlemips") == 0)
6432 as_fatal ("No compiled in support for 64 bit object file format");
6446 md_show_usage (stream
)
6451 -membedded-pic generate embedded position independent code\n\
6452 -EB generate big endian output\n\
6453 -EL generate little endian output\n\
6454 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6455 -G NUM allow referencing objects up to NUM bytes\n\
6456 implicitly with the gp register [default 8]\n");
6458 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6459 -mips2, -mcpu=r6000 generate code for r6000\n\
6460 -mips3, -mcpu=r4000 generate code for r4000\n\
6461 -mips4, -mcpu=r8000 generate code for r8000\n\
6462 -mcpu=vr4300 generate code for vr4300\n\
6463 -mcpu=vr4100 generate code for vr4100\n\
6464 -m4650 permit R4650 instructions\n\
6465 -no-m4650 do not permit R4650 instructions\n\
6466 -m4010 permit R4010 instructions\n\
6467 -no-m4010 do not permit R4010 instructions\n\
6468 -m4100 permit VR4100 instructions\n\
6469 -no-m4100 do not permit VR4100 instructions\n");
6471 -O0 remove unneeded NOPs, do not swap branches\n\
6472 -O remove unneeded NOPs and swap branches\n\
6473 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6474 --break, --no-trap break exception on div by 0 and mult overflow\n");
6477 -KPIC, -call_shared generate SVR4 position independent code\n\
6478 -non_shared do not generate position independent code\n\
6479 -xgot assume a 32 bit GOT\n\
6480 -32 create 32 bit object file (default)\n\
6481 -64 create 64 bit object file\n");
6486 mips_init_after_args ()
6488 if (target_big_endian
)
6489 byte_order
= BIG_ENDIAN
;
6491 byte_order
= LITTLE_ENDIAN
;
6495 md_pcrel_from (fixP
)
6498 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6499 && fixP
->fx_addsy
!= (symbolS
*) NULL
6500 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6502 /* This makes a branch to an undefined symbol be a branch to the
6503 current location. */
6507 /* return the address of the delay slot */
6508 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6511 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6512 reloc for a cons. We could use the definition there, except that
6513 we want to handle 64 bit relocs specially. */
6516 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6519 unsigned int nbytes
;
6522 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6524 if (nbytes
== 8 && ! mips_64
)
6526 if (byte_order
== BIG_ENDIAN
)
6531 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6532 as_bad ("Unsupported reloc size %d", nbytes
);
6534 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6537 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6540 /* Sort any unmatched HI16_S relocs so that they immediately precede
6541 the corresponding LO reloc. This is called before md_apply_fix and
6542 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6543 explicit use of the %hi modifier. */
6548 struct mips_hi_fixup
*l
;
6550 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6552 segment_info_type
*seginfo
;
6555 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6557 /* Check quickly whether the next fixup happens to be a matching
6559 if (l
->fixp
->fx_next
!= NULL
6560 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6561 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6562 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6565 /* Look through the fixups for this segment for a matching %lo.
6566 When we find one, move the %hi just in front of it. We do
6567 this in two passes. In the first pass, we try to find a
6568 unique %lo. In the second pass, we permit multiple %hi
6569 relocs for a single %lo (this is a GNU extension). */
6570 seginfo
= seg_info (l
->seg
);
6571 for (pass
= 0; pass
< 2; pass
++)
6576 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6578 /* Check whether this is a %lo fixup which matches l->fixp. */
6579 if (f
->fx_r_type
== BFD_RELOC_LO16
6580 && f
->fx_addsy
== l
->fixp
->fx_addsy
6581 && f
->fx_offset
== l
->fixp
->fx_offset
6584 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6585 || prev
->fx_addsy
!= f
->fx_addsy
6586 || prev
->fx_offset
!= f
->fx_offset
))
6590 /* Move l->fixp before f. */
6591 for (pf
= &seginfo
->fix_root
;
6593 pf
= &(*pf
)->fx_next
)
6594 assert (*pf
!= NULL
);
6596 *pf
= l
->fixp
->fx_next
;
6598 l
->fixp
->fx_next
= f
;
6600 seginfo
->fix_root
= l
->fixp
;
6602 prev
->fx_next
= l
->fixp
;
6614 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6615 "Unmatched %%hi reloc");
6620 /* When generating embedded PIC code we need to use a special
6621 relocation to represent the difference of two symbols in the .text
6622 section (switch tables use a difference of this sort). See
6623 include/coff/mips.h for details. This macro checks whether this
6624 fixup requires the special reloc. */
6625 #define SWITCH_TABLE(fixp) \
6626 ((fixp)->fx_r_type == BFD_RELOC_32 \
6627 && (fixp)->fx_addsy != NULL \
6628 && (fixp)->fx_subsy != NULL \
6629 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6630 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6632 /* When generating embedded PIC code we must keep all PC relative
6633 relocations, in case the linker has to relax a call. We also need
6634 to keep relocations for switch table entries. */
6638 mips_force_relocation (fixp
)
6641 return (mips_pic
== EMBEDDED_PIC
6643 || SWITCH_TABLE (fixp
)
6644 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6645 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6648 /* Apply a fixup to the object file. */
6651 md_apply_fix (fixP
, valueP
)
6658 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6661 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6663 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6666 switch (fixP
->fx_r_type
)
6668 case BFD_RELOC_MIPS_JMP
:
6669 case BFD_RELOC_HI16
:
6670 case BFD_RELOC_HI16_S
:
6671 case BFD_RELOC_MIPS_GPREL
:
6672 case BFD_RELOC_MIPS_LITERAL
:
6673 case BFD_RELOC_MIPS_CALL16
:
6674 case BFD_RELOC_MIPS_GOT16
:
6675 case BFD_RELOC_MIPS_GPREL32
:
6676 case BFD_RELOC_MIPS_GOT_HI16
:
6677 case BFD_RELOC_MIPS_GOT_LO16
:
6678 case BFD_RELOC_MIPS_CALL_HI16
:
6679 case BFD_RELOC_MIPS_CALL_LO16
:
6681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6682 "Invalid PC relative reloc");
6683 /* Nothing needed to do. The value comes from the reloc entry */
6686 case BFD_RELOC_PCREL_HI16_S
:
6687 /* The addend for this is tricky if it is internal, so we just
6688 do everything here rather than in bfd_perform_relocation. */
6689 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6691 /* For an external symbol adjust by the address to make it
6692 pcrel_offset. We use the address of the RELLO reloc
6693 which follows this one. */
6694 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6695 + fixP
->fx_next
->fx_where
);
6700 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6701 if (byte_order
== BIG_ENDIAN
)
6703 md_number_to_chars (buf
, value
, 2);
6706 case BFD_RELOC_PCREL_LO16
:
6707 /* The addend for this is tricky if it is internal, so we just
6708 do everything here rather than in bfd_perform_relocation. */
6709 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6710 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6711 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6712 if (byte_order
== BIG_ENDIAN
)
6714 md_number_to_chars (buf
, value
, 2);
6718 /* If we are deleting this reloc entry, we must fill in the
6719 value now. This can happen if we have a .word which is not
6720 resolved when it appears but is later defined. We also need
6721 to fill in the value if this is an embedded PIC switch table
6724 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6725 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6730 /* If we are deleting this reloc entry, we must fill in the
6732 assert (fixP
->fx_size
== 2);
6734 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6738 case BFD_RELOC_LO16
:
6739 /* When handling an embedded PIC switch statement, we can wind
6740 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6743 if (value
< -0x8000 || value
> 0x7fff)
6744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6745 "relocation overflow");
6746 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6747 if (byte_order
== BIG_ENDIAN
)
6749 md_number_to_chars (buf
, value
, 2);
6753 case BFD_RELOC_16_PCREL_S2
:
6755 * We need to save the bits in the instruction since fixup_segment()
6756 * might be deleting the relocation entry (i.e., a branch within
6757 * the current segment).
6760 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6761 "Branch to odd address (%lx)", value
);
6764 /* update old instruction data */
6765 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6769 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6773 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6781 if (value
>= -0x8000 && value
< 0x8000)
6782 insn
|= value
& 0xffff;
6785 /* The branch offset is too large. If this is an
6786 unconditional branch, and we are not generating PIC code,
6787 we can convert it to an absolute jump instruction. */
6788 if (mips_pic
== NO_PIC
6790 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6791 && (fixP
->fx_frag
->fr_address
6792 < text_section
->vma
+ text_section
->_raw_size
)
6793 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6794 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6795 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6797 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6798 insn
= 0x0c000000; /* jal */
6800 insn
= 0x08000000; /* j */
6801 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6803 fixP
->fx_addsy
= section_symbol (text_section
);
6804 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6808 /* FIXME. It would be possible in principle to handle
6809 conditional branches which overflow. They could be
6810 transformed into a branch around a jump. This would
6811 require setting up variant frags for each different
6812 branch type. The native MIPS assembler attempts to
6813 handle these cases, but it appears to do it
6815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6816 "Relocation overflow");
6820 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6835 const struct mips_opcode
*p
;
6836 int treg
, sreg
, dreg
, shamt
;
6841 for (i
= 0; i
< NUMOPCODES
; ++i
)
6843 p
= &mips_opcodes
[i
];
6844 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6846 printf ("%08lx %s\t", oc
, p
->name
);
6847 treg
= (oc
>> 16) & 0x1f;
6848 sreg
= (oc
>> 21) & 0x1f;
6849 dreg
= (oc
>> 11) & 0x1f;
6850 shamt
= (oc
>> 6) & 0x1f;
6852 for (args
= p
->args
;; ++args
)
6863 printf ("%c", *args
);
6867 assert (treg
== sreg
);
6868 printf ("$%d,$%d", treg
, sreg
);
6873 printf ("$%d", dreg
);
6878 printf ("$%d", treg
);
6882 printf ("0x%x", treg
);
6887 printf ("$%d", sreg
);
6891 printf ("0x%08lx", oc
& 0x1ffffff);
6903 printf ("$%d", shamt
);
6914 printf ("%08lx UNDEFINED\n", oc
);
6925 name
= input_line_pointer
;
6926 c
= get_symbol_end ();
6927 p
= (symbolS
*) symbol_find_or_make (name
);
6928 *input_line_pointer
= c
;
6932 /* Align the current frag to a given power of two. The MIPS assembler
6933 also automatically adjusts any preceding label. */
6936 mips_align (to
, fill
, label
)
6941 mips_emit_delays ();
6942 frag_align (to
, fill
);
6943 record_alignment (now_seg
, to
);
6946 assert (S_GET_SEGMENT (label
) == now_seg
);
6947 label
->sy_frag
= frag_now
;
6948 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6952 /* Align to a given power of two. .align 0 turns off the automatic
6953 alignment used by the data creating pseudo-ops. */
6960 register long temp_fill
;
6961 long max_alignment
= 15;
6965 o Note that the assembler pulls down any immediately preceeding label
6966 to the aligned address.
6967 o It's not documented but auto alignment is reinstated by
6968 a .align pseudo instruction.
6969 o Note also that after auto alignment is turned off the mips assembler
6970 issues an error on attempt to assemble an improperly aligned data item.
6975 temp
= get_absolute_expression ();
6976 if (temp
> max_alignment
)
6977 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6980 as_warn ("Alignment negative: 0 assumed.");
6983 if (*input_line_pointer
== ',')
6985 input_line_pointer
++;
6986 temp_fill
= get_absolute_expression ();
6993 mips_align (temp
, (int) temp_fill
, insn_label
);
7000 demand_empty_rest_of_line ();
7004 mips_flush_pending_output ()
7006 mips_emit_delays ();
7016 /* When generating embedded PIC code, we only use the .text, .lit8,
7017 .sdata and .sbss sections. We change the .data and .rdata
7018 pseudo-ops to use .sdata. */
7019 if (mips_pic
== EMBEDDED_PIC
7020 && (sec
== 'd' || sec
== 'r'))
7023 mips_emit_delays ();
7033 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
7034 demand_empty_rest_of_line ();
7038 if (USE_GLOBAL_POINTER_OPT
)
7040 seg
= subseg_new (RDATA_SECTION_NAME
,
7041 (subsegT
) get_absolute_expression ());
7042 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7044 bfd_set_section_flags (stdoutput
, seg
,
7050 bfd_set_section_alignment (stdoutput
, seg
, 4);
7052 demand_empty_rest_of_line ();
7056 as_bad ("No read only data section in this object file format");
7057 demand_empty_rest_of_line ();
7063 if (USE_GLOBAL_POINTER_OPT
)
7065 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
7066 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7068 bfd_set_section_flags (stdoutput
, seg
,
7069 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
7071 bfd_set_section_alignment (stdoutput
, seg
, 4);
7073 demand_empty_rest_of_line ();
7078 as_bad ("Global pointers not supported; recompile -G 0");
7079 demand_empty_rest_of_line ();
7088 mips_enable_auto_align ()
7100 mips_emit_delays ();
7101 if (log_size
> 0 && auto_align
)
7102 mips_align (log_size
, 0, label
);
7104 cons (1 << log_size
);
7115 mips_emit_delays ();
7119 mips_align (3, 0, label
);
7121 mips_align (2, 0, label
);
7128 /* Handle .globl. We need to override it because on Irix 5 you are
7131 where foo is an undefined symbol, to mean that foo should be
7132 considered to be the address of a function. */
7143 name
= input_line_pointer
;
7144 c
= get_symbol_end ();
7145 symbolP
= symbol_find_or_make (name
);
7146 *input_line_pointer
= c
;
7149 /* On Irix 5, every global symbol that is not explicitly labelled as
7150 being a function is apparently labelled as being an object. */
7153 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7158 secname
= input_line_pointer
;
7159 c
= get_symbol_end ();
7160 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7162 as_bad ("%s: no such section", secname
);
7163 *input_line_pointer
= c
;
7165 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7166 flag
= BSF_FUNCTION
;
7169 symbolP
->bsym
->flags
|= flag
;
7171 S_SET_EXTERNAL (symbolP
);
7172 demand_empty_rest_of_line ();
7182 opt
= input_line_pointer
;
7183 c
= get_symbol_end ();
7187 /* FIXME: What does this mean? */
7189 else if (strncmp (opt
, "pic", 3) == 0)
7197 mips_pic
= SVR4_PIC
;
7199 as_bad (".option pic%d not supported", i
);
7201 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7203 if (g_switch_seen
&& g_switch_value
!= 0)
7204 as_warn ("-G may not be used with SVR4 PIC code");
7206 bfd_set_gp_size (stdoutput
, 0);
7210 as_warn ("Unrecognized option \"%s\"", opt
);
7212 *input_line_pointer
= c
;
7213 demand_empty_rest_of_line ();
7220 char *name
= input_line_pointer
, ch
;
7222 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7223 input_line_pointer
++;
7224 ch
= *input_line_pointer
;
7225 *input_line_pointer
= '\0';
7227 if (strcmp (name
, "reorder") == 0)
7231 prev_insn_unreordered
= 1;
7232 prev_prev_insn_unreordered
= 1;
7236 else if (strcmp (name
, "noreorder") == 0)
7238 mips_emit_delays ();
7240 mips_any_noreorder
= 1;
7242 else if (strcmp (name
, "at") == 0)
7246 else if (strcmp (name
, "noat") == 0)
7250 else if (strcmp (name
, "macro") == 0)
7252 mips_warn_about_macros
= 0;
7254 else if (strcmp (name
, "nomacro") == 0)
7256 if (mips_noreorder
== 0)
7257 as_bad ("`noreorder' must be set before `nomacro'");
7258 mips_warn_about_macros
= 1;
7260 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7264 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7268 else if (strcmp (name
, "bopt") == 0)
7272 else if (strcmp (name
, "nobopt") == 0)
7276 else if (strncmp (name
, "mips", 4) == 0)
7280 /* Permit the user to change the ISA on the fly. Needless to
7281 say, misuse can cause serious problems. */
7282 isa
= atoi (name
+ 4);
7284 mips_isa
= file_mips_isa
;
7285 else if (isa
< 1 || isa
> 4)
7286 as_bad ("unknown ISA level");
7292 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7294 *input_line_pointer
= ch
;
7295 demand_empty_rest_of_line ();
7298 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7299 .option pic2. It means to generate SVR4 PIC calls. */
7305 mips_pic
= SVR4_PIC
;
7306 if (USE_GLOBAL_POINTER_OPT
)
7308 if (g_switch_seen
&& g_switch_value
!= 0)
7309 as_warn ("-G may not be used with SVR4 PIC code");
7312 bfd_set_gp_size (stdoutput
, 0);
7313 demand_empty_rest_of_line ();
7316 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7317 PIC code. It sets the $gp register for the function based on the
7318 function address, which is in the register named in the argument.
7319 This uses a relocation against _gp_disp, which is handled specially
7320 by the linker. The result is:
7321 lui $gp,%hi(_gp_disp)
7322 addiu $gp,$gp,%lo(_gp_disp)
7323 addu $gp,$gp,.cpload argument
7324 The .cpload argument is normally $25 == $t9. */
7333 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7334 if (mips_pic
!= SVR4_PIC
)
7340 /* .cpload should be a in .set noreorder section. */
7341 if (mips_noreorder
== 0)
7342 as_warn (".cpload not in noreorder section");
7345 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7346 ex
.X_op_symbol
= NULL
;
7347 ex
.X_add_number
= 0;
7349 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7350 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7352 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7353 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7354 (int) BFD_RELOC_LO16
);
7356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7357 GP
, GP
, tc_get_register (0));
7359 demand_empty_rest_of_line ();
7362 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7363 offset from $sp. The offset is remembered, and after making a PIC
7364 call $gp is restored from that location. */
7367 s_cprestore (ignore
)
7373 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7374 if (mips_pic
!= SVR4_PIC
)
7380 mips_cprestore_offset
= get_absolute_expression ();
7382 ex
.X_op
= O_constant
;
7383 ex
.X_add_symbol
= NULL
;
7384 ex
.X_op_symbol
= NULL
;
7385 ex
.X_add_number
= mips_cprestore_offset
;
7387 macro_build ((char *) NULL
, &icnt
, &ex
,
7388 mips_isa
< 3 ? "sw" : "sd",
7389 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7391 demand_empty_rest_of_line ();
7394 /* Handle the .gpword pseudo-op. This is used when generating PIC
7395 code. It generates a 32 bit GP relative reloc. */
7405 /* When not generating PIC code, this is treated as .word. */
7406 if (mips_pic
!= SVR4_PIC
)
7413 mips_emit_delays ();
7415 mips_align (2, 0, label
);
7420 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7422 as_bad ("Unsupported use of .gpword");
7423 ignore_rest_of_line ();
7427 md_number_to_chars (p
, (valueT
) 0, 4);
7428 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7429 BFD_RELOC_MIPS_GPREL32
);
7431 demand_empty_rest_of_line ();
7434 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7435 tables in SVR4 PIC code. */
7444 /* This is ignored when not generating SVR4 PIC code. */
7445 if (mips_pic
!= SVR4_PIC
)
7451 /* Add $gp to the register named as an argument. */
7452 reg
= tc_get_register (0);
7453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7454 mips_isa
< 3 ? "addu" : "daddu",
7455 "d,v,t", reg
, reg
, GP
);
7457 demand_empty_rest_of_line ();
7460 /* Parse a register string into a number. Called from the ECOFF code
7461 to parse .frame. The argument is non-zero if this is the frame
7462 register, so that we can record it in mips_frame_reg. */
7465 tc_get_register (frame
)
7471 if (*input_line_pointer
++ != '$')
7473 as_warn ("expected `$'");
7476 else if (isdigit ((unsigned char) *input_line_pointer
))
7478 reg
= get_absolute_expression ();
7479 if (reg
< 0 || reg
>= 32)
7481 as_warn ("Bad register number");
7487 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7489 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7491 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7493 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7497 as_warn ("Unrecognized register name");
7500 input_line_pointer
+= 2;
7503 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7508 md_section_align (seg
, addr
)
7512 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7515 /* We don't need to align ELF sections to the full alignment.
7516 However, Irix 5 may prefer that we align them at least to a 16
7522 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7525 /* Utility routine, called from above as well. If called while the
7526 input file is still being read, it's only an approximation. (For
7527 example, a symbol may later become defined which appeared to be
7528 undefined earlier.) */
7531 nopic_need_relax (sym
)
7537 if (USE_GLOBAL_POINTER_OPT
)
7539 const char *symname
;
7542 /* Find out whether this symbol can be referenced off the GP
7543 register. It can be if it is smaller than the -G size or if
7544 it is in the .sdata or .sbss section. Certain symbols can
7545 not be referenced off the GP, although it appears as though
7547 symname
= S_GET_NAME (sym
);
7548 if (symname
!= (const char *) NULL
7549 && (strcmp (symname
, "eprol") == 0
7550 || strcmp (symname
, "etext") == 0
7551 || strcmp (symname
, "_gp") == 0
7552 || strcmp (symname
, "edata") == 0
7553 || strcmp (symname
, "_fbss") == 0
7554 || strcmp (symname
, "_fdata") == 0
7555 || strcmp (symname
, "_ftext") == 0
7556 || strcmp (symname
, "end") == 0
7557 || strcmp (symname
, "_gp_disp") == 0))
7559 else if (! S_IS_DEFINED (sym
)
7561 #ifndef NO_ECOFF_DEBUGGING
7562 || (sym
->ecoff_extern_size
!= 0
7563 && sym
->ecoff_extern_size
<= g_switch_value
)
7565 || (S_GET_VALUE (sym
) != 0
7566 && S_GET_VALUE (sym
) <= g_switch_value
)))
7570 const char *segname
;
7572 segname
= segment_name (S_GET_SEGMENT (sym
));
7573 assert (strcmp (segname
, ".lit8") != 0
7574 && strcmp (segname
, ".lit4") != 0);
7575 change
= (strcmp (segname
, ".sdata") != 0
7576 && strcmp (segname
, ".sbss") != 0);
7581 /* We are not optimizing for the GP register. */
7585 /* Estimate the size of a frag before relaxing. We are not really
7586 relaxing here, and the final size is encoded in the subtype
7591 md_estimate_size_before_relax (fragp
, segtype
)
7597 if (mips_pic
== NO_PIC
)
7599 change
= nopic_need_relax (fragp
->fr_symbol
);
7601 else if (mips_pic
== SVR4_PIC
)
7603 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7605 /* This must duplicate the test in adjust_reloc_syms. */
7606 change
= (symsec
!= &bfd_und_section
7607 && symsec
!= &bfd_abs_section
7608 && ! bfd_is_com_section (symsec
));
7615 /* Record the offset to the first reloc in the fr_opcode field.
7616 This lets md_convert_frag and tc_gen_reloc know that the code
7617 must be expanded. */
7618 fragp
->fr_opcode
= (fragp
->fr_literal
7620 - RELAX_OLD (fragp
->fr_subtype
)
7621 + RELAX_RELOC1 (fragp
->fr_subtype
));
7622 /* FIXME: This really needs as_warn_where. */
7623 if (RELAX_WARN (fragp
->fr_subtype
))
7624 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7630 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7633 /* Translate internal representation of relocation info to BFD target
7637 tc_gen_reloc (section
, fixp
)
7641 static arelent
*retval
[4];
7643 bfd_reloc_code_real_type code
;
7645 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7648 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7649 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7651 if (mips_pic
== EMBEDDED_PIC
7652 && SWITCH_TABLE (fixp
))
7654 /* For a switch table entry we use a special reloc. The addend
7655 is actually the difference between the reloc address and the
7657 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7658 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7659 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7660 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7662 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7664 /* We use a special addend for an internal RELLO reloc. */
7665 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7666 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7668 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7670 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7672 assert (fixp
->fx_next
!= NULL
7673 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7674 /* We use a special addend for an internal RELHI reloc. The
7675 reloc is relative to the RELLO; adjust the addend
7677 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7678 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7679 + fixp
->fx_next
->fx_where
7680 - S_GET_VALUE (fixp
->fx_subsy
));
7682 reloc
->addend
= (fixp
->fx_addnumber
7683 + fixp
->fx_next
->fx_frag
->fr_address
7684 + fixp
->fx_next
->fx_where
);
7686 else if (fixp
->fx_pcrel
== 0)
7687 reloc
->addend
= fixp
->fx_addnumber
;
7690 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7691 /* A gruesome hack which is a result of the gruesome gas reloc
7693 reloc
->addend
= reloc
->address
;
7695 reloc
->addend
= -reloc
->address
;
7698 /* If this is a variant frag, we may need to adjust the existing
7699 reloc and generate a new one. */
7700 if (fixp
->fx_frag
->fr_opcode
!= NULL
7701 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7702 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7703 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7704 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7705 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7706 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7707 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7711 /* If this is not the last reloc in this frag, then we have two
7712 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7713 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7714 the second one handle all of them. */
7715 if (fixp
->fx_next
!= NULL
7716 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7718 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7719 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7720 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7721 && (fixp
->fx_next
->fx_r_type
7722 == BFD_RELOC_MIPS_GOT_LO16
))
7723 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7724 && (fixp
->fx_next
->fx_r_type
7725 == BFD_RELOC_MIPS_CALL_LO16
)));
7730 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7731 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7732 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7734 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7735 reloc2
->address
= (reloc
->address
7736 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7737 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7738 reloc2
->addend
= fixp
->fx_addnumber
;
7739 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7740 assert (reloc2
->howto
!= NULL
);
7742 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7746 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7749 reloc3
->address
+= 4;
7752 if (mips_pic
== NO_PIC
)
7754 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7755 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7757 else if (mips_pic
== SVR4_PIC
)
7759 switch (fixp
->fx_r_type
)
7763 case BFD_RELOC_MIPS_GOT16
:
7765 case BFD_RELOC_MIPS_CALL16
:
7766 case BFD_RELOC_MIPS_GOT_LO16
:
7767 case BFD_RELOC_MIPS_CALL_LO16
:
7768 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7776 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7777 fixup_segment converted a non-PC relative reloc into a PC
7778 relative reloc. In such a case, we need to convert the reloc
7780 code
= fixp
->fx_r_type
;
7786 code
= BFD_RELOC_8_PCREL
;
7789 code
= BFD_RELOC_16_PCREL
;
7792 code
= BFD_RELOC_32_PCREL
;
7794 case BFD_RELOC_8_PCREL
:
7795 case BFD_RELOC_16_PCREL
:
7796 case BFD_RELOC_32_PCREL
:
7797 case BFD_RELOC_16_PCREL_S2
:
7798 case BFD_RELOC_PCREL_HI16_S
:
7799 case BFD_RELOC_PCREL_LO16
:
7802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7803 "Cannot make %s relocation PC relative",
7804 bfd_get_reloc_code_name (code
));
7808 /* To support a PC relative reloc when generating embedded PIC code
7809 for ECOFF, we use a Cygnus extension. We check for that here to
7810 make sure that we don't let such a reloc escape normally. */
7811 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7812 && code
== BFD_RELOC_16_PCREL_S2
7813 && mips_pic
!= EMBEDDED_PIC
)
7814 reloc
->howto
= NULL
;
7816 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7818 if (reloc
->howto
== NULL
)
7820 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7821 "Can not represent %s relocation in this object file format",
7822 bfd_get_reloc_code_name (code
));
7829 /* Convert a machine dependent frag. */
7832 md_convert_frag (abfd
, asec
, fragp
)
7840 if (fragp
->fr_opcode
== NULL
)
7843 old
= RELAX_OLD (fragp
->fr_subtype
);
7844 new = RELAX_NEW (fragp
->fr_subtype
);
7845 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7848 memcpy (fixptr
- old
, fixptr
, new);
7850 fragp
->fr_fix
+= new - old
;
7853 /* This function is called whenever a label is defined. It is used
7854 when handling branch delays; if a branch has a label, we assume we
7858 mips_define_label (sym
)
7864 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7865 In order to work with gcc when using mips-tfile, we must keep all
7866 local labels. However, in other cases, we want to discard them,
7867 since they are useless. */
7870 mips_local_label (name
)
7873 #ifndef NO_ECOFF_DEBUGGING
7876 && ! ecoff_debugging_seen
)
7878 /* We were called with -g, but we didn't see any debugging
7879 information. That may mean that gcc is smuggling debugging
7880 information through to mips-tfile, in which case we must
7881 generate all local labels. */
7886 /* Here it's OK to discard local labels. */
7888 return name
[0] == '$';
7891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7893 /* Some special processing for a MIPS ELF file. */
7896 mips_elf_final_processing ()
7898 /* Write out the register information. */
7903 s
.ri_gprmask
= mips_gprmask
;
7904 s
.ri_cprmask
[0] = mips_cprmask
[0];
7905 s
.ri_cprmask
[1] = mips_cprmask
[1];
7906 s
.ri_cprmask
[2] = mips_cprmask
[2];
7907 s
.ri_cprmask
[3] = mips_cprmask
[3];
7908 /* The gp_value field is set by the MIPS ELF backend. */
7910 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7911 ((Elf32_External_RegInfo
*)
7912 mips_regmask_frag
));
7916 Elf64_Internal_RegInfo s
;
7918 s
.ri_gprmask
= mips_gprmask
;
7920 s
.ri_cprmask
[0] = mips_cprmask
[0];
7921 s
.ri_cprmask
[1] = mips_cprmask
[1];
7922 s
.ri_cprmask
[2] = mips_cprmask
[2];
7923 s
.ri_cprmask
[3] = mips_cprmask
[3];
7924 /* The gp_value field is set by the MIPS ELF backend. */
7926 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7927 ((Elf64_External_RegInfo
*)
7928 mips_regmask_frag
));
7931 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7932 sort of BFD interface for this. */
7933 if (mips_any_noreorder
)
7934 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7935 if (mips_pic
!= NO_PIC
)
7936 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7939 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7941 /* These functions should really be defined by the object file format,
7942 since they are related to debugging information. However, this
7943 code has to work for the a.out format, which does not define them,
7944 so we provide simple versions here. These don't actually generate
7945 any debugging information, but they do simple checking and someday
7946 somebody may make them useful. */
7950 struct loc
*loc_next
;
7951 unsigned long loc_fileno
;
7952 unsigned long loc_lineno
;
7953 unsigned long loc_offset
;
7954 unsigned short loc_delta
;
7955 unsigned short loc_count
;
7964 struct proc
*proc_next
;
7965 struct symbol
*proc_isym
;
7966 struct symbol
*proc_end
;
7967 unsigned long proc_reg_mask
;
7968 unsigned long proc_reg_offset
;
7969 unsigned long proc_fpreg_mask
;
7970 unsigned long proc_fpreg_offset
;
7971 unsigned long proc_frameoffset
;
7972 unsigned long proc_framereg
;
7973 unsigned long proc_pcreg
;
7975 struct file
*proc_file
;
7982 struct file
*file_next
;
7983 unsigned long file_fileno
;
7984 struct symbol
*file_symbol
;
7985 struct symbol
*file_end
;
7986 struct proc
*file_proc
;
7991 static struct obstack proc_frags
;
7992 static procS
*proc_lastP
;
7993 static procS
*proc_rootP
;
7994 static int numprocs
;
7999 obstack_begin (&proc_frags
, 0x2000);
8005 /* check for premature end, nesting errors, etc */
8006 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8007 as_warn ("missing `.end' at end of assembly");
8016 if (*input_line_pointer
== '-')
8018 ++input_line_pointer
;
8021 if (!isdigit (*input_line_pointer
))
8022 as_bad ("Expected simple number.");
8023 if (input_line_pointer
[0] == '0')
8025 if (input_line_pointer
[1] == 'x')
8027 input_line_pointer
+= 2;
8028 while (isxdigit (*input_line_pointer
))
8031 val
|= hex_value (*input_line_pointer
++);
8033 return negative
? -val
: val
;
8037 ++input_line_pointer
;
8038 while (isdigit (*input_line_pointer
))
8041 val
|= *input_line_pointer
++ - '0';
8043 return negative
? -val
: val
;
8046 if (!isdigit (*input_line_pointer
))
8048 printf (" *input_line_pointer == '%c' 0x%02x\n",
8049 *input_line_pointer
, *input_line_pointer
);
8050 as_warn ("Invalid number");
8053 while (isdigit (*input_line_pointer
))
8056 val
+= *input_line_pointer
++ - '0';
8058 return negative
? -val
: val
;
8061 /* The .file directive; just like the usual .file directive, but there
8062 is an initial number which is the ECOFF file index. */
8070 line
= get_number ();
8075 /* The .end directive. */
8083 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8086 demand_empty_rest_of_line ();
8090 if (now_seg
!= text_section
)
8091 as_warn (".end not in text section");
8094 as_warn (".end and no .ent seen yet.");
8100 assert (S_GET_NAME (p
));
8101 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
8102 as_warn (".end symbol does not match .ent symbol.");
8105 proc_lastP
->proc_end
= (symbolS
*) 1;
8108 /* The .aent and .ent directives. */
8118 symbolP
= get_symbol ();
8119 if (*input_line_pointer
== ',')
8120 input_line_pointer
++;
8122 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8123 number
= get_number ();
8124 if (now_seg
!= text_section
)
8125 as_warn (".ent or .aent not in text section.");
8127 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8128 as_warn ("missing `.end'");
8132 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8133 procP
->proc_isym
= symbolP
;
8134 procP
->proc_reg_mask
= 0;
8135 procP
->proc_reg_offset
= 0;
8136 procP
->proc_fpreg_mask
= 0;
8137 procP
->proc_fpreg_offset
= 0;
8138 procP
->proc_frameoffset
= 0;
8139 procP
->proc_framereg
= 0;
8140 procP
->proc_pcreg
= 0;
8141 procP
->proc_end
= NULL
;
8142 procP
->proc_next
= NULL
;
8144 proc_lastP
->proc_next
= procP
;
8150 demand_empty_rest_of_line ();
8153 /* The .frame directive. */
8166 frame_reg
= tc_get_register (1);
8167 if (*input_line_pointer
== ',')
8168 input_line_pointer
++;
8169 frame_off
= get_absolute_expression ();
8170 if (*input_line_pointer
== ',')
8171 input_line_pointer
++;
8172 pcreg
= tc_get_register (0);
8175 assert (proc_rootP
);
8176 proc_rootP
->proc_framereg
= frame_reg
;
8177 proc_rootP
->proc_frameoffset
= frame_off
;
8178 proc_rootP
->proc_pcreg
= pcreg
;
8179 /* bob macho .frame */
8181 /* We don't have to write out a frame stab for unoptimized code. */
8182 if (!(frame_reg
== FP
&& frame_off
== 0))
8185 as_warn ("No .ent for .frame to use.");
8186 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8187 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8188 S_SET_TYPE (symP
, N_RMASK
);
8189 S_SET_OTHER (symP
, 0);
8190 S_SET_DESC (symP
, 0);
8191 symP
->sy_forward
= proc_lastP
->proc_isym
;
8192 /* bob perhaps I should have used pseudo set */
8194 demand_empty_rest_of_line ();
8198 /* The .fmask and .mask directives. */
8205 char str
[100], *strP
;
8211 mask
= get_number ();
8212 if (*input_line_pointer
== ',')
8213 input_line_pointer
++;
8214 off
= get_absolute_expression ();
8216 /* bob only for coff */
8217 assert (proc_rootP
);
8218 if (reg_type
== 'F')
8220 proc_rootP
->proc_fpreg_mask
= mask
;
8221 proc_rootP
->proc_fpreg_offset
= off
;
8225 proc_rootP
->proc_reg_mask
= mask
;
8226 proc_rootP
->proc_reg_offset
= off
;
8229 /* bob macho .mask + .fmask */
8231 /* We don't have to write out a mask stab if no saved regs. */
8235 as_warn ("No .ent for .mask to use.");
8237 for (i
= 0; i
< 32; i
++)
8241 sprintf (strP
, "%c%d,", reg_type
, i
);
8242 strP
+= strlen (strP
);
8246 sprintf (strP
, ";%d,", off
);
8247 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8248 S_SET_TYPE (symP
, N_RMASK
);
8249 S_SET_OTHER (symP
, 0);
8250 S_SET_DESC (symP
, 0);
8251 symP
->sy_forward
= proc_lastP
->proc_isym
;
8252 /* bob perhaps I should have used pseudo set */
8257 /* The .loc directive. */
8268 assert (now_seg
== text_section
);
8270 lineno
= get_number ();
8271 addroff
= frag_now_fix ();
8273 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8274 S_SET_TYPE (symbolP
, N_SLINE
);
8275 S_SET_OTHER (symbolP
, 0);
8276 S_SET_DESC (symbolP
, lineno
);
8277 symbolP
->sy_segment
= now_seg
;