1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2015 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #define PUSH_1X_WORKAROUND
27 #include "opcode/msp430.h"
28 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "elf/msp430.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax
;
70 int msp430_enable_polys
;
72 /* Set linkrelax here to avoid fixups in most sections. */
75 /* GCC uses the some condition codes which we'll
76 implement as new polymorph instructions.
78 COND EXPL SHORT JUMP LONG JUMP
79 ===============================================
80 eq == jeq jne +4; br lab
81 ne != jne jeq +4; br lab
83 ltn honours no-overflow flag
84 ltn < jn jn +2; jmp +4; br lab
86 lt < jl jge +4; br lab
87 ltu < jlo lhs +4; br lab
93 ge >= jge jl +4; br lab
94 geu >= jhs jlo +4; br lab
95 ===============================================
97 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
98 beq,bne,blt,bltn,bltu,bge,bgeu
99 'u' means unsigned compares
101 Also, we add 'jump' instruction:
102 jump UNCOND -> jmp br lab
104 They will have fmt == 4, and insn_opnumb == number of instruction. */
109 int index
; /* Corresponding insn_opnumb. */
110 int sop
; /* Opcode if jump length is short. */
111 long lpos
; /* Label position. */
112 long lop0
; /* Opcode 1 _word_ (16 bits). */
113 long lop1
; /* Opcode second word. */
114 long lop2
; /* Opcode third word. */
117 #define MSP430_RLC(n,i,sop,o1) \
118 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
120 static struct rcodes_s msp430_rcodes
[] =
122 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
123 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
124 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
125 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
126 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
127 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
128 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
129 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
134 #define MSP430_RLC(n,i,sop,o1) \
135 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
137 static struct rcodes_s msp430x_rcodes
[] =
139 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
140 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
141 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
142 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
143 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
144 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
145 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
146 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
151 /* More difficult than above and they have format 5.
154 =================================================================
155 gt > jeq +2; jge label jeq +6; jl +4; br label
156 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
157 leu <= jeq label; jlo label jeq +2; jhs +4; br label
158 le <= jeq label; jl label jeq +2; jge +4; br label
159 ================================================================= */
164 int index
; /* Corresponding insn_opnumb. */
165 int tlab
; /* Number of labels in short mode. */
166 int op0
; /* Opcode for first word of short jump. */
167 int op1
; /* Opcode for second word of short jump. */
168 int lop0
; /* Opcodes for long jump mode. */
173 static struct hcodes_s msp430_hcodes
[] =
175 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
176 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
177 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
178 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
182 static struct hcodes_s msp430x_hcodes
[] =
184 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
185 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
186 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
187 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
191 const char comment_chars
[] = ";";
192 const char line_comment_chars
[] = "#";
193 const char line_separator_chars
[] = "{";
194 const char EXP_CHARS
[] = "eE";
195 const char FLT_CHARS
[] = "dD";
197 /* Handle long expressions. */
198 extern LITTLENUM_TYPE generic_bignum
[];
200 static struct hash_control
*msp430_hash
;
203 #define STATE_UNCOND_BRANCH 1 /* jump */
204 #define STATE_NOOV_BRANCH 3 /* bltn */
205 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
206 #define STATE_EMUL_BRANCH 4
215 #define STATE_BITS10 1 /* wild guess. short jump */
216 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
217 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
219 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
220 #define RELAX_STATE(s) ((s) & 3)
221 #define RELAX_LEN(s) ((s) >> 2)
222 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
224 relax_typeS md_relax_table
[] =
232 /* Unconditional jump. */
234 {1024, -1024, CNRL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
235 {0, 0, CUBL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_WORD
)}, /* state word */
236 {1, 1, CUBL
, 0}, /* state undef */
238 /* Simple branches. */
240 {1024, -1024, CNRL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
241 {0, 0, CSBL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_WORD
)}, /* state word */
244 /* blt no overflow branch. */
246 {1024, -1024, CNRL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
247 {0, 0, CNOL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_WORD
)}, /* state word */
250 /* Emulated branches. */
252 {1020, -1020, CEBL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
253 {0, 0, CNOL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_WORD
)}, /* state word */
258 #define MAX_OP_LEN 4096
267 static enum msp_isa selected_isa
= MSP_ISA_430Xv2
;
269 static inline bfd_boolean
270 target_is_430x (void)
272 return selected_isa
>= MSP_ISA_430X
;
275 static inline bfd_boolean
276 target_is_430xv2 (void)
278 return selected_isa
== MSP_ISA_430Xv2
;
281 /* Generate an absolute 16-bit relocation.
282 For the 430X we generate a relocation without linker range checking
283 if the value is being used in an extended (ie 20-bit) instruction,
284 otherwise if have a shifted expression we use a HI reloc.
285 For the 430 we generate a relocation without assembler range checking
286 if we are handling an immediate value or a byte-width instruction. */
288 #undef CHECK_RELOC_MSP430
289 #define CHECK_RELOC_MSP430(OP) \
293 : ((OP).vshift == 1) \
294 ? BFD_RELOC_MSP430_ABS_HI16 \
295 : BFD_RELOC_MSP430X_ABS16) \
296 : ((imm_op || byte_op) \
297 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
299 /* Generate a 16-bit pc-relative relocation.
300 For the 430X we generate a relocation without linkwer range checking.
301 For the 430 we generate a relocation without assembler range checking
302 if we are handling an immediate value or a byte-width instruction. */
303 #undef CHECK_RELOC_MSP430_PCREL
304 #define CHECK_RELOC_MSP430_PCREL \
306 ? BFD_RELOC_MSP430X_PCR16 \
307 : (imm_op || byte_op) \
308 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
310 /* Profiling capability:
311 It is a performance hit to use gcc's profiling approach for this tiny target.
312 Even more -- jtag hardware facility does not perform any profiling functions.
313 However we've got gdb's built-in simulator where we can do anything.
314 Therefore my suggestion is:
316 We define new section ".profiler" which holds all profiling information.
317 We define new pseudo operation .profiler which will instruct assembler to
318 add new profile entry to the object file. Profile should take place at the
323 .profiler flags,function_to_profile [, cycle_corrector, extra]
325 where 'flags' is a combination of the following chars:
328 i - function is in Init section
329 f - function is in Fini section
331 c - libC standard call
332 d - stack value Demand (saved at run-time in simulator)
333 I - Interrupt service routine
338 j - long Jump/ sjlj unwind
339 a - an Arbitrary code fragment
340 t - exTra parameter saved (constant value like frame size)
341 '""' optional: "sil" == sil
343 function_to_profile - function's address
344 cycle_corrector - a value which should be added to the cycle
345 counter, zero if omitted
346 extra - some extra parameter, zero if omitted.
349 ------------------------------
353 .LFrameOffset_fxx=0x08
354 .profiler "scdP", fxx ; function entry.
355 ; we also demand stack value to be displayed
360 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
361 ; (this is a prologue end)
362 ; note, that spare var filled with the frame size
365 .profiler cdE,fxx ; check stack
370 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
371 ret ; cause 'ret' insn takes 3 cycles
372 -------------------------------
374 This profiling approach does not produce any overhead and
376 So, even profiled code can be uploaded to the MCU. */
377 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
378 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
379 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
380 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
381 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
382 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
383 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
384 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
385 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
386 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
387 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
388 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
389 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
390 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
391 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
392 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
405 for (; x
; x
= x
>> 1)
412 /* Parse ordinary expression. */
415 parse_exp (char * s
, expressionS
* op
)
417 input_line_pointer
= s
;
419 if (op
->X_op
== O_absent
)
420 as_bad (_("missing operand"));
421 return input_line_pointer
;
425 /* Delete spaces from s: X ( r 1 2) => X(r12). */
428 del_spaces (char * s
)
436 while (ISSPACE (*m
) && *m
)
438 memmove (s
, m
, strlen (m
) + 1);
446 skip_space (char * s
)
453 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
456 extract_operand (char * from
, char * to
, int limit
)
460 /* Drop leading whitespace. */
461 from
= skip_space (from
);
463 while (size
< limit
&& *from
)
465 *(to
+ size
) = *from
;
466 if (*from
== ',' || *from
== ';' || *from
== '\n')
481 msp430_profiler (int dummy ATTRIBUTE_UNUSED
)
498 s
= input_line_pointer
;
499 end
= input_line_pointer
;
501 while (*end
&& *end
!= '\n')
504 while (*s
&& *s
!= '\n')
515 as_bad (_(".profiler pseudo requires at least two operands."));
516 input_line_pointer
= end
;
520 input_line_pointer
= extract_operand (input_line_pointer
, flags
, 32);
529 p_flags
|= MSP430_PROFILER_FLAG_FRAGMENT
;
532 p_flags
|= MSP430_PROFILER_FLAG_JUMP
;
535 p_flags
|= MSP430_PROFILER_FLAG_PROLSTART
;
538 p_flags
|= MSP430_PROFILER_FLAG_PROLEND
;
541 p_flags
|= MSP430_PROFILER_FLAG_EPISTART
;
544 p_flags
|= MSP430_PROFILER_FLAG_EPIEND
;
547 p_flags
|= MSP430_PROFILER_FLAG_ENTRY
;
550 p_flags
|= MSP430_PROFILER_FLAG_EXIT
;
553 p_flags
|= MSP430_PROFILER_FLAG_INITSECT
;
556 p_flags
|= MSP430_PROFILER_FLAG_FINISECT
;
559 p_flags
|= MSP430_PROFILER_FLAG_LIBCALL
;
562 p_flags
|= MSP430_PROFILER_FLAG_STDCALL
;
565 p_flags
|= MSP430_PROFILER_FLAG_STACKDMD
;
568 p_flags
|= MSP430_PROFILER_FLAG_ISR
;
571 p_flags
|= MSP430_PROFILER_FLAG_EXTRA
;
574 as_warn (_("unknown profiling flag - ignored."));
581 && ( ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_ENTRY
582 | MSP430_PROFILER_FLAG_EXIT
))
583 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_PROLSTART
584 | MSP430_PROFILER_FLAG_PROLEND
585 | MSP430_PROFILER_FLAG_EPISTART
586 | MSP430_PROFILER_FLAG_EPIEND
))
587 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_INITSECT
588 | MSP430_PROFILER_FLAG_FINISECT
))))
590 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
591 input_line_pointer
= end
;
595 /* Generate temp symbol which denotes current location. */
596 if (now_seg
== absolute_section
) /* Paranoia ? */
598 exp1
.X_op
= O_constant
;
599 exp1
.X_add_number
= abs_section_offset
;
600 as_warn (_("profiling in absolute section?"));
604 exp1
.X_op
= O_symbol
;
605 exp1
.X_add_symbol
= symbol_temp_new_now ();
606 exp1
.X_add_number
= 0;
609 /* Generate a symbol which holds flags value. */
610 exp
.X_op
= O_constant
;
611 exp
.X_add_number
= p_flags
;
613 /* Save current section. */
617 /* Now go to .profiler section. */
618 obj_elf_change_section (".profiler", SHT_PROGBITS
, 0, 0, 0, 0, 0);
621 emit_expr (& exp
, 2);
623 /* Save label value. */
624 emit_expr (& exp1
, 2);
628 /* Now get profiling info. */
629 halt
= extract_operand (input_line_pointer
, str
, 1024);
630 /* Process like ".word xxx" directive. */
631 parse_exp (str
, & exp
);
632 emit_expr (& exp
, 2);
633 input_line_pointer
= halt
;
636 /* Fill the rest with zeros. */
637 exp
.X_op
= O_constant
;
638 exp
.X_add_number
= 0;
640 emit_expr (& exp
, 2);
642 /* Return to current section. */
643 subseg_set (seg
, subseg
);
647 extract_word (char * from
, char * to
, int limit
)
652 /* Drop leading whitespace. */
653 from
= skip_space (from
);
656 /* Find the op code end. */
657 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
659 to
[size
++] = *op_end
++;
660 if (size
+ 1 >= limit
)
668 #define OPTION_MMCU 'm'
669 #define OPTION_RELAX 'Q'
670 #define OPTION_POLYMORPHS 'P'
671 #define OPTION_LARGE 'l'
672 static bfd_boolean large_model
= FALSE
;
673 #define OPTION_NO_INTR_NOPS 'N'
674 #define OPTION_INTR_NOPS 'n'
675 static bfd_boolean gen_interrupt_nops
= FALSE
;
676 #define OPTION_WARN_INTR_NOPS 'y'
677 #define OPTION_NO_WARN_INTR_NOPS 'Y'
678 static bfd_boolean warn_interrupt_nops
= TRUE
;
679 #define OPTION_MCPU 'c'
680 #define OPTION_MOVE_DATA 'd'
681 static bfd_boolean move_data
= FALSE
;
684 msp430_set_arch (int option
)
686 char *str
= (char *) alloca (32); /* 32 for good measure. */
688 input_line_pointer
= extract_word (input_line_pointer
, str
, 32);
690 md_parse_option (option
, str
);
691 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
692 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
695 /* This is the full list of MCU names that are known to only
696 support the 430 ISA. */
697 static const char * msp430_mcu_names
[] =
699 "msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231",
700 "msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252",
701 "msp430afe253", "msp430c091", "msp430c092", "msp430c111",
702 "msp430c1111", "msp430c112", "msp430c1121", "msp430c1331",
703 "msp430c1351", "msp430c311s", "msp430c312", "msp430c313",
704 "msp430c314", "msp430c315", "msp430c323", "msp430c325",
705 "msp430c336", "msp430c337", "msp430c412", "msp430c413",
706 "msp430e112", "msp430e313", "msp430e315", "msp430e325",
707 "msp430e337", "msp430f110", "msp430f1101", "msp430f1101a",
708 "msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121",
709 "msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122",
710 "msp430f1222", "msp430f123", "msp430f1232", "msp430f133",
711 "msp430f135", "msp430f147", "msp430f1471", "msp430f148",
712 "msp430f1481", "msp430f149", "msp430f1491", "msp430f155",
713 "msp430f156", "msp430f157", "msp430f1610", "msp430f1611",
714 "msp430f1612", "msp430f167", "msp430f168", "msp430f169",
715 "msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011",
716 "msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111",
717 "msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131",
718 "msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252",
719 "msp430f2254", "msp430f2272", "msp430f2274", "msp430f233",
720 "msp430f2330", "msp430f235", "msp430f2350", "msp430f2370",
721 "msp430f2410", "msp430f247", "msp430f2471", "msp430f248",
722 "msp430f2481", "msp430f249", "msp430f2491", "msp430f412",
723 "msp430f413", "msp430f4132", "msp430f415", "msp430f4152",
724 "msp430f417", "msp430f423", "msp430f423a", "msp430f425",
725 "msp430f4250", "msp430f425a", "msp430f4260", "msp430f427",
726 "msp430f4270", "msp430f427a", "msp430f435", "msp430f4351",
727 "msp430f436", "msp430f4361", "msp430f437", "msp430f4371",
728 "msp430f438", "msp430f439", "msp430f447", "msp430f448",
729 "msp430f4481", "msp430f449", "msp430f4491", "msp430f477",
730 "msp430f478", "msp430f4783", "msp430f4784", "msp430f479",
731 "msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232",
732 "msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252",
733 "msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a",
734 "msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437",
735 "msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478",
736 "msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427",
737 "msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101",
738 "msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113",
739 "msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152",
740 "msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203",
741 "msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213",
742 "msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232",
743 "msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302",
744 "msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332",
745 "msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402",
746 "msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432",
747 "msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453",
748 "msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553",
749 "msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955",
750 "msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031",
751 "msp430i2040", "msp430i2041", "msp430l092", "msp430p112",
752 "msp430p313", "msp430p315", "msp430p315s", "msp430p325",
753 "msp430p337", "msp430tch5e"
757 md_parse_option (int c
, char * arg
)
763 as_fatal (_("MCU option requires a name\n"));
765 if (strcasecmp ("msp430", arg
) == 0)
766 selected_isa
= MSP_ISA_430
;
767 else if (strcasecmp ("msp430xv2", arg
) == 0)
768 selected_isa
= MSP_ISA_430Xv2
;
769 else if (strcasecmp ("msp430x", arg
) == 0)
770 selected_isa
= MSP_ISA_430X
;
775 for (i
= sizeof msp430_mcu_names
/ sizeof msp430_mcu_names
[0]; i
--;)
776 if (strcasecmp (msp430_mcu_names
[i
], arg
) == 0)
778 selected_isa
= MSP_ISA_430
;
782 /* It is not an error if we do not match the MCU name. */
786 if (strcmp (arg
, "430") == 0
787 || strcasecmp (arg
, "msp430") == 0)
788 selected_isa
= MSP_ISA_430
;
789 else if (strcasecmp (arg
, "430x") == 0
790 || strcasecmp (arg
, "msp430x") == 0)
791 selected_isa
= MSP_ISA_430X
;
792 else if (strcasecmp (arg
, "430xv2") == 0
793 || strcasecmp (arg
, "msp430xv2") == 0)
794 selected_isa
= MSP_ISA_430Xv2
;
796 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg
);
800 msp430_enable_relax
= 1;
803 case OPTION_POLYMORPHS
:
804 msp430_enable_polys
= 1;
811 case OPTION_NO_INTR_NOPS
:
812 gen_interrupt_nops
= FALSE
;
814 case OPTION_INTR_NOPS
:
815 gen_interrupt_nops
= TRUE
;
818 case OPTION_WARN_INTR_NOPS
:
819 warn_interrupt_nops
= TRUE
;
821 case OPTION_NO_WARN_INTR_NOPS
:
822 warn_interrupt_nops
= FALSE
;
825 case OPTION_MOVE_DATA
:
833 /* The intention here is to have the mere presence of these sections
834 cause the object to have a reference to a well-known symbol. This
835 reference pulls in the bits of the runtime (crt0) that initialize
836 these sections. Thus, for example, the startup code to call
837 memset() to initialize .bss will only be linked in when there is a
838 non-empty .bss section. Otherwise, the call would exist but have a
839 zero length parameter, which is a waste of memory and cycles.
841 The code which initializes these sections should have a global
842 label for these symbols, and should be marked with KEEP() in the
846 msp430_make_init_symbols (const char * name
)
848 if (strncmp (name
, ".bss", 4) == 0
849 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
850 (void) symbol_find_or_make ("__crt0_init_bss");
852 if (strncmp (name
, ".data", 5) == 0
853 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
854 (void) symbol_find_or_make ("__crt0_movedata");
856 /* Note - data assigned to the .either.data section may end up being
857 placed in the .upper.data section if the .lower.data section is
858 full. Hence the need to define the crt0 symbol. */
859 if (strncmp (name
, ".either.data", 12) == 0
860 || strncmp (name
, ".upper.data", 11) == 0)
861 (void) symbol_find_or_make ("__crt0_move_highdata");
863 /* See note about .either.data above. */
864 if (strncmp (name
, ".upper.bss", 10) == 0
865 || strncmp (name
, ".either.bss", 11) == 0)
866 (void) symbol_find_or_make ("__crt0_init_highbss");
870 msp430_section (int arg
)
872 char * saved_ilp
= input_line_pointer
;
873 char * name
= obj_elf_section_name ();
875 msp430_make_init_symbols (name
);
877 input_line_pointer
= saved_ilp
;
878 obj_elf_section (arg
);
882 msp430_frob_section (asection
*sec
)
884 const char *name
= sec
->name
;
889 msp430_make_init_symbols (name
);
893 msp430_lcomm (int ignore ATTRIBUTE_UNUSED
)
895 symbolS
*symbolP
= s_comm_internal (0, s_lcomm_internal
);
898 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
899 (void) symbol_find_or_make ("__crt0_init_bss");
903 msp430_comm (int needs_align
)
905 s_comm_internal (needs_align
, elf_common_parse
);
906 (void) symbol_find_or_make ("__crt0_init_bss");
910 msp430_refsym (int arg ATTRIBUTE_UNUSED
)
913 input_line_pointer
= extract_word (input_line_pointer
, sym_name
, 1024);
915 (void) symbol_find_or_make (sym_name
);
918 const pseudo_typeS md_pseudo_table
[] =
920 {"arch", msp430_set_arch
, OPTION_MMCU
},
921 {"cpu", msp430_set_arch
, OPTION_MCPU
},
922 {"profiler", msp430_profiler
, 0},
923 {"section", msp430_section
, 0},
924 {"section.s", msp430_section
, 0},
925 {"sect", msp430_section
, 0},
926 {"sect.s", msp430_section
, 0},
927 {"pushsection", msp430_section
, 1},
928 {"refsym", msp430_refsym
, 0},
929 {"comm", msp430_comm
, 0},
930 {"lcomm", msp430_lcomm
, 0},
934 const char *md_shortopts
= "mm:,mP,mQ,ml,mN,mn,my,mY";
936 struct option md_longopts
[] =
938 {"mmcu", required_argument
, NULL
, OPTION_MMCU
},
939 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
940 {"mP", no_argument
, NULL
, OPTION_POLYMORPHS
},
941 {"mQ", no_argument
, NULL
, OPTION_RELAX
},
942 {"ml", no_argument
, NULL
, OPTION_LARGE
},
943 {"mN", no_argument
, NULL
, OPTION_NO_INTR_NOPS
},
944 {"mn", no_argument
, NULL
, OPTION_INTR_NOPS
},
945 {"mY", no_argument
, NULL
, OPTION_NO_WARN_INTR_NOPS
},
946 {"my", no_argument
, NULL
, OPTION_WARN_INTR_NOPS
},
947 {"md", no_argument
, NULL
, OPTION_MOVE_DATA
},
948 {NULL
, no_argument
, NULL
, 0}
951 size_t md_longopts_size
= sizeof (md_longopts
);
954 md_show_usage (FILE * stream
)
957 _("MSP430 options:\n"
958 " -mmcu=<msp430-name> - select microcontroller type\n"
959 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
961 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
962 " -mP - enable polymorph instructions\n"));
964 _(" -ml - enable large code model\n"));
966 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
968 _(" -mn - insert a NOP after changing interrupts\n"));
970 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
972 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
974 _(" -md - Force copying of data from ROM to RAM at startup\n"));
978 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
984 extract_cmd (char * from
, char * to
, int limit
)
988 while (*from
&& ! ISSPACE (*from
) && *from
!= '.' && limit
> size
)
990 *(to
+ size
) = *from
;
1001 md_atof (int type
, char * litP
, int * sizeP
)
1003 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
1009 struct msp430_opcode_s
* opcode
;
1010 msp430_hash
= hash_new ();
1012 for (opcode
= msp430_opcodes
; opcode
->name
; opcode
++)
1013 hash_insert (msp430_hash
, opcode
->name
, (char *) opcode
);
1015 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
1016 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
1019 /* Returns the register number equivalent to the string T.
1020 Returns -1 if there is no such register.
1021 Skips a leading 'r' or 'R' character if there is one.
1022 Handles the register aliases PC and SP. */
1025 check_reg (char * t
)
1032 if (*t
== 'r' || *t
== 'R')
1035 if (strncasecmp (t
, "pc", 2) == 0)
1038 if (strncasecmp (t
, "sp", 2) == 0)
1041 if (strncasecmp (t
, "sr", 2) == 0)
1049 if (val
< 1 || val
> 15)
1056 msp430_srcoperand (struct msp430_operand_s
* op
,
1059 bfd_boolean
* imm_op
,
1060 bfd_boolean allow_20bit_values
,
1061 bfd_boolean constants_allowed
)
1065 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1072 /* Check if there is:
1073 llo(x) - least significant 16 bits, x &= 0xffff
1074 lhi(x) - x = (x >> 16) & 0xffff,
1075 hlo(x) - x = (x >> 32) & 0xffff,
1076 hhi(x) - x = (x >> 48) & 0xffff
1077 The value _MUST_ be constant expression: #hlo(1231231231). */
1081 if (strncasecmp (h
, "#llo(", 5) == 0)
1086 else if (strncasecmp (h
, "#lhi(", 5) == 0)
1091 else if (strncasecmp (h
, "#hlo(", 5) == 0)
1096 else if (strncasecmp (h
, "#hhi(", 5) == 0)
1101 else if (strncasecmp (h
, "#lo(", 4) == 0)
1106 else if (strncasecmp (h
, "#hi(", 4) == 0)
1112 op
->reg
= 0; /* Reg PC. */
1114 op
->ol
= 1; /* Immediate will follow an instruction. */
1115 __tl
= h
+ 1 + rval
;
1117 op
->vshift
= vshift
;
1119 parse_exp (__tl
, &(op
->exp
));
1120 if (op
->exp
.X_op
== O_constant
)
1122 int x
= op
->exp
.X_add_number
;
1127 op
->exp
.X_add_number
= x
;
1129 else if (vshift
== 1)
1131 x
= (x
>> 16) & 0xffff;
1132 op
->exp
.X_add_number
= x
;
1135 else if (vshift
> 1)
1138 op
->exp
.X_add_number
= -1;
1140 op
->exp
.X_add_number
= 0; /* Nothing left. */
1141 x
= op
->exp
.X_add_number
;
1145 if (allow_20bit_values
)
1147 if (op
->exp
.X_add_number
> 0xfffff || op
->exp
.X_add_number
< -524288)
1149 as_bad (_("value 0x%x out of extended range."), x
);
1153 else if (op
->exp
.X_add_number
> 65535 || op
->exp
.X_add_number
< -32768)
1155 as_bad (_("value %d out of range. Use #lo() or #hi()"), x
);
1159 /* Now check constants. */
1160 /* Substitute register mode with a constant generator if applicable. */
1162 if (!allow_20bit_values
)
1163 x
= (short) x
; /* Extend sign. */
1165 if (! constants_allowed
)
1197 #ifdef PUSH_1X_WORKAROUND
1200 /* Remove warning as confusing.
1201 as_warn (_("Hardware push bug workaround")); */
1214 #ifdef PUSH_1X_WORKAROUND
1217 /* Remove warning as confusing.
1218 as_warn (_("Hardware push bug workaround")); */
1230 else if (op
->exp
.X_op
== O_symbol
)
1233 as_bad (_("error: unsupported #foo() directive used on symbol"));
1236 else if (op
->exp
.X_op
== O_big
)
1242 op
->exp
.X_op
= O_constant
;
1243 op
->exp
.X_add_number
= 0xffff & generic_bignum
[vshift
];
1244 x
= op
->exp
.X_add_number
;
1250 ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
1298 /* Redundant (yet) check. */
1299 else if (op
->exp
.X_op
== O_register
)
1301 (_("Registers cannot be used within immediate expression [%s]"), l
);
1303 as_bad (_("unknown operand %s"), l
);
1308 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1313 op
->reg
= 2; /* reg 2 in absolute addr mode. */
1314 op
->am
= 1; /* mode As == 01 bin. */
1315 op
->ol
= 1; /* Immediate value followed by instruction. */
1317 parse_exp (__tl
, &(op
->exp
));
1320 if (op
->exp
.X_op
== O_constant
)
1322 int x
= op
->exp
.X_add_number
;
1324 if (allow_20bit_values
)
1326 if (x
> 0xfffff || x
< -(0x7ffff))
1328 as_bad (_("value 0x%x out of extended range."), x
);
1332 else if (x
> 65535 || x
< -32768)
1334 as_bad (_("value out of range: 0x%x"), x
);
1338 else if (op
->exp
.X_op
== O_symbol
)
1342 /* Redundant (yet) check. */
1343 if (op
->exp
.X_op
== O_register
)
1345 (_("Registers cannot be used within absolute expression [%s]"), l
);
1347 as_bad (_("unknown expression in operand %s"), l
);
1353 /* Check if indirect register mode @Rn / postincrement @Rn+. */
1357 char *m
= strchr (l
, '+');
1361 as_bad (_("unknown addressing mode %s"), l
);
1367 if ((op
->reg
= check_reg (t
)) == -1)
1369 as_bad (_("Bad register name %s"), t
);
1377 /* PC cannot be used in indirect addressing. */
1378 if (target_is_430xv2 () && op
->reg
== 0)
1380 as_bad (_("cannot use indirect addressing with the PC"));
1387 /* Check if register indexed X(Rn). */
1390 char *h
= strrchr (l
, '(');
1391 char *m
= strrchr (l
, ')');
1400 as_bad (_("')' required"));
1408 /* Extract a register. */
1409 if ((op
->reg
= check_reg (t
+ 1)) == -1)
1412 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
1419 as_bad (_("r2 should not be used in indexed addressing mode"));
1423 /* Extract constant. */
1428 parse_exp (__tl
, &(op
->exp
));
1429 if (op
->exp
.X_op
== O_constant
)
1431 int x
= op
->exp
.X_add_number
;
1433 if (allow_20bit_values
)
1435 if (x
> 0xfffff || x
< - (0x7ffff))
1437 as_bad (_("value 0x%x out of extended range."), x
);
1441 else if (x
> 65535 || x
< -32768)
1443 as_bad (_("value out of range: 0x%x"), x
);
1455 else if (op
->exp
.X_op
== O_symbol
)
1459 /* Redundant (yet) check. */
1460 if (op
->exp
.X_op
== O_register
)
1462 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l
);
1464 as_bad (_("unknown expression in operand %s"), l
);
1472 /* Possibly register mode 'mov r1,r2'. */
1473 if ((op
->reg
= check_reg (l
)) != -1)
1481 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
1485 op
->reg
= 0; /* PC relative... be careful. */
1486 /* An expression starting with a minus sign is a constant, not an address. */
1487 op
->am
= (*l
== '-' ? 3 : 1);
1491 parse_exp (__tl
, &(op
->exp
));
1497 as_bad (_("unknown addressing mode for operand %s"), l
);
1503 msp430_dstoperand (struct msp430_operand_s
* op
,
1506 bfd_boolean allow_20bit_values
,
1507 bfd_boolean constants_allowed
)
1510 int ret
= msp430_srcoperand (op
, l
, bin
, & dummy
,
1525 parse_exp (__tl
, &(op
->exp
));
1527 if (op
->exp
.X_op
!= O_constant
|| op
->exp
.X_add_number
!= 0)
1529 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
1539 ("this addressing mode is not applicable for destination operand"));
1545 /* Attempt to encode a MOVA instruction with the given operands.
1546 Returns the length of the encoded instruction if successful
1547 or 0 upon failure. If the encoding fails, an error message
1548 will be returned if a pointer is provided. */
1551 try_encode_mova (bfd_boolean imm_op
,
1553 struct msp430_operand_s
* op1
,
1554 struct msp430_operand_s
* op2
,
1555 const char ** error_message_return
)
1561 /* Only a restricted subset of the normal MSP430 addressing modes
1562 are supported here, so check for the ones that are allowed. */
1565 if (op1
->mode
== OP_EXP
)
1567 if (op2
->mode
!= OP_REG
)
1569 if (error_message_return
!= NULL
)
1570 * error_message_return
= _("expected register as second argument of %s");
1576 /* MOVA #imm20, Rdst. */
1577 bin
|= 0x80 | op2
->reg
;
1578 frag
= frag_more (4);
1579 where
= frag
- frag_now
->fr_literal
;
1580 if (op1
->exp
.X_op
== O_constant
)
1582 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1583 bfd_putl16 ((bfd_vma
) bin
, frag
);
1584 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1588 bfd_putl16 ((bfd_vma
) bin
, frag
);
1589 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1590 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1591 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1596 else if (op1
->am
== 1)
1598 /* MOVA z16(Rsrc), Rdst. */
1599 bin
|= 0x30 | (op1
->reg
<< 8) | op2
->reg
;
1600 frag
= frag_more (4);
1601 where
= frag
- frag_now
->fr_literal
;
1602 bfd_putl16 ((bfd_vma
) bin
, frag
);
1603 if (op1
->exp
.X_op
== O_constant
)
1605 if (op1
->exp
.X_add_number
> 0xffff
1606 || op1
->exp
.X_add_number
< -(0x7fff))
1608 if (error_message_return
!= NULL
)
1609 * error_message_return
= _("index value too big for %s");
1612 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1616 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1617 fix_new_exp (frag_now
, where
+ 2, 2, &(op1
->exp
), FALSE
,
1619 BFD_RELOC_MSP430X_PCR16
:
1620 BFD_RELOC_MSP430X_ABS16
);
1625 if (error_message_return
!= NULL
)
1626 * error_message_return
= _("unexpected addressing mode for %s");
1629 else if (op1
->am
== 0)
1631 /* MOVA Rsrc, ... */
1632 if (op2
->mode
== OP_REG
)
1634 bin
|= 0xc0 | (op1
->reg
<< 8) | op2
->reg
;
1635 frag
= frag_more (2);
1636 where
= frag
- frag_now
->fr_literal
;
1637 bfd_putl16 ((bfd_vma
) bin
, frag
);
1640 else if (op2
->am
== 1)
1644 /* MOVA Rsrc, &abs20. */
1645 bin
|= 0x60 | (op1
->reg
<< 8);
1646 frag
= frag_more (4);
1647 where
= frag
- frag_now
->fr_literal
;
1648 if (op2
->exp
.X_op
== O_constant
)
1650 bin
|= (op2
->exp
.X_add_number
>> 16) & 0xf;
1651 bfd_putl16 ((bfd_vma
) bin
, frag
);
1652 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1656 bfd_putl16 ((bfd_vma
) bin
, frag
);
1657 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1658 fix_new_exp (frag_now
, where
, 4, &(op2
->exp
), FALSE
,
1659 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
1664 /* MOVA Rsrc, z16(Rdst). */
1665 bin
|= 0x70 | (op1
->reg
<< 8) | op2
->reg
;
1666 frag
= frag_more (4);
1667 where
= frag
- frag_now
->fr_literal
;
1668 bfd_putl16 ((bfd_vma
) bin
, frag
);
1669 if (op2
->exp
.X_op
== O_constant
)
1671 if (op2
->exp
.X_add_number
> 0xffff
1672 || op2
->exp
.X_add_number
< -(0x7fff))
1674 if (error_message_return
!= NULL
)
1675 * error_message_return
= _("index value too big for %s");
1678 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1682 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1683 fix_new_exp (frag_now
, where
+ 2, 2, &(op2
->exp
), FALSE
,
1685 BFD_RELOC_MSP430X_PCR16
:
1686 BFD_RELOC_MSP430X_ABS16
);
1691 if (error_message_return
!= NULL
)
1692 * error_message_return
= _("unexpected addressing mode for %s");
1697 /* imm_op == FALSE. */
1699 if (op1
->reg
== 2 && op1
->am
== 1 && op1
->mode
== OP_EXP
)
1701 /* MOVA &abs20, Rdst. */
1702 if (op2
->mode
!= OP_REG
)
1704 if (error_message_return
!= NULL
)
1705 * error_message_return
= _("expected register as second argument of %s");
1709 if (op2
->reg
== 2 || op2
->reg
== 3)
1711 if (error_message_return
!= NULL
)
1712 * error_message_return
= _("constant generator destination register found in %s");
1716 bin
|= 0x20 | op2
->reg
;
1717 frag
= frag_more (4);
1718 where
= frag
- frag_now
->fr_literal
;
1719 if (op1
->exp
.X_op
== O_constant
)
1721 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1722 bfd_putl16 ((bfd_vma
) bin
, frag
);
1723 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1727 bfd_putl16 ((bfd_vma
) bin
, frag
);
1728 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1729 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1730 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1734 else if (op1
->mode
== OP_REG
)
1738 /* MOVA @Rsrc+, Rdst. */
1739 if (op2
->mode
!= OP_REG
)
1741 if (error_message_return
!= NULL
)
1742 * error_message_return
= _("expected register as second argument of %s");
1746 if (op2
->reg
== 2 || op2
->reg
== 3)
1748 if (error_message_return
!= NULL
)
1749 * error_message_return
= _("constant generator destination register found in %s");
1753 if (op1
->reg
== 2 || op1
->reg
== 3)
1755 if (error_message_return
!= NULL
)
1756 * error_message_return
= _("constant generator source register found in %s");
1760 bin
|= 0x10 | (op1
->reg
<< 8) | op2
->reg
;
1761 frag
= frag_more (2);
1762 where
= frag
- frag_now
->fr_literal
;
1763 bfd_putl16 ((bfd_vma
) bin
, frag
);
1766 else if (op1
->am
== 2)
1768 /* MOVA @Rsrc,Rdst */
1769 if (op2
->mode
!= OP_REG
)
1771 if (error_message_return
!= NULL
)
1772 * error_message_return
= _("expected register as second argument of %s");
1776 if (op2
->reg
== 2 || op2
->reg
== 3)
1778 if (error_message_return
!= NULL
)
1779 * error_message_return
= _("constant generator destination register found in %s");
1783 if (op1
->reg
== 2 || op1
->reg
== 3)
1785 if (error_message_return
!= NULL
)
1786 * error_message_return
= _("constant generator source register found in %s");
1790 bin
|= (op1
->reg
<< 8) | op2
->reg
;
1791 frag
= frag_more (2);
1792 where
= frag
- frag_now
->fr_literal
;
1793 bfd_putl16 ((bfd_vma
) bin
, frag
);
1798 if (error_message_return
!= NULL
)
1799 * error_message_return
= _("unexpected addressing mode for %s");
1804 static bfd_boolean check_for_nop
= FALSE
;
1806 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
1808 /* Parse instruction operands.
1809 Return binary opcode. */
1812 msp430_operands (struct msp430_opcode_s
* opcode
, char * line
)
1814 int bin
= opcode
->bin_opcode
; /* Opcode mask. */
1815 int insn_length
= 0;
1816 char l1
[MAX_OP_LEN
], l2
[MAX_OP_LEN
];
1819 struct msp430_operand_s op1
, op2
;
1821 static short ZEROS
= 0;
1822 bfd_boolean byte_op
, imm_op
;
1825 int extended
= 0x1800;
1826 bfd_boolean extended_op
= FALSE
;
1827 bfd_boolean addr_op
;
1828 const char * error_message
;
1829 static signed int repeat_count
= 0;
1830 bfd_boolean fix_emitted
;
1831 bfd_boolean nop_check_needed
= FALSE
;
1833 /* Opcode is the one from opcodes table
1834 line contains something like
1843 bfd_boolean check
= FALSE
;
1846 switch (TOLOWER (* line
))
1849 /* Byte operation. */
1850 bin
|= BYTE_OPERATION
;
1856 /* "Address" ops work on 20-bit values. */
1858 bin
|= BYTE_OPERATION
;
1863 /* Word operation - this is the default. */
1871 as_warn (_("no size modifier after period, .w assumed"));
1875 as_bad (_("unrecognised instruction size modifier .%c"),
1887 if (*line
&& ! ISSPACE (*line
))
1889 as_bad (_("junk found after instruction: %s.%s"),
1890 opcode
->name
, line
);
1894 /* Catch the case where the programmer has used a ".a" size modifier on an
1895 instruction that does not support it. Look for an alternative extended
1896 instruction that has the same name without the period. Eg: "add.a"
1897 becomes "adda". Although this not an officially supported way of
1898 specifing instruction aliases other MSP430 assemblers allow it. So we
1899 support it for compatibility purposes. */
1900 if (addr_op
&& opcode
->fmt
>= 0)
1902 char * old_name
= opcode
->name
;
1905 sprintf (real_name
, "%sa", old_name
);
1906 opcode
= hash_find (msp430_hash
, real_name
);
1909 as_bad (_("instruction %s.a does not exist"), old_name
);
1912 #if 0 /* Enable for debugging. */
1913 as_warn ("treating %s.a as %s", old_name
, real_name
);
1916 bin
= opcode
->bin_opcode
;
1919 if (opcode
->fmt
!= -1
1920 && opcode
->insn_opnumb
1921 && (!*line
|| *line
== '\n'))
1923 as_bad (_("instruction %s requires %d operand(s)"),
1924 opcode
->name
, opcode
->insn_opnumb
);
1928 memset (l1
, 0, sizeof (l1
));
1929 memset (l2
, 0, sizeof (l2
));
1930 memset (&op1
, 0, sizeof (op1
));
1931 memset (&op2
, 0, sizeof (op2
));
1935 if ((fmt
= opcode
->fmt
) < 0)
1937 if (! target_is_430x ())
1939 as_bad (_("instruction %s requires MSP430X mcu"),
1950 /* If requested set the extended instruction repeat count. */
1953 if (repeat_count
> 0)
1954 extended
|= (repeat_count
- 1);
1956 extended
|= (1 << 7) | (- repeat_count
);
1959 as_bad (_("unable to repeat %s insn"), opcode
->name
);
1964 if (check_for_nop
&& is_opcode ("nop"))
1965 check_for_nop
= FALSE
;
1969 case 0: /* Emulated. */
1970 switch (opcode
->insn_opnumb
)
1973 if (is_opcode ("eint") || is_opcode ("dint"))
1977 if (warn_interrupt_nops
)
1979 if (gen_interrupt_nops
)
1980 as_warn (_("NOP inserted between two instructions that change interrupt state"));
1982 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
1985 if (gen_interrupt_nops
)
1987 /* Emit a NOP between interrupt enable/disable.
1988 See 1.3.4.1 of the MSP430x5xx User Guide. */
1990 frag
= frag_more (2);
1991 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
1995 nop_check_needed
= TRUE
;
1998 /* Set/clear bits instructions. */
2002 extended
|= BYTE_OPERATION
;
2004 /* Emit the extension word. */
2006 frag
= frag_more (2);
2007 bfd_putl16 (extended
, frag
);
2011 frag
= frag_more (2);
2012 bfd_putl16 ((bfd_vma
) bin
, frag
);
2013 dwarf2_emit_insn (insn_length
);
2017 /* Something which works with destination operand. */
2018 line
= extract_operand (line
, l1
, sizeof (l1
));
2019 res
= msp430_dstoperand (&op1
, l1
, opcode
->bin_opcode
, extended_op
, TRUE
);
2023 bin
|= (op1
.reg
| (op1
.am
<< 7));
2025 if (is_opcode ("clr") && bin
== 0x4302 /* CLR R2*/)
2029 if (warn_interrupt_nops
)
2031 if (gen_interrupt_nops
)
2032 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2034 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2037 if (gen_interrupt_nops
)
2039 /* Emit a NOP between interrupt enable/disable.
2040 See 1.3.4.1 of the MSP430x5xx User Guide. */
2042 frag
= frag_more (2);
2043 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2047 nop_check_needed
= TRUE
;
2050 /* Compute the entire instruction length, in bytes. */
2051 op_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2052 insn_length
+= op_length
;
2053 frag
= frag_more (op_length
);
2054 where
= frag
- frag_now
->fr_literal
;
2059 extended
|= BYTE_OPERATION
;
2061 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2063 as_bad (_("repeat instruction used with non-register mode instruction"));
2067 if (op1
.mode
== OP_EXP
)
2069 if (op1
.exp
.X_op
== O_constant
)
2070 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2072 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2073 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2074 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2076 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2077 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2080 /* Emit the extension word. */
2081 bfd_putl16 (extended
, frag
);
2086 bfd_putl16 ((bfd_vma
) bin
, frag
);
2090 if (op1
.mode
== OP_EXP
)
2092 if (op1
.exp
.X_op
== O_constant
)
2094 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2098 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2103 fix_new_exp (frag_now
, where
, 2,
2104 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2106 fix_new_exp (frag_now
, where
, 2,
2107 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2112 dwarf2_emit_insn (insn_length
);
2116 /* Shift instruction. */
2117 line
= extract_operand (line
, l1
, sizeof (l1
));
2118 strncpy (l2
, l1
, sizeof (l2
));
2119 l2
[sizeof (l2
) - 1] = '\0';
2120 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2121 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2124 break; /* An error occurred. All warnings were done before. */
2126 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2) + (op2
.ol
* 2);
2127 frag
= frag_more (insn_length
);
2128 where
= frag
- frag_now
->fr_literal
;
2130 if (target_is_430xv2 ()
2131 && op1
.mode
== OP_REG
2133 && (is_opcode ("rlax")
2134 || is_opcode ("rlcx")
2135 || is_opcode ("rla")
2136 || is_opcode ("rlc")))
2138 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2145 extended
|= BYTE_OPERATION
;
2147 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2149 as_bad (_("repeat instruction used with non-register mode instruction"));
2153 if (op1
.mode
== OP_EXP
)
2155 if (op1
.exp
.X_op
== O_constant
)
2156 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2158 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2159 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2160 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2162 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2163 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2166 if (op2
.mode
== OP_EXP
)
2168 if (op2
.exp
.X_op
== O_constant
)
2169 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2171 else if (op1
.mode
== OP_EXP
)
2172 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2173 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2174 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2176 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2177 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2178 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2181 /* Emit the extension word. */
2182 bfd_putl16 (extended
, frag
);
2187 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2188 bfd_putl16 ((bfd_vma
) bin
, frag
);
2192 if (op1
.mode
== OP_EXP
)
2194 if (op1
.exp
.X_op
== O_constant
)
2196 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2200 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2204 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2205 fix_new_exp (frag_now
, where
, 2,
2206 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2208 fix_new_exp (frag_now
, where
, 2,
2209 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2216 if (op2
.mode
== OP_EXP
)
2218 if (op2
.exp
.X_op
== O_constant
)
2220 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2224 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2228 if (op2
.reg
) /* Not PC relative. */
2229 fix_new_exp (frag_now
, where
, 2,
2230 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
2232 fix_new_exp (frag_now
, where
, 2,
2233 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2238 dwarf2_emit_insn (insn_length
);
2242 /* Branch instruction => mov dst, r0. */
2245 as_bad ("Internal error: state 0/3 not coded for extended instructions");
2249 line
= extract_operand (line
, l1
, sizeof (l1
));
2250 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, FALSE
);
2256 bin
|= ((op1
.reg
<< 8) | (op1
.am
<< 4));
2257 op_length
= 2 + 2 * op1
.ol
;
2258 frag
= frag_more (op_length
);
2259 where
= frag
- frag_now
->fr_literal
;
2260 bfd_putl16 ((bfd_vma
) bin
, frag
);
2262 if (op1
.mode
== OP_EXP
)
2264 if (op1
.exp
.X_op
== O_constant
)
2266 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
+ 2);
2272 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2274 if (op1
.reg
|| op1
.am
== 3)
2275 fix_new_exp (frag_now
, where
, 2,
2276 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2278 fix_new_exp (frag_now
, where
, 2,
2279 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2283 dwarf2_emit_insn (insn_length
+ op_length
);
2287 /* CALLA instructions. */
2288 fix_emitted
= FALSE
;
2290 line
= extract_operand (line
, l1
, sizeof (l1
));
2293 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
,
2294 extended_op
, FALSE
);
2300 op_length
= 2 + 2 * op1
.ol
;
2301 frag
= frag_more (op_length
);
2302 where
= frag
- frag_now
->fr_literal
;
2310 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2311 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2314 else if (op1
.am
== 1)
2320 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2321 BFD_RELOC_MSP430X_PCR20_CALL
);
2325 bin
|= 0x50 | op1
.reg
;
2327 else if (op1
.am
== 0)
2328 bin
|= 0x40 | op1
.reg
;
2330 else if (op1
.am
== 1)
2334 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2335 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2338 else if (op1
.am
== 2)
2339 bin
|= 0x60 | op1
.reg
;
2340 else if (op1
.am
== 3)
2341 bin
|= 0x70 | op1
.reg
;
2343 bfd_putl16 ((bfd_vma
) bin
, frag
);
2345 if (op1
.mode
== OP_EXP
)
2349 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1
.ol
);
2353 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2356 fix_new_exp (frag_now
, where
+ 2, 2,
2357 &(op1
.exp
), FALSE
, BFD_RELOC_16
);
2360 dwarf2_emit_insn (insn_length
+ op_length
);
2368 /* [POP|PUSH]M[.A] #N, Rd */
2369 line
= extract_operand (line
, l1
, sizeof (l1
));
2370 line
= extract_operand (line
, l2
, sizeof (l2
));
2374 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2377 parse_exp (l1
+ 1, &(op1
.exp
));
2378 if (op1
.exp
.X_op
!= O_constant
)
2380 as_bad (_("expected constant expression for first argument of %s"),
2385 if ((reg
= check_reg (l2
)) == -1)
2387 as_bad (_("expected register as second argument of %s"),
2393 frag
= frag_more (op_length
);
2394 where
= frag
- frag_now
->fr_literal
;
2395 bin
= opcode
->bin_opcode
;
2398 n
= op1
.exp
.X_add_number
;
2399 bin
|= (n
- 1) << 4;
2400 if (is_opcode ("pushm"))
2404 if (reg
- n
+ 1 < 0)
2406 as_bad (_("Too many registers popped"));
2410 /* CPU21 errata: cannot use POPM to restore the SR register. */
2411 if (target_is_430xv2 ()
2412 && (reg
- n
+ 1 < 3)
2414 && is_opcode ("popm"))
2416 as_bad (_("Cannot use POPM to restore the SR register"));
2420 bin
|= (reg
- n
+ 1);
2423 bfd_putl16 ((bfd_vma
) bin
, frag
);
2424 dwarf2_emit_insn (op_length
);
2433 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
2434 if (extended
& 0xff)
2436 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2440 line
= extract_operand (line
, l1
, sizeof (l1
));
2441 line
= extract_operand (line
, l2
, sizeof (l2
));
2445 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2448 parse_exp (l1
+ 1, &(op1
.exp
));
2449 if (op1
.exp
.X_op
!= O_constant
)
2451 as_bad (_("expected constant expression for first argument of %s"),
2455 n
= op1
.exp
.X_add_number
;
2458 as_bad (_("expected first argument of %s to be in the range 1-4"),
2463 if ((reg
= check_reg (l2
)) == -1)
2465 as_bad (_("expected register as second argument of %s"),
2470 if (target_is_430xv2 () && reg
== 0)
2472 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2477 frag
= frag_more (op_length
);
2478 where
= frag
- frag_now
->fr_literal
;
2480 bin
= opcode
->bin_opcode
;
2483 bin
|= (n
- 1) << 10;
2486 bfd_putl16 ((bfd_vma
) bin
, frag
);
2487 dwarf2_emit_insn (op_length
);
2495 /* RRUX: Synthetic unsigned right shift of a register by one bit. */
2496 if (extended
& 0xff)
2498 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2502 line
= extract_operand (line
, l1
, sizeof (l1
));
2503 if ((reg
= check_reg (l1
)) == -1)
2505 as_bad (_("expected register as argument of %s"),
2510 if (target_is_430xv2 () && reg
== 0)
2512 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2518 /* Tricky - there is no single instruction that will do this.
2519 Encode as: RRA.B rN { BIC.B #0x80, rN */
2521 frag
= frag_more (op_length
);
2522 where
= frag
- frag_now
->fr_literal
;
2524 bfd_putl16 ((bfd_vma
) bin
, frag
);
2525 dwarf2_emit_insn (2);
2527 bfd_putl16 ((bfd_vma
) bin
, frag
+ 2);
2529 bfd_putl16 ((bfd_vma
) bin
, frag
+ 4);
2530 dwarf2_emit_insn (4);
2534 /* Encode as RRUM[.A] rN. */
2535 bin
= opcode
->bin_opcode
;
2540 frag
= frag_more (op_length
);
2541 where
= frag
- frag_now
->fr_literal
;
2542 bfd_putl16 ((bfd_vma
) bin
, frag
);
2543 dwarf2_emit_insn (op_length
);
2550 bfd_boolean need_reloc
= FALSE
;
2554 /* ADDA, CMPA and SUBA address instructions. */
2555 if (extended
& 0xff)
2557 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2561 line
= extract_operand (line
, l1
, sizeof (l1
));
2562 line
= extract_operand (line
, l2
, sizeof (l2
));
2564 bin
= opcode
->bin_opcode
;
2568 parse_exp (l1
+ 1, &(op1
.exp
));
2570 if (op1
.exp
.X_op
== O_constant
)
2572 n
= op1
.exp
.X_add_number
;
2573 if (n
> 0xfffff || n
< - (0x7ffff))
2575 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
2580 bin
|= ((n
>> 16) & 0xf) << 8;
2592 if ((n
= check_reg (l1
)) == -1)
2594 as_bad (_("expected register name or constant as first argument of %s"),
2599 bin
|= (n
<< 8) | (1 << 6);
2603 if ((reg
= check_reg (l2
)) == -1)
2605 as_bad (_("expected register as second argument of %s"),
2610 frag
= frag_more (op_length
);
2611 where
= frag
- frag_now
->fr_literal
;
2614 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2615 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
2617 bfd_putl16 ((bfd_vma
) bin
, frag
);
2619 bfd_putl16 ((bfd_vma
) (n
& 0xffff), frag
+ 2);
2620 dwarf2_emit_insn (op_length
);
2624 case 9: /* MOVA, BRA, RETA. */
2626 bin
= opcode
->bin_opcode
;
2628 if (is_opcode ("reta"))
2630 /* The RETA instruction does not take any arguments.
2631 The implicit first argument is @SP+.
2632 The implicit second argument is PC. */
2642 line
= extract_operand (line
, l1
, sizeof (l1
));
2643 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2644 &imm_op
, extended_op
, FALSE
);
2646 if (is_opcode ("bra"))
2648 /* This is the BRA synthetic instruction.
2649 The second argument is always PC. */
2655 line
= extract_operand (line
, l2
, sizeof (l2
));
2656 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
,
2661 break; /* Error occurred. All warnings were done before. */
2664 /* Only a restricted subset of the normal MSP430 addressing modes
2665 are supported here, so check for the ones that are allowed. */
2666 if ((op_length
= try_encode_mova (imm_op
, bin
, & op1
, & op2
,
2667 & error_message
)) == 0)
2669 as_bad (error_message
, opcode
->name
);
2672 dwarf2_emit_insn (op_length
);
2676 line
= extract_operand (line
, l1
, sizeof l1
);
2677 /* The RPT instruction only accepted immediates and registers. */
2680 parse_exp (l1
+ 1, &(op1
.exp
));
2681 if (op1
.exp
.X_op
!= O_constant
)
2683 as_bad (_("expected constant value as argument to RPT"));
2686 if (op1
.exp
.X_add_number
< 1
2687 || op1
.exp
.X_add_number
> (1 << 4))
2689 as_bad (_("expected constant in the range 2..16"));
2693 /* We silently accept and ignore a repeat count of 1. */
2694 if (op1
.exp
.X_add_number
> 1)
2695 repeat_count
= op1
.exp
.X_add_number
;
2701 if ((reg
= check_reg (l1
)) != -1)
2704 as_warn (_("PC used as an argument to RPT"));
2706 repeat_count
= - reg
;
2710 as_bad (_("expected constant or register name as argument to RPT insn"));
2717 as_bad (_("Illegal emulated instruction "));
2722 case 1: /* Format 1, double operand. */
2723 line
= extract_operand (line
, l1
, sizeof (l1
));
2724 line
= extract_operand (line
, l2
, sizeof (l2
));
2725 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2726 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2729 break; /* Error occurred. All warnings were done before. */
2732 && is_opcode ("movx")
2734 && msp430_enable_relax
)
2736 /* This is the MOVX.A instruction. See if we can convert
2737 it into the MOVA instruction instead. This saves 2 bytes. */
2738 if ((op_length
= try_encode_mova (imm_op
, 0x0000, & op1
, & op2
,
2741 dwarf2_emit_insn (op_length
);
2746 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2748 if ( (is_opcode ("bic") && bin
== 0xc232)
2749 || (is_opcode ("bis") && bin
== 0xd232)
2750 || (is_opcode ("mov") && op2
.mode
== OP_REG
&& op2
.reg
== 2))
2754 if (warn_interrupt_nops
)
2756 if (gen_interrupt_nops
)
2757 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2759 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2762 if (gen_interrupt_nops
)
2764 /* Emit a NOP between interrupt enable/disable.
2765 See 1.3.4.1 of the MSP430x5xx User Guide. */
2767 frag
= frag_more (2);
2768 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2772 nop_check_needed
= TRUE
;
2775 /* Compute the entire length of the instruction in bytes. */
2776 op_length
= (extended_op
? 2 : 0) /* The extension word. */
2777 + 2 /* The opcode */
2778 + (2 * op1
.ol
) /* The first operand. */
2779 + (2 * op2
.ol
); /* The second operand. */
2781 insn_length
+= op_length
;
2782 frag
= frag_more (op_length
);
2783 where
= frag
- frag_now
->fr_literal
;
2788 extended
|= BYTE_OPERATION
;
2790 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2792 as_bad (_("repeat instruction used with non-register mode instruction"));
2796 /* If necessary, emit a reloc to update the extension word. */
2797 if (op1
.mode
== OP_EXP
)
2799 if (op1
.exp
.X_op
== O_constant
)
2800 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2802 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2803 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2804 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2806 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2807 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2810 if (op2
.mode
== OP_EXP
)
2812 if (op2
.exp
.X_op
== O_constant
)
2813 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2815 else if (op1
.mode
== OP_EXP
)
2816 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2817 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2818 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2821 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2822 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2823 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2826 /* Emit the extension word. */
2827 bfd_putl16 (extended
, frag
);
2832 bfd_putl16 ((bfd_vma
) bin
, frag
);
2836 if (op1
.mode
== OP_EXP
)
2838 if (op1
.exp
.X_op
== O_constant
)
2840 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2844 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2848 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2849 fix_new_exp (frag_now
, where
, 2,
2850 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2852 fix_new_exp (frag_now
, where
, 2,
2853 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2861 if (op2
.mode
== OP_EXP
)
2863 if (op2
.exp
.X_op
== O_constant
)
2865 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2869 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2873 if (op2
.reg
) /* Not PC relative. */
2874 fix_new_exp (frag_now
, where
, 2,
2875 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
2877 fix_new_exp (frag_now
, where
, 2,
2878 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2883 dwarf2_emit_insn (insn_length
);
2886 case 2: /* Single-operand mostly instr. */
2887 if (opcode
->insn_opnumb
== 0)
2889 /* reti instruction. */
2891 frag
= frag_more (2);
2892 bfd_putl16 ((bfd_vma
) bin
, frag
);
2893 dwarf2_emit_insn (insn_length
);
2897 line
= extract_operand (line
, l1
, sizeof (l1
));
2898 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2899 &imm_op
, extended_op
, TRUE
);
2901 break; /* Error in operand. */
2903 if (target_is_430xv2 ()
2904 && op1
.mode
== OP_REG
2906 && (is_opcode ("rrax")
2907 || is_opcode ("rrcx")
2908 || is_opcode ("rra")
2909 || is_opcode ("rrc")))
2911 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2915 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2916 frag
= frag_more (insn_length
);
2917 where
= frag
- frag_now
->fr_literal
;
2921 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
2923 /* These two instructions use a special
2924 encoding of the A/L and B/W bits. */
2925 bin
&= ~ BYTE_OPERATION
;
2929 as_bad (_("%s instruction does not accept a .b suffix"),
2934 extended
|= BYTE_OPERATION
;
2937 extended
|= BYTE_OPERATION
;
2939 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2941 as_bad (_("repeat instruction used with non-register mode instruction"));
2945 if (op1
.mode
== OP_EXP
)
2947 if (op1
.exp
.X_op
== O_constant
)
2948 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2950 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2951 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2952 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2954 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2955 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2958 /* Emit the extension word. */
2959 bfd_putl16 (extended
, frag
);
2964 bin
|= op1
.reg
| (op1
.am
<< 4);
2965 bfd_putl16 ((bfd_vma
) bin
, frag
);
2969 if (op1
.mode
== OP_EXP
)
2971 if (op1
.exp
.X_op
== O_constant
)
2973 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2977 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2981 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2982 fix_new_exp (frag_now
, where
, 2,
2983 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2985 fix_new_exp (frag_now
, where
, 2,
2986 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2991 dwarf2_emit_insn (insn_length
);
2994 case 3: /* Conditional jumps instructions. */
2995 line
= extract_operand (line
, l1
, sizeof (l1
));
2996 /* l1 is a label. */
3005 parse_exp (m
, &exp
);
3007 /* In order to handle something like:
3011 jz 4 ; skip next 4 bytes
3014 nop ; will jump here if r5 positive or zero
3016 jCOND -n ;assumes jump n bytes backward:
3026 jCOND $n ; jump from PC in either direction. */
3028 if (exp
.X_op
== O_constant
)
3030 int x
= exp
.X_add_number
;
3034 as_warn (_("Even number required. Rounded to %d"), x
+ 1);
3038 if ((*l1
== '$' && x
> 0) || x
< 0)
3043 if (x
> 512 || x
< -511)
3045 as_bad (_("Wrong displacement %d"), x
<< 1);
3050 frag
= frag_more (2); /* Instr size is 1 word. */
3053 bfd_putl16 ((bfd_vma
) bin
, frag
);
3055 else if (exp
.X_op
== O_symbol
&& *l1
!= '$')
3058 frag
= frag_more (2); /* Instr size is 1 word. */
3059 where
= frag
- frag_now
->fr_literal
;
3060 fix_new_exp (frag_now
, where
, 2,
3061 &exp
, TRUE
, BFD_RELOC_MSP430_10_PCREL
);
3063 bfd_putl16 ((bfd_vma
) bin
, frag
);
3065 else if (*l1
== '$')
3067 as_bad (_("instruction requires label sans '$'"));
3071 ("instruction requires label or value in range -511:512"));
3072 dwarf2_emit_insn (insn_length
);
3077 as_bad (_("instruction requires label"));
3082 case 4: /* Extended jumps. */
3083 if (!msp430_enable_polys
)
3085 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3089 line
= extract_operand (line
, l1
, sizeof (l1
));
3095 /* Ignore absolute addressing. make it PC relative anyway. */
3096 if (*m
== '#' || *m
== '$')
3099 parse_exp (m
, & exp
);
3100 if (exp
.X_op
== O_symbol
)
3102 /* Relaxation required. */
3103 struct rcodes_s rc
= msp430_rcodes
[opcode
->insn_opnumb
];
3105 if (target_is_430x ())
3106 rc
= msp430x_rcodes
[opcode
->insn_opnumb
];
3108 /* The parameter to dwarf2_emit_insn is actually the offset to
3109 the start of the insn from the fix piece of instruction that
3110 was emitted. Since next fragments may have variable size we
3111 tie debug info to the beginning of the instruction. */
3113 frag
= frag_more (8);
3114 dwarf2_emit_insn (0);
3115 bfd_putl16 ((bfd_vma
) rc
.sop
, frag
);
3116 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3118 ENCODE_RELAX (rc
.lpos
, STATE_BITS10
),
3120 0, /* Offset is zero if jump dist less than 1K. */
3126 as_bad (_("instruction requires label"));
3129 case 5: /* Emulated extended branches. */
3130 if (!msp430_enable_polys
)
3132 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3135 line
= extract_operand (line
, l1
, sizeof (l1
));
3141 /* Ignore absolute addressing. make it PC relative anyway. */
3142 if (*m
== '#' || *m
== '$')
3145 parse_exp (m
, & exp
);
3146 if (exp
.X_op
== O_symbol
)
3148 /* Relaxation required. */
3149 struct hcodes_s hc
= msp430_hcodes
[opcode
->insn_opnumb
];
3151 if (target_is_430x ())
3152 hc
= msp430x_hcodes
[opcode
->insn_opnumb
];
3155 frag
= frag_more (8);
3156 dwarf2_emit_insn (0);
3157 bfd_putl16 ((bfd_vma
) hc
.op0
, frag
);
3158 bfd_putl16 ((bfd_vma
) hc
.op1
, frag
+2);
3160 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3161 ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
), /* Wild guess. */
3163 0, /* Offset is zero if jump dist less than 1K. */
3169 as_bad (_("instruction requires label"));
3173 as_bad (_("Illegal instruction or not implemented opcode."));
3176 input_line_pointer
= line
;
3177 check_for_nop
= nop_check_needed
;
3182 md_assemble (char * str
)
3184 struct msp430_opcode_s
* opcode
;
3188 str
= skip_space (str
); /* Skip leading spaces. */
3189 str
= extract_cmd (str
, cmd
, sizeof (cmd
) - 1);
3193 char a
= TOLOWER (cmd
[i
]);
3200 as_bad (_("can't find opcode "));
3204 opcode
= (struct msp430_opcode_s
*) hash_find (msp430_hash
, cmd
);
3208 as_bad (_("unknown opcode `%s'"), cmd
);
3213 char *__t
= input_line_pointer
;
3215 msp430_operands (opcode
, str
);
3216 input_line_pointer
= __t
;
3220 /* GAS will call this function for each section at the end of the assembly,
3221 to permit the CPU backend to adjust the alignment of a section. */
3224 md_section_align (asection
* seg
, valueT addr
)
3226 int align
= bfd_get_section_alignment (stdoutput
, seg
);
3228 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
3231 /* If you define this macro, it should return the offset between the
3232 address of a PC relative fixup and the position from which the PC
3233 relative adjustment should be made. On many processors, the base
3234 of a PC relative instruction is the next instruction, so this
3235 macro would return the length of an instruction. */
3238 md_pcrel_from_section (fixS
* fixp
, segT sec
)
3240 if (fixp
->fx_addsy
!= (symbolS
*) NULL
3241 && (!S_IS_DEFINED (fixp
->fx_addsy
)
3242 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
3245 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3248 /* Replaces standard TC_FORCE_RELOCATION_LOCAL.
3249 Now it handles the situation when relocations
3250 have to be passed to linker. */
3252 msp430_force_relocation_local (fixS
*fixp
)
3254 if (fixp
->fx_r_type
== BFD_RELOC_MSP430_10_PCREL
)
3258 if (msp430_enable_polys
3259 && !msp430_enable_relax
)
3262 return (!fixp
->fx_pcrel
3263 || generic_force_reloc (fixp
));
3267 /* GAS will call this for each fixup. It should store the correct
3268 value in the object file. */
3270 md_apply_fix (fixS
* fixp
, valueT
* valuep
, segT seg
)
3272 unsigned char * where
;
3276 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
3281 else if (fixp
->fx_pcrel
)
3283 segT s
= S_GET_SEGMENT (fixp
->fx_addsy
);
3285 if (fixp
->fx_addsy
&& (s
== seg
|| s
== absolute_section
))
3287 /* FIXME: We can appear here only in case if we perform a pc
3288 relative jump to the label which is i) global, ii) locally
3289 defined or this is a jump to an absolute symbol.
3290 If this is an absolute symbol -- everything is OK.
3291 If this is a global label, we've got a symbol value defined
3293 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
3294 from this section start
3295 2. *valuep will contain the real offset from jump insn to the
3297 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
3298 will be incorrect. Therefore remove s_get_value. */
3299 value
= /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep
;
3307 value
= fixp
->fx_offset
;
3309 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
3311 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3313 value
-= S_GET_VALUE (fixp
->fx_subsy
);
3319 fixp
->fx_no_overflow
= 1;
3321 /* If polymorphs are enabled and relax disabled.
3322 do not kill any relocs and pass them to linker. */
3323 if (msp430_enable_polys
3324 && !msp430_enable_relax
)
3327 || S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
3328 fixp
->fx_done
= 1; /* It is ok to kill 'abs' reloc. */
3335 /* Fetch the instruction, insert the fully resolved operand
3336 value, and stuff the instruction back again. */
3337 where
= (unsigned char *) fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
3339 insn
= bfd_getl16 (where
);
3341 switch (fixp
->fx_r_type
)
3343 case BFD_RELOC_MSP430_10_PCREL
:
3345 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3346 _("odd address operand: %ld"), value
);
3348 /* Jumps are in words. */
3350 --value
; /* Correct PC. */
3352 if (value
< -512 || value
> 511)
3353 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3354 _("operand out of range: %ld"), value
);
3356 value
&= 0x3ff; /* get rid of extended sign */
3357 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
3360 case BFD_RELOC_MSP430X_PCR16
:
3361 case BFD_RELOC_MSP430_RL_PCREL
:
3362 case BFD_RELOC_MSP430_16_PCREL
:
3364 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3365 _("odd address operand: %ld"), value
);
3368 case BFD_RELOC_MSP430_16_PCREL_BYTE
:
3369 /* Nothing to be corrected here. */
3370 if (value
< -32768 || value
> 65536)
3371 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3372 _("operand out of range: %ld"), value
);
3375 case BFD_RELOC_MSP430X_ABS16
:
3376 case BFD_RELOC_MSP430_16
:
3378 case BFD_RELOC_MSP430_16_BYTE
:
3379 value
&= 0xffff; /* Get rid of extended sign. */
3380 bfd_putl16 ((bfd_vma
) value
, where
);
3383 case BFD_RELOC_MSP430_ABS_HI16
:
3385 value
&= 0xffff; /* Get rid of extended sign. */
3386 bfd_putl16 ((bfd_vma
) value
, where
);
3390 bfd_putl16 ((bfd_vma
) value
, where
);
3393 case BFD_RELOC_MSP430_ABS8
:
3395 bfd_put_8 (NULL
, (bfd_vma
) value
, where
);
3398 case BFD_RELOC_MSP430X_ABS20_EXT_SRC
:
3399 case BFD_RELOC_MSP430X_PCR20_EXT_SRC
:
3400 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3402 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 7) | insn
), where
);
3405 case BFD_RELOC_MSP430X_ABS20_ADR_SRC
:
3406 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3408 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 8) | insn
), where
);
3411 case BFD_RELOC_MSP430X_ABS20_EXT_ODST
:
3412 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3414 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3417 case BFD_RELOC_MSP430X_PCR20_CALL
:
3418 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3420 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3423 case BFD_RELOC_MSP430X_ABS20_EXT_DST
:
3424 case BFD_RELOC_MSP430X_PCR20_EXT_DST
:
3425 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3427 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3430 case BFD_RELOC_MSP430X_PCR20_EXT_ODST
:
3431 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3433 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3436 case BFD_RELOC_MSP430X_ABS20_ADR_DST
:
3437 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3439 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3443 as_fatal (_("line %d: unknown relocation type: 0x%x"),
3444 fixp
->fx_line
, fixp
->fx_r_type
);
3450 fixp
->fx_addnumber
= value
;
3455 S_IS_GAS_LOCAL (symbolS
* s
)
3462 name
= S_GET_NAME (s
);
3463 len
= strlen (name
) - 1;
3465 return name
[len
] == 1 || name
[len
] == 2;
3468 /* GAS will call this to generate a reloc, passing the resulting reloc
3469 to `bfd_install_relocation'. This currently works poorly, as
3470 `bfd_install_relocation' often does the wrong thing, and instances of
3471 `tc_gen_reloc' have been written to work around the problems, which
3472 in turns makes it difficult to fix `bfd_install_relocation'. */
3474 /* If while processing a fixup, a reloc really needs to be created
3475 then it is done here. */
3478 tc_gen_reloc (asection
* seg ATTRIBUTE_UNUSED
, fixS
* fixp
)
3480 static arelent
* no_relocs
= NULL
;
3481 static arelent
* relocs
[MAX_RELOC_EXPANSION
+ 1];
3484 reloc
= xmalloc (sizeof (arelent
));
3485 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3486 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3488 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3490 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3491 _("reloc %d not supported by object file format"),
3492 (int) fixp
->fx_r_type
);
3501 && S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3503 fixp
->fx_offset
-= S_GET_VALUE (fixp
->fx_subsy
);
3504 fixp
->fx_subsy
= NULL
;
3507 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
3509 asection
*asec
, *ssec
;
3511 asec
= S_GET_SEGMENT (fixp
->fx_addsy
);
3512 ssec
= S_GET_SEGMENT (fixp
->fx_subsy
);
3514 /* If we have a difference between two different, non-absolute symbols
3515 we must generate two relocs (one for each symbol) and allow the
3516 linker to resolve them - relaxation may change the distances between
3517 symbols, even local symbols defined in the same section.
3519 Unfortunately we cannot do this with assembler generated local labels
3520 because there can be multiple incarnations of the same label, with
3521 exactly the same name, in any given section and the linker will have
3522 no way to identify the correct one. Instead we just have to hope
3523 that no relaxtion will occur between the local label and the other
3524 symbol in the expression.
3526 Similarly we have to compute differences between symbols in the .eh_frame
3527 section as the linker is not smart enough to apply relocations there
3528 before attempting to process it. */
3529 if ((ssec
!= absolute_section
|| asec
!= absolute_section
)
3530 && (fixp
->fx_addsy
!= fixp
->fx_subsy
)
3531 && strcmp (ssec
->name
, ".eh_frame") != 0
3532 && ! S_IS_GAS_LOCAL (fixp
->fx_addsy
)
3533 && ! S_IS_GAS_LOCAL (fixp
->fx_subsy
))
3535 arelent
* reloc2
= xmalloc (sizeof * reloc
);
3540 reloc2
->address
= reloc
->address
;
3541 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
,
3542 BFD_RELOC_MSP430_SYM_DIFF
);
3543 reloc2
->addend
= - S_GET_VALUE (fixp
->fx_subsy
);
3545 if (ssec
== absolute_section
)
3546 reloc2
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3549 reloc2
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3550 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_subsy
);
3553 reloc
->addend
= fixp
->fx_offset
;
3554 if (asec
== absolute_section
)
3556 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
3557 reloc
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3561 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3562 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3571 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3573 reloc
->addend
= (S_GET_VALUE (fixp
->fx_addsy
)
3574 - S_GET_VALUE (fixp
->fx_subsy
) + fixp
->fx_offset
);
3576 switch (fixp
->fx_r_type
)
3579 md_number_to_chars (fixpos
, reloc
->addend
, 1);
3583 md_number_to_chars (fixpos
, reloc
->addend
, 2);
3587 md_number_to_chars (fixpos
, reloc
->addend
, 3);
3591 md_number_to_chars (fixpos
, reloc
->addend
, 4);
3596 = (asymbol
**) bfd_abs_section_ptr
->symbol_ptr_ptr
;
3607 if (fixp
->fx_r_type
== BFD_RELOC_MSP430X_ABS16
3608 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
3610 bfd_vma amount
= S_GET_VALUE (fixp
->fx_addsy
);
3611 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3613 md_number_to_chars (fixpos
, amount
, 2);
3618 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3619 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3620 reloc
->addend
= fixp
->fx_offset
;
3622 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3623 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3624 reloc
->address
= fixp
->fx_offset
;
3631 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
3632 asection
* segment_type ATTRIBUTE_UNUSED
)
3634 if (fragP
->fr_symbol
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
3636 /* This is a jump -> pcrel mode. Nothing to do much here.
3637 Return value == 2. */
3639 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_BITS10
);
3641 else if (fragP
->fr_symbol
)
3643 /* Its got a segment, but its not ours. Even if fr_symbol is in
3644 an absolute segment, we don't know a displacement until we link
3645 object files. So it will always be long. This also applies to
3646 labels in a subsegment of current. Liker may relax it to short
3647 jump later. Return value == 8. */
3649 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_WORD
);
3653 /* We know the abs value. may be it is a jump to fixed address.
3654 Impossible in our case, cause all constants already handled. */
3656 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_UNDEF
);
3659 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3663 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
,
3664 asection
* sec ATTRIBUTE_UNUSED
,
3670 struct rcodes_s
* cc
= NULL
;
3671 struct hcodes_s
* hc
= NULL
;
3673 switch (fragP
->fr_subtype
)
3675 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_BITS10
):
3676 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_BITS10
):
3677 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_BITS10
):
3678 /* We do not have to convert anything here.
3679 Just apply a fix. */
3680 rela
= BFD_RELOC_MSP430_10_PCREL
;
3683 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_WORD
):
3684 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_UNDEF
):
3685 /* Convert uncond branch jmp lab -> br lab. */
3686 if (target_is_430x ())
3687 cc
= msp430x_rcodes
+ 7;
3689 cc
= msp430_rcodes
+ 7;
3690 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3691 bfd_putl16 (cc
->lop0
, where
);
3692 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3696 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_WORD
):
3697 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_UNDEF
):
3699 /* Other simple branches. */
3700 int insn
= bfd_getl16 (fragP
->fr_opcode
);
3703 /* Find actual instruction. */
3704 if (target_is_430x ())
3706 for (i
= 0; i
< 7 && !cc
; i
++)
3707 if (msp430x_rcodes
[i
].sop
== insn
)
3708 cc
= msp430x_rcodes
+ i
;
3712 for (i
= 0; i
< 7 && !cc
; i
++)
3713 if (msp430_rcodes
[i
].sop
== insn
)
3714 cc
= & msp430_rcodes
[i
];
3717 if (!cc
|| !cc
->name
)
3718 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
3719 __FUNCTION__
, (long) insn
);
3720 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3721 bfd_putl16 (cc
->lop0
, where
);
3722 bfd_putl16 (cc
->lop1
, where
+ 2);
3723 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3728 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_WORD
):
3729 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_UNDEF
):
3730 if (target_is_430x ())
3731 cc
= msp430x_rcodes
+ 6;
3733 cc
= msp430_rcodes
+ 6;
3734 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3735 bfd_putl16 (cc
->lop0
, where
);
3736 bfd_putl16 (cc
->lop1
, where
+ 2);
3737 bfd_putl16 (cc
->lop2
, where
+ 4);
3738 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3742 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
):
3744 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3747 if (target_is_430x ())
3749 for (i
= 0; i
< 4 && !hc
; i
++)
3750 if (msp430x_hcodes
[i
].op1
== insn
)
3751 hc
= msp430x_hcodes
+ i
;
3755 for (i
= 0; i
< 4 && !hc
; i
++)
3756 if (msp430_hcodes
[i
].op1
== insn
)
3757 hc
= &msp430_hcodes
[i
];
3759 if (!hc
|| !hc
->name
)
3760 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3761 __FUNCTION__
, (long) insn
);
3762 rela
= BFD_RELOC_MSP430_10_PCREL
;
3763 /* Apply a fix for a first label if necessary.
3764 another fix will be applied to the next word of insn anyway. */
3766 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3767 fragP
->fr_offset
, TRUE
, rela
);
3773 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_WORD
):
3774 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_UNDEF
):
3776 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3779 if (target_is_430x ())
3781 for (i
= 0; i
< 4 && !hc
; i
++)
3782 if (msp430x_hcodes
[i
].op1
== insn
)
3783 hc
= msp430x_hcodes
+ i
;
3787 for (i
= 0; i
< 4 && !hc
; i
++)
3788 if (msp430_hcodes
[i
].op1
== insn
)
3789 hc
= & msp430_hcodes
[i
];
3791 if (!hc
|| !hc
->name
)
3792 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3793 __FUNCTION__
, (long) insn
);
3794 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3795 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3796 bfd_putl16 (hc
->lop0
, where
);
3797 bfd_putl16 (hc
->lop1
, where
+ 2);
3798 bfd_putl16 (hc
->lop2
, where
+ 4);
3804 as_fatal (_("internal inconsistency problem in %s: %lx"),
3805 __FUNCTION__
, (long) fragP
->fr_subtype
);
3809 /* Now apply fix. */
3810 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3811 fragP
->fr_offset
, TRUE
, rela
);
3812 /* Just fixed 2 bytes. */
3816 /* Relax fragment. Mostly stolen from hc11 and mcore
3817 which arches I think I know. */
3820 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
* fragP
,
3821 long stretch ATTRIBUTE_UNUSED
)
3826 const relax_typeS
*this_type
;
3827 const relax_typeS
*start_type
;
3828 relax_substateT next_state
;
3829 relax_substateT this_state
;
3830 const relax_typeS
*table
= md_relax_table
;
3832 /* Nothing to be done if the frag has already max size. */
3833 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_UNDEF
3834 || RELAX_STATE (fragP
->fr_subtype
) == STATE_WORD
)
3837 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_BITS10
)
3839 symbolP
= fragP
->fr_symbol
;
3840 if (symbol_resolved_p (symbolP
))
3841 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3843 /* We know the offset. calculate a distance. */
3844 aim
= S_GET_VALUE (symbolP
) - fragP
->fr_address
- fragP
->fr_fix
;
3847 if (!msp430_enable_relax
)
3849 /* Relaxation is not enabled. So, make all jump as long ones
3850 by setting 'aim' to quite high value. */
3854 this_state
= fragP
->fr_subtype
;
3855 start_type
= this_type
= table
+ this_state
;
3859 /* Look backwards. */
3860 for (next_state
= this_type
->rlx_more
; next_state
;)
3861 if (aim
>= this_type
->rlx_backward
|| !this_type
->rlx_backward
)
3865 /* Grow to next state. */
3866 this_state
= next_state
;
3867 this_type
= table
+ this_state
;
3868 next_state
= this_type
->rlx_more
;
3873 /* Look forwards. */
3874 for (next_state
= this_type
->rlx_more
; next_state
;)
3875 if (aim
<= this_type
->rlx_forward
|| !this_type
->rlx_forward
)
3879 /* Grow to next state. */
3880 this_state
= next_state
;
3881 this_type
= table
+ this_state
;
3882 next_state
= this_type
->rlx_more
;
3886 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3888 fragP
->fr_subtype
= this_state
;
3892 /* Return FALSE if the fixup in fixp should be left alone and not
3893 adjusted. We return FALSE here so that linker relaxation will
3897 msp430_fix_adjustable (struct fix
*fixp ATTRIBUTE_UNUSED
)
3899 /* If the symbol is in a non-code section then it should be OK. */
3901 && ((S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_CODE
) == 0))
3907 /* Set the contents of the .MSP430.attributes section. */
3910 msp430_md_end (void)
3912 if (check_for_nop
== TRUE
&& warn_interrupt_nops
)
3913 as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed");
3915 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_ISA
,
3916 target_is_430x () ? 2 : 1);
3918 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Code_Model
,
3919 large_model
? 2 : 1);
3921 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Data_Model
,
3922 large_model
? 2 : 1);
3925 /* Returns FALSE if there is a msp430 specific reason why the
3926 subtraction of two same-section symbols cannot be computed by
3930 msp430_allow_local_subtract (expressionS
* left
,
3931 expressionS
* right
,
3934 /* If the symbols are not in a code section then they are OK. */
3935 if ((section
->flags
& SEC_CODE
) == 0)
3938 if (S_IS_GAS_LOCAL (left
->X_add_symbol
) || S_IS_GAS_LOCAL (right
->X_add_symbol
))
3941 if (left
->X_add_symbol
== right
->X_add_symbol
)
3944 /* We have to assume that there may be instructions between the
3945 two symbols and that relaxation may increase the distance between