1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2018 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "opcode/msp430.h"
27 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
29 #include "elf/msp430.h"
30 #include "libiberty.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax
;
70 int msp430_enable_polys
;
72 /* GCC uses the some condition codes which we'll
73 implement as new polymorph instructions.
75 COND EXPL SHORT JUMP LONG JUMP
76 ===============================================
77 eq == jeq jne +4; br lab
78 ne != jne jeq +4; br lab
80 ltn honours no-overflow flag
81 ltn < jn jn +2; jmp +4; br lab
83 lt < jl jge +4; br lab
84 ltu < jlo lhs +4; br lab
90 ge >= jge jl +4; br lab
91 geu >= jhs jlo +4; br lab
92 ===============================================
94 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
95 beq,bne,blt,bltn,bltu,bge,bgeu
96 'u' means unsigned compares
98 Also, we add 'jump' instruction:
99 jump UNCOND -> jmp br lab
101 They will have fmt == 4, and insn_opnumb == number of instruction. */
106 int index
; /* Corresponding insn_opnumb. */
107 int sop
; /* Opcode if jump length is short. */
108 long lpos
; /* Label position. */
109 long lop0
; /* Opcode 1 _word_ (16 bits). */
110 long lop1
; /* Opcode second word. */
111 long lop2
; /* Opcode third word. */
114 #define MSP430_RLC(n,i,sop,o1) \
115 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
117 static struct rcodes_s msp430_rcodes
[] =
119 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
120 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
121 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
122 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
123 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
124 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
125 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
126 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
131 #define MSP430_RLC(n,i,sop,o1) \
132 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
134 static struct rcodes_s msp430x_rcodes
[] =
136 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
137 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
138 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
139 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
140 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
141 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
142 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
143 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
148 /* More difficult than above and they have format 5.
151 =================================================================
152 gt > jeq +2; jge label jeq +6; jl +4; br label
153 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
154 leu <= jeq label; jlo label jeq +2; jhs +4; br label
155 le <= jeq label; jl label jeq +2; jge +4; br label
156 ================================================================= */
161 int index
; /* Corresponding insn_opnumb. */
162 int tlab
; /* Number of labels in short mode. */
163 int op0
; /* Opcode for first word of short jump. */
164 int op1
; /* Opcode for second word of short jump. */
165 int lop0
; /* Opcodes for long jump mode. */
170 static struct hcodes_s msp430_hcodes
[] =
172 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
173 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
174 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
175 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
179 static struct hcodes_s msp430x_hcodes
[] =
181 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
182 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
183 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
184 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
188 const char comment_chars
[] = ";";
189 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = "{";
191 const char EXP_CHARS
[] = "eE";
192 const char FLT_CHARS
[] = "dD";
194 /* Handle long expressions. */
195 extern LITTLENUM_TYPE generic_bignum
[];
197 static struct hash_control
*msp430_hash
;
200 #define STATE_UNCOND_BRANCH 1 /* jump */
201 #define STATE_NOOV_BRANCH 3 /* bltn */
202 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
203 #define STATE_EMUL_BRANCH 4
212 #define STATE_BITS10 1 /* wild guess. short jump */
213 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
214 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
216 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
217 #define RELAX_STATE(s) ((s) & 3)
218 #define RELAX_LEN(s) ((s) >> 2)
219 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
221 relax_typeS md_relax_table
[] =
229 /* Unconditional jump. */
231 {1024, -1024, CNRL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
232 {0, 0, CUBL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_WORD
)}, /* state word */
233 {1, 1, CUBL
, 0}, /* state undef */
235 /* Simple branches. */
237 {1024, -1024, CNRL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
238 {0, 0, CSBL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_WORD
)}, /* state word */
241 /* blt no overflow branch. */
243 {1024, -1024, CNRL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
244 {0, 0, CNOL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_WORD
)}, /* state word */
247 /* Emulated branches. */
249 {1020, -1020, CEBL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
250 {0, 0, CNOL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_WORD
)}, /* state word */
255 #define MAX_OP_LEN 4096
264 static enum msp_isa selected_isa
= MSP_ISA_430Xv2
;
266 static inline bfd_boolean
267 target_is_430x (void)
269 return selected_isa
>= MSP_ISA_430X
;
272 static inline bfd_boolean
273 target_is_430xv2 (void)
275 return selected_isa
== MSP_ISA_430Xv2
;
278 /* Generate an absolute 16-bit relocation.
279 For the 430X we generate a relocation without linker range checking
280 if the value is being used in an extended (ie 20-bit) instruction,
281 otherwise if have a shifted expression we use a HI reloc.
282 For the 430 we generate a relocation without assembler range checking
283 if we are handling an immediate value or a byte-width instruction. */
285 #undef CHECK_RELOC_MSP430
286 #define CHECK_RELOC_MSP430(OP) \
290 : ((OP).vshift == 1) \
291 ? BFD_RELOC_MSP430_ABS_HI16 \
292 : BFD_RELOC_MSP430X_ABS16) \
293 : ((imm_op || byte_op) \
294 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
296 /* Generate a 16-bit pc-relative relocation.
297 For the 430X we generate a relocation without linker range checking.
298 For the 430 we generate a relocation without assembler range checking
299 if we are handling an immediate value or a byte-width instruction. */
300 #undef CHECK_RELOC_MSP430_PCREL
301 #define CHECK_RELOC_MSP430_PCREL \
303 ? BFD_RELOC_MSP430X_PCR16 \
304 : (imm_op || byte_op) \
305 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
307 /* Profiling capability:
308 It is a performance hit to use gcc's profiling approach for this tiny target.
309 Even more -- jtag hardware facility does not perform any profiling functions.
310 However we've got gdb's built-in simulator where we can do anything.
311 Therefore my suggestion is:
313 We define new section ".profiler" which holds all profiling information.
314 We define new pseudo operation .profiler which will instruct assembler to
315 add new profile entry to the object file. Profile should take place at the
320 .profiler flags,function_to_profile [, cycle_corrector, extra]
322 where 'flags' is a combination of the following chars:
325 i - function is in Init section
326 f - function is in Fini section
328 c - libC standard call
329 d - stack value Demand (saved at run-time in simulator)
330 I - Interrupt service routine
335 j - long Jump/ sjlj unwind
336 a - an Arbitrary code fragment
337 t - exTra parameter saved (constant value like frame size)
338 '""' optional: "sil" == sil
340 function_to_profile - function's address
341 cycle_corrector - a value which should be added to the cycle
342 counter, zero if omitted
343 extra - some extra parameter, zero if omitted.
346 ------------------------------
350 .LFrameOffset_fxx=0x08
351 .profiler "scdP", fxx ; function entry.
352 ; we also demand stack value to be displayed
357 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
358 ; (this is a prologue end)
359 ; note, that spare var filled with the frame size
362 .profiler cdE,fxx ; check stack
367 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
368 ret ; cause 'ret' insn takes 3 cycles
369 -------------------------------
371 This profiling approach does not produce any overhead and
373 So, even profiled code can be uploaded to the MCU. */
374 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
375 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
376 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
377 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
378 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
379 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
380 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
381 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
382 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
383 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
384 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
385 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
386 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
387 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
388 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
389 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
402 for (; x
; x
= x
>> 1)
409 /* Parse ordinary expression. */
412 parse_exp (char * s
, expressionS
* op
)
414 input_line_pointer
= s
;
416 if (op
->X_op
== O_absent
)
417 as_bad (_("missing operand"));
418 /* Our caller is likely to check that the entire expression was parsed.
419 If we have found a hex constant with an 'h' suffix, ilp will be left
420 pointing at the 'h', so skip it here. */
421 if (input_line_pointer
!= NULL
422 && op
->X_op
== O_constant
423 && (*input_line_pointer
== 'h' || *input_line_pointer
== 'H'))
424 ++ input_line_pointer
;
425 return input_line_pointer
;
429 /* Delete spaces from s: X ( r 1 2) => X(r12). */
432 del_spaces (char * s
)
440 while (ISSPACE (*m
) && *m
)
442 memmove (s
, m
, strlen (m
) + 1);
450 skip_space (char * s
)
457 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
460 extract_operand (char * from
, char * to
, int limit
)
464 /* Drop leading whitespace. */
465 from
= skip_space (from
);
467 while (size
< limit
&& *from
)
469 *(to
+ size
) = *from
;
470 if (*from
== ',' || *from
== ';' || *from
== '\n')
485 msp430_profiler (int dummy ATTRIBUTE_UNUSED
)
502 s
= input_line_pointer
;
503 end
= input_line_pointer
;
505 while (*end
&& *end
!= '\n')
508 while (*s
&& *s
!= '\n')
519 as_bad (_(".profiler pseudo requires at least two operands."));
520 input_line_pointer
= end
;
524 input_line_pointer
= extract_operand (input_line_pointer
, flags
, 32);
533 p_flags
|= MSP430_PROFILER_FLAG_FRAGMENT
;
536 p_flags
|= MSP430_PROFILER_FLAG_JUMP
;
539 p_flags
|= MSP430_PROFILER_FLAG_PROLSTART
;
542 p_flags
|= MSP430_PROFILER_FLAG_PROLEND
;
545 p_flags
|= MSP430_PROFILER_FLAG_EPISTART
;
548 p_flags
|= MSP430_PROFILER_FLAG_EPIEND
;
551 p_flags
|= MSP430_PROFILER_FLAG_ENTRY
;
554 p_flags
|= MSP430_PROFILER_FLAG_EXIT
;
557 p_flags
|= MSP430_PROFILER_FLAG_INITSECT
;
560 p_flags
|= MSP430_PROFILER_FLAG_FINISECT
;
563 p_flags
|= MSP430_PROFILER_FLAG_LIBCALL
;
566 p_flags
|= MSP430_PROFILER_FLAG_STDCALL
;
569 p_flags
|= MSP430_PROFILER_FLAG_STACKDMD
;
572 p_flags
|= MSP430_PROFILER_FLAG_ISR
;
575 p_flags
|= MSP430_PROFILER_FLAG_EXTRA
;
578 as_warn (_("unknown profiling flag - ignored."));
585 && ( ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_ENTRY
586 | MSP430_PROFILER_FLAG_EXIT
))
587 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_PROLSTART
588 | MSP430_PROFILER_FLAG_PROLEND
589 | MSP430_PROFILER_FLAG_EPISTART
590 | MSP430_PROFILER_FLAG_EPIEND
))
591 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_INITSECT
592 | MSP430_PROFILER_FLAG_FINISECT
))))
594 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
595 input_line_pointer
= end
;
599 /* Generate temp symbol which denotes current location. */
600 if (now_seg
== absolute_section
) /* Paranoia ? */
602 exp1
.X_op
= O_constant
;
603 exp1
.X_add_number
= abs_section_offset
;
604 as_warn (_("profiling in absolute section?"));
608 exp1
.X_op
= O_symbol
;
609 exp1
.X_add_symbol
= symbol_temp_new_now ();
610 exp1
.X_add_number
= 0;
613 /* Generate a symbol which holds flags value. */
614 exp
.X_op
= O_constant
;
615 exp
.X_add_number
= p_flags
;
617 /* Save current section. */
621 /* Now go to .profiler section. */
622 obj_elf_change_section (".profiler", SHT_PROGBITS
, 0, 0, 0, 0, 0, 0);
625 emit_expr (& exp
, 2);
627 /* Save label value. */
628 emit_expr (& exp1
, 2);
632 /* Now get profiling info. */
633 halt
= extract_operand (input_line_pointer
, str
, 1024);
634 /* Process like ".word xxx" directive. */
635 (void) parse_exp (str
, & exp
);
636 emit_expr (& exp
, 2);
637 input_line_pointer
= halt
;
640 /* Fill the rest with zeros. */
641 exp
.X_op
= O_constant
;
642 exp
.X_add_number
= 0;
644 emit_expr (& exp
, 2);
646 /* Return to current section. */
647 subseg_set (seg
, subseg
);
651 extract_word (char * from
, char * to
, int limit
)
656 /* Drop leading whitespace. */
657 from
= skip_space (from
);
660 /* Find the op code end. */
661 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
663 to
[size
++] = *op_end
++;
664 if (size
+ 1 >= limit
)
672 #define OPTION_MMCU 'm'
673 #define OPTION_RELAX 'Q'
674 #define OPTION_POLYMORPHS 'P'
675 #define OPTION_LARGE 'l'
676 static bfd_boolean large_model
= FALSE
;
677 #define OPTION_NO_INTR_NOPS 'N'
678 #define OPTION_INTR_NOPS 'n'
679 static bfd_boolean gen_interrupt_nops
= FALSE
;
680 #define OPTION_WARN_INTR_NOPS 'y'
681 #define OPTION_NO_WARN_INTR_NOPS 'Y'
682 static bfd_boolean warn_interrupt_nops
= TRUE
;
683 #define OPTION_MCPU 'c'
684 #define OPTION_MOVE_DATA 'd'
685 static bfd_boolean move_data
= FALSE
;
686 #define OPTION_DATA_REGION 'r'
687 static bfd_boolean upper_data_region_in_use
= FALSE
;
691 OPTION_SILICON_ERRATA
= OPTION_MD_BASE
,
692 OPTION_SILICON_ERRATA_WARN
,
695 static unsigned int silicon_errata_fix
= 0;
696 static unsigned int silicon_errata_warn
= 0;
697 #define SILICON_ERRATA_CPU4 (1 << 0)
698 #define SILICON_ERRATA_CPU8 (1 << 1)
699 #define SILICON_ERRATA_CPU11 (1 << 2)
700 #define SILICON_ERRATA_CPU12 (1 << 3)
701 #define SILICON_ERRATA_CPU13 (1 << 4)
702 #define SILICON_ERRATA_CPU19 (1 << 5)
705 msp430_set_arch (int option
)
707 char str
[32]; /* 32 for good measure. */
709 input_line_pointer
= extract_word (input_line_pointer
, str
, 32);
711 md_parse_option (option
, str
);
712 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
713 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
716 /* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
717 Keep these two structures in sync.
718 The data in this structure has been extracted from version 1.194 of the
719 devices.csv file released by TI in September 2016. */
721 struct msp430_mcu_data
724 unsigned int revision
; /* 0=> MSP430, 1=>MSP430X, 2=> MSP430Xv2. */
725 unsigned int hwmpy
; /* 0=>none, 1=>16-bit, 2=>16-bit w/sign extend, 4=>32-bit, 8=> 32-bit (5xx). */
729 { "cc430f5123",2,8 },
730 { "cc430f5125",2,8 },
731 { "cc430f5133",2,8 },
732 { "cc430f5135",2,8 },
733 { "cc430f5137",2,8 },
734 { "cc430f5143",2,8 },
735 { "cc430f5145",2,8 },
736 { "cc430f5147",2,8 },
737 { "cc430f6125",2,8 },
738 { "cc430f6126",2,8 },
739 { "cc430f6127",2,8 },
740 { "cc430f6135",2,8 },
741 { "cc430f6137",2,8 },
742 { "cc430f6143",2,8 },
743 { "cc430f6145",2,8 },
744 { "cc430f6147",2,8 },
745 { "msp430afe221",0,2 },
746 { "msp430afe222",0,2 },
747 { "msp430afe223",0,2 },
748 { "msp430afe231",0,2 },
749 { "msp430afe232",0,2 },
750 { "msp430afe233",0,2 },
751 { "msp430afe251",0,2 },
752 { "msp430afe252",0,2 },
753 { "msp430afe253",0,2 },
754 { "msp430bt5190",2,8 },
755 { "msp430c091",0,0 },
756 { "msp430c092",0,0 },
757 { "msp430c111",0,0 },
758 { "msp430c1111",0,0 },
759 { "msp430c112",0,0 },
760 { "msp430c1121",0,0 },
761 { "msp430c1331",0,0 },
762 { "msp430c1351",0,0 },
763 { "msp430c311s",0,0 },
764 { "msp430c312",0,0 },
765 { "msp430c313",0,0 },
766 { "msp430c314",0,0 },
767 { "msp430c315",0,0 },
768 { "msp430c323",0,0 },
769 { "msp430c325",0,0 },
770 { "msp430c336",0,1 },
771 { "msp430c337",0,1 },
772 { "msp430c412",0,0 },
773 { "msp430c413",0,0 },
774 { "msp430cg4616",1,1 },
775 { "msp430cg4617",1,1 },
776 { "msp430cg4618",1,1 },
777 { "msp430cg4619",1,1 },
778 { "msp430e112",0,0 },
779 { "msp430e313",0,0 },
780 { "msp430e315",0,0 },
781 { "msp430e325",0,0 },
782 { "msp430e337",0,1 },
783 { "msp430f110",0,0 },
784 { "msp430f1101",0,0 },
785 { "msp430f1101a",0,0 },
786 { "msp430f1111",0,0 },
787 { "msp430f1111a",0,0 },
788 { "msp430f112",0,0 },
789 { "msp430f1121",0,0 },
790 { "msp430f1121a",0,0 },
791 { "msp430f1122",0,0 },
792 { "msp430f1132",0,0 },
793 { "msp430f122",0,0 },
794 { "msp430f1222",0,0 },
795 { "msp430f123",0,0 },
796 { "msp430f1232",0,0 },
797 { "msp430f133",0,0 },
798 { "msp430f135",0,0 },
799 { "msp430f147",0,1 },
800 { "msp430f1471",0,1 },
801 { "msp430f148",0,1 },
802 { "msp430f1481",0,1 },
803 { "msp430f149",0,1 },
804 { "msp430f1491",0,1 },
805 { "msp430f155",0,0 },
806 { "msp430f156",0,0 },
807 { "msp430f157",0,0 },
808 { "msp430f1610",0,1 },
809 { "msp430f1611",0,1 },
810 { "msp430f1612",0,1 },
811 { "msp430f167",0,1 },
812 { "msp430f168",0,1 },
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1297 { "msp430g2444",0,0 },
1298 { "msp430g2452",0,0 },
1299 { "msp430g2453",0,0 },
1300 { "msp430g2513",0,0 },
1301 { "msp430g2533",0,0 },
1302 { "msp430g2544",0,0 },
1303 { "msp430g2553",0,0 },
1304 { "msp430g2744",0,0 },
1305 { "msp430g2755",0,0 },
1306 { "msp430g2855",0,0 },
1307 { "msp430g2955",0,0 },
1308 { "msp430i2020",0,2 },
1309 { "msp430i2021",0,2 },
1310 { "msp430i2030",0,2 },
1311 { "msp430i2031",0,2 },
1312 { "msp430i2040",0,2 },
1313 { "msp430i2041",0,2 },
1314 { "msp430i2xxgeneric",0,2 },
1315 { "msp430l092",0,0 },
1316 { "msp430p112",0,0 },
1317 { "msp430p313",0,0 },
1318 { "msp430p315",0,0 },
1319 { "msp430p315s",0,0 },
1320 { "msp430p325",0,0 },
1321 { "msp430p337",0,1 },
1322 { "msp430sl5438a",2,8 },
1323 { "msp430tch5e",0,0 },
1324 { "msp430xgeneric",2,8 },
1325 { "rf430f5144",2,8 },
1326 { "rf430f5155",2,8 },
1327 { "rf430f5175",2,8 },
1328 { "rf430frl152h",0,0 },
1329 { "rf430frl152h_rom",0,0 },
1330 { "rf430frl153h",0,0 },
1331 { "rf430frl153h_rom",0,0 },
1332 { "rf430frl154h",0,0 },
1333 { "rf430frl154h_rom",0,0 }
1337 md_parse_option (int c
, const char * arg
)
1341 case OPTION_SILICON_ERRATA
:
1342 case OPTION_SILICON_ERRATA_WARN
:
1348 unsigned int length
;
1349 unsigned int bitfield
;
1352 { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4
},
1353 { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8
},
1354 { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11
},
1355 { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12
},
1356 { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13
},
1357 { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19
},
1362 for (i
= ARRAY_SIZE (erratas
); i
--;)
1363 if (strncasecmp (arg
, erratas
[i
].name
, erratas
[i
].length
) == 0)
1365 if (c
== OPTION_SILICON_ERRATA
)
1366 silicon_errata_fix
|= erratas
[i
].bitfield
;
1368 silicon_errata_warn
|= erratas
[i
].bitfield
;
1369 arg
+= erratas
[i
].length
;
1374 as_warn (_("Unrecognised CPU errata name starting here: %s"), arg
);
1380 as_warn (_("Expecting comma after CPU errata name, not: %s"), arg
);
1390 as_fatal (_("MCU option requires a name\n"));
1392 if (strcasecmp ("msp430", arg
) == 0)
1393 selected_isa
= MSP_ISA_430
;
1394 else if (strcasecmp ("msp430xv2", arg
) == 0)
1395 selected_isa
= MSP_ISA_430Xv2
;
1396 else if (strcasecmp ("msp430x", arg
) == 0)
1397 selected_isa
= MSP_ISA_430X
;
1402 for (i
= ARRAY_SIZE (msp430_mcu_data
); i
--;)
1403 if (strcasecmp (msp430_mcu_data
[i
].name
, arg
) == 0)
1405 switch (msp430_mcu_data
[i
].revision
)
1407 case 0: selected_isa
= MSP_ISA_430
; break;
1408 case 1: selected_isa
= MSP_ISA_430X
; break;
1409 case 2: selected_isa
= MSP_ISA_430Xv2
; break;
1414 /* It is not an error if we do not match the MCU name. */
1418 if (strcmp (arg
, "430") == 0
1419 || strcasecmp (arg
, "msp430") == 0)
1420 selected_isa
= MSP_ISA_430
;
1421 else if (strcasecmp (arg
, "430x") == 0
1422 || strcasecmp (arg
, "msp430x") == 0)
1423 selected_isa
= MSP_ISA_430X
;
1424 else if (strcasecmp (arg
, "430xv2") == 0
1425 || strcasecmp (arg
, "msp430xv2") == 0)
1426 selected_isa
= MSP_ISA_430Xv2
;
1428 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg
);
1432 msp430_enable_relax
= 1;
1435 case OPTION_POLYMORPHS
:
1436 msp430_enable_polys
= 1;
1443 case OPTION_NO_INTR_NOPS
:
1444 gen_interrupt_nops
= FALSE
;
1446 case OPTION_INTR_NOPS
:
1447 gen_interrupt_nops
= TRUE
;
1450 case OPTION_WARN_INTR_NOPS
:
1451 warn_interrupt_nops
= TRUE
;
1453 case OPTION_NO_WARN_INTR_NOPS
:
1454 warn_interrupt_nops
= FALSE
;
1457 case OPTION_MOVE_DATA
:
1461 case OPTION_DATA_REGION
:
1462 if (strcmp (arg
, "upper") == 0
1463 || strcmp (arg
, "either") == 0)
1464 upper_data_region_in_use
= TRUE
;
1471 /* The intention here is to have the mere presence of these sections
1472 cause the object to have a reference to a well-known symbol. This
1473 reference pulls in the bits of the runtime (crt0) that initialize
1474 these sections. Thus, for example, the startup code to call
1475 memset() to initialize .bss will only be linked in when there is a
1476 non-empty .bss section. Otherwise, the call would exist but have a
1477 zero length parameter, which is a waste of memory and cycles.
1479 The code which initializes these sections should have a global
1480 label for these symbols, and should be marked with KEEP() in the
1484 msp430_make_init_symbols (const char * name
)
1486 if (strncmp (name
, ".bss", 4) == 0
1487 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
1488 (void) symbol_find_or_make ("__crt0_init_bss");
1490 if (strncmp (name
, ".data", 5) == 0
1491 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
1492 (void) symbol_find_or_make ("__crt0_movedata");
1494 /* Note - data assigned to the .either.data section may end up being
1495 placed in the .upper.data section if the .lower.data section is
1496 full. Hence the need to define the crt0 symbol.
1497 The linker may create upper or either data sections, even when none exist
1498 at the moment, so use the value of the data-region flag to determine if
1499 the symbol is needed. */
1500 if (strncmp (name
, ".either.data", 12) == 0
1501 || strncmp (name
, ".upper.data", 11) == 0
1502 || upper_data_region_in_use
)
1503 (void) symbol_find_or_make ("__crt0_move_highdata");
1505 /* See note about .either.data above. */
1506 if (strncmp (name
, ".upper.bss", 10) == 0
1507 || strncmp (name
, ".either.bss", 11) == 0
1508 || upper_data_region_in_use
)
1509 (void) symbol_find_or_make ("__crt0_init_highbss");
1513 msp430_section (int arg
)
1515 char * saved_ilp
= input_line_pointer
;
1516 const char * name
= obj_elf_section_name ();
1518 msp430_make_init_symbols (name
);
1520 input_line_pointer
= saved_ilp
;
1521 obj_elf_section (arg
);
1525 msp430_frob_section (asection
*sec
)
1527 const char *name
= sec
->name
;
1532 msp430_make_init_symbols (name
);
1536 msp430_lcomm (int ignore ATTRIBUTE_UNUSED
)
1538 symbolS
*symbolP
= s_comm_internal (0, s_lcomm_internal
);
1541 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
1542 (void) symbol_find_or_make ("__crt0_init_bss");
1546 msp430_comm (int needs_align
)
1548 s_comm_internal (needs_align
, elf_common_parse
);
1549 (void) symbol_find_or_make ("__crt0_init_bss");
1553 msp430_refsym (int arg ATTRIBUTE_UNUSED
)
1555 char sym_name
[1024];
1556 input_line_pointer
= extract_word (input_line_pointer
, sym_name
, 1024);
1558 (void) symbol_find_or_make (sym_name
);
1561 const pseudo_typeS md_pseudo_table
[] =
1563 {"arch", msp430_set_arch
, OPTION_MMCU
},
1564 {"cpu", msp430_set_arch
, OPTION_MCPU
},
1565 {"profiler", msp430_profiler
, 0},
1566 {"section", msp430_section
, 0},
1567 {"section.s", msp430_section
, 0},
1568 {"sect", msp430_section
, 0},
1569 {"sect.s", msp430_section
, 0},
1570 {"pushsection", msp430_section
, 1},
1571 {"refsym", msp430_refsym
, 0},
1572 {"comm", msp430_comm
, 0},
1573 {"lcomm", msp430_lcomm
, 0},
1577 const char *md_shortopts
= "mm:,mP,mQ,ml,mN,mn,my,mY";
1579 struct option md_longopts
[] =
1581 {"msilicon-errata", required_argument
, NULL
, OPTION_SILICON_ERRATA
},
1582 {"msilicon-errata-warn", required_argument
, NULL
, OPTION_SILICON_ERRATA_WARN
},
1583 {"mmcu", required_argument
, NULL
, OPTION_MMCU
},
1584 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
1585 {"mP", no_argument
, NULL
, OPTION_POLYMORPHS
},
1586 {"mQ", no_argument
, NULL
, OPTION_RELAX
},
1587 {"ml", no_argument
, NULL
, OPTION_LARGE
},
1588 {"mN", no_argument
, NULL
, OPTION_NO_INTR_NOPS
},
1589 {"mn", no_argument
, NULL
, OPTION_INTR_NOPS
},
1590 {"mY", no_argument
, NULL
, OPTION_NO_WARN_INTR_NOPS
},
1591 {"my", no_argument
, NULL
, OPTION_WARN_INTR_NOPS
},
1592 {"md", no_argument
, NULL
, OPTION_MOVE_DATA
},
1593 {"mdata-region", required_argument
, NULL
, OPTION_DATA_REGION
},
1594 {NULL
, no_argument
, NULL
, 0}
1597 size_t md_longopts_size
= sizeof (md_longopts
);
1600 md_show_usage (FILE * stream
)
1603 _("MSP430 options:\n"
1604 " -mmcu=<msp430-name> - select microcontroller type\n"
1605 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
1607 _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
1608 " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
1609 " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
1611 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
1612 " -mP - enable polymorph instructions\n"));
1614 _(" -ml - enable large code model\n"));
1616 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
1618 _(" -mn - insert a NOP after changing interrupts\n"));
1620 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
1622 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
1624 _(" -md - Force copying of data from ROM to RAM at startup\n"));
1626 _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
1631 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
1637 extract_cmd (char * from
, char * to
, int limit
)
1641 while (*from
&& ! ISSPACE (*from
) && *from
!= '.' && limit
> size
)
1643 *(to
+ size
) = *from
;
1654 md_atof (int type
, char * litP
, int * sizeP
)
1656 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
1662 struct msp430_opcode_s
* opcode
;
1663 msp430_hash
= hash_new ();
1665 for (opcode
= msp430_opcodes
; opcode
->name
; opcode
++)
1666 hash_insert (msp430_hash
, opcode
->name
, (char *) opcode
);
1668 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
1669 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
1671 /* Set linkrelax here to avoid fixups in most sections. */
1675 static inline bfd_boolean
1676 is_regname_end (char c
)
1678 return (c
== 0 || ! ISALNUM (c
));
1681 /* Returns the register number equivalent to the string T.
1682 Returns -1 if there is no such register.
1683 Skips a leading 'r' or 'R' character if there is one.
1684 Handles the register aliases PC and SP. */
1687 check_reg (char * t
)
1690 signed long int val
;
1692 if (t
== NULL
|| t
[0] == 0)
1695 if (*t
== 'r' || *t
== 'R')
1698 if (strncasecmp (t
, "pc", 2) == 0 && is_regname_end (t
[2]))
1701 if (strncasecmp (t
, "sp", 2) == 0 && is_regname_end (t
[2]))
1704 if (strncasecmp (t
, "sr", 2) == 0 && is_regname_end (t
[2]))
1707 if (*t
== '0' && is_regname_end (t
[1]))
1710 val
= strtol (t
, & endt
, 0);
1712 if (val
< 1 || val
> 15)
1715 if (is_regname_end (*endt
))
1722 msp430_srcoperand (struct msp430_operand_s
* op
,
1725 bfd_boolean
* imm_op
,
1726 bfd_boolean allow_20bit_values
,
1727 bfd_boolean constants_allowed
)
1732 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1739 /* Check if there is:
1740 llo(x) - least significant 16 bits, x &= 0xffff
1741 lhi(x) - x = (x >> 16) & 0xffff,
1742 hlo(x) - x = (x >> 32) & 0xffff,
1743 hhi(x) - x = (x >> 48) & 0xffff
1744 The value _MUST_ be constant expression: #hlo(1231231231). */
1748 if (strncasecmp (h
, "#llo(", 5) == 0)
1753 else if (strncasecmp (h
, "#lhi(", 5) == 0)
1758 else if (strncasecmp (h
, "#hlo(", 5) == 0)
1763 else if (strncasecmp (h
, "#hhi(", 5) == 0)
1768 else if (strncasecmp (h
, "#lo(", 4) == 0)
1773 else if (strncasecmp (h
, "#hi(", 4) == 0)
1779 op
->reg
= 0; /* Reg PC. */
1781 op
->ol
= 1; /* Immediate will follow an instruction. */
1782 __tl
= h
+ 1 + rval
;
1784 op
->vshift
= vshift
;
1786 end
= parse_exp (__tl
, &(op
->exp
));
1787 if (end
!= NULL
&& *end
!= 0 && *end
!= ')' )
1789 as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end
, l
);
1792 if (op
->exp
.X_op
== O_constant
)
1794 int x
= op
->exp
.X_add_number
;
1799 op
->exp
.X_add_number
= x
;
1801 else if (vshift
== 1)
1803 x
= (x
>> 16) & 0xffff;
1804 op
->exp
.X_add_number
= x
;
1807 else if (vshift
> 1)
1810 op
->exp
.X_add_number
= -1;
1812 op
->exp
.X_add_number
= 0; /* Nothing left. */
1813 x
= op
->exp
.X_add_number
;
1817 if (allow_20bit_values
)
1819 if (op
->exp
.X_add_number
> 0xfffff || op
->exp
.X_add_number
< -524288)
1821 as_bad (_("value 0x%x out of extended range."), x
);
1825 else if (op
->exp
.X_add_number
> 65535 || op
->exp
.X_add_number
< -32768)
1827 as_bad (_("value %d out of range. Use #lo() or #hi()"), x
);
1831 /* Now check constants. */
1832 /* Substitute register mode with a constant generator if applicable. */
1834 if (!allow_20bit_values
)
1835 x
= (short) x
; /* Extend sign. */
1837 if (! constants_allowed
)
1869 if (bin
== 0x1200 && ! target_is_430x ())
1871 /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
1872 if (silicon_errata_warn
& SILICON_ERRATA_CPU4
)
1873 as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
1874 /* No need to check silicon_errata_fixes - this fix is always implemented. */
1886 if (bin
== 0x1200 && ! target_is_430x ())
1888 /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
1889 if (silicon_errata_warn
& SILICON_ERRATA_CPU4
)
1890 as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
1901 else if (op
->exp
.X_op
== O_symbol
)
1904 as_bad (_("error: unsupported #foo() directive used on symbol"));
1907 else if (op
->exp
.X_op
== O_big
)
1913 op
->exp
.X_op
= O_constant
;
1914 op
->exp
.X_add_number
= 0xffff & generic_bignum
[vshift
];
1915 x
= op
->exp
.X_add_number
;
1921 ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
1969 /* Redundant (yet) check. */
1970 else if (op
->exp
.X_op
== O_register
)
1972 (_("Registers cannot be used within immediate expression [%s]"), l
);
1974 as_bad (_("unknown operand %s"), l
);
1979 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1984 op
->reg
= 2; /* reg 2 in absolute addr mode. */
1985 op
->am
= 1; /* mode As == 01 bin. */
1986 op
->ol
= 1; /* Immediate value followed by instruction. */
1988 end
= parse_exp (__tl
, &(op
->exp
));
1989 if (end
!= NULL
&& *end
!= 0)
1991 as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end
, l
);
1996 if (op
->exp
.X_op
== O_constant
)
1998 int x
= op
->exp
.X_add_number
;
2000 if (allow_20bit_values
)
2002 if (x
> 0xfffff || x
< -(0x7ffff))
2004 as_bad (_("value 0x%x out of extended range."), x
);
2008 else if (x
> 65535 || x
< -32768)
2010 as_bad (_("value out of range: 0x%x"), x
);
2014 else if (op
->exp
.X_op
== O_symbol
)
2018 /* Redundant (yet) check. */
2019 if (op
->exp
.X_op
== O_register
)
2021 (_("Registers cannot be used within absolute expression [%s]"), l
);
2023 as_bad (_("unknown expression in operand %s"), l
);
2029 /* Check if indirect register mode @Rn / postincrement @Rn+. */
2033 char *m
= strchr (l
, '+');
2037 as_bad (_("unknown addressing mode %s"), l
);
2043 if ((op
->reg
= check_reg (t
)) == -1)
2045 as_bad (_("Bad register name %s"), t
);
2053 /* PC cannot be used in indirect addressing. */
2054 if (target_is_430xv2 () && op
->reg
== 0)
2056 as_bad (_("cannot use indirect addressing with the PC"));
2063 /* Check if register indexed X(Rn). */
2066 char *h
= strrchr (l
, '(');
2067 char *m
= strrchr (l
, ')');
2076 as_bad (_("')' required"));
2084 /* Extract a register. */
2085 if ((op
->reg
= check_reg (t
+ 1)) == -1)
2088 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
2095 as_bad (_("r2 should not be used in indexed addressing mode"));
2099 /* Extract constant. */
2104 end
= parse_exp (__tl
, &(op
->exp
));
2105 if (end
!= NULL
&& *end
!= 0)
2107 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l
);
2110 if (op
->exp
.X_op
== O_constant
)
2112 int x
= op
->exp
.X_add_number
;
2114 if (allow_20bit_values
)
2116 if (x
> 0xfffff || x
< - (0x7ffff))
2118 as_bad (_("value 0x%x out of extended range."), x
);
2122 else if (x
> 65535 || x
< -32768)
2124 as_bad (_("value out of range: 0x%x"), x
);
2136 if (op
->reg
== 1 && (x
& 1))
2138 if (silicon_errata_fix
& SILICON_ERRATA_CPU8
)
2139 as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
2140 else if (silicon_errata_warn
& SILICON_ERRATA_CPU8
)
2141 as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
2144 else if (op
->exp
.X_op
== O_symbol
)
2148 /* Redundant (yet) check. */
2149 if (op
->exp
.X_op
== O_register
)
2151 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l
);
2153 as_bad (_("unknown expression in operand %s"), l
);
2161 /* Possibly register mode 'mov r1,r2'. */
2162 if ((op
->reg
= check_reg (l
)) != -1)
2170 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
2172 op
->reg
= 0; /* PC relative... be careful. */
2173 /* An expression starting with a minus sign is a constant, not an address. */
2174 op
->am
= (*l
== '-' ? 3 : 1);
2178 end
= parse_exp (__tl
, &(op
->exp
));
2179 if (end
!= NULL
&& * end
!= 0)
2181 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l
);
2189 msp430_dstoperand (struct msp430_operand_s
* op
,
2192 bfd_boolean allow_20bit_values
,
2193 bfd_boolean constants_allowed
)
2196 int ret
= msp430_srcoperand (op
, l
, bin
, & dummy
,
2205 char *__tl
= (char *) "0";
2211 (void) parse_exp (__tl
, &(op
->exp
));
2213 if (op
->exp
.X_op
!= O_constant
|| op
->exp
.X_add_number
!= 0)
2215 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
2225 ("this addressing mode is not applicable for destination operand"));
2231 /* Attempt to encode a MOVA instruction with the given operands.
2232 Returns the length of the encoded instruction if successful
2233 or 0 upon failure. If the encoding fails, an error message
2234 will be returned if a pointer is provided. */
2237 try_encode_mova (bfd_boolean imm_op
,
2239 struct msp430_operand_s
* op1
,
2240 struct msp430_operand_s
* op2
,
2241 const char ** error_message_return
)
2247 /* Only a restricted subset of the normal MSP430 addressing modes
2248 are supported here, so check for the ones that are allowed. */
2251 if (op1
->mode
== OP_EXP
)
2253 if (op2
->mode
!= OP_REG
)
2255 if (error_message_return
!= NULL
)
2256 * error_message_return
= _("expected register as second argument of %s");
2262 /* MOVA #imm20, Rdst. */
2263 bin
|= 0x80 | op2
->reg
;
2264 frag
= frag_more (4);
2265 where
= frag
- frag_now
->fr_literal
;
2266 if (op1
->exp
.X_op
== O_constant
)
2268 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
2269 bfd_putl16 ((bfd_vma
) bin
, frag
);
2270 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
2274 bfd_putl16 ((bfd_vma
) bin
, frag
);
2275 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
2276 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
2277 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2282 else if (op1
->am
== 1)
2284 /* MOVA z16(Rsrc), Rdst. */
2285 bin
|= 0x30 | (op1
->reg
<< 8) | op2
->reg
;
2286 frag
= frag_more (4);
2287 where
= frag
- frag_now
->fr_literal
;
2288 bfd_putl16 ((bfd_vma
) bin
, frag
);
2289 if (op1
->exp
.X_op
== O_constant
)
2291 if (op1
->exp
.X_add_number
> 0xffff
2292 || op1
->exp
.X_add_number
< -(0x7fff))
2294 if (error_message_return
!= NULL
)
2295 * error_message_return
= _("index value too big for %s");
2298 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
2302 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2303 fix_new_exp (frag_now
, where
+ 2, 2, &(op1
->exp
), FALSE
,
2305 BFD_RELOC_MSP430X_PCR16
:
2306 BFD_RELOC_MSP430X_ABS16
);
2311 if (error_message_return
!= NULL
)
2312 * error_message_return
= _("unexpected addressing mode for %s");
2315 else if (op1
->am
== 0)
2317 /* MOVA Rsrc, ... */
2318 if (op2
->mode
== OP_REG
)
2320 bin
|= 0xc0 | (op1
->reg
<< 8) | op2
->reg
;
2321 frag
= frag_more (2);
2322 where
= frag
- frag_now
->fr_literal
;
2323 bfd_putl16 ((bfd_vma
) bin
, frag
);
2326 else if (op2
->am
== 1)
2330 /* MOVA Rsrc, &abs20. */
2331 bin
|= 0x60 | (op1
->reg
<< 8);
2332 frag
= frag_more (4);
2333 where
= frag
- frag_now
->fr_literal
;
2334 if (op2
->exp
.X_op
== O_constant
)
2336 bin
|= (op2
->exp
.X_add_number
>> 16) & 0xf;
2337 bfd_putl16 ((bfd_vma
) bin
, frag
);
2338 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
2342 bfd_putl16 ((bfd_vma
) bin
, frag
);
2343 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2344 fix_new_exp (frag_now
, where
, 4, &(op2
->exp
), FALSE
,
2345 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2350 /* MOVA Rsrc, z16(Rdst). */
2351 bin
|= 0x70 | (op1
->reg
<< 8) | op2
->reg
;
2352 frag
= frag_more (4);
2353 where
= frag
- frag_now
->fr_literal
;
2354 bfd_putl16 ((bfd_vma
) bin
, frag
);
2355 if (op2
->exp
.X_op
== O_constant
)
2357 if (op2
->exp
.X_add_number
> 0xffff
2358 || op2
->exp
.X_add_number
< -(0x7fff))
2360 if (error_message_return
!= NULL
)
2361 * error_message_return
= _("index value too big for %s");
2364 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
2368 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2369 fix_new_exp (frag_now
, where
+ 2, 2, &(op2
->exp
), FALSE
,
2371 BFD_RELOC_MSP430X_PCR16
:
2372 BFD_RELOC_MSP430X_ABS16
);
2377 if (error_message_return
!= NULL
)
2378 * error_message_return
= _("unexpected addressing mode for %s");
2383 /* imm_op == FALSE. */
2385 if (op1
->reg
== 2 && op1
->am
== 1 && op1
->mode
== OP_EXP
)
2387 /* MOVA &abs20, Rdst. */
2388 if (op2
->mode
!= OP_REG
)
2390 if (error_message_return
!= NULL
)
2391 * error_message_return
= _("expected register as second argument of %s");
2395 if (op2
->reg
== 2 || op2
->reg
== 3)
2397 if (error_message_return
!= NULL
)
2398 * error_message_return
= _("constant generator destination register found in %s");
2402 bin
|= 0x20 | op2
->reg
;
2403 frag
= frag_more (4);
2404 where
= frag
- frag_now
->fr_literal
;
2405 if (op1
->exp
.X_op
== O_constant
)
2407 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
2408 bfd_putl16 ((bfd_vma
) bin
, frag
);
2409 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
2413 bfd_putl16 ((bfd_vma
) bin
, frag
);
2414 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2415 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
2416 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
2420 else if (op1
->mode
== OP_REG
)
2424 /* MOVA @Rsrc+, Rdst. */
2425 if (op2
->mode
!= OP_REG
)
2427 if (error_message_return
!= NULL
)
2428 * error_message_return
= _("expected register as second argument of %s");
2432 if (op2
->reg
== 2 || op2
->reg
== 3)
2434 if (error_message_return
!= NULL
)
2435 * error_message_return
= _("constant generator destination register found in %s");
2439 if (op1
->reg
== 2 || op1
->reg
== 3)
2441 if (error_message_return
!= NULL
)
2442 * error_message_return
= _("constant generator source register found in %s");
2446 bin
|= 0x10 | (op1
->reg
<< 8) | op2
->reg
;
2447 frag
= frag_more (2);
2448 where
= frag
- frag_now
->fr_literal
;
2449 bfd_putl16 ((bfd_vma
) bin
, frag
);
2452 else if (op1
->am
== 2)
2454 /* MOVA @Rsrc,Rdst */
2455 if (op2
->mode
!= OP_REG
)
2457 if (error_message_return
!= NULL
)
2458 * error_message_return
= _("expected register as second argument of %s");
2462 if (op2
->reg
== 2 || op2
->reg
== 3)
2464 if (error_message_return
!= NULL
)
2465 * error_message_return
= _("constant generator destination register found in %s");
2469 if (op1
->reg
== 2 || op1
->reg
== 3)
2471 if (error_message_return
!= NULL
)
2472 * error_message_return
= _("constant generator source register found in %s");
2476 bin
|= (op1
->reg
<< 8) | op2
->reg
;
2477 frag
= frag_more (2);
2478 where
= frag
- frag_now
->fr_literal
;
2479 bfd_putl16 ((bfd_vma
) bin
, frag
);
2484 if (error_message_return
!= NULL
)
2485 * error_message_return
= _("unexpected addressing mode for %s");
2490 #define NOP_CHECK_INTERRUPT (1 << 0)
2491 #define NOP_CHECK_CPU12 (1 << 1)
2492 #define NOP_CHECK_CPU19 (1 << 2)
2494 static signed int check_for_nop
= 0;
2496 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
2498 /* is_{e,d}int only check the explicit enabling/disabling of interrupts.
2499 For MOV insns, more sophisticated processing is needed to determine if they
2500 result in enabling/disabling interrupts. */
2501 #define is_dint(OPCODE, BIN) ((strcmp (OPCODE, "dint") == 0) \
2502 || ((strcmp (OPCODE, "bic") == 0) \
2504 || ((strcmp (OPCODE, "clr") == 0) \
2507 #define is_eint(OPCODE, BIN) ((strcmp (OPCODE, "eint") == 0) \
2508 || ((strcmp (OPCODE, "bis") == 0) \
2511 const char * const INSERT_NOP_BEFORE_EINT
= "NOP inserted here, before an interrupt enable instruction";
2512 const char * const INSERT_NOP_AFTER_DINT
= "NOP inserted here, after an interrupt disable instruction";
2513 const char * const INSERT_NOP_AFTER_EINT
= "NOP inserted here, after an interrupt enable instruction";
2514 const char * const INSERT_NOP_BEFORE_UNKNOWN
= "NOP inserted here, before this interrupt state change";
2515 const char * const INSERT_NOP_AFTER_UNKNOWN
="NOP inserted here, after the instruction that changed interrupt state";
2516 const char * const INSERT_NOP_AT_EOF
= "NOP inserted after the interrupt state change at the end of the file";
2518 const char * const WARN_NOP_BEFORE_EINT
= "a NOP might be needed here, before an interrupt enable instruction";
2519 const char * const WARN_NOP_AFTER_DINT
= "a NOP might be needed here, after an interrupt disable instruction";
2520 const char * const WARN_NOP_AFTER_EINT
= "a NOP might be needed here, after an interrupt enable instruction";
2521 const char * const WARN_NOP_BEFORE_UNKNOWN
= "a NOP might be needed here, before this interrupt state change";
2522 const char * const WARN_NOP_AFTER_UNKNOWN
= "a NOP might also be needed here, after the instruction that changed interrupt state";
2523 const char * const WARN_NOP_AT_EOF
= "a NOP might be needed after the interrupt state change at the end of the file";
2529 frag
= frag_more (2);
2530 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2531 dwarf2_emit_insn (2);
2534 /* Insert/inform about adding a NOP if this insn enables interrupts. */
2536 warn_eint_nop (bfd_boolean prev_insn_is_nop
, bfd_boolean prev_insn_is_dint
)
2538 if (prev_insn_is_nop
2539 /* Prevent double warning for DINT immediately before EINT. */
2540 || prev_insn_is_dint
2541 /* 430 ISA does not require a NOP before EINT. */
2542 || (! target_is_430x ()))
2544 if (gen_interrupt_nops
)
2547 if (warn_interrupt_nops
)
2548 as_warn (_(INSERT_NOP_BEFORE_EINT
));
2550 else if (warn_interrupt_nops
)
2551 as_warn (_(WARN_NOP_BEFORE_EINT
));
2554 /* Use when unsure what effect the insn will have on the interrupt status,
2555 to insert/warn about adding a NOP before the current insn. */
2557 warn_unsure_interrupt (void)
2559 /* Since this could enable or disable interrupts, need to add/warn about
2560 adding a NOP before and after this insn. */
2561 if (gen_interrupt_nops
)
2564 if (warn_interrupt_nops
)
2565 as_warn (_(INSERT_NOP_BEFORE_UNKNOWN
));
2567 else if (warn_interrupt_nops
)
2568 as_warn (_(WARN_NOP_BEFORE_UNKNOWN
));
2571 /* Parse instruction operands.
2572 Return binary opcode. */
2575 msp430_operands (struct msp430_opcode_s
* opcode
, char * line
)
2577 int bin
= opcode
->bin_opcode
; /* Opcode mask. */
2578 int insn_length
= 0;
2579 char l1
[MAX_OP_LEN
], l2
[MAX_OP_LEN
];
2583 struct msp430_operand_s op1
, op2
;
2585 static short ZEROS
= 0;
2586 bfd_boolean byte_op
, imm_op
;
2589 int extended
= 0x1800;
2590 bfd_boolean extended_op
= FALSE
;
2591 bfd_boolean addr_op
;
2592 const char * error_message
;
2593 static signed int repeat_count
= 0;
2594 static bfd_boolean prev_insn_is_nop
= FALSE
;
2595 static bfd_boolean prev_insn_is_dint
= FALSE
;
2596 static bfd_boolean prev_insn_is_eint
= FALSE
;
2597 /* We might decide before the end of the function that the current insn is
2598 equivalent to DINT/EINT. */
2599 bfd_boolean this_insn_is_dint
= FALSE
;
2600 bfd_boolean this_insn_is_eint
= FALSE
;
2601 bfd_boolean fix_emitted
;
2603 /* Opcode is the one from opcodes table
2604 line contains something like
2613 bfd_boolean check
= FALSE
;
2616 switch (TOLOWER (* line
))
2619 /* Byte operation. */
2620 bin
|= BYTE_OPERATION
;
2626 /* "Address" ops work on 20-bit values. */
2628 bin
|= BYTE_OPERATION
;
2633 /* Word operation - this is the default. */
2641 as_warn (_("no size modifier after period, .w assumed"));
2645 as_bad (_("unrecognised instruction size modifier .%c"),
2657 if (*line
&& ! ISSPACE (*line
))
2659 as_bad (_("junk found after instruction: %s.%s"),
2660 opcode
->name
, line
);
2664 /* Catch the case where the programmer has used a ".a" size modifier on an
2665 instruction that does not support it. Look for an alternative extended
2666 instruction that has the same name without the period. Eg: "add.a"
2667 becomes "adda". Although this not an officially supported way of
2668 specifying instruction aliases other MSP430 assemblers allow it. So we
2669 support it for compatibility purposes. */
2670 if (addr_op
&& opcode
->fmt
>= 0)
2672 const char * old_name
= opcode
->name
;
2675 sprintf (real_name
, "%sa", old_name
);
2676 opcode
= hash_find (msp430_hash
, real_name
);
2679 as_bad (_("instruction %s.a does not exist"), old_name
);
2682 #if 0 /* Enable for debugging. */
2683 as_warn ("treating %s.a as %s", old_name
, real_name
);
2686 bin
= opcode
->bin_opcode
;
2689 if (opcode
->fmt
!= -1
2690 && opcode
->insn_opnumb
2691 && (!*line
|| *line
== '\n'))
2693 as_bad (ngettext ("instruction %s requires %d operand",
2694 "instruction %s requires %d operands",
2695 opcode
->insn_opnumb
),
2696 opcode
->name
, opcode
->insn_opnumb
);
2700 memset (l1
, 0, sizeof (l1
));
2701 memset (l2
, 0, sizeof (l2
));
2702 memset (&op1
, 0, sizeof (op1
));
2703 memset (&op2
, 0, sizeof (op2
));
2707 if ((fmt
= opcode
->fmt
) < 0)
2709 if (! target_is_430x ())
2711 as_bad (_("instruction %s requires MSP430X mcu"),
2722 /* If requested set the extended instruction repeat count. */
2725 if (repeat_count
> 0)
2726 extended
|= (repeat_count
- 1);
2728 extended
|= (1 << 7) | (- repeat_count
);
2731 as_bad (_("unable to repeat %s insn"), opcode
->name
);
2736 /* The previous instruction set this flag if it wants to check if this insn
2740 if (! is_opcode ("nop"))
2744 switch (check_for_nop
& - check_for_nop
)
2746 case NOP_CHECK_INTERRUPT
:
2747 /* NOP_CHECK_INTERRUPT rules:
2748 1. 430 and 430x ISA require a NOP after DINT.
2749 2. Only the 430x ISA requires NOP before EINT (this has
2750 been dealt with in the previous call to this function).
2751 3. Only the 430x ISA requires NOP after every EINT.
2753 if (gen_interrupt_nops
|| warn_interrupt_nops
)
2755 if (prev_insn_is_dint
)
2757 if (gen_interrupt_nops
)
2760 if (warn_interrupt_nops
)
2761 as_warn (_(INSERT_NOP_AFTER_DINT
));
2764 as_warn (_(WARN_NOP_AFTER_DINT
));
2766 else if (prev_insn_is_eint
)
2768 if (gen_interrupt_nops
)
2771 if (warn_interrupt_nops
)
2772 as_warn (_(INSERT_NOP_AFTER_EINT
));
2775 as_warn (_(WARN_NOP_AFTER_EINT
));
2777 /* If we get here it's because the last instruction was
2778 determined to either disable or enable interrupts, but
2779 we're not sure which.
2780 We have no information yet about what effect the
2781 current instruction has on interrupts, that has to be
2783 The last insn may have required a NOP after it, so we
2784 deal with that now. */
2787 if (gen_interrupt_nops
)
2790 if (warn_interrupt_nops
)
2791 as_warn (_(INSERT_NOP_AFTER_UNKNOWN
));
2794 /* warn_unsure_interrupt was called on the previous
2796 as_warn (_(WARN_NOP_AFTER_UNKNOWN
));
2801 case NOP_CHECK_CPU12
:
2802 if (silicon_errata_warn
& SILICON_ERRATA_CPU12
)
2803 as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
2805 if (silicon_errata_fix
& SILICON_ERRATA_CPU12
)
2809 case NOP_CHECK_CPU19
:
2810 if (silicon_errata_warn
& SILICON_ERRATA_CPU19
)
2811 as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
2813 if (silicon_errata_fix
& SILICON_ERRATA_CPU19
)
2818 as_bad (_("internal error: unknown nop check state"));
2821 check_for_nop
&= ~ (check_for_nop
& - check_for_nop
);
2823 while (check_for_nop
);
2830 case 0: /* Emulated. */
2831 switch (opcode
->insn_opnumb
)
2834 if (is_opcode ("eint"))
2835 warn_eint_nop (prev_insn_is_nop
, prev_insn_is_dint
);
2837 /* Set/clear bits instructions. */
2841 extended
|= BYTE_OPERATION
;
2843 /* Emit the extension word. */
2845 frag
= frag_more (2);
2846 bfd_putl16 (extended
, frag
);
2850 frag
= frag_more (2);
2851 bfd_putl16 ((bfd_vma
) bin
, frag
);
2852 dwarf2_emit_insn (insn_length
);
2856 /* Something which works with destination operand. */
2857 line
= extract_operand (line
, l1
, sizeof (l1
));
2858 res
= msp430_dstoperand (&op1
, l1
, opcode
->bin_opcode
, extended_op
, TRUE
);
2862 bin
|= (op1
.reg
| (op1
.am
<< 7));
2864 /* If the PC is the destination... */
2865 if (op1
.am
== 0 && op1
.reg
== 0
2866 /* ... and the opcode alters the SR. */
2867 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
2868 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
2870 if (silicon_errata_fix
& SILICON_ERRATA_CPU11
)
2871 as_bad (_("CPU11: PC is destination of SR altering instruction"));
2872 else if (silicon_errata_warn
& SILICON_ERRATA_CPU11
)
2873 as_warn (_("CPU11: PC is destination of SR altering instruction"));
2876 /* If the status register is the destination... */
2877 if (op1
.am
== 0 && op1
.reg
== 2
2878 /* ... and the opcode alters the SR. */
2879 && (is_opcode ("adc") || is_opcode ("dec") || is_opcode ("decd")
2880 || is_opcode ("inc") || is_opcode ("incd") || is_opcode ("inv")
2881 || is_opcode ("sbc") || is_opcode ("sxt")
2882 || is_opcode ("adcx") || is_opcode ("decx") || is_opcode ("decdx")
2883 || is_opcode ("incx") || is_opcode ("incdx") || is_opcode ("invx")
2884 || is_opcode ("sbcx")
2887 if (silicon_errata_fix
& SILICON_ERRATA_CPU13
)
2888 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2889 else if (silicon_errata_warn
& SILICON_ERRATA_CPU13
)
2890 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2893 /* Compute the entire instruction length, in bytes. */
2894 op_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2895 insn_length
+= op_length
;
2896 frag
= frag_more (op_length
);
2897 where
= frag
- frag_now
->fr_literal
;
2902 extended
|= BYTE_OPERATION
;
2904 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2906 as_bad (_("repeat instruction used with non-register mode instruction"));
2910 if (op1
.mode
== OP_EXP
)
2912 if (op1
.exp
.X_op
== O_constant
)
2913 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2915 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
2916 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2917 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2919 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2920 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2923 /* Emit the extension word. */
2924 bfd_putl16 (extended
, frag
);
2929 bfd_putl16 ((bfd_vma
) bin
, frag
);
2933 if (op1
.mode
== OP_EXP
)
2935 if (op1
.exp
.X_op
== O_constant
)
2937 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2941 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2946 fix_new_exp (frag_now
, where
, 2,
2947 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2949 fix_new_exp (frag_now
, where
, 2,
2950 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2955 dwarf2_emit_insn (insn_length
);
2959 /* Shift instruction. */
2960 line
= extract_operand (line
, l1
, sizeof (l1
));
2961 strncpy (l2
, l1
, sizeof (l2
));
2962 l2
[sizeof (l2
) - 1] = '\0';
2963 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2964 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2967 break; /* An error occurred. All warnings were done before. */
2969 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2) + (op2
.ol
* 2);
2970 frag
= frag_more (insn_length
);
2971 where
= frag
- frag_now
->fr_literal
;
2973 if (target_is_430xv2 ()
2974 && op1
.mode
== OP_REG
2976 && (is_opcode ("rlax")
2977 || is_opcode ("rlcx")
2978 || is_opcode ("rla")
2979 || is_opcode ("rlc")))
2981 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2985 /* If the status register is the destination... */
2986 if (op1
.am
== 0 && op1
.reg
== 2
2987 /* ... and the opcode alters the SR. */
2988 && (is_opcode ("rla") || is_opcode ("rlc")
2989 || is_opcode ("rlax") || is_opcode ("rlcx")
2990 || is_opcode ("sxt") || is_opcode ("sxtx")
2991 || is_opcode ("swpb")
2994 if (silicon_errata_fix
& SILICON_ERRATA_CPU13
)
2995 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2996 else if (silicon_errata_warn
& SILICON_ERRATA_CPU13
)
2997 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3003 extended
|= BYTE_OPERATION
;
3005 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
3007 as_bad (_("repeat instruction used with non-register mode instruction"));
3011 if (op1
.mode
== OP_EXP
)
3013 if (op1
.exp
.X_op
== O_constant
)
3014 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
3016 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3017 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3018 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
3020 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3021 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
3024 if (op2
.mode
== OP_EXP
)
3026 if (op2
.exp
.X_op
== O_constant
)
3027 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
3029 else if (op1
.mode
== OP_EXP
)
3030 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
3031 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3032 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
3034 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
3035 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
3036 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
3039 /* Emit the extension word. */
3040 bfd_putl16 (extended
, frag
);
3045 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
3046 bfd_putl16 ((bfd_vma
) bin
, frag
);
3050 if (op1
.mode
== OP_EXP
)
3052 if (op1
.exp
.X_op
== O_constant
)
3054 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
3058 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
3062 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3063 fix_new_exp (frag_now
, where
, 2,
3064 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
3066 fix_new_exp (frag_now
, where
, 2,
3067 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3074 if (op2
.mode
== OP_EXP
)
3076 if (op2
.exp
.X_op
== O_constant
)
3078 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
3082 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
3086 if (op2
.reg
) /* Not PC relative. */
3087 fix_new_exp (frag_now
, where
, 2,
3088 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
3090 fix_new_exp (frag_now
, where
, 2,
3091 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3096 dwarf2_emit_insn (insn_length
);
3100 /* Branch instruction => mov dst, r0. */
3103 as_bad ("Internal error: state 0/3 not coded for extended instructions");
3107 line
= extract_operand (line
, l1
, sizeof (l1
));
3108 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, FALSE
);
3114 bin
|= ((op1
.reg
<< 8) | (op1
.am
<< 4));
3115 op_length
= 2 + 2 * op1
.ol
;
3116 frag
= frag_more (op_length
);
3117 where
= frag
- frag_now
->fr_literal
;
3118 bfd_putl16 ((bfd_vma
) bin
, frag
);
3120 if (op1
.mode
== OP_EXP
)
3122 if (op1
.exp
.X_op
== O_constant
)
3124 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
+ 2);
3130 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
3132 if (op1
.reg
|| op1
.am
== 3)
3133 fix_new_exp (frag_now
, where
, 2,
3134 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
3136 fix_new_exp (frag_now
, where
, 2,
3137 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3141 dwarf2_emit_insn (insn_length
+ op_length
);
3145 /* CALLA instructions. */
3146 fix_emitted
= FALSE
;
3148 line
= extract_operand (line
, l1
, sizeof (l1
));
3151 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
,
3152 extended_op
, FALSE
);
3158 op_length
= 2 + 2 * op1
.ol
;
3159 frag
= frag_more (op_length
);
3160 where
= frag
- frag_now
->fr_literal
;
3168 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
3169 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
3172 else if (op1
.am
== 1)
3178 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
3179 BFD_RELOC_MSP430X_PCR20_CALL
);
3183 bin
|= 0x50 | op1
.reg
;
3185 else if (op1
.am
== 0)
3186 bin
|= 0x40 | op1
.reg
;
3188 else if (op1
.am
== 1)
3192 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
3193 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
3196 else if (op1
.am
== 2)
3197 bin
|= 0x60 | op1
.reg
;
3198 else if (op1
.am
== 3)
3199 bin
|= 0x70 | op1
.reg
;
3201 bfd_putl16 ((bfd_vma
) bin
, frag
);
3203 if (op1
.mode
== OP_EXP
)
3207 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1
.ol
);
3211 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
3214 fix_new_exp (frag_now
, where
+ 2, 2,
3215 &(op1
.exp
), FALSE
, BFD_RELOC_16
);
3218 dwarf2_emit_insn (insn_length
+ op_length
);
3226 /* [POP|PUSH]M[.A] #N, Rd */
3227 line
= extract_operand (line
, l1
, sizeof (l1
));
3228 line
= extract_operand (line
, l2
, sizeof (l2
));
3232 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
3235 end
= parse_exp (l1
+ 1, &(op1
.exp
));
3236 if (end
!= NULL
&& *end
!= 0)
3238 as_bad (_("extra characters '%s' at end of constant expression '%s'"), end
, l1
);
3241 if (op1
.exp
.X_op
!= O_constant
)
3243 as_bad (_("expected constant expression as first argument of %s"),
3248 if ((reg
= check_reg (l2
)) == -1)
3250 as_bad (_("expected register as second argument of %s"),
3256 frag
= frag_more (op_length
);
3257 where
= frag
- frag_now
->fr_literal
;
3258 bin
= opcode
->bin_opcode
;
3261 n
= op1
.exp
.X_add_number
;
3262 bin
|= (n
- 1) << 4;
3263 if (is_opcode ("pushm"))
3267 if (reg
- n
+ 1 < 0)
3269 as_bad (_("Too many registers popped"));
3273 /* CPU21 errata: cannot use POPM to restore the SR register. */
3274 if (target_is_430xv2 ()
3275 && (reg
- n
+ 1 < 3)
3277 && is_opcode ("popm"))
3279 as_bad (_("Cannot use POPM to restore the SR register"));
3283 bin
|= (reg
- n
+ 1);
3286 bfd_putl16 ((bfd_vma
) bin
, frag
);
3287 dwarf2_emit_insn (op_length
);
3296 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
3297 if (extended
& 0xff)
3299 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
3303 line
= extract_operand (line
, l1
, sizeof (l1
));
3304 line
= extract_operand (line
, l2
, sizeof (l2
));
3308 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
3311 end
= parse_exp (l1
+ 1, &(op1
.exp
));
3312 if (end
!= NULL
&& *end
!= 0)
3314 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
3317 if (op1
.exp
.X_op
!= O_constant
)
3319 as_bad (_("expected constant expression as first argument of %s"),
3323 n
= op1
.exp
.X_add_number
;
3326 as_bad (_("expected first argument of %s to be in the range 1-4"),
3331 if ((reg
= check_reg (l2
)) == -1)
3333 as_bad (_("expected register as second argument of %s"),
3338 if (target_is_430xv2 () && reg
== 0)
3340 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
3345 frag
= frag_more (op_length
);
3346 where
= frag
- frag_now
->fr_literal
;
3348 bin
= opcode
->bin_opcode
;
3351 bin
|= (n
- 1) << 10;
3354 bfd_putl16 ((bfd_vma
) bin
, frag
);
3355 dwarf2_emit_insn (op_length
);
3361 bfd_boolean need_reloc
= FALSE
;
3365 /* ADDA, CMPA and SUBA address instructions. */
3366 if (extended
& 0xff)
3368 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
3372 line
= extract_operand (line
, l1
, sizeof (l1
));
3373 line
= extract_operand (line
, l2
, sizeof (l2
));
3375 bin
= opcode
->bin_opcode
;
3379 end
= parse_exp (l1
+ 1, &(op1
.exp
));
3380 if (end
!= NULL
&& *end
!= 0)
3382 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
3386 if (op1
.exp
.X_op
== O_constant
)
3388 n
= op1
.exp
.X_add_number
;
3389 if (n
> 0xfffff || n
< - (0x7ffff))
3391 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
3396 bin
|= ((n
>> 16) & 0xf) << 8;
3408 if ((n
= check_reg (l1
)) == -1)
3410 as_bad (_("expected register name or constant as first argument of %s"),
3415 bin
|= (n
<< 8) | (1 << 6);
3419 if ((reg
= check_reg (l2
)) == -1)
3421 as_bad (_("expected register as second argument of %s"),
3426 frag
= frag_more (op_length
);
3427 where
= frag
- frag_now
->fr_literal
;
3430 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
3431 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
3433 bfd_putl16 ((bfd_vma
) bin
, frag
);
3435 bfd_putl16 ((bfd_vma
) (n
& 0xffff), frag
+ 2);
3436 dwarf2_emit_insn (op_length
);
3440 case 9: /* MOVA, BRA, RETA. */
3442 bin
= opcode
->bin_opcode
;
3444 if (is_opcode ("reta"))
3446 /* The RETA instruction does not take any arguments.
3447 The implicit first argument is @SP+.
3448 The implicit second argument is PC. */
3458 line
= extract_operand (line
, l1
, sizeof (l1
));
3459 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
3460 &imm_op
, extended_op
, FALSE
);
3462 if (is_opcode ("bra"))
3464 /* This is the BRA synthetic instruction.
3465 The second argument is always PC. */
3471 line
= extract_operand (line
, l2
, sizeof (l2
));
3472 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
,
3477 break; /* Error occurred. All warnings were done before. */
3480 /* Only a restricted subset of the normal MSP430 addressing modes
3481 are supported here, so check for the ones that are allowed. */
3482 if ((op_length
= try_encode_mova (imm_op
, bin
, & op1
, & op2
,
3483 & error_message
)) == 0)
3485 as_bad (error_message
, opcode
->name
);
3488 dwarf2_emit_insn (op_length
);
3492 line
= extract_operand (line
, l1
, sizeof l1
);
3493 /* The RPT instruction only accepted immediates and registers. */
3496 end
= parse_exp (l1
+ 1, &(op1
.exp
));
3497 if (end
!= NULL
&& *end
!= 0)
3499 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
3502 if (op1
.exp
.X_op
!= O_constant
)
3504 as_bad (_("expected constant value as argument to RPT"));
3507 if (op1
.exp
.X_add_number
< 1
3508 || op1
.exp
.X_add_number
> (1 << 4))
3510 as_bad (_("expected constant in the range 2..16"));
3514 /* We silently accept and ignore a repeat count of 1. */
3515 if (op1
.exp
.X_add_number
> 1)
3516 repeat_count
= op1
.exp
.X_add_number
;
3522 if ((reg
= check_reg (l1
)) != -1)
3525 as_warn (_("PC used as an argument to RPT"));
3527 repeat_count
= - reg
;
3531 as_bad (_("expected constant or register name as argument to RPT insn"));
3538 as_bad (_("Illegal emulated instruction"));
3543 /* FIXME: Emit warning when dest reg SR(R2) is addressed with .B or .A.
3544 From f5 ref man 6.3.3:
3545 The 16-bit Status Register (SR, also called R2), used as a source or
3546 destination register, can only be used in register mode addressed
3547 with word instructions. */
3549 case 1: /* Format 1, double operand. */
3550 line
= extract_operand (line
, l1
, sizeof (l1
));
3551 line
= extract_operand (line
, l2
, sizeof (l2
));
3552 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
3553 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
3556 break; /* Error occurred. All warnings were done before. */
3559 && is_opcode ("movx")
3561 && msp430_enable_relax
)
3563 /* This is the MOVX.A instruction. See if we can convert
3564 it into the MOVA instruction instead. This saves 2 bytes. */
3565 if ((op_length
= try_encode_mova (imm_op
, 0x0000, & op1
, & op2
,
3568 dwarf2_emit_insn (op_length
);
3573 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
3575 /* If the PC is the destination... */
3576 if (op2
.am
== 0 && op2
.reg
== 0
3577 /* ... and the opcode alters the SR. */
3578 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
3579 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
3581 if (silicon_errata_fix
& SILICON_ERRATA_CPU11
)
3582 as_bad (_("CPU11: PC is destination of SR altering instruction"));
3583 else if (silicon_errata_warn
& SILICON_ERRATA_CPU11
)
3584 as_warn (_("CPU11: PC is destination of SR altering instruction"));
3587 /* If the status register is the destination... */
3588 if (op2
.am
== 0 && op2
.reg
== 2
3589 /* ... and the opcode alters the SR. */
3590 && (is_opcode ("add") || is_opcode ("addc") || is_opcode ("and")
3591 || is_opcode ("dadd") || is_opcode ("sub") || is_opcode ("subc")
3592 || is_opcode ("xor")
3593 || is_opcode ("addx") || is_opcode ("addcx") || is_opcode ("andx")
3594 || is_opcode ("daddx") || is_opcode ("subx") || is_opcode ("subcx")
3595 || is_opcode ("xorx")
3598 if (silicon_errata_fix
& SILICON_ERRATA_CPU13
)
3599 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3600 else if (silicon_errata_warn
& SILICON_ERRATA_CPU13
)
3601 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3604 /* Chain these checks for SR manipulations so we can warn if they are not
3606 if (((is_opcode ("bis") && bin
== 0xd032)
3607 || (is_opcode ("mov") && bin
== 0x4032)
3608 || (is_opcode ("xor") && bin
== 0xe032))
3609 && op1
.mode
== OP_EXP
3610 && op1
.exp
.X_op
== O_constant
3611 && (op1
.exp
.X_add_number
& 0x10) == 0x10)
3612 check_for_nop
|= NOP_CHECK_CPU19
;
3613 else if ((is_opcode ("mov") && op2
.mode
== OP_REG
&& op2
.reg
== 2))
3615 /* Any MOV with the SR as the destination either enables or disables
3617 if (op1
.mode
== OP_EXP
3618 && op1
.exp
.X_op
== O_constant
)
3620 if ((op1
.exp
.X_add_number
& 0x8) == 0x8)
3622 /* The GIE bit is being set. */
3623 warn_eint_nop (prev_insn_is_nop
, prev_insn_is_dint
);
3624 this_insn_is_eint
= TRUE
;
3627 /* The GIE bit is being cleared. */
3628 this_insn_is_dint
= TRUE
;
3630 /* If an immediate value which is covered by the constant generator
3631 is the src, then op1 will have been changed to either R2 or R3 by
3633 The only constants covered by CG1 and CG2, which have bit 3 set
3634 and therefore would enable interrupts when writing to the SR, are
3635 R2 with addresing mode 0b11 and R3 with 0b11.
3636 The addressing mode is in bits 5:4 of the binary opcode. */
3637 else if (op1
.mode
== OP_REG
3638 && (op1
.reg
== 2 || op1
.reg
== 3)
3639 && (bin
& 0x30) == 0x30)
3641 warn_eint_nop (prev_insn_is_nop
, prev_insn_is_dint
);
3642 this_insn_is_eint
= TRUE
;
3644 /* Any other use of the constant generator with destination R2, will
3645 disable interrupts. */
3646 else if (op1
.mode
== OP_REG
3647 && (op1
.reg
== 2 || op1
.reg
== 3))
3648 this_insn_is_dint
= TRUE
;
3651 /* FIXME: Couldn't work out whether the insn is enabling or
3652 disabling interrupts, so for safety need to treat it as both
3654 warn_unsure_interrupt ();
3655 check_for_nop
|= NOP_CHECK_INTERRUPT
;
3658 else if (is_eint (opcode
->name
, bin
))
3659 warn_eint_nop (prev_insn_is_nop
, prev_insn_is_dint
);
3660 else if ((bin
& 0x32) == 0x32)
3662 /* Double-operand insn with the As==0b11 and Rdst==0x2 will result in
3663 * an interrupt state change if a write happens. */
3664 /* FIXME: How strict to be here? */
3668 /* Compute the entire length of the instruction in bytes. */
3669 op_length
= (extended_op
? 2 : 0) /* The extension word. */
3670 + 2 /* The opcode */
3671 + (2 * op1
.ol
) /* The first operand. */
3672 + (2 * op2
.ol
); /* The second operand. */
3674 insn_length
+= op_length
;
3675 frag
= frag_more (op_length
);
3676 where
= frag
- frag_now
->fr_literal
;
3681 extended
|= BYTE_OPERATION
;
3683 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
3685 as_bad (_("repeat instruction used with non-register mode instruction"));
3689 /* If necessary, emit a reloc to update the extension word. */
3690 if (op1
.mode
== OP_EXP
)
3692 if (op1
.exp
.X_op
== O_constant
)
3693 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
3695 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3696 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3697 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
3699 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3700 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
3703 if (op2
.mode
== OP_EXP
)
3705 if (op2
.exp
.X_op
== O_constant
)
3706 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
3708 else if (op1
.mode
== OP_EXP
)
3709 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
3710 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3711 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
3714 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
3715 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
3716 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
3719 /* Emit the extension word. */
3720 bfd_putl16 (extended
, frag
);
3725 bfd_putl16 ((bfd_vma
) bin
, frag
);
3729 if (op1
.mode
== OP_EXP
)
3731 if (op1
.exp
.X_op
== O_constant
)
3733 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
3737 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
3741 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3742 fix_new_exp (frag_now
, where
, 2,
3743 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
3745 fix_new_exp (frag_now
, where
, 2,
3746 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3754 if (op2
.mode
== OP_EXP
)
3756 if (op2
.exp
.X_op
== O_constant
)
3758 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
3762 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
3766 if (op2
.reg
) /* Not PC relative. */
3767 fix_new_exp (frag_now
, where
, 2,
3768 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
3770 fix_new_exp (frag_now
, where
, 2,
3771 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3776 dwarf2_emit_insn (insn_length
);
3778 /* If the PC is the destination... */
3779 if (op2
.am
== 0 && op2
.reg
== 0
3780 /* ... but the opcode does not alter the destination. */
3781 && (is_opcode ("cmp") || is_opcode ("bit") || is_opcode ("cmpx")))
3782 check_for_nop
|= NOP_CHECK_CPU12
;
3785 case 2: /* Single-operand mostly instr. */
3786 if (opcode
->insn_opnumb
== 0)
3788 /* reti instruction. */
3790 frag
= frag_more (2);
3791 bfd_putl16 ((bfd_vma
) bin
, frag
);
3792 dwarf2_emit_insn (insn_length
);
3796 line
= extract_operand (line
, l1
, sizeof (l1
));
3797 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
3798 &imm_op
, extended_op
, TRUE
);
3800 break; /* Error in operand. */
3802 if (target_is_430xv2 ()
3803 && op1
.mode
== OP_REG
3805 && (is_opcode ("rrax")
3806 || is_opcode ("rrcx")
3807 || is_opcode ("rra")
3808 || is_opcode ("rrc")))
3810 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
3814 /* If the status register is the destination... */
3815 if (op1
.am
== 0 && op1
.reg
== 2
3816 /* ... and the opcode alters the SR. */
3817 && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
3819 if (silicon_errata_fix
& SILICON_ERRATA_CPU13
)
3820 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3821 else if (silicon_errata_warn
& SILICON_ERRATA_CPU13
)
3822 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3825 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
3826 frag
= frag_more (insn_length
);
3827 where
= frag
- frag_now
->fr_literal
;
3831 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
3833 /* These two instructions use a special
3834 encoding of the A/L and B/W bits. */
3835 bin
&= ~ BYTE_OPERATION
;
3839 as_bad (_("%s instruction does not accept a .b suffix"),
3844 extended
|= BYTE_OPERATION
;
3847 extended
|= BYTE_OPERATION
;
3849 if (is_opcode ("rrux"))
3850 extended
|= IGNORE_CARRY_BIT
;
3852 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
3854 as_bad (_("repeat instruction used with non-register mode instruction"));
3858 if (op1
.mode
== OP_EXP
)
3860 if (op1
.exp
.X_op
== O_constant
)
3861 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
3863 else if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3864 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3865 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
3867 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
3868 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
3871 /* Emit the extension word. */
3872 bfd_putl16 (extended
, frag
);
3877 bin
|= op1
.reg
| (op1
.am
<< 4);
3878 bfd_putl16 ((bfd_vma
) bin
, frag
);
3882 if (op1
.mode
== OP_EXP
)
3884 if (op1
.exp
.X_op
== O_constant
)
3886 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
3890 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
3894 if (op1
.reg
|| op1
.am
== 3) /* Not PC relative. */
3895 fix_new_exp (frag_now
, where
, 2,
3896 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
3898 fix_new_exp (frag_now
, where
, 2,
3899 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
3904 dwarf2_emit_insn (insn_length
);
3907 case 3: /* Conditional jumps instructions. */
3908 line
= extract_operand (line
, l1
, sizeof (l1
));
3909 /* l1 is a label. */
3918 end
= parse_exp (m
, &exp
);
3919 if (end
!= NULL
&& *end
!= 0)
3921 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
3925 /* In order to handle something like:
3929 jz 4 ; skip next 4 bytes
3932 nop ; will jump here if r5 positive or zero
3934 jCOND -n ;assumes jump n bytes backward:
3944 jCOND $n ; jump from PC in either direction. */
3946 if (exp
.X_op
== O_constant
)
3948 int x
= exp
.X_add_number
;
3952 as_warn (_("Even number required. Rounded to %d"), x
+ 1);
3956 if ((*l1
== '$' && x
> 0) || x
< 0)
3961 if (x
> 512 || x
< -511)
3963 as_bad (_("Wrong displacement %d"), x
<< 1);
3968 frag
= frag_more (2); /* Instr size is 1 word. */
3971 bfd_putl16 ((bfd_vma
) bin
, frag
);
3973 else if (exp
.X_op
== O_symbol
&& *l1
!= '$')
3976 frag
= frag_more (2); /* Instr size is 1 word. */
3977 where
= frag
- frag_now
->fr_literal
;
3978 fix_new_exp (frag_now
, where
, 2,
3979 &exp
, TRUE
, BFD_RELOC_MSP430_10_PCREL
);
3981 bfd_putl16 ((bfd_vma
) bin
, frag
);
3983 else if (*l1
== '$')
3985 as_bad (_("instruction requires label sans '$'"));
3989 ("instruction requires label or value in range -511:512"));
3990 dwarf2_emit_insn (insn_length
);
3995 as_bad (_("instruction requires label"));
4000 case 4: /* Extended jumps. */
4001 if (!msp430_enable_polys
)
4003 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
4007 line
= extract_operand (line
, l1
, sizeof (l1
));
4013 /* Ignore absolute addressing. make it PC relative anyway. */
4014 if (*m
== '#' || *m
== '$')
4017 end
= parse_exp (m
, & exp
);
4018 if (end
!= NULL
&& *end
!= 0)
4020 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
4023 if (exp
.X_op
== O_symbol
)
4025 /* Relaxation required. */
4026 struct rcodes_s rc
= msp430_rcodes
[opcode
->insn_opnumb
];
4028 if (target_is_430x ())
4029 rc
= msp430x_rcodes
[opcode
->insn_opnumb
];
4031 /* The parameter to dwarf2_emit_insn is actually the offset to
4032 the start of the insn from the fix piece of instruction that
4033 was emitted. Since next fragments may have variable size we
4034 tie debug info to the beginning of the instruction. */
4036 frag
= frag_more (8);
4037 dwarf2_emit_insn (0);
4038 bfd_putl16 ((bfd_vma
) rc
.sop
, frag
);
4039 frag
= frag_variant (rs_machine_dependent
, 8, 2,
4041 ENCODE_RELAX (rc
.lpos
, STATE_BITS10
),
4043 0, /* Offset is zero if jump dist less than 1K. */
4049 as_bad (_("instruction requires label"));
4052 case 5: /* Emulated extended branches. */
4053 if (!msp430_enable_polys
)
4055 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
4058 line
= extract_operand (line
, l1
, sizeof (l1
));
4064 /* Ignore absolute addressing. make it PC relative anyway. */
4065 if (*m
== '#' || *m
== '$')
4068 end
= parse_exp (m
, & exp
);
4069 if (end
!= NULL
&& *end
!= 0)
4071 as_bad (_("extra characters '%s' at end of operand '%s'"), end
, l1
);
4074 if (exp
.X_op
== O_symbol
)
4076 /* Relaxation required. */
4077 struct hcodes_s hc
= msp430_hcodes
[opcode
->insn_opnumb
];
4079 if (target_is_430x ())
4080 hc
= msp430x_hcodes
[opcode
->insn_opnumb
];
4083 frag
= frag_more (8);
4084 dwarf2_emit_insn (0);
4085 bfd_putl16 ((bfd_vma
) hc
.op0
, frag
);
4086 bfd_putl16 ((bfd_vma
) hc
.op1
, frag
+2);
4088 frag
= frag_variant (rs_machine_dependent
, 8, 2,
4089 ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
), /* Wild guess. */
4091 0, /* Offset is zero if jump dist less than 1K. */
4097 as_bad (_("instruction requires label"));
4101 as_bad (_("Illegal instruction or not implemented opcode."));
4104 if (is_opcode ("nop"))
4106 prev_insn_is_nop
= TRUE
;
4107 prev_insn_is_dint
= FALSE
;
4108 prev_insn_is_eint
= FALSE
;
4110 else if (this_insn_is_dint
|| is_dint (opcode
->name
, bin
))
4112 prev_insn_is_dint
= TRUE
;
4113 prev_insn_is_eint
= FALSE
;
4114 prev_insn_is_nop
= FALSE
;
4115 check_for_nop
|= NOP_CHECK_INTERRUPT
;
4117 /* NOP is not needed after EINT for 430 ISA. */
4118 else if (target_is_430x () && (this_insn_is_eint
|| is_eint (opcode
->name
, bin
)))
4120 prev_insn_is_eint
= TRUE
;
4121 prev_insn_is_nop
= FALSE
;
4122 prev_insn_is_dint
= FALSE
;
4123 check_for_nop
|= NOP_CHECK_INTERRUPT
;
4127 prev_insn_is_nop
= FALSE
;
4128 prev_insn_is_dint
= FALSE
;
4129 prev_insn_is_eint
= FALSE
;
4132 input_line_pointer
= line
;
4137 md_assemble (char * str
)
4139 struct msp430_opcode_s
* opcode
;
4143 str
= skip_space (str
); /* Skip leading spaces. */
4144 str
= extract_cmd (str
, cmd
, sizeof (cmd
) - 1);
4148 char a
= TOLOWER (cmd
[i
]);
4155 as_bad (_("can't find opcode"));
4159 opcode
= (struct msp430_opcode_s
*) hash_find (msp430_hash
, cmd
);
4163 as_bad (_("unknown opcode `%s'"), cmd
);
4168 char *__t
= input_line_pointer
;
4170 msp430_operands (opcode
, str
);
4171 input_line_pointer
= __t
;
4175 /* GAS will call this function for each section at the end of the assembly,
4176 to permit the CPU backend to adjust the alignment of a section. */
4179 md_section_align (asection
* seg
, valueT addr
)
4181 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4183 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
4186 /* If you define this macro, it should return the offset between the
4187 address of a PC relative fixup and the position from which the PC
4188 relative adjustment should be made. On many processors, the base
4189 of a PC relative instruction is the next instruction, so this
4190 macro would return the length of an instruction. */
4193 md_pcrel_from_section (fixS
* fixp
, segT sec
)
4195 if (fixp
->fx_addsy
!= (symbolS
*) NULL
4196 && (!S_IS_DEFINED (fixp
->fx_addsy
)
4197 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
4200 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4203 /* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
4204 Now it handles the situation when relocations
4205 have to be passed to linker. */
4207 msp430_force_relocation_local (fixS
*fixp
)
4209 if (fixp
->fx_r_type
== BFD_RELOC_MSP430_10_PCREL
)
4213 if (msp430_enable_polys
4214 && !msp430_enable_relax
)
4221 /* GAS will call this for each fixup. It should store the correct
4222 value in the object file. */
4224 md_apply_fix (fixS
* fixp
, valueT
* valuep
, segT seg
)
4226 unsigned char * where
;
4230 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
4235 else if (fixp
->fx_pcrel
)
4237 segT s
= S_GET_SEGMENT (fixp
->fx_addsy
);
4239 if (fixp
->fx_addsy
&& (s
== seg
|| s
== absolute_section
))
4241 /* FIXME: We can appear here only in case if we perform a pc
4242 relative jump to the label which is i) global, ii) locally
4243 defined or this is a jump to an absolute symbol.
4244 If this is an absolute symbol -- everything is OK.
4245 If this is a global label, we've got a symbol value defined
4247 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
4248 from this section start
4249 2. *valuep will contain the real offset from jump insn to the
4251 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
4252 will be incorrect. Therefore remove s_get_value. */
4253 value
= /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep
;
4261 value
= fixp
->fx_offset
;
4263 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
4265 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
4267 value
-= S_GET_VALUE (fixp
->fx_subsy
);
4273 fixp
->fx_no_overflow
= 1;
4275 /* If polymorphs are enabled and relax disabled.
4276 do not kill any relocs and pass them to linker. */
4277 if (msp430_enable_polys
4278 && !msp430_enable_relax
)
4281 || S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
4282 fixp
->fx_done
= 1; /* It is ok to kill 'abs' reloc. */
4289 /* Fetch the instruction, insert the fully resolved operand
4290 value, and stuff the instruction back again. */
4291 where
= (unsigned char *) fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
4293 insn
= bfd_getl16 (where
);
4295 switch (fixp
->fx_r_type
)
4297 case BFD_RELOC_MSP430_10_PCREL
:
4299 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4300 _("odd address operand: %ld"), value
);
4302 /* Jumps are in words. */
4304 --value
; /* Correct PC. */
4306 if (value
< -512 || value
> 511)
4307 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4308 _("operand out of range: %ld"), value
);
4310 value
&= 0x3ff; /* get rid of extended sign */
4311 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
4314 case BFD_RELOC_MSP430X_PCR16
:
4315 case BFD_RELOC_MSP430_RL_PCREL
:
4316 case BFD_RELOC_MSP430_16_PCREL
:
4318 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4319 _("odd address operand: %ld"), value
);
4322 case BFD_RELOC_MSP430_16_PCREL_BYTE
:
4323 /* Nothing to be corrected here. */
4324 if (value
< -32768 || value
> 65536)
4325 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4326 _("operand out of range: %ld"), value
);
4329 case BFD_RELOC_MSP430X_ABS16
:
4330 case BFD_RELOC_MSP430_16
:
4332 case BFD_RELOC_MSP430_16_BYTE
:
4333 value
&= 0xffff; /* Get rid of extended sign. */
4334 bfd_putl16 ((bfd_vma
) value
, where
);
4337 case BFD_RELOC_MSP430_ABS_HI16
:
4339 value
&= 0xffff; /* Get rid of extended sign. */
4340 bfd_putl16 ((bfd_vma
) value
, where
);
4344 bfd_putl16 ((bfd_vma
) value
, where
);
4347 case BFD_RELOC_MSP430_ABS8
:
4349 bfd_put_8 (NULL
, (bfd_vma
) value
, where
);
4352 case BFD_RELOC_MSP430X_ABS20_EXT_SRC
:
4353 case BFD_RELOC_MSP430X_PCR20_EXT_SRC
:
4354 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
4356 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 7) | insn
), where
);
4359 case BFD_RELOC_MSP430X_ABS20_ADR_SRC
:
4360 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
4362 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 8) | insn
), where
);
4365 case BFD_RELOC_MSP430X_ABS20_EXT_ODST
:
4366 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
4368 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
4371 case BFD_RELOC_MSP430X_PCR20_CALL
:
4372 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
4374 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
4377 case BFD_RELOC_MSP430X_ABS20_EXT_DST
:
4378 case BFD_RELOC_MSP430X_PCR20_EXT_DST
:
4379 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
4381 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
4384 case BFD_RELOC_MSP430X_PCR20_EXT_ODST
:
4385 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
4387 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
4390 case BFD_RELOC_MSP430X_ABS20_ADR_DST
:
4391 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
4393 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
4397 as_fatal (_("line %d: unknown relocation type: 0x%x"),
4398 fixp
->fx_line
, fixp
->fx_r_type
);
4404 fixp
->fx_addnumber
= value
;
4409 S_IS_GAS_LOCAL (symbolS
* s
)
4416 name
= S_GET_NAME (s
);
4417 len
= strlen (name
) - 1;
4419 return name
[len
] == 1 || name
[len
] == 2;
4422 /* GAS will call this to generate a reloc, passing the resulting reloc
4423 to `bfd_install_relocation'. This currently works poorly, as
4424 `bfd_install_relocation' often does the wrong thing, and instances of
4425 `tc_gen_reloc' have been written to work around the problems, which
4426 in turns makes it difficult to fix `bfd_install_relocation'. */
4428 /* If while processing a fixup, a reloc really needs to be created
4429 then it is done here. */
4432 tc_gen_reloc (asection
* seg ATTRIBUTE_UNUSED
, fixS
* fixp
)
4434 static arelent
* no_relocs
= NULL
;
4435 static arelent
* relocs
[MAX_RELOC_EXPANSION
+ 1];
4438 reloc
= XNEW (arelent
);
4439 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4440 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4442 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
4444 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4445 _("reloc %d not supported by object file format"),
4446 (int) fixp
->fx_r_type
);
4455 && S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
4457 fixp
->fx_offset
-= S_GET_VALUE (fixp
->fx_subsy
);
4458 fixp
->fx_subsy
= NULL
;
4461 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
4463 asection
*asec
, *ssec
;
4465 asec
= S_GET_SEGMENT (fixp
->fx_addsy
);
4466 ssec
= S_GET_SEGMENT (fixp
->fx_subsy
);
4468 /* If we have a difference between two different, non-absolute symbols
4469 we must generate two relocs (one for each symbol) and allow the
4470 linker to resolve them - relaxation may change the distances between
4471 symbols, even local symbols defined in the same section.
4473 Unfortunately we cannot do this with assembler generated local labels
4474 because there can be multiple incarnations of the same label, with
4475 exactly the same name, in any given section and the linker will have
4476 no way to identify the correct one. Instead we just have to hope
4477 that no relaxation will occur between the local label and the other
4478 symbol in the expression.
4480 Similarly we have to compute differences between symbols in the .eh_frame
4481 section as the linker is not smart enough to apply relocations there
4482 before attempting to process it. */
4483 if ((ssec
!= absolute_section
|| asec
!= absolute_section
)
4484 && (fixp
->fx_addsy
!= fixp
->fx_subsy
)
4485 && strcmp (ssec
->name
, ".eh_frame") != 0
4486 && ! S_IS_GAS_LOCAL (fixp
->fx_addsy
)
4487 && ! S_IS_GAS_LOCAL (fixp
->fx_subsy
))
4489 arelent
* reloc2
= XNEW (arelent
);
4494 reloc2
->address
= reloc
->address
;
4495 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
,
4496 BFD_RELOC_MSP430_SYM_DIFF
);
4497 reloc2
->addend
= - S_GET_VALUE (fixp
->fx_subsy
);
4499 if (ssec
== absolute_section
)
4500 reloc2
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
4503 reloc2
->sym_ptr_ptr
= XNEW (asymbol
*);
4504 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_subsy
);
4507 reloc
->addend
= fixp
->fx_offset
;
4508 if (asec
== absolute_section
)
4510 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
4511 reloc
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
4515 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4516 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4525 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
4527 reloc
->addend
= (S_GET_VALUE (fixp
->fx_addsy
)
4528 - S_GET_VALUE (fixp
->fx_subsy
) + fixp
->fx_offset
);
4530 switch (fixp
->fx_r_type
)
4533 md_number_to_chars (fixpos
, reloc
->addend
, 1);
4537 md_number_to_chars (fixpos
, reloc
->addend
, 2);
4541 md_number_to_chars (fixpos
, reloc
->addend
, 3);
4545 md_number_to_chars (fixpos
, reloc
->addend
, 4);
4550 = (asymbol
**) bfd_abs_section_ptr
->symbol_ptr_ptr
;
4561 if (fixp
->fx_r_type
== BFD_RELOC_MSP430X_ABS16
4562 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
4564 bfd_vma amount
= S_GET_VALUE (fixp
->fx_addsy
);
4565 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
4567 md_number_to_chars (fixpos
, amount
, 2);
4572 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4573 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4574 reloc
->addend
= fixp
->fx_offset
;
4576 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4577 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4578 reloc
->address
= fixp
->fx_offset
;
4585 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
4586 asection
* segment_type ATTRIBUTE_UNUSED
)
4588 if (fragP
->fr_symbol
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
4590 /* This is a jump -> pcrel mode. Nothing to do much here.
4591 Return value == 2. */
4593 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_BITS10
);
4595 else if (fragP
->fr_symbol
)
4597 /* It's got a segment, but it's not ours. Even if fr_symbol is in
4598 an absolute segment, we don't know a displacement until we link
4599 object files. So it will always be long. This also applies to
4600 labels in a subsegment of current. Liker may relax it to short
4601 jump later. Return value == 8. */
4603 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_WORD
);
4607 /* We know the abs value. may be it is a jump to fixed address.
4608 Impossible in our case, cause all constants already handled. */
4610 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_UNDEF
);
4613 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4617 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
,
4618 asection
* sec ATTRIBUTE_UNUSED
,
4624 struct rcodes_s
* cc
= NULL
;
4625 struct hcodes_s
* hc
= NULL
;
4627 switch (fragP
->fr_subtype
)
4629 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_BITS10
):
4630 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_BITS10
):
4631 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_BITS10
):
4632 /* We do not have to convert anything here.
4633 Just apply a fix. */
4634 rela
= BFD_RELOC_MSP430_10_PCREL
;
4637 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_WORD
):
4638 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_UNDEF
):
4639 /* Convert uncond branch jmp lab -> br lab. */
4640 if (target_is_430x ())
4641 cc
= msp430x_rcodes
+ 7;
4643 cc
= msp430_rcodes
+ 7;
4644 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
4645 bfd_putl16 (cc
->lop0
, where
);
4646 rela
= BFD_RELOC_MSP430_RL_PCREL
;
4650 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_WORD
):
4651 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_UNDEF
):
4653 /* Other simple branches. */
4654 int insn
= bfd_getl16 (fragP
->fr_opcode
);
4657 /* Find actual instruction. */
4658 if (target_is_430x ())
4660 for (i
= 0; i
< 7 && !cc
; i
++)
4661 if (msp430x_rcodes
[i
].sop
== insn
)
4662 cc
= msp430x_rcodes
+ i
;
4666 for (i
= 0; i
< 7 && !cc
; i
++)
4667 if (msp430_rcodes
[i
].sop
== insn
)
4668 cc
= & msp430_rcodes
[i
];
4671 if (!cc
|| !cc
->name
)
4672 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
4673 __FUNCTION__
, (long) insn
);
4674 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
4675 bfd_putl16 (cc
->lop0
, where
);
4676 bfd_putl16 (cc
->lop1
, where
+ 2);
4677 rela
= BFD_RELOC_MSP430_RL_PCREL
;
4682 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_WORD
):
4683 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_UNDEF
):
4684 if (target_is_430x ())
4685 cc
= msp430x_rcodes
+ 6;
4687 cc
= msp430_rcodes
+ 6;
4688 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
4689 bfd_putl16 (cc
->lop0
, where
);
4690 bfd_putl16 (cc
->lop1
, where
+ 2);
4691 bfd_putl16 (cc
->lop2
, where
+ 4);
4692 rela
= BFD_RELOC_MSP430_RL_PCREL
;
4696 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
):
4698 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
4701 if (target_is_430x ())
4703 for (i
= 0; i
< 4 && !hc
; i
++)
4704 if (msp430x_hcodes
[i
].op1
== insn
)
4705 hc
= msp430x_hcodes
+ i
;
4709 for (i
= 0; i
< 4 && !hc
; i
++)
4710 if (msp430_hcodes
[i
].op1
== insn
)
4711 hc
= &msp430_hcodes
[i
];
4713 if (!hc
|| !hc
->name
)
4714 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4715 __FUNCTION__
, (long) insn
);
4716 rela
= BFD_RELOC_MSP430_10_PCREL
;
4717 /* Apply a fix for a first label if necessary.
4718 another fix will be applied to the next word of insn anyway. */
4720 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4721 fragP
->fr_offset
, TRUE
, rela
);
4727 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_WORD
):
4728 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_UNDEF
):
4730 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
4733 if (target_is_430x ())
4735 for (i
= 0; i
< 4 && !hc
; i
++)
4736 if (msp430x_hcodes
[i
].op1
== insn
)
4737 hc
= msp430x_hcodes
+ i
;
4741 for (i
= 0; i
< 4 && !hc
; i
++)
4742 if (msp430_hcodes
[i
].op1
== insn
)
4743 hc
= & msp430_hcodes
[i
];
4745 if (!hc
|| !hc
->name
)
4746 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4747 __FUNCTION__
, (long) insn
);
4748 rela
= BFD_RELOC_MSP430_RL_PCREL
;
4749 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
4750 bfd_putl16 (hc
->lop0
, where
);
4751 bfd_putl16 (hc
->lop1
, where
+ 2);
4752 bfd_putl16 (hc
->lop2
, where
+ 4);
4758 as_fatal (_("internal inconsistency problem in %s: %lx"),
4759 __FUNCTION__
, (long) fragP
->fr_subtype
);
4763 /* Now apply fix. */
4764 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4765 fragP
->fr_offset
, TRUE
, rela
);
4766 /* Just fixed 2 bytes. */
4770 /* Relax fragment. Mostly stolen from hc11 and mcore
4771 which arches I think I know. */
4774 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
* fragP
,
4775 long stretch ATTRIBUTE_UNUSED
)
4780 const relax_typeS
*this_type
;
4781 const relax_typeS
*start_type
;
4782 relax_substateT next_state
;
4783 relax_substateT this_state
;
4784 const relax_typeS
*table
= md_relax_table
;
4786 /* Nothing to be done if the frag has already max size. */
4787 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_UNDEF
4788 || RELAX_STATE (fragP
->fr_subtype
) == STATE_WORD
)
4791 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_BITS10
)
4793 symbolP
= fragP
->fr_symbol
;
4794 if (symbol_resolved_p (symbolP
))
4795 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
4797 /* We know the offset. calculate a distance. */
4798 aim
= S_GET_VALUE (symbolP
) - fragP
->fr_address
- fragP
->fr_fix
;
4801 if (!msp430_enable_relax
)
4803 /* Relaxation is not enabled. So, make all jump as long ones
4804 by setting 'aim' to quite high value. */
4808 this_state
= fragP
->fr_subtype
;
4809 start_type
= this_type
= table
+ this_state
;
4813 /* Look backwards. */
4814 for (next_state
= this_type
->rlx_more
; next_state
;)
4815 if (aim
>= this_type
->rlx_backward
|| !this_type
->rlx_backward
)
4819 /* Grow to next state. */
4820 this_state
= next_state
;
4821 this_type
= table
+ this_state
;
4822 next_state
= this_type
->rlx_more
;
4827 /* Look forwards. */
4828 for (next_state
= this_type
->rlx_more
; next_state
;)
4829 if (aim
<= this_type
->rlx_forward
|| !this_type
->rlx_forward
)
4833 /* Grow to next state. */
4834 this_state
= next_state
;
4835 this_type
= table
+ this_state
;
4836 next_state
= this_type
->rlx_more
;
4840 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
4842 fragP
->fr_subtype
= this_state
;
4846 /* Return FALSE if the fixup in fixp should be left alone and not
4847 adjusted. We return FALSE here so that linker relaxation will
4851 msp430_fix_adjustable (struct fix
*fixp ATTRIBUTE_UNUSED
)
4853 /* If the symbol is in a non-code section then it should be OK. */
4855 && ((S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_CODE
) == 0))
4861 /* Set the contents of the .MSP430.attributes section. */
4864 msp430_md_end (void)
4868 if (gen_interrupt_nops
)
4871 if (warn_interrupt_nops
)
4872 as_warn (INSERT_NOP_AT_EOF
);
4874 else if (warn_interrupt_nops
)
4875 as_warn (_(WARN_NOP_AT_EOF
));
4878 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_ISA
,
4879 target_is_430x () ? 2 : 1);
4881 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Code_Model
,
4882 large_model
? 2 : 1);
4884 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Data_Model
,
4885 large_model
? 2 : 1);
4888 /* Returns FALSE if there is a msp430 specific reason why the
4889 subtraction of two same-section symbols cannot be computed by
4893 msp430_allow_local_subtract (expressionS
* left
,
4894 expressionS
* right
,
4897 /* If the symbols are not in a code section then they are OK. */
4898 if ((section
->flags
& SEC_CODE
) == 0)
4901 if (S_IS_GAS_LOCAL (left
->X_add_symbol
) || S_IS_GAS_LOCAL (right
->X_add_symbol
))
4904 if (left
->X_add_symbol
== right
->X_add_symbol
)
4907 /* We have to assume that there may be instructions between the
4908 two symbols and that relaxation may increase the distance between