1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2014 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #define PUSH_1X_WORKAROUND
27 #include "opcode/msp430.h"
28 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "elf/msp430.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax
;
70 int msp430_enable_polys
;
72 /* Set linkrelax here to avoid fixups in most sections. */
75 /* GCC uses the some condition codes which we'll
76 implement as new polymorph instructions.
78 COND EXPL SHORT JUMP LONG JUMP
79 ===============================================
80 eq == jeq jne +4; br lab
81 ne != jne jeq +4; br lab
83 ltn honours no-overflow flag
84 ltn < jn jn +2; jmp +4; br lab
86 lt < jl jge +4; br lab
87 ltu < jlo lhs +4; br lab
93 ge >= jge jl +4; br lab
94 geu >= jhs jlo +4; br lab
95 ===============================================
97 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
98 beq,bne,blt,bltn,bltu,bge,bgeu
99 'u' means unsigned compares
101 Also, we add 'jump' instruction:
102 jump UNCOND -> jmp br lab
104 They will have fmt == 4, and insn_opnumb == number of instruction. */
109 int index
; /* Corresponding insn_opnumb. */
110 int sop
; /* Opcode if jump length is short. */
111 long lpos
; /* Label position. */
112 long lop0
; /* Opcode 1 _word_ (16 bits). */
113 long lop1
; /* Opcode second word. */
114 long lop2
; /* Opcode third word. */
117 #define MSP430_RLC(n,i,sop,o1) \
118 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
120 static struct rcodes_s msp430_rcodes
[] =
122 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
123 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
124 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
125 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
126 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
127 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
128 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
129 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
134 #define MSP430_RLC(n,i,sop,o1) \
135 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
137 static struct rcodes_s msp430x_rcodes
[] =
139 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
140 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
141 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
142 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
143 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
144 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
145 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
146 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
151 /* More difficult than above and they have format 5.
154 =================================================================
155 gt > jeq +2; jge label jeq +6; jl +4; br label
156 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
157 leu <= jeq label; jlo label jeq +2; jhs +4; br label
158 le <= jeq label; jl label jeq +2; jge +4; br label
159 ================================================================= */
164 int index
; /* Corresponding insn_opnumb. */
165 int tlab
; /* Number of labels in short mode. */
166 int op0
; /* Opcode for first word of short jump. */
167 int op1
; /* Opcode for second word of short jump. */
168 int lop0
; /* Opcodes for long jump mode. */
173 static struct hcodes_s msp430_hcodes
[] =
175 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
176 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
177 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
178 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
182 static struct hcodes_s msp430x_hcodes
[] =
184 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
185 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
186 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
187 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
191 const char comment_chars
[] = ";";
192 const char line_comment_chars
[] = "#";
193 const char line_separator_chars
[] = "{";
194 const char EXP_CHARS
[] = "eE";
195 const char FLT_CHARS
[] = "dD";
197 /* Handle long expressions. */
198 extern LITTLENUM_TYPE generic_bignum
[];
200 static struct hash_control
*msp430_hash
;
203 #define STATE_UNCOND_BRANCH 1 /* jump */
204 #define STATE_NOOV_BRANCH 3 /* bltn */
205 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
206 #define STATE_EMUL_BRANCH 4
215 #define STATE_BITS10 1 /* wild guess. short jump */
216 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
217 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
219 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
220 #define RELAX_STATE(s) ((s) & 3)
221 #define RELAX_LEN(s) ((s) >> 2)
222 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
224 relax_typeS md_relax_table
[] =
232 /* Unconditional jump. */
234 {1024, -1024, CNRL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
235 {0, 0, CUBL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_WORD
)}, /* state word */
236 {1, 1, CUBL
, 0}, /* state undef */
238 /* Simple branches. */
240 {1024, -1024, CNRL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
241 {0, 0, CSBL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_WORD
)}, /* state word */
244 /* blt no overflow branch. */
246 {1024, -1024, CNRL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
247 {0, 0, CNOL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_WORD
)}, /* state word */
250 /* Emulated branches. */
252 {1020, -1020, CEBL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
253 {0, 0, CNOL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_WORD
)}, /* state word */
258 #define MAX_OP_LEN 256
267 static enum msp_isa selected_isa
= MSP_ISA_430Xv2
;
269 static inline bfd_boolean
270 target_is_430x (void)
272 return selected_isa
>= MSP_ISA_430X
;
275 static inline bfd_boolean
276 target_is_430xv2 (void)
278 return selected_isa
== MSP_ISA_430Xv2
;
281 /* Generate a 16-bit relocation.
282 For the 430X we generate a relocation without linkwer range checking
283 if the value is being used in an extended (ie 20-bit) instruction.
284 For the 430 we generate a relocation without assembler range checking
285 if we are handling an immediate value or a byte-width instruction. */
286 #undef CHECK_RELOC_MSP430
287 #define CHECK_RELOC_MSP430 \
289 ? (extended_op ? BFD_RELOC_16 : BFD_RELOC_MSP430X_ABS16) \
290 : ((imm_op || byte_op) \
291 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
293 /* Generate a 16-bit pc-relative relocation.
294 For the 430X we generate a relocation without linkwer range checking.
295 For the 430 we generate a relocation without assembler range checking
296 if we are handling an immediate value or a byte-width instruction. */
297 #undef CHECK_RELOC_MSP430_PCREL
298 #define CHECK_RELOC_MSP430_PCREL \
300 ? BFD_RELOC_MSP430X_PCR16 \
301 : (imm_op || byte_op) \
302 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
304 /* Profiling capability:
305 It is a performance hit to use gcc's profiling approach for this tiny target.
306 Even more -- jtag hardware facility does not perform any profiling functions.
307 However we've got gdb's built-in simulator where we can do anything.
308 Therefore my suggestion is:
310 We define new section ".profiler" which holds all profiling information.
311 We define new pseudo operation .profiler which will instruct assembler to
312 add new profile entry to the object file. Profile should take place at the
317 .profiler flags,function_to_profile [, cycle_corrector, extra]
319 where 'flags' is a combination of the following chars:
322 i - function is in Init section
323 f - function is in Fini section
325 c - libC standard call
326 d - stack value Demand (saved at run-time in simulator)
327 I - Interrupt service routine
332 j - long Jump/ sjlj unwind
333 a - an Arbitrary code fragment
334 t - exTra parameter saved (constant value like frame size)
335 '""' optional: "sil" == sil
337 function_to_profile - function's address
338 cycle_corrector - a value which should be added to the cycle
339 counter, zero if omitted
340 extra - some extra parameter, zero if omitted.
343 ------------------------------
347 .LFrameOffset_fxx=0x08
348 .profiler "scdP", fxx ; function entry.
349 ; we also demand stack value to be displayed
354 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
355 ; (this is a prologue end)
356 ; note, that spare var filled with the frame size
359 .profiler cdE,fxx ; check stack
364 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
365 ret ; cause 'ret' insn takes 3 cycles
366 -------------------------------
368 This profiling approach does not produce any overhead and
370 So, even profiled code can be uploaded to the MCU. */
371 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
372 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
373 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
374 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
375 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
376 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
377 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
378 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
379 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
380 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
381 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
382 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
383 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
384 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
385 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
386 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
399 for (; x
; x
= x
>> 1)
406 /* Parse ordinary expression. */
409 parse_exp (char * s
, expressionS
* op
)
411 input_line_pointer
= s
;
413 if (op
->X_op
== O_absent
)
414 as_bad (_("missing operand"));
415 return input_line_pointer
;
419 /* Delete spaces from s: X ( r 1 2) => X(r12). */
422 del_spaces (char * s
)
430 while (ISSPACE (*m
) && *m
)
432 memmove (s
, m
, strlen (m
) + 1);
440 skip_space (char * s
)
447 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
450 extract_operand (char * from
, char * to
, int limit
)
454 /* Drop leading whitespace. */
455 from
= skip_space (from
);
457 while (size
< limit
&& *from
)
459 *(to
+ size
) = *from
;
460 if (*from
== ',' || *from
== ';' || *from
== '\n')
475 msp430_profiler (int dummy ATTRIBUTE_UNUSED
)
492 s
= input_line_pointer
;
493 end
= input_line_pointer
;
495 while (*end
&& *end
!= '\n')
498 while (*s
&& *s
!= '\n')
509 as_bad (_(".profiler pseudo requires at least two operands."));
510 input_line_pointer
= end
;
514 input_line_pointer
= extract_operand (input_line_pointer
, flags
, 32);
523 p_flags
|= MSP430_PROFILER_FLAG_FRAGMENT
;
526 p_flags
|= MSP430_PROFILER_FLAG_JUMP
;
529 p_flags
|= MSP430_PROFILER_FLAG_PROLSTART
;
532 p_flags
|= MSP430_PROFILER_FLAG_PROLEND
;
535 p_flags
|= MSP430_PROFILER_FLAG_EPISTART
;
538 p_flags
|= MSP430_PROFILER_FLAG_EPIEND
;
541 p_flags
|= MSP430_PROFILER_FLAG_ENTRY
;
544 p_flags
|= MSP430_PROFILER_FLAG_EXIT
;
547 p_flags
|= MSP430_PROFILER_FLAG_INITSECT
;
550 p_flags
|= MSP430_PROFILER_FLAG_FINISECT
;
553 p_flags
|= MSP430_PROFILER_FLAG_LIBCALL
;
556 p_flags
|= MSP430_PROFILER_FLAG_STDCALL
;
559 p_flags
|= MSP430_PROFILER_FLAG_STACKDMD
;
562 p_flags
|= MSP430_PROFILER_FLAG_ISR
;
565 p_flags
|= MSP430_PROFILER_FLAG_EXTRA
;
568 as_warn (_("unknown profiling flag - ignored."));
575 && ( ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_ENTRY
576 | MSP430_PROFILER_FLAG_EXIT
))
577 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_PROLSTART
578 | MSP430_PROFILER_FLAG_PROLEND
579 | MSP430_PROFILER_FLAG_EPISTART
580 | MSP430_PROFILER_FLAG_EPIEND
))
581 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_INITSECT
582 | MSP430_PROFILER_FLAG_FINISECT
))))
584 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
585 input_line_pointer
= end
;
589 /* Generate temp symbol which denotes current location. */
590 if (now_seg
== absolute_section
) /* Paranoia ? */
592 exp1
.X_op
= O_constant
;
593 exp1
.X_add_number
= abs_section_offset
;
594 as_warn (_("profiling in absolute section?"));
598 exp1
.X_op
= O_symbol
;
599 exp1
.X_add_symbol
= symbol_temp_new_now ();
600 exp1
.X_add_number
= 0;
603 /* Generate a symbol which holds flags value. */
604 exp
.X_op
= O_constant
;
605 exp
.X_add_number
= p_flags
;
607 /* Save current section. */
611 /* Now go to .profiler section. */
612 obj_elf_change_section (".profiler", SHT_PROGBITS
, 0, 0, 0, 0, 0);
615 emit_expr (& exp
, 2);
617 /* Save label value. */
618 emit_expr (& exp1
, 2);
622 /* Now get profiling info. */
623 halt
= extract_operand (input_line_pointer
, str
, 1024);
624 /* Process like ".word xxx" directive. */
625 parse_exp (str
, & exp
);
626 emit_expr (& exp
, 2);
627 input_line_pointer
= halt
;
630 /* Fill the rest with zeros. */
631 exp
.X_op
= O_constant
;
632 exp
.X_add_number
= 0;
634 emit_expr (& exp
, 2);
636 /* Return to current section. */
637 subseg_set (seg
, subseg
);
641 extract_word (char * from
, char * to
, int limit
)
646 /* Drop leading whitespace. */
647 from
= skip_space (from
);
650 /* Find the op code end. */
651 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
653 to
[size
++] = *op_end
++;
654 if (size
+ 1 >= limit
)
662 #define OPTION_MMCU 'm'
663 #define OPTION_RELAX 'Q'
664 #define OPTION_POLYMORPHS 'P'
665 #define OPTION_LARGE 'l'
666 static bfd_boolean large_model
= FALSE
;
667 #define OPTION_NO_INTR_NOPS 'N'
668 #define OPTION_INTR_NOPS 'n'
669 static bfd_boolean gen_interrupt_nops
= FALSE
;
670 #define OPTION_WARN_INTR_NOPS 'z'
671 #define OPTION_NO_WARN_INTR_NOPS 'Z'
672 static bfd_boolean warn_interrupt_nops
= TRUE
;
673 #define OPTION_MCPU 'c'
674 #define OPTION_MOVE_DATA 'd'
675 static bfd_boolean move_data
= FALSE
;
678 msp430_set_arch (int option
)
680 char *str
= (char *) alloca (32); /* 32 for good measure. */
682 input_line_pointer
= extract_word (input_line_pointer
, str
, 32);
684 md_parse_option (option
, str
);
685 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
686 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
689 /* This is the full list of MCU names that are known to only
690 support the 430 ISA. */
691 static const char * msp430_mcu_names
[] =
693 "msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231",
694 "msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252",
695 "msp430afe253", "msp430c091", "msp430c092", "msp430c111",
696 "msp430c1111", "msp430c112", "msp430c1121", "msp430c1331",
697 "msp430c1351", "msp430c311s", "msp430c312", "msp430c313",
698 "msp430c314", "msp430c315", "msp430c323", "msp430c325",
699 "msp430c336", "msp430c337", "msp430c412", "msp430c413",
700 "msp430e112", "msp430e313", "msp430e315", "msp430e325",
701 "msp430e337", "msp430f110", "msp430f1101", "msp430f1101a",
702 "msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121",
703 "msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122",
704 "msp430f1222", "msp430f123", "msp430f1232", "msp430f133",
705 "msp430f135", "msp430f147", "msp430f1471", "msp430f148",
706 "msp430f1481", "msp430f149", "msp430f1491", "msp430f155",
707 "msp430f156", "msp430f157", "msp430f1610", "msp430f1611",
708 "msp430f1612", "msp430f167", "msp430f168", "msp430f169",
709 "msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011",
710 "msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111",
711 "msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131",
712 "msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252",
713 "msp430f2254", "msp430f2272", "msp430f2274", "msp430f233",
714 "msp430f2330", "msp430f235", "msp430f2350", "msp430f2370",
715 "msp430f2410", "msp430f247", "msp430f2471", "msp430f248",
716 "msp430f2481", "msp430f249", "msp430f2491", "msp430f412",
717 "msp430f413", "msp430f4132", "msp430f415", "msp430f4152",
718 "msp430f417", "msp430f423", "msp430f423a", "msp430f425",
719 "msp430f4250", "msp430f425a", "msp430f4260", "msp430f427",
720 "msp430f4270", "msp430f427a", "msp430f435", "msp430f4351",
721 "msp430f436", "msp430f4361", "msp430f437", "msp430f4371",
722 "msp430f438", "msp430f439", "msp430f447", "msp430f448",
723 "msp430f4481", "msp430f449", "msp430f4491", "msp430f477",
724 "msp430f478", "msp430f4783", "msp430f4784", "msp430f479",
725 "msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232",
726 "msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252",
727 "msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a",
728 "msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437",
729 "msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478",
730 "msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427",
731 "msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101",
732 "msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113",
733 "msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152",
734 "msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203",
735 "msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213",
736 "msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232",
737 "msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302",
738 "msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332",
739 "msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402",
740 "msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432",
741 "msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453",
742 "msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553",
743 "msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955",
744 "msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031",
745 "msp430i2040", "msp430i2041", "msp430l092", "msp430p112",
746 "msp430p313", "msp430p315", "msp430p315s", "msp430p325",
747 "msp430p337", "msp430tch5e"
751 md_parse_option (int c
, char * arg
)
757 as_fatal (_("MCU option requires a name\n"));
759 if (strcasecmp ("msp430", arg
) == 0)
760 selected_isa
= MSP_ISA_430
;
761 else if (strcasecmp ("msp430xv2", arg
) == 0)
762 selected_isa
= MSP_ISA_430Xv2
;
763 else if (strcasecmp ("msp430x", arg
) == 0)
764 selected_isa
= MSP_ISA_430X
;
769 for (i
= sizeof msp430_mcu_names
/ sizeof msp430_mcu_names
[0]; i
--;)
770 if (strcasecmp (msp430_mcu_names
[i
], arg
) == 0)
772 selected_isa
= MSP_ISA_430
;
776 /* It is not an error if we do not match the MCU name. */
780 if (strcmp (arg
, "430") == 0
781 || strcasecmp (arg
, "msp430") == 0)
782 selected_isa
= MSP_ISA_430
;
783 else if (strcasecmp (arg
, "430x") == 0
784 || strcasecmp (arg
, "msp430x") == 0)
785 selected_isa
= MSP_ISA_430X
;
786 else if (strcasecmp (arg
, "430xv2") == 0
787 || strcasecmp (arg
, "msp430xv2") == 0)
788 selected_isa
= MSP_ISA_430Xv2
;
790 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg
);
794 msp430_enable_relax
= 1;
797 case OPTION_POLYMORPHS
:
798 msp430_enable_polys
= 1;
805 case OPTION_NO_INTR_NOPS
:
806 gen_interrupt_nops
= FALSE
;
808 case OPTION_INTR_NOPS
:
809 gen_interrupt_nops
= TRUE
;
812 case OPTION_WARN_INTR_NOPS
:
813 warn_interrupt_nops
= TRUE
;
815 case OPTION_NO_WARN_INTR_NOPS
:
816 warn_interrupt_nops
= FALSE
;
819 case OPTION_MOVE_DATA
:
827 /* The intention here is to have the mere presence of these sections
828 cause the object to have a reference to a well-known symbol. This
829 reference pulls in the bits of the runtime (crt0) that initialize
830 these sections. Thus, for example, the startup code to call
831 memset() to initialize .bss will only be linked in when there is a
832 non-empty .bss section. Otherwise, the call would exist but have a
833 zero length parameter, which is a waste of memory and cycles.
835 The code which initializes these sections should have a global
836 label for these symbols, and should be marked with KEEP() in the
840 msp430_section (int arg
)
842 char * saved_ilp
= input_line_pointer
;
843 char * name
= obj_elf_section_name ();
845 if (strncmp (name
, ".bss", 4) == 0
846 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
847 (void) symbol_find_or_make ("__crt0_init_bss");
849 if (strncmp (name
, ".data", 5) == 0
850 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
851 (void) symbol_find_or_make ("__crt0_movedata");
853 input_line_pointer
= saved_ilp
;
854 obj_elf_section (arg
);
858 msp430_frob_section (asection
*sec
)
860 const char *name
= sec
->name
;
865 if (strncmp (name
, ".bss", 4) == 0
866 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
867 (void) symbol_find_or_make ("__crt0_init_bss");
869 if (strncmp (name
, ".data", 5) == 0
870 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
871 (void) symbol_find_or_make ("__crt0_movedata");
875 msp430_lcomm (int ignore ATTRIBUTE_UNUSED
)
877 symbolS
*symbolP
= s_comm_internal (0, s_lcomm_internal
);
880 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
881 (void) symbol_find_or_make ("__crt0_init_bss");
885 msp430_comm (int needs_align
)
887 s_comm_internal (needs_align
, elf_common_parse
);
888 (void) symbol_find_or_make ("__crt0_init_bss");
892 msp430_refsym (int arg ATTRIBUTE_UNUSED
)
895 input_line_pointer
= extract_word (input_line_pointer
, sym_name
, 1024);
897 (void) symbol_find_or_make (sym_name
);
900 const pseudo_typeS md_pseudo_table
[] =
902 {"arch", msp430_set_arch
, OPTION_MMCU
},
903 {"cpu", msp430_set_arch
, OPTION_MCPU
},
904 {"profiler", msp430_profiler
, 0},
905 {"section", msp430_section
, 0},
906 {"section.s", msp430_section
, 0},
907 {"sect", msp430_section
, 0},
908 {"sect.s", msp430_section
, 0},
909 {"pushsection", msp430_section
, 1},
910 {"refsym", msp430_refsym
, 0},
911 {"comm", msp430_comm
, 0},
912 {"lcomm", msp430_lcomm
, 0},
916 const char *md_shortopts
= "mm:,mP,mQ,ml,mN,mn,mz,mZ";
918 struct option md_longopts
[] =
920 {"mmcu", required_argument
, NULL
, OPTION_MMCU
},
921 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
922 {"mP", no_argument
, NULL
, OPTION_POLYMORPHS
},
923 {"mQ", no_argument
, NULL
, OPTION_RELAX
},
924 {"ml", no_argument
, NULL
, OPTION_LARGE
},
925 {"mN", no_argument
, NULL
, OPTION_NO_INTR_NOPS
},
926 {"mn", no_argument
, NULL
, OPTION_INTR_NOPS
},
927 {"mZ", no_argument
, NULL
, OPTION_NO_WARN_INTR_NOPS
},
928 {"mz", no_argument
, NULL
, OPTION_WARN_INTR_NOPS
},
929 {"md", no_argument
, NULL
, OPTION_MOVE_DATA
},
930 {NULL
, no_argument
, NULL
, 0}
933 size_t md_longopts_size
= sizeof (md_longopts
);
936 md_show_usage (FILE * stream
)
939 _("MSP430 options:\n"
940 " -mmcu=<msp430-name> - select microcontroller type\n"
941 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
943 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
944 " -mP - enable polymorph instructions\n"));
946 _(" -ml - enable large code model\n"));
948 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
950 _(" -mn - insert a NOP after changing interrupts\n"));
952 _(" -mZ - do not warn about missing NOPs after changing interrupts\n"));
954 _(" -mz - warn about missing NOPs after changing interrupts (default)\n"));
956 _(" -md - Force copying of data from ROM to RAM at startup\n"));
960 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
966 extract_cmd (char * from
, char * to
, int limit
)
970 while (*from
&& ! ISSPACE (*from
) && *from
!= '.' && limit
> size
)
972 *(to
+ size
) = *from
;
983 md_atof (int type
, char * litP
, int * sizeP
)
985 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
991 struct msp430_opcode_s
* opcode
;
992 msp430_hash
= hash_new ();
994 for (opcode
= msp430_opcodes
; opcode
->name
; opcode
++)
995 hash_insert (msp430_hash
, opcode
->name
, (char *) opcode
);
997 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
998 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
1001 /* Returns the register number equivalent to the string T.
1002 Returns -1 if there is no such register.
1003 Skips a leading 'r' or 'R' character if there is one.
1004 Handles the register aliases PC and SP. */
1007 check_reg (char * t
)
1014 if (*t
== 'r' || *t
== 'R')
1017 if (strncasecmp (t
, "pc", 2) == 0)
1020 if (strncasecmp (t
, "sp", 2) == 0)
1023 if (strncasecmp (t
, "sr", 2) == 0)
1031 if (val
< 1 || val
> 15)
1038 msp430_srcoperand (struct msp430_operand_s
* op
,
1042 bfd_boolean allow_20bit_values
,
1043 bfd_boolean constants_allowed
)
1047 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1054 /* Check if there is:
1055 llo(x) - least significant 16 bits, x &= 0xffff
1056 lhi(x) - x = (x >> 16) & 0xffff,
1057 hlo(x) - x = (x >> 32) & 0xffff,
1058 hhi(x) - x = (x >> 48) & 0xffff
1059 The value _MUST_ be constant expression: #hlo(1231231231). */
1063 if (strncasecmp (h
, "#llo(", 5) == 0)
1068 else if (strncasecmp (h
, "#lhi(", 5) == 0)
1073 else if (strncasecmp (h
, "#hlo(", 5) == 0)
1078 else if (strncasecmp (h
, "#hhi(", 5) == 0)
1083 else if (strncasecmp (h
, "#lo(", 4) == 0)
1088 else if (strncasecmp (h
, "#hi(", 4) == 0)
1094 op
->reg
= 0; /* Reg PC. */
1096 op
->ol
= 1; /* Immediate will follow an instruction. */
1097 __tl
= h
+ 1 + rval
;
1100 parse_exp (__tl
, &(op
->exp
));
1101 if (op
->exp
.X_op
== O_constant
)
1103 int x
= op
->exp
.X_add_number
;
1108 op
->exp
.X_add_number
= x
;
1110 else if (vshift
== 1)
1112 x
= (x
>> 16) & 0xffff;
1113 op
->exp
.X_add_number
= x
;
1115 else if (vshift
> 1)
1118 op
->exp
.X_add_number
= -1;
1120 op
->exp
.X_add_number
= 0; /* Nothing left. */
1121 x
= op
->exp
.X_add_number
;
1124 if (allow_20bit_values
)
1126 if (op
->exp
.X_add_number
> 0xfffff || op
->exp
.X_add_number
< - (0x7ffff))
1128 as_bad (_("value 0x%x out of extended range."), x
);
1132 else if (op
->exp
.X_add_number
> 65535 || op
->exp
.X_add_number
< -32768)
1134 as_bad (_("value %d out of range. Use #lo() or #hi()"), x
);
1138 /* Now check constants. */
1139 /* Substitute register mode with a constant generator if applicable. */
1141 if (!allow_20bit_values
)
1142 x
= (short) x
; /* Extend sign. */
1144 if (! constants_allowed
)
1176 #ifdef PUSH_1X_WORKAROUND
1179 /* Remove warning as confusing.
1180 as_warn (_("Hardware push bug workaround")); */
1193 #ifdef PUSH_1X_WORKAROUND
1196 /* Remove warning as confusing.
1197 as_warn (_("Hardware push bug workaround")); */
1209 else if (op
->exp
.X_op
== O_symbol
)
1213 else if (op
->exp
.X_op
== O_big
)
1219 op
->exp
.X_op
= O_constant
;
1220 op
->exp
.X_add_number
= 0xffff & generic_bignum
[vshift
];
1221 x
= op
->exp
.X_add_number
;
1226 ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
1274 /* Redundant (yet) check. */
1275 else if (op
->exp
.X_op
== O_register
)
1277 (_("Registers cannot be used within immediate expression [%s]"), l
);
1279 as_bad (_("unknown operand %s"), l
);
1284 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1289 op
->reg
= 2; /* reg 2 in absolute addr mode. */
1290 op
->am
= 1; /* mode As == 01 bin. */
1291 op
->ol
= 1; /* Immediate value followed by instruction. */
1293 parse_exp (__tl
, &(op
->exp
));
1295 if (op
->exp
.X_op
== O_constant
)
1297 int x
= op
->exp
.X_add_number
;
1299 if (allow_20bit_values
)
1301 if (x
> 0xfffff || x
< -(0x7ffff))
1303 as_bad (_("value 0x%x out of extended range."), x
);
1307 else if (x
> 65535 || x
< -32768)
1309 as_bad (_("value out of range: 0x%x"), x
);
1313 else if (op
->exp
.X_op
== O_symbol
)
1317 /* Redundant (yet) check. */
1318 if (op
->exp
.X_op
== O_register
)
1320 (_("Registers cannot be used within absolute expression [%s]"), l
);
1322 as_bad (_("unknown expression in operand %s"), l
);
1328 /* Check if indirect register mode @Rn / postincrement @Rn+. */
1332 char *m
= strchr (l
, '+');
1336 as_bad (_("unknown addressing mode %s"), l
);
1342 if ((op
->reg
= check_reg (t
)) == -1)
1344 as_bad (_("Bad register name %s"), t
);
1352 /* PC cannot be used in indirect addressing. */
1353 if (target_is_430xv2 () && op
->reg
== 0)
1355 as_bad (_("cannot use indirect addressing with the PC"));
1362 /* Check if register indexed X(Rn). */
1365 char *h
= strrchr (l
, '(');
1366 char *m
= strrchr (l
, ')');
1375 as_bad (_("')' required"));
1383 /* Extract a register. */
1384 if ((op
->reg
= check_reg (t
+ 1)) == -1)
1387 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
1394 as_bad (_("r2 should not be used in indexed addressing mode"));
1398 /* Extract constant. */
1402 parse_exp (__tl
, &(op
->exp
));
1403 if (op
->exp
.X_op
== O_constant
)
1405 int x
= op
->exp
.X_add_number
;
1407 if (allow_20bit_values
)
1409 if (x
> 0xfffff || x
< - (0x7ffff))
1411 as_bad (_("value 0x%x out of extended range."), x
);
1415 else if (x
> 65535 || x
< -32768)
1417 as_bad (_("value out of range: 0x%x"), x
);
1429 else if (op
->exp
.X_op
== O_symbol
)
1433 /* Redundant (yet) check. */
1434 if (op
->exp
.X_op
== O_register
)
1436 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l
);
1438 as_bad (_("unknown expression in operand %s"), l
);
1446 /* Possibly register mode 'mov r1,r2'. */
1447 if ((op
->reg
= check_reg (l
)) != -1)
1455 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
1459 op
->reg
= 0; /* PC relative... be careful. */
1460 /* An expression starting with a minus sign is a constant, not an address. */
1461 op
->am
= (*l
== '-' ? 3 : 1);
1464 parse_exp (__tl
, &(op
->exp
));
1470 as_bad (_("unknown addressing mode for operand %s"), l
);
1476 msp430_dstoperand (struct msp430_operand_s
* op
,
1479 bfd_boolean allow_20bit_values
,
1480 bfd_boolean constants_allowed
)
1483 int ret
= msp430_srcoperand (op
, l
, bin
, & dummy
,
1497 parse_exp (__tl
, &(op
->exp
));
1499 if (op
->exp
.X_op
!= O_constant
|| op
->exp
.X_add_number
!= 0)
1501 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
1511 ("this addressing mode is not applicable for destination operand"));
1517 /* Attempt to encode a MOVA instruction with the given operands.
1518 Returns the length of the encoded instruction if successful
1519 or 0 upon failure. If the encoding fails, an error message
1520 will be returned if a pointer is provided. */
1523 try_encode_mova (bfd_boolean imm_op
,
1525 struct msp430_operand_s
* op1
,
1526 struct msp430_operand_s
* op2
,
1527 const char ** error_message_return
)
1533 /* Only a restricted subset of the normal MSP430 addressing modes
1534 are supported here, so check for the ones that are allowed. */
1537 if (op1
->mode
== OP_EXP
)
1539 if (op2
->mode
!= OP_REG
)
1541 if (error_message_return
!= NULL
)
1542 * error_message_return
= _("expected register as second argument of %s");
1548 /* MOVA #imm20, Rdst. */
1549 bin
|= 0x80 | op2
->reg
;
1550 frag
= frag_more (4);
1551 where
= frag
- frag_now
->fr_literal
;
1552 if (op1
->exp
.X_op
== O_constant
)
1554 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1555 bfd_putl16 ((bfd_vma
) bin
, frag
);
1556 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1560 bfd_putl16 ((bfd_vma
) bin
, frag
);
1561 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1562 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1563 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1568 else if (op1
->am
== 1)
1570 /* MOVA z16(Rsrc), Rdst. */
1571 bin
|= 0x30 | (op1
->reg
<< 8) | op2
->reg
;
1572 frag
= frag_more (4);
1573 where
= frag
- frag_now
->fr_literal
;
1574 bfd_putl16 ((bfd_vma
) bin
, frag
);
1575 if (op1
->exp
.X_op
== O_constant
)
1577 if (op1
->exp
.X_add_number
> 0xffff
1578 || op1
->exp
.X_add_number
< -(0x7fff))
1580 if (error_message_return
!= NULL
)
1581 * error_message_return
= _("index value too big for %s");
1584 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1588 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1589 fix_new_exp (frag_now
, where
+ 2, 2, &(op1
->exp
), FALSE
,
1591 BFD_RELOC_MSP430X_PCR16
:
1592 BFD_RELOC_MSP430X_ABS16
);
1597 if (error_message_return
!= NULL
)
1598 * error_message_return
= _("unexpected addressing mode for %s");
1601 else if (op1
->am
== 0)
1603 /* MOVA Rsrc, ... */
1604 if (op2
->mode
== OP_REG
)
1606 bin
|= 0xc0 | (op1
->reg
<< 8) | op2
->reg
;
1607 frag
= frag_more (2);
1608 where
= frag
- frag_now
->fr_literal
;
1609 bfd_putl16 ((bfd_vma
) bin
, frag
);
1612 else if (op2
->am
== 1)
1616 /* MOVA Rsrc, &abs20. */
1617 bin
|= 0x60 | (op1
->reg
<< 8);
1618 frag
= frag_more (4);
1619 where
= frag
- frag_now
->fr_literal
;
1620 if (op2
->exp
.X_op
== O_constant
)
1622 bin
|= (op2
->exp
.X_add_number
>> 16) & 0xf;
1623 bfd_putl16 ((bfd_vma
) bin
, frag
);
1624 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1628 bfd_putl16 ((bfd_vma
) bin
, frag
);
1629 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1630 fix_new_exp (frag_now
, where
, 4, &(op2
->exp
), FALSE
,
1631 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
1636 /* MOVA Rsrc, z16(Rdst). */
1637 bin
|= 0x70 | (op1
->reg
<< 8) | op2
->reg
;
1638 frag
= frag_more (4);
1639 where
= frag
- frag_now
->fr_literal
;
1640 bfd_putl16 ((bfd_vma
) bin
, frag
);
1641 if (op2
->exp
.X_op
== O_constant
)
1643 if (op2
->exp
.X_add_number
> 0xffff
1644 || op2
->exp
.X_add_number
< -(0x7fff))
1646 if (error_message_return
!= NULL
)
1647 * error_message_return
= _("index value too big for %s");
1650 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1654 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1655 fix_new_exp (frag_now
, where
+ 2, 2, &(op2
->exp
), FALSE
,
1657 BFD_RELOC_MSP430X_PCR16
:
1658 BFD_RELOC_MSP430X_ABS16
);
1663 if (error_message_return
!= NULL
)
1664 * error_message_return
= _("unexpected addressing mode for %s");
1669 /* imm_op == FALSE. */
1671 if (op1
->reg
== 2 && op1
->am
== 1 && op1
->mode
== OP_EXP
)
1673 /* MOVA &abs20, Rdst. */
1674 if (op2
->mode
!= OP_REG
)
1676 if (error_message_return
!= NULL
)
1677 * error_message_return
= _("expected register as second argument of %s");
1681 if (op2
->reg
== 2 || op2
->reg
== 3)
1683 if (error_message_return
!= NULL
)
1684 * error_message_return
= _("constant generator destination register found in %s");
1688 bin
|= 0x20 | op2
->reg
;
1689 frag
= frag_more (4);
1690 where
= frag
- frag_now
->fr_literal
;
1691 if (op1
->exp
.X_op
== O_constant
)
1693 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1694 bfd_putl16 ((bfd_vma
) bin
, frag
);
1695 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1699 bfd_putl16 ((bfd_vma
) bin
, frag
);
1700 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1701 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1702 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1706 else if (op1
->mode
== OP_REG
)
1710 /* MOVA @Rsrc+, Rdst. */
1711 if (op2
->mode
!= OP_REG
)
1713 if (error_message_return
!= NULL
)
1714 * error_message_return
= _("expected register as second argument of %s");
1718 if (op2
->reg
== 2 || op2
->reg
== 3)
1720 if (error_message_return
!= NULL
)
1721 * error_message_return
= _("constant generator destination register found in %s");
1725 if (op1
->reg
== 2 || op1
->reg
== 3)
1727 if (error_message_return
!= NULL
)
1728 * error_message_return
= _("constant generator source register found in %s");
1732 bin
|= 0x10 | (op1
->reg
<< 8) | op2
->reg
;
1733 frag
= frag_more (2);
1734 where
= frag
- frag_now
->fr_literal
;
1735 bfd_putl16 ((bfd_vma
) bin
, frag
);
1738 else if (op1
->am
== 2)
1740 /* MOVA @Rsrc,Rdst */
1741 if (op2
->mode
!= OP_REG
)
1743 if (error_message_return
!= NULL
)
1744 * error_message_return
= _("expected register as second argument of %s");
1748 if (op2
->reg
== 2 || op2
->reg
== 3)
1750 if (error_message_return
!= NULL
)
1751 * error_message_return
= _("constant generator destination register found in %s");
1755 if (op1
->reg
== 2 || op1
->reg
== 3)
1757 if (error_message_return
!= NULL
)
1758 * error_message_return
= _("constant generator source register found in %s");
1762 bin
|= (op1
->reg
<< 8) | op2
->reg
;
1763 frag
= frag_more (2);
1764 where
= frag
- frag_now
->fr_literal
;
1765 bfd_putl16 ((bfd_vma
) bin
, frag
);
1770 if (error_message_return
!= NULL
)
1771 * error_message_return
= _("unexpected addressing mode for %s");
1776 static bfd_boolean check_for_nop
= FALSE
;
1778 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
1780 /* Parse instruction operands.
1781 Return binary opcode. */
1784 msp430_operands (struct msp430_opcode_s
* opcode
, char * line
)
1786 int bin
= opcode
->bin_opcode
; /* Opcode mask. */
1787 int insn_length
= 0;
1788 char l1
[MAX_OP_LEN
], l2
[MAX_OP_LEN
];
1791 struct msp430_operand_s op1
, op2
;
1793 static short ZEROS
= 0;
1794 int byte_op
, imm_op
;
1797 int extended
= 0x1800;
1798 bfd_boolean extended_op
= FALSE
;
1799 bfd_boolean addr_op
;
1800 const char * error_message
;
1801 static signed int repeat_count
= 0;
1802 bfd_boolean fix_emitted
;
1803 bfd_boolean nop_check_needed
= FALSE
;
1805 /* Opcode is the one from opcodes table
1806 line contains something like
1815 bfd_boolean check
= FALSE
;
1818 switch (TOLOWER (* line
))
1821 /* Byte operation. */
1822 bin
|= BYTE_OPERATION
;
1828 /* "Address" ops work on 20-bit values. */
1830 bin
|= BYTE_OPERATION
;
1835 /* Word operation - this is the default. */
1843 as_warn (_("no size modifier after period, .w assumed"));
1847 as_bad (_("unrecognised instruction size modifier .%c"),
1859 if (*line
&& ! ISSPACE (*line
))
1861 as_bad (_("junk found after instruction: %s.%s"),
1862 opcode
->name
, line
);
1866 /* Catch the case where the programmer has used a ".a" size modifier on an
1867 instruction that does not support it. Look for an alternative extended
1868 instruction that has the same name without the period. Eg: "add.a"
1869 becomes "adda". Although this not an officially supported way of
1870 specifing instruction aliases other MSP430 assemblers allow it. So we
1871 support it for compatibility purposes. */
1872 if (addr_op
&& opcode
->fmt
>= 0)
1874 char * old_name
= opcode
->name
;
1877 sprintf (real_name
, "%sa", old_name
);
1878 opcode
= hash_find (msp430_hash
, real_name
);
1881 as_bad (_("instruction %s.a does not exist"), old_name
);
1884 #if 0 /* Enable for debugging. */
1885 as_warn ("treating %s.a as %s", old_name
, real_name
);
1888 bin
= opcode
->bin_opcode
;
1891 if (opcode
->fmt
!= -1
1892 && opcode
->insn_opnumb
1893 && (!*line
|| *line
== '\n'))
1895 as_bad (_("instruction %s requires %d operand(s)"),
1896 opcode
->name
, opcode
->insn_opnumb
);
1900 memset (l1
, 0, sizeof (l1
));
1901 memset (l2
, 0, sizeof (l2
));
1902 memset (&op1
, 0, sizeof (op1
));
1903 memset (&op2
, 0, sizeof (op2
));
1907 if ((fmt
= opcode
->fmt
) < 0)
1909 if (! target_is_430x ())
1911 as_bad (_("instruction %s requires MSP430X mcu"),
1922 /* If requested set the extended instruction repeat count. */
1925 if (repeat_count
> 0)
1926 extended
|= (repeat_count
- 1);
1928 extended
|= (1 << 7) | (- repeat_count
);
1931 as_bad (_("unable to repeat %s insn"), opcode
->name
);
1936 if (check_for_nop
&& is_opcode ("nop"))
1937 check_for_nop
= FALSE
;
1941 case 0: /* Emulated. */
1942 switch (opcode
->insn_opnumb
)
1945 if (is_opcode ("eint") || is_opcode ("dint"))
1949 if (warn_interrupt_nops
)
1951 if (gen_interrupt_nops
)
1952 as_warn (_("NOP inserted between two instructions that change interrupt state"));
1954 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
1957 if (gen_interrupt_nops
)
1959 /* Emit a NOP between interrupt enable/disable.
1960 See 1.3.4.1 of the MSP430x5xx User Guide. */
1962 frag
= frag_more (2);
1963 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
1967 nop_check_needed
= TRUE
;
1970 /* Set/clear bits instructions. */
1974 extended
|= BYTE_OPERATION
;
1976 /* Emit the extension word. */
1978 frag
= frag_more (2);
1979 bfd_putl16 (extended
, frag
);
1983 frag
= frag_more (2);
1984 bfd_putl16 ((bfd_vma
) bin
, frag
);
1985 dwarf2_emit_insn (insn_length
);
1989 /* Something which works with destination operand. */
1990 line
= extract_operand (line
, l1
, sizeof (l1
));
1991 res
= msp430_dstoperand (&op1
, l1
, opcode
->bin_opcode
, extended_op
, TRUE
);
1995 bin
|= (op1
.reg
| (op1
.am
<< 7));
1997 if (is_opcode ("clr") && bin
== 0x4302 /* CLR R2*/)
2001 if (warn_interrupt_nops
)
2003 if (gen_interrupt_nops
)
2004 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2006 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2009 if (gen_interrupt_nops
)
2011 /* Emit a NOP between interrupt enable/disable.
2012 See 1.3.4.1 of the MSP430x5xx User Guide. */
2014 frag
= frag_more (2);
2015 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2019 nop_check_needed
= TRUE
;
2022 /* Compute the entire instruction length, in bytes. */
2023 op_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2024 insn_length
+= op_length
;
2025 frag
= frag_more (op_length
);
2026 where
= frag
- frag_now
->fr_literal
;
2031 extended
|= BYTE_OPERATION
;
2033 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2035 as_bad (_("repeat instruction used with non-register mode instruction"));
2039 if (op1
.mode
== OP_EXP
)
2041 if (op1
.exp
.X_op
== O_constant
)
2042 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2044 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2045 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2046 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2048 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2049 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2052 /* Emit the extension word. */
2053 bfd_putl16 (extended
, frag
);
2058 bfd_putl16 ((bfd_vma
) bin
, frag
);
2062 if (op1
.mode
== OP_EXP
)
2064 if (op1
.exp
.X_op
== O_constant
)
2066 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2070 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2075 fix_new_exp (frag_now
, where
, 2,
2076 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2078 fix_new_exp (frag_now
, where
, 2,
2079 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2084 dwarf2_emit_insn (insn_length
);
2088 /* Shift instruction. */
2089 line
= extract_operand (line
, l1
, sizeof (l1
));
2090 strncpy (l2
, l1
, sizeof (l2
));
2091 l2
[sizeof (l2
) - 1] = '\0';
2092 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2093 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2096 break; /* An error occurred. All warnings were done before. */
2098 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2) + (op2
.ol
* 2);
2099 frag
= frag_more (insn_length
);
2100 where
= frag
- frag_now
->fr_literal
;
2102 if (target_is_430xv2 ()
2103 && op1
.mode
== OP_REG
2105 && (is_opcode ("rlax")
2106 || is_opcode ("rlcx")
2107 || is_opcode ("rla")
2108 || is_opcode ("rlc")))
2110 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2117 extended
|= BYTE_OPERATION
;
2119 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2121 as_bad (_("repeat instruction used with non-register mode instruction"));
2125 if (op1
.mode
== OP_EXP
)
2127 if (op1
.exp
.X_op
== O_constant
)
2128 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2130 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2131 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2132 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2134 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2135 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2138 if (op2
.mode
== OP_EXP
)
2140 if (op2
.exp
.X_op
== O_constant
)
2141 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2143 else if (op1
.mode
== OP_EXP
)
2144 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2145 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2146 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2148 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2149 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2150 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2153 /* Emit the extension word. */
2154 bfd_putl16 (extended
, frag
);
2159 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2160 bfd_putl16 ((bfd_vma
) bin
, frag
);
2164 if (op1
.mode
== OP_EXP
)
2166 if (op1
.exp
.X_op
== O_constant
)
2168 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2172 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2176 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2177 fix_new_exp (frag_now
, where
, 2,
2178 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2180 fix_new_exp (frag_now
, where
, 2,
2181 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2188 if (op2
.mode
== OP_EXP
)
2190 if (op2
.exp
.X_op
== O_constant
)
2192 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2196 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2200 if (op2
.reg
) /* Not PC relative. */
2201 fix_new_exp (frag_now
, where
, 2,
2202 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2204 fix_new_exp (frag_now
, where
, 2,
2205 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2210 dwarf2_emit_insn (insn_length
);
2214 /* Branch instruction => mov dst, r0. */
2217 as_bad ("Internal error: state 0/3 not coded for extended instructions");
2221 line
= extract_operand (line
, l1
, sizeof (l1
));
2222 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, FALSE
);
2228 bin
|= ((op1
.reg
<< 8) | (op1
.am
<< 4));
2229 op_length
= 2 + 2 * op1
.ol
;
2230 frag
= frag_more (op_length
);
2231 where
= frag
- frag_now
->fr_literal
;
2232 bfd_putl16 ((bfd_vma
) bin
, frag
);
2234 if (op1
.mode
== OP_EXP
)
2236 if (op1
.exp
.X_op
== O_constant
)
2238 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
+ 2);
2244 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2246 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3))
2247 fix_new_exp (frag_now
, where
, 2,
2248 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2250 fix_new_exp (frag_now
, where
, 2,
2251 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2255 dwarf2_emit_insn (insn_length
+ op_length
);
2259 /* CALLA instructions. */
2260 fix_emitted
= FALSE
;
2262 line
= extract_operand (line
, l1
, sizeof (l1
));
2265 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
,
2266 extended_op
, FALSE
);
2272 op_length
= 2 + 2 * op1
.ol
;
2273 frag
= frag_more (op_length
);
2274 where
= frag
- frag_now
->fr_literal
;
2282 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2283 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2286 else if (op1
.am
== 1)
2292 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2293 BFD_RELOC_MSP430X_PCR20_CALL
);
2297 bin
|= 0x50 | op1
.reg
;
2299 else if (op1
.am
== 0)
2300 bin
|= 0x40 | op1
.reg
;
2302 else if (op1
.am
== 1)
2306 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2307 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2310 else if (op1
.am
== 2)
2311 bin
|= 0x60 | op1
.reg
;
2312 else if (op1
.am
== 3)
2313 bin
|= 0x70 | op1
.reg
;
2315 bfd_putl16 ((bfd_vma
) bin
, frag
);
2317 if (op1
.mode
== OP_EXP
)
2321 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1
.ol
);
2325 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2328 fix_new_exp (frag_now
, where
+ 2, 2,
2329 &(op1
.exp
), FALSE
, BFD_RELOC_16
);
2332 dwarf2_emit_insn (insn_length
+ op_length
);
2340 /* [POP|PUSH]M[.A] #N, Rd */
2341 line
= extract_operand (line
, l1
, sizeof (l1
));
2342 line
= extract_operand (line
, l2
, sizeof (l2
));
2346 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2349 parse_exp (l1
+ 1, &(op1
.exp
));
2350 if (op1
.exp
.X_op
!= O_constant
)
2352 as_bad (_("expected constant expression for first argument of %s"),
2357 if ((reg
= check_reg (l2
)) == -1)
2359 as_bad (_("expected register as second argument of %s"),
2365 frag
= frag_more (op_length
);
2366 where
= frag
- frag_now
->fr_literal
;
2367 bin
= opcode
->bin_opcode
;
2370 n
= op1
.exp
.X_add_number
;
2371 bin
|= (n
- 1) << 4;
2372 if (is_opcode ("pushm"))
2376 if (reg
- n
+ 1 < 0)
2378 as_bad (_("Too many registers popped"));
2382 /* CPU21 errata: cannot use POPM to restore the SR register. */
2383 if (target_is_430xv2 ()
2384 && (reg
- n
+ 1 < 3)
2386 && is_opcode ("popm"))
2388 as_bad (_("Cannot use POPM to restore the SR register"));
2392 bin
|= (reg
- n
+ 1);
2395 bfd_putl16 ((bfd_vma
) bin
, frag
);
2396 dwarf2_emit_insn (op_length
);
2405 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
2406 if (extended
& 0xff)
2408 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2412 line
= extract_operand (line
, l1
, sizeof (l1
));
2413 line
= extract_operand (line
, l2
, sizeof (l2
));
2417 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2420 parse_exp (l1
+ 1, &(op1
.exp
));
2421 if (op1
.exp
.X_op
!= O_constant
)
2423 as_bad (_("expected constant expression for first argument of %s"),
2427 n
= op1
.exp
.X_add_number
;
2430 as_bad (_("expected first argument of %s to be in the range 1-4"),
2435 if ((reg
= check_reg (l2
)) == -1)
2437 as_bad (_("expected register as second argument of %s"),
2442 if (target_is_430xv2 () && reg
== 0)
2444 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2449 frag
= frag_more (op_length
);
2450 where
= frag
- frag_now
->fr_literal
;
2452 bin
= opcode
->bin_opcode
;
2455 bin
|= (n
- 1) << 10;
2458 bfd_putl16 ((bfd_vma
) bin
, frag
);
2459 dwarf2_emit_insn (op_length
);
2467 /* RRUX: Synthetic unsigned right shift of a register by one bit. */
2468 if (extended
& 0xff)
2470 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2474 line
= extract_operand (line
, l1
, sizeof (l1
));
2475 if ((reg
= check_reg (l1
)) == -1)
2477 as_bad (_("expected register as argument of %s"),
2482 if (target_is_430xv2 () && reg
== 0)
2484 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2490 /* Tricky - there is no single instruction that will do this.
2491 Encode as: RRA.B rN { BIC.B #0x80, rN */
2493 frag
= frag_more (op_length
);
2494 where
= frag
- frag_now
->fr_literal
;
2496 bfd_putl16 ((bfd_vma
) bin
, frag
);
2497 dwarf2_emit_insn (2);
2499 bfd_putl16 ((bfd_vma
) bin
, frag
+ 2);
2501 bfd_putl16 ((bfd_vma
) bin
, frag
+ 4);
2502 dwarf2_emit_insn (4);
2506 /* Encode as RRUM[.A] rN. */
2507 bin
= opcode
->bin_opcode
;
2512 frag
= frag_more (op_length
);
2513 where
= frag
- frag_now
->fr_literal
;
2514 bfd_putl16 ((bfd_vma
) bin
, frag
);
2515 dwarf2_emit_insn (op_length
);
2522 bfd_boolean need_reloc
= FALSE
;
2526 /* ADDA, CMPA and SUBA address instructions. */
2527 if (extended
& 0xff)
2529 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2533 line
= extract_operand (line
, l1
, sizeof (l1
));
2534 line
= extract_operand (line
, l2
, sizeof (l2
));
2536 bin
= opcode
->bin_opcode
;
2540 parse_exp (l1
+ 1, &(op1
.exp
));
2542 if (op1
.exp
.X_op
== O_constant
)
2544 n
= op1
.exp
.X_add_number
;
2545 if (n
> 0xfffff || n
< - (0x7ffff))
2547 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
2552 bin
|= ((n
>> 16) & 0xf) << 8;
2564 if ((n
= check_reg (l1
)) == -1)
2566 as_bad (_("expected register name or constant as first argument of %s"),
2571 bin
|= (n
<< 8) | (1 << 6);
2575 if ((reg
= check_reg (l2
)) == -1)
2577 as_bad (_("expected register as second argument of %s"),
2582 frag
= frag_more (op_length
);
2583 where
= frag
- frag_now
->fr_literal
;
2586 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2587 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
2589 bfd_putl16 ((bfd_vma
) bin
, frag
);
2591 bfd_putl16 ((bfd_vma
) (n
& 0xffff), frag
+ 2);
2592 dwarf2_emit_insn (op_length
);
2596 case 9: /* MOVA, BRA, RETA. */
2598 bin
= opcode
->bin_opcode
;
2600 if (is_opcode ("reta"))
2602 /* The RETA instruction does not take any arguments.
2603 The implicit first argument is @SP+.
2604 The implicit second argument is PC. */
2614 line
= extract_operand (line
, l1
, sizeof (l1
));
2615 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2616 &imm_op
, extended_op
, FALSE
);
2618 if (is_opcode ("bra"))
2620 /* This is the BRA synthetic instruction.
2621 The second argument is always PC. */
2627 line
= extract_operand (line
, l2
, sizeof (l2
));
2628 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
,
2633 break; /* Error occurred. All warnings were done before. */
2636 /* Only a restricted subset of the normal MSP430 addressing modes
2637 are supported here, so check for the ones that are allowed. */
2638 if ((op_length
= try_encode_mova (imm_op
, bin
, & op1
, & op2
,
2639 & error_message
)) == 0)
2641 as_bad (error_message
, opcode
->name
);
2644 dwarf2_emit_insn (op_length
);
2648 line
= extract_operand (line
, l1
, sizeof l1
);
2649 /* The RPT instruction only accepted immediates and registers. */
2652 parse_exp (l1
+ 1, &(op1
.exp
));
2653 if (op1
.exp
.X_op
!= O_constant
)
2655 as_bad (_("expected constant value as argument to RPT"));
2658 if (op1
.exp
.X_add_number
< 1
2659 || op1
.exp
.X_add_number
> (1 << 4))
2661 as_bad (_("expected constant in the range 2..16"));
2665 /* We silently accept and ignore a repeat count of 1. */
2666 if (op1
.exp
.X_add_number
> 1)
2667 repeat_count
= op1
.exp
.X_add_number
;
2673 if ((reg
= check_reg (l1
)) != -1)
2676 as_warn (_("PC used as an argument to RPT"));
2678 repeat_count
= - reg
;
2682 as_bad (_("expected constant or register name as argument to RPT insn"));
2689 as_bad (_("Illegal emulated instruction "));
2694 case 1: /* Format 1, double operand. */
2695 line
= extract_operand (line
, l1
, sizeof (l1
));
2696 line
= extract_operand (line
, l2
, sizeof (l2
));
2697 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2698 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2701 break; /* Error occurred. All warnings were done before. */
2704 && is_opcode ("movx")
2706 && msp430_enable_relax
)
2708 /* This is the MOVX.A instruction. See if we can convert
2709 it into the MOVA instruction instead. This saves 2 bytes. */
2710 if ((op_length
= try_encode_mova (imm_op
, 0x0000, & op1
, & op2
,
2713 dwarf2_emit_insn (op_length
);
2718 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2720 if ( (is_opcode ("bic") && bin
== 0xc232)
2721 || (is_opcode ("bis") && bin
== 0xd232)
2722 || (is_opcode ("mov") && op2
.mode
== OP_REG
&& op2
.reg
== 2))
2726 if (warn_interrupt_nops
)
2728 if (gen_interrupt_nops
)
2729 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2731 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2734 if (gen_interrupt_nops
)
2736 /* Emit a NOP between interrupt enable/disable.
2737 See 1.3.4.1 of the MSP430x5xx User Guide. */
2739 frag
= frag_more (2);
2740 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2744 nop_check_needed
= TRUE
;
2747 /* Compute the entire length of the instruction in bytes. */
2748 op_length
= (extended_op
? 2 : 0) /* The extension word. */
2749 + 2 /* The opcode */
2750 + (2 * op1
.ol
) /* The first operand. */
2751 + (2 * op2
.ol
); /* The second operand. */
2753 insn_length
+= op_length
;
2754 frag
= frag_more (op_length
);
2755 where
= frag
- frag_now
->fr_literal
;
2760 extended
|= BYTE_OPERATION
;
2762 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2764 as_bad (_("repeat instruction used with non-register mode instruction"));
2768 /* If necessary, emit a reloc to update the extension word. */
2769 if (op1
.mode
== OP_EXP
)
2771 if (op1
.exp
.X_op
== O_constant
)
2772 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2774 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2775 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2776 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2778 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2779 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2782 if (op2
.mode
== OP_EXP
)
2784 if (op2
.exp
.X_op
== O_constant
)
2785 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2787 else if (op1
.mode
== OP_EXP
)
2788 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2789 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2790 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2793 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2794 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2795 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2798 /* Emit the extension word. */
2799 bfd_putl16 (extended
, frag
);
2804 bfd_putl16 ((bfd_vma
) bin
, frag
);
2808 if (op1
.mode
== OP_EXP
)
2810 if (op1
.exp
.X_op
== O_constant
)
2812 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2816 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2820 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2821 fix_new_exp (frag_now
, where
, 2,
2822 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2824 fix_new_exp (frag_now
, where
, 2,
2825 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2833 if (op2
.mode
== OP_EXP
)
2835 if (op2
.exp
.X_op
== O_constant
)
2837 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2841 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2845 if (op2
.reg
) /* Not PC relative. */
2846 fix_new_exp (frag_now
, where
, 2,
2847 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2849 fix_new_exp (frag_now
, where
, 2,
2850 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2855 dwarf2_emit_insn (insn_length
);
2858 case 2: /* Single-operand mostly instr. */
2859 if (opcode
->insn_opnumb
== 0)
2861 /* reti instruction. */
2863 frag
= frag_more (2);
2864 bfd_putl16 ((bfd_vma
) bin
, frag
);
2865 dwarf2_emit_insn (insn_length
);
2869 line
= extract_operand (line
, l1
, sizeof (l1
));
2870 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2871 &imm_op
, extended_op
, TRUE
);
2873 break; /* Error in operand. */
2875 if (target_is_430xv2 ()
2876 && op1
.mode
== OP_REG
2878 && (is_opcode ("rrax")
2879 || is_opcode ("rrcx")
2880 || is_opcode ("rra")
2881 || is_opcode ("rrc")))
2883 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2887 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2888 frag
= frag_more (insn_length
);
2889 where
= frag
- frag_now
->fr_literal
;
2893 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
2895 /* These two instructions use a special
2896 encoding of the A/L and B/W bits. */
2897 bin
&= ~ BYTE_OPERATION
;
2901 as_bad (_("%s instruction does not accept a .b suffix"),
2906 extended
|= BYTE_OPERATION
;
2909 extended
|= BYTE_OPERATION
;
2911 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2913 as_bad (_("repeat instruction used with non-register mode instruction"));
2917 if (op1
.mode
== OP_EXP
)
2919 if (op1
.exp
.X_op
== O_constant
)
2920 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2922 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2923 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2924 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2926 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2927 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2930 /* Emit the extension word. */
2931 bfd_putl16 (extended
, frag
);
2936 bin
|= op1
.reg
| (op1
.am
<< 4);
2937 bfd_putl16 ((bfd_vma
) bin
, frag
);
2941 if (op1
.mode
== OP_EXP
)
2943 if (op1
.exp
.X_op
== O_constant
)
2945 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2949 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2953 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2954 fix_new_exp (frag_now
, where
, 2,
2955 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430
);
2957 fix_new_exp (frag_now
, where
, 2,
2958 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2963 dwarf2_emit_insn (insn_length
);
2966 case 3: /* Conditional jumps instructions. */
2967 line
= extract_operand (line
, l1
, sizeof (l1
));
2968 /* l1 is a label. */
2977 parse_exp (m
, &exp
);
2979 /* In order to handle something like:
2983 jz 4 ; skip next 4 bytes
2986 nop ; will jump here if r5 positive or zero
2988 jCOND -n ;assumes jump n bytes backward:
2998 jCOND $n ; jump from PC in either direction. */
3000 if (exp
.X_op
== O_constant
)
3002 int x
= exp
.X_add_number
;
3006 as_warn (_("Even number required. Rounded to %d"), x
+ 1);
3010 if ((*l1
== '$' && x
> 0) || x
< 0)
3015 if (x
> 512 || x
< -511)
3017 as_bad (_("Wrong displacement %d"), x
<< 1);
3022 frag
= frag_more (2); /* Instr size is 1 word. */
3025 bfd_putl16 ((bfd_vma
) bin
, frag
);
3027 else if (exp
.X_op
== O_symbol
&& *l1
!= '$')
3030 frag
= frag_more (2); /* Instr size is 1 word. */
3031 where
= frag
- frag_now
->fr_literal
;
3032 fix_new_exp (frag_now
, where
, 2,
3033 &exp
, TRUE
, BFD_RELOC_MSP430_10_PCREL
);
3035 bfd_putl16 ((bfd_vma
) bin
, frag
);
3037 else if (*l1
== '$')
3039 as_bad (_("instruction requires label sans '$'"));
3043 ("instruction requires label or value in range -511:512"));
3044 dwarf2_emit_insn (insn_length
);
3049 as_bad (_("instruction requires label"));
3054 case 4: /* Extended jumps. */
3055 if (!msp430_enable_polys
)
3057 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3061 line
= extract_operand (line
, l1
, sizeof (l1
));
3067 /* Ignore absolute addressing. make it PC relative anyway. */
3068 if (*m
== '#' || *m
== '$')
3071 parse_exp (m
, & exp
);
3072 if (exp
.X_op
== O_symbol
)
3074 /* Relaxation required. */
3075 struct rcodes_s rc
= msp430_rcodes
[opcode
->insn_opnumb
];
3077 if (target_is_430x ())
3078 rc
= msp430x_rcodes
[opcode
->insn_opnumb
];
3080 /* The parameter to dwarf2_emit_insn is actually the offset to
3081 the start of the insn from the fix piece of instruction that
3082 was emitted. Since next fragments may have variable size we
3083 tie debug info to the beginning of the instruction. */
3085 frag
= frag_more (8);
3086 dwarf2_emit_insn (0);
3087 bfd_putl16 ((bfd_vma
) rc
.sop
, frag
);
3088 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3090 ENCODE_RELAX (rc
.lpos
, STATE_BITS10
),
3092 0, /* Offset is zero if jump dist less than 1K. */
3098 as_bad (_("instruction requires label"));
3101 case 5: /* Emulated extended branches. */
3102 if (!msp430_enable_polys
)
3104 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3107 line
= extract_operand (line
, l1
, sizeof (l1
));
3113 /* Ignore absolute addressing. make it PC relative anyway. */
3114 if (*m
== '#' || *m
== '$')
3117 parse_exp (m
, & exp
);
3118 if (exp
.X_op
== O_symbol
)
3120 /* Relaxation required. */
3121 struct hcodes_s hc
= msp430_hcodes
[opcode
->insn_opnumb
];
3123 if (target_is_430x ())
3124 hc
= msp430x_hcodes
[opcode
->insn_opnumb
];
3127 frag
= frag_more (8);
3128 dwarf2_emit_insn (0);
3129 bfd_putl16 ((bfd_vma
) hc
.op0
, frag
);
3130 bfd_putl16 ((bfd_vma
) hc
.op1
, frag
+2);
3132 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3133 ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
), /* Wild guess. */
3135 0, /* Offset is zero if jump dist less than 1K. */
3141 as_bad (_("instruction requires label"));
3145 as_bad (_("Illegal instruction or not implemented opcode."));
3148 input_line_pointer
= line
;
3149 check_for_nop
= nop_check_needed
;
3154 md_assemble (char * str
)
3156 struct msp430_opcode_s
* opcode
;
3160 str
= skip_space (str
); /* Skip leading spaces. */
3161 str
= extract_cmd (str
, cmd
, sizeof (cmd
));
3163 while (cmd
[i
] && i
< sizeof (cmd
))
3165 char a
= TOLOWER (cmd
[i
]);
3172 as_bad (_("can't find opcode "));
3176 opcode
= (struct msp430_opcode_s
*) hash_find (msp430_hash
, cmd
);
3180 as_bad (_("unknown opcode `%s'"), cmd
);
3185 char *__t
= input_line_pointer
;
3187 msp430_operands (opcode
, str
);
3188 input_line_pointer
= __t
;
3192 /* GAS will call this function for each section at the end of the assembly,
3193 to permit the CPU backend to adjust the alignment of a section. */
3196 md_section_align (asection
* seg
, valueT addr
)
3198 int align
= bfd_get_section_alignment (stdoutput
, seg
);
3200 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
3203 /* If you define this macro, it should return the offset between the
3204 address of a PC relative fixup and the position from which the PC
3205 relative adjustment should be made. On many processors, the base
3206 of a PC relative instruction is the next instruction, so this
3207 macro would return the length of an instruction. */
3210 md_pcrel_from_section (fixS
* fixp
, segT sec
)
3212 if (fixp
->fx_addsy
!= (symbolS
*) NULL
3213 && (!S_IS_DEFINED (fixp
->fx_addsy
)
3214 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
3217 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3220 /* Replaces standard TC_FORCE_RELOCATION_LOCAL.
3221 Now it handles the situation when relocations
3222 have to be passed to linker. */
3224 msp430_force_relocation_local (fixS
*fixp
)
3226 if (fixp
->fx_r_type
== BFD_RELOC_MSP430_10_PCREL
)
3230 if (msp430_enable_polys
3231 && !msp430_enable_relax
)
3234 return (!fixp
->fx_pcrel
3235 || generic_force_reloc (fixp
));
3239 /* GAS will call this for each fixup. It should store the correct
3240 value in the object file. */
3242 md_apply_fix (fixS
* fixp
, valueT
* valuep
, segT seg
)
3244 unsigned char * where
;
3248 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
3253 else if (fixp
->fx_pcrel
)
3255 segT s
= S_GET_SEGMENT (fixp
->fx_addsy
);
3257 if (fixp
->fx_addsy
&& (s
== seg
|| s
== absolute_section
))
3259 /* FIXME: We can appear here only in case if we perform a pc
3260 relative jump to the label which is i) global, ii) locally
3261 defined or this is a jump to an absolute symbol.
3262 If this is an absolute symbol -- everything is OK.
3263 If this is a global label, we've got a symbol value defined
3265 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
3266 from this section start
3267 2. *valuep will contain the real offset from jump insn to the
3269 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
3270 will be incorrect. Therefore remove s_get_value. */
3271 value
= /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep
;
3279 value
= fixp
->fx_offset
;
3281 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
3283 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3285 value
-= S_GET_VALUE (fixp
->fx_subsy
);
3291 fixp
->fx_no_overflow
= 1;
3293 /* If polymorphs are enabled and relax disabled.
3294 do not kill any relocs and pass them to linker. */
3295 if (msp430_enable_polys
3296 && !msp430_enable_relax
)
3298 if (!fixp
->fx_addsy
|| (fixp
->fx_addsy
3299 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
))
3300 fixp
->fx_done
= 1; /* It is ok to kill 'abs' reloc. */
3307 /* Fetch the instruction, insert the fully resolved operand
3308 value, and stuff the instruction back again. */
3309 where
= (unsigned char *) fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
3311 insn
= bfd_getl16 (where
);
3313 switch (fixp
->fx_r_type
)
3315 case BFD_RELOC_MSP430_10_PCREL
:
3317 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3318 _("odd address operand: %ld"), value
);
3320 /* Jumps are in words. */
3322 --value
; /* Correct PC. */
3324 if (value
< -512 || value
> 511)
3325 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3326 _("operand out of range: %ld"), value
);
3328 value
&= 0x3ff; /* get rid of extended sign */
3329 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
3332 case BFD_RELOC_MSP430X_PCR16
:
3333 case BFD_RELOC_MSP430_RL_PCREL
:
3334 case BFD_RELOC_MSP430_16_PCREL
:
3336 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3337 _("odd address operand: %ld"), value
);
3340 case BFD_RELOC_MSP430_16_PCREL_BYTE
:
3341 /* Nothing to be corrected here. */
3342 if (value
< -32768 || value
> 65536)
3343 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3344 _("operand out of range: %ld"), value
);
3347 case BFD_RELOC_MSP430X_ABS16
:
3348 case BFD_RELOC_MSP430_16
:
3350 case BFD_RELOC_MSP430_16_BYTE
:
3351 value
&= 0xffff; /* Get rid of extended sign. */
3352 bfd_putl16 ((bfd_vma
) value
, where
);
3356 bfd_putl16 ((bfd_vma
) value
, where
);
3359 case BFD_RELOC_MSP430_ABS8
:
3361 bfd_put_8 (NULL
, (bfd_vma
) value
, where
);
3364 case BFD_RELOC_MSP430X_ABS20_EXT_SRC
:
3365 case BFD_RELOC_MSP430X_PCR20_EXT_SRC
:
3366 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3368 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 7) | insn
), where
);
3371 case BFD_RELOC_MSP430X_ABS20_ADR_SRC
:
3372 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3374 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 8) | insn
), where
);
3377 case BFD_RELOC_MSP430X_ABS20_EXT_ODST
:
3378 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3380 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3383 case BFD_RELOC_MSP430X_PCR20_CALL
:
3384 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3386 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3389 case BFD_RELOC_MSP430X_ABS20_EXT_DST
:
3390 case BFD_RELOC_MSP430X_PCR20_EXT_DST
:
3391 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3393 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3396 case BFD_RELOC_MSP430X_PCR20_EXT_ODST
:
3397 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3399 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3402 case BFD_RELOC_MSP430X_ABS20_ADR_DST
:
3403 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3405 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3409 as_fatal (_("line %d: unknown relocation type: 0x%x"),
3410 fixp
->fx_line
, fixp
->fx_r_type
);
3416 fixp
->fx_addnumber
= value
;
3421 S_IS_GAS_LOCAL (symbolS
* s
)
3428 name
= S_GET_NAME (s
);
3429 len
= strlen (name
) - 1;
3431 return name
[len
] == 1 || name
[len
] == 2;
3434 /* GAS will call this to generate a reloc, passing the resulting reloc
3435 to `bfd_install_relocation'. This currently works poorly, as
3436 `bfd_install_relocation' often does the wrong thing, and instances of
3437 `tc_gen_reloc' have been written to work around the problems, which
3438 in turns makes it difficult to fix `bfd_install_relocation'. */
3440 /* If while processing a fixup, a reloc really needs to be created
3441 then it is done here. */
3444 tc_gen_reloc (asection
* seg ATTRIBUTE_UNUSED
, fixS
* fixp
)
3446 static arelent
* no_relocs
= NULL
;
3447 static arelent
* relocs
[MAX_RELOC_EXPANSION
+ 1];
3450 reloc
= xmalloc (sizeof (arelent
));
3451 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3452 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3454 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3457 _("reloc %d not supported by object file format"),
3458 (int) fixp
->fx_r_type
);
3467 && S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3469 fixp
->fx_offset
-= S_GET_VALUE (fixp
->fx_subsy
);
3470 fixp
->fx_subsy
= NULL
;
3473 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
3475 asection
*asec
, *ssec
;
3477 asec
= S_GET_SEGMENT (fixp
->fx_addsy
);
3478 ssec
= S_GET_SEGMENT (fixp
->fx_subsy
);
3480 /* If we have a difference between two different, non-absolute symbols
3481 we must generate two relocs (one for each symbol) and allow the
3482 linker to resolve them - relaxation may change the distances between
3483 symbols, even local symbols defined in the same section.
3485 Unfortunately we cannot do this with assembler generated local labels
3486 because there can be multiple incarnations of the same label, with
3487 exactly the same name, in any given section and the linker will have
3488 no way to identify the correct one. Instead we just have to hope
3489 that no relaxtion will occur between the local label and the other
3490 symbol in the expression.
3492 Similarly we have to compute differences between symbols in the .eh_frame
3493 section as the linker is not smart enough to apply relocations there
3494 before attempting to process it. */
3495 if ((ssec
!= absolute_section
|| asec
!= absolute_section
)
3496 && (fixp
->fx_addsy
!= fixp
->fx_subsy
)
3497 && strcmp (ssec
->name
, ".eh_frame") != 0
3498 && ! S_IS_GAS_LOCAL (fixp
->fx_addsy
)
3499 && ! S_IS_GAS_LOCAL (fixp
->fx_subsy
))
3501 arelent
* reloc2
= xmalloc (sizeof * reloc
);
3506 reloc2
->address
= reloc
->address
;
3507 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
,
3508 BFD_RELOC_MSP430_SYM_DIFF
);
3509 reloc2
->addend
= - S_GET_VALUE (fixp
->fx_subsy
);
3511 if (ssec
== absolute_section
)
3512 reloc2
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3515 reloc2
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3516 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_subsy
);
3519 reloc
->addend
= fixp
->fx_offset
;
3520 if (asec
== absolute_section
)
3522 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
3523 reloc
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3527 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3528 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3537 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3539 reloc
->addend
= (S_GET_VALUE (fixp
->fx_addsy
)
3540 - S_GET_VALUE (fixp
->fx_subsy
) + fixp
->fx_offset
);
3542 switch (fixp
->fx_r_type
)
3545 md_number_to_chars (fixpos
, reloc
->addend
, 1);
3549 md_number_to_chars (fixpos
, reloc
->addend
, 2);
3553 md_number_to_chars (fixpos
, reloc
->addend
, 3);
3557 md_number_to_chars (fixpos
, reloc
->addend
, 4);
3562 = (asymbol
**) bfd_abs_section_ptr
->symbol_ptr_ptr
;
3573 if (fixp
->fx_r_type
== BFD_RELOC_MSP430X_ABS16
3574 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
3576 bfd_vma amount
= S_GET_VALUE (fixp
->fx_addsy
);
3577 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3579 md_number_to_chars (fixpos
, amount
, 2);
3584 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3585 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3586 reloc
->addend
= fixp
->fx_offset
;
3588 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3589 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3590 reloc
->address
= fixp
->fx_offset
;
3597 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
3598 asection
* segment_type ATTRIBUTE_UNUSED
)
3600 if (fragP
->fr_symbol
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
3602 /* This is a jump -> pcrel mode. Nothing to do much here.
3603 Return value == 2. */
3605 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_BITS10
);
3607 else if (fragP
->fr_symbol
)
3609 /* Its got a segment, but its not ours. Even if fr_symbol is in
3610 an absolute segment, we don't know a displacement until we link
3611 object files. So it will always be long. This also applies to
3612 labels in a subsegment of current. Liker may relax it to short
3613 jump later. Return value == 8. */
3615 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_WORD
);
3619 /* We know the abs value. may be it is a jump to fixed address.
3620 Impossible in our case, cause all constants already handled. */
3622 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_UNDEF
);
3625 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3629 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
,
3630 asection
* sec ATTRIBUTE_UNUSED
,
3636 struct rcodes_s
* cc
= NULL
;
3637 struct hcodes_s
* hc
= NULL
;
3639 switch (fragP
->fr_subtype
)
3641 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_BITS10
):
3642 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_BITS10
):
3643 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_BITS10
):
3644 /* We do not have to convert anything here.
3645 Just apply a fix. */
3646 rela
= BFD_RELOC_MSP430_10_PCREL
;
3649 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_WORD
):
3650 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_UNDEF
):
3651 /* Convert uncond branch jmp lab -> br lab. */
3652 if (target_is_430x ())
3653 cc
= msp430x_rcodes
+ 7;
3655 cc
= msp430_rcodes
+ 7;
3656 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3657 bfd_putl16 (cc
->lop0
, where
);
3658 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3662 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_WORD
):
3663 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_UNDEF
):
3665 /* Other simple branches. */
3666 int insn
= bfd_getl16 (fragP
->fr_opcode
);
3669 /* Find actual instruction. */
3670 if (target_is_430x ())
3672 for (i
= 0; i
< 7 && !cc
; i
++)
3673 if (msp430x_rcodes
[i
].sop
== insn
)
3674 cc
= msp430x_rcodes
+ i
;
3678 for (i
= 0; i
< 7 && !cc
; i
++)
3679 if (msp430_rcodes
[i
].sop
== insn
)
3680 cc
= & msp430_rcodes
[i
];
3683 if (!cc
|| !cc
->name
)
3684 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
3685 __FUNCTION__
, (long) insn
);
3686 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3687 bfd_putl16 (cc
->lop0
, where
);
3688 bfd_putl16 (cc
->lop1
, where
+ 2);
3689 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3694 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_WORD
):
3695 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_UNDEF
):
3696 if (target_is_430x ())
3697 cc
= msp430x_rcodes
+ 6;
3699 cc
= msp430_rcodes
+ 6;
3700 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3701 bfd_putl16 (cc
->lop0
, where
);
3702 bfd_putl16 (cc
->lop1
, where
+ 2);
3703 bfd_putl16 (cc
->lop2
, where
+ 4);
3704 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3708 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
):
3710 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3713 if (target_is_430x ())
3715 for (i
= 0; i
< 4 && !hc
; i
++)
3716 if (msp430x_hcodes
[i
].op1
== insn
)
3717 hc
= msp430x_hcodes
+ i
;
3721 for (i
= 0; i
< 4 && !hc
; i
++)
3722 if (msp430_hcodes
[i
].op1
== insn
)
3723 hc
= &msp430_hcodes
[i
];
3725 if (!hc
|| !hc
->name
)
3726 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3727 __FUNCTION__
, (long) insn
);
3728 rela
= BFD_RELOC_MSP430_10_PCREL
;
3729 /* Apply a fix for a first label if necessary.
3730 another fix will be applied to the next word of insn anyway. */
3732 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3733 fragP
->fr_offset
, TRUE
, rela
);
3739 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_WORD
):
3740 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_UNDEF
):
3742 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3745 if (target_is_430x ())
3747 for (i
= 0; i
< 4 && !hc
; i
++)
3748 if (msp430x_hcodes
[i
].op1
== insn
)
3749 hc
= msp430x_hcodes
+ i
;
3753 for (i
= 0; i
< 4 && !hc
; i
++)
3754 if (msp430_hcodes
[i
].op1
== insn
)
3755 hc
= & msp430_hcodes
[i
];
3757 if (!hc
|| !hc
->name
)
3758 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3759 __FUNCTION__
, (long) insn
);
3760 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3761 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3762 bfd_putl16 (hc
->lop0
, where
);
3763 bfd_putl16 (hc
->lop1
, where
+ 2);
3764 bfd_putl16 (hc
->lop2
, where
+ 4);
3770 as_fatal (_("internal inconsistency problem in %s: %lx"),
3771 __FUNCTION__
, (long) fragP
->fr_subtype
);
3775 /* Now apply fix. */
3776 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3777 fragP
->fr_offset
, TRUE
, rela
);
3778 /* Just fixed 2 bytes. */
3782 /* Relax fragment. Mostly stolen from hc11 and mcore
3783 which arches I think I know. */
3786 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
* fragP
,
3787 long stretch ATTRIBUTE_UNUSED
)
3792 const relax_typeS
*this_type
;
3793 const relax_typeS
*start_type
;
3794 relax_substateT next_state
;
3795 relax_substateT this_state
;
3796 const relax_typeS
*table
= md_relax_table
;
3798 /* Nothing to be done if the frag has already max size. */
3799 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_UNDEF
3800 || RELAX_STATE (fragP
->fr_subtype
) == STATE_WORD
)
3803 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_BITS10
)
3805 symbolP
= fragP
->fr_symbol
;
3806 if (symbol_resolved_p (symbolP
))
3807 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3809 /* We know the offset. calculate a distance. */
3810 aim
= S_GET_VALUE (symbolP
) - fragP
->fr_address
- fragP
->fr_fix
;
3813 if (!msp430_enable_relax
)
3815 /* Relaxation is not enabled. So, make all jump as long ones
3816 by setting 'aim' to quite high value. */
3820 this_state
= fragP
->fr_subtype
;
3821 start_type
= this_type
= table
+ this_state
;
3825 /* Look backwards. */
3826 for (next_state
= this_type
->rlx_more
; next_state
;)
3827 if (aim
>= this_type
->rlx_backward
|| !this_type
->rlx_backward
)
3831 /* Grow to next state. */
3832 this_state
= next_state
;
3833 this_type
= table
+ this_state
;
3834 next_state
= this_type
->rlx_more
;
3839 /* Look forwards. */
3840 for (next_state
= this_type
->rlx_more
; next_state
;)
3841 if (aim
<= this_type
->rlx_forward
|| !this_type
->rlx_forward
)
3845 /* Grow to next state. */
3846 this_state
= next_state
;
3847 this_type
= table
+ this_state
;
3848 next_state
= this_type
->rlx_more
;
3852 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3854 fragP
->fr_subtype
= this_state
;
3858 /* Return FALSE if the fixup in fixp should be left alone and not
3859 adjusted. We return FALSE here so that linker relaxation will
3863 msp430_fix_adjustable (struct fix
*fixp ATTRIBUTE_UNUSED
)
3865 /* If the symbol is in a non-code section then it should be OK. */
3867 && ((S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_CODE
) == 0))
3873 /* Set the contents of the .MSP430.attributes section. */
3876 msp430_md_end (void)
3878 if (check_for_nop
== TRUE
&& warn_interrupt_nops
)
3879 as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed");
3881 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_ISA
,
3882 target_is_430x () ? 2 : 1);
3884 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Code_Model
,
3885 large_model
? 2 : 1);
3887 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Data_Model
,
3888 large_model
? 2 : 1);
3891 /* Returns FALSE if there is a msp430 specific reason why the
3892 subtraction of two same-section symbols cannot be computed by
3896 msp430_allow_local_subtract (expressionS
* left
,
3897 expressionS
* right
,
3900 /* If the symbols are not in a code section then they are OK. */
3901 if ((section
->flags
& SEC_CODE
) == 0)
3904 if (S_IS_GAS_LOCAL (left
->X_add_symbol
) || S_IS_GAS_LOCAL (right
->X_add_symbol
))
3907 if (left
->X_add_symbol
== right
->X_add_symbol
)
3910 /* We have to assume that there may be instructions between the
3911 two symbols and that relaxation may increase the distance between