1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
88 static struct riscv_set_options riscv_opts
=
94 DEFAULT_RISCV_ATTR
, /* arch_attr */
98 riscv_set_rvc (bfd_boolean rvc_value
)
101 elf_flags
|= EF_RISCV_RVC
;
103 riscv_opts
.rvc
= rvc_value
;
107 riscv_set_rve (bfd_boolean rve_value
)
109 riscv_opts
.rve
= rve_value
;
112 static riscv_subset_list_t riscv_subsets
;
115 riscv_subset_supports (const char *feature
)
117 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
120 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
124 riscv_multi_subset_supports (const char *features
[])
127 bfd_boolean supported
= TRUE
;
129 for (;features
[i
]; ++i
)
130 supported
= supported
&& riscv_subset_supports (features
[i
]);
135 /* Set which ISA and extensions are available. */
138 riscv_set_arch (const char *s
)
140 riscv_parse_subset_t rps
;
141 rps
.subset_list
= &riscv_subsets
;
142 rps
.error_handler
= as_fatal
;
145 riscv_release_subset_list (&riscv_subsets
);
146 riscv_parse_subset (&rps
, s
);
149 /* Handle of the OPCODE hash table. */
150 static struct hash_control
*op_hash
= NULL
;
152 /* Handle of the type of .insn hash table. */
153 static struct hash_control
*insn_type_hash
= NULL
;
155 /* This array holds the chars that always start a comment. If the
156 pre-processor is disabled, these aren't very useful */
157 const char comment_chars
[] = "#";
159 /* This array holds the chars that only start a comment at the beginning of
160 a line. If the line seems to have the form '# 123 filename'
161 .line and .file directives will appear in the pre-processed output */
162 /* Note that input_file.c hand checks for '#' at the beginning of the
163 first line of the input file. This is because the compiler outputs
164 #NO_APP at the beginning of its output. */
165 /* Also note that C style comments are always supported. */
166 const char line_comment_chars
[] = "#";
168 /* This array holds machine specific line separator characters. */
169 const char line_separator_chars
[] = ";";
171 /* Chars that can be used to separate mant from exp in floating point nums */
172 const char EXP_CHARS
[] = "eE";
174 /* Chars that mean this number is a floating point constant */
177 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
179 /* Indicate we are already assemble any instructions or not. */
180 static bfd_boolean start_assemble
= FALSE
;
182 /* Indicate arch attribute is explictly set. */
183 static bfd_boolean explicit_arch_attr
= FALSE
;
185 /* Macros for encoding relaxation state for RVC branches and far jumps. */
186 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
189 | ((uncond) ? 1 : 0) \
192 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
193 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
194 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
195 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
197 /* Is the given value a sign-extended 32-bit value? */
198 #define IS_SEXT_32BIT_NUM(x) \
199 (((x) &~ (offsetT) 0x7fffffff) == 0 \
200 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
203 #define IS_ZEXT_32BIT_NUM(x) \
204 (((x) &~ (offsetT) 0xffffffff) == 0 \
205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
207 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
208 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
209 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
210 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
212 /* Determine if an instruction matches an opcode. */
213 #define OPCODE_MATCHES(OPCODE, OP) \
214 (((OPCODE) & MASK_##OP) == MATCH_##OP)
216 static char *expr_end
;
218 /* The default target format to use. */
221 riscv_target_format (void)
223 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
226 /* Return the length of instruction INSN. */
228 static inline unsigned int
229 insn_length (const struct riscv_cl_insn
*insn
)
231 return riscv_insn_length (insn
->insn_opcode
);
234 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
237 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
240 insn
->insn_opcode
= mo
->match
;
246 /* Install INSN at the location specified by its "frag" and "where" fields. */
249 install_insn (const struct riscv_cl_insn
*insn
)
251 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
252 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
255 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
256 and install the opcode in the new location. */
259 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
263 if (insn
->fixp
!= NULL
)
265 insn
->fixp
->fx_frag
= frag
;
266 insn
->fixp
->fx_where
= where
;
271 /* Add INSN to the end of the output. */
274 add_fixed_insn (struct riscv_cl_insn
*insn
)
276 char *f
= frag_more (insn_length (insn
));
277 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
281 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
282 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
284 frag_grow (max_chars
);
285 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
286 frag_var (rs_machine_dependent
, max_chars
, var
,
287 subtype
, symbol
, offset
, NULL
);
290 /* Compute the length of a branch sequence, and adjust the stored length
291 accordingly. If FRAGP is NULL, the worst-case length is returned. */
294 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
296 int jump
, rvc
, length
= 8;
301 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
302 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
303 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
305 /* Assume jumps are in range; the linker will catch any that aren't. */
306 length
= jump
? 4 : 8;
308 if (fragp
->fr_symbol
!= NULL
309 && S_IS_DEFINED (fragp
->fr_symbol
)
310 && !S_IS_WEAK (fragp
->fr_symbol
)
311 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
313 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
314 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
315 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
317 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
319 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
321 else if (!jump
&& rvc
)
326 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
331 /* Information about an opcode name, mnemonics and its value. */
338 /* List for all supported opcode name. */
339 static const struct opcode_name_t opcode_name_list
[] =
384 /* Hash table for lookup opcode name. */
385 static struct hash_control
*opcode_names_hash
= NULL
;
387 /* Initialization for hash table of opcode name. */
389 init_opcode_names_hash (void)
392 const struct opcode_name_t
*opcode
;
394 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
396 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
399 as_fatal (_("internal error: can't hash `%s': %s"),
400 opcode
->name
, retval
);
404 /* Find `s` is a valid opcode name or not,
405 return the opcode name info if found. */
406 static const struct opcode_name_t
*
407 opcode_name_lookup (char **s
)
411 struct opcode_name_t
*o
;
413 /* Find end of name. */
415 if (is_name_beginner (*e
))
417 while (is_part_of_name (*e
))
420 /* Terminate name. */
424 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
426 /* Advance to next token if one was recognized. */
450 static struct hash_control
*reg_names_hash
= NULL
;
452 #define ENCODE_REG_HASH(cls, n) \
453 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
454 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
455 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
458 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
460 void *hash
= ENCODE_REG_HASH (class, n
);
461 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
464 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
468 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
472 for (i
= 0; i
< n
; i
++)
473 hash_reg_name (class, names
[i
], i
);
477 reg_lookup_internal (const char *s
, enum reg_class
class)
479 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
481 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
484 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
487 return DECODE_REG_NUM (r
);
491 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
497 /* Find end of name. */
499 if (is_name_beginner (*e
))
501 while (is_part_of_name (*e
))
504 /* Terminate name. */
508 /* Look for the register. Advance to next token if one was recognized. */
509 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
519 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
521 const char *p
= strchr (*s
, ',');
522 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
527 for (i
= 0; i
< size
; i
++)
528 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
538 /* For consistency checking, verify that all bits are specified either
539 by the match/mask part of the instruction definition, or by the
542 `length` could be 0, 4 or 8, 0 for auto detection. */
544 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
546 const char *p
= opc
->args
;
548 insn_t used_bits
= opc
->mask
;
550 insn_t required_bits
;
553 insn_width
= 8 * riscv_insn_length (opc
->match
);
555 insn_width
= 8 * length
;
557 required_bits
= ~0ULL >> (64 - insn_width
);
559 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
561 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
562 opc
->name
, opc
->args
);
566 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
573 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
574 case 'c': break; /* RS1, constrained to equal sp */
575 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
576 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
577 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
578 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
579 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
580 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
581 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
582 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
583 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
584 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
585 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
586 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
587 case 'w': break; /* RS1S, constrained to equal RD */
588 case 'x': break; /* RS2S, constrained to equal RD */
589 case 'z': break; /* RS2S, contrained to be x0 */
590 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
591 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
592 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
593 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
594 case 'U': break; /* RS1, constrained to equal RD */
595 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
596 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
597 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
598 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
599 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
600 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
601 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
602 case 'F': /* funct */
605 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
606 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
607 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
608 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
610 as_bad (_("internal: bad RISC-V opcode"
611 " (unknown operand type `CF%c'): %s %s"),
612 c
, opc
->name
, opc
->args
);
617 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
618 c
, opc
->name
, opc
->args
);
625 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
626 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
628 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
629 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
630 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
632 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
633 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
634 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
635 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
636 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
637 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
638 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
639 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
640 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
641 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
642 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
644 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
645 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
646 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
647 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
648 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
654 case 'F': /* funct */
657 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
658 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
659 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
661 as_bad (_("internal: bad RISC-V opcode"
662 " (unknown operand type `F%c'): %s %s"),
663 c
, opc
->name
, opc
->args
);
667 case 'O': /* opcode */
670 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
671 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
673 as_bad (_("internal: bad RISC-V opcode"
674 " (unknown operand type `F%c'): %s %s"),
675 c
, opc
->name
, opc
->args
);
680 as_bad (_("internal: bad RISC-V opcode "
681 "(unknown operand type `%c'): %s %s"),
682 c
, opc
->name
, opc
->args
);
686 if (used_bits
!= required_bits
)
688 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
689 ~(unsigned long)(used_bits
& required_bits
),
690 opc
->name
, opc
->args
);
696 struct percent_op_match
699 bfd_reloc_code_real_type reloc
;
702 /* Common hash table initialization function for
703 instruction and .insn directive. */
704 static struct hash_control
*
705 init_opcode_hash (const struct riscv_opcode
*opcodes
,
706 bfd_boolean insn_directive_p
)
710 struct hash_control
*hash
= hash_new ();
711 while (opcodes
[i
].name
)
713 const char *name
= opcodes
[i
].name
;
714 const char *hash_error
=
715 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
719 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
720 opcodes
[i
].name
, hash_error
);
721 /* Probably a memory allocation problem? Give up now. */
722 as_fatal (_("Broken assembler. No assembly attempted."));
727 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
729 if (insn_directive_p
)
730 length
= ((name
[0] == 'c') ? 2 : 4);
732 length
= 0; /* Let assembler determine the length. */
733 if (!validate_riscv_insn (&opcodes
[i
], length
))
734 as_fatal (_("Broken assembler. No assembly attempted."));
737 gas_assert (!insn_directive_p
);
740 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
746 /* This function is called once, at assembler startup time. It should set up
747 all the tables, etc. that the MD part of the assembler will need. */
752 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
754 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
755 as_warn (_("Could not set architecture and machine"));
757 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
758 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
760 reg_names_hash
= hash_new ();
761 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
762 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
763 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
764 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
766 /* Add "fp" as an alias for "s0". */
767 hash_reg_name (RCLASS_GPR
, "fp", 8);
769 opcode_names_hash
= hash_new ();
770 init_opcode_names_hash ();
772 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
773 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
774 #include "opcode/riscv-opc.h"
777 /* Set the default alignment for the text section. */
778 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
782 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
789 case BFD_RELOC_RISCV_HI20
:
790 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
792 case BFD_RELOC_RISCV_LO12_S
:
793 return ENCODE_STYPE_IMM (value
);
795 case BFD_RELOC_RISCV_LO12_I
:
796 return ENCODE_ITYPE_IMM (value
);
803 /* Output an instruction. IP is the instruction information.
804 ADDRESS_EXPR is an operand of the instruction to be used with
808 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
809 bfd_reloc_code_real_type reloc_type
)
811 dwarf2_emit_insn (0);
813 if (reloc_type
!= BFD_RELOC_UNUSED
)
815 reloc_howto_type
*howto
;
817 gas_assert (address_expr
);
818 if (reloc_type
== BFD_RELOC_12_PCREL
819 || reloc_type
== BFD_RELOC_RISCV_JMP
)
821 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
822 int best_case
= riscv_insn_length (ip
->insn_opcode
);
823 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
824 add_relaxed_insn (ip
, worst_case
, best_case
,
825 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
826 address_expr
->X_add_symbol
,
827 address_expr
->X_add_number
);
832 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
834 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
836 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
837 bfd_get_reloc_size (howto
),
838 address_expr
, FALSE
, reloc_type
);
840 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
847 /* We need to start a new frag after any instruction that can be
848 optimized away or compressed by the linker during relaxation, to prevent
849 the assembler from computing static offsets across such an instruction.
850 This is necessary to get correct EH info. */
851 if (reloc_type
== BFD_RELOC_RISCV_CALL
852 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
853 || reloc_type
== BFD_RELOC_RISCV_HI20
854 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
855 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
856 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
858 frag_wane (frag_now
);
863 /* Build an instruction created by a macro expansion. This is passed
864 a pointer to the count of instructions created so far, an
865 expression, the name of the instruction to build, an operand format
866 string, and corresponding arguments. */
869 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
871 const struct riscv_opcode
*mo
;
872 struct riscv_cl_insn insn
;
873 bfd_reloc_code_real_type r
;
876 va_start (args
, fmt
);
878 r
= BFD_RELOC_UNUSED
;
879 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
882 /* Find a non-RVC variant of the instruction. append_insn will compress
884 while (riscv_insn_length (mo
->match
) < 4)
886 gas_assert (strcmp (name
, mo
->name
) == 0);
888 create_insn (&insn
, mo
);
894 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
898 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
902 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
906 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
912 gas_assert (ep
!= NULL
);
913 r
= va_arg (args
, int);
921 as_fatal (_("internal error: invalid macro"));
926 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
928 append_insn (&insn
, ep
, r
);
931 /* Build an instruction created by a macro expansion. Like md_assemble but
932 accept a printf-style format string and arguments. */
935 md_assemblef (const char *format
, ...)
941 va_start (ap
, format
);
943 r
= vasprintf (&buf
, format
, ap
);
946 as_fatal (_("internal error: vasprintf failed"));
954 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
957 normalize_constant_expr (expressionS
*ex
)
961 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
962 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
963 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
967 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
968 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
971 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
972 bfd_boolean maybe_csr
)
974 if (ex
->X_op
== O_big
)
975 as_bad (_("unsupported large constant"));
976 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
977 as_bad (_("unknown CSR `%s'"),
978 S_GET_NAME (ex
->X_add_symbol
));
979 else if (ex
->X_op
!= O_constant
)
980 as_bad (_("Instruction %s requires absolute expression"),
982 normalize_constant_expr (ex
);
986 make_internal_label (void)
988 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
989 (valueT
) frag_now_fix (), frag_now
);
992 /* Load an entry from the GOT. */
994 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
995 const char *lo_insn
, const char *lo_pattern
,
996 bfd_reloc_code_real_type hi_reloc
,
997 bfd_reloc_code_real_type lo_reloc
)
1000 ep2
.X_op
= O_symbol
;
1001 ep2
.X_add_symbol
= make_internal_label ();
1002 ep2
.X_add_number
= 0;
1004 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1005 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1009 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1010 bfd_reloc_code_real_type hi_reloc
,
1011 bfd_reloc_code_real_type lo_reloc
)
1013 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1017 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1018 bfd_reloc_code_real_type hi_reloc
,
1019 bfd_reloc_code_real_type lo_reloc
)
1021 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1024 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1026 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1027 bfd_reloc_code_real_type reloc
)
1029 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1030 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1033 /* Load an integer constant into a register. */
1036 load_const (int reg
, expressionS
*ep
)
1038 int shift
= RISCV_IMM_BITS
;
1040 expressionS upper
= *ep
, lower
= *ep
;
1041 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1042 upper
.X_add_number
-= lower
.X_add_number
;
1044 if (ep
->X_op
!= O_constant
)
1046 as_bad (_("unsupported large constant"));
1050 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1052 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1053 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1056 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1057 load_const (reg
, &upper
);
1059 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1060 if (lower
.X_add_number
!= 0)
1061 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1062 lower
.X_add_number
);
1066 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1069 if (upper
.X_add_number
!= 0)
1071 /* Discard low part and zero-extend upper immediate. */
1072 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1074 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1078 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1079 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1080 lower
.X_add_number
);
1084 /* Expand RISC-V assembly macros into one or more instructions. */
1086 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1087 bfd_reloc_code_real_type
*imm_reloc
)
1089 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1090 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1091 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1092 int mask
= ip
->insn_mo
->mask
;
1097 load_const (rd
, imm_expr
);
1102 /* Load the address of a symbol into a register. */
1103 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1104 as_bad (_("offset too large"));
1106 if (imm_expr
->X_op
== O_constant
)
1107 load_const (rd
, imm_expr
);
1108 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1109 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1110 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1111 else /* Local PIC symbol, or any non-PIC symbol */
1112 pcrel_load (rd
, rd
, imm_expr
, "addi",
1113 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1117 pcrel_load (rd
, rd
, imm_expr
, "addi",
1118 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1122 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1123 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1127 pcrel_load (rd
, rd
, imm_expr
, "lb",
1128 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1132 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1133 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1137 pcrel_load (rd
, rd
, imm_expr
, "lh",
1138 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1142 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1143 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1147 pcrel_load (rd
, rd
, imm_expr
, "lw",
1148 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1152 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1153 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1157 pcrel_load (rd
, rd
, imm_expr
, "ld",
1158 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1162 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1163 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1167 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1168 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1172 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1173 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1177 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1178 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1182 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1183 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1187 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1188 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1192 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1193 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1197 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1198 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1202 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1206 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1211 static const struct percent_op_match percent_op_utype
[] =
1213 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1214 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1215 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1216 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1217 {"%hi", BFD_RELOC_RISCV_HI20
},
1221 static const struct percent_op_match percent_op_itype
[] =
1223 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1224 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1225 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1229 static const struct percent_op_match percent_op_stype
[] =
1231 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1232 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1233 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1237 static const struct percent_op_match percent_op_rtype
[] =
1239 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1243 static const struct percent_op_match percent_op_null
[] =
1248 /* Return true if *STR points to a relocation operator. When returning true,
1249 move *STR over the operator and store its relocation code in *RELOC.
1250 Leave both *STR and *RELOC alone when returning false. */
1253 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1254 const struct percent_op_match
*percent_op
)
1256 for ( ; percent_op
->str
; percent_op
++)
1257 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1259 int len
= strlen (percent_op
->str
);
1261 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1264 *str
+= strlen (percent_op
->str
);
1265 *reloc
= percent_op
->reloc
;
1267 /* Check whether the output BFD supports this relocation.
1268 If not, issue an error and fall back on something safe. */
1269 if (*reloc
!= BFD_RELOC_UNUSED
1270 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1272 as_bad ("relocation %s isn't supported by the current ABI",
1274 *reloc
= BFD_RELOC_UNUSED
;
1282 my_getExpression (expressionS
*ep
, char *str
)
1286 save_in
= input_line_pointer
;
1287 input_line_pointer
= str
;
1289 expr_end
= input_line_pointer
;
1290 input_line_pointer
= save_in
;
1293 /* Parse string STR as a 16-bit relocatable operand. Store the
1294 expression in *EP and the relocation, if any, in RELOC.
1295 Return the number of relocation operators used (0 or 1).
1297 On exit, EXPR_END points to the first character after the expression. */
1300 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1301 char *str
, const struct percent_op_match
*percent_op
)
1304 unsigned crux_depth
, str_depth
, regno
;
1307 /* First, check for integer registers. No callers can accept a reg, but
1308 we need to avoid accidentally creating a useless undefined symbol below,
1309 if this is an instruction pattern that can't match. A glibc build fails
1310 if this is removed. */
1311 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1313 ep
->X_op
= O_register
;
1314 ep
->X_add_number
= regno
;
1319 /* Search for the start of the main expression.
1320 End the loop with CRUX pointing to the start
1321 of the main expression and with CRUX_DEPTH containing the number
1322 of open brackets at that point. */
1329 crux_depth
= str_depth
;
1331 /* Skip over whitespace and brackets, keeping count of the number
1333 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1339 && parse_relocation (&str
, reloc
, percent_op
));
1341 my_getExpression (ep
, crux
);
1344 /* Match every open bracket. */
1345 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1350 as_bad ("unclosed '('");
1357 /* Parse opcode name, could be an mnemonics or number. */
1359 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1360 char *str
, const struct percent_op_match
*percent_op
)
1362 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1366 ep
->X_op
= O_constant
;
1367 ep
->X_add_number
= o
->val
;
1371 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1374 /* Detect and handle implicitly zero load-store offsets. For example,
1375 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1376 an implicit offset was detected. */
1379 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1381 /* Check whether there is only a single bracketed expression left.
1382 If so, it must be the base register and the constant must be zero. */
1383 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1385 ep
->X_op
= O_constant
;
1386 ep
->X_add_number
= 0;
1393 /* This routine assembles an instruction into its binary format. As a
1394 side effect, it sets the global variable imm_reloc to the type of
1395 relocation to do if one of the operands is an address expression. */
1398 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1399 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1404 struct riscv_opcode
*insn
;
1409 const struct percent_op_match
*p
;
1410 const char *error
= "unrecognized opcode";
1412 /* Parse the name of the instruction. Terminate the string if whitespace
1413 is found so that hash_find only sees the name part of the string. */
1414 for (s
= str
; *s
!= '\0'; ++s
)
1422 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1425 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1427 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1430 if (!riscv_multi_subset_supports (insn
->subset
))
1433 create_insn (ip
, insn
);
1436 imm_expr
->X_op
= O_absent
;
1437 *imm_reloc
= BFD_RELOC_UNUSED
;
1438 p
= percent_op_itype
;
1440 for (args
= insn
->args
;; ++args
)
1442 s
+= strspn (s
, " \t");
1445 case '\0': /* End of args. */
1446 if (insn
->pinfo
!= INSN_MACRO
)
1448 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1451 /* For .insn, insn->match and insn->mask are 0. */
1452 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1460 /* Successful assembly. */
1467 case 's': /* RS1 x8-x15 */
1468 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1469 || !(regno
>= 8 && regno
<= 15))
1471 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1473 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1474 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1475 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1478 case 't': /* RS2 x8-x15 */
1479 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1480 || !(regno
>= 8 && regno
<= 15))
1482 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1484 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1485 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1486 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1489 case 'U': /* RS1, constrained to equal RD. */
1490 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1491 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1495 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1497 INSERT_OPERAND (CRS2
, *ip
, regno
);
1499 case 'c': /* RS1, constrained to equal sp. */
1500 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1504 case 'z': /* RS2, contrained to equal x0. */
1505 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1510 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1511 || imm_expr
->X_op
!= O_constant
1512 || imm_expr
->X_add_number
<= 0
1513 || imm_expr
->X_add_number
>= 64)
1515 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1518 imm_expr
->X_op
= O_absent
;
1521 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1522 || imm_expr
->X_op
!= O_constant
1523 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1524 || imm_expr
->X_add_number
<= 0
1525 || imm_expr
->X_add_number
>= 32)
1527 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1530 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1531 || imm_expr
->X_op
!= O_constant
1532 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1533 || imm_expr
->X_add_number
< 0
1534 || imm_expr
->X_add_number
>= 256)
1536 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1539 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1540 || imm_expr
->X_op
!= O_constant
1541 || imm_expr
->X_add_number
== 0
1542 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1544 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1547 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1548 || imm_expr
->X_op
!= O_constant
1549 || imm_expr
->X_add_number
== 0
1550 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1552 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1555 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1557 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1558 || imm_expr
->X_op
!= O_constant
1559 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1561 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1564 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1566 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1567 || imm_expr
->X_op
!= O_constant
1568 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1570 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1573 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1575 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1576 || imm_expr
->X_op
!= O_constant
1577 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1580 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1583 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1585 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1586 || imm_expr
->X_op
!= O_constant
1587 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1590 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1593 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1594 || imm_expr
->X_op
!= O_constant
1595 /* C.addiw, c.li, and c.andi allow zero immediate.
1596 C.addi allows zero immediate as hint. Otherwise this
1598 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1600 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1603 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1604 || imm_expr
->X_op
!= O_constant
1605 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1606 || imm_expr
->X_add_number
== 0)
1609 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1612 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1613 || imm_expr
->X_op
!= O_constant
1614 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1615 || imm_expr
->X_add_number
== 0)
1618 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1621 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1623 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1624 || imm_expr
->X_op
!= O_constant
1625 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1628 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1631 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1633 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1634 || imm_expr
->X_op
!= O_constant
1635 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1638 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1641 p
= percent_op_utype
;
1642 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1645 if (imm_expr
->X_op
!= O_constant
1646 || imm_expr
->X_add_number
<= 0
1647 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1648 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1649 && (imm_expr
->X_add_number
<
1650 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1652 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1655 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1656 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1657 || ((int32_t)imm_expr
->X_add_number
1658 != imm_expr
->X_add_number
))
1660 imm_expr
->X_add_number
=
1661 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1667 case 'S': /* Floating-point RS1 x8-x15. */
1668 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1669 || !(regno
>= 8 && regno
<= 15))
1671 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1673 case 'D': /* Floating-point RS2 x8-x15. */
1674 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1675 || !(regno
>= 8 && regno
<= 15))
1677 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1679 case 'T': /* Floating-point RS2. */
1680 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1682 INSERT_OPERAND (CRS2
, *ip
, regno
);
1688 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1689 || imm_expr
->X_op
!= O_constant
1690 || imm_expr
->X_add_number
< 0
1691 || imm_expr
->X_add_number
>= 64)
1693 as_bad (_("bad value for funct6 field, "
1694 "value must be 0...64"));
1698 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1699 imm_expr
->X_op
= O_absent
;
1703 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1704 || imm_expr
->X_op
!= O_constant
1705 || imm_expr
->X_add_number
< 0
1706 || imm_expr
->X_add_number
>= 16)
1708 as_bad (_("bad value for funct4 field, "
1709 "value must be 0...15"));
1713 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1714 imm_expr
->X_op
= O_absent
;
1718 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1719 || imm_expr
->X_op
!= O_constant
1720 || imm_expr
->X_add_number
< 0
1721 || imm_expr
->X_add_number
>= 8)
1723 as_bad (_("bad value for funct3 field, "
1724 "value must be 0...7"));
1727 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1728 imm_expr
->X_op
= O_absent
;
1732 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1733 || imm_expr
->X_op
!= O_constant
1734 || imm_expr
->X_add_number
< 0
1735 || imm_expr
->X_add_number
>= 4)
1737 as_bad (_("bad value for funct2 field, "
1738 "value must be 0...3"));
1741 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1742 imm_expr
->X_op
= O_absent
;
1746 as_bad (_("bad compressed FUNCT field"
1747 " specifier 'CF%c'\n"),
1753 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1772 case '<': /* Shift amount, 0 - 31. */
1773 my_getExpression (imm_expr
, s
);
1774 check_absolute_expr (ip
, imm_expr
, FALSE
);
1775 if ((unsigned long) imm_expr
->X_add_number
> 31)
1776 as_bad (_("Improper shift amount (%lu)"),
1777 (unsigned long) imm_expr
->X_add_number
);
1778 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1779 imm_expr
->X_op
= O_absent
;
1783 case '>': /* Shift amount, 0 - (XLEN-1). */
1784 my_getExpression (imm_expr
, s
);
1785 check_absolute_expr (ip
, imm_expr
, FALSE
);
1786 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1787 as_bad (_("Improper shift amount (%lu)"),
1788 (unsigned long) imm_expr
->X_add_number
);
1789 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1790 imm_expr
->X_op
= O_absent
;
1794 case 'Z': /* CSRRxI immediate. */
1795 my_getExpression (imm_expr
, s
);
1796 check_absolute_expr (ip
, imm_expr
, FALSE
);
1797 if ((unsigned long) imm_expr
->X_add_number
> 31)
1798 as_bad (_("Improper CSRxI immediate (%lu)"),
1799 (unsigned long) imm_expr
->X_add_number
);
1800 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1801 imm_expr
->X_op
= O_absent
;
1805 case 'E': /* Control register. */
1806 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1807 INSERT_OPERAND (CSR
, *ip
, regno
);
1810 my_getExpression (imm_expr
, s
);
1811 check_absolute_expr (ip
, imm_expr
, TRUE
);
1812 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1813 as_bad (_("Improper CSR address (%lu)"),
1814 (unsigned long) imm_expr
->X_add_number
);
1815 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1816 imm_expr
->X_op
= O_absent
;
1821 case 'm': /* Rounding mode. */
1822 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1824 INSERT_OPERAND (RM
, *ip
, regno
);
1830 case 'Q': /* Fence predecessor/successor. */
1831 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1835 INSERT_OPERAND (PRED
, *ip
, regno
);
1837 INSERT_OPERAND (SUCC
, *ip
, regno
);
1842 case 'd': /* Destination register. */
1843 case 's': /* Source register. */
1844 case 't': /* Target register. */
1845 case 'r': /* rs3. */
1846 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1852 /* Now that we have assembled one operand, we use the args
1853 string to figure out where it goes in the instruction. */
1857 INSERT_OPERAND (RS1
, *ip
, regno
);
1860 INSERT_OPERAND (RD
, *ip
, regno
);
1863 INSERT_OPERAND (RS2
, *ip
, regno
);
1866 INSERT_OPERAND (RS3
, *ip
, regno
);
1873 case 'D': /* Floating point rd. */
1874 case 'S': /* Floating point rs1. */
1875 case 'T': /* Floating point rs2. */
1876 case 'U': /* Floating point rs1 and rs2. */
1877 case 'R': /* Floating point rs3. */
1878 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1886 INSERT_OPERAND (RD
, *ip
, regno
);
1889 INSERT_OPERAND (RS1
, *ip
, regno
);
1892 INSERT_OPERAND (RS1
, *ip
, regno
);
1895 INSERT_OPERAND (RS2
, *ip
, regno
);
1898 INSERT_OPERAND (RS3
, *ip
, regno
);
1907 my_getExpression (imm_expr
, s
);
1908 if (imm_expr
->X_op
!= O_big
1909 && imm_expr
->X_op
!= O_constant
)
1911 normalize_constant_expr (imm_expr
);
1916 my_getExpression (imm_expr
, s
);
1917 normalize_constant_expr (imm_expr
);
1918 /* The 'A' format specifier must be a symbol. */
1919 if (imm_expr
->X_op
!= O_symbol
)
1921 *imm_reloc
= BFD_RELOC_32
;
1926 my_getExpression (imm_expr
, s
);
1927 normalize_constant_expr (imm_expr
);
1928 /* The 'B' format specifier must be a symbol or a constant. */
1929 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1931 if (imm_expr
->X_op
== O_symbol
)
1932 *imm_reloc
= BFD_RELOC_32
;
1936 case 'j': /* Sign-extended immediate. */
1937 p
= percent_op_itype
;
1938 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1940 case 'q': /* Store displacement. */
1941 p
= percent_op_stype
;
1942 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1944 case 'o': /* Load displacement. */
1945 p
= percent_op_itype
;
1946 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1948 case '1': /* 4-operand add, must be %tprel_add. */
1949 p
= percent_op_rtype
;
1951 case '0': /* AMO "displacement," which must be zero. */
1952 p
= percent_op_null
;
1954 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1957 /* If this value won't fit into a 16 bit offset, then go
1958 find a macro that will generate the 32 bit offset
1960 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1962 normalize_constant_expr (imm_expr
);
1963 if (imm_expr
->X_op
!= O_constant
1964 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1966 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1967 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1974 case 'p': /* PC-relative offset. */
1976 *imm_reloc
= BFD_RELOC_12_PCREL
;
1977 my_getExpression (imm_expr
, s
);
1981 case 'u': /* Upper 20 bits. */
1982 p
= percent_op_utype
;
1983 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1985 if (imm_expr
->X_op
!= O_constant
)
1988 if (imm_expr
->X_add_number
< 0
1989 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1990 as_bad (_("lui expression not in range 0..1048575"));
1992 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1993 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1998 case 'a': /* 20-bit PC-relative offset. */
2000 my_getExpression (imm_expr
, s
);
2002 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2006 my_getExpression (imm_expr
, s
);
2008 if (strcmp (s
, "@plt") == 0)
2010 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2014 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2020 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2021 || imm_expr
->X_op
!= O_constant
2022 || imm_expr
->X_add_number
< 0
2023 || imm_expr
->X_add_number
>= 128
2024 || (imm_expr
->X_add_number
& 0x3) != 3)
2026 as_bad (_("bad value for opcode field, "
2027 "value must be 0...127 and "
2028 "lower 2 bits must be 0x3"));
2032 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2033 imm_expr
->X_op
= O_absent
;
2037 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2038 || imm_expr
->X_op
!= O_constant
2039 || imm_expr
->X_add_number
< 0
2040 || imm_expr
->X_add_number
>= 3)
2042 as_bad (_("bad value for opcode field, "
2043 "value must be 0...2"));
2047 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2048 imm_expr
->X_op
= O_absent
;
2052 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2060 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2061 || imm_expr
->X_op
!= O_constant
2062 || imm_expr
->X_add_number
< 0
2063 || imm_expr
->X_add_number
>= 128)
2065 as_bad (_("bad value for funct7 field, "
2066 "value must be 0...127"));
2070 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2071 imm_expr
->X_op
= O_absent
;
2075 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2076 || imm_expr
->X_op
!= O_constant
2077 || imm_expr
->X_add_number
< 0
2078 || imm_expr
->X_add_number
>= 8)
2080 as_bad (_("bad value for funct3 field, "
2081 "value must be 0...7"));
2085 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2086 imm_expr
->X_op
= O_absent
;
2090 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2091 || imm_expr
->X_op
!= O_constant
2092 || imm_expr
->X_add_number
< 0
2093 || imm_expr
->X_add_number
>= 4)
2095 as_bad (_("bad value for funct2 field, "
2096 "value must be 0...3"));
2100 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2101 imm_expr
->X_op
= O_absent
;
2106 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || imm_expr
->X_add_number
!= 0)
2116 imm_expr
->X_op
= O_absent
;
2120 as_fatal (_("internal error: bad argument type %c"), *args
);
2125 error
= _("illegal operands");
2129 /* Restore the character we might have clobbered above. */
2131 *(argsStart
- 1) = save_c
;
2137 md_assemble (char *str
)
2139 struct riscv_cl_insn insn
;
2140 expressionS imm_expr
;
2141 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2143 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2145 start_assemble
= TRUE
;
2149 as_bad ("%s `%s'", error
, str
);
2153 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2154 macro (&insn
, &imm_expr
, &imm_reloc
);
2156 append_insn (&insn
, &imm_expr
, imm_reloc
);
2160 md_atof (int type
, char *litP
, int *sizeP
)
2162 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2166 md_number_to_chars (char *buf
, valueT val
, int n
)
2168 number_to_chars_littleendian (buf
, val
, n
);
2171 const char *md_shortopts
= "O::g::G:";
2175 OPTION_MARCH
= OPTION_MD_BASE
,
2182 OPTION_NO_ARCH_ATTR
,
2186 struct option md_longopts
[] =
2188 {"march", required_argument
, NULL
, OPTION_MARCH
},
2189 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2190 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2191 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2192 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2193 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2194 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2195 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2196 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2198 {NULL
, no_argument
, NULL
, 0}
2200 size_t md_longopts_size
= sizeof (md_longopts
);
2203 FLOAT_ABI_DEFAULT
= -1,
2209 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2212 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2214 abi_xlen
= new_xlen
;
2215 float_abi
= new_float_abi
;
2220 md_parse_option (int c
, const char *arg
)
2225 riscv_set_arch (arg
);
2229 riscv_opts
.pic
= FALSE
;
2233 riscv_opts
.pic
= TRUE
;
2237 if (strcmp (arg
, "ilp32") == 0)
2238 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2239 else if (strcmp (arg
, "ilp32e") == 0)
2240 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2241 else if (strcmp (arg
, "ilp32f") == 0)
2242 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2243 else if (strcmp (arg
, "ilp32d") == 0)
2244 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2245 else if (strcmp (arg
, "ilp32q") == 0)
2246 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2247 else if (strcmp (arg
, "lp64") == 0)
2248 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2249 else if (strcmp (arg
, "lp64f") == 0)
2250 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2251 else if (strcmp (arg
, "lp64d") == 0)
2252 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2253 else if (strcmp (arg
, "lp64q") == 0)
2254 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2260 riscv_opts
.relax
= TRUE
;
2263 case OPTION_NO_RELAX
:
2264 riscv_opts
.relax
= FALSE
;
2267 case OPTION_ARCH_ATTR
:
2268 riscv_opts
.arch_attr
= TRUE
;
2271 case OPTION_NO_ARCH_ATTR
:
2272 riscv_opts
.arch_attr
= FALSE
;
2283 riscv_after_parse_args (void)
2287 if (strcmp (default_arch
, "riscv32") == 0)
2289 else if (strcmp (default_arch
, "riscv64") == 0)
2292 as_bad ("unknown default architecture `%s'", default_arch
);
2295 if (riscv_subsets
.head
== NULL
)
2296 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2298 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2299 riscv_set_rvc (FALSE
);
2300 if (riscv_subset_supports ("c"))
2301 riscv_set_rvc (TRUE
);
2303 /* Enable RVE if specified by the -march option. */
2304 riscv_set_rve (FALSE
);
2305 if (riscv_subset_supports ("e"))
2306 riscv_set_rve (TRUE
);
2308 /* Infer ABI from ISA if not specified on command line. */
2311 else if (abi_xlen
> xlen
)
2312 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2313 else if (abi_xlen
< xlen
)
2314 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2316 if (float_abi
== FLOAT_ABI_DEFAULT
)
2318 riscv_subset_t
*subset
;
2320 /* Assume soft-float unless D extension is present. */
2321 float_abi
= FLOAT_ABI_SOFT
;
2323 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2325 if (strcasecmp (subset
->name
, "D") == 0)
2326 float_abi
= FLOAT_ABI_DOUBLE
;
2327 if (strcasecmp (subset
->name
, "Q") == 0)
2328 float_abi
= FLOAT_ABI_QUAD
;
2333 elf_flags
|= EF_RISCV_RVE
;
2335 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2336 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2340 md_pcrel_from (fixS
*fixP
)
2342 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2345 /* Apply a fixup to the object file. */
2348 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2350 unsigned int subtype
;
2351 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2352 bfd_boolean relaxable
= FALSE
;
2356 /* Remember value for tc_gen_reloc. */
2357 fixP
->fx_addnumber
= *valP
;
2359 switch (fixP
->fx_r_type
)
2361 case BFD_RELOC_RISCV_HI20
:
2362 case BFD_RELOC_RISCV_LO12_I
:
2363 case BFD_RELOC_RISCV_LO12_S
:
2364 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2365 | bfd_getl32 (buf
), buf
);
2366 if (fixP
->fx_addsy
== NULL
)
2367 fixP
->fx_done
= TRUE
;
2371 case BFD_RELOC_RISCV_GOT_HI20
:
2372 case BFD_RELOC_RISCV_ADD8
:
2373 case BFD_RELOC_RISCV_ADD16
:
2374 case BFD_RELOC_RISCV_ADD32
:
2375 case BFD_RELOC_RISCV_ADD64
:
2376 case BFD_RELOC_RISCV_SUB6
:
2377 case BFD_RELOC_RISCV_SUB8
:
2378 case BFD_RELOC_RISCV_SUB16
:
2379 case BFD_RELOC_RISCV_SUB32
:
2380 case BFD_RELOC_RISCV_SUB64
:
2381 case BFD_RELOC_RISCV_RELAX
:
2384 case BFD_RELOC_RISCV_TPREL_HI20
:
2385 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2386 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2387 case BFD_RELOC_RISCV_TPREL_ADD
:
2391 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2392 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2393 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2394 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2395 if (fixP
->fx_addsy
!= NULL
)
2396 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2399 _("TLS relocation against a constant"));
2403 /* Use pc-relative relocation for FDE initial location.
2404 The symbol address in .eh_frame may be adjusted in
2405 _bfd_elf_discard_section_eh_frame, and the content of
2406 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2407 Therefore, we cannot insert a relocation whose addend symbol is
2408 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2409 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2410 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2411 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2412 && S_GET_VALUE (fixP
->fx_subsy
)
2413 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2415 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2416 fixP
->fx_subsy
= NULL
;
2423 case BFD_RELOC_RISCV_CFA
:
2424 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2426 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2427 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2428 fixP
->fx_next
->fx_subsy
= NULL
;
2429 fixP
->fx_next
->fx_offset
= 0;
2430 fixP
->fx_subsy
= NULL
;
2432 switch (fixP
->fx_r_type
)
2435 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2436 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2440 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2441 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2445 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2446 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2450 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2451 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2454 case BFD_RELOC_RISCV_CFA
:
2455 /* Load the byte to get the subtype. */
2456 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2457 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2460 case DW_CFA_advance_loc1
:
2461 fixP
->fx_where
= loc
+ 1;
2462 fixP
->fx_next
->fx_where
= loc
+ 1;
2463 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2464 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2467 case DW_CFA_advance_loc2
:
2469 fixP
->fx_next
->fx_size
= 2;
2470 fixP
->fx_where
= loc
+ 1;
2471 fixP
->fx_next
->fx_where
= loc
+ 1;
2472 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2473 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2476 case DW_CFA_advance_loc4
:
2478 fixP
->fx_next
->fx_size
= 4;
2479 fixP
->fx_where
= loc
;
2480 fixP
->fx_next
->fx_where
= loc
;
2481 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2482 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2486 if (subtype
< 0x80 && (subtype
& 0x40))
2488 /* DW_CFA_advance_loc */
2489 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2490 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2491 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2492 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2495 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2501 /* This case is unreachable. */
2508 /* If we are deleting this reloc entry, we must fill in the
2509 value now. This can happen if we have a .word which is not
2510 resolved when it appears but is later defined. */
2511 if (fixP
->fx_addsy
== NULL
)
2513 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2514 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2519 case BFD_RELOC_RISCV_JMP
:
2522 /* Fill in a tentative value to improve objdump readability. */
2523 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2524 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2525 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2529 case BFD_RELOC_12_PCREL
:
2532 /* Fill in a tentative value to improve objdump readability. */
2533 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2534 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2535 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2539 case BFD_RELOC_RISCV_RVC_BRANCH
:
2542 /* Fill in a tentative value to improve objdump readability. */
2543 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2544 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2545 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2549 case BFD_RELOC_RISCV_RVC_JUMP
:
2552 /* Fill in a tentative value to improve objdump readability. */
2553 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2554 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2555 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2559 case BFD_RELOC_RISCV_CALL
:
2560 case BFD_RELOC_RISCV_CALL_PLT
:
2564 case BFD_RELOC_RISCV_PCREL_HI20
:
2565 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2566 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2567 relaxable
= riscv_opts
.relax
;
2570 case BFD_RELOC_RISCV_ALIGN
:
2574 /* We ignore generic BFD relocations we don't know about. */
2575 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2576 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2579 if (fixP
->fx_subsy
!= NULL
)
2580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2581 _("unsupported symbol subtraction"));
2583 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2584 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2586 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2587 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2588 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2592 /* Because the value of .cfi_remember_state may changed after relaxation,
2593 we insert a fix to relocate it again in link-time. */
2596 riscv_pre_output_hook (void)
2598 const frchainS
*frch
;
2601 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2602 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2606 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2608 if (frag
->fr_type
== rs_cfa
)
2611 expressionS
*symval
;
2613 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2614 exp
.X_op
= O_subtract
;
2615 exp
.X_add_symbol
= symval
->X_add_symbol
;
2616 exp
.X_add_number
= 0;
2617 exp
.X_op_symbol
= symval
->X_op_symbol
;
2619 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2620 BFD_RELOC_RISCV_CFA
);
2627 /* This structure is used to hold a stack of .option values. */
2629 struct riscv_option_stack
2631 struct riscv_option_stack
*next
;
2632 struct riscv_set_options options
;
2635 static struct riscv_option_stack
*riscv_opts_stack
;
2637 /* Handle the .option pseudo-op. */
2640 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2642 char *name
= input_line_pointer
, ch
;
2644 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2645 ++input_line_pointer
;
2646 ch
= *input_line_pointer
;
2647 *input_line_pointer
= '\0';
2649 if (strcmp (name
, "rvc") == 0)
2650 riscv_set_rvc (TRUE
);
2651 else if (strcmp (name
, "norvc") == 0)
2652 riscv_set_rvc (FALSE
);
2653 else if (strcmp (name
, "pic") == 0)
2654 riscv_opts
.pic
= TRUE
;
2655 else if (strcmp (name
, "nopic") == 0)
2656 riscv_opts
.pic
= FALSE
;
2657 else if (strcmp (name
, "relax") == 0)
2658 riscv_opts
.relax
= TRUE
;
2659 else if (strcmp (name
, "norelax") == 0)
2660 riscv_opts
.relax
= FALSE
;
2661 else if (strcmp (name
, "push") == 0)
2663 struct riscv_option_stack
*s
;
2665 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2666 s
->next
= riscv_opts_stack
;
2667 s
->options
= riscv_opts
;
2668 riscv_opts_stack
= s
;
2670 else if (strcmp (name
, "pop") == 0)
2672 struct riscv_option_stack
*s
;
2674 s
= riscv_opts_stack
;
2676 as_bad (_(".option pop with no .option push"));
2679 riscv_opts
= s
->options
;
2680 riscv_opts_stack
= s
->next
;
2686 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2688 *input_line_pointer
= ch
;
2689 demand_empty_rest_of_line ();
2692 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2693 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2694 use in DWARF debug information. */
2697 s_dtprel (int bytes
)
2704 if (ex
.X_op
!= O_symbol
)
2706 as_bad (_("Unsupported use of %s"), (bytes
== 8
2709 ignore_rest_of_line ();
2712 p
= frag_more (bytes
);
2713 md_number_to_chars (p
, 0, bytes
);
2714 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2716 ? BFD_RELOC_RISCV_TLS_DTPREL64
2717 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2719 demand_empty_rest_of_line ();
2722 /* Handle the .bss pseudo-op. */
2725 s_bss (int ignore ATTRIBUTE_UNUSED
)
2727 subseg_set (bss_section
, 0);
2728 demand_empty_rest_of_line ();
2732 riscv_make_nops (char *buf
, bfd_vma bytes
)
2736 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2737 means we are not within a valid instruction sequence. It is thus safe
2738 to use a zero byte, even though that is not a valid instruction. */
2742 /* Use at most one 2-byte NOP. */
2743 if ((bytes
- i
) % 4 == 2)
2745 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2749 /* Fill the remainder with 4-byte NOPs. */
2750 for ( ; i
< bytes
; i
+= 4)
2751 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2754 /* Called from md_do_align. Used to create an alignment frag in a
2755 code section by emitting a worst-case NOP sequence that the linker
2756 will later relax to the correct number of NOPs. We can't compute
2757 the correct alignment now because of other linker relaxations. */
2760 riscv_frag_align_code (int n
)
2762 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2763 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2764 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2768 /* If we are moving to a smaller alignment than the instruction size, then no
2769 alignment is required. */
2770 if (bytes
<= insn_alignment
)
2773 /* When not relaxing, riscv_handle_align handles code alignment. */
2774 if (!riscv_opts
.relax
)
2777 nops
= frag_more (worst_case_bytes
);
2779 ex
.X_op
= O_constant
;
2780 ex
.X_add_number
= worst_case_bytes
;
2782 riscv_make_nops (nops
, worst_case_bytes
);
2784 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2785 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2790 /* Implement HANDLE_ALIGN. */
2793 riscv_handle_align (fragS
*fragP
)
2795 switch (fragP
->fr_type
)
2798 /* When relaxing, riscv_frag_align_code handles code alignment. */
2799 if (!riscv_opts
.relax
)
2801 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2802 - fragP
->fr_address
- fragP
->fr_fix
);
2803 /* We have 4 byte uncompressed nops. */
2804 bfd_signed_vma size
= 4;
2805 bfd_signed_vma excess
= bytes
% size
;
2806 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2811 /* Insert zeros or compressed nops to get 4 byte alignment. */
2814 riscv_make_nops (p
, excess
);
2815 fragP
->fr_fix
+= excess
;
2819 /* Insert variable number of 4 byte uncompressed nops. */
2820 riscv_make_nops (p
, size
);
2821 fragP
->fr_var
= size
;
2831 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2833 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2836 /* Translate internal representation of relocation info to BFD target
2840 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2842 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2844 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2845 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2846 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2847 reloc
->addend
= fixp
->fx_addnumber
;
2849 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2850 if (reloc
->howto
== NULL
)
2852 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2853 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2855 /* We don't have R_RISCV_8/16, but for this special case,
2856 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2860 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2861 _("cannot represent %s relocation in object file"),
2862 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2870 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2872 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2874 offsetT old_var
= fragp
->fr_var
;
2875 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2876 return fragp
->fr_var
- old_var
;
2882 /* Expand far branches to multi-instruction sequences. */
2885 md_convert_frag_branch (fragS
*fragp
)
2893 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2895 exp
.X_op
= O_symbol
;
2896 exp
.X_add_symbol
= fragp
->fr_symbol
;
2897 exp
.X_add_number
= fragp
->fr_offset
;
2899 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2901 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2903 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2907 /* Expand the RVC branch into a RISC-V one. */
2908 insn
= bfd_getl16 (buf
);
2909 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2910 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2912 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2913 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2914 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2915 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2916 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2917 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2920 bfd_putl32 (insn
, buf
);
2924 /* Invert the branch condition. Branch over the jump. */
2925 insn
= bfd_getl16 (buf
);
2926 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2927 insn
|= ENCODE_RVC_B_IMM (6);
2928 bfd_putl16 (insn
, buf
);
2933 /* Just keep the RVC branch. */
2934 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2935 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2936 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2937 2, &exp
, FALSE
, reloc
);
2946 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2949 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2951 /* Invert the branch condition. Branch over the jump. */
2952 insn
= bfd_getl32 (buf
);
2953 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2954 insn
|= ENCODE_SBTYPE_IMM (8);
2955 md_number_to_chars ((char *) buf
, insn
, 4);
2959 /* Jump to the target. */
2960 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2961 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2962 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2967 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2968 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2969 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2970 4, &exp
, FALSE
, reloc
);
2979 fixp
->fx_file
= fragp
->fr_file
;
2980 fixp
->fx_line
= fragp
->fr_line
;
2982 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2983 + fragp
->fr_fix
+ fragp
->fr_var
);
2985 fragp
->fr_fix
+= fragp
->fr_var
;
2988 /* Relax a machine dependent frag. This returns the amount by which
2989 the current size of the frag should change. */
2992 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2995 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2996 md_convert_frag_branch (fragp
);
3000 md_show_usage (FILE *stream
)
3002 fprintf (stream
, _("\
3004 -fpic generate position-independent code\n\
3005 -fno-pic don't generate position-independent code (default)\n\
3006 -march=ISA set the RISC-V architecture\n\
3007 -mabi=ABI set the RISC-V ABI\n\
3008 -mrelax enable relax (default)\n\
3009 -mno-relax disable relax\n\
3010 -march-attr generate RISC-V arch attribute\n\
3011 -mno-arch-attr don't generate RISC-V arch attribute\n\
3015 /* Standard calling conventions leave the CFA at SP on entry. */
3017 riscv_cfi_frame_initial_instructions (void)
3019 cfi_add_CFA_def_cfa_register (X_SP
);
3023 tc_riscv_regname_to_dw2regnum (char *regname
)
3027 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3030 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3033 as_bad (_("unknown register `%s'"), regname
);
3038 riscv_elf_final_processing (void)
3040 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3043 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3044 since these directives break relaxation when used with symbol deltas. */
3047 s_riscv_leb128 (int sign
)
3050 char *save_in
= input_line_pointer
;
3053 if (exp
.X_op
!= O_constant
)
3054 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3055 demand_empty_rest_of_line ();
3057 input_line_pointer
= save_in
;
3058 return s_leb128 (sign
);
3061 /* Parse the .insn directive. */
3064 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3066 char *str
= input_line_pointer
;
3067 struct riscv_cl_insn insn
;
3068 expressionS imm_expr
;
3069 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3072 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3073 ++input_line_pointer
;
3075 save_c
= *input_line_pointer
;
3076 *input_line_pointer
= '\0';
3078 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3079 &imm_reloc
, insn_type_hash
);
3083 as_bad ("%s `%s'", error
, str
);
3087 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3088 append_insn (&insn
, &imm_expr
, imm_reloc
);
3091 *input_line_pointer
= save_c
;
3092 demand_empty_rest_of_line ();
3095 /* Update arch attributes. */
3098 riscv_write_out_arch_attr (void)
3100 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3102 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3104 xfree ((void *)arch_str
);
3107 /* Add the default contents for the .riscv.attributes section. */
3110 riscv_set_public_attributes (void)
3112 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3113 /* Re-write arch attribute to normalize the arch string. */
3114 riscv_write_out_arch_attr ();
3117 /* Called after all assembly has been done. */
3122 riscv_set_public_attributes ();
3125 /* Given a symbolic attribute NAME, return the proper integer value.
3126 Returns -1 if the attribute is not known. */
3129 riscv_convert_symbolic_attribute (const char *name
)
3138 /* When you modify this table you should
3139 also modify the list in doc/c-riscv.texi. */
3140 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3144 T(priv_spec_revision
),
3145 T(unaligned_access
),
3155 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3156 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3157 return attribute_table
[i
].tag
;
3162 /* Parse a .attribute directive. */
3165 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3167 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3169 if (tag
== Tag_RISCV_arch
)
3171 unsigned old_xlen
= xlen
;
3173 explicit_arch_attr
= TRUE
;
3174 obj_attribute
*attr
;
3175 attr
= elf_known_obj_attributes_proc (stdoutput
);
3176 if (!start_assemble
)
3177 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3179 as_fatal (_(".attribute arch must set before any instructions"));
3181 if (old_xlen
!= xlen
)
3183 /* We must re-init bfd again if xlen is changed. */
3184 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3185 bfd_find_target (riscv_target_format (), stdoutput
);
3187 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3188 as_warn (_("Could not set architecture and machine"));
3193 /* Pseudo-op table. */
3195 static const pseudo_typeS riscv_pseudo_table
[] =
3197 /* RISC-V-specific pseudo-ops. */
3198 {"option", s_riscv_option
, 0},
3202 {"dtprelword", s_dtprel
, 4},
3203 {"dtpreldword", s_dtprel
, 8},
3205 {"uleb128", s_riscv_leb128
, 0},
3206 {"sleb128", s_riscv_leb128
, 1},
3207 {"insn", s_riscv_insn
, 0},
3208 {"attribute", s_riscv_attribute
, 0},
3214 riscv_pop_insert (void)
3216 extern void pop_insert (const pseudo_typeS
*);
3218 pop_insert (riscv_pseudo_table
);