1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
86 int csr_check
; /* Enable the CSR checking. */
89 static struct riscv_set_options riscv_opts
=
95 DEFAULT_RISCV_ATTR
, /* arch_attr */
100 riscv_set_rvc (bfd_boolean rvc_value
)
103 elf_flags
|= EF_RISCV_RVC
;
105 riscv_opts
.rvc
= rvc_value
;
109 riscv_set_rve (bfd_boolean rve_value
)
111 riscv_opts
.rve
= rve_value
;
114 static riscv_subset_list_t riscv_subsets
;
117 riscv_subset_supports (const char *feature
)
119 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
122 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
126 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
130 case INSN_CLASS_I
: return riscv_subset_supports ("i");
131 case INSN_CLASS_C
: return riscv_subset_supports ("c");
132 case INSN_CLASS_A
: return riscv_subset_supports ("a");
133 case INSN_CLASS_M
: return riscv_subset_supports ("m");
134 case INSN_CLASS_F
: return riscv_subset_supports ("f");
135 case INSN_CLASS_D
: return riscv_subset_supports ("d");
136 case INSN_CLASS_D_AND_C
:
137 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
139 case INSN_CLASS_F_AND_C
:
140 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
142 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
145 as_fatal ("Unreachable");
150 /* Set which ISA and extensions are available. */
153 riscv_set_arch (const char *s
)
155 riscv_parse_subset_t rps
;
156 rps
.subset_list
= &riscv_subsets
;
157 rps
.error_handler
= as_fatal
;
160 riscv_release_subset_list (&riscv_subsets
);
161 riscv_parse_subset (&rps
, s
);
164 /* Handle of the OPCODE hash table. */
165 static struct hash_control
*op_hash
= NULL
;
167 /* Handle of the type of .insn hash table. */
168 static struct hash_control
*insn_type_hash
= NULL
;
170 /* This array holds the chars that always start a comment. If the
171 pre-processor is disabled, these aren't very useful */
172 const char comment_chars
[] = "#";
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that C style comments are always supported. */
181 const char line_comment_chars
[] = "#";
183 /* This array holds machine specific line separator characters. */
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point nums */
187 const char EXP_CHARS
[] = "eE";
189 /* Chars that mean this number is a floating point constant */
192 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
194 /* Indicate we are already assemble any instructions or not. */
195 static bfd_boolean start_assemble
= FALSE
;
197 /* Indicate arch attribute is explictly set. */
198 static bfd_boolean explicit_arch_attr
= FALSE
;
200 /* Macros for encoding relaxation state for RVC branches and far jumps. */
201 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
204 | ((uncond) ? 1 : 0) \
207 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
208 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
209 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
210 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
212 /* Is the given value a sign-extended 32-bit value? */
213 #define IS_SEXT_32BIT_NUM(x) \
214 (((x) &~ (offsetT) 0x7fffffff) == 0 \
215 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
217 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
218 #define IS_ZEXT_32BIT_NUM(x) \
219 (((x) &~ (offsetT) 0xffffffff) == 0 \
220 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
223 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
224 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
225 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
227 /* Determine if an instruction matches an opcode. */
228 #define OPCODE_MATCHES(OPCODE, OP) \
229 (((OPCODE) & MASK_##OP) == MATCH_##OP)
231 static char *expr_end
;
233 /* The default target format to use. */
236 riscv_target_format (void)
238 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
241 /* Return the length of instruction INSN. */
243 static inline unsigned int
244 insn_length (const struct riscv_cl_insn
*insn
)
246 return riscv_insn_length (insn
->insn_opcode
);
249 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
252 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
255 insn
->insn_opcode
= mo
->match
;
261 /* Install INSN at the location specified by its "frag" and "where" fields. */
264 install_insn (const struct riscv_cl_insn
*insn
)
266 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
267 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
270 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
271 and install the opcode in the new location. */
274 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
278 if (insn
->fixp
!= NULL
)
280 insn
->fixp
->fx_frag
= frag
;
281 insn
->fixp
->fx_where
= where
;
286 /* Add INSN to the end of the output. */
289 add_fixed_insn (struct riscv_cl_insn
*insn
)
291 char *f
= frag_more (insn_length (insn
));
292 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
296 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
297 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
299 frag_grow (max_chars
);
300 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
301 frag_var (rs_machine_dependent
, max_chars
, var
,
302 subtype
, symbol
, offset
, NULL
);
305 /* Compute the length of a branch sequence, and adjust the stored length
306 accordingly. If FRAGP is NULL, the worst-case length is returned. */
309 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
311 int jump
, rvc
, length
= 8;
316 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
317 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
318 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
320 /* Assume jumps are in range; the linker will catch any that aren't. */
321 length
= jump
? 4 : 8;
323 if (fragp
->fr_symbol
!= NULL
324 && S_IS_DEFINED (fragp
->fr_symbol
)
325 && !S_IS_WEAK (fragp
->fr_symbol
)
326 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
328 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
329 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
330 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
332 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
334 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
336 else if (!jump
&& rvc
)
341 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
346 /* Information about an opcode name, mnemonics and its value. */
353 /* List for all supported opcode name. */
354 static const struct opcode_name_t opcode_name_list
[] =
399 /* Hash table for lookup opcode name. */
400 static struct hash_control
*opcode_names_hash
= NULL
;
402 /* Initialization for hash table of opcode name. */
404 init_opcode_names_hash (void)
407 const struct opcode_name_t
*opcode
;
409 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
411 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
414 as_fatal (_("internal error: can't hash `%s': %s"),
415 opcode
->name
, retval
);
419 /* Find `s` is a valid opcode name or not,
420 return the opcode name info if found. */
421 static const struct opcode_name_t
*
422 opcode_name_lookup (char **s
)
426 struct opcode_name_t
*o
;
428 /* Find end of name. */
430 if (is_name_beginner (*e
))
432 while (is_part_of_name (*e
))
435 /* Terminate name. */
439 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
441 /* Advance to next token if one was recognized. */
459 static struct hash_control
*reg_names_hash
= NULL
;
460 static struct hash_control
*csr_extra_hash
= NULL
;
462 #define ENCODE_REG_HASH(cls, n) \
463 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
464 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
465 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
468 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
470 void *hash
= ENCODE_REG_HASH (class, n
);
471 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
474 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
478 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
482 for (i
= 0; i
< n
; i
++)
483 hash_reg_name (class, names
[i
], i
);
486 /* All RISC-V CSRs belong to one of these classes. */
493 CSR_CLASS_I_32
, /* rv32 only */
494 CSR_CLASS_F
, /* f-ext only */
497 /* This structure holds all restricted conditions for a CSR. */
499 struct riscv_csr_extra
501 /* Class to which this CSR belongs. Used to decide whether or
502 not this CSR is legal in the current -march context. */
503 enum riscv_csr_class csr_class
;
506 /* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
509 riscv_init_csr_hashes (const char *name
,
511 enum riscv_csr_class
class)
513 struct riscv_csr_extra
*entry
= XNEW (struct riscv_csr_extra
);
514 entry
->csr_class
= class;
516 const char *hash_error
=
517 hash_insert (csr_extra_hash
, name
, (void *) entry
);
518 if (hash_error
!= NULL
)
520 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
522 /* Probably a memory allocation problem? Give up now. */
523 as_fatal (_("Broken assembler. No assembly attempted."));
526 hash_reg_name (RCLASS_CSR
, name
, address
);
529 /* Check wether the CSR is valid according to the ISA. */
532 riscv_csr_class_check (enum riscv_csr_class csr_class
)
536 case CSR_CLASS_I
: return riscv_subset_supports ("i");
537 case CSR_CLASS_F
: return riscv_subset_supports ("f");
539 return (xlen
== 32 && riscv_subset_supports ("i"));
546 /* If the CSR is defined, then we call `riscv_csr_class_check` to do the
547 further checking. Return FALSE if the CSR is not defined. Otherwise,
551 reg_csr_lookup_internal (const char *s
)
553 struct riscv_csr_extra
*r
=
554 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
559 /* We just report the warning when the CSR is invalid. */
560 if (!riscv_csr_class_check (r
->csr_class
))
561 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
567 reg_lookup_internal (const char *s
, enum reg_class
class)
569 void *r
= hash_find (reg_names_hash
, s
);
571 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
574 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
577 if (class == RCLASS_CSR
578 && riscv_opts
.csr_check
579 && !reg_csr_lookup_internal (s
))
582 return DECODE_REG_NUM (r
);
586 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
592 /* Find end of name. */
594 if (is_name_beginner (*e
))
596 while (is_part_of_name (*e
))
599 /* Terminate name. */
603 /* Look for the register. Advance to next token if one was recognized. */
604 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
614 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
616 const char *p
= strchr (*s
, ',');
617 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
622 for (i
= 0; i
< size
; i
++)
623 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
633 /* For consistency checking, verify that all bits are specified either
634 by the match/mask part of the instruction definition, or by the
637 `length` could be 0, 4 or 8, 0 for auto detection. */
639 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
641 const char *p
= opc
->args
;
643 insn_t used_bits
= opc
->mask
;
645 insn_t required_bits
;
648 insn_width
= 8 * riscv_insn_length (opc
->match
);
650 insn_width
= 8 * length
;
652 required_bits
= ~0ULL >> (64 - insn_width
);
654 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
656 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
657 opc
->name
, opc
->args
);
661 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
668 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
669 case 'c': break; /* RS1, constrained to equal sp */
670 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
671 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
672 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
673 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
674 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
675 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
676 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
677 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
678 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
679 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
680 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
681 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
682 case 'w': break; /* RS1S, constrained to equal RD */
683 case 'x': break; /* RS2S, constrained to equal RD */
684 case 'z': break; /* RS2S, contrained to be x0 */
685 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
686 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
687 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
688 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
689 case 'U': break; /* RS1, constrained to equal RD */
690 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
691 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
692 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
693 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
694 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
695 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
696 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
697 case 'F': /* funct */
700 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
701 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
702 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
703 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
705 as_bad (_("internal: bad RISC-V opcode"
706 " (unknown operand type `CF%c'): %s %s"),
707 c
, opc
->name
, opc
->args
);
712 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
713 c
, opc
->name
, opc
->args
);
720 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
721 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
723 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
724 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
725 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
727 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
728 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
729 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
730 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
731 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
732 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
733 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
734 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
735 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
736 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
737 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
739 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
740 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
741 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
742 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
743 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
749 case 'F': /* funct */
752 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
753 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
754 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
756 as_bad (_("internal: bad RISC-V opcode"
757 " (unknown operand type `F%c'): %s %s"),
758 c
, opc
->name
, opc
->args
);
762 case 'O': /* opcode */
765 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
766 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
768 as_bad (_("internal: bad RISC-V opcode"
769 " (unknown operand type `F%c'): %s %s"),
770 c
, opc
->name
, opc
->args
);
775 as_bad (_("internal: bad RISC-V opcode "
776 "(unknown operand type `%c'): %s %s"),
777 c
, opc
->name
, opc
->args
);
781 if (used_bits
!= required_bits
)
783 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
784 ~(unsigned long)(used_bits
& required_bits
),
785 opc
->name
, opc
->args
);
791 struct percent_op_match
794 bfd_reloc_code_real_type reloc
;
797 /* Common hash table initialization function for
798 instruction and .insn directive. */
799 static struct hash_control
*
800 init_opcode_hash (const struct riscv_opcode
*opcodes
,
801 bfd_boolean insn_directive_p
)
805 struct hash_control
*hash
= hash_new ();
806 while (opcodes
[i
].name
)
808 const char *name
= opcodes
[i
].name
;
809 const char *hash_error
=
810 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
812 if (hash_error
!= NULL
)
814 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
815 opcodes
[i
].name
, hash_error
);
816 /* Probably a memory allocation problem? Give up now. */
817 as_fatal (_("Broken assembler. No assembly attempted."));
822 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
824 if (insn_directive_p
)
825 length
= ((name
[0] == 'c') ? 2 : 4);
827 length
= 0; /* Let assembler determine the length. */
828 if (!validate_riscv_insn (&opcodes
[i
], length
))
829 as_fatal (_("Broken assembler. No assembly attempted."));
832 gas_assert (!insn_directive_p
);
835 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
841 /* This function is called once, at assembler startup time. It should set up
842 all the tables, etc. that the MD part of the assembler will need. */
847 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
849 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
850 as_warn (_("Could not set architecture and machine"));
852 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
853 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
855 reg_names_hash
= hash_new ();
856 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
857 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
858 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
859 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
860 /* Add "fp" as an alias for "s0". */
861 hash_reg_name (RCLASS_GPR
, "fp", 8);
863 /* Create and insert CSR hash tables. */
864 csr_extra_hash
= hash_new ();
865 #define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
866 #define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
867 #include "opcode/riscv-opc.h"
870 opcode_names_hash
= hash_new ();
871 init_opcode_names_hash ();
873 /* Set the default alignment for the text section. */
874 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
878 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
885 case BFD_RELOC_RISCV_HI20
:
886 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
888 case BFD_RELOC_RISCV_LO12_S
:
889 return ENCODE_STYPE_IMM (value
);
891 case BFD_RELOC_RISCV_LO12_I
:
892 return ENCODE_ITYPE_IMM (value
);
899 /* Output an instruction. IP is the instruction information.
900 ADDRESS_EXPR is an operand of the instruction to be used with
904 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
905 bfd_reloc_code_real_type reloc_type
)
907 dwarf2_emit_insn (0);
909 if (reloc_type
!= BFD_RELOC_UNUSED
)
911 reloc_howto_type
*howto
;
913 gas_assert (address_expr
);
914 if (reloc_type
== BFD_RELOC_12_PCREL
915 || reloc_type
== BFD_RELOC_RISCV_JMP
)
917 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
918 int best_case
= riscv_insn_length (ip
->insn_opcode
);
919 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
920 add_relaxed_insn (ip
, worst_case
, best_case
,
921 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
922 address_expr
->X_add_symbol
,
923 address_expr
->X_add_number
);
928 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
930 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
932 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
933 bfd_get_reloc_size (howto
),
934 address_expr
, FALSE
, reloc_type
);
936 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
943 /* We need to start a new frag after any instruction that can be
944 optimized away or compressed by the linker during relaxation, to prevent
945 the assembler from computing static offsets across such an instruction.
946 This is necessary to get correct EH info. */
947 if (reloc_type
== BFD_RELOC_RISCV_CALL
948 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
949 || reloc_type
== BFD_RELOC_RISCV_HI20
950 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
951 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
952 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
954 frag_wane (frag_now
);
959 /* Build an instruction created by a macro expansion. This is passed
960 a pointer to the count of instructions created so far, an
961 expression, the name of the instruction to build, an operand format
962 string, and corresponding arguments. */
965 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
967 const struct riscv_opcode
*mo
;
968 struct riscv_cl_insn insn
;
969 bfd_reloc_code_real_type r
;
972 va_start (args
, fmt
);
974 r
= BFD_RELOC_UNUSED
;
975 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
978 /* Find a non-RVC variant of the instruction. append_insn will compress
980 while (riscv_insn_length (mo
->match
) < 4)
982 gas_assert (strcmp (name
, mo
->name
) == 0);
984 create_insn (&insn
, mo
);
990 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
994 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
998 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1002 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1008 gas_assert (ep
!= NULL
);
1009 r
= va_arg (args
, int);
1017 as_fatal (_("internal error: invalid macro"));
1022 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1024 append_insn (&insn
, ep
, r
);
1027 /* Build an instruction created by a macro expansion. Like md_assemble but
1028 accept a printf-style format string and arguments. */
1031 md_assemblef (const char *format
, ...)
1037 va_start (ap
, format
);
1039 r
= vasprintf (&buf
, format
, ap
);
1042 as_fatal (_("internal error: vasprintf failed"));
1050 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1053 normalize_constant_expr (expressionS
*ex
)
1057 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1058 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1059 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1063 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1064 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1067 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1068 bfd_boolean maybe_csr
)
1070 if (ex
->X_op
== O_big
)
1071 as_bad (_("unsupported large constant"));
1072 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1073 as_bad (_("unknown CSR `%s'"),
1074 S_GET_NAME (ex
->X_add_symbol
));
1075 else if (ex
->X_op
!= O_constant
)
1076 as_bad (_("Instruction %s requires absolute expression"),
1078 normalize_constant_expr (ex
);
1082 make_internal_label (void)
1084 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1085 (valueT
) frag_now_fix (), frag_now
);
1088 /* Load an entry from the GOT. */
1090 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1091 const char *lo_insn
, const char *lo_pattern
,
1092 bfd_reloc_code_real_type hi_reloc
,
1093 bfd_reloc_code_real_type lo_reloc
)
1096 ep2
.X_op
= O_symbol
;
1097 ep2
.X_add_symbol
= make_internal_label ();
1098 ep2
.X_add_number
= 0;
1100 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1101 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1105 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1106 bfd_reloc_code_real_type hi_reloc
,
1107 bfd_reloc_code_real_type lo_reloc
)
1109 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1113 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1114 bfd_reloc_code_real_type hi_reloc
,
1115 bfd_reloc_code_real_type lo_reloc
)
1117 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1120 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1122 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1123 bfd_reloc_code_real_type reloc
)
1125 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1126 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1129 /* Load an integer constant into a register. */
1132 load_const (int reg
, expressionS
*ep
)
1134 int shift
= RISCV_IMM_BITS
;
1135 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1136 expressionS upper
= *ep
, lower
= *ep
;
1137 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1138 upper
.X_add_number
-= lower
.X_add_number
;
1140 if (ep
->X_op
!= O_constant
)
1142 as_bad (_("unsupported large constant"));
1146 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1148 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1149 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1152 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1153 load_const (reg
, &upper
);
1155 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1156 if (lower
.X_add_number
!= 0)
1157 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1158 lower
.X_add_number
);
1162 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1165 if (upper
.X_add_number
!= 0)
1167 /* Discard low part and zero-extend upper immediate. */
1168 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1170 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1174 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1175 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1176 lower
.X_add_number
);
1180 /* Expand RISC-V assembly macros into one or more instructions. */
1182 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1183 bfd_reloc_code_real_type
*imm_reloc
)
1185 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1186 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1187 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1188 int mask
= ip
->insn_mo
->mask
;
1193 load_const (rd
, imm_expr
);
1198 /* Load the address of a symbol into a register. */
1199 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1200 as_bad (_("offset too large"));
1202 if (imm_expr
->X_op
== O_constant
)
1203 load_const (rd
, imm_expr
);
1204 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1205 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1206 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1207 else /* Local PIC symbol, or any non-PIC symbol */
1208 pcrel_load (rd
, rd
, imm_expr
, "addi",
1209 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1213 pcrel_load (rd
, rd
, imm_expr
, "addi",
1214 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1218 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1219 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1223 pcrel_load (rd
, rd
, imm_expr
, "lb",
1224 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1228 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1229 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1233 pcrel_load (rd
, rd
, imm_expr
, "lh",
1234 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1238 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1239 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1243 pcrel_load (rd
, rd
, imm_expr
, "lw",
1244 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1248 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1249 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1253 pcrel_load (rd
, rd
, imm_expr
, "ld",
1254 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1258 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1259 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1263 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1264 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1268 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1269 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1273 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1274 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1278 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1279 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1283 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1284 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1288 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1289 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1293 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1294 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1298 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1302 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1307 static const struct percent_op_match percent_op_utype
[] =
1309 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1310 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1311 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1312 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1313 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1314 {"%hi", BFD_RELOC_RISCV_HI20
},
1318 static const struct percent_op_match percent_op_itype
[] =
1320 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1321 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1322 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1326 static const struct percent_op_match percent_op_stype
[] =
1328 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1329 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1330 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1334 static const struct percent_op_match percent_op_rtype
[] =
1336 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1340 static const struct percent_op_match percent_op_null
[] =
1345 /* Return true if *STR points to a relocation operator. When returning true,
1346 move *STR over the operator and store its relocation code in *RELOC.
1347 Leave both *STR and *RELOC alone when returning false. */
1350 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1351 const struct percent_op_match
*percent_op
)
1353 for ( ; percent_op
->str
; percent_op
++)
1354 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1356 int len
= strlen (percent_op
->str
);
1358 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1361 *str
+= strlen (percent_op
->str
);
1362 *reloc
= percent_op
->reloc
;
1364 /* Check whether the output BFD supports this relocation.
1365 If not, issue an error and fall back on something safe. */
1366 if (*reloc
!= BFD_RELOC_UNUSED
1367 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1369 as_bad ("relocation %s isn't supported by the current ABI",
1371 *reloc
= BFD_RELOC_UNUSED
;
1379 my_getExpression (expressionS
*ep
, char *str
)
1383 save_in
= input_line_pointer
;
1384 input_line_pointer
= str
;
1386 expr_end
= input_line_pointer
;
1387 input_line_pointer
= save_in
;
1390 /* Parse string STR as a 16-bit relocatable operand. Store the
1391 expression in *EP and the relocation, if any, in RELOC.
1392 Return the number of relocation operators used (0 or 1).
1394 On exit, EXPR_END points to the first character after the expression. */
1397 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1398 char *str
, const struct percent_op_match
*percent_op
)
1401 unsigned crux_depth
, str_depth
, regno
;
1404 /* First, check for integer registers. No callers can accept a reg, but
1405 we need to avoid accidentally creating a useless undefined symbol below,
1406 if this is an instruction pattern that can't match. A glibc build fails
1407 if this is removed. */
1408 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1410 ep
->X_op
= O_register
;
1411 ep
->X_add_number
= regno
;
1416 /* Search for the start of the main expression.
1417 End the loop with CRUX pointing to the start
1418 of the main expression and with CRUX_DEPTH containing the number
1419 of open brackets at that point. */
1426 crux_depth
= str_depth
;
1428 /* Skip over whitespace and brackets, keeping count of the number
1430 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1436 && parse_relocation (&str
, reloc
, percent_op
));
1438 my_getExpression (ep
, crux
);
1441 /* Match every open bracket. */
1442 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1447 as_bad ("unclosed '('");
1454 /* Parse opcode name, could be an mnemonics or number. */
1456 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1457 char *str
, const struct percent_op_match
*percent_op
)
1459 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1463 ep
->X_op
= O_constant
;
1464 ep
->X_add_number
= o
->val
;
1468 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1471 /* Detect and handle implicitly zero load-store offsets. For example,
1472 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1473 an implicit offset was detected. */
1476 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1478 /* Check whether there is only a single bracketed expression left.
1479 If so, it must be the base register and the constant must be zero. */
1480 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1482 ep
->X_op
= O_constant
;
1483 ep
->X_add_number
= 0;
1490 /* All RISC-V CSR instructions belong to one of these classes. */
1500 /* Return which CSR instruction is checking. */
1502 static enum csr_insn_type
1503 riscv_csr_insn_type (insn_t insn
)
1505 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1506 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1508 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1509 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1511 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1512 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1515 return INSN_NOT_CSR
;
1518 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1519 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1520 CSR address is 0x3. */
1523 riscv_csr_read_only_check (insn_t insn
)
1525 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1526 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1527 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1528 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1531 && (((csr_insn
== INSN_CSRRS
1532 || csr_insn
== INSN_CSRRC
)
1534 || csr_insn
== INSN_CSRRW
))
1540 /* This routine assembles an instruction into its binary format. As a
1541 side effect, it sets the global variable imm_reloc to the type of
1542 relocation to do if one of the operands is an address expression. */
1545 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1546 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1551 struct riscv_opcode
*insn
;
1556 const struct percent_op_match
*p
;
1557 const char *error
= "unrecognized opcode";
1558 /* Indicate we are assembling instruction with CSR. */
1559 bfd_boolean insn_with_csr
= FALSE
;
1561 /* Parse the name of the instruction. Terminate the string if whitespace
1562 is found so that hash_find only sees the name part of the string. */
1563 for (s
= str
; *s
!= '\0'; ++s
)
1571 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1574 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1576 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1579 if (!riscv_multi_subset_supports (insn
->insn_class
))
1582 create_insn (ip
, insn
);
1585 imm_expr
->X_op
= O_absent
;
1586 *imm_reloc
= BFD_RELOC_UNUSED
;
1587 p
= percent_op_itype
;
1589 for (args
= insn
->args
;; ++args
)
1591 s
+= strspn (s
, " \t");
1594 case '\0': /* End of args. */
1595 if (insn
->pinfo
!= INSN_MACRO
)
1597 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1600 /* For .insn, insn->match and insn->mask are 0. */
1601 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1607 /* Check if we write a read-only CSR by the CSR
1610 && riscv_opts
.csr_check
1611 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1613 /* Restore the character in advance, since we want to
1614 report the detailed warning message here. */
1616 *(argsStart
- 1) = save_c
;
1617 as_warn (_("Read-only CSR is written `%s'"), str
);
1618 insn_with_csr
= FALSE
;
1623 /* Successful assembly. */
1625 insn_with_csr
= FALSE
;
1631 case 's': /* RS1 x8-x15 */
1632 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1633 || !(regno
>= 8 && regno
<= 15))
1635 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1637 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1638 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1639 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1642 case 't': /* RS2 x8-x15 */
1643 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1644 || !(regno
>= 8 && regno
<= 15))
1646 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1648 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1649 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1650 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1653 case 'U': /* RS1, constrained to equal RD. */
1654 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1655 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1659 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1661 INSERT_OPERAND (CRS2
, *ip
, regno
);
1663 case 'c': /* RS1, constrained to equal sp. */
1664 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1668 case 'z': /* RS2, contrained to equal x0. */
1669 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1674 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1675 || imm_expr
->X_op
!= O_constant
1676 || imm_expr
->X_add_number
<= 0
1677 || imm_expr
->X_add_number
>= 64)
1679 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1682 imm_expr
->X_op
= O_absent
;
1685 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1686 || imm_expr
->X_op
!= O_constant
1687 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1688 || imm_expr
->X_add_number
<= 0
1689 || imm_expr
->X_add_number
>= 32)
1691 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1694 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1695 || imm_expr
->X_op
!= O_constant
1696 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1697 || imm_expr
->X_add_number
< 0
1698 || imm_expr
->X_add_number
>= 256)
1700 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1703 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1704 || imm_expr
->X_op
!= O_constant
1705 || imm_expr
->X_add_number
== 0
1706 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1708 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1711 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1712 || imm_expr
->X_op
!= O_constant
1713 || imm_expr
->X_add_number
== 0
1714 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1716 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1719 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1721 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1722 || imm_expr
->X_op
!= O_constant
1723 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1725 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1728 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1730 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1731 || imm_expr
->X_op
!= O_constant
1732 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1734 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1737 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1739 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1740 || imm_expr
->X_op
!= O_constant
1741 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1744 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1747 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1749 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1750 || imm_expr
->X_op
!= O_constant
1751 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1754 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1757 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1758 || imm_expr
->X_op
!= O_constant
1759 /* C.addiw, c.li, and c.andi allow zero immediate.
1760 C.addi allows zero immediate as hint. Otherwise this
1762 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1764 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1767 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1768 || imm_expr
->X_op
!= O_constant
1769 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1770 || imm_expr
->X_add_number
== 0)
1773 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1776 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1777 || imm_expr
->X_op
!= O_constant
1778 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1779 || imm_expr
->X_add_number
== 0)
1782 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1785 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1787 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1788 || imm_expr
->X_op
!= O_constant
1789 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1792 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1795 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1797 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1798 || imm_expr
->X_op
!= O_constant
1799 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1802 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1805 p
= percent_op_utype
;
1806 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1809 if (imm_expr
->X_op
!= O_constant
1810 || imm_expr
->X_add_number
<= 0
1811 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1812 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1813 && (imm_expr
->X_add_number
<
1814 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1816 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1819 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1820 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1821 || ((int32_t)imm_expr
->X_add_number
1822 != imm_expr
->X_add_number
))
1824 imm_expr
->X_add_number
=
1825 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1831 case 'S': /* Floating-point RS1 x8-x15. */
1832 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1833 || !(regno
>= 8 && regno
<= 15))
1835 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1837 case 'D': /* Floating-point RS2 x8-x15. */
1838 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1839 || !(regno
>= 8 && regno
<= 15))
1841 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1843 case 'T': /* Floating-point RS2. */
1844 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1846 INSERT_OPERAND (CRS2
, *ip
, regno
);
1852 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1853 || imm_expr
->X_op
!= O_constant
1854 || imm_expr
->X_add_number
< 0
1855 || imm_expr
->X_add_number
>= 64)
1857 as_bad (_("bad value for funct6 field, "
1858 "value must be 0...64"));
1862 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1863 imm_expr
->X_op
= O_absent
;
1867 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1868 || imm_expr
->X_op
!= O_constant
1869 || imm_expr
->X_add_number
< 0
1870 || imm_expr
->X_add_number
>= 16)
1872 as_bad (_("bad value for funct4 field, "
1873 "value must be 0...15"));
1877 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1878 imm_expr
->X_op
= O_absent
;
1882 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1883 || imm_expr
->X_op
!= O_constant
1884 || imm_expr
->X_add_number
< 0
1885 || imm_expr
->X_add_number
>= 8)
1887 as_bad (_("bad value for funct3 field, "
1888 "value must be 0...7"));
1891 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1892 imm_expr
->X_op
= O_absent
;
1896 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1897 || imm_expr
->X_op
!= O_constant
1898 || imm_expr
->X_add_number
< 0
1899 || imm_expr
->X_add_number
>= 4)
1901 as_bad (_("bad value for funct2 field, "
1902 "value must be 0...3"));
1905 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1906 imm_expr
->X_op
= O_absent
;
1910 as_bad (_("bad compressed FUNCT field"
1911 " specifier 'CF%c'\n"),
1917 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1936 case '<': /* Shift amount, 0 - 31. */
1937 my_getExpression (imm_expr
, s
);
1938 check_absolute_expr (ip
, imm_expr
, FALSE
);
1939 if ((unsigned long) imm_expr
->X_add_number
> 31)
1940 as_bad (_("Improper shift amount (%lu)"),
1941 (unsigned long) imm_expr
->X_add_number
);
1942 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1943 imm_expr
->X_op
= O_absent
;
1947 case '>': /* Shift amount, 0 - (XLEN-1). */
1948 my_getExpression (imm_expr
, s
);
1949 check_absolute_expr (ip
, imm_expr
, FALSE
);
1950 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1951 as_bad (_("Improper shift amount (%lu)"),
1952 (unsigned long) imm_expr
->X_add_number
);
1953 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1954 imm_expr
->X_op
= O_absent
;
1958 case 'Z': /* CSRRxI immediate. */
1959 my_getExpression (imm_expr
, s
);
1960 check_absolute_expr (ip
, imm_expr
, FALSE
);
1961 if ((unsigned long) imm_expr
->X_add_number
> 31)
1962 as_bad (_("Improper CSRxI immediate (%lu)"),
1963 (unsigned long) imm_expr
->X_add_number
);
1964 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1965 imm_expr
->X_op
= O_absent
;
1969 case 'E': /* Control register. */
1970 insn_with_csr
= TRUE
;
1971 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1972 INSERT_OPERAND (CSR
, *ip
, regno
);
1975 my_getExpression (imm_expr
, s
);
1976 check_absolute_expr (ip
, imm_expr
, TRUE
);
1977 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1978 as_bad (_("Improper CSR address (%lu)"),
1979 (unsigned long) imm_expr
->X_add_number
);
1980 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1981 imm_expr
->X_op
= O_absent
;
1986 case 'm': /* Rounding mode. */
1987 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1989 INSERT_OPERAND (RM
, *ip
, regno
);
1995 case 'Q': /* Fence predecessor/successor. */
1996 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2000 INSERT_OPERAND (PRED
, *ip
, regno
);
2002 INSERT_OPERAND (SUCC
, *ip
, regno
);
2007 case 'd': /* Destination register. */
2008 case 's': /* Source register. */
2009 case 't': /* Target register. */
2010 case 'r': /* rs3. */
2011 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2017 /* Now that we have assembled one operand, we use the args
2018 string to figure out where it goes in the instruction. */
2022 INSERT_OPERAND (RS1
, *ip
, regno
);
2025 INSERT_OPERAND (RD
, *ip
, regno
);
2028 INSERT_OPERAND (RS2
, *ip
, regno
);
2031 INSERT_OPERAND (RS3
, *ip
, regno
);
2038 case 'D': /* Floating point rd. */
2039 case 'S': /* Floating point rs1. */
2040 case 'T': /* Floating point rs2. */
2041 case 'U': /* Floating point rs1 and rs2. */
2042 case 'R': /* Floating point rs3. */
2043 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2051 INSERT_OPERAND (RD
, *ip
, regno
);
2054 INSERT_OPERAND (RS1
, *ip
, regno
);
2057 INSERT_OPERAND (RS1
, *ip
, regno
);
2060 INSERT_OPERAND (RS2
, *ip
, regno
);
2063 INSERT_OPERAND (RS3
, *ip
, regno
);
2072 my_getExpression (imm_expr
, s
);
2073 if (imm_expr
->X_op
!= O_big
2074 && imm_expr
->X_op
!= O_constant
)
2076 normalize_constant_expr (imm_expr
);
2081 my_getExpression (imm_expr
, s
);
2082 normalize_constant_expr (imm_expr
);
2083 /* The 'A' format specifier must be a symbol. */
2084 if (imm_expr
->X_op
!= O_symbol
)
2086 *imm_reloc
= BFD_RELOC_32
;
2091 my_getExpression (imm_expr
, s
);
2092 normalize_constant_expr (imm_expr
);
2093 /* The 'B' format specifier must be a symbol or a constant. */
2094 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2096 if (imm_expr
->X_op
== O_symbol
)
2097 *imm_reloc
= BFD_RELOC_32
;
2101 case 'j': /* Sign-extended immediate. */
2102 p
= percent_op_itype
;
2103 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2105 case 'q': /* Store displacement. */
2106 p
= percent_op_stype
;
2107 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2109 case 'o': /* Load displacement. */
2110 p
= percent_op_itype
;
2111 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2113 case '1': /* 4-operand add, must be %tprel_add. */
2114 p
= percent_op_rtype
;
2116 case '0': /* AMO "displacement," which must be zero. */
2117 p
= percent_op_null
;
2119 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2122 /* If this value won't fit into a 16 bit offset, then go
2123 find a macro that will generate the 32 bit offset
2125 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2127 normalize_constant_expr (imm_expr
);
2128 if (imm_expr
->X_op
!= O_constant
2129 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2131 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2132 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2139 case 'p': /* PC-relative offset. */
2141 *imm_reloc
= BFD_RELOC_12_PCREL
;
2142 my_getExpression (imm_expr
, s
);
2146 case 'u': /* Upper 20 bits. */
2147 p
= percent_op_utype
;
2148 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2150 if (imm_expr
->X_op
!= O_constant
)
2153 if (imm_expr
->X_add_number
< 0
2154 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2155 as_bad (_("lui expression not in range 0..1048575"));
2157 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2158 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2163 case 'a': /* 20-bit PC-relative offset. */
2165 my_getExpression (imm_expr
, s
);
2167 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2171 my_getExpression (imm_expr
, s
);
2173 if (strcmp (s
, "@plt") == 0)
2175 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2179 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2185 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2186 || imm_expr
->X_op
!= O_constant
2187 || imm_expr
->X_add_number
< 0
2188 || imm_expr
->X_add_number
>= 128
2189 || (imm_expr
->X_add_number
& 0x3) != 3)
2191 as_bad (_("bad value for opcode field, "
2192 "value must be 0...127 and "
2193 "lower 2 bits must be 0x3"));
2197 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2198 imm_expr
->X_op
= O_absent
;
2202 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2203 || imm_expr
->X_op
!= O_constant
2204 || imm_expr
->X_add_number
< 0
2205 || imm_expr
->X_add_number
>= 3)
2207 as_bad (_("bad value for opcode field, "
2208 "value must be 0...2"));
2212 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2213 imm_expr
->X_op
= O_absent
;
2217 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2225 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2226 || imm_expr
->X_op
!= O_constant
2227 || imm_expr
->X_add_number
< 0
2228 || imm_expr
->X_add_number
>= 128)
2230 as_bad (_("bad value for funct7 field, "
2231 "value must be 0...127"));
2235 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2236 imm_expr
->X_op
= O_absent
;
2240 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2241 || imm_expr
->X_op
!= O_constant
2242 || imm_expr
->X_add_number
< 0
2243 || imm_expr
->X_add_number
>= 8)
2245 as_bad (_("bad value for funct3 field, "
2246 "value must be 0...7"));
2250 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2251 imm_expr
->X_op
= O_absent
;
2255 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2256 || imm_expr
->X_op
!= O_constant
2257 || imm_expr
->X_add_number
< 0
2258 || imm_expr
->X_add_number
>= 4)
2260 as_bad (_("bad value for funct2 field, "
2261 "value must be 0...3"));
2265 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2266 imm_expr
->X_op
= O_absent
;
2271 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2276 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2277 || imm_expr
->X_op
!= O_constant
2278 || imm_expr
->X_add_number
!= 0)
2281 imm_expr
->X_op
= O_absent
;
2285 as_fatal (_("internal error: bad argument type %c"), *args
);
2290 error
= _("illegal operands");
2291 insn_with_csr
= FALSE
;
2295 /* Restore the character we might have clobbered above. */
2297 *(argsStart
- 1) = save_c
;
2303 md_assemble (char *str
)
2305 struct riscv_cl_insn insn
;
2306 expressionS imm_expr
;
2307 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2309 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2311 start_assemble
= TRUE
;
2315 as_bad ("%s `%s'", error
, str
);
2319 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2320 macro (&insn
, &imm_expr
, &imm_reloc
);
2322 append_insn (&insn
, &imm_expr
, imm_reloc
);
2326 md_atof (int type
, char *litP
, int *sizeP
)
2328 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2332 md_number_to_chars (char *buf
, valueT val
, int n
)
2334 number_to_chars_littleendian (buf
, val
, n
);
2337 const char *md_shortopts
= "O::g::G:";
2341 OPTION_MARCH
= OPTION_MD_BASE
,
2348 OPTION_NO_ARCH_ATTR
,
2350 OPTION_NO_CSR_CHECK
,
2354 struct option md_longopts
[] =
2356 {"march", required_argument
, NULL
, OPTION_MARCH
},
2357 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2358 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2359 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2360 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2361 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2362 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2363 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2364 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2365 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2366 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2368 {NULL
, no_argument
, NULL
, 0}
2370 size_t md_longopts_size
= sizeof (md_longopts
);
2373 FLOAT_ABI_DEFAULT
= -1,
2379 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2382 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2384 abi_xlen
= new_xlen
;
2385 float_abi
= new_float_abi
;
2390 md_parse_option (int c
, const char *arg
)
2395 riscv_set_arch (arg
);
2399 riscv_opts
.pic
= FALSE
;
2403 riscv_opts
.pic
= TRUE
;
2407 if (strcmp (arg
, "ilp32") == 0)
2408 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2409 else if (strcmp (arg
, "ilp32e") == 0)
2410 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2411 else if (strcmp (arg
, "ilp32f") == 0)
2412 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2413 else if (strcmp (arg
, "ilp32d") == 0)
2414 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2415 else if (strcmp (arg
, "ilp32q") == 0)
2416 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2417 else if (strcmp (arg
, "lp64") == 0)
2418 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2419 else if (strcmp (arg
, "lp64f") == 0)
2420 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2421 else if (strcmp (arg
, "lp64d") == 0)
2422 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2423 else if (strcmp (arg
, "lp64q") == 0)
2424 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2430 riscv_opts
.relax
= TRUE
;
2433 case OPTION_NO_RELAX
:
2434 riscv_opts
.relax
= FALSE
;
2437 case OPTION_ARCH_ATTR
:
2438 riscv_opts
.arch_attr
= TRUE
;
2441 case OPTION_NO_ARCH_ATTR
:
2442 riscv_opts
.arch_attr
= FALSE
;
2445 case OPTION_CSR_CHECK
:
2446 riscv_opts
.csr_check
= TRUE
;
2449 case OPTION_NO_CSR_CHECK
:
2450 riscv_opts
.csr_check
= FALSE
;
2461 riscv_after_parse_args (void)
2465 if (strcmp (default_arch
, "riscv32") == 0)
2467 else if (strcmp (default_arch
, "riscv64") == 0)
2470 as_bad ("unknown default architecture `%s'", default_arch
);
2473 if (riscv_subsets
.head
== NULL
)
2474 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2476 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2477 riscv_set_rvc (FALSE
);
2478 if (riscv_subset_supports ("c"))
2479 riscv_set_rvc (TRUE
);
2481 /* Enable RVE if specified by the -march option. */
2482 riscv_set_rve (FALSE
);
2483 if (riscv_subset_supports ("e"))
2484 riscv_set_rve (TRUE
);
2486 /* Infer ABI from ISA if not specified on command line. */
2489 else if (abi_xlen
> xlen
)
2490 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2491 else if (abi_xlen
< xlen
)
2492 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2494 if (float_abi
== FLOAT_ABI_DEFAULT
)
2496 riscv_subset_t
*subset
;
2498 /* Assume soft-float unless D extension is present. */
2499 float_abi
= FLOAT_ABI_SOFT
;
2501 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2503 if (strcasecmp (subset
->name
, "D") == 0)
2504 float_abi
= FLOAT_ABI_DOUBLE
;
2505 if (strcasecmp (subset
->name
, "Q") == 0)
2506 float_abi
= FLOAT_ABI_QUAD
;
2511 elf_flags
|= EF_RISCV_RVE
;
2513 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2514 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2516 /* If the CIE to be produced has not been overridden on the command line,
2517 then produce version 3 by default. This allows us to use the full
2518 range of registers in a .cfi_return_column directive. */
2519 if (flag_dwarf_cie_version
== -1)
2520 flag_dwarf_cie_version
= 3;
2524 md_pcrel_from (fixS
*fixP
)
2526 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2529 /* Apply a fixup to the object file. */
2532 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2534 unsigned int subtype
;
2535 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2536 bfd_boolean relaxable
= FALSE
;
2540 /* Remember value for tc_gen_reloc. */
2541 fixP
->fx_addnumber
= *valP
;
2543 switch (fixP
->fx_r_type
)
2545 case BFD_RELOC_RISCV_HI20
:
2546 case BFD_RELOC_RISCV_LO12_I
:
2547 case BFD_RELOC_RISCV_LO12_S
:
2548 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2549 | bfd_getl32 (buf
), buf
);
2550 if (fixP
->fx_addsy
== NULL
)
2551 fixP
->fx_done
= TRUE
;
2555 case BFD_RELOC_RISCV_GOT_HI20
:
2556 case BFD_RELOC_RISCV_ADD8
:
2557 case BFD_RELOC_RISCV_ADD16
:
2558 case BFD_RELOC_RISCV_ADD32
:
2559 case BFD_RELOC_RISCV_ADD64
:
2560 case BFD_RELOC_RISCV_SUB6
:
2561 case BFD_RELOC_RISCV_SUB8
:
2562 case BFD_RELOC_RISCV_SUB16
:
2563 case BFD_RELOC_RISCV_SUB32
:
2564 case BFD_RELOC_RISCV_SUB64
:
2565 case BFD_RELOC_RISCV_RELAX
:
2568 case BFD_RELOC_RISCV_TPREL_HI20
:
2569 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2570 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2571 case BFD_RELOC_RISCV_TPREL_ADD
:
2575 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2576 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2577 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2578 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2579 if (fixP
->fx_addsy
!= NULL
)
2580 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2583 _("TLS relocation against a constant"));
2587 /* Use pc-relative relocation for FDE initial location.
2588 The symbol address in .eh_frame may be adjusted in
2589 _bfd_elf_discard_section_eh_frame, and the content of
2590 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2591 Therefore, we cannot insert a relocation whose addend symbol is
2592 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2593 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2594 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2595 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2596 && S_GET_VALUE (fixP
->fx_subsy
)
2597 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2599 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2600 fixP
->fx_subsy
= NULL
;
2607 case BFD_RELOC_RISCV_CFA
:
2608 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2610 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2611 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2612 fixP
->fx_next
->fx_subsy
= NULL
;
2613 fixP
->fx_next
->fx_offset
= 0;
2614 fixP
->fx_subsy
= NULL
;
2616 switch (fixP
->fx_r_type
)
2619 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2620 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2624 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2625 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2629 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2630 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2634 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2635 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2638 case BFD_RELOC_RISCV_CFA
:
2639 /* Load the byte to get the subtype. */
2640 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2641 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2644 case DW_CFA_advance_loc1
:
2645 fixP
->fx_where
= loc
+ 1;
2646 fixP
->fx_next
->fx_where
= loc
+ 1;
2647 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2648 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2651 case DW_CFA_advance_loc2
:
2653 fixP
->fx_next
->fx_size
= 2;
2654 fixP
->fx_where
= loc
+ 1;
2655 fixP
->fx_next
->fx_where
= loc
+ 1;
2656 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2657 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2660 case DW_CFA_advance_loc4
:
2662 fixP
->fx_next
->fx_size
= 4;
2663 fixP
->fx_where
= loc
;
2664 fixP
->fx_next
->fx_where
= loc
;
2665 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2666 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2670 if (subtype
< 0x80 && (subtype
& 0x40))
2672 /* DW_CFA_advance_loc */
2673 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2674 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2675 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2676 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2679 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2685 /* This case is unreachable. */
2692 /* If we are deleting this reloc entry, we must fill in the
2693 value now. This can happen if we have a .word which is not
2694 resolved when it appears but is later defined. */
2695 if (fixP
->fx_addsy
== NULL
)
2697 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2698 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2703 case BFD_RELOC_RISCV_JMP
:
2706 /* Fill in a tentative value to improve objdump readability. */
2707 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2708 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2709 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2713 case BFD_RELOC_12_PCREL
:
2716 /* Fill in a tentative value to improve objdump readability. */
2717 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2718 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2719 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2723 case BFD_RELOC_RISCV_RVC_BRANCH
:
2726 /* Fill in a tentative value to improve objdump readability. */
2727 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2728 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2729 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2733 case BFD_RELOC_RISCV_RVC_JUMP
:
2736 /* Fill in a tentative value to improve objdump readability. */
2737 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2738 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2739 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2743 case BFD_RELOC_RISCV_CALL
:
2744 case BFD_RELOC_RISCV_CALL_PLT
:
2748 case BFD_RELOC_RISCV_PCREL_HI20
:
2749 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2750 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2751 relaxable
= riscv_opts
.relax
;
2754 case BFD_RELOC_RISCV_ALIGN
:
2758 /* We ignore generic BFD relocations we don't know about. */
2759 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2760 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2763 if (fixP
->fx_subsy
!= NULL
)
2764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2765 _("unsupported symbol subtraction"));
2767 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2768 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2770 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2771 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2772 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2776 /* Because the value of .cfi_remember_state may changed after relaxation,
2777 we insert a fix to relocate it again in link-time. */
2780 riscv_pre_output_hook (void)
2782 const frchainS
*frch
;
2785 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2786 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2790 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2792 if (frag
->fr_type
== rs_cfa
)
2795 expressionS
*symval
;
2797 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2798 exp
.X_op
= O_subtract
;
2799 exp
.X_add_symbol
= symval
->X_add_symbol
;
2800 exp
.X_add_number
= 0;
2801 exp
.X_op_symbol
= symval
->X_op_symbol
;
2803 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2804 BFD_RELOC_RISCV_CFA
);
2811 /* This structure is used to hold a stack of .option values. */
2813 struct riscv_option_stack
2815 struct riscv_option_stack
*next
;
2816 struct riscv_set_options options
;
2819 static struct riscv_option_stack
*riscv_opts_stack
;
2821 /* Handle the .option pseudo-op. */
2824 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2826 char *name
= input_line_pointer
, ch
;
2828 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2829 ++input_line_pointer
;
2830 ch
= *input_line_pointer
;
2831 *input_line_pointer
= '\0';
2833 if (strcmp (name
, "rvc") == 0)
2834 riscv_set_rvc (TRUE
);
2835 else if (strcmp (name
, "norvc") == 0)
2836 riscv_set_rvc (FALSE
);
2837 else if (strcmp (name
, "pic") == 0)
2838 riscv_opts
.pic
= TRUE
;
2839 else if (strcmp (name
, "nopic") == 0)
2840 riscv_opts
.pic
= FALSE
;
2841 else if (strcmp (name
, "relax") == 0)
2842 riscv_opts
.relax
= TRUE
;
2843 else if (strcmp (name
, "norelax") == 0)
2844 riscv_opts
.relax
= FALSE
;
2845 else if (strcmp (name
, "csr-check") == 0)
2846 riscv_opts
.csr_check
= TRUE
;
2847 else if (strcmp (name
, "no-csr-check") == 0)
2848 riscv_opts
.csr_check
= FALSE
;
2849 else if (strcmp (name
, "push") == 0)
2851 struct riscv_option_stack
*s
;
2853 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2854 s
->next
= riscv_opts_stack
;
2855 s
->options
= riscv_opts
;
2856 riscv_opts_stack
= s
;
2858 else if (strcmp (name
, "pop") == 0)
2860 struct riscv_option_stack
*s
;
2862 s
= riscv_opts_stack
;
2864 as_bad (_(".option pop with no .option push"));
2867 riscv_opts
= s
->options
;
2868 riscv_opts_stack
= s
->next
;
2874 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2876 *input_line_pointer
= ch
;
2877 demand_empty_rest_of_line ();
2880 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2881 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2882 use in DWARF debug information. */
2885 s_dtprel (int bytes
)
2892 if (ex
.X_op
!= O_symbol
)
2894 as_bad (_("Unsupported use of %s"), (bytes
== 8
2897 ignore_rest_of_line ();
2900 p
= frag_more (bytes
);
2901 md_number_to_chars (p
, 0, bytes
);
2902 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2904 ? BFD_RELOC_RISCV_TLS_DTPREL64
2905 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2907 demand_empty_rest_of_line ();
2910 /* Handle the .bss pseudo-op. */
2913 s_bss (int ignore ATTRIBUTE_UNUSED
)
2915 subseg_set (bss_section
, 0);
2916 demand_empty_rest_of_line ();
2920 riscv_make_nops (char *buf
, bfd_vma bytes
)
2924 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2925 means we are not within a valid instruction sequence. It is thus safe
2926 to use a zero byte, even though that is not a valid instruction. */
2930 /* Use at most one 2-byte NOP. */
2931 if ((bytes
- i
) % 4 == 2)
2933 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2937 /* Fill the remainder with 4-byte NOPs. */
2938 for ( ; i
< bytes
; i
+= 4)
2939 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2942 /* Called from md_do_align. Used to create an alignment frag in a
2943 code section by emitting a worst-case NOP sequence that the linker
2944 will later relax to the correct number of NOPs. We can't compute
2945 the correct alignment now because of other linker relaxations. */
2948 riscv_frag_align_code (int n
)
2950 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2951 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2952 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2956 /* If we are moving to a smaller alignment than the instruction size, then no
2957 alignment is required. */
2958 if (bytes
<= insn_alignment
)
2961 /* When not relaxing, riscv_handle_align handles code alignment. */
2962 if (!riscv_opts
.relax
)
2965 nops
= frag_more (worst_case_bytes
);
2967 ex
.X_op
= O_constant
;
2968 ex
.X_add_number
= worst_case_bytes
;
2970 riscv_make_nops (nops
, worst_case_bytes
);
2972 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2973 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2978 /* Implement HANDLE_ALIGN. */
2981 riscv_handle_align (fragS
*fragP
)
2983 switch (fragP
->fr_type
)
2986 /* When relaxing, riscv_frag_align_code handles code alignment. */
2987 if (!riscv_opts
.relax
)
2989 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2990 - fragP
->fr_address
- fragP
->fr_fix
);
2991 /* We have 4 byte uncompressed nops. */
2992 bfd_signed_vma size
= 4;
2993 bfd_signed_vma excess
= bytes
% size
;
2994 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2999 /* Insert zeros or compressed nops to get 4 byte alignment. */
3002 riscv_make_nops (p
, excess
);
3003 fragP
->fr_fix
+= excess
;
3007 /* Insert variable number of 4 byte uncompressed nops. */
3008 riscv_make_nops (p
, size
);
3009 fragP
->fr_var
= size
;
3019 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3021 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3024 /* Translate internal representation of relocation info to BFD target
3028 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3030 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3032 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3033 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3034 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3035 reloc
->addend
= fixp
->fx_addnumber
;
3037 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3038 if (reloc
->howto
== NULL
)
3040 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3041 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3043 /* We don't have R_RISCV_8/16, but for this special case,
3044 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3048 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3049 _("cannot represent %s relocation in object file"),
3050 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3058 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3060 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3062 offsetT old_var
= fragp
->fr_var
;
3063 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3064 return fragp
->fr_var
- old_var
;
3070 /* Expand far branches to multi-instruction sequences. */
3073 md_convert_frag_branch (fragS
*fragp
)
3081 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3083 exp
.X_op
= O_symbol
;
3084 exp
.X_add_symbol
= fragp
->fr_symbol
;
3085 exp
.X_add_number
= fragp
->fr_offset
;
3087 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3089 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3091 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3095 /* Expand the RVC branch into a RISC-V one. */
3096 insn
= bfd_getl16 (buf
);
3097 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3098 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3100 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3101 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3102 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3103 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3104 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3105 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3108 bfd_putl32 (insn
, buf
);
3112 /* Invert the branch condition. Branch over the jump. */
3113 insn
= bfd_getl16 (buf
);
3114 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3115 insn
|= ENCODE_RVC_B_IMM (6);
3116 bfd_putl16 (insn
, buf
);
3121 /* Just keep the RVC branch. */
3122 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3123 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3124 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3125 2, &exp
, FALSE
, reloc
);
3134 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3137 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3139 /* Invert the branch condition. Branch over the jump. */
3140 insn
= bfd_getl32 (buf
);
3141 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3142 insn
|= ENCODE_SBTYPE_IMM (8);
3143 md_number_to_chars ((char *) buf
, insn
, 4);
3147 /* Jump to the target. */
3148 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3149 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3150 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3155 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3156 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3157 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3158 4, &exp
, FALSE
, reloc
);
3167 fixp
->fx_file
= fragp
->fr_file
;
3168 fixp
->fx_line
= fragp
->fr_line
;
3170 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3171 + fragp
->fr_fix
+ fragp
->fr_var
);
3173 fragp
->fr_fix
+= fragp
->fr_var
;
3176 /* Relax a machine dependent frag. This returns the amount by which
3177 the current size of the frag should change. */
3180 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3183 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3184 md_convert_frag_branch (fragp
);
3188 md_show_usage (FILE *stream
)
3190 fprintf (stream
, _("\
3192 -fpic generate position-independent code\n\
3193 -fno-pic don't generate position-independent code (default)\n\
3194 -march=ISA set the RISC-V architecture\n\
3195 -mabi=ABI set the RISC-V ABI\n\
3196 -mrelax enable relax (default)\n\
3197 -mno-relax disable relax\n\
3198 -march-attr generate RISC-V arch attribute\n\
3199 -mno-arch-attr don't generate RISC-V arch attribute\n\
3203 /* Standard calling conventions leave the CFA at SP on entry. */
3205 riscv_cfi_frame_initial_instructions (void)
3207 cfi_add_CFA_def_cfa_register (X_SP
);
3211 tc_riscv_regname_to_dw2regnum (char *regname
)
3215 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3218 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3221 /* CSRs are numbered 4096 -> 8191. */
3222 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3225 as_bad (_("unknown register `%s'"), regname
);
3230 riscv_elf_final_processing (void)
3232 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3235 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3236 since these directives break relaxation when used with symbol deltas. */
3239 s_riscv_leb128 (int sign
)
3242 char *save_in
= input_line_pointer
;
3245 if (exp
.X_op
!= O_constant
)
3246 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3247 demand_empty_rest_of_line ();
3249 input_line_pointer
= save_in
;
3250 return s_leb128 (sign
);
3253 /* Parse the .insn directive. */
3256 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3258 char *str
= input_line_pointer
;
3259 struct riscv_cl_insn insn
;
3260 expressionS imm_expr
;
3261 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3264 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3265 ++input_line_pointer
;
3267 save_c
= *input_line_pointer
;
3268 *input_line_pointer
= '\0';
3270 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3271 &imm_reloc
, insn_type_hash
);
3275 as_bad ("%s `%s'", error
, str
);
3279 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3280 append_insn (&insn
, &imm_expr
, imm_reloc
);
3283 *input_line_pointer
= save_c
;
3284 demand_empty_rest_of_line ();
3287 /* Update arch attributes. */
3290 riscv_write_out_arch_attr (void)
3292 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3294 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3296 xfree ((void *)arch_str
);
3299 /* Add the default contents for the .riscv.attributes section. */
3302 riscv_set_public_attributes (void)
3304 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3305 /* Re-write arch attribute to normalize the arch string. */
3306 riscv_write_out_arch_attr ();
3309 /* Called after all assembly has been done. */
3314 riscv_set_public_attributes ();
3317 /* Given a symbolic attribute NAME, return the proper integer value.
3318 Returns -1 if the attribute is not known. */
3321 riscv_convert_symbolic_attribute (const char *name
)
3330 /* When you modify this table you should
3331 also modify the list in doc/c-riscv.texi. */
3332 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3336 T(priv_spec_revision
),
3337 T(unaligned_access
),
3347 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3348 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3349 return attribute_table
[i
].tag
;
3354 /* Parse a .attribute directive. */
3357 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3359 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3361 if (tag
== Tag_RISCV_arch
)
3363 unsigned old_xlen
= xlen
;
3365 explicit_arch_attr
= TRUE
;
3366 obj_attribute
*attr
;
3367 attr
= elf_known_obj_attributes_proc (stdoutput
);
3368 if (!start_assemble
)
3369 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3371 as_fatal (_(".attribute arch must set before any instructions"));
3373 if (old_xlen
!= xlen
)
3375 /* We must re-init bfd again if xlen is changed. */
3376 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3377 bfd_find_target (riscv_target_format (), stdoutput
);
3379 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3380 as_warn (_("Could not set architecture and machine"));
3385 /* Pseudo-op table. */
3387 static const pseudo_typeS riscv_pseudo_table
[] =
3389 /* RISC-V-specific pseudo-ops. */
3390 {"option", s_riscv_option
, 0},
3394 {"dtprelword", s_dtprel
, 4},
3395 {"dtpreldword", s_dtprel
, 8},
3397 {"uleb128", s_riscv_leb128
, 0},
3398 {"sleb128", s_riscv_leb128
, 1},
3399 {"insn", s_riscv_insn
, 0},
3400 {"attribute", s_riscv_attribute
, 0},
3406 riscv_pop_insert (void)
3408 extern void pop_insert (const pseudo_typeS
*);
3410 pop_insert (riscv_pseudo_table
);