1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
132 /* Find the corresponding priv spec class. */
133 if (riscv_get_priv_spec_class (s
, &class))
135 default_priv_spec
= class;
141 as_bad (_("Unknown default privilege spec `%s' set by "
142 "-mpriv-spec or --with-priv-spec"), s
);
146 /* Try to set the default_priv_spec according to the priv attributes. */
147 attr
= elf_known_obj_attributes_proc (stdoutput
);
148 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
149 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
150 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
152 /* The priv attributes setting 0.0.0 is meaningless. We should have set
153 the default_priv_spec by md_parse_option and riscv_after_parse_args,
154 so just skip the following setting. */
155 if (major
== 0 && minor
== 0 && revision
== 0)
158 buf_size
= riscv_estimate_digit (major
)
160 + riscv_estimate_digit (minor
)
161 + 1; /* string terminator */
164 buf_size
+= 1 /* '.' */
165 + riscv_estimate_digit (revision
);
166 buf
= xmalloc (buf_size
);
167 snprintf (buf
, buf_size
, "%d.%d.%d", major
, minor
, revision
);
171 buf
= xmalloc (buf_size
);
172 snprintf (buf
, buf_size
, "%d.%d", major
, minor
);
175 if (riscv_get_priv_spec_class (buf
, &class))
177 default_priv_spec
= class;
182 /* Still can not find the priv spec class. */
183 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
184 "privilege attributes"), major
, minor
, revision
);
189 /* This is the set of options which the .option pseudo-op may modify. */
191 struct riscv_set_options
193 int pic
; /* Generate position-independent code. */
194 int rvc
; /* Generate RVC code. */
195 int rve
; /* Generate RVE code. */
196 int relax
; /* Emit relocs the linker is allowed to relax. */
197 int arch_attr
; /* Emit arch attribute. */
198 int csr_check
; /* Enable the CSR checking. */
201 static struct riscv_set_options riscv_opts
=
207 DEFAULT_RISCV_ATTR
, /* arch_attr */
212 riscv_set_rvc (bfd_boolean rvc_value
)
215 elf_flags
|= EF_RISCV_RVC
;
217 riscv_opts
.rvc
= rvc_value
;
221 riscv_set_rve (bfd_boolean rve_value
)
223 riscv_opts
.rve
= rve_value
;
226 static riscv_subset_list_t riscv_subsets
;
229 riscv_subset_supports (const char *feature
)
231 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
234 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
238 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
242 case INSN_CLASS_I
: return riscv_subset_supports ("i");
243 case INSN_CLASS_C
: return riscv_subset_supports ("c");
244 case INSN_CLASS_A
: return riscv_subset_supports ("a");
245 case INSN_CLASS_M
: return riscv_subset_supports ("m");
246 case INSN_CLASS_F
: return riscv_subset_supports ("f");
247 case INSN_CLASS_D
: return riscv_subset_supports ("d");
248 case INSN_CLASS_D_AND_C
:
249 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
251 case INSN_CLASS_F_AND_C
:
252 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
254 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
257 as_fatal ("Unreachable");
262 /* Handle of the extension with version hash table. */
263 static struct hash_control
*ext_version_hash
= NULL
;
265 static struct hash_control
*
266 init_ext_version_hash (const struct riscv_ext_version
*table
)
269 struct hash_control
*hash
= hash_new ();
271 while (table
[i
].name
)
273 const char *name
= table
[i
].name
;
274 const char *hash_error
=
275 hash_insert (hash
, name
, (void *) &table
[i
]);
277 if (hash_error
!= NULL
)
279 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
280 table
[i
].name
, hash_error
);
281 /* Probably a memory allocation problem? Give up now. */
282 as_fatal (_("Broken assembler. No assembly attempted."));
288 && strcmp (table
[i
].name
, name
) == 0)
296 riscv_get_default_ext_version (const char *name
,
297 unsigned int *major_version
,
298 unsigned int *minor_version
)
300 struct riscv_ext_version
*ext
;
305 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
308 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
311 && strcmp (ext
->name
, name
) == 0)
313 if (ext
->isa_spec_class
== default_isa_spec
)
315 *major_version
= ext
->major_version
;
316 *minor_version
= ext
->minor_version
;
323 /* Set which ISA and extensions are available. */
326 riscv_set_arch (const char *s
)
328 riscv_parse_subset_t rps
;
329 rps
.subset_list
= &riscv_subsets
;
330 rps
.error_handler
= as_fatal
;
332 rps
.get_default_version
= riscv_get_default_ext_version
;
337 riscv_release_subset_list (&riscv_subsets
);
338 riscv_parse_subset (&rps
, s
);
341 /* Handle of the OPCODE hash table. */
342 static struct hash_control
*op_hash
= NULL
;
344 /* Handle of the type of .insn hash table. */
345 static struct hash_control
*insn_type_hash
= NULL
;
347 /* This array holds the chars that always start a comment. If the
348 pre-processor is disabled, these aren't very useful */
349 const char comment_chars
[] = "#";
351 /* This array holds the chars that only start a comment at the beginning of
352 a line. If the line seems to have the form '# 123 filename'
353 .line and .file directives will appear in the pre-processed output */
354 /* Note that input_file.c hand checks for '#' at the beginning of the
355 first line of the input file. This is because the compiler outputs
356 #NO_APP at the beginning of its output. */
357 /* Also note that C style comments are always supported. */
358 const char line_comment_chars
[] = "#";
360 /* This array holds machine specific line separator characters. */
361 const char line_separator_chars
[] = ";";
363 /* Chars that can be used to separate mant from exp in floating point nums */
364 const char EXP_CHARS
[] = "eE";
366 /* Chars that mean this number is a floating point constant */
369 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
371 /* Indicate we are already assemble any instructions or not. */
372 static bfd_boolean start_assemble
= FALSE
;
374 /* Indicate ELF attributes are explictly set. */
375 static bfd_boolean explicit_attr
= FALSE
;
377 /* Macros for encoding relaxation state for RVC branches and far jumps. */
378 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
381 | ((uncond) ? 1 : 0) \
384 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
385 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
386 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
387 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
389 /* Is the given value a sign-extended 32-bit value? */
390 #define IS_SEXT_32BIT_NUM(x) \
391 (((x) &~ (offsetT) 0x7fffffff) == 0 \
392 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
394 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
395 #define IS_ZEXT_32BIT_NUM(x) \
396 (((x) &~ (offsetT) 0xffffffff) == 0 \
397 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
399 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
400 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
401 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
402 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
404 /* Determine if an instruction matches an opcode. */
405 #define OPCODE_MATCHES(OPCODE, OP) \
406 (((OPCODE) & MASK_##OP) == MATCH_##OP)
408 static char *expr_end
;
410 /* The default target format to use. */
413 riscv_target_format (void)
415 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
418 /* Return the length of instruction INSN. */
420 static inline unsigned int
421 insn_length (const struct riscv_cl_insn
*insn
)
423 return riscv_insn_length (insn
->insn_opcode
);
426 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
429 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
432 insn
->insn_opcode
= mo
->match
;
438 /* Install INSN at the location specified by its "frag" and "where" fields. */
441 install_insn (const struct riscv_cl_insn
*insn
)
443 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
444 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
447 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
448 and install the opcode in the new location. */
451 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
455 if (insn
->fixp
!= NULL
)
457 insn
->fixp
->fx_frag
= frag
;
458 insn
->fixp
->fx_where
= where
;
463 /* Add INSN to the end of the output. */
466 add_fixed_insn (struct riscv_cl_insn
*insn
)
468 char *f
= frag_more (insn_length (insn
));
469 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
473 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
474 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
476 frag_grow (max_chars
);
477 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
478 frag_var (rs_machine_dependent
, max_chars
, var
,
479 subtype
, symbol
, offset
, NULL
);
482 /* Compute the length of a branch sequence, and adjust the stored length
483 accordingly. If FRAGP is NULL, the worst-case length is returned. */
486 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
488 int jump
, rvc
, length
= 8;
493 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
494 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
495 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
497 /* Assume jumps are in range; the linker will catch any that aren't. */
498 length
= jump
? 4 : 8;
500 if (fragp
->fr_symbol
!= NULL
501 && S_IS_DEFINED (fragp
->fr_symbol
)
502 && !S_IS_WEAK (fragp
->fr_symbol
)
503 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
505 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
506 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
507 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
509 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
511 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
513 else if (!jump
&& rvc
)
518 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
523 /* Information about an opcode name, mnemonics and its value. */
530 /* List for all supported opcode name. */
531 static const struct opcode_name_t opcode_name_list
[] =
576 /* Hash table for lookup opcode name. */
577 static struct hash_control
*opcode_names_hash
= NULL
;
579 /* Initialization for hash table of opcode name. */
581 init_opcode_names_hash (void)
584 const struct opcode_name_t
*opcode
;
586 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
588 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
591 as_fatal (_("internal error: can't hash `%s': %s"),
592 opcode
->name
, retval
);
596 /* Find `s` is a valid opcode name or not,
597 return the opcode name info if found. */
598 static const struct opcode_name_t
*
599 opcode_name_lookup (char **s
)
603 struct opcode_name_t
*o
;
605 /* Find end of name. */
607 if (is_name_beginner (*e
))
609 while (is_part_of_name (*e
))
612 /* Terminate name. */
616 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
618 /* Advance to next token if one was recognized. */
637 static struct hash_control
*reg_names_hash
= NULL
;
638 static struct hash_control
*csr_extra_hash
= NULL
;
640 #define ENCODE_REG_HASH(cls, n) \
641 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
642 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
643 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
646 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
648 void *hash
= ENCODE_REG_HASH (class, n
);
649 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
652 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
656 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
660 for (i
= 0; i
< n
; i
++)
661 hash_reg_name (class, names
[i
], i
);
664 /* Init hash table csr_extra_hash to handle CSR. */
666 riscv_init_csr_hash (const char *name
,
668 enum riscv_csr_class
class,
669 enum riscv_priv_spec_class define_version
,
670 enum riscv_priv_spec_class abort_version
)
672 struct riscv_csr_extra
*entry
, *pre_entry
;
673 const char *hash_error
= NULL
;
674 bfd_boolean need_enrty
= TRUE
;
677 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
678 while (need_enrty
&& entry
!= NULL
)
680 if (entry
->csr_class
== class
681 && entry
->address
== address
682 && entry
->define_version
== define_version
683 && entry
->abort_version
== abort_version
)
689 /* Duplicate setting for the CSR, just return and do nothing. */
693 entry
= XNEW (struct riscv_csr_extra
);
694 entry
->csr_class
= class;
695 entry
->address
= address
;
696 entry
->define_version
= define_version
;
697 entry
->abort_version
= abort_version
;
699 /* If the CSR hasn't been inserted in the hash table, then insert it.
700 Otherwise, attach the extra information to the entry which is already
701 in the hash table. */
702 if (pre_entry
== NULL
)
704 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
705 if (hash_error
!= NULL
)
707 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
709 /* Probably a memory allocation problem? Give up now. */
710 as_fatal (_("Broken assembler. No assembly attempted."));
714 pre_entry
->next
= entry
;
717 /* Check wether the CSR is valid according to the ISA. */
720 riscv_csr_class_check (const char *s
,
721 enum riscv_csr_class csr_class
)
723 bfd_boolean result
= TRUE
;
725 /* Don't check the ISA dependency when -mcsr-check isn't set. */
726 if (!riscv_opts
.csr_check
)
732 result
= riscv_subset_supports ("i");
735 result
= riscv_subset_supports ("f");
738 result
= (xlen
== 32 && riscv_subset_supports ("i"));
741 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
745 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
748 /* Check and find the CSR address according to the privilege spec version. */
751 riscv_csr_version_check (const char *csr_name
,
752 struct riscv_csr_extra
**entryP
)
754 struct riscv_csr_extra
*entry
= *entryP
;
756 while (entry
!= NULL
)
758 if (default_priv_spec
>= entry
->define_version
759 && default_priv_spec
< entry
->abort_version
)
761 /* Find the suitable CSR according to the specific version. */
768 /* We can not find the suitable CSR address according to the privilege
769 version. Therefore, we use the last defined value. Report the warning
770 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
771 otherwise, you may get the unexpected CSR address. */
772 if (riscv_opts
.csr_check
)
774 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
776 if (priv_name
!= NULL
)
777 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
778 csr_name
, priv_name
);
782 /* Once the CSR is defined, including the old privilege spec, then we call
783 riscv_csr_class_check and riscv_csr_version_check to do the further checking
784 and get the corresponding address. Return -1 if the CSR is never been
785 defined. Otherwise, return the address. */
788 reg_csr_lookup_internal (const char *s
)
790 struct riscv_csr_extra
*r
=
791 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
796 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
797 the CSR was defined, but isn't allowed for the current ISA setting or
798 the privilege spec. If the CSR is never been defined, then assembler
799 will regard it as a "Unknown CSR" and report error. If user use number
800 to set the CSR, but over the range (> 0xfff), then assembler will report
801 "Improper CSR" error for it. */
802 riscv_csr_class_check (s
, r
->csr_class
);
803 riscv_csr_version_check (s
, &r
);
809 reg_lookup_internal (const char *s
, enum reg_class
class)
813 if (class == RCLASS_CSR
)
814 return reg_csr_lookup_internal (s
);
816 r
= hash_find (reg_names_hash
, s
);
817 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
820 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
823 return DECODE_REG_NUM (r
);
827 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
833 /* Find end of name. */
835 if (is_name_beginner (*e
))
837 while (is_part_of_name (*e
))
840 /* Terminate name. */
844 /* Look for the register. Advance to next token if one was recognized. */
845 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
855 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
857 const char *p
= strchr (*s
, ',');
858 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
863 for (i
= 0; i
< size
; i
++)
864 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
874 /* For consistency checking, verify that all bits are specified either
875 by the match/mask part of the instruction definition, or by the
878 `length` could be 0, 4 or 8, 0 for auto detection. */
880 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
882 const char *p
= opc
->args
;
884 insn_t used_bits
= opc
->mask
;
886 insn_t required_bits
;
889 insn_width
= 8 * riscv_insn_length (opc
->match
);
891 insn_width
= 8 * length
;
893 required_bits
= ~0ULL >> (64 - insn_width
);
895 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
897 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
898 opc
->name
, opc
->args
);
902 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
909 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
910 case 'c': break; /* RS1, constrained to equal sp */
911 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
912 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
913 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
914 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
915 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
916 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
917 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
918 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
919 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
920 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
921 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
922 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
923 case 'w': break; /* RS1S, constrained to equal RD */
924 case 'x': break; /* RS2S, constrained to equal RD */
925 case 'z': break; /* RS2S, contrained to be x0 */
926 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
927 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
928 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
929 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
930 case 'U': break; /* RS1, constrained to equal RD */
931 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
932 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
933 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
934 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
935 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
936 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
937 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
938 case 'F': /* funct */
941 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
942 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
943 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
944 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
946 as_bad (_("internal: bad RISC-V opcode"
947 " (unknown operand type `CF%c'): %s %s"),
948 c
, opc
->name
, opc
->args
);
953 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
954 c
, opc
->name
, opc
->args
);
961 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
962 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
964 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
965 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
966 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
968 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
969 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
970 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
971 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
972 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
973 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
974 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
975 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
976 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
977 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
978 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
980 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
981 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
982 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
983 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
984 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
990 case 'F': /* funct */
993 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
994 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
995 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
997 as_bad (_("internal: bad RISC-V opcode"
998 " (unknown operand type `F%c'): %s %s"),
999 c
, opc
->name
, opc
->args
);
1003 case 'O': /* opcode */
1006 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1007 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1009 as_bad (_("internal: bad RISC-V opcode"
1010 " (unknown operand type `F%c'): %s %s"),
1011 c
, opc
->name
, opc
->args
);
1016 as_bad (_("internal: bad RISC-V opcode "
1017 "(unknown operand type `%c'): %s %s"),
1018 c
, opc
->name
, opc
->args
);
1022 if (used_bits
!= required_bits
)
1024 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1025 ~(unsigned long)(used_bits
& required_bits
),
1026 opc
->name
, opc
->args
);
1032 struct percent_op_match
1035 bfd_reloc_code_real_type reloc
;
1038 /* Common hash table initialization function for
1039 instruction and .insn directive. */
1040 static struct hash_control
*
1041 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1042 bfd_boolean insn_directive_p
)
1046 struct hash_control
*hash
= hash_new ();
1047 while (opcodes
[i
].name
)
1049 const char *name
= opcodes
[i
].name
;
1050 const char *hash_error
=
1051 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1053 if (hash_error
!= NULL
)
1055 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1056 opcodes
[i
].name
, hash_error
);
1057 /* Probably a memory allocation problem? Give up now. */
1058 as_fatal (_("Broken assembler. No assembly attempted."));
1063 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1065 if (insn_directive_p
)
1066 length
= ((name
[0] == 'c') ? 2 : 4);
1068 length
= 0; /* Let assembler determine the length. */
1069 if (!validate_riscv_insn (&opcodes
[i
], length
))
1070 as_fatal (_("Broken assembler. No assembly attempted."));
1073 gas_assert (!insn_directive_p
);
1076 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1082 /* This function is called once, at assembler startup time. It should set up
1083 all the tables, etc. that the MD part of the assembler will need. */
1088 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1090 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1091 as_warn (_("Could not set architecture and machine"));
1093 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1094 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1096 reg_names_hash
= hash_new ();
1097 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1098 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1099 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1100 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1101 /* Add "fp" as an alias for "s0". */
1102 hash_reg_name (RCLASS_GPR
, "fp", 8);
1104 /* Create and insert CSR hash tables. */
1105 csr_extra_hash
= hash_new ();
1106 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1107 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1108 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1109 DECLARE_CSR(name, num, class, define_version, abort_version);
1110 #include "opcode/riscv-opc.h"
1113 opcode_names_hash
= hash_new ();
1114 init_opcode_names_hash ();
1116 /* Set the default alignment for the text section. */
1117 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1121 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1128 case BFD_RELOC_RISCV_HI20
:
1129 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1131 case BFD_RELOC_RISCV_LO12_S
:
1132 return ENCODE_STYPE_IMM (value
);
1134 case BFD_RELOC_RISCV_LO12_I
:
1135 return ENCODE_ITYPE_IMM (value
);
1142 /* Output an instruction. IP is the instruction information.
1143 ADDRESS_EXPR is an operand of the instruction to be used with
1147 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1148 bfd_reloc_code_real_type reloc_type
)
1150 dwarf2_emit_insn (0);
1152 if (reloc_type
!= BFD_RELOC_UNUSED
)
1154 reloc_howto_type
*howto
;
1156 gas_assert (address_expr
);
1157 if (reloc_type
== BFD_RELOC_12_PCREL
1158 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1160 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1161 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1162 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1163 add_relaxed_insn (ip
, worst_case
, best_case
,
1164 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1165 address_expr
->X_add_symbol
,
1166 address_expr
->X_add_number
);
1171 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1173 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1175 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1176 bfd_get_reloc_size (howto
),
1177 address_expr
, FALSE
, reloc_type
);
1179 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1183 add_fixed_insn (ip
);
1186 /* We need to start a new frag after any instruction that can be
1187 optimized away or compressed by the linker during relaxation, to prevent
1188 the assembler from computing static offsets across such an instruction.
1189 This is necessary to get correct EH info. */
1190 if (reloc_type
== BFD_RELOC_RISCV_CALL
1191 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1192 || reloc_type
== BFD_RELOC_RISCV_HI20
1193 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1194 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1195 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1197 frag_wane (frag_now
);
1202 /* Build an instruction created by a macro expansion. This is passed
1203 a pointer to the count of instructions created so far, an
1204 expression, the name of the instruction to build, an operand format
1205 string, and corresponding arguments. */
1208 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1210 const struct riscv_opcode
*mo
;
1211 struct riscv_cl_insn insn
;
1212 bfd_reloc_code_real_type r
;
1215 va_start (args
, fmt
);
1217 r
= BFD_RELOC_UNUSED
;
1218 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1221 /* Find a non-RVC variant of the instruction. append_insn will compress
1223 while (riscv_insn_length (mo
->match
) < 4)
1225 gas_assert (strcmp (name
, mo
->name
) == 0);
1227 create_insn (&insn
, mo
);
1233 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1237 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1241 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1245 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1251 gas_assert (ep
!= NULL
);
1252 r
= va_arg (args
, int);
1260 as_fatal (_("internal error: invalid macro"));
1265 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1267 append_insn (&insn
, ep
, r
);
1270 /* Build an instruction created by a macro expansion. Like md_assemble but
1271 accept a printf-style format string and arguments. */
1274 md_assemblef (const char *format
, ...)
1280 va_start (ap
, format
);
1282 r
= vasprintf (&buf
, format
, ap
);
1285 as_fatal (_("internal error: vasprintf failed"));
1293 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1296 normalize_constant_expr (expressionS
*ex
)
1300 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1301 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1302 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1306 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1307 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1310 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1311 bfd_boolean maybe_csr
)
1313 if (ex
->X_op
== O_big
)
1314 as_bad (_("unsupported large constant"));
1315 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1316 as_bad (_("unknown CSR `%s'"),
1317 S_GET_NAME (ex
->X_add_symbol
));
1318 else if (ex
->X_op
!= O_constant
)
1319 as_bad (_("Instruction %s requires absolute expression"),
1321 normalize_constant_expr (ex
);
1325 make_internal_label (void)
1327 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1328 (valueT
) frag_now_fix (), frag_now
);
1331 /* Load an entry from the GOT. */
1333 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1334 const char *lo_insn
, const char *lo_pattern
,
1335 bfd_reloc_code_real_type hi_reloc
,
1336 bfd_reloc_code_real_type lo_reloc
)
1339 ep2
.X_op
= O_symbol
;
1340 ep2
.X_add_symbol
= make_internal_label ();
1341 ep2
.X_add_number
= 0;
1343 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1344 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1348 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1349 bfd_reloc_code_real_type hi_reloc
,
1350 bfd_reloc_code_real_type lo_reloc
)
1352 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1356 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1357 bfd_reloc_code_real_type hi_reloc
,
1358 bfd_reloc_code_real_type lo_reloc
)
1360 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1363 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1365 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1366 bfd_reloc_code_real_type reloc
)
1368 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1369 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1372 /* Load an integer constant into a register. */
1375 load_const (int reg
, expressionS
*ep
)
1377 int shift
= RISCV_IMM_BITS
;
1378 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1379 expressionS upper
= *ep
, lower
= *ep
;
1380 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1381 upper
.X_add_number
-= lower
.X_add_number
;
1383 if (ep
->X_op
!= O_constant
)
1385 as_bad (_("unsupported large constant"));
1389 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1391 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1392 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1395 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1396 load_const (reg
, &upper
);
1398 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1399 if (lower
.X_add_number
!= 0)
1400 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1401 lower
.X_add_number
);
1405 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1408 if (upper
.X_add_number
!= 0)
1410 /* Discard low part and zero-extend upper immediate. */
1411 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1413 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1417 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1418 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1419 lower
.X_add_number
);
1423 /* Expand RISC-V assembly macros into one or more instructions. */
1425 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1426 bfd_reloc_code_real_type
*imm_reloc
)
1428 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1429 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1430 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1431 int mask
= ip
->insn_mo
->mask
;
1436 load_const (rd
, imm_expr
);
1441 /* Load the address of a symbol into a register. */
1442 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1443 as_bad (_("offset too large"));
1445 if (imm_expr
->X_op
== O_constant
)
1446 load_const (rd
, imm_expr
);
1447 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1448 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1449 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1450 else /* Local PIC symbol, or any non-PIC symbol */
1451 pcrel_load (rd
, rd
, imm_expr
, "addi",
1452 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1456 pcrel_load (rd
, rd
, imm_expr
, "addi",
1457 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1461 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1462 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1466 pcrel_load (rd
, rd
, imm_expr
, "lb",
1467 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1471 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1472 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1476 pcrel_load (rd
, rd
, imm_expr
, "lh",
1477 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1481 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1482 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1486 pcrel_load (rd
, rd
, imm_expr
, "lw",
1487 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1491 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1492 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1496 pcrel_load (rd
, rd
, imm_expr
, "ld",
1497 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1501 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1502 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1506 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1507 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1511 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1512 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1516 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1517 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1521 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1522 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1526 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1527 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1531 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1532 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1536 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1537 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1541 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1545 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1550 static const struct percent_op_match percent_op_utype
[] =
1552 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1553 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1554 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1555 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1556 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1557 {"%hi", BFD_RELOC_RISCV_HI20
},
1561 static const struct percent_op_match percent_op_itype
[] =
1563 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1564 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1565 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1569 static const struct percent_op_match percent_op_stype
[] =
1571 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1572 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1573 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1577 static const struct percent_op_match percent_op_rtype
[] =
1579 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1583 static const struct percent_op_match percent_op_null
[] =
1588 /* Return true if *STR points to a relocation operator. When returning true,
1589 move *STR over the operator and store its relocation code in *RELOC.
1590 Leave both *STR and *RELOC alone when returning false. */
1593 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1594 const struct percent_op_match
*percent_op
)
1596 for ( ; percent_op
->str
; percent_op
++)
1597 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1599 int len
= strlen (percent_op
->str
);
1601 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1604 *str
+= strlen (percent_op
->str
);
1605 *reloc
= percent_op
->reloc
;
1607 /* Check whether the output BFD supports this relocation.
1608 If not, issue an error and fall back on something safe. */
1609 if (*reloc
!= BFD_RELOC_UNUSED
1610 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1612 as_bad ("relocation %s isn't supported by the current ABI",
1614 *reloc
= BFD_RELOC_UNUSED
;
1622 my_getExpression (expressionS
*ep
, char *str
)
1626 save_in
= input_line_pointer
;
1627 input_line_pointer
= str
;
1629 expr_end
= input_line_pointer
;
1630 input_line_pointer
= save_in
;
1633 /* Parse string STR as a 16-bit relocatable operand. Store the
1634 expression in *EP and the relocation, if any, in RELOC.
1635 Return the number of relocation operators used (0 or 1).
1637 On exit, EXPR_END points to the first character after the expression. */
1640 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1641 char *str
, const struct percent_op_match
*percent_op
)
1644 unsigned crux_depth
, str_depth
, regno
;
1647 /* First, check for integer registers. No callers can accept a reg, but
1648 we need to avoid accidentally creating a useless undefined symbol below,
1649 if this is an instruction pattern that can't match. A glibc build fails
1650 if this is removed. */
1651 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1653 ep
->X_op
= O_register
;
1654 ep
->X_add_number
= regno
;
1659 /* Search for the start of the main expression.
1660 End the loop with CRUX pointing to the start
1661 of the main expression and with CRUX_DEPTH containing the number
1662 of open brackets at that point. */
1669 crux_depth
= str_depth
;
1671 /* Skip over whitespace and brackets, keeping count of the number
1673 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1679 && parse_relocation (&str
, reloc
, percent_op
));
1681 my_getExpression (ep
, crux
);
1684 /* Match every open bracket. */
1685 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1690 as_bad ("unclosed '('");
1697 /* Parse opcode name, could be an mnemonics or number. */
1699 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1700 char *str
, const struct percent_op_match
*percent_op
)
1702 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1706 ep
->X_op
= O_constant
;
1707 ep
->X_add_number
= o
->val
;
1711 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1714 /* Detect and handle implicitly zero load-store offsets. For example,
1715 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1716 an implicit offset was detected. */
1719 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1721 /* Check whether there is only a single bracketed expression left.
1722 If so, it must be the base register and the constant must be zero. */
1723 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1725 ep
->X_op
= O_constant
;
1726 ep
->X_add_number
= 0;
1733 /* All RISC-V CSR instructions belong to one of these classes. */
1743 /* Return which CSR instruction is checking. */
1745 static enum csr_insn_type
1746 riscv_csr_insn_type (insn_t insn
)
1748 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1749 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1751 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1752 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1754 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1755 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1758 return INSN_NOT_CSR
;
1761 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1762 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1763 CSR address is 0x3. */
1766 riscv_csr_read_only_check (insn_t insn
)
1768 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1769 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1770 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1771 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1774 && (((csr_insn
== INSN_CSRRS
1775 || csr_insn
== INSN_CSRRC
)
1777 || csr_insn
== INSN_CSRRW
))
1783 /* This routine assembles an instruction into its binary format. As a
1784 side effect, it sets the global variable imm_reloc to the type of
1785 relocation to do if one of the operands is an address expression. */
1788 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1789 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1794 struct riscv_opcode
*insn
;
1799 const struct percent_op_match
*p
;
1800 const char *error
= "unrecognized opcode";
1801 /* Indicate we are assembling instruction with CSR. */
1802 bfd_boolean insn_with_csr
= FALSE
;
1804 /* Parse the name of the instruction. Terminate the string if whitespace
1805 is found so that hash_find only sees the name part of the string. */
1806 for (s
= str
; *s
!= '\0'; ++s
)
1814 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1817 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1819 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1822 if (!riscv_multi_subset_supports (insn
->insn_class
))
1825 create_insn (ip
, insn
);
1828 imm_expr
->X_op
= O_absent
;
1829 *imm_reloc
= BFD_RELOC_UNUSED
;
1830 p
= percent_op_itype
;
1832 for (args
= insn
->args
;; ++args
)
1834 s
+= strspn (s
, " \t");
1837 case '\0': /* End of args. */
1838 if (insn
->pinfo
!= INSN_MACRO
)
1840 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1843 /* For .insn, insn->match and insn->mask are 0. */
1844 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1850 /* Check if we write a read-only CSR by the CSR
1853 && riscv_opts
.csr_check
1854 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1856 /* Restore the character in advance, since we want to
1857 report the detailed warning message here. */
1859 *(argsStart
- 1) = save_c
;
1860 as_warn (_("Read-only CSR is written `%s'"), str
);
1861 insn_with_csr
= FALSE
;
1866 /* Successful assembly. */
1868 insn_with_csr
= FALSE
;
1874 case 's': /* RS1 x8-x15 */
1875 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1876 || !(regno
>= 8 && regno
<= 15))
1878 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1880 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1881 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1882 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1885 case 't': /* RS2 x8-x15 */
1886 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1887 || !(regno
>= 8 && regno
<= 15))
1889 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1891 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1892 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1893 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1896 case 'U': /* RS1, constrained to equal RD. */
1897 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1898 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1902 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1904 INSERT_OPERAND (CRS2
, *ip
, regno
);
1906 case 'c': /* RS1, constrained to equal sp. */
1907 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1911 case 'z': /* RS2, contrained to equal x0. */
1912 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1917 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1918 || imm_expr
->X_op
!= O_constant
1919 || imm_expr
->X_add_number
<= 0
1920 || imm_expr
->X_add_number
>= 64)
1922 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1925 imm_expr
->X_op
= O_absent
;
1928 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1929 || imm_expr
->X_op
!= O_constant
1930 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1931 || imm_expr
->X_add_number
<= 0
1932 || imm_expr
->X_add_number
>= 32)
1934 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1937 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1938 || imm_expr
->X_op
!= O_constant
1939 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1940 || imm_expr
->X_add_number
< 0
1941 || imm_expr
->X_add_number
>= 256)
1943 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1946 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1947 || imm_expr
->X_op
!= O_constant
1948 || imm_expr
->X_add_number
== 0
1949 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1951 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1954 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1955 || imm_expr
->X_op
!= O_constant
1956 || imm_expr
->X_add_number
== 0
1957 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1959 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1962 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1964 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1965 || imm_expr
->X_op
!= O_constant
1966 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1968 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1971 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1973 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1974 || imm_expr
->X_op
!= O_constant
1975 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1977 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1980 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1982 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1983 || imm_expr
->X_op
!= O_constant
1984 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1987 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1990 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1992 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1993 || imm_expr
->X_op
!= O_constant
1994 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1997 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2000 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2001 || imm_expr
->X_op
!= O_constant
2002 /* C.addiw, c.li, and c.andi allow zero immediate.
2003 C.addi allows zero immediate as hint. Otherwise this
2005 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
2007 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2010 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2011 || imm_expr
->X_op
!= O_constant
2012 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
2013 || imm_expr
->X_add_number
== 0)
2016 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2019 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2020 || imm_expr
->X_op
!= O_constant
2021 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2022 || imm_expr
->X_add_number
== 0)
2025 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2028 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2030 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2031 || imm_expr
->X_op
!= O_constant
2032 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2035 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2038 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2040 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2041 || imm_expr
->X_op
!= O_constant
2042 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2045 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2048 p
= percent_op_utype
;
2049 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2052 if (imm_expr
->X_op
!= O_constant
2053 || imm_expr
->X_add_number
<= 0
2054 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2055 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2056 && (imm_expr
->X_add_number
<
2057 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2059 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2062 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2063 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2064 || ((int32_t)imm_expr
->X_add_number
2065 != imm_expr
->X_add_number
))
2067 imm_expr
->X_add_number
=
2068 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2074 case 'S': /* Floating-point RS1 x8-x15. */
2075 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2076 || !(regno
>= 8 && regno
<= 15))
2078 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2080 case 'D': /* Floating-point RS2 x8-x15. */
2081 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2082 || !(regno
>= 8 && regno
<= 15))
2084 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2086 case 'T': /* Floating-point RS2. */
2087 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2089 INSERT_OPERAND (CRS2
, *ip
, regno
);
2095 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2096 || imm_expr
->X_op
!= O_constant
2097 || imm_expr
->X_add_number
< 0
2098 || imm_expr
->X_add_number
>= 64)
2100 as_bad (_("bad value for funct6 field, "
2101 "value must be 0...64"));
2105 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2106 imm_expr
->X_op
= O_absent
;
2110 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2111 || imm_expr
->X_op
!= O_constant
2112 || imm_expr
->X_add_number
< 0
2113 || imm_expr
->X_add_number
>= 16)
2115 as_bad (_("bad value for funct4 field, "
2116 "value must be 0...15"));
2120 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2121 imm_expr
->X_op
= O_absent
;
2125 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2126 || imm_expr
->X_op
!= O_constant
2127 || imm_expr
->X_add_number
< 0
2128 || imm_expr
->X_add_number
>= 8)
2130 as_bad (_("bad value for funct3 field, "
2131 "value must be 0...7"));
2134 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2135 imm_expr
->X_op
= O_absent
;
2139 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2140 || imm_expr
->X_op
!= O_constant
2141 || imm_expr
->X_add_number
< 0
2142 || imm_expr
->X_add_number
>= 4)
2144 as_bad (_("bad value for funct2 field, "
2145 "value must be 0...3"));
2148 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2149 imm_expr
->X_op
= O_absent
;
2153 as_bad (_("bad compressed FUNCT field"
2154 " specifier 'CF%c'\n"),
2160 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2179 case '<': /* Shift amount, 0 - 31. */
2180 my_getExpression (imm_expr
, s
);
2181 check_absolute_expr (ip
, imm_expr
, FALSE
);
2182 if ((unsigned long) imm_expr
->X_add_number
> 31)
2183 as_bad (_("Improper shift amount (%lu)"),
2184 (unsigned long) imm_expr
->X_add_number
);
2185 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2186 imm_expr
->X_op
= O_absent
;
2190 case '>': /* Shift amount, 0 - (XLEN-1). */
2191 my_getExpression (imm_expr
, s
);
2192 check_absolute_expr (ip
, imm_expr
, FALSE
);
2193 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2194 as_bad (_("Improper shift amount (%lu)"),
2195 (unsigned long) imm_expr
->X_add_number
);
2196 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2197 imm_expr
->X_op
= O_absent
;
2201 case 'Z': /* CSRRxI immediate. */
2202 my_getExpression (imm_expr
, s
);
2203 check_absolute_expr (ip
, imm_expr
, FALSE
);
2204 if ((unsigned long) imm_expr
->X_add_number
> 31)
2205 as_bad (_("Improper CSRxI immediate (%lu)"),
2206 (unsigned long) imm_expr
->X_add_number
);
2207 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2208 imm_expr
->X_op
= O_absent
;
2212 case 'E': /* Control register. */
2213 insn_with_csr
= TRUE
;
2214 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2215 INSERT_OPERAND (CSR
, *ip
, regno
);
2218 my_getExpression (imm_expr
, s
);
2219 check_absolute_expr (ip
, imm_expr
, TRUE
);
2220 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2221 as_bad (_("Improper CSR address (%lu)"),
2222 (unsigned long) imm_expr
->X_add_number
);
2223 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2224 imm_expr
->X_op
= O_absent
;
2229 case 'm': /* Rounding mode. */
2230 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2232 INSERT_OPERAND (RM
, *ip
, regno
);
2238 case 'Q': /* Fence predecessor/successor. */
2239 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2243 INSERT_OPERAND (PRED
, *ip
, regno
);
2245 INSERT_OPERAND (SUCC
, *ip
, regno
);
2250 case 'd': /* Destination register. */
2251 case 's': /* Source register. */
2252 case 't': /* Target register. */
2253 case 'r': /* rs3. */
2254 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2260 /* Now that we have assembled one operand, we use the args
2261 string to figure out where it goes in the instruction. */
2265 INSERT_OPERAND (RS1
, *ip
, regno
);
2268 INSERT_OPERAND (RD
, *ip
, regno
);
2271 INSERT_OPERAND (RS2
, *ip
, regno
);
2274 INSERT_OPERAND (RS3
, *ip
, regno
);
2281 case 'D': /* Floating point rd. */
2282 case 'S': /* Floating point rs1. */
2283 case 'T': /* Floating point rs2. */
2284 case 'U': /* Floating point rs1 and rs2. */
2285 case 'R': /* Floating point rs3. */
2286 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2294 INSERT_OPERAND (RD
, *ip
, regno
);
2297 INSERT_OPERAND (RS1
, *ip
, regno
);
2300 INSERT_OPERAND (RS1
, *ip
, regno
);
2303 INSERT_OPERAND (RS2
, *ip
, regno
);
2306 INSERT_OPERAND (RS3
, *ip
, regno
);
2315 my_getExpression (imm_expr
, s
);
2316 if (imm_expr
->X_op
!= O_big
2317 && imm_expr
->X_op
!= O_constant
)
2319 normalize_constant_expr (imm_expr
);
2324 my_getExpression (imm_expr
, s
);
2325 normalize_constant_expr (imm_expr
);
2326 /* The 'A' format specifier must be a symbol. */
2327 if (imm_expr
->X_op
!= O_symbol
)
2329 *imm_reloc
= BFD_RELOC_32
;
2334 my_getExpression (imm_expr
, s
);
2335 normalize_constant_expr (imm_expr
);
2336 /* The 'B' format specifier must be a symbol or a constant. */
2337 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2339 if (imm_expr
->X_op
== O_symbol
)
2340 *imm_reloc
= BFD_RELOC_32
;
2344 case 'j': /* Sign-extended immediate. */
2345 p
= percent_op_itype
;
2346 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2348 case 'q': /* Store displacement. */
2349 p
= percent_op_stype
;
2350 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2352 case 'o': /* Load displacement. */
2353 p
= percent_op_itype
;
2354 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2356 case '1': /* 4-operand add, must be %tprel_add. */
2357 p
= percent_op_rtype
;
2359 case '0': /* AMO "displacement," which must be zero. */
2360 p
= percent_op_null
;
2362 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2365 /* If this value won't fit into a 16 bit offset, then go
2366 find a macro that will generate the 32 bit offset
2368 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2370 normalize_constant_expr (imm_expr
);
2371 if (imm_expr
->X_op
!= O_constant
2372 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2374 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2375 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2382 case 'p': /* PC-relative offset. */
2384 *imm_reloc
= BFD_RELOC_12_PCREL
;
2385 my_getExpression (imm_expr
, s
);
2389 case 'u': /* Upper 20 bits. */
2390 p
= percent_op_utype
;
2391 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2393 if (imm_expr
->X_op
!= O_constant
)
2396 if (imm_expr
->X_add_number
< 0
2397 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2398 as_bad (_("lui expression not in range 0..1048575"));
2400 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2401 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2406 case 'a': /* 20-bit PC-relative offset. */
2408 my_getExpression (imm_expr
, s
);
2410 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2414 my_getExpression (imm_expr
, s
);
2416 if (strcmp (s
, "@plt") == 0)
2418 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2422 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2428 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2429 || imm_expr
->X_op
!= O_constant
2430 || imm_expr
->X_add_number
< 0
2431 || imm_expr
->X_add_number
>= 128
2432 || (imm_expr
->X_add_number
& 0x3) != 3)
2434 as_bad (_("bad value for opcode field, "
2435 "value must be 0...127 and "
2436 "lower 2 bits must be 0x3"));
2440 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2441 imm_expr
->X_op
= O_absent
;
2445 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2446 || imm_expr
->X_op
!= O_constant
2447 || imm_expr
->X_add_number
< 0
2448 || imm_expr
->X_add_number
>= 3)
2450 as_bad (_("bad value for opcode field, "
2451 "value must be 0...2"));
2455 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2456 imm_expr
->X_op
= O_absent
;
2460 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2468 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2469 || imm_expr
->X_op
!= O_constant
2470 || imm_expr
->X_add_number
< 0
2471 || imm_expr
->X_add_number
>= 128)
2473 as_bad (_("bad value for funct7 field, "
2474 "value must be 0...127"));
2478 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2479 imm_expr
->X_op
= O_absent
;
2483 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2484 || imm_expr
->X_op
!= O_constant
2485 || imm_expr
->X_add_number
< 0
2486 || imm_expr
->X_add_number
>= 8)
2488 as_bad (_("bad value for funct3 field, "
2489 "value must be 0...7"));
2493 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2494 imm_expr
->X_op
= O_absent
;
2498 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2499 || imm_expr
->X_op
!= O_constant
2500 || imm_expr
->X_add_number
< 0
2501 || imm_expr
->X_add_number
>= 4)
2503 as_bad (_("bad value for funct2 field, "
2504 "value must be 0...3"));
2508 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2509 imm_expr
->X_op
= O_absent
;
2514 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2519 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2520 || imm_expr
->X_op
!= O_constant
2521 || imm_expr
->X_add_number
!= 0)
2524 imm_expr
->X_op
= O_absent
;
2528 as_fatal (_("internal error: bad argument type %c"), *args
);
2533 error
= _("illegal operands");
2534 insn_with_csr
= FALSE
;
2538 /* Restore the character we might have clobbered above. */
2540 *(argsStart
- 1) = save_c
;
2546 md_assemble (char *str
)
2548 struct riscv_cl_insn insn
;
2549 expressionS imm_expr
;
2550 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2552 /* The arch and priv attributes should be set before assembling. */
2553 if (!start_assemble
)
2555 start_assemble
= TRUE
;
2557 /* Set the default_priv_spec according to the priv attributes. */
2558 if (!riscv_set_default_priv_spec (NULL
))
2562 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2566 as_bad ("%s `%s'", error
, str
);
2570 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2571 macro (&insn
, &imm_expr
, &imm_reloc
);
2573 append_insn (&insn
, &imm_expr
, imm_reloc
);
2577 md_atof (int type
, char *litP
, int *sizeP
)
2579 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2583 md_number_to_chars (char *buf
, valueT val
, int n
)
2585 number_to_chars_littleendian (buf
, val
, n
);
2588 const char *md_shortopts
= "O::g::G:";
2592 OPTION_MARCH
= OPTION_MD_BASE
,
2599 OPTION_NO_ARCH_ATTR
,
2601 OPTION_NO_CSR_CHECK
,
2607 struct option md_longopts
[] =
2609 {"march", required_argument
, NULL
, OPTION_MARCH
},
2610 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2611 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2612 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2613 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2614 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2615 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2616 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2617 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2618 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2619 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2620 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2621 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2623 {NULL
, no_argument
, NULL
, 0}
2625 size_t md_longopts_size
= sizeof (md_longopts
);
2628 FLOAT_ABI_DEFAULT
= -1,
2634 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2637 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2639 abi_xlen
= new_xlen
;
2640 float_abi
= new_float_abi
;
2645 md_parse_option (int c
, const char *arg
)
2650 /* riscv_after_parse_args will call riscv_set_arch to parse
2651 the architecture. */
2652 default_arch_with_ext
= arg
;
2656 riscv_opts
.pic
= FALSE
;
2660 riscv_opts
.pic
= TRUE
;
2664 if (strcmp (arg
, "ilp32") == 0)
2665 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2666 else if (strcmp (arg
, "ilp32e") == 0)
2667 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2668 else if (strcmp (arg
, "ilp32f") == 0)
2669 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2670 else if (strcmp (arg
, "ilp32d") == 0)
2671 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2672 else if (strcmp (arg
, "ilp32q") == 0)
2673 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2674 else if (strcmp (arg
, "lp64") == 0)
2675 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2676 else if (strcmp (arg
, "lp64f") == 0)
2677 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2678 else if (strcmp (arg
, "lp64d") == 0)
2679 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2680 else if (strcmp (arg
, "lp64q") == 0)
2681 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2687 riscv_opts
.relax
= TRUE
;
2690 case OPTION_NO_RELAX
:
2691 riscv_opts
.relax
= FALSE
;
2694 case OPTION_ARCH_ATTR
:
2695 riscv_opts
.arch_attr
= TRUE
;
2698 case OPTION_NO_ARCH_ATTR
:
2699 riscv_opts
.arch_attr
= FALSE
;
2702 case OPTION_CSR_CHECK
:
2703 riscv_opts
.csr_check
= TRUE
;
2706 case OPTION_NO_CSR_CHECK
:
2707 riscv_opts
.csr_check
= FALSE
;
2710 case OPTION_MISA_SPEC
:
2711 return riscv_set_default_isa_spec (arg
);
2713 case OPTION_MPRIV_SPEC
:
2714 return riscv_set_default_priv_spec (arg
);
2724 riscv_after_parse_args (void)
2726 /* The --with-arch is optional for now, so we have to set the xlen
2727 according to the default_arch, which is set by the --targte, first.
2728 Then, we use the xlen to set the default_arch_with_ext if the
2729 -march and --with-arch are not set. */
2732 if (strcmp (default_arch
, "riscv32") == 0)
2734 else if (strcmp (default_arch
, "riscv64") == 0)
2737 as_bad ("unknown default architecture `%s'", default_arch
);
2739 if (default_arch_with_ext
== NULL
)
2740 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2742 /* Initialize the hash table for extensions with default version. */
2743 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2745 /* If the -misa-spec isn't set, then we set the default ISA spec according
2746 to DEFAULT_RISCV_ISA_SPEC. */
2747 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2748 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2750 /* Set the architecture according to -march or or --with-arch. */
2751 riscv_set_arch (default_arch_with_ext
);
2753 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2754 riscv_set_rvc (FALSE
);
2755 if (riscv_subset_supports ("c"))
2756 riscv_set_rvc (TRUE
);
2758 /* Enable RVE if specified by the -march option. */
2759 riscv_set_rve (FALSE
);
2760 if (riscv_subset_supports ("e"))
2761 riscv_set_rve (TRUE
);
2763 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2764 according to DEFAULT_PRIV_SPEC. */
2765 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2766 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2768 /* Infer ABI from ISA if not specified on command line. */
2771 else if (abi_xlen
> xlen
)
2772 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2773 else if (abi_xlen
< xlen
)
2774 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2776 if (float_abi
== FLOAT_ABI_DEFAULT
)
2778 riscv_subset_t
*subset
;
2780 /* Assume soft-float unless D extension is present. */
2781 float_abi
= FLOAT_ABI_SOFT
;
2783 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2785 if (strcasecmp (subset
->name
, "D") == 0)
2786 float_abi
= FLOAT_ABI_DOUBLE
;
2787 if (strcasecmp (subset
->name
, "Q") == 0)
2788 float_abi
= FLOAT_ABI_QUAD
;
2793 elf_flags
|= EF_RISCV_RVE
;
2795 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2796 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2798 /* If the CIE to be produced has not been overridden on the command line,
2799 then produce version 3 by default. This allows us to use the full
2800 range of registers in a .cfi_return_column directive. */
2801 if (flag_dwarf_cie_version
== -1)
2802 flag_dwarf_cie_version
= 3;
2806 md_pcrel_from (fixS
*fixP
)
2808 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2811 /* Apply a fixup to the object file. */
2814 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2816 unsigned int subtype
;
2817 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2818 bfd_boolean relaxable
= FALSE
;
2822 /* Remember value for tc_gen_reloc. */
2823 fixP
->fx_addnumber
= *valP
;
2825 switch (fixP
->fx_r_type
)
2827 case BFD_RELOC_RISCV_HI20
:
2828 case BFD_RELOC_RISCV_LO12_I
:
2829 case BFD_RELOC_RISCV_LO12_S
:
2830 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2831 | bfd_getl32 (buf
), buf
);
2832 if (fixP
->fx_addsy
== NULL
)
2833 fixP
->fx_done
= TRUE
;
2837 case BFD_RELOC_RISCV_GOT_HI20
:
2838 case BFD_RELOC_RISCV_ADD8
:
2839 case BFD_RELOC_RISCV_ADD16
:
2840 case BFD_RELOC_RISCV_ADD32
:
2841 case BFD_RELOC_RISCV_ADD64
:
2842 case BFD_RELOC_RISCV_SUB6
:
2843 case BFD_RELOC_RISCV_SUB8
:
2844 case BFD_RELOC_RISCV_SUB16
:
2845 case BFD_RELOC_RISCV_SUB32
:
2846 case BFD_RELOC_RISCV_SUB64
:
2847 case BFD_RELOC_RISCV_RELAX
:
2850 case BFD_RELOC_RISCV_TPREL_HI20
:
2851 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2852 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2853 case BFD_RELOC_RISCV_TPREL_ADD
:
2857 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2858 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2859 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2860 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2861 if (fixP
->fx_addsy
!= NULL
)
2862 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2865 _("TLS relocation against a constant"));
2869 /* Use pc-relative relocation for FDE initial location.
2870 The symbol address in .eh_frame may be adjusted in
2871 _bfd_elf_discard_section_eh_frame, and the content of
2872 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2873 Therefore, we cannot insert a relocation whose addend symbol is
2874 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2875 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2876 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2877 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2878 && S_GET_VALUE (fixP
->fx_subsy
)
2879 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2881 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2882 fixP
->fx_subsy
= NULL
;
2889 case BFD_RELOC_RISCV_CFA
:
2890 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2892 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2893 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2894 fixP
->fx_next
->fx_subsy
= NULL
;
2895 fixP
->fx_next
->fx_offset
= 0;
2896 fixP
->fx_subsy
= NULL
;
2898 switch (fixP
->fx_r_type
)
2901 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2902 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2906 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2907 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2911 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2912 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2916 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2917 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2920 case BFD_RELOC_RISCV_CFA
:
2921 /* Load the byte to get the subtype. */
2922 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2923 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2926 case DW_CFA_advance_loc1
:
2927 fixP
->fx_where
= loc
+ 1;
2928 fixP
->fx_next
->fx_where
= loc
+ 1;
2929 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2930 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2933 case DW_CFA_advance_loc2
:
2935 fixP
->fx_next
->fx_size
= 2;
2936 fixP
->fx_where
= loc
+ 1;
2937 fixP
->fx_next
->fx_where
= loc
+ 1;
2938 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2939 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2942 case DW_CFA_advance_loc4
:
2944 fixP
->fx_next
->fx_size
= 4;
2945 fixP
->fx_where
= loc
;
2946 fixP
->fx_next
->fx_where
= loc
;
2947 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2948 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2952 if (subtype
< 0x80 && (subtype
& 0x40))
2954 /* DW_CFA_advance_loc */
2955 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2956 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2957 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2958 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2961 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2967 /* This case is unreachable. */
2974 /* If we are deleting this reloc entry, we must fill in the
2975 value now. This can happen if we have a .word which is not
2976 resolved when it appears but is later defined. */
2977 if (fixP
->fx_addsy
== NULL
)
2979 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2980 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2985 case BFD_RELOC_RISCV_JMP
:
2988 /* Fill in a tentative value to improve objdump readability. */
2989 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2990 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2991 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2995 case BFD_RELOC_12_PCREL
:
2998 /* Fill in a tentative value to improve objdump readability. */
2999 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3000 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3001 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3005 case BFD_RELOC_RISCV_RVC_BRANCH
:
3008 /* Fill in a tentative value to improve objdump readability. */
3009 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3010 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3011 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3015 case BFD_RELOC_RISCV_RVC_JUMP
:
3018 /* Fill in a tentative value to improve objdump readability. */
3019 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3020 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3021 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3025 case BFD_RELOC_RISCV_CALL
:
3026 case BFD_RELOC_RISCV_CALL_PLT
:
3030 case BFD_RELOC_RISCV_PCREL_HI20
:
3031 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3032 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3033 relaxable
= riscv_opts
.relax
;
3036 case BFD_RELOC_RISCV_ALIGN
:
3040 /* We ignore generic BFD relocations we don't know about. */
3041 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3042 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3045 if (fixP
->fx_subsy
!= NULL
)
3046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3047 _("unsupported symbol subtraction"));
3049 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3050 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3052 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3053 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3054 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3058 /* Because the value of .cfi_remember_state may changed after relaxation,
3059 we insert a fix to relocate it again in link-time. */
3062 riscv_pre_output_hook (void)
3064 const frchainS
*frch
;
3067 /* Save the current segment info. */
3069 subsegT subseg
= now_subseg
;
3071 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3072 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3076 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3078 if (frag
->fr_type
== rs_cfa
)
3081 expressionS
*symval
;
3083 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3084 exp
.X_op
= O_subtract
;
3085 exp
.X_add_symbol
= symval
->X_add_symbol
;
3086 exp
.X_add_number
= 0;
3087 exp
.X_op_symbol
= symval
->X_op_symbol
;
3089 /* We must set the segment before creating a frag after all
3090 frag chains have been chained together. */
3091 subseg_set (s
, frch
->frch_subseg
);
3093 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3094 BFD_RELOC_RISCV_CFA
);
3099 /* Restore the original segment info. */
3100 subseg_set (seg
, subseg
);
3104 /* This structure is used to hold a stack of .option values. */
3106 struct riscv_option_stack
3108 struct riscv_option_stack
*next
;
3109 struct riscv_set_options options
;
3112 static struct riscv_option_stack
*riscv_opts_stack
;
3114 /* Handle the .option pseudo-op. */
3117 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3119 char *name
= input_line_pointer
, ch
;
3121 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3122 ++input_line_pointer
;
3123 ch
= *input_line_pointer
;
3124 *input_line_pointer
= '\0';
3126 if (strcmp (name
, "rvc") == 0)
3127 riscv_set_rvc (TRUE
);
3128 else if (strcmp (name
, "norvc") == 0)
3129 riscv_set_rvc (FALSE
);
3130 else if (strcmp (name
, "pic") == 0)
3131 riscv_opts
.pic
= TRUE
;
3132 else if (strcmp (name
, "nopic") == 0)
3133 riscv_opts
.pic
= FALSE
;
3134 else if (strcmp (name
, "relax") == 0)
3135 riscv_opts
.relax
= TRUE
;
3136 else if (strcmp (name
, "norelax") == 0)
3137 riscv_opts
.relax
= FALSE
;
3138 else if (strcmp (name
, "csr-check") == 0)
3139 riscv_opts
.csr_check
= TRUE
;
3140 else if (strcmp (name
, "no-csr-check") == 0)
3141 riscv_opts
.csr_check
= FALSE
;
3142 else if (strcmp (name
, "push") == 0)
3144 struct riscv_option_stack
*s
;
3146 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3147 s
->next
= riscv_opts_stack
;
3148 s
->options
= riscv_opts
;
3149 riscv_opts_stack
= s
;
3151 else if (strcmp (name
, "pop") == 0)
3153 struct riscv_option_stack
*s
;
3155 s
= riscv_opts_stack
;
3157 as_bad (_(".option pop with no .option push"));
3160 riscv_opts
= s
->options
;
3161 riscv_opts_stack
= s
->next
;
3167 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3169 *input_line_pointer
= ch
;
3170 demand_empty_rest_of_line ();
3173 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3174 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3175 use in DWARF debug information. */
3178 s_dtprel (int bytes
)
3185 if (ex
.X_op
!= O_symbol
)
3187 as_bad (_("Unsupported use of %s"), (bytes
== 8
3190 ignore_rest_of_line ();
3193 p
= frag_more (bytes
);
3194 md_number_to_chars (p
, 0, bytes
);
3195 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3197 ? BFD_RELOC_RISCV_TLS_DTPREL64
3198 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3200 demand_empty_rest_of_line ();
3203 /* Handle the .bss pseudo-op. */
3206 s_bss (int ignore ATTRIBUTE_UNUSED
)
3208 subseg_set (bss_section
, 0);
3209 demand_empty_rest_of_line ();
3213 riscv_make_nops (char *buf
, bfd_vma bytes
)
3217 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3218 means we are not within a valid instruction sequence. It is thus safe
3219 to use a zero byte, even though that is not a valid instruction. */
3223 /* Use at most one 2-byte NOP. */
3224 if ((bytes
- i
) % 4 == 2)
3226 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3230 /* Fill the remainder with 4-byte NOPs. */
3231 for ( ; i
< bytes
; i
+= 4)
3232 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3235 /* Called from md_do_align. Used to create an alignment frag in a
3236 code section by emitting a worst-case NOP sequence that the linker
3237 will later relax to the correct number of NOPs. We can't compute
3238 the correct alignment now because of other linker relaxations. */
3241 riscv_frag_align_code (int n
)
3243 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3244 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3245 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3249 /* If we are moving to a smaller alignment than the instruction size, then no
3250 alignment is required. */
3251 if (bytes
<= insn_alignment
)
3254 /* When not relaxing, riscv_handle_align handles code alignment. */
3255 if (!riscv_opts
.relax
)
3258 nops
= frag_more (worst_case_bytes
);
3260 ex
.X_op
= O_constant
;
3261 ex
.X_add_number
= worst_case_bytes
;
3263 riscv_make_nops (nops
, worst_case_bytes
);
3265 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3266 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3271 /* Implement HANDLE_ALIGN. */
3274 riscv_handle_align (fragS
*fragP
)
3276 switch (fragP
->fr_type
)
3279 /* When relaxing, riscv_frag_align_code handles code alignment. */
3280 if (!riscv_opts
.relax
)
3282 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3283 - fragP
->fr_address
- fragP
->fr_fix
);
3284 /* We have 4 byte uncompressed nops. */
3285 bfd_signed_vma size
= 4;
3286 bfd_signed_vma excess
= bytes
% size
;
3287 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3292 /* Insert zeros or compressed nops to get 4 byte alignment. */
3295 riscv_make_nops (p
, excess
);
3296 fragP
->fr_fix
+= excess
;
3300 /* Insert variable number of 4 byte uncompressed nops. */
3301 riscv_make_nops (p
, size
);
3302 fragP
->fr_var
= size
;
3312 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3314 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3317 /* Translate internal representation of relocation info to BFD target
3321 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3323 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3325 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3326 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3327 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3328 reloc
->addend
= fixp
->fx_addnumber
;
3330 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3331 if (reloc
->howto
== NULL
)
3333 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3334 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3336 /* We don't have R_RISCV_8/16, but for this special case,
3337 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3341 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3342 _("cannot represent %s relocation in object file"),
3343 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3351 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3353 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3355 offsetT old_var
= fragp
->fr_var
;
3356 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3357 return fragp
->fr_var
- old_var
;
3363 /* Expand far branches to multi-instruction sequences. */
3366 md_convert_frag_branch (fragS
*fragp
)
3374 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3376 exp
.X_op
= O_symbol
;
3377 exp
.X_add_symbol
= fragp
->fr_symbol
;
3378 exp
.X_add_number
= fragp
->fr_offset
;
3380 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3382 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3384 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3388 /* Expand the RVC branch into a RISC-V one. */
3389 insn
= bfd_getl16 (buf
);
3390 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3391 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3393 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3394 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3395 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3396 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3397 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3398 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3401 bfd_putl32 (insn
, buf
);
3405 /* Invert the branch condition. Branch over the jump. */
3406 insn
= bfd_getl16 (buf
);
3407 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3408 insn
|= ENCODE_RVC_B_IMM (6);
3409 bfd_putl16 (insn
, buf
);
3414 /* Just keep the RVC branch. */
3415 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3416 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3417 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3418 2, &exp
, FALSE
, reloc
);
3427 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3430 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3432 /* Invert the branch condition. Branch over the jump. */
3433 insn
= bfd_getl32 (buf
);
3434 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3435 insn
|= ENCODE_SBTYPE_IMM (8);
3436 md_number_to_chars ((char *) buf
, insn
, 4);
3440 /* Jump to the target. */
3441 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3442 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3443 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3448 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3449 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3450 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3451 4, &exp
, FALSE
, reloc
);
3460 fixp
->fx_file
= fragp
->fr_file
;
3461 fixp
->fx_line
= fragp
->fr_line
;
3463 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3464 + fragp
->fr_fix
+ fragp
->fr_var
);
3466 fragp
->fr_fix
+= fragp
->fr_var
;
3469 /* Relax a machine dependent frag. This returns the amount by which
3470 the current size of the frag should change. */
3473 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3476 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3477 md_convert_frag_branch (fragp
);
3481 md_show_usage (FILE *stream
)
3483 fprintf (stream
, _("\
3485 -fpic generate position-independent code\n\
3486 -fno-pic don't generate position-independent code (default)\n\
3487 -march=ISA set the RISC-V architecture\n\
3488 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3489 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3490 -mabi=ABI set the RISC-V ABI\n\
3491 -mrelax enable relax (default)\n\
3492 -mno-relax disable relax\n\
3493 -march-attr generate RISC-V arch attribute\n\
3494 -mno-arch-attr don't generate RISC-V arch attribute\n\
3498 /* Standard calling conventions leave the CFA at SP on entry. */
3500 riscv_cfi_frame_initial_instructions (void)
3502 cfi_add_CFA_def_cfa_register (X_SP
);
3506 tc_riscv_regname_to_dw2regnum (char *regname
)
3510 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3513 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3516 /* CSRs are numbered 4096 -> 8191. */
3517 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3520 as_bad (_("unknown register `%s'"), regname
);
3525 riscv_elf_final_processing (void)
3527 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3530 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3531 since these directives break relaxation when used with symbol deltas. */
3534 s_riscv_leb128 (int sign
)
3537 char *save_in
= input_line_pointer
;
3540 if (exp
.X_op
!= O_constant
)
3541 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3542 demand_empty_rest_of_line ();
3544 input_line_pointer
= save_in
;
3545 return s_leb128 (sign
);
3548 /* Parse the .insn directive. */
3551 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3553 char *str
= input_line_pointer
;
3554 struct riscv_cl_insn insn
;
3555 expressionS imm_expr
;
3556 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3559 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3560 ++input_line_pointer
;
3562 save_c
= *input_line_pointer
;
3563 *input_line_pointer
= '\0';
3565 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3566 &imm_reloc
, insn_type_hash
);
3570 as_bad ("%s `%s'", error
, str
);
3574 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3575 append_insn (&insn
, &imm_expr
, imm_reloc
);
3578 *input_line_pointer
= save_c
;
3579 demand_empty_rest_of_line ();
3582 /* Update arch and priv attributes. If we don't set the corresponding ELF
3583 attributes, then try to output the default ones. */
3586 riscv_write_out_attrs (void)
3588 const char *arch_str
, *priv_str
, *p
;
3589 /* versions[0] is major, versions[1] is minor,
3590 and versions[3] is revision. */
3591 unsigned versions
[3] = {0}, number
= 0;
3594 /* Re-write arch attribute to normalize the arch string. */
3595 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3596 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3597 xfree ((void *)arch_str
);
3599 /* For the file without any instruction, we don't set the default_priv_spec
3600 according to the priv attributes since the md_assemble isn't called.
3601 Call riscv_set_default_priv_spec here for the above case, although
3602 it seems strange. */
3604 && !riscv_set_default_priv_spec (NULL
))
3607 /* Re-write priv attributes by default_priv_spec. */
3608 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3610 for (i
= 0; *p
; ++p
)
3612 if (*p
== '.' && i
< 3)
3614 versions
[i
++] = number
;
3617 else if (ISDIGIT (*p
))
3618 number
= (number
* 10) + (*p
- '0');
3621 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3625 versions
[i
] = number
;
3627 /* Set the priv attributes. */
3628 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3629 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3630 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3633 /* Add the default contents for the .riscv.attributes section. If any
3634 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3635 to update the arch and priv attributes. */
3638 riscv_set_public_attributes (void)
3640 if (riscv_opts
.arch_attr
|| explicit_attr
)
3641 riscv_write_out_attrs ();
3644 /* Called after all assembly has been done. */
3649 riscv_set_public_attributes ();
3652 /* Given a symbolic attribute NAME, return the proper integer value.
3653 Returns -1 if the attribute is not known. */
3656 riscv_convert_symbolic_attribute (const char *name
)
3665 /* When you modify this table you should
3666 also modify the list in doc/c-riscv.texi. */
3667 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3671 T(priv_spec_revision
),
3672 T(unaligned_access
),
3682 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3683 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3684 return attribute_table
[i
].tag
;
3689 /* Parse a .attribute directive. */
3692 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3694 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3696 obj_attribute
*attr
;
3698 explicit_attr
= TRUE
;
3701 case Tag_RISCV_arch
:
3703 attr
= elf_known_obj_attributes_proc (stdoutput
);
3704 if (!start_assemble
)
3705 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3707 as_fatal (_(".attribute arch must set before any instructions"));
3709 if (old_xlen
!= xlen
)
3711 /* We must re-init bfd again if xlen is changed. */
3712 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3713 bfd_find_target (riscv_target_format (), stdoutput
);
3715 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3716 as_warn (_("Could not set architecture and machine"));
3720 case Tag_RISCV_priv_spec
:
3721 case Tag_RISCV_priv_spec_minor
:
3722 case Tag_RISCV_priv_spec_revision
:
3724 as_fatal (_(".attribute priv spec must set before any instructions"));
3732 /* Pseudo-op table. */
3734 static const pseudo_typeS riscv_pseudo_table
[] =
3736 /* RISC-V-specific pseudo-ops. */
3737 {"option", s_riscv_option
, 0},
3741 {"dtprelword", s_dtprel
, 4},
3742 {"dtpreldword", s_dtprel
, 8},
3744 {"uleb128", s_riscv_leb128
, 0},
3745 {"sleb128", s_riscv_leb128
, 1},
3746 {"insn", s_riscv_insn
, 0},
3747 {"attribute", s_riscv_attribute
, 0},
3753 riscv_pop_insert (void)
3755 extern void pop_insert (const pseudo_typeS
*);
3757 pop_insert (riscv_pseudo_table
);