1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_clear_subsets (void)
126 while (riscv_subsets
!= NULL
)
128 struct riscv_subset
*next
= riscv_subsets
->next
;
129 free ((void *) riscv_subsets
->name
);
130 free (riscv_subsets
);
131 riscv_subsets
= next
;
136 riscv_add_subset (const char *subset
)
138 struct riscv_subset
*s
= xmalloc (sizeof *s
);
140 s
->name
= xstrdup (subset
);
141 s
->next
= riscv_subsets
;
145 /* Set which ISA and extensions are available. */
148 riscv_set_arch (const char *s
)
150 const char *all_subsets
= "imafdqc";
151 char *extension
= NULL
;
154 riscv_clear_subsets();
156 if (strncmp (p
, "rv32", 4) == 0)
161 else if (strncmp (p
, "rv64", 4) == 0)
167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
176 for ( ; *all_subsets
!= 'q'; all_subsets
++)
178 const char subset
[] = {*all_subsets
, '\0'};
179 riscv_add_subset (subset
);
184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
191 char *subset
= xstrdup (p
);
194 while (*++q
!= '\0' && *q
!= '_')
199 as_fatal ("-march=%s: only one non-standard extension is supported"
200 " (found `%s' and `%s')", s
, extension
, subset
);
202 riscv_add_subset (subset
);
203 p
+= strlen (subset
);
207 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
209 const char subset
[] = {*p
, 0};
210 riscv_add_subset (subset
);
215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
221 /* Handle of the OPCODE hash table. */
222 static struct hash_control
*op_hash
= NULL
;
224 /* This array holds the chars that always start a comment. If the
225 pre-processor is disabled, these aren't very useful */
226 const char comment_chars
[] = "#";
228 /* This array holds the chars that only start a comment at the beginning of
229 a line. If the line seems to have the form '# 123 filename'
230 .line and .file directives will appear in the pre-processed output */
231 /* Note that input_file.c hand checks for '#' at the beginning of the
232 first line of the input file. This is because the compiler outputs
233 #NO_APP at the beginning of its output. */
234 /* Also note that C style comments are always supported. */
235 const char line_comment_chars
[] = "#";
237 /* This array holds machine specific line separator characters. */
238 const char line_separator_chars
[] = ";";
240 /* Chars that can be used to separate mant from exp in floating point nums */
241 const char EXP_CHARS
[] = "eE";
243 /* Chars that mean this number is a floating point constant */
246 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
248 /* Macros for encoding relaxation state for RVC branches and far jumps. */
249 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
252 | ((uncond) ? 1 : 0) \
255 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
256 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
257 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
258 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
260 /* Is the given value a sign-extended 32-bit value? */
261 #define IS_SEXT_32BIT_NUM(x) \
262 (((x) &~ (offsetT) 0x7fffffff) == 0 \
263 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
265 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
266 #define IS_ZEXT_32BIT_NUM(x) \
267 (((x) &~ (offsetT) 0xffffffff) == 0 \
268 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
270 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
271 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
272 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
273 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
275 /* Determine if an instruction matches an opcode. */
276 #define OPCODE_MATCHES(OPCODE, OP) \
277 (((OPCODE) & MASK_##OP) == MATCH_##OP)
279 static char *expr_end
;
281 /* The default target format to use. */
284 riscv_target_format (void)
286 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
289 /* Return the length of instruction INSN. */
291 static inline unsigned int
292 insn_length (const struct riscv_cl_insn
*insn
)
294 return riscv_insn_length (insn
->insn_opcode
);
297 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
300 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
303 insn
->insn_opcode
= mo
->match
;
309 /* Install INSN at the location specified by its "frag" and "where" fields. */
312 install_insn (const struct riscv_cl_insn
*insn
)
314 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
315 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
318 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
319 and install the opcode in the new location. */
322 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
326 if (insn
->fixp
!= NULL
)
328 insn
->fixp
->fx_frag
= frag
;
329 insn
->fixp
->fx_where
= where
;
334 /* Add INSN to the end of the output. */
337 add_fixed_insn (struct riscv_cl_insn
*insn
)
339 char *f
= frag_more (insn_length (insn
));
340 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
344 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
345 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
347 frag_grow (max_chars
);
348 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
349 frag_var (rs_machine_dependent
, max_chars
, var
,
350 subtype
, symbol
, offset
, NULL
);
353 /* Compute the length of a branch sequence, and adjust the stored length
354 accordingly. If FRAGP is NULL, the worst-case length is returned. */
357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
359 int jump
, rvc
, length
= 8;
364 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
365 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
366 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
368 /* Assume jumps are in range; the linker will catch any that aren't. */
369 length
= jump
? 4 : 8;
371 if (fragp
->fr_symbol
!= NULL
372 && S_IS_DEFINED (fragp
->fr_symbol
)
373 && !S_IS_WEAK (fragp
->fr_symbol
)
374 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
376 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
377 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
378 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
380 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
382 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
384 else if (!jump
&& rvc
)
389 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
408 static struct hash_control
*reg_names_hash
= NULL
;
410 #define ENCODE_REG_HASH(cls, n) \
411 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
412 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
413 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
416 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
418 void *hash
= ENCODE_REG_HASH (class, n
);
419 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
422 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
426 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
430 for (i
= 0; i
< n
; i
++)
431 hash_reg_name (class, names
[i
], i
);
435 reg_lookup_internal (const char *s
, enum reg_class
class)
437 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
439 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
441 return DECODE_REG_NUM (r
);
445 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
451 /* Find end of name. */
453 if (is_name_beginner (*e
))
455 while (is_part_of_name (*e
))
458 /* Terminate name. */
462 /* Look for the register. Advance to next token if one was recognized. */
463 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
473 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
475 const char *p
= strchr (*s
, ',');
476 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
478 for (i
= 0; i
< size
; i
++)
479 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
489 /* For consistency checking, verify that all bits are specified either
490 by the match/mask part of the instruction definition, or by the
493 validate_riscv_insn (const struct riscv_opcode
*opc
)
495 const char *p
= opc
->args
;
497 insn_t used_bits
= opc
->mask
;
498 int insn_width
= 8 * riscv_insn_length (opc
->match
);
499 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
501 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
503 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
504 opc
->name
, opc
->args
);
508 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
515 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
516 case 'c': break; /* RS1, constrained to equal sp */
517 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
518 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
519 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
520 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
521 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
522 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
523 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
524 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
525 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
526 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
527 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
528 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
529 case 'w': break; /* RS1S, constrained to equal RD */
530 case 'x': break; /* RS2S, constrained to equal RD */
531 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
532 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
533 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
534 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
535 case 'U': break; /* RS1, constrained to equal RD */
536 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
537 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
538 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
539 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
540 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
542 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
543 c
, opc
->name
, opc
->args
);
550 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
551 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
553 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
554 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
555 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
557 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
558 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
559 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
560 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
561 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
562 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
563 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
564 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
565 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
566 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
568 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
569 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
570 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
571 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
572 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
577 as_bad (_("internal: bad RISC-V opcode "
578 "(unknown operand type `%c'): %s %s"),
579 c
, opc
->name
, opc
->args
);
583 if (used_bits
!= required_bits
)
585 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
586 ~(unsigned long)(used_bits
& required_bits
),
587 opc
->name
, opc
->args
);
593 struct percent_op_match
596 bfd_reloc_code_real_type reloc
;
599 /* This function is called once, at assembler startup time. It should set up
600 all the tables, etc. that the MD part of the assembler will need. */
606 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
608 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
609 as_warn (_("Could not set architecture and machine"));
611 op_hash
= hash_new ();
613 while (riscv_opcodes
[i
].name
)
615 const char *name
= riscv_opcodes
[i
].name
;
616 const char *hash_error
=
617 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
621 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
622 riscv_opcodes
[i
].name
, hash_error
);
623 /* Probably a memory allocation problem? Give up now. */
624 as_fatal (_("Broken assembler. No assembly attempted."));
629 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
631 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
632 as_fatal (_("Broken assembler. No assembly attempted."));
636 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
639 reg_names_hash
= hash_new ();
640 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
641 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
642 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
643 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
645 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
646 #include "opcode/riscv-opc.h"
649 /* Set the default alignment for the text section. */
650 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
654 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
661 case BFD_RELOC_RISCV_HI20
:
662 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
664 case BFD_RELOC_RISCV_LO12_S
:
665 return ENCODE_STYPE_IMM (value
);
667 case BFD_RELOC_RISCV_LO12_I
:
668 return ENCODE_ITYPE_IMM (value
);
675 /* Output an instruction. IP is the instruction information.
676 ADDRESS_EXPR is an operand of the instruction to be used with
680 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
681 bfd_reloc_code_real_type reloc_type
)
683 dwarf2_emit_insn (0);
685 if (reloc_type
!= BFD_RELOC_UNUSED
)
687 reloc_howto_type
*howto
;
689 gas_assert (address_expr
);
690 if (reloc_type
== BFD_RELOC_12_PCREL
691 || reloc_type
== BFD_RELOC_RISCV_JMP
)
693 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
694 int best_case
= riscv_insn_length (ip
->insn_opcode
);
695 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
696 add_relaxed_insn (ip
, worst_case
, best_case
,
697 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
698 address_expr
->X_add_symbol
,
699 address_expr
->X_add_number
);
704 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
706 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
708 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
709 bfd_get_reloc_size (howto
),
710 address_expr
, FALSE
, reloc_type
);
712 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
720 /* Build an instruction created by a macro expansion. This is passed
721 a pointer to the count of instructions created so far, an
722 expression, the name of the instruction to build, an operand format
723 string, and corresponding arguments. */
726 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
728 const struct riscv_opcode
*mo
;
729 struct riscv_cl_insn insn
;
730 bfd_reloc_code_real_type r
;
733 va_start (args
, fmt
);
735 r
= BFD_RELOC_UNUSED
;
736 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
739 /* Find a non-RVC variant of the instruction. append_insn will compress
741 while (riscv_insn_length (mo
->match
) < 4)
743 gas_assert (strcmp (name
, mo
->name
) == 0);
745 create_insn (&insn
, mo
);
751 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
755 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
759 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
763 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
769 gas_assert (ep
!= NULL
);
770 r
= va_arg (args
, int);
778 as_fatal (_("internal error: invalid macro"));
783 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
785 append_insn (&insn
, ep
, r
);
788 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
791 normalize_constant_expr (expressionS
*ex
)
795 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
796 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
797 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
801 /* Fail if an expression is not a constant. */
804 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
806 if (ex
->X_op
== O_big
)
807 as_bad (_("unsupported large constant"));
808 else if (ex
->X_op
!= O_constant
)
809 as_bad (_("Instruction %s requires absolute expression"),
811 normalize_constant_expr (ex
);
815 make_internal_label (void)
817 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
818 (valueT
) frag_now_fix (), frag_now
);
821 /* Load an entry from the GOT. */
823 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
824 const char *lo_insn
, const char *lo_pattern
,
825 bfd_reloc_code_real_type hi_reloc
,
826 bfd_reloc_code_real_type lo_reloc
)
830 ep2
.X_add_symbol
= make_internal_label ();
831 ep2
.X_add_number
= 0;
833 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
834 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
838 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
839 bfd_reloc_code_real_type hi_reloc
,
840 bfd_reloc_code_real_type lo_reloc
)
842 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
846 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
847 bfd_reloc_code_real_type hi_reloc
,
848 bfd_reloc_code_real_type lo_reloc
)
850 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
853 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
855 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
856 bfd_reloc_code_real_type reloc
)
858 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
859 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
862 /* Load an integer constant into a register. */
865 load_const (int reg
, expressionS
*ep
)
867 int shift
= RISCV_IMM_BITS
;
868 expressionS upper
= *ep
, lower
= *ep
;
869 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
870 upper
.X_add_number
-= lower
.X_add_number
;
872 if (ep
->X_op
!= O_constant
)
874 as_bad (_("unsupported large constant"));
878 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
880 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
881 while (((upper
.X_add_number
>> shift
) & 1) == 0)
884 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
885 load_const (reg
, &upper
);
887 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
888 if (lower
.X_add_number
!= 0)
889 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
893 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
896 if (upper
.X_add_number
!= 0)
898 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
902 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
903 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
904 BFD_RELOC_RISCV_LO12_I
);
908 /* Expand RISC-V assembly macros into one or more instructions. */
910 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
911 bfd_reloc_code_real_type
*imm_reloc
)
913 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
914 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
915 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
916 int mask
= ip
->insn_mo
->mask
;
921 load_const (rd
, imm_expr
);
926 /* Load the address of a symbol into a register. */
927 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
928 as_bad (_("offset too large"));
930 if (imm_expr
->X_op
== O_constant
)
931 load_const (rd
, imm_expr
);
932 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
933 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
934 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
935 else /* Local PIC symbol, or any non-PIC symbol */
936 pcrel_load (rd
, rd
, imm_expr
, "addi",
937 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
941 pcrel_load (rd
, rd
, imm_expr
, "addi",
942 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
946 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
947 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
951 pcrel_load (rd
, rd
, imm_expr
, "lb",
952 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
956 pcrel_load (rd
, rd
, imm_expr
, "lbu",
957 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
961 pcrel_load (rd
, rd
, imm_expr
, "lh",
962 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
966 pcrel_load (rd
, rd
, imm_expr
, "lhu",
967 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
971 pcrel_load (rd
, rd
, imm_expr
, "lw",
972 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
976 pcrel_load (rd
, rd
, imm_expr
, "lwu",
977 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
981 pcrel_load (rd
, rd
, imm_expr
, "ld",
982 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
986 pcrel_load (rd
, rs1
, imm_expr
, "flw",
987 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
991 pcrel_load (rd
, rs1
, imm_expr
, "fld",
992 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
996 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
997 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1001 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1002 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1006 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1007 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1011 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1012 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1016 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1017 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1021 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1022 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1026 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1030 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1035 static const struct percent_op_match percent_op_utype
[] =
1037 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1038 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1039 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1040 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1041 {"%hi", BFD_RELOC_RISCV_HI20
},
1045 static const struct percent_op_match percent_op_itype
[] =
1047 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1048 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1049 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1053 static const struct percent_op_match percent_op_stype
[] =
1055 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1056 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1057 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1061 static const struct percent_op_match percent_op_rtype
[] =
1063 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1067 /* Return true if *STR points to a relocation operator. When returning true,
1068 move *STR over the operator and store its relocation code in *RELOC.
1069 Leave both *STR and *RELOC alone when returning false. */
1072 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1073 const struct percent_op_match
*percent_op
)
1075 for ( ; percent_op
->str
; percent_op
++)
1076 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1078 int len
= strlen (percent_op
->str
);
1080 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1083 *str
+= strlen (percent_op
->str
);
1084 *reloc
= percent_op
->reloc
;
1086 /* Check whether the output BFD supports this relocation.
1087 If not, issue an error and fall back on something safe. */
1088 if (*reloc
!= BFD_RELOC_UNUSED
1089 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1091 as_bad ("relocation %s isn't supported by the current ABI",
1093 *reloc
= BFD_RELOC_UNUSED
;
1101 my_getExpression (expressionS
*ep
, char *str
)
1105 save_in
= input_line_pointer
;
1106 input_line_pointer
= str
;
1108 expr_end
= input_line_pointer
;
1109 input_line_pointer
= save_in
;
1112 /* Parse string STR as a 16-bit relocatable operand. Store the
1113 expression in *EP and the relocation, if any, in RELOC.
1114 Return the number of relocation operators used (0 or 1).
1116 On exit, EXPR_END points to the first character after the expression. */
1119 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1120 char *str
, const struct percent_op_match
*percent_op
)
1123 unsigned crux_depth
, str_depth
, regno
;
1126 /* First, check for integer registers. */
1127 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1129 ep
->X_op
= O_register
;
1130 ep
->X_add_number
= regno
;
1134 /* Search for the start of the main expression.
1135 End the loop with CRUX pointing to the start
1136 of the main expression and with CRUX_DEPTH containing the number
1137 of open brackets at that point. */
1144 crux_depth
= str_depth
;
1146 /* Skip over whitespace and brackets, keeping count of the number
1148 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1154 && parse_relocation (&str
, reloc
, percent_op
));
1156 my_getExpression (ep
, crux
);
1159 /* Match every open bracket. */
1160 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1165 as_bad ("unclosed '('");
1172 /* This routine assembles an instruction into its binary format. As a
1173 side effect, it sets the global variable imm_reloc to the type of
1174 relocation to do if one of the operands is an address expression. */
1177 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1178 bfd_reloc_code_real_type
*imm_reloc
)
1183 struct riscv_opcode
*insn
;
1188 const struct percent_op_match
*p
;
1189 const char *error
= "unrecognized opcode";
1191 /* Parse the name of the instruction. Terminate the string if whitespace
1192 is found so that hash_find only sees the name part of the string. */
1193 for (s
= str
; *s
!= '\0'; ++s
)
1201 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1204 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1206 if (!riscv_subset_supports (insn
->subset
))
1209 create_insn (ip
, insn
);
1212 imm_expr
->X_op
= O_absent
;
1213 *imm_reloc
= BFD_RELOC_UNUSED
;
1214 p
= percent_op_itype
;
1216 for (args
= insn
->args
;; ++args
)
1218 s
+= strspn (s
, " \t");
1221 case '\0': /* End of args. */
1222 if (insn
->pinfo
!= INSN_MACRO
)
1224 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1226 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1231 /* Successful assembly. */
1238 case 's': /* RS1 x8-x15 */
1239 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1240 || !(regno
>= 8 && regno
<= 15))
1242 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1244 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1245 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1246 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1249 case 't': /* RS2 x8-x15 */
1250 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1251 || !(regno
>= 8 && regno
<= 15))
1253 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1255 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1256 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1257 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1260 case 'U': /* RS1, constrained to equal RD. */
1261 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1262 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1266 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1268 INSERT_OPERAND (CRS2
, *ip
, regno
);
1270 case 'c': /* RS1, constrained to equal sp. */
1271 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1276 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1277 || imm_expr
->X_op
!= O_constant
1278 || imm_expr
->X_add_number
<= 0
1279 || imm_expr
->X_add_number
>= 64)
1281 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1284 imm_expr
->X_op
= O_absent
;
1287 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1288 || imm_expr
->X_op
!= O_constant
1289 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1290 || imm_expr
->X_add_number
<= 0
1291 || imm_expr
->X_add_number
>= 32)
1293 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1296 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1297 || imm_expr
->X_op
!= O_constant
1298 || imm_expr
->X_add_number
== 0
1299 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1301 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1304 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1305 || imm_expr
->X_op
!= O_constant
1306 || imm_expr
->X_add_number
== 0
1307 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1309 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1312 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1313 || imm_expr
->X_op
!= O_constant
1314 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1316 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1319 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1320 || imm_expr
->X_op
!= O_constant
1321 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1323 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1326 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1327 || imm_expr
->X_op
!= O_constant
1328 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1331 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1334 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1335 || imm_expr
->X_op
!= O_constant
1336 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1339 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1342 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1343 || imm_expr
->X_op
!= O_constant
1344 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1346 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1349 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1350 || imm_expr
->X_op
!= O_constant
1351 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1352 || imm_expr
->X_add_number
== 0)
1355 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1358 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1359 || imm_expr
->X_op
!= O_constant
1360 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1361 || imm_expr
->X_add_number
== 0)
1364 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1367 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1368 || imm_expr
->X_op
!= O_constant
1369 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1372 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1375 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1376 || imm_expr
->X_op
!= O_constant
1377 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1380 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1383 p
= percent_op_utype
;
1384 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1387 if (imm_expr
->X_op
!= O_constant
1388 || imm_expr
->X_add_number
<= 0
1389 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1390 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1391 && (imm_expr
->X_add_number
<
1392 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1394 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1397 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1398 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1399 || ((int32_t)imm_expr
->X_add_number
1400 != imm_expr
->X_add_number
))
1402 imm_expr
->X_add_number
=
1403 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1409 case 'D': /* Floating-point RS2 x8-x15. */
1410 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1411 || !(regno
>= 8 && regno
<= 15))
1413 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1415 case 'T': /* Floating-point RS2. */
1416 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1418 INSERT_OPERAND (CRS2
, *ip
, regno
);
1421 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1440 case '<': /* Shift amount, 0 - 31. */
1441 my_getExpression (imm_expr
, s
);
1442 check_absolute_expr (ip
, imm_expr
);
1443 if ((unsigned long) imm_expr
->X_add_number
> 31)
1444 as_bad (_("Improper shift amount (%lu)"),
1445 (unsigned long) imm_expr
->X_add_number
);
1446 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1447 imm_expr
->X_op
= O_absent
;
1451 case '>': /* Shift amount, 0 - (XLEN-1). */
1452 my_getExpression (imm_expr
, s
);
1453 check_absolute_expr (ip
, imm_expr
);
1454 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1455 as_bad (_("Improper shift amount (%lu)"),
1456 (unsigned long) imm_expr
->X_add_number
);
1457 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1458 imm_expr
->X_op
= O_absent
;
1462 case 'Z': /* CSRRxI immediate. */
1463 my_getExpression (imm_expr
, s
);
1464 check_absolute_expr (ip
, imm_expr
);
1465 if ((unsigned long) imm_expr
->X_add_number
> 31)
1466 as_bad (_("Improper CSRxI immediate (%lu)"),
1467 (unsigned long) imm_expr
->X_add_number
);
1468 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1469 imm_expr
->X_op
= O_absent
;
1473 case 'E': /* Control register. */
1474 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1475 INSERT_OPERAND (CSR
, *ip
, regno
);
1478 my_getExpression (imm_expr
, s
);
1479 check_absolute_expr (ip
, imm_expr
);
1480 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1481 as_bad (_("Improper CSR address (%lu)"),
1482 (unsigned long) imm_expr
->X_add_number
);
1483 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1484 imm_expr
->X_op
= O_absent
;
1489 case 'm': /* Rounding mode. */
1490 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1492 INSERT_OPERAND (RM
, *ip
, regno
);
1498 case 'Q': /* Fence predecessor/successor. */
1499 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1503 INSERT_OPERAND (PRED
, *ip
, regno
);
1505 INSERT_OPERAND (SUCC
, *ip
, regno
);
1510 case 'd': /* Destination register. */
1511 case 's': /* Source register. */
1512 case 't': /* Target register. */
1513 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1519 /* Now that we have assembled one operand, we use the args
1520 string to figure out where it goes in the instruction. */
1524 INSERT_OPERAND (RS1
, *ip
, regno
);
1527 INSERT_OPERAND (RD
, *ip
, regno
);
1530 INSERT_OPERAND (RS2
, *ip
, regno
);
1537 case 'D': /* Floating point rd. */
1538 case 'S': /* Floating point rs1. */
1539 case 'T': /* Floating point rs2. */
1540 case 'U': /* Floating point rs1 and rs2. */
1541 case 'R': /* Floating point rs3. */
1542 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1550 INSERT_OPERAND (RD
, *ip
, regno
);
1553 INSERT_OPERAND (RS1
, *ip
, regno
);
1556 INSERT_OPERAND (RS1
, *ip
, regno
);
1559 INSERT_OPERAND (RS2
, *ip
, regno
);
1562 INSERT_OPERAND (RS3
, *ip
, regno
);
1571 my_getExpression (imm_expr
, s
);
1572 if (imm_expr
->X_op
!= O_big
1573 && imm_expr
->X_op
!= O_constant
)
1575 normalize_constant_expr (imm_expr
);
1580 my_getExpression (imm_expr
, s
);
1581 normalize_constant_expr (imm_expr
);
1582 /* The 'A' format specifier must be a symbol. */
1583 if (imm_expr
->X_op
!= O_symbol
)
1585 *imm_reloc
= BFD_RELOC_32
;
1589 case 'j': /* Sign-extended immediate. */
1590 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1591 p
= percent_op_itype
;
1593 case 'q': /* Store displacement. */
1594 p
= percent_op_stype
;
1595 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1597 case 'o': /* Load displacement. */
1598 p
= percent_op_itype
;
1599 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1601 case '0': /* AMO "displacement," which must be zero. */
1602 p
= percent_op_rtype
;
1603 *imm_reloc
= BFD_RELOC_UNUSED
;
1605 /* Check whether there is only a single bracketed expression
1606 left. If so, it must be the base register and the
1607 constant must be zero. */
1608 imm_expr
->X_op
= O_constant
;
1609 imm_expr
->X_add_number
= 0;
1610 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1613 /* If this value won't fit into a 16 bit offset, then go
1614 find a macro that will generate the 32 bit offset
1616 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1618 normalize_constant_expr (imm_expr
);
1619 if (imm_expr
->X_op
!= O_constant
1620 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1621 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1622 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1629 case 'p': /* PC-relative offset. */
1631 *imm_reloc
= BFD_RELOC_12_PCREL
;
1632 my_getExpression (imm_expr
, s
);
1636 case 'u': /* Upper 20 bits. */
1637 p
= percent_op_utype
;
1638 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1639 && imm_expr
->X_op
== O_constant
)
1641 if (imm_expr
->X_add_number
< 0
1642 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1643 as_bad (_("lui expression not in range 0..1048575"));
1645 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1646 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1651 case 'a': /* 20-bit PC-relative offset. */
1653 my_getExpression (imm_expr
, s
);
1655 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1659 my_getExpression (imm_expr
, s
);
1661 if (strcmp (s
, "@plt") == 0)
1663 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1667 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1671 as_fatal (_("internal error: bad argument type %c"), *args
);
1676 error
= _("illegal operands");
1680 /* Restore the character we might have clobbered above. */
1682 *(argsStart
- 1) = save_c
;
1688 md_assemble (char *str
)
1690 struct riscv_cl_insn insn
;
1691 expressionS imm_expr
;
1692 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1694 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1698 as_bad ("%s `%s'", error
, str
);
1702 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1703 macro (&insn
, &imm_expr
, &imm_reloc
);
1705 append_insn (&insn
, &imm_expr
, imm_reloc
);
1709 md_atof (int type
, char *litP
, int *sizeP
)
1711 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1715 md_number_to_chars (char *buf
, valueT val
, int n
)
1717 number_to_chars_littleendian (buf
, val
, n
);
1720 const char *md_shortopts
= "O::g::G:";
1724 OPTION_MARCH
= OPTION_MD_BASE
,
1731 struct option md_longopts
[] =
1733 {"march", required_argument
, NULL
, OPTION_MARCH
},
1734 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1735 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1736 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1737 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1739 {NULL
, no_argument
, NULL
, 0}
1741 size_t md_longopts_size
= sizeof (md_longopts
);
1744 FLOAT_ABI_DEFAULT
= -1,
1750 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1753 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1755 abi_xlen
= new_xlen
;
1756 float_abi
= new_float_abi
;
1760 md_parse_option (int c
, const char *arg
)
1765 riscv_set_arch (arg
);
1769 riscv_opts
.pic
= FALSE
;
1773 riscv_opts
.pic
= TRUE
;
1777 if (strcmp (arg
, "ilp32") == 0)
1778 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1779 else if (strcmp (arg
, "ilp32f") == 0)
1780 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1781 else if (strcmp (arg
, "ilp32d") == 0)
1782 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1783 else if (strcmp (arg
, "ilp32q") == 0)
1784 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1785 else if (strcmp (arg
, "lp64") == 0)
1786 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1787 else if (strcmp (arg
, "lp64f") == 0)
1788 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1789 else if (strcmp (arg
, "lp64d") == 0)
1790 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1791 else if (strcmp (arg
, "lp64q") == 0)
1792 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1805 riscv_after_parse_args (void)
1809 if (strcmp (default_arch
, "riscv32") == 0)
1811 else if (strcmp (default_arch
, "riscv64") == 0)
1814 as_bad ("unknown default architecture `%s'", default_arch
);
1817 if (riscv_subsets
== NULL
)
1818 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1820 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1821 riscv_set_rvc (FALSE
);
1822 if (riscv_subset_supports ("c"))
1823 riscv_set_rvc (TRUE
);
1825 riscv_add_subset ("c");
1827 /* Infer ABI from ISA if not specified on command line. */
1830 else if (abi_xlen
> xlen
)
1831 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1832 else if (abi_xlen
< xlen
)
1833 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1835 if (float_abi
== FLOAT_ABI_DEFAULT
)
1837 struct riscv_subset
*subset
;
1839 /* Assume soft-float unless D extension is present. */
1840 float_abi
= FLOAT_ABI_SOFT
;
1842 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1844 if (strcasecmp (subset
->name
, "D") == 0)
1845 float_abi
= FLOAT_ABI_DOUBLE
;
1846 if (strcasecmp (subset
->name
, "Q") == 0)
1847 float_abi
= FLOAT_ABI_QUAD
;
1851 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1852 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1856 md_pcrel_from (fixS
*fixP
)
1858 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1861 /* Apply a fixup to the object file. */
1864 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1866 unsigned int subtype
;
1867 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1868 bfd_boolean relaxable
= FALSE
;
1872 /* Remember value for tc_gen_reloc. */
1873 fixP
->fx_addnumber
= *valP
;
1875 switch (fixP
->fx_r_type
)
1877 case BFD_RELOC_RISCV_HI20
:
1878 case BFD_RELOC_RISCV_LO12_I
:
1879 case BFD_RELOC_RISCV_LO12_S
:
1880 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1881 | bfd_getl32 (buf
), buf
);
1882 if (fixP
->fx_addsy
== NULL
)
1883 fixP
->fx_done
= TRUE
;
1887 case BFD_RELOC_RISCV_GOT_HI20
:
1888 case BFD_RELOC_RISCV_PCREL_HI20
:
1889 case BFD_RELOC_RISCV_ADD8
:
1890 case BFD_RELOC_RISCV_ADD16
:
1891 case BFD_RELOC_RISCV_ADD32
:
1892 case BFD_RELOC_RISCV_ADD64
:
1893 case BFD_RELOC_RISCV_SUB6
:
1894 case BFD_RELOC_RISCV_SUB8
:
1895 case BFD_RELOC_RISCV_SUB16
:
1896 case BFD_RELOC_RISCV_SUB32
:
1897 case BFD_RELOC_RISCV_SUB64
:
1898 case BFD_RELOC_RISCV_RELAX
:
1901 case BFD_RELOC_RISCV_TPREL_HI20
:
1902 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1903 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1904 case BFD_RELOC_RISCV_TPREL_ADD
:
1908 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1909 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1910 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1911 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1912 if (fixP
->fx_addsy
!= NULL
)
1913 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1916 _("TLS relocation against a constant"));
1920 /* Use pc-relative relocation for FDE initial location.
1921 The symbol address in .eh_frame may be adjusted in
1922 _bfd_elf_discard_section_eh_frame, and the content of
1923 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
1924 Therefore, we cannot insert a relocation whose addend symbol is
1925 in .eh_frame. Othrewise, the value may be adjusted twice.*/
1926 if (fixP
->fx_addsy
&& fixP
->fx_subsy
1927 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
1928 && strcmp (sub_segment
->name
, ".eh_frame") == 0
1929 && S_GET_VALUE (fixP
->fx_subsy
)
1930 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
1932 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
1933 fixP
->fx_subsy
= NULL
;
1940 case BFD_RELOC_RISCV_CFA
:
1941 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1943 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1944 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1945 fixP
->fx_next
->fx_subsy
= NULL
;
1946 fixP
->fx_next
->fx_offset
= 0;
1947 fixP
->fx_subsy
= NULL
;
1949 switch (fixP
->fx_r_type
)
1952 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1953 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
1957 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
1958 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1962 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
1963 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1967 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
1968 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1971 case BFD_RELOC_RISCV_CFA
:
1972 /* Load the byte to get the subtype. */
1973 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
1974 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
1977 case DW_CFA_advance_loc1
:
1978 fixP
->fx_where
= loc
+ 1;
1979 fixP
->fx_next
->fx_where
= loc
+ 1;
1980 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
1981 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1984 case DW_CFA_advance_loc2
:
1986 fixP
->fx_next
->fx_size
= 2;
1987 fixP
->fx_where
= loc
+ 1;
1988 fixP
->fx_next
->fx_where
= loc
+ 1;
1989 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
1990 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1993 case DW_CFA_advance_loc4
:
1995 fixP
->fx_next
->fx_size
= 4;
1996 fixP
->fx_where
= loc
;
1997 fixP
->fx_next
->fx_where
= loc
;
1998 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
1999 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2003 if (subtype
< 0x80 && (subtype
& 0x40))
2005 /* DW_CFA_advance_loc */
2006 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2007 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2008 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2009 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2012 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2018 /* This case is unreachable. */
2025 /* If we are deleting this reloc entry, we must fill in the
2026 value now. This can happen if we have a .word which is not
2027 resolved when it appears but is later defined. */
2028 if (fixP
->fx_addsy
== NULL
)
2030 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2031 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2036 case BFD_RELOC_RISCV_JMP
:
2039 /* Fill in a tentative value to improve objdump readability. */
2040 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2041 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2042 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2046 case BFD_RELOC_12_PCREL
:
2049 /* Fill in a tentative value to improve objdump readability. */
2050 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2051 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2052 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2056 case BFD_RELOC_RISCV_RVC_BRANCH
:
2059 /* Fill in a tentative value to improve objdump readability. */
2060 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2061 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2062 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2066 case BFD_RELOC_RISCV_RVC_JUMP
:
2069 /* Fill in a tentative value to improve objdump readability. */
2070 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2071 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2072 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2076 case BFD_RELOC_RISCV_CALL
:
2077 case BFD_RELOC_RISCV_CALL_PLT
:
2081 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2082 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2083 case BFD_RELOC_RISCV_ALIGN
:
2087 /* We ignore generic BFD relocations we don't know about. */
2088 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2089 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2092 if (fixP
->fx_subsy
!= NULL
)
2093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2094 _("unsupported symbol subtraction"));
2096 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2097 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2099 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2100 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2101 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2105 /* Because the value of .cfi_remember_state may changed after relaxation,
2106 we insert a fix to relocate it again in link-time. */
2109 riscv_pre_output_hook (void)
2111 const frchainS
*frch
;
2114 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2115 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2119 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2121 if (frag
->fr_type
== rs_cfa
)
2125 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2126 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2128 exp
.X_op
= O_subtract
;
2129 exp
.X_add_symbol
= add_symbol
;
2130 exp
.X_add_number
= 0;
2131 exp
.X_op_symbol
= op_symbol
;
2133 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2134 BFD_RELOC_RISCV_CFA
);
2141 /* This structure is used to hold a stack of .option values. */
2143 struct riscv_option_stack
2145 struct riscv_option_stack
*next
;
2146 struct riscv_set_options options
;
2149 static struct riscv_option_stack
*riscv_opts_stack
;
2151 /* Handle the .option pseudo-op. */
2154 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2156 char *name
= input_line_pointer
, ch
;
2158 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2159 ++input_line_pointer
;
2160 ch
= *input_line_pointer
;
2161 *input_line_pointer
= '\0';
2163 if (strcmp (name
, "rvc") == 0)
2164 riscv_set_rvc (TRUE
);
2165 else if (strcmp (name
, "norvc") == 0)
2166 riscv_set_rvc (FALSE
);
2167 else if (strcmp (name
, "pic") == 0)
2168 riscv_opts
.pic
= TRUE
;
2169 else if (strcmp (name
, "nopic") == 0)
2170 riscv_opts
.pic
= FALSE
;
2171 else if (strcmp (name
, "relax") == 0)
2172 riscv_opts
.relax
= TRUE
;
2173 else if (strcmp (name
, "norelax") == 0)
2174 riscv_opts
.relax
= FALSE
;
2175 else if (strcmp (name
, "push") == 0)
2177 struct riscv_option_stack
*s
;
2179 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2180 s
->next
= riscv_opts_stack
;
2181 s
->options
= riscv_opts
;
2182 riscv_opts_stack
= s
;
2184 else if (strcmp (name
, "pop") == 0)
2186 struct riscv_option_stack
*s
;
2188 s
= riscv_opts_stack
;
2190 as_bad (_(".option pop with no .option push"));
2193 riscv_opts
= s
->options
;
2194 riscv_opts_stack
= s
->next
;
2200 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2202 *input_line_pointer
= ch
;
2203 demand_empty_rest_of_line ();
2206 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2207 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2208 use in DWARF debug information. */
2211 s_dtprel (int bytes
)
2218 if (ex
.X_op
!= O_symbol
)
2220 as_bad (_("Unsupported use of %s"), (bytes
== 8
2223 ignore_rest_of_line ();
2226 p
= frag_more (bytes
);
2227 md_number_to_chars (p
, 0, bytes
);
2228 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2230 ? BFD_RELOC_RISCV_TLS_DTPREL64
2231 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2233 demand_empty_rest_of_line ();
2236 /* Handle the .bss pseudo-op. */
2239 s_bss (int ignore ATTRIBUTE_UNUSED
)
2241 subseg_set (bss_section
, 0);
2242 demand_empty_rest_of_line ();
2246 riscv_make_nops (char *buf
, bfd_vma bytes
)
2250 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2251 means we are not within a valid instruction sequence. It is thus safe
2252 to use a zero byte, even though that is not a valid instruction. */
2256 /* Use at most one 2-byte NOP. */
2257 if ((bytes
- i
) % 4 == 2)
2259 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2263 /* Fill the remainder with 4-byte NOPs. */
2264 for ( ; i
< bytes
; i
+= 4)
2265 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2268 /* Called from md_do_align. Used to create an alignment frag in a
2269 code section by emitting a worst-case NOP sequence that the linker
2270 will later relax to the correct number of NOPs. We can't compute
2271 the correct alignment now because of other linker relaxations. */
2274 riscv_frag_align_code (int n
)
2276 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2277 bfd_vma min_text_alignment_order
= riscv_opts
.rvc
? 1 : 2;
2278 bfd_vma min_text_alignment
= (bfd_vma
) 1 << min_text_alignment_order
;
2280 /* First, get back to minimal alignment. */
2281 frag_align_code (min_text_alignment_order
, 0);
2283 /* When not relaxing, riscv_handle_align handles code alignment. */
2284 if (!riscv_opts
.relax
)
2287 if (bytes
> min_text_alignment
)
2289 bfd_vma worst_case_bytes
= bytes
- min_text_alignment
;
2290 char *nops
= frag_more (worst_case_bytes
);
2293 ex
.X_op
= O_constant
;
2294 ex
.X_add_number
= worst_case_bytes
;
2296 riscv_make_nops (nops
, worst_case_bytes
);
2298 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2299 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2305 /* Implement HANDLE_ALIGN. */
2308 riscv_handle_align (fragS
*fragP
)
2310 switch (fragP
->fr_type
)
2313 /* When relaxing, riscv_frag_align_code handles code alignment. */
2314 if (!riscv_opts
.relax
)
2316 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2317 - fragP
->fr_address
- fragP
->fr_fix
;
2322 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2323 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2324 fragP
->fr_var
= count
;
2334 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2336 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2339 /* Translate internal representation of relocation info to BFD target
2343 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2345 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2347 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2348 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2349 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2350 reloc
->addend
= fixp
->fx_addnumber
;
2352 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2353 if (reloc
->howto
== NULL
)
2355 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2356 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2358 /* We don't have R_RISCV_8/16, but for this special case,
2359 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2363 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2364 _("cannot represent %s relocation in object file"),
2365 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2373 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2375 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2377 offsetT old_var
= fragp
->fr_var
;
2378 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2379 return fragp
->fr_var
- old_var
;
2385 /* Expand far branches to multi-instruction sequences. */
2388 md_convert_frag_branch (fragS
*fragp
)
2396 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2398 exp
.X_op
= O_symbol
;
2399 exp
.X_add_symbol
= fragp
->fr_symbol
;
2400 exp
.X_add_number
= fragp
->fr_offset
;
2402 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2404 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2406 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2410 /* Expand the RVC branch into a RISC-V one. */
2411 insn
= bfd_getl16 (buf
);
2412 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2413 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2415 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2416 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2417 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2418 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2419 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2420 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2423 bfd_putl32 (insn
, buf
);
2427 /* Invert the branch condition. Branch over the jump. */
2428 insn
= bfd_getl16 (buf
);
2429 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2430 insn
|= ENCODE_RVC_B_IMM (6);
2431 bfd_putl16 (insn
, buf
);
2436 /* Just keep the RVC branch. */
2437 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2438 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2439 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2440 2, &exp
, FALSE
, reloc
);
2449 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2452 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2454 /* Invert the branch condition. Branch over the jump. */
2455 insn
= bfd_getl32 (buf
);
2456 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2457 insn
|= ENCODE_SBTYPE_IMM (8);
2458 md_number_to_chars ((char *) buf
, insn
, 4);
2462 /* Jump to the target. */
2463 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2464 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2465 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2470 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2471 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2472 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2473 4, &exp
, FALSE
, reloc
);
2482 fixp
->fx_file
= fragp
->fr_file
;
2483 fixp
->fx_line
= fragp
->fr_line
;
2485 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2486 + fragp
->fr_fix
+ fragp
->fr_var
);
2488 fragp
->fr_fix
+= fragp
->fr_var
;
2491 /* Relax a machine dependent frag. This returns the amount by which
2492 the current size of the frag should change. */
2495 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2498 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2499 md_convert_frag_branch (fragp
);
2503 md_show_usage (FILE *stream
)
2505 fprintf (stream
, _("\
2507 -fpic generate position-independent code\n\
2508 -fno-pic don't generate position-independent code (default)\n\
2509 -march=ISA set the RISC-V architecture\n\
2510 -mabi=ABI set the RISC-V ABI\n\
2514 /* Standard calling conventions leave the CFA at SP on entry. */
2516 riscv_cfi_frame_initial_instructions (void)
2518 cfi_add_CFA_def_cfa_register (X_SP
);
2522 tc_riscv_regname_to_dw2regnum (char *regname
)
2526 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2529 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2532 as_bad (_("unknown register `%s'"), regname
);
2537 riscv_elf_final_processing (void)
2539 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2542 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2543 since these directives break relaxation when used with symbol deltas. */
2546 s_riscv_leb128 (int sign
)
2549 char *save_in
= input_line_pointer
;
2552 if (exp
.X_op
!= O_constant
)
2553 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2554 demand_empty_rest_of_line ();
2556 input_line_pointer
= save_in
;
2557 return s_leb128 (sign
);
2560 /* Pseudo-op table. */
2562 static const pseudo_typeS riscv_pseudo_table
[] =
2564 /* RISC-V-specific pseudo-ops. */
2565 {"option", s_riscv_option
, 0},
2569 {"dtprelword", s_dtprel
, 4},
2570 {"dtpreldword", s_dtprel
, 8},
2572 {"uleb128", s_riscv_leb128
, 0},
2573 {"sleb128", s_riscv_leb128
, 1},
2579 riscv_pop_insert (void)
2581 extern void pop_insert (const pseudo_typeS
*);
2583 pop_insert (riscv_pseudo_table
);