1 /* tc-riscv.c -- RISC-V assembler
2 Copyright 2011-2016 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_add_subset (const char *subset
)
126 struct riscv_subset
*s
= xmalloc (sizeof *s
);
128 s
->name
= xstrdup (subset
);
129 s
->next
= riscv_subsets
;
133 /* Set which ISA and extensions are available. */
136 riscv_set_arch (const char *s
)
138 const char *all_subsets
= "imafdc";
139 const char *extension
= NULL
;
142 if (strncmp (p
, "rv32", 4) == 0)
147 else if (strncmp (p
, "rv64", 4) == 0)
153 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
162 for ( ; *all_subsets
!= 'c'; all_subsets
++)
164 const char subset
[] = {*all_subsets
, '\0'};
165 riscv_add_subset (subset
);
170 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
177 char *subset
= xstrdup (p
), *q
= subset
;
179 while (*++q
!= '\0' && *q
!= '_')
184 as_fatal ("-march=%s: only one non-standard extension is supported"
185 " (found `%s' and `%s')", s
, extension
, subset
);
187 riscv_add_subset (subset
);
188 p
+= strlen (subset
);
193 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
195 const char subset
[] = {*p
, 0};
196 riscv_add_subset (subset
);
201 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
205 /* Handle of the OPCODE hash table. */
206 static struct hash_control
*op_hash
= NULL
;
208 /* This array holds the chars that always start a comment. If the
209 pre-processor is disabled, these aren't very useful */
210 const char comment_chars
[] = "#";
212 /* This array holds the chars that only start a comment at the beginning of
213 a line. If the line seems to have the form '# 123 filename'
214 .line and .file directives will appear in the pre-processed output */
215 /* Note that input_file.c hand checks for '#' at the beginning of the
216 first line of the input file. This is because the compiler outputs
217 #NO_APP at the beginning of its output. */
218 /* Also note that C style comments are always supported. */
219 const char line_comment_chars
[] = "#";
221 /* This array holds machine specific line separator characters. */
222 const char line_separator_chars
[] = ";";
224 /* Chars that can be used to separate mant from exp in floating point nums */
225 const char EXP_CHARS
[] = "eE";
227 /* Chars that mean this number is a floating point constant */
230 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
232 /* Macros for encoding relaxation state for RVC branches and far jumps. */
233 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
236 | ((uncond) ? 1 : 0) \
239 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
240 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
241 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
242 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
244 /* Is the given value a sign-extended 32-bit value? */
245 #define IS_SEXT_32BIT_NUM(x) \
246 (((x) &~ (offsetT) 0x7fffffff) == 0 \
247 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
249 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
250 #define IS_ZEXT_32BIT_NUM(x) \
251 (((x) &~ (offsetT) 0xffffffff) == 0 \
252 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
254 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
255 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
256 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
257 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
259 /* Determine if an instruction matches an opcode. */
260 #define OPCODE_MATCHES(OPCODE, OP) \
261 (((OPCODE) & MASK_##OP) == MATCH_##OP)
263 static char *expr_end
;
265 /* The default target format to use. */
268 riscv_target_format (void)
270 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
273 /* Return the length of instruction INSN. */
275 static inline unsigned int
276 insn_length (const struct riscv_cl_insn
*insn
)
278 return riscv_insn_length (insn
->insn_opcode
);
281 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
284 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
287 insn
->insn_opcode
= mo
->match
;
293 /* Install INSN at the location specified by its "frag" and "where" fields. */
296 install_insn (const struct riscv_cl_insn
*insn
)
298 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
299 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
302 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
303 and install the opcode in the new location. */
306 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
310 if (insn
->fixp
!= NULL
)
312 insn
->fixp
->fx_frag
= frag
;
313 insn
->fixp
->fx_where
= where
;
318 /* Add INSN to the end of the output. */
321 add_fixed_insn (struct riscv_cl_insn
*insn
)
323 char *f
= frag_more (insn_length (insn
));
324 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
328 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
329 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
331 frag_grow (max_chars
);
332 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
333 frag_var (rs_machine_dependent
, max_chars
, var
,
334 subtype
, symbol
, offset
, NULL
);
337 /* Compute the length of a branch sequence, and adjust the stored length
338 accordingly. If FRAGP is NULL, the worst-case length is returned. */
341 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
343 int jump
, rvc
, length
= 8;
348 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
349 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
350 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
352 /* Assume jumps are in range; the linker will catch any that aren't. */
353 length
= jump
? 4 : 8;
355 if (fragp
->fr_symbol
!= NULL
356 && S_IS_DEFINED (fragp
->fr_symbol
)
357 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
359 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
360 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
361 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
363 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
365 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
367 else if (!jump
&& rvc
)
372 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
391 static struct hash_control
*reg_names_hash
= NULL
;
393 #define ENCODE_REG_HASH(cls, n) \
394 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
395 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
396 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
399 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
401 void *hash
= ENCODE_REG_HASH (class, n
);
402 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
405 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
409 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
413 for (i
= 0; i
< n
; i
++)
414 hash_reg_name (class, names
[i
], i
);
418 reg_lookup_internal (const char *s
, enum reg_class
class)
420 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
422 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
424 return DECODE_REG_NUM (r
);
428 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
434 /* Find end of name. */
436 if (is_name_beginner (*e
))
438 while (is_part_of_name (*e
))
441 /* Terminate name. */
445 /* Look for the register. Advance to next token if one was recognized. */
446 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
456 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
458 const char *p
= strchr (*s
, ',');
459 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
461 for (i
= 0; i
< size
; i
++)
462 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
472 /* For consistency checking, verify that all bits are specified either
473 by the match/mask part of the instruction definition, or by the
476 validate_riscv_insn (const struct riscv_opcode
*opc
)
478 const char *p
= opc
->args
;
480 insn_t used_bits
= opc
->mask
;
481 int insn_width
= 8 * riscv_insn_length (opc
->match
);
482 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
484 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
486 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
487 opc
->name
, opc
->args
);
491 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
498 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
499 case 'c': break; /* RS1, constrained to equal sp */
500 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
501 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
502 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
503 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
504 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
505 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
506 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
507 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
508 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
509 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
510 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
511 case 'w': break; /* RS1S, constrained to equal RD */
512 case 'x': break; /* RS2S, constrained to equal RD */
513 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
514 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
515 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
516 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
517 case 'U': break; /* RS1, constrained to equal RD */
518 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
519 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
520 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
521 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
522 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
524 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
525 c
, opc
->name
, opc
->args
);
532 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
533 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
535 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
536 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
537 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
539 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
540 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
541 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
542 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
543 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
544 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
545 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
546 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
547 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
548 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
550 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
551 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
552 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
553 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
554 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
559 as_bad (_("internal: bad RISC-V opcode "
560 "(unknown operand type `%c'): %s %s"),
561 c
, opc
->name
, opc
->args
);
565 if (used_bits
!= required_bits
)
567 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
568 ~(unsigned long)(used_bits
& required_bits
),
569 opc
->name
, opc
->args
);
575 struct percent_op_match
578 bfd_reloc_code_real_type reloc
;
581 /* This function is called once, at assembler startup time. It should set up
582 all the tables, etc. that the MD part of the assembler will need. */
588 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
590 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
591 as_warn (_("Could not set architecture and machine"));
593 op_hash
= hash_new ();
595 while (riscv_opcodes
[i
].name
)
597 const char *name
= riscv_opcodes
[i
].name
;
598 const char *hash_error
=
599 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
603 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
604 riscv_opcodes
[i
].name
, hash_error
);
605 /* Probably a memory allocation problem? Give up now. */
606 as_fatal (_("Broken assembler. No assembly attempted."));
611 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
613 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
614 as_fatal (_("Broken assembler. No assembly attempted."));
618 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
621 reg_names_hash
= hash_new ();
622 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
623 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
624 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
625 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
627 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
628 #include "opcode/riscv-opc.h"
631 /* Set the default alignment for the text section. */
632 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
636 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
643 case BFD_RELOC_RISCV_HI20
:
644 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
646 case BFD_RELOC_RISCV_LO12_S
:
647 return ENCODE_STYPE_IMM (value
);
649 case BFD_RELOC_RISCV_LO12_I
:
650 return ENCODE_ITYPE_IMM (value
);
657 /* Output an instruction. IP is the instruction information.
658 ADDRESS_EXPR is an operand of the instruction to be used with
662 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
663 bfd_reloc_code_real_type reloc_type
)
665 dwarf2_emit_insn (0);
667 if (reloc_type
!= BFD_RELOC_UNUSED
)
669 reloc_howto_type
*howto
;
671 gas_assert (address_expr
);
672 if (reloc_type
== BFD_RELOC_12_PCREL
673 || reloc_type
== BFD_RELOC_RISCV_JMP
)
675 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
676 int best_case
= riscv_insn_length (ip
->insn_opcode
);
677 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
678 add_relaxed_insn (ip
, worst_case
, best_case
,
679 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
680 address_expr
->X_add_symbol
,
681 address_expr
->X_add_number
);
684 else if (address_expr
->X_op
== O_constant
)
685 ip
->insn_opcode
|= riscv_apply_const_reloc (reloc_type
,
686 address_expr
->X_add_number
);
689 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
691 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
693 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
694 bfd_get_reloc_size (howto
),
695 address_expr
, FALSE
, reloc_type
);
697 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
705 /* Build an instruction created by a macro expansion. This is passed
706 a pointer to the count of instructions created so far, an
707 expression, the name of the instruction to build, an operand format
708 string, and corresponding arguments. */
711 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
713 const struct riscv_opcode
*mo
;
714 struct riscv_cl_insn insn
;
715 bfd_reloc_code_real_type r
;
718 va_start (args
, fmt
);
720 r
= BFD_RELOC_UNUSED
;
721 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
724 /* Find a non-RVC variant of the instruction. append_insn will compress
726 while (riscv_insn_length (mo
->match
) < 4)
728 gas_assert (strcmp (name
, mo
->name
) == 0);
730 create_insn (&insn
, mo
);
736 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
740 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
744 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
748 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
754 gas_assert (ep
!= NULL
);
755 r
= va_arg (args
, int);
763 as_fatal (_("internal error: invalid macro"));
768 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
770 append_insn (&insn
, ep
, r
);
773 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
776 normalize_constant_expr (expressionS
*ex
)
780 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
781 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
782 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
786 /* Fail if an expression is not a constant. */
789 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
791 if (ex
->X_op
== O_big
)
792 as_bad (_("unsupported large constant"));
793 else if (ex
->X_op
!= O_constant
)
794 as_bad (_("Instruction %s requires absolute expression"),
796 normalize_constant_expr (ex
);
800 make_internal_label (void)
802 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
803 (valueT
) frag_now_fix (), frag_now
);
806 /* Load an entry from the GOT. */
808 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
809 const char *lo_insn
, const char *lo_pattern
,
810 bfd_reloc_code_real_type hi_reloc
,
811 bfd_reloc_code_real_type lo_reloc
)
815 ep2
.X_add_symbol
= make_internal_label ();
816 ep2
.X_add_number
= 0;
818 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
819 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
823 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
824 bfd_reloc_code_real_type hi_reloc
,
825 bfd_reloc_code_real_type lo_reloc
)
827 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
831 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
832 bfd_reloc_code_real_type hi_reloc
,
833 bfd_reloc_code_real_type lo_reloc
)
835 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
838 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
840 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
841 bfd_reloc_code_real_type reloc
)
843 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
844 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
847 /* Load an integer constant into a register. */
850 load_const (int reg
, expressionS
*ep
)
852 int shift
= RISCV_IMM_BITS
;
853 expressionS upper
= *ep
, lower
= *ep
;
854 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
855 upper
.X_add_number
-= lower
.X_add_number
;
857 if (ep
->X_op
!= O_constant
)
859 as_bad (_("unsupported large constant"));
863 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
865 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
866 while (((upper
.X_add_number
>> shift
) & 1) == 0)
869 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
870 load_const (reg
, &upper
);
872 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
873 if (lower
.X_add_number
!= 0)
874 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
878 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
881 if (upper
.X_add_number
!= 0)
883 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
887 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
888 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
889 BFD_RELOC_RISCV_LO12_I
);
893 /* Expand RISC-V assembly macros into one or more instructions. */
895 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
896 bfd_reloc_code_real_type
*imm_reloc
)
898 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
899 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
900 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
901 int mask
= ip
->insn_mo
->mask
;
906 load_const (rd
, imm_expr
);
911 /* Load the address of a symbol into a register. */
912 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
913 as_bad (_("offset too large"));
915 if (imm_expr
->X_op
== O_constant
)
916 load_const (rd
, imm_expr
);
917 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
918 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
919 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
920 else /* Local PIC symbol, or any non-PIC symbol */
921 pcrel_load (rd
, rd
, imm_expr
, "addi",
922 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
926 pcrel_load (rd
, rd
, imm_expr
, "addi",
927 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
931 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
932 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
936 pcrel_load (rd
, rd
, imm_expr
, "lb",
937 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
941 pcrel_load (rd
, rd
, imm_expr
, "lbu",
942 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
946 pcrel_load (rd
, rd
, imm_expr
, "lh",
947 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
951 pcrel_load (rd
, rd
, imm_expr
, "lhu",
952 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
956 pcrel_load (rd
, rd
, imm_expr
, "lw",
957 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
961 pcrel_load (rd
, rd
, imm_expr
, "lwu",
962 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
966 pcrel_load (rd
, rd
, imm_expr
, "ld",
967 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
971 pcrel_load (rd
, rs1
, imm_expr
, "flw",
972 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
976 pcrel_load (rd
, rs1
, imm_expr
, "fld",
977 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
981 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
982 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
986 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
987 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
991 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
992 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
996 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
997 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1001 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1002 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1006 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1007 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1011 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1015 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1020 static const struct percent_op_match percent_op_utype
[] =
1022 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1023 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1024 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1025 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1026 {"%hi", BFD_RELOC_RISCV_HI20
},
1030 static const struct percent_op_match percent_op_itype
[] =
1032 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1033 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1034 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1038 static const struct percent_op_match percent_op_stype
[] =
1040 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1041 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1042 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1046 static const struct percent_op_match percent_op_rtype
[] =
1048 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1052 /* Return true if *STR points to a relocation operator. When returning true,
1053 move *STR over the operator and store its relocation code in *RELOC.
1054 Leave both *STR and *RELOC alone when returning false. */
1057 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1058 const struct percent_op_match
*percent_op
)
1060 for ( ; percent_op
->str
; percent_op
++)
1061 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1063 int len
= strlen (percent_op
->str
);
1065 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1068 *str
+= strlen (percent_op
->str
);
1069 *reloc
= percent_op
->reloc
;
1071 /* Check whether the output BFD supports this relocation.
1072 If not, issue an error and fall back on something safe. */
1073 if (*reloc
!= BFD_RELOC_UNUSED
1074 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1076 as_bad ("relocation %s isn't supported by the current ABI",
1078 *reloc
= BFD_RELOC_UNUSED
;
1086 my_getExpression (expressionS
*ep
, char *str
)
1090 save_in
= input_line_pointer
;
1091 input_line_pointer
= str
;
1093 expr_end
= input_line_pointer
;
1094 input_line_pointer
= save_in
;
1097 /* Parse string STR as a 16-bit relocatable operand. Store the
1098 expression in *EP and the relocation, if any, in RELOC.
1099 Return the number of relocation operators used (0 or 1).
1101 On exit, EXPR_END points to the first character after the expression. */
1104 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1105 char *str
, const struct percent_op_match
*percent_op
)
1108 unsigned crux_depth
, str_depth
, regno
;
1111 /* First, check for integer registers. */
1112 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1114 ep
->X_op
= O_register
;
1115 ep
->X_add_number
= regno
;
1119 /* Search for the start of the main expression.
1120 End the loop with CRUX pointing to the start
1121 of the main expression and with CRUX_DEPTH containing the number
1122 of open brackets at that point. */
1129 crux_depth
= str_depth
;
1131 /* Skip over whitespace and brackets, keeping count of the number
1133 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1139 && parse_relocation (&str
, reloc
, percent_op
));
1141 my_getExpression (ep
, crux
);
1144 /* Match every open bracket. */
1145 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1150 as_bad ("unclosed '('");
1157 /* This routine assembles an instruction into its binary format. As a
1158 side effect, it sets the global variable imm_reloc to the type of
1159 relocation to do if one of the operands is an address expression. */
1162 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1163 bfd_reloc_code_real_type
*imm_reloc
)
1168 struct riscv_opcode
*insn
;
1173 const struct percent_op_match
*p
;
1174 const char *error
= "unrecognized opcode";
1176 /* Parse the name of the instruction. Terminate the string if whitespace
1177 is found so that hash_find only sees the name part of the string. */
1178 for (s
= str
; *s
!= '\0'; ++s
)
1186 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1189 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1191 if (!riscv_subset_supports (insn
->subset
))
1194 create_insn (ip
, insn
);
1197 imm_expr
->X_op
= O_absent
;
1198 *imm_reloc
= BFD_RELOC_UNUSED
;
1199 p
= percent_op_itype
;
1201 for (args
= insn
->args
;; ++args
)
1203 s
+= strspn (s
, " \t");
1206 case '\0': /* End of args. */
1207 if (insn
->pinfo
!= INSN_MACRO
)
1209 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1211 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1216 /* Successful assembly. */
1223 case 's': /* RS1 x8-x15 */
1224 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1225 || !(regno
>= 8 && regno
<= 15))
1227 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1229 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1230 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1231 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1234 case 't': /* RS2 x8-x15 */
1235 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1236 || !(regno
>= 8 && regno
<= 15))
1238 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1240 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1241 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1242 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1245 case 'U': /* RS1, constrained to equal RD. */
1246 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1247 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1251 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1253 INSERT_OPERAND (CRS2
, *ip
, regno
);
1255 case 'c': /* RS1, constrained to equal sp. */
1256 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1261 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1262 || imm_expr
->X_op
!= O_constant
1263 || imm_expr
->X_add_number
<= 0
1264 || imm_expr
->X_add_number
>= 64)
1266 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1269 imm_expr
->X_op
= O_absent
;
1272 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1273 || imm_expr
->X_op
!= O_constant
1274 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1275 || imm_expr
->X_add_number
<= 0
1276 || imm_expr
->X_add_number
>= 32)
1278 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1281 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1282 || imm_expr
->X_op
!= O_constant
1283 || imm_expr
->X_add_number
== 0
1284 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1286 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1289 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1290 || imm_expr
->X_op
!= O_constant
1291 || imm_expr
->X_add_number
== 0
1292 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1294 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1297 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1298 || imm_expr
->X_op
!= O_constant
1299 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1301 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1304 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1305 || imm_expr
->X_op
!= O_constant
1306 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1308 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1311 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1312 || imm_expr
->X_op
!= O_constant
1313 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1316 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1319 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1320 || imm_expr
->X_op
!= O_constant
1321 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1324 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1327 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1328 || imm_expr
->X_op
!= O_constant
1329 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1330 || imm_expr
->X_add_number
== 0)
1333 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1336 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1337 || imm_expr
->X_op
!= O_constant
1338 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1339 || imm_expr
->X_add_number
== 0)
1342 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1345 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1346 || imm_expr
->X_op
!= O_constant
1347 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1350 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1353 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1354 || imm_expr
->X_op
!= O_constant
1355 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1358 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1361 p
= percent_op_utype
;
1362 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1365 if (imm_expr
->X_op
!= O_constant
1366 || imm_expr
->X_add_number
<= 0
1367 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1368 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1369 && (imm_expr
->X_add_number
<
1370 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1372 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1375 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1376 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1377 || ((int32_t)imm_expr
->X_add_number
1378 != imm_expr
->X_add_number
))
1380 imm_expr
->X_add_number
=
1381 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1387 case 'D': /* Floating-point RS2 x8-x15. */
1388 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1389 || !(regno
>= 8 && regno
<= 15))
1391 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1393 case 'T': /* Floating-point RS2. */
1394 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1396 INSERT_OPERAND (CRS2
, *ip
, regno
);
1399 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1418 case '<': /* Shift amount, 0 - 31. */
1419 my_getExpression (imm_expr
, s
);
1420 check_absolute_expr (ip
, imm_expr
);
1421 if ((unsigned long) imm_expr
->X_add_number
> 31)
1422 as_warn (_("Improper shift amount (%lu)"),
1423 (unsigned long) imm_expr
->X_add_number
);
1424 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1425 imm_expr
->X_op
= O_absent
;
1429 case '>': /* Shift amount, 0 - (XLEN-1). */
1430 my_getExpression (imm_expr
, s
);
1431 check_absolute_expr (ip
, imm_expr
);
1432 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1433 as_warn (_("Improper shift amount (%lu)"),
1434 (unsigned long) imm_expr
->X_add_number
);
1435 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1436 imm_expr
->X_op
= O_absent
;
1440 case 'Z': /* CSRRxI immediate. */
1441 my_getExpression (imm_expr
, s
);
1442 check_absolute_expr (ip
, imm_expr
);
1443 if ((unsigned long) imm_expr
->X_add_number
> 31)
1444 as_warn (_("Improper CSRxI immediate (%lu)"),
1445 (unsigned long) imm_expr
->X_add_number
);
1446 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1447 imm_expr
->X_op
= O_absent
;
1451 case 'E': /* Control register. */
1452 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1453 INSERT_OPERAND (CSR
, *ip
, regno
);
1456 my_getExpression (imm_expr
, s
);
1457 check_absolute_expr (ip
, imm_expr
);
1458 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1459 as_warn (_("Improper CSR address (%lu)"),
1460 (unsigned long) imm_expr
->X_add_number
);
1461 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1462 imm_expr
->X_op
= O_absent
;
1467 case 'm': /* Rounding mode. */
1468 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1470 INSERT_OPERAND (RM
, *ip
, regno
);
1476 case 'Q': /* Fence predecessor/successor. */
1477 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1481 INSERT_OPERAND (PRED
, *ip
, regno
);
1483 INSERT_OPERAND (SUCC
, *ip
, regno
);
1488 case 'd': /* Destination register. */
1489 case 's': /* Source register. */
1490 case 't': /* Target register. */
1491 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1497 /* Now that we have assembled one operand, we use the args
1498 string to figure out where it goes in the instruction. */
1502 INSERT_OPERAND (RS1
, *ip
, regno
);
1505 INSERT_OPERAND (RD
, *ip
, regno
);
1508 INSERT_OPERAND (RS2
, *ip
, regno
);
1515 case 'D': /* Floating point rd. */
1516 case 'S': /* Floating point rs1. */
1517 case 'T': /* Floating point rs2. */
1518 case 'U': /* Floating point rs1 and rs2. */
1519 case 'R': /* Floating point rs3. */
1520 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1528 INSERT_OPERAND (RD
, *ip
, regno
);
1531 INSERT_OPERAND (RS1
, *ip
, regno
);
1534 INSERT_OPERAND (RS1
, *ip
, regno
);
1537 INSERT_OPERAND (RS2
, *ip
, regno
);
1540 INSERT_OPERAND (RS3
, *ip
, regno
);
1549 my_getExpression (imm_expr
, s
);
1550 if (imm_expr
->X_op
!= O_big
1551 && imm_expr
->X_op
!= O_constant
)
1553 normalize_constant_expr (imm_expr
);
1558 my_getExpression (imm_expr
, s
);
1559 normalize_constant_expr (imm_expr
);
1560 /* The 'A' format specifier must be a symbol. */
1561 if (imm_expr
->X_op
!= O_symbol
)
1563 *imm_reloc
= BFD_RELOC_32
;
1567 case 'j': /* Sign-extended immediate. */
1568 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1569 p
= percent_op_itype
;
1571 case 'q': /* Store displacement. */
1572 p
= percent_op_stype
;
1573 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1575 case 'o': /* Load displacement. */
1576 p
= percent_op_itype
;
1577 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1579 case '0': /* AMO "displacement," which must be zero. */
1580 p
= percent_op_rtype
;
1581 *imm_reloc
= BFD_RELOC_UNUSED
;
1583 /* Check whether there is only a single bracketed expression
1584 left. If so, it must be the base register and the
1585 constant must be zero. */
1586 imm_expr
->X_op
= O_constant
;
1587 imm_expr
->X_add_number
= 0;
1588 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1591 /* If this value won't fit into a 16 bit offset, then go
1592 find a macro that will generate the 32 bit offset
1594 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1596 normalize_constant_expr (imm_expr
);
1597 if (imm_expr
->X_op
!= O_constant
1598 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1599 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1600 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1607 case 'p': /* PC-relative offset. */
1609 *imm_reloc
= BFD_RELOC_12_PCREL
;
1610 my_getExpression (imm_expr
, s
);
1614 case 'u': /* Upper 20 bits. */
1615 p
= percent_op_utype
;
1616 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1617 && imm_expr
->X_op
== O_constant
)
1619 if (imm_expr
->X_add_number
< 0
1620 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1621 as_bad (_("lui expression not in range 0..1048575"));
1623 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1624 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1629 case 'a': /* 20-bit PC-relative offset. */
1631 my_getExpression (imm_expr
, s
);
1633 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1637 my_getExpression (imm_expr
, s
);
1639 if (strcmp (s
, "@plt") == 0)
1641 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1645 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1649 as_fatal (_("internal error: bad argument type %c"), *args
);
1654 error
= _("illegal operands");
1658 /* Restore the character we might have clobbered above. */
1660 *(argsStart
- 1) = save_c
;
1666 md_assemble (char *str
)
1668 struct riscv_cl_insn insn
;
1669 expressionS imm_expr
;
1670 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1672 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1676 as_bad ("%s `%s'", error
, str
);
1680 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1681 macro (&insn
, &imm_expr
, &imm_reloc
);
1683 append_insn (&insn
, &imm_expr
, imm_reloc
);
1687 md_atof (int type
, char *litP
, int *sizeP
)
1689 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1693 md_number_to_chars (char *buf
, valueT val
, int n
)
1695 number_to_chars_littleendian (buf
, val
, n
);
1698 const char *md_shortopts
= "O::g::G:";
1702 OPTION_MARCH
= OPTION_MD_BASE
,
1709 struct option md_longopts
[] =
1711 {"march", required_argument
, NULL
, OPTION_MARCH
},
1712 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1713 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1714 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1715 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1717 {NULL
, no_argument
, NULL
, 0}
1719 size_t md_longopts_size
= sizeof (md_longopts
);
1722 FLOAT_ABI_DEFAULT
= -1,
1728 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1731 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1733 abi_xlen
= new_xlen
;
1734 float_abi
= new_float_abi
;
1738 md_parse_option (int c
, const char *arg
)
1743 riscv_set_arch (arg
);
1747 riscv_opts
.pic
= FALSE
;
1751 riscv_opts
.pic
= TRUE
;
1755 if (strcmp (arg
, "ilp32") == 0)
1756 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1757 else if (strcmp (arg
, "ilp32f") == 0)
1758 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1759 else if (strcmp (arg
, "ilp32d") == 0)
1760 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1761 else if (strcmp (arg
, "ilp32q") == 0)
1762 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1763 else if (strcmp (arg
, "lp64") == 0)
1764 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1765 else if (strcmp (arg
, "lp64f") == 0)
1766 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1767 else if (strcmp (arg
, "lp64d") == 0)
1768 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1769 else if (strcmp (arg
, "lp64q") == 0)
1770 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1783 riscv_after_parse_args (void)
1787 if (strcmp (default_arch
, "riscv32") == 0)
1789 else if (strcmp (default_arch
, "riscv64") == 0)
1792 as_bad ("unknown default architecture `%s'", default_arch
);
1795 if (riscv_subsets
== NULL
)
1796 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1798 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1799 if (riscv_subset_supports ("c"))
1800 riscv_set_rvc (TRUE
);
1802 riscv_add_subset ("c");
1804 /* Infer ABI from ISA if not specified on command line. */
1807 else if (abi_xlen
> xlen
)
1808 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1809 else if (abi_xlen
< xlen
)
1810 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1812 if (float_abi
== FLOAT_ABI_DEFAULT
)
1814 struct riscv_subset
*subset
;
1816 /* Assume soft-float unless D extension is present. */
1817 float_abi
= FLOAT_ABI_SOFT
;
1819 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1820 if (strcasecmp (subset
->name
, "D") == 0)
1821 float_abi
= FLOAT_ABI_DOUBLE
;
1824 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1825 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1829 md_pcrel_from (fixS
*fixP
)
1831 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1834 /* Apply a fixup to the object file. */
1837 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1839 unsigned int subtype
;
1840 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1841 bfd_boolean relaxable
= FALSE
;
1843 /* Remember value for tc_gen_reloc. */
1844 fixP
->fx_addnumber
= *valP
;
1846 switch (fixP
->fx_r_type
)
1848 case BFD_RELOC_RISCV_HI20
:
1849 case BFD_RELOC_RISCV_LO12_I
:
1850 case BFD_RELOC_RISCV_LO12_S
:
1851 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1852 | bfd_getl32 (buf
), buf
);
1856 case BFD_RELOC_RISCV_GOT_HI20
:
1857 case BFD_RELOC_RISCV_PCREL_HI20
:
1858 case BFD_RELOC_RISCV_ADD8
:
1859 case BFD_RELOC_RISCV_ADD16
:
1860 case BFD_RELOC_RISCV_ADD32
:
1861 case BFD_RELOC_RISCV_ADD64
:
1862 case BFD_RELOC_RISCV_SUB6
:
1863 case BFD_RELOC_RISCV_SUB8
:
1864 case BFD_RELOC_RISCV_SUB16
:
1865 case BFD_RELOC_RISCV_SUB32
:
1866 case BFD_RELOC_RISCV_SUB64
:
1867 case BFD_RELOC_RISCV_RELAX
:
1870 case BFD_RELOC_RISCV_TPREL_HI20
:
1871 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1872 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1873 case BFD_RELOC_RISCV_TPREL_ADD
:
1877 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1878 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1879 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1880 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1881 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1888 case BFD_RELOC_RISCV_CFA
:
1889 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1891 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1892 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1893 fixP
->fx_next
->fx_subsy
= NULL
;
1894 fixP
->fx_next
->fx_offset
= 0;
1895 fixP
->fx_subsy
= NULL
;
1897 switch (fixP
->fx_r_type
)
1900 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1901 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
1905 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
1906 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1910 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
1911 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1915 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
1916 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1919 case BFD_RELOC_RISCV_CFA
:
1920 /* Load the byte to get the subtype. */
1921 subtype
= bfd_get_8 (NULL
, &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
]);
1924 case DW_CFA_advance_loc1
:
1926 fixP
->fx_next
->fx_where
++;
1927 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
1928 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1931 case DW_CFA_advance_loc2
:
1934 fixP
->fx_next
->fx_size
= 2;
1935 fixP
->fx_next
->fx_where
++;
1936 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
1937 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1940 case DW_CFA_advance_loc4
:
1943 fixP
->fx_next
->fx_size
= 4;
1944 fixP
->fx_next
->fx_where
++;
1945 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
1946 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1950 if (subtype
< 0x80 && (subtype
& 0x40))
1952 /* DW_CFA_advance_loc */
1953 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
1954 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
1957 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
1963 /* This case is unreachable. */
1970 /* If we are deleting this reloc entry, we must fill in the
1971 value now. This can happen if we have a .word which is not
1972 resolved when it appears but is later defined. */
1973 if (fixP
->fx_addsy
== NULL
)
1975 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
1976 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
1981 case BFD_RELOC_RISCV_JMP
:
1984 /* Fill in a tentative value to improve objdump readability. */
1985 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
1986 bfd_vma delta
= target
- md_pcrel_from (fixP
);
1987 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
1991 case BFD_RELOC_12_PCREL
:
1994 /* Fill in a tentative value to improve objdump readability. */
1995 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
1996 bfd_vma delta
= target
- md_pcrel_from (fixP
);
1997 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2001 case BFD_RELOC_RISCV_RVC_BRANCH
:
2004 /* Fill in a tentative value to improve objdump readability. */
2005 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2006 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2007 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2011 case BFD_RELOC_RISCV_RVC_JUMP
:
2014 /* Fill in a tentative value to improve objdump readability. */
2015 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2016 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2017 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2021 case BFD_RELOC_RISCV_CALL
:
2022 case BFD_RELOC_RISCV_CALL_PLT
:
2026 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2027 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2028 case BFD_RELOC_RISCV_ALIGN
:
2032 /* We ignore generic BFD relocations we don't know about. */
2033 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2034 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2037 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2038 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2040 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2041 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2042 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2046 /* Because the value of .cfi_remember_state may changed after relaxation,
2047 we insert a fix to relocate it again in link-time. */
2050 riscv_pre_output_hook (void)
2052 const frchainS
*frch
;
2055 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2056 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2060 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2062 if (frag
->fr_type
== rs_cfa
)
2064 const fragS
*loc4_frag
;
2067 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2068 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2070 exp
.X_op
= O_subtract
;
2071 exp
.X_add_symbol
= add_symbol
;
2072 exp
.X_add_number
= 0;
2073 exp
.X_op_symbol
= op_symbol
;
2075 loc4_frag
= (fragS
*) frag
->fr_opcode
;
2076 fix_new_exp (loc4_frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2077 BFD_RELOC_RISCV_CFA
);
2084 /* This structure is used to hold a stack of .option values. */
2086 struct riscv_option_stack
2088 struct riscv_option_stack
*next
;
2089 struct riscv_set_options options
;
2092 static struct riscv_option_stack
*riscv_opts_stack
;
2094 /* Handle the .option pseudo-op. */
2097 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2099 char *name
= input_line_pointer
, ch
;
2101 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2102 ++input_line_pointer
;
2103 ch
= *input_line_pointer
;
2104 *input_line_pointer
= '\0';
2106 if (strcmp (name
, "rvc") == 0)
2107 riscv_set_rvc (TRUE
);
2108 else if (strcmp (name
, "norvc") == 0)
2109 riscv_set_rvc (FALSE
);
2110 else if (strcmp (name
, "pic") == 0)
2111 riscv_opts
.pic
= TRUE
;
2112 else if (strcmp (name
, "nopic") == 0)
2113 riscv_opts
.pic
= FALSE
;
2114 else if (strcmp (name
, "relax") == 0)
2115 riscv_opts
.relax
= TRUE
;
2116 else if (strcmp (name
, "norelax") == 0)
2117 riscv_opts
.relax
= FALSE
;
2118 else if (strcmp (name
, "push") == 0)
2120 struct riscv_option_stack
*s
;
2122 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2123 s
->next
= riscv_opts_stack
;
2124 s
->options
= riscv_opts
;
2125 riscv_opts_stack
= s
;
2127 else if (strcmp (name
, "pop") == 0)
2129 struct riscv_option_stack
*s
;
2131 s
= riscv_opts_stack
;
2133 as_bad (_(".option pop with no .option push"));
2136 riscv_opts
= s
->options
;
2137 riscv_opts_stack
= s
->next
;
2143 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2145 *input_line_pointer
= ch
;
2146 demand_empty_rest_of_line ();
2149 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2150 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2151 use in DWARF debug information. */
2154 s_dtprel (int bytes
)
2161 if (ex
.X_op
!= O_symbol
)
2163 as_bad (_("Unsupported use of %s"), (bytes
== 8
2166 ignore_rest_of_line ();
2169 p
= frag_more (bytes
);
2170 md_number_to_chars (p
, 0, bytes
);
2171 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2173 ? BFD_RELOC_RISCV_TLS_DTPREL64
2174 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2176 demand_empty_rest_of_line ();
2179 /* Handle the .bss pseudo-op. */
2182 s_bss (int ignore ATTRIBUTE_UNUSED
)
2184 subseg_set (bss_section
, 0);
2185 demand_empty_rest_of_line ();
2188 /* Align to a given power of two. */
2191 s_align (int bytes_p
)
2193 int fill_value
= 0, fill_value_specified
= 0;
2194 int min_text_alignment
= riscv_opts
.rvc
? 2 : 4;
2195 int alignment
= get_absolute_expression(), bytes
;
2200 if (bytes
< 1 || (bytes
& (bytes
-1)) != 0)
2201 as_bad (_("alignment not a power of 2: %d"), bytes
);
2202 for (alignment
= 0; bytes
> 1; bytes
>>= 1)
2206 bytes
= 1 << alignment
;
2208 if (alignment
< 0 || alignment
> 31)
2209 as_bad (_("unsatisfiable alignment: %d"), alignment
);
2211 if (*input_line_pointer
== ',')
2213 ++input_line_pointer
;
2214 fill_value
= get_absolute_expression ();
2215 fill_value_specified
= 1;
2218 if (!fill_value_specified
2219 && subseg_text_p (now_seg
)
2220 && bytes
> min_text_alignment
)
2222 /* Emit the worst-case NOP string. The linker will delete any
2223 unnecessary NOPs. This allows us to support code alignment
2224 in spite of linker relaxations. */
2225 bfd_vma i
, worst_case_bytes
= bytes
- min_text_alignment
;
2226 char *nops
= frag_more (worst_case_bytes
);
2227 for (i
= 0; i
< worst_case_bytes
- 2; i
+= 4)
2228 md_number_to_chars (nops
+ i
, RISCV_NOP
, 4);
2229 if (i
< worst_case_bytes
)
2230 md_number_to_chars (nops
+ i
, RVC_NOP
, 2);
2233 ex
.X_op
= O_constant
;
2234 ex
.X_add_number
= worst_case_bytes
;
2236 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2237 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2240 frag_align (alignment
, fill_value
, 0);
2242 record_alignment (now_seg
, alignment
);
2244 demand_empty_rest_of_line ();
2248 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2250 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2253 /* Translate internal representation of relocation info to BFD target
2257 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2259 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2261 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2262 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2263 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2264 reloc
->addend
= fixp
->fx_addnumber
;
2266 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2267 if (reloc
->howto
== NULL
)
2269 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2270 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2272 /* We don't have R_RISCV_8/16, but for this special case,
2273 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2278 _("cannot represent %s relocation in object file"),
2279 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2287 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2289 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2291 offsetT old_var
= fragp
->fr_var
;
2292 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2293 return fragp
->fr_var
- old_var
;
2299 /* Expand far branches to multi-instruction sequences. */
2302 md_convert_frag_branch (fragS
*fragp
)
2310 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2312 exp
.X_op
= O_symbol
;
2313 exp
.X_add_symbol
= fragp
->fr_symbol
;
2314 exp
.X_add_number
= fragp
->fr_offset
;
2316 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2318 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2320 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2324 /* Expand the RVC branch into a RISC-V one. */
2325 insn
= bfd_getl16 (buf
);
2326 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2327 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2329 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2330 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2331 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2332 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2333 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2334 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2337 bfd_putl32 (insn
, buf
);
2341 /* Invert the branch condition. Branch over the jump. */
2342 insn
= bfd_getl16 (buf
);
2343 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2344 insn
|= ENCODE_RVC_B_IMM (6);
2345 bfd_putl16 (insn
, buf
);
2350 /* Just keep the RVC branch. */
2351 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2352 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2353 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2354 2, &exp
, FALSE
, reloc
);
2363 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2366 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2368 /* Invert the branch condition. Branch over the jump. */
2369 insn
= bfd_getl32 (buf
);
2370 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2371 insn
|= ENCODE_SBTYPE_IMM (8);
2372 md_number_to_chars ((char *) buf
, insn
, 4);
2376 /* Jump to the target. */
2377 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2378 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2379 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2384 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2385 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2386 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2387 4, &exp
, FALSE
, reloc
);
2396 fixp
->fx_file
= fragp
->fr_file
;
2397 fixp
->fx_line
= fragp
->fr_line
;
2399 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2400 + fragp
->fr_fix
+ fragp
->fr_var
);
2402 fragp
->fr_fix
+= fragp
->fr_var
;
2405 /* Relax a machine dependent frag. This returns the amount by which
2406 the current size of the frag should change. */
2409 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2412 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2413 md_convert_frag_branch (fragp
);
2417 md_show_usage (FILE *stream
)
2419 fprintf (stream
, _("\
2421 -m32 assemble RV32 code\n\
2422 -m64 assemble RV64 code (default)\n\
2423 -fpic generate position-independent code\n\
2424 -fno-pic don't generate position-independent code (default)\n\
2425 -msoft-float don't use F registers for floating-point values\n\
2426 -mhard-float use F registers for floating-point values (default)\n\
2427 -mno-rvc disable the C extension for compressed instructions (default)\n\
2428 -mrvc enable the C extension for compressed instructions\n\
2429 -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
2433 /* Standard calling conventions leave the CFA at SP on entry. */
2435 riscv_cfi_frame_initial_instructions (void)
2437 cfi_add_CFA_def_cfa_register (X_SP
);
2441 tc_riscv_regname_to_dw2regnum (char *regname
)
2445 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2448 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2451 as_bad (_("unknown register `%s'"), regname
);
2456 riscv_elf_final_processing (void)
2458 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2461 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2462 since these directives break relaxation when used with symbol deltas. */
2465 s_riscv_leb128 (int sign
)
2468 char *save_in
= input_line_pointer
;
2471 if (exp
.X_op
!= O_constant
)
2472 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2473 demand_empty_rest_of_line ();
2475 input_line_pointer
= save_in
;
2476 return s_leb128 (sign
);
2479 /* Pseudo-op table. */
2481 static const pseudo_typeS riscv_pseudo_table
[] =
2483 /* RISC-V-specific pseudo-ops. */
2484 {"option", s_riscv_option
, 0},
2488 {"dtprelword", s_dtprel
, 4},
2489 {"dtpreldword", s_dtprel
, 8},
2491 {"align", s_align
, 0},
2492 {"p2align", s_align
, 0},
2493 {"balign", s_align
, 1},
2494 {"uleb128", s_riscv_leb128
, 0},
2495 {"sleb128", s_riscv_leb128
, 1},
2501 riscv_pop_insert (void)
2503 extern void pop_insert (const pseudo_typeS
*);
2505 pop_insert (riscv_pseudo_table
);