1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 FLOAT_ABI_DEFAULT
= -1,
101 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
103 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
104 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
106 static unsigned elf_flags
= 0;
108 /* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
112 riscv_set_default_isa_spec (const char *s
)
114 enum riscv_isa_spec_class
class;
115 if (!riscv_get_isa_spec_class (s
, &class))
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s
);
122 default_isa_spec
= class;
126 /* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
132 riscv_set_default_priv_spec (const char *s
)
134 enum riscv_priv_spec_class
class;
135 unsigned major
, minor
, revision
;
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s
, &class))
141 default_priv_spec
= class;
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s
);
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr
= elf_known_obj_attributes_proc (stdoutput
);
154 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
155 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
156 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
158 if (riscv_get_priv_spec_class_from_numbers (major
,
163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE
)
169 default_priv_spec
= class;
173 /* Still can not find the priv spec class. */
174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
175 "privilege attributes"), major
, minor
, revision
);
179 /* This is the set of options which the .option pseudo-op may modify. */
181 struct riscv_set_options
183 int pic
; /* Generate position-independent code. */
184 int rvc
; /* Generate RVC code. */
185 int rve
; /* Generate RVE code. */
186 int relax
; /* Emit relocs the linker is allowed to relax. */
187 int arch_attr
; /* Emit arch attribute. */
188 int csr_check
; /* Enable the CSR checking. */
191 static struct riscv_set_options riscv_opts
=
197 DEFAULT_RISCV_ATTR
, /* arch_attr */
202 riscv_set_rvc (bfd_boolean rvc_value
)
205 elf_flags
|= EF_RISCV_RVC
;
207 riscv_opts
.rvc
= rvc_value
;
211 riscv_set_rve (bfd_boolean rve_value
)
213 riscv_opts
.rve
= rve_value
;
216 static riscv_subset_list_t riscv_subsets
;
219 riscv_subset_supports (const char *feature
)
221 struct riscv_subset_t
*subset
;
223 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
226 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
230 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
234 case INSN_CLASS_I
: return riscv_subset_supports ("i");
235 case INSN_CLASS_C
: return riscv_subset_supports ("c");
236 case INSN_CLASS_A
: return riscv_subset_supports ("a");
237 case INSN_CLASS_M
: return riscv_subset_supports ("m");
238 case INSN_CLASS_F
: return riscv_subset_supports ("f");
239 case INSN_CLASS_D
: return riscv_subset_supports ("d");
240 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
242 case INSN_CLASS_F_AND_C
:
243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C
:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
249 case INSN_CLASS_ZICSR
:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI
:
252 return riscv_subset_supports ("zifencei");
253 case INSN_CLASS_ZIHINTPAUSE
:
254 return riscv_subset_supports ("zihintpause");
257 return riscv_subset_supports ("zba");
259 return riscv_subset_supports ("zbb");
261 return riscv_subset_supports ("zbc");
262 case INSN_CLASS_ZBA_OR_ZBB
:
263 return (riscv_subset_supports ("zba")
264 || riscv_subset_supports ("zbb"));
267 as_fatal ("Unreachable");
272 /* Handle of the extension with version hash table. */
273 static htab_t ext_version_hash
= NULL
;
276 init_ext_version_hash (const struct riscv_ext_version
*table
)
279 htab_t hash
= str_htab_create ();
281 while (table
[i
].name
)
283 const char *name
= table
[i
].name
;
284 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
285 as_fatal (_("duplicate %s"), name
);
289 && strcmp (table
[i
].name
, name
) == 0)
297 riscv_get_default_ext_version (const char *name
,
301 struct riscv_ext_version
*ext
;
303 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
306 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
309 && strcmp (ext
->name
, name
) == 0)
311 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
312 || ext
->isa_spec_class
== default_isa_spec
)
314 *major_version
= ext
->major_version
;
315 *minor_version
= ext
->minor_version
;
322 /* Set which ISA and extensions are available. */
325 riscv_set_arch (const char *s
)
327 riscv_parse_subset_t rps
;
328 rps
.subset_list
= &riscv_subsets
;
329 rps
.error_handler
= as_bad
;
331 rps
.get_default_version
= riscv_get_default_ext_version
;
336 riscv_release_subset_list (&riscv_subsets
);
337 riscv_parse_subset (&rps
, s
);
340 /* Indicate -mabi= option is explictly set. */
341 static bfd_boolean explicit_mabi
= FALSE
;
344 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
347 float_abi
= new_float_abi
;
351 /* If the -mabi option isn't set, then we set the abi according to the arch
352 string. Otherwise, check if there are conflicts between architecture
356 riscv_set_abi_by_arch (void)
360 if (riscv_subset_supports ("q"))
361 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
362 else if (riscv_subset_supports ("d"))
363 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
365 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
369 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
371 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
372 else if (abi_xlen
< xlen
)
373 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
376 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
377 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
378 elf_flags
|= float_abi
<< 1;
381 elf_flags
|= EF_RISCV_RVE
;
384 /* Handle of the OPCODE hash table. */
385 static htab_t op_hash
= NULL
;
387 /* Handle of the type of .insn hash table. */
388 static htab_t insn_type_hash
= NULL
;
390 /* This array holds the chars that always start a comment. If the
391 pre-processor is disabled, these aren't very useful */
392 const char comment_chars
[] = "#";
394 /* This array holds the chars that only start a comment at the beginning of
395 a line. If the line seems to have the form '# 123 filename'
396 .line and .file directives will appear in the pre-processed output */
397 /* Note that input_file.c hand checks for '#' at the beginning of the
398 first line of the input file. This is because the compiler outputs
399 #NO_APP at the beginning of its output. */
400 /* Also note that C style comments are always supported. */
401 const char line_comment_chars
[] = "#";
403 /* This array holds machine specific line separator characters. */
404 const char line_separator_chars
[] = ";";
406 /* Chars that can be used to separate mant from exp in floating point nums */
407 const char EXP_CHARS
[] = "eE";
409 /* Chars that mean this number is a floating point constant */
412 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
414 /* Indicate we are already assemble any instructions or not. */
415 static bfd_boolean start_assemble
= FALSE
;
417 /* Indicate ELF attributes are explicitly set. */
418 static bfd_boolean explicit_attr
= FALSE
;
420 /* Indicate CSR or priv instructions are explicitly used. */
421 static bfd_boolean explicit_priv_attr
= FALSE
;
423 /* Macros for encoding relaxation state for RVC branches and far jumps. */
424 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
427 | ((uncond) ? 1 : 0) \
430 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
431 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
432 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
433 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
435 /* Is the given value a sign-extended 32-bit value? */
436 #define IS_SEXT_32BIT_NUM(x) \
437 (((x) &~ (offsetT) 0x7fffffff) == 0 \
438 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
440 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
441 #define IS_ZEXT_32BIT_NUM(x) \
442 (((x) &~ (offsetT) 0xffffffff) == 0 \
443 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
445 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
446 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
447 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
448 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
450 /* Determine if an instruction matches an opcode. */
451 #define OPCODE_MATCHES(OPCODE, OP) \
452 (((OPCODE) & MASK_##OP) == MATCH_##OP)
454 static char *expr_end
;
456 /* The default target format to use. */
459 riscv_target_format (void)
461 if (target_big_endian
)
462 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
464 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
467 /* Return the length of instruction INSN. */
469 static inline unsigned int
470 insn_length (const struct riscv_cl_insn
*insn
)
472 return riscv_insn_length (insn
->insn_opcode
);
475 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
478 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
481 insn
->insn_opcode
= mo
->match
;
487 /* Install INSN at the location specified by its "frag" and "where" fields. */
490 install_insn (const struct riscv_cl_insn
*insn
)
492 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
493 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
496 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
497 and install the opcode in the new location. */
500 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
504 if (insn
->fixp
!= NULL
)
506 insn
->fixp
->fx_frag
= frag
;
507 insn
->fixp
->fx_where
= where
;
512 /* Add INSN to the end of the output. */
515 add_fixed_insn (struct riscv_cl_insn
*insn
)
517 char *f
= frag_more (insn_length (insn
));
518 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
522 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
523 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
525 frag_grow (max_chars
);
526 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
527 frag_var (rs_machine_dependent
, max_chars
, var
,
528 subtype
, symbol
, offset
, NULL
);
531 /* Compute the length of a branch sequence, and adjust the stored length
532 accordingly. If FRAGP is NULL, the worst-case length is returned. */
535 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
537 int jump
, rvc
, length
= 8;
542 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
543 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
544 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
546 /* Assume jumps are in range; the linker will catch any that aren't. */
547 length
= jump
? 4 : 8;
549 if (fragp
->fr_symbol
!= NULL
550 && S_IS_DEFINED (fragp
->fr_symbol
)
551 && !S_IS_WEAK (fragp
->fr_symbol
)
552 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
554 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
555 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
556 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
558 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
560 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
562 else if (!jump
&& rvc
)
567 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
572 /* Information about an opcode name, mnemonics and its value. */
579 /* List for all supported opcode name. */
580 static const struct opcode_name_t opcode_name_list
[] =
625 /* Hash table for lookup opcode name. */
626 static htab_t opcode_names_hash
= NULL
;
628 /* Initialization for hash table of opcode name. */
630 init_opcode_names_hash (void)
632 const struct opcode_name_t
*opcode
;
634 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
635 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
636 as_fatal (_("duplicate %s"), opcode
->name
);
639 /* Find `s` is a valid opcode name or not,
640 return the opcode name info if found. */
641 static const struct opcode_name_t
*
642 opcode_name_lookup (char **s
)
646 struct opcode_name_t
*o
;
648 /* Find end of name. */
650 if (is_name_beginner (*e
))
652 while (is_part_of_name (*e
))
655 /* Terminate name. */
659 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
661 /* Advance to next token if one was recognized. */
680 static htab_t reg_names_hash
= NULL
;
681 static htab_t csr_extra_hash
= NULL
;
683 #define ENCODE_REG_HASH(cls, n) \
684 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
685 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
686 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
689 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
691 void *hash
= ENCODE_REG_HASH (class, n
);
692 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
693 as_fatal (_("duplicate %s"), name
);
697 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
701 for (i
= 0; i
< n
; i
++)
702 hash_reg_name (class, names
[i
], i
);
705 /* Init hash table csr_extra_hash to handle CSR. */
707 riscv_init_csr_hash (const char *name
,
709 enum riscv_csr_class
class,
710 enum riscv_priv_spec_class define_version
,
711 enum riscv_priv_spec_class abort_version
)
713 struct riscv_csr_extra
*entry
, *pre_entry
;
714 bfd_boolean need_enrty
= TRUE
;
717 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
718 while (need_enrty
&& entry
!= NULL
)
720 if (entry
->csr_class
== class
721 && entry
->address
== address
722 && entry
->define_version
== define_version
723 && entry
->abort_version
== abort_version
)
729 /* Duplicate setting for the CSR, just return and do nothing. */
733 entry
= XNEW (struct riscv_csr_extra
);
734 entry
->csr_class
= class;
735 entry
->address
= address
;
736 entry
->define_version
= define_version
;
737 entry
->abort_version
= abort_version
;
740 /* If the CSR hasn't been inserted in the hash table, then insert it.
741 Otherwise, attach the extra information to the entry which is already
742 in the hash table. */
743 if (pre_entry
== NULL
)
744 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
746 pre_entry
->next
= entry
;
749 /* Return the suitable CSR address after checking the ISA dependency and
750 priv spec versions. */
753 riscv_csr_address (const char *csr_name
,
754 struct riscv_csr_extra
*entry
)
756 struct riscv_csr_extra
*saved_entry
= entry
;
757 enum riscv_csr_class csr_class
= entry
->csr_class
;
758 bfd_boolean need_check_version
= TRUE
;
759 bfd_boolean result
= TRUE
;
764 result
= riscv_subset_supports ("i");
767 result
= (xlen
== 32 && riscv_subset_supports ("i"));
770 result
= riscv_subset_supports ("f");
771 need_check_version
= FALSE
;
773 case CSR_CLASS_DEBUG
:
774 need_check_version
= FALSE
;
777 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
780 /* Don't report the ISA conflict when -mcsr-check isn't set. */
781 if (riscv_opts
.csr_check
&& !result
)
782 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
784 while (entry
!= NULL
)
786 if (!need_check_version
787 || (default_priv_spec
>= entry
->define_version
788 && default_priv_spec
< entry
->abort_version
))
790 /* Find the suitable CSR according to the specific version. */
791 return entry
->address
;
796 /* We can not find the suitable CSR address according to the privilege
797 version. Therefore, we use the last defined value. Report the warning
798 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
799 otherwise, you may get the unexpected CSR address. */
800 if (riscv_opts
.csr_check
)
802 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
804 if (priv_name
!= NULL
)
805 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
806 csr_name
, priv_name
);
809 return saved_entry
->address
;
812 /* Once the CSR is defined, including the old privilege spec, then we call
813 riscv_csr_class_check and riscv_csr_version_check to do the further checking
814 and get the corresponding address. Return -1 if the CSR is never been
815 defined. Otherwise, return the address. */
818 reg_csr_lookup_internal (const char *s
)
820 struct riscv_csr_extra
*r
=
821 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
826 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
827 the CSR was defined, but isn't allowed for the current ISA setting or
828 the privilege spec. If the CSR is never been defined, then assembler
829 will regard it as a "Unknown CSR" and report error. If user use number
830 to set the CSR, but over the range (> 0xfff), then assembler will report
831 "Improper CSR" error for it. */
832 return riscv_csr_address (s
, r
);
836 reg_lookup_internal (const char *s
, enum reg_class
class)
840 if (class == RCLASS_CSR
)
841 return reg_csr_lookup_internal (s
);
843 r
= str_hash_find (reg_names_hash
, s
);
844 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
847 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
850 return DECODE_REG_NUM (r
);
854 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
860 /* Find end of name. */
862 if (is_name_beginner (*e
))
864 while (is_part_of_name (*e
))
867 /* Terminate name. */
871 /* Look for the register. Advance to next token if one was recognized. */
872 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
882 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
884 const char *p
= strchr (*s
, ',');
885 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
890 for (i
= 0; i
< size
; i
++)
891 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
901 /* For consistency checking, verify that all bits are specified either
902 by the match/mask part of the instruction definition, or by the
905 `length` could be 0, 4 or 8, 0 for auto detection. */
907 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
909 const char *p
= opc
->args
;
911 insn_t used_bits
= opc
->mask
;
913 insn_t required_bits
;
916 insn_width
= 8 * riscv_insn_length (opc
->match
);
918 insn_width
= 8 * length
;
920 required_bits
= ~0ULL >> (64 - insn_width
);
922 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
924 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
925 opc
->name
, opc
->args
);
929 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
936 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
937 case 'c': break; /* RS1, constrained to equal sp */
938 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
939 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
940 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
941 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
942 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
943 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
944 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
945 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
946 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
947 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
948 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
949 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
950 case 'w': break; /* RS1S, constrained to equal RD */
951 case 'x': break; /* RS2S, constrained to equal RD */
952 case 'z': break; /* RS2S, contrained to be x0 */
953 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
954 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
955 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
956 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
957 case 'U': break; /* RS1, constrained to equal RD */
958 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
959 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
960 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
961 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
962 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
963 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
964 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
965 case 'F': /* funct */
968 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
969 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
970 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
971 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
973 as_bad (_("internal: bad RISC-V opcode"
974 " (unknown operand type `CF%c'): %s %s"),
975 c
, opc
->name
, opc
->args
);
980 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
981 c
, opc
->name
, opc
->args
);
988 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
989 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
991 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
992 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
993 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
995 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
996 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
997 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
998 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
999 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1000 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1001 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1002 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1003 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1004 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1005 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1007 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1008 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
1009 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
1010 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1011 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1017 case 'F': /* funct */
1020 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1021 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1022 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1024 as_bad (_("internal: bad RISC-V opcode"
1025 " (unknown operand type `F%c'): %s %s"),
1026 c
, opc
->name
, opc
->args
);
1030 case 'O': /* opcode */
1033 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1034 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1036 as_bad (_("internal: bad RISC-V opcode"
1037 " (unknown operand type `F%c'): %s %s"),
1038 c
, opc
->name
, opc
->args
);
1043 as_bad (_("internal: bad RISC-V opcode "
1044 "(unknown operand type `%c'): %s %s"),
1045 c
, opc
->name
, opc
->args
);
1049 if (used_bits
!= required_bits
)
1051 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1052 ~(unsigned long)(used_bits
& required_bits
),
1053 opc
->name
, opc
->args
);
1059 struct percent_op_match
1062 bfd_reloc_code_real_type reloc
;
1065 /* Common hash table initialization function for
1066 instruction and .insn directive. */
1068 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1069 bfd_boolean insn_directive_p
)
1073 htab_t hash
= str_htab_create ();
1074 while (opcodes
[i
].name
)
1076 const char *name
= opcodes
[i
].name
;
1077 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1078 as_fatal (_("duplicate %s"), name
);
1082 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1084 if (insn_directive_p
)
1085 length
= ((name
[0] == 'c') ? 2 : 4);
1087 length
= 0; /* Let assembler determine the length. */
1088 if (!validate_riscv_insn (&opcodes
[i
], length
))
1089 as_fatal (_("Broken assembler. No assembly attempted."));
1092 gas_assert (!insn_directive_p
);
1095 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1101 /* This function is called once, at assembler startup time. It should set up
1102 all the tables, etc. that the MD part of the assembler will need. */
1107 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1109 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1110 as_warn (_("Could not set architecture and machine"));
1112 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1113 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1115 reg_names_hash
= str_htab_create ();
1116 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1117 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1118 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1119 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1120 /* Add "fp" as an alias for "s0". */
1121 hash_reg_name (RCLASS_GPR
, "fp", 8);
1123 /* Create and insert CSR hash tables. */
1124 csr_extra_hash
= str_htab_create ();
1125 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1126 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1127 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1128 DECLARE_CSR(name, num, class, define_version, abort_version);
1129 #include "opcode/riscv-opc.h"
1132 opcode_names_hash
= str_htab_create ();
1133 init_opcode_names_hash ();
1135 /* Set the default alignment for the text section. */
1136 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1140 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1147 case BFD_RELOC_RISCV_HI20
:
1148 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1150 case BFD_RELOC_RISCV_LO12_S
:
1151 return ENCODE_STYPE_IMM (value
);
1153 case BFD_RELOC_RISCV_LO12_I
:
1154 return ENCODE_ITYPE_IMM (value
);
1161 /* Output an instruction. IP is the instruction information.
1162 ADDRESS_EXPR is an operand of the instruction to be used with
1166 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1167 bfd_reloc_code_real_type reloc_type
)
1169 dwarf2_emit_insn (0);
1171 if (reloc_type
!= BFD_RELOC_UNUSED
)
1173 reloc_howto_type
*howto
;
1175 gas_assert (address_expr
);
1176 if (reloc_type
== BFD_RELOC_12_PCREL
1177 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1179 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1180 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1181 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1183 if (now_seg
== absolute_section
)
1185 as_bad (_("relaxable branches not supported in absolute section"));
1189 add_relaxed_insn (ip
, worst_case
, best_case
,
1190 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1191 address_expr
->X_add_symbol
,
1192 address_expr
->X_add_number
);
1197 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1199 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1201 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1202 bfd_get_reloc_size (howto
),
1203 address_expr
, FALSE
, reloc_type
);
1205 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1209 add_fixed_insn (ip
);
1212 /* We need to start a new frag after any instruction that can be
1213 optimized away or compressed by the linker during relaxation, to prevent
1214 the assembler from computing static offsets across such an instruction.
1215 This is necessary to get correct EH info. */
1216 if (reloc_type
== BFD_RELOC_RISCV_HI20
1217 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1218 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1219 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1221 frag_wane (frag_now
);
1226 /* Build an instruction created by a macro expansion. This is passed
1227 a pointer to the count of instructions created so far, an
1228 expression, the name of the instruction to build, an operand format
1229 string, and corresponding arguments. */
1232 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1234 const struct riscv_opcode
*mo
;
1235 struct riscv_cl_insn insn
;
1236 bfd_reloc_code_real_type r
;
1239 va_start (args
, fmt
);
1241 r
= BFD_RELOC_UNUSED
;
1242 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1245 /* Find a non-RVC variant of the instruction. append_insn will compress
1247 while (riscv_insn_length (mo
->match
) < 4)
1249 gas_assert (strcmp (name
, mo
->name
) == 0);
1251 create_insn (&insn
, mo
);
1257 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1261 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1265 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1269 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1275 gas_assert (ep
!= NULL
);
1276 r
= va_arg (args
, int);
1284 as_fatal (_("internal error: invalid macro"));
1289 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1291 append_insn (&insn
, ep
, r
);
1294 /* Build an instruction created by a macro expansion. Like md_assemble but
1295 accept a printf-style format string and arguments. */
1298 md_assemblef (const char *format
, ...)
1304 va_start (ap
, format
);
1306 r
= vasprintf (&buf
, format
, ap
);
1309 as_fatal (_("internal error: vasprintf failed"));
1317 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1320 normalize_constant_expr (expressionS
*ex
)
1324 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1325 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1326 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1330 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1331 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1334 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1335 bfd_boolean maybe_csr
)
1337 if (ex
->X_op
== O_big
)
1338 as_bad (_("unsupported large constant"));
1339 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1340 as_bad (_("unknown CSR `%s'"),
1341 S_GET_NAME (ex
->X_add_symbol
));
1342 else if (ex
->X_op
!= O_constant
)
1343 as_bad (_("Instruction %s requires absolute expression"),
1345 normalize_constant_expr (ex
);
1349 make_internal_label (void)
1351 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1355 /* Load an entry from the GOT. */
1357 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1358 const char *lo_insn
, const char *lo_pattern
,
1359 bfd_reloc_code_real_type hi_reloc
,
1360 bfd_reloc_code_real_type lo_reloc
)
1363 ep2
.X_op
= O_symbol
;
1364 ep2
.X_add_symbol
= make_internal_label ();
1365 ep2
.X_add_number
= 0;
1367 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1368 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1372 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1373 bfd_reloc_code_real_type hi_reloc
,
1374 bfd_reloc_code_real_type lo_reloc
)
1376 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1380 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1381 bfd_reloc_code_real_type hi_reloc
,
1382 bfd_reloc_code_real_type lo_reloc
)
1384 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1387 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1389 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1390 bfd_reloc_code_real_type reloc
)
1392 /* Ensure the jalr is emitted to the same frag as the auipc. */
1394 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1395 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1396 /* See comment at end of append_insn. */
1397 frag_wane (frag_now
);
1401 /* Load an integer constant into a register. */
1404 load_const (int reg
, expressionS
*ep
)
1406 int shift
= RISCV_IMM_BITS
;
1407 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1408 expressionS upper
= *ep
, lower
= *ep
;
1409 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1410 upper
.X_add_number
-= lower
.X_add_number
;
1412 if (ep
->X_op
!= O_constant
)
1414 as_bad (_("unsupported large constant"));
1418 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1420 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1421 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1424 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1425 load_const (reg
, &upper
);
1427 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1428 if (lower
.X_add_number
!= 0)
1429 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1430 lower
.X_add_number
);
1434 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1437 if (upper
.X_add_number
!= 0)
1439 /* Discard low part and zero-extend upper immediate. */
1440 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1442 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1446 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1447 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1448 lower
.X_add_number
);
1452 /* Zero extend and sign extend byte/half-word/word. */
1455 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1459 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1460 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1464 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1465 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1469 /* Expand RISC-V assembly macros into one or more instructions. */
1472 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1473 bfd_reloc_code_real_type
*imm_reloc
)
1475 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1476 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1477 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1478 int mask
= ip
->insn_mo
->mask
;
1483 load_const (rd
, imm_expr
);
1488 /* Load the address of a symbol into a register. */
1489 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1490 as_bad (_("offset too large"));
1492 if (imm_expr
->X_op
== O_constant
)
1493 load_const (rd
, imm_expr
);
1494 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1495 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1496 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1497 else /* Local PIC symbol, or any non-PIC symbol */
1498 pcrel_load (rd
, rd
, imm_expr
, "addi",
1499 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1503 pcrel_load (rd
, rd
, imm_expr
, "addi",
1504 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1508 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1509 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1513 pcrel_load (rd
, rd
, imm_expr
, "lb",
1514 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1518 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1519 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1523 pcrel_load (rd
, rd
, imm_expr
, "lh",
1524 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1528 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1529 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1533 pcrel_load (rd
, rd
, imm_expr
, "lw",
1534 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1538 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1539 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1543 pcrel_load (rd
, rd
, imm_expr
, "ld",
1544 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1548 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1549 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1553 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1554 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1558 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1559 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1563 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1564 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1568 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1569 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1573 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1574 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1578 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1579 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1583 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1584 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1588 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1592 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1596 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1600 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1604 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1608 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1613 static const struct percent_op_match percent_op_utype
[] =
1615 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1616 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1617 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1618 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1619 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1620 {"%hi", BFD_RELOC_RISCV_HI20
},
1624 static const struct percent_op_match percent_op_itype
[] =
1626 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1627 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1628 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1632 static const struct percent_op_match percent_op_stype
[] =
1634 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1635 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1636 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1640 static const struct percent_op_match percent_op_rtype
[] =
1642 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1646 static const struct percent_op_match percent_op_null
[] =
1651 /* Return true if *STR points to a relocation operator. When returning true,
1652 move *STR over the operator and store its relocation code in *RELOC.
1653 Leave both *STR and *RELOC alone when returning false. */
1656 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1657 const struct percent_op_match
*percent_op
)
1659 for ( ; percent_op
->str
; percent_op
++)
1660 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1662 int len
= strlen (percent_op
->str
);
1664 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1667 *str
+= strlen (percent_op
->str
);
1668 *reloc
= percent_op
->reloc
;
1670 /* Check whether the output BFD supports this relocation.
1671 If not, issue an error and fall back on something safe. */
1672 if (*reloc
!= BFD_RELOC_UNUSED
1673 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1675 as_bad ("relocation %s isn't supported by the current ABI",
1677 *reloc
= BFD_RELOC_UNUSED
;
1685 my_getExpression (expressionS
*ep
, char *str
)
1689 save_in
= input_line_pointer
;
1690 input_line_pointer
= str
;
1692 expr_end
= input_line_pointer
;
1693 input_line_pointer
= save_in
;
1696 /* Parse string STR as a 16-bit relocatable operand. Store the
1697 expression in *EP and the relocation, if any, in RELOC.
1698 Return the number of relocation operators used (0 or 1).
1700 On exit, EXPR_END points to the first character after the expression. */
1703 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1704 char *str
, const struct percent_op_match
*percent_op
)
1707 unsigned crux_depth
, str_depth
, regno
;
1710 /* First, check for integer registers. No callers can accept a reg, but
1711 we need to avoid accidentally creating a useless undefined symbol below,
1712 if this is an instruction pattern that can't match. A glibc build fails
1713 if this is removed. */
1714 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1716 ep
->X_op
= O_register
;
1717 ep
->X_add_number
= regno
;
1722 /* Search for the start of the main expression.
1723 End the loop with CRUX pointing to the start
1724 of the main expression and with CRUX_DEPTH containing the number
1725 of open brackets at that point. */
1732 crux_depth
= str_depth
;
1734 /* Skip over whitespace and brackets, keeping count of the number
1736 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1742 && parse_relocation (&str
, reloc
, percent_op
));
1744 my_getExpression (ep
, crux
);
1747 /* Match every open bracket. */
1748 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1753 as_bad ("unclosed '('");
1760 /* Parse opcode name, could be an mnemonics or number. */
1762 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1763 char *str
, const struct percent_op_match
*percent_op
)
1765 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1769 ep
->X_op
= O_constant
;
1770 ep
->X_add_number
= o
->val
;
1774 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1777 /* Detect and handle implicitly zero load-store offsets. For example,
1778 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1779 an implicit offset was detected. */
1782 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1784 /* Check whether there is only a single bracketed expression left.
1785 If so, it must be the base register and the constant must be zero. */
1786 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1788 ep
->X_op
= O_constant
;
1789 ep
->X_add_number
= 0;
1796 /* All RISC-V CSR instructions belong to one of these classes. */
1806 /* Return which CSR instruction is checking. */
1808 static enum csr_insn_type
1809 riscv_csr_insn_type (insn_t insn
)
1811 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1812 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1814 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1815 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1817 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1818 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1821 return INSN_NOT_CSR
;
1824 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1825 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1826 CSR address is 0x3. */
1829 riscv_csr_read_only_check (insn_t insn
)
1831 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1832 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1833 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1834 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1837 && (((csr_insn
== INSN_CSRRS
1838 || csr_insn
== INSN_CSRRC
)
1840 || csr_insn
== INSN_CSRRW
))
1846 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1848 uret is actually a N-ext instruction. So it is better to regard it as
1849 an user instruction rather than the priv instruction.
1851 hret is used to return from traps in H-mode. H-mode is removed since
1852 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1853 Therefore, hret should be controlled by the hypervisor spec rather than
1854 priv spec in the future.
1856 dret is defined in the debug spec, so it should be checked in the future,
1860 riscv_is_priv_insn (insn_t insn
)
1862 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1863 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1864 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1865 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1866 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1867 check it here to keep the compatible. Maybe we should issue warning
1868 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1869 We already have a similar check for CSR, but not yet for instructions.
1870 It would be good if we could check the spec versions both for CSR and
1871 instructions, but not here. */
1872 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1875 /* This routine assembles an instruction into its binary format. As a
1876 side effect, it sets the global variable imm_reloc to the type of
1877 relocation to do if one of the operands is an address expression. */
1880 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1881 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1886 struct riscv_opcode
*insn
;
1891 const struct percent_op_match
*p
;
1892 const char *error
= "unrecognized opcode";
1893 /* Indicate we are assembling instruction with CSR. */
1894 bfd_boolean insn_with_csr
= FALSE
;
1896 /* Parse the name of the instruction. Terminate the string if whitespace
1897 is found so that str_hash_find only sees the name part of the string. */
1898 for (s
= str
; *s
!= '\0'; ++s
)
1906 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1909 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1911 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1914 if (!riscv_multi_subset_supports (insn
->insn_class
))
1917 create_insn (ip
, insn
);
1920 imm_expr
->X_op
= O_absent
;
1921 *imm_reloc
= BFD_RELOC_UNUSED
;
1922 p
= percent_op_itype
;
1924 for (args
= insn
->args
;; ++args
)
1926 s
+= strspn (s
, " \t");
1929 case '\0': /* End of args. */
1930 if (insn
->pinfo
!= INSN_MACRO
)
1932 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1935 /* For .insn, insn->match and insn->mask are 0. */
1936 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1942 if (riscv_is_priv_insn (ip
->insn_opcode
))
1943 explicit_priv_attr
= TRUE
;
1945 /* Check if we write a read-only CSR by the CSR
1948 && riscv_opts
.csr_check
1949 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1951 /* Restore the character in advance, since we want to
1952 report the detailed warning message here. */
1954 *(argsStart
- 1) = save_c
;
1955 as_warn (_("Read-only CSR is written `%s'"), str
);
1956 insn_with_csr
= FALSE
;
1961 /* Successful assembly. */
1963 insn_with_csr
= FALSE
;
1969 case 's': /* RS1 x8-x15 */
1970 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1971 || !(regno
>= 8 && regno
<= 15))
1973 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1975 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1976 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1977 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1980 case 't': /* RS2 x8-x15 */
1981 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1982 || !(regno
>= 8 && regno
<= 15))
1984 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1986 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1987 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1988 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1991 case 'U': /* RS1, constrained to equal RD. */
1992 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1993 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1997 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1999 INSERT_OPERAND (CRS2
, *ip
, regno
);
2001 case 'c': /* RS1, constrained to equal sp. */
2002 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2006 case 'z': /* RS2, contrained to equal x0. */
2007 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2012 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2013 || imm_expr
->X_op
!= O_constant
2014 || imm_expr
->X_add_number
<= 0
2015 || imm_expr
->X_add_number
>= 64)
2017 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2020 imm_expr
->X_op
= O_absent
;
2023 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2024 || imm_expr
->X_op
!= O_constant
2025 || imm_expr
->X_add_number
<= 0
2026 || imm_expr
->X_add_number
>= 32
2027 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2029 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2032 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2033 || imm_expr
->X_op
!= O_constant
2034 || imm_expr
->X_add_number
< 0
2035 || imm_expr
->X_add_number
>= 256
2036 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2038 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2041 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2042 || imm_expr
->X_op
!= O_constant
2043 || imm_expr
->X_add_number
== 0
2044 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2046 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2049 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2050 || imm_expr
->X_op
!= O_constant
2051 || imm_expr
->X_add_number
== 0
2052 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2054 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2057 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2059 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2060 || imm_expr
->X_op
!= O_constant
2061 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2063 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2066 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2068 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2069 || imm_expr
->X_op
!= O_constant
2070 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2072 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2075 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2077 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2078 || imm_expr
->X_op
!= O_constant
2079 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2082 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2085 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2087 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2088 || imm_expr
->X_op
!= O_constant
2089 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2092 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2095 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2096 || imm_expr
->X_op
!= O_constant
2097 /* C.addiw, c.li, and c.andi allow zero immediate.
2098 C.addi allows zero immediate as hint. Otherwise this
2100 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2102 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2105 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2106 || imm_expr
->X_op
!= O_constant
2107 || imm_expr
->X_add_number
== 0
2108 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2111 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2114 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2115 || imm_expr
->X_op
!= O_constant
2116 || imm_expr
->X_add_number
== 0
2117 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2120 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2123 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2125 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2126 || imm_expr
->X_op
!= O_constant
2127 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2130 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2133 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2135 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2136 || imm_expr
->X_op
!= O_constant
2137 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2140 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2143 p
= percent_op_utype
;
2144 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2147 if (imm_expr
->X_op
!= O_constant
2148 || imm_expr
->X_add_number
<= 0
2149 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2150 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2151 && (imm_expr
->X_add_number
<
2152 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2154 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2157 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2158 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2159 || ((int32_t)imm_expr
->X_add_number
2160 != imm_expr
->X_add_number
))
2162 imm_expr
->X_add_number
=
2163 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2169 case 'S': /* Floating-point RS1 x8-x15. */
2170 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2171 || !(regno
>= 8 && regno
<= 15))
2173 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2175 case 'D': /* Floating-point RS2 x8-x15. */
2176 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2177 || !(regno
>= 8 && regno
<= 15))
2179 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2181 case 'T': /* Floating-point RS2. */
2182 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2184 INSERT_OPERAND (CRS2
, *ip
, regno
);
2190 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2191 || imm_expr
->X_op
!= O_constant
2192 || imm_expr
->X_add_number
< 0
2193 || imm_expr
->X_add_number
>= 64)
2195 as_bad (_("bad value for funct6 field, "
2196 "value must be 0...64"));
2200 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2201 imm_expr
->X_op
= O_absent
;
2205 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2206 || imm_expr
->X_op
!= O_constant
2207 || imm_expr
->X_add_number
< 0
2208 || imm_expr
->X_add_number
>= 16)
2210 as_bad (_("bad value for funct4 field, "
2211 "value must be 0...15"));
2215 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2216 imm_expr
->X_op
= O_absent
;
2220 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2221 || imm_expr
->X_op
!= O_constant
2222 || imm_expr
->X_add_number
< 0
2223 || imm_expr
->X_add_number
>= 8)
2225 as_bad (_("bad value for funct3 field, "
2226 "value must be 0...7"));
2229 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2230 imm_expr
->X_op
= O_absent
;
2234 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2235 || imm_expr
->X_op
!= O_constant
2236 || imm_expr
->X_add_number
< 0
2237 || imm_expr
->X_add_number
>= 4)
2239 as_bad (_("bad value for funct2 field, "
2240 "value must be 0...3"));
2243 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2244 imm_expr
->X_op
= O_absent
;
2248 as_bad (_("bad compressed FUNCT field"
2249 " specifier 'CF%c'\n"),
2255 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2274 case '<': /* Shift amount, 0 - 31. */
2275 my_getExpression (imm_expr
, s
);
2276 check_absolute_expr (ip
, imm_expr
, FALSE
);
2277 if ((unsigned long) imm_expr
->X_add_number
> 31)
2278 as_bad (_("Improper shift amount (%lu)"),
2279 (unsigned long) imm_expr
->X_add_number
);
2280 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2281 imm_expr
->X_op
= O_absent
;
2285 case '>': /* Shift amount, 0 - (XLEN-1). */
2286 my_getExpression (imm_expr
, s
);
2287 check_absolute_expr (ip
, imm_expr
, FALSE
);
2288 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2289 as_bad (_("Improper shift amount (%lu)"),
2290 (unsigned long) imm_expr
->X_add_number
);
2291 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2292 imm_expr
->X_op
= O_absent
;
2296 case 'Z': /* CSRRxI immediate. */
2297 my_getExpression (imm_expr
, s
);
2298 check_absolute_expr (ip
, imm_expr
, FALSE
);
2299 if ((unsigned long) imm_expr
->X_add_number
> 31)
2300 as_bad (_("Improper CSRxI immediate (%lu)"),
2301 (unsigned long) imm_expr
->X_add_number
);
2302 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2303 imm_expr
->X_op
= O_absent
;
2307 case 'E': /* Control register. */
2308 insn_with_csr
= TRUE
;
2309 explicit_priv_attr
= TRUE
;
2310 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2311 INSERT_OPERAND (CSR
, *ip
, regno
);
2314 my_getExpression (imm_expr
, s
);
2315 check_absolute_expr (ip
, imm_expr
, TRUE
);
2316 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2317 as_bad (_("Improper CSR address (%lu)"),
2318 (unsigned long) imm_expr
->X_add_number
);
2319 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2320 imm_expr
->X_op
= O_absent
;
2325 case 'm': /* Rounding mode. */
2326 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2328 INSERT_OPERAND (RM
, *ip
, regno
);
2334 case 'Q': /* Fence predecessor/successor. */
2335 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2339 INSERT_OPERAND (PRED
, *ip
, regno
);
2341 INSERT_OPERAND (SUCC
, *ip
, regno
);
2346 case 'd': /* Destination register. */
2347 case 's': /* Source register. */
2348 case 't': /* Target register. */
2349 case 'r': /* rs3. */
2350 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2356 /* Now that we have assembled one operand, we use the args
2357 string to figure out where it goes in the instruction. */
2361 INSERT_OPERAND (RS1
, *ip
, regno
);
2364 INSERT_OPERAND (RD
, *ip
, regno
);
2367 INSERT_OPERAND (RS2
, *ip
, regno
);
2370 INSERT_OPERAND (RS3
, *ip
, regno
);
2377 case 'D': /* Floating point rd. */
2378 case 'S': /* Floating point rs1. */
2379 case 'T': /* Floating point rs2. */
2380 case 'U': /* Floating point rs1 and rs2. */
2381 case 'R': /* Floating point rs3. */
2382 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2390 INSERT_OPERAND (RD
, *ip
, regno
);
2393 INSERT_OPERAND (RS1
, *ip
, regno
);
2396 INSERT_OPERAND (RS1
, *ip
, regno
);
2399 INSERT_OPERAND (RS2
, *ip
, regno
);
2402 INSERT_OPERAND (RS3
, *ip
, regno
);
2411 my_getExpression (imm_expr
, s
);
2412 if (imm_expr
->X_op
!= O_big
2413 && imm_expr
->X_op
!= O_constant
)
2415 normalize_constant_expr (imm_expr
);
2420 my_getExpression (imm_expr
, s
);
2421 normalize_constant_expr (imm_expr
);
2422 /* The 'A' format specifier must be a symbol. */
2423 if (imm_expr
->X_op
!= O_symbol
)
2425 *imm_reloc
= BFD_RELOC_32
;
2430 my_getExpression (imm_expr
, s
);
2431 normalize_constant_expr (imm_expr
);
2432 /* The 'B' format specifier must be a symbol or a constant. */
2433 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2435 if (imm_expr
->X_op
== O_symbol
)
2436 *imm_reloc
= BFD_RELOC_32
;
2440 case 'j': /* Sign-extended immediate. */
2441 p
= percent_op_itype
;
2442 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2444 case 'q': /* Store displacement. */
2445 p
= percent_op_stype
;
2446 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2448 case 'o': /* Load displacement. */
2449 p
= percent_op_itype
;
2450 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2452 case '1': /* 4-operand add, must be %tprel_add. */
2453 p
= percent_op_rtype
;
2455 case '0': /* AMO "displacement," which must be zero. */
2456 p
= percent_op_null
;
2458 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2461 /* If this value won't fit into a 16 bit offset, then go
2462 find a macro that will generate the 32 bit offset
2464 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2466 normalize_constant_expr (imm_expr
);
2467 if (imm_expr
->X_op
!= O_constant
2468 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2470 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2471 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2478 case 'p': /* PC-relative offset. */
2480 *imm_reloc
= BFD_RELOC_12_PCREL
;
2481 my_getExpression (imm_expr
, s
);
2485 case 'u': /* Upper 20 bits. */
2486 p
= percent_op_utype
;
2487 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2489 if (imm_expr
->X_op
!= O_constant
)
2492 if (imm_expr
->X_add_number
< 0
2493 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2494 as_bad (_("lui expression not in range 0..1048575"));
2496 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2497 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2502 case 'a': /* 20-bit PC-relative offset. */
2504 my_getExpression (imm_expr
, s
);
2506 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2510 my_getExpression (imm_expr
, s
);
2512 if (strcmp (s
, "@plt") == 0)
2514 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2518 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2524 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2525 || imm_expr
->X_op
!= O_constant
2526 || imm_expr
->X_add_number
< 0
2527 || imm_expr
->X_add_number
>= 128
2528 || (imm_expr
->X_add_number
& 0x3) != 3)
2530 as_bad (_("bad value for opcode field, "
2531 "value must be 0...127 and "
2532 "lower 2 bits must be 0x3"));
2536 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2537 imm_expr
->X_op
= O_absent
;
2541 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2542 || imm_expr
->X_op
!= O_constant
2543 || imm_expr
->X_add_number
< 0
2544 || imm_expr
->X_add_number
>= 3)
2546 as_bad (_("bad value for opcode field, "
2547 "value must be 0...2"));
2551 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2552 imm_expr
->X_op
= O_absent
;
2556 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2564 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2565 || imm_expr
->X_op
!= O_constant
2566 || imm_expr
->X_add_number
< 0
2567 || imm_expr
->X_add_number
>= 128)
2569 as_bad (_("bad value for funct7 field, "
2570 "value must be 0...127"));
2574 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2575 imm_expr
->X_op
= O_absent
;
2579 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2580 || imm_expr
->X_op
!= O_constant
2581 || imm_expr
->X_add_number
< 0
2582 || imm_expr
->X_add_number
>= 8)
2584 as_bad (_("bad value for funct3 field, "
2585 "value must be 0...7"));
2589 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2590 imm_expr
->X_op
= O_absent
;
2594 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2595 || imm_expr
->X_op
!= O_constant
2596 || imm_expr
->X_add_number
< 0
2597 || imm_expr
->X_add_number
>= 4)
2599 as_bad (_("bad value for funct2 field, "
2600 "value must be 0...3"));
2604 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2605 imm_expr
->X_op
= O_absent
;
2610 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2615 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2616 || imm_expr
->X_op
!= O_constant
2617 || imm_expr
->X_add_number
!= 0)
2620 imm_expr
->X_op
= O_absent
;
2624 as_fatal (_("internal error: bad argument type %c"), *args
);
2629 error
= _("illegal operands");
2630 insn_with_csr
= FALSE
;
2634 /* Restore the character we might have clobbered above. */
2636 *(argsStart
- 1) = save_c
;
2642 md_assemble (char *str
)
2644 struct riscv_cl_insn insn
;
2645 expressionS imm_expr
;
2646 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2648 /* The arch and priv attributes should be set before assembling. */
2649 if (!start_assemble
)
2651 start_assemble
= TRUE
;
2652 riscv_set_abi_by_arch ();
2654 /* Set the default_priv_spec according to the priv attributes. */
2655 if (!riscv_set_default_priv_spec (NULL
))
2659 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2663 as_bad ("%s `%s'", error
, str
);
2667 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2668 macro (&insn
, &imm_expr
, &imm_reloc
);
2670 append_insn (&insn
, &imm_expr
, imm_reloc
);
2674 md_atof (int type
, char *litP
, int *sizeP
)
2676 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2680 md_number_to_chars (char *buf
, valueT val
, int n
)
2682 if (target_big_endian
)
2683 number_to_chars_bigendian (buf
, val
, n
);
2685 number_to_chars_littleendian (buf
, val
, n
);
2688 const char *md_shortopts
= "O::g::G:";
2692 OPTION_MARCH
= OPTION_MD_BASE
,
2699 OPTION_NO_ARCH_ATTR
,
2701 OPTION_NO_CSR_CHECK
,
2705 OPTION_LITTLE_ENDIAN
,
2709 struct option md_longopts
[] =
2711 {"march", required_argument
, NULL
, OPTION_MARCH
},
2712 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2713 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2714 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2715 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2716 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2717 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2718 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2719 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2720 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2721 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2722 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2723 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2724 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2725 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2727 {NULL
, no_argument
, NULL
, 0}
2729 size_t md_longopts_size
= sizeof (md_longopts
);
2732 md_parse_option (int c
, const char *arg
)
2737 /* riscv_after_parse_args will call riscv_set_arch to parse
2738 the architecture. */
2739 default_arch_with_ext
= arg
;
2743 riscv_opts
.pic
= FALSE
;
2747 riscv_opts
.pic
= TRUE
;
2751 if (strcmp (arg
, "ilp32") == 0)
2752 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2753 else if (strcmp (arg
, "ilp32e") == 0)
2754 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2755 else if (strcmp (arg
, "ilp32f") == 0)
2756 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2757 else if (strcmp (arg
, "ilp32d") == 0)
2758 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2759 else if (strcmp (arg
, "ilp32q") == 0)
2760 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2761 else if (strcmp (arg
, "lp64") == 0)
2762 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2763 else if (strcmp (arg
, "lp64f") == 0)
2764 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2765 else if (strcmp (arg
, "lp64d") == 0)
2766 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2767 else if (strcmp (arg
, "lp64q") == 0)
2768 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2771 explicit_mabi
= TRUE
;
2775 riscv_opts
.relax
= TRUE
;
2778 case OPTION_NO_RELAX
:
2779 riscv_opts
.relax
= FALSE
;
2782 case OPTION_ARCH_ATTR
:
2783 riscv_opts
.arch_attr
= TRUE
;
2786 case OPTION_NO_ARCH_ATTR
:
2787 riscv_opts
.arch_attr
= FALSE
;
2790 case OPTION_CSR_CHECK
:
2791 riscv_opts
.csr_check
= TRUE
;
2794 case OPTION_NO_CSR_CHECK
:
2795 riscv_opts
.csr_check
= FALSE
;
2798 case OPTION_MISA_SPEC
:
2799 return riscv_set_default_isa_spec (arg
);
2801 case OPTION_MPRIV_SPEC
:
2802 return riscv_set_default_priv_spec (arg
);
2804 case OPTION_BIG_ENDIAN
:
2805 target_big_endian
= 1;
2808 case OPTION_LITTLE_ENDIAN
:
2809 target_big_endian
= 0;
2820 riscv_after_parse_args (void)
2822 /* The --with-arch is optional for now, so we have to set the xlen
2823 according to the default_arch, which is set by the --targte, first.
2824 Then, we use the xlen to set the default_arch_with_ext if the
2825 -march and --with-arch are not set. */
2828 if (strcmp (default_arch
, "riscv32") == 0)
2830 else if (strcmp (default_arch
, "riscv64") == 0)
2833 as_bad ("unknown default architecture `%s'", default_arch
);
2835 if (default_arch_with_ext
== NULL
)
2836 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2838 /* Initialize the hash table for extensions with default version. */
2839 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2841 /* If the -misa-spec isn't set, then we set the default ISA spec according
2842 to DEFAULT_RISCV_ISA_SPEC. */
2843 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2844 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2846 /* Set the architecture according to -march or or --with-arch. */
2847 riscv_set_arch (default_arch_with_ext
);
2849 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2850 riscv_set_rvc (FALSE
);
2851 if (riscv_subset_supports ("c"))
2852 riscv_set_rvc (TRUE
);
2854 /* Enable RVE if specified by the -march option. */
2855 riscv_set_rve (FALSE
);
2856 if (riscv_subset_supports ("e"))
2857 riscv_set_rve (TRUE
);
2859 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2860 according to DEFAULT_PRIV_SPEC. */
2861 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2862 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2864 /* If the CIE to be produced has not been overridden on the command line,
2865 then produce version 3 by default. This allows us to use the full
2866 range of registers in a .cfi_return_column directive. */
2867 if (flag_dwarf_cie_version
== -1)
2868 flag_dwarf_cie_version
= 3;
2872 md_pcrel_from (fixS
*fixP
)
2874 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2877 /* Apply a fixup to the object file. */
2880 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2882 unsigned int subtype
;
2883 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2884 bfd_boolean relaxable
= FALSE
;
2888 /* Remember value for tc_gen_reloc. */
2889 fixP
->fx_addnumber
= *valP
;
2891 switch (fixP
->fx_r_type
)
2893 case BFD_RELOC_RISCV_HI20
:
2894 case BFD_RELOC_RISCV_LO12_I
:
2895 case BFD_RELOC_RISCV_LO12_S
:
2896 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2897 | bfd_getl32 (buf
), buf
);
2898 if (fixP
->fx_addsy
== NULL
)
2899 fixP
->fx_done
= TRUE
;
2903 case BFD_RELOC_RISCV_GOT_HI20
:
2904 case BFD_RELOC_RISCV_ADD8
:
2905 case BFD_RELOC_RISCV_ADD16
:
2906 case BFD_RELOC_RISCV_ADD32
:
2907 case BFD_RELOC_RISCV_ADD64
:
2908 case BFD_RELOC_RISCV_SUB6
:
2909 case BFD_RELOC_RISCV_SUB8
:
2910 case BFD_RELOC_RISCV_SUB16
:
2911 case BFD_RELOC_RISCV_SUB32
:
2912 case BFD_RELOC_RISCV_SUB64
:
2913 case BFD_RELOC_RISCV_RELAX
:
2916 case BFD_RELOC_RISCV_TPREL_HI20
:
2917 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2918 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2919 case BFD_RELOC_RISCV_TPREL_ADD
:
2923 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2924 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2925 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2926 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2927 if (fixP
->fx_addsy
!= NULL
)
2928 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2931 _("TLS relocation against a constant"));
2935 /* Use pc-relative relocation for FDE initial location.
2936 The symbol address in .eh_frame may be adjusted in
2937 _bfd_elf_discard_section_eh_frame, and the content of
2938 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2939 Therefore, we cannot insert a relocation whose addend symbol is
2940 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2941 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2942 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2943 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2944 && S_GET_VALUE (fixP
->fx_subsy
)
2945 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2947 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2948 fixP
->fx_subsy
= NULL
;
2955 case BFD_RELOC_RISCV_CFA
:
2956 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2958 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2959 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2960 fixP
->fx_next
->fx_subsy
= NULL
;
2961 fixP
->fx_next
->fx_offset
= 0;
2962 fixP
->fx_subsy
= NULL
;
2964 switch (fixP
->fx_r_type
)
2967 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2968 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2972 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2973 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2977 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2978 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2982 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2983 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2986 case BFD_RELOC_RISCV_CFA
:
2987 /* Load the byte to get the subtype. */
2988 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2989 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2992 case DW_CFA_advance_loc1
:
2993 fixP
->fx_where
= loc
+ 1;
2994 fixP
->fx_next
->fx_where
= loc
+ 1;
2995 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2996 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2999 case DW_CFA_advance_loc2
:
3001 fixP
->fx_next
->fx_size
= 2;
3002 fixP
->fx_where
= loc
+ 1;
3003 fixP
->fx_next
->fx_where
= loc
+ 1;
3004 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3005 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3008 case DW_CFA_advance_loc4
:
3010 fixP
->fx_next
->fx_size
= 4;
3011 fixP
->fx_where
= loc
;
3012 fixP
->fx_next
->fx_where
= loc
;
3013 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3014 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3018 if (subtype
< 0x80 && (subtype
& 0x40))
3020 /* DW_CFA_advance_loc */
3021 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3022 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3023 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3024 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3027 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
3033 /* This case is unreachable. */
3040 /* If we are deleting this reloc entry, we must fill in the
3041 value now. This can happen if we have a .word which is not
3042 resolved when it appears but is later defined. */
3043 if (fixP
->fx_addsy
== NULL
)
3045 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3046 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3051 case BFD_RELOC_RISCV_JMP
:
3054 /* Fill in a tentative value to improve objdump readability. */
3055 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3056 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3057 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3061 case BFD_RELOC_12_PCREL
:
3064 /* Fill in a tentative value to improve objdump readability. */
3065 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3066 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3067 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3071 case BFD_RELOC_RISCV_RVC_BRANCH
:
3074 /* Fill in a tentative value to improve objdump readability. */
3075 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3076 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3077 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3081 case BFD_RELOC_RISCV_RVC_JUMP
:
3084 /* Fill in a tentative value to improve objdump readability. */
3085 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3086 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3087 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3091 case BFD_RELOC_RISCV_CALL
:
3092 case BFD_RELOC_RISCV_CALL_PLT
:
3096 case BFD_RELOC_RISCV_PCREL_HI20
:
3097 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3098 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3099 relaxable
= riscv_opts
.relax
;
3102 case BFD_RELOC_RISCV_ALIGN
:
3106 /* We ignore generic BFD relocations we don't know about. */
3107 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3108 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3111 if (fixP
->fx_subsy
!= NULL
)
3112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3113 _("unsupported symbol subtraction"));
3115 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3116 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3118 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3119 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3120 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3121 fixP
->fx_next
->fx_size
= 0;
3125 /* Because the value of .cfi_remember_state may changed after relaxation,
3126 we insert a fix to relocate it again in link-time. */
3129 riscv_pre_output_hook (void)
3131 const frchainS
*frch
;
3134 /* Save the current segment info. */
3136 subsegT subseg
= now_subseg
;
3138 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3139 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3143 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3145 if (frag
->fr_type
== rs_cfa
)
3148 expressionS
*symval
;
3150 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3151 exp
.X_op
= O_subtract
;
3152 exp
.X_add_symbol
= symval
->X_add_symbol
;
3153 exp
.X_add_number
= 0;
3154 exp
.X_op_symbol
= symval
->X_op_symbol
;
3156 /* We must set the segment before creating a frag after all
3157 frag chains have been chained together. */
3158 subseg_set (s
, frch
->frch_subseg
);
3160 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3161 BFD_RELOC_RISCV_CFA
);
3166 /* Restore the original segment info. */
3167 subseg_set (seg
, subseg
);
3171 /* This structure is used to hold a stack of .option values. */
3173 struct riscv_option_stack
3175 struct riscv_option_stack
*next
;
3176 struct riscv_set_options options
;
3179 static struct riscv_option_stack
*riscv_opts_stack
;
3181 /* Handle the .option pseudo-op. */
3184 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3186 char *name
= input_line_pointer
, ch
;
3188 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3189 ++input_line_pointer
;
3190 ch
= *input_line_pointer
;
3191 *input_line_pointer
= '\0';
3193 if (strcmp (name
, "rvc") == 0)
3194 riscv_set_rvc (TRUE
);
3195 else if (strcmp (name
, "norvc") == 0)
3196 riscv_set_rvc (FALSE
);
3197 else if (strcmp (name
, "pic") == 0)
3198 riscv_opts
.pic
= TRUE
;
3199 else if (strcmp (name
, "nopic") == 0)
3200 riscv_opts
.pic
= FALSE
;
3201 else if (strcmp (name
, "relax") == 0)
3202 riscv_opts
.relax
= TRUE
;
3203 else if (strcmp (name
, "norelax") == 0)
3204 riscv_opts
.relax
= FALSE
;
3205 else if (strcmp (name
, "csr-check") == 0)
3206 riscv_opts
.csr_check
= TRUE
;
3207 else if (strcmp (name
, "no-csr-check") == 0)
3208 riscv_opts
.csr_check
= FALSE
;
3209 else if (strcmp (name
, "push") == 0)
3211 struct riscv_option_stack
*s
;
3213 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3214 s
->next
= riscv_opts_stack
;
3215 s
->options
= riscv_opts
;
3216 riscv_opts_stack
= s
;
3218 else if (strcmp (name
, "pop") == 0)
3220 struct riscv_option_stack
*s
;
3222 s
= riscv_opts_stack
;
3224 as_bad (_(".option pop with no .option push"));
3227 riscv_opts
= s
->options
;
3228 riscv_opts_stack
= s
->next
;
3234 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3236 *input_line_pointer
= ch
;
3237 demand_empty_rest_of_line ();
3240 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3241 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3242 use in DWARF debug information. */
3245 s_dtprel (int bytes
)
3252 if (ex
.X_op
!= O_symbol
)
3254 as_bad (_("Unsupported use of %s"), (bytes
== 8
3257 ignore_rest_of_line ();
3260 p
= frag_more (bytes
);
3261 md_number_to_chars (p
, 0, bytes
);
3262 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3264 ? BFD_RELOC_RISCV_TLS_DTPREL64
3265 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3267 demand_empty_rest_of_line ();
3270 /* Handle the .bss pseudo-op. */
3273 s_bss (int ignore ATTRIBUTE_UNUSED
)
3275 subseg_set (bss_section
, 0);
3276 demand_empty_rest_of_line ();
3280 riscv_make_nops (char *buf
, bfd_vma bytes
)
3284 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3285 means we are not within a valid instruction sequence. It is thus safe
3286 to use a zero byte, even though that is not a valid instruction. */
3290 /* Use at most one 2-byte NOP. */
3291 if ((bytes
- i
) % 4 == 2)
3293 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3297 /* Fill the remainder with 4-byte NOPs. */
3298 for ( ; i
< bytes
; i
+= 4)
3299 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3302 /* Called from md_do_align. Used to create an alignment frag in a
3303 code section by emitting a worst-case NOP sequence that the linker
3304 will later relax to the correct number of NOPs. We can't compute
3305 the correct alignment now because of other linker relaxations. */
3308 riscv_frag_align_code (int n
)
3310 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3311 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3312 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3316 /* If we are moving to a smaller alignment than the instruction size, then no
3317 alignment is required. */
3318 if (bytes
<= insn_alignment
)
3321 /* When not relaxing, riscv_handle_align handles code alignment. */
3322 if (!riscv_opts
.relax
)
3325 nops
= frag_more (worst_case_bytes
);
3327 ex
.X_op
= O_constant
;
3328 ex
.X_add_number
= worst_case_bytes
;
3330 riscv_make_nops (nops
, worst_case_bytes
);
3332 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3333 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3338 /* Implement HANDLE_ALIGN. */
3341 riscv_handle_align (fragS
*fragP
)
3343 switch (fragP
->fr_type
)
3346 /* When relaxing, riscv_frag_align_code handles code alignment. */
3347 if (!riscv_opts
.relax
)
3349 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3350 - fragP
->fr_address
- fragP
->fr_fix
);
3351 /* We have 4 byte uncompressed nops. */
3352 bfd_signed_vma size
= 4;
3353 bfd_signed_vma excess
= bytes
% size
;
3354 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3359 /* Insert zeros or compressed nops to get 4 byte alignment. */
3362 riscv_make_nops (p
, excess
);
3363 fragP
->fr_fix
+= excess
;
3367 /* Insert variable number of 4 byte uncompressed nops. */
3368 riscv_make_nops (p
, size
);
3369 fragP
->fr_var
= size
;
3379 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3381 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3384 /* Translate internal representation of relocation info to BFD target
3388 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3390 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3392 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3393 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3394 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3395 reloc
->addend
= fixp
->fx_addnumber
;
3397 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3398 if (reloc
->howto
== NULL
)
3400 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3401 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3403 /* We don't have R_RISCV_8/16, but for this special case,
3404 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3408 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3409 _("cannot represent %s relocation in object file"),
3410 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3418 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3420 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3422 offsetT old_var
= fragp
->fr_var
;
3423 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3424 return fragp
->fr_var
- old_var
;
3430 /* Expand far branches to multi-instruction sequences. */
3433 md_convert_frag_branch (fragS
*fragp
)
3441 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3443 exp
.X_op
= O_symbol
;
3444 exp
.X_add_symbol
= fragp
->fr_symbol
;
3445 exp
.X_add_number
= fragp
->fr_offset
;
3447 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3449 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3451 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3455 /* Expand the RVC branch into a RISC-V one. */
3456 insn
= bfd_getl16 (buf
);
3457 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3458 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3460 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3461 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3462 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3463 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3464 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3465 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3468 bfd_putl32 (insn
, buf
);
3472 /* Invert the branch condition. Branch over the jump. */
3473 insn
= bfd_getl16 (buf
);
3474 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3475 insn
|= ENCODE_RVC_B_IMM (6);
3476 bfd_putl16 (insn
, buf
);
3481 /* Just keep the RVC branch. */
3482 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3483 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3484 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3485 2, &exp
, FALSE
, reloc
);
3494 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3497 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3499 /* Invert the branch condition. Branch over the jump. */
3500 insn
= bfd_getl32 (buf
);
3501 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3502 insn
|= ENCODE_SBTYPE_IMM (8);
3503 bfd_putl32 (insn
, buf
);
3507 /* Jump to the target. */
3508 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3509 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3510 bfd_putl32 (MATCH_JAL
, buf
);
3515 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3516 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3517 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3518 4, &exp
, FALSE
, reloc
);
3527 fixp
->fx_file
= fragp
->fr_file
;
3528 fixp
->fx_line
= fragp
->fr_line
;
3530 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3531 + fragp
->fr_fix
+ fragp
->fr_var
);
3533 fragp
->fr_fix
+= fragp
->fr_var
;
3536 /* Relax a machine dependent frag. This returns the amount by which
3537 the current size of the frag should change. */
3540 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3543 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3544 md_convert_frag_branch (fragp
);
3548 md_show_usage (FILE *stream
)
3550 fprintf (stream
, _("\
3552 -fpic generate position-independent code\n\
3553 -fno-pic don't generate position-independent code (default)\n\
3554 -march=ISA set the RISC-V architecture\n\
3555 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3556 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3557 -mabi=ABI set the RISC-V ABI\n\
3558 -mrelax enable relax (default)\n\
3559 -mno-relax disable relax\n\
3560 -march-attr generate RISC-V arch attribute\n\
3561 -mno-arch-attr don't generate RISC-V arch attribute\n\
3565 /* Standard calling conventions leave the CFA at SP on entry. */
3567 riscv_cfi_frame_initial_instructions (void)
3569 cfi_add_CFA_def_cfa_register (X_SP
);
3573 tc_riscv_regname_to_dw2regnum (char *regname
)
3577 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3580 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3583 /* CSRs are numbered 4096 -> 8191. */
3584 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3587 as_bad (_("unknown register `%s'"), regname
);
3592 riscv_elf_final_processing (void)
3594 riscv_set_abi_by_arch ();
3595 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3598 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3599 since these directives break relaxation when used with symbol deltas. */
3602 s_riscv_leb128 (int sign
)
3605 char *save_in
= input_line_pointer
;
3608 if (exp
.X_op
!= O_constant
)
3609 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3610 demand_empty_rest_of_line ();
3612 input_line_pointer
= save_in
;
3613 return s_leb128 (sign
);
3616 /* Parse the .insn directive. */
3619 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3621 char *str
= input_line_pointer
;
3622 struct riscv_cl_insn insn
;
3623 expressionS imm_expr
;
3624 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3627 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3628 ++input_line_pointer
;
3630 save_c
= *input_line_pointer
;
3631 *input_line_pointer
= '\0';
3633 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3634 &imm_reloc
, insn_type_hash
);
3638 as_bad ("%s `%s'", error
, str
);
3642 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3643 append_insn (&insn
, &imm_expr
, imm_reloc
);
3646 *input_line_pointer
= save_c
;
3647 demand_empty_rest_of_line ();
3650 /* Update arch and priv attributes. If we don't set the corresponding ELF
3651 attributes, then try to output the default ones. */
3654 riscv_write_out_attrs (void)
3656 const char *arch_str
, *priv_str
, *p
;
3657 /* versions[0] is major, versions[1] is minor,
3658 and versions[3] is revision. */
3659 unsigned versions
[3] = {0}, number
= 0;
3662 /* Re-write arch attribute to normalize the arch string. */
3663 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3664 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3665 xfree ((void *)arch_str
);
3667 /* For the file without any instruction, we don't set the default_priv_spec
3668 according to the priv attributes since the md_assemble isn't called.
3669 Call riscv_set_default_priv_spec here for the above case, although
3670 it seems strange. */
3672 && !riscv_set_default_priv_spec (NULL
))
3675 /* If we already have set elf priv attributes, then no need to do anything,
3676 assembler will generate them according to what you set. Otherwise, don't
3677 generate or update them when no CSR and priv instructions are used.
3678 Generate the priv attributes according to default_priv_spec, which can be
3679 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3680 priv attribute sets. */
3681 if (!explicit_priv_attr
)
3684 /* Re-write priv attributes by default_priv_spec. */
3685 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3687 for (i
= 0; *p
; ++p
)
3689 if (*p
== '.' && i
< 3)
3691 versions
[i
++] = number
;
3694 else if (ISDIGIT (*p
))
3695 number
= (number
* 10) + (*p
- '0');
3698 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3702 versions
[i
] = number
;
3704 /* Set the priv attributes. */
3705 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3706 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3707 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3710 /* Add the default contents for the .riscv.attributes section. If any
3711 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3712 to update the arch and priv attributes. */
3715 riscv_set_public_attributes (void)
3717 if (riscv_opts
.arch_attr
|| explicit_attr
)
3718 riscv_write_out_attrs ();
3721 /* Called after all assembly has been done. */
3726 riscv_set_public_attributes ();
3729 /* Given a symbolic attribute NAME, return the proper integer value.
3730 Returns -1 if the attribute is not known. */
3733 riscv_convert_symbolic_attribute (const char *name
)
3742 /* When you modify this table you should
3743 also modify the list in doc/c-riscv.texi. */
3744 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3748 T(priv_spec_revision
),
3749 T(unaligned_access
),
3759 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3760 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3761 return attribute_table
[i
].tag
;
3766 /* Parse a .attribute directive. */
3769 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3771 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3773 obj_attribute
*attr
;
3775 explicit_attr
= TRUE
;
3778 case Tag_RISCV_arch
:
3780 attr
= elf_known_obj_attributes_proc (stdoutput
);
3781 if (!start_assemble
)
3782 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3784 as_fatal (_(".attribute arch must set before any instructions"));
3786 if (old_xlen
!= xlen
)
3788 /* We must re-init bfd again if xlen is changed. */
3789 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3790 bfd_find_target (riscv_target_format (), stdoutput
);
3792 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3793 as_warn (_("Could not set architecture and machine"));
3797 case Tag_RISCV_priv_spec
:
3798 case Tag_RISCV_priv_spec_minor
:
3799 case Tag_RISCV_priv_spec_revision
:
3801 as_fatal (_(".attribute priv spec must set before any instructions"));
3809 /* Pseudo-op table. */
3811 static const pseudo_typeS riscv_pseudo_table
[] =
3813 /* RISC-V-specific pseudo-ops. */
3814 {"option", s_riscv_option
, 0},
3818 {"dtprelword", s_dtprel
, 4},
3819 {"dtpreldword", s_dtprel
, 8},
3821 {"uleb128", s_riscv_leb128
, 0},
3822 {"sleb128", s_riscv_leb128
, 1},
3823 {"insn", s_riscv_insn
, 0},
3824 {"attribute", s_riscv_attribute
, 0},
3830 riscv_pop_insert (void)
3832 extern void pop_insert (const pseudo_typeS
*);
3834 pop_insert (riscv_pseudo_table
);