1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
88 static struct riscv_set_options riscv_opts
=
94 DEFAULT_RISCV_ATTR
, /* arch_attr */
98 riscv_set_rvc (bfd_boolean rvc_value
)
101 elf_flags
|= EF_RISCV_RVC
;
103 riscv_opts
.rvc
= rvc_value
;
107 riscv_set_rve (bfd_boolean rve_value
)
109 riscv_opts
.rve
= rve_value
;
112 static riscv_subset_list_t riscv_subsets
;
115 riscv_subset_supports (const char *feature
)
117 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
120 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
124 riscv_multi_subset_supports (const char *features
[])
127 bfd_boolean supported
= TRUE
;
129 for (;features
[i
]; ++i
)
130 supported
= supported
&& riscv_subset_supports (features
[i
]);
135 /* Set which ISA and extensions are available. */
138 riscv_set_arch (const char *s
)
140 riscv_parse_subset_t rps
;
141 rps
.subset_list
= &riscv_subsets
;
142 rps
.error_handler
= as_fatal
;
145 riscv_release_subset_list (&riscv_subsets
);
146 riscv_parse_subset (&rps
, s
);
149 /* Handle of the OPCODE hash table. */
150 static struct hash_control
*op_hash
= NULL
;
152 /* Handle of the type of .insn hash table. */
153 static struct hash_control
*insn_type_hash
= NULL
;
155 /* This array holds the chars that always start a comment. If the
156 pre-processor is disabled, these aren't very useful */
157 const char comment_chars
[] = "#";
159 /* This array holds the chars that only start a comment at the beginning of
160 a line. If the line seems to have the form '# 123 filename'
161 .line and .file directives will appear in the pre-processed output */
162 /* Note that input_file.c hand checks for '#' at the beginning of the
163 first line of the input file. This is because the compiler outputs
164 #NO_APP at the beginning of its output. */
165 /* Also note that C style comments are always supported. */
166 const char line_comment_chars
[] = "#";
168 /* This array holds machine specific line separator characters. */
169 const char line_separator_chars
[] = ";";
171 /* Chars that can be used to separate mant from exp in floating point nums */
172 const char EXP_CHARS
[] = "eE";
174 /* Chars that mean this number is a floating point constant */
177 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
179 /* Indicate we are already assemble any instructions or not. */
180 static bfd_boolean start_assemble
= FALSE
;
182 /* Indicate arch attribute is explictly set. */
183 static bfd_boolean explicit_arch_attr
= FALSE
;
185 /* Macros for encoding relaxation state for RVC branches and far jumps. */
186 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
189 | ((uncond) ? 1 : 0) \
192 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
193 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
194 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
195 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
197 /* Is the given value a sign-extended 32-bit value? */
198 #define IS_SEXT_32BIT_NUM(x) \
199 (((x) &~ (offsetT) 0x7fffffff) == 0 \
200 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
203 #define IS_ZEXT_32BIT_NUM(x) \
204 (((x) &~ (offsetT) 0xffffffff) == 0 \
205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
207 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
208 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
209 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
210 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
212 /* Determine if an instruction matches an opcode. */
213 #define OPCODE_MATCHES(OPCODE, OP) \
214 (((OPCODE) & MASK_##OP) == MATCH_##OP)
216 static char *expr_end
;
218 /* The default target format to use. */
221 riscv_target_format (void)
223 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
226 /* Return the length of instruction INSN. */
228 static inline unsigned int
229 insn_length (const struct riscv_cl_insn
*insn
)
231 return riscv_insn_length (insn
->insn_opcode
);
234 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
237 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
240 insn
->insn_opcode
= mo
->match
;
246 /* Install INSN at the location specified by its "frag" and "where" fields. */
249 install_insn (const struct riscv_cl_insn
*insn
)
251 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
252 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
255 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
256 and install the opcode in the new location. */
259 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
263 if (insn
->fixp
!= NULL
)
265 insn
->fixp
->fx_frag
= frag
;
266 insn
->fixp
->fx_where
= where
;
271 /* Add INSN to the end of the output. */
274 add_fixed_insn (struct riscv_cl_insn
*insn
)
276 char *f
= frag_more (insn_length (insn
));
277 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
281 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
282 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
284 frag_grow (max_chars
);
285 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
286 frag_var (rs_machine_dependent
, max_chars
, var
,
287 subtype
, symbol
, offset
, NULL
);
290 /* Compute the length of a branch sequence, and adjust the stored length
291 accordingly. If FRAGP is NULL, the worst-case length is returned. */
294 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
296 int jump
, rvc
, length
= 8;
301 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
302 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
303 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
305 /* Assume jumps are in range; the linker will catch any that aren't. */
306 length
= jump
? 4 : 8;
308 if (fragp
->fr_symbol
!= NULL
309 && S_IS_DEFINED (fragp
->fr_symbol
)
310 && !S_IS_WEAK (fragp
->fr_symbol
)
311 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
313 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
314 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
315 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
317 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
319 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
321 else if (!jump
&& rvc
)
326 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
331 /* Information about an opcode name, mnemonics and its value. */
338 /* List for all supported opcode name. */
339 static const struct opcode_name_t opcode_name_list
[] =
384 /* Hash table for lookup opcode name. */
385 static struct hash_control
*opcode_names_hash
= NULL
;
387 /* Initialization for hash table of opcode name. */
389 init_opcode_names_hash (void)
392 const struct opcode_name_t
*opcode
;
394 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
396 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
399 as_fatal (_("internal error: can't hash `%s': %s"),
400 opcode
->name
, retval
);
404 /* Find `s` is a valid opcode name or not,
405 return the opcode name info if found. */
406 static const struct opcode_name_t
*
407 opcode_name_lookup (char **s
)
411 struct opcode_name_t
*o
;
413 /* Find end of name. */
415 if (is_name_beginner (*e
))
417 while (is_part_of_name (*e
))
420 /* Terminate name. */
424 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
426 /* Advance to next token if one was recognized. */
450 static struct hash_control
*reg_names_hash
= NULL
;
452 #define ENCODE_REG_HASH(cls, n) \
453 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
454 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
455 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
458 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
460 void *hash
= ENCODE_REG_HASH (class, n
);
461 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
464 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
468 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
472 for (i
= 0; i
< n
; i
++)
473 hash_reg_name (class, names
[i
], i
);
477 reg_lookup_internal (const char *s
, enum reg_class
class)
479 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
481 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
484 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
487 return DECODE_REG_NUM (r
);
491 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
497 /* Find end of name. */
499 if (is_name_beginner (*e
))
501 while (is_part_of_name (*e
))
504 /* Terminate name. */
508 /* Look for the register. Advance to next token if one was recognized. */
509 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
519 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
521 const char *p
= strchr (*s
, ',');
522 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
527 for (i
= 0; i
< size
; i
++)
528 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
538 /* For consistency checking, verify that all bits are specified either
539 by the match/mask part of the instruction definition, or by the
542 `length` could be 0, 4 or 8, 0 for auto detection. */
544 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
546 const char *p
= opc
->args
;
548 insn_t used_bits
= opc
->mask
;
550 insn_t required_bits
;
553 insn_width
= 8 * riscv_insn_length (opc
->match
);
555 insn_width
= 8 * length
;
557 required_bits
= ~0ULL >> (64 - insn_width
);
559 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
561 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
562 opc
->name
, opc
->args
);
566 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
573 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
574 case 'c': break; /* RS1, constrained to equal sp */
575 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
576 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
577 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
578 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
579 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
580 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
581 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
582 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
583 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
584 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
585 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
586 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
587 case 'w': break; /* RS1S, constrained to equal RD */
588 case 'x': break; /* RS2S, constrained to equal RD */
589 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
590 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
591 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
592 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
593 case 'U': break; /* RS1, constrained to equal RD */
594 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
595 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
596 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
597 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
598 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
599 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
600 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
601 case 'F': /* funct */
604 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
605 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
606 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
607 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
609 as_bad (_("internal: bad RISC-V opcode"
610 " (unknown operand type `CF%c'): %s %s"),
611 c
, opc
->name
, opc
->args
);
616 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
617 c
, opc
->name
, opc
->args
);
624 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
625 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
627 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
628 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
629 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
631 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
632 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
633 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
634 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
635 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
636 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
637 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
638 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
639 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
640 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
641 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
643 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
644 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
645 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
646 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
647 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
653 case 'F': /* funct */
656 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
657 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
658 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
660 as_bad (_("internal: bad RISC-V opcode"
661 " (unknown operand type `F%c'): %s %s"),
662 c
, opc
->name
, opc
->args
);
666 case 'O': /* opcode */
669 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
670 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
672 as_bad (_("internal: bad RISC-V opcode"
673 " (unknown operand type `F%c'): %s %s"),
674 c
, opc
->name
, opc
->args
);
679 as_bad (_("internal: bad RISC-V opcode "
680 "(unknown operand type `%c'): %s %s"),
681 c
, opc
->name
, opc
->args
);
685 if (used_bits
!= required_bits
)
687 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
688 ~(unsigned long)(used_bits
& required_bits
),
689 opc
->name
, opc
->args
);
695 struct percent_op_match
698 bfd_reloc_code_real_type reloc
;
701 /* Common hash table initialization function for
702 instruction and .insn directive. */
703 static struct hash_control
*
704 init_opcode_hash (const struct riscv_opcode
*opcodes
,
705 bfd_boolean insn_directive_p
)
709 struct hash_control
*hash
= hash_new ();
710 while (opcodes
[i
].name
)
712 const char *name
= opcodes
[i
].name
;
713 const char *hash_error
=
714 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
718 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
719 opcodes
[i
].name
, hash_error
);
720 /* Probably a memory allocation problem? Give up now. */
721 as_fatal (_("Broken assembler. No assembly attempted."));
726 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
728 if (insn_directive_p
)
729 length
= ((name
[0] == 'c') ? 2 : 4);
731 length
= 0; /* Let assembler determine the length. */
732 if (!validate_riscv_insn (&opcodes
[i
], length
))
733 as_fatal (_("Broken assembler. No assembly attempted."));
736 gas_assert (!insn_directive_p
);
739 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
745 /* This function is called once, at assembler startup time. It should set up
746 all the tables, etc. that the MD part of the assembler will need. */
751 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
753 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
754 as_warn (_("Could not set architecture and machine"));
756 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
757 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
759 reg_names_hash
= hash_new ();
760 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
761 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
762 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
763 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
765 /* Add "fp" as an alias for "s0". */
766 hash_reg_name (RCLASS_GPR
, "fp", 8);
768 opcode_names_hash
= hash_new ();
769 init_opcode_names_hash ();
771 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
772 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
773 #include "opcode/riscv-opc.h"
776 /* Set the default alignment for the text section. */
777 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
781 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
788 case BFD_RELOC_RISCV_HI20
:
789 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
791 case BFD_RELOC_RISCV_LO12_S
:
792 return ENCODE_STYPE_IMM (value
);
794 case BFD_RELOC_RISCV_LO12_I
:
795 return ENCODE_ITYPE_IMM (value
);
802 /* Output an instruction. IP is the instruction information.
803 ADDRESS_EXPR is an operand of the instruction to be used with
807 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
808 bfd_reloc_code_real_type reloc_type
)
810 dwarf2_emit_insn (0);
812 if (reloc_type
!= BFD_RELOC_UNUSED
)
814 reloc_howto_type
*howto
;
816 gas_assert (address_expr
);
817 if (reloc_type
== BFD_RELOC_12_PCREL
818 || reloc_type
== BFD_RELOC_RISCV_JMP
)
820 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
821 int best_case
= riscv_insn_length (ip
->insn_opcode
);
822 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
823 add_relaxed_insn (ip
, worst_case
, best_case
,
824 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
825 address_expr
->X_add_symbol
,
826 address_expr
->X_add_number
);
831 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
833 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
835 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
836 bfd_get_reloc_size (howto
),
837 address_expr
, FALSE
, reloc_type
);
839 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
846 /* We need to start a new frag after any instruction that can be
847 optimized away or compressed by the linker during relaxation, to prevent
848 the assembler from computing static offsets across such an instruction.
849 This is necessary to get correct EH info. */
850 if (reloc_type
== BFD_RELOC_RISCV_CALL
851 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
852 || reloc_type
== BFD_RELOC_RISCV_HI20
853 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
854 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
855 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
857 frag_wane (frag_now
);
862 /* Build an instruction created by a macro expansion. This is passed
863 a pointer to the count of instructions created so far, an
864 expression, the name of the instruction to build, an operand format
865 string, and corresponding arguments. */
868 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
870 const struct riscv_opcode
*mo
;
871 struct riscv_cl_insn insn
;
872 bfd_reloc_code_real_type r
;
875 va_start (args
, fmt
);
877 r
= BFD_RELOC_UNUSED
;
878 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
881 /* Find a non-RVC variant of the instruction. append_insn will compress
883 while (riscv_insn_length (mo
->match
) < 4)
885 gas_assert (strcmp (name
, mo
->name
) == 0);
887 create_insn (&insn
, mo
);
893 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
897 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
901 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
905 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
911 gas_assert (ep
!= NULL
);
912 r
= va_arg (args
, int);
920 as_fatal (_("internal error: invalid macro"));
925 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
927 append_insn (&insn
, ep
, r
);
930 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
933 normalize_constant_expr (expressionS
*ex
)
937 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
938 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
939 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
943 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
944 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
947 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
948 bfd_boolean maybe_csr
)
950 if (ex
->X_op
== O_big
)
951 as_bad (_("unsupported large constant"));
952 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
953 as_bad (_("unknown CSR `%s'"),
954 S_GET_NAME (ex
->X_add_symbol
));
955 else if (ex
->X_op
!= O_constant
)
956 as_bad (_("Instruction %s requires absolute expression"),
958 normalize_constant_expr (ex
);
962 make_internal_label (void)
964 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
965 (valueT
) frag_now_fix (), frag_now
);
968 /* Load an entry from the GOT. */
970 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
971 const char *lo_insn
, const char *lo_pattern
,
972 bfd_reloc_code_real_type hi_reloc
,
973 bfd_reloc_code_real_type lo_reloc
)
977 ep2
.X_add_symbol
= make_internal_label ();
978 ep2
.X_add_number
= 0;
980 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
981 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
985 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
986 bfd_reloc_code_real_type hi_reloc
,
987 bfd_reloc_code_real_type lo_reloc
)
989 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
993 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
994 bfd_reloc_code_real_type hi_reloc
,
995 bfd_reloc_code_real_type lo_reloc
)
997 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1000 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1002 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1003 bfd_reloc_code_real_type reloc
)
1005 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1006 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1009 /* Load an integer constant into a register. */
1012 load_const (int reg
, expressionS
*ep
)
1014 int shift
= RISCV_IMM_BITS
;
1015 expressionS upper
= *ep
, lower
= *ep
;
1016 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1017 upper
.X_add_number
-= lower
.X_add_number
;
1019 if (ep
->X_op
!= O_constant
)
1021 as_bad (_("unsupported large constant"));
1025 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1027 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1028 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1031 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1032 load_const (reg
, &upper
);
1034 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1035 if (lower
.X_add_number
!= 0)
1036 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1040 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1043 if (upper
.X_add_number
!= 0)
1045 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1049 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1050 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1051 BFD_RELOC_RISCV_LO12_I
);
1055 /* Expand RISC-V assembly macros into one or more instructions. */
1057 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1058 bfd_reloc_code_real_type
*imm_reloc
)
1060 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1061 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1062 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1063 int mask
= ip
->insn_mo
->mask
;
1068 load_const (rd
, imm_expr
);
1073 /* Load the address of a symbol into a register. */
1074 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1075 as_bad (_("offset too large"));
1077 if (imm_expr
->X_op
== O_constant
)
1078 load_const (rd
, imm_expr
);
1079 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1080 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1081 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1082 else /* Local PIC symbol, or any non-PIC symbol */
1083 pcrel_load (rd
, rd
, imm_expr
, "addi",
1084 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1088 pcrel_load (rd
, rd
, imm_expr
, "addi",
1089 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1093 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1094 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1098 pcrel_load (rd
, rd
, imm_expr
, "lb",
1099 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1103 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1104 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1108 pcrel_load (rd
, rd
, imm_expr
, "lh",
1109 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1113 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1114 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1118 pcrel_load (rd
, rd
, imm_expr
, "lw",
1119 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1123 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1124 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1128 pcrel_load (rd
, rd
, imm_expr
, "ld",
1129 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1133 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1134 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1138 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1139 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1143 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1144 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1148 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1149 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1153 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1154 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1158 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1159 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1163 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1164 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1168 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1169 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1173 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1177 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1182 static const struct percent_op_match percent_op_utype
[] =
1184 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1185 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1186 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1187 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1188 {"%hi", BFD_RELOC_RISCV_HI20
},
1192 static const struct percent_op_match percent_op_itype
[] =
1194 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1195 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1196 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1200 static const struct percent_op_match percent_op_stype
[] =
1202 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1203 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1204 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1208 static const struct percent_op_match percent_op_rtype
[] =
1210 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1214 static const struct percent_op_match percent_op_null
[] =
1219 /* Return true if *STR points to a relocation operator. When returning true,
1220 move *STR over the operator and store its relocation code in *RELOC.
1221 Leave both *STR and *RELOC alone when returning false. */
1224 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1225 const struct percent_op_match
*percent_op
)
1227 for ( ; percent_op
->str
; percent_op
++)
1228 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1230 int len
= strlen (percent_op
->str
);
1232 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1235 *str
+= strlen (percent_op
->str
);
1236 *reloc
= percent_op
->reloc
;
1238 /* Check whether the output BFD supports this relocation.
1239 If not, issue an error and fall back on something safe. */
1240 if (*reloc
!= BFD_RELOC_UNUSED
1241 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1243 as_bad ("relocation %s isn't supported by the current ABI",
1245 *reloc
= BFD_RELOC_UNUSED
;
1253 my_getExpression (expressionS
*ep
, char *str
)
1257 save_in
= input_line_pointer
;
1258 input_line_pointer
= str
;
1260 expr_end
= input_line_pointer
;
1261 input_line_pointer
= save_in
;
1264 /* Parse string STR as a 16-bit relocatable operand. Store the
1265 expression in *EP and the relocation, if any, in RELOC.
1266 Return the number of relocation operators used (0 or 1).
1268 On exit, EXPR_END points to the first character after the expression. */
1271 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1272 char *str
, const struct percent_op_match
*percent_op
)
1275 unsigned crux_depth
, str_depth
, regno
;
1278 /* First, check for integer registers. No callers can accept a reg, but
1279 we need to avoid accidentally creating a useless undefined symbol below,
1280 if this is an instruction pattern that can't match. A glibc build fails
1281 if this is removed. */
1282 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1284 ep
->X_op
= O_register
;
1285 ep
->X_add_number
= regno
;
1290 /* Search for the start of the main expression.
1291 End the loop with CRUX pointing to the start
1292 of the main expression and with CRUX_DEPTH containing the number
1293 of open brackets at that point. */
1300 crux_depth
= str_depth
;
1302 /* Skip over whitespace and brackets, keeping count of the number
1304 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1310 && parse_relocation (&str
, reloc
, percent_op
));
1312 my_getExpression (ep
, crux
);
1315 /* Match every open bracket. */
1316 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1321 as_bad ("unclosed '('");
1328 /* Parse opcode name, could be an mnemonics or number. */
1330 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1331 char *str
, const struct percent_op_match
*percent_op
)
1333 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1337 ep
->X_op
= O_constant
;
1338 ep
->X_add_number
= o
->val
;
1342 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1345 /* Detect and handle implicitly zero load-store offsets. For example,
1346 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1347 an implicit offset was detected. */
1350 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1352 /* Check whether there is only a single bracketed expression left.
1353 If so, it must be the base register and the constant must be zero. */
1354 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1356 ep
->X_op
= O_constant
;
1357 ep
->X_add_number
= 0;
1364 /* This routine assembles an instruction into its binary format. As a
1365 side effect, it sets the global variable imm_reloc to the type of
1366 relocation to do if one of the operands is an address expression. */
1369 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1370 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1375 struct riscv_opcode
*insn
;
1380 const struct percent_op_match
*p
;
1381 const char *error
= "unrecognized opcode";
1383 /* Parse the name of the instruction. Terminate the string if whitespace
1384 is found so that hash_find only sees the name part of the string. */
1385 for (s
= str
; *s
!= '\0'; ++s
)
1393 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1396 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1398 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1401 if (!riscv_multi_subset_supports (insn
->subset
))
1404 create_insn (ip
, insn
);
1407 imm_expr
->X_op
= O_absent
;
1408 *imm_reloc
= BFD_RELOC_UNUSED
;
1409 p
= percent_op_itype
;
1411 for (args
= insn
->args
;; ++args
)
1413 s
+= strspn (s
, " \t");
1416 case '\0': /* End of args. */
1417 if (insn
->pinfo
!= INSN_MACRO
)
1419 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1422 /* For .insn, insn->match and insn->mask are 0. */
1423 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1431 /* Successful assembly. */
1438 case 's': /* RS1 x8-x15 */
1439 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1440 || !(regno
>= 8 && regno
<= 15))
1442 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1444 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1445 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1446 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1449 case 't': /* RS2 x8-x15 */
1450 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1451 || !(regno
>= 8 && regno
<= 15))
1453 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1455 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1456 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1457 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1460 case 'U': /* RS1, constrained to equal RD. */
1461 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1462 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1466 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1468 INSERT_OPERAND (CRS2
, *ip
, regno
);
1470 case 'c': /* RS1, constrained to equal sp. */
1471 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1476 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1477 || imm_expr
->X_op
!= O_constant
1478 || imm_expr
->X_add_number
<= 0
1479 || imm_expr
->X_add_number
>= 64)
1481 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1484 imm_expr
->X_op
= O_absent
;
1487 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1488 || imm_expr
->X_op
!= O_constant
1489 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1490 || imm_expr
->X_add_number
<= 0
1491 || imm_expr
->X_add_number
>= 32)
1493 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1496 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1497 || imm_expr
->X_op
!= O_constant
1498 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1499 || imm_expr
->X_add_number
< 0
1500 || imm_expr
->X_add_number
>= 256)
1502 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1505 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1506 || imm_expr
->X_op
!= O_constant
1507 || imm_expr
->X_add_number
== 0
1508 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1510 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1513 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1514 || imm_expr
->X_op
!= O_constant
1515 || imm_expr
->X_add_number
== 0
1516 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1518 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1521 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1523 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1524 || imm_expr
->X_op
!= O_constant
1525 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1527 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1530 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1532 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1533 || imm_expr
->X_op
!= O_constant
1534 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1536 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1539 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1541 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1542 || imm_expr
->X_op
!= O_constant
1543 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1546 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1549 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1551 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1552 || imm_expr
->X_op
!= O_constant
1553 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1556 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1559 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1560 || imm_expr
->X_op
!= O_constant
1561 /* C.addiw, c.li, and c.andi allow zero immediate.
1562 C.addi allows zero immediate as hint. Otherwise this
1564 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1566 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1569 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1570 || imm_expr
->X_op
!= O_constant
1571 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1572 || imm_expr
->X_add_number
== 0)
1575 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1578 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1579 || imm_expr
->X_op
!= O_constant
1580 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1581 || imm_expr
->X_add_number
== 0)
1584 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1587 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1589 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1590 || imm_expr
->X_op
!= O_constant
1591 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1594 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1597 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1599 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1600 || imm_expr
->X_op
!= O_constant
1601 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1604 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1607 p
= percent_op_utype
;
1608 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1611 if (imm_expr
->X_op
!= O_constant
1612 || imm_expr
->X_add_number
<= 0
1613 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1614 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1615 && (imm_expr
->X_add_number
<
1616 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1618 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1621 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1622 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1623 || ((int32_t)imm_expr
->X_add_number
1624 != imm_expr
->X_add_number
))
1626 imm_expr
->X_add_number
=
1627 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1633 case 'S': /* Floating-point RS1 x8-x15. */
1634 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1635 || !(regno
>= 8 && regno
<= 15))
1637 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1639 case 'D': /* Floating-point RS2 x8-x15. */
1640 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1641 || !(regno
>= 8 && regno
<= 15))
1643 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1645 case 'T': /* Floating-point RS2. */
1646 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1648 INSERT_OPERAND (CRS2
, *ip
, regno
);
1654 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1655 || imm_expr
->X_op
!= O_constant
1656 || imm_expr
->X_add_number
< 0
1657 || imm_expr
->X_add_number
>= 64)
1659 as_bad (_("bad value for funct6 field, "
1660 "value must be 0...64"));
1664 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1665 imm_expr
->X_op
= O_absent
;
1669 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1670 || imm_expr
->X_op
!= O_constant
1671 || imm_expr
->X_add_number
< 0
1672 || imm_expr
->X_add_number
>= 16)
1674 as_bad (_("bad value for funct4 field, "
1675 "value must be 0...15"));
1679 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1680 imm_expr
->X_op
= O_absent
;
1684 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1685 || imm_expr
->X_op
!= O_constant
1686 || imm_expr
->X_add_number
< 0
1687 || imm_expr
->X_add_number
>= 8)
1689 as_bad (_("bad value for funct3 field, "
1690 "value must be 0...7"));
1693 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1694 imm_expr
->X_op
= O_absent
;
1698 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1699 || imm_expr
->X_op
!= O_constant
1700 || imm_expr
->X_add_number
< 0
1701 || imm_expr
->X_add_number
>= 4)
1703 as_bad (_("bad value for funct2 field, "
1704 "value must be 0...3"));
1707 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1708 imm_expr
->X_op
= O_absent
;
1712 as_bad (_("bad compressed FUNCT field"
1713 " specifier 'CF%c'\n"),
1719 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1738 case '<': /* Shift amount, 0 - 31. */
1739 my_getExpression (imm_expr
, s
);
1740 check_absolute_expr (ip
, imm_expr
, FALSE
);
1741 if ((unsigned long) imm_expr
->X_add_number
> 31)
1742 as_bad (_("Improper shift amount (%lu)"),
1743 (unsigned long) imm_expr
->X_add_number
);
1744 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1745 imm_expr
->X_op
= O_absent
;
1749 case '>': /* Shift amount, 0 - (XLEN-1). */
1750 my_getExpression (imm_expr
, s
);
1751 check_absolute_expr (ip
, imm_expr
, FALSE
);
1752 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1753 as_bad (_("Improper shift amount (%lu)"),
1754 (unsigned long) imm_expr
->X_add_number
);
1755 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1756 imm_expr
->X_op
= O_absent
;
1760 case 'Z': /* CSRRxI immediate. */
1761 my_getExpression (imm_expr
, s
);
1762 check_absolute_expr (ip
, imm_expr
, FALSE
);
1763 if ((unsigned long) imm_expr
->X_add_number
> 31)
1764 as_bad (_("Improper CSRxI immediate (%lu)"),
1765 (unsigned long) imm_expr
->X_add_number
);
1766 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1767 imm_expr
->X_op
= O_absent
;
1771 case 'E': /* Control register. */
1772 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1773 INSERT_OPERAND (CSR
, *ip
, regno
);
1776 my_getExpression (imm_expr
, s
);
1777 check_absolute_expr (ip
, imm_expr
, TRUE
);
1778 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1779 as_bad (_("Improper CSR address (%lu)"),
1780 (unsigned long) imm_expr
->X_add_number
);
1781 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1782 imm_expr
->X_op
= O_absent
;
1787 case 'm': /* Rounding mode. */
1788 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1790 INSERT_OPERAND (RM
, *ip
, regno
);
1796 case 'Q': /* Fence predecessor/successor. */
1797 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1801 INSERT_OPERAND (PRED
, *ip
, regno
);
1803 INSERT_OPERAND (SUCC
, *ip
, regno
);
1808 case 'd': /* Destination register. */
1809 case 's': /* Source register. */
1810 case 't': /* Target register. */
1811 case 'r': /* rs3. */
1812 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1818 /* Now that we have assembled one operand, we use the args
1819 string to figure out where it goes in the instruction. */
1823 INSERT_OPERAND (RS1
, *ip
, regno
);
1826 INSERT_OPERAND (RD
, *ip
, regno
);
1829 INSERT_OPERAND (RS2
, *ip
, regno
);
1832 INSERT_OPERAND (RS3
, *ip
, regno
);
1839 case 'D': /* Floating point rd. */
1840 case 'S': /* Floating point rs1. */
1841 case 'T': /* Floating point rs2. */
1842 case 'U': /* Floating point rs1 and rs2. */
1843 case 'R': /* Floating point rs3. */
1844 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1852 INSERT_OPERAND (RD
, *ip
, regno
);
1855 INSERT_OPERAND (RS1
, *ip
, regno
);
1858 INSERT_OPERAND (RS1
, *ip
, regno
);
1861 INSERT_OPERAND (RS2
, *ip
, regno
);
1864 INSERT_OPERAND (RS3
, *ip
, regno
);
1873 my_getExpression (imm_expr
, s
);
1874 if (imm_expr
->X_op
!= O_big
1875 && imm_expr
->X_op
!= O_constant
)
1877 normalize_constant_expr (imm_expr
);
1882 my_getExpression (imm_expr
, s
);
1883 normalize_constant_expr (imm_expr
);
1884 /* The 'A' format specifier must be a symbol. */
1885 if (imm_expr
->X_op
!= O_symbol
)
1887 *imm_reloc
= BFD_RELOC_32
;
1892 my_getExpression (imm_expr
, s
);
1893 normalize_constant_expr (imm_expr
);
1894 /* The 'B' format specifier must be a symbol or a constant. */
1895 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1897 if (imm_expr
->X_op
== O_symbol
)
1898 *imm_reloc
= BFD_RELOC_32
;
1902 case 'j': /* Sign-extended immediate. */
1903 p
= percent_op_itype
;
1904 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1906 case 'q': /* Store displacement. */
1907 p
= percent_op_stype
;
1908 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1910 case 'o': /* Load displacement. */
1911 p
= percent_op_itype
;
1912 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1914 case '1': /* 4-operand add, must be %tprel_add. */
1915 p
= percent_op_rtype
;
1917 case '0': /* AMO "displacement," which must be zero. */
1918 p
= percent_op_null
;
1920 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1923 /* If this value won't fit into a 16 bit offset, then go
1924 find a macro that will generate the 32 bit offset
1926 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1928 normalize_constant_expr (imm_expr
);
1929 if (imm_expr
->X_op
!= O_constant
1930 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1932 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1933 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1940 case 'p': /* PC-relative offset. */
1942 *imm_reloc
= BFD_RELOC_12_PCREL
;
1943 my_getExpression (imm_expr
, s
);
1947 case 'u': /* Upper 20 bits. */
1948 p
= percent_op_utype
;
1949 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1950 && imm_expr
->X_op
== O_constant
)
1952 if (imm_expr
->X_add_number
< 0
1953 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1954 as_bad (_("lui expression not in range 0..1048575"));
1956 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1957 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1959 /* The 'u' format specifier must be a symbol or a constant. */
1960 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1965 case 'a': /* 20-bit PC-relative offset. */
1967 my_getExpression (imm_expr
, s
);
1969 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1973 my_getExpression (imm_expr
, s
);
1975 if (strcmp (s
, "@plt") == 0)
1977 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1981 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1987 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
1988 || imm_expr
->X_op
!= O_constant
1989 || imm_expr
->X_add_number
< 0
1990 || imm_expr
->X_add_number
>= 128
1991 || (imm_expr
->X_add_number
& 0x3) != 3)
1993 as_bad (_("bad value for opcode field, "
1994 "value must be 0...127 and "
1995 "lower 2 bits must be 0x3"));
1999 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2000 imm_expr
->X_op
= O_absent
;
2004 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2005 || imm_expr
->X_op
!= O_constant
2006 || imm_expr
->X_add_number
< 0
2007 || imm_expr
->X_add_number
>= 3)
2009 as_bad (_("bad value for opcode field, "
2010 "value must be 0...2"));
2014 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2015 imm_expr
->X_op
= O_absent
;
2019 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2027 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2028 || imm_expr
->X_op
!= O_constant
2029 || imm_expr
->X_add_number
< 0
2030 || imm_expr
->X_add_number
>= 128)
2032 as_bad (_("bad value for funct7 field, "
2033 "value must be 0...127"));
2037 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2038 imm_expr
->X_op
= O_absent
;
2042 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2043 || imm_expr
->X_op
!= O_constant
2044 || imm_expr
->X_add_number
< 0
2045 || imm_expr
->X_add_number
>= 8)
2047 as_bad (_("bad value for funct3 field, "
2048 "value must be 0...7"));
2052 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2053 imm_expr
->X_op
= O_absent
;
2057 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2058 || imm_expr
->X_op
!= O_constant
2059 || imm_expr
->X_add_number
< 0
2060 || imm_expr
->X_add_number
>= 4)
2062 as_bad (_("bad value for funct2 field, "
2063 "value must be 0...3"));
2067 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2068 imm_expr
->X_op
= O_absent
;
2073 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2078 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2079 || imm_expr
->X_op
!= O_constant
2080 || imm_expr
->X_add_number
!= 0)
2083 imm_expr
->X_op
= O_absent
;
2087 as_fatal (_("internal error: bad argument type %c"), *args
);
2092 error
= _("illegal operands");
2096 /* Restore the character we might have clobbered above. */
2098 *(argsStart
- 1) = save_c
;
2104 md_assemble (char *str
)
2106 struct riscv_cl_insn insn
;
2107 expressionS imm_expr
;
2108 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2110 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2112 start_assemble
= TRUE
;
2116 as_bad ("%s `%s'", error
, str
);
2120 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2121 macro (&insn
, &imm_expr
, &imm_reloc
);
2123 append_insn (&insn
, &imm_expr
, imm_reloc
);
2127 md_atof (int type
, char *litP
, int *sizeP
)
2129 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2133 md_number_to_chars (char *buf
, valueT val
, int n
)
2135 number_to_chars_littleendian (buf
, val
, n
);
2138 const char *md_shortopts
= "O::g::G:";
2142 OPTION_MARCH
= OPTION_MD_BASE
,
2149 OPTION_NO_ARCH_ATTR
,
2153 struct option md_longopts
[] =
2155 {"march", required_argument
, NULL
, OPTION_MARCH
},
2156 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2157 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2158 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2159 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2160 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2161 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2162 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2163 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2165 {NULL
, no_argument
, NULL
, 0}
2167 size_t md_longopts_size
= sizeof (md_longopts
);
2170 FLOAT_ABI_DEFAULT
= -1,
2176 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2179 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2181 abi_xlen
= new_xlen
;
2182 float_abi
= new_float_abi
;
2187 md_parse_option (int c
, const char *arg
)
2192 riscv_set_arch (arg
);
2196 riscv_opts
.pic
= FALSE
;
2200 riscv_opts
.pic
= TRUE
;
2204 if (strcmp (arg
, "ilp32") == 0)
2205 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2206 else if (strcmp (arg
, "ilp32e") == 0)
2207 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2208 else if (strcmp (arg
, "ilp32f") == 0)
2209 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2210 else if (strcmp (arg
, "ilp32d") == 0)
2211 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2212 else if (strcmp (arg
, "ilp32q") == 0)
2213 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2214 else if (strcmp (arg
, "lp64") == 0)
2215 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2216 else if (strcmp (arg
, "lp64f") == 0)
2217 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2218 else if (strcmp (arg
, "lp64d") == 0)
2219 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2220 else if (strcmp (arg
, "lp64q") == 0)
2221 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2227 riscv_opts
.relax
= TRUE
;
2230 case OPTION_NO_RELAX
:
2231 riscv_opts
.relax
= FALSE
;
2234 case OPTION_ARCH_ATTR
:
2235 riscv_opts
.arch_attr
= TRUE
;
2238 case OPTION_NO_ARCH_ATTR
:
2239 riscv_opts
.arch_attr
= FALSE
;
2250 riscv_after_parse_args (void)
2254 if (strcmp (default_arch
, "riscv32") == 0)
2256 else if (strcmp (default_arch
, "riscv64") == 0)
2259 as_bad ("unknown default architecture `%s'", default_arch
);
2262 if (riscv_subsets
.head
== NULL
)
2263 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2265 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2266 riscv_set_rvc (FALSE
);
2267 if (riscv_subset_supports ("c"))
2268 riscv_set_rvc (TRUE
);
2270 /* Enable RVE if specified by the -march option. */
2271 riscv_set_rve (FALSE
);
2272 if (riscv_subset_supports ("e"))
2273 riscv_set_rve (TRUE
);
2275 /* Infer ABI from ISA if not specified on command line. */
2278 else if (abi_xlen
> xlen
)
2279 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2280 else if (abi_xlen
< xlen
)
2281 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2283 if (float_abi
== FLOAT_ABI_DEFAULT
)
2285 riscv_subset_t
*subset
;
2287 /* Assume soft-float unless D extension is present. */
2288 float_abi
= FLOAT_ABI_SOFT
;
2290 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2292 if (strcasecmp (subset
->name
, "D") == 0)
2293 float_abi
= FLOAT_ABI_DOUBLE
;
2294 if (strcasecmp (subset
->name
, "Q") == 0)
2295 float_abi
= FLOAT_ABI_QUAD
;
2300 elf_flags
|= EF_RISCV_RVE
;
2302 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2303 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2307 md_pcrel_from (fixS
*fixP
)
2309 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2312 /* Apply a fixup to the object file. */
2315 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2317 unsigned int subtype
;
2318 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2319 bfd_boolean relaxable
= FALSE
;
2323 /* Remember value for tc_gen_reloc. */
2324 fixP
->fx_addnumber
= *valP
;
2326 switch (fixP
->fx_r_type
)
2328 case BFD_RELOC_RISCV_HI20
:
2329 case BFD_RELOC_RISCV_LO12_I
:
2330 case BFD_RELOC_RISCV_LO12_S
:
2331 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2332 | bfd_getl32 (buf
), buf
);
2333 if (fixP
->fx_addsy
== NULL
)
2334 fixP
->fx_done
= TRUE
;
2338 case BFD_RELOC_RISCV_GOT_HI20
:
2339 case BFD_RELOC_RISCV_ADD8
:
2340 case BFD_RELOC_RISCV_ADD16
:
2341 case BFD_RELOC_RISCV_ADD32
:
2342 case BFD_RELOC_RISCV_ADD64
:
2343 case BFD_RELOC_RISCV_SUB6
:
2344 case BFD_RELOC_RISCV_SUB8
:
2345 case BFD_RELOC_RISCV_SUB16
:
2346 case BFD_RELOC_RISCV_SUB32
:
2347 case BFD_RELOC_RISCV_SUB64
:
2348 case BFD_RELOC_RISCV_RELAX
:
2351 case BFD_RELOC_RISCV_TPREL_HI20
:
2352 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2353 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2354 case BFD_RELOC_RISCV_TPREL_ADD
:
2358 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2359 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2360 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2361 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2362 if (fixP
->fx_addsy
!= NULL
)
2363 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2366 _("TLS relocation against a constant"));
2370 /* Use pc-relative relocation for FDE initial location.
2371 The symbol address in .eh_frame may be adjusted in
2372 _bfd_elf_discard_section_eh_frame, and the content of
2373 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2374 Therefore, we cannot insert a relocation whose addend symbol is
2375 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2376 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2377 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2378 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2379 && S_GET_VALUE (fixP
->fx_subsy
)
2380 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2382 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2383 fixP
->fx_subsy
= NULL
;
2390 case BFD_RELOC_RISCV_CFA
:
2391 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2393 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2394 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2395 fixP
->fx_next
->fx_subsy
= NULL
;
2396 fixP
->fx_next
->fx_offset
= 0;
2397 fixP
->fx_subsy
= NULL
;
2399 switch (fixP
->fx_r_type
)
2402 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2403 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2407 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2408 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2412 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2413 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2417 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2418 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2421 case BFD_RELOC_RISCV_CFA
:
2422 /* Load the byte to get the subtype. */
2423 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2424 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2427 case DW_CFA_advance_loc1
:
2428 fixP
->fx_where
= loc
+ 1;
2429 fixP
->fx_next
->fx_where
= loc
+ 1;
2430 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2431 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2434 case DW_CFA_advance_loc2
:
2436 fixP
->fx_next
->fx_size
= 2;
2437 fixP
->fx_where
= loc
+ 1;
2438 fixP
->fx_next
->fx_where
= loc
+ 1;
2439 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2440 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2443 case DW_CFA_advance_loc4
:
2445 fixP
->fx_next
->fx_size
= 4;
2446 fixP
->fx_where
= loc
;
2447 fixP
->fx_next
->fx_where
= loc
;
2448 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2449 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2453 if (subtype
< 0x80 && (subtype
& 0x40))
2455 /* DW_CFA_advance_loc */
2456 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2457 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2458 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2459 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2462 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2468 /* This case is unreachable. */
2475 /* If we are deleting this reloc entry, we must fill in the
2476 value now. This can happen if we have a .word which is not
2477 resolved when it appears but is later defined. */
2478 if (fixP
->fx_addsy
== NULL
)
2480 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2481 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2486 case BFD_RELOC_RISCV_JMP
:
2489 /* Fill in a tentative value to improve objdump readability. */
2490 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2491 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2492 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2496 case BFD_RELOC_12_PCREL
:
2499 /* Fill in a tentative value to improve objdump readability. */
2500 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2501 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2502 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2506 case BFD_RELOC_RISCV_RVC_BRANCH
:
2509 /* Fill in a tentative value to improve objdump readability. */
2510 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2511 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2512 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2516 case BFD_RELOC_RISCV_RVC_JUMP
:
2519 /* Fill in a tentative value to improve objdump readability. */
2520 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2521 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2522 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2526 case BFD_RELOC_RISCV_CALL
:
2527 case BFD_RELOC_RISCV_CALL_PLT
:
2531 case BFD_RELOC_RISCV_PCREL_HI20
:
2532 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2533 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2534 relaxable
= riscv_opts
.relax
;
2537 case BFD_RELOC_RISCV_ALIGN
:
2541 /* We ignore generic BFD relocations we don't know about. */
2542 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2543 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2546 if (fixP
->fx_subsy
!= NULL
)
2547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2548 _("unsupported symbol subtraction"));
2550 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2551 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2553 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2554 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2555 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2559 /* Because the value of .cfi_remember_state may changed after relaxation,
2560 we insert a fix to relocate it again in link-time. */
2563 riscv_pre_output_hook (void)
2565 const frchainS
*frch
;
2568 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2569 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2573 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2575 if (frag
->fr_type
== rs_cfa
)
2578 expressionS
*symval
;
2580 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2581 exp
.X_op
= O_subtract
;
2582 exp
.X_add_symbol
= symval
->X_add_symbol
;
2583 exp
.X_add_number
= 0;
2584 exp
.X_op_symbol
= symval
->X_op_symbol
;
2586 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2587 BFD_RELOC_RISCV_CFA
);
2594 /* This structure is used to hold a stack of .option values. */
2596 struct riscv_option_stack
2598 struct riscv_option_stack
*next
;
2599 struct riscv_set_options options
;
2602 static struct riscv_option_stack
*riscv_opts_stack
;
2604 /* Handle the .option pseudo-op. */
2607 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2609 char *name
= input_line_pointer
, ch
;
2611 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2612 ++input_line_pointer
;
2613 ch
= *input_line_pointer
;
2614 *input_line_pointer
= '\0';
2616 if (strcmp (name
, "rvc") == 0)
2617 riscv_set_rvc (TRUE
);
2618 else if (strcmp (name
, "norvc") == 0)
2619 riscv_set_rvc (FALSE
);
2620 else if (strcmp (name
, "pic") == 0)
2621 riscv_opts
.pic
= TRUE
;
2622 else if (strcmp (name
, "nopic") == 0)
2623 riscv_opts
.pic
= FALSE
;
2624 else if (strcmp (name
, "relax") == 0)
2625 riscv_opts
.relax
= TRUE
;
2626 else if (strcmp (name
, "norelax") == 0)
2627 riscv_opts
.relax
= FALSE
;
2628 else if (strcmp (name
, "push") == 0)
2630 struct riscv_option_stack
*s
;
2632 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2633 s
->next
= riscv_opts_stack
;
2634 s
->options
= riscv_opts
;
2635 riscv_opts_stack
= s
;
2637 else if (strcmp (name
, "pop") == 0)
2639 struct riscv_option_stack
*s
;
2641 s
= riscv_opts_stack
;
2643 as_bad (_(".option pop with no .option push"));
2646 riscv_opts
= s
->options
;
2647 riscv_opts_stack
= s
->next
;
2653 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2655 *input_line_pointer
= ch
;
2656 demand_empty_rest_of_line ();
2659 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2660 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2661 use in DWARF debug information. */
2664 s_dtprel (int bytes
)
2671 if (ex
.X_op
!= O_symbol
)
2673 as_bad (_("Unsupported use of %s"), (bytes
== 8
2676 ignore_rest_of_line ();
2679 p
= frag_more (bytes
);
2680 md_number_to_chars (p
, 0, bytes
);
2681 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2683 ? BFD_RELOC_RISCV_TLS_DTPREL64
2684 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2686 demand_empty_rest_of_line ();
2689 /* Handle the .bss pseudo-op. */
2692 s_bss (int ignore ATTRIBUTE_UNUSED
)
2694 subseg_set (bss_section
, 0);
2695 demand_empty_rest_of_line ();
2699 riscv_make_nops (char *buf
, bfd_vma bytes
)
2703 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2704 means we are not within a valid instruction sequence. It is thus safe
2705 to use a zero byte, even though that is not a valid instruction. */
2709 /* Use at most one 2-byte NOP. */
2710 if ((bytes
- i
) % 4 == 2)
2712 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2716 /* Fill the remainder with 4-byte NOPs. */
2717 for ( ; i
< bytes
; i
+= 4)
2718 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2721 /* Called from md_do_align. Used to create an alignment frag in a
2722 code section by emitting a worst-case NOP sequence that the linker
2723 will later relax to the correct number of NOPs. We can't compute
2724 the correct alignment now because of other linker relaxations. */
2727 riscv_frag_align_code (int n
)
2729 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2730 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2731 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2735 /* If we are moving to a smaller alignment than the instruction size, then no
2736 alignment is required. */
2737 if (bytes
<= insn_alignment
)
2740 /* When not relaxing, riscv_handle_align handles code alignment. */
2741 if (!riscv_opts
.relax
)
2744 nops
= frag_more (worst_case_bytes
);
2746 ex
.X_op
= O_constant
;
2747 ex
.X_add_number
= worst_case_bytes
;
2749 riscv_make_nops (nops
, worst_case_bytes
);
2751 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2752 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2757 /* Implement HANDLE_ALIGN. */
2760 riscv_handle_align (fragS
*fragP
)
2762 switch (fragP
->fr_type
)
2765 /* When relaxing, riscv_frag_align_code handles code alignment. */
2766 if (!riscv_opts
.relax
)
2768 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2769 - fragP
->fr_address
- fragP
->fr_fix
);
2770 /* We have 4 byte uncompressed nops. */
2771 bfd_signed_vma size
= 4;
2772 bfd_signed_vma excess
= bytes
% size
;
2773 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2778 /* Insert zeros or compressed nops to get 4 byte alignment. */
2781 riscv_make_nops (p
, excess
);
2782 fragP
->fr_fix
+= excess
;
2786 /* Insert variable number of 4 byte uncompressed nops. */
2787 riscv_make_nops (p
, size
);
2788 fragP
->fr_var
= size
;
2798 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2800 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2803 /* Translate internal representation of relocation info to BFD target
2807 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2809 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2811 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2812 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2813 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2814 reloc
->addend
= fixp
->fx_addnumber
;
2816 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2817 if (reloc
->howto
== NULL
)
2819 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2820 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2822 /* We don't have R_RISCV_8/16, but for this special case,
2823 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2827 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2828 _("cannot represent %s relocation in object file"),
2829 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2837 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2839 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2841 offsetT old_var
= fragp
->fr_var
;
2842 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2843 return fragp
->fr_var
- old_var
;
2849 /* Expand far branches to multi-instruction sequences. */
2852 md_convert_frag_branch (fragS
*fragp
)
2860 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2862 exp
.X_op
= O_symbol
;
2863 exp
.X_add_symbol
= fragp
->fr_symbol
;
2864 exp
.X_add_number
= fragp
->fr_offset
;
2866 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2868 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2870 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2874 /* Expand the RVC branch into a RISC-V one. */
2875 insn
= bfd_getl16 (buf
);
2876 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2877 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2879 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2880 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2881 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2882 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2883 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2884 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2887 bfd_putl32 (insn
, buf
);
2891 /* Invert the branch condition. Branch over the jump. */
2892 insn
= bfd_getl16 (buf
);
2893 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2894 insn
|= ENCODE_RVC_B_IMM (6);
2895 bfd_putl16 (insn
, buf
);
2900 /* Just keep the RVC branch. */
2901 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2902 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2903 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2904 2, &exp
, FALSE
, reloc
);
2913 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2916 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2918 /* Invert the branch condition. Branch over the jump. */
2919 insn
= bfd_getl32 (buf
);
2920 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2921 insn
|= ENCODE_SBTYPE_IMM (8);
2922 md_number_to_chars ((char *) buf
, insn
, 4);
2926 /* Jump to the target. */
2927 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2928 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2929 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2934 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2935 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2936 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2937 4, &exp
, FALSE
, reloc
);
2946 fixp
->fx_file
= fragp
->fr_file
;
2947 fixp
->fx_line
= fragp
->fr_line
;
2949 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2950 + fragp
->fr_fix
+ fragp
->fr_var
);
2952 fragp
->fr_fix
+= fragp
->fr_var
;
2955 /* Relax a machine dependent frag. This returns the amount by which
2956 the current size of the frag should change. */
2959 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2962 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2963 md_convert_frag_branch (fragp
);
2967 md_show_usage (FILE *stream
)
2969 fprintf (stream
, _("\
2971 -fpic generate position-independent code\n\
2972 -fno-pic don't generate position-independent code (default)\n\
2973 -march=ISA set the RISC-V architecture\n\
2974 -mabi=ABI set the RISC-V ABI\n\
2975 -mrelax enable relax (default)\n\
2976 -mno-relax disable relax\n\
2977 -march-attr generate RISC-V arch attribute\n\
2978 -mno-arch-attr don't generate RISC-V arch attribute\n\
2982 /* Standard calling conventions leave the CFA at SP on entry. */
2984 riscv_cfi_frame_initial_instructions (void)
2986 cfi_add_CFA_def_cfa_register (X_SP
);
2990 tc_riscv_regname_to_dw2regnum (char *regname
)
2994 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2997 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3000 as_bad (_("unknown register `%s'"), regname
);
3005 riscv_elf_final_processing (void)
3007 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3010 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3011 since these directives break relaxation when used with symbol deltas. */
3014 s_riscv_leb128 (int sign
)
3017 char *save_in
= input_line_pointer
;
3020 if (exp
.X_op
!= O_constant
)
3021 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3022 demand_empty_rest_of_line ();
3024 input_line_pointer
= save_in
;
3025 return s_leb128 (sign
);
3028 /* Parse the .insn directive. */
3031 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3033 char *str
= input_line_pointer
;
3034 struct riscv_cl_insn insn
;
3035 expressionS imm_expr
;
3036 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3039 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3040 ++input_line_pointer
;
3042 save_c
= *input_line_pointer
;
3043 *input_line_pointer
= '\0';
3045 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3046 &imm_reloc
, insn_type_hash
);
3050 as_bad ("%s `%s'", error
, str
);
3054 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3055 append_insn (&insn
, &imm_expr
, imm_reloc
);
3058 *input_line_pointer
= save_c
;
3059 demand_empty_rest_of_line ();
3062 /* Update arch attributes. */
3065 riscv_write_out_arch_attr (void)
3067 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3069 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3071 xfree ((void *)arch_str
);
3074 /* Add the default contents for the .riscv.attributes section. */
3077 riscv_set_public_attributes (void)
3079 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3080 /* Re-write arch attribute to normalize the arch string. */
3081 riscv_write_out_arch_attr ();
3084 /* Called after all assembly has been done. */
3089 riscv_set_public_attributes ();
3092 /* Given a symbolic attribute NAME, return the proper integer value.
3093 Returns -1 if the attribute is not known. */
3096 riscv_convert_symbolic_attribute (const char *name
)
3105 /* When you modify this table you should
3106 also modify the list in doc/c-riscv.texi. */
3107 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3111 T(priv_spec_revision
),
3112 T(unaligned_access
),
3122 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3123 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3124 return attribute_table
[i
].tag
;
3129 /* Parse a .attribute directive. */
3132 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3134 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3136 if (tag
== Tag_RISCV_arch
)
3138 unsigned old_xlen
= xlen
;
3140 explicit_arch_attr
= TRUE
;
3141 obj_attribute
*attr
;
3142 attr
= elf_known_obj_attributes_proc (stdoutput
);
3143 if (!start_assemble
)
3144 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3146 as_fatal (_(".attribute arch must set before any instructions"));
3148 if (old_xlen
!= xlen
)
3150 /* We must re-init bfd again if xlen is changed. */
3151 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3152 bfd_find_target (riscv_target_format (), stdoutput
);
3154 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3155 as_warn (_("Could not set architecture and machine"));
3160 /* Pseudo-op table. */
3162 static const pseudo_typeS riscv_pseudo_table
[] =
3164 /* RISC-V-specific pseudo-ops. */
3165 {"option", s_riscv_option
, 0},
3169 {"dtprelword", s_dtprel
, 4},
3170 {"dtpreldword", s_dtprel
, 8},
3172 {"uleb128", s_riscv_leb128
, 0},
3173 {"sleb128", s_riscv_leb128
, 1},
3174 {"insn", s_riscv_insn
, 0},
3175 {"attribute", s_riscv_attribute
, 0},
3181 riscv_pop_insert (void)
3183 extern void pop_insert (const pseudo_typeS
*);
3185 pop_insert (riscv_pseudo_table
);