1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/cpu-riscv.h"
33 #include "bfd/elfxx-riscv.h"
34 #include "elf/riscv.h"
35 #include "opcode/riscv.h"
39 /* Information about an instruction, including its format, operands
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode
*insn_mo
;
46 /* The encoded instruction bits. */
49 /* The frag that contains the instruction. */
52 /* The offset into FRAG of the first instruction byte. */
55 /* The relocs associated with the instruction, if any. */
59 /* All RISC-V CSR belong to one of these classes. */
65 CSR_CLASS_I_32
, /* rv32 only */
66 CSR_CLASS_F
, /* f-ext only */
67 CSR_CLASS_DEBUG
/* debug CSR */
70 /* This structure holds all restricted conditions for a CSR. */
71 struct riscv_csr_extra
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class
;
77 /* CSR may have differnet numbers in the previous priv spec. */
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version
;
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version
;
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra
*next
;
91 /* All standard/Z* extensions defined in all supported ISA spec. */
92 struct riscv_ext_version
95 enum riscv_spec_class isa_spec_class
;
100 static const struct riscv_ext_version ext_version_table
[] =
102 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
106 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
110 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
114 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
118 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
122 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
126 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
130 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
134 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
137 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
142 /* Terminate the list. */
147 #define DEFAULT_ARCH "riscv64"
150 #ifndef DEFAULT_RISCV_ATTR
151 #define DEFAULT_RISCV_ATTR 0
154 /* Let riscv_after_parse_args set the default value according to xlen. */
155 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
156 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
159 /* Need to sync the version with RISC-V compiler. */
160 #ifndef DEFAULT_RISCV_ISA_SPEC
161 #define DEFAULT_RISCV_ISA_SPEC "2.2"
164 #ifndef DEFAULT_RISCV_PRIV_SPEC
165 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
168 static const char default_arch
[] = DEFAULT_ARCH
;
169 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
170 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
171 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
173 static unsigned xlen
= 0; /* The width of an x-register. */
174 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
175 static bfd_boolean rve_abi
= FALSE
;
178 FLOAT_ABI_DEFAULT
= -1,
184 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
186 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
187 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
189 static unsigned elf_flags
= 0;
191 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
192 Otherwise, return 1. */
195 riscv_set_default_isa_spec (const char *s
)
197 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
198 RISCV_GET_ISA_SPEC_CLASS (s
, class);
199 if (class == ISA_SPEC_CLASS_NONE
)
201 as_bad ("unknown default ISA spec `%s' set by "
202 "-misa-spec or --with-isa-spec", s
);
206 default_isa_spec
= class;
210 /* Set the default_priv_spec. Find the privileged elf attributes when
211 the input string is NULL. Return 0 if the spec isn't supported.
212 Otherwise, return 1. */
215 riscv_set_default_priv_spec (const char *s
)
217 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
218 unsigned major
, minor
, revision
;
221 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
222 if (class != PRIV_SPEC_CLASS_NONE
)
224 default_priv_spec
= class;
230 as_bad (_("unknown default privileged spec `%s' set by "
231 "-mpriv-spec or --with-priv-spec"), s
);
235 /* Set the default_priv_spec by the privileged elf attributes. */
236 attr
= elf_known_obj_attributes_proc (stdoutput
);
237 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
238 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
239 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
240 /* Version 0.0.0 is the default value and meningless. */
241 if (major
== 0 && minor
== 0 && revision
== 0)
244 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
245 if (class != PRIV_SPEC_CLASS_NONE
)
247 default_priv_spec
= class;
251 /* Still can not find the privileged spec class. */
252 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
253 "privileged elf attributes"), major
, minor
, revision
);
257 /* This is the set of options which the .option pseudo-op may modify. */
258 struct riscv_set_options
260 int pic
; /* Generate position-independent code. */
261 int rvc
; /* Generate RVC code. */
262 int rve
; /* Generate RVE code. */
263 int relax
; /* Emit relocs the linker is allowed to relax. */
264 int arch_attr
; /* Emit architecture and privileged elf attributes. */
265 int csr_check
; /* Enable the CSR checking. */
268 static struct riscv_set_options riscv_opts
=
274 DEFAULT_RISCV_ATTR
, /* arch_attr */
279 riscv_set_rvc (bfd_boolean rvc_value
)
282 elf_flags
|= EF_RISCV_RVC
;
284 riscv_opts
.rvc
= rvc_value
;
288 riscv_set_rve (bfd_boolean rve_value
)
290 riscv_opts
.rve
= rve_value
;
293 static riscv_subset_list_t riscv_subsets
;
296 riscv_subset_supports (const char *feature
)
298 struct riscv_subset_t
*subset
;
300 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
303 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
307 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
311 case INSN_CLASS_I
: return riscv_subset_supports ("i");
312 case INSN_CLASS_C
: return riscv_subset_supports ("c");
313 case INSN_CLASS_A
: return riscv_subset_supports ("a");
314 case INSN_CLASS_M
: return riscv_subset_supports ("m");
315 case INSN_CLASS_F
: return riscv_subset_supports ("f");
316 case INSN_CLASS_D
: return riscv_subset_supports ("d");
317 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
319 case INSN_CLASS_F_AND_C
:
320 return (riscv_subset_supports ("f")
321 && riscv_subset_supports ("c"));
322 case INSN_CLASS_D_AND_C
:
323 return (riscv_subset_supports ("d")
324 && riscv_subset_supports ("c"));
326 case INSN_CLASS_ZICSR
:
327 return riscv_subset_supports ("zicsr");
328 case INSN_CLASS_ZIFENCEI
:
329 return riscv_subset_supports ("zifencei");
330 case INSN_CLASS_ZIHINTPAUSE
:
331 return riscv_subset_supports ("zihintpause");
334 as_fatal ("internal: unreachable");
339 /* Handle of the extension with version hash table. */
340 static htab_t ext_version_hash
= NULL
;
343 init_ext_version_hash (void)
345 const struct riscv_ext_version
*table
= ext_version_table
;
346 htab_t hash
= str_htab_create ();
349 while (table
[i
].name
)
351 const char *name
= table
[i
].name
;
352 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
353 as_fatal (_("internal: duplicate %s"), name
);
357 && strcmp (table
[i
].name
, name
) == 0)
365 riscv_get_default_ext_version (const char *name
,
369 struct riscv_ext_version
*ext
;
371 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
374 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
377 && strcmp (ext
->name
, name
) == 0)
379 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
380 || ext
->isa_spec_class
== default_isa_spec
)
382 *major_version
= ext
->major_version
;
383 *minor_version
= ext
->minor_version
;
390 /* Set which ISA and extensions are available. */
393 riscv_set_arch (const char *s
)
395 riscv_parse_subset_t rps
;
396 rps
.subset_list
= &riscv_subsets
;
397 rps
.error_handler
= as_bad
;
399 rps
.get_default_version
= riscv_get_default_ext_version
;
404 riscv_release_subset_list (&riscv_subsets
);
405 riscv_parse_subset (&rps
, s
);
408 /* Indicate -mabi option is explictly set. */
409 static bfd_boolean explicit_mabi
= FALSE
;
412 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
415 float_abi
= new_float_abi
;
419 /* If the -mabi option isn't set, then set the abi according to the
420 ISA string. Otherwise, check if there is any conflict. */
423 riscv_set_abi_by_arch (void)
427 if (riscv_subset_supports ("q"))
428 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
429 else if (riscv_subset_supports ("d"))
430 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
432 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
436 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
438 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
439 else if (abi_xlen
< xlen
)
440 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
443 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
444 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
445 elf_flags
|= float_abi
<< 1;
448 elf_flags
|= EF_RISCV_RVE
;
451 /* Handle of the OPCODE hash table. */
452 static htab_t op_hash
= NULL
;
454 /* Handle of the type of .insn hash table. */
455 static htab_t insn_type_hash
= NULL
;
457 /* This array holds the chars that always start a comment. If the
458 pre-processor is disabled, these aren't very useful. */
459 const char comment_chars
[] = "#";
461 /* This array holds the chars that only start a comment at the beginning of
462 a line. If the line seems to have the form '# 123 filename'
463 .line and .file directives will appear in the pre-processed output
465 Note that input_file.c hand checks for '#' at the beginning of the
466 first line of the input file. This is because the compiler outputs
467 #NO_APP at the beginning of its output.
469 Also note that C style comments are always supported. */
470 const char line_comment_chars
[] = "#";
472 /* This array holds machine specific line separator characters. */
473 const char line_separator_chars
[] = ";";
475 /* Chars that can be used to separate mant from exp in floating point nums. */
476 const char EXP_CHARS
[] = "eE";
478 /* Chars that mean this number is a floating point constant.
479 As in 0f12.456 or 0d1.2345e12. */
480 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
482 /* Indicate we are already assemble any instructions or not. */
483 static bfd_boolean start_assemble
= FALSE
;
485 /* Indicate ELF attributes are explicitly set. */
486 static bfd_boolean explicit_attr
= FALSE
;
488 /* Indicate CSR or priv instructions are explicitly used. */
489 static bfd_boolean explicit_priv_attr
= FALSE
;
491 /* Macros for encoding relaxation state for RVC branches and far jumps. */
492 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
495 | ((uncond) ? 1 : 0) \
498 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
499 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
500 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
501 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
503 /* Is the given value a sign-extended 32-bit value? */
504 #define IS_SEXT_32BIT_NUM(x) \
505 (((x) &~ (offsetT) 0x7fffffff) == 0 \
506 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
508 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
509 #define IS_ZEXT_32BIT_NUM(x) \
510 (((x) &~ (offsetT) 0xffffffff) == 0 \
511 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
513 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
514 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
515 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
516 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
518 /* Determine if an instruction matches an opcode. */
519 #define OPCODE_MATCHES(OPCODE, OP) \
520 (((OPCODE) & MASK_##OP) == MATCH_##OP)
522 static char *expr_end
;
524 /* The default target format to use. */
527 riscv_target_format (void)
529 if (target_big_endian
)
530 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
532 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
535 /* Return the length of instruction INSN. */
537 static inline unsigned int
538 insn_length (const struct riscv_cl_insn
*insn
)
540 return riscv_insn_length (insn
->insn_opcode
);
543 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
546 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
549 insn
->insn_opcode
= mo
->match
;
555 /* Install INSN at the location specified by its "frag" and "where" fields. */
558 install_insn (const struct riscv_cl_insn
*insn
)
560 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
561 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
564 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
565 and install the opcode in the new location. */
568 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
572 if (insn
->fixp
!= NULL
)
574 insn
->fixp
->fx_frag
= frag
;
575 insn
->fixp
->fx_where
= where
;
580 /* Add INSN to the end of the output. */
583 add_fixed_insn (struct riscv_cl_insn
*insn
)
585 char *f
= frag_more (insn_length (insn
));
586 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
590 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
591 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
593 frag_grow (max_chars
);
594 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
595 frag_var (rs_machine_dependent
, max_chars
, var
,
596 subtype
, symbol
, offset
, NULL
);
599 /* Compute the length of a branch sequence, and adjust the stored length
600 accordingly. If FRAGP is NULL, the worst-case length is returned. */
603 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
605 int jump
, rvc
, length
= 8;
610 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
611 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
612 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
614 /* Assume jumps are in range; the linker will catch any that aren't. */
615 length
= jump
? 4 : 8;
617 if (fragp
->fr_symbol
!= NULL
618 && S_IS_DEFINED (fragp
->fr_symbol
)
619 && !S_IS_WEAK (fragp
->fr_symbol
)
620 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
622 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
623 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
624 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
626 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
628 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
630 else if (!jump
&& rvc
)
635 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
640 /* Information about an opcode name, mnemonics and its value. */
647 /* List for all supported opcode name. */
648 static const struct opcode_name_t opcode_name_list
[] =
693 /* Hash table for lookup opcode name. */
694 static htab_t opcode_names_hash
= NULL
;
696 /* Initialization for hash table of opcode name. */
699 init_opcode_names_hash (void)
701 const struct opcode_name_t
*opcode
;
703 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
704 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
705 as_fatal (_("internal: duplicate %s"), opcode
->name
);
708 /* Find `s` is a valid opcode name or not, return the opcode name info
711 static const struct opcode_name_t
*
712 opcode_name_lookup (char **s
)
716 struct opcode_name_t
*o
;
718 /* Find end of name. */
720 if (is_name_beginner (*e
))
722 while (is_part_of_name (*e
))
725 /* Terminate name. */
729 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
731 /* Advance to next token if one was recognized. */
750 static htab_t reg_names_hash
= NULL
;
751 static htab_t csr_extra_hash
= NULL
;
753 #define ENCODE_REG_HASH(cls, n) \
754 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
755 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
756 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
759 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
761 void *hash
= ENCODE_REG_HASH (class, n
);
762 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
763 as_fatal (_("internal: duplicate %s"), name
);
767 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
771 for (i
= 0; i
< n
; i
++)
772 hash_reg_name (class, names
[i
], i
);
775 /* Init hash table csr_extra_hash to handle CSR. */
778 riscv_init_csr_hash (const char *name
,
780 enum riscv_csr_class
class,
781 enum riscv_spec_class define_version
,
782 enum riscv_spec_class abort_version
)
784 struct riscv_csr_extra
*entry
, *pre_entry
;
785 bfd_boolean need_enrty
= TRUE
;
788 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
789 while (need_enrty
&& entry
!= NULL
)
791 if (entry
->csr_class
== class
792 && entry
->address
== address
793 && entry
->define_version
== define_version
794 && entry
->abort_version
== abort_version
)
804 entry
= XNEW (struct riscv_csr_extra
);
805 entry
->csr_class
= class;
806 entry
->address
= address
;
807 entry
->define_version
= define_version
;
808 entry
->abort_version
= abort_version
;
811 if (pre_entry
== NULL
)
812 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
814 pre_entry
->next
= entry
;
817 /* Return the CSR address after checking the ISA dependency and
818 the privileged spec version.
820 There are one warning and two errors for CSR,
822 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
823 or the privileged spec, report warning only if -mcsr-check is set.
824 Unknown CSR: the CSR has never been defined, report error.
825 Improper CSR: the CSR number over the range (> 0xfff), report error. */
828 riscv_csr_address (const char *csr_name
,
829 struct riscv_csr_extra
*entry
)
831 struct riscv_csr_extra
*saved_entry
= entry
;
832 enum riscv_csr_class csr_class
= entry
->csr_class
;
833 bfd_boolean need_check_version
= TRUE
;
834 bfd_boolean result
= TRUE
;
839 result
= riscv_subset_supports ("i");
842 result
= (xlen
== 32 && riscv_subset_supports ("i"));
845 result
= riscv_subset_supports ("f");
846 need_check_version
= FALSE
;
848 case CSR_CLASS_DEBUG
:
849 need_check_version
= FALSE
;
852 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
855 if (riscv_opts
.csr_check
&& !result
)
856 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
858 while (entry
!= NULL
)
860 if (!need_check_version
861 || (default_priv_spec
>= entry
->define_version
862 && default_priv_spec
< entry
->abort_version
))
864 /* Find the CSR according to the specific version. */
865 return entry
->address
;
870 /* Can not find the CSR address from the chosen privileged version,
871 so use the newly defined value. */
872 if (riscv_opts
.csr_check
)
874 const char *priv_name
= NULL
;
875 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
876 if (priv_name
!= NULL
)
877 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
878 csr_name
, priv_name
);
881 return saved_entry
->address
;
884 /* Return -1 if the CSR has never been defined. Otherwise, return
888 reg_csr_lookup_internal (const char *s
)
890 struct riscv_csr_extra
*r
=
891 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
896 return riscv_csr_address (s
, r
);
900 reg_lookup_internal (const char *s
, enum reg_class
class)
904 if (class == RCLASS_CSR
)
905 return reg_csr_lookup_internal (s
);
907 r
= str_hash_find (reg_names_hash
, s
);
908 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
911 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
914 return DECODE_REG_NUM (r
);
918 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
924 /* Find end of name. */
926 if (is_name_beginner (*e
))
928 while (is_part_of_name (*e
))
931 /* Terminate name. */
935 /* Look for the register. Advance to next token if one was recognized. */
936 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
946 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
948 const char *p
= strchr (*s
, ',');
949 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
954 for (i
= 0; i
< size
; i
++)
955 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
965 /* For consistency checking, verify that all bits are specified either
966 by the match/mask part of the instruction definition, or by the
967 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
970 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
972 const char *p
= opc
->args
;
974 insn_t used_bits
= opc
->mask
;
976 insn_t required_bits
;
979 insn_width
= 8 * riscv_insn_length (opc
->match
);
981 insn_width
= 8 * length
;
983 required_bits
= ~0ULL >> (64 - insn_width
);
985 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
987 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
988 opc
->name
, opc
->args
);
992 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
999 case 'U': break; /* CRS1, constrained to equal RD. */
1000 case 'c': break; /* CRS1, constrained to equal sp. */
1001 case 'T': /* CRS2, floating point. */
1002 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1003 case 'S': /* CRS1S, floating point. */
1004 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1005 case 'w': break; /* CRS1S, constrained to equal RD. */
1006 case 'D': /* CRS2S, floating point. */
1007 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1008 case 'x': break; /* CRS2S, constrained to equal RD. */
1009 case 'z': break; /* CRS2S, constrained to be x0. */
1010 case '>': /* CITYPE immediate, compressed shift. */
1011 case 'u': /* CITYPE immediate, compressed lui. */
1012 case 'v': /* CITYPE immediate, li to compressed lui. */
1013 case 'o': /* CITYPE immediate, allow zero. */
1014 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1015 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1016 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1017 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1018 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1019 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1020 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1021 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1022 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1023 /* CLTYPE and CSTYPE have the same immediate encoding. */
1024 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1025 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1026 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1027 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1028 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1029 case 'F': /* Compressed funct for .insn directive. */
1032 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1033 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1034 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1035 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1037 as_bad (_("internal: bad RISC-V opcode "
1038 "(unknown operand type `CF%c'): %s %s"),
1039 c
, opc
->name
, opc
->args
);
1044 as_bad (_("internal: bad RISC-V opcode "
1045 "(unknown operand type `C%c'): %s %s"),
1046 c
, opc
->name
, opc
->args
);
1053 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1054 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1055 case 'A': break; /* Macro operand, must be symbol. */
1056 case 'B': break; /* Macro operand, must be symbol or constant. */
1057 case 'I': break; /* Macro operand, must be constant. */
1058 case 'D': /* RD, floating point. */
1059 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1060 case 'Z': /* RS1, CSR number. */
1061 case 'S': /* RS1, floating point. */
1062 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1063 case 'U': /* RS1 and RS2 are the same, floating point. */
1064 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1066 case 'T': /* RS2, floating point. */
1067 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1068 case 'R': /* RS3, floating point. */
1069 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1070 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1071 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1072 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1073 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1074 case 'o': /* ITYPE immediate, load displacement. */
1075 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1076 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1077 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1078 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1079 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1080 case 'z': break; /* Zero immediate. */
1081 case '[': break; /* Unused operand. */
1082 case ']': break; /* Unused operand. */
1083 case '0': break; /* AMO displacement, must to zero. */
1084 case '1': break; /* Relaxation operand. */
1085 case 'F': /* Funct for .insn directive. */
1088 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1089 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1090 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1092 as_bad (_("internal: bad RISC-V opcode "
1093 "(unknown operand type `F%c'): %s %s"),
1094 c
, opc
->name
, opc
->args
);
1098 case 'O': /* Opcode for .insn directive. */
1101 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1102 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1104 as_bad (_("internal: bad RISC-V opcode "
1105 "(unknown operand type `F%c'): %s %s"),
1106 c
, opc
->name
, opc
->args
);
1111 as_bad (_("internal: bad RISC-V opcode "
1112 "(unknown operand type `%c'): %s %s"),
1113 c
, opc
->name
, opc
->args
);
1117 if (used_bits
!= required_bits
)
1119 as_bad (_("internal: bad RISC-V opcode "
1120 "(bits 0x%lx undefined): %s %s"),
1121 ~(unsigned long)(used_bits
& required_bits
),
1122 opc
->name
, opc
->args
);
1128 struct percent_op_match
1131 bfd_reloc_code_real_type reloc
;
1134 /* Common hash table initialization function for instruction and .insn
1138 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1139 bfd_boolean insn_directive_p
)
1143 htab_t hash
= str_htab_create ();
1144 while (opcodes
[i
].name
)
1146 const char *name
= opcodes
[i
].name
;
1147 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1148 as_fatal (_("internal: duplicate %s"), name
);
1152 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1154 if (insn_directive_p
)
1155 length
= ((name
[0] == 'c') ? 2 : 4);
1157 length
= 0; /* Let assembler determine the length. */
1158 if (!validate_riscv_insn (&opcodes
[i
], length
))
1159 as_fatal (_("internal: broken assembler. "
1160 "No assembly attempted"));
1163 gas_assert (!insn_directive_p
);
1166 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1172 /* This function is called once, at assembler startup time. It should set up
1173 all the tables, etc. that the MD part of the assembler will need. */
1178 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1180 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1181 as_warn (_("could not set architecture and machine"));
1183 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1184 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1186 reg_names_hash
= str_htab_create ();
1187 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1188 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1189 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1190 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1191 /* Add "fp" as an alias for "s0". */
1192 hash_reg_name (RCLASS_GPR
, "fp", 8);
1194 /* Create and insert CSR hash tables. */
1195 csr_extra_hash
= str_htab_create ();
1196 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1197 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1198 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1199 DECLARE_CSR(name, num, class, define_version, abort_version);
1200 #include "opcode/riscv-opc.h"
1203 opcode_names_hash
= str_htab_create ();
1204 init_opcode_names_hash ();
1206 /* Set the default alignment for the text section. */
1207 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1211 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1218 case BFD_RELOC_RISCV_HI20
:
1219 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1221 case BFD_RELOC_RISCV_LO12_S
:
1222 return ENCODE_STYPE_IMM (value
);
1224 case BFD_RELOC_RISCV_LO12_I
:
1225 return ENCODE_ITYPE_IMM (value
);
1232 /* Output an instruction. IP is the instruction information.
1233 ADDRESS_EXPR is an operand of the instruction to be used with
1237 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1238 bfd_reloc_code_real_type reloc_type
)
1240 dwarf2_emit_insn (0);
1242 if (reloc_type
!= BFD_RELOC_UNUSED
)
1244 reloc_howto_type
*howto
;
1246 gas_assert (address_expr
);
1247 if (reloc_type
== BFD_RELOC_12_PCREL
1248 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1250 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1251 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1252 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1254 if (now_seg
== absolute_section
)
1256 as_bad (_("relaxable branches not supported in absolute section"));
1260 add_relaxed_insn (ip
, worst_case
, best_case
,
1261 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1262 address_expr
->X_add_symbol
,
1263 address_expr
->X_add_number
);
1268 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1270 as_bad (_("internal: usupported RISC-V relocation number %d"),
1273 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1274 bfd_get_reloc_size (howto
),
1275 address_expr
, FALSE
, reloc_type
);
1277 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1281 add_fixed_insn (ip
);
1284 /* We need to start a new frag after any instruction that can be
1285 optimized away or compressed by the linker during relaxation, to prevent
1286 the assembler from computing static offsets across such an instruction.
1287 This is necessary to get correct EH info. */
1288 if (reloc_type
== BFD_RELOC_RISCV_HI20
1289 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1290 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1291 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1293 frag_wane (frag_now
);
1298 /* Build an instruction created by a macro expansion. This is passed
1299 a pointer to the count of instructions created so far, an expression,
1300 the name of the instruction to build, an operand format string, and
1301 corresponding arguments. */
1304 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1306 const struct riscv_opcode
*mo
;
1307 struct riscv_cl_insn insn
;
1308 bfd_reloc_code_real_type r
;
1311 va_start (args
, fmt
);
1313 r
= BFD_RELOC_UNUSED
;
1314 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1317 /* Find a non-RVC variant of the instruction. append_insn will compress
1319 while (riscv_insn_length (mo
->match
) < 4)
1321 gas_assert (strcmp (name
, mo
->name
) == 0);
1323 create_insn (&insn
, mo
);
1329 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1333 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1337 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1343 gas_assert (ep
!= NULL
);
1344 r
= va_arg (args
, int);
1352 as_fatal (_("internal: invalid macro"));
1357 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1359 append_insn (&insn
, ep
, r
);
1362 /* Build an instruction created by a macro expansion. Like md_assemble but
1363 accept a printf-style format string and arguments. */
1366 md_assemblef (const char *format
, ...)
1372 va_start (ap
, format
);
1374 r
= vasprintf (&buf
, format
, ap
);
1377 as_fatal (_("internal: vasprintf failed"));
1385 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1389 normalize_constant_expr (expressionS
*ex
)
1393 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1394 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1395 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1399 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1400 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1403 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1404 bfd_boolean maybe_csr
)
1406 if (ex
->X_op
== O_big
)
1407 as_bad (_("unsupported large constant"));
1408 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1409 as_bad (_("unknown CSR `%s'"),
1410 S_GET_NAME (ex
->X_add_symbol
));
1411 else if (ex
->X_op
!= O_constant
)
1412 as_bad (_("instruction %s requires absolute expression"),
1414 normalize_constant_expr (ex
);
1418 make_internal_label (void)
1420 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1424 /* Load an entry from the GOT. */
1427 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1428 const char *lo_insn
, const char *lo_pattern
,
1429 bfd_reloc_code_real_type hi_reloc
,
1430 bfd_reloc_code_real_type lo_reloc
)
1433 ep2
.X_op
= O_symbol
;
1434 ep2
.X_add_symbol
= make_internal_label ();
1435 ep2
.X_add_number
= 0;
1437 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1438 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1442 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1443 bfd_reloc_code_real_type hi_reloc
,
1444 bfd_reloc_code_real_type lo_reloc
)
1446 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1450 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1451 bfd_reloc_code_real_type hi_reloc
,
1452 bfd_reloc_code_real_type lo_reloc
)
1454 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1457 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1460 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1461 bfd_reloc_code_real_type reloc
)
1463 /* Ensure the jalr is emitted to the same frag as the auipc. */
1465 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1466 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1467 /* See comment at end of append_insn. */
1468 frag_wane (frag_now
);
1472 /* Load an integer constant into a register. */
1475 load_const (int reg
, expressionS
*ep
)
1477 int shift
= RISCV_IMM_BITS
;
1478 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1479 expressionS upper
= *ep
, lower
= *ep
;
1480 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1481 upper
.X_add_number
-= lower
.X_add_number
;
1483 if (ep
->X_op
!= O_constant
)
1485 as_bad (_("unsupported large constant"));
1489 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1491 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1492 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1495 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1496 load_const (reg
, &upper
);
1498 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1499 if (lower
.X_add_number
!= 0)
1500 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1501 lower
.X_add_number
);
1505 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1508 if (upper
.X_add_number
!= 0)
1510 /* Discard low part and zero-extend upper immediate. */
1511 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1513 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1517 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1518 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1519 lower
.X_add_number
);
1523 /* Zero extend and sign extend byte/half-word/word. */
1526 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1530 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1531 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1535 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1536 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1540 /* Expand RISC-V assembly macros into one or more instructions. */
1543 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1544 bfd_reloc_code_real_type
*imm_reloc
)
1546 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1547 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1548 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1549 int mask
= ip
->insn_mo
->mask
;
1554 load_const (rd
, imm_expr
);
1559 /* Load the address of a symbol into a register. */
1560 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1561 as_bad (_("offset too large"));
1563 if (imm_expr
->X_op
== O_constant
)
1564 load_const (rd
, imm_expr
);
1565 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1566 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1567 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1568 else /* Local PIC symbol, or any non-PIC symbol. */
1569 pcrel_load (rd
, rd
, imm_expr
, "addi",
1570 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1574 pcrel_load (rd
, rd
, imm_expr
, "addi",
1575 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1579 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1580 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1584 pcrel_load (rd
, rd
, imm_expr
, "lb",
1585 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1589 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1590 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1594 pcrel_load (rd
, rd
, imm_expr
, "lh",
1595 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1599 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1600 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1604 pcrel_load (rd
, rd
, imm_expr
, "lw",
1605 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1609 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1610 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1614 pcrel_load (rd
, rd
, imm_expr
, "ld",
1615 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1619 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1620 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1624 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1625 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1629 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1630 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1634 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1635 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1639 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1640 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1644 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1645 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1649 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1650 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1654 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1655 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1659 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1663 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1667 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1671 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1675 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1679 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1684 static const struct percent_op_match percent_op_utype
[] =
1686 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1687 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1688 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1689 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1690 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1691 {"%hi", BFD_RELOC_RISCV_HI20
},
1695 static const struct percent_op_match percent_op_itype
[] =
1697 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1698 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1699 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1703 static const struct percent_op_match percent_op_stype
[] =
1705 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1706 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1707 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1711 static const struct percent_op_match percent_op_rtype
[] =
1713 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1717 static const struct percent_op_match percent_op_null
[] =
1722 /* Return true if *STR points to a relocation operator. When returning true,
1723 move *STR over the operator and store its relocation code in *RELOC.
1724 Leave both *STR and *RELOC alone when returning false. */
1727 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1728 const struct percent_op_match
*percent_op
)
1730 for ( ; percent_op
->str
; percent_op
++)
1731 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1733 int len
= strlen (percent_op
->str
);
1735 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1738 *str
+= strlen (percent_op
->str
);
1739 *reloc
= percent_op
->reloc
;
1741 /* Check whether the output BFD supports this relocation.
1742 If not, issue an error and fall back on something safe. */
1743 if (*reloc
!= BFD_RELOC_UNUSED
1744 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1746 as_bad ("internal: relocation %s isn't supported by the "
1747 "current ABI", percent_op
->str
);
1748 *reloc
= BFD_RELOC_UNUSED
;
1756 my_getExpression (expressionS
*ep
, char *str
)
1760 save_in
= input_line_pointer
;
1761 input_line_pointer
= str
;
1763 expr_end
= input_line_pointer
;
1764 input_line_pointer
= save_in
;
1767 /* Parse string STR as a 16-bit relocatable operand. Store the
1768 expression in *EP and the relocation, if any, in RELOC.
1769 Return the number of relocation operators used (0 or 1).
1771 On exit, EXPR_END points to the first character after the expression. */
1774 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1775 char *str
, const struct percent_op_match
*percent_op
)
1778 unsigned crux_depth
, str_depth
, regno
;
1781 /* First, check for integer registers. No callers can accept a reg, but
1782 we need to avoid accidentally creating a useless undefined symbol below,
1783 if this is an instruction pattern that can't match. A glibc build fails
1784 if this is removed. */
1785 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1787 ep
->X_op
= O_register
;
1788 ep
->X_add_number
= regno
;
1793 /* Search for the start of the main expression.
1795 End the loop with CRUX pointing to the start of the main expression and
1796 with CRUX_DEPTH containing the number of open brackets at that point. */
1803 crux_depth
= str_depth
;
1805 /* Skip over whitespace and brackets, keeping count of the number
1807 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1813 && parse_relocation (&str
, reloc
, percent_op
));
1815 my_getExpression (ep
, crux
);
1818 /* Match every open bracket. */
1819 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1824 as_bad ("unclosed '('");
1831 /* Parse opcode name, could be an mnemonics or number. */
1834 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1835 char *str
, const struct percent_op_match
*percent_op
)
1837 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1841 ep
->X_op
= O_constant
;
1842 ep
->X_add_number
= o
->val
;
1846 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1849 /* Detect and handle implicitly zero load-store offsets. For example,
1850 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1851 an implicit offset was detected. */
1854 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1856 /* Check whether there is only a single bracketed expression left.
1857 If so, it must be the base register and the constant must be zero. */
1858 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1860 ep
->X_op
= O_constant
;
1861 ep
->X_add_number
= 0;
1868 /* All RISC-V CSR instructions belong to one of these classes. */
1877 /* Return which CSR instruction is checking. */
1879 static enum csr_insn_type
1880 riscv_csr_insn_type (insn_t insn
)
1882 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1883 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1885 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1886 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1888 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1889 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1892 return INSN_NOT_CSR
;
1895 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1896 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1897 CSR address is 0x3. */
1900 riscv_csr_read_only_check (insn_t insn
)
1902 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1903 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1904 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1905 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1908 && (((csr_insn
== INSN_CSRRS
1909 || csr_insn
== INSN_CSRRC
)
1911 || csr_insn
== INSN_CSRRW
))
1917 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1919 uret is actually a N-ext instruction. So it is better to regard it as
1920 an user instruction rather than the priv instruction.
1922 hret is used to return from traps in H-mode. H-mode is removed since
1923 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1924 Therefore, hret should be controlled by the hypervisor spec rather than
1925 priv spec in the future.
1927 dret is defined in the debug spec, so it should be checked in the future,
1931 riscv_is_priv_insn (insn_t insn
)
1933 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1934 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1935 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1936 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1937 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1938 check it here to keep the compatible. */
1939 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1942 /* This routine assembles an instruction into its binary format. As a
1943 side effect, it sets the global variable imm_reloc to the type of
1944 relocation to do if one of the operands is an address expression. */
1947 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1948 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1953 struct riscv_opcode
*insn
;
1958 const struct percent_op_match
*p
;
1959 const char *error
= "unrecognized opcode";
1960 /* Indicate we are assembling instruction with CSR. */
1961 bfd_boolean insn_with_csr
= FALSE
;
1963 /* Parse the name of the instruction. Terminate the string if whitespace
1964 is found so that str_hash_find only sees the name part of the string. */
1965 for (s
= str
; *s
!= '\0'; ++s
)
1973 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1976 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1978 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1981 if (!riscv_multi_subset_supports (insn
->insn_class
))
1984 create_insn (ip
, insn
);
1987 imm_expr
->X_op
= O_absent
;
1988 *imm_reloc
= BFD_RELOC_UNUSED
;
1989 p
= percent_op_itype
;
1991 for (args
= insn
->args
;; ++args
)
1993 s
+= strspn (s
, " \t");
1996 case '\0': /* End of args. */
1997 if (insn
->pinfo
!= INSN_MACRO
)
1999 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2002 /* For .insn, insn->match and insn->mask are 0. */
2003 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2009 if (riscv_is_priv_insn (ip
->insn_opcode
))
2010 explicit_priv_attr
= TRUE
;
2012 /* Check if we write a read-only CSR by the CSR
2015 && riscv_opts
.csr_check
2016 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2018 /* Restore the character in advance, since we want to
2019 report the detailed warning message here. */
2021 *(argsStart
- 1) = save_c
;
2022 as_warn (_("read-only CSR is written `%s'"), str
);
2023 insn_with_csr
= FALSE
;
2028 /* Successful assembly. */
2030 insn_with_csr
= FALSE
;
2036 case 's': /* RS1 x8-x15. */
2037 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2038 || !(regno
>= 8 && regno
<= 15))
2040 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2042 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2043 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2044 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2047 case 't': /* RS2 x8-x15. */
2048 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2049 || !(regno
>= 8 && regno
<= 15))
2051 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2053 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2054 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2055 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2058 case 'U': /* RS1, constrained to equal RD. */
2059 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2060 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2064 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
2066 INSERT_OPERAND (CRS2
, *ip
, regno
);
2068 case 'c': /* RS1, constrained to equal sp. */
2069 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2073 case 'z': /* RS2, constrained to equal x0. */
2074 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2079 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2080 || imm_expr
->X_op
!= O_constant
2081 || imm_expr
->X_add_number
<= 0
2082 || imm_expr
->X_add_number
>= 64)
2084 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2087 imm_expr
->X_op
= O_absent
;
2090 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2091 || imm_expr
->X_op
!= O_constant
2092 || imm_expr
->X_add_number
< 0
2093 || imm_expr
->X_add_number
>= 32
2094 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2096 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2099 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2100 || imm_expr
->X_op
!= O_constant
2101 || imm_expr
->X_add_number
< 0
2102 || imm_expr
->X_add_number
>= 64
2103 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2105 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2108 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2109 || imm_expr
->X_op
!= O_constant
2110 || imm_expr
->X_add_number
< 0
2111 || imm_expr
->X_add_number
>= 256
2112 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2114 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2117 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2118 || imm_expr
->X_op
!= O_constant
2119 || imm_expr
->X_add_number
== 0
2120 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2122 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2125 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2127 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2128 || imm_expr
->X_op
!= O_constant
2129 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2131 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2134 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2136 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2137 || imm_expr
->X_op
!= O_constant
2138 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2140 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2143 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2145 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2146 || imm_expr
->X_op
!= O_constant
2147 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2150 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2153 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2155 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2156 || imm_expr
->X_op
!= O_constant
2157 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2160 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2163 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2164 || imm_expr
->X_op
!= O_constant
2165 /* C.addiw, c.li, and c.andi allow zero immediate.
2166 C.addi allows zero immediate as hint. Otherwise this
2168 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2170 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2173 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2174 || imm_expr
->X_op
!= O_constant
2175 || imm_expr
->X_add_number
== 0
2176 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2179 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2182 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2183 || imm_expr
->X_op
!= O_constant
2184 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2187 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2190 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2192 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2193 || imm_expr
->X_op
!= O_constant
2194 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2197 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2200 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2202 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2203 || imm_expr
->X_op
!= O_constant
2204 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2207 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2210 p
= percent_op_utype
;
2211 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2214 if (imm_expr
->X_op
!= O_constant
2215 || imm_expr
->X_add_number
<= 0
2216 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2217 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2218 && (imm_expr
->X_add_number
<
2219 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2221 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2224 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2225 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2226 || ((int32_t)imm_expr
->X_add_number
2227 != imm_expr
->X_add_number
))
2229 imm_expr
->X_add_number
=
2230 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2236 case 'S': /* Floating-point RS1 x8-x15. */
2237 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2238 || !(regno
>= 8 && regno
<= 15))
2240 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2242 case 'D': /* Floating-point RS2 x8-x15. */
2243 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2244 || !(regno
>= 8 && regno
<= 15))
2246 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2248 case 'T': /* Floating-point RS2. */
2249 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2251 INSERT_OPERAND (CRS2
, *ip
, regno
);
2257 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2258 || imm_expr
->X_op
!= O_constant
2259 || imm_expr
->X_add_number
< 0
2260 || imm_expr
->X_add_number
>= 64)
2262 as_bad (_("bad value for compressed funct6 "
2263 "field, value must be 0...64"));
2266 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2267 imm_expr
->X_op
= O_absent
;
2272 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2273 || imm_expr
->X_op
!= O_constant
2274 || imm_expr
->X_add_number
< 0
2275 || imm_expr
->X_add_number
>= 16)
2277 as_bad (_("bad value for compressed funct4 "
2278 "field, value must be 0...15"));
2281 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2282 imm_expr
->X_op
= O_absent
;
2287 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2288 || imm_expr
->X_op
!= O_constant
2289 || imm_expr
->X_add_number
< 0
2290 || imm_expr
->X_add_number
>= 8)
2292 as_bad (_("bad value for compressed funct3 "
2293 "field, value must be 0...7"));
2296 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2297 imm_expr
->X_op
= O_absent
;
2302 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2303 || imm_expr
->X_op
!= O_constant
2304 || imm_expr
->X_add_number
< 0
2305 || imm_expr
->X_add_number
>= 4)
2307 as_bad (_("bad value for compressed funct2 "
2308 "field, value must be 0...3"));
2311 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2312 imm_expr
->X_op
= O_absent
;
2317 as_bad (_("internal: unknown compressed funct "
2318 "field specifier `CF%c'"), *args
);
2323 as_bad (_("internal: unknown compressed field "
2324 "specifier `C%c'"), *args
);
2343 case '<': /* Shift amount, 0 - 31. */
2344 my_getExpression (imm_expr
, s
);
2345 check_absolute_expr (ip
, imm_expr
, FALSE
);
2346 if ((unsigned long) imm_expr
->X_add_number
> 31)
2347 as_bad (_("improper shift amount (%lu)"),
2348 (unsigned long) imm_expr
->X_add_number
);
2349 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2350 imm_expr
->X_op
= O_absent
;
2354 case '>': /* Shift amount, 0 - (XLEN-1). */
2355 my_getExpression (imm_expr
, s
);
2356 check_absolute_expr (ip
, imm_expr
, FALSE
);
2357 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2358 as_bad (_("improper shift amount (%lu)"),
2359 (unsigned long) imm_expr
->X_add_number
);
2360 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2361 imm_expr
->X_op
= O_absent
;
2365 case 'Z': /* CSRRxI immediate. */
2366 my_getExpression (imm_expr
, s
);
2367 check_absolute_expr (ip
, imm_expr
, FALSE
);
2368 if ((unsigned long) imm_expr
->X_add_number
> 31)
2369 as_bad (_("improper CSRxI immediate (%lu)"),
2370 (unsigned long) imm_expr
->X_add_number
);
2371 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2372 imm_expr
->X_op
= O_absent
;
2376 case 'E': /* Control register. */
2377 insn_with_csr
= TRUE
;
2378 explicit_priv_attr
= TRUE
;
2379 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2380 INSERT_OPERAND (CSR
, *ip
, regno
);
2383 my_getExpression (imm_expr
, s
);
2384 check_absolute_expr (ip
, imm_expr
, TRUE
);
2385 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2386 as_bad (_("improper CSR address (%lu)"),
2387 (unsigned long) imm_expr
->X_add_number
);
2388 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2389 imm_expr
->X_op
= O_absent
;
2394 case 'm': /* Rounding mode. */
2395 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2397 INSERT_OPERAND (RM
, *ip
, regno
);
2403 case 'Q': /* Fence predecessor/successor. */
2404 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2408 INSERT_OPERAND (PRED
, *ip
, regno
);
2410 INSERT_OPERAND (SUCC
, *ip
, regno
);
2415 case 'd': /* Destination register. */
2416 case 's': /* Source register. */
2417 case 't': /* Target register. */
2419 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2425 /* Now that we have assembled one operand, we use the args
2426 string to figure out where it goes in the instruction. */
2430 INSERT_OPERAND (RS1
, *ip
, regno
);
2433 INSERT_OPERAND (RD
, *ip
, regno
);
2436 INSERT_OPERAND (RS2
, *ip
, regno
);
2439 INSERT_OPERAND (RS3
, *ip
, regno
);
2446 case 'D': /* Floating point RD. */
2447 case 'S': /* Floating point RS1. */
2448 case 'T': /* Floating point RS2. */
2449 case 'U': /* Floating point RS1 and RS2. */
2450 case 'R': /* Floating point RS3. */
2451 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2459 INSERT_OPERAND (RD
, *ip
, regno
);
2462 INSERT_OPERAND (RS1
, *ip
, regno
);
2465 INSERT_OPERAND (RS1
, *ip
, regno
);
2468 INSERT_OPERAND (RS2
, *ip
, regno
);
2471 INSERT_OPERAND (RS3
, *ip
, regno
);
2479 my_getExpression (imm_expr
, s
);
2480 if (imm_expr
->X_op
!= O_big
2481 && imm_expr
->X_op
!= O_constant
)
2483 normalize_constant_expr (imm_expr
);
2488 my_getExpression (imm_expr
, s
);
2489 normalize_constant_expr (imm_expr
);
2490 /* The 'A' format specifier must be a symbol. */
2491 if (imm_expr
->X_op
!= O_symbol
)
2493 *imm_reloc
= BFD_RELOC_32
;
2498 my_getExpression (imm_expr
, s
);
2499 normalize_constant_expr (imm_expr
);
2500 /* The 'B' format specifier must be a symbol or a constant. */
2501 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2503 if (imm_expr
->X_op
== O_symbol
)
2504 *imm_reloc
= BFD_RELOC_32
;
2508 case 'j': /* Sign-extended immediate. */
2509 p
= percent_op_itype
;
2510 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2512 case 'q': /* Store displacement. */
2513 p
= percent_op_stype
;
2514 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2516 case 'o': /* Load displacement. */
2517 p
= percent_op_itype
;
2518 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2521 /* This is used for TLS, where the fourth operand is
2522 %tprel_add, to get a relocation applied to an add
2523 instruction, for relaxation to use. */
2524 p
= percent_op_rtype
;
2526 case '0': /* AMO displacement, which must be zero. */
2527 p
= percent_op_null
;
2529 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2532 /* If this value won't fit into a 16 bit offset, then go
2533 find a macro that will generate the 32 bit offset
2535 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2537 normalize_constant_expr (imm_expr
);
2538 if (imm_expr
->X_op
!= O_constant
2539 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2541 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2542 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2548 case 'p': /* PC-relative offset. */
2550 *imm_reloc
= BFD_RELOC_12_PCREL
;
2551 my_getExpression (imm_expr
, s
);
2555 case 'u': /* Upper 20 bits. */
2556 p
= percent_op_utype
;
2557 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2559 if (imm_expr
->X_op
!= O_constant
)
2562 if (imm_expr
->X_add_number
< 0
2563 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2564 as_bad (_("lui expression not in range 0..1048575"));
2566 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2567 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2572 case 'a': /* 20-bit PC-relative offset. */
2574 my_getExpression (imm_expr
, s
);
2576 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2580 my_getExpression (imm_expr
, s
);
2582 if (strcmp (s
, "@plt") == 0)
2584 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2588 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2595 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2596 || imm_expr
->X_op
!= O_constant
2597 || imm_expr
->X_add_number
< 0
2598 || imm_expr
->X_add_number
>= 128
2599 || (imm_expr
->X_add_number
& 0x3) != 3)
2601 as_bad (_("bad value for opcode field, "
2602 "value must be 0...127 and "
2603 "lower 2 bits must be 0x3"));
2606 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2607 imm_expr
->X_op
= O_absent
;
2612 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2613 || imm_expr
->X_op
!= O_constant
2614 || imm_expr
->X_add_number
< 0
2615 || imm_expr
->X_add_number
>= 3)
2617 as_bad (_("bad value for opcode field, "
2618 "value must be 0...2"));
2621 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2622 imm_expr
->X_op
= O_absent
;
2627 as_bad (_("internal: unknown opcode field "
2628 "specifier `O%c'"), *args
);
2636 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2637 || imm_expr
->X_op
!= O_constant
2638 || imm_expr
->X_add_number
< 0
2639 || imm_expr
->X_add_number
>= 128)
2641 as_bad (_("bad value for funct7 field, "
2642 "value must be 0...127"));
2645 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2646 imm_expr
->X_op
= O_absent
;
2651 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2652 || imm_expr
->X_op
!= O_constant
2653 || imm_expr
->X_add_number
< 0
2654 || imm_expr
->X_add_number
>= 8)
2656 as_bad (_("bad value for funct3 field, "
2657 "value must be 0...7"));
2660 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2661 imm_expr
->X_op
= O_absent
;
2666 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2667 || imm_expr
->X_op
!= O_constant
2668 || imm_expr
->X_add_number
< 0
2669 || imm_expr
->X_add_number
>= 4)
2671 as_bad (_("bad value for funct2 field, "
2672 "value must be 0...3"));
2675 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2676 imm_expr
->X_op
= O_absent
;
2681 as_bad (_("internal: unknown funct field "
2682 "specifier `F%c'\n"), *args
);
2687 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2688 || imm_expr
->X_op
!= O_constant
2689 || imm_expr
->X_add_number
!= 0)
2692 imm_expr
->X_op
= O_absent
;
2696 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2701 error
= _("illegal operands");
2702 insn_with_csr
= FALSE
;
2706 /* Restore the character we might have clobbered above. */
2708 *(argsStart
- 1) = save_c
;
2714 md_assemble (char *str
)
2716 struct riscv_cl_insn insn
;
2717 expressionS imm_expr
;
2718 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2720 /* The architecture and privileged elf attributes should be set
2721 before assembling. */
2722 if (!start_assemble
)
2724 start_assemble
= TRUE
;
2726 riscv_set_abi_by_arch ();
2727 if (!riscv_set_default_priv_spec (NULL
))
2731 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2735 as_bad ("%s `%s'", error
, str
);
2739 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2740 macro (&insn
, &imm_expr
, &imm_reloc
);
2742 append_insn (&insn
, &imm_expr
, imm_reloc
);
2746 md_atof (int type
, char *litP
, int *sizeP
)
2748 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2752 md_number_to_chars (char *buf
, valueT val
, int n
)
2754 if (target_big_endian
)
2755 number_to_chars_bigendian (buf
, val
, n
);
2757 number_to_chars_littleendian (buf
, val
, n
);
2760 const char *md_shortopts
= "O::g::G:";
2764 OPTION_MARCH
= OPTION_MD_BASE
,
2771 OPTION_NO_ARCH_ATTR
,
2773 OPTION_NO_CSR_CHECK
,
2777 OPTION_LITTLE_ENDIAN
,
2781 struct option md_longopts
[] =
2783 {"march", required_argument
, NULL
, OPTION_MARCH
},
2784 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2785 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2786 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2787 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2788 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2789 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2790 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2791 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2792 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2793 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2794 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2795 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2796 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2797 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2799 {NULL
, no_argument
, NULL
, 0}
2801 size_t md_longopts_size
= sizeof (md_longopts
);
2804 md_parse_option (int c
, const char *arg
)
2809 default_arch_with_ext
= arg
;
2813 riscv_opts
.pic
= FALSE
;
2817 riscv_opts
.pic
= TRUE
;
2821 if (strcmp (arg
, "ilp32") == 0)
2822 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2823 else if (strcmp (arg
, "ilp32e") == 0)
2824 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2825 else if (strcmp (arg
, "ilp32f") == 0)
2826 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2827 else if (strcmp (arg
, "ilp32d") == 0)
2828 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2829 else if (strcmp (arg
, "ilp32q") == 0)
2830 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2831 else if (strcmp (arg
, "lp64") == 0)
2832 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2833 else if (strcmp (arg
, "lp64f") == 0)
2834 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2835 else if (strcmp (arg
, "lp64d") == 0)
2836 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2837 else if (strcmp (arg
, "lp64q") == 0)
2838 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2841 explicit_mabi
= TRUE
;
2845 riscv_opts
.relax
= TRUE
;
2848 case OPTION_NO_RELAX
:
2849 riscv_opts
.relax
= FALSE
;
2852 case OPTION_ARCH_ATTR
:
2853 riscv_opts
.arch_attr
= TRUE
;
2856 case OPTION_NO_ARCH_ATTR
:
2857 riscv_opts
.arch_attr
= FALSE
;
2860 case OPTION_CSR_CHECK
:
2861 riscv_opts
.csr_check
= TRUE
;
2864 case OPTION_NO_CSR_CHECK
:
2865 riscv_opts
.csr_check
= FALSE
;
2868 case OPTION_MISA_SPEC
:
2869 return riscv_set_default_isa_spec (arg
);
2871 case OPTION_MPRIV_SPEC
:
2872 return riscv_set_default_priv_spec (arg
);
2874 case OPTION_BIG_ENDIAN
:
2875 target_big_endian
= 1;
2878 case OPTION_LITTLE_ENDIAN
:
2879 target_big_endian
= 0;
2890 riscv_after_parse_args (void)
2892 /* The --with-arch is optional for now, so we still need to set the xlen
2893 according to the default_arch, which is set by the --target. */
2896 if (strcmp (default_arch
, "riscv32") == 0)
2898 else if (strcmp (default_arch
, "riscv64") == 0)
2901 as_bad ("unknown default architecture `%s'", default_arch
);
2903 if (default_arch_with_ext
== NULL
)
2904 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2906 /* Initialize the hash table for extensions with default version. */
2907 ext_version_hash
= init_ext_version_hash ();
2909 /* Set default specs. */
2910 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2911 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2912 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2913 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2915 riscv_set_arch (default_arch_with_ext
);
2917 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2918 riscv_set_rvc (FALSE
);
2919 if (riscv_subset_supports ("c"))
2920 riscv_set_rvc (TRUE
);
2922 /* Enable RVE if specified by the -march option. */
2923 riscv_set_rve (FALSE
);
2924 if (riscv_subset_supports ("e"))
2925 riscv_set_rve (TRUE
);
2927 /* If the CIE to be produced has not been overridden on the command line,
2928 then produce version 3 by default. This allows us to use the full
2929 range of registers in a .cfi_return_column directive. */
2930 if (flag_dwarf_cie_version
== -1)
2931 flag_dwarf_cie_version
= 3;
2935 md_pcrel_from (fixS
*fixP
)
2937 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2940 /* Apply a fixup to the object file. */
2943 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2945 unsigned int subtype
;
2946 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2947 bfd_boolean relaxable
= FALSE
;
2951 /* Remember value for tc_gen_reloc. */
2952 fixP
->fx_addnumber
= *valP
;
2954 switch (fixP
->fx_r_type
)
2956 case BFD_RELOC_RISCV_HI20
:
2957 case BFD_RELOC_RISCV_LO12_I
:
2958 case BFD_RELOC_RISCV_LO12_S
:
2959 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2960 | bfd_getl32 (buf
), buf
);
2961 if (fixP
->fx_addsy
== NULL
)
2962 fixP
->fx_done
= TRUE
;
2966 case BFD_RELOC_RISCV_GOT_HI20
:
2967 case BFD_RELOC_RISCV_ADD8
:
2968 case BFD_RELOC_RISCV_ADD16
:
2969 case BFD_RELOC_RISCV_ADD32
:
2970 case BFD_RELOC_RISCV_ADD64
:
2971 case BFD_RELOC_RISCV_SUB6
:
2972 case BFD_RELOC_RISCV_SUB8
:
2973 case BFD_RELOC_RISCV_SUB16
:
2974 case BFD_RELOC_RISCV_SUB32
:
2975 case BFD_RELOC_RISCV_SUB64
:
2976 case BFD_RELOC_RISCV_RELAX
:
2979 case BFD_RELOC_RISCV_TPREL_HI20
:
2980 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2981 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2982 case BFD_RELOC_RISCV_TPREL_ADD
:
2986 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2987 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2988 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2989 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2990 if (fixP
->fx_addsy
!= NULL
)
2991 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2994 _("TLS relocation against a constant"));
2998 /* Use pc-relative relocation for FDE initial location.
2999 The symbol address in .eh_frame may be adjusted in
3000 _bfd_elf_discard_section_eh_frame, and the content of
3001 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3002 Therefore, we cannot insert a relocation whose addend symbol is
3003 in .eh_frame. Othrewise, the value may be adjusted twice. */
3004 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3005 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3006 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3007 && S_GET_VALUE (fixP
->fx_subsy
)
3008 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3010 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3011 fixP
->fx_subsy
= NULL
;
3018 case BFD_RELOC_RISCV_CFA
:
3019 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3021 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3022 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3023 fixP
->fx_next
->fx_subsy
= NULL
;
3024 fixP
->fx_next
->fx_offset
= 0;
3025 fixP
->fx_subsy
= NULL
;
3027 switch (fixP
->fx_r_type
)
3030 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3031 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3035 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3036 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3040 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3041 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3045 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3046 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3049 case BFD_RELOC_RISCV_CFA
:
3050 /* Load the byte to get the subtype. */
3051 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3052 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3055 case DW_CFA_advance_loc1
:
3056 fixP
->fx_where
= loc
+ 1;
3057 fixP
->fx_next
->fx_where
= loc
+ 1;
3058 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3059 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3062 case DW_CFA_advance_loc2
:
3064 fixP
->fx_next
->fx_size
= 2;
3065 fixP
->fx_where
= loc
+ 1;
3066 fixP
->fx_next
->fx_where
= loc
+ 1;
3067 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3068 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3071 case DW_CFA_advance_loc4
:
3073 fixP
->fx_next
->fx_size
= 4;
3074 fixP
->fx_where
= loc
;
3075 fixP
->fx_next
->fx_where
= loc
;
3076 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3077 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3081 if (subtype
< 0x80 && (subtype
& 0x40))
3083 /* DW_CFA_advance_loc */
3084 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3085 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3086 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3087 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3090 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3096 /* This case is unreachable. */
3103 /* If we are deleting this reloc entry, we must fill in the
3104 value now. This can happen if we have a .word which is not
3105 resolved when it appears but is later defined. */
3106 if (fixP
->fx_addsy
== NULL
)
3108 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3109 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3114 case BFD_RELOC_RISCV_JMP
:
3117 /* Fill in a tentative value to improve objdump readability. */
3118 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3119 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3120 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3124 case BFD_RELOC_12_PCREL
:
3127 /* Fill in a tentative value to improve objdump readability. */
3128 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3129 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3130 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3134 case BFD_RELOC_RISCV_RVC_BRANCH
:
3137 /* Fill in a tentative value to improve objdump readability. */
3138 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3139 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3140 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3144 case BFD_RELOC_RISCV_RVC_JUMP
:
3147 /* Fill in a tentative value to improve objdump readability. */
3148 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3149 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3150 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3154 case BFD_RELOC_RISCV_CALL
:
3155 case BFD_RELOC_RISCV_CALL_PLT
:
3159 case BFD_RELOC_RISCV_PCREL_HI20
:
3160 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3161 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3162 relaxable
= riscv_opts
.relax
;
3165 case BFD_RELOC_RISCV_ALIGN
:
3169 /* We ignore generic BFD relocations we don't know about. */
3170 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3171 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3174 if (fixP
->fx_subsy
!= NULL
)
3175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3176 _("unsupported symbol subtraction"));
3178 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3179 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3181 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3182 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3183 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3184 fixP
->fx_next
->fx_size
= 0;
3188 /* Because the value of .cfi_remember_state may changed after relaxation,
3189 we insert a fix to relocate it again in link-time. */
3192 riscv_pre_output_hook (void)
3194 const frchainS
*frch
;
3197 /* Save the current segment info. */
3199 subsegT subseg
= now_subseg
;
3201 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3202 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3206 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3208 if (frag
->fr_type
== rs_cfa
)
3211 expressionS
*symval
;
3213 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3214 exp
.X_op
= O_subtract
;
3215 exp
.X_add_symbol
= symval
->X_add_symbol
;
3216 exp
.X_add_number
= 0;
3217 exp
.X_op_symbol
= symval
->X_op_symbol
;
3219 /* We must set the segment before creating a frag after all
3220 frag chains have been chained together. */
3221 subseg_set (s
, frch
->frch_subseg
);
3223 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3224 BFD_RELOC_RISCV_CFA
);
3229 /* Restore the original segment info. */
3230 subseg_set (seg
, subseg
);
3233 /* This structure is used to hold a stack of .option values. */
3234 struct riscv_option_stack
3236 struct riscv_option_stack
*next
;
3237 struct riscv_set_options options
;
3240 static struct riscv_option_stack
*riscv_opts_stack
;
3242 /* Handle the .option pseudo-op. */
3245 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3247 char *name
= input_line_pointer
, ch
;
3249 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3250 ++input_line_pointer
;
3251 ch
= *input_line_pointer
;
3252 *input_line_pointer
= '\0';
3254 if (strcmp (name
, "rvc") == 0)
3255 riscv_set_rvc (TRUE
);
3256 else if (strcmp (name
, "norvc") == 0)
3257 riscv_set_rvc (FALSE
);
3258 else if (strcmp (name
, "pic") == 0)
3259 riscv_opts
.pic
= TRUE
;
3260 else if (strcmp (name
, "nopic") == 0)
3261 riscv_opts
.pic
= FALSE
;
3262 else if (strcmp (name
, "relax") == 0)
3263 riscv_opts
.relax
= TRUE
;
3264 else if (strcmp (name
, "norelax") == 0)
3265 riscv_opts
.relax
= FALSE
;
3266 else if (strcmp (name
, "csr-check") == 0)
3267 riscv_opts
.csr_check
= TRUE
;
3268 else if (strcmp (name
, "no-csr-check") == 0)
3269 riscv_opts
.csr_check
= FALSE
;
3270 else if (strcmp (name
, "push") == 0)
3272 struct riscv_option_stack
*s
;
3274 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3275 s
->next
= riscv_opts_stack
;
3276 s
->options
= riscv_opts
;
3277 riscv_opts_stack
= s
;
3279 else if (strcmp (name
, "pop") == 0)
3281 struct riscv_option_stack
*s
;
3283 s
= riscv_opts_stack
;
3285 as_bad (_(".option pop with no .option push"));
3288 riscv_opts
= s
->options
;
3289 riscv_opts_stack
= s
->next
;
3295 as_warn (_("unrecognized .option directive: %s\n"), name
);
3297 *input_line_pointer
= ch
;
3298 demand_empty_rest_of_line ();
3301 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3302 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3303 use in DWARF debug information. */
3306 s_dtprel (int bytes
)
3313 if (ex
.X_op
!= O_symbol
)
3315 as_bad (_("unsupported use of %s"), (bytes
== 8
3318 ignore_rest_of_line ();
3321 p
= frag_more (bytes
);
3322 md_number_to_chars (p
, 0, bytes
);
3323 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3325 ? BFD_RELOC_RISCV_TLS_DTPREL64
3326 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3328 demand_empty_rest_of_line ();
3331 /* Handle the .bss pseudo-op. */
3334 s_bss (int ignore ATTRIBUTE_UNUSED
)
3336 subseg_set (bss_section
, 0);
3337 demand_empty_rest_of_line ();
3341 riscv_make_nops (char *buf
, bfd_vma bytes
)
3345 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3346 means we are not within a valid instruction sequence. It is thus safe
3347 to use a zero byte, even though that is not a valid instruction. */
3351 /* Use at most one 2-byte NOP. */
3352 if ((bytes
- i
) % 4 == 2)
3354 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3358 /* Fill the remainder with 4-byte NOPs. */
3359 for ( ; i
< bytes
; i
+= 4)
3360 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3363 /* Called from md_do_align. Used to create an alignment frag in a
3364 code section by emitting a worst-case NOP sequence that the linker
3365 will later relax to the correct number of NOPs. We can't compute
3366 the correct alignment now because of other linker relaxations. */
3369 riscv_frag_align_code (int n
)
3371 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3372 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3373 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3377 /* If we are moving to a smaller alignment than the instruction size, then no
3378 alignment is required. */
3379 if (bytes
<= insn_alignment
)
3382 /* When not relaxing, riscv_handle_align handles code alignment. */
3383 if (!riscv_opts
.relax
)
3386 nops
= frag_more (worst_case_bytes
);
3388 ex
.X_op
= O_constant
;
3389 ex
.X_add_number
= worst_case_bytes
;
3391 riscv_make_nops (nops
, worst_case_bytes
);
3393 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3394 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3399 /* Implement HANDLE_ALIGN. */
3402 riscv_handle_align (fragS
*fragP
)
3404 switch (fragP
->fr_type
)
3407 /* When relaxing, riscv_frag_align_code handles code alignment. */
3408 if (!riscv_opts
.relax
)
3410 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3411 - fragP
->fr_address
- fragP
->fr_fix
);
3412 /* We have 4 byte uncompressed nops. */
3413 bfd_signed_vma size
= 4;
3414 bfd_signed_vma excess
= bytes
% size
;
3415 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3420 /* Insert zeros or compressed nops to get 4 byte alignment. */
3423 riscv_make_nops (p
, excess
);
3424 fragP
->fr_fix
+= excess
;
3428 /* Insert variable number of 4 byte uncompressed nops. */
3429 riscv_make_nops (p
, size
);
3430 fragP
->fr_var
= size
;
3440 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3442 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3445 /* Translate internal representation of relocation info to BFD target
3449 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3451 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3453 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3454 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3455 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3456 reloc
->addend
= fixp
->fx_addnumber
;
3458 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3459 if (reloc
->howto
== NULL
)
3461 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3462 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3464 /* We don't have R_RISCV_8/16, but for this special case,
3465 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3469 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3470 _("cannot represent %s relocation in object file"),
3471 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3479 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3481 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3483 offsetT old_var
= fragp
->fr_var
;
3484 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3485 return fragp
->fr_var
- old_var
;
3491 /* Expand far branches to multi-instruction sequences. */
3494 md_convert_frag_branch (fragS
*fragp
)
3502 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3504 exp
.X_op
= O_symbol
;
3505 exp
.X_add_symbol
= fragp
->fr_symbol
;
3506 exp
.X_add_number
= fragp
->fr_offset
;
3508 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3510 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3512 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3516 /* Expand the RVC branch into a RISC-V one. */
3517 insn
= bfd_getl16 (buf
);
3518 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3519 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3521 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3522 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3523 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3524 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3525 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3526 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3529 bfd_putl32 (insn
, buf
);
3533 /* Invert the branch condition. Branch over the jump. */
3534 insn
= bfd_getl16 (buf
);
3535 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3536 insn
|= ENCODE_CBTYPE_IMM (6);
3537 bfd_putl16 (insn
, buf
);
3542 /* Just keep the RVC branch. */
3543 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3544 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3545 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3546 2, &exp
, FALSE
, reloc
);
3555 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3558 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3560 /* Invert the branch condition. Branch over the jump. */
3561 insn
= bfd_getl32 (buf
);
3562 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3563 insn
|= ENCODE_BTYPE_IMM (8);
3564 bfd_putl32 (insn
, buf
);
3568 /* Jump to the target. */
3569 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3570 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3571 bfd_putl32 (MATCH_JAL
, buf
);
3576 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3577 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3578 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3579 4, &exp
, FALSE
, reloc
);
3588 fixp
->fx_file
= fragp
->fr_file
;
3589 fixp
->fx_line
= fragp
->fr_line
;
3591 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3592 + fragp
->fr_fix
+ fragp
->fr_var
);
3594 fragp
->fr_fix
+= fragp
->fr_var
;
3597 /* Relax a machine dependent frag. This returns the amount by which
3598 the current size of the frag should change. */
3601 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3604 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3605 md_convert_frag_branch (fragp
);
3609 md_show_usage (FILE *stream
)
3611 fprintf (stream
, _("\
3613 -fpic generate position-independent code\n\
3614 -fno-pic don't generate position-independent code (default)\n\
3615 -march=ISA set the RISC-V architecture\n\
3616 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3617 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3618 -mabi=ABI set the RISC-V ABI\n\
3619 -mrelax enable relax (default)\n\
3620 -mno-relax disable relax\n\
3621 -march-attr generate RISC-V arch attribute\n\
3622 -mno-arch-attr don't generate RISC-V arch attribute\n\
3626 /* Standard calling conventions leave the CFA at SP on entry. */
3629 riscv_cfi_frame_initial_instructions (void)
3631 cfi_add_CFA_def_cfa_register (X_SP
);
3635 tc_riscv_regname_to_dw2regnum (char *regname
)
3639 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3642 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3645 /* CSRs are numbered 4096 -> 8191. */
3646 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3649 as_bad (_("unknown register `%s'"), regname
);
3654 riscv_elf_final_processing (void)
3656 riscv_set_abi_by_arch ();
3657 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3660 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3661 since these directives break relaxation when used with symbol deltas. */
3664 s_riscv_leb128 (int sign
)
3667 char *save_in
= input_line_pointer
;
3670 if (exp
.X_op
!= O_constant
)
3671 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3672 demand_empty_rest_of_line ();
3674 input_line_pointer
= save_in
;
3675 return s_leb128 (sign
);
3678 /* Parse the .insn directive. */
3681 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3683 char *str
= input_line_pointer
;
3684 struct riscv_cl_insn insn
;
3685 expressionS imm_expr
;
3686 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3689 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3690 ++input_line_pointer
;
3692 save_c
= *input_line_pointer
;
3693 *input_line_pointer
= '\0';
3695 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3696 &imm_reloc
, insn_type_hash
);
3700 as_bad ("%s `%s'", error
, str
);
3704 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3705 append_insn (&insn
, &imm_expr
, imm_reloc
);
3708 *input_line_pointer
= save_c
;
3709 demand_empty_rest_of_line ();
3712 /* Update architecture and privileged elf attributes. If we don't set
3713 them, then try to output the default ones. */
3716 riscv_write_out_attrs (void)
3718 const char *arch_str
, *priv_str
, *p
;
3719 /* versions[0]: major version.
3720 versions[1]: minor version.
3721 versions[2]: revision version. */
3722 unsigned versions
[3] = {0}, number
= 0;
3725 /* Re-write architecture elf attribute. */
3726 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3727 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3728 xfree ((void *) arch_str
);
3730 /* For the file without any instruction, we don't set the default_priv_spec
3731 according to the privileged elf attributes since the md_assemble isn't
3734 && !riscv_set_default_priv_spec (NULL
))
3737 /* If we already have set privileged elf attributes, then no need to do
3738 anything. Otherwise, don't generate or update them when no CSR and
3739 privileged instructions are used. */
3740 if (!explicit_priv_attr
)
3743 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
3745 for (i
= 0; *p
; ++p
)
3747 if (*p
== '.' && i
< 3)
3749 versions
[i
++] = number
;
3752 else if (ISDIGIT (*p
))
3753 number
= (number
* 10) + (*p
- '0');
3756 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3760 versions
[i
] = number
;
3762 /* Re-write privileged elf attributes. */
3763 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3764 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3765 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3768 /* Add the default contents for the .riscv.attributes section. */
3771 riscv_set_public_attributes (void)
3773 if (riscv_opts
.arch_attr
|| explicit_attr
)
3774 riscv_write_out_attrs ();
3777 /* Called after all assembly has been done. */
3782 riscv_set_public_attributes ();
3785 /* Given a symbolic attribute NAME, return the proper integer value.
3786 Returns -1 if the attribute is not known. */
3789 riscv_convert_symbolic_attribute (const char *name
)
3798 /* When you modify this table you should
3799 also modify the list in doc/c-riscv.texi. */
3800 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3804 T(priv_spec_revision
),
3805 T(unaligned_access
),
3814 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3815 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3816 return attribute_table
[i
].tag
;
3821 /* Parse a .attribute directive. */
3824 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3826 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3828 obj_attribute
*attr
;
3830 explicit_attr
= TRUE
;
3833 case Tag_RISCV_arch
:
3835 attr
= elf_known_obj_attributes_proc (stdoutput
);
3836 if (!start_assemble
)
3837 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3839 as_fatal (_("architecture elf attributes must set before "
3840 "any instructions"));
3842 if (old_xlen
!= xlen
)
3844 /* We must re-init bfd again if xlen is changed. */
3845 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3846 bfd_find_target (riscv_target_format (), stdoutput
);
3848 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3849 as_warn (_("could not set architecture and machine"));
3853 case Tag_RISCV_priv_spec
:
3854 case Tag_RISCV_priv_spec_minor
:
3855 case Tag_RISCV_priv_spec_revision
:
3857 as_fatal (_("privileged elf attributes must set before "
3858 "any instructions"));
3866 /* RISC-V pseudo-ops table. */
3867 static const pseudo_typeS riscv_pseudo_table
[] =
3869 {"option", s_riscv_option
, 0},
3873 {"dtprelword", s_dtprel
, 4},
3874 {"dtpreldword", s_dtprel
, 8},
3876 {"uleb128", s_riscv_leb128
, 0},
3877 {"sleb128", s_riscv_leb128
, 1},
3878 {"insn", s_riscv_insn
, 0},
3879 {"attribute", s_riscv_attribute
, 0},
3885 riscv_pop_insert (void)
3887 extern void pop_insert (const pseudo_typeS
*);
3889 pop_insert (riscv_pseudo_table
);