1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
132 /* Find the corresponding priv spec class. */
133 if (riscv_get_priv_spec_class (s
, &class))
135 default_priv_spec
= class;
141 as_bad (_("Unknown default privilege spec `%s' set by "
142 "-mpriv-spec or --with-priv-spec"), s
);
146 /* Try to set the default_priv_spec according to the priv attributes. */
147 attr
= elf_known_obj_attributes_proc (stdoutput
);
148 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
149 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
150 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
152 /* The priv attributes setting 0.0.0 is meaningless. We should have set
153 the default_priv_spec by md_parse_option and riscv_after_parse_args,
154 so just skip the following setting. */
155 if (major
== 0 && minor
== 0 && revision
== 0)
158 buf_size
= riscv_estimate_digit (major
)
160 + riscv_estimate_digit (minor
)
161 + 1; /* string terminator */
164 buf_size
+= 1 /* '.' */
165 + riscv_estimate_digit (revision
);
166 buf
= xmalloc (buf_size
);
167 snprintf (buf
, buf_size
, "%d.%d.%d", major
, minor
, revision
);
171 buf
= xmalloc (buf_size
);
172 snprintf (buf
, buf_size
, "%d.%d", major
, minor
);
175 if (riscv_get_priv_spec_class (buf
, &class))
177 default_priv_spec
= class;
182 /* Still can not find the priv spec class. */
183 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
184 "privilege attributes"), major
, minor
, revision
);
189 /* This is the set of options which the .option pseudo-op may modify. */
191 struct riscv_set_options
193 int pic
; /* Generate position-independent code. */
194 int rvc
; /* Generate RVC code. */
195 int rve
; /* Generate RVE code. */
196 int relax
; /* Emit relocs the linker is allowed to relax. */
197 int arch_attr
; /* Emit arch attribute. */
198 int csr_check
; /* Enable the CSR checking. */
201 static struct riscv_set_options riscv_opts
=
207 DEFAULT_RISCV_ATTR
, /* arch_attr */
212 riscv_set_rvc (bfd_boolean rvc_value
)
215 elf_flags
|= EF_RISCV_RVC
;
217 riscv_opts
.rvc
= rvc_value
;
221 riscv_set_rve (bfd_boolean rve_value
)
223 riscv_opts
.rve
= rve_value
;
226 static riscv_subset_list_t riscv_subsets
;
229 riscv_subset_supports (const char *feature
)
231 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
234 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
238 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
242 case INSN_CLASS_I
: return riscv_subset_supports ("i");
243 case INSN_CLASS_C
: return riscv_subset_supports ("c");
244 case INSN_CLASS_A
: return riscv_subset_supports ("a");
245 case INSN_CLASS_M
: return riscv_subset_supports ("m");
246 case INSN_CLASS_F
: return riscv_subset_supports ("f");
247 case INSN_CLASS_D
: return riscv_subset_supports ("d");
248 case INSN_CLASS_D_AND_C
:
249 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
251 case INSN_CLASS_F_AND_C
:
252 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
254 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
257 as_fatal ("Unreachable");
262 /* Handle of the extension with version hash table. */
263 static struct hash_control
*ext_version_hash
= NULL
;
265 static struct hash_control
*
266 init_ext_version_hash (const struct riscv_ext_version
*table
)
269 struct hash_control
*hash
= hash_new ();
271 while (table
[i
].name
)
273 const char *name
= table
[i
].name
;
274 const char *hash_error
=
275 hash_insert (hash
, name
, (void *) &table
[i
]);
277 if (hash_error
!= NULL
)
279 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
280 table
[i
].name
, hash_error
);
281 /* Probably a memory allocation problem? Give up now. */
282 as_fatal (_("Broken assembler. No assembly attempted."));
288 && strcmp (table
[i
].name
, name
) == 0)
296 riscv_get_default_ext_version (const char *name
,
297 unsigned int *major_version
,
298 unsigned int *minor_version
)
300 struct riscv_ext_version
*ext
;
305 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
308 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
311 && strcmp (ext
->name
, name
) == 0)
313 if (ext
->isa_spec_class
== default_isa_spec
)
315 *major_version
= ext
->major_version
;
316 *minor_version
= ext
->minor_version
;
323 /* Set which ISA and extensions are available. */
326 riscv_set_arch (const char *s
)
328 riscv_parse_subset_t rps
;
329 rps
.subset_list
= &riscv_subsets
;
330 rps
.error_handler
= as_fatal
;
332 rps
.get_default_version
= riscv_get_default_ext_version
;
337 riscv_release_subset_list (&riscv_subsets
);
338 riscv_parse_subset (&rps
, s
);
341 /* Handle of the OPCODE hash table. */
342 static struct hash_control
*op_hash
= NULL
;
344 /* Handle of the type of .insn hash table. */
345 static struct hash_control
*insn_type_hash
= NULL
;
347 /* This array holds the chars that always start a comment. If the
348 pre-processor is disabled, these aren't very useful */
349 const char comment_chars
[] = "#";
351 /* This array holds the chars that only start a comment at the beginning of
352 a line. If the line seems to have the form '# 123 filename'
353 .line and .file directives will appear in the pre-processed output */
354 /* Note that input_file.c hand checks for '#' at the beginning of the
355 first line of the input file. This is because the compiler outputs
356 #NO_APP at the beginning of its output. */
357 /* Also note that C style comments are always supported. */
358 const char line_comment_chars
[] = "#";
360 /* This array holds machine specific line separator characters. */
361 const char line_separator_chars
[] = ";";
363 /* Chars that can be used to separate mant from exp in floating point nums */
364 const char EXP_CHARS
[] = "eE";
366 /* Chars that mean this number is a floating point constant */
369 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
371 /* Indicate we are already assemble any instructions or not. */
372 static bfd_boolean start_assemble
= FALSE
;
374 /* Indicate ELF attributes are explictly set. */
375 static bfd_boolean explicit_attr
= FALSE
;
377 /* Macros for encoding relaxation state for RVC branches and far jumps. */
378 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
381 | ((uncond) ? 1 : 0) \
384 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
385 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
386 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
387 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
389 /* Is the given value a sign-extended 32-bit value? */
390 #define IS_SEXT_32BIT_NUM(x) \
391 (((x) &~ (offsetT) 0x7fffffff) == 0 \
392 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
394 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
395 #define IS_ZEXT_32BIT_NUM(x) \
396 (((x) &~ (offsetT) 0xffffffff) == 0 \
397 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
399 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
400 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
401 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
402 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
404 /* Determine if an instruction matches an opcode. */
405 #define OPCODE_MATCHES(OPCODE, OP) \
406 (((OPCODE) & MASK_##OP) == MATCH_##OP)
408 static char *expr_end
;
410 /* The default target format to use. */
413 riscv_target_format (void)
415 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
418 /* Return the length of instruction INSN. */
420 static inline unsigned int
421 insn_length (const struct riscv_cl_insn
*insn
)
423 return riscv_insn_length (insn
->insn_opcode
);
426 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
429 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
432 insn
->insn_opcode
= mo
->match
;
438 /* Install INSN at the location specified by its "frag" and "where" fields. */
441 install_insn (const struct riscv_cl_insn
*insn
)
443 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
444 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
447 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
448 and install the opcode in the new location. */
451 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
455 if (insn
->fixp
!= NULL
)
457 insn
->fixp
->fx_frag
= frag
;
458 insn
->fixp
->fx_where
= where
;
463 /* Add INSN to the end of the output. */
466 add_fixed_insn (struct riscv_cl_insn
*insn
)
468 char *f
= frag_more (insn_length (insn
));
469 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
473 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
474 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
476 frag_grow (max_chars
);
477 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
478 frag_var (rs_machine_dependent
, max_chars
, var
,
479 subtype
, symbol
, offset
, NULL
);
482 /* Compute the length of a branch sequence, and adjust the stored length
483 accordingly. If FRAGP is NULL, the worst-case length is returned. */
486 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
488 int jump
, rvc
, length
= 8;
493 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
494 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
495 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
497 /* Assume jumps are in range; the linker will catch any that aren't. */
498 length
= jump
? 4 : 8;
500 if (fragp
->fr_symbol
!= NULL
501 && S_IS_DEFINED (fragp
->fr_symbol
)
502 && !S_IS_WEAK (fragp
->fr_symbol
)
503 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
505 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
506 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
507 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
509 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
511 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
513 else if (!jump
&& rvc
)
518 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
523 /* Information about an opcode name, mnemonics and its value. */
530 /* List for all supported opcode name. */
531 static const struct opcode_name_t opcode_name_list
[] =
576 /* Hash table for lookup opcode name. */
577 static struct hash_control
*opcode_names_hash
= NULL
;
579 /* Initialization for hash table of opcode name. */
581 init_opcode_names_hash (void)
584 const struct opcode_name_t
*opcode
;
586 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
588 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
591 as_fatal (_("internal error: can't hash `%s': %s"),
592 opcode
->name
, retval
);
596 /* Find `s` is a valid opcode name or not,
597 return the opcode name info if found. */
598 static const struct opcode_name_t
*
599 opcode_name_lookup (char **s
)
603 struct opcode_name_t
*o
;
605 /* Find end of name. */
607 if (is_name_beginner (*e
))
609 while (is_part_of_name (*e
))
612 /* Terminate name. */
616 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
618 /* Advance to next token if one was recognized. */
637 static struct hash_control
*reg_names_hash
= NULL
;
638 static struct hash_control
*csr_extra_hash
= NULL
;
640 #define ENCODE_REG_HASH(cls, n) \
641 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
642 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
643 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
646 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
648 void *hash
= ENCODE_REG_HASH (class, n
);
649 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
652 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
656 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
660 for (i
= 0; i
< n
; i
++)
661 hash_reg_name (class, names
[i
], i
);
664 /* Init hash table csr_extra_hash to handle CSR. */
666 riscv_init_csr_hash (const char *name
,
668 enum riscv_csr_class
class,
669 enum riscv_priv_spec_class define_version
,
670 enum riscv_priv_spec_class abort_version
)
672 struct riscv_csr_extra
*entry
, *pre_entry
;
673 const char *hash_error
= NULL
;
674 bfd_boolean need_enrty
= TRUE
;
677 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
678 while (need_enrty
&& entry
!= NULL
)
680 if (entry
->csr_class
== class
681 && entry
->address
== address
682 && entry
->define_version
== define_version
683 && entry
->abort_version
== abort_version
)
689 /* Duplicate setting for the CSR, just return and do nothing. */
693 entry
= XNEW (struct riscv_csr_extra
);
694 entry
->csr_class
= class;
695 entry
->address
= address
;
696 entry
->define_version
= define_version
;
697 entry
->abort_version
= abort_version
;
700 /* If the CSR hasn't been inserted in the hash table, then insert it.
701 Otherwise, attach the extra information to the entry which is already
702 in the hash table. */
703 if (pre_entry
== NULL
)
705 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
706 if (hash_error
!= NULL
)
708 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
710 /* Probably a memory allocation problem? Give up now. */
711 as_fatal (_("Broken assembler. No assembly attempted."));
715 pre_entry
->next
= entry
;
718 /* Check wether the CSR is valid according to the ISA. */
721 riscv_csr_class_check (const char *s
,
722 enum riscv_csr_class csr_class
)
724 bfd_boolean result
= TRUE
;
726 /* Don't check the ISA dependency when -mcsr-check isn't set. */
727 if (!riscv_opts
.csr_check
)
733 result
= riscv_subset_supports ("i");
736 result
= riscv_subset_supports ("f");
739 result
= (xlen
== 32 && riscv_subset_supports ("i"));
742 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
746 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
749 /* Check and find the CSR address according to the privilege spec version. */
752 riscv_csr_version_check (const char *csr_name
,
753 struct riscv_csr_extra
**entryP
)
755 struct riscv_csr_extra
*entry
= *entryP
;
757 while (entry
!= NULL
)
759 if (default_priv_spec
>= entry
->define_version
760 && default_priv_spec
< entry
->abort_version
)
762 /* Find the suitable CSR according to the specific version. */
769 /* We can not find the suitable CSR address according to the privilege
770 version. Therefore, we use the last defined value. Report the warning
771 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
772 otherwise, you may get the unexpected CSR address. */
773 if (riscv_opts
.csr_check
)
775 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
777 if (priv_name
!= NULL
)
778 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
779 csr_name
, priv_name
);
783 /* Once the CSR is defined, including the old privilege spec, then we call
784 riscv_csr_class_check and riscv_csr_version_check to do the further checking
785 and get the corresponding address. Return -1 if the CSR is never been
786 defined. Otherwise, return the address. */
789 reg_csr_lookup_internal (const char *s
)
791 struct riscv_csr_extra
*r
=
792 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
797 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
798 the CSR was defined, but isn't allowed for the current ISA setting or
799 the privilege spec. If the CSR is never been defined, then assembler
800 will regard it as a "Unknown CSR" and report error. If user use number
801 to set the CSR, but over the range (> 0xfff), then assembler will report
802 "Improper CSR" error for it. */
803 riscv_csr_class_check (s
, r
->csr_class
);
804 riscv_csr_version_check (s
, &r
);
810 reg_lookup_internal (const char *s
, enum reg_class
class)
814 if (class == RCLASS_CSR
)
815 return reg_csr_lookup_internal (s
);
817 r
= hash_find (reg_names_hash
, s
);
818 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
821 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
824 return DECODE_REG_NUM (r
);
828 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
834 /* Find end of name. */
836 if (is_name_beginner (*e
))
838 while (is_part_of_name (*e
))
841 /* Terminate name. */
845 /* Look for the register. Advance to next token if one was recognized. */
846 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
856 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
858 const char *p
= strchr (*s
, ',');
859 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
864 for (i
= 0; i
< size
; i
++)
865 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
875 /* For consistency checking, verify that all bits are specified either
876 by the match/mask part of the instruction definition, or by the
879 `length` could be 0, 4 or 8, 0 for auto detection. */
881 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
883 const char *p
= opc
->args
;
885 insn_t used_bits
= opc
->mask
;
887 insn_t required_bits
;
890 insn_width
= 8 * riscv_insn_length (opc
->match
);
892 insn_width
= 8 * length
;
894 required_bits
= ~0ULL >> (64 - insn_width
);
896 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
898 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
899 opc
->name
, opc
->args
);
903 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
910 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
911 case 'c': break; /* RS1, constrained to equal sp */
912 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
913 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
914 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
915 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
916 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
917 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
918 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
919 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
920 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
921 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
922 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
923 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
924 case 'w': break; /* RS1S, constrained to equal RD */
925 case 'x': break; /* RS2S, constrained to equal RD */
926 case 'z': break; /* RS2S, contrained to be x0 */
927 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
928 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
929 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
930 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
931 case 'U': break; /* RS1, constrained to equal RD */
932 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
933 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
934 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
935 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
936 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
937 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
938 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
939 case 'F': /* funct */
942 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
943 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
944 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
945 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
947 as_bad (_("internal: bad RISC-V opcode"
948 " (unknown operand type `CF%c'): %s %s"),
949 c
, opc
->name
, opc
->args
);
954 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
955 c
, opc
->name
, opc
->args
);
962 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
963 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
965 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
966 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
967 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
969 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
970 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
971 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
972 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
973 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
974 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
975 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
976 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
977 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
978 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
979 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
981 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
982 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
983 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
984 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
985 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
991 case 'F': /* funct */
994 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
995 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
996 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
998 as_bad (_("internal: bad RISC-V opcode"
999 " (unknown operand type `F%c'): %s %s"),
1000 c
, opc
->name
, opc
->args
);
1004 case 'O': /* opcode */
1007 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1008 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1010 as_bad (_("internal: bad RISC-V opcode"
1011 " (unknown operand type `F%c'): %s %s"),
1012 c
, opc
->name
, opc
->args
);
1017 as_bad (_("internal: bad RISC-V opcode "
1018 "(unknown operand type `%c'): %s %s"),
1019 c
, opc
->name
, opc
->args
);
1023 if (used_bits
!= required_bits
)
1025 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1026 ~(unsigned long)(used_bits
& required_bits
),
1027 opc
->name
, opc
->args
);
1033 struct percent_op_match
1036 bfd_reloc_code_real_type reloc
;
1039 /* Common hash table initialization function for
1040 instruction and .insn directive. */
1041 static struct hash_control
*
1042 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1043 bfd_boolean insn_directive_p
)
1047 struct hash_control
*hash
= hash_new ();
1048 while (opcodes
[i
].name
)
1050 const char *name
= opcodes
[i
].name
;
1051 const char *hash_error
=
1052 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1054 if (hash_error
!= NULL
)
1056 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1057 opcodes
[i
].name
, hash_error
);
1058 /* Probably a memory allocation problem? Give up now. */
1059 as_fatal (_("Broken assembler. No assembly attempted."));
1064 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1066 if (insn_directive_p
)
1067 length
= ((name
[0] == 'c') ? 2 : 4);
1069 length
= 0; /* Let assembler determine the length. */
1070 if (!validate_riscv_insn (&opcodes
[i
], length
))
1071 as_fatal (_("Broken assembler. No assembly attempted."));
1074 gas_assert (!insn_directive_p
);
1077 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1083 /* This function is called once, at assembler startup time. It should set up
1084 all the tables, etc. that the MD part of the assembler will need. */
1089 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1091 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1092 as_warn (_("Could not set architecture and machine"));
1094 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1095 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1097 reg_names_hash
= hash_new ();
1098 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1099 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1100 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1101 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1102 /* Add "fp" as an alias for "s0". */
1103 hash_reg_name (RCLASS_GPR
, "fp", 8);
1105 /* Create and insert CSR hash tables. */
1106 csr_extra_hash
= hash_new ();
1107 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1108 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1109 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1110 DECLARE_CSR(name, num, class, define_version, abort_version);
1111 #include "opcode/riscv-opc.h"
1114 opcode_names_hash
= hash_new ();
1115 init_opcode_names_hash ();
1117 /* Set the default alignment for the text section. */
1118 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1122 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1129 case BFD_RELOC_RISCV_HI20
:
1130 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1132 case BFD_RELOC_RISCV_LO12_S
:
1133 return ENCODE_STYPE_IMM (value
);
1135 case BFD_RELOC_RISCV_LO12_I
:
1136 return ENCODE_ITYPE_IMM (value
);
1143 /* Output an instruction. IP is the instruction information.
1144 ADDRESS_EXPR is an operand of the instruction to be used with
1148 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1149 bfd_reloc_code_real_type reloc_type
)
1151 dwarf2_emit_insn (0);
1153 if (reloc_type
!= BFD_RELOC_UNUSED
)
1155 reloc_howto_type
*howto
;
1157 gas_assert (address_expr
);
1158 if (reloc_type
== BFD_RELOC_12_PCREL
1159 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1161 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1162 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1163 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1164 add_relaxed_insn (ip
, worst_case
, best_case
,
1165 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1166 address_expr
->X_add_symbol
,
1167 address_expr
->X_add_number
);
1172 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1174 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1176 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1177 bfd_get_reloc_size (howto
),
1178 address_expr
, FALSE
, reloc_type
);
1180 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1184 add_fixed_insn (ip
);
1187 /* We need to start a new frag after any instruction that can be
1188 optimized away or compressed by the linker during relaxation, to prevent
1189 the assembler from computing static offsets across such an instruction.
1190 This is necessary to get correct EH info. */
1191 if (reloc_type
== BFD_RELOC_RISCV_CALL
1192 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1193 || reloc_type
== BFD_RELOC_RISCV_HI20
1194 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1195 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1196 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1198 frag_wane (frag_now
);
1203 /* Build an instruction created by a macro expansion. This is passed
1204 a pointer to the count of instructions created so far, an
1205 expression, the name of the instruction to build, an operand format
1206 string, and corresponding arguments. */
1209 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1211 const struct riscv_opcode
*mo
;
1212 struct riscv_cl_insn insn
;
1213 bfd_reloc_code_real_type r
;
1216 va_start (args
, fmt
);
1218 r
= BFD_RELOC_UNUSED
;
1219 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1222 /* Find a non-RVC variant of the instruction. append_insn will compress
1224 while (riscv_insn_length (mo
->match
) < 4)
1226 gas_assert (strcmp (name
, mo
->name
) == 0);
1228 create_insn (&insn
, mo
);
1234 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1238 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1242 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1246 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1252 gas_assert (ep
!= NULL
);
1253 r
= va_arg (args
, int);
1261 as_fatal (_("internal error: invalid macro"));
1266 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1268 append_insn (&insn
, ep
, r
);
1271 /* Build an instruction created by a macro expansion. Like md_assemble but
1272 accept a printf-style format string and arguments. */
1275 md_assemblef (const char *format
, ...)
1281 va_start (ap
, format
);
1283 r
= vasprintf (&buf
, format
, ap
);
1286 as_fatal (_("internal error: vasprintf failed"));
1294 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1297 normalize_constant_expr (expressionS
*ex
)
1301 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1302 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1303 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1307 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1308 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1311 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1312 bfd_boolean maybe_csr
)
1314 if (ex
->X_op
== O_big
)
1315 as_bad (_("unsupported large constant"));
1316 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1317 as_bad (_("unknown CSR `%s'"),
1318 S_GET_NAME (ex
->X_add_symbol
));
1319 else if (ex
->X_op
!= O_constant
)
1320 as_bad (_("Instruction %s requires absolute expression"),
1322 normalize_constant_expr (ex
);
1326 make_internal_label (void)
1328 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1329 (valueT
) frag_now_fix (), frag_now
);
1332 /* Load an entry from the GOT. */
1334 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1335 const char *lo_insn
, const char *lo_pattern
,
1336 bfd_reloc_code_real_type hi_reloc
,
1337 bfd_reloc_code_real_type lo_reloc
)
1340 ep2
.X_op
= O_symbol
;
1341 ep2
.X_add_symbol
= make_internal_label ();
1342 ep2
.X_add_number
= 0;
1344 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1345 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1349 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1350 bfd_reloc_code_real_type hi_reloc
,
1351 bfd_reloc_code_real_type lo_reloc
)
1353 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1357 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1358 bfd_reloc_code_real_type hi_reloc
,
1359 bfd_reloc_code_real_type lo_reloc
)
1361 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1364 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1366 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1367 bfd_reloc_code_real_type reloc
)
1369 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1370 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1373 /* Load an integer constant into a register. */
1376 load_const (int reg
, expressionS
*ep
)
1378 int shift
= RISCV_IMM_BITS
;
1379 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1380 expressionS upper
= *ep
, lower
= *ep
;
1381 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1382 upper
.X_add_number
-= lower
.X_add_number
;
1384 if (ep
->X_op
!= O_constant
)
1386 as_bad (_("unsupported large constant"));
1390 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1392 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1393 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1396 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1397 load_const (reg
, &upper
);
1399 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1400 if (lower
.X_add_number
!= 0)
1401 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1402 lower
.X_add_number
);
1406 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1409 if (upper
.X_add_number
!= 0)
1411 /* Discard low part and zero-extend upper immediate. */
1412 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1414 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1418 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1419 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1420 lower
.X_add_number
);
1424 /* Expand RISC-V assembly macros into one or more instructions. */
1426 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1427 bfd_reloc_code_real_type
*imm_reloc
)
1429 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1430 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1431 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1432 int mask
= ip
->insn_mo
->mask
;
1437 load_const (rd
, imm_expr
);
1442 /* Load the address of a symbol into a register. */
1443 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1444 as_bad (_("offset too large"));
1446 if (imm_expr
->X_op
== O_constant
)
1447 load_const (rd
, imm_expr
);
1448 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1449 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1450 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1451 else /* Local PIC symbol, or any non-PIC symbol */
1452 pcrel_load (rd
, rd
, imm_expr
, "addi",
1453 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1457 pcrel_load (rd
, rd
, imm_expr
, "addi",
1458 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1462 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1463 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1467 pcrel_load (rd
, rd
, imm_expr
, "lb",
1468 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1472 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1473 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1477 pcrel_load (rd
, rd
, imm_expr
, "lh",
1478 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1482 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1483 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1487 pcrel_load (rd
, rd
, imm_expr
, "lw",
1488 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1492 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1493 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1497 pcrel_load (rd
, rd
, imm_expr
, "ld",
1498 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1502 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1503 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1507 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1508 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1512 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1513 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1517 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1518 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1522 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1523 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1527 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1528 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1532 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1533 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1537 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1538 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1542 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1546 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1551 static const struct percent_op_match percent_op_utype
[] =
1553 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1554 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1555 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1556 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1557 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1558 {"%hi", BFD_RELOC_RISCV_HI20
},
1562 static const struct percent_op_match percent_op_itype
[] =
1564 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1565 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1566 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1570 static const struct percent_op_match percent_op_stype
[] =
1572 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1573 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1574 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1578 static const struct percent_op_match percent_op_rtype
[] =
1580 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1584 static const struct percent_op_match percent_op_null
[] =
1589 /* Return true if *STR points to a relocation operator. When returning true,
1590 move *STR over the operator and store its relocation code in *RELOC.
1591 Leave both *STR and *RELOC alone when returning false. */
1594 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1595 const struct percent_op_match
*percent_op
)
1597 for ( ; percent_op
->str
; percent_op
++)
1598 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1600 int len
= strlen (percent_op
->str
);
1602 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1605 *str
+= strlen (percent_op
->str
);
1606 *reloc
= percent_op
->reloc
;
1608 /* Check whether the output BFD supports this relocation.
1609 If not, issue an error and fall back on something safe. */
1610 if (*reloc
!= BFD_RELOC_UNUSED
1611 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1613 as_bad ("relocation %s isn't supported by the current ABI",
1615 *reloc
= BFD_RELOC_UNUSED
;
1623 my_getExpression (expressionS
*ep
, char *str
)
1627 save_in
= input_line_pointer
;
1628 input_line_pointer
= str
;
1630 expr_end
= input_line_pointer
;
1631 input_line_pointer
= save_in
;
1634 /* Parse string STR as a 16-bit relocatable operand. Store the
1635 expression in *EP and the relocation, if any, in RELOC.
1636 Return the number of relocation operators used (0 or 1).
1638 On exit, EXPR_END points to the first character after the expression. */
1641 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1642 char *str
, const struct percent_op_match
*percent_op
)
1645 unsigned crux_depth
, str_depth
, regno
;
1648 /* First, check for integer registers. No callers can accept a reg, but
1649 we need to avoid accidentally creating a useless undefined symbol below,
1650 if this is an instruction pattern that can't match. A glibc build fails
1651 if this is removed. */
1652 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1654 ep
->X_op
= O_register
;
1655 ep
->X_add_number
= regno
;
1660 /* Search for the start of the main expression.
1661 End the loop with CRUX pointing to the start
1662 of the main expression and with CRUX_DEPTH containing the number
1663 of open brackets at that point. */
1670 crux_depth
= str_depth
;
1672 /* Skip over whitespace and brackets, keeping count of the number
1674 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1680 && parse_relocation (&str
, reloc
, percent_op
));
1682 my_getExpression (ep
, crux
);
1685 /* Match every open bracket. */
1686 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1691 as_bad ("unclosed '('");
1698 /* Parse opcode name, could be an mnemonics or number. */
1700 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1701 char *str
, const struct percent_op_match
*percent_op
)
1703 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1707 ep
->X_op
= O_constant
;
1708 ep
->X_add_number
= o
->val
;
1712 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1715 /* Detect and handle implicitly zero load-store offsets. For example,
1716 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1717 an implicit offset was detected. */
1720 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1722 /* Check whether there is only a single bracketed expression left.
1723 If so, it must be the base register and the constant must be zero. */
1724 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1726 ep
->X_op
= O_constant
;
1727 ep
->X_add_number
= 0;
1734 /* All RISC-V CSR instructions belong to one of these classes. */
1744 /* Return which CSR instruction is checking. */
1746 static enum csr_insn_type
1747 riscv_csr_insn_type (insn_t insn
)
1749 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1750 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1752 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1753 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1755 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1756 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1759 return INSN_NOT_CSR
;
1762 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1763 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1764 CSR address is 0x3. */
1767 riscv_csr_read_only_check (insn_t insn
)
1769 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1770 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1771 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1772 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1775 && (((csr_insn
== INSN_CSRRS
1776 || csr_insn
== INSN_CSRRC
)
1778 || csr_insn
== INSN_CSRRW
))
1784 /* This routine assembles an instruction into its binary format. As a
1785 side effect, it sets the global variable imm_reloc to the type of
1786 relocation to do if one of the operands is an address expression. */
1789 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1790 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1795 struct riscv_opcode
*insn
;
1800 const struct percent_op_match
*p
;
1801 const char *error
= "unrecognized opcode";
1802 /* Indicate we are assembling instruction with CSR. */
1803 bfd_boolean insn_with_csr
= FALSE
;
1805 /* Parse the name of the instruction. Terminate the string if whitespace
1806 is found so that hash_find only sees the name part of the string. */
1807 for (s
= str
; *s
!= '\0'; ++s
)
1815 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1818 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1820 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1823 if (!riscv_multi_subset_supports (insn
->insn_class
))
1826 create_insn (ip
, insn
);
1829 imm_expr
->X_op
= O_absent
;
1830 *imm_reloc
= BFD_RELOC_UNUSED
;
1831 p
= percent_op_itype
;
1833 for (args
= insn
->args
;; ++args
)
1835 s
+= strspn (s
, " \t");
1838 case '\0': /* End of args. */
1839 if (insn
->pinfo
!= INSN_MACRO
)
1841 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1844 /* For .insn, insn->match and insn->mask are 0. */
1845 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1851 /* Check if we write a read-only CSR by the CSR
1854 && riscv_opts
.csr_check
1855 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1857 /* Restore the character in advance, since we want to
1858 report the detailed warning message here. */
1860 *(argsStart
- 1) = save_c
;
1861 as_warn (_("Read-only CSR is written `%s'"), str
);
1862 insn_with_csr
= FALSE
;
1867 /* Successful assembly. */
1869 insn_with_csr
= FALSE
;
1875 case 's': /* RS1 x8-x15 */
1876 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1877 || !(regno
>= 8 && regno
<= 15))
1879 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1881 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1882 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1883 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1886 case 't': /* RS2 x8-x15 */
1887 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1888 || !(regno
>= 8 && regno
<= 15))
1890 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1892 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1893 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1894 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1897 case 'U': /* RS1, constrained to equal RD. */
1898 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1899 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1903 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1905 INSERT_OPERAND (CRS2
, *ip
, regno
);
1907 case 'c': /* RS1, constrained to equal sp. */
1908 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1912 case 'z': /* RS2, contrained to equal x0. */
1913 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1918 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1919 || imm_expr
->X_op
!= O_constant
1920 || imm_expr
->X_add_number
<= 0
1921 || imm_expr
->X_add_number
>= 64)
1923 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1926 imm_expr
->X_op
= O_absent
;
1929 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1930 || imm_expr
->X_op
!= O_constant
1931 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1932 || imm_expr
->X_add_number
<= 0
1933 || imm_expr
->X_add_number
>= 32)
1935 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1938 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1939 || imm_expr
->X_op
!= O_constant
1940 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1941 || imm_expr
->X_add_number
< 0
1942 || imm_expr
->X_add_number
>= 256)
1944 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1947 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1948 || imm_expr
->X_op
!= O_constant
1949 || imm_expr
->X_add_number
== 0
1950 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1952 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1955 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1956 || imm_expr
->X_op
!= O_constant
1957 || imm_expr
->X_add_number
== 0
1958 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1960 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1963 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1965 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1966 || imm_expr
->X_op
!= O_constant
1967 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1969 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1972 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1974 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1975 || imm_expr
->X_op
!= O_constant
1976 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1978 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1981 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1983 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1984 || imm_expr
->X_op
!= O_constant
1985 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1988 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1991 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1993 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1994 || imm_expr
->X_op
!= O_constant
1995 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1998 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2001 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2002 || imm_expr
->X_op
!= O_constant
2003 /* C.addiw, c.li, and c.andi allow zero immediate.
2004 C.addi allows zero immediate as hint. Otherwise this
2006 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
2008 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2011 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2012 || imm_expr
->X_op
!= O_constant
2013 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
2014 || imm_expr
->X_add_number
== 0)
2017 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2020 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2021 || imm_expr
->X_op
!= O_constant
2022 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2023 || imm_expr
->X_add_number
== 0)
2026 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2029 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2031 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2032 || imm_expr
->X_op
!= O_constant
2033 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2036 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2039 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2041 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2042 || imm_expr
->X_op
!= O_constant
2043 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2046 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2049 p
= percent_op_utype
;
2050 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2053 if (imm_expr
->X_op
!= O_constant
2054 || imm_expr
->X_add_number
<= 0
2055 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2056 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2057 && (imm_expr
->X_add_number
<
2058 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2060 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2063 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2064 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2065 || ((int32_t)imm_expr
->X_add_number
2066 != imm_expr
->X_add_number
))
2068 imm_expr
->X_add_number
=
2069 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2075 case 'S': /* Floating-point RS1 x8-x15. */
2076 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2077 || !(regno
>= 8 && regno
<= 15))
2079 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2081 case 'D': /* Floating-point RS2 x8-x15. */
2082 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2083 || !(regno
>= 8 && regno
<= 15))
2085 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2087 case 'T': /* Floating-point RS2. */
2088 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2090 INSERT_OPERAND (CRS2
, *ip
, regno
);
2096 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2097 || imm_expr
->X_op
!= O_constant
2098 || imm_expr
->X_add_number
< 0
2099 || imm_expr
->X_add_number
>= 64)
2101 as_bad (_("bad value for funct6 field, "
2102 "value must be 0...64"));
2106 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2107 imm_expr
->X_op
= O_absent
;
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || imm_expr
->X_add_number
< 0
2114 || imm_expr
->X_add_number
>= 16)
2116 as_bad (_("bad value for funct4 field, "
2117 "value must be 0...15"));
2121 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2122 imm_expr
->X_op
= O_absent
;
2126 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2127 || imm_expr
->X_op
!= O_constant
2128 || imm_expr
->X_add_number
< 0
2129 || imm_expr
->X_add_number
>= 8)
2131 as_bad (_("bad value for funct3 field, "
2132 "value must be 0...7"));
2135 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2136 imm_expr
->X_op
= O_absent
;
2140 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2141 || imm_expr
->X_op
!= O_constant
2142 || imm_expr
->X_add_number
< 0
2143 || imm_expr
->X_add_number
>= 4)
2145 as_bad (_("bad value for funct2 field, "
2146 "value must be 0...3"));
2149 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2150 imm_expr
->X_op
= O_absent
;
2154 as_bad (_("bad compressed FUNCT field"
2155 " specifier 'CF%c'\n"),
2161 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2180 case '<': /* Shift amount, 0 - 31. */
2181 my_getExpression (imm_expr
, s
);
2182 check_absolute_expr (ip
, imm_expr
, FALSE
);
2183 if ((unsigned long) imm_expr
->X_add_number
> 31)
2184 as_bad (_("Improper shift amount (%lu)"),
2185 (unsigned long) imm_expr
->X_add_number
);
2186 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2187 imm_expr
->X_op
= O_absent
;
2191 case '>': /* Shift amount, 0 - (XLEN-1). */
2192 my_getExpression (imm_expr
, s
);
2193 check_absolute_expr (ip
, imm_expr
, FALSE
);
2194 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2195 as_bad (_("Improper shift amount (%lu)"),
2196 (unsigned long) imm_expr
->X_add_number
);
2197 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2198 imm_expr
->X_op
= O_absent
;
2202 case 'Z': /* CSRRxI immediate. */
2203 my_getExpression (imm_expr
, s
);
2204 check_absolute_expr (ip
, imm_expr
, FALSE
);
2205 if ((unsigned long) imm_expr
->X_add_number
> 31)
2206 as_bad (_("Improper CSRxI immediate (%lu)"),
2207 (unsigned long) imm_expr
->X_add_number
);
2208 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2209 imm_expr
->X_op
= O_absent
;
2213 case 'E': /* Control register. */
2214 insn_with_csr
= TRUE
;
2215 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2216 INSERT_OPERAND (CSR
, *ip
, regno
);
2219 my_getExpression (imm_expr
, s
);
2220 check_absolute_expr (ip
, imm_expr
, TRUE
);
2221 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2222 as_bad (_("Improper CSR address (%lu)"),
2223 (unsigned long) imm_expr
->X_add_number
);
2224 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2225 imm_expr
->X_op
= O_absent
;
2230 case 'm': /* Rounding mode. */
2231 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2233 INSERT_OPERAND (RM
, *ip
, regno
);
2239 case 'Q': /* Fence predecessor/successor. */
2240 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2244 INSERT_OPERAND (PRED
, *ip
, regno
);
2246 INSERT_OPERAND (SUCC
, *ip
, regno
);
2251 case 'd': /* Destination register. */
2252 case 's': /* Source register. */
2253 case 't': /* Target register. */
2254 case 'r': /* rs3. */
2255 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2261 /* Now that we have assembled one operand, we use the args
2262 string to figure out where it goes in the instruction. */
2266 INSERT_OPERAND (RS1
, *ip
, regno
);
2269 INSERT_OPERAND (RD
, *ip
, regno
);
2272 INSERT_OPERAND (RS2
, *ip
, regno
);
2275 INSERT_OPERAND (RS3
, *ip
, regno
);
2282 case 'D': /* Floating point rd. */
2283 case 'S': /* Floating point rs1. */
2284 case 'T': /* Floating point rs2. */
2285 case 'U': /* Floating point rs1 and rs2. */
2286 case 'R': /* Floating point rs3. */
2287 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2295 INSERT_OPERAND (RD
, *ip
, regno
);
2298 INSERT_OPERAND (RS1
, *ip
, regno
);
2301 INSERT_OPERAND (RS1
, *ip
, regno
);
2304 INSERT_OPERAND (RS2
, *ip
, regno
);
2307 INSERT_OPERAND (RS3
, *ip
, regno
);
2316 my_getExpression (imm_expr
, s
);
2317 if (imm_expr
->X_op
!= O_big
2318 && imm_expr
->X_op
!= O_constant
)
2320 normalize_constant_expr (imm_expr
);
2325 my_getExpression (imm_expr
, s
);
2326 normalize_constant_expr (imm_expr
);
2327 /* The 'A' format specifier must be a symbol. */
2328 if (imm_expr
->X_op
!= O_symbol
)
2330 *imm_reloc
= BFD_RELOC_32
;
2335 my_getExpression (imm_expr
, s
);
2336 normalize_constant_expr (imm_expr
);
2337 /* The 'B' format specifier must be a symbol or a constant. */
2338 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2340 if (imm_expr
->X_op
== O_symbol
)
2341 *imm_reloc
= BFD_RELOC_32
;
2345 case 'j': /* Sign-extended immediate. */
2346 p
= percent_op_itype
;
2347 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2349 case 'q': /* Store displacement. */
2350 p
= percent_op_stype
;
2351 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2353 case 'o': /* Load displacement. */
2354 p
= percent_op_itype
;
2355 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2357 case '1': /* 4-operand add, must be %tprel_add. */
2358 p
= percent_op_rtype
;
2360 case '0': /* AMO "displacement," which must be zero. */
2361 p
= percent_op_null
;
2363 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2366 /* If this value won't fit into a 16 bit offset, then go
2367 find a macro that will generate the 32 bit offset
2369 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2371 normalize_constant_expr (imm_expr
);
2372 if (imm_expr
->X_op
!= O_constant
2373 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2375 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2376 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2383 case 'p': /* PC-relative offset. */
2385 *imm_reloc
= BFD_RELOC_12_PCREL
;
2386 my_getExpression (imm_expr
, s
);
2390 case 'u': /* Upper 20 bits. */
2391 p
= percent_op_utype
;
2392 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2394 if (imm_expr
->X_op
!= O_constant
)
2397 if (imm_expr
->X_add_number
< 0
2398 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2399 as_bad (_("lui expression not in range 0..1048575"));
2401 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2402 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2407 case 'a': /* 20-bit PC-relative offset. */
2409 my_getExpression (imm_expr
, s
);
2411 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2415 my_getExpression (imm_expr
, s
);
2417 if (strcmp (s
, "@plt") == 0)
2419 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2423 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2429 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2430 || imm_expr
->X_op
!= O_constant
2431 || imm_expr
->X_add_number
< 0
2432 || imm_expr
->X_add_number
>= 128
2433 || (imm_expr
->X_add_number
& 0x3) != 3)
2435 as_bad (_("bad value for opcode field, "
2436 "value must be 0...127 and "
2437 "lower 2 bits must be 0x3"));
2441 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2442 imm_expr
->X_op
= O_absent
;
2446 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2447 || imm_expr
->X_op
!= O_constant
2448 || imm_expr
->X_add_number
< 0
2449 || imm_expr
->X_add_number
>= 3)
2451 as_bad (_("bad value for opcode field, "
2452 "value must be 0...2"));
2456 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2457 imm_expr
->X_op
= O_absent
;
2461 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2469 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2470 || imm_expr
->X_op
!= O_constant
2471 || imm_expr
->X_add_number
< 0
2472 || imm_expr
->X_add_number
>= 128)
2474 as_bad (_("bad value for funct7 field, "
2475 "value must be 0...127"));
2479 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2480 imm_expr
->X_op
= O_absent
;
2484 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2485 || imm_expr
->X_op
!= O_constant
2486 || imm_expr
->X_add_number
< 0
2487 || imm_expr
->X_add_number
>= 8)
2489 as_bad (_("bad value for funct3 field, "
2490 "value must be 0...7"));
2494 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2495 imm_expr
->X_op
= O_absent
;
2499 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2500 || imm_expr
->X_op
!= O_constant
2501 || imm_expr
->X_add_number
< 0
2502 || imm_expr
->X_add_number
>= 4)
2504 as_bad (_("bad value for funct2 field, "
2505 "value must be 0...3"));
2509 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2510 imm_expr
->X_op
= O_absent
;
2515 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2520 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2521 || imm_expr
->X_op
!= O_constant
2522 || imm_expr
->X_add_number
!= 0)
2525 imm_expr
->X_op
= O_absent
;
2529 as_fatal (_("internal error: bad argument type %c"), *args
);
2534 error
= _("illegal operands");
2535 insn_with_csr
= FALSE
;
2539 /* Restore the character we might have clobbered above. */
2541 *(argsStart
- 1) = save_c
;
2547 md_assemble (char *str
)
2549 struct riscv_cl_insn insn
;
2550 expressionS imm_expr
;
2551 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2553 /* The arch and priv attributes should be set before assembling. */
2554 if (!start_assemble
)
2556 start_assemble
= TRUE
;
2558 /* Set the default_priv_spec according to the priv attributes. */
2559 if (!riscv_set_default_priv_spec (NULL
))
2563 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2567 as_bad ("%s `%s'", error
, str
);
2571 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2572 macro (&insn
, &imm_expr
, &imm_reloc
);
2574 append_insn (&insn
, &imm_expr
, imm_reloc
);
2578 md_atof (int type
, char *litP
, int *sizeP
)
2580 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2584 md_number_to_chars (char *buf
, valueT val
, int n
)
2586 number_to_chars_littleendian (buf
, val
, n
);
2589 const char *md_shortopts
= "O::g::G:";
2593 OPTION_MARCH
= OPTION_MD_BASE
,
2600 OPTION_NO_ARCH_ATTR
,
2602 OPTION_NO_CSR_CHECK
,
2608 struct option md_longopts
[] =
2610 {"march", required_argument
, NULL
, OPTION_MARCH
},
2611 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2612 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2613 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2614 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2615 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2616 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2617 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2618 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2619 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2620 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2621 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2622 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2624 {NULL
, no_argument
, NULL
, 0}
2626 size_t md_longopts_size
= sizeof (md_longopts
);
2629 FLOAT_ABI_DEFAULT
= -1,
2635 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2638 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2640 abi_xlen
= new_xlen
;
2641 float_abi
= new_float_abi
;
2646 md_parse_option (int c
, const char *arg
)
2651 /* riscv_after_parse_args will call riscv_set_arch to parse
2652 the architecture. */
2653 default_arch_with_ext
= arg
;
2657 riscv_opts
.pic
= FALSE
;
2661 riscv_opts
.pic
= TRUE
;
2665 if (strcmp (arg
, "ilp32") == 0)
2666 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2667 else if (strcmp (arg
, "ilp32e") == 0)
2668 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2669 else if (strcmp (arg
, "ilp32f") == 0)
2670 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2671 else if (strcmp (arg
, "ilp32d") == 0)
2672 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2673 else if (strcmp (arg
, "ilp32q") == 0)
2674 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2675 else if (strcmp (arg
, "lp64") == 0)
2676 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2677 else if (strcmp (arg
, "lp64f") == 0)
2678 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2679 else if (strcmp (arg
, "lp64d") == 0)
2680 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2681 else if (strcmp (arg
, "lp64q") == 0)
2682 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2688 riscv_opts
.relax
= TRUE
;
2691 case OPTION_NO_RELAX
:
2692 riscv_opts
.relax
= FALSE
;
2695 case OPTION_ARCH_ATTR
:
2696 riscv_opts
.arch_attr
= TRUE
;
2699 case OPTION_NO_ARCH_ATTR
:
2700 riscv_opts
.arch_attr
= FALSE
;
2703 case OPTION_CSR_CHECK
:
2704 riscv_opts
.csr_check
= TRUE
;
2707 case OPTION_NO_CSR_CHECK
:
2708 riscv_opts
.csr_check
= FALSE
;
2711 case OPTION_MISA_SPEC
:
2712 return riscv_set_default_isa_spec (arg
);
2714 case OPTION_MPRIV_SPEC
:
2715 return riscv_set_default_priv_spec (arg
);
2725 riscv_after_parse_args (void)
2727 /* The --with-arch is optional for now, so we have to set the xlen
2728 according to the default_arch, which is set by the --targte, first.
2729 Then, we use the xlen to set the default_arch_with_ext if the
2730 -march and --with-arch are not set. */
2733 if (strcmp (default_arch
, "riscv32") == 0)
2735 else if (strcmp (default_arch
, "riscv64") == 0)
2738 as_bad ("unknown default architecture `%s'", default_arch
);
2740 if (default_arch_with_ext
== NULL
)
2741 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2743 /* Initialize the hash table for extensions with default version. */
2744 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2746 /* If the -misa-spec isn't set, then we set the default ISA spec according
2747 to DEFAULT_RISCV_ISA_SPEC. */
2748 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2749 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2751 /* Set the architecture according to -march or or --with-arch. */
2752 riscv_set_arch (default_arch_with_ext
);
2754 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2755 riscv_set_rvc (FALSE
);
2756 if (riscv_subset_supports ("c"))
2757 riscv_set_rvc (TRUE
);
2759 /* Enable RVE if specified by the -march option. */
2760 riscv_set_rve (FALSE
);
2761 if (riscv_subset_supports ("e"))
2762 riscv_set_rve (TRUE
);
2764 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2765 according to DEFAULT_PRIV_SPEC. */
2766 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2767 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2769 /* Infer ABI from ISA if not specified on command line. */
2772 else if (abi_xlen
> xlen
)
2773 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2774 else if (abi_xlen
< xlen
)
2775 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2777 if (float_abi
== FLOAT_ABI_DEFAULT
)
2779 riscv_subset_t
*subset
;
2781 /* Assume soft-float unless D extension is present. */
2782 float_abi
= FLOAT_ABI_SOFT
;
2784 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2786 if (strcasecmp (subset
->name
, "D") == 0)
2787 float_abi
= FLOAT_ABI_DOUBLE
;
2788 if (strcasecmp (subset
->name
, "Q") == 0)
2789 float_abi
= FLOAT_ABI_QUAD
;
2794 elf_flags
|= EF_RISCV_RVE
;
2796 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2797 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2799 /* If the CIE to be produced has not been overridden on the command line,
2800 then produce version 3 by default. This allows us to use the full
2801 range of registers in a .cfi_return_column directive. */
2802 if (flag_dwarf_cie_version
== -1)
2803 flag_dwarf_cie_version
= 3;
2807 md_pcrel_from (fixS
*fixP
)
2809 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2812 /* Apply a fixup to the object file. */
2815 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2817 unsigned int subtype
;
2818 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2819 bfd_boolean relaxable
= FALSE
;
2823 /* Remember value for tc_gen_reloc. */
2824 fixP
->fx_addnumber
= *valP
;
2826 switch (fixP
->fx_r_type
)
2828 case BFD_RELOC_RISCV_HI20
:
2829 case BFD_RELOC_RISCV_LO12_I
:
2830 case BFD_RELOC_RISCV_LO12_S
:
2831 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2832 | bfd_getl32 (buf
), buf
);
2833 if (fixP
->fx_addsy
== NULL
)
2834 fixP
->fx_done
= TRUE
;
2838 case BFD_RELOC_RISCV_GOT_HI20
:
2839 case BFD_RELOC_RISCV_ADD8
:
2840 case BFD_RELOC_RISCV_ADD16
:
2841 case BFD_RELOC_RISCV_ADD32
:
2842 case BFD_RELOC_RISCV_ADD64
:
2843 case BFD_RELOC_RISCV_SUB6
:
2844 case BFD_RELOC_RISCV_SUB8
:
2845 case BFD_RELOC_RISCV_SUB16
:
2846 case BFD_RELOC_RISCV_SUB32
:
2847 case BFD_RELOC_RISCV_SUB64
:
2848 case BFD_RELOC_RISCV_RELAX
:
2851 case BFD_RELOC_RISCV_TPREL_HI20
:
2852 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2853 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2854 case BFD_RELOC_RISCV_TPREL_ADD
:
2858 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2859 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2860 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2861 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2862 if (fixP
->fx_addsy
!= NULL
)
2863 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2866 _("TLS relocation against a constant"));
2870 /* Use pc-relative relocation for FDE initial location.
2871 The symbol address in .eh_frame may be adjusted in
2872 _bfd_elf_discard_section_eh_frame, and the content of
2873 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2874 Therefore, we cannot insert a relocation whose addend symbol is
2875 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2876 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2877 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2878 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2879 && S_GET_VALUE (fixP
->fx_subsy
)
2880 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2882 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2883 fixP
->fx_subsy
= NULL
;
2890 case BFD_RELOC_RISCV_CFA
:
2891 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2893 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2894 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2895 fixP
->fx_next
->fx_subsy
= NULL
;
2896 fixP
->fx_next
->fx_offset
= 0;
2897 fixP
->fx_subsy
= NULL
;
2899 switch (fixP
->fx_r_type
)
2902 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2903 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2907 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2908 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2912 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2913 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2917 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2918 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2921 case BFD_RELOC_RISCV_CFA
:
2922 /* Load the byte to get the subtype. */
2923 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2924 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2927 case DW_CFA_advance_loc1
:
2928 fixP
->fx_where
= loc
+ 1;
2929 fixP
->fx_next
->fx_where
= loc
+ 1;
2930 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2931 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2934 case DW_CFA_advance_loc2
:
2936 fixP
->fx_next
->fx_size
= 2;
2937 fixP
->fx_where
= loc
+ 1;
2938 fixP
->fx_next
->fx_where
= loc
+ 1;
2939 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2940 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2943 case DW_CFA_advance_loc4
:
2945 fixP
->fx_next
->fx_size
= 4;
2946 fixP
->fx_where
= loc
;
2947 fixP
->fx_next
->fx_where
= loc
;
2948 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2949 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2953 if (subtype
< 0x80 && (subtype
& 0x40))
2955 /* DW_CFA_advance_loc */
2956 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2957 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2958 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2959 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2962 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2968 /* This case is unreachable. */
2975 /* If we are deleting this reloc entry, we must fill in the
2976 value now. This can happen if we have a .word which is not
2977 resolved when it appears but is later defined. */
2978 if (fixP
->fx_addsy
== NULL
)
2980 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2981 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2986 case BFD_RELOC_RISCV_JMP
:
2989 /* Fill in a tentative value to improve objdump readability. */
2990 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2991 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2992 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2996 case BFD_RELOC_12_PCREL
:
2999 /* Fill in a tentative value to improve objdump readability. */
3000 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3001 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3002 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3006 case BFD_RELOC_RISCV_RVC_BRANCH
:
3009 /* Fill in a tentative value to improve objdump readability. */
3010 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3011 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3012 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3016 case BFD_RELOC_RISCV_RVC_JUMP
:
3019 /* Fill in a tentative value to improve objdump readability. */
3020 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3021 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3022 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3026 case BFD_RELOC_RISCV_CALL
:
3027 case BFD_RELOC_RISCV_CALL_PLT
:
3031 case BFD_RELOC_RISCV_PCREL_HI20
:
3032 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3033 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3034 relaxable
= riscv_opts
.relax
;
3037 case BFD_RELOC_RISCV_ALIGN
:
3041 /* We ignore generic BFD relocations we don't know about. */
3042 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3043 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3046 if (fixP
->fx_subsy
!= NULL
)
3047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3048 _("unsupported symbol subtraction"));
3050 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3051 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3053 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3054 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3055 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3059 /* Because the value of .cfi_remember_state may changed after relaxation,
3060 we insert a fix to relocate it again in link-time. */
3063 riscv_pre_output_hook (void)
3065 const frchainS
*frch
;
3068 /* Save the current segment info. */
3070 subsegT subseg
= now_subseg
;
3072 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3073 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3077 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3079 if (frag
->fr_type
== rs_cfa
)
3082 expressionS
*symval
;
3084 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3085 exp
.X_op
= O_subtract
;
3086 exp
.X_add_symbol
= symval
->X_add_symbol
;
3087 exp
.X_add_number
= 0;
3088 exp
.X_op_symbol
= symval
->X_op_symbol
;
3090 /* We must set the segment before creating a frag after all
3091 frag chains have been chained together. */
3092 subseg_set (s
, frch
->frch_subseg
);
3094 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3095 BFD_RELOC_RISCV_CFA
);
3100 /* Restore the original segment info. */
3101 subseg_set (seg
, subseg
);
3105 /* This structure is used to hold a stack of .option values. */
3107 struct riscv_option_stack
3109 struct riscv_option_stack
*next
;
3110 struct riscv_set_options options
;
3113 static struct riscv_option_stack
*riscv_opts_stack
;
3115 /* Handle the .option pseudo-op. */
3118 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3120 char *name
= input_line_pointer
, ch
;
3122 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3123 ++input_line_pointer
;
3124 ch
= *input_line_pointer
;
3125 *input_line_pointer
= '\0';
3127 if (strcmp (name
, "rvc") == 0)
3128 riscv_set_rvc (TRUE
);
3129 else if (strcmp (name
, "norvc") == 0)
3130 riscv_set_rvc (FALSE
);
3131 else if (strcmp (name
, "pic") == 0)
3132 riscv_opts
.pic
= TRUE
;
3133 else if (strcmp (name
, "nopic") == 0)
3134 riscv_opts
.pic
= FALSE
;
3135 else if (strcmp (name
, "relax") == 0)
3136 riscv_opts
.relax
= TRUE
;
3137 else if (strcmp (name
, "norelax") == 0)
3138 riscv_opts
.relax
= FALSE
;
3139 else if (strcmp (name
, "csr-check") == 0)
3140 riscv_opts
.csr_check
= TRUE
;
3141 else if (strcmp (name
, "no-csr-check") == 0)
3142 riscv_opts
.csr_check
= FALSE
;
3143 else if (strcmp (name
, "push") == 0)
3145 struct riscv_option_stack
*s
;
3147 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3148 s
->next
= riscv_opts_stack
;
3149 s
->options
= riscv_opts
;
3150 riscv_opts_stack
= s
;
3152 else if (strcmp (name
, "pop") == 0)
3154 struct riscv_option_stack
*s
;
3156 s
= riscv_opts_stack
;
3158 as_bad (_(".option pop with no .option push"));
3161 riscv_opts
= s
->options
;
3162 riscv_opts_stack
= s
->next
;
3168 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3170 *input_line_pointer
= ch
;
3171 demand_empty_rest_of_line ();
3174 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3175 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3176 use in DWARF debug information. */
3179 s_dtprel (int bytes
)
3186 if (ex
.X_op
!= O_symbol
)
3188 as_bad (_("Unsupported use of %s"), (bytes
== 8
3191 ignore_rest_of_line ();
3194 p
= frag_more (bytes
);
3195 md_number_to_chars (p
, 0, bytes
);
3196 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3198 ? BFD_RELOC_RISCV_TLS_DTPREL64
3199 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3201 demand_empty_rest_of_line ();
3204 /* Handle the .bss pseudo-op. */
3207 s_bss (int ignore ATTRIBUTE_UNUSED
)
3209 subseg_set (bss_section
, 0);
3210 demand_empty_rest_of_line ();
3214 riscv_make_nops (char *buf
, bfd_vma bytes
)
3218 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3219 means we are not within a valid instruction sequence. It is thus safe
3220 to use a zero byte, even though that is not a valid instruction. */
3224 /* Use at most one 2-byte NOP. */
3225 if ((bytes
- i
) % 4 == 2)
3227 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3231 /* Fill the remainder with 4-byte NOPs. */
3232 for ( ; i
< bytes
; i
+= 4)
3233 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3236 /* Called from md_do_align. Used to create an alignment frag in a
3237 code section by emitting a worst-case NOP sequence that the linker
3238 will later relax to the correct number of NOPs. We can't compute
3239 the correct alignment now because of other linker relaxations. */
3242 riscv_frag_align_code (int n
)
3244 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3245 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3246 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3250 /* If we are moving to a smaller alignment than the instruction size, then no
3251 alignment is required. */
3252 if (bytes
<= insn_alignment
)
3255 /* When not relaxing, riscv_handle_align handles code alignment. */
3256 if (!riscv_opts
.relax
)
3259 nops
= frag_more (worst_case_bytes
);
3261 ex
.X_op
= O_constant
;
3262 ex
.X_add_number
= worst_case_bytes
;
3264 riscv_make_nops (nops
, worst_case_bytes
);
3266 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3267 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3272 /* Implement HANDLE_ALIGN. */
3275 riscv_handle_align (fragS
*fragP
)
3277 switch (fragP
->fr_type
)
3280 /* When relaxing, riscv_frag_align_code handles code alignment. */
3281 if (!riscv_opts
.relax
)
3283 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3284 - fragP
->fr_address
- fragP
->fr_fix
);
3285 /* We have 4 byte uncompressed nops. */
3286 bfd_signed_vma size
= 4;
3287 bfd_signed_vma excess
= bytes
% size
;
3288 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3293 /* Insert zeros or compressed nops to get 4 byte alignment. */
3296 riscv_make_nops (p
, excess
);
3297 fragP
->fr_fix
+= excess
;
3301 /* Insert variable number of 4 byte uncompressed nops. */
3302 riscv_make_nops (p
, size
);
3303 fragP
->fr_var
= size
;
3313 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3315 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3318 /* Translate internal representation of relocation info to BFD target
3322 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3324 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3326 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3327 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3328 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3329 reloc
->addend
= fixp
->fx_addnumber
;
3331 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3332 if (reloc
->howto
== NULL
)
3334 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3335 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3337 /* We don't have R_RISCV_8/16, but for this special case,
3338 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3342 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3343 _("cannot represent %s relocation in object file"),
3344 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3352 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3354 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3356 offsetT old_var
= fragp
->fr_var
;
3357 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3358 return fragp
->fr_var
- old_var
;
3364 /* Expand far branches to multi-instruction sequences. */
3367 md_convert_frag_branch (fragS
*fragp
)
3375 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3377 exp
.X_op
= O_symbol
;
3378 exp
.X_add_symbol
= fragp
->fr_symbol
;
3379 exp
.X_add_number
= fragp
->fr_offset
;
3381 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3383 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3385 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3389 /* Expand the RVC branch into a RISC-V one. */
3390 insn
= bfd_getl16 (buf
);
3391 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3392 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3394 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3395 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3396 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3397 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3398 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3399 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3402 bfd_putl32 (insn
, buf
);
3406 /* Invert the branch condition. Branch over the jump. */
3407 insn
= bfd_getl16 (buf
);
3408 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3409 insn
|= ENCODE_RVC_B_IMM (6);
3410 bfd_putl16 (insn
, buf
);
3415 /* Just keep the RVC branch. */
3416 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3417 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3418 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3419 2, &exp
, FALSE
, reloc
);
3428 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3431 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3433 /* Invert the branch condition. Branch over the jump. */
3434 insn
= bfd_getl32 (buf
);
3435 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3436 insn
|= ENCODE_SBTYPE_IMM (8);
3437 md_number_to_chars ((char *) buf
, insn
, 4);
3441 /* Jump to the target. */
3442 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3443 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3444 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3449 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3450 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3451 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3452 4, &exp
, FALSE
, reloc
);
3461 fixp
->fx_file
= fragp
->fr_file
;
3462 fixp
->fx_line
= fragp
->fr_line
;
3464 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3465 + fragp
->fr_fix
+ fragp
->fr_var
);
3467 fragp
->fr_fix
+= fragp
->fr_var
;
3470 /* Relax a machine dependent frag. This returns the amount by which
3471 the current size of the frag should change. */
3474 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3477 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3478 md_convert_frag_branch (fragp
);
3482 md_show_usage (FILE *stream
)
3484 fprintf (stream
, _("\
3486 -fpic generate position-independent code\n\
3487 -fno-pic don't generate position-independent code (default)\n\
3488 -march=ISA set the RISC-V architecture\n\
3489 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3490 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3491 -mabi=ABI set the RISC-V ABI\n\
3492 -mrelax enable relax (default)\n\
3493 -mno-relax disable relax\n\
3494 -march-attr generate RISC-V arch attribute\n\
3495 -mno-arch-attr don't generate RISC-V arch attribute\n\
3499 /* Standard calling conventions leave the CFA at SP on entry. */
3501 riscv_cfi_frame_initial_instructions (void)
3503 cfi_add_CFA_def_cfa_register (X_SP
);
3507 tc_riscv_regname_to_dw2regnum (char *regname
)
3511 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3514 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3517 /* CSRs are numbered 4096 -> 8191. */
3518 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3521 as_bad (_("unknown register `%s'"), regname
);
3526 riscv_elf_final_processing (void)
3528 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3531 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3532 since these directives break relaxation when used with symbol deltas. */
3535 s_riscv_leb128 (int sign
)
3538 char *save_in
= input_line_pointer
;
3541 if (exp
.X_op
!= O_constant
)
3542 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3543 demand_empty_rest_of_line ();
3545 input_line_pointer
= save_in
;
3546 return s_leb128 (sign
);
3549 /* Parse the .insn directive. */
3552 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3554 char *str
= input_line_pointer
;
3555 struct riscv_cl_insn insn
;
3556 expressionS imm_expr
;
3557 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3560 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3561 ++input_line_pointer
;
3563 save_c
= *input_line_pointer
;
3564 *input_line_pointer
= '\0';
3566 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3567 &imm_reloc
, insn_type_hash
);
3571 as_bad ("%s `%s'", error
, str
);
3575 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3576 append_insn (&insn
, &imm_expr
, imm_reloc
);
3579 *input_line_pointer
= save_c
;
3580 demand_empty_rest_of_line ();
3583 /* Update arch and priv attributes. If we don't set the corresponding ELF
3584 attributes, then try to output the default ones. */
3587 riscv_write_out_attrs (void)
3589 const char *arch_str
, *priv_str
, *p
;
3590 /* versions[0] is major, versions[1] is minor,
3591 and versions[3] is revision. */
3592 unsigned versions
[3] = {0}, number
= 0;
3595 /* Re-write arch attribute to normalize the arch string. */
3596 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3597 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3598 xfree ((void *)arch_str
);
3600 /* For the file without any instruction, we don't set the default_priv_spec
3601 according to the priv attributes since the md_assemble isn't called.
3602 Call riscv_set_default_priv_spec here for the above case, although
3603 it seems strange. */
3605 && !riscv_set_default_priv_spec (NULL
))
3608 /* Re-write priv attributes by default_priv_spec. */
3609 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3611 for (i
= 0; *p
; ++p
)
3613 if (*p
== '.' && i
< 3)
3615 versions
[i
++] = number
;
3618 else if (ISDIGIT (*p
))
3619 number
= (number
* 10) + (*p
- '0');
3622 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3626 versions
[i
] = number
;
3628 /* Set the priv attributes. */
3629 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3630 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3631 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3634 /* Add the default contents for the .riscv.attributes section. If any
3635 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3636 to update the arch and priv attributes. */
3639 riscv_set_public_attributes (void)
3641 if (riscv_opts
.arch_attr
|| explicit_attr
)
3642 riscv_write_out_attrs ();
3645 /* Called after all assembly has been done. */
3650 riscv_set_public_attributes ();
3653 /* Given a symbolic attribute NAME, return the proper integer value.
3654 Returns -1 if the attribute is not known. */
3657 riscv_convert_symbolic_attribute (const char *name
)
3666 /* When you modify this table you should
3667 also modify the list in doc/c-riscv.texi. */
3668 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3672 T(priv_spec_revision
),
3673 T(unaligned_access
),
3683 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3684 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3685 return attribute_table
[i
].tag
;
3690 /* Parse a .attribute directive. */
3693 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3695 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3697 obj_attribute
*attr
;
3699 explicit_attr
= TRUE
;
3702 case Tag_RISCV_arch
:
3704 attr
= elf_known_obj_attributes_proc (stdoutput
);
3705 if (!start_assemble
)
3706 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3708 as_fatal (_(".attribute arch must set before any instructions"));
3710 if (old_xlen
!= xlen
)
3712 /* We must re-init bfd again if xlen is changed. */
3713 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3714 bfd_find_target (riscv_target_format (), stdoutput
);
3716 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3717 as_warn (_("Could not set architecture and machine"));
3721 case Tag_RISCV_priv_spec
:
3722 case Tag_RISCV_priv_spec_minor
:
3723 case Tag_RISCV_priv_spec_revision
:
3725 as_fatal (_(".attribute priv spec must set before any instructions"));
3733 /* Pseudo-op table. */
3735 static const pseudo_typeS riscv_pseudo_table
[] =
3737 /* RISC-V-specific pseudo-ops. */
3738 {"option", s_riscv_option
, 0},
3742 {"dtprelword", s_dtprel
, 4},
3743 {"dtpreldword", s_dtprel
, 8},
3745 {"uleb128", s_riscv_leb128
, 0},
3746 {"sleb128", s_riscv_leb128
, 1},
3747 {"insn", s_riscv_insn
, 0},
3748 {"attribute", s_riscv_attribute
, 0},
3754 riscv_pop_insert (void)
3756 extern void pop_insert (const pseudo_typeS
*);
3758 pop_insert (riscv_pseudo_table
);