1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
88 static struct riscv_set_options riscv_opts
=
94 DEFAULT_RISCV_ATTR
, /* arch_attr */
98 riscv_set_rvc (bfd_boolean rvc_value
)
101 elf_flags
|= EF_RISCV_RVC
;
103 riscv_opts
.rvc
= rvc_value
;
107 riscv_set_rve (bfd_boolean rve_value
)
109 riscv_opts
.rve
= rve_value
;
112 static riscv_subset_list_t riscv_subsets
;
115 riscv_subset_supports (const char *feature
)
117 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
120 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
124 riscv_multi_subset_supports (const char *features
[])
127 bfd_boolean supported
= TRUE
;
129 for (;features
[i
]; ++i
)
130 supported
= supported
&& riscv_subset_supports (features
[i
]);
135 /* Set which ISA and extensions are available. */
138 riscv_set_arch (const char *s
)
140 riscv_parse_subset_t rps
;
141 rps
.subset_list
= &riscv_subsets
;
142 rps
.error_handler
= as_fatal
;
145 riscv_release_subset_list (&riscv_subsets
);
146 riscv_parse_subset (&rps
, s
);
149 /* Handle of the OPCODE hash table. */
150 static struct hash_control
*op_hash
= NULL
;
152 /* Handle of the type of .insn hash table. */
153 static struct hash_control
*insn_type_hash
= NULL
;
155 /* This array holds the chars that always start a comment. If the
156 pre-processor is disabled, these aren't very useful */
157 const char comment_chars
[] = "#";
159 /* This array holds the chars that only start a comment at the beginning of
160 a line. If the line seems to have the form '# 123 filename'
161 .line and .file directives will appear in the pre-processed output */
162 /* Note that input_file.c hand checks for '#' at the beginning of the
163 first line of the input file. This is because the compiler outputs
164 #NO_APP at the beginning of its output. */
165 /* Also note that C style comments are always supported. */
166 const char line_comment_chars
[] = "#";
168 /* This array holds machine specific line separator characters. */
169 const char line_separator_chars
[] = ";";
171 /* Chars that can be used to separate mant from exp in floating point nums */
172 const char EXP_CHARS
[] = "eE";
174 /* Chars that mean this number is a floating point constant */
177 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
179 /* Indicate we are already assemble any instructions or not. */
180 static bfd_boolean start_assemble
= FALSE
;
182 /* Indicate arch attribute is explictly set. */
183 static bfd_boolean explicit_arch_attr
= FALSE
;
185 /* Macros for encoding relaxation state for RVC branches and far jumps. */
186 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
189 | ((uncond) ? 1 : 0) \
192 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
193 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
194 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
195 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
197 /* Is the given value a sign-extended 32-bit value? */
198 #define IS_SEXT_32BIT_NUM(x) \
199 (((x) &~ (offsetT) 0x7fffffff) == 0 \
200 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
203 #define IS_ZEXT_32BIT_NUM(x) \
204 (((x) &~ (offsetT) 0xffffffff) == 0 \
205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
207 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
208 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
209 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
210 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
212 /* Determine if an instruction matches an opcode. */
213 #define OPCODE_MATCHES(OPCODE, OP) \
214 (((OPCODE) & MASK_##OP) == MATCH_##OP)
216 static char *expr_end
;
218 /* The default target format to use. */
221 riscv_target_format (void)
223 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
226 /* Return the length of instruction INSN. */
228 static inline unsigned int
229 insn_length (const struct riscv_cl_insn
*insn
)
231 return riscv_insn_length (insn
->insn_opcode
);
234 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
237 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
240 insn
->insn_opcode
= mo
->match
;
246 /* Install INSN at the location specified by its "frag" and "where" fields. */
249 install_insn (const struct riscv_cl_insn
*insn
)
251 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
252 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
255 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
256 and install the opcode in the new location. */
259 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
263 if (insn
->fixp
!= NULL
)
265 insn
->fixp
->fx_frag
= frag
;
266 insn
->fixp
->fx_where
= where
;
271 /* Add INSN to the end of the output. */
274 add_fixed_insn (struct riscv_cl_insn
*insn
)
276 char *f
= frag_more (insn_length (insn
));
277 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
281 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
282 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
284 frag_grow (max_chars
);
285 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
286 frag_var (rs_machine_dependent
, max_chars
, var
,
287 subtype
, symbol
, offset
, NULL
);
290 /* Compute the length of a branch sequence, and adjust the stored length
291 accordingly. If FRAGP is NULL, the worst-case length is returned. */
294 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
296 int jump
, rvc
, length
= 8;
301 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
302 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
303 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
305 /* Assume jumps are in range; the linker will catch any that aren't. */
306 length
= jump
? 4 : 8;
308 if (fragp
->fr_symbol
!= NULL
309 && S_IS_DEFINED (fragp
->fr_symbol
)
310 && !S_IS_WEAK (fragp
->fr_symbol
)
311 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
313 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
314 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
315 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
317 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
319 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
321 else if (!jump
&& rvc
)
326 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
331 /* Information about an opcode name, mnemonics and its value. */
338 /* List for all supported opcode name. */
339 static const struct opcode_name_t opcode_name_list
[] =
384 /* Hash table for lookup opcode name. */
385 static struct hash_control
*opcode_names_hash
= NULL
;
387 /* Initialization for hash table of opcode name. */
389 init_opcode_names_hash (void)
392 const struct opcode_name_t
*opcode
;
394 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
396 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
399 as_fatal (_("internal error: can't hash `%s': %s"),
400 opcode
->name
, retval
);
404 /* Find `s` is a valid opcode name or not,
405 return the opcode name info if found. */
406 static const struct opcode_name_t
*
407 opcode_name_lookup (char **s
)
411 struct opcode_name_t
*o
;
413 /* Find end of name. */
415 if (is_name_beginner (*e
))
417 while (is_part_of_name (*e
))
420 /* Terminate name. */
424 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
426 /* Advance to next token if one was recognized. */
450 static struct hash_control
*reg_names_hash
= NULL
;
452 #define ENCODE_REG_HASH(cls, n) \
453 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
454 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
455 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
458 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
460 void *hash
= ENCODE_REG_HASH (class, n
);
461 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
464 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
468 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
472 for (i
= 0; i
< n
; i
++)
473 hash_reg_name (class, names
[i
], i
);
477 reg_lookup_internal (const char *s
, enum reg_class
class)
479 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
481 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
484 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
487 return DECODE_REG_NUM (r
);
491 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
497 /* Find end of name. */
499 if (is_name_beginner (*e
))
501 while (is_part_of_name (*e
))
504 /* Terminate name. */
508 /* Look for the register. Advance to next token if one was recognized. */
509 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
519 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
521 const char *p
= strchr (*s
, ',');
522 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
527 for (i
= 0; i
< size
; i
++)
528 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
538 /* For consistency checking, verify that all bits are specified either
539 by the match/mask part of the instruction definition, or by the
542 `length` could be 0, 4 or 8, 0 for auto detection. */
544 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
546 const char *p
= opc
->args
;
548 insn_t used_bits
= opc
->mask
;
550 insn_t required_bits
;
553 insn_width
= 8 * riscv_insn_length (opc
->match
);
555 insn_width
= 8 * length
;
557 required_bits
= ~0ULL >> (64 - insn_width
);
559 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
561 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
562 opc
->name
, opc
->args
);
566 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
573 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
574 case 'c': break; /* RS1, constrained to equal sp */
575 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
576 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
577 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
578 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
579 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
580 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
581 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
582 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
583 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
584 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
585 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
586 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
587 case 'w': break; /* RS1S, constrained to equal RD */
588 case 'x': break; /* RS2S, constrained to equal RD */
589 case 'z': break; /* RS2S, contrained to be x0 */
590 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
591 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
592 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
593 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
594 case 'U': break; /* RS1, constrained to equal RD */
595 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
596 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
597 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
598 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
599 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
600 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
601 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
602 case 'F': /* funct */
605 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
606 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
607 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
608 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
610 as_bad (_("internal: bad RISC-V opcode"
611 " (unknown operand type `CF%c'): %s %s"),
612 c
, opc
->name
, opc
->args
);
617 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
618 c
, opc
->name
, opc
->args
);
625 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
626 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
628 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
629 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
630 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
632 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
633 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
634 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
635 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
636 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
637 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
638 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
639 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
640 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
641 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
642 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
644 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
645 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
646 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
647 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
648 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
654 case 'F': /* funct */
657 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
658 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
659 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
661 as_bad (_("internal: bad RISC-V opcode"
662 " (unknown operand type `F%c'): %s %s"),
663 c
, opc
->name
, opc
->args
);
667 case 'O': /* opcode */
670 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
671 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
673 as_bad (_("internal: bad RISC-V opcode"
674 " (unknown operand type `F%c'): %s %s"),
675 c
, opc
->name
, opc
->args
);
680 as_bad (_("internal: bad RISC-V opcode "
681 "(unknown operand type `%c'): %s %s"),
682 c
, opc
->name
, opc
->args
);
686 if (used_bits
!= required_bits
)
688 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
689 ~(unsigned long)(used_bits
& required_bits
),
690 opc
->name
, opc
->args
);
696 struct percent_op_match
699 bfd_reloc_code_real_type reloc
;
702 /* Common hash table initialization function for
703 instruction and .insn directive. */
704 static struct hash_control
*
705 init_opcode_hash (const struct riscv_opcode
*opcodes
,
706 bfd_boolean insn_directive_p
)
710 struct hash_control
*hash
= hash_new ();
711 while (opcodes
[i
].name
)
713 const char *name
= opcodes
[i
].name
;
714 const char *hash_error
=
715 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
719 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
720 opcodes
[i
].name
, hash_error
);
721 /* Probably a memory allocation problem? Give up now. */
722 as_fatal (_("Broken assembler. No assembly attempted."));
727 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
729 if (insn_directive_p
)
730 length
= ((name
[0] == 'c') ? 2 : 4);
732 length
= 0; /* Let assembler determine the length. */
733 if (!validate_riscv_insn (&opcodes
[i
], length
))
734 as_fatal (_("Broken assembler. No assembly attempted."));
737 gas_assert (!insn_directive_p
);
740 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
746 /* This function is called once, at assembler startup time. It should set up
747 all the tables, etc. that the MD part of the assembler will need. */
752 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
754 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
755 as_warn (_("Could not set architecture and machine"));
757 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
758 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
760 reg_names_hash
= hash_new ();
761 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
762 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
763 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
764 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
766 /* Add "fp" as an alias for "s0". */
767 hash_reg_name (RCLASS_GPR
, "fp", 8);
769 opcode_names_hash
= hash_new ();
770 init_opcode_names_hash ();
772 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
773 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
774 #include "opcode/riscv-opc.h"
777 /* Set the default alignment for the text section. */
778 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
782 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
789 case BFD_RELOC_RISCV_HI20
:
790 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
792 case BFD_RELOC_RISCV_LO12_S
:
793 return ENCODE_STYPE_IMM (value
);
795 case BFD_RELOC_RISCV_LO12_I
:
796 return ENCODE_ITYPE_IMM (value
);
803 /* Output an instruction. IP is the instruction information.
804 ADDRESS_EXPR is an operand of the instruction to be used with
808 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
809 bfd_reloc_code_real_type reloc_type
)
811 dwarf2_emit_insn (0);
813 if (reloc_type
!= BFD_RELOC_UNUSED
)
815 reloc_howto_type
*howto
;
817 gas_assert (address_expr
);
818 if (reloc_type
== BFD_RELOC_12_PCREL
819 || reloc_type
== BFD_RELOC_RISCV_JMP
)
821 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
822 int best_case
= riscv_insn_length (ip
->insn_opcode
);
823 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
824 add_relaxed_insn (ip
, worst_case
, best_case
,
825 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
826 address_expr
->X_add_symbol
,
827 address_expr
->X_add_number
);
832 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
834 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
836 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
837 bfd_get_reloc_size (howto
),
838 address_expr
, FALSE
, reloc_type
);
840 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
847 /* We need to start a new frag after any instruction that can be
848 optimized away or compressed by the linker during relaxation, to prevent
849 the assembler from computing static offsets across such an instruction.
850 This is necessary to get correct EH info. */
851 if (reloc_type
== BFD_RELOC_RISCV_CALL
852 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
853 || reloc_type
== BFD_RELOC_RISCV_HI20
854 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
855 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
856 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
858 frag_wane (frag_now
);
863 /* Build an instruction created by a macro expansion. This is passed
864 a pointer to the count of instructions created so far, an
865 expression, the name of the instruction to build, an operand format
866 string, and corresponding arguments. */
869 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
871 const struct riscv_opcode
*mo
;
872 struct riscv_cl_insn insn
;
873 bfd_reloc_code_real_type r
;
876 va_start (args
, fmt
);
878 r
= BFD_RELOC_UNUSED
;
879 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
882 /* Find a non-RVC variant of the instruction. append_insn will compress
884 while (riscv_insn_length (mo
->match
) < 4)
886 gas_assert (strcmp (name
, mo
->name
) == 0);
888 create_insn (&insn
, mo
);
894 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
898 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
902 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
906 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
912 gas_assert (ep
!= NULL
);
913 r
= va_arg (args
, int);
921 as_fatal (_("internal error: invalid macro"));
926 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
928 append_insn (&insn
, ep
, r
);
931 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
934 normalize_constant_expr (expressionS
*ex
)
938 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
939 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
940 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
944 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
945 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
948 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
949 bfd_boolean maybe_csr
)
951 if (ex
->X_op
== O_big
)
952 as_bad (_("unsupported large constant"));
953 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
954 as_bad (_("unknown CSR `%s'"),
955 S_GET_NAME (ex
->X_add_symbol
));
956 else if (ex
->X_op
!= O_constant
)
957 as_bad (_("Instruction %s requires absolute expression"),
959 normalize_constant_expr (ex
);
963 make_internal_label (void)
965 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
966 (valueT
) frag_now_fix (), frag_now
);
969 /* Load an entry from the GOT. */
971 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
972 const char *lo_insn
, const char *lo_pattern
,
973 bfd_reloc_code_real_type hi_reloc
,
974 bfd_reloc_code_real_type lo_reloc
)
978 ep2
.X_add_symbol
= make_internal_label ();
979 ep2
.X_add_number
= 0;
981 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
982 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
986 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
987 bfd_reloc_code_real_type hi_reloc
,
988 bfd_reloc_code_real_type lo_reloc
)
990 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
994 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
995 bfd_reloc_code_real_type hi_reloc
,
996 bfd_reloc_code_real_type lo_reloc
)
998 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1001 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1003 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1004 bfd_reloc_code_real_type reloc
)
1006 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1007 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1010 /* Load an integer constant into a register. */
1013 load_const (int reg
, expressionS
*ep
)
1015 int shift
= RISCV_IMM_BITS
;
1016 expressionS upper
= *ep
, lower
= *ep
;
1017 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1018 upper
.X_add_number
-= lower
.X_add_number
;
1020 if (ep
->X_op
!= O_constant
)
1022 as_bad (_("unsupported large constant"));
1026 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1028 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1029 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1032 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1033 load_const (reg
, &upper
);
1035 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1036 if (lower
.X_add_number
!= 0)
1037 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1041 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1044 if (upper
.X_add_number
!= 0)
1046 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1050 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1051 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1052 BFD_RELOC_RISCV_LO12_I
);
1056 /* Expand RISC-V assembly macros into one or more instructions. */
1058 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1059 bfd_reloc_code_real_type
*imm_reloc
)
1061 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1062 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1063 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1064 int mask
= ip
->insn_mo
->mask
;
1069 load_const (rd
, imm_expr
);
1074 /* Load the address of a symbol into a register. */
1075 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1076 as_bad (_("offset too large"));
1078 if (imm_expr
->X_op
== O_constant
)
1079 load_const (rd
, imm_expr
);
1080 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1081 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1082 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1083 else /* Local PIC symbol, or any non-PIC symbol */
1084 pcrel_load (rd
, rd
, imm_expr
, "addi",
1085 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1089 pcrel_load (rd
, rd
, imm_expr
, "addi",
1090 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1094 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1095 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1099 pcrel_load (rd
, rd
, imm_expr
, "lb",
1100 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1104 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1105 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1109 pcrel_load (rd
, rd
, imm_expr
, "lh",
1110 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1114 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1115 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1119 pcrel_load (rd
, rd
, imm_expr
, "lw",
1120 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1124 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1125 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1129 pcrel_load (rd
, rd
, imm_expr
, "ld",
1130 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1134 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1135 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1139 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1140 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1144 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1145 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1149 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1150 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1154 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1155 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1159 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1160 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1164 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1165 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1169 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1170 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1174 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1178 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1183 static const struct percent_op_match percent_op_utype
[] =
1185 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1186 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1187 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1188 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1189 {"%hi", BFD_RELOC_RISCV_HI20
},
1193 static const struct percent_op_match percent_op_itype
[] =
1195 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1196 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1197 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1201 static const struct percent_op_match percent_op_stype
[] =
1203 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1204 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1205 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1209 static const struct percent_op_match percent_op_rtype
[] =
1211 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1215 static const struct percent_op_match percent_op_null
[] =
1220 /* Return true if *STR points to a relocation operator. When returning true,
1221 move *STR over the operator and store its relocation code in *RELOC.
1222 Leave both *STR and *RELOC alone when returning false. */
1225 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1226 const struct percent_op_match
*percent_op
)
1228 for ( ; percent_op
->str
; percent_op
++)
1229 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1231 int len
= strlen (percent_op
->str
);
1233 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1236 *str
+= strlen (percent_op
->str
);
1237 *reloc
= percent_op
->reloc
;
1239 /* Check whether the output BFD supports this relocation.
1240 If not, issue an error and fall back on something safe. */
1241 if (*reloc
!= BFD_RELOC_UNUSED
1242 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1244 as_bad ("relocation %s isn't supported by the current ABI",
1246 *reloc
= BFD_RELOC_UNUSED
;
1254 my_getExpression (expressionS
*ep
, char *str
)
1258 save_in
= input_line_pointer
;
1259 input_line_pointer
= str
;
1261 expr_end
= input_line_pointer
;
1262 input_line_pointer
= save_in
;
1265 /* Parse string STR as a 16-bit relocatable operand. Store the
1266 expression in *EP and the relocation, if any, in RELOC.
1267 Return the number of relocation operators used (0 or 1).
1269 On exit, EXPR_END points to the first character after the expression. */
1272 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1273 char *str
, const struct percent_op_match
*percent_op
)
1276 unsigned crux_depth
, str_depth
, regno
;
1279 /* First, check for integer registers. No callers can accept a reg, but
1280 we need to avoid accidentally creating a useless undefined symbol below,
1281 if this is an instruction pattern that can't match. A glibc build fails
1282 if this is removed. */
1283 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1285 ep
->X_op
= O_register
;
1286 ep
->X_add_number
= regno
;
1291 /* Search for the start of the main expression.
1292 End the loop with CRUX pointing to the start
1293 of the main expression and with CRUX_DEPTH containing the number
1294 of open brackets at that point. */
1301 crux_depth
= str_depth
;
1303 /* Skip over whitespace and brackets, keeping count of the number
1305 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1311 && parse_relocation (&str
, reloc
, percent_op
));
1313 my_getExpression (ep
, crux
);
1316 /* Match every open bracket. */
1317 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1322 as_bad ("unclosed '('");
1329 /* Parse opcode name, could be an mnemonics or number. */
1331 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1332 char *str
, const struct percent_op_match
*percent_op
)
1334 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1338 ep
->X_op
= O_constant
;
1339 ep
->X_add_number
= o
->val
;
1343 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1346 /* Detect and handle implicitly zero load-store offsets. For example,
1347 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1348 an implicit offset was detected. */
1351 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1353 /* Check whether there is only a single bracketed expression left.
1354 If so, it must be the base register and the constant must be zero. */
1355 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1357 ep
->X_op
= O_constant
;
1358 ep
->X_add_number
= 0;
1365 /* This routine assembles an instruction into its binary format. As a
1366 side effect, it sets the global variable imm_reloc to the type of
1367 relocation to do if one of the operands is an address expression. */
1370 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1371 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1376 struct riscv_opcode
*insn
;
1381 const struct percent_op_match
*p
;
1382 const char *error
= "unrecognized opcode";
1384 /* Parse the name of the instruction. Terminate the string if whitespace
1385 is found so that hash_find only sees the name part of the string. */
1386 for (s
= str
; *s
!= '\0'; ++s
)
1394 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1397 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1399 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1402 if (!riscv_multi_subset_supports (insn
->subset
))
1405 create_insn (ip
, insn
);
1408 imm_expr
->X_op
= O_absent
;
1409 *imm_reloc
= BFD_RELOC_UNUSED
;
1410 p
= percent_op_itype
;
1412 for (args
= insn
->args
;; ++args
)
1414 s
+= strspn (s
, " \t");
1417 case '\0': /* End of args. */
1418 if (insn
->pinfo
!= INSN_MACRO
)
1420 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1423 /* For .insn, insn->match and insn->mask are 0. */
1424 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1432 /* Successful assembly. */
1439 case 's': /* RS1 x8-x15 */
1440 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1441 || !(regno
>= 8 && regno
<= 15))
1443 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1445 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1446 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1447 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1450 case 't': /* RS2 x8-x15 */
1451 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1452 || !(regno
>= 8 && regno
<= 15))
1454 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1456 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1457 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1458 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1461 case 'U': /* RS1, constrained to equal RD. */
1462 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1463 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1467 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1469 INSERT_OPERAND (CRS2
, *ip
, regno
);
1471 case 'c': /* RS1, constrained to equal sp. */
1472 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1476 case 'z': /* RS2, contrained to equal x0. */
1477 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1482 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1483 || imm_expr
->X_op
!= O_constant
1484 || imm_expr
->X_add_number
<= 0
1485 || imm_expr
->X_add_number
>= 64)
1487 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1490 imm_expr
->X_op
= O_absent
;
1493 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1494 || imm_expr
->X_op
!= O_constant
1495 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1496 || imm_expr
->X_add_number
<= 0
1497 || imm_expr
->X_add_number
>= 32)
1499 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1502 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1503 || imm_expr
->X_op
!= O_constant
1504 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1505 || imm_expr
->X_add_number
< 0
1506 || imm_expr
->X_add_number
>= 256)
1508 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1511 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1512 || imm_expr
->X_op
!= O_constant
1513 || imm_expr
->X_add_number
== 0
1514 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1516 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1519 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1520 || imm_expr
->X_op
!= O_constant
1521 || imm_expr
->X_add_number
== 0
1522 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1524 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1527 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1529 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1530 || imm_expr
->X_op
!= O_constant
1531 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1533 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1536 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1538 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1539 || imm_expr
->X_op
!= O_constant
1540 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1542 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1545 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1547 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1548 || imm_expr
->X_op
!= O_constant
1549 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1552 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1555 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1557 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1558 || imm_expr
->X_op
!= O_constant
1559 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1562 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1565 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1566 || imm_expr
->X_op
!= O_constant
1567 /* C.addiw, c.li, and c.andi allow zero immediate.
1568 C.addi allows zero immediate as hint. Otherwise this
1570 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1572 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1575 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1576 || imm_expr
->X_op
!= O_constant
1577 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1578 || imm_expr
->X_add_number
== 0)
1581 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1584 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1585 || imm_expr
->X_op
!= O_constant
1586 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1587 || imm_expr
->X_add_number
== 0)
1590 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1593 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1595 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1596 || imm_expr
->X_op
!= O_constant
1597 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1600 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1603 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1605 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1606 || imm_expr
->X_op
!= O_constant
1607 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1610 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1613 p
= percent_op_utype
;
1614 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1617 if (imm_expr
->X_op
!= O_constant
1618 || imm_expr
->X_add_number
<= 0
1619 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1620 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1621 && (imm_expr
->X_add_number
<
1622 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1624 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1627 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1628 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1629 || ((int32_t)imm_expr
->X_add_number
1630 != imm_expr
->X_add_number
))
1632 imm_expr
->X_add_number
=
1633 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1639 case 'S': /* Floating-point RS1 x8-x15. */
1640 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1641 || !(regno
>= 8 && regno
<= 15))
1643 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1645 case 'D': /* Floating-point RS2 x8-x15. */
1646 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1647 || !(regno
>= 8 && regno
<= 15))
1649 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1651 case 'T': /* Floating-point RS2. */
1652 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1654 INSERT_OPERAND (CRS2
, *ip
, regno
);
1660 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1661 || imm_expr
->X_op
!= O_constant
1662 || imm_expr
->X_add_number
< 0
1663 || imm_expr
->X_add_number
>= 64)
1665 as_bad (_("bad value for funct6 field, "
1666 "value must be 0...64"));
1670 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1671 imm_expr
->X_op
= O_absent
;
1675 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1676 || imm_expr
->X_op
!= O_constant
1677 || imm_expr
->X_add_number
< 0
1678 || imm_expr
->X_add_number
>= 16)
1680 as_bad (_("bad value for funct4 field, "
1681 "value must be 0...15"));
1685 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1686 imm_expr
->X_op
= O_absent
;
1690 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1691 || imm_expr
->X_op
!= O_constant
1692 || imm_expr
->X_add_number
< 0
1693 || imm_expr
->X_add_number
>= 8)
1695 as_bad (_("bad value for funct3 field, "
1696 "value must be 0...7"));
1699 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1700 imm_expr
->X_op
= O_absent
;
1704 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1705 || imm_expr
->X_op
!= O_constant
1706 || imm_expr
->X_add_number
< 0
1707 || imm_expr
->X_add_number
>= 4)
1709 as_bad (_("bad value for funct2 field, "
1710 "value must be 0...3"));
1713 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1714 imm_expr
->X_op
= O_absent
;
1718 as_bad (_("bad compressed FUNCT field"
1719 " specifier 'CF%c'\n"),
1725 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1744 case '<': /* Shift amount, 0 - 31. */
1745 my_getExpression (imm_expr
, s
);
1746 check_absolute_expr (ip
, imm_expr
, FALSE
);
1747 if ((unsigned long) imm_expr
->X_add_number
> 31)
1748 as_bad (_("Improper shift amount (%lu)"),
1749 (unsigned long) imm_expr
->X_add_number
);
1750 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1751 imm_expr
->X_op
= O_absent
;
1755 case '>': /* Shift amount, 0 - (XLEN-1). */
1756 my_getExpression (imm_expr
, s
);
1757 check_absolute_expr (ip
, imm_expr
, FALSE
);
1758 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1759 as_bad (_("Improper shift amount (%lu)"),
1760 (unsigned long) imm_expr
->X_add_number
);
1761 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1762 imm_expr
->X_op
= O_absent
;
1766 case 'Z': /* CSRRxI immediate. */
1767 my_getExpression (imm_expr
, s
);
1768 check_absolute_expr (ip
, imm_expr
, FALSE
);
1769 if ((unsigned long) imm_expr
->X_add_number
> 31)
1770 as_bad (_("Improper CSRxI immediate (%lu)"),
1771 (unsigned long) imm_expr
->X_add_number
);
1772 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1773 imm_expr
->X_op
= O_absent
;
1777 case 'E': /* Control register. */
1778 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1779 INSERT_OPERAND (CSR
, *ip
, regno
);
1782 my_getExpression (imm_expr
, s
);
1783 check_absolute_expr (ip
, imm_expr
, TRUE
);
1784 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1785 as_bad (_("Improper CSR address (%lu)"),
1786 (unsigned long) imm_expr
->X_add_number
);
1787 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1788 imm_expr
->X_op
= O_absent
;
1793 case 'm': /* Rounding mode. */
1794 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1796 INSERT_OPERAND (RM
, *ip
, regno
);
1802 case 'Q': /* Fence predecessor/successor. */
1803 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1807 INSERT_OPERAND (PRED
, *ip
, regno
);
1809 INSERT_OPERAND (SUCC
, *ip
, regno
);
1814 case 'd': /* Destination register. */
1815 case 's': /* Source register. */
1816 case 't': /* Target register. */
1817 case 'r': /* rs3. */
1818 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1824 /* Now that we have assembled one operand, we use the args
1825 string to figure out where it goes in the instruction. */
1829 INSERT_OPERAND (RS1
, *ip
, regno
);
1832 INSERT_OPERAND (RD
, *ip
, regno
);
1835 INSERT_OPERAND (RS2
, *ip
, regno
);
1838 INSERT_OPERAND (RS3
, *ip
, regno
);
1845 case 'D': /* Floating point rd. */
1846 case 'S': /* Floating point rs1. */
1847 case 'T': /* Floating point rs2. */
1848 case 'U': /* Floating point rs1 and rs2. */
1849 case 'R': /* Floating point rs3. */
1850 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1858 INSERT_OPERAND (RD
, *ip
, regno
);
1861 INSERT_OPERAND (RS1
, *ip
, regno
);
1864 INSERT_OPERAND (RS1
, *ip
, regno
);
1867 INSERT_OPERAND (RS2
, *ip
, regno
);
1870 INSERT_OPERAND (RS3
, *ip
, regno
);
1879 my_getExpression (imm_expr
, s
);
1880 if (imm_expr
->X_op
!= O_big
1881 && imm_expr
->X_op
!= O_constant
)
1883 normalize_constant_expr (imm_expr
);
1888 my_getExpression (imm_expr
, s
);
1889 normalize_constant_expr (imm_expr
);
1890 /* The 'A' format specifier must be a symbol. */
1891 if (imm_expr
->X_op
!= O_symbol
)
1893 *imm_reloc
= BFD_RELOC_32
;
1898 my_getExpression (imm_expr
, s
);
1899 normalize_constant_expr (imm_expr
);
1900 /* The 'B' format specifier must be a symbol or a constant. */
1901 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1903 if (imm_expr
->X_op
== O_symbol
)
1904 *imm_reloc
= BFD_RELOC_32
;
1908 case 'j': /* Sign-extended immediate. */
1909 p
= percent_op_itype
;
1910 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1912 case 'q': /* Store displacement. */
1913 p
= percent_op_stype
;
1914 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1916 case 'o': /* Load displacement. */
1917 p
= percent_op_itype
;
1918 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1920 case '1': /* 4-operand add, must be %tprel_add. */
1921 p
= percent_op_rtype
;
1923 case '0': /* AMO "displacement," which must be zero. */
1924 p
= percent_op_null
;
1926 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1929 /* If this value won't fit into a 16 bit offset, then go
1930 find a macro that will generate the 32 bit offset
1932 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1934 normalize_constant_expr (imm_expr
);
1935 if (imm_expr
->X_op
!= O_constant
1936 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1938 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1939 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1946 case 'p': /* PC-relative offset. */
1948 *imm_reloc
= BFD_RELOC_12_PCREL
;
1949 my_getExpression (imm_expr
, s
);
1953 case 'u': /* Upper 20 bits. */
1954 p
= percent_op_utype
;
1955 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1957 if (imm_expr
->X_op
!= O_constant
)
1960 if (imm_expr
->X_add_number
< 0
1961 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1962 as_bad (_("lui expression not in range 0..1048575"));
1964 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1965 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1970 case 'a': /* 20-bit PC-relative offset. */
1972 my_getExpression (imm_expr
, s
);
1974 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1978 my_getExpression (imm_expr
, s
);
1980 if (strcmp (s
, "@plt") == 0)
1982 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1986 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1992 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
1993 || imm_expr
->X_op
!= O_constant
1994 || imm_expr
->X_add_number
< 0
1995 || imm_expr
->X_add_number
>= 128
1996 || (imm_expr
->X_add_number
& 0x3) != 3)
1998 as_bad (_("bad value for opcode field, "
1999 "value must be 0...127 and "
2000 "lower 2 bits must be 0x3"));
2004 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2005 imm_expr
->X_op
= O_absent
;
2009 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2010 || imm_expr
->X_op
!= O_constant
2011 || imm_expr
->X_add_number
< 0
2012 || imm_expr
->X_add_number
>= 3)
2014 as_bad (_("bad value for opcode field, "
2015 "value must be 0...2"));
2019 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2020 imm_expr
->X_op
= O_absent
;
2024 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2032 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2033 || imm_expr
->X_op
!= O_constant
2034 || imm_expr
->X_add_number
< 0
2035 || imm_expr
->X_add_number
>= 128)
2037 as_bad (_("bad value for funct7 field, "
2038 "value must be 0...127"));
2042 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2043 imm_expr
->X_op
= O_absent
;
2047 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2048 || imm_expr
->X_op
!= O_constant
2049 || imm_expr
->X_add_number
< 0
2050 || imm_expr
->X_add_number
>= 8)
2052 as_bad (_("bad value for funct3 field, "
2053 "value must be 0...7"));
2057 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2058 imm_expr
->X_op
= O_absent
;
2062 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2063 || imm_expr
->X_op
!= O_constant
2064 || imm_expr
->X_add_number
< 0
2065 || imm_expr
->X_add_number
>= 4)
2067 as_bad (_("bad value for funct2 field, "
2068 "value must be 0...3"));
2072 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2073 imm_expr
->X_op
= O_absent
;
2078 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2083 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2084 || imm_expr
->X_op
!= O_constant
2085 || imm_expr
->X_add_number
!= 0)
2088 imm_expr
->X_op
= O_absent
;
2092 as_fatal (_("internal error: bad argument type %c"), *args
);
2097 error
= _("illegal operands");
2101 /* Restore the character we might have clobbered above. */
2103 *(argsStart
- 1) = save_c
;
2109 md_assemble (char *str
)
2111 struct riscv_cl_insn insn
;
2112 expressionS imm_expr
;
2113 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2115 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2117 start_assemble
= TRUE
;
2121 as_bad ("%s `%s'", error
, str
);
2125 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2126 macro (&insn
, &imm_expr
, &imm_reloc
);
2128 append_insn (&insn
, &imm_expr
, imm_reloc
);
2132 md_atof (int type
, char *litP
, int *sizeP
)
2134 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2138 md_number_to_chars (char *buf
, valueT val
, int n
)
2140 number_to_chars_littleendian (buf
, val
, n
);
2143 const char *md_shortopts
= "O::g::G:";
2147 OPTION_MARCH
= OPTION_MD_BASE
,
2154 OPTION_NO_ARCH_ATTR
,
2158 struct option md_longopts
[] =
2160 {"march", required_argument
, NULL
, OPTION_MARCH
},
2161 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2162 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2163 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2164 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2165 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2166 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2167 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2168 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2170 {NULL
, no_argument
, NULL
, 0}
2172 size_t md_longopts_size
= sizeof (md_longopts
);
2175 FLOAT_ABI_DEFAULT
= -1,
2181 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2184 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2186 abi_xlen
= new_xlen
;
2187 float_abi
= new_float_abi
;
2192 md_parse_option (int c
, const char *arg
)
2197 riscv_set_arch (arg
);
2201 riscv_opts
.pic
= FALSE
;
2205 riscv_opts
.pic
= TRUE
;
2209 if (strcmp (arg
, "ilp32") == 0)
2210 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2211 else if (strcmp (arg
, "ilp32e") == 0)
2212 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2213 else if (strcmp (arg
, "ilp32f") == 0)
2214 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2215 else if (strcmp (arg
, "ilp32d") == 0)
2216 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2217 else if (strcmp (arg
, "ilp32q") == 0)
2218 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2219 else if (strcmp (arg
, "lp64") == 0)
2220 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2221 else if (strcmp (arg
, "lp64f") == 0)
2222 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2223 else if (strcmp (arg
, "lp64d") == 0)
2224 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2225 else if (strcmp (arg
, "lp64q") == 0)
2226 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2232 riscv_opts
.relax
= TRUE
;
2235 case OPTION_NO_RELAX
:
2236 riscv_opts
.relax
= FALSE
;
2239 case OPTION_ARCH_ATTR
:
2240 riscv_opts
.arch_attr
= TRUE
;
2243 case OPTION_NO_ARCH_ATTR
:
2244 riscv_opts
.arch_attr
= FALSE
;
2255 riscv_after_parse_args (void)
2259 if (strcmp (default_arch
, "riscv32") == 0)
2261 else if (strcmp (default_arch
, "riscv64") == 0)
2264 as_bad ("unknown default architecture `%s'", default_arch
);
2267 if (riscv_subsets
.head
== NULL
)
2268 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2270 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2271 riscv_set_rvc (FALSE
);
2272 if (riscv_subset_supports ("c"))
2273 riscv_set_rvc (TRUE
);
2275 /* Enable RVE if specified by the -march option. */
2276 riscv_set_rve (FALSE
);
2277 if (riscv_subset_supports ("e"))
2278 riscv_set_rve (TRUE
);
2280 /* Infer ABI from ISA if not specified on command line. */
2283 else if (abi_xlen
> xlen
)
2284 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2285 else if (abi_xlen
< xlen
)
2286 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2288 if (float_abi
== FLOAT_ABI_DEFAULT
)
2290 riscv_subset_t
*subset
;
2292 /* Assume soft-float unless D extension is present. */
2293 float_abi
= FLOAT_ABI_SOFT
;
2295 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2297 if (strcasecmp (subset
->name
, "D") == 0)
2298 float_abi
= FLOAT_ABI_DOUBLE
;
2299 if (strcasecmp (subset
->name
, "Q") == 0)
2300 float_abi
= FLOAT_ABI_QUAD
;
2305 elf_flags
|= EF_RISCV_RVE
;
2307 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2308 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2312 md_pcrel_from (fixS
*fixP
)
2314 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2317 /* Apply a fixup to the object file. */
2320 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2322 unsigned int subtype
;
2323 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2324 bfd_boolean relaxable
= FALSE
;
2328 /* Remember value for tc_gen_reloc. */
2329 fixP
->fx_addnumber
= *valP
;
2331 switch (fixP
->fx_r_type
)
2333 case BFD_RELOC_RISCV_HI20
:
2334 case BFD_RELOC_RISCV_LO12_I
:
2335 case BFD_RELOC_RISCV_LO12_S
:
2336 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2337 | bfd_getl32 (buf
), buf
);
2338 if (fixP
->fx_addsy
== NULL
)
2339 fixP
->fx_done
= TRUE
;
2343 case BFD_RELOC_RISCV_GOT_HI20
:
2344 case BFD_RELOC_RISCV_ADD8
:
2345 case BFD_RELOC_RISCV_ADD16
:
2346 case BFD_RELOC_RISCV_ADD32
:
2347 case BFD_RELOC_RISCV_ADD64
:
2348 case BFD_RELOC_RISCV_SUB6
:
2349 case BFD_RELOC_RISCV_SUB8
:
2350 case BFD_RELOC_RISCV_SUB16
:
2351 case BFD_RELOC_RISCV_SUB32
:
2352 case BFD_RELOC_RISCV_SUB64
:
2353 case BFD_RELOC_RISCV_RELAX
:
2356 case BFD_RELOC_RISCV_TPREL_HI20
:
2357 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2358 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2359 case BFD_RELOC_RISCV_TPREL_ADD
:
2363 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2364 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2365 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2366 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2367 if (fixP
->fx_addsy
!= NULL
)
2368 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2370 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2371 _("TLS relocation against a constant"));
2375 /* Use pc-relative relocation for FDE initial location.
2376 The symbol address in .eh_frame may be adjusted in
2377 _bfd_elf_discard_section_eh_frame, and the content of
2378 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2379 Therefore, we cannot insert a relocation whose addend symbol is
2380 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2381 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2382 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2383 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2384 && S_GET_VALUE (fixP
->fx_subsy
)
2385 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2387 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2388 fixP
->fx_subsy
= NULL
;
2395 case BFD_RELOC_RISCV_CFA
:
2396 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2398 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2399 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2400 fixP
->fx_next
->fx_subsy
= NULL
;
2401 fixP
->fx_next
->fx_offset
= 0;
2402 fixP
->fx_subsy
= NULL
;
2404 switch (fixP
->fx_r_type
)
2407 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2408 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2412 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2413 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2417 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2418 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2422 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2423 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2426 case BFD_RELOC_RISCV_CFA
:
2427 /* Load the byte to get the subtype. */
2428 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2429 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2432 case DW_CFA_advance_loc1
:
2433 fixP
->fx_where
= loc
+ 1;
2434 fixP
->fx_next
->fx_where
= loc
+ 1;
2435 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2436 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2439 case DW_CFA_advance_loc2
:
2441 fixP
->fx_next
->fx_size
= 2;
2442 fixP
->fx_where
= loc
+ 1;
2443 fixP
->fx_next
->fx_where
= loc
+ 1;
2444 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2445 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2448 case DW_CFA_advance_loc4
:
2450 fixP
->fx_next
->fx_size
= 4;
2451 fixP
->fx_where
= loc
;
2452 fixP
->fx_next
->fx_where
= loc
;
2453 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2454 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2458 if (subtype
< 0x80 && (subtype
& 0x40))
2460 /* DW_CFA_advance_loc */
2461 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2462 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2463 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2464 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2467 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2473 /* This case is unreachable. */
2480 /* If we are deleting this reloc entry, we must fill in the
2481 value now. This can happen if we have a .word which is not
2482 resolved when it appears but is later defined. */
2483 if (fixP
->fx_addsy
== NULL
)
2485 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2486 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2491 case BFD_RELOC_RISCV_JMP
:
2494 /* Fill in a tentative value to improve objdump readability. */
2495 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2496 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2497 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2501 case BFD_RELOC_12_PCREL
:
2504 /* Fill in a tentative value to improve objdump readability. */
2505 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2506 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2507 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2511 case BFD_RELOC_RISCV_RVC_BRANCH
:
2514 /* Fill in a tentative value to improve objdump readability. */
2515 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2516 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2517 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2521 case BFD_RELOC_RISCV_RVC_JUMP
:
2524 /* Fill in a tentative value to improve objdump readability. */
2525 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2526 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2527 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2531 case BFD_RELOC_RISCV_CALL
:
2532 case BFD_RELOC_RISCV_CALL_PLT
:
2536 case BFD_RELOC_RISCV_PCREL_HI20
:
2537 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2538 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2539 relaxable
= riscv_opts
.relax
;
2542 case BFD_RELOC_RISCV_ALIGN
:
2546 /* We ignore generic BFD relocations we don't know about. */
2547 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2548 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2551 if (fixP
->fx_subsy
!= NULL
)
2552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2553 _("unsupported symbol subtraction"));
2555 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2556 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2558 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2559 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2560 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2564 /* Because the value of .cfi_remember_state may changed after relaxation,
2565 we insert a fix to relocate it again in link-time. */
2568 riscv_pre_output_hook (void)
2570 const frchainS
*frch
;
2573 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2574 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2578 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2580 if (frag
->fr_type
== rs_cfa
)
2583 expressionS
*symval
;
2585 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2586 exp
.X_op
= O_subtract
;
2587 exp
.X_add_symbol
= symval
->X_add_symbol
;
2588 exp
.X_add_number
= 0;
2589 exp
.X_op_symbol
= symval
->X_op_symbol
;
2591 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2592 BFD_RELOC_RISCV_CFA
);
2599 /* This structure is used to hold a stack of .option values. */
2601 struct riscv_option_stack
2603 struct riscv_option_stack
*next
;
2604 struct riscv_set_options options
;
2607 static struct riscv_option_stack
*riscv_opts_stack
;
2609 /* Handle the .option pseudo-op. */
2612 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2614 char *name
= input_line_pointer
, ch
;
2616 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2617 ++input_line_pointer
;
2618 ch
= *input_line_pointer
;
2619 *input_line_pointer
= '\0';
2621 if (strcmp (name
, "rvc") == 0)
2622 riscv_set_rvc (TRUE
);
2623 else if (strcmp (name
, "norvc") == 0)
2624 riscv_set_rvc (FALSE
);
2625 else if (strcmp (name
, "pic") == 0)
2626 riscv_opts
.pic
= TRUE
;
2627 else if (strcmp (name
, "nopic") == 0)
2628 riscv_opts
.pic
= FALSE
;
2629 else if (strcmp (name
, "relax") == 0)
2630 riscv_opts
.relax
= TRUE
;
2631 else if (strcmp (name
, "norelax") == 0)
2632 riscv_opts
.relax
= FALSE
;
2633 else if (strcmp (name
, "push") == 0)
2635 struct riscv_option_stack
*s
;
2637 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2638 s
->next
= riscv_opts_stack
;
2639 s
->options
= riscv_opts
;
2640 riscv_opts_stack
= s
;
2642 else if (strcmp (name
, "pop") == 0)
2644 struct riscv_option_stack
*s
;
2646 s
= riscv_opts_stack
;
2648 as_bad (_(".option pop with no .option push"));
2651 riscv_opts
= s
->options
;
2652 riscv_opts_stack
= s
->next
;
2658 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2660 *input_line_pointer
= ch
;
2661 demand_empty_rest_of_line ();
2664 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2665 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2666 use in DWARF debug information. */
2669 s_dtprel (int bytes
)
2676 if (ex
.X_op
!= O_symbol
)
2678 as_bad (_("Unsupported use of %s"), (bytes
== 8
2681 ignore_rest_of_line ();
2684 p
= frag_more (bytes
);
2685 md_number_to_chars (p
, 0, bytes
);
2686 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2688 ? BFD_RELOC_RISCV_TLS_DTPREL64
2689 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2691 demand_empty_rest_of_line ();
2694 /* Handle the .bss pseudo-op. */
2697 s_bss (int ignore ATTRIBUTE_UNUSED
)
2699 subseg_set (bss_section
, 0);
2700 demand_empty_rest_of_line ();
2704 riscv_make_nops (char *buf
, bfd_vma bytes
)
2708 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2709 means we are not within a valid instruction sequence. It is thus safe
2710 to use a zero byte, even though that is not a valid instruction. */
2714 /* Use at most one 2-byte NOP. */
2715 if ((bytes
- i
) % 4 == 2)
2717 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2721 /* Fill the remainder with 4-byte NOPs. */
2722 for ( ; i
< bytes
; i
+= 4)
2723 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2726 /* Called from md_do_align. Used to create an alignment frag in a
2727 code section by emitting a worst-case NOP sequence that the linker
2728 will later relax to the correct number of NOPs. We can't compute
2729 the correct alignment now because of other linker relaxations. */
2732 riscv_frag_align_code (int n
)
2734 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2735 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2736 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2740 /* If we are moving to a smaller alignment than the instruction size, then no
2741 alignment is required. */
2742 if (bytes
<= insn_alignment
)
2745 /* When not relaxing, riscv_handle_align handles code alignment. */
2746 if (!riscv_opts
.relax
)
2749 nops
= frag_more (worst_case_bytes
);
2751 ex
.X_op
= O_constant
;
2752 ex
.X_add_number
= worst_case_bytes
;
2754 riscv_make_nops (nops
, worst_case_bytes
);
2756 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2757 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2762 /* Implement HANDLE_ALIGN. */
2765 riscv_handle_align (fragS
*fragP
)
2767 switch (fragP
->fr_type
)
2770 /* When relaxing, riscv_frag_align_code handles code alignment. */
2771 if (!riscv_opts
.relax
)
2773 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2774 - fragP
->fr_address
- fragP
->fr_fix
);
2775 /* We have 4 byte uncompressed nops. */
2776 bfd_signed_vma size
= 4;
2777 bfd_signed_vma excess
= bytes
% size
;
2778 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2783 /* Insert zeros or compressed nops to get 4 byte alignment. */
2786 riscv_make_nops (p
, excess
);
2787 fragP
->fr_fix
+= excess
;
2791 /* Insert variable number of 4 byte uncompressed nops. */
2792 riscv_make_nops (p
, size
);
2793 fragP
->fr_var
= size
;
2803 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2805 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2808 /* Translate internal representation of relocation info to BFD target
2812 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2814 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2816 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2817 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2818 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2819 reloc
->addend
= fixp
->fx_addnumber
;
2821 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2822 if (reloc
->howto
== NULL
)
2824 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2825 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2827 /* We don't have R_RISCV_8/16, but for this special case,
2828 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2832 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2833 _("cannot represent %s relocation in object file"),
2834 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2842 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2844 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2846 offsetT old_var
= fragp
->fr_var
;
2847 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2848 return fragp
->fr_var
- old_var
;
2854 /* Expand far branches to multi-instruction sequences. */
2857 md_convert_frag_branch (fragS
*fragp
)
2865 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2867 exp
.X_op
= O_symbol
;
2868 exp
.X_add_symbol
= fragp
->fr_symbol
;
2869 exp
.X_add_number
= fragp
->fr_offset
;
2871 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2873 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2875 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2879 /* Expand the RVC branch into a RISC-V one. */
2880 insn
= bfd_getl16 (buf
);
2881 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2882 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2884 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2885 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2886 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2887 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2888 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2889 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2892 bfd_putl32 (insn
, buf
);
2896 /* Invert the branch condition. Branch over the jump. */
2897 insn
= bfd_getl16 (buf
);
2898 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2899 insn
|= ENCODE_RVC_B_IMM (6);
2900 bfd_putl16 (insn
, buf
);
2905 /* Just keep the RVC branch. */
2906 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2907 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2908 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2909 2, &exp
, FALSE
, reloc
);
2918 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2921 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2923 /* Invert the branch condition. Branch over the jump. */
2924 insn
= bfd_getl32 (buf
);
2925 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2926 insn
|= ENCODE_SBTYPE_IMM (8);
2927 md_number_to_chars ((char *) buf
, insn
, 4);
2931 /* Jump to the target. */
2932 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2933 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2934 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2939 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2940 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2941 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2942 4, &exp
, FALSE
, reloc
);
2951 fixp
->fx_file
= fragp
->fr_file
;
2952 fixp
->fx_line
= fragp
->fr_line
;
2954 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2955 + fragp
->fr_fix
+ fragp
->fr_var
);
2957 fragp
->fr_fix
+= fragp
->fr_var
;
2960 /* Relax a machine dependent frag. This returns the amount by which
2961 the current size of the frag should change. */
2964 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2967 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2968 md_convert_frag_branch (fragp
);
2972 md_show_usage (FILE *stream
)
2974 fprintf (stream
, _("\
2976 -fpic generate position-independent code\n\
2977 -fno-pic don't generate position-independent code (default)\n\
2978 -march=ISA set the RISC-V architecture\n\
2979 -mabi=ABI set the RISC-V ABI\n\
2980 -mrelax enable relax (default)\n\
2981 -mno-relax disable relax\n\
2982 -march-attr generate RISC-V arch attribute\n\
2983 -mno-arch-attr don't generate RISC-V arch attribute\n\
2987 /* Standard calling conventions leave the CFA at SP on entry. */
2989 riscv_cfi_frame_initial_instructions (void)
2991 cfi_add_CFA_def_cfa_register (X_SP
);
2995 tc_riscv_regname_to_dw2regnum (char *regname
)
2999 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3002 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3005 as_bad (_("unknown register `%s'"), regname
);
3010 riscv_elf_final_processing (void)
3012 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3015 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3016 since these directives break relaxation when used with symbol deltas. */
3019 s_riscv_leb128 (int sign
)
3022 char *save_in
= input_line_pointer
;
3025 if (exp
.X_op
!= O_constant
)
3026 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3027 demand_empty_rest_of_line ();
3029 input_line_pointer
= save_in
;
3030 return s_leb128 (sign
);
3033 /* Parse the .insn directive. */
3036 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3038 char *str
= input_line_pointer
;
3039 struct riscv_cl_insn insn
;
3040 expressionS imm_expr
;
3041 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3044 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3045 ++input_line_pointer
;
3047 save_c
= *input_line_pointer
;
3048 *input_line_pointer
= '\0';
3050 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3051 &imm_reloc
, insn_type_hash
);
3055 as_bad ("%s `%s'", error
, str
);
3059 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3060 append_insn (&insn
, &imm_expr
, imm_reloc
);
3063 *input_line_pointer
= save_c
;
3064 demand_empty_rest_of_line ();
3067 /* Update arch attributes. */
3070 riscv_write_out_arch_attr (void)
3072 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3074 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3076 xfree ((void *)arch_str
);
3079 /* Add the default contents for the .riscv.attributes section. */
3082 riscv_set_public_attributes (void)
3084 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3085 /* Re-write arch attribute to normalize the arch string. */
3086 riscv_write_out_arch_attr ();
3089 /* Called after all assembly has been done. */
3094 riscv_set_public_attributes ();
3097 /* Given a symbolic attribute NAME, return the proper integer value.
3098 Returns -1 if the attribute is not known. */
3101 riscv_convert_symbolic_attribute (const char *name
)
3110 /* When you modify this table you should
3111 also modify the list in doc/c-riscv.texi. */
3112 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3116 T(priv_spec_revision
),
3117 T(unaligned_access
),
3127 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3128 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3129 return attribute_table
[i
].tag
;
3134 /* Parse a .attribute directive. */
3137 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3139 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3141 if (tag
== Tag_RISCV_arch
)
3143 unsigned old_xlen
= xlen
;
3145 explicit_arch_attr
= TRUE
;
3146 obj_attribute
*attr
;
3147 attr
= elf_known_obj_attributes_proc (stdoutput
);
3148 if (!start_assemble
)
3149 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3151 as_fatal (_(".attribute arch must set before any instructions"));
3153 if (old_xlen
!= xlen
)
3155 /* We must re-init bfd again if xlen is changed. */
3156 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3157 bfd_find_target (riscv_target_format (), stdoutput
);
3159 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3160 as_warn (_("Could not set architecture and machine"));
3165 /* Pseudo-op table. */
3167 static const pseudo_typeS riscv_pseudo_table
[] =
3169 /* RISC-V-specific pseudo-ops. */
3170 {"option", s_riscv_option
, 0},
3174 {"dtprelword", s_dtprel
, 4},
3175 {"dtpreldword", s_dtprel
, 8},
3177 {"uleb128", s_riscv_leb128
, 0},
3178 {"sleb128", s_riscv_leb128
, 1},
3179 {"insn", s_riscv_insn
, 0},
3180 {"attribute", s_riscv_attribute
, 0},
3186 riscv_pop_insert (void)
3188 extern void pop_insert (const pseudo_typeS
*);
3190 pop_insert (riscv_pseudo_table
);