1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* careful, this file includes data *declarations* */
28 #include "opcode/sparc.h"
30 static void sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
32 /* Current architecture. We don't bump up unless necessary. */
33 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
35 /* The maximum architecture level we can bump up to.
36 In a 32 bit environment, don't allow bumping up to v9 by default.
37 The native assembler works this way. The user is required to pass
38 an explicit argument before we'll create v9 object files. However, if
39 we don't see any v9 insns, a v9 object file is not created. */
41 static enum sparc_opcode_arch_val max_architecture
= SPARC_OPCODE_ARCH_V9
;
43 /* ??? This should be V8, but sparclite support was added by making it the
44 default. GCC now passes -Asparclite, so maybe sometime in the future
45 we can set this to V8. */
46 static enum sparc_opcode_arch_val max_architecture
= SPARC_OPCODE_ARCH_SPARCLITE
;
49 static int architecture_requested
;
50 static int warn_on_bump
;
52 /* If warn_on_bump and the needed architecture is higher than this
53 architecture, issue a warning. */
54 static enum sparc_opcode_arch_val warn_after_architecture
;
56 /* Non-zero if we are generating PIC code. */
59 /* Non-zero if we should give an error when misaligned data is seen. */
60 static int enforce_aligned_data
;
62 extern int target_big_endian
;
64 /* V9 has big and little endian data, but instructions are always big endian.
65 The sparclet has bi-endian support but both data and insns have the same
66 endianness. Global `target_big_endian' is used for data. The following
67 macro is used for instructions. */
68 #define INSN_BIG_ENDIAN (target_big_endian \
69 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
71 /* handle of the OPCODE hash table */
72 static struct hash_control
*op_hash
;
74 static void s_data1
PARAMS ((void));
75 static void s_seg
PARAMS ((int));
76 static void s_proc
PARAMS ((int));
77 static void s_reserve
PARAMS ((int));
78 static void s_common
PARAMS ((int));
79 static void s_empty
PARAMS ((int));
80 static void s_uacons
PARAMS ((int));
82 const pseudo_typeS md_pseudo_table
[] =
84 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
85 {"common", s_common
, 0},
86 {"empty", s_empty
, 0},
87 {"global", s_globl
, 0},
89 {"optim", s_ignore
, 0},
91 {"reserve", s_reserve
, 0},
96 {"uahalf", s_uacons
, 2},
97 {"uaword", s_uacons
, 4},
98 {"uaxword", s_uacons
, 8},
100 /* these are specific to sparc/svr4 */
101 {"pushsection", obj_elf_section
, 0},
102 {"popsection", obj_elf_previous
, 0},
103 {"2byte", s_uacons
, 2},
104 {"4byte", s_uacons
, 4},
105 {"8byte", s_uacons
, 8},
110 const int md_reloc_size
= 12; /* Size of relocation record */
112 /* This array holds the chars that always start a comment. If the
113 pre-processor is disabled, these aren't very useful */
114 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
116 /* This array holds the chars that only start a comment at the beginning of
117 a line. If the line seems to have the form '# 123 filename'
118 .line and .file directives will appear in the pre-processed output */
119 /* Note that input_file.c hand checks for '#' at the beginning of the
120 first line of the input file. This is because the compiler outputs
121 #NO_APP at the beginning of its output. */
122 /* Also note that comments started like this one will always
123 work if '/' isn't otherwise defined. */
124 const char line_comment_chars
[] = "#";
126 const char line_separator_chars
[] = "";
128 /* Chars that can be used to separate mant from exp in floating point nums */
129 const char EXP_CHARS
[] = "eE";
131 /* Chars that mean this number is a floating point constant */
134 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
136 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
137 changed in read.c. Ideally it shouldn't have to know about it at all,
138 but nothing is ideal around here. */
140 static unsigned char octal
[256];
141 #define isoctal(c) octal[(unsigned char) (c)]
142 static unsigned char toHex
[256];
147 unsigned long opcode
;
148 struct nlist
*nlistp
;
151 bfd_reloc_code_real_type reloc
;
154 struct sparc_it the_insn
, set_insn
;
156 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
159 in_signed_range (val
, max
)
160 bfd_signed_vma val
, max
;
171 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
172 (e.g. -15 to +31). */
175 in_bitfield_range (val
, max
)
176 bfd_signed_vma val
, max
;
182 if (val
< ~(max
>> 1))
196 for (i
= 0; (mask
& 1) == 0; ++i
)
201 /* Implement big shift right. */
207 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
208 as_fatal ("Support for 64-bit arithmetic not compiled in.");
209 return val
>> amount
;
213 static void print_insn
PARAMS ((struct sparc_it
*insn
));
215 static int getExpression
PARAMS ((char *str
));
217 static char *expr_end
;
218 static int special_case
;
221 * Instructions that require wierd handling because they're longer than
224 #define SPECIAL_CASE_SET 1
225 #define SPECIAL_CASE_SETSW 2
226 #define SPECIAL_CASE_SETX 3
227 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
228 #define SPECIAL_CASE_FDIV 4
230 /* Bit masks of various insns. */
231 #define NOP_INSN 0x01000000
232 #define OR_INSN 0x80100000
233 #define FMOVS_INSN 0x81A00020
234 #define SETHI_INSN 0x01000000
235 #define SLLX_INSN 0x81281000
236 #define SRA_INSN 0x81380000
238 /* The last instruction to be assembled. */
239 static const struct sparc_opcode
*last_insn
;
242 * sort of like s_lcomm
246 static int max_alignment
= 15;
261 name
= input_line_pointer
;
262 c
= get_symbol_end ();
263 p
= input_line_pointer
;
267 if (*input_line_pointer
!= ',')
269 as_bad ("Expected comma after name");
270 ignore_rest_of_line ();
274 ++input_line_pointer
;
276 if ((size
= get_absolute_expression ()) < 0)
278 as_bad ("BSS length (%d.) <0! Ignored.", size
);
279 ignore_rest_of_line ();
284 symbolP
= symbol_find_or_make (name
);
287 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
288 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
290 as_bad ("bad .reserve segment -- expected BSS segment");
294 if (input_line_pointer
[2] == '.')
295 input_line_pointer
+= 7;
297 input_line_pointer
+= 6;
300 if (*input_line_pointer
== ',')
302 ++input_line_pointer
;
305 if (*input_line_pointer
== '\n')
307 as_bad ("Missing alignment");
311 align
= get_absolute_expression ();
313 if (align
> max_alignment
)
315 align
= max_alignment
;
316 as_warn ("Alignment too large: %d. assumed.", align
);
322 as_warn ("Alignment negative. 0 assumed.");
325 record_alignment (bss_section
, align
);
327 /* convert to a power of 2 alignment */
328 for (temp
= 0; (align
& 1) == 0; align
>>= 1, ++temp
);;
332 as_bad ("Alignment not a power of 2");
333 ignore_rest_of_line ();
335 } /* not a power of two */
338 } /* if has optional alignment */
342 if (!S_IS_DEFINED (symbolP
)
344 && S_GET_OTHER (symbolP
) == 0
345 && S_GET_DESC (symbolP
) == 0
352 segT current_seg
= now_seg
;
353 subsegT current_subseg
= now_subseg
;
355 subseg_set (bss_section
, 1); /* switch to bss */
358 frag_align (align
, 0, 0); /* do alignment */
360 /* detach from old frag */
361 if (S_GET_SEGMENT(symbolP
) == bss_section
)
362 symbolP
->sy_frag
->fr_symbol
= NULL
;
364 symbolP
->sy_frag
= frag_now
;
365 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
369 S_SET_SEGMENT (symbolP
, bss_section
);
371 subseg_set (current_seg
, current_subseg
);
376 as_warn("Ignoring attempt to re-define symbol %s",
377 S_GET_NAME (symbolP
));
378 } /* if not redefining */
380 demand_empty_rest_of_line ();
393 name
= input_line_pointer
;
394 c
= get_symbol_end ();
395 /* just after name is now '\0' */
396 p
= input_line_pointer
;
399 if (*input_line_pointer
!= ',')
401 as_bad ("Expected comma after symbol-name");
402 ignore_rest_of_line ();
405 input_line_pointer
++; /* skip ',' */
406 if ((temp
= get_absolute_expression ()) < 0)
408 as_bad (".COMMon length (%d.) <0! Ignored.", temp
);
409 ignore_rest_of_line ();
414 symbolP
= symbol_find_or_make (name
);
416 if (S_IS_DEFINED (symbolP
))
418 as_bad ("Ignoring attempt to re-define symbol");
419 ignore_rest_of_line ();
422 if (S_GET_VALUE (symbolP
) != 0)
424 if (S_GET_VALUE (symbolP
) != size
)
426 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
427 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
433 S_SET_VALUE (symbolP
, (valueT
) size
);
434 S_SET_EXTERNAL (symbolP
);
437 know (symbolP
->sy_frag
== &zero_address_frag
);
438 if (*input_line_pointer
!= ',')
440 as_bad ("Expected comma after common length");
441 ignore_rest_of_line ();
444 input_line_pointer
++;
446 if (*input_line_pointer
!= '"')
448 temp
= get_absolute_expression ();
450 if (temp
> max_alignment
)
452 temp
= max_alignment
;
453 as_warn ("Common alignment too large: %d. assumed", temp
);
459 as_warn ("Common alignment negative; 0 assumed");
470 old_subsec
= now_subseg
;
472 record_alignment (bss_section
, align
);
473 subseg_set (bss_section
, 0);
475 frag_align (align
, 0, 0);
476 if (S_GET_SEGMENT (symbolP
) == bss_section
)
477 symbolP
->sy_frag
->fr_symbol
= 0;
478 symbolP
->sy_frag
= frag_now
;
479 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
482 S_SET_SEGMENT (symbolP
, bss_section
);
483 S_CLEAR_EXTERNAL (symbolP
);
484 subseg_set (old_sec
, old_subsec
);
490 S_SET_VALUE (symbolP
, (valueT
) size
);
492 S_SET_ALIGN (symbolP
, temp
);
494 S_SET_EXTERNAL (symbolP
);
495 /* should be common, but this is how gas does it for now */
496 S_SET_SEGMENT (symbolP
, bfd_und_section_ptr
);
501 input_line_pointer
++;
502 /* @@ Some use the dot, some don't. Can we get some consistency?? */
503 if (*input_line_pointer
== '.')
504 input_line_pointer
++;
505 /* @@ Some say data, some say bss. */
506 if (strncmp (input_line_pointer
, "bss\"", 4)
507 && strncmp (input_line_pointer
, "data\"", 5))
509 while (*--input_line_pointer
!= '"')
511 input_line_pointer
--;
512 goto bad_common_segment
;
514 while (*input_line_pointer
++ != '"')
516 goto allocate_common
;
520 symbolP
->bsym
->flags
|= BSF_OBJECT
;
523 demand_empty_rest_of_line ();
528 p
= input_line_pointer
;
529 while (*p
&& *p
!= '\n')
533 as_bad ("bad .common segment %s", input_line_pointer
+ 1);
535 input_line_pointer
= p
;
536 ignore_rest_of_line ();
541 /* Handle the .empty pseudo-op. This supresses the warnings about
542 invalid delay slot usage. */
548 /* The easy way to implement is to just forget about the last
558 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
560 input_line_pointer
+= 6;
564 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
566 input_line_pointer
+= 6;
570 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
572 input_line_pointer
+= 7;
576 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
578 input_line_pointer
+= 5;
579 /* We only support 2 segments -- text and data -- for now, so
580 things in the "bss segment" will have to go into data for now.
581 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
582 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
585 as_bad ("Unknown segment type");
586 demand_empty_rest_of_line ();
592 subseg_set (data_section
, 1);
593 demand_empty_rest_of_line ();
600 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
602 ++input_line_pointer
;
604 ++input_line_pointer
;
607 /* This static variable is set by s_uacons to tell sparc_cons_align
608 that the expession does not need to be aligned. */
610 static int sparc_no_align_cons
= 0;
612 /* This handles the unaligned space allocation pseudo-ops, such as
613 .uaword. .uaword is just like .word, but the value does not need
620 /* Tell sparc_cons_align not to align this value. */
621 sparc_no_align_cons
= 1;
625 /* If the --enforce-aligned-data option is used, we require .word,
626 et. al., to be aligned correctly. We do it by setting up an
627 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
628 no unexpected alignment was introduced.
630 The SunOS and Solaris native assemblers enforce aligned data by
631 default. We don't want to do that, because gcc can deliberately
632 generate misaligned data if the packed attribute is used. Instead,
633 we permit misaligned data by default, and permit the user to set an
634 option to check for it. */
637 sparc_cons_align (nbytes
)
643 /* Only do this if we are enforcing aligned data. */
644 if (! enforce_aligned_data
)
647 if (sparc_no_align_cons
)
649 /* This is an unaligned pseudo-op. */
650 sparc_no_align_cons
= 0;
655 while ((nbytes
& 1) == 0)
664 if (now_seg
== absolute_section
)
666 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
667 as_bad ("misaligned data");
671 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
672 (symbolS
*) NULL
, (long) nalign
, (char *) NULL
);
674 record_alignment (now_seg
, nalign
);
677 /* This is where we do the unexpected alignment check. */
680 sparc_handle_align (fragp
)
683 if (fragp
->fr_type
== rs_align_code
684 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
685 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "misaligned data");
688 /* sparc64 priviledged registers */
690 struct priv_reg_entry
696 struct priv_reg_entry priv_reg_table
[] =
715 {"", -1}, /* end marker */
720 struct priv_reg_entry
*p
, *q
;
722 return strcmp (q
->name
, p
->name
);
725 /* This function is called once, at assembler startup time. It should
726 set up all the tables, etc. that the MD part of the assembler will need. */
731 register const char *retval
= NULL
;
733 register unsigned int i
= 0;
735 op_hash
= hash_new ();
737 while (i
< sparc_num_opcodes
)
739 const char *name
= sparc_opcodes
[i
].name
;
740 retval
= hash_insert (op_hash
, name
, &sparc_opcodes
[i
]);
743 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
744 sparc_opcodes
[i
].name
, retval
);
749 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
751 fprintf (stderr
, "internal error: losing opcode: `%s' \"%s\"\n",
752 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
757 while (i
< sparc_num_opcodes
758 && !strcmp (sparc_opcodes
[i
].name
, name
));
762 as_fatal ("Broken assembler. No assembly attempted.");
764 for (i
= '0'; i
< '8'; ++i
)
766 for (i
= '0'; i
<= '9'; ++i
)
768 for (i
= 'a'; i
<= 'f'; ++i
)
769 toHex
[i
] = i
+ 10 - 'a';
770 for (i
= 'A'; i
<= 'F'; ++i
)
771 toHex
[i
] = i
+ 10 - 'A';
773 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
774 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
776 /* If -bump, record the architecture level at which we start issuing
777 warnings. The behaviour is different depending upon whether an
778 architecture was explicitly specified. If it wasn't, we issue warnings
779 for all upwards bumps. If it was, we don't start issuing warnings until
780 we need to bump beyond the requested architecture or when we bump between
781 conflicting architectures. */
784 && architecture_requested
)
786 /* `max_architecture' records the requested architecture.
787 Issue warnings if we go above it. */
788 warn_after_architecture
= max_architecture
;
790 /* Find the highest architecture level that doesn't conflict with
791 the requested one. */
792 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
793 max_architecture
> warn_after_architecture
;
795 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
796 warn_after_architecture
))
801 /* Called after all assembly has been done. */
807 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
808 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
810 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
812 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
813 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
814 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
815 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
816 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
817 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
820 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
821 be but for now it is (since that's the way it's always been
823 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
828 /* Utility to output one insn. */
831 output_insn (insn
, the_insn
)
832 const struct sparc_opcode
*insn
;
833 struct sparc_it
*the_insn
;
835 char *toP
= frag_more (4);
837 /* put out the opcode */
839 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
841 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
843 /* put out the symbol-dependent stuff */
844 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
846 fix_new_exp (frag_now
, /* which frag */
847 (toP
- frag_now
->fr_literal
), /* where */
861 const struct sparc_opcode
*insn
;
865 sparc_ip (str
, &insn
);
867 /* We warn about attempts to put a floating point branch in a delay slot. */
870 && (insn
->flags
& F_FBR
) != 0
871 && (last_insn
->flags
& F_DELAYED
) != 0)
872 as_warn ("FP branch in delay slot");
874 /* SPARC before v9 requires a nop instruction between a floating
875 point instruction and a floating point branch. We insert one
876 automatically, with a warning. */
877 if (max_architecture
< SPARC_OPCODE_ARCH_V9
880 && (insn
->flags
& F_FBR
) != 0
881 && (last_insn
->flags
& F_FLOAT
) != 0)
883 struct sparc_it nop_insn
;
885 nop_insn
.opcode
= NOP_INSN
;
886 nop_insn
.reloc
= BFD_RELOC_NONE
;
887 output_insn (insn
, &nop_insn
);
888 as_warn ("FP branch preceded by FP instruction; NOP inserted");
891 switch (special_case
)
895 output_insn (insn
, &the_insn
);
898 case SPECIAL_CASE_SET
:
902 /* "set" is not defined for negative numbers in v9: it doesn't yield
903 what you expect it to. */
904 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
)
905 && the_insn
.exp
.X_op
== O_constant
)
907 if (the_insn
.exp
.X_add_number
< 0)
908 as_warn ("set: used with negative number");
909 else if (the_insn
.exp
.X_add_number
> 0xffffffff)
910 as_warn ("set: number larger than 4294967295");
913 /* See if operand is absolute and small; skip sethi if so. */
914 if (the_insn
.exp
.X_op
!= O_constant
915 || the_insn
.exp
.X_add_number
>= (1 << 12)
916 || the_insn
.exp
.X_add_number
< -(1 << 12))
918 output_insn (insn
, &the_insn
);
921 /* See if operand has no low-order bits; skip OR if so. */
922 if (the_insn
.exp
.X_op
!= O_constant
923 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
926 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
927 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
930 | (the_insn
.exp
.X_add_number
931 & (need_hi22_p
? 0x3ff : 0x1fff)));
932 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
935 output_insn (insn
, &the_insn
);
940 case SPECIAL_CASE_SETSW
:
942 /* FIXME: Not finished. */
946 case SPECIAL_CASE_SETX
:
948 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
949 int upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
950 int lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
952 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
953 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
954 /* Output directly to dst reg if lower 32 bits are all zero. */
955 int upper_dstreg
= (the_insn
.exp
.X_op
== O_constant
956 && lower32
== 0) ? dstreg
: tmpreg
;
957 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
959 /* The tmp reg should not be the dst reg. */
960 if (tmpreg
== dstreg
)
961 as_warn ("setx: temporary register same as destination register");
963 /* Reset X_add_number, we've extracted it as upper32/lower32.
964 Otherwise fixup_segment will complain about not being able to
965 write an 8 byte number in a 4 byte field. */
966 the_insn
.exp
.X_add_number
= 0;
968 /* ??? Obviously there are other optimizations we can do
969 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
970 doing some of these. Later. If you do change things, try to
971 change all of this to be table driven as well. */
973 /* What to output depends on the number if it's constant.
974 Compute that first, then output what we've decided upon. */
975 if (the_insn
.exp
.X_op
!= O_constant
)
976 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
979 /* Only need hh22 if `or' insn can't handle constant. */
980 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
983 /* Does bottom part (after sethi) have bits? */
984 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
985 /* No hh22, but does upper32 still have bits we can't set
989 && (upper32
!= -1 || lower32
>= 0)))
992 /* If the lower half is all zero, we build the upper half directly
995 /* Need lower half if number is zero. */
996 || (! need_hh22_p
&& ! need_hm10_p
))
998 /* No need for sethi if `or' insn can handle constant. */
999 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1000 /* Note that we can't use a negative constant in the `or'
1001 insn unless the upper 32 bits are all ones. */
1002 || (lower32
< 0 && upper32
!= -1))
1005 /* Does bottom part (after sethi) have bits? */
1006 if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1008 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1009 /* Need `or' if we didn't set anything else. */
1010 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1017 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1018 | ((upper32
>> 10) & 0x3fffff));
1019 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1020 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1021 output_insn (insn
, &the_insn
);
1026 the_insn
.opcode
= (OR_INSN
1027 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1031 & (need_hh22_p
? 0x3ff : 0x1fff)));
1032 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1033 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1034 output_insn (insn
, &the_insn
);
1039 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1040 | ((lower32
>> 10) & 0x3fffff));
1041 the_insn
.reloc
= BFD_RELOC_HI22
;
1042 output_insn (insn
, &the_insn
);
1047 /* FIXME: One nice optimization to do here is to OR the low part
1048 with the highpart if hi22 isn't needed and the low part is
1050 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1054 & (need_hi22_p
? 0x3ff : 0x1fff)));
1055 the_insn
.reloc
= BFD_RELOC_LO10
;
1056 output_insn (insn
, &the_insn
);
1059 /* If we needed to build the upper part, shift it into place. */
1060 if (need_hh22_p
|| need_hm10_p
)
1062 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1064 the_insn
.reloc
= BFD_RELOC_NONE
;
1065 output_insn (insn
, &the_insn
);
1068 /* If we needed to build both upper and lower parts, OR them together. */
1069 if ((need_hh22_p
|| need_hm10_p
)
1070 && (need_hi22_p
|| need_lo10_p
))
1072 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1074 the_insn
.reloc
= BFD_RELOC_NONE
;
1075 output_insn (insn
, &the_insn
);
1077 /* We didn't need both regs, but we may have to sign extend lower32. */
1078 else if (need_hi22_p
&& upper32
== -1)
1080 the_insn
.opcode
= (SRA_INSN
| RS1 (dstreg
) | RD (dstreg
)
1082 the_insn
.reloc
= BFD_RELOC_NONE
;
1083 output_insn (insn
, &the_insn
);
1088 case SPECIAL_CASE_FDIV
:
1090 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1092 output_insn (insn
, &the_insn
);
1094 /* According to information leaked from Sun, the "fdiv" instructions
1095 on early SPARC machines would produce incorrect results sometimes.
1096 The workaround is to add an fmovs of the destination register to
1097 itself just after the instruction. This was true on machines
1098 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1099 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1100 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1101 output_insn (insn
, &the_insn
);
1106 as_fatal ("failed special case insn sanity check");
1110 /* Parse an argument that can be expressed as a keyword.
1111 (eg: #StoreStore or %ccfr).
1112 The result is a boolean indicating success.
1113 If successful, INPUT_POINTER is updated. */
1116 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
1117 int (*lookup_fn
) ();
1118 char **input_pointerP
;
1124 p
= *input_pointerP
;
1125 for (q
= p
+ (*p
== '#' || *p
== '%'); isalpha (*q
) || *q
== '_'; ++q
)
1129 value
= (*lookup_fn
) (p
);
1134 *input_pointerP
= q
;
1138 /* Parse an argument that is a constant expression.
1139 The result is a boolean indicating success. */
1142 parse_const_expr_arg (input_pointerP
, valueP
)
1143 char **input_pointerP
;
1146 char *save
= input_line_pointer
;
1149 input_line_pointer
= *input_pointerP
;
1150 /* The next expression may be something other than a constant
1151 (say if we're not processing the right variant of the insn).
1152 Don't call expression unless we're sure it will succeed as it will
1153 signal an error (which we want to defer until later). */
1154 /* FIXME: It might be better to define md_operand and have it recognize
1155 things like %asi, etc. but continuing that route through to the end
1156 is a lot of work. */
1157 if (*input_line_pointer
== '%')
1159 input_line_pointer
= save
;
1163 *input_pointerP
= input_line_pointer
;
1164 input_line_pointer
= save
;
1165 if (exp
.X_op
!= O_constant
)
1167 *valueP
= exp
.X_add_number
;
1172 sparc_ip (str
, pinsn
)
1174 const struct sparc_opcode
**pinsn
;
1176 char *error_message
= "";
1180 const struct sparc_opcode
*insn
;
1182 unsigned long opcode
;
1183 unsigned int mask
= 0;
1186 long immediate_max
= 0;
1189 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3'); ++s
)
1207 as_fatal ("Unknown opcode: `%s'", str
);
1209 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1213 as_bad ("Unknown opcode: `%s'", str
);
1224 opcode
= insn
->match
;
1225 memset (&the_insn
, '\0', sizeof (the_insn
));
1226 the_insn
.reloc
= BFD_RELOC_NONE
;
1230 * Build the opcode, checking as we go to make
1231 * sure that the operands match
1233 for (args
= insn
->args
;; ++args
)
1241 /* Parse a series of masks. */
1248 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1251 error_message
= ": invalid membar mask name";
1255 while (*s
== ' ') { ++s
; continue; }
1256 if (*s
== '|' || *s
== '+')
1258 while (*s
== ' ') { ++s
; continue; }
1263 if (! parse_const_expr_arg (&s
, &kmask
))
1265 error_message
= ": invalid membar mask expression";
1268 if (kmask
< 0 || kmask
> 127)
1270 error_message
= ": invalid membar mask number";
1275 opcode
|= MEMBAR (kmask
);
1283 /* Parse a prefetch function. */
1286 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1288 error_message
= ": invalid prefetch function name";
1294 if (! parse_const_expr_arg (&s
, &fcn
))
1296 error_message
= ": invalid prefetch function expression";
1299 if (fcn
< 0 || fcn
> 31)
1301 error_message
= ": invalid prefetch function number";
1311 /* Parse a sparc64 privileged register. */
1314 struct priv_reg_entry
*p
= priv_reg_table
;
1315 unsigned int len
= 9999999; /* init to make gcc happy */
1318 while (p
->name
[0] > s
[0])
1320 while (p
->name
[0] == s
[0])
1322 len
= strlen (p
->name
);
1323 if (strncmp (p
->name
, s
, len
) == 0)
1327 if (p
->name
[0] != s
[0])
1329 error_message
= ": unrecognizable privileged register";
1333 opcode
|= (p
->regnum
<< 14);
1335 opcode
|= (p
->regnum
<< 25);
1341 error_message
= ": unrecognizable privileged register";
1347 if (strncmp (s
, "%asr", 4) == 0)
1355 while (isdigit (*s
))
1357 num
= num
* 10 + *s
- '0';
1361 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1363 if (num
< 16 || 31 < num
)
1365 error_message
= ": asr number must be between 16 and 31";
1371 if (num
< 0 || 31 < num
)
1373 error_message
= ": asr number must be between 0 and 31";
1378 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1383 error_message
= ": expecting %asrN";
1390 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1391 immediate_max
= 0x03FF;
1395 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1396 immediate_max
= 0x01FF;
1400 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1401 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1402 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1404 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1405 /* These fields are unsigned, but for upward compatibility,
1406 allow negative values as well. */
1407 immediate_max
= 0x1f;
1411 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1412 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1413 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1415 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1416 /* These fields are unsigned, but for upward compatibility,
1417 allow negative values as well. */
1418 immediate_max
= 0x3f;
1422 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1427 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1432 if (*s
== 'p' && s
[1] == 'n')
1440 if (*s
== 'p' && s
[1] == 't')
1452 if (strncmp (s
, "%icc", 4) == 0)
1464 if (strncmp (s
, "%xcc", 4) == 0)
1476 if (strncmp (s
, "%fcc0", 5) == 0)
1488 if (strncmp (s
, "%fcc1", 5) == 0)
1500 if (strncmp (s
, "%fcc2", 5) == 0)
1512 if (strncmp (s
, "%fcc3", 5) == 0)
1520 if (strncmp (s
, "%pc", 3) == 0)
1528 if (strncmp (s
, "%tick", 5) == 0)
1535 case '\0': /* end of args */
1554 case '[': /* these must match exactly */
1562 case '#': /* must be at least one digit */
1565 while (isdigit (*s
))
1573 case 'C': /* coprocessor state register */
1574 if (strncmp (s
, "%csr", 4) == 0)
1581 case 'b': /* next operand is a coprocessor register */
1584 if (*s
++ == '%' && *s
++ == 'c' && isdigit (*s
))
1589 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1603 opcode
|= mask
<< 14;
1611 opcode
|= mask
<< 25;
1617 case 'r': /* next operand must be a register */
1627 case 'f': /* frame pointer */
1635 case 'g': /* global register */
1636 if (isoctal (c
= *s
++))
1643 case 'i': /* in register */
1644 if (isoctal (c
= *s
++))
1646 mask
= c
- '0' + 24;
1651 case 'l': /* local register */
1652 if (isoctal (c
= *s
++))
1654 mask
= (c
- '0' + 16);
1659 case 'o': /* out register */
1660 if (isoctal (c
= *s
++))
1662 mask
= (c
- '0' + 8);
1667 case 's': /* stack pointer */
1675 case 'r': /* any register */
1676 if (!isdigit (c
= *s
++))
1693 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1709 /* Got the register, now figure out where
1710 it goes in the opcode. */
1714 opcode
|= mask
<< 14;
1722 opcode
|= mask
<< 25;
1726 opcode
|= (mask
<< 25) | (mask
<< 14);
1730 opcode
|= (mask
<< 25) | (mask
<< 0);
1736 case 'e': /* next operand is a floating point register */
1751 && ((format
= *s
) == 'f')
1754 for (mask
= 0; isdigit (*s
); ++s
)
1756 mask
= 10 * mask
+ (*s
- '0');
1757 } /* read the number */
1765 } /* register must be even numbered */
1773 } /* register must be multiple of 4 */
1777 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1778 error_message
= ": There are only 64 f registers; [0-63]";
1780 error_message
= ": There are only 32 f registers; [0-31]";
1783 else if (mask
>= 32)
1785 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1788 mask
-= 31; /* wrap high bit */
1792 error_message
= ": There are only 32 f registers; [0-31]";
1800 } /* if not an 'f' register. */
1807 opcode
|= RS1 (mask
);
1814 opcode
|= RS2 (mask
);
1820 opcode
|= RD (mask
);
1829 if (strncmp (s
, "%fsr", 4) == 0)
1836 case '0': /* 64 bit immediate (setx insn) */
1837 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1840 case 'h': /* high 22 bits */
1841 the_insn
.reloc
= BFD_RELOC_HI22
;
1844 case 'l': /* 22 bit PC relative immediate */
1845 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
1849 case 'L': /* 30 bit immediate */
1850 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
1854 case 'n': /* 22 bit immediate */
1855 the_insn
.reloc
= BFD_RELOC_SPARC22
;
1858 case 'i': /* 13 bit immediate */
1859 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1860 immediate_max
= 0x0FFF;
1869 if ((c
= s
[1]) == 'h' && s
[2] == 'i')
1871 the_insn
.reloc
= BFD_RELOC_HI22
;
1874 else if (c
== 'l' && s
[2] == 'o')
1876 the_insn
.reloc
= BFD_RELOC_LO10
;
1883 the_insn
.reloc
= BFD_RELOC_SPARC_HH22
;
1891 the_insn
.reloc
= BFD_RELOC_SPARC_HM10
;
1898 /* Note that if the getExpression() fails, we will still
1899 have created U entries in the symbol table for the
1900 'symbols' in the input string. Try not to create U
1901 symbols for registers, etc. */
1903 /* This stuff checks to see if the expression ends in
1904 +%reg. If it does, it removes the register from
1905 the expression, and re-sets 's' to point to the
1910 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
1912 if (s1
!= s
&& isdigit (s1
[-1]))
1914 if (s1
[-2] == '%' && s1
[-3] == '+')
1918 (void) getExpression (s
);
1923 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
1927 (void) getExpression (s
);
1934 (void) getExpression (s
);
1937 if (the_insn
.exp
.X_op
== O_constant
1938 && the_insn
.exp
.X_add_symbol
== 0
1939 && the_insn
.exp
.X_op_symbol
== 0)
1941 /* Handle %uhi/%ulo by moving the upper word to the lower
1942 one and pretending it's %hi/%lo. We also need to watch
1943 for %hi/%lo: the top word needs to be zeroed otherwise
1944 fixup_segment will complain the value is too big. */
1945 switch (the_insn
.reloc
)
1947 case BFD_RELOC_SPARC_HH22
:
1948 the_insn
.reloc
= BFD_RELOC_HI22
;
1949 the_insn
.exp
.X_add_number
= BSR (the_insn
.exp
.X_add_number
, 32);
1951 case BFD_RELOC_SPARC_HM10
:
1952 the_insn
.reloc
= BFD_RELOC_LO10
;
1953 the_insn
.exp
.X_add_number
= BSR (the_insn
.exp
.X_add_number
, 32);
1955 case BFD_RELOC_HI22
:
1956 case BFD_RELOC_LO10
:
1957 the_insn
.exp
.X_add_number
&= 0xffffffff;
1963 /* For pc-relative call instructions, we reject
1964 constants to get better code. */
1966 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
1967 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff)
1970 error_message
= ": PC-relative operand can't be a constant";
1973 /* Check for invalid constant values. Don't warn if
1974 constant was inside %hi or %lo, since these
1975 truncate the constant to fit. */
1976 if (immediate_max
!= 0
1977 && the_insn
.reloc
!= BFD_RELOC_LO10
1978 && the_insn
.reloc
!= BFD_RELOC_HI22
1979 && !in_signed_range (the_insn
.exp
.X_add_number
,
1984 /* Who knows? After relocation, we may be within
1985 range. Let the linker figure it out. */
1987 the_insn
.exp
.X_op
= O_symbol
;
1988 the_insn
.exp
.X_add_symbol
= section_symbol (absolute_section
);
1991 /* Immediate value is non-pcrel, and out of
1993 as_bad ("constant value %ld out of range (%ld .. %ld)",
1994 the_insn
.exp
.X_add_number
,
1995 ~immediate_max
, immediate_max
);
1999 /* Reset to prevent extraneous range check. */
2019 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2021 error_message
= ": invalid ASI name";
2027 if (! parse_const_expr_arg (&s
, &asi
))
2029 error_message
= ": invalid ASI expression";
2032 if (asi
< 0 || asi
> 255)
2034 error_message
= ": invalid ASI number";
2038 opcode
|= ASI (asi
);
2040 } /* alternate space */
2043 if (strncmp (s
, "%psr", 4) == 0)
2050 case 'q': /* floating point queue */
2051 if (strncmp (s
, "%fq", 3) == 0)
2058 case 'Q': /* coprocessor queue */
2059 if (strncmp (s
, "%cq", 3) == 0)
2067 if (strcmp (str
, "set") == 0
2068 || strcmp (str
, "setuw") == 0)
2070 special_case
= SPECIAL_CASE_SET
;
2073 else if (strcmp (str
, "setsw") == 0)
2075 special_case
= SPECIAL_CASE_SETSW
;
2078 else if (strcmp (str
, "setx") == 0)
2080 special_case
= SPECIAL_CASE_SETX
;
2083 else if (strncmp (str
, "fdiv", 4) == 0)
2085 special_case
= SPECIAL_CASE_FDIV
;
2091 if (strncmp (s
, "%asi", 4) != 0)
2097 if (strncmp (s
, "%fprs", 5) != 0)
2103 if (strncmp (s
, "%ccr", 4) != 0)
2109 if (strncmp (s
, "%tbr", 4) != 0)
2115 if (strncmp (s
, "%wim", 4) != 0)
2122 char *push
= input_line_pointer
;
2125 input_line_pointer
= s
;
2127 if (e
.X_op
== O_constant
)
2129 int n
= e
.X_add_number
;
2130 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2131 as_bad ("OPF immediate operand out of range (0-0x1ff)");
2133 opcode
|= e
.X_add_number
<< 5;
2136 as_bad ("non-immediate OPF operand, ignored");
2137 s
= input_line_pointer
;
2138 input_line_pointer
= push
;
2143 if (strncmp (s
, "%y", 2) != 0)
2151 /* Parse a sparclet cpreg. */
2153 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2155 error_message
= ": invalid cpreg name";
2158 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2163 as_fatal ("failed sanity check.");
2164 } /* switch on arg code */
2166 /* Break out of for() loop. */
2168 } /* for each arg that we expect */
2173 /* Args don't match. */
2174 if (((unsigned) (&insn
[1] - sparc_opcodes
)) < sparc_num_opcodes
2175 && (insn
->name
== insn
[1].name
2176 || !strcmp (insn
->name
, insn
[1].name
)))
2184 as_bad ("Illegal operands%s", error_message
);
2190 /* We have a match. Now see if the architecture is ok. */
2191 int needed_arch_mask
= insn
->architecture
;
2195 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2196 | (1 << SPARC_OPCODE_ARCH_V9A
));
2197 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2200 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2202 /* Can we bump up the architecture? */
2203 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2205 enum sparc_opcode_arch_val needed_architecture
=
2206 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2207 & needed_arch_mask
);
2209 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2211 && needed_architecture
> warn_after_architecture
)
2213 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2214 sparc_opcode_archs
[current_architecture
].name
,
2215 sparc_opcode_archs
[needed_architecture
].name
,
2217 warn_after_architecture
= needed_architecture
;
2219 current_architecture
= needed_architecture
;
2222 /* ??? This seems to be a bit fragile. What if the next entry in
2223 the opcode table is the one we want and it is supported?
2224 It is possible to arrange the table today so that this can't
2225 happen but what about tomorrow? */
2228 int arch
,printed_one_p
= 0;
2230 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2232 /* Create a list of the architectures that support the insn. */
2233 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2235 arch
= sparc_ffs (needed_arch_mask
);
2236 while ((1 << arch
) <= needed_arch_mask
)
2238 if ((1 << arch
) & needed_arch_mask
)
2242 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2249 as_bad ("Architecture mismatch on \"%s\".", str
);
2250 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2252 sparc_opcode_archs
[max_architecture
].name
);
2258 } /* forever looking for a match */
2260 the_insn
.opcode
= opcode
;
2270 save_in
= input_line_pointer
;
2271 input_line_pointer
= str
;
2272 seg
= expression (&the_insn
.exp
);
2273 if (seg
!= absolute_section
2274 && seg
!= text_section
2275 && seg
!= data_section
2276 && seg
!= bss_section
2277 && seg
!= undefined_section
)
2279 the_insn
.error
= "bad segment";
2280 expr_end
= input_line_pointer
;
2281 input_line_pointer
= save_in
;
2284 expr_end
= input_line_pointer
;
2285 input_line_pointer
= save_in
;
2287 } /* getExpression() */
2291 This is identical to the md_atof in m68k.c. I think this is right,
2294 Turn a string in input_line_pointer into a floating point constant of type
2295 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2296 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2299 /* Equal to MAX_PRECISION in atof-ieee.c */
2300 #define MAX_LITTLENUMS 6
2303 md_atof (type
, litP
, sizeP
)
2309 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2341 return "Bad call to MD_ATOF()";
2344 t
= atof_ieee (input_line_pointer
, type
, words
);
2346 input_line_pointer
= t
;
2347 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2349 if (target_big_endian
)
2351 for (i
= 0; i
< prec
; i
++)
2353 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2354 litP
+= sizeof (LITTLENUM_TYPE
);
2359 for (i
= prec
- 1; i
>= 0; i
--)
2361 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2362 litP
+= sizeof (LITTLENUM_TYPE
);
2369 /* Write a value out to the object file, using the appropriate
2373 md_number_to_chars (buf
, val
, n
)
2378 if (target_big_endian
)
2379 number_to_chars_bigendian (buf
, val
, n
);
2381 number_to_chars_littleendian (buf
, val
, n
);
2384 /* Apply a fixS to the frags, now that we know the value it ought to
2388 md_apply_fix3 (fixP
, value
, segment
)
2393 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2399 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2401 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2404 /* FIXME: SPARC ELF relocations don't use an addend in the data
2405 field itself. This whole approach should be somehow combined
2406 with the calls to bfd_install_relocation. Also, the value passed
2407 in by fixup_segment includes the value of a defined symbol. We
2408 don't want to include the value of an externally visible symbol. */
2409 if (fixP
->fx_addsy
!= NULL
)
2411 if (fixP
->fx_addsy
->sy_used_in_reloc
2412 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2413 || S_IS_WEAK (fixP
->fx_addsy
)
2414 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2415 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2416 && ((bfd_get_section_flags (stdoutput
,
2417 S_GET_SEGMENT (fixP
->fx_addsy
))
2418 & SEC_LINK_ONCE
) != 0
2419 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2421 sizeof ".gnu.linkonce" - 1) == 0)))
2422 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2423 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2424 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2425 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2430 /* This is a hack. There should be a better way to
2431 handle this. Probably in terms of howto fields, once
2432 we can look at these fixups in terms of howtos. */
2433 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2434 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2437 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2438 generate a reloc, then we just want to let the reloc addend set
2439 the value. We do not want to also stuff the addend into the
2440 object file. Including the addend in the object file works when
2441 doing a static link, because the linker will ignore the object
2442 file contents. However, the dynamic linker does not ignore the
2443 object file contents. */
2444 if (fixP
->fx_addsy
!= NULL
2445 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2448 /* When generating PIC code, we do not want an addend for a reloc
2449 against a local symbol. We adjust fx_addnumber to cancel out the
2450 value already included in val, and to also cancel out the
2451 adjustment which bfd_install_relocation will create. */
2453 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2454 && fixP
->fx_addsy
!= NULL
2455 && ! S_IS_COMMON (fixP
->fx_addsy
)
2456 && (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
2457 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2460 /* If this is a data relocation, just output VAL. */
2462 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2464 md_number_to_chars (buf
, val
, 2);
2466 else if (fixP
->fx_r_type
== BFD_RELOC_32
)
2468 md_number_to_chars (buf
, val
, 4);
2470 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2472 md_number_to_chars (buf
, val
, 8);
2476 /* It's a relocation against an instruction. */
2478 if (INSN_BIG_ENDIAN
)
2479 insn
= bfd_getb32 ((unsigned char *) buf
);
2481 insn
= bfd_getl32 ((unsigned char *) buf
);
2483 switch (fixP
->fx_r_type
)
2485 case BFD_RELOC_32_PCREL_S2
:
2487 /* FIXME: This increment-by-one deserves a comment of why it's
2489 if (! sparc_pic_code
2490 || fixP
->fx_addsy
== NULL
2491 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2493 insn
|= val
& 0x3fffffff;
2496 case BFD_RELOC_SPARC_11
:
2497 if (! in_signed_range (val
, 0x7ff))
2498 as_bad ("relocation overflow.");
2499 insn
|= val
& 0x7ff;
2502 case BFD_RELOC_SPARC_10
:
2503 if (! in_signed_range (val
, 0x3ff))
2504 as_bad ("relocation overflow.");
2505 insn
|= val
& 0x3ff;
2508 case BFD_RELOC_SPARC_6
:
2509 if (! in_bitfield_range (val
, 0x3f))
2510 as_bad ("relocation overflow.");
2514 case BFD_RELOC_SPARC_5
:
2515 if (! in_bitfield_range (val
, 0x1f))
2516 as_bad ("relocation overflow.");
2520 case BFD_RELOC_SPARC_WDISP16
:
2521 /* FIXME: simplify */
2522 if (((val
> 0) && (val
& ~0x3fffc))
2523 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2524 as_bad ("relocation overflow.");
2525 /* FIXME: The +1 deserves a comment. */
2526 val
= (val
>> 2) + 1;
2527 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2530 case BFD_RELOC_SPARC_WDISP19
:
2531 /* FIXME: simplify */
2532 if (((val
> 0) && (val
& ~0x1ffffc))
2533 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2534 as_bad ("relocation overflow.");
2535 /* FIXME: The +1 deserves a comment. */
2536 val
= (val
>> 2) + 1;
2537 insn
|= val
& 0x7ffff;
2540 case BFD_RELOC_SPARC_HH22
:
2541 val
= BSR (val
, 32);
2542 /* intentional fallthrough */
2544 case BFD_RELOC_SPARC_LM22
:
2545 case BFD_RELOC_HI22
:
2546 if (!fixP
->fx_addsy
)
2548 insn
|= (val
>> 10) & 0x3fffff;
2552 /* FIXME: Need comment explaining why we do this. */
2557 case BFD_RELOC_SPARC22
:
2558 if (val
& ~0x003fffff)
2559 as_bad ("relocation overflow");
2560 insn
|= (val
& 0x3fffff);
2563 case BFD_RELOC_SPARC_HM10
:
2564 val
= BSR (val
, 32);
2565 /* intentional fallthrough */
2567 case BFD_RELOC_LO10
:
2568 if (!fixP
->fx_addsy
)
2570 insn
|= val
& 0x3ff;
2574 /* FIXME: Need comment explaining why we do this. */
2579 case BFD_RELOC_SPARC13
:
2580 if (! in_signed_range (val
, 0x1fff))
2581 as_bad ("relocation overflow");
2582 insn
|= val
& 0x1fff;
2585 case BFD_RELOC_SPARC_WDISP22
:
2586 val
= (val
>> 2) + 1;
2588 case BFD_RELOC_SPARC_BASE22
:
2589 insn
|= val
& 0x3fffff;
2592 case BFD_RELOC_NONE
:
2594 as_bad ("bad or unhandled relocation type: 0x%02x", fixP
->fx_r_type
);
2598 if (INSN_BIG_ENDIAN
)
2599 bfd_putb32 (insn
, (unsigned char *) buf
);
2601 bfd_putl32 (insn
, (unsigned char *) buf
);
2604 /* Are we finished with this relocation now? */
2605 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
2611 /* Translate internal representation of relocation info to BFD target
2614 tc_gen_reloc (section
, fixp
)
2619 bfd_reloc_code_real_type code
;
2621 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2623 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
2624 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2626 switch (fixp
->fx_r_type
)
2630 case BFD_RELOC_HI22
:
2631 case BFD_RELOC_LO10
:
2632 case BFD_RELOC_32_PCREL_S2
:
2633 case BFD_RELOC_SPARC13
:
2634 case BFD_RELOC_SPARC_BASE13
:
2635 case BFD_RELOC_SPARC_WDISP16
:
2636 case BFD_RELOC_SPARC_WDISP19
:
2637 case BFD_RELOC_SPARC_WDISP22
:
2639 case BFD_RELOC_SPARC_5
:
2640 case BFD_RELOC_SPARC_6
:
2641 case BFD_RELOC_SPARC_10
:
2642 case BFD_RELOC_SPARC_11
:
2643 case BFD_RELOC_SPARC_HH22
:
2644 case BFD_RELOC_SPARC_HM10
:
2645 case BFD_RELOC_SPARC_LM22
:
2646 case BFD_RELOC_SPARC_PC_HH22
:
2647 case BFD_RELOC_SPARC_PC_HM10
:
2648 case BFD_RELOC_SPARC_PC_LM22
:
2649 code
= fixp
->fx_r_type
;
2655 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2656 /* If we are generating PIC code, we need to generate a different
2660 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2662 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2669 case BFD_RELOC_32_PCREL_S2
:
2670 if (! S_IS_DEFINED (fixp
->fx_addsy
)
2671 || S_IS_EXTERNAL (fixp
->fx_addsy
)
2672 || S_IS_WEAK (fixp
->fx_addsy
))
2673 code
= BFD_RELOC_SPARC_WPLT30
;
2675 case BFD_RELOC_HI22
:
2676 if (fixp
->fx_addsy
!= NULL
2677 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2678 code
= BFD_RELOC_SPARC_PC22
;
2680 code
= BFD_RELOC_SPARC_GOT22
;
2682 case BFD_RELOC_LO10
:
2683 if (fixp
->fx_addsy
!= NULL
2684 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2685 code
= BFD_RELOC_SPARC_PC10
;
2687 code
= BFD_RELOC_SPARC_GOT10
;
2689 case BFD_RELOC_SPARC13
:
2690 code
= BFD_RELOC_SPARC_GOT13
;
2696 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2698 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2699 if (reloc
->howto
== 0)
2701 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2702 "internal error: can't export reloc type %d (`%s')",
2703 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
2707 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2710 if (reloc
->howto
->pc_relative
== 0
2711 || code
== BFD_RELOC_SPARC_PC10
2712 || code
== BFD_RELOC_SPARC_PC22
)
2713 reloc
->addend
= fixp
->fx_addnumber
;
2715 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
2717 #else /* elf or coff */
2719 if (reloc
->howto
->pc_relative
== 0
2720 || code
== BFD_RELOC_SPARC_PC10
2721 || code
== BFD_RELOC_SPARC_PC22
)
2722 reloc
->addend
= fixp
->fx_addnumber
;
2723 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2724 reloc
->addend
= (section
->vma
2725 + fixp
->fx_addnumber
2726 + md_pcrel_from (fixp
));
2728 reloc
->addend
= fixp
->fx_offset
;
2736 /* for debugging only */
2739 struct sparc_it
*insn
;
2741 const char *const Reloc
[] = {
2770 fprintf (stderr
, "ERROR: %s\n");
2771 fprintf (stderr
, "opcode=0x%08x\n", insn
->opcode
);
2772 fprintf (stderr
, "reloc = %s\n", Reloc
[insn
->reloc
]);
2773 fprintf (stderr
, "exp = {\n");
2774 fprintf (stderr
, "\t\tX_add_symbol = %s\n",
2775 ((insn
->exp
.X_add_symbol
!= NULL
)
2776 ? ((S_GET_NAME (insn
->exp
.X_add_symbol
) != NULL
)
2777 ? S_GET_NAME (insn
->exp
.X_add_symbol
)
2780 fprintf (stderr
, "\t\tX_sub_symbol = %s\n",
2781 ((insn
->exp
.X_op_symbol
!= NULL
)
2782 ? (S_GET_NAME (insn
->exp
.X_op_symbol
)
2783 ? S_GET_NAME (insn
->exp
.X_op_symbol
)
2786 fprintf (stderr
, "\t\tX_add_number = %d\n",
2787 insn
->exp
.X_add_number
);
2788 fprintf (stderr
, "}\n");
2794 * Invocation line includes a switch not recognized by the base assembler.
2795 * See if it's a processor-specific option. These are:
2798 * Warn on architecture bumps. See also -A.
2800 * -Av6, -Av7, -Av8, -Av9, -Av9a, -Asparclite
2801 * -xarch=v8plus, -xarch=v8plusa
2802 * Select the architecture. Instructions or features not
2803 * supported by the selected architecture cause fatal errors.
2805 * The default is to start at v6, and bump the architecture up
2806 * whenever an instruction is seen at a higher level. If 32 bit
2807 * environments, v9 is not bumped up to, the user must pass -Av9.
2809 * -xarch=v8plus{,a} is for compatibility with the Sun assembler.
2811 * If -bump is specified, a warning is printing when bumping to
2814 * If an architecture is specified, all instructions must match
2815 * that architecture. Any higher level instructions are flagged
2816 * as errors. Note that in the 32 bit environment specifying
2817 * -Av9 does not automatically create a v9 object file, a v9
2818 * insn must be seen.
2820 * If both an architecture and -bump are specified, the
2821 * architecture starts at the specified level, but bumps are
2822 * warnings. Note that we can't set `current_architecture' to
2823 * the requested level in this case: in the 32 bit environment,
2824 * we still must avoid creating v9 object files unless v9 insns
2828 * Bumping between incompatible architectures is always an
2829 * error. For example, from sparclite to v9.
2833 CONST
char *md_shortopts
= "A:K:VQ:sq";
2836 CONST
char *md_shortopts
= "A:k";
2838 CONST
char *md_shortopts
= "A:";
2841 struct option md_longopts
[] = {
2842 #define OPTION_BUMP (OPTION_MD_BASE)
2843 {"bump", no_argument
, NULL
, OPTION_BUMP
},
2844 #define OPTION_SPARC (OPTION_MD_BASE + 1)
2845 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
2846 #define OPTION_XARCH (OPTION_MD_BASE + 2)
2847 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
2848 #ifdef SPARC_BIENDIAN
2849 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
2850 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2851 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
2852 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2854 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
2855 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
2856 {NULL
, no_argument
, NULL
, 0}
2858 size_t md_longopts_size
= sizeof(md_longopts
);
2861 md_parse_option (c
, arg
)
2869 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
2873 /* ??? We could add v8plus and v8plusa to sparc_opcode_archs.
2874 But we might want v8plus to mean something different than v9
2875 someday, and we'd recognize more -xarch options than Sun's
2876 assembler does (which may lead to a conflict someday). */
2877 if (strcmp (arg
, "v8plus") == 0)
2879 else if (strcmp (arg
, "v8plusa") == 0)
2883 as_bad ("invalid architecture -xarch=%s", arg
);
2891 enum sparc_opcode_arch_val new_arch
= sparc_opcode_lookup_arch (arg
);
2893 if (new_arch
== SPARC_OPCODE_ARCH_BAD
)
2895 as_bad ("invalid architecture -A%s", arg
);
2900 max_architecture
= new_arch
;
2901 architecture_requested
= 1;
2907 /* Ignore -sparc, used by SunOS make default .s.o rule. */
2910 case OPTION_ENFORCE_ALIGNED_DATA
:
2911 enforce_aligned_data
= 1;
2914 #ifdef SPARC_BIENDIAN
2915 case OPTION_LITTLE_ENDIAN
:
2916 target_big_endian
= 0;
2918 case OPTION_BIG_ENDIAN
:
2919 target_big_endian
= 1;
2931 print_version_id ();
2935 /* Qy - do emit .comment
2936 Qn - do not emit .comment */
2940 /* use .stab instead of .stab.excl */
2944 /* quick -- native assembler does fewer checks */
2948 if (strcmp (arg
, "PIC") != 0)
2949 as_warn ("Unrecognized option following -K");
2963 md_show_usage (stream
)
2966 const struct sparc_opcode_arch
*arch
;
2968 fprintf(stream
, "SPARC options:\n");
2969 for (arch
= &sparc_opcode_archs
[0]; arch
->name
; arch
++)
2971 if (arch
!= &sparc_opcode_archs
[0])
2972 fprintf (stream
, " | ");
2973 fprintf (stream
, "-A%s", arch
->name
);
2975 fprintf (stream
, "\n-xarch=v8plus | -xarch=v8plusa\n");
2977 specify variant of SPARC architecture\n\
2978 -bump warn when assembler switches architectures\n\
2980 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
2983 -k generate PIC\n");
2987 -KPIC generate PIC\n\
2988 -V print assembler version number\n\
2993 #ifdef SPARC_BIENDIAN
2995 -EL generate code for a little endian machine\n\
2996 -EB generate code for a big endian machine\n");
3000 /* We have no need to default values of symbols. */
3004 md_undefined_symbol (name
)
3008 } /* md_undefined_symbol() */
3010 /* Round up a section size to the appropriate boundary. */
3012 md_section_align (segment
, size
)
3017 /* This is not right for ELF; a.out wants it, and COFF will force
3018 the alignment anyways. */
3019 valueT align
= ((valueT
) 1
3020 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3022 /* turn alignment value into a mask */
3024 newsize
= (size
+ align
) & ~align
;
3031 /* Exactly what point is a PC-relative offset relative TO?
3032 On the sparc, they're relative to the address of the offset, plus
3033 its size. This gets us to the following instruction.
3034 (??? Is this right? FIXME-SOON) */
3036 md_pcrel_from (fixP
)
3041 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3042 if (! sparc_pic_code
3043 || fixP
->fx_addsy
== NULL
3044 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
3045 ret
+= fixP
->fx_size
;
3049 /* end of tc-sparc.c */