1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
41 static void init_default_arch
PARAMS ((void));
42 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
43 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
44 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
45 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
46 static int sparc_ffs
PARAMS ((unsigned int));
47 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
48 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
49 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
50 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
51 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
52 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
53 static int parse_const_expr_arg
PARAMS ((char **, int *));
54 static int get_expression
PARAMS ((char *str
));
56 /* Default architecture. */
57 /* ??? The default value should be V8, but sparclite support was added
58 by making it the default. GCC now passes -Asparclite, so maybe sometime in
59 the future we can set this to V8. */
61 #define DEFAULT_ARCH "sparclite"
63 static char *default_arch
= DEFAULT_ARCH
;
65 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 static int default_init_p
;
69 /* Current architecture. We don't bump up unless necessary. */
70 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
72 /* The maximum architecture level we can bump up to.
73 In a 32 bit environment, don't allow bumping up to v9 by default.
74 The native assembler works this way. The user is required to pass
75 an explicit argument before we'll create v9 object files. However, if
76 we don't see any v9 insns, a v8plus object file is not created. */
77 static enum sparc_opcode_arch_val max_architecture
;
79 /* Either 32 or 64, selects file format. */
80 static int sparc_arch_size
;
81 /* Initial (default) value, recorded separately in case a user option
82 changes the value before md_show_usage is called. */
83 static int default_arch_size
;
86 /* The currently selected v9 memory model. Currently only used for
88 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
91 static int architecture_requested
;
92 static int warn_on_bump
;
94 /* If warn_on_bump and the needed architecture is higher than this
95 architecture, issue a warning. */
96 static enum sparc_opcode_arch_val warn_after_architecture
;
98 /* Non-zero if as should generate error if an undeclared g[23] register
99 has been used in -64. */
100 static int no_undeclared_regs
;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax
;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data
;
111 extern int target_big_endian
;
113 static int target_little_endian_data
;
115 /* Symbols for global registers on v9. */
116 static symbolS
*globals
[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment
;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control
*op_hash
;
134 static int mylog2
PARAMS ((int));
135 static void s_data1
PARAMS ((void));
136 static void s_seg
PARAMS ((int));
137 static void s_proc
PARAMS ((int));
138 static void s_reserve
PARAMS ((int));
139 static void s_common
PARAMS ((int));
140 static void s_empty
PARAMS ((int));
141 static void s_uacons
PARAMS ((int));
142 static void s_ncons
PARAMS ((int));
144 static void s_register
PARAMS ((int));
147 const pseudo_typeS md_pseudo_table
[] =
149 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common
, 0},
151 {"empty", s_empty
, 0},
152 {"global", s_globl
, 0},
154 {"nword", s_ncons
, 0},
155 {"optim", s_ignore
, 0},
157 {"reserve", s_reserve
, 0},
159 {"skip", s_space
, 0},
162 {"uahalf", s_uacons
, 2},
163 {"uaword", s_uacons
, 4},
164 {"uaxword", s_uacons
, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars
[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS
[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode
;
211 struct nlist
*nlistp
;
215 bfd_reloc_code_real_type reloc
;
218 struct sparc_it the_insn
, set_insn
;
220 static void output_insn
221 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
223 /* Table of arguments to -A.
224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225 for this use. That table is for opcodes only. This table is for opcodes
228 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
229 v8plusa
, v9
, v9a
, v9b
, v9_64
};
231 static struct sparc_arch
{
234 enum sparc_arch_types arch_type
;
235 /* Default word size, as specified during configuration.
236 A value of zero means can't be used to specify default architecture. */
237 int default_arch_size
;
238 /* Allowable arg to -A? */
240 } sparc_arch_table
[] = {
241 { "v6", "v6", v6
, 0, 1 },
242 { "v7", "v7", v7
, 0, 1 },
243 { "v8", "v8", v8
, 32, 1 },
244 { "sparclet", "sparclet", sparclet
, 32, 1 },
245 { "sparclite", "sparclite", sparclite
, 32, 1 },
246 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
247 { "v8plus", "v9", v9
, 0, 1 },
248 { "v8plusa", "v9a", v9
, 0, 1 },
249 { "v8plusb", "v9b", v9
, 0, 1 },
250 { "v9", "v9", v9
, 0, 1 },
251 { "v9a", "v9a", v9
, 0, 1 },
252 { "v9b", "v9b", v9
, 0, 1 },
253 /* This exists to allow configure.in/Makefile.in to pass one
254 value to specify both the default machine and default word size. */
255 { "v9-64", "v9", v9
, 64, 0 },
256 { NULL
, NULL
, v8
, 0, 0 }
259 /* Variant of default_arch */
260 static enum sparc_arch_types default_arch_type
;
262 static struct sparc_arch
*
266 struct sparc_arch
*sa
;
268 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
269 if (strcmp (sa
->name
, name
) == 0)
271 if (sa
->name
== NULL
)
276 /* Initialize the default opcode arch and word size from the default
277 architecture name. */
282 struct sparc_arch
*sa
= lookup_arch (default_arch
);
285 || sa
->default_arch_size
== 0)
286 as_fatal (_("Invalid default architecture, broken assembler."));
288 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
289 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
290 as_fatal (_("Bad opcode table, broken assembler."));
291 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
293 default_arch_type
= sa
->arch_type
;
296 /* Called by TARGET_FORMAT. */
299 sparc_target_format ()
301 /* We don't get a chance to initialize anything before we're called,
302 so handle that now. */
303 if (! default_init_p
)
304 init_default_arch ();
308 return "a.out-sparc-netbsd";
311 if (target_big_endian
)
312 return "a.out-sunos-big";
313 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
314 return "a.out-sunos-big";
316 return "a.out-sparc-little";
318 return "a.out-sunos-big";
329 return "coff-sparc-lynx";
336 return "elf32-sparc-vxworks";
340 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
347 * Invocation line includes a switch not recognized by the base assembler.
348 * See if it's a processor-specific option. These are:
351 * Warn on architecture bumps. See also -A.
353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354 * Standard 32 bit architectures.
356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357 * This used to only mean 64 bits, but properly specifying it
358 * complicated gcc's ASM_SPECs, so now opcode selection is
359 * specified orthogonally to word size (except when specifying
360 * the default, but that is an internal implementation detail).
361 * -Av8plus, -Av8plusa, -Av8plusb
362 * Same as -Av9{,a,b}.
363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
366 * -xarch=v9, -xarch=v9a, -xarch=v9b
367 * Same as -Av9{,a,b} -64, for compatibility with Sun's
370 * Select the architecture and possibly the file format.
371 * Instructions or features not supported by the selected
372 * architecture cause fatal errors.
374 * The default is to start at v6, and bump the architecture up
375 * whenever an instruction is seen at a higher level. In 32 bit
376 * environments, v9 is not bumped up to, the user must pass
379 * If -bump is specified, a warning is printing when bumping to
382 * If an architecture is specified, all instructions must match
383 * that architecture. Any higher level instructions are flagged
384 * as errors. Note that in the 32 bit environment specifying
385 * -Av8plus does not automatically create a v8plus object file, a
386 * v9 insn must be seen.
388 * If both an architecture and -bump are specified, the
389 * architecture starts at the specified level, but bumps are
390 * warnings. Note that we can't set `current_architecture' to
391 * the requested level in this case: in the 32 bit environment,
392 * we still must avoid creating v8plus object files unless v9
396 * Bumping between incompatible architectures is always an
397 * error. For example, from sparclite to v9.
401 const char *md_shortopts
= "A:K:VQ:sq";
404 const char *md_shortopts
= "A:k";
406 const char *md_shortopts
= "A:";
409 struct option md_longopts
[] = {
410 #define OPTION_BUMP (OPTION_MD_BASE)
411 {"bump", no_argument
, NULL
, OPTION_BUMP
},
412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
413 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
415 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
417 #define OPTION_32 (OPTION_MD_BASE + 3)
418 {"32", no_argument
, NULL
, OPTION_32
},
419 #define OPTION_64 (OPTION_MD_BASE + 4)
420 {"64", no_argument
, NULL
, OPTION_64
},
421 #define OPTION_TSO (OPTION_MD_BASE + 5)
422 {"TSO", no_argument
, NULL
, OPTION_TSO
},
423 #define OPTION_PSO (OPTION_MD_BASE + 6)
424 {"PSO", no_argument
, NULL
, OPTION_PSO
},
425 #define OPTION_RMO (OPTION_MD_BASE + 7)
426 {"RMO", no_argument
, NULL
, OPTION_RMO
},
428 #ifdef SPARC_BIENDIAN
429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
445 {"relax", no_argument
, NULL
, OPTION_RELAX
},
446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
448 {NULL
, no_argument
, NULL
, 0}
451 size_t md_longopts_size
= sizeof (md_longopts
);
454 md_parse_option (c
, arg
)
458 /* We don't get a chance to initialize anything before we're called,
459 so handle that now. */
460 if (! default_init_p
)
461 init_default_arch ();
467 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
472 if (strncmp (arg
, "v9", 2) != 0)
473 md_parse_option (OPTION_32
, NULL
);
475 md_parse_option (OPTION_64
, NULL
);
481 struct sparc_arch
*sa
;
482 enum sparc_opcode_arch_val opcode_arch
;
484 sa
= lookup_arch (arg
);
486 || ! sa
->user_option_p
)
488 if (c
== OPTION_XARCH
)
489 as_bad (_("invalid architecture -xarch=%s"), arg
);
491 as_bad (_("invalid architecture -A%s"), arg
);
495 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
496 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
497 as_fatal (_("Bad opcode table, broken assembler."));
499 max_architecture
= opcode_arch
;
500 architecture_requested
= 1;
505 /* Ignore -sparc, used by SunOS make default .s.o rule. */
508 case OPTION_ENFORCE_ALIGNED_DATA
:
509 enforce_aligned_data
= 1;
512 #ifdef SPARC_BIENDIAN
513 case OPTION_LITTLE_ENDIAN
:
514 target_big_endian
= 0;
515 if (default_arch_type
!= sparclet
)
516 as_fatal ("This target does not support -EL");
518 case OPTION_LITTLE_ENDIAN_DATA
:
519 target_little_endian_data
= 1;
520 target_big_endian
= 0;
521 if (default_arch_type
!= sparc86x
522 && default_arch_type
!= v9
)
523 as_fatal ("This target does not support --little-endian-data");
525 case OPTION_BIG_ENDIAN
:
526 target_big_endian
= 1;
540 const char **list
, **l
;
542 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
543 list
= bfd_target_list ();
544 for (l
= list
; *l
!= NULL
; l
++)
546 if (sparc_arch_size
== 32)
548 if (CONST_STRNEQ (*l
, "elf32-sparc"))
553 if (CONST_STRNEQ (*l
, "elf64-sparc"))
558 as_fatal (_("No compiled in support for %d bit object file format"),
565 sparc_memory_model
= MM_TSO
;
569 sparc_memory_model
= MM_PSO
;
573 sparc_memory_model
= MM_RMO
;
581 /* Qy - do emit .comment
582 Qn - do not emit .comment. */
586 /* Use .stab instead of .stab.excl. */
590 /* quick -- Native assembler does fewer checks. */
594 if (strcmp (arg
, "PIC") != 0)
595 as_warn (_("Unrecognized option following -K"));
600 case OPTION_NO_UNDECLARED_REGS
:
601 no_undeclared_regs
= 1;
604 case OPTION_UNDECLARED_REGS
:
605 no_undeclared_regs
= 0;
613 case OPTION_NO_RELAX
:
625 md_show_usage (stream
)
628 const struct sparc_arch
*arch
;
631 /* We don't get a chance to initialize anything before we're called,
632 so handle that now. */
633 if (! default_init_p
)
634 init_default_arch ();
636 fprintf (stream
, _("SPARC options:\n"));
638 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
640 if (!arch
->user_option_p
)
642 if (arch
!= &sparc_arch_table
[0])
643 fprintf (stream
, " | ");
644 if (column
+ strlen (arch
->name
) > 70)
647 fputc ('\n', stream
);
649 column
+= 5 + 2 + strlen (arch
->name
);
650 fprintf (stream
, "-A%s", arch
->name
);
652 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
654 if (!arch
->user_option_p
)
656 fprintf (stream
, " | ");
657 if (column
+ strlen (arch
->name
) > 65)
660 fputc ('\n', stream
);
662 column
+= 5 + 7 + strlen (arch
->name
);
663 fprintf (stream
, "-xarch=%s", arch
->name
);
665 fprintf (stream
, _("\n\
666 specify variant of SPARC architecture\n\
667 -bump warn when assembler switches architectures\n\
669 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
670 -relax relax jumps and branches (default)\n\
671 -no-relax avoid changing any jumps and branches\n"));
673 fprintf (stream
, _("\
674 -k generate PIC\n"));
677 fprintf (stream
, _("\
678 -32 create 32 bit object file\n\
679 -64 create 64 bit object file\n"));
680 fprintf (stream
, _("\
681 [default is %d]\n"), default_arch_size
);
682 fprintf (stream
, _("\
683 -TSO use Total Store Ordering\n\
684 -PSO use Partial Store Ordering\n\
685 -RMO use Relaxed Memory Ordering\n"));
686 fprintf (stream
, _("\
687 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
688 fprintf (stream
, _("\
689 -KPIC generate PIC\n\
690 -V print assembler version number\n\
691 -undeclared-regs ignore application global register usage without\n\
692 appropriate .register directive (default)\n\
693 -no-undeclared-regs force error on application global register usage\n\
694 without appropriate .register directive\n\
699 #ifdef SPARC_BIENDIAN
700 fprintf (stream
, _("\
701 -EL generate code for a little endian machine\n\
702 -EB generate code for a big endian machine\n\
703 --little-endian-data generate code for a machine having big endian\n\
704 instructions and little endian data.\n"));
708 /* Native operand size opcode translation. */
714 } native_op_table
[] =
716 {"ldn", "ld", "ldx"},
717 {"ldna", "lda", "ldxa"},
718 {"stn", "st", "stx"},
719 {"stna", "sta", "stxa"},
720 {"slln", "sll", "sllx"},
721 {"srln", "srl", "srlx"},
722 {"sran", "sra", "srax"},
723 {"casn", "cas", "casx"},
724 {"casna", "casa", "casxa"},
725 {"clrn", "clr", "clrx"},
729 /* sparc64 privileged and hyperprivileged registers. */
731 struct priv_reg_entry
737 struct priv_reg_entry priv_reg_table
[] =
757 {"", -1}, /* End marker. */
760 struct priv_reg_entry hpriv_reg_table
[] =
768 {"", -1}, /* End marker. */
771 /* v9a specific asrs. */
773 struct priv_reg_entry v9a_asr_table
[] =
776 {"sys_tick_cmpr", 25},
784 {"clear_softint", 21},
785 {"", -1}, /* End marker. */
789 cmp_reg_entry (parg
, qarg
)
793 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
794 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
796 return strcmp (q
->name
, p
->name
);
799 /* This function is called once, at assembler startup time. It should
800 set up all the tables, etc. that the MD part of the assembler will
806 register const char *retval
= NULL
;
808 register unsigned int i
= 0;
810 /* We don't get a chance to initialize anything before md_parse_option
811 is called, and it may not be called, so handle default initialization
812 now if not already done. */
813 if (! default_init_p
)
814 init_default_arch ();
816 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
817 op_hash
= hash_new ();
819 while (i
< (unsigned int) sparc_num_opcodes
)
821 const char *name
= sparc_opcodes
[i
].name
;
822 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
825 as_bad (_("Internal error: can't hash `%s': %s\n"),
826 sparc_opcodes
[i
].name
, retval
);
831 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
833 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
834 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
839 while (i
< (unsigned int) sparc_num_opcodes
840 && !strcmp (sparc_opcodes
[i
].name
, name
));
843 for (i
= 0; native_op_table
[i
].name
; i
++)
845 const struct sparc_opcode
*insn
;
846 char *name
= ((sparc_arch_size
== 32)
847 ? native_op_table
[i
].name32
848 : native_op_table
[i
].name64
);
849 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
852 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
853 name
, native_op_table
[i
].name
);
858 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
861 as_bad (_("Internal error: can't hash `%s': %s\n"),
862 sparc_opcodes
[i
].name
, retval
);
869 as_fatal (_("Broken assembler. No assembly attempted."));
871 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
872 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
874 /* If -bump, record the architecture level at which we start issuing
875 warnings. The behaviour is different depending upon whether an
876 architecture was explicitly specified. If it wasn't, we issue warnings
877 for all upwards bumps. If it was, we don't start issuing warnings until
878 we need to bump beyond the requested architecture or when we bump between
879 conflicting architectures. */
882 && architecture_requested
)
884 /* `max_architecture' records the requested architecture.
885 Issue warnings if we go above it. */
886 warn_after_architecture
= max_architecture
;
888 /* Find the highest architecture level that doesn't conflict with
889 the requested one. */
890 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
891 max_architecture
> warn_after_architecture
;
893 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
894 warn_after_architecture
))
899 /* Called after all assembly has been done. */
904 unsigned long mach
= bfd_mach_sparc
;
906 if (sparc_arch_size
== 64)
907 switch (current_architecture
)
909 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
910 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
911 default: mach
= bfd_mach_sparc_v9
; break;
914 switch (current_architecture
)
916 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
917 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
918 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
919 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
920 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
921 be but for now it is (since that's the way it's always been
925 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
928 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
931 in_signed_range (val
, max
)
932 bfd_signed_vma val
, max
;
936 /* Sign-extend the value from the architecture word size, so that
937 0xffffffff is always considered -1 on sparc32. */
938 if (sparc_arch_size
== 32)
940 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
941 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
950 /* Return non-zero if VAL is in the range 0 to MAX. */
953 in_unsigned_range (val
, max
)
961 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
962 (e.g. -15 to +31). */
965 in_bitfield_range (val
, max
)
966 bfd_signed_vma val
, max
;
972 if (val
< ~(max
>> 1))
986 for (i
= 0; (mask
& 1) == 0; ++i
)
991 /* Implement big shift right. */
997 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
998 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
999 return val
>> amount
;
1002 /* For communication between sparc_ip and get_expression. */
1003 static char *expr_end
;
1005 /* Values for `special_case'.
1006 Instructions that require wierd handling because they're longer than
1008 #define SPECIAL_CASE_NONE 0
1009 #define SPECIAL_CASE_SET 1
1010 #define SPECIAL_CASE_SETSW 2
1011 #define SPECIAL_CASE_SETX 3
1012 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1013 #define SPECIAL_CASE_FDIV 4
1015 /* Bit masks of various insns. */
1016 #define NOP_INSN 0x01000000
1017 #define OR_INSN 0x80100000
1018 #define XOR_INSN 0x80180000
1019 #define FMOVS_INSN 0x81A00020
1020 #define SETHI_INSN 0x01000000
1021 #define SLLX_INSN 0x81281000
1022 #define SRA_INSN 0x81380000
1024 /* The last instruction to be assembled. */
1025 static const struct sparc_opcode
*last_insn
;
1026 /* The assembled opcode of `last_insn'. */
1027 static unsigned long last_opcode
;
1029 /* Handle the set and setuw synthetic instructions. */
1032 synthetize_setuw (insn
)
1033 const struct sparc_opcode
*insn
;
1035 int need_hi22_p
= 0;
1036 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1038 if (the_insn
.exp
.X_op
== O_constant
)
1040 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1042 if (sizeof (offsetT
) > 4
1043 && (the_insn
.exp
.X_add_number
< 0
1044 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1045 as_warn (_("set: number not in 0..4294967295 range"));
1049 if (sizeof (offsetT
) > 4
1050 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1051 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1052 as_warn (_("set: number not in -2147483648..4294967295 range"));
1053 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1057 /* See if operand is absolute and small; skip sethi if so. */
1058 if (the_insn
.exp
.X_op
!= O_constant
1059 || the_insn
.exp
.X_add_number
>= (1 << 12)
1060 || the_insn
.exp
.X_add_number
< -(1 << 12))
1062 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1063 | ((the_insn
.exp
.X_add_number
>> 10)
1064 & (the_insn
.exp
.X_op
== O_constant
1066 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1067 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1068 output_insn (insn
, &the_insn
);
1072 /* See if operand has no low-order bits; skip OR if so. */
1073 if (the_insn
.exp
.X_op
!= O_constant
1074 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1077 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1079 | (the_insn
.exp
.X_add_number
1080 & (the_insn
.exp
.X_op
!= O_constant
1081 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1082 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1083 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1084 output_insn (insn
, &the_insn
);
1088 /* Handle the setsw synthetic instruction. */
1091 synthetize_setsw (insn
)
1092 const struct sparc_opcode
*insn
;
1096 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1098 if (the_insn
.exp
.X_op
!= O_constant
)
1100 synthetize_setuw (insn
);
1102 /* Need to sign extend it. */
1103 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1104 the_insn
.reloc
= BFD_RELOC_NONE
;
1105 output_insn (insn
, &the_insn
);
1109 if (sizeof (offsetT
) > 4
1110 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1111 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1112 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1114 low32
= the_insn
.exp
.X_add_number
;
1118 synthetize_setuw (insn
);
1124 the_insn
.reloc
= BFD_RELOC_NONE
;
1125 /* See if operand is absolute and small; skip sethi if so. */
1126 if (low32
< -(1 << 12))
1128 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1129 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1130 output_insn (insn
, &the_insn
);
1131 low32
= 0x1c00 | (low32
& 0x3ff);
1132 opc
= RS1 (rd
) | XOR_INSN
;
1135 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1136 | (low32
& 0x1fff));
1137 output_insn (insn
, &the_insn
);
1140 /* Handle the setsw synthetic instruction. */
1143 synthetize_setx (insn
)
1144 const struct sparc_opcode
*insn
;
1146 int upper32
, lower32
;
1147 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1148 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1150 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1151 int need_xor10_p
= 0;
1153 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1154 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1155 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1158 upper_dstreg
= tmpreg
;
1159 /* The tmp reg should not be the dst reg. */
1160 if (tmpreg
== dstreg
)
1161 as_warn (_("setx: temporary register same as destination register"));
1163 /* ??? Obviously there are other optimizations we can do
1164 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1165 doing some of these. Later. If you do change things, try to
1166 change all of this to be table driven as well. */
1167 /* What to output depends on the number if it's constant.
1168 Compute that first, then output what we've decided upon. */
1169 if (the_insn
.exp
.X_op
!= O_constant
)
1171 if (sparc_arch_size
== 32)
1173 /* When arch size is 32, we want setx to be equivalent
1174 to setuw for anything but constants. */
1175 the_insn
.exp
.X_add_number
&= 0xffffffff;
1176 synthetize_setuw (insn
);
1179 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1185 /* Reset X_add_number, we've extracted it as upper32/lower32.
1186 Otherwise fixup_segment will complain about not being able to
1187 write an 8 byte number in a 4 byte field. */
1188 the_insn
.exp
.X_add_number
= 0;
1190 /* Only need hh22 if `or' insn can't handle constant. */
1191 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1194 /* Does bottom part (after sethi) have bits? */
1195 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1196 /* No hh22, but does upper32 still have bits we can't set
1198 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1201 /* If the lower half is all zero, we build the upper half directly
1202 into the dst reg. */
1204 /* Need lower half if number is zero or 0xffffffff00000000. */
1205 || (! need_hh22_p
&& ! need_hm10_p
))
1207 /* No need for sethi if `or' insn can handle constant. */
1208 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1209 /* Note that we can't use a negative constant in the `or'
1210 insn unless the upper 32 bits are all ones. */
1211 || (lower32
< 0 && upper32
!= -1)
1212 || (lower32
>= 0 && upper32
== -1))
1215 if (need_hi22_p
&& upper32
== -1)
1218 /* Does bottom part (after sethi) have bits? */
1219 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1221 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1222 /* Need `or' if we didn't set anything else. */
1223 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1227 /* Output directly to dst reg if lower 32 bits are all zero. */
1228 upper_dstreg
= dstreg
;
1231 if (!upper_dstreg
&& dstreg
)
1232 as_warn (_("setx: illegal temporary register g0"));
1236 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1237 | ((upper32
>> 10) & 0x3fffff));
1238 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1239 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1240 output_insn (insn
, &the_insn
);
1245 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1246 | (((need_xor10_p
? ~lower32
: lower32
)
1247 >> 10) & 0x3fffff));
1248 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1249 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1250 output_insn (insn
, &the_insn
);
1255 the_insn
.opcode
= (OR_INSN
1256 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1259 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1260 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1261 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1262 output_insn (insn
, &the_insn
);
1267 /* FIXME: One nice optimization to do here is to OR the low part
1268 with the highpart if hi22 isn't needed and the low part is
1270 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1273 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1274 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1275 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1276 output_insn (insn
, &the_insn
);
1279 /* If we needed to build the upper part, shift it into place. */
1280 if (need_hh22_p
|| need_hm10_p
)
1282 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1284 the_insn
.reloc
= BFD_RELOC_NONE
;
1285 output_insn (insn
, &the_insn
);
1288 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1291 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1292 | 0x1c00 | (lower32
& 0x3ff));
1293 the_insn
.reloc
= BFD_RELOC_NONE
;
1294 output_insn (insn
, &the_insn
);
1297 /* If we needed to build both upper and lower parts, OR them together. */
1298 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1300 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1302 the_insn
.reloc
= BFD_RELOC_NONE
;
1303 output_insn (insn
, &the_insn
);
1307 /* Main entry point to assemble one instruction. */
1313 const struct sparc_opcode
*insn
;
1317 special_case
= sparc_ip (str
, &insn
);
1321 /* We warn about attempts to put a floating point branch in a delay slot,
1322 unless the delay slot has been annulled. */
1323 if (last_insn
!= NULL
1324 && (insn
->flags
& F_FBR
) != 0
1325 && (last_insn
->flags
& F_DELAYED
) != 0
1326 /* ??? This test isn't completely accurate. We assume anything with
1327 F_{UNBR,CONDBR,FBR} set is annullable. */
1328 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1329 || (last_opcode
& ANNUL
) == 0))
1330 as_warn (_("FP branch in delay slot"));
1332 /* SPARC before v9 requires a nop instruction between a floating
1333 point instruction and a floating point branch. We insert one
1334 automatically, with a warning. */
1335 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1336 && last_insn
!= NULL
1337 && (insn
->flags
& F_FBR
) != 0
1338 && (last_insn
->flags
& F_FLOAT
) != 0)
1340 struct sparc_it nop_insn
;
1342 nop_insn
.opcode
= NOP_INSN
;
1343 nop_insn
.reloc
= BFD_RELOC_NONE
;
1344 output_insn (insn
, &nop_insn
);
1345 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1348 switch (special_case
)
1350 case SPECIAL_CASE_NONE
:
1352 output_insn (insn
, &the_insn
);
1355 case SPECIAL_CASE_SETSW
:
1356 synthetize_setsw (insn
);
1359 case SPECIAL_CASE_SET
:
1360 synthetize_setuw (insn
);
1363 case SPECIAL_CASE_SETX
:
1364 synthetize_setx (insn
);
1367 case SPECIAL_CASE_FDIV
:
1369 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1371 output_insn (insn
, &the_insn
);
1373 /* According to information leaked from Sun, the "fdiv" instructions
1374 on early SPARC machines would produce incorrect results sometimes.
1375 The workaround is to add an fmovs of the destination register to
1376 itself just after the instruction. This was true on machines
1377 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1378 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1379 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1380 output_insn (insn
, &the_insn
);
1385 as_fatal (_("failed special case insn sanity check"));
1389 /* Subroutine of md_assemble to do the actual parsing. */
1392 sparc_ip (str
, pinsn
)
1394 const struct sparc_opcode
**pinsn
;
1396 char *error_message
= "";
1400 const struct sparc_opcode
*insn
;
1402 unsigned long opcode
;
1403 unsigned int mask
= 0;
1407 int special_case
= SPECIAL_CASE_NONE
;
1414 while (ISLOWER (*s
) || ISDIGIT (*s
));
1431 as_bad (_("Unknown opcode: `%s'"), str
);
1433 return special_case
;
1435 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1439 as_bad (_("Unknown opcode: `%s'"), str
);
1440 return special_case
;
1450 opcode
= insn
->match
;
1451 memset (&the_insn
, '\0', sizeof (the_insn
));
1452 the_insn
.reloc
= BFD_RELOC_NONE
;
1455 /* Build the opcode, checking as we go to make sure that the
1457 for (args
= insn
->args
;; ++args
)
1465 /* Parse a series of masks. */
1472 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1475 error_message
= _(": invalid membar mask name");
1481 if (*s
== '|' || *s
== '+')
1489 if (! parse_const_expr_arg (&s
, &kmask
))
1491 error_message
= _(": invalid membar mask expression");
1494 if (kmask
< 0 || kmask
> 127)
1496 error_message
= _(": invalid membar mask number");
1501 opcode
|= MEMBAR (kmask
);
1509 if (! parse_const_expr_arg (&s
, &smask
))
1511 error_message
= _(": invalid siam mode expression");
1514 if (smask
< 0 || smask
> 7)
1516 error_message
= _(": invalid siam mode number");
1527 /* Parse a prefetch function. */
1530 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1532 error_message
= _(": invalid prefetch function name");
1538 if (! parse_const_expr_arg (&s
, &fcn
))
1540 error_message
= _(": invalid prefetch function expression");
1543 if (fcn
< 0 || fcn
> 31)
1545 error_message
= _(": invalid prefetch function number");
1555 /* Parse a sparc64 privileged register. */
1558 struct priv_reg_entry
*p
= priv_reg_table
;
1559 unsigned int len
= 9999999; /* Init to make gcc happy. */
1562 while (p
->name
[0] > s
[0])
1564 while (p
->name
[0] == s
[0])
1566 len
= strlen (p
->name
);
1567 if (strncmp (p
->name
, s
, len
) == 0)
1571 if (p
->name
[0] != s
[0])
1573 error_message
= _(": unrecognizable privileged register");
1577 opcode
|= (p
->regnum
<< 14);
1579 opcode
|= (p
->regnum
<< 25);
1585 error_message
= _(": unrecognizable privileged register");
1591 /* Parse a sparc64 hyperprivileged register. */
1594 struct priv_reg_entry
*p
= hpriv_reg_table
;
1595 unsigned int len
= 9999999; /* Init to make gcc happy. */
1598 while (p
->name
[0] > s
[0])
1600 while (p
->name
[0] == s
[0])
1602 len
= strlen (p
->name
);
1603 if (strncmp (p
->name
, s
, len
) == 0)
1607 if (p
->name
[0] != s
[0])
1609 error_message
= _(": unrecognizable hyperprivileged register");
1613 opcode
|= (p
->regnum
<< 14);
1615 opcode
|= (p
->regnum
<< 25);
1621 error_message
= _(": unrecognizable hyperprivileged register");
1627 /* Parse a v9a/v9b ancillary state register. */
1630 struct priv_reg_entry
*p
= v9a_asr_table
;
1631 unsigned int len
= 9999999; /* Init to make gcc happy. */
1634 while (p
->name
[0] > s
[0])
1636 while (p
->name
[0] == s
[0])
1638 len
= strlen (p
->name
);
1639 if (strncmp (p
->name
, s
, len
) == 0)
1643 if (p
->name
[0] != s
[0])
1645 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1648 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1650 error_message
= _(": rd on write only ancillary state register");
1654 && (insn
->architecture
1655 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1657 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1658 error_message
= _(": unrecognizable v9a ancillary state register");
1662 opcode
|= (p
->regnum
<< 14);
1664 opcode
|= (p
->regnum
<< 25);
1670 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1676 if (strncmp (s
, "%asr", 4) == 0)
1684 while (ISDIGIT (*s
))
1686 num
= num
* 10 + *s
- '0';
1690 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1692 if (num
< 16 || 31 < num
)
1694 error_message
= _(": asr number must be between 16 and 31");
1700 if (num
< 0 || 31 < num
)
1702 error_message
= _(": asr number must be between 0 and 31");
1707 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1712 error_message
= _(": expecting %asrN");
1719 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1723 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1727 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1728 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1729 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1731 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1732 /* These fields are unsigned, but for upward compatibility,
1733 allow negative values as well. */
1737 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1738 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1739 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1741 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1742 /* These fields are unsigned, but for upward compatibility,
1743 allow negative values as well. */
1747 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1752 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1757 if (*s
== 'p' && s
[1] == 'n')
1765 if (*s
== 'p' && s
[1] == 't')
1777 if (strncmp (s
, "%icc", 4) == 0)
1789 if (strncmp (s
, "%xcc", 4) == 0)
1801 if (strncmp (s
, "%fcc0", 5) == 0)
1813 if (strncmp (s
, "%fcc1", 5) == 0)
1825 if (strncmp (s
, "%fcc2", 5) == 0)
1837 if (strncmp (s
, "%fcc3", 5) == 0)
1845 if (strncmp (s
, "%pc", 3) == 0)
1853 if (strncmp (s
, "%tick", 5) == 0)
1860 case '\0': /* End of args. */
1861 if (s
[0] == ',' && s
[1] == '%')
1863 static const struct ops
1865 /* The name as it appears in assembler. */
1867 /* strlen (name), precomputed for speed */
1869 /* The reloc this pseudo-op translates to. */
1871 /* 1 if tls call. */
1876 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1877 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1878 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1879 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1880 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1881 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1882 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1883 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
1884 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
1887 const struct ops
*o
;
1891 for (o
= ops
; o
->name
; o
++)
1892 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1894 if (o
->name
== NULL
)
1897 if (s
[o
->len
+ 2] != '(')
1899 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1900 return special_case
;
1903 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1905 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1907 return special_case
;
1911 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1912 || the_insn
.exp
.X_add_number
!= 0
1913 || the_insn
.exp
.X_add_symbol
1914 != symbol_find_or_make ("__tls_get_addr")))
1916 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1918 return special_case
;
1921 the_insn
.reloc
= o
->reloc
;
1922 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1925 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1928 else if (*s1
== ')')
1937 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1938 return special_case
;
1942 (void) get_expression (s
);
1962 case '[': /* These must match exactly. */
1970 case '#': /* Must be at least one digit. */
1973 while (ISDIGIT (*s
))
1981 case 'C': /* Coprocessor state register. */
1982 if (strncmp (s
, "%csr", 4) == 0)
1989 case 'b': /* Next operand is a coprocessor register. */
1992 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
1997 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2011 opcode
|= mask
<< 14;
2019 opcode
|= mask
<< 25;
2025 case 'r': /* next operand must be a register */
2035 case 'f': /* frame pointer */
2043 case 'g': /* global register */
2052 case 'i': /* in register */
2056 mask
= c
- '0' + 24;
2061 case 'l': /* local register */
2065 mask
= (c
- '0' + 16);
2070 case 'o': /* out register */
2074 mask
= (c
- '0' + 8);
2079 case 's': /* stack pointer */
2087 case 'r': /* any register */
2088 if (!ISDIGIT ((c
= *s
++)))
2105 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2121 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2122 && no_undeclared_regs
&& ! globals
[mask
])
2123 as_bad (_("detected global register use not covered by .register pseudo-op"));
2125 /* Got the register, now figure out where
2126 it goes in the opcode. */
2130 opcode
|= mask
<< 14;
2138 opcode
|= mask
<< 25;
2142 opcode
|= (mask
<< 25) | (mask
<< 14);
2146 opcode
|= (mask
<< 25) | (mask
<< 0);
2152 case 'e': /* next operand is a floating point register */
2167 && ((format
= *s
) == 'f')
2170 for (mask
= 0; ISDIGIT (*s
); ++s
)
2172 mask
= 10 * mask
+ (*s
- '0');
2173 } /* read the number */
2181 } /* register must be even numbered */
2189 } /* register must be multiple of 4 */
2193 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2194 error_message
= _(": There are only 64 f registers; [0-63]");
2196 error_message
= _(": There are only 32 f registers; [0-31]");
2199 else if (mask
>= 32)
2201 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2203 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2206 = _(": There are only 32 single precision f registers; [0-31]");
2210 mask
-= 31; /* wrap high bit */
2214 error_message
= _(": There are only 32 f registers; [0-31]");
2222 } /* if not an 'f' register. */
2229 opcode
|= RS1 (mask
);
2235 opcode
|= RS2 (mask
);
2241 opcode
|= RD (mask
);
2250 if (strncmp (s
, "%fsr", 4) == 0)
2257 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2258 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2261 case 'l': /* 22 bit PC relative immediate */
2262 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2266 case 'L': /* 30 bit immediate */
2267 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2272 case 'n': /* 22 bit immediate */
2273 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2276 case 'i': /* 13 bit immediate */
2277 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2287 char *op_arg
= NULL
;
2288 static expressionS op_exp
;
2289 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2291 /* Check for %hi, etc. */
2294 static const struct ops
{
2295 /* The name as it appears in assembler. */
2297 /* strlen (name), precomputed for speed */
2299 /* The reloc this pseudo-op translates to. */
2301 /* Non-zero if for v9 only. */
2303 /* Non-zero if can be used in pc-relative contexts. */
2304 int pcrel_p
;/*FIXME:wip*/
2306 /* hix/lox must appear before hi/lo so %hix won't be
2307 mistaken for %hi. */
2308 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2309 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2310 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2311 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2312 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2313 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2314 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2315 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2316 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2317 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2318 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2319 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2320 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2321 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2322 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2323 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2324 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2326 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2328 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2329 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2330 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2331 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2332 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2334 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2336 { NULL
, 0, 0, 0, 0 }
2338 const struct ops
*o
;
2340 for (o
= ops
; o
->name
; o
++)
2341 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2343 if (o
->name
== NULL
)
2346 if (s
[o
->len
+ 1] != '(')
2348 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2349 return special_case
;
2353 the_insn
.reloc
= o
->reloc
;
2358 /* Note that if the get_expression() fails, we will still
2359 have created U entries in the symbol table for the
2360 'symbols' in the input string. Try not to create U
2361 symbols for registers, etc. */
2363 /* This stuff checks to see if the expression ends in
2364 +%reg. If it does, it removes the register from
2365 the expression, and re-sets 's' to point to the
2372 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2375 else if (*s1
== ')')
2384 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2385 return special_case
;
2389 (void) get_expression (s
);
2392 if (*s
== ',' || *s
== ']' || !*s
)
2394 if (*s
!= '+' && *s
!= '-')
2396 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2397 return special_case
;
2401 op_exp
= the_insn
.exp
;
2402 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2405 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2408 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2410 if (s1
[-2] == '%' && s1
[-3] == '+')
2412 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2419 if (op_arg
&& s1
== s
+ 1)
2420 the_insn
.exp
.X_op
= O_absent
;
2422 (void) get_expression (s
);
2434 (void) get_expression (s
);
2442 the_insn
.exp2
= the_insn
.exp
;
2443 the_insn
.exp
= op_exp
;
2444 if (the_insn
.exp2
.X_op
== O_absent
)
2445 the_insn
.exp2
.X_op
= O_illegal
;
2446 else if (the_insn
.exp
.X_op
== O_absent
)
2448 the_insn
.exp
= the_insn
.exp2
;
2449 the_insn
.exp2
.X_op
= O_illegal
;
2451 else if (the_insn
.exp
.X_op
== O_constant
)
2453 valueT val
= the_insn
.exp
.X_add_number
;
2454 switch (the_insn
.reloc
)
2459 case BFD_RELOC_SPARC_HH22
:
2460 val
= BSR (val
, 32);
2463 case BFD_RELOC_SPARC_LM22
:
2464 case BFD_RELOC_HI22
:
2465 val
= (val
>> 10) & 0x3fffff;
2468 case BFD_RELOC_SPARC_HM10
:
2469 val
= BSR (val
, 32);
2472 case BFD_RELOC_LO10
:
2476 case BFD_RELOC_SPARC_H44
:
2481 case BFD_RELOC_SPARC_M44
:
2486 case BFD_RELOC_SPARC_L44
:
2490 case BFD_RELOC_SPARC_HIX22
:
2492 val
= (val
>> 10) & 0x3fffff;
2495 case BFD_RELOC_SPARC_LOX10
:
2496 val
= (val
& 0x3ff) | 0x1c00;
2499 the_insn
.exp
= the_insn
.exp2
;
2500 the_insn
.exp
.X_add_number
+= val
;
2501 the_insn
.exp2
.X_op
= O_illegal
;
2502 the_insn
.reloc
= old_reloc
;
2504 else if (the_insn
.exp2
.X_op
!= O_constant
)
2506 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2507 return special_case
;
2511 if (old_reloc
!= BFD_RELOC_SPARC13
2512 || the_insn
.reloc
!= BFD_RELOC_LO10
2513 || sparc_arch_size
!= 64
2516 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2517 return special_case
;
2519 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2523 /* Check for constants that don't require emitting a reloc. */
2524 if (the_insn
.exp
.X_op
== O_constant
2525 && the_insn
.exp
.X_add_symbol
== 0
2526 && the_insn
.exp
.X_op_symbol
== 0)
2528 /* For pc-relative call instructions, we reject
2529 constants to get better code. */
2531 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2532 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2534 error_message
= _(": PC-relative operand can't be a constant");
2538 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2539 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2541 error_message
= _(": TLS operand can't be a constant");
2545 /* Constants that won't fit are checked in md_apply_fix
2546 and bfd_install_relocation.
2547 ??? It would be preferable to install the constants
2548 into the insn here and save having to create a fixS
2549 for each one. There already exists code to handle
2550 all the various cases (e.g. in md_apply_fix and
2551 bfd_install_relocation) so duplicating all that code
2552 here isn't right. */
2572 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2574 error_message
= _(": invalid ASI name");
2580 if (! parse_const_expr_arg (&s
, &asi
))
2582 error_message
= _(": invalid ASI expression");
2585 if (asi
< 0 || asi
> 255)
2587 error_message
= _(": invalid ASI number");
2591 opcode
|= ASI (asi
);
2593 } /* Alternate space. */
2596 if (strncmp (s
, "%psr", 4) == 0)
2603 case 'q': /* Floating point queue. */
2604 if (strncmp (s
, "%fq", 3) == 0)
2611 case 'Q': /* Coprocessor queue. */
2612 if (strncmp (s
, "%cq", 3) == 0)
2620 if (strcmp (str
, "set") == 0
2621 || strcmp (str
, "setuw") == 0)
2623 special_case
= SPECIAL_CASE_SET
;
2626 else if (strcmp (str
, "setsw") == 0)
2628 special_case
= SPECIAL_CASE_SETSW
;
2631 else if (strcmp (str
, "setx") == 0)
2633 special_case
= SPECIAL_CASE_SETX
;
2636 else if (strncmp (str
, "fdiv", 4) == 0)
2638 special_case
= SPECIAL_CASE_FDIV
;
2644 if (strncmp (s
, "%asi", 4) != 0)
2650 if (strncmp (s
, "%fprs", 5) != 0)
2656 if (strncmp (s
, "%ccr", 4) != 0)
2662 if (strncmp (s
, "%tbr", 4) != 0)
2668 if (strncmp (s
, "%wim", 4) != 0)
2675 char *push
= input_line_pointer
;
2678 input_line_pointer
= s
;
2680 if (e
.X_op
== O_constant
)
2682 int n
= e
.X_add_number
;
2683 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2684 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2686 opcode
|= e
.X_add_number
<< 5;
2689 as_bad (_("non-immediate OPF operand, ignored"));
2690 s
= input_line_pointer
;
2691 input_line_pointer
= push
;
2696 if (strncmp (s
, "%y", 2) != 0)
2704 /* Parse a sparclet cpreg. */
2706 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2708 error_message
= _(": invalid cpreg name");
2711 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2716 as_fatal (_("failed sanity check."));
2717 } /* switch on arg code. */
2719 /* Break out of for() loop. */
2721 } /* For each arg that we expect. */
2726 /* Args don't match. */
2727 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2728 && (insn
->name
== insn
[1].name
2729 || !strcmp (insn
->name
, insn
[1].name
)))
2737 as_bad (_("Illegal operands%s"), error_message
);
2738 return special_case
;
2743 /* We have a match. Now see if the architecture is OK. */
2744 int needed_arch_mask
= insn
->architecture
;
2749 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2750 if (! needed_arch_mask
)
2752 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2755 if (needed_arch_mask
2756 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2759 /* Can we bump up the architecture? */
2760 else if (needed_arch_mask
2761 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2763 enum sparc_opcode_arch_val needed_architecture
=
2764 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2765 & needed_arch_mask
);
2767 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2769 && needed_architecture
> warn_after_architecture
)
2771 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2772 sparc_opcode_archs
[current_architecture
].name
,
2773 sparc_opcode_archs
[needed_architecture
].name
,
2775 warn_after_architecture
= needed_architecture
;
2777 current_architecture
= needed_architecture
;
2780 /* ??? This seems to be a bit fragile. What if the next entry in
2781 the opcode table is the one we want and it is supported?
2782 It is possible to arrange the table today so that this can't
2783 happen but what about tomorrow? */
2786 int arch
, printed_one_p
= 0;
2788 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2790 /* Create a list of the architectures that support the insn. */
2791 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2793 arch
= sparc_ffs (needed_arch_mask
);
2794 while ((1 << arch
) <= needed_arch_mask
)
2796 if ((1 << arch
) & needed_arch_mask
)
2800 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2807 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2808 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2810 sparc_opcode_archs
[max_architecture
].name
);
2811 return special_case
;
2813 } /* If no match. */
2816 } /* Forever looking for a match. */
2818 the_insn
.opcode
= opcode
;
2819 return special_case
;
2822 /* Parse an argument that can be expressed as a keyword.
2823 (eg: #StoreStore or %ccfr).
2824 The result is a boolean indicating success.
2825 If successful, INPUT_POINTER is updated. */
2828 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2829 int (*lookup_fn
) PARAMS ((const char *));
2830 char **input_pointerP
;
2836 p
= *input_pointerP
;
2837 for (q
= p
+ (*p
== '#' || *p
== '%');
2838 ISALNUM (*q
) || *q
== '_';
2843 value
= (*lookup_fn
) (p
);
2848 *input_pointerP
= q
;
2852 /* Parse an argument that is a constant expression.
2853 The result is a boolean indicating success. */
2856 parse_const_expr_arg (input_pointerP
, valueP
)
2857 char **input_pointerP
;
2860 char *save
= input_line_pointer
;
2863 input_line_pointer
= *input_pointerP
;
2864 /* The next expression may be something other than a constant
2865 (say if we're not processing the right variant of the insn).
2866 Don't call expression unless we're sure it will succeed as it will
2867 signal an error (which we want to defer until later). */
2868 /* FIXME: It might be better to define md_operand and have it recognize
2869 things like %asi, etc. but continuing that route through to the end
2870 is a lot of work. */
2871 if (*input_line_pointer
== '%')
2873 input_line_pointer
= save
;
2877 *input_pointerP
= input_line_pointer
;
2878 input_line_pointer
= save
;
2879 if (exp
.X_op
!= O_constant
)
2881 *valueP
= exp
.X_add_number
;
2885 /* Subroutine of sparc_ip to parse an expression. */
2888 get_expression (str
)
2894 save_in
= input_line_pointer
;
2895 input_line_pointer
= str
;
2896 seg
= expression (&the_insn
.exp
);
2897 if (seg
!= absolute_section
2898 && seg
!= text_section
2899 && seg
!= data_section
2900 && seg
!= bss_section
2901 && seg
!= undefined_section
)
2903 the_insn
.error
= _("bad segment");
2904 expr_end
= input_line_pointer
;
2905 input_line_pointer
= save_in
;
2908 expr_end
= input_line_pointer
;
2909 input_line_pointer
= save_in
;
2913 /* Subroutine of md_assemble to output one insn. */
2916 output_insn (insn
, the_insn
)
2917 const struct sparc_opcode
*insn
;
2918 struct sparc_it
*the_insn
;
2920 char *toP
= frag_more (4);
2922 /* Put out the opcode. */
2923 if (INSN_BIG_ENDIAN
)
2924 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2926 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2928 /* Put out the symbol-dependent stuff. */
2929 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2931 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2932 (toP
- frag_now
->fr_literal
), /* Where. */
2937 /* Turn off overflow checking in fixup_segment. We'll do our
2938 own overflow checking in md_apply_fix. This is necessary because
2939 the insn size is 4 and fixup_segment will signal an overflow for
2940 large 8 byte quantities. */
2941 fixP
->fx_no_overflow
= 1;
2942 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2943 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2947 last_opcode
= the_insn
->opcode
;
2950 dwarf2_emit_insn (4);
2955 md_atof (int type
, char *litP
, int *sizeP
)
2957 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
2960 /* Write a value out to the object file, using the appropriate
2964 md_number_to_chars (buf
, val
, n
)
2969 if (target_big_endian
)
2970 number_to_chars_bigendian (buf
, val
, n
);
2971 else if (target_little_endian_data
2972 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2973 /* Output debug words, which are not in allocated sections, as big
2975 number_to_chars_bigendian (buf
, val
, n
);
2976 else if (target_little_endian_data
|| ! target_big_endian
)
2977 number_to_chars_littleendian (buf
, val
, n
);
2980 /* Apply a fixS to the frags, now that we know the value it ought to
2984 md_apply_fix (fixP
, valP
, segment
)
2987 segT segment ATTRIBUTE_UNUSED
;
2989 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2990 offsetT val
= * (offsetT
*) valP
;
2993 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2995 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
2998 /* SPARC ELF relocations don't use an addend in the data field. */
2999 if (fixP
->fx_addsy
!= NULL
)
3001 switch (fixP
->fx_r_type
)
3003 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3004 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3005 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3006 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3007 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3008 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3009 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3010 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3011 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3012 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3013 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3014 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3015 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3016 case BFD_RELOC_SPARC_TLS_IE_LD
:
3017 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3018 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3019 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3020 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3021 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3022 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3023 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3024 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3025 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3026 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3027 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3037 /* This is a hack. There should be a better way to
3038 handle this. Probably in terms of howto fields, once
3039 we can look at these fixups in terms of howtos. */
3040 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3041 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3044 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3045 generate a reloc, then we just want to let the reloc addend set
3046 the value. We do not want to also stuff the addend into the
3047 object file. Including the addend in the object file works when
3048 doing a static link, because the linker will ignore the object
3049 file contents. However, the dynamic linker does not ignore the
3050 object file contents. */
3051 if (fixP
->fx_addsy
!= NULL
3052 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3055 /* When generating PIC code, we do not want an addend for a reloc
3056 against a local symbol. We adjust fx_addnumber to cancel out the
3057 value already included in val, and to also cancel out the
3058 adjustment which bfd_install_relocation will create. */
3060 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3061 && fixP
->fx_addsy
!= NULL
3062 && ! S_IS_COMMON (fixP
->fx_addsy
)
3063 && symbol_section_p (fixP
->fx_addsy
))
3064 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3066 /* When generating PIC code, we need to fiddle to get
3067 bfd_install_relocation to do the right thing for a PC relative
3068 reloc against a local symbol which we are going to keep. */
3070 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3071 && fixP
->fx_addsy
!= NULL
3072 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3073 || S_IS_WEAK (fixP
->fx_addsy
))
3074 && S_IS_DEFINED (fixP
->fx_addsy
)
3075 && ! S_IS_COMMON (fixP
->fx_addsy
))
3078 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3082 /* If this is a data relocation, just output VAL. */
3084 if (fixP
->fx_r_type
== BFD_RELOC_16
3085 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3087 md_number_to_chars (buf
, val
, 2);
3089 else if (fixP
->fx_r_type
== BFD_RELOC_32
3090 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3091 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3093 md_number_to_chars (buf
, val
, 4);
3095 else if (fixP
->fx_r_type
== BFD_RELOC_64
3096 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3098 md_number_to_chars (buf
, val
, 8);
3100 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3101 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3108 /* It's a relocation against an instruction. */
3110 if (INSN_BIG_ENDIAN
)
3111 insn
= bfd_getb32 ((unsigned char *) buf
);
3113 insn
= bfd_getl32 ((unsigned char *) buf
);
3115 switch (fixP
->fx_r_type
)
3117 case BFD_RELOC_32_PCREL_S2
:
3119 /* FIXME: This increment-by-one deserves a comment of why it's
3121 if (! sparc_pic_code
3122 || fixP
->fx_addsy
== NULL
3123 || symbol_section_p (fixP
->fx_addsy
))
3126 insn
|= val
& 0x3fffffff;
3128 /* See if we have a delay slot. */
3129 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3133 #define XCC (2 << 20)
3134 #define COND(x) (((x)&0xf)<<25)
3135 #define CONDA COND(0x8)
3136 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3137 #define INSN_BA (F2(0,2) | CONDA)
3138 #define INSN_OR F3(2, 0x2, 0)
3139 #define INSN_NOP F2(0,4)
3143 /* If the instruction is a call with either:
3145 arithmetic instruction with rd == %o7
3146 where rs1 != %o7 and rs2 if it is register != %o7
3147 then we can optimize if the call destination is near
3148 by changing the call into a branch always. */
3149 if (INSN_BIG_ENDIAN
)
3150 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3152 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3153 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3155 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3156 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3157 || ((delay
& RD (~0)) != RD (O7
))))
3159 if ((delay
& RS1 (~0)) == RS1 (O7
)
3160 || ((delay
& F3I (~0)) == 0
3161 && (delay
& RS2 (~0)) == RS2 (O7
)))
3163 /* Ensure the branch will fit into simm22. */
3164 if ((val
& 0x3fe00000)
3165 && (val
& 0x3fe00000) != 0x3fe00000)
3167 /* Check if the arch is v9 and branch will fit
3169 if (((val
& 0x3c0000) == 0
3170 || (val
& 0x3c0000) == 0x3c0000)
3171 && (sparc_arch_size
== 64
3172 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3174 insn
= INSN_BPA
| (val
& 0x7ffff);
3177 insn
= INSN_BA
| (val
& 0x3fffff);
3178 if (fixP
->fx_where
>= 4
3179 && ((delay
& (0xffffffff ^ RS1 (~0)))
3180 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3185 if (INSN_BIG_ENDIAN
)
3186 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3188 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3189 if ((setter
& (0xffffffff ^ RD (~0)))
3190 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3197 If call foo was replaced with ba, replace
3198 or %rN, %g0, %o7 with nop. */
3199 reg
= (delay
& RS1 (~0)) >> 14;
3200 if (reg
!= ((setter
& RD (~0)) >> 25)
3201 || reg
== G0
|| reg
== O7
)
3204 if (INSN_BIG_ENDIAN
)
3205 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3207 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3212 case BFD_RELOC_SPARC_11
:
3213 if (! in_signed_range (val
, 0x7ff))
3214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3215 _("relocation overflow"));
3216 insn
|= val
& 0x7ff;
3219 case BFD_RELOC_SPARC_10
:
3220 if (! in_signed_range (val
, 0x3ff))
3221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3222 _("relocation overflow"));
3223 insn
|= val
& 0x3ff;
3226 case BFD_RELOC_SPARC_7
:
3227 if (! in_bitfield_range (val
, 0x7f))
3228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3229 _("relocation overflow"));
3233 case BFD_RELOC_SPARC_6
:
3234 if (! in_bitfield_range (val
, 0x3f))
3235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3236 _("relocation overflow"));
3240 case BFD_RELOC_SPARC_5
:
3241 if (! in_bitfield_range (val
, 0x1f))
3242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3243 _("relocation overflow"));
3247 case BFD_RELOC_SPARC_WDISP16
:
3250 || val
<= -(offsetT
) 0x20008)
3251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3252 _("relocation overflow"));
3253 /* FIXME: The +1 deserves a comment. */
3254 val
= (val
>> 2) + 1;
3255 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3258 case BFD_RELOC_SPARC_WDISP19
:
3261 || val
<= -(offsetT
) 0x100008)
3262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3263 _("relocation overflow"));
3264 /* FIXME: The +1 deserves a comment. */
3265 val
= (val
>> 2) + 1;
3266 insn
|= val
& 0x7ffff;
3269 case BFD_RELOC_SPARC_HH22
:
3270 val
= BSR (val
, 32);
3273 case BFD_RELOC_SPARC_LM22
:
3274 case BFD_RELOC_HI22
:
3275 if (!fixP
->fx_addsy
)
3276 insn
|= (val
>> 10) & 0x3fffff;
3278 /* FIXME: Need comment explaining why we do this. */
3282 case BFD_RELOC_SPARC22
:
3283 if (val
& ~0x003fffff)
3284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3285 _("relocation overflow"));
3286 insn
|= (val
& 0x3fffff);
3289 case BFD_RELOC_SPARC_HM10
:
3290 val
= BSR (val
, 32);
3293 case BFD_RELOC_LO10
:
3294 if (!fixP
->fx_addsy
)
3295 insn
|= val
& 0x3ff;
3297 /* FIXME: Need comment explaining why we do this. */
3301 case BFD_RELOC_SPARC_OLO10
:
3303 val
+= fixP
->tc_fix_data
;
3306 case BFD_RELOC_SPARC13
:
3307 if (! in_signed_range (val
, 0x1fff))
3308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3309 _("relocation overflow"));
3310 insn
|= val
& 0x1fff;
3313 case BFD_RELOC_SPARC_WDISP22
:
3314 val
= (val
>> 2) + 1;
3316 case BFD_RELOC_SPARC_BASE22
:
3317 insn
|= val
& 0x3fffff;
3320 case BFD_RELOC_SPARC_H44
:
3321 if (!fixP
->fx_addsy
)
3325 insn
|= tval
& 0x3fffff;
3329 case BFD_RELOC_SPARC_M44
:
3330 if (!fixP
->fx_addsy
)
3331 insn
|= (val
>> 12) & 0x3ff;
3334 case BFD_RELOC_SPARC_L44
:
3335 if (!fixP
->fx_addsy
)
3336 insn
|= val
& 0xfff;
3339 case BFD_RELOC_SPARC_HIX22
:
3340 if (!fixP
->fx_addsy
)
3342 val
^= ~(offsetT
) 0;
3343 insn
|= (val
>> 10) & 0x3fffff;
3347 case BFD_RELOC_SPARC_LOX10
:
3348 if (!fixP
->fx_addsy
)
3349 insn
|= 0x1c00 | (val
& 0x3ff);
3352 case BFD_RELOC_NONE
:
3354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3355 _("bad or unhandled relocation type: 0x%02x"),
3360 if (INSN_BIG_ENDIAN
)
3361 bfd_putb32 (insn
, (unsigned char *) buf
);
3363 bfd_putl32 (insn
, (unsigned char *) buf
);
3366 /* Are we finished with this relocation now? */
3367 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3371 /* Translate internal representation of relocation info to BFD target
3375 tc_gen_reloc (section
, fixp
)
3379 static arelent
*relocs
[3];
3381 bfd_reloc_code_real_type code
;
3383 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3386 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3387 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3388 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3390 switch (fixp
->fx_r_type
)
3394 case BFD_RELOC_HI22
:
3395 case BFD_RELOC_LO10
:
3396 case BFD_RELOC_32_PCREL_S2
:
3397 case BFD_RELOC_SPARC13
:
3398 case BFD_RELOC_SPARC22
:
3399 case BFD_RELOC_SPARC_BASE13
:
3400 case BFD_RELOC_SPARC_WDISP16
:
3401 case BFD_RELOC_SPARC_WDISP19
:
3402 case BFD_RELOC_SPARC_WDISP22
:
3404 case BFD_RELOC_SPARC_5
:
3405 case BFD_RELOC_SPARC_6
:
3406 case BFD_RELOC_SPARC_7
:
3407 case BFD_RELOC_SPARC_10
:
3408 case BFD_RELOC_SPARC_11
:
3409 case BFD_RELOC_SPARC_HH22
:
3410 case BFD_RELOC_SPARC_HM10
:
3411 case BFD_RELOC_SPARC_LM22
:
3412 case BFD_RELOC_SPARC_PC_HH22
:
3413 case BFD_RELOC_SPARC_PC_HM10
:
3414 case BFD_RELOC_SPARC_PC_LM22
:
3415 case BFD_RELOC_SPARC_H44
:
3416 case BFD_RELOC_SPARC_M44
:
3417 case BFD_RELOC_SPARC_L44
:
3418 case BFD_RELOC_SPARC_HIX22
:
3419 case BFD_RELOC_SPARC_LOX10
:
3420 case BFD_RELOC_SPARC_REV32
:
3421 case BFD_RELOC_SPARC_OLO10
:
3422 case BFD_RELOC_SPARC_UA16
:
3423 case BFD_RELOC_SPARC_UA32
:
3424 case BFD_RELOC_SPARC_UA64
:
3425 case BFD_RELOC_8_PCREL
:
3426 case BFD_RELOC_16_PCREL
:
3427 case BFD_RELOC_32_PCREL
:
3428 case BFD_RELOC_64_PCREL
:
3429 case BFD_RELOC_SPARC_PLT32
:
3430 case BFD_RELOC_SPARC_PLT64
:
3431 case BFD_RELOC_VTABLE_ENTRY
:
3432 case BFD_RELOC_VTABLE_INHERIT
:
3433 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3434 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3435 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3436 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3437 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3438 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3439 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3440 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3441 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3442 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3443 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3444 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3445 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3446 case BFD_RELOC_SPARC_TLS_IE_LD
:
3447 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3448 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3449 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3450 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3451 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3452 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3453 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3454 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3455 case BFD_RELOC_SPARC_GOTDATA_OP
:
3456 code
= fixp
->fx_r_type
;
3463 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3464 /* If we are generating PIC code, we need to generate a different
3468 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3470 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3473 #define GOTT_BASE "__GOTT_BASE__"
3474 #define GOTT_INDEX "__GOTT_INDEX__"
3477 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3483 case BFD_RELOC_32_PCREL_S2
:
3484 if (generic_force_reloc (fixp
))
3485 code
= BFD_RELOC_SPARC_WPLT30
;
3487 case BFD_RELOC_HI22
:
3488 code
= BFD_RELOC_SPARC_GOT22
;
3489 if (fixp
->fx_addsy
!= NULL
)
3491 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3492 code
= BFD_RELOC_SPARC_PC22
;
3494 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3495 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3496 code
= BFD_RELOC_HI22
; /* Unchanged. */
3500 case BFD_RELOC_LO10
:
3501 code
= BFD_RELOC_SPARC_GOT10
;
3502 if (fixp
->fx_addsy
!= NULL
)
3504 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3505 code
= BFD_RELOC_SPARC_PC10
;
3507 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3508 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3509 code
= BFD_RELOC_LO10
; /* Unchanged. */
3513 case BFD_RELOC_SPARC13
:
3514 code
= BFD_RELOC_SPARC_GOT13
;
3520 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3522 /* Nothing is aligned in DWARF debugging sections. */
3523 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3526 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3527 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3528 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3532 if (code
== BFD_RELOC_SPARC_OLO10
)
3533 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3535 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3536 if (reloc
->howto
== 0)
3538 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3539 _("internal error: can't export reloc type %d (`%s')"),
3540 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3546 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3549 if (reloc
->howto
->pc_relative
== 0
3550 || code
== BFD_RELOC_SPARC_PC10
3551 || code
== BFD_RELOC_SPARC_PC22
)
3552 reloc
->addend
= fixp
->fx_addnumber
;
3553 else if (sparc_pic_code
3554 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3555 && fixp
->fx_addsy
!= NULL
3556 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3557 || S_IS_WEAK (fixp
->fx_addsy
))
3558 && S_IS_DEFINED (fixp
->fx_addsy
)
3559 && ! S_IS_COMMON (fixp
->fx_addsy
))
3560 reloc
->addend
= fixp
->fx_addnumber
;
3562 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3564 #else /* elf or coff */
3566 if (code
!= BFD_RELOC_32_PCREL_S2
3567 && code
!= BFD_RELOC_SPARC_WDISP22
3568 && code
!= BFD_RELOC_SPARC_WDISP16
3569 && code
!= BFD_RELOC_SPARC_WDISP19
3570 && code
!= BFD_RELOC_SPARC_WPLT30
3571 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3572 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3573 reloc
->addend
= fixp
->fx_addnumber
;
3574 else if (symbol_section_p (fixp
->fx_addsy
))
3575 reloc
->addend
= (section
->vma
3576 + fixp
->fx_addnumber
3577 + md_pcrel_from (fixp
));
3579 reloc
->addend
= fixp
->fx_offset
;
3582 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3583 on the same location. */
3584 if (code
== BFD_RELOC_SPARC_OLO10
)
3586 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3589 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3591 = symbol_get_bfdsym (section_symbol (absolute_section
));
3592 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3593 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3594 reloc
->addend
= fixp
->tc_fix_data
;
3600 /* We have no need to default values of symbols. */
3603 md_undefined_symbol (name
)
3604 char *name ATTRIBUTE_UNUSED
;
3609 /* Round up a section size to the appropriate boundary. */
3612 md_section_align (segment
, size
)
3613 segT segment ATTRIBUTE_UNUSED
;
3617 /* This is not right for ELF; a.out wants it, and COFF will force
3618 the alignment anyways. */
3619 valueT align
= ((valueT
) 1
3620 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3623 /* Turn alignment value into a mask. */
3625 newsize
= (size
+ align
) & ~align
;
3632 /* Exactly what point is a PC-relative offset relative TO?
3633 On the sparc, they're relative to the address of the offset, plus
3634 its size. This gets us to the following instruction.
3635 (??? Is this right? FIXME-SOON) */
3637 md_pcrel_from (fixP
)
3642 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3643 if (! sparc_pic_code
3644 || fixP
->fx_addsy
== NULL
3645 || symbol_section_p (fixP
->fx_addsy
))
3646 ret
+= fixP
->fx_size
;
3650 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3662 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3665 return (value
== 1) ? shift
: -1;
3668 /* Sort of like s_lcomm. */
3671 static int max_alignment
= 15;
3676 int ignore ATTRIBUTE_UNUSED
;
3686 name
= input_line_pointer
;
3687 c
= get_symbol_end ();
3688 p
= input_line_pointer
;
3692 if (*input_line_pointer
!= ',')
3694 as_bad (_("Expected comma after name"));
3695 ignore_rest_of_line ();
3699 ++input_line_pointer
;
3701 if ((size
= get_absolute_expression ()) < 0)
3703 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3704 ignore_rest_of_line ();
3709 symbolP
= symbol_find_or_make (name
);
3712 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3713 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3715 as_bad (_("bad .reserve segment -- expected BSS segment"));
3719 if (input_line_pointer
[2] == '.')
3720 input_line_pointer
+= 7;
3722 input_line_pointer
+= 6;
3725 if (*input_line_pointer
== ',')
3727 ++input_line_pointer
;
3730 if (*input_line_pointer
== '\n')
3732 as_bad (_("missing alignment"));
3733 ignore_rest_of_line ();
3737 align
= (int) get_absolute_expression ();
3740 if (align
> max_alignment
)
3742 align
= max_alignment
;
3743 as_warn (_("alignment too large; assuming %d"), align
);
3749 as_bad (_("negative alignment"));
3750 ignore_rest_of_line ();
3756 temp
= mylog2 (align
);
3759 as_bad (_("alignment not a power of 2"));
3760 ignore_rest_of_line ();
3767 record_alignment (bss_section
, align
);
3772 if (!S_IS_DEFINED (symbolP
)
3774 && S_GET_OTHER (symbolP
) == 0
3775 && S_GET_DESC (symbolP
) == 0
3782 segT current_seg
= now_seg
;
3783 subsegT current_subseg
= now_subseg
;
3785 /* Switch to bss. */
3786 subseg_set (bss_section
, 1);
3790 frag_align (align
, 0, 0);
3792 /* Detach from old frag. */
3793 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3794 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3796 symbol_set_frag (symbolP
, frag_now
);
3797 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3798 (offsetT
) size
, (char *) 0);
3801 S_SET_SEGMENT (symbolP
, bss_section
);
3803 subseg_set (current_seg
, current_subseg
);
3806 S_SET_SIZE (symbolP
, size
);
3812 as_warn ("Ignoring attempt to re-define symbol %s",
3813 S_GET_NAME (symbolP
));
3814 } /* if not redefining. */
3816 demand_empty_rest_of_line ();
3821 int ignore ATTRIBUTE_UNUSED
;
3829 name
= input_line_pointer
;
3830 c
= get_symbol_end ();
3831 /* Just after name is now '\0'. */
3832 p
= input_line_pointer
;
3835 if (*input_line_pointer
!= ',')
3837 as_bad (_("Expected comma after symbol-name"));
3838 ignore_rest_of_line ();
3843 input_line_pointer
++;
3845 if ((temp
= get_absolute_expression ()) < 0)
3847 as_bad (_(".COMMon length (%lu) out of range ignored"),
3848 (unsigned long) temp
);
3849 ignore_rest_of_line ();
3854 symbolP
= symbol_find_or_make (name
);
3856 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3858 as_bad (_("Ignoring attempt to re-define symbol"));
3859 ignore_rest_of_line ();
3862 if (S_GET_VALUE (symbolP
) != 0)
3864 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3866 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3867 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
3873 S_SET_VALUE (symbolP
, (valueT
) size
);
3874 S_SET_EXTERNAL (symbolP
);
3877 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3878 if (*input_line_pointer
!= ',')
3880 as_bad (_("Expected comma after common length"));
3881 ignore_rest_of_line ();
3884 input_line_pointer
++;
3886 if (*input_line_pointer
!= '"')
3888 temp
= get_absolute_expression ();
3891 if (temp
> max_alignment
)
3893 temp
= max_alignment
;
3894 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
3900 as_bad (_("negative alignment"));
3901 ignore_rest_of_line ();
3906 if (symbol_get_obj (symbolP
)->local
)
3914 old_subsec
= now_subseg
;
3919 align
= mylog2 (temp
);
3923 as_bad (_("alignment not a power of 2"));
3924 ignore_rest_of_line ();
3928 record_alignment (bss_section
, align
);
3929 subseg_set (bss_section
, 0);
3931 frag_align (align
, 0, 0);
3932 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3933 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3934 symbol_set_frag (symbolP
, frag_now
);
3935 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3936 (offsetT
) size
, (char *) 0);
3938 S_SET_SEGMENT (symbolP
, bss_section
);
3939 S_CLEAR_EXTERNAL (symbolP
);
3940 S_SET_SIZE (symbolP
, size
);
3941 subseg_set (old_sec
, old_subsec
);
3944 #endif /* OBJ_ELF */
3947 S_SET_VALUE (symbolP
, (valueT
) size
);
3949 S_SET_ALIGN (symbolP
, temp
);
3950 S_SET_SIZE (symbolP
, size
);
3952 S_SET_EXTERNAL (symbolP
);
3953 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3958 input_line_pointer
++;
3959 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3960 if (*input_line_pointer
== '.')
3961 input_line_pointer
++;
3962 /* @@ Some say data, some say bss. */
3963 if (strncmp (input_line_pointer
, "bss\"", 4)
3964 && strncmp (input_line_pointer
, "data\"", 5))
3966 while (*--input_line_pointer
!= '"')
3968 input_line_pointer
--;
3969 goto bad_common_segment
;
3971 while (*input_line_pointer
++ != '"')
3973 goto allocate_common
;
3976 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3978 demand_empty_rest_of_line ();
3983 p
= input_line_pointer
;
3984 while (*p
&& *p
!= '\n')
3988 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3990 input_line_pointer
= p
;
3991 ignore_rest_of_line ();
3996 /* Handle the .empty pseudo-op. This suppresses the warnings about
3997 invalid delay slot usage. */
4001 int ignore ATTRIBUTE_UNUSED
;
4003 /* The easy way to implement is to just forget about the last
4010 int ignore ATTRIBUTE_UNUSED
;
4013 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4015 input_line_pointer
+= 6;
4019 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4021 input_line_pointer
+= 6;
4025 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4027 input_line_pointer
+= 7;
4031 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4033 input_line_pointer
+= 5;
4034 /* We only support 2 segments -- text and data -- for now, so
4035 things in the "bss segment" will have to go into data for now.
4036 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4037 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4040 as_bad (_("Unknown segment type"));
4041 demand_empty_rest_of_line ();
4047 subseg_set (data_section
, 1);
4048 demand_empty_rest_of_line ();
4053 int ignore ATTRIBUTE_UNUSED
;
4055 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4057 ++input_line_pointer
;
4059 ++input_line_pointer
;
4062 /* This static variable is set by s_uacons to tell sparc_cons_align
4063 that the expression does not need to be aligned. */
4065 static int sparc_no_align_cons
= 0;
4067 /* This static variable is set by sparc_cons to emit requested types
4068 of relocations in cons_fix_new_sparc. */
4070 static const char *sparc_cons_special_reloc
;
4072 /* This handles the unaligned space allocation pseudo-ops, such as
4073 .uaword. .uaword is just like .word, but the value does not need
4080 /* Tell sparc_cons_align not to align this value. */
4081 sparc_no_align_cons
= 1;
4083 sparc_no_align_cons
= 0;
4086 /* This handles the native word allocation pseudo-op .nword.
4087 For sparc_arch_size 32 it is equivalent to .word, for
4088 sparc_arch_size 64 it is equivalent to .xword. */
4092 int bytes ATTRIBUTE_UNUSED
;
4094 cons (sparc_arch_size
== 32 ? 4 : 8);
4098 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4102 .register %g[2367],{#scratch|symbolname|#ignore}
4107 int ignore ATTRIBUTE_UNUSED
;
4112 const char *regname
;
4114 if (input_line_pointer
[0] != '%'
4115 || input_line_pointer
[1] != 'g'
4116 || ((input_line_pointer
[2] & ~1) != '2'
4117 && (input_line_pointer
[2] & ~1) != '6')
4118 || input_line_pointer
[3] != ',')
4119 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4120 reg
= input_line_pointer
[2] - '0';
4121 input_line_pointer
+= 4;
4123 if (*input_line_pointer
== '#')
4125 ++input_line_pointer
;
4126 regname
= input_line_pointer
;
4127 c
= get_symbol_end ();
4128 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4129 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4130 if (regname
[0] == 'i')
4137 regname
= input_line_pointer
;
4138 c
= get_symbol_end ();
4140 if (sparc_arch_size
== 64)
4144 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4145 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4146 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4147 as_bad (_("redefinition of global register"));
4151 if (regname
== NULL
)
4152 globals
[reg
] = (symbolS
*) 1;
4157 if (symbol_find (regname
))
4158 as_bad (_("Register symbol %s already defined."),
4161 globals
[reg
] = symbol_make (regname
);
4162 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4164 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4165 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4166 flags
|= BSF_GLOBAL
;
4167 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4168 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4169 S_SET_ALIGN (globals
[reg
], reg
);
4170 S_SET_SIZE (globals
[reg
], 0);
4171 /* Although we actually want undefined_section here,
4172 we have to use absolute_section, because otherwise
4173 generic as code will make it a COM section.
4174 We fix this up in sparc_adjust_symtab. */
4175 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4176 S_SET_OTHER (globals
[reg
], 0);
4177 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4178 ->internal_elf_sym
.st_info
=
4179 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4180 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4181 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4186 *input_line_pointer
= c
;
4188 demand_empty_rest_of_line ();
4191 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4192 symbols which need it. */
4195 sparc_adjust_symtab ()
4199 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4201 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4202 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4205 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4206 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4209 S_SET_SEGMENT (sym
, undefined_section
);
4214 /* If the --enforce-aligned-data option is used, we require .word,
4215 et. al., to be aligned correctly. We do it by setting up an
4216 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4217 no unexpected alignment was introduced.
4219 The SunOS and Solaris native assemblers enforce aligned data by
4220 default. We don't want to do that, because gcc can deliberately
4221 generate misaligned data if the packed attribute is used. Instead,
4222 we permit misaligned data by default, and permit the user to set an
4223 option to check for it. */
4226 sparc_cons_align (nbytes
)
4232 /* Only do this if we are enforcing aligned data. */
4233 if (! enforce_aligned_data
)
4236 /* Don't align if this is an unaligned pseudo-op. */
4237 if (sparc_no_align_cons
)
4240 nalign
= mylog2 (nbytes
);
4244 assert (nalign
> 0);
4246 if (now_seg
== absolute_section
)
4248 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4249 as_bad (_("misaligned data"));
4253 p
= frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4254 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4256 record_alignment (now_seg
, nalign
);
4259 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4262 sparc_handle_align (fragp
)
4268 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4270 switch (fragp
->fr_type
)
4274 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4278 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4289 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4291 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4292 if (INSN_BIG_ENDIAN
)
4293 number_to_chars_bigendian (p
, wval
, 4);
4295 number_to_chars_littleendian (p
, wval
, 4);
4301 if (INSN_BIG_ENDIAN
)
4302 number_to_chars_bigendian (p
, 0x01000000, 4);
4304 number_to_chars_littleendian (p
, 0x01000000, 4);
4306 fragp
->fr_fix
+= fix
;
4316 /* Some special processing for a Sparc ELF file. */
4319 sparc_elf_final_processing ()
4321 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4322 sort of BFD interface for this. */
4323 if (sparc_arch_size
== 64)
4325 switch (sparc_memory_model
)
4328 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4331 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4337 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4338 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4339 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4340 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4341 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4342 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4346 sparc_cons (exp
, size
)
4353 sparc_cons_special_reloc
= NULL
;
4354 save
= input_line_pointer
;
4355 if (input_line_pointer
[0] == '%'
4356 && input_line_pointer
[1] == 'r'
4357 && input_line_pointer
[2] == '_')
4359 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4361 input_line_pointer
+= 7;
4362 sparc_cons_special_reloc
= "disp";
4364 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4366 if (size
!= 4 && size
!= 8)
4367 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4370 input_line_pointer
+= 6;
4371 sparc_cons_special_reloc
= "plt";
4374 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4376 if (size
!= 4 && size
!= 8)
4377 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4380 input_line_pointer
+= 13;
4381 sparc_cons_special_reloc
= "tls_dtpoff";
4384 if (sparc_cons_special_reloc
)
4391 if (*input_line_pointer
!= '8')
4393 input_line_pointer
--;
4396 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4400 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4404 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4414 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4415 sparc_cons_special_reloc
, size
* 8, size
);
4419 input_line_pointer
+= 2;
4420 if (*input_line_pointer
!= '(')
4422 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4423 sparc_cons_special_reloc
, size
* 8);
4430 input_line_pointer
= save
;
4431 sparc_cons_special_reloc
= NULL
;
4436 char *end
= ++input_line_pointer
;
4439 while (! is_end_of_line
[(c
= *end
)])
4453 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4454 sparc_cons_special_reloc
, size
* 8);
4460 if (input_line_pointer
!= end
)
4462 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4463 sparc_cons_special_reloc
, size
* 8);
4467 input_line_pointer
++;
4469 c
= *input_line_pointer
;
4470 if (! is_end_of_line
[c
] && c
!= ',')
4471 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4472 sparc_cons_special_reloc
, size
* 8);
4478 if (sparc_cons_special_reloc
== NULL
)
4484 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4485 reloc for a cons. We could use the definition there, except that
4486 we want to handle little endian relocs specially. */
4489 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4492 unsigned int nbytes
;
4495 bfd_reloc_code_real_type r
;
4497 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4498 (nbytes
== 2 ? BFD_RELOC_16
:
4499 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4501 if (target_little_endian_data
4503 && now_seg
->flags
& SEC_ALLOC
)
4504 r
= BFD_RELOC_SPARC_REV32
;
4506 if (sparc_cons_special_reloc
)
4508 if (*sparc_cons_special_reloc
== 'd')
4511 case 1: r
= BFD_RELOC_8_PCREL
; break;
4512 case 2: r
= BFD_RELOC_16_PCREL
; break;
4513 case 4: r
= BFD_RELOC_32_PCREL
; break;
4514 case 8: r
= BFD_RELOC_64_PCREL
; break;
4517 else if (*sparc_cons_special_reloc
== 'p')
4520 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4521 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4526 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4527 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4530 else if (sparc_no_align_cons
)
4534 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4535 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4536 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4541 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4542 sparc_cons_special_reloc
= NULL
;
4546 sparc_cfi_frame_initial_instructions ()
4548 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4552 sparc_regname_to_dw2regnum (char *regname
)
4560 p
= strchr (q
, regname
[0]);
4563 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4565 return (p
- q
) * 8 + regname
[1] - '0';
4567 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4569 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4571 if (regname
[0] == 'f' || regname
[0] == 'r')
4573 unsigned int regnum
;
4575 regnum
= strtoul (regname
+ 1, &q
, 10);
4578 if (regnum
>= ((regname
[0] == 'f'
4579 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4582 if (regname
[0] == 'f')
4585 if (regnum
>= 64 && (regnum
& 1))
4594 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4596 sparc_cons_special_reloc
= "disp";
4597 sparc_no_align_cons
= 1;
4598 emit_expr (exp
, nbytes
);
4599 sparc_no_align_cons
= 0;
4600 sparc_cons_special_reloc
= NULL
;