1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch
{
246 enum sparc_arch_types arch_type
;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size
;
250 /* Allowable arg to -A? */
254 } sparc_arch_table
[] = {
255 { "v6", "v6", v6
, 0, 1, 0, 0 },
256 { "v7", "v7", v7
, 0, 1, 0, 0 },
257 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
258 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
259 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
260 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
261 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
262 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
263 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
264 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
265 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
267 { "sparc4", "v9b", v9
, 0, 1, HWS_VV
, 0 },
268 { "sparc5", "v9b", v9
, 0, 1, HWS_VM
, HWS2_VM
},
270 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
271 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
272 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
273 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
275 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
276 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
277 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
278 { "v8plusc", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
279 { "v8plusd", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
280 { "v8pluse", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
281 { "v8plusv", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
282 { "v8plusm", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
284 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
285 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
286 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
287 { "v9c", "v9b", v9
, 0, 1, HWS_VC
, 0 },
288 { "v9d", "v9b", v9
, 0, 1, HWS_VD
, 0 },
289 { "v9e", "v9b", v9
, 0, 1, HWS_VE
, 0 },
290 { "v9v", "v9b", v9
, 0, 1, HWS_VV
, 0 },
291 { "v9m", "v9b", v9
, 0, 1, HWS_VM
, HWS2_VM
},
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
296 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type
;
302 static struct sparc_arch
*
303 lookup_arch (char *name
)
305 struct sparc_arch
*sa
;
307 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
308 if (strcmp (sa
->name
, name
) == 0)
310 if (sa
->name
== NULL
)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch
*sa
= lookup_arch (default_arch
);
324 || sa
->default_arch_size
== 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
328 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
332 default_arch_type
= sa
->arch_type
;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p
)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian
)
351 return "a.out-sunos-big";
352 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts
= "A:K:VQ:sq";
443 const char *md_shortopts
= "A:k";
445 const char *md_shortopts
= "A:";
448 struct option md_longopts
[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument
, NULL
, OPTION_BUMP
},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument
, NULL
, OPTION_32
},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument
, NULL
, OPTION_64
},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument
, NULL
, OPTION_TSO
},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument
, NULL
, OPTION_PSO
},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument
, NULL
, OPTION_RMO
},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument
, NULL
, OPTION_RELAX
},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
487 {NULL
, no_argument
, NULL
, 0}
490 size_t md_longopts_size
= sizeof (md_longopts
);
493 md_parse_option (int c
, char *arg
)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p
)
498 init_default_arch ();
504 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
509 if (!strncmp (arg
, "v9", 2))
510 md_parse_option (OPTION_64
, NULL
);
513 if (!strncmp (arg
, "v8", 2)
514 || !strncmp (arg
, "v7", 2)
515 || !strncmp (arg
, "v6", 2)
516 || !strcmp (arg
, "sparclet")
517 || !strcmp (arg
, "sparclite")
518 || !strcmp (arg
, "sparc86x"))
519 md_parse_option (OPTION_32
, NULL
);
526 struct sparc_arch
*sa
;
527 enum sparc_opcode_arch_val opcode_arch
;
529 sa
= lookup_arch (arg
);
531 || ! sa
->user_option_p
)
533 if (c
== OPTION_XARCH
)
534 as_bad (_("invalid architecture -xarch=%s"), arg
);
536 as_bad (_("invalid architecture -A%s"), arg
);
540 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
541 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch
> max_architecture
)
546 max_architecture
= opcode_arch
;
548 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
678 md_show_usage (FILE *stream
)
680 const struct sparc_arch
*arch
;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p
)
686 init_default_arch ();
688 fprintf (stream
, _("SPARC options:\n"));
690 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
692 if (!arch
->user_option_p
)
694 if (arch
!= &sparc_arch_table
[0])
695 fprintf (stream
, " | ");
696 if (column
+ strlen (arch
->name
) > 70)
699 fputc ('\n', stream
);
701 column
+= 5 + 2 + strlen (arch
->name
);
702 fprintf (stream
, "-A%s", arch
->name
);
704 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
706 if (!arch
->user_option_p
)
708 fprintf (stream
, " | ");
709 if (column
+ strlen (arch
->name
) > 65)
712 fputc ('\n', stream
);
714 column
+= 5 + 7 + strlen (arch
->name
);
715 fprintf (stream
, "-xarch=%s", arch
->name
);
717 fprintf (stream
, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream
, _("\
726 -k generate PIC\n"));
729 fprintf (stream
, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream
, _("\
733 [default is %d]\n"), default_arch_size
);
734 fprintf (stream
, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream
, _("\
739 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
740 fprintf (stream
, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream
, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table
[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table
[] =
809 {"", -1}, /* End marker. */
812 struct priv_reg_entry hpriv_reg_table
[] =
819 {"hstick_offset", 28},
820 {"hstick_enable", 29},
822 {"", -1}, /* End marker. */
825 /* v9a specific asrs. This table is ordered by initial
826 letter, in reverse. */
828 struct priv_reg_entry v9a_asr_table
[] =
831 {"sys_tick_cmpr", 25},
835 {"softint_clear", 21},
846 {"clear_softint", 21},
847 {"", -1}, /* End marker. */
851 cmp_reg_entry (const void *parg
, const void *qarg
)
853 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
854 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
856 return strcmp (q
->name
, p
->name
);
859 /* This function is called once, at assembler startup time. It should
860 set up all the tables, etc. that the MD part of the assembler will
866 const char *retval
= NULL
;
870 /* We don't get a chance to initialize anything before md_parse_option
871 is called, and it may not be called, so handle default initialization
872 now if not already done. */
873 if (! default_init_p
)
874 init_default_arch ();
876 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
877 op_hash
= hash_new ();
879 while (i
< (unsigned int) sparc_num_opcodes
)
881 const char *name
= sparc_opcodes
[i
].name
;
882 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
885 as_bad (_("Internal error: can't hash `%s': %s\n"),
886 sparc_opcodes
[i
].name
, retval
);
891 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
893 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
894 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
899 while (i
< (unsigned int) sparc_num_opcodes
900 && !strcmp (sparc_opcodes
[i
].name
, name
));
903 for (i
= 0; native_op_table
[i
].name
; i
++)
905 const struct sparc_opcode
*insn
;
906 char *name
= ((sparc_arch_size
== 32)
907 ? native_op_table
[i
].name32
908 : native_op_table
[i
].name64
);
909 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
912 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
913 name
, native_op_table
[i
].name
);
918 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
922 as_bad (_("Internal error: can't hash `%s': %s\n"),
923 sparc_opcodes
[i
].name
, retval
);
930 as_fatal (_("Broken assembler. No assembly attempted."));
932 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
933 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
935 /* If -bump, record the architecture level at which we start issuing
936 warnings. The behaviour is different depending upon whether an
937 architecture was explicitly specified. If it wasn't, we issue warnings
938 for all upwards bumps. If it was, we don't start issuing warnings until
939 we need to bump beyond the requested architecture or when we bump between
940 conflicting architectures. */
943 && architecture_requested
)
945 /* `max_architecture' records the requested architecture.
946 Issue warnings if we go above it. */
947 warn_after_architecture
= max_architecture
;
950 /* Find the highest architecture level that doesn't conflict with
951 the requested one. */
954 || !architecture_requested
)
956 enum sparc_opcode_arch_val current_max_architecture
959 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
960 max_architecture
> warn_after_architecture
;
962 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
963 current_max_architecture
))
968 /* Called after all assembly has been done. */
973 unsigned long mach
= bfd_mach_sparc
;
974 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
978 if (sparc_arch_size
== 64)
979 switch (current_architecture
)
981 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
982 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
983 default: mach
= bfd_mach_sparc_v9
; break;
986 switch (current_architecture
)
988 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
989 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
990 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
991 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
992 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
993 be but for now it is (since that's the way it's always been
997 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
999 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1000 hwcaps
= hwcap_seen
& U0xffffffff
;
1001 hwcaps2
= hwcap_seen
>> 32;
1004 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1006 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1010 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1013 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1017 /* Sign-extend the value from the architecture word size, so that
1018 0xffffffff is always considered -1 on sparc32. */
1019 if (sparc_arch_size
== 32)
1021 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1022 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1031 /* Return non-zero if VAL is in the range 0 to MAX. */
1034 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1041 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1042 (e.g. -15 to +31). */
1045 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1051 if (val
< ~(max
>> 1))
1057 sparc_ffs (unsigned int mask
)
1064 for (i
= 0; (mask
& 1) == 0; ++i
)
1069 /* Implement big shift right. */
1071 BSR (bfd_vma val
, int amount
)
1073 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1074 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1075 return val
>> amount
;
1078 /* For communication between sparc_ip and get_expression. */
1079 static char *expr_end
;
1081 /* Values for `special_case'.
1082 Instructions that require wierd handling because they're longer than
1084 #define SPECIAL_CASE_NONE 0
1085 #define SPECIAL_CASE_SET 1
1086 #define SPECIAL_CASE_SETSW 2
1087 #define SPECIAL_CASE_SETX 3
1088 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1089 #define SPECIAL_CASE_FDIV 4
1091 /* Bit masks of various insns. */
1092 #define NOP_INSN 0x01000000
1093 #define OR_INSN 0x80100000
1094 #define XOR_INSN 0x80180000
1095 #define FMOVS_INSN 0x81A00020
1096 #define SETHI_INSN 0x01000000
1097 #define SLLX_INSN 0x81281000
1098 #define SRA_INSN 0x81380000
1100 /* The last instruction to be assembled. */
1101 static const struct sparc_opcode
*last_insn
;
1102 /* The assembled opcode of `last_insn'. */
1103 static unsigned long last_opcode
;
1105 /* Handle the set and setuw synthetic instructions. */
1108 synthetize_setuw (const struct sparc_opcode
*insn
)
1110 int need_hi22_p
= 0;
1111 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1113 if (the_insn
.exp
.X_op
== O_constant
)
1115 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1117 if (sizeof (offsetT
) > 4
1118 && (the_insn
.exp
.X_add_number
< 0
1119 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1120 as_warn (_("set: number not in 0..4294967295 range"));
1124 if (sizeof (offsetT
) > 4
1125 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1126 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1127 as_warn (_("set: number not in -2147483648..4294967295 range"));
1128 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1132 /* See if operand is absolute and small; skip sethi if so. */
1133 if (the_insn
.exp
.X_op
!= O_constant
1134 || the_insn
.exp
.X_add_number
>= (1 << 12)
1135 || the_insn
.exp
.X_add_number
< -(1 << 12))
1137 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1138 | ((the_insn
.exp
.X_add_number
>> 10)
1139 & (the_insn
.exp
.X_op
== O_constant
1141 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1142 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1143 output_insn (insn
, &the_insn
);
1147 /* See if operand has no low-order bits; skip OR if so. */
1148 if (the_insn
.exp
.X_op
!= O_constant
1149 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1152 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1154 | (the_insn
.exp
.X_add_number
1155 & (the_insn
.exp
.X_op
!= O_constant
1156 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1157 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1158 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1159 output_insn (insn
, &the_insn
);
1163 /* Handle the setsw synthetic instruction. */
1166 synthetize_setsw (const struct sparc_opcode
*insn
)
1170 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1172 if (the_insn
.exp
.X_op
!= O_constant
)
1174 synthetize_setuw (insn
);
1176 /* Need to sign extend it. */
1177 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1178 the_insn
.reloc
= BFD_RELOC_NONE
;
1179 output_insn (insn
, &the_insn
);
1183 if (sizeof (offsetT
) > 4
1184 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1185 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1186 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1188 low32
= the_insn
.exp
.X_add_number
;
1192 synthetize_setuw (insn
);
1198 the_insn
.reloc
= BFD_RELOC_NONE
;
1199 /* See if operand is absolute and small; skip sethi if so. */
1200 if (low32
< -(1 << 12))
1202 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1203 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1204 output_insn (insn
, &the_insn
);
1205 low32
= 0x1c00 | (low32
& 0x3ff);
1206 opc
= RS1 (rd
) | XOR_INSN
;
1209 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1210 | (low32
& 0x1fff));
1211 output_insn (insn
, &the_insn
);
1214 /* Handle the setsw synthetic instruction. */
1217 synthetize_setx (const struct sparc_opcode
*insn
)
1219 int upper32
, lower32
;
1220 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1221 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1223 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1224 int need_xor10_p
= 0;
1226 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1227 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1228 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1231 upper_dstreg
= tmpreg
;
1232 /* The tmp reg should not be the dst reg. */
1233 if (tmpreg
== dstreg
)
1234 as_warn (_("setx: temporary register same as destination register"));
1236 /* ??? Obviously there are other optimizations we can do
1237 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1238 doing some of these. Later. If you do change things, try to
1239 change all of this to be table driven as well. */
1240 /* What to output depends on the number if it's constant.
1241 Compute that first, then output what we've decided upon. */
1242 if (the_insn
.exp
.X_op
!= O_constant
)
1244 if (sparc_arch_size
== 32)
1246 /* When arch size is 32, we want setx to be equivalent
1247 to setuw for anything but constants. */
1248 the_insn
.exp
.X_add_number
&= 0xffffffff;
1249 synthetize_setuw (insn
);
1252 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1258 /* Reset X_add_number, we've extracted it as upper32/lower32.
1259 Otherwise fixup_segment will complain about not being able to
1260 write an 8 byte number in a 4 byte field. */
1261 the_insn
.exp
.X_add_number
= 0;
1263 /* Only need hh22 if `or' insn can't handle constant. */
1264 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1267 /* Does bottom part (after sethi) have bits? */
1268 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1269 /* No hh22, but does upper32 still have bits we can't set
1271 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1274 /* If the lower half is all zero, we build the upper half directly
1275 into the dst reg. */
1277 /* Need lower half if number is zero or 0xffffffff00000000. */
1278 || (! need_hh22_p
&& ! need_hm10_p
))
1280 /* No need for sethi if `or' insn can handle constant. */
1281 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1282 /* Note that we can't use a negative constant in the `or'
1283 insn unless the upper 32 bits are all ones. */
1284 || (lower32
< 0 && upper32
!= -1)
1285 || (lower32
>= 0 && upper32
== -1))
1288 if (need_hi22_p
&& upper32
== -1)
1291 /* Does bottom part (after sethi) have bits? */
1292 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1294 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1295 /* Need `or' if we didn't set anything else. */
1296 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1300 /* Output directly to dst reg if lower 32 bits are all zero. */
1301 upper_dstreg
= dstreg
;
1304 if (!upper_dstreg
&& dstreg
)
1305 as_warn (_("setx: illegal temporary register g0"));
1309 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1310 | ((upper32
>> 10) & 0x3fffff));
1311 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1312 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1313 output_insn (insn
, &the_insn
);
1318 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1319 | (((need_xor10_p
? ~lower32
: lower32
)
1320 >> 10) & 0x3fffff));
1321 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1322 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1323 output_insn (insn
, &the_insn
);
1328 the_insn
.opcode
= (OR_INSN
1329 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1332 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1333 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1334 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1335 output_insn (insn
, &the_insn
);
1340 /* FIXME: One nice optimization to do here is to OR the low part
1341 with the highpart if hi22 isn't needed and the low part is
1343 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1346 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1347 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1348 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1349 output_insn (insn
, &the_insn
);
1352 /* If we needed to build the upper part, shift it into place. */
1353 if (need_hh22_p
|| need_hm10_p
)
1355 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1357 the_insn
.reloc
= BFD_RELOC_NONE
;
1358 output_insn (insn
, &the_insn
);
1361 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1364 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1365 | 0x1c00 | (lower32
& 0x3ff));
1366 the_insn
.reloc
= BFD_RELOC_NONE
;
1367 output_insn (insn
, &the_insn
);
1370 /* If we needed to build both upper and lower parts, OR them together. */
1371 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1373 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1375 the_insn
.reloc
= BFD_RELOC_NONE
;
1376 output_insn (insn
, &the_insn
);
1380 /* Main entry point to assemble one instruction. */
1383 md_assemble (char *str
)
1385 const struct sparc_opcode
*insn
;
1389 special_case
= sparc_ip (str
, &insn
);
1393 /* We warn about attempts to put a floating point branch in a delay slot,
1394 unless the delay slot has been annulled. */
1395 if (last_insn
!= NULL
1396 && (insn
->flags
& F_FBR
) != 0
1397 && (last_insn
->flags
& F_DELAYED
) != 0
1398 /* ??? This test isn't completely accurate. We assume anything with
1399 F_{UNBR,CONDBR,FBR} set is annullable. */
1400 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1401 || (last_opcode
& ANNUL
) == 0))
1402 as_warn (_("FP branch in delay slot"));
1404 /* SPARC before v9 requires a nop instruction between a floating
1405 point instruction and a floating point branch. We insert one
1406 automatically, with a warning. */
1407 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1408 && last_insn
!= NULL
1409 && (insn
->flags
& F_FBR
) != 0
1410 && (last_insn
->flags
& F_FLOAT
) != 0)
1412 struct sparc_it nop_insn
;
1414 nop_insn
.opcode
= NOP_INSN
;
1415 nop_insn
.reloc
= BFD_RELOC_NONE
;
1416 output_insn (insn
, &nop_insn
);
1417 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1420 switch (special_case
)
1422 case SPECIAL_CASE_NONE
:
1424 output_insn (insn
, &the_insn
);
1427 case SPECIAL_CASE_SETSW
:
1428 synthetize_setsw (insn
);
1431 case SPECIAL_CASE_SET
:
1432 synthetize_setuw (insn
);
1435 case SPECIAL_CASE_SETX
:
1436 synthetize_setx (insn
);
1439 case SPECIAL_CASE_FDIV
:
1441 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1443 output_insn (insn
, &the_insn
);
1445 /* According to information leaked from Sun, the "fdiv" instructions
1446 on early SPARC machines would produce incorrect results sometimes.
1447 The workaround is to add an fmovs of the destination register to
1448 itself just after the instruction. This was true on machines
1449 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1450 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1451 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1452 output_insn (insn
, &the_insn
);
1457 as_fatal (_("failed special case insn sanity check"));
1462 get_hwcap_name (bfd_uint64_t mask
)
1464 if (mask
& HWCAP_MUL32
)
1466 if (mask
& HWCAP_DIV32
)
1468 if (mask
& HWCAP_FSMULD
)
1470 if (mask
& HWCAP_V8PLUS
)
1472 if (mask
& HWCAP_POPC
)
1474 if (mask
& HWCAP_VIS
)
1476 if (mask
& HWCAP_VIS2
)
1478 if (mask
& HWCAP_ASI_BLK_INIT
)
1479 return "ASIBlkInit";
1480 if (mask
& HWCAP_FMAF
)
1482 if (mask
& HWCAP_VIS3
)
1484 if (mask
& HWCAP_HPC
)
1486 if (mask
& HWCAP_RANDOM
)
1488 if (mask
& HWCAP_TRANS
)
1490 if (mask
& HWCAP_FJFMAU
)
1492 if (mask
& HWCAP_IMA
)
1494 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1496 if (mask
& HWCAP_AES
)
1498 if (mask
& HWCAP_DES
)
1500 if (mask
& HWCAP_KASUMI
)
1502 if (mask
& HWCAP_CAMELLIA
)
1504 if (mask
& HWCAP_MD5
)
1506 if (mask
& HWCAP_SHA1
)
1508 if (mask
& HWCAP_SHA256
)
1510 if (mask
& HWCAP_SHA512
)
1512 if (mask
& HWCAP_MPMUL
)
1514 if (mask
& HWCAP_MONT
)
1516 if (mask
& HWCAP_PAUSE
)
1518 if (mask
& HWCAP_CBCOND
)
1520 if (mask
& HWCAP_CRC32C
)
1524 if (mask
& HWCAP2_FJATHPLUS
)
1526 if (mask
& HWCAP2_VIS3B
)
1528 if (mask
& HWCAP2_ADP
)
1530 if (mask
& HWCAP2_SPARC5
)
1532 if (mask
& HWCAP2_MWAIT
)
1534 if (mask
& HWCAP2_XMPMUL
)
1536 if (mask
& HWCAP2_XMONT
)
1538 if (mask
& HWCAP2_NSEC
)
1544 /* Subroutine of md_assemble to do the actual parsing. */
1547 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1549 char *error_message
= "";
1553 const struct sparc_opcode
*insn
;
1555 unsigned long opcode
;
1556 unsigned int mask
= 0;
1560 int special_case
= SPECIAL_CASE_NONE
;
1567 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1584 as_bad (_("Unknown opcode: `%s'"), str
);
1586 return special_case
;
1588 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1592 as_bad (_("Unknown opcode: `%s'"), str
);
1593 return special_case
;
1603 opcode
= insn
->match
;
1604 memset (&the_insn
, '\0', sizeof (the_insn
));
1605 the_insn
.reloc
= BFD_RELOC_NONE
;
1608 /* Build the opcode, checking as we go to make sure that the
1610 for (args
= insn
->args
;; ++args
)
1618 /* Parse a series of masks. */
1625 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1628 error_message
= _(": invalid membar mask name");
1634 if (*s
== '|' || *s
== '+')
1642 if (! parse_const_expr_arg (&s
, &kmask
))
1644 error_message
= _(": invalid membar mask expression");
1647 if (kmask
< 0 || kmask
> 127)
1649 error_message
= _(": invalid membar mask number");
1654 opcode
|= MEMBAR (kmask
);
1662 if (! parse_const_expr_arg (&s
, &smask
))
1664 error_message
= _(": invalid siam mode expression");
1667 if (smask
< 0 || smask
> 7)
1669 error_message
= _(": invalid siam mode number");
1680 /* Parse a prefetch function. */
1683 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1685 error_message
= _(": invalid prefetch function name");
1691 if (! parse_const_expr_arg (&s
, &fcn
))
1693 error_message
= _(": invalid prefetch function expression");
1696 if (fcn
< 0 || fcn
> 31)
1698 error_message
= _(": invalid prefetch function number");
1708 /* Parse a sparc64 privileged register. */
1711 struct priv_reg_entry
*p
= priv_reg_table
;
1712 unsigned int len
= 9999999; /* Init to make gcc happy. */
1715 while (p
->name
[0] > s
[0])
1717 while (p
->name
[0] == s
[0])
1719 len
= strlen (p
->name
);
1720 if (strncmp (p
->name
, s
, len
) == 0)
1724 if (p
->name
[0] != s
[0])
1726 error_message
= _(": unrecognizable privileged register");
1730 opcode
|= (p
->regnum
<< 14);
1732 opcode
|= (p
->regnum
<< 25);
1738 error_message
= _(": unrecognizable privileged register");
1744 /* Parse a sparc64 hyperprivileged register. */
1747 struct priv_reg_entry
*p
= hpriv_reg_table
;
1748 unsigned int len
= 9999999; /* Init to make gcc happy. */
1751 while (p
->name
[0] > s
[0])
1753 while (p
->name
[0] == s
[0])
1755 len
= strlen (p
->name
);
1756 if (strncmp (p
->name
, s
, len
) == 0)
1760 if (p
->name
[0] != s
[0])
1762 error_message
= _(": unrecognizable hyperprivileged register");
1766 opcode
|= (p
->regnum
<< 14);
1768 opcode
|= (p
->regnum
<< 25);
1774 error_message
= _(": unrecognizable hyperprivileged register");
1780 /* Parse a v9a/v9b ancillary state register. */
1783 struct priv_reg_entry
*p
= v9a_asr_table
;
1784 unsigned int len
= 9999999; /* Init to make gcc happy. */
1787 while (p
->name
[0] > s
[0])
1789 while (p
->name
[0] == s
[0])
1791 len
= strlen (p
->name
);
1792 if (strncmp (p
->name
, s
, len
) == 0)
1796 if (p
->name
[0] != s
[0])
1798 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1801 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1803 error_message
= _(": rd on write only ancillary state register");
1807 && (insn
->architecture
1808 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1810 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1811 error_message
= _(": unrecognizable v9a ancillary state register");
1815 opcode
|= (p
->regnum
<< 14);
1817 opcode
|= (p
->regnum
<< 25);
1823 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1829 if (strncmp (s
, "%asr", 4) == 0)
1837 while (ISDIGIT (*s
))
1839 num
= num
* 10 + *s
- '0';
1843 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1845 if (num
< 16 || 31 < num
)
1847 error_message
= _(": asr number must be between 16 and 31");
1853 if (num
< 0 || 31 < num
)
1855 error_message
= _(": asr number must be between 0 and 31");
1860 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1865 error_message
= _(": expecting %asrN");
1872 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1876 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1882 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
1887 if (s
[0] == '0' && s
[1] == 'x')
1890 while (ISXDIGIT (*s
))
1893 num
|= hex_value (*s
);
1899 while (ISDIGIT (*s
))
1901 num
= num
* 10 + *s
- '0';
1905 if (num
< 0 || num
> 31)
1907 error_message
= _(": crypto immediate must be between 0 and 31");
1911 opcode
|= RS3 (num
);
1916 error_message
= _(": expecting crypto immediate");
1921 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1922 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1923 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1925 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1926 /* These fields are unsigned, but for upward compatibility,
1927 allow negative values as well. */
1931 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1932 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1933 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1935 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1936 /* These fields are unsigned, but for upward compatibility,
1937 allow negative values as well. */
1941 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1946 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
1951 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1956 if (*s
== 'p' && s
[1] == 'n')
1964 if (*s
== 'p' && s
[1] == 't')
1976 if (strncmp (s
, "%icc", 4) == 0)
1988 if (strncmp (s
, "%xcc", 4) == 0)
2000 if (strncmp (s
, "%fcc0", 5) == 0)
2012 if (strncmp (s
, "%fcc1", 5) == 0)
2024 if (strncmp (s
, "%fcc2", 5) == 0)
2036 if (strncmp (s
, "%fcc3", 5) == 0)
2044 if (strncmp (s
, "%pc", 3) == 0)
2052 if (strncmp (s
, "%tick", 5) == 0)
2059 case '\0': /* End of args. */
2060 if (s
[0] == ',' && s
[1] == '%')
2062 static const struct ops
2064 /* The name as it appears in assembler. */
2066 /* strlen (name), precomputed for speed */
2068 /* The reloc this pseudo-op translates to. */
2070 /* 1 if tls call. */
2075 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
2076 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
2077 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
2078 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
2079 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
2080 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
2081 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
2082 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
2083 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
2086 const struct ops
*o
;
2090 for (o
= ops
; o
->name
; o
++)
2091 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
2093 if (o
->name
== NULL
)
2096 if (s
[o
->len
+ 2] != '(')
2098 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2099 return special_case
;
2102 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
2104 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2106 return special_case
;
2110 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2111 || the_insn
.exp
.X_add_number
!= 0
2112 || the_insn
.exp
.X_add_symbol
2113 != symbol_find_or_make ("__tls_get_addr")))
2115 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2117 return special_case
;
2120 the_insn
.reloc
= o
->reloc
;
2121 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2124 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2127 else if (*s1
== ')')
2136 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2137 return special_case
;
2141 (void) get_expression (s
);
2161 case '[': /* These must match exactly. */
2169 case '#': /* Must be at least one digit. */
2172 while (ISDIGIT (*s
))
2180 case 'C': /* Coprocessor state register. */
2181 if (strncmp (s
, "%csr", 4) == 0)
2188 case 'b': /* Next operand is a coprocessor register. */
2191 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2196 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2210 opcode
|= mask
<< 14;
2218 opcode
|= mask
<< 25;
2224 case 'r': /* next operand must be a register */
2234 case 'f': /* frame pointer */
2242 case 'g': /* global register */
2251 case 'i': /* in register */
2255 mask
= c
- '0' + 24;
2260 case 'l': /* local register */
2264 mask
= (c
- '0' + 16);
2269 case 'o': /* out register */
2273 mask
= (c
- '0' + 8);
2278 case 's': /* stack pointer */
2286 case 'r': /* any register */
2287 if (!ISDIGIT ((c
= *s
++)))
2304 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2320 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2321 && no_undeclared_regs
&& ! globals
[mask
])
2322 as_bad (_("detected global register use not covered by .register pseudo-op"));
2324 /* Got the register, now figure out where
2325 it goes in the opcode. */
2329 opcode
|= mask
<< 14;
2337 opcode
|= mask
<< 25;
2341 opcode
|= (mask
<< 25) | (mask
<< 14);
2345 opcode
|= (mask
<< 25) | (mask
<< 0);
2351 case 'e': /* next operand is a floating point register */
2370 && ((format
= *s
) == 'f')
2373 for (mask
= 0; ISDIGIT (*s
); ++s
)
2375 mask
= 10 * mask
+ (*s
- '0');
2376 } /* read the number */
2385 } /* register must be even numbered */
2393 } /* register must be multiple of 4 */
2397 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2398 error_message
= _(": There are only 64 f registers; [0-63]");
2400 error_message
= _(": There are only 32 f registers; [0-31]");
2403 else if (mask
>= 32)
2405 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2407 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2410 = _(": There are only 32 single precision f registers; [0-31]");
2414 mask
-= 31; /* wrap high bit */
2418 error_message
= _(": There are only 32 f registers; [0-31]");
2426 } /* if not an 'f' register. */
2428 if (*args
== '}' && mask
!= RS2 (opcode
))
2431 = _(": Instruction requires frs2 and frsd must be the same register");
2440 opcode
|= RS1 (mask
);
2446 opcode
|= RS2 (mask
);
2451 opcode
|= RS3 (mask
);
2458 opcode
|= RD (mask
);
2467 if (strncmp (s
, "%fsr", 4) == 0)
2475 if (strncmp (s
, "%efsr", 5) == 0)
2482 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2483 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2486 case 'l': /* 22 bit PC relative immediate */
2487 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2491 case 'L': /* 30 bit immediate */
2492 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2497 case 'n': /* 22 bit immediate */
2498 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2501 case 'i': /* 13 bit immediate */
2502 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2512 char *op_arg
= NULL
;
2513 static expressionS op_exp
;
2514 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2516 /* Check for %hi, etc. */
2519 static const struct ops
{
2520 /* The name as it appears in assembler. */
2522 /* strlen (name), precomputed for speed */
2524 /* The reloc this pseudo-op translates to. */
2526 /* Non-zero if for v9 only. */
2528 /* Non-zero if can be used in pc-relative contexts. */
2529 int pcrel_p
;/*FIXME:wip*/
2531 /* hix/lox must appear before hi/lo so %hix won't be
2532 mistaken for %hi. */
2533 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2534 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2535 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2536 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2537 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2538 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2539 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2540 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2541 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2542 { "h34", 3, BFD_RELOC_SPARC_H34
, 1, 0 },
2543 { "l34", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2544 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2545 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2546 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2547 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2548 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2549 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2550 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2551 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2552 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2553 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2555 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2557 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2558 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2559 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2560 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2561 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2563 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2565 { NULL
, 0, 0, 0, 0 }
2567 const struct ops
*o
;
2569 for (o
= ops
; o
->name
; o
++)
2570 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2572 if (o
->name
== NULL
)
2575 if (s
[o
->len
+ 1] != '(')
2577 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2578 return special_case
;
2582 the_insn
.reloc
= o
->reloc
;
2587 /* Note that if the get_expression() fails, we will still
2588 have created U entries in the symbol table for the
2589 'symbols' in the input string. Try not to create U
2590 symbols for registers, etc. */
2592 /* This stuff checks to see if the expression ends in
2593 +%reg. If it does, it removes the register from
2594 the expression, and re-sets 's' to point to the
2601 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2604 else if (*s1
== ')')
2613 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2614 return special_case
;
2618 (void) get_expression (s
);
2621 if (*s
== ',' || *s
== ']' || !*s
)
2623 if (*s
!= '+' && *s
!= '-')
2625 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2626 return special_case
;
2630 op_exp
= the_insn
.exp
;
2631 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2634 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2637 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2639 if (s1
[-2] == '%' && s1
[-3] == '+')
2641 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2643 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2650 if (op_arg
&& s1
== s
+ 1)
2651 the_insn
.exp
.X_op
= O_absent
;
2653 (void) get_expression (s
);
2665 (void) get_expression (s
);
2673 the_insn
.exp2
= the_insn
.exp
;
2674 the_insn
.exp
= op_exp
;
2675 if (the_insn
.exp2
.X_op
== O_absent
)
2676 the_insn
.exp2
.X_op
= O_illegal
;
2677 else if (the_insn
.exp
.X_op
== O_absent
)
2679 the_insn
.exp
= the_insn
.exp2
;
2680 the_insn
.exp2
.X_op
= O_illegal
;
2682 else if (the_insn
.exp
.X_op
== O_constant
)
2684 valueT val
= the_insn
.exp
.X_add_number
;
2685 switch (the_insn
.reloc
)
2690 case BFD_RELOC_SPARC_HH22
:
2691 val
= BSR (val
, 32);
2694 case BFD_RELOC_SPARC_LM22
:
2695 case BFD_RELOC_HI22
:
2696 val
= (val
>> 10) & 0x3fffff;
2699 case BFD_RELOC_SPARC_HM10
:
2700 val
= BSR (val
, 32);
2703 case BFD_RELOC_LO10
:
2707 case BFD_RELOC_SPARC_H34
:
2712 case BFD_RELOC_SPARC_H44
:
2717 case BFD_RELOC_SPARC_M44
:
2722 case BFD_RELOC_SPARC_L44
:
2726 case BFD_RELOC_SPARC_HIX22
:
2728 val
= (val
>> 10) & 0x3fffff;
2731 case BFD_RELOC_SPARC_LOX10
:
2732 val
= (val
& 0x3ff) | 0x1c00;
2735 the_insn
.exp
= the_insn
.exp2
;
2736 the_insn
.exp
.X_add_number
+= val
;
2737 the_insn
.exp2
.X_op
= O_illegal
;
2738 the_insn
.reloc
= old_reloc
;
2740 else if (the_insn
.exp2
.X_op
!= O_constant
)
2742 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2743 return special_case
;
2747 if (old_reloc
!= BFD_RELOC_SPARC13
2748 || the_insn
.reloc
!= BFD_RELOC_LO10
2749 || sparc_arch_size
!= 64
2752 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2753 return special_case
;
2755 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2759 /* Check for constants that don't require emitting a reloc. */
2760 if (the_insn
.exp
.X_op
== O_constant
2761 && the_insn
.exp
.X_add_symbol
== 0
2762 && the_insn
.exp
.X_op_symbol
== 0)
2764 /* For pc-relative call instructions, we reject
2765 constants to get better code. */
2767 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2768 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2770 error_message
= _(": PC-relative operand can't be a constant");
2774 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2775 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2777 error_message
= _(": TLS operand can't be a constant");
2781 /* Constants that won't fit are checked in md_apply_fix
2782 and bfd_install_relocation.
2783 ??? It would be preferable to install the constants
2784 into the insn here and save having to create a fixS
2785 for each one. There already exists code to handle
2786 all the various cases (e.g. in md_apply_fix and
2787 bfd_install_relocation) so duplicating all that code
2788 here isn't right. */
2790 /* This is a special case to handle cbcond instructions
2791 properly, which can need two relocations. The first
2792 one is for the 5-bit immediate field and the latter
2793 is going to be for the WDISP10 branch part. We
2794 handle the R_SPARC_5 immediate directly here so that
2795 we don't need to add support for multiple relocations
2796 in one instruction just yet. */
2797 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2799 valueT val
= the_insn
.exp
.X_add_number
;
2801 if (! in_bitfield_range (val
, 0x1f))
2803 error_message
= _(": Immediate value in cbcond is out of range.");
2806 opcode
|= val
& 0x1f;
2807 the_insn
.reloc
= BFD_RELOC_NONE
;
2828 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2830 error_message
= _(": invalid ASI name");
2836 if (! parse_const_expr_arg (&s
, &asi
))
2838 error_message
= _(": invalid ASI expression");
2841 if (asi
< 0 || asi
> 255)
2843 error_message
= _(": invalid ASI number");
2847 opcode
|= ASI (asi
);
2849 } /* Alternate space. */
2852 if (strncmp (s
, "%psr", 4) == 0)
2859 case 'q': /* Floating point queue. */
2860 if (strncmp (s
, "%fq", 3) == 0)
2867 case 'Q': /* Coprocessor queue. */
2868 if (strncmp (s
, "%cq", 3) == 0)
2876 if (strcmp (str
, "set") == 0
2877 || strcmp (str
, "setuw") == 0)
2879 special_case
= SPECIAL_CASE_SET
;
2882 else if (strcmp (str
, "setsw") == 0)
2884 special_case
= SPECIAL_CASE_SETSW
;
2887 else if (strcmp (str
, "setx") == 0)
2889 special_case
= SPECIAL_CASE_SETX
;
2892 else if (strncmp (str
, "fdiv", 4) == 0)
2894 special_case
= SPECIAL_CASE_FDIV
;
2900 if (strncmp (s
, "%asi", 4) != 0)
2906 if (strncmp (s
, "%fprs", 5) != 0)
2912 if (strncmp (s
, "%mcdper",7) != 0)
2918 if (strncmp (s
, "%ccr", 4) != 0)
2924 if (strncmp (s
, "%tbr", 4) != 0)
2930 if (strncmp (s
, "%wim", 4) != 0)
2937 char *push
= input_line_pointer
;
2940 input_line_pointer
= s
;
2942 if (e
.X_op
== O_constant
)
2944 int n
= e
.X_add_number
;
2945 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2946 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2948 opcode
|= e
.X_add_number
<< 5;
2951 as_bad (_("non-immediate OPF operand, ignored"));
2952 s
= input_line_pointer
;
2953 input_line_pointer
= push
;
2958 if (strncmp (s
, "%y", 2) != 0)
2966 /* Parse a sparclet cpreg. */
2968 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2970 error_message
= _(": invalid cpreg name");
2973 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2978 as_fatal (_("failed sanity check."));
2979 } /* switch on arg code. */
2981 /* Break out of for() loop. */
2983 } /* For each arg that we expect. */
2988 /* Args don't match. */
2989 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2990 && (insn
->name
== insn
[1].name
2991 || !strcmp (insn
->name
, insn
[1].name
)))
2999 as_bad (_("Illegal operands%s"), error_message
);
3000 return special_case
;
3005 /* We have a match. Now see if the architecture is OK. */
3006 int needed_arch_mask
= insn
->architecture
;
3008 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3010 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3012 hwcap_seen
|= hwcaps
;
3017 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3018 if (! needed_arch_mask
)
3020 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3023 if (needed_arch_mask
3024 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3027 /* Can we bump up the architecture? */
3028 else if (needed_arch_mask
3029 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3031 enum sparc_opcode_arch_val needed_architecture
=
3032 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3033 & needed_arch_mask
);
3035 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3037 && needed_architecture
> warn_after_architecture
)
3039 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3040 sparc_opcode_archs
[current_architecture
].name
,
3041 sparc_opcode_archs
[needed_architecture
].name
,
3043 warn_after_architecture
= needed_architecture
;
3045 current_architecture
= needed_architecture
;
3046 hwcap_allowed
|= hwcaps
;
3049 /* ??? This seems to be a bit fragile. What if the next entry in
3050 the opcode table is the one we want and it is supported?
3051 It is possible to arrange the table today so that this can't
3052 happen but what about tomorrow? */
3055 int arch
, printed_one_p
= 0;
3057 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3059 /* Create a list of the architectures that support the insn. */
3060 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3062 arch
= sparc_ffs (needed_arch_mask
);
3063 while ((1 << arch
) <= needed_arch_mask
)
3065 if ((1 << arch
) & needed_arch_mask
)
3069 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3076 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3077 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3079 sparc_opcode_archs
[max_architecture
].name
);
3080 return special_case
;
3083 /* Make sure the hwcaps used by the instruction are
3084 currently enabled. */
3085 if (hwcaps
& ~hwcap_allowed
)
3087 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3089 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3091 return special_case
;
3093 } /* If no match. */
3096 } /* Forever looking for a match. */
3098 the_insn
.opcode
= opcode
;
3099 return special_case
;
3102 /* Parse an argument that can be expressed as a keyword.
3103 (eg: #StoreStore or %ccfr).
3104 The result is a boolean indicating success.
3105 If successful, INPUT_POINTER is updated. */
3108 parse_keyword_arg (int (*lookup_fn
) (const char *),
3109 char **input_pointerP
,
3115 p
= *input_pointerP
;
3116 for (q
= p
+ (*p
== '#' || *p
== '%');
3117 ISALNUM (*q
) || *q
== '_';
3122 value
= (*lookup_fn
) (p
);
3127 *input_pointerP
= q
;
3131 /* Parse an argument that is a constant expression.
3132 The result is a boolean indicating success. */
3135 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3137 char *save
= input_line_pointer
;
3140 input_line_pointer
= *input_pointerP
;
3141 /* The next expression may be something other than a constant
3142 (say if we're not processing the right variant of the insn).
3143 Don't call expression unless we're sure it will succeed as it will
3144 signal an error (which we want to defer until later). */
3145 /* FIXME: It might be better to define md_operand and have it recognize
3146 things like %asi, etc. but continuing that route through to the end
3147 is a lot of work. */
3148 if (*input_line_pointer
== '%')
3150 input_line_pointer
= save
;
3154 *input_pointerP
= input_line_pointer
;
3155 input_line_pointer
= save
;
3156 if (exp
.X_op
!= O_constant
)
3158 *valueP
= exp
.X_add_number
;
3162 /* Subroutine of sparc_ip to parse an expression. */
3165 get_expression (char *str
)
3170 save_in
= input_line_pointer
;
3171 input_line_pointer
= str
;
3172 seg
= expression (&the_insn
.exp
);
3173 if (seg
!= absolute_section
3174 && seg
!= text_section
3175 && seg
!= data_section
3176 && seg
!= bss_section
3177 && seg
!= undefined_section
)
3179 the_insn
.error
= _("bad segment");
3180 expr_end
= input_line_pointer
;
3181 input_line_pointer
= save_in
;
3184 expr_end
= input_line_pointer
;
3185 input_line_pointer
= save_in
;
3189 /* Subroutine of md_assemble to output one insn. */
3192 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3194 char *toP
= frag_more (4);
3196 /* Put out the opcode. */
3197 if (INSN_BIG_ENDIAN
)
3198 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3200 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3202 /* Put out the symbol-dependent stuff. */
3203 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3205 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3206 (toP
- frag_now
->fr_literal
), /* Where. */
3211 /* Turn off overflow checking in fixup_segment. We'll do our
3212 own overflow checking in md_apply_fix. This is necessary because
3213 the insn size is 4 and fixup_segment will signal an overflow for
3214 large 8 byte quantities. */
3215 fixP
->fx_no_overflow
= 1;
3216 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3217 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3221 last_opcode
= theinsn
->opcode
;
3224 dwarf2_emit_insn (4);
3229 md_atof (int type
, char *litP
, int *sizeP
)
3231 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3234 /* Write a value out to the object file, using the appropriate
3238 md_number_to_chars (char *buf
, valueT val
, int n
)
3240 if (target_big_endian
)
3241 number_to_chars_bigendian (buf
, val
, n
);
3242 else if (target_little_endian_data
3243 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3244 /* Output debug words, which are not in allocated sections, as big
3246 number_to_chars_bigendian (buf
, val
, n
);
3247 else if (target_little_endian_data
|| ! target_big_endian
)
3248 number_to_chars_littleendian (buf
, val
, n
);
3251 /* Apply a fixS to the frags, now that we know the value it ought to
3255 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3257 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3258 offsetT val
= * (offsetT
*) valP
;
3261 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3263 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3266 /* SPARC ELF relocations don't use an addend in the data field. */
3267 if (fixP
->fx_addsy
!= NULL
)
3269 switch (fixP
->fx_r_type
)
3271 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3272 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3273 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3274 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3275 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3276 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3277 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3278 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3279 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3280 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3281 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3282 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3283 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3284 case BFD_RELOC_SPARC_TLS_IE_LD
:
3285 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3286 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3287 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3288 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3289 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3290 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3291 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3292 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3293 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3294 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3295 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3305 /* This is a hack. There should be a better way to
3306 handle this. Probably in terms of howto fields, once
3307 we can look at these fixups in terms of howtos. */
3308 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3309 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3312 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3313 generate a reloc, then we just want to let the reloc addend set
3314 the value. We do not want to also stuff the addend into the
3315 object file. Including the addend in the object file works when
3316 doing a static link, because the linker will ignore the object
3317 file contents. However, the dynamic linker does not ignore the
3318 object file contents. */
3319 if (fixP
->fx_addsy
!= NULL
3320 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3323 /* When generating PIC code, we do not want an addend for a reloc
3324 against a local symbol. We adjust fx_addnumber to cancel out the
3325 value already included in val, and to also cancel out the
3326 adjustment which bfd_install_relocation will create. */
3328 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3329 && fixP
->fx_addsy
!= NULL
3330 && ! S_IS_COMMON (fixP
->fx_addsy
)
3331 && symbol_section_p (fixP
->fx_addsy
))
3332 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3334 /* When generating PIC code, we need to fiddle to get
3335 bfd_install_relocation to do the right thing for a PC relative
3336 reloc against a local symbol which we are going to keep. */
3338 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3339 && fixP
->fx_addsy
!= NULL
3340 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3341 || S_IS_WEAK (fixP
->fx_addsy
))
3342 && S_IS_DEFINED (fixP
->fx_addsy
)
3343 && ! S_IS_COMMON (fixP
->fx_addsy
))
3346 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3350 /* If this is a data relocation, just output VAL. */
3352 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3354 md_number_to_chars (buf
, val
, 1);
3356 else if (fixP
->fx_r_type
== BFD_RELOC_16
3357 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3359 md_number_to_chars (buf
, val
, 2);
3361 else if (fixP
->fx_r_type
== BFD_RELOC_32
3362 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3363 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3365 md_number_to_chars (buf
, val
, 4);
3367 else if (fixP
->fx_r_type
== BFD_RELOC_64
3368 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3370 md_number_to_chars (buf
, val
, 8);
3372 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3373 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3380 /* It's a relocation against an instruction. */
3382 if (INSN_BIG_ENDIAN
)
3383 insn
= bfd_getb32 ((unsigned char *) buf
);
3385 insn
= bfd_getl32 ((unsigned char *) buf
);
3387 switch (fixP
->fx_r_type
)
3389 case BFD_RELOC_32_PCREL_S2
:
3391 /* FIXME: This increment-by-one deserves a comment of why it's
3393 if (! sparc_pic_code
3394 || fixP
->fx_addsy
== NULL
3395 || symbol_section_p (fixP
->fx_addsy
))
3398 insn
|= val
& 0x3fffffff;
3400 /* See if we have a delay slot. */
3401 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3405 #define XCC (2 << 20)
3406 #define COND(x) (((x)&0xf)<<25)
3407 #define CONDA COND(0x8)
3408 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3409 #define INSN_BA (F2(0,2) | CONDA)
3410 #define INSN_OR F3(2, 0x2, 0)
3411 #define INSN_NOP F2(0,4)
3415 /* If the instruction is a call with either:
3417 arithmetic instruction with rd == %o7
3418 where rs1 != %o7 and rs2 if it is register != %o7
3419 then we can optimize if the call destination is near
3420 by changing the call into a branch always. */
3421 if (INSN_BIG_ENDIAN
)
3422 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3424 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3425 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3427 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3428 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3429 || ((delay
& RD (~0)) != RD (O7
))))
3431 if ((delay
& RS1 (~0)) == RS1 (O7
)
3432 || ((delay
& F3I (~0)) == 0
3433 && (delay
& RS2 (~0)) == RS2 (O7
)))
3435 /* Ensure the branch will fit into simm22. */
3436 if ((val
& 0x3fe00000)
3437 && (val
& 0x3fe00000) != 0x3fe00000)
3439 /* Check if the arch is v9 and branch will fit
3441 if (((val
& 0x3c0000) == 0
3442 || (val
& 0x3c0000) == 0x3c0000)
3443 && (sparc_arch_size
== 64
3444 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3446 insn
= INSN_BPA
| (val
& 0x7ffff);
3449 insn
= INSN_BA
| (val
& 0x3fffff);
3450 if (fixP
->fx_where
>= 4
3451 && ((delay
& (0xffffffff ^ RS1 (~0)))
3452 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3457 if (INSN_BIG_ENDIAN
)
3458 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3460 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3461 if ((setter
& (0xffffffff ^ RD (~0)))
3462 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3469 If call foo was replaced with ba, replace
3470 or %rN, %g0, %o7 with nop. */
3471 reg
= (delay
& RS1 (~0)) >> 14;
3472 if (reg
!= ((setter
& RD (~0)) >> 25)
3473 || reg
== G0
|| reg
== O7
)
3476 if (INSN_BIG_ENDIAN
)
3477 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3479 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3484 case BFD_RELOC_SPARC_11
:
3485 if (! in_signed_range (val
, 0x7ff))
3486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3487 _("relocation overflow"));
3488 insn
|= val
& 0x7ff;
3491 case BFD_RELOC_SPARC_10
:
3492 if (! in_signed_range (val
, 0x3ff))
3493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3494 _("relocation overflow"));
3495 insn
|= val
& 0x3ff;
3498 case BFD_RELOC_SPARC_7
:
3499 if (! in_bitfield_range (val
, 0x7f))
3500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3501 _("relocation overflow"));
3505 case BFD_RELOC_SPARC_6
:
3506 if (! in_bitfield_range (val
, 0x3f))
3507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3508 _("relocation overflow"));
3512 case BFD_RELOC_SPARC_5
:
3513 if (! in_bitfield_range (val
, 0x1f))
3514 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3515 _("relocation overflow"));
3519 case BFD_RELOC_SPARC_WDISP10
:
3522 || val
<= -(offsetT
) 0x808)
3523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3524 _("relocation overflow"));
3525 /* FIXME: The +1 deserves a comment. */
3526 val
= (val
>> 2) + 1;
3527 insn
|= ((val
& 0x300) << 11)
3528 | ((val
& 0xff) << 5);
3531 case BFD_RELOC_SPARC_WDISP16
:
3534 || val
<= -(offsetT
) 0x20008)
3535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3536 _("relocation overflow"));
3537 /* FIXME: The +1 deserves a comment. */
3538 val
= (val
>> 2) + 1;
3539 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3542 case BFD_RELOC_SPARC_WDISP19
:
3545 || val
<= -(offsetT
) 0x100008)
3546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3547 _("relocation overflow"));
3548 /* FIXME: The +1 deserves a comment. */
3549 val
= (val
>> 2) + 1;
3550 insn
|= val
& 0x7ffff;
3553 case BFD_RELOC_SPARC_HH22
:
3554 val
= BSR (val
, 32);
3557 case BFD_RELOC_SPARC_LM22
:
3558 case BFD_RELOC_HI22
:
3559 if (!fixP
->fx_addsy
)
3560 insn
|= (val
>> 10) & 0x3fffff;
3562 /* FIXME: Need comment explaining why we do this. */
3566 case BFD_RELOC_SPARC22
:
3567 if (val
& ~0x003fffff)
3568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3569 _("relocation overflow"));
3570 insn
|= (val
& 0x3fffff);
3573 case BFD_RELOC_SPARC_HM10
:
3574 val
= BSR (val
, 32);
3577 case BFD_RELOC_LO10
:
3578 if (!fixP
->fx_addsy
)
3579 insn
|= val
& 0x3ff;
3581 /* FIXME: Need comment explaining why we do this. */
3585 case BFD_RELOC_SPARC_OLO10
:
3587 val
+= fixP
->tc_fix_data
;
3590 case BFD_RELOC_SPARC13
:
3591 if (! in_signed_range (val
, 0x1fff))
3592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3593 _("relocation overflow"));
3594 insn
|= val
& 0x1fff;
3597 case BFD_RELOC_SPARC_WDISP22
:
3598 val
= (val
>> 2) + 1;
3600 case BFD_RELOC_SPARC_BASE22
:
3601 insn
|= val
& 0x3fffff;
3604 case BFD_RELOC_SPARC_H34
:
3605 if (!fixP
->fx_addsy
)
3609 insn
|= tval
& 0x3fffff;
3613 case BFD_RELOC_SPARC_H44
:
3614 if (!fixP
->fx_addsy
)
3618 insn
|= tval
& 0x3fffff;
3622 case BFD_RELOC_SPARC_M44
:
3623 if (!fixP
->fx_addsy
)
3624 insn
|= (val
>> 12) & 0x3ff;
3627 case BFD_RELOC_SPARC_L44
:
3628 if (!fixP
->fx_addsy
)
3629 insn
|= val
& 0xfff;
3632 case BFD_RELOC_SPARC_HIX22
:
3633 if (!fixP
->fx_addsy
)
3635 val
^= ~(offsetT
) 0;
3636 insn
|= (val
>> 10) & 0x3fffff;
3640 case BFD_RELOC_SPARC_LOX10
:
3641 if (!fixP
->fx_addsy
)
3642 insn
|= 0x1c00 | (val
& 0x3ff);
3645 case BFD_RELOC_NONE
:
3647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3648 _("bad or unhandled relocation type: 0x%02x"),
3653 if (INSN_BIG_ENDIAN
)
3654 bfd_putb32 (insn
, (unsigned char *) buf
);
3656 bfd_putl32 (insn
, (unsigned char *) buf
);
3659 /* Are we finished with this relocation now? */
3660 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3664 /* Translate internal representation of relocation info to BFD target
3668 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3670 static arelent
*relocs
[3];
3672 bfd_reloc_code_real_type code
;
3674 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3677 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3678 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3679 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3681 switch (fixp
->fx_r_type
)
3685 case BFD_RELOC_HI22
:
3686 case BFD_RELOC_LO10
:
3687 case BFD_RELOC_32_PCREL_S2
:
3688 case BFD_RELOC_SPARC13
:
3689 case BFD_RELOC_SPARC22
:
3690 case BFD_RELOC_SPARC_PC22
:
3691 case BFD_RELOC_SPARC_PC10
:
3692 case BFD_RELOC_SPARC_BASE13
:
3693 case BFD_RELOC_SPARC_WDISP10
:
3694 case BFD_RELOC_SPARC_WDISP16
:
3695 case BFD_RELOC_SPARC_WDISP19
:
3696 case BFD_RELOC_SPARC_WDISP22
:
3698 case BFD_RELOC_SPARC_5
:
3699 case BFD_RELOC_SPARC_6
:
3700 case BFD_RELOC_SPARC_7
:
3701 case BFD_RELOC_SPARC_10
:
3702 case BFD_RELOC_SPARC_11
:
3703 case BFD_RELOC_SPARC_HH22
:
3704 case BFD_RELOC_SPARC_HM10
:
3705 case BFD_RELOC_SPARC_LM22
:
3706 case BFD_RELOC_SPARC_PC_HH22
:
3707 case BFD_RELOC_SPARC_PC_HM10
:
3708 case BFD_RELOC_SPARC_PC_LM22
:
3709 case BFD_RELOC_SPARC_H34
:
3710 case BFD_RELOC_SPARC_H44
:
3711 case BFD_RELOC_SPARC_M44
:
3712 case BFD_RELOC_SPARC_L44
:
3713 case BFD_RELOC_SPARC_HIX22
:
3714 case BFD_RELOC_SPARC_LOX10
:
3715 case BFD_RELOC_SPARC_REV32
:
3716 case BFD_RELOC_SPARC_OLO10
:
3717 case BFD_RELOC_SPARC_UA16
:
3718 case BFD_RELOC_SPARC_UA32
:
3719 case BFD_RELOC_SPARC_UA64
:
3720 case BFD_RELOC_8_PCREL
:
3721 case BFD_RELOC_16_PCREL
:
3722 case BFD_RELOC_32_PCREL
:
3723 case BFD_RELOC_64_PCREL
:
3724 case BFD_RELOC_SPARC_PLT32
:
3725 case BFD_RELOC_SPARC_PLT64
:
3726 case BFD_RELOC_VTABLE_ENTRY
:
3727 case BFD_RELOC_VTABLE_INHERIT
:
3728 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3729 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3730 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3731 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3732 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3733 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3734 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3735 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3736 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3737 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3738 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3739 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3740 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3741 case BFD_RELOC_SPARC_TLS_IE_LD
:
3742 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3743 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3744 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3745 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3746 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3747 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3748 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3749 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3750 case BFD_RELOC_SPARC_GOTDATA_OP
:
3751 code
= fixp
->fx_r_type
;
3758 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3759 /* If we are generating PIC code, we need to generate a different
3763 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3765 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3768 #define GOTT_BASE "__GOTT_BASE__"
3769 #define GOTT_INDEX "__GOTT_INDEX__"
3772 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3778 case BFD_RELOC_32_PCREL_S2
:
3779 if (generic_force_reloc (fixp
))
3780 code
= BFD_RELOC_SPARC_WPLT30
;
3782 case BFD_RELOC_HI22
:
3783 code
= BFD_RELOC_SPARC_GOT22
;
3784 if (fixp
->fx_addsy
!= NULL
)
3786 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3787 code
= BFD_RELOC_SPARC_PC22
;
3789 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3790 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3791 code
= BFD_RELOC_HI22
; /* Unchanged. */
3795 case BFD_RELOC_LO10
:
3796 code
= BFD_RELOC_SPARC_GOT10
;
3797 if (fixp
->fx_addsy
!= NULL
)
3799 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3800 code
= BFD_RELOC_SPARC_PC10
;
3802 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3803 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3804 code
= BFD_RELOC_LO10
; /* Unchanged. */
3808 case BFD_RELOC_SPARC13
:
3809 code
= BFD_RELOC_SPARC_GOT13
;
3815 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3817 /* Nothing is aligned in DWARF debugging sections. */
3818 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3821 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3822 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3823 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3827 if (code
== BFD_RELOC_SPARC_OLO10
)
3828 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3830 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3831 if (reloc
->howto
== 0)
3833 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3834 _("internal error: can't export reloc type %d (`%s')"),
3835 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3841 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3844 if (reloc
->howto
->pc_relative
== 0
3845 || code
== BFD_RELOC_SPARC_PC10
3846 || code
== BFD_RELOC_SPARC_PC22
)
3847 reloc
->addend
= fixp
->fx_addnumber
;
3848 else if (sparc_pic_code
3849 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3850 && fixp
->fx_addsy
!= NULL
3851 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3852 || S_IS_WEAK (fixp
->fx_addsy
))
3853 && S_IS_DEFINED (fixp
->fx_addsy
)
3854 && ! S_IS_COMMON (fixp
->fx_addsy
))
3855 reloc
->addend
= fixp
->fx_addnumber
;
3857 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3859 #else /* elf or coff */
3861 if (code
!= BFD_RELOC_32_PCREL_S2
3862 && code
!= BFD_RELOC_SPARC_WDISP22
3863 && code
!= BFD_RELOC_SPARC_WDISP16
3864 && code
!= BFD_RELOC_SPARC_WDISP19
3865 && code
!= BFD_RELOC_SPARC_WDISP10
3866 && code
!= BFD_RELOC_SPARC_WPLT30
3867 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3868 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3869 reloc
->addend
= fixp
->fx_addnumber
;
3870 else if (symbol_section_p (fixp
->fx_addsy
))
3871 reloc
->addend
= (section
->vma
3872 + fixp
->fx_addnumber
3873 + md_pcrel_from (fixp
));
3875 reloc
->addend
= fixp
->fx_offset
;
3878 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3879 on the same location. */
3880 if (code
== BFD_RELOC_SPARC_OLO10
)
3882 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3885 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3887 = symbol_get_bfdsym (section_symbol (absolute_section
));
3888 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3889 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3890 reloc
->addend
= fixp
->tc_fix_data
;
3896 /* We have no need to default values of symbols. */
3899 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3904 /* Round up a section size to the appropriate boundary. */
3907 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3910 /* This is not right for ELF; a.out wants it, and COFF will force
3911 the alignment anyways. */
3912 valueT align
= ((valueT
) 1
3913 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3916 /* Turn alignment value into a mask. */
3918 newsize
= (size
+ align
) & ~align
;
3925 /* Exactly what point is a PC-relative offset relative TO?
3926 On the sparc, they're relative to the address of the offset, plus
3927 its size. This gets us to the following instruction.
3928 (??? Is this right? FIXME-SOON) */
3930 md_pcrel_from (fixS
*fixP
)
3934 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3935 if (! sparc_pic_code
3936 || fixP
->fx_addsy
== NULL
3937 || symbol_section_p (fixP
->fx_addsy
))
3938 ret
+= fixP
->fx_size
;
3942 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3953 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3956 return (value
== 1) ? shift
: -1;
3959 /* Sort of like s_lcomm. */
3962 static int max_alignment
= 15;
3966 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3976 name
= input_line_pointer
;
3977 c
= get_symbol_end ();
3978 p
= input_line_pointer
;
3982 if (*input_line_pointer
!= ',')
3984 as_bad (_("Expected comma after name"));
3985 ignore_rest_of_line ();
3989 ++input_line_pointer
;
3991 if ((size
= get_absolute_expression ()) < 0)
3993 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3994 ignore_rest_of_line ();
3999 symbolP
= symbol_find_or_make (name
);
4002 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4003 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4005 as_bad (_("bad .reserve segment -- expected BSS segment"));
4009 if (input_line_pointer
[2] == '.')
4010 input_line_pointer
+= 7;
4012 input_line_pointer
+= 6;
4015 if (*input_line_pointer
== ',')
4017 ++input_line_pointer
;
4020 if (*input_line_pointer
== '\n')
4022 as_bad (_("missing alignment"));
4023 ignore_rest_of_line ();
4027 align
= (int) get_absolute_expression ();
4030 if (align
> max_alignment
)
4032 align
= max_alignment
;
4033 as_warn (_("alignment too large; assuming %d"), align
);
4039 as_bad (_("negative alignment"));
4040 ignore_rest_of_line ();
4046 temp
= mylog2 (align
);
4049 as_bad (_("alignment not a power of 2"));
4050 ignore_rest_of_line ();
4057 record_alignment (bss_section
, align
);
4062 if (!S_IS_DEFINED (symbolP
)
4064 && S_GET_OTHER (symbolP
) == 0
4065 && S_GET_DESC (symbolP
) == 0
4072 segT current_seg
= now_seg
;
4073 subsegT current_subseg
= now_subseg
;
4075 /* Switch to bss. */
4076 subseg_set (bss_section
, 1);
4080 frag_align (align
, 0, 0);
4082 /* Detach from old frag. */
4083 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4084 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4086 symbol_set_frag (symbolP
, frag_now
);
4087 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4088 (offsetT
) size
, (char *) 0);
4091 S_SET_SEGMENT (symbolP
, bss_section
);
4093 subseg_set (current_seg
, current_subseg
);
4096 S_SET_SIZE (symbolP
, size
);
4102 as_warn (_("Ignoring attempt to re-define symbol %s"),
4103 S_GET_NAME (symbolP
));
4106 demand_empty_rest_of_line ();
4110 s_common (int ignore ATTRIBUTE_UNUSED
)
4118 name
= input_line_pointer
;
4119 c
= get_symbol_end ();
4120 /* Just after name is now '\0'. */
4121 p
= input_line_pointer
;
4124 if (*input_line_pointer
!= ',')
4126 as_bad (_("Expected comma after symbol-name"));
4127 ignore_rest_of_line ();
4132 input_line_pointer
++;
4134 if ((temp
= get_absolute_expression ()) < 0)
4136 as_bad (_(".COMMon length (%lu) out of range ignored"),
4137 (unsigned long) temp
);
4138 ignore_rest_of_line ();
4143 symbolP
= symbol_find_or_make (name
);
4145 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4147 as_bad (_("Ignoring attempt to re-define symbol"));
4148 ignore_rest_of_line ();
4151 if (S_GET_VALUE (symbolP
) != 0)
4153 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4155 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4156 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4162 S_SET_VALUE (symbolP
, (valueT
) size
);
4163 S_SET_EXTERNAL (symbolP
);
4166 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4167 if (*input_line_pointer
!= ',')
4169 as_bad (_("Expected comma after common length"));
4170 ignore_rest_of_line ();
4173 input_line_pointer
++;
4175 if (*input_line_pointer
!= '"')
4177 temp
= get_absolute_expression ();
4180 if (temp
> max_alignment
)
4182 temp
= max_alignment
;
4183 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4189 as_bad (_("negative alignment"));
4190 ignore_rest_of_line ();
4195 if (symbol_get_obj (symbolP
)->local
)
4202 old_subsec
= now_subseg
;
4207 align
= mylog2 (temp
);
4211 as_bad (_("alignment not a power of 2"));
4212 ignore_rest_of_line ();
4216 record_alignment (bss_section
, align
);
4217 subseg_set (bss_section
, 0);
4219 frag_align (align
, 0, 0);
4220 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4221 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4222 symbol_set_frag (symbolP
, frag_now
);
4223 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4224 (offsetT
) size
, (char *) 0);
4226 S_SET_SEGMENT (symbolP
, bss_section
);
4227 S_CLEAR_EXTERNAL (symbolP
);
4228 S_SET_SIZE (symbolP
, size
);
4229 subseg_set (old_sec
, old_subsec
);
4232 #endif /* OBJ_ELF */
4235 S_SET_VALUE (symbolP
, (valueT
) size
);
4237 S_SET_ALIGN (symbolP
, temp
);
4238 S_SET_SIZE (symbolP
, size
);
4240 S_SET_EXTERNAL (symbolP
);
4241 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4246 input_line_pointer
++;
4247 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4248 if (*input_line_pointer
== '.')
4249 input_line_pointer
++;
4250 /* @@ Some say data, some say bss. */
4251 if (strncmp (input_line_pointer
, "bss\"", 4)
4252 && strncmp (input_line_pointer
, "data\"", 5))
4254 while (*--input_line_pointer
!= '"')
4256 input_line_pointer
--;
4257 goto bad_common_segment
;
4259 while (*input_line_pointer
++ != '"')
4261 goto allocate_common
;
4264 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4266 demand_empty_rest_of_line ();
4271 p
= input_line_pointer
;
4272 while (*p
&& *p
!= '\n')
4276 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4278 input_line_pointer
= p
;
4279 ignore_rest_of_line ();
4284 /* Handle the .empty pseudo-op. This suppresses the warnings about
4285 invalid delay slot usage. */
4288 s_empty (int ignore ATTRIBUTE_UNUSED
)
4290 /* The easy way to implement is to just forget about the last
4296 s_seg (int ignore ATTRIBUTE_UNUSED
)
4299 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4301 input_line_pointer
+= 6;
4305 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4307 input_line_pointer
+= 6;
4311 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4313 input_line_pointer
+= 7;
4317 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4319 input_line_pointer
+= 5;
4320 /* We only support 2 segments -- text and data -- for now, so
4321 things in the "bss segment" will have to go into data for now.
4322 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4323 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4326 as_bad (_("Unknown segment type"));
4327 demand_empty_rest_of_line ();
4333 subseg_set (data_section
, 1);
4334 demand_empty_rest_of_line ();
4338 s_proc (int ignore ATTRIBUTE_UNUSED
)
4340 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4342 ++input_line_pointer
;
4344 ++input_line_pointer
;
4347 /* This static variable is set by s_uacons to tell sparc_cons_align
4348 that the expression does not need to be aligned. */
4350 static int sparc_no_align_cons
= 0;
4352 /* This handles the unaligned space allocation pseudo-ops, such as
4353 .uaword. .uaword is just like .word, but the value does not need
4357 s_uacons (int bytes
)
4359 /* Tell sparc_cons_align not to align this value. */
4360 sparc_no_align_cons
= 1;
4362 sparc_no_align_cons
= 0;
4365 /* This handles the native word allocation pseudo-op .nword.
4366 For sparc_arch_size 32 it is equivalent to .word, for
4367 sparc_arch_size 64 it is equivalent to .xword. */
4370 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4372 cons (sparc_arch_size
== 32 ? 4 : 8);
4376 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4380 .register %g[2367],{#scratch|symbolname|#ignore}
4384 s_register (int ignore ATTRIBUTE_UNUSED
)
4389 const char *regname
;
4391 if (input_line_pointer
[0] != '%'
4392 || input_line_pointer
[1] != 'g'
4393 || ((input_line_pointer
[2] & ~1) != '2'
4394 && (input_line_pointer
[2] & ~1) != '6')
4395 || input_line_pointer
[3] != ',')
4396 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4397 reg
= input_line_pointer
[2] - '0';
4398 input_line_pointer
+= 4;
4400 if (*input_line_pointer
== '#')
4402 ++input_line_pointer
;
4403 regname
= input_line_pointer
;
4404 c
= get_symbol_end ();
4405 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4406 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4407 if (regname
[0] == 'i')
4414 regname
= input_line_pointer
;
4415 c
= get_symbol_end ();
4417 if (sparc_arch_size
== 64)
4421 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4422 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4423 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4424 as_bad (_("redefinition of global register"));
4428 if (regname
== NULL
)
4429 globals
[reg
] = (symbolS
*) 1;
4434 if (symbol_find (regname
))
4435 as_bad (_("Register symbol %s already defined."),
4438 globals
[reg
] = symbol_make (regname
);
4439 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4441 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4442 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4443 flags
|= BSF_GLOBAL
;
4444 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4445 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4446 S_SET_ALIGN (globals
[reg
], reg
);
4447 S_SET_SIZE (globals
[reg
], 0);
4448 /* Although we actually want undefined_section here,
4449 we have to use absolute_section, because otherwise
4450 generic as code will make it a COM section.
4451 We fix this up in sparc_adjust_symtab. */
4452 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4453 S_SET_OTHER (globals
[reg
], 0);
4454 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4455 ->internal_elf_sym
.st_info
=
4456 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4457 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4458 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4463 *input_line_pointer
= c
;
4465 demand_empty_rest_of_line ();
4468 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4469 symbols which need it. */
4472 sparc_adjust_symtab (void)
4476 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4478 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4479 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4482 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4483 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4486 S_SET_SEGMENT (sym
, undefined_section
);
4491 /* If the --enforce-aligned-data option is used, we require .word,
4492 et. al., to be aligned correctly. We do it by setting up an
4493 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4494 no unexpected alignment was introduced.
4496 The SunOS and Solaris native assemblers enforce aligned data by
4497 default. We don't want to do that, because gcc can deliberately
4498 generate misaligned data if the packed attribute is used. Instead,
4499 we permit misaligned data by default, and permit the user to set an
4500 option to check for it. */
4503 sparc_cons_align (int nbytes
)
4507 /* Only do this if we are enforcing aligned data. */
4508 if (! enforce_aligned_data
)
4511 /* Don't align if this is an unaligned pseudo-op. */
4512 if (sparc_no_align_cons
)
4515 nalign
= mylog2 (nbytes
);
4519 gas_assert (nalign
> 0);
4521 if (now_seg
== absolute_section
)
4523 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4524 as_bad (_("misaligned data"));
4528 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4529 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4531 record_alignment (now_seg
, nalign
);
4534 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4537 sparc_handle_align (fragS
*fragp
)
4542 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4544 switch (fragp
->fr_type
)
4548 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4552 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4563 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4565 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4566 if (INSN_BIG_ENDIAN
)
4567 number_to_chars_bigendian (p
, wval
, 4);
4569 number_to_chars_littleendian (p
, wval
, 4);
4575 if (INSN_BIG_ENDIAN
)
4576 number_to_chars_bigendian (p
, 0x01000000, 4);
4578 number_to_chars_littleendian (p
, 0x01000000, 4);
4580 fragp
->fr_fix
+= fix
;
4590 /* Some special processing for a Sparc ELF file. */
4593 sparc_elf_final_processing (void)
4595 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4596 sort of BFD interface for this. */
4597 if (sparc_arch_size
== 64)
4599 switch (sparc_memory_model
)
4602 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4605 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4611 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4612 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4613 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4614 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4615 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4616 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4620 sparc_cons (expressionS
*exp
, int size
)
4623 const char *sparc_cons_special_reloc
= NULL
;
4626 save
= input_line_pointer
;
4627 if (input_line_pointer
[0] == '%'
4628 && input_line_pointer
[1] == 'r'
4629 && input_line_pointer
[2] == '_')
4631 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4633 input_line_pointer
+= 7;
4634 sparc_cons_special_reloc
= "disp";
4636 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4638 if (size
!= 4 && size
!= 8)
4639 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4642 input_line_pointer
+= 6;
4643 sparc_cons_special_reloc
= "plt";
4646 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4648 if (size
!= 4 && size
!= 8)
4649 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4652 input_line_pointer
+= 13;
4653 sparc_cons_special_reloc
= "tls_dtpoff";
4656 if (sparc_cons_special_reloc
)
4663 if (*input_line_pointer
!= '8')
4665 input_line_pointer
--;
4668 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4672 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4676 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4686 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4687 sparc_cons_special_reloc
, size
* 8, size
);
4691 input_line_pointer
+= 2;
4692 if (*input_line_pointer
!= '(')
4694 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4695 sparc_cons_special_reloc
, size
* 8);
4702 input_line_pointer
= save
;
4703 sparc_cons_special_reloc
= NULL
;
4708 char *end
= ++input_line_pointer
;
4711 while (! is_end_of_line
[(c
= *end
)])
4725 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4726 sparc_cons_special_reloc
, size
* 8);
4732 if (input_line_pointer
!= end
)
4734 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4735 sparc_cons_special_reloc
, size
* 8);
4739 input_line_pointer
++;
4741 c
= *input_line_pointer
;
4742 if (! is_end_of_line
[c
] && c
!= ',')
4743 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4744 sparc_cons_special_reloc
, size
* 8);
4750 if (sparc_cons_special_reloc
== NULL
)
4752 return sparc_cons_special_reloc
;
4757 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4758 reloc for a cons. We could use the definition there, except that
4759 we want to handle little endian relocs specially. */
4762 cons_fix_new_sparc (fragS
*frag
,
4764 unsigned int nbytes
,
4766 const char *sparc_cons_special_reloc
)
4768 bfd_reloc_code_real_type r
;
4770 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4771 (nbytes
== 2 ? BFD_RELOC_16
:
4772 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4774 if (target_little_endian_data
4776 && now_seg
->flags
& SEC_ALLOC
)
4777 r
= BFD_RELOC_SPARC_REV32
;
4779 if (sparc_cons_special_reloc
)
4781 if (*sparc_cons_special_reloc
== 'd')
4784 case 1: r
= BFD_RELOC_8_PCREL
; break;
4785 case 2: r
= BFD_RELOC_16_PCREL
; break;
4786 case 4: r
= BFD_RELOC_32_PCREL
; break;
4787 case 8: r
= BFD_RELOC_64_PCREL
; break;
4790 else if (*sparc_cons_special_reloc
== 'p')
4793 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4794 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4799 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4800 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4803 else if (sparc_no_align_cons
)
4807 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4808 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4809 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4814 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4818 sparc_cfi_frame_initial_instructions (void)
4820 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4824 sparc_regname_to_dw2regnum (char *regname
)
4832 p
= strchr (q
, regname
[0]);
4835 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4837 return (p
- q
) * 8 + regname
[1] - '0';
4839 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4841 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4843 if (regname
[0] == 'f' || regname
[0] == 'r')
4845 unsigned int regnum
;
4847 regnum
= strtoul (regname
+ 1, &q
, 10);
4850 if (regnum
>= ((regname
[0] == 'f'
4851 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4854 if (regname
[0] == 'f')
4857 if (regnum
>= 64 && (regnum
& 1))
4866 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4868 sparc_no_align_cons
= 1;
4869 emit_expr_with_reloc (exp
, nbytes
, "disp");
4870 sparc_no_align_cons
= 0;