1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
41 static void init_default_arch
PARAMS ((void));
42 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
43 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
44 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
45 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
46 static int sparc_ffs
PARAMS ((unsigned int));
47 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
48 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
49 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
50 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
51 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
52 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
53 static int parse_const_expr_arg
PARAMS ((char **, int *));
54 static int get_expression
PARAMS ((char *str
));
56 /* Default architecture. */
57 /* ??? The default value should be V8, but sparclite support was added
58 by making it the default. GCC now passes -Asparclite, so maybe sometime in
59 the future we can set this to V8. */
61 #define DEFAULT_ARCH "sparclite"
63 static char *default_arch
= DEFAULT_ARCH
;
65 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 static int default_init_p
;
69 /* Current architecture. We don't bump up unless necessary. */
70 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
72 /* The maximum architecture level we can bump up to.
73 In a 32 bit environment, don't allow bumping up to v9 by default.
74 The native assembler works this way. The user is required to pass
75 an explicit argument before we'll create v9 object files. However, if
76 we don't see any v9 insns, a v8plus object file is not created. */
77 static enum sparc_opcode_arch_val max_architecture
;
79 /* Either 32 or 64, selects file format. */
80 static int sparc_arch_size
;
81 /* Initial (default) value, recorded separately in case a user option
82 changes the value before md_show_usage is called. */
83 static int default_arch_size
;
86 /* The currently selected v9 memory model. Currently only used for
88 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
91 static int architecture_requested
;
92 static int warn_on_bump
;
94 /* If warn_on_bump and the needed architecture is higher than this
95 architecture, issue a warning. */
96 static enum sparc_opcode_arch_val warn_after_architecture
;
98 /* Non-zero if as should generate error if an undeclared g[23] register
99 has been used in -64. */
100 static int no_undeclared_regs
;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax
;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data
;
111 extern int target_big_endian
;
113 static int target_little_endian_data
;
115 /* Symbols for global registers on v9. */
116 static symbolS
*globals
[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment
;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control
*op_hash
;
134 static int mylog2
PARAMS ((int));
135 static void s_data1
PARAMS ((void));
136 static void s_seg
PARAMS ((int));
137 static void s_proc
PARAMS ((int));
138 static void s_reserve
PARAMS ((int));
139 static void s_common
PARAMS ((int));
140 static void s_empty
PARAMS ((int));
141 static void s_uacons
PARAMS ((int));
142 static void s_ncons
PARAMS ((int));
144 static void s_register
PARAMS ((int));
147 const pseudo_typeS md_pseudo_table
[] =
149 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common
, 0},
151 {"empty", s_empty
, 0},
152 {"global", s_globl
, 0},
154 {"nword", s_ncons
, 0},
155 {"optim", s_ignore
, 0},
157 {"reserve", s_reserve
, 0},
159 {"skip", s_space
, 0},
162 {"uahalf", s_uacons
, 2},
163 {"uaword", s_uacons
, 4},
164 {"uaxword", s_uacons
, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars
[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS
[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode
;
211 struct nlist
*nlistp
;
215 bfd_reloc_code_real_type reloc
;
218 struct sparc_it the_insn
, set_insn
;
220 static void output_insn
221 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
223 /* Table of arguments to -A.
224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225 for this use. That table is for opcodes only. This table is for opcodes
228 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
229 v8plusa
, v9
, v9a
, v9b
, v9_64
};
231 static struct sparc_arch
{
234 enum sparc_arch_types arch_type
;
235 /* Default word size, as specified during configuration.
236 A value of zero means can't be used to specify default architecture. */
237 int default_arch_size
;
238 /* Allowable arg to -A? */
240 } sparc_arch_table
[] = {
241 { "v6", "v6", v6
, 0, 1 },
242 { "v7", "v7", v7
, 0, 1 },
243 { "v8", "v8", v8
, 32, 1 },
244 { "sparclet", "sparclet", sparclet
, 32, 1 },
245 { "sparclite", "sparclite", sparclite
, 32, 1 },
246 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
247 { "v8plus", "v9", v9
, 0, 1 },
248 { "v8plusa", "v9a", v9
, 0, 1 },
249 { "v8plusb", "v9b", v9
, 0, 1 },
250 { "v9", "v9", v9
, 0, 1 },
251 { "v9a", "v9a", v9
, 0, 1 },
252 { "v9b", "v9b", v9
, 0, 1 },
253 /* This exists to allow configure.in/Makefile.in to pass one
254 value to specify both the default machine and default word size. */
255 { "v9-64", "v9", v9
, 64, 0 },
256 { NULL
, NULL
, v8
, 0, 0 }
259 /* Variant of default_arch */
260 static enum sparc_arch_types default_arch_type
;
262 static struct sparc_arch
*
266 struct sparc_arch
*sa
;
268 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
269 if (strcmp (sa
->name
, name
) == 0)
271 if (sa
->name
== NULL
)
276 /* Initialize the default opcode arch and word size from the default
277 architecture name. */
282 struct sparc_arch
*sa
= lookup_arch (default_arch
);
285 || sa
->default_arch_size
== 0)
286 as_fatal (_("Invalid default architecture, broken assembler."));
288 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
289 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
290 as_fatal (_("Bad opcode table, broken assembler."));
291 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
293 default_arch_type
= sa
->arch_type
;
296 /* Called by TARGET_FORMAT. */
299 sparc_target_format ()
301 /* We don't get a chance to initialize anything before we're called,
302 so handle that now. */
303 if (! default_init_p
)
304 init_default_arch ();
308 return "a.out-sparc-netbsd";
311 if (target_big_endian
)
312 return "a.out-sunos-big";
313 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
314 return "a.out-sunos-big";
316 return "a.out-sparc-little";
318 return "a.out-sunos-big";
329 return "coff-sparc-lynx";
336 return "elf32-sparc-vxworks";
340 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
347 * Invocation line includes a switch not recognized by the base assembler.
348 * See if it's a processor-specific option. These are:
351 * Warn on architecture bumps. See also -A.
353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354 * Standard 32 bit architectures.
356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357 * This used to only mean 64 bits, but properly specifying it
358 * complicated gcc's ASM_SPECs, so now opcode selection is
359 * specified orthogonally to word size (except when specifying
360 * the default, but that is an internal implementation detail).
361 * -Av8plus, -Av8plusa, -Av8plusb
362 * Same as -Av9{,a,b}.
363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
366 * -xarch=v9, -xarch=v9a, -xarch=v9b
367 * Same as -Av9{,a,b} -64, for compatibility with Sun's
370 * Select the architecture and possibly the file format.
371 * Instructions or features not supported by the selected
372 * architecture cause fatal errors.
374 * The default is to start at v6, and bump the architecture up
375 * whenever an instruction is seen at a higher level. In 32 bit
376 * environments, v9 is not bumped up to, the user must pass
379 * If -bump is specified, a warning is printing when bumping to
382 * If an architecture is specified, all instructions must match
383 * that architecture. Any higher level instructions are flagged
384 * as errors. Note that in the 32 bit environment specifying
385 * -Av8plus does not automatically create a v8plus object file, a
386 * v9 insn must be seen.
388 * If both an architecture and -bump are specified, the
389 * architecture starts at the specified level, but bumps are
390 * warnings. Note that we can't set `current_architecture' to
391 * the requested level in this case: in the 32 bit environment,
392 * we still must avoid creating v8plus object files unless v9
396 * Bumping between incompatible architectures is always an
397 * error. For example, from sparclite to v9.
401 const char *md_shortopts
= "A:K:VQ:sq";
404 const char *md_shortopts
= "A:k";
406 const char *md_shortopts
= "A:";
409 struct option md_longopts
[] = {
410 #define OPTION_BUMP (OPTION_MD_BASE)
411 {"bump", no_argument
, NULL
, OPTION_BUMP
},
412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
413 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
415 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
417 #define OPTION_32 (OPTION_MD_BASE + 3)
418 {"32", no_argument
, NULL
, OPTION_32
},
419 #define OPTION_64 (OPTION_MD_BASE + 4)
420 {"64", no_argument
, NULL
, OPTION_64
},
421 #define OPTION_TSO (OPTION_MD_BASE + 5)
422 {"TSO", no_argument
, NULL
, OPTION_TSO
},
423 #define OPTION_PSO (OPTION_MD_BASE + 6)
424 {"PSO", no_argument
, NULL
, OPTION_PSO
},
425 #define OPTION_RMO (OPTION_MD_BASE + 7)
426 {"RMO", no_argument
, NULL
, OPTION_RMO
},
428 #ifdef SPARC_BIENDIAN
429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
445 {"relax", no_argument
, NULL
, OPTION_RELAX
},
446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
448 {NULL
, no_argument
, NULL
, 0}
451 size_t md_longopts_size
= sizeof (md_longopts
);
454 md_parse_option (c
, arg
)
458 /* We don't get a chance to initialize anything before we're called,
459 so handle that now. */
460 if (! default_init_p
)
461 init_default_arch ();
467 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
472 if (strncmp (arg
, "v9", 2) != 0)
473 md_parse_option (OPTION_32
, NULL
);
475 md_parse_option (OPTION_64
, NULL
);
481 struct sparc_arch
*sa
;
482 enum sparc_opcode_arch_val opcode_arch
;
484 sa
= lookup_arch (arg
);
486 || ! sa
->user_option_p
)
488 if (c
== OPTION_XARCH
)
489 as_bad (_("invalid architecture -xarch=%s"), arg
);
491 as_bad (_("invalid architecture -A%s"), arg
);
495 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
496 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
497 as_fatal (_("Bad opcode table, broken assembler."));
499 max_architecture
= opcode_arch
;
500 architecture_requested
= 1;
505 /* Ignore -sparc, used by SunOS make default .s.o rule. */
508 case OPTION_ENFORCE_ALIGNED_DATA
:
509 enforce_aligned_data
= 1;
512 #ifdef SPARC_BIENDIAN
513 case OPTION_LITTLE_ENDIAN
:
514 target_big_endian
= 0;
515 if (default_arch_type
!= sparclet
)
516 as_fatal ("This target does not support -EL");
518 case OPTION_LITTLE_ENDIAN_DATA
:
519 target_little_endian_data
= 1;
520 target_big_endian
= 0;
521 if (default_arch_type
!= sparc86x
522 && default_arch_type
!= v9
)
523 as_fatal ("This target does not support --little-endian-data");
525 case OPTION_BIG_ENDIAN
:
526 target_big_endian
= 1;
540 const char **list
, **l
;
542 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
543 list
= bfd_target_list ();
544 for (l
= list
; *l
!= NULL
; l
++)
546 if (sparc_arch_size
== 32)
548 if (CONST_STRNEQ (*l
, "elf32-sparc"))
553 if (CONST_STRNEQ (*l
, "elf64-sparc"))
558 as_fatal (_("No compiled in support for %d bit object file format"),
565 sparc_memory_model
= MM_TSO
;
569 sparc_memory_model
= MM_PSO
;
573 sparc_memory_model
= MM_RMO
;
581 /* Qy - do emit .comment
582 Qn - do not emit .comment. */
586 /* Use .stab instead of .stab.excl. */
590 /* quick -- Native assembler does fewer checks. */
594 if (strcmp (arg
, "PIC") != 0)
595 as_warn (_("Unrecognized option following -K"));
600 case OPTION_NO_UNDECLARED_REGS
:
601 no_undeclared_regs
= 1;
604 case OPTION_UNDECLARED_REGS
:
605 no_undeclared_regs
= 0;
613 case OPTION_NO_RELAX
:
625 md_show_usage (stream
)
628 const struct sparc_arch
*arch
;
631 /* We don't get a chance to initialize anything before we're called,
632 so handle that now. */
633 if (! default_init_p
)
634 init_default_arch ();
636 fprintf (stream
, _("SPARC options:\n"));
638 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
640 if (!arch
->user_option_p
)
642 if (arch
!= &sparc_arch_table
[0])
643 fprintf (stream
, " | ");
644 if (column
+ strlen (arch
->name
) > 70)
647 fputc ('\n', stream
);
649 column
+= 5 + 2 + strlen (arch
->name
);
650 fprintf (stream
, "-A%s", arch
->name
);
652 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
654 if (!arch
->user_option_p
)
656 fprintf (stream
, " | ");
657 if (column
+ strlen (arch
->name
) > 65)
660 fputc ('\n', stream
);
662 column
+= 5 + 7 + strlen (arch
->name
);
663 fprintf (stream
, "-xarch=%s", arch
->name
);
665 fprintf (stream
, _("\n\
666 specify variant of SPARC architecture\n\
667 -bump warn when assembler switches architectures\n\
669 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
670 -relax relax jumps and branches (default)\n\
671 -no-relax avoid changing any jumps and branches\n"));
673 fprintf (stream
, _("\
674 -k generate PIC\n"));
677 fprintf (stream
, _("\
678 -32 create 32 bit object file\n\
679 -64 create 64 bit object file\n"));
680 fprintf (stream
, _("\
681 [default is %d]\n"), default_arch_size
);
682 fprintf (stream
, _("\
683 -TSO use Total Store Ordering\n\
684 -PSO use Partial Store Ordering\n\
685 -RMO use Relaxed Memory Ordering\n"));
686 fprintf (stream
, _("\
687 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
688 fprintf (stream
, _("\
689 -KPIC generate PIC\n\
690 -V print assembler version number\n\
691 -undeclared-regs ignore application global register usage without\n\
692 appropriate .register directive (default)\n\
693 -no-undeclared-regs force error on application global register usage\n\
694 without appropriate .register directive\n\
699 #ifdef SPARC_BIENDIAN
700 fprintf (stream
, _("\
701 -EL generate code for a little endian machine\n\
702 -EB generate code for a big endian machine\n\
703 --little-endian-data generate code for a machine having big endian\n\
704 instructions and little endian data.\n"));
708 /* Native operand size opcode translation. */
714 } native_op_table
[] =
716 {"ldn", "ld", "ldx"},
717 {"ldna", "lda", "ldxa"},
718 {"stn", "st", "stx"},
719 {"stna", "sta", "stxa"},
720 {"slln", "sll", "sllx"},
721 {"srln", "srl", "srlx"},
722 {"sran", "sra", "srax"},
723 {"casn", "cas", "casx"},
724 {"casna", "casa", "casxa"},
725 {"clrn", "clr", "clrx"},
729 /* sparc64 privileged and hyperprivileged registers. */
731 struct priv_reg_entry
737 struct priv_reg_entry priv_reg_table
[] =
757 {"", -1}, /* End marker. */
760 struct priv_reg_entry hpriv_reg_table
[] =
768 {"", -1}, /* End marker. */
771 /* v9a specific asrs. */
773 struct priv_reg_entry v9a_asr_table
[] =
776 {"sys_tick_cmpr", 25},
784 {"clear_softint", 21},
785 {"", -1}, /* End marker. */
789 cmp_reg_entry (parg
, qarg
)
793 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
794 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
796 return strcmp (q
->name
, p
->name
);
799 /* This function is called once, at assembler startup time. It should
800 set up all the tables, etc. that the MD part of the assembler will
806 register const char *retval
= NULL
;
808 register unsigned int i
= 0;
810 /* We don't get a chance to initialize anything before md_parse_option
811 is called, and it may not be called, so handle default initialization
812 now if not already done. */
813 if (! default_init_p
)
814 init_default_arch ();
816 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
817 op_hash
= hash_new ();
819 while (i
< (unsigned int) sparc_num_opcodes
)
821 const char *name
= sparc_opcodes
[i
].name
;
822 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
825 as_bad (_("Internal error: can't hash `%s': %s\n"),
826 sparc_opcodes
[i
].name
, retval
);
831 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
833 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
834 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
839 while (i
< (unsigned int) sparc_num_opcodes
840 && !strcmp (sparc_opcodes
[i
].name
, name
));
843 for (i
= 0; native_op_table
[i
].name
; i
++)
845 const struct sparc_opcode
*insn
;
846 char *name
= ((sparc_arch_size
== 32)
847 ? native_op_table
[i
].name32
848 : native_op_table
[i
].name64
);
849 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
852 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
853 name
, native_op_table
[i
].name
);
858 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
861 as_bad (_("Internal error: can't hash `%s': %s\n"),
862 sparc_opcodes
[i
].name
, retval
);
869 as_fatal (_("Broken assembler. No assembly attempted."));
871 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
872 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
874 /* If -bump, record the architecture level at which we start issuing
875 warnings. The behaviour is different depending upon whether an
876 architecture was explicitly specified. If it wasn't, we issue warnings
877 for all upwards bumps. If it was, we don't start issuing warnings until
878 we need to bump beyond the requested architecture or when we bump between
879 conflicting architectures. */
882 && architecture_requested
)
884 /* `max_architecture' records the requested architecture.
885 Issue warnings if we go above it. */
886 warn_after_architecture
= max_architecture
;
888 /* Find the highest architecture level that doesn't conflict with
889 the requested one. */
890 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
891 max_architecture
> warn_after_architecture
;
893 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
894 warn_after_architecture
))
899 /* Called after all assembly has been done. */
904 unsigned long mach
= bfd_mach_sparc
;
906 if (sparc_arch_size
== 64)
907 switch (current_architecture
)
909 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
910 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
911 default: mach
= bfd_mach_sparc_v9
; break;
914 switch (current_architecture
)
916 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
917 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
918 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
919 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
920 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
921 be but for now it is (since that's the way it's always been
925 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
928 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
931 in_signed_range (val
, max
)
932 bfd_signed_vma val
, max
;
936 /* Sign-extend the value from the architecture word size, so that
937 0xffffffff is always considered -1 on sparc32. */
938 if (sparc_arch_size
== 32)
940 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
941 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
950 /* Return non-zero if VAL is in the range 0 to MAX. */
953 in_unsigned_range (val
, max
)
961 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
962 (e.g. -15 to +31). */
965 in_bitfield_range (val
, max
)
966 bfd_signed_vma val
, max
;
972 if (val
< ~(max
>> 1))
986 for (i
= 0; (mask
& 1) == 0; ++i
)
991 /* Implement big shift right. */
997 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
998 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
999 return val
>> amount
;
1002 /* For communication between sparc_ip and get_expression. */
1003 static char *expr_end
;
1005 /* Values for `special_case'.
1006 Instructions that require wierd handling because they're longer than
1008 #define SPECIAL_CASE_NONE 0
1009 #define SPECIAL_CASE_SET 1
1010 #define SPECIAL_CASE_SETSW 2
1011 #define SPECIAL_CASE_SETX 3
1012 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1013 #define SPECIAL_CASE_FDIV 4
1015 /* Bit masks of various insns. */
1016 #define NOP_INSN 0x01000000
1017 #define OR_INSN 0x80100000
1018 #define XOR_INSN 0x80180000
1019 #define FMOVS_INSN 0x81A00020
1020 #define SETHI_INSN 0x01000000
1021 #define SLLX_INSN 0x81281000
1022 #define SRA_INSN 0x81380000
1024 /* The last instruction to be assembled. */
1025 static const struct sparc_opcode
*last_insn
;
1026 /* The assembled opcode of `last_insn'. */
1027 static unsigned long last_opcode
;
1029 /* Handle the set and setuw synthetic instructions. */
1032 synthetize_setuw (insn
)
1033 const struct sparc_opcode
*insn
;
1035 int need_hi22_p
= 0;
1036 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1038 if (the_insn
.exp
.X_op
== O_constant
)
1040 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1042 if (sizeof (offsetT
) > 4
1043 && (the_insn
.exp
.X_add_number
< 0
1044 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1045 as_warn (_("set: number not in 0..4294967295 range"));
1049 if (sizeof (offsetT
) > 4
1050 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1051 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1052 as_warn (_("set: number not in -2147483648..4294967295 range"));
1053 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1057 /* See if operand is absolute and small; skip sethi if so. */
1058 if (the_insn
.exp
.X_op
!= O_constant
1059 || the_insn
.exp
.X_add_number
>= (1 << 12)
1060 || the_insn
.exp
.X_add_number
< -(1 << 12))
1062 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1063 | ((the_insn
.exp
.X_add_number
>> 10)
1064 & (the_insn
.exp
.X_op
== O_constant
1066 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1067 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1068 output_insn (insn
, &the_insn
);
1072 /* See if operand has no low-order bits; skip OR if so. */
1073 if (the_insn
.exp
.X_op
!= O_constant
1074 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1077 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1079 | (the_insn
.exp
.X_add_number
1080 & (the_insn
.exp
.X_op
!= O_constant
1081 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1082 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1083 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1084 output_insn (insn
, &the_insn
);
1088 /* Handle the setsw synthetic instruction. */
1091 synthetize_setsw (insn
)
1092 const struct sparc_opcode
*insn
;
1096 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1098 if (the_insn
.exp
.X_op
!= O_constant
)
1100 synthetize_setuw (insn
);
1102 /* Need to sign extend it. */
1103 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1104 the_insn
.reloc
= BFD_RELOC_NONE
;
1105 output_insn (insn
, &the_insn
);
1109 if (sizeof (offsetT
) > 4
1110 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1111 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1112 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1114 low32
= the_insn
.exp
.X_add_number
;
1118 synthetize_setuw (insn
);
1124 the_insn
.reloc
= BFD_RELOC_NONE
;
1125 /* See if operand is absolute and small; skip sethi if so. */
1126 if (low32
< -(1 << 12))
1128 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1129 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1130 output_insn (insn
, &the_insn
);
1131 low32
= 0x1c00 | (low32
& 0x3ff);
1132 opc
= RS1 (rd
) | XOR_INSN
;
1135 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1136 | (low32
& 0x1fff));
1137 output_insn (insn
, &the_insn
);
1140 /* Handle the setsw synthetic instruction. */
1143 synthetize_setx (insn
)
1144 const struct sparc_opcode
*insn
;
1146 int upper32
, lower32
;
1147 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1148 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1150 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1151 int need_xor10_p
= 0;
1153 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1154 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1155 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1158 upper_dstreg
= tmpreg
;
1159 /* The tmp reg should not be the dst reg. */
1160 if (tmpreg
== dstreg
)
1161 as_warn (_("setx: temporary register same as destination register"));
1163 /* ??? Obviously there are other optimizations we can do
1164 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1165 doing some of these. Later. If you do change things, try to
1166 change all of this to be table driven as well. */
1167 /* What to output depends on the number if it's constant.
1168 Compute that first, then output what we've decided upon. */
1169 if (the_insn
.exp
.X_op
!= O_constant
)
1171 if (sparc_arch_size
== 32)
1173 /* When arch size is 32, we want setx to be equivalent
1174 to setuw for anything but constants. */
1175 the_insn
.exp
.X_add_number
&= 0xffffffff;
1176 synthetize_setuw (insn
);
1179 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1185 /* Reset X_add_number, we've extracted it as upper32/lower32.
1186 Otherwise fixup_segment will complain about not being able to
1187 write an 8 byte number in a 4 byte field. */
1188 the_insn
.exp
.X_add_number
= 0;
1190 /* Only need hh22 if `or' insn can't handle constant. */
1191 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1194 /* Does bottom part (after sethi) have bits? */
1195 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1196 /* No hh22, but does upper32 still have bits we can't set
1198 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1201 /* If the lower half is all zero, we build the upper half directly
1202 into the dst reg. */
1204 /* Need lower half if number is zero or 0xffffffff00000000. */
1205 || (! need_hh22_p
&& ! need_hm10_p
))
1207 /* No need for sethi if `or' insn can handle constant. */
1208 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1209 /* Note that we can't use a negative constant in the `or'
1210 insn unless the upper 32 bits are all ones. */
1211 || (lower32
< 0 && upper32
!= -1)
1212 || (lower32
>= 0 && upper32
== -1))
1215 if (need_hi22_p
&& upper32
== -1)
1218 /* Does bottom part (after sethi) have bits? */
1219 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1221 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1222 /* Need `or' if we didn't set anything else. */
1223 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1227 /* Output directly to dst reg if lower 32 bits are all zero. */
1228 upper_dstreg
= dstreg
;
1231 if (!upper_dstreg
&& dstreg
)
1232 as_warn (_("setx: illegal temporary register g0"));
1236 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1237 | ((upper32
>> 10) & 0x3fffff));
1238 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1239 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1240 output_insn (insn
, &the_insn
);
1245 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1246 | (((need_xor10_p
? ~lower32
: lower32
)
1247 >> 10) & 0x3fffff));
1248 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1249 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1250 output_insn (insn
, &the_insn
);
1255 the_insn
.opcode
= (OR_INSN
1256 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1259 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1260 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1261 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1262 output_insn (insn
, &the_insn
);
1267 /* FIXME: One nice optimization to do here is to OR the low part
1268 with the highpart if hi22 isn't needed and the low part is
1270 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1273 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1274 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1275 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1276 output_insn (insn
, &the_insn
);
1279 /* If we needed to build the upper part, shift it into place. */
1280 if (need_hh22_p
|| need_hm10_p
)
1282 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1284 the_insn
.reloc
= BFD_RELOC_NONE
;
1285 output_insn (insn
, &the_insn
);
1288 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1291 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1292 | 0x1c00 | (lower32
& 0x3ff));
1293 the_insn
.reloc
= BFD_RELOC_NONE
;
1294 output_insn (insn
, &the_insn
);
1297 /* If we needed to build both upper and lower parts, OR them together. */
1298 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1300 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1302 the_insn
.reloc
= BFD_RELOC_NONE
;
1303 output_insn (insn
, &the_insn
);
1307 /* Main entry point to assemble one instruction. */
1313 const struct sparc_opcode
*insn
;
1317 special_case
= sparc_ip (str
, &insn
);
1321 /* We warn about attempts to put a floating point branch in a delay slot,
1322 unless the delay slot has been annulled. */
1323 if (last_insn
!= NULL
1324 && (insn
->flags
& F_FBR
) != 0
1325 && (last_insn
->flags
& F_DELAYED
) != 0
1326 /* ??? This test isn't completely accurate. We assume anything with
1327 F_{UNBR,CONDBR,FBR} set is annullable. */
1328 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1329 || (last_opcode
& ANNUL
) == 0))
1330 as_warn (_("FP branch in delay slot"));
1332 /* SPARC before v9 requires a nop instruction between a floating
1333 point instruction and a floating point branch. We insert one
1334 automatically, with a warning. */
1335 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1336 && last_insn
!= NULL
1337 && (insn
->flags
& F_FBR
) != 0
1338 && (last_insn
->flags
& F_FLOAT
) != 0)
1340 struct sparc_it nop_insn
;
1342 nop_insn
.opcode
= NOP_INSN
;
1343 nop_insn
.reloc
= BFD_RELOC_NONE
;
1344 output_insn (insn
, &nop_insn
);
1345 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1348 switch (special_case
)
1350 case SPECIAL_CASE_NONE
:
1352 output_insn (insn
, &the_insn
);
1355 case SPECIAL_CASE_SETSW
:
1356 synthetize_setsw (insn
);
1359 case SPECIAL_CASE_SET
:
1360 synthetize_setuw (insn
);
1363 case SPECIAL_CASE_SETX
:
1364 synthetize_setx (insn
);
1367 case SPECIAL_CASE_FDIV
:
1369 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1371 output_insn (insn
, &the_insn
);
1373 /* According to information leaked from Sun, the "fdiv" instructions
1374 on early SPARC machines would produce incorrect results sometimes.
1375 The workaround is to add an fmovs of the destination register to
1376 itself just after the instruction. This was true on machines
1377 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1378 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1379 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1380 output_insn (insn
, &the_insn
);
1385 as_fatal (_("failed special case insn sanity check"));
1389 /* Subroutine of md_assemble to do the actual parsing. */
1392 sparc_ip (str
, pinsn
)
1394 const struct sparc_opcode
**pinsn
;
1396 char *error_message
= "";
1400 const struct sparc_opcode
*insn
;
1402 unsigned long opcode
;
1403 unsigned int mask
= 0;
1407 int special_case
= SPECIAL_CASE_NONE
;
1414 while (ISLOWER (*s
) || ISDIGIT (*s
));
1431 as_bad (_("Unknown opcode: `%s'"), str
);
1433 return special_case
;
1435 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1439 as_bad (_("Unknown opcode: `%s'"), str
);
1440 return special_case
;
1450 opcode
= insn
->match
;
1451 memset (&the_insn
, '\0', sizeof (the_insn
));
1452 the_insn
.reloc
= BFD_RELOC_NONE
;
1455 /* Build the opcode, checking as we go to make sure that the
1457 for (args
= insn
->args
;; ++args
)
1465 /* Parse a series of masks. */
1472 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1475 error_message
= _(": invalid membar mask name");
1481 if (*s
== '|' || *s
== '+')
1489 if (! parse_const_expr_arg (&s
, &kmask
))
1491 error_message
= _(": invalid membar mask expression");
1494 if (kmask
< 0 || kmask
> 127)
1496 error_message
= _(": invalid membar mask number");
1501 opcode
|= MEMBAR (kmask
);
1509 if (! parse_const_expr_arg (&s
, &smask
))
1511 error_message
= _(": invalid siam mode expression");
1514 if (smask
< 0 || smask
> 7)
1516 error_message
= _(": invalid siam mode number");
1527 /* Parse a prefetch function. */
1530 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1532 error_message
= _(": invalid prefetch function name");
1538 if (! parse_const_expr_arg (&s
, &fcn
))
1540 error_message
= _(": invalid prefetch function expression");
1543 if (fcn
< 0 || fcn
> 31)
1545 error_message
= _(": invalid prefetch function number");
1555 /* Parse a sparc64 privileged register. */
1558 struct priv_reg_entry
*p
= priv_reg_table
;
1559 unsigned int len
= 9999999; /* Init to make gcc happy. */
1562 while (p
->name
[0] > s
[0])
1564 while (p
->name
[0] == s
[0])
1566 len
= strlen (p
->name
);
1567 if (strncmp (p
->name
, s
, len
) == 0)
1571 if (p
->name
[0] != s
[0])
1573 error_message
= _(": unrecognizable privileged register");
1577 opcode
|= (p
->regnum
<< 14);
1579 opcode
|= (p
->regnum
<< 25);
1585 error_message
= _(": unrecognizable privileged register");
1591 /* Parse a sparc64 hyperprivileged register. */
1594 struct priv_reg_entry
*p
= hpriv_reg_table
;
1595 unsigned int len
= 9999999; /* Init to make gcc happy. */
1598 while (p
->name
[0] > s
[0])
1600 while (p
->name
[0] == s
[0])
1602 len
= strlen (p
->name
);
1603 if (strncmp (p
->name
, s
, len
) == 0)
1607 if (p
->name
[0] != s
[0])
1609 error_message
= _(": unrecognizable hyperprivileged register");
1613 opcode
|= (p
->regnum
<< 14);
1615 opcode
|= (p
->regnum
<< 25);
1621 error_message
= _(": unrecognizable hyperprivileged register");
1627 /* Parse a v9a/v9b ancillary state register. */
1630 struct priv_reg_entry
*p
= v9a_asr_table
;
1631 unsigned int len
= 9999999; /* Init to make gcc happy. */
1634 while (p
->name
[0] > s
[0])
1636 while (p
->name
[0] == s
[0])
1638 len
= strlen (p
->name
);
1639 if (strncmp (p
->name
, s
, len
) == 0)
1643 if (p
->name
[0] != s
[0])
1645 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1648 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1650 error_message
= _(": rd on write only ancillary state register");
1654 && (insn
->architecture
1655 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1657 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1658 error_message
= _(": unrecognizable v9a ancillary state register");
1662 opcode
|= (p
->regnum
<< 14);
1664 opcode
|= (p
->regnum
<< 25);
1670 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1676 if (strncmp (s
, "%asr", 4) == 0)
1684 while (ISDIGIT (*s
))
1686 num
= num
* 10 + *s
- '0';
1690 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1692 if (num
< 16 || 31 < num
)
1694 error_message
= _(": asr number must be between 16 and 31");
1700 if (num
< 0 || 31 < num
)
1702 error_message
= _(": asr number must be between 0 and 31");
1707 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1712 error_message
= _(": expecting %asrN");
1719 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1723 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1727 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1728 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1729 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1731 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1732 /* These fields are unsigned, but for upward compatibility,
1733 allow negative values as well. */
1737 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1738 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1739 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1741 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1742 /* These fields are unsigned, but for upward compatibility,
1743 allow negative values as well. */
1747 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1752 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1757 if (*s
== 'p' && s
[1] == 'n')
1765 if (*s
== 'p' && s
[1] == 't')
1777 if (strncmp (s
, "%icc", 4) == 0)
1789 if (strncmp (s
, "%xcc", 4) == 0)
1801 if (strncmp (s
, "%fcc0", 5) == 0)
1813 if (strncmp (s
, "%fcc1", 5) == 0)
1825 if (strncmp (s
, "%fcc2", 5) == 0)
1837 if (strncmp (s
, "%fcc3", 5) == 0)
1845 if (strncmp (s
, "%pc", 3) == 0)
1853 if (strncmp (s
, "%tick", 5) == 0)
1860 case '\0': /* End of args. */
1861 if (s
[0] == ',' && s
[1] == '%')
1863 static const struct ops
1865 /* The name as it appears in assembler. */
1867 /* strlen (name), precomputed for speed */
1869 /* The reloc this pseudo-op translates to. */
1871 /* 1 if tls call. */
1876 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1877 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1878 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1879 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1880 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1881 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1882 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1883 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
1884 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
1887 const struct ops
*o
;
1891 for (o
= ops
; o
->name
; o
++)
1892 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1894 if (o
->name
== NULL
)
1897 if (s
[o
->len
+ 2] != '(')
1899 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1900 return special_case
;
1903 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1905 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1907 return special_case
;
1911 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1912 || the_insn
.exp
.X_add_number
!= 0
1913 || the_insn
.exp
.X_add_symbol
1914 != symbol_find_or_make ("__tls_get_addr")))
1916 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1918 return special_case
;
1921 the_insn
.reloc
= o
->reloc
;
1922 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1925 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1928 else if (*s1
== ')')
1937 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1938 return special_case
;
1942 (void) get_expression (s
);
1962 case '[': /* These must match exactly. */
1970 case '#': /* Must be at least one digit. */
1973 while (ISDIGIT (*s
))
1981 case 'C': /* Coprocessor state register. */
1982 if (strncmp (s
, "%csr", 4) == 0)
1989 case 'b': /* Next operand is a coprocessor register. */
1992 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
1997 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2011 opcode
|= mask
<< 14;
2019 opcode
|= mask
<< 25;
2025 case 'r': /* next operand must be a register */
2035 case 'f': /* frame pointer */
2043 case 'g': /* global register */
2052 case 'i': /* in register */
2056 mask
= c
- '0' + 24;
2061 case 'l': /* local register */
2065 mask
= (c
- '0' + 16);
2070 case 'o': /* out register */
2074 mask
= (c
- '0' + 8);
2079 case 's': /* stack pointer */
2087 case 'r': /* any register */
2088 if (!ISDIGIT ((c
= *s
++)))
2105 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2121 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2122 && no_undeclared_regs
&& ! globals
[mask
])
2123 as_bad (_("detected global register use not covered by .register pseudo-op"));
2125 /* Got the register, now figure out where
2126 it goes in the opcode. */
2130 opcode
|= mask
<< 14;
2138 opcode
|= mask
<< 25;
2142 opcode
|= (mask
<< 25) | (mask
<< 14);
2146 opcode
|= (mask
<< 25) | (mask
<< 0);
2152 case 'e': /* next operand is a floating point register */
2167 && ((format
= *s
) == 'f')
2170 for (mask
= 0; ISDIGIT (*s
); ++s
)
2172 mask
= 10 * mask
+ (*s
- '0');
2173 } /* read the number */
2181 } /* register must be even numbered */
2189 } /* register must be multiple of 4 */
2193 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2194 error_message
= _(": There are only 64 f registers; [0-63]");
2196 error_message
= _(": There are only 32 f registers; [0-31]");
2199 else if (mask
>= 32)
2201 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2203 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2206 = _(": There are only 32 single precision f registers; [0-31]");
2210 mask
-= 31; /* wrap high bit */
2214 error_message
= _(": There are only 32 f registers; [0-31]");
2222 } /* if not an 'f' register. */
2229 opcode
|= RS1 (mask
);
2235 opcode
|= RS2 (mask
);
2241 opcode
|= RD (mask
);
2250 if (strncmp (s
, "%fsr", 4) == 0)
2257 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2258 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2261 case 'l': /* 22 bit PC relative immediate */
2262 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2266 case 'L': /* 30 bit immediate */
2267 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2272 case 'n': /* 22 bit immediate */
2273 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2276 case 'i': /* 13 bit immediate */
2277 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2287 char *op_arg
= NULL
;
2288 static expressionS op_exp
;
2289 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2291 /* Check for %hi, etc. */
2294 static const struct ops
{
2295 /* The name as it appears in assembler. */
2297 /* strlen (name), precomputed for speed */
2299 /* The reloc this pseudo-op translates to. */
2301 /* Non-zero if for v9 only. */
2303 /* Non-zero if can be used in pc-relative contexts. */
2304 int pcrel_p
;/*FIXME:wip*/
2306 /* hix/lox must appear before hi/lo so %hix won't be
2307 mistaken for %hi. */
2308 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2309 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2310 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2311 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2312 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2313 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2314 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2315 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2316 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2317 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2318 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2319 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2320 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2321 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2322 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2323 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2324 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2325 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2326 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2328 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2330 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2331 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2332 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2333 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2334 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2336 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2338 { NULL
, 0, 0, 0, 0 }
2340 const struct ops
*o
;
2342 for (o
= ops
; o
->name
; o
++)
2343 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2345 if (o
->name
== NULL
)
2348 if (s
[o
->len
+ 1] != '(')
2350 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2351 return special_case
;
2355 the_insn
.reloc
= o
->reloc
;
2360 /* Note that if the get_expression() fails, we will still
2361 have created U entries in the symbol table for the
2362 'symbols' in the input string. Try not to create U
2363 symbols for registers, etc. */
2365 /* This stuff checks to see if the expression ends in
2366 +%reg. If it does, it removes the register from
2367 the expression, and re-sets 's' to point to the
2374 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2377 else if (*s1
== ')')
2386 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2387 return special_case
;
2391 (void) get_expression (s
);
2394 if (*s
== ',' || *s
== ']' || !*s
)
2396 if (*s
!= '+' && *s
!= '-')
2398 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2399 return special_case
;
2403 op_exp
= the_insn
.exp
;
2404 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2407 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2410 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2412 if (s1
[-2] == '%' && s1
[-3] == '+')
2414 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2421 if (op_arg
&& s1
== s
+ 1)
2422 the_insn
.exp
.X_op
= O_absent
;
2424 (void) get_expression (s
);
2436 (void) get_expression (s
);
2444 the_insn
.exp2
= the_insn
.exp
;
2445 the_insn
.exp
= op_exp
;
2446 if (the_insn
.exp2
.X_op
== O_absent
)
2447 the_insn
.exp2
.X_op
= O_illegal
;
2448 else if (the_insn
.exp
.X_op
== O_absent
)
2450 the_insn
.exp
= the_insn
.exp2
;
2451 the_insn
.exp2
.X_op
= O_illegal
;
2453 else if (the_insn
.exp
.X_op
== O_constant
)
2455 valueT val
= the_insn
.exp
.X_add_number
;
2456 switch (the_insn
.reloc
)
2461 case BFD_RELOC_SPARC_HH22
:
2462 val
= BSR (val
, 32);
2465 case BFD_RELOC_SPARC_LM22
:
2466 case BFD_RELOC_HI22
:
2467 val
= (val
>> 10) & 0x3fffff;
2470 case BFD_RELOC_SPARC_HM10
:
2471 val
= BSR (val
, 32);
2474 case BFD_RELOC_LO10
:
2478 case BFD_RELOC_SPARC_H44
:
2483 case BFD_RELOC_SPARC_M44
:
2488 case BFD_RELOC_SPARC_L44
:
2492 case BFD_RELOC_SPARC_HIX22
:
2494 val
= (val
>> 10) & 0x3fffff;
2497 case BFD_RELOC_SPARC_LOX10
:
2498 val
= (val
& 0x3ff) | 0x1c00;
2501 the_insn
.exp
= the_insn
.exp2
;
2502 the_insn
.exp
.X_add_number
+= val
;
2503 the_insn
.exp2
.X_op
= O_illegal
;
2504 the_insn
.reloc
= old_reloc
;
2506 else if (the_insn
.exp2
.X_op
!= O_constant
)
2508 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2509 return special_case
;
2513 if (old_reloc
!= BFD_RELOC_SPARC13
2514 || the_insn
.reloc
!= BFD_RELOC_LO10
2515 || sparc_arch_size
!= 64
2518 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2519 return special_case
;
2521 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2525 /* Check for constants that don't require emitting a reloc. */
2526 if (the_insn
.exp
.X_op
== O_constant
2527 && the_insn
.exp
.X_add_symbol
== 0
2528 && the_insn
.exp
.X_op_symbol
== 0)
2530 /* For pc-relative call instructions, we reject
2531 constants to get better code. */
2533 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2534 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2536 error_message
= _(": PC-relative operand can't be a constant");
2540 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2541 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2543 error_message
= _(": TLS operand can't be a constant");
2547 /* Constants that won't fit are checked in md_apply_fix
2548 and bfd_install_relocation.
2549 ??? It would be preferable to install the constants
2550 into the insn here and save having to create a fixS
2551 for each one. There already exists code to handle
2552 all the various cases (e.g. in md_apply_fix and
2553 bfd_install_relocation) so duplicating all that code
2554 here isn't right. */
2574 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2576 error_message
= _(": invalid ASI name");
2582 if (! parse_const_expr_arg (&s
, &asi
))
2584 error_message
= _(": invalid ASI expression");
2587 if (asi
< 0 || asi
> 255)
2589 error_message
= _(": invalid ASI number");
2593 opcode
|= ASI (asi
);
2595 } /* Alternate space. */
2598 if (strncmp (s
, "%psr", 4) == 0)
2605 case 'q': /* Floating point queue. */
2606 if (strncmp (s
, "%fq", 3) == 0)
2613 case 'Q': /* Coprocessor queue. */
2614 if (strncmp (s
, "%cq", 3) == 0)
2622 if (strcmp (str
, "set") == 0
2623 || strcmp (str
, "setuw") == 0)
2625 special_case
= SPECIAL_CASE_SET
;
2628 else if (strcmp (str
, "setsw") == 0)
2630 special_case
= SPECIAL_CASE_SETSW
;
2633 else if (strcmp (str
, "setx") == 0)
2635 special_case
= SPECIAL_CASE_SETX
;
2638 else if (strncmp (str
, "fdiv", 4) == 0)
2640 special_case
= SPECIAL_CASE_FDIV
;
2646 if (strncmp (s
, "%asi", 4) != 0)
2652 if (strncmp (s
, "%fprs", 5) != 0)
2658 if (strncmp (s
, "%ccr", 4) != 0)
2664 if (strncmp (s
, "%tbr", 4) != 0)
2670 if (strncmp (s
, "%wim", 4) != 0)
2677 char *push
= input_line_pointer
;
2680 input_line_pointer
= s
;
2682 if (e
.X_op
== O_constant
)
2684 int n
= e
.X_add_number
;
2685 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2686 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2688 opcode
|= e
.X_add_number
<< 5;
2691 as_bad (_("non-immediate OPF operand, ignored"));
2692 s
= input_line_pointer
;
2693 input_line_pointer
= push
;
2698 if (strncmp (s
, "%y", 2) != 0)
2706 /* Parse a sparclet cpreg. */
2708 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2710 error_message
= _(": invalid cpreg name");
2713 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2718 as_fatal (_("failed sanity check."));
2719 } /* switch on arg code. */
2721 /* Break out of for() loop. */
2723 } /* For each arg that we expect. */
2728 /* Args don't match. */
2729 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2730 && (insn
->name
== insn
[1].name
2731 || !strcmp (insn
->name
, insn
[1].name
)))
2739 as_bad (_("Illegal operands%s"), error_message
);
2740 return special_case
;
2745 /* We have a match. Now see if the architecture is OK. */
2746 int needed_arch_mask
= insn
->architecture
;
2751 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2752 if (! needed_arch_mask
)
2754 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2757 if (needed_arch_mask
2758 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2761 /* Can we bump up the architecture? */
2762 else if (needed_arch_mask
2763 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2765 enum sparc_opcode_arch_val needed_architecture
=
2766 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2767 & needed_arch_mask
);
2769 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2771 && needed_architecture
> warn_after_architecture
)
2773 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2774 sparc_opcode_archs
[current_architecture
].name
,
2775 sparc_opcode_archs
[needed_architecture
].name
,
2777 warn_after_architecture
= needed_architecture
;
2779 current_architecture
= needed_architecture
;
2782 /* ??? This seems to be a bit fragile. What if the next entry in
2783 the opcode table is the one we want and it is supported?
2784 It is possible to arrange the table today so that this can't
2785 happen but what about tomorrow? */
2788 int arch
, printed_one_p
= 0;
2790 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2792 /* Create a list of the architectures that support the insn. */
2793 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2795 arch
= sparc_ffs (needed_arch_mask
);
2796 while ((1 << arch
) <= needed_arch_mask
)
2798 if ((1 << arch
) & needed_arch_mask
)
2802 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2809 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2810 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2812 sparc_opcode_archs
[max_architecture
].name
);
2813 return special_case
;
2815 } /* If no match. */
2818 } /* Forever looking for a match. */
2820 the_insn
.opcode
= opcode
;
2821 return special_case
;
2824 /* Parse an argument that can be expressed as a keyword.
2825 (eg: #StoreStore or %ccfr).
2826 The result is a boolean indicating success.
2827 If successful, INPUT_POINTER is updated. */
2830 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2831 int (*lookup_fn
) PARAMS ((const char *));
2832 char **input_pointerP
;
2838 p
= *input_pointerP
;
2839 for (q
= p
+ (*p
== '#' || *p
== '%');
2840 ISALNUM (*q
) || *q
== '_';
2845 value
= (*lookup_fn
) (p
);
2850 *input_pointerP
= q
;
2854 /* Parse an argument that is a constant expression.
2855 The result is a boolean indicating success. */
2858 parse_const_expr_arg (input_pointerP
, valueP
)
2859 char **input_pointerP
;
2862 char *save
= input_line_pointer
;
2865 input_line_pointer
= *input_pointerP
;
2866 /* The next expression may be something other than a constant
2867 (say if we're not processing the right variant of the insn).
2868 Don't call expression unless we're sure it will succeed as it will
2869 signal an error (which we want to defer until later). */
2870 /* FIXME: It might be better to define md_operand and have it recognize
2871 things like %asi, etc. but continuing that route through to the end
2872 is a lot of work. */
2873 if (*input_line_pointer
== '%')
2875 input_line_pointer
= save
;
2879 *input_pointerP
= input_line_pointer
;
2880 input_line_pointer
= save
;
2881 if (exp
.X_op
!= O_constant
)
2883 *valueP
= exp
.X_add_number
;
2887 /* Subroutine of sparc_ip to parse an expression. */
2890 get_expression (str
)
2896 save_in
= input_line_pointer
;
2897 input_line_pointer
= str
;
2898 seg
= expression (&the_insn
.exp
);
2899 if (seg
!= absolute_section
2900 && seg
!= text_section
2901 && seg
!= data_section
2902 && seg
!= bss_section
2903 && seg
!= undefined_section
)
2905 the_insn
.error
= _("bad segment");
2906 expr_end
= input_line_pointer
;
2907 input_line_pointer
= save_in
;
2910 expr_end
= input_line_pointer
;
2911 input_line_pointer
= save_in
;
2915 /* Subroutine of md_assemble to output one insn. */
2918 output_insn (insn
, the_insn
)
2919 const struct sparc_opcode
*insn
;
2920 struct sparc_it
*the_insn
;
2922 char *toP
= frag_more (4);
2924 /* Put out the opcode. */
2925 if (INSN_BIG_ENDIAN
)
2926 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2928 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2930 /* Put out the symbol-dependent stuff. */
2931 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2933 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2934 (toP
- frag_now
->fr_literal
), /* Where. */
2939 /* Turn off overflow checking in fixup_segment. We'll do our
2940 own overflow checking in md_apply_fix. This is necessary because
2941 the insn size is 4 and fixup_segment will signal an overflow for
2942 large 8 byte quantities. */
2943 fixP
->fx_no_overflow
= 1;
2944 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2945 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2949 last_opcode
= the_insn
->opcode
;
2952 dwarf2_emit_insn (4);
2957 md_atof (int type
, char *litP
, int *sizeP
)
2959 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
2962 /* Write a value out to the object file, using the appropriate
2966 md_number_to_chars (buf
, val
, n
)
2971 if (target_big_endian
)
2972 number_to_chars_bigendian (buf
, val
, n
);
2973 else if (target_little_endian_data
2974 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2975 /* Output debug words, which are not in allocated sections, as big
2977 number_to_chars_bigendian (buf
, val
, n
);
2978 else if (target_little_endian_data
|| ! target_big_endian
)
2979 number_to_chars_littleendian (buf
, val
, n
);
2982 /* Apply a fixS to the frags, now that we know the value it ought to
2986 md_apply_fix (fixP
, valP
, segment
)
2989 segT segment ATTRIBUTE_UNUSED
;
2991 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2992 offsetT val
= * (offsetT
*) valP
;
2995 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2997 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3000 /* SPARC ELF relocations don't use an addend in the data field. */
3001 if (fixP
->fx_addsy
!= NULL
)
3003 switch (fixP
->fx_r_type
)
3005 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3006 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3007 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3008 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3009 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3010 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3011 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3012 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3013 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3014 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3015 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3016 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3017 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3018 case BFD_RELOC_SPARC_TLS_IE_LD
:
3019 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3020 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3021 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3022 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3023 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3024 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3025 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3026 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3027 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3028 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3029 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3039 /* This is a hack. There should be a better way to
3040 handle this. Probably in terms of howto fields, once
3041 we can look at these fixups in terms of howtos. */
3042 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3043 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3046 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3047 generate a reloc, then we just want to let the reloc addend set
3048 the value. We do not want to also stuff the addend into the
3049 object file. Including the addend in the object file works when
3050 doing a static link, because the linker will ignore the object
3051 file contents. However, the dynamic linker does not ignore the
3052 object file contents. */
3053 if (fixP
->fx_addsy
!= NULL
3054 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3057 /* When generating PIC code, we do not want an addend for a reloc
3058 against a local symbol. We adjust fx_addnumber to cancel out the
3059 value already included in val, and to also cancel out the
3060 adjustment which bfd_install_relocation will create. */
3062 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3063 && fixP
->fx_addsy
!= NULL
3064 && ! S_IS_COMMON (fixP
->fx_addsy
)
3065 && symbol_section_p (fixP
->fx_addsy
))
3066 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3068 /* When generating PIC code, we need to fiddle to get
3069 bfd_install_relocation to do the right thing for a PC relative
3070 reloc against a local symbol which we are going to keep. */
3072 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3073 && fixP
->fx_addsy
!= NULL
3074 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3075 || S_IS_WEAK (fixP
->fx_addsy
))
3076 && S_IS_DEFINED (fixP
->fx_addsy
)
3077 && ! S_IS_COMMON (fixP
->fx_addsy
))
3080 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3084 /* If this is a data relocation, just output VAL. */
3086 if (fixP
->fx_r_type
== BFD_RELOC_16
3087 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3089 md_number_to_chars (buf
, val
, 2);
3091 else if (fixP
->fx_r_type
== BFD_RELOC_32
3092 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3093 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3095 md_number_to_chars (buf
, val
, 4);
3097 else if (fixP
->fx_r_type
== BFD_RELOC_64
3098 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3100 md_number_to_chars (buf
, val
, 8);
3102 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3103 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3110 /* It's a relocation against an instruction. */
3112 if (INSN_BIG_ENDIAN
)
3113 insn
= bfd_getb32 ((unsigned char *) buf
);
3115 insn
= bfd_getl32 ((unsigned char *) buf
);
3117 switch (fixP
->fx_r_type
)
3119 case BFD_RELOC_32_PCREL_S2
:
3121 /* FIXME: This increment-by-one deserves a comment of why it's
3123 if (! sparc_pic_code
3124 || fixP
->fx_addsy
== NULL
3125 || symbol_section_p (fixP
->fx_addsy
))
3128 insn
|= val
& 0x3fffffff;
3130 /* See if we have a delay slot. */
3131 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3135 #define XCC (2 << 20)
3136 #define COND(x) (((x)&0xf)<<25)
3137 #define CONDA COND(0x8)
3138 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3139 #define INSN_BA (F2(0,2) | CONDA)
3140 #define INSN_OR F3(2, 0x2, 0)
3141 #define INSN_NOP F2(0,4)
3145 /* If the instruction is a call with either:
3147 arithmetic instruction with rd == %o7
3148 where rs1 != %o7 and rs2 if it is register != %o7
3149 then we can optimize if the call destination is near
3150 by changing the call into a branch always. */
3151 if (INSN_BIG_ENDIAN
)
3152 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3154 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3155 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3157 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3158 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3159 || ((delay
& RD (~0)) != RD (O7
))))
3161 if ((delay
& RS1 (~0)) == RS1 (O7
)
3162 || ((delay
& F3I (~0)) == 0
3163 && (delay
& RS2 (~0)) == RS2 (O7
)))
3165 /* Ensure the branch will fit into simm22. */
3166 if ((val
& 0x3fe00000)
3167 && (val
& 0x3fe00000) != 0x3fe00000)
3169 /* Check if the arch is v9 and branch will fit
3171 if (((val
& 0x3c0000) == 0
3172 || (val
& 0x3c0000) == 0x3c0000)
3173 && (sparc_arch_size
== 64
3174 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3176 insn
= INSN_BPA
| (val
& 0x7ffff);
3179 insn
= INSN_BA
| (val
& 0x3fffff);
3180 if (fixP
->fx_where
>= 4
3181 && ((delay
& (0xffffffff ^ RS1 (~0)))
3182 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3187 if (INSN_BIG_ENDIAN
)
3188 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3190 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3191 if ((setter
& (0xffffffff ^ RD (~0)))
3192 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3199 If call foo was replaced with ba, replace
3200 or %rN, %g0, %o7 with nop. */
3201 reg
= (delay
& RS1 (~0)) >> 14;
3202 if (reg
!= ((setter
& RD (~0)) >> 25)
3203 || reg
== G0
|| reg
== O7
)
3206 if (INSN_BIG_ENDIAN
)
3207 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3209 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3214 case BFD_RELOC_SPARC_11
:
3215 if (! in_signed_range (val
, 0x7ff))
3216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3217 _("relocation overflow"));
3218 insn
|= val
& 0x7ff;
3221 case BFD_RELOC_SPARC_10
:
3222 if (! in_signed_range (val
, 0x3ff))
3223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3224 _("relocation overflow"));
3225 insn
|= val
& 0x3ff;
3228 case BFD_RELOC_SPARC_7
:
3229 if (! in_bitfield_range (val
, 0x7f))
3230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3231 _("relocation overflow"));
3235 case BFD_RELOC_SPARC_6
:
3236 if (! in_bitfield_range (val
, 0x3f))
3237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3238 _("relocation overflow"));
3242 case BFD_RELOC_SPARC_5
:
3243 if (! in_bitfield_range (val
, 0x1f))
3244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3245 _("relocation overflow"));
3249 case BFD_RELOC_SPARC_WDISP16
:
3252 || val
<= -(offsetT
) 0x20008)
3253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3254 _("relocation overflow"));
3255 /* FIXME: The +1 deserves a comment. */
3256 val
= (val
>> 2) + 1;
3257 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3260 case BFD_RELOC_SPARC_WDISP19
:
3263 || val
<= -(offsetT
) 0x100008)
3264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3265 _("relocation overflow"));
3266 /* FIXME: The +1 deserves a comment. */
3267 val
= (val
>> 2) + 1;
3268 insn
|= val
& 0x7ffff;
3271 case BFD_RELOC_SPARC_HH22
:
3272 val
= BSR (val
, 32);
3275 case BFD_RELOC_SPARC_LM22
:
3276 case BFD_RELOC_HI22
:
3277 if (!fixP
->fx_addsy
)
3278 insn
|= (val
>> 10) & 0x3fffff;
3280 /* FIXME: Need comment explaining why we do this. */
3284 case BFD_RELOC_SPARC22
:
3285 if (val
& ~0x003fffff)
3286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3287 _("relocation overflow"));
3288 insn
|= (val
& 0x3fffff);
3291 case BFD_RELOC_SPARC_HM10
:
3292 val
= BSR (val
, 32);
3295 case BFD_RELOC_LO10
:
3296 if (!fixP
->fx_addsy
)
3297 insn
|= val
& 0x3ff;
3299 /* FIXME: Need comment explaining why we do this. */
3303 case BFD_RELOC_SPARC_OLO10
:
3305 val
+= fixP
->tc_fix_data
;
3308 case BFD_RELOC_SPARC13
:
3309 if (! in_signed_range (val
, 0x1fff))
3310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3311 _("relocation overflow"));
3312 insn
|= val
& 0x1fff;
3315 case BFD_RELOC_SPARC_WDISP22
:
3316 val
= (val
>> 2) + 1;
3318 case BFD_RELOC_SPARC_BASE22
:
3319 insn
|= val
& 0x3fffff;
3322 case BFD_RELOC_SPARC_H44
:
3323 if (!fixP
->fx_addsy
)
3327 insn
|= tval
& 0x3fffff;
3331 case BFD_RELOC_SPARC_M44
:
3332 if (!fixP
->fx_addsy
)
3333 insn
|= (val
>> 12) & 0x3ff;
3336 case BFD_RELOC_SPARC_L44
:
3337 if (!fixP
->fx_addsy
)
3338 insn
|= val
& 0xfff;
3341 case BFD_RELOC_SPARC_HIX22
:
3342 if (!fixP
->fx_addsy
)
3344 val
^= ~(offsetT
) 0;
3345 insn
|= (val
>> 10) & 0x3fffff;
3349 case BFD_RELOC_SPARC_LOX10
:
3350 if (!fixP
->fx_addsy
)
3351 insn
|= 0x1c00 | (val
& 0x3ff);
3354 case BFD_RELOC_NONE
:
3356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3357 _("bad or unhandled relocation type: 0x%02x"),
3362 if (INSN_BIG_ENDIAN
)
3363 bfd_putb32 (insn
, (unsigned char *) buf
);
3365 bfd_putl32 (insn
, (unsigned char *) buf
);
3368 /* Are we finished with this relocation now? */
3369 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3373 /* Translate internal representation of relocation info to BFD target
3377 tc_gen_reloc (section
, fixp
)
3381 static arelent
*relocs
[3];
3383 bfd_reloc_code_real_type code
;
3385 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3388 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3389 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3390 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3392 switch (fixp
->fx_r_type
)
3396 case BFD_RELOC_HI22
:
3397 case BFD_RELOC_LO10
:
3398 case BFD_RELOC_32_PCREL_S2
:
3399 case BFD_RELOC_SPARC13
:
3400 case BFD_RELOC_SPARC22
:
3401 case BFD_RELOC_SPARC_BASE13
:
3402 case BFD_RELOC_SPARC_WDISP16
:
3403 case BFD_RELOC_SPARC_WDISP19
:
3404 case BFD_RELOC_SPARC_WDISP22
:
3406 case BFD_RELOC_SPARC_5
:
3407 case BFD_RELOC_SPARC_6
:
3408 case BFD_RELOC_SPARC_7
:
3409 case BFD_RELOC_SPARC_10
:
3410 case BFD_RELOC_SPARC_11
:
3411 case BFD_RELOC_SPARC_HH22
:
3412 case BFD_RELOC_SPARC_HM10
:
3413 case BFD_RELOC_SPARC_LM22
:
3414 case BFD_RELOC_SPARC_PC_HH22
:
3415 case BFD_RELOC_SPARC_PC_HM10
:
3416 case BFD_RELOC_SPARC_PC_LM22
:
3417 case BFD_RELOC_SPARC_H44
:
3418 case BFD_RELOC_SPARC_M44
:
3419 case BFD_RELOC_SPARC_L44
:
3420 case BFD_RELOC_SPARC_HIX22
:
3421 case BFD_RELOC_SPARC_LOX10
:
3422 case BFD_RELOC_SPARC_REV32
:
3423 case BFD_RELOC_SPARC_OLO10
:
3424 case BFD_RELOC_SPARC_UA16
:
3425 case BFD_RELOC_SPARC_UA32
:
3426 case BFD_RELOC_SPARC_UA64
:
3427 case BFD_RELOC_8_PCREL
:
3428 case BFD_RELOC_16_PCREL
:
3429 case BFD_RELOC_32_PCREL
:
3430 case BFD_RELOC_64_PCREL
:
3431 case BFD_RELOC_SPARC_PLT32
:
3432 case BFD_RELOC_SPARC_PLT64
:
3433 case BFD_RELOC_VTABLE_ENTRY
:
3434 case BFD_RELOC_VTABLE_INHERIT
:
3435 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3436 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3437 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3438 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3439 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3440 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3441 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3442 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3443 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3444 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3445 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3446 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3447 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3448 case BFD_RELOC_SPARC_TLS_IE_LD
:
3449 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3450 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3451 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3452 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3453 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3454 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3455 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3456 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3457 case BFD_RELOC_SPARC_GOTDATA_OP
:
3458 code
= fixp
->fx_r_type
;
3465 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3466 /* If we are generating PIC code, we need to generate a different
3470 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3472 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3475 #define GOTT_BASE "__GOTT_BASE__"
3476 #define GOTT_INDEX "__GOTT_INDEX__"
3479 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3485 case BFD_RELOC_32_PCREL_S2
:
3486 if (generic_force_reloc (fixp
))
3487 code
= BFD_RELOC_SPARC_WPLT30
;
3489 case BFD_RELOC_HI22
:
3490 code
= BFD_RELOC_SPARC_GOT22
;
3491 if (fixp
->fx_addsy
!= NULL
)
3493 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3494 code
= BFD_RELOC_SPARC_PC22
;
3496 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3497 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3498 code
= BFD_RELOC_HI22
; /* Unchanged. */
3502 case BFD_RELOC_LO10
:
3503 code
= BFD_RELOC_SPARC_GOT10
;
3504 if (fixp
->fx_addsy
!= NULL
)
3506 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3507 code
= BFD_RELOC_SPARC_PC10
;
3509 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3510 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3511 code
= BFD_RELOC_LO10
; /* Unchanged. */
3515 case BFD_RELOC_SPARC13
:
3516 code
= BFD_RELOC_SPARC_GOT13
;
3522 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3524 /* Nothing is aligned in DWARF debugging sections. */
3525 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3528 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3529 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3530 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3534 if (code
== BFD_RELOC_SPARC_OLO10
)
3535 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3537 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3538 if (reloc
->howto
== 0)
3540 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3541 _("internal error: can't export reloc type %d (`%s')"),
3542 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3548 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3551 if (reloc
->howto
->pc_relative
== 0
3552 || code
== BFD_RELOC_SPARC_PC10
3553 || code
== BFD_RELOC_SPARC_PC22
)
3554 reloc
->addend
= fixp
->fx_addnumber
;
3555 else if (sparc_pic_code
3556 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3557 && fixp
->fx_addsy
!= NULL
3558 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3559 || S_IS_WEAK (fixp
->fx_addsy
))
3560 && S_IS_DEFINED (fixp
->fx_addsy
)
3561 && ! S_IS_COMMON (fixp
->fx_addsy
))
3562 reloc
->addend
= fixp
->fx_addnumber
;
3564 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3566 #else /* elf or coff */
3568 if (code
!= BFD_RELOC_32_PCREL_S2
3569 && code
!= BFD_RELOC_SPARC_WDISP22
3570 && code
!= BFD_RELOC_SPARC_WDISP16
3571 && code
!= BFD_RELOC_SPARC_WDISP19
3572 && code
!= BFD_RELOC_SPARC_WPLT30
3573 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3574 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3575 reloc
->addend
= fixp
->fx_addnumber
;
3576 else if (symbol_section_p (fixp
->fx_addsy
))
3577 reloc
->addend
= (section
->vma
3578 + fixp
->fx_addnumber
3579 + md_pcrel_from (fixp
));
3581 reloc
->addend
= fixp
->fx_offset
;
3584 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3585 on the same location. */
3586 if (code
== BFD_RELOC_SPARC_OLO10
)
3588 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3591 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3593 = symbol_get_bfdsym (section_symbol (absolute_section
));
3594 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3595 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3596 reloc
->addend
= fixp
->tc_fix_data
;
3602 /* We have no need to default values of symbols. */
3605 md_undefined_symbol (name
)
3606 char *name ATTRIBUTE_UNUSED
;
3611 /* Round up a section size to the appropriate boundary. */
3614 md_section_align (segment
, size
)
3615 segT segment ATTRIBUTE_UNUSED
;
3619 /* This is not right for ELF; a.out wants it, and COFF will force
3620 the alignment anyways. */
3621 valueT align
= ((valueT
) 1
3622 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3625 /* Turn alignment value into a mask. */
3627 newsize
= (size
+ align
) & ~align
;
3634 /* Exactly what point is a PC-relative offset relative TO?
3635 On the sparc, they're relative to the address of the offset, plus
3636 its size. This gets us to the following instruction.
3637 (??? Is this right? FIXME-SOON) */
3639 md_pcrel_from (fixP
)
3644 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3645 if (! sparc_pic_code
3646 || fixP
->fx_addsy
== NULL
3647 || symbol_section_p (fixP
->fx_addsy
))
3648 ret
+= fixP
->fx_size
;
3652 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3664 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3667 return (value
== 1) ? shift
: -1;
3670 /* Sort of like s_lcomm. */
3673 static int max_alignment
= 15;
3678 int ignore ATTRIBUTE_UNUSED
;
3688 name
= input_line_pointer
;
3689 c
= get_symbol_end ();
3690 p
= input_line_pointer
;
3694 if (*input_line_pointer
!= ',')
3696 as_bad (_("Expected comma after name"));
3697 ignore_rest_of_line ();
3701 ++input_line_pointer
;
3703 if ((size
= get_absolute_expression ()) < 0)
3705 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3706 ignore_rest_of_line ();
3711 symbolP
= symbol_find_or_make (name
);
3714 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3715 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3717 as_bad (_("bad .reserve segment -- expected BSS segment"));
3721 if (input_line_pointer
[2] == '.')
3722 input_line_pointer
+= 7;
3724 input_line_pointer
+= 6;
3727 if (*input_line_pointer
== ',')
3729 ++input_line_pointer
;
3732 if (*input_line_pointer
== '\n')
3734 as_bad (_("missing alignment"));
3735 ignore_rest_of_line ();
3739 align
= (int) get_absolute_expression ();
3742 if (align
> max_alignment
)
3744 align
= max_alignment
;
3745 as_warn (_("alignment too large; assuming %d"), align
);
3751 as_bad (_("negative alignment"));
3752 ignore_rest_of_line ();
3758 temp
= mylog2 (align
);
3761 as_bad (_("alignment not a power of 2"));
3762 ignore_rest_of_line ();
3769 record_alignment (bss_section
, align
);
3774 if (!S_IS_DEFINED (symbolP
)
3776 && S_GET_OTHER (symbolP
) == 0
3777 && S_GET_DESC (symbolP
) == 0
3784 segT current_seg
= now_seg
;
3785 subsegT current_subseg
= now_subseg
;
3787 /* Switch to bss. */
3788 subseg_set (bss_section
, 1);
3792 frag_align (align
, 0, 0);
3794 /* Detach from old frag. */
3795 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3796 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3798 symbol_set_frag (symbolP
, frag_now
);
3799 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3800 (offsetT
) size
, (char *) 0);
3803 S_SET_SEGMENT (symbolP
, bss_section
);
3805 subseg_set (current_seg
, current_subseg
);
3808 S_SET_SIZE (symbolP
, size
);
3814 as_warn ("Ignoring attempt to re-define symbol %s",
3815 S_GET_NAME (symbolP
));
3816 } /* if not redefining. */
3818 demand_empty_rest_of_line ();
3823 int ignore ATTRIBUTE_UNUSED
;
3831 name
= input_line_pointer
;
3832 c
= get_symbol_end ();
3833 /* Just after name is now '\0'. */
3834 p
= input_line_pointer
;
3837 if (*input_line_pointer
!= ',')
3839 as_bad (_("Expected comma after symbol-name"));
3840 ignore_rest_of_line ();
3845 input_line_pointer
++;
3847 if ((temp
= get_absolute_expression ()) < 0)
3849 as_bad (_(".COMMon length (%lu) out of range ignored"),
3850 (unsigned long) temp
);
3851 ignore_rest_of_line ();
3856 symbolP
= symbol_find_or_make (name
);
3858 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3860 as_bad (_("Ignoring attempt to re-define symbol"));
3861 ignore_rest_of_line ();
3864 if (S_GET_VALUE (symbolP
) != 0)
3866 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3868 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3869 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
3875 S_SET_VALUE (symbolP
, (valueT
) size
);
3876 S_SET_EXTERNAL (symbolP
);
3879 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3880 if (*input_line_pointer
!= ',')
3882 as_bad (_("Expected comma after common length"));
3883 ignore_rest_of_line ();
3886 input_line_pointer
++;
3888 if (*input_line_pointer
!= '"')
3890 temp
= get_absolute_expression ();
3893 if (temp
> max_alignment
)
3895 temp
= max_alignment
;
3896 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
3902 as_bad (_("negative alignment"));
3903 ignore_rest_of_line ();
3908 if (symbol_get_obj (symbolP
)->local
)
3916 old_subsec
= now_subseg
;
3921 align
= mylog2 (temp
);
3925 as_bad (_("alignment not a power of 2"));
3926 ignore_rest_of_line ();
3930 record_alignment (bss_section
, align
);
3931 subseg_set (bss_section
, 0);
3933 frag_align (align
, 0, 0);
3934 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3935 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3936 symbol_set_frag (symbolP
, frag_now
);
3937 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3938 (offsetT
) size
, (char *) 0);
3940 S_SET_SEGMENT (symbolP
, bss_section
);
3941 S_CLEAR_EXTERNAL (symbolP
);
3942 S_SET_SIZE (symbolP
, size
);
3943 subseg_set (old_sec
, old_subsec
);
3946 #endif /* OBJ_ELF */
3949 S_SET_VALUE (symbolP
, (valueT
) size
);
3951 S_SET_ALIGN (symbolP
, temp
);
3952 S_SET_SIZE (symbolP
, size
);
3954 S_SET_EXTERNAL (symbolP
);
3955 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3960 input_line_pointer
++;
3961 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3962 if (*input_line_pointer
== '.')
3963 input_line_pointer
++;
3964 /* @@ Some say data, some say bss. */
3965 if (strncmp (input_line_pointer
, "bss\"", 4)
3966 && strncmp (input_line_pointer
, "data\"", 5))
3968 while (*--input_line_pointer
!= '"')
3970 input_line_pointer
--;
3971 goto bad_common_segment
;
3973 while (*input_line_pointer
++ != '"')
3975 goto allocate_common
;
3978 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3980 demand_empty_rest_of_line ();
3985 p
= input_line_pointer
;
3986 while (*p
&& *p
!= '\n')
3990 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3992 input_line_pointer
= p
;
3993 ignore_rest_of_line ();
3998 /* Handle the .empty pseudo-op. This suppresses the warnings about
3999 invalid delay slot usage. */
4003 int ignore ATTRIBUTE_UNUSED
;
4005 /* The easy way to implement is to just forget about the last
4012 int ignore ATTRIBUTE_UNUSED
;
4015 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4017 input_line_pointer
+= 6;
4021 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4023 input_line_pointer
+= 6;
4027 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4029 input_line_pointer
+= 7;
4033 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4035 input_line_pointer
+= 5;
4036 /* We only support 2 segments -- text and data -- for now, so
4037 things in the "bss segment" will have to go into data for now.
4038 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4039 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4042 as_bad (_("Unknown segment type"));
4043 demand_empty_rest_of_line ();
4049 subseg_set (data_section
, 1);
4050 demand_empty_rest_of_line ();
4055 int ignore ATTRIBUTE_UNUSED
;
4057 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4059 ++input_line_pointer
;
4061 ++input_line_pointer
;
4064 /* This static variable is set by s_uacons to tell sparc_cons_align
4065 that the expression does not need to be aligned. */
4067 static int sparc_no_align_cons
= 0;
4069 /* This static variable is set by sparc_cons to emit requested types
4070 of relocations in cons_fix_new_sparc. */
4072 static const char *sparc_cons_special_reloc
;
4074 /* This handles the unaligned space allocation pseudo-ops, such as
4075 .uaword. .uaword is just like .word, but the value does not need
4082 /* Tell sparc_cons_align not to align this value. */
4083 sparc_no_align_cons
= 1;
4085 sparc_no_align_cons
= 0;
4088 /* This handles the native word allocation pseudo-op .nword.
4089 For sparc_arch_size 32 it is equivalent to .word, for
4090 sparc_arch_size 64 it is equivalent to .xword. */
4094 int bytes ATTRIBUTE_UNUSED
;
4096 cons (sparc_arch_size
== 32 ? 4 : 8);
4100 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4104 .register %g[2367],{#scratch|symbolname|#ignore}
4109 int ignore ATTRIBUTE_UNUSED
;
4114 const char *regname
;
4116 if (input_line_pointer
[0] != '%'
4117 || input_line_pointer
[1] != 'g'
4118 || ((input_line_pointer
[2] & ~1) != '2'
4119 && (input_line_pointer
[2] & ~1) != '6')
4120 || input_line_pointer
[3] != ',')
4121 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4122 reg
= input_line_pointer
[2] - '0';
4123 input_line_pointer
+= 4;
4125 if (*input_line_pointer
== '#')
4127 ++input_line_pointer
;
4128 regname
= input_line_pointer
;
4129 c
= get_symbol_end ();
4130 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4131 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4132 if (regname
[0] == 'i')
4139 regname
= input_line_pointer
;
4140 c
= get_symbol_end ();
4142 if (sparc_arch_size
== 64)
4146 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4147 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4148 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4149 as_bad (_("redefinition of global register"));
4153 if (regname
== NULL
)
4154 globals
[reg
] = (symbolS
*) 1;
4159 if (symbol_find (regname
))
4160 as_bad (_("Register symbol %s already defined."),
4163 globals
[reg
] = symbol_make (regname
);
4164 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4166 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4167 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4168 flags
|= BSF_GLOBAL
;
4169 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4170 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4171 S_SET_ALIGN (globals
[reg
], reg
);
4172 S_SET_SIZE (globals
[reg
], 0);
4173 /* Although we actually want undefined_section here,
4174 we have to use absolute_section, because otherwise
4175 generic as code will make it a COM section.
4176 We fix this up in sparc_adjust_symtab. */
4177 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4178 S_SET_OTHER (globals
[reg
], 0);
4179 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4180 ->internal_elf_sym
.st_info
=
4181 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4182 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4183 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4188 *input_line_pointer
= c
;
4190 demand_empty_rest_of_line ();
4193 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4194 symbols which need it. */
4197 sparc_adjust_symtab ()
4201 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4203 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4204 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4207 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4208 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4211 S_SET_SEGMENT (sym
, undefined_section
);
4216 /* If the --enforce-aligned-data option is used, we require .word,
4217 et. al., to be aligned correctly. We do it by setting up an
4218 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4219 no unexpected alignment was introduced.
4221 The SunOS and Solaris native assemblers enforce aligned data by
4222 default. We don't want to do that, because gcc can deliberately
4223 generate misaligned data if the packed attribute is used. Instead,
4224 we permit misaligned data by default, and permit the user to set an
4225 option to check for it. */
4228 sparc_cons_align (nbytes
)
4234 /* Only do this if we are enforcing aligned data. */
4235 if (! enforce_aligned_data
)
4238 /* Don't align if this is an unaligned pseudo-op. */
4239 if (sparc_no_align_cons
)
4242 nalign
= mylog2 (nbytes
);
4246 assert (nalign
> 0);
4248 if (now_seg
== absolute_section
)
4250 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4251 as_bad (_("misaligned data"));
4255 p
= frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4256 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4258 record_alignment (now_seg
, nalign
);
4261 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4264 sparc_handle_align (fragp
)
4270 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4272 switch (fragp
->fr_type
)
4276 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4280 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4291 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4293 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4294 if (INSN_BIG_ENDIAN
)
4295 number_to_chars_bigendian (p
, wval
, 4);
4297 number_to_chars_littleendian (p
, wval
, 4);
4303 if (INSN_BIG_ENDIAN
)
4304 number_to_chars_bigendian (p
, 0x01000000, 4);
4306 number_to_chars_littleendian (p
, 0x01000000, 4);
4308 fragp
->fr_fix
+= fix
;
4318 /* Some special processing for a Sparc ELF file. */
4321 sparc_elf_final_processing ()
4323 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4324 sort of BFD interface for this. */
4325 if (sparc_arch_size
== 64)
4327 switch (sparc_memory_model
)
4330 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4333 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4339 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4340 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4341 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4342 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4343 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4344 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4348 sparc_cons (exp
, size
)
4355 sparc_cons_special_reloc
= NULL
;
4356 save
= input_line_pointer
;
4357 if (input_line_pointer
[0] == '%'
4358 && input_line_pointer
[1] == 'r'
4359 && input_line_pointer
[2] == '_')
4361 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4363 input_line_pointer
+= 7;
4364 sparc_cons_special_reloc
= "disp";
4366 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4368 if (size
!= 4 && size
!= 8)
4369 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4372 input_line_pointer
+= 6;
4373 sparc_cons_special_reloc
= "plt";
4376 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4378 if (size
!= 4 && size
!= 8)
4379 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4382 input_line_pointer
+= 13;
4383 sparc_cons_special_reloc
= "tls_dtpoff";
4386 if (sparc_cons_special_reloc
)
4393 if (*input_line_pointer
!= '8')
4395 input_line_pointer
--;
4398 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4402 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4406 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4416 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4417 sparc_cons_special_reloc
, size
* 8, size
);
4421 input_line_pointer
+= 2;
4422 if (*input_line_pointer
!= '(')
4424 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4425 sparc_cons_special_reloc
, size
* 8);
4432 input_line_pointer
= save
;
4433 sparc_cons_special_reloc
= NULL
;
4438 char *end
= ++input_line_pointer
;
4441 while (! is_end_of_line
[(c
= *end
)])
4455 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4456 sparc_cons_special_reloc
, size
* 8);
4462 if (input_line_pointer
!= end
)
4464 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4465 sparc_cons_special_reloc
, size
* 8);
4469 input_line_pointer
++;
4471 c
= *input_line_pointer
;
4472 if (! is_end_of_line
[c
] && c
!= ',')
4473 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4474 sparc_cons_special_reloc
, size
* 8);
4480 if (sparc_cons_special_reloc
== NULL
)
4486 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4487 reloc for a cons. We could use the definition there, except that
4488 we want to handle little endian relocs specially. */
4491 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4494 unsigned int nbytes
;
4497 bfd_reloc_code_real_type r
;
4499 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4500 (nbytes
== 2 ? BFD_RELOC_16
:
4501 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4503 if (target_little_endian_data
4505 && now_seg
->flags
& SEC_ALLOC
)
4506 r
= BFD_RELOC_SPARC_REV32
;
4508 if (sparc_cons_special_reloc
)
4510 if (*sparc_cons_special_reloc
== 'd')
4513 case 1: r
= BFD_RELOC_8_PCREL
; break;
4514 case 2: r
= BFD_RELOC_16_PCREL
; break;
4515 case 4: r
= BFD_RELOC_32_PCREL
; break;
4516 case 8: r
= BFD_RELOC_64_PCREL
; break;
4519 else if (*sparc_cons_special_reloc
== 'p')
4522 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4523 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4528 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4529 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4532 else if (sparc_no_align_cons
)
4536 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4537 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4538 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4543 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4544 sparc_cons_special_reloc
= NULL
;
4548 sparc_cfi_frame_initial_instructions ()
4550 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4554 sparc_regname_to_dw2regnum (char *regname
)
4562 p
= strchr (q
, regname
[0]);
4565 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4567 return (p
- q
) * 8 + regname
[1] - '0';
4569 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4571 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4573 if (regname
[0] == 'f' || regname
[0] == 'r')
4575 unsigned int regnum
;
4577 regnum
= strtoul (regname
+ 1, &q
, 10);
4580 if (regnum
>= ((regname
[0] == 'f'
4581 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4584 if (regname
[0] == 'f')
4587 if (regnum
>= 64 && (regnum
& 1))
4596 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4598 sparc_cons_special_reloc
= "disp";
4599 sparc_no_align_cons
= 1;
4600 emit_expr (exp
, nbytes
);
4601 sparc_no_align_cons
= 0;
4602 sparc_cons_special_reloc
= NULL
;