1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
33 static void init_default_arch
PARAMS ((void));
34 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
35 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
36 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
37 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
38 static int sparc_ffs
PARAMS ((unsigned int));
39 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
40 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
41 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
42 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
43 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
44 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
45 static int parse_const_expr_arg
PARAMS ((char **, int *));
46 static int get_expression
PARAMS ((char *str
));
48 /* Default architecture. */
49 /* ??? The default value should be V8, but sparclite support was added
50 by making it the default. GCC now passes -Asparclite, so maybe sometime in
51 the future we can set this to V8. */
53 #define DEFAULT_ARCH "sparclite"
55 static char *default_arch
= DEFAULT_ARCH
;
57 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 static int default_init_p
;
61 /* Current architecture. We don't bump up unless necessary. */
62 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
64 /* The maximum architecture level we can bump up to.
65 In a 32 bit environment, don't allow bumping up to v9 by default.
66 The native assembler works this way. The user is required to pass
67 an explicit argument before we'll create v9 object files. However, if
68 we don't see any v9 insns, a v8plus object file is not created. */
69 static enum sparc_opcode_arch_val max_architecture
;
71 /* Either 32 or 64, selects file format. */
72 static int sparc_arch_size
;
73 /* Initial (default) value, recorded separately in case a user option
74 changes the value before md_show_usage is called. */
75 static int default_arch_size
;
78 /* The currently selected v9 memory model. Currently only used for
80 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if we are generating PIC code. */
93 /* Non-zero if we should give an error when misaligned data is seen. */
94 static int enforce_aligned_data
;
96 extern int target_big_endian
;
98 static int target_little_endian_data
;
100 /* V9 and 86x have big and little endian data, but instructions are always big
101 endian. The sparclet has bi-endian support but both data and insns have
102 the same endianness. Global `target_big_endian' is used for data.
103 The following macro is used for instructions. */
104 #ifndef INSN_BIG_ENDIAN
105 #define INSN_BIG_ENDIAN (target_big_endian \
106 || default_arch_type == sparc86x \
107 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
110 /* handle of the OPCODE hash table */
111 static struct hash_control
*op_hash
;
113 static int log2
PARAMS ((int));
114 static void s_data1
PARAMS ((void));
115 static void s_seg
PARAMS ((int));
116 static void s_proc
PARAMS ((int));
117 static void s_reserve
PARAMS ((int));
118 static void s_common
PARAMS ((int));
119 static void s_empty
PARAMS ((int));
120 static void s_uacons
PARAMS ((int));
121 static void s_ncons
PARAMS ((int));
123 const pseudo_typeS md_pseudo_table
[] =
125 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
126 {"common", s_common
, 0},
127 {"empty", s_empty
, 0},
128 {"global", s_globl
, 0},
130 {"nword", s_ncons
, 0},
131 {"optim", s_ignore
, 0},
133 {"reserve", s_reserve
, 0},
135 {"skip", s_space
, 0},
138 {"uahalf", s_uacons
, 2},
139 {"uaword", s_uacons
, 4},
140 {"uaxword", s_uacons
, 8},
142 /* these are specific to sparc/svr4 */
143 {"pushsection", obj_elf_section
, 0},
144 {"popsection", obj_elf_previous
, 0},
145 {"2byte", s_uacons
, 2},
146 {"4byte", s_uacons
, 4},
147 {"8byte", s_uacons
, 8},
152 const int md_reloc_size
= 12; /* Size of relocation record */
154 /* This array holds the chars that always start a comment. If the
155 pre-processor is disabled, these aren't very useful */
156 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
158 /* This array holds the chars that only start a comment at the beginning of
159 a line. If the line seems to have the form '# 123 filename'
160 .line and .file directives will appear in the pre-processed output */
161 /* Note that input_file.c hand checks for '#' at the beginning of the
162 first line of the input file. This is because the compiler outputs
163 #NO_APP at the beginning of its output. */
164 /* Also note that comments started like this one will always
165 work if '/' isn't otherwise defined. */
166 const char line_comment_chars
[] = "#";
168 const char line_separator_chars
[] = "";
170 /* Chars that can be used to separate mant from exp in floating point nums */
171 const char EXP_CHARS
[] = "eE";
173 /* Chars that mean this number is a floating point constant */
176 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
178 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
179 changed in read.c. Ideally it shouldn't have to know about it at all,
180 but nothing is ideal around here. */
182 #define isoctal(c) ((unsigned)((c) - '0') < '8')
187 unsigned long opcode
;
188 struct nlist
*nlistp
;
192 bfd_reloc_code_real_type reloc
;
195 struct sparc_it the_insn
, set_insn
;
197 static void output_insn
198 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
200 /* Table of arguments to -A.
201 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
202 for this use. That table is for opcodes only. This table is for opcodes
205 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
206 v8plusa
, v9
, v9a
, v9_64
};
208 static struct sparc_arch
{
211 enum sparc_arch_types arch_type
;
212 /* Default word size, as specified during configuration.
213 A value of zero means can't be used to specify default architecture. */
214 int default_arch_size
;
215 /* Allowable arg to -A? */
217 } sparc_arch_table
[] = {
218 { "v6", "v6", v6
, 0, 1 },
219 { "v7", "v7", v7
, 0, 1 },
220 { "v8", "v8", v8
, 32, 1 },
221 { "sparclet", "sparclet", sparclet
, 32, 1 },
222 { "sparclite", "sparclite", sparclite
, 32, 1 },
223 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
224 { "v8plus", "v9", v9
, 0, 1 },
225 { "v8plusa", "v9a", v9
, 0, 1 },
226 { "v9", "v9", v9
, 0, 1 },
227 { "v9a", "v9a", v9
, 0, 1 },
228 /* This exists to allow configure.in/Makefile.in to pass one
229 value to specify both the default machine and default word size. */
230 { "v9-64", "v9", v9
, 64, 0 },
231 { NULL
, NULL
, v8
, 0, 0 }
234 /* Variant of default_arch */
235 static enum sparc_arch_types default_arch_type
;
237 static struct sparc_arch
*
241 struct sparc_arch
*sa
;
243 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
244 if (strcmp (sa
->name
, name
) == 0)
246 if (sa
->name
== NULL
)
251 /* Initialize the default opcode arch and word size from the default
252 architecture name. */
257 struct sparc_arch
*sa
= lookup_arch (default_arch
);
260 || sa
->default_arch_size
== 0)
261 as_fatal (_("Invalid default architecture, broken assembler."));
263 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
264 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
265 as_fatal (_("Bad opcode table, broken assembler."));
266 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
268 default_arch_type
= sa
->arch_type
;
271 /* Called by TARGET_FORMAT. */
274 sparc_target_format ()
276 /* We don't get a chance to initialize anything before we're called,
277 so handle that now. */
278 if (! default_init_p
)
279 init_default_arch ();
283 return "a.out-sparc-netbsd";
286 if (target_big_endian
)
287 return "a.out-sunos-big";
288 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
289 return "a.out-sunos-big";
290 else return "a.out-sparc-little";
292 return "a.out-sunos-big";
303 return "coff-sparc-lynx";
310 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
318 * Invocation line includes a switch not recognized by the base assembler.
319 * See if it's a processor-specific option. These are:
322 * Warn on architecture bumps. See also -A.
324 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
325 * Standard 32 bit architectures.
326 * -Av8plus, -Av8plusa
327 * Sparc64 in a 32 bit world.
329 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
330 * This used to only mean 64 bits, but properly specifying it
331 * complicated gcc's ASM_SPECs, so now opcode selection is
332 * specified orthogonally to word size (except when specifying
333 * the default, but that is an internal implementation detail).
334 * -xarch=v8plus, -xarch=v8plusa
335 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
337 * Select the architecture and possibly the file format.
338 * Instructions or features not supported by the selected
339 * architecture cause fatal errors.
341 * The default is to start at v6, and bump the architecture up
342 * whenever an instruction is seen at a higher level. In 32 bit
343 * environments, v9 is not bumped up to, the user must pass
346 * If -bump is specified, a warning is printing when bumping to
349 * If an architecture is specified, all instructions must match
350 * that architecture. Any higher level instructions are flagged
351 * as errors. Note that in the 32 bit environment specifying
352 * -Av8plus does not automatically create a v8plus object file, a
353 * v9 insn must be seen.
355 * If both an architecture and -bump are specified, the
356 * architecture starts at the specified level, but bumps are
357 * warnings. Note that we can't set `current_architecture' to
358 * the requested level in this case: in the 32 bit environment,
359 * we still must avoid creating v8plus object files unless v9
363 * Bumping between incompatible architectures is always an
364 * error. For example, from sparclite to v9.
368 CONST
char *md_shortopts
= "A:K:VQ:sq";
371 CONST
char *md_shortopts
= "A:k";
373 CONST
char *md_shortopts
= "A:";
376 struct option md_longopts
[] = {
377 #define OPTION_BUMP (OPTION_MD_BASE)
378 {"bump", no_argument
, NULL
, OPTION_BUMP
},
379 #define OPTION_SPARC (OPTION_MD_BASE + 1)
380 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
381 #define OPTION_XARCH (OPTION_MD_BASE + 2)
382 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
384 #define OPTION_32 (OPTION_MD_BASE + 3)
385 {"32", no_argument
, NULL
, OPTION_32
},
386 #define OPTION_64 (OPTION_MD_BASE + 4)
387 {"64", no_argument
, NULL
, OPTION_64
},
388 #define OPTION_TSO (OPTION_MD_BASE + 5)
389 {"TSO", no_argument
, NULL
, OPTION_TSO
},
390 #define OPTION_PSO (OPTION_MD_BASE + 6)
391 {"PSO", no_argument
, NULL
, OPTION_PSO
},
392 #define OPTION_RMO (OPTION_MD_BASE + 7)
393 {"RMO", no_argument
, NULL
, OPTION_RMO
},
395 #ifdef SPARC_BIENDIAN
396 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
397 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
398 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
399 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
401 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
402 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
403 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
404 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
405 {NULL
, no_argument
, NULL
, 0}
407 size_t md_longopts_size
= sizeof(md_longopts
);
410 md_parse_option (c
, arg
)
414 /* We don't get a chance to initialize anything before we're called,
415 so handle that now. */
416 if (! default_init_p
)
417 init_default_arch ();
423 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
427 /* This is for compatibility with Sun's assembler. */
428 if (strcmp (arg
, "v8plus") != 0
429 && strcmp (arg
, "v8plusa") != 0)
431 as_bad (_("invalid architecture -xarch=%s"), arg
);
439 struct sparc_arch
*sa
;
440 enum sparc_opcode_arch_val opcode_arch
;
442 sa
= lookup_arch (arg
);
444 || ! sa
->user_option_p
)
446 as_bad (_("invalid architecture -A%s"), arg
);
450 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
451 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
452 as_fatal (_("Bad opcode table, broken assembler."));
454 max_architecture
= opcode_arch
;
455 architecture_requested
= 1;
460 /* Ignore -sparc, used by SunOS make default .s.o rule. */
463 case OPTION_ENFORCE_ALIGNED_DATA
:
464 enforce_aligned_data
= 1;
467 #ifdef SPARC_BIENDIAN
468 case OPTION_LITTLE_ENDIAN
:
469 target_big_endian
= 0;
470 if (default_arch_type
!= sparclet
)
471 as_fatal ("This target does not support -EL");
473 case OPTION_LITTLE_ENDIAN_DATA
:
474 target_little_endian_data
= 1;
475 target_big_endian
= 0;
476 if (default_arch_type
!= sparc86x
477 && default_arch_type
!= v9
)
478 as_fatal ("This target does not support --little-endian-data");
480 case OPTION_BIG_ENDIAN
:
481 target_big_endian
= 1;
495 const char **list
, **l
;
497 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
498 list
= bfd_target_list ();
499 for (l
= list
; *l
!= NULL
; l
++)
501 if (sparc_arch_size
== 32)
503 if (strcmp (*l
, "elf32-sparc") == 0)
508 if (strcmp (*l
, "elf64-sparc") == 0)
513 as_fatal (_("No compiled in support for %d bit object file format"),
520 sparc_memory_model
= MM_TSO
;
524 sparc_memory_model
= MM_PSO
;
528 sparc_memory_model
= MM_RMO
;
536 /* Qy - do emit .comment
537 Qn - do not emit .comment */
541 /* use .stab instead of .stab.excl */
545 /* quick -- native assembler does fewer checks */
549 if (strcmp (arg
, "PIC") != 0)
550 as_warn (_("Unrecognized option following -K"));
564 md_show_usage (stream
)
567 const struct sparc_arch
*arch
;
569 /* We don't get a chance to initialize anything before we're called,
570 so handle that now. */
571 if (! default_init_p
)
572 init_default_arch ();
574 fprintf(stream
, _("SPARC options:\n"));
575 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
577 if (arch
!= &sparc_arch_table
[0])
578 fprintf (stream
, " | ");
579 if (arch
->user_option_p
)
580 fprintf (stream
, "-A%s", arch
->name
);
582 fprintf (stream
, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
583 fprintf (stream
, _("\
584 specify variant of SPARC architecture\n\
585 -bump warn when assembler switches architectures\n\
587 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
589 fprintf (stream
, _("\
590 -k generate PIC\n"));
593 fprintf (stream
, _("\
594 -32 create 32 bit object file\n\
595 -64 create 64 bit object file\n"));
596 fprintf (stream
, _("\
597 [default is %d]\n"), default_arch_size
);
598 fprintf (stream
, _("\
599 -TSO use Total Store Ordering\n\
600 -PSO use Partial Store Ordering\n\
601 -RMO use Relaxed Memory Ordering\n"));
602 fprintf (stream
, _("\
603 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
604 fprintf (stream
, _("\
605 -KPIC generate PIC\n\
606 -V print assembler version number\n\
611 #ifdef SPARC_BIENDIAN
612 fprintf (stream
, _("\
613 -EL generate code for a little endian machine\n\
614 -EB generate code for a big endian machine\n\
615 --little-endian-data generate code for a machine having big endian\n\
616 instructions and little endian data."));
620 /* native operand size opcode translation */
626 } native_op_table
[] =
628 {"ldn", "ld", "ldx"},
629 {"ldna", "lda", "ldxa"},
630 {"stn", "st", "stx"},
631 {"stna", "sta", "stxa"},
632 {"slln", "sll", "sllx"},
633 {"srln", "srl", "srlx"},
634 {"sran", "sra", "srax"},
635 {"casn", "cas", "casx"},
636 {"casna", "casa", "casxa"},
637 {"clrn", "clr", "clrx"},
641 /* sparc64 priviledged registers */
643 struct priv_reg_entry
649 struct priv_reg_entry priv_reg_table
[] =
668 {"", -1}, /* end marker */
671 /* v9a specific asrs */
673 struct priv_reg_entry v9a_asr_table
[] =
682 {"clear_softint", 21},
683 {"", -1}, /* end marker */
687 cmp_reg_entry (parg
, qarg
)
691 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
692 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
694 return strcmp (q
->name
, p
->name
);
697 /* This function is called once, at assembler startup time. It should
698 set up all the tables, etc. that the MD part of the assembler will need. */
703 register const char *retval
= NULL
;
705 register unsigned int i
= 0;
707 /* We don't get a chance to initialize anything before md_parse_option
708 is called, and it may not be called, so handle default initialization
709 now if not already done. */
710 if (! default_init_p
)
711 init_default_arch ();
713 op_hash
= hash_new ();
715 while (i
< (unsigned int) sparc_num_opcodes
)
717 const char *name
= sparc_opcodes
[i
].name
;
718 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
721 as_bad (_("Internal error: can't hash `%s': %s\n"),
722 sparc_opcodes
[i
].name
, retval
);
727 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
729 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
730 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
735 while (i
< (unsigned int) sparc_num_opcodes
736 && !strcmp (sparc_opcodes
[i
].name
, name
));
739 for (i
= 0; native_op_table
[i
].name
; i
++)
741 const struct sparc_opcode
*insn
;
742 char *name
= sparc_arch_size
== 32 ? native_op_table
[i
].name32
:
743 native_op_table
[i
].name64
;
744 insn
= (struct sparc_opcode
*)hash_find (op_hash
, name
);
747 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
748 name
, native_op_table
[i
].name
);
753 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
756 as_bad (_("Internal error: can't hash `%s': %s\n"),
757 sparc_opcodes
[i
].name
, retval
);
764 as_fatal (_("Broken assembler. No assembly attempted."));
766 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
767 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
769 /* If -bump, record the architecture level at which we start issuing
770 warnings. The behaviour is different depending upon whether an
771 architecture was explicitly specified. If it wasn't, we issue warnings
772 for all upwards bumps. If it was, we don't start issuing warnings until
773 we need to bump beyond the requested architecture or when we bump between
774 conflicting architectures. */
777 && architecture_requested
)
779 /* `max_architecture' records the requested architecture.
780 Issue warnings if we go above it. */
781 warn_after_architecture
= max_architecture
;
783 /* Find the highest architecture level that doesn't conflict with
784 the requested one. */
785 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
786 max_architecture
> warn_after_architecture
;
788 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
789 warn_after_architecture
))
794 /* Called after all assembly has been done. */
799 if (sparc_arch_size
== 64)
801 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
802 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
804 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
808 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
809 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
810 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
811 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
812 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
813 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
814 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
815 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclite_le
);
818 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
819 be but for now it is (since that's the way it's always been
821 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
826 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
829 in_signed_range (val
, max
)
830 bfd_signed_vma val
, max
;
834 /* Sign-extend the value from the architecture word size, so that
835 0xffffffff is always considered -1 on sparc32. */
836 if (sparc_arch_size
== 32)
838 bfd_signed_vma sign
= (bfd_signed_vma
)1 << 31;
839 val
= ((val
& 0xffffffff) ^ sign
) - sign
;
848 /* Return non-zero if VAL is in the range 0 to MAX. */
851 in_unsigned_range (val
, max
)
859 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
860 (e.g. -15 to +31). */
863 in_bitfield_range (val
, max
)
864 bfd_signed_vma val
, max
;
870 if (val
< ~(max
>> 1))
884 for (i
= 0; (mask
& 1) == 0; ++i
)
889 /* Implement big shift right. */
895 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
896 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
897 return val
>> amount
;
900 /* For communication between sparc_ip and get_expression. */
901 static char *expr_end
;
903 /* Values for `special_case'.
904 Instructions that require wierd handling because they're longer than
906 #define SPECIAL_CASE_NONE 0
907 #define SPECIAL_CASE_SET 1
908 #define SPECIAL_CASE_SETSW 2
909 #define SPECIAL_CASE_SETX 3
910 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
911 #define SPECIAL_CASE_FDIV 4
913 /* Bit masks of various insns. */
914 #define NOP_INSN 0x01000000
915 #define OR_INSN 0x80100000
916 #define XOR_INSN 0x80180000
917 #define FMOVS_INSN 0x81A00020
918 #define SETHI_INSN 0x01000000
919 #define SLLX_INSN 0x81281000
920 #define SRA_INSN 0x81380000
922 /* The last instruction to be assembled. */
923 static const struct sparc_opcode
*last_insn
;
924 /* The assembled opcode of `last_insn'. */
925 static unsigned long last_opcode
;
927 /* Handle the set and setuw synthetic instructions. */
929 synthetize_setuw (insn
)
930 const struct sparc_opcode
*insn
;
933 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
935 if (the_insn
.exp
.X_op
== O_constant
)
937 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
939 if (sizeof(offsetT
) > 4
940 && (the_insn
.exp
.X_add_number
< 0
941 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
942 as_warn (_("set: number not in 0..4294967295 range"));
946 if (sizeof(offsetT
) > 4
947 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
948 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
949 as_warn (_("set: number not in -2147483648..4294967295 range"));
950 the_insn
.exp
.X_add_number
= (int)the_insn
.exp
.X_add_number
;
954 /* See if operand is absolute and small; skip sethi if so. */
955 if (the_insn
.exp
.X_op
!= O_constant
956 || the_insn
.exp
.X_add_number
>= (1 << 12)
957 || the_insn
.exp
.X_add_number
< -(1 << 12))
959 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
960 | ((the_insn
.exp
.X_add_number
>> 10)
961 & (the_insn
.exp
.X_op
== O_constant
? 0x3fffff : 0)));
962 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
965 output_insn (insn
, &the_insn
);
969 /* See if operand has no low-order bits; skip OR if so. */
970 if (the_insn
.exp
.X_op
!= O_constant
971 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
974 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
976 | (the_insn
.exp
.X_add_number
977 & (the_insn
.exp
.X_op
!= O_constant
? 0 :
978 need_hi22_p
? 0x3ff : 0x1fff)));
979 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
982 output_insn (insn
, &the_insn
);
986 /* Handle the setsw synthetic instruction. */
988 synthetize_setsw (insn
)
989 const struct sparc_opcode
*insn
;
993 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
995 if (the_insn
.exp
.X_op
!= O_constant
)
997 synthetize_setuw (insn
);
999 /* Need to sign extend it. */
1000 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1001 the_insn
.reloc
= BFD_RELOC_NONE
;
1002 output_insn (insn
, &the_insn
);
1006 if (sizeof(offsetT
) > 4
1007 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1008 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1009 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1011 low32
= the_insn
.exp
.X_add_number
;
1015 synthetize_setuw (insn
);
1021 the_insn
.reloc
= BFD_RELOC_NONE
;
1022 /* See if operand is absolute and small; skip sethi if so. */
1023 if (low32
< -(1 << 12))
1025 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1026 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1027 output_insn (insn
, &the_insn
);
1028 low32
= 0x1c00 | (low32
& 0x3ff);
1029 opc
= RS1 (rd
) | XOR_INSN
;
1032 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1033 | (low32
& 0x1fff));
1034 output_insn (insn
, &the_insn
);
1037 /* Handle the setsw synthetic instruction. */
1039 synthetize_setx (insn
)
1040 const struct sparc_opcode
*insn
;
1042 int upper32
, lower32
;
1043 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1044 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1046 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1047 int need_xor10_p
= 0;
1049 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1050 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1051 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1054 upper_dstreg
= tmpreg
;
1055 /* The tmp reg should not be the dst reg. */
1056 if (tmpreg
== dstreg
)
1057 as_warn (_("setx: temporary register same as destination register"));
1059 /* ??? Obviously there are other optimizations we can do
1060 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1061 doing some of these. Later. If you do change things, try to
1062 change all of this to be table driven as well. */
1063 /* What to output depends on the number if it's constant.
1064 Compute that first, then output what we've decided upon. */
1065 if (the_insn
.exp
.X_op
!= O_constant
)
1067 if (sparc_arch_size
== 32)
1069 /* When arch size is 32, we want setx to be equivalent
1070 to setuw for anything but constants. */
1071 the_insn
.exp
.X_add_number
&= 0xffffffff;
1072 synthetize_setuw (insn
);
1075 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1076 lower32
= 0; upper32
= 0;
1080 /* Reset X_add_number, we've extracted it as upper32/lower32.
1081 Otherwise fixup_segment will complain about not being able to
1082 write an 8 byte number in a 4 byte field. */
1083 the_insn
.exp
.X_add_number
= 0;
1085 /* Only need hh22 if `or' insn can't handle constant. */
1086 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1089 /* Does bottom part (after sethi) have bits? */
1090 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1091 /* No hh22, but does upper32 still have bits we can't set
1093 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1096 /* If the lower half is all zero, we build the upper half directly
1097 into the dst reg. */
1099 /* Need lower half if number is zero or 0xffffffff00000000. */
1100 || (! need_hh22_p
&& ! need_hm10_p
))
1102 /* No need for sethi if `or' insn can handle constant. */
1103 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1104 /* Note that we can't use a negative constant in the `or'
1105 insn unless the upper 32 bits are all ones. */
1106 || (lower32
< 0 && upper32
!= -1)
1107 || (lower32
>= 0 && upper32
== -1))
1110 if (need_hi22_p
&& upper32
== -1)
1113 /* Does bottom part (after sethi) have bits? */
1114 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1116 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1117 /* Need `or' if we didn't set anything else. */
1118 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1122 /* Output directly to dst reg if lower 32 bits are all zero. */
1123 upper_dstreg
= dstreg
;
1126 if (!upper_dstreg
&& dstreg
)
1127 as_warn (_("setx: illegal temporary register g0"));
1131 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1132 | ((upper32
>> 10) & 0x3fffff));
1133 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1134 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1135 output_insn (insn
, &the_insn
);
1140 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1141 | (((need_xor10_p
? ~lower32
: lower32
)
1142 >> 10) & 0x3fffff));
1143 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1144 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1145 output_insn (insn
, &the_insn
);
1150 the_insn
.opcode
= (OR_INSN
1151 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1154 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1155 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1156 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1157 output_insn (insn
, &the_insn
);
1162 /* FIXME: One nice optimization to do here is to OR the low part
1163 with the highpart if hi22 isn't needed and the low part is
1165 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1168 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1169 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1170 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1171 output_insn (insn
, &the_insn
);
1174 /* If we needed to build the upper part, shift it into place. */
1175 if (need_hh22_p
|| need_hm10_p
)
1177 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1179 the_insn
.reloc
= BFD_RELOC_NONE
;
1180 output_insn (insn
, &the_insn
);
1183 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1186 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1187 | 0x1c00 | (lower32
& 0x3ff));
1188 the_insn
.reloc
= BFD_RELOC_NONE
;
1189 output_insn (insn
, &the_insn
);
1192 /* If we needed to build both upper and lower parts, OR them together. */
1193 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1195 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1197 the_insn
.reloc
= BFD_RELOC_NONE
;
1198 output_insn (insn
, &the_insn
);
1202 /* Main entry point to assemble one instruction. */
1208 const struct sparc_opcode
*insn
;
1212 special_case
= sparc_ip (str
, &insn
);
1214 /* We warn about attempts to put a floating point branch in a delay slot,
1215 unless the delay slot has been annulled. */
1217 && last_insn
!= NULL
1218 && (insn
->flags
& F_FBR
) != 0
1219 && (last_insn
->flags
& F_DELAYED
) != 0
1220 /* ??? This test isn't completely accurate. We assume anything with
1221 F_{UNBR,CONDBR,FBR} set is annullable. */
1222 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1223 || (last_opcode
& ANNUL
) == 0))
1224 as_warn (_("FP branch in delay slot"));
1226 /* SPARC before v9 requires a nop instruction between a floating
1227 point instruction and a floating point branch. We insert one
1228 automatically, with a warning. */
1229 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1231 && last_insn
!= NULL
1232 && (insn
->flags
& F_FBR
) != 0
1233 && (last_insn
->flags
& F_FLOAT
) != 0)
1235 struct sparc_it nop_insn
;
1237 nop_insn
.opcode
= NOP_INSN
;
1238 nop_insn
.reloc
= BFD_RELOC_NONE
;
1239 output_insn (insn
, &nop_insn
);
1240 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1243 switch (special_case
)
1245 case SPECIAL_CASE_NONE
:
1247 output_insn (insn
, &the_insn
);
1250 case SPECIAL_CASE_SETSW
:
1251 synthetize_setsw (insn
);
1254 case SPECIAL_CASE_SET
:
1255 synthetize_setuw (insn
);
1258 case SPECIAL_CASE_SETX
:
1259 synthetize_setx (insn
);
1262 case SPECIAL_CASE_FDIV
:
1264 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1266 output_insn (insn
, &the_insn
);
1268 /* According to information leaked from Sun, the "fdiv" instructions
1269 on early SPARC machines would produce incorrect results sometimes.
1270 The workaround is to add an fmovs of the destination register to
1271 itself just after the instruction. This was true on machines
1272 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1273 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1274 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1275 output_insn (insn
, &the_insn
);
1280 as_fatal (_("failed special case insn sanity check"));
1284 /* Subroutine of md_assemble to do the actual parsing. */
1287 sparc_ip (str
, pinsn
)
1289 const struct sparc_opcode
**pinsn
;
1291 char *error_message
= "";
1295 const struct sparc_opcode
*insn
;
1297 unsigned long opcode
;
1298 unsigned int mask
= 0;
1302 int special_case
= SPECIAL_CASE_NONE
;
1305 if (islower ((unsigned char) *s
))
1309 while (islower ((unsigned char) *s
) || isdigit ((unsigned char) *s
));
1327 as_fatal (_("Unknown opcode: `%s'"), str
);
1329 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1333 as_bad (_("Unknown opcode: `%s'"), str
);
1334 return special_case
;
1344 opcode
= insn
->match
;
1345 memset (&the_insn
, '\0', sizeof (the_insn
));
1346 the_insn
.reloc
= BFD_RELOC_NONE
;
1350 * Build the opcode, checking as we go to make
1351 * sure that the operands match
1353 for (args
= insn
->args
;; ++args
)
1361 /* Parse a series of masks. */
1368 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1371 error_message
= _(": invalid membar mask name");
1375 while (*s
== ' ') { ++s
; continue; }
1376 if (*s
== '|' || *s
== '+')
1378 while (*s
== ' ') { ++s
; continue; }
1383 if (! parse_const_expr_arg (&s
, &kmask
))
1385 error_message
= _(": invalid membar mask expression");
1388 if (kmask
< 0 || kmask
> 127)
1390 error_message
= _(": invalid membar mask number");
1395 opcode
|= MEMBAR (kmask
);
1403 /* Parse a prefetch function. */
1406 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1408 error_message
= _(": invalid prefetch function name");
1414 if (! parse_const_expr_arg (&s
, &fcn
))
1416 error_message
= _(": invalid prefetch function expression");
1419 if (fcn
< 0 || fcn
> 31)
1421 error_message
= _(": invalid prefetch function number");
1431 /* Parse a sparc64 privileged register. */
1434 struct priv_reg_entry
*p
= priv_reg_table
;
1435 unsigned int len
= 9999999; /* init to make gcc happy */
1438 while (p
->name
[0] > s
[0])
1440 while (p
->name
[0] == s
[0])
1442 len
= strlen (p
->name
);
1443 if (strncmp (p
->name
, s
, len
) == 0)
1447 if (p
->name
[0] != s
[0])
1449 error_message
= _(": unrecognizable privileged register");
1453 opcode
|= (p
->regnum
<< 14);
1455 opcode
|= (p
->regnum
<< 25);
1461 error_message
= _(": unrecognizable privileged register");
1467 /* Parse a v9a ancillary state register. */
1470 struct priv_reg_entry
*p
= v9a_asr_table
;
1471 unsigned int len
= 9999999; /* init to make gcc happy */
1474 while (p
->name
[0] > s
[0])
1476 while (p
->name
[0] == s
[0])
1478 len
= strlen (p
->name
);
1479 if (strncmp (p
->name
, s
, len
) == 0)
1483 if (p
->name
[0] != s
[0])
1485 error_message
= _(": unrecognizable v9a ancillary state register");
1488 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1490 error_message
= _(": rd on write only ancillary state register");
1494 opcode
|= (p
->regnum
<< 14);
1496 opcode
|= (p
->regnum
<< 25);
1502 error_message
= _(": unrecognizable v9a ancillary state register");
1508 if (strncmp (s
, "%asr", 4) == 0)
1512 if (isdigit ((unsigned char) *s
))
1516 while (isdigit ((unsigned char) *s
))
1518 num
= num
* 10 + *s
- '0';
1522 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1524 if (num
< 16 || 31 < num
)
1526 error_message
= _(": asr number must be between 16 and 31");
1532 if (num
< 0 || 31 < num
)
1534 error_message
= _(": asr number must be between 0 and 31");
1539 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1544 error_message
= _(": expecting %asrN");
1551 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1555 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1559 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1560 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1561 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1563 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1564 /* These fields are unsigned, but for upward compatibility,
1565 allow negative values as well. */
1569 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1570 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1571 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1573 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1574 /* These fields are unsigned, but for upward compatibility,
1575 allow negative values as well. */
1579 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1584 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1589 if (*s
== 'p' && s
[1] == 'n')
1597 if (*s
== 'p' && s
[1] == 't')
1609 if (strncmp (s
, "%icc", 4) == 0)
1621 if (strncmp (s
, "%xcc", 4) == 0)
1633 if (strncmp (s
, "%fcc0", 5) == 0)
1645 if (strncmp (s
, "%fcc1", 5) == 0)
1657 if (strncmp (s
, "%fcc2", 5) == 0)
1669 if (strncmp (s
, "%fcc3", 5) == 0)
1677 if (strncmp (s
, "%pc", 3) == 0)
1685 if (strncmp (s
, "%tick", 5) == 0)
1692 case '\0': /* end of args */
1711 case '[': /* these must match exactly */
1719 case '#': /* must be at least one digit */
1720 if (isdigit ((unsigned char) *s
++))
1722 while (isdigit ((unsigned char) *s
))
1730 case 'C': /* coprocessor state register */
1731 if (strncmp (s
, "%csr", 4) == 0)
1738 case 'b': /* next operand is a coprocessor register */
1741 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1744 if (isdigit ((unsigned char) *s
))
1746 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1760 opcode
|= mask
<< 14;
1768 opcode
|= mask
<< 25;
1774 case 'r': /* next operand must be a register */
1784 case 'f': /* frame pointer */
1792 case 'g': /* global register */
1801 case 'i': /* in register */
1805 mask
= c
- '0' + 24;
1810 case 'l': /* local register */
1814 mask
= (c
- '0' + 16);
1819 case 'o': /* out register */
1823 mask
= (c
- '0' + 8);
1828 case 's': /* stack pointer */
1836 case 'r': /* any register */
1837 if (!isdigit ((unsigned char) (c
= *s
++)))
1852 if (isdigit ((unsigned char) *s
))
1854 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1870 /* Got the register, now figure out where
1871 it goes in the opcode. */
1875 opcode
|= mask
<< 14;
1883 opcode
|= mask
<< 25;
1887 opcode
|= (mask
<< 25) | (mask
<< 14);
1891 opcode
|= (mask
<< 25) | (mask
<< 0);
1897 case 'e': /* next operand is a floating point register */
1912 && ((format
= *s
) == 'f')
1913 && isdigit ((unsigned char) *++s
))
1915 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1917 mask
= 10 * mask
+ (*s
- '0');
1918 } /* read the number */
1926 } /* register must be even numbered */
1934 } /* register must be multiple of 4 */
1938 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1939 error_message
= _(": There are only 64 f registers; [0-63]");
1941 error_message
= _(": There are only 32 f registers; [0-31]");
1944 else if (mask
>= 32)
1946 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1949 mask
-= 31; /* wrap high bit */
1953 error_message
= _(": There are only 32 f registers; [0-31]");
1961 } /* if not an 'f' register. */
1968 opcode
|= RS1 (mask
);
1975 opcode
|= RS2 (mask
);
1981 opcode
|= RD (mask
);
1990 if (strncmp (s
, "%fsr", 4) == 0)
1997 case '0': /* 64 bit immediate (set, setsw, setx insn) */
1998 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2001 case 'l': /* 22 bit PC relative immediate */
2002 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2006 case 'L': /* 30 bit immediate */
2007 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2012 case 'n': /* 22 bit immediate */
2013 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2016 case 'i': /* 13 bit immediate */
2017 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2027 char *op_arg
= NULL
;
2029 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2031 /* Check for %hi, etc. */
2034 static const struct ops
{
2035 /* The name as it appears in assembler. */
2037 /* strlen (name), precomputed for speed */
2039 /* The reloc this pseudo-op translates to. */
2041 /* Non-zero if for v9 only. */
2043 /* Non-zero if can be used in pc-relative contexts. */
2044 int pcrel_p
;/*FIXME:wip*/
2046 /* hix/lox must appear before hi/lo so %hix won't be
2047 mistaken for %hi. */
2048 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2049 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2050 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2051 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2052 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2053 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2054 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2055 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2056 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2057 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2058 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2059 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2062 const struct ops
*o
;
2064 for (o
= ops
; o
->name
; o
++)
2065 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2067 if (o
->name
== NULL
)
2070 if (s
[o
->len
+ 1] != '(')
2072 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2073 return special_case
;
2077 the_insn
.reloc
= o
->reloc
;
2082 /* Note that if the get_expression() fails, we will still
2083 have created U entries in the symbol table for the
2084 'symbols' in the input string. Try not to create U
2085 symbols for registers, etc. */
2087 /* This stuff checks to see if the expression ends in
2088 +%reg. If it does, it removes the register from
2089 the expression, and re-sets 's' to point to the
2096 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2099 else if (*s1
== ')')
2108 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2109 return special_case
;
2113 (void) get_expression (s
);
2116 if (*s
== ',' || *s
== ']' || !*s
)
2118 if (*s
!= '+' && *s
!= '-')
2120 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2121 return special_case
;
2125 op_exp
= the_insn
.exp
;
2126 memset (&the_insn
.exp
, 0, sizeof(the_insn
.exp
));
2129 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
2131 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
2133 if (s1
[-2] == '%' && s1
[-3] == '+')
2135 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2142 (void) get_expression (s
);
2154 (void) get_expression (s
);
2162 the_insn
.exp2
= the_insn
.exp
;
2163 the_insn
.exp
= op_exp
;
2164 if (the_insn
.exp2
.X_op
== O_absent
)
2165 the_insn
.exp2
.X_op
= O_illegal
;
2166 else if (the_insn
.exp
.X_op
== O_absent
)
2168 the_insn
.exp
= the_insn
.exp2
;
2169 the_insn
.exp2
.X_op
= O_illegal
;
2171 else if (the_insn
.exp
.X_op
== O_constant
)
2173 valueT val
= the_insn
.exp
.X_add_number
;
2174 switch (the_insn
.reloc
)
2179 case BFD_RELOC_SPARC_HH22
:
2180 val
= BSR (val
, 32);
2181 /* intentional fallthrough */
2183 case BFD_RELOC_SPARC_LM22
:
2184 case BFD_RELOC_HI22
:
2185 val
= (val
>> 10) & 0x3fffff;
2188 case BFD_RELOC_SPARC_HM10
:
2189 val
= BSR (val
, 32);
2190 /* intentional fallthrough */
2192 case BFD_RELOC_LO10
:
2196 case BFD_RELOC_SPARC_H44
:
2201 case BFD_RELOC_SPARC_M44
:
2206 case BFD_RELOC_SPARC_L44
:
2210 case BFD_RELOC_SPARC_HIX22
:
2212 val
= (val
>> 10) & 0x3fffff;
2215 case BFD_RELOC_SPARC_LOX10
:
2216 val
= (val
& 0x3ff) | 0x1c00;
2219 the_insn
.exp
= the_insn
.exp2
;
2220 the_insn
.exp
.X_add_number
+= val
;
2221 the_insn
.exp2
.X_op
= O_illegal
;
2222 the_insn
.reloc
= old_reloc
;
2224 else if (the_insn
.exp2
.X_op
!= O_constant
)
2226 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2227 return special_case
;
2231 if (1 || old_reloc
!= BFD_RELOC_SPARC13
2232 || the_insn
.reloc
!= BFD_RELOC_LO10
2233 || sparc_arch_size
!= 64
2236 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2237 return special_case
;
2239 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2243 /* Check for constants that don't require emitting a reloc. */
2244 if (the_insn
.exp
.X_op
== O_constant
2245 && the_insn
.exp
.X_add_symbol
== 0
2246 && the_insn
.exp
.X_op_symbol
== 0)
2248 /* For pc-relative call instructions, we reject
2249 constants to get better code. */
2251 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2252 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2254 error_message
= _(": PC-relative operand can't be a constant");
2258 /* Constants that won't fit are checked in md_apply_fix3
2259 and bfd_install_relocation.
2260 ??? It would be preferable to install the constants
2261 into the insn here and save having to create a fixS
2262 for each one. There already exists code to handle
2263 all the various cases (e.g. in md_apply_fix3 and
2264 bfd_install_relocation) so duplicating all that code
2265 here isn't right. */
2285 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2287 error_message
= _(": invalid ASI name");
2293 if (! parse_const_expr_arg (&s
, &asi
))
2295 error_message
= _(": invalid ASI expression");
2298 if (asi
< 0 || asi
> 255)
2300 error_message
= _(": invalid ASI number");
2304 opcode
|= ASI (asi
);
2306 } /* alternate space */
2309 if (strncmp (s
, "%psr", 4) == 0)
2316 case 'q': /* floating point queue */
2317 if (strncmp (s
, "%fq", 3) == 0)
2324 case 'Q': /* coprocessor queue */
2325 if (strncmp (s
, "%cq", 3) == 0)
2333 if (strcmp (str
, "set") == 0
2334 || strcmp (str
, "setuw") == 0)
2336 special_case
= SPECIAL_CASE_SET
;
2339 else if (strcmp (str
, "setsw") == 0)
2341 special_case
= SPECIAL_CASE_SETSW
;
2344 else if (strcmp (str
, "setx") == 0)
2346 special_case
= SPECIAL_CASE_SETX
;
2349 else if (strncmp (str
, "fdiv", 4) == 0)
2351 special_case
= SPECIAL_CASE_FDIV
;
2357 if (strncmp (s
, "%asi", 4) != 0)
2363 if (strncmp (s
, "%fprs", 5) != 0)
2369 if (strncmp (s
, "%ccr", 4) != 0)
2375 if (strncmp (s
, "%tbr", 4) != 0)
2381 if (strncmp (s
, "%wim", 4) != 0)
2388 char *push
= input_line_pointer
;
2391 input_line_pointer
= s
;
2393 if (e
.X_op
== O_constant
)
2395 int n
= e
.X_add_number
;
2396 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2397 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2399 opcode
|= e
.X_add_number
<< 5;
2402 as_bad (_("non-immediate OPF operand, ignored"));
2403 s
= input_line_pointer
;
2404 input_line_pointer
= push
;
2409 if (strncmp (s
, "%y", 2) != 0)
2417 /* Parse a sparclet cpreg. */
2419 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2421 error_message
= _(": invalid cpreg name");
2424 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2429 as_fatal (_("failed sanity check."));
2430 } /* switch on arg code */
2432 /* Break out of for() loop. */
2434 } /* for each arg that we expect */
2439 /* Args don't match. */
2440 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2441 && (insn
->name
== insn
[1].name
2442 || !strcmp (insn
->name
, insn
[1].name
)))
2450 as_bad (_("Illegal operands%s"), error_message
);
2451 return special_case
;
2456 /* We have a match. Now see if the architecture is ok. */
2457 int needed_arch_mask
= insn
->architecture
;
2461 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2462 | (1 << SPARC_OPCODE_ARCH_V9A
));
2463 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2466 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2468 /* Can we bump up the architecture? */
2469 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2471 enum sparc_opcode_arch_val needed_architecture
=
2472 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2473 & needed_arch_mask
);
2475 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2477 && needed_architecture
> warn_after_architecture
)
2479 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2480 sparc_opcode_archs
[current_architecture
].name
,
2481 sparc_opcode_archs
[needed_architecture
].name
,
2483 warn_after_architecture
= needed_architecture
;
2485 current_architecture
= needed_architecture
;
2488 /* ??? This seems to be a bit fragile. What if the next entry in
2489 the opcode table is the one we want and it is supported?
2490 It is possible to arrange the table today so that this can't
2491 happen but what about tomorrow? */
2494 int arch
,printed_one_p
= 0;
2496 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2498 /* Create a list of the architectures that support the insn. */
2499 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2501 arch
= sparc_ffs (needed_arch_mask
);
2502 while ((1 << arch
) <= needed_arch_mask
)
2504 if ((1 << arch
) & needed_arch_mask
)
2508 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2515 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2516 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2518 sparc_opcode_archs
[max_architecture
].name
);
2519 return special_case
;
2524 } /* forever looking for a match */
2526 the_insn
.opcode
= opcode
;
2527 return special_case
;
2530 /* Parse an argument that can be expressed as a keyword.
2531 (eg: #StoreStore or %ccfr).
2532 The result is a boolean indicating success.
2533 If successful, INPUT_POINTER is updated. */
2536 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2537 int (*lookup_fn
) PARAMS ((const char *));
2538 char **input_pointerP
;
2544 p
= *input_pointerP
;
2545 for (q
= p
+ (*p
== '#' || *p
== '%');
2546 isalnum ((unsigned char) *q
) || *q
== '_';
2551 value
= (*lookup_fn
) (p
);
2556 *input_pointerP
= q
;
2560 /* Parse an argument that is a constant expression.
2561 The result is a boolean indicating success. */
2564 parse_const_expr_arg (input_pointerP
, valueP
)
2565 char **input_pointerP
;
2568 char *save
= input_line_pointer
;
2571 input_line_pointer
= *input_pointerP
;
2572 /* The next expression may be something other than a constant
2573 (say if we're not processing the right variant of the insn).
2574 Don't call expression unless we're sure it will succeed as it will
2575 signal an error (which we want to defer until later). */
2576 /* FIXME: It might be better to define md_operand and have it recognize
2577 things like %asi, etc. but continuing that route through to the end
2578 is a lot of work. */
2579 if (*input_line_pointer
== '%')
2581 input_line_pointer
= save
;
2585 *input_pointerP
= input_line_pointer
;
2586 input_line_pointer
= save
;
2587 if (exp
.X_op
!= O_constant
)
2589 *valueP
= exp
.X_add_number
;
2593 /* Subroutine of sparc_ip to parse an expression. */
2596 get_expression (str
)
2602 save_in
= input_line_pointer
;
2603 input_line_pointer
= str
;
2604 seg
= expression (&the_insn
.exp
);
2605 if (seg
!= absolute_section
2606 && seg
!= text_section
2607 && seg
!= data_section
2608 && seg
!= bss_section
2609 && seg
!= undefined_section
)
2611 the_insn
.error
= _("bad segment");
2612 expr_end
= input_line_pointer
;
2613 input_line_pointer
= save_in
;
2616 expr_end
= input_line_pointer
;
2617 input_line_pointer
= save_in
;
2621 /* Subroutine of md_assemble to output one insn. */
2624 output_insn (insn
, the_insn
)
2625 const struct sparc_opcode
*insn
;
2626 struct sparc_it
*the_insn
;
2628 char *toP
= frag_more (4);
2630 /* put out the opcode */
2631 if (INSN_BIG_ENDIAN
)
2632 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2634 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2636 /* put out the symbol-dependent stuff */
2637 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2639 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2640 (toP
- frag_now
->fr_literal
), /* where */
2645 /* Turn off overflow checking in fixup_segment. We'll do our
2646 own overflow checking in md_apply_fix3. This is necessary because
2647 the insn size is 4 and fixup_segment will signal an overflow for
2648 large 8 byte quantities. */
2649 fixP
->fx_no_overflow
= 1;
2653 last_opcode
= the_insn
->opcode
;
2657 This is identical to the md_atof in m68k.c. I think this is right,
2660 Turn a string in input_line_pointer into a floating point constant of type
2661 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2662 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2665 /* Equal to MAX_PRECISION in atof-ieee.c */
2666 #define MAX_LITTLENUMS 6
2669 md_atof (type
, litP
, sizeP
)
2675 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2706 return _("Bad call to MD_ATOF()");
2709 t
= atof_ieee (input_line_pointer
, type
, words
);
2711 input_line_pointer
= t
;
2712 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2714 if (target_big_endian
)
2716 for (i
= 0; i
< prec
; i
++)
2718 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2719 litP
+= sizeof (LITTLENUM_TYPE
);
2724 for (i
= prec
- 1; i
>= 0; i
--)
2726 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2727 litP
+= sizeof (LITTLENUM_TYPE
);
2734 /* Write a value out to the object file, using the appropriate
2738 md_number_to_chars (buf
, val
, n
)
2743 if (target_big_endian
)
2744 number_to_chars_bigendian (buf
, val
, n
);
2745 else if (target_little_endian_data
2746 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2747 /* Output debug words, which are not in allocated sections, as big endian */
2748 number_to_chars_bigendian (buf
, val
, n
);
2749 else if (target_little_endian_data
|| ! target_big_endian
)
2750 number_to_chars_littleendian (buf
, val
, n
);
2753 /* Apply a fixS to the frags, now that we know the value it ought to
2757 md_apply_fix3 (fixP
, value
, segment
)
2762 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2768 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2770 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2773 /* FIXME: SPARC ELF relocations don't use an addend in the data
2774 field itself. This whole approach should be somehow combined
2775 with the calls to bfd_install_relocation. Also, the value passed
2776 in by fixup_segment includes the value of a defined symbol. We
2777 don't want to include the value of an externally visible symbol. */
2778 if (fixP
->fx_addsy
!= NULL
)
2780 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
2781 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2782 || S_IS_WEAK (fixP
->fx_addsy
)
2783 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2784 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2785 && ((bfd_get_section_flags (stdoutput
,
2786 S_GET_SEGMENT (fixP
->fx_addsy
))
2787 & SEC_LINK_ONCE
) != 0
2788 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2790 sizeof ".gnu.linkonce" - 1) == 0)))
2791 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2792 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2793 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2794 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2799 /* This is a hack. There should be a better way to
2800 handle this. Probably in terms of howto fields, once
2801 we can look at these fixups in terms of howtos. */
2802 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2803 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2806 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2807 generate a reloc, then we just want to let the reloc addend set
2808 the value. We do not want to also stuff the addend into the
2809 object file. Including the addend in the object file works when
2810 doing a static link, because the linker will ignore the object
2811 file contents. However, the dynamic linker does not ignore the
2812 object file contents. */
2813 if (fixP
->fx_addsy
!= NULL
2814 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2817 /* When generating PIC code, we do not want an addend for a reloc
2818 against a local symbol. We adjust fx_addnumber to cancel out the
2819 value already included in val, and to also cancel out the
2820 adjustment which bfd_install_relocation will create. */
2822 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2823 && fixP
->fx_addsy
!= NULL
2824 && ! S_IS_COMMON (fixP
->fx_addsy
)
2825 && symbol_section_p (fixP
->fx_addsy
))
2826 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2828 /* When generating PIC code, we need to fiddle to get
2829 bfd_install_relocation to do the right thing for a PC relative
2830 reloc against a local symbol which we are going to keep. */
2832 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
2833 && fixP
->fx_addsy
!= NULL
2834 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2835 || S_IS_WEAK (fixP
->fx_addsy
))
2836 && S_IS_DEFINED (fixP
->fx_addsy
)
2837 && ! S_IS_COMMON (fixP
->fx_addsy
))
2840 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2844 /* If this is a data relocation, just output VAL. */
2846 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2848 md_number_to_chars (buf
, val
, 2);
2850 else if (fixP
->fx_r_type
== BFD_RELOC_32
2851 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
2853 md_number_to_chars (buf
, val
, 4);
2855 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2857 md_number_to_chars (buf
, val
, 8);
2859 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2860 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2867 /* It's a relocation against an instruction. */
2869 if (INSN_BIG_ENDIAN
)
2870 insn
= bfd_getb32 ((unsigned char *) buf
);
2872 insn
= bfd_getl32 ((unsigned char *) buf
);
2874 switch (fixP
->fx_r_type
)
2876 case BFD_RELOC_32_PCREL_S2
:
2878 /* FIXME: This increment-by-one deserves a comment of why it's
2880 if (! sparc_pic_code
2881 || fixP
->fx_addsy
== NULL
2882 || symbol_section_p (fixP
->fx_addsy
))
2884 insn
|= val
& 0x3fffffff;
2887 case BFD_RELOC_SPARC_11
:
2888 if (! in_signed_range (val
, 0x7ff))
2889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2890 _("relocation overflow"));
2891 insn
|= val
& 0x7ff;
2894 case BFD_RELOC_SPARC_10
:
2895 if (! in_signed_range (val
, 0x3ff))
2896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2897 _("relocation overflow"));
2898 insn
|= val
& 0x3ff;
2901 case BFD_RELOC_SPARC_7
:
2902 if (! in_bitfield_range (val
, 0x7f))
2903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2904 _("relocation overflow"));
2908 case BFD_RELOC_SPARC_6
:
2909 if (! in_bitfield_range (val
, 0x3f))
2910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2911 _("relocation overflow"));
2915 case BFD_RELOC_SPARC_5
:
2916 if (! in_bitfield_range (val
, 0x1f))
2917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2918 _("relocation overflow"));
2922 case BFD_RELOC_SPARC_WDISP16
:
2923 /* FIXME: simplify */
2924 if (((val
> 0) && (val
& ~0x3fffc))
2925 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2927 _("relocation overflow"));
2928 /* FIXME: The +1 deserves a comment. */
2929 val
= (val
>> 2) + 1;
2930 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2933 case BFD_RELOC_SPARC_WDISP19
:
2934 /* FIXME: simplify */
2935 if (((val
> 0) && (val
& ~0x1ffffc))
2936 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2938 _("relocation overflow"));
2939 /* FIXME: The +1 deserves a comment. */
2940 val
= (val
>> 2) + 1;
2941 insn
|= val
& 0x7ffff;
2944 case BFD_RELOC_SPARC_HH22
:
2945 val
= BSR (val
, 32);
2946 /* intentional fallthrough */
2948 case BFD_RELOC_SPARC_LM22
:
2949 case BFD_RELOC_HI22
:
2950 if (!fixP
->fx_addsy
)
2952 insn
|= (val
>> 10) & 0x3fffff;
2956 /* FIXME: Need comment explaining why we do this. */
2961 case BFD_RELOC_SPARC22
:
2962 if (val
& ~0x003fffff)
2963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2964 _("relocation overflow"));
2965 insn
|= (val
& 0x3fffff);
2968 case BFD_RELOC_SPARC_HM10
:
2969 val
= BSR (val
, 32);
2970 /* intentional fallthrough */
2972 case BFD_RELOC_LO10
:
2973 if (!fixP
->fx_addsy
)
2975 insn
|= val
& 0x3ff;
2979 /* FIXME: Need comment explaining why we do this. */
2984 case BFD_RELOC_SPARC13
:
2985 if (! in_signed_range (val
, 0x1fff))
2986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2987 _("relocation overflow"));
2988 insn
|= val
& 0x1fff;
2991 case BFD_RELOC_SPARC_WDISP22
:
2992 val
= (val
>> 2) + 1;
2994 case BFD_RELOC_SPARC_BASE22
:
2995 insn
|= val
& 0x3fffff;
2998 case BFD_RELOC_SPARC_H44
:
2999 if (!fixP
->fx_addsy
)
3003 insn
|= tval
& 0x3fffff;
3007 case BFD_RELOC_SPARC_M44
:
3008 if (!fixP
->fx_addsy
)
3009 insn
|= (val
>> 12) & 0x3ff;
3012 case BFD_RELOC_SPARC_L44
:
3013 if (!fixP
->fx_addsy
)
3014 insn
|= val
& 0xfff;
3017 case BFD_RELOC_SPARC_HIX22
:
3018 if (!fixP
->fx_addsy
)
3020 val
^= ~ (offsetT
) 0;
3021 insn
|= (val
>> 10) & 0x3fffff;
3025 case BFD_RELOC_SPARC_LOX10
:
3026 if (!fixP
->fx_addsy
)
3027 insn
|= 0x1c00 | (val
& 0x3ff);
3030 case BFD_RELOC_NONE
:
3032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3033 _("bad or unhandled relocation type: 0x%02x"),
3038 if (INSN_BIG_ENDIAN
)
3039 bfd_putb32 (insn
, (unsigned char *) buf
);
3041 bfd_putl32 (insn
, (unsigned char *) buf
);
3044 /* Are we finished with this relocation now? */
3045 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3051 /* Translate internal representation of relocation info to BFD target
3054 tc_gen_reloc (section
, fixp
)
3059 bfd_reloc_code_real_type code
;
3061 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3063 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3064 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3065 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3067 switch (fixp
->fx_r_type
)
3071 case BFD_RELOC_HI22
:
3072 case BFD_RELOC_LO10
:
3073 case BFD_RELOC_32_PCREL_S2
:
3074 case BFD_RELOC_SPARC13
:
3075 case BFD_RELOC_SPARC22
:
3076 case BFD_RELOC_SPARC_BASE13
:
3077 case BFD_RELOC_SPARC_WDISP16
:
3078 case BFD_RELOC_SPARC_WDISP19
:
3079 case BFD_RELOC_SPARC_WDISP22
:
3081 case BFD_RELOC_SPARC_5
:
3082 case BFD_RELOC_SPARC_6
:
3083 case BFD_RELOC_SPARC_7
:
3084 case BFD_RELOC_SPARC_10
:
3085 case BFD_RELOC_SPARC_11
:
3086 case BFD_RELOC_SPARC_HH22
:
3087 case BFD_RELOC_SPARC_HM10
:
3088 case BFD_RELOC_SPARC_LM22
:
3089 case BFD_RELOC_SPARC_PC_HH22
:
3090 case BFD_RELOC_SPARC_PC_HM10
:
3091 case BFD_RELOC_SPARC_PC_LM22
:
3092 case BFD_RELOC_SPARC_H44
:
3093 case BFD_RELOC_SPARC_M44
:
3094 case BFD_RELOC_SPARC_L44
:
3095 case BFD_RELOC_SPARC_HIX22
:
3096 case BFD_RELOC_SPARC_LOX10
:
3097 case BFD_RELOC_SPARC_REV32
:
3098 case BFD_RELOC_VTABLE_ENTRY
:
3099 case BFD_RELOC_VTABLE_INHERIT
:
3100 code
= fixp
->fx_r_type
;
3107 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3108 /* If we are generating PIC code, we need to generate a different
3112 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3114 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3121 case BFD_RELOC_32_PCREL_S2
:
3122 if (! S_IS_DEFINED (fixp
->fx_addsy
)
3123 || S_IS_COMMON (fixp
->fx_addsy
)
3124 || S_IS_EXTERNAL (fixp
->fx_addsy
)
3125 || S_IS_WEAK (fixp
->fx_addsy
))
3126 code
= BFD_RELOC_SPARC_WPLT30
;
3128 case BFD_RELOC_HI22
:
3129 if (fixp
->fx_addsy
!= NULL
3130 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3131 code
= BFD_RELOC_SPARC_PC22
;
3133 code
= BFD_RELOC_SPARC_GOT22
;
3135 case BFD_RELOC_LO10
:
3136 if (fixp
->fx_addsy
!= NULL
3137 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3138 code
= BFD_RELOC_SPARC_PC10
;
3140 code
= BFD_RELOC_SPARC_GOT10
;
3142 case BFD_RELOC_SPARC13
:
3143 code
= BFD_RELOC_SPARC_GOT13
;
3149 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3151 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3152 if (reloc
->howto
== 0)
3154 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3155 _("internal error: can't export reloc type %d (`%s')"),
3156 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3160 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3163 if (reloc
->howto
->pc_relative
== 0
3164 || code
== BFD_RELOC_SPARC_PC10
3165 || code
== BFD_RELOC_SPARC_PC22
)
3166 reloc
->addend
= fixp
->fx_addnumber
;
3167 else if (sparc_pic_code
3168 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3169 && fixp
->fx_addsy
!= NULL
3170 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3171 || S_IS_WEAK (fixp
->fx_addsy
))
3172 && S_IS_DEFINED (fixp
->fx_addsy
)
3173 && ! S_IS_COMMON (fixp
->fx_addsy
))
3174 reloc
->addend
= fixp
->fx_addnumber
;
3176 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3178 #else /* elf or coff */
3180 if (reloc
->howto
->pc_relative
== 0
3181 || code
== BFD_RELOC_SPARC_PC10
3182 || code
== BFD_RELOC_SPARC_PC22
)
3183 reloc
->addend
= fixp
->fx_addnumber
;
3184 else if (symbol_section_p (fixp
->fx_addsy
))
3185 reloc
->addend
= (section
->vma
3186 + fixp
->fx_addnumber
3187 + md_pcrel_from (fixp
));
3189 reloc
->addend
= fixp
->fx_offset
;
3195 /* We have no need to default values of symbols. */
3199 md_undefined_symbol (name
)
3203 } /* md_undefined_symbol() */
3205 /* Round up a section size to the appropriate boundary. */
3207 md_section_align (segment
, size
)
3212 /* This is not right for ELF; a.out wants it, and COFF will force
3213 the alignment anyways. */
3214 valueT align
= ((valueT
) 1
3215 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3217 /* turn alignment value into a mask */
3219 newsize
= (size
+ align
) & ~align
;
3226 /* Exactly what point is a PC-relative offset relative TO?
3227 On the sparc, they're relative to the address of the offset, plus
3228 its size. This gets us to the following instruction.
3229 (??? Is this right? FIXME-SOON) */
3231 md_pcrel_from (fixP
)
3236 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3237 if (! sparc_pic_code
3238 || fixP
->fx_addsy
== NULL
3239 || symbol_section_p (fixP
->fx_addsy
))
3240 ret
+= fixP
->fx_size
;
3244 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3256 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3259 return (value
== 1) ? shift
: -1;
3263 * sort of like s_lcomm
3267 static int max_alignment
= 15;
3282 name
= input_line_pointer
;
3283 c
= get_symbol_end ();
3284 p
= input_line_pointer
;
3288 if (*input_line_pointer
!= ',')
3290 as_bad (_("Expected comma after name"));
3291 ignore_rest_of_line ();
3295 ++input_line_pointer
;
3297 if ((size
= get_absolute_expression ()) < 0)
3299 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3300 ignore_rest_of_line ();
3305 symbolP
= symbol_find_or_make (name
);
3308 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3309 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3311 as_bad (_("bad .reserve segment -- expected BSS segment"));
3315 if (input_line_pointer
[2] == '.')
3316 input_line_pointer
+= 7;
3318 input_line_pointer
+= 6;
3321 if (*input_line_pointer
== ',')
3323 ++input_line_pointer
;
3326 if (*input_line_pointer
== '\n')
3328 as_bad (_("missing alignment"));
3329 ignore_rest_of_line ();
3333 align
= (int) get_absolute_expression ();
3336 if (align
> max_alignment
)
3338 align
= max_alignment
;
3339 as_warn (_("alignment too large; assuming %d"), align
);
3345 as_bad (_("negative alignment"));
3346 ignore_rest_of_line ();
3352 temp
= log2 (align
);
3355 as_bad (_("alignment not a power of 2"));
3356 ignore_rest_of_line ();
3363 record_alignment (bss_section
, align
);
3368 if (!S_IS_DEFINED (symbolP
)
3370 && S_GET_OTHER (symbolP
) == 0
3371 && S_GET_DESC (symbolP
) == 0
3378 segT current_seg
= now_seg
;
3379 subsegT current_subseg
= now_subseg
;
3381 subseg_set (bss_section
, 1); /* switch to bss */
3384 frag_align (align
, 0, 0); /* do alignment */
3386 /* detach from old frag */
3387 if (S_GET_SEGMENT(symbolP
) == bss_section
)
3388 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3390 symbol_set_frag (symbolP
, frag_now
);
3391 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
3392 (offsetT
) size
, (char *)0);
3395 S_SET_SEGMENT (symbolP
, bss_section
);
3397 subseg_set (current_seg
, current_subseg
);
3400 S_SET_SIZE (symbolP
, size
);
3406 as_warn("Ignoring attempt to re-define symbol %s",
3407 S_GET_NAME (symbolP
));
3408 } /* if not redefining */
3410 demand_empty_rest_of_line ();
3423 name
= input_line_pointer
;
3424 c
= get_symbol_end ();
3425 /* just after name is now '\0' */
3426 p
= input_line_pointer
;
3429 if (*input_line_pointer
!= ',')
3431 as_bad (_("Expected comma after symbol-name"));
3432 ignore_rest_of_line ();
3435 input_line_pointer
++; /* skip ',' */
3436 if ((temp
= get_absolute_expression ()) < 0)
3438 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3439 ignore_rest_of_line ();
3444 symbolP
= symbol_find_or_make (name
);
3446 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3448 as_bad (_("Ignoring attempt to re-define symbol"));
3449 ignore_rest_of_line ();
3452 if (S_GET_VALUE (symbolP
) != 0)
3454 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3456 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3457 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3463 S_SET_VALUE (symbolP
, (valueT
) size
);
3464 S_SET_EXTERNAL (symbolP
);
3467 know (symbolP
->sy_frag
== &zero_address_frag
);
3468 if (*input_line_pointer
!= ',')
3470 as_bad (_("Expected comma after common length"));
3471 ignore_rest_of_line ();
3474 input_line_pointer
++;
3476 if (*input_line_pointer
!= '"')
3478 temp
= get_absolute_expression ();
3481 if (temp
> max_alignment
)
3483 temp
= max_alignment
;
3484 as_warn (_("alignment too large; assuming %d"), temp
);
3490 as_bad (_("negative alignment"));
3491 ignore_rest_of_line ();
3496 if (symbol_get_obj (symbolP
)->local
)
3504 old_subsec
= now_subseg
;
3509 align
= log2 (temp
);
3513 as_bad (_("alignment not a power of 2"));
3514 ignore_rest_of_line ();
3518 record_alignment (bss_section
, align
);
3519 subseg_set (bss_section
, 0);
3521 frag_align (align
, 0, 0);
3522 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3523 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3524 symbol_set_frag (symbolP
, frag_now
);
3525 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3526 (offsetT
) size
, (char *) 0);
3528 S_SET_SEGMENT (symbolP
, bss_section
);
3529 S_CLEAR_EXTERNAL (symbolP
);
3530 S_SET_SIZE (symbolP
, size
);
3531 subseg_set (old_sec
, old_subsec
);
3534 #endif /* OBJ_ELF */
3537 S_SET_VALUE (symbolP
, (valueT
) size
);
3539 S_SET_ALIGN (symbolP
, temp
);
3540 S_SET_SIZE (symbolP
, size
);
3542 S_SET_EXTERNAL (symbolP
);
3543 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3548 input_line_pointer
++;
3549 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3550 if (*input_line_pointer
== '.')
3551 input_line_pointer
++;
3552 /* @@ Some say data, some say bss. */
3553 if (strncmp (input_line_pointer
, "bss\"", 4)
3554 && strncmp (input_line_pointer
, "data\"", 5))
3556 while (*--input_line_pointer
!= '"')
3558 input_line_pointer
--;
3559 goto bad_common_segment
;
3561 while (*input_line_pointer
++ != '"')
3563 goto allocate_common
;
3566 #ifdef BFD_ASSEMBLER
3567 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3570 demand_empty_rest_of_line ();
3575 p
= input_line_pointer
;
3576 while (*p
&& *p
!= '\n')
3580 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3582 input_line_pointer
= p
;
3583 ignore_rest_of_line ();
3588 /* Handle the .empty pseudo-op. This supresses the warnings about
3589 invalid delay slot usage. */
3595 /* The easy way to implement is to just forget about the last
3605 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3607 input_line_pointer
+= 6;
3611 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3613 input_line_pointer
+= 6;
3617 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3619 input_line_pointer
+= 7;
3623 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3625 input_line_pointer
+= 5;
3626 /* We only support 2 segments -- text and data -- for now, so
3627 things in the "bss segment" will have to go into data for now.
3628 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3629 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3632 as_bad (_("Unknown segment type"));
3633 demand_empty_rest_of_line ();
3639 subseg_set (data_section
, 1);
3640 demand_empty_rest_of_line ();
3647 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3649 ++input_line_pointer
;
3651 ++input_line_pointer
;
3654 /* This static variable is set by s_uacons to tell sparc_cons_align
3655 that the expession does not need to be aligned. */
3657 static int sparc_no_align_cons
= 0;
3659 /* This handles the unaligned space allocation pseudo-ops, such as
3660 .uaword. .uaword is just like .word, but the value does not need
3667 /* Tell sparc_cons_align not to align this value. */
3668 sparc_no_align_cons
= 1;
3672 /* This handles the native word allocation pseudo-op .nword.
3673 For sparc_arch_size 32 it is equivalent to .word, for
3674 sparc_arch_size 64 it is equivalent to .xword. */
3680 cons (sparc_arch_size
== 32 ? 4 : 8);
3683 /* If the --enforce-aligned-data option is used, we require .word,
3684 et. al., to be aligned correctly. We do it by setting up an
3685 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3686 no unexpected alignment was introduced.
3688 The SunOS and Solaris native assemblers enforce aligned data by
3689 default. We don't want to do that, because gcc can deliberately
3690 generate misaligned data if the packed attribute is used. Instead,
3691 we permit misaligned data by default, and permit the user to set an
3692 option to check for it. */
3695 sparc_cons_align (nbytes
)
3701 /* Only do this if we are enforcing aligned data. */
3702 if (! enforce_aligned_data
)
3705 if (sparc_no_align_cons
)
3707 /* This is an unaligned pseudo-op. */
3708 sparc_no_align_cons
= 0;
3712 nalign
= log2 (nbytes
);
3716 assert (nalign
> 0);
3718 if (now_seg
== absolute_section
)
3720 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3721 as_bad (_("misaligned data"));
3725 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3726 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3728 record_alignment (now_seg
, nalign
);
3731 /* This is where we do the unexpected alignment check.
3732 This is called from HANDLE_ALIGN in tc-sparc.h. */
3735 sparc_handle_align (fragp
)
3738 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
3739 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3740 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
3741 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
3743 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
3748 && !((long)(fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
3750 unsigned *p
= (unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
);
3753 for (i
= 0; i
< count
; i
+= 4, p
++)
3754 if (INSN_BIG_ENDIAN
)
3755 number_to_chars_bigendian ((char *)p
, 0x01000000, 4); /* emit nops */
3757 number_to_chars_littleendian ((char *)p
, 0x10000000, 4);
3759 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
3761 char *waddr
= &fragp
->fr_literal
[fragp
->fr_fix
];
3762 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
3763 if (INSN_BIG_ENDIAN
)
3764 number_to_chars_bigendian (waddr
, wval
, 4);
3766 number_to_chars_littleendian (waddr
, wval
, 4);
3768 fragp
->fr_var
= count
;
3774 /* Some special processing for a Sparc ELF file. */
3777 sparc_elf_final_processing ()
3779 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3780 sort of BFD interface for this. */
3781 if (sparc_arch_size
== 64)
3783 switch (sparc_memory_model
)
3786 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
3789 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
3795 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
3796 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
3797 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
3798 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
3802 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3803 reloc for a cons. We could use the definition there, except that
3804 we want to handle little endian relocs specially. */
3807 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
3810 unsigned int nbytes
;
3813 bfd_reloc_code_real_type r
;
3815 r
= (nbytes
== 1 ? BFD_RELOC_8
:
3816 (nbytes
== 2 ? BFD_RELOC_16
:
3817 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
3819 if (target_little_endian_data
&& nbytes
== 4
3820 && now_seg
->flags
& SEC_ALLOC
)
3821 r
= BFD_RELOC_SPARC_REV32
;
3822 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
3827 elf32_sparc_force_relocation (fixp
)
3830 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3831 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)