1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
27 #include "elf/sparc.h"
28 #include "dwarf2dbg.h"
30 /* Some ancient Sun C compilers would not take such hex constants as
31 unsigned, and would end up sign-extending them to form an offsetT,
32 so use these constants instead. */
33 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
34 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
36 static int sparc_ip (char *, const struct sparc_opcode
**);
37 static int parse_sparc_asi (char **, const sparc_asi
**);
38 static int parse_keyword_arg (int (*) (const char *), char **, int *);
39 static int parse_const_expr_arg (char **, int *);
40 static int get_expression (char *);
42 /* Default architecture. */
43 /* ??? The default value should be V8, but sparclite support was added
44 by making it the default. GCC now passes -Asparclite, so maybe sometime in
45 the future we can set this to V8. */
47 #define DEFAULT_ARCH "sparclite"
49 static const char *default_arch
= DEFAULT_ARCH
;
51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
53 static int default_init_p
;
55 /* Current architecture. We don't bump up unless necessary. */
56 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
58 /* The maximum architecture level we can bump up to.
59 In a 32 bit environment, don't allow bumping up to v9 by default.
60 The native assembler works this way. The user is required to pass
61 an explicit argument before we'll create v9 object files. However, if
62 we don't see any v9 insns, a v8plus object file is not created. */
63 static enum sparc_opcode_arch_val max_architecture
;
65 /* Either 32 or 64, selects file format. */
66 static int sparc_arch_size
;
67 /* Initial (default) value, recorded separately in case a user option
68 changes the value before md_show_usage is called. */
69 static int default_arch_size
;
71 /* The currently selected v9 memory model. Currently only used for
73 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
76 /* Bitmask of instruction types seen so far, used to populate the
77 GNU attributes section with hwcap information. */
78 static bfd_uint64_t hwcap_seen
;
81 static bfd_uint64_t hwcap_allowed
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if the assembler should generate error if an undeclared
91 g[23] register has been used in -64. */
92 static int no_undeclared_regs
;
94 /* Non-zero if the assembler should generate a warning if an
95 unpredictable DCTI (delayed control transfer instruction) couple is
97 static int dcti_couples_detect
;
99 /* Non-zero if we should try to relax jumps and calls. */
100 static int sparc_relax
;
102 /* Non-zero if we are generating PIC code. */
105 /* Non-zero if we should give an error when misaligned data is seen. */
106 static int enforce_aligned_data
;
108 extern int target_big_endian
;
110 static int target_little_endian_data
;
112 /* Symbols for global registers on v9. */
113 static symbolS
*globals
[8];
115 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
116 int sparc_cie_data_alignment
;
118 /* V9 and 86x have big and little endian data, but instructions are always big
119 endian. The sparclet has bi-endian support but both data and insns have
120 the same endianness. Global `target_big_endian' is used for data.
121 The following macro is used for instructions. */
122 #ifndef INSN_BIG_ENDIAN
123 #define INSN_BIG_ENDIAN (target_big_endian \
124 || default_arch_type == sparc86x \
125 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
128 /* Handle of the OPCODE hash table. */
129 static htab_t op_hash
;
131 static void s_data1 (void);
132 static void s_seg (int);
133 static void s_proc (int);
134 static void s_reserve (int);
135 static void s_common (int);
136 static void s_empty (int);
137 static void s_uacons (int);
138 static void s_ncons (int);
139 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
159 /* These are specific to sparc/svr4. */
160 {"2byte", s_uacons
, 2},
161 {"4byte", s_uacons
, 4},
162 {"8byte", s_uacons
, 8},
163 {"register", s_register
, 0},
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful. */
169 const char comment_chars
[] = "!"; /* JF removed '|' from
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output. */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that comments started like this one will always
179 work if '/' isn't otherwise defined. */
180 const char line_comment_chars
[] = "#";
182 const char line_separator_chars
[] = ";";
184 /* Chars that can be used to separate mant from exp in floating point
186 const char EXP_CHARS
[] = "eE";
188 /* Chars that mean this number is a floating point constant.
191 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
193 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
194 changed in read.c. Ideally it shouldn't have to know about it at all,
195 but nothing is ideal around here. */
197 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
202 unsigned long opcode
;
203 struct nlist
*nlistp
;
207 bfd_reloc_code_real_type reloc
;
210 struct sparc_it the_insn
, set_insn
;
212 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
220 v8plusa
, v9
, v9a
, v9b
, v9_64
};
222 static struct sparc_arch
{
224 const char *opcode_arch
;
225 enum sparc_arch_types arch_type
;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size
;
229 /* Allowable arg to -A? */
231 /* Extra hardware capabilities allowed. These are added to the
232 hardware capabilities associated with the opcode
236 } sparc_arch_table
[] = {
237 { "v6", "v6", v6
, 0, 1, 0, 0 },
238 { "v7", "v7", v7
, 0, 1, 0, 0 },
239 { "v8", "v8", v8
, 32, 1, 0, 0 },
240 { "v8a", "v8", v8
, 32, 1, 0, 0 },
241 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
242 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
243 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
244 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
245 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
246 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
247 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
249 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
250 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
251 { "sparc6", "m8", v9
, 0, 1, 0, 0 },
253 { "leon", "leon", leon
, 32, 1, 0, 0 },
254 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
255 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
256 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
258 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
259 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
260 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
261 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
262 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
263 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
264 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
265 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
266 { "v8plusm8", "m8", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v9", "v9", v9
, 0, 1, 0, 0 },
269 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
270 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
271 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
272 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
273 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
274 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
275 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
276 { "v9m8", "m8", v9
, 0, 1, 0, 0 },
278 /* This exists to allow configure.tgt to pass one
279 value to specify both the default machine and default word size. */
280 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
281 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
284 /* Variant of default_arch */
285 static enum sparc_arch_types default_arch_type
;
287 static struct sparc_arch
*
288 lookup_arch (const char *name
)
290 struct sparc_arch
*sa
;
292 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
293 if (strcmp (sa
->name
, name
) == 0)
295 if (sa
->name
== NULL
)
300 /* Initialize the default opcode arch and word size from the default
301 architecture name. */
304 init_default_arch (void)
306 struct sparc_arch
*sa
= lookup_arch (default_arch
);
309 || sa
->default_arch_size
== 0)
310 as_fatal (_("Invalid default architecture, broken assembler."));
312 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
313 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
314 as_fatal (_("Bad opcode table, broken assembler."));
315 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
317 default_arch_type
= sa
->arch_type
;
320 /* Called by TARGET_MACH. */
325 /* We don't get a chance to initialize anything before we're called,
326 so handle that now. */
327 if (! default_init_p
)
328 init_default_arch ();
330 return sparc_arch_size
== 64 ? bfd_mach_sparc_v9
: bfd_mach_sparc
;
333 /* Called by TARGET_FORMAT. */
336 sparc_target_format (void)
338 /* We don't get a chance to initialize anything before we're called,
339 so handle that now. */
340 if (! default_init_p
)
341 init_default_arch ();
344 return "elf32-sparc-vxworks";
347 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
351 * Invocation line includes a switch not recognized by the base assembler.
352 * See if it's a processor-specific option. These are:
355 * Warn on architecture bumps. See also -A.
357 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
358 * Standard 32 bit architectures.
360 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
361 * This used to only mean 64 bits, but properly specifying it
362 * complicated gcc's ASM_SPECs, so now opcode selection is
363 * specified orthogonally to word size (except when specifying
364 * the default, but that is an internal implementation detail).
365 * -Av8plus, -Av8plusa, -Av8plusb
366 * Same as -Av9{,a,b}.
367 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
368 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
370 * -xarch=v9, -xarch=v9a, -xarch=v9b
371 * Same as -Av9{,a,b} -64, for compatibility with Sun's
374 * Select the architecture and possibly the file format.
375 * Instructions or features not supported by the selected
376 * architecture cause fatal errors.
378 * The default is to start at v6, and bump the architecture up
379 * whenever an instruction is seen at a higher level. In 32 bit
380 * environments, v9 is not bumped up to, the user must pass
383 * If -bump is specified, a warning is printing when bumping to
386 * If an architecture is specified, all instructions must match
387 * that architecture. Any higher level instructions are flagged
388 * as errors. Note that in the 32 bit environment specifying
389 * -Av8plus does not automatically create a v8plus object file, a
390 * v9 insn must be seen.
392 * If both an architecture and -bump are specified, the
393 * architecture starts at the specified level, but bumps are
394 * warnings. Note that we can't set `current_architecture' to
395 * the requested level in this case: in the 32 bit environment,
396 * we still must avoid creating v8plus object files unless v9
400 * Bumping between incompatible architectures is always an
401 * error. For example, from sparclite to v9.
404 const char *md_shortopts
= "A:K:VQ:sq";
405 struct option md_longopts
[] = {
406 #define OPTION_BUMP (OPTION_MD_BASE)
407 {"bump", no_argument
, NULL
, OPTION_BUMP
},
408 #define OPTION_SPARC (OPTION_MD_BASE + 1)
409 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
410 #define OPTION_XARCH (OPTION_MD_BASE + 2)
411 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
412 #define OPTION_32 (OPTION_MD_BASE + 3)
413 {"32", no_argument
, NULL
, OPTION_32
},
414 #define OPTION_64 (OPTION_MD_BASE + 4)
415 {"64", no_argument
, NULL
, OPTION_64
},
416 #define OPTION_TSO (OPTION_MD_BASE + 5)
417 {"TSO", no_argument
, NULL
, OPTION_TSO
},
418 #define OPTION_PSO (OPTION_MD_BASE + 6)
419 {"PSO", no_argument
, NULL
, OPTION_PSO
},
420 #define OPTION_RMO (OPTION_MD_BASE + 7)
421 {"RMO", no_argument
, NULL
, OPTION_RMO
},
422 #ifdef SPARC_BIENDIAN
423 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
424 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
425 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
426 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
428 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
429 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
430 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
431 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
432 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
433 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
434 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
435 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
436 #define OPTION_RELAX (OPTION_MD_BASE + 14)
437 {"relax", no_argument
, NULL
, OPTION_RELAX
},
438 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
439 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
440 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
441 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
442 {NULL
, no_argument
, NULL
, 0}
445 size_t md_longopts_size
= sizeof (md_longopts
);
448 md_parse_option (int c
, const char *arg
)
450 /* We don't get a chance to initialize anything before we're called,
451 so handle that now. */
452 if (! default_init_p
)
453 init_default_arch ();
459 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
463 if (!strncmp (arg
, "v9", 2))
464 md_parse_option (OPTION_64
, NULL
);
467 if (!strncmp (arg
, "v8", 2)
468 || !strncmp (arg
, "v7", 2)
469 || !strncmp (arg
, "v6", 2)
470 || !strcmp (arg
, "sparclet")
471 || !strcmp (arg
, "sparclite")
472 || !strcmp (arg
, "sparc86x"))
473 md_parse_option (OPTION_32
, NULL
);
479 struct sparc_arch
*sa
;
480 enum sparc_opcode_arch_val opcode_arch
;
482 sa
= lookup_arch (arg
);
484 || ! sa
->user_option_p
)
486 if (c
== OPTION_XARCH
)
487 as_bad (_("invalid architecture -xarch=%s"), arg
);
489 as_bad (_("invalid architecture -A%s"), arg
);
493 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
494 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
495 as_fatal (_("Bad opcode table, broken assembler."));
497 if (!architecture_requested
498 || opcode_arch
> max_architecture
)
499 max_architecture
= opcode_arch
;
501 /* The allowed hardware capabilities are the implied by the
502 opcodes arch plus any extra capabilities defined in the GAS
506 | (((bfd_uint64_t
) sparc_opcode_archs
[opcode_arch
].hwcaps2
) << 32)
507 | (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32)
508 | sparc_opcode_archs
[opcode_arch
].hwcaps
509 | sa
->hwcap_allowed
);
510 architecture_requested
= 1;
515 /* Ignore -sparc, used by SunOS make default .s.o rule. */
518 case OPTION_ENFORCE_ALIGNED_DATA
:
519 enforce_aligned_data
= 1;
522 #ifdef SPARC_BIENDIAN
523 case OPTION_LITTLE_ENDIAN
:
524 target_big_endian
= 0;
525 if (default_arch_type
!= sparclet
)
526 as_fatal ("This target does not support -EL");
528 case OPTION_LITTLE_ENDIAN_DATA
:
529 target_little_endian_data
= 1;
530 target_big_endian
= 0;
531 if (default_arch_type
!= sparc86x
532 && default_arch_type
!= v9
)
533 as_fatal ("This target does not support --little-endian-data");
535 case OPTION_BIG_ENDIAN
:
536 target_big_endian
= 1;
543 const char **list
, **l
;
545 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
546 list
= bfd_target_list ();
547 for (l
= list
; *l
!= NULL
; l
++)
549 if (sparc_arch_size
== 32)
551 if (CONST_STRNEQ (*l
, "elf32-sparc"))
556 if (CONST_STRNEQ (*l
, "elf64-sparc"))
561 as_fatal (_("No compiled in support for %d bit object file format"),
565 if (sparc_arch_size
== 64
566 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
567 max_architecture
= SPARC_OPCODE_ARCH_V9
;
572 sparc_memory_model
= MM_TSO
;
576 sparc_memory_model
= MM_PSO
;
580 sparc_memory_model
= MM_RMO
;
588 /* Qy - do emit .comment
589 Qn - do not emit .comment. */
593 /* Use .stab instead of .stab.excl. */
597 /* quick -- Native assembler does fewer checks. */
601 if (strcmp (arg
, "PIC") != 0)
602 as_warn (_("Unrecognized option following -K"));
607 case OPTION_NO_UNDECLARED_REGS
:
608 no_undeclared_regs
= 1;
611 case OPTION_UNDECLARED_REGS
:
612 no_undeclared_regs
= 0;
619 case OPTION_NO_RELAX
:
623 case OPTION_DCTI_COUPLES_DETECT
:
624 dcti_couples_detect
= 1;
635 md_show_usage (FILE *stream
)
637 const struct sparc_arch
*arch
;
640 /* We don't get a chance to initialize anything before we're called,
641 so handle that now. */
642 if (! default_init_p
)
643 init_default_arch ();
645 fprintf (stream
, _("SPARC options:\n"));
647 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
649 if (!arch
->user_option_p
)
651 if (arch
!= &sparc_arch_table
[0])
652 fprintf (stream
, " | ");
653 if (column
+ strlen (arch
->name
) > 70)
656 fputc ('\n', stream
);
658 column
+= 5 + 2 + strlen (arch
->name
);
659 fprintf (stream
, "-A%s", arch
->name
);
661 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
663 if (!arch
->user_option_p
)
665 fprintf (stream
, " | ");
666 if (column
+ strlen (arch
->name
) > 65)
669 fputc ('\n', stream
);
671 column
+= 5 + 7 + strlen (arch
->name
);
672 fprintf (stream
, "-xarch=%s", arch
->name
);
674 fprintf (stream
, _("\n\
675 specify variant of SPARC architecture\n\
676 -bump warn when assembler switches architectures\n\
678 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
679 -relax relax jumps and branches (default)\n\
680 -no-relax avoid changing any jumps and branches\n"));
681 fprintf (stream
, _("\
682 -32 create 32 bit object file\n\
683 -64 create 64 bit object file\n"));
684 fprintf (stream
, _("\
685 [default is %d]\n"), default_arch_size
);
686 fprintf (stream
, _("\
687 -TSO use Total Store Ordering\n\
688 -PSO use Partial Store Ordering\n\
689 -RMO use Relaxed Memory Ordering\n"));
690 fprintf (stream
, _("\
691 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
692 fprintf (stream
, _("\
693 -KPIC generate PIC\n\
694 -V print assembler version number\n\
695 -undeclared-regs ignore application global register usage without\n\
696 appropriate .register directive (default)\n\
697 -no-undeclared-regs force error on application global register usage\n\
698 without appropriate .register directive\n\
699 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
703 #ifdef SPARC_BIENDIAN
704 fprintf (stream
, _("\
705 -EL generate code for a little endian machine\n\
706 -EB generate code for a big endian machine\n\
707 --little-endian-data generate code for a machine having big endian\n\
708 instructions and little endian data.\n"));
712 /* Native operand size opcode translation. */
718 } native_op_table
[] =
720 {"ldn", "ld", "ldx"},
721 {"ldna", "lda", "ldxa"},
722 {"stn", "st", "stx"},
723 {"stna", "sta", "stxa"},
724 {"slln", "sll", "sllx"},
725 {"srln", "srl", "srlx"},
726 {"sran", "sra", "srax"},
727 {"casn", "cas", "casx"},
728 {"casna", "casa", "casxa"},
729 {"clrn", "clr", "clrx"},
733 /* sparc64 privileged and hyperprivileged registers. */
735 struct priv_reg_entry
741 struct priv_reg_entry priv_reg_table
[] =
762 {NULL
, -1}, /* End marker. */
765 struct priv_reg_entry hpriv_reg_table
[] =
775 {"hstick_offset", 28},
776 {"hstick_enable", 29},
778 {NULL
, -1}, /* End marker. */
781 /* v9a or later specific ancillary state registers. */
783 struct priv_reg_entry v9a_asr_table
[] =
786 {"sys_tick_cmpr", 25},
790 {"softint_clear", 21},
801 {"clear_softint", 21},
802 {NULL
, -1}, /* End marker. */
806 cmp_reg_entry (const void *parg
, const void *qarg
)
808 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
809 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
811 if (p
->name
== q
->name
)
813 else if (p
->name
== NULL
)
815 else if (q
->name
== NULL
)
818 return strcmp (q
->name
, p
->name
);
821 /* sparc %-pseudo-operations. */
824 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
825 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
827 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
828 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
830 instruction. (Generally they can appear
831 anywhere an immediate operand is
835 /* The name as it appears in assembler. */
837 /* The reloc this pseudo-op translates to. */
838 bfd_reloc_code_real_type reloc
;
839 /* Flags. See F_POP_* above. */
843 struct pop_entry pop_table
[] =
845 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
846 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
847 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
848 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
849 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
850 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
851 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
852 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
853 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
854 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
855 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
856 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
857 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
858 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
859 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
860 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
861 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
862 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
863 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
864 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
865 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
866 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
867 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
868 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
869 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
870 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
871 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
872 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
873 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
874 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
875 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
876 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
877 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
878 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
879 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
880 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
881 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
884 /* Table of %-names that can appear in a sparc assembly program. This
885 table is initialized in md_begin and contains entries for each
886 privileged/hyperprivileged/alternate register and %-pseudo-op. */
899 enum perc_entry_type type
;
900 /* Name of the %-entity. */
904 /* Value. Either a pop or a reg depending on type.*/
907 struct pop_entry
*pop
;
908 struct priv_reg_entry
*reg
;
912 #define NUM_PERC_ENTRIES \
913 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
914 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
915 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
916 + ARRAY_SIZE (pop_table) \
919 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
922 cmp_perc_entry (const void *parg
, const void *qarg
)
924 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
925 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
927 if (p
->name
== q
->name
)
929 else if (p
->name
== NULL
)
931 else if (q
->name
== NULL
)
934 return strcmp (q
->name
, p
->name
);
937 /* This function is called once, at assembler startup time. It should
938 set up all the tables, etc. that the MD part of the assembler will
947 /* We don't get a chance to initialize anything before md_parse_option
948 is called, and it may not be called, so handle default initialization
949 now if not already done. */
950 if (! default_init_p
)
951 init_default_arch ();
953 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
954 op_hash
= str_htab_create ();
956 while (i
< (unsigned int) sparc_num_opcodes
)
958 const char *name
= sparc_opcodes
[i
].name
;
959 if (str_hash_insert (op_hash
, name
, &sparc_opcodes
[i
], 0) != NULL
)
961 as_bad (_("duplicate %s"), name
);
966 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
968 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
969 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
974 while (i
< (unsigned int) sparc_num_opcodes
975 && !strcmp (sparc_opcodes
[i
].name
, name
));
978 for (i
= 0; native_op_table
[i
].name
; i
++)
980 const struct sparc_opcode
*insn
;
981 const char *name
= ((sparc_arch_size
== 32)
982 ? native_op_table
[i
].name32
983 : native_op_table
[i
].name64
);
984 insn
= (struct sparc_opcode
*) str_hash_find (op_hash
, name
);
987 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
988 name
, native_op_table
[i
].name
);
991 else if (str_hash_insert (op_hash
, native_op_table
[i
].name
, insn
, 0))
993 as_bad (_("duplicate %s"), native_op_table
[i
].name
);
999 as_fatal (_("Broken assembler. No assembly attempted."));
1001 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1002 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1003 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1004 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1005 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1006 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1008 /* If -bump, record the architecture level at which we start issuing
1009 warnings. The behaviour is different depending upon whether an
1010 architecture was explicitly specified. If it wasn't, we issue warnings
1011 for all upwards bumps. If it was, we don't start issuing warnings until
1012 we need to bump beyond the requested architecture or when we bump between
1013 conflicting architectures. */
1016 && architecture_requested
)
1018 /* `max_architecture' records the requested architecture.
1019 Issue warnings if we go above it. */
1020 warn_after_architecture
= max_architecture
;
1023 /* Find the highest architecture level that doesn't conflict with
1024 the requested one. */
1027 || !architecture_requested
)
1029 enum sparc_opcode_arch_val current_max_architecture
1032 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1033 max_architecture
> warn_after_architecture
;
1035 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1036 current_max_architecture
))
1040 /* Prepare the tables of %-pseudo-ops. */
1042 struct priv_reg_entry
*reg_tables
[]
1043 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1044 struct priv_reg_entry
**reg_table
;
1047 /* Add registers. */
1048 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1050 struct priv_reg_entry
*reg
;
1051 for (reg
= *reg_table
; reg
->name
; reg
++)
1053 struct perc_entry
*p
= &perc_table
[entry
++];
1054 p
->type
= perc_entry_reg
;
1055 p
->name
= reg
->name
;
1056 p
->len
= strlen (reg
->name
);
1061 /* Add %-pseudo-ops. */
1062 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1064 struct perc_entry
*p
= &perc_table
[entry
++];
1065 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1066 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1067 p
->name
= pop_table
[i
].name
;
1068 p
->len
= strlen (pop_table
[i
].name
);
1069 p
->pop
= &pop_table
[i
];
1072 /* Last entry is the sentinel. */
1073 perc_table
[entry
].type
= perc_entry_none
;
1075 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1076 sizeof (perc_table
[0]), cmp_perc_entry
);
1081 /* Called after all assembly has been done. */
1088 int hwcaps
, hwcaps2
;
1091 if (sparc_arch_size
== 64)
1092 switch (current_architecture
)
1094 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1095 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1096 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1097 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1098 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1099 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1100 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1101 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v9m8
; break;
1102 default: mach
= bfd_mach_sparc_v9
; break;
1105 switch (current_architecture
)
1107 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1108 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1109 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1110 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1111 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1112 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1113 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1114 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1115 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1116 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v8plusm8
; break;
1117 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1118 be but for now it is (since that's the way it's always been
1120 default: mach
= bfd_mach_sparc
; break;
1122 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1125 hwcaps
= hwcap_seen
& U0xffffffff
;
1126 hwcaps2
= hwcap_seen
>> 32;
1129 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1131 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1135 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1138 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1142 /* Sign-extend the value from the architecture word size, so that
1143 0xffffffff is always considered -1 on sparc32. */
1144 if (sparc_arch_size
== 32)
1146 bfd_vma sign
= (bfd_vma
) 1 << 31;
1147 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1156 /* Return non-zero if VAL is in the range 0 to MAX. */
1159 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1166 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1167 (e.g. -15 to +31). */
1170 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1176 if (val
< ~(max
>> 1))
1182 sparc_ffs (unsigned int mask
)
1189 for (i
= 0; (mask
& 1) == 0; ++i
)
1194 /* Implement big shift right. */
1196 BSR (bfd_vma val
, int amount
)
1198 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1199 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1200 return val
>> amount
;
1203 /* For communication between sparc_ip and get_expression. */
1204 static char *expr_end
;
1206 /* Values for `special_case'.
1207 Instructions that require weird handling because they're longer than
1209 #define SPECIAL_CASE_NONE 0
1210 #define SPECIAL_CASE_SET 1
1211 #define SPECIAL_CASE_SETSW 2
1212 #define SPECIAL_CASE_SETX 3
1213 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1214 #define SPECIAL_CASE_FDIV 4
1216 /* Bit masks of various insns. */
1217 #define NOP_INSN 0x01000000
1218 #define OR_INSN 0x80100000
1219 #define XOR_INSN 0x80180000
1220 #define FMOVS_INSN 0x81A00020
1221 #define SETHI_INSN 0x01000000
1222 #define SLLX_INSN 0x81281000
1223 #define SRA_INSN 0x81380000
1225 /* The last instruction to be assembled. */
1226 static const struct sparc_opcode
*last_insn
;
1227 /* The assembled opcode of `last_insn'. */
1228 static unsigned long last_opcode
;
1230 /* Handle the set and setuw synthetic instructions. */
1233 synthetize_setuw (const struct sparc_opcode
*insn
)
1235 int need_hi22_p
= 0;
1236 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1238 if (the_insn
.exp
.X_op
== O_constant
)
1240 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1242 if (sizeof (offsetT
) > 4
1243 && (the_insn
.exp
.X_add_number
< 0
1244 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1245 as_warn (_("set: number not in 0..4294967295 range"));
1249 if (sizeof (offsetT
) > 4
1250 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1251 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1252 as_warn (_("set: number not in -2147483648..4294967295 range"));
1253 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1257 /* See if operand is absolute and small; skip sethi if so. */
1258 if (the_insn
.exp
.X_op
!= O_constant
1259 || the_insn
.exp
.X_add_number
>= (1 << 12)
1260 || the_insn
.exp
.X_add_number
< -(1 << 12))
1262 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1263 | ((the_insn
.exp
.X_add_number
>> 10)
1264 & (the_insn
.exp
.X_op
== O_constant
1266 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1267 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1268 output_insn (insn
, &the_insn
);
1272 /* See if operand has no low-order bits; skip OR if so. */
1273 if (the_insn
.exp
.X_op
!= O_constant
1274 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1277 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1279 | (the_insn
.exp
.X_add_number
1280 & (the_insn
.exp
.X_op
!= O_constant
1281 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1282 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1283 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1284 output_insn (insn
, &the_insn
);
1288 /* Handle the setsw synthetic instruction. */
1291 synthetize_setsw (const struct sparc_opcode
*insn
)
1295 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1297 if (the_insn
.exp
.X_op
!= O_constant
)
1299 synthetize_setuw (insn
);
1301 /* Need to sign extend it. */
1302 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1303 the_insn
.reloc
= BFD_RELOC_NONE
;
1304 output_insn (insn
, &the_insn
);
1308 if (sizeof (offsetT
) > 4
1309 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1310 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1311 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1313 low32
= the_insn
.exp
.X_add_number
;
1317 synthetize_setuw (insn
);
1323 the_insn
.reloc
= BFD_RELOC_NONE
;
1324 /* See if operand is absolute and small; skip sethi if so. */
1325 if (low32
< -(1 << 12))
1327 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1328 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1329 output_insn (insn
, &the_insn
);
1330 low32
= 0x1c00 | (low32
& 0x3ff);
1331 opc
= RS1 (rd
) | XOR_INSN
;
1334 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1335 | (low32
& 0x1fff));
1336 output_insn (insn
, &the_insn
);
1339 /* Handle the setx synthetic instruction. */
1342 synthetize_setx (const struct sparc_opcode
*insn
)
1344 int upper32
, lower32
;
1345 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1346 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1348 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1349 int need_xor10_p
= 0;
1351 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1352 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1353 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1356 upper_dstreg
= tmpreg
;
1357 /* The tmp reg should not be the dst reg. */
1358 if (tmpreg
== dstreg
)
1359 as_warn (_("setx: temporary register same as destination register"));
1361 /* ??? Obviously there are other optimizations we can do
1362 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1363 doing some of these. Later. If you do change things, try to
1364 change all of this to be table driven as well. */
1365 /* What to output depends on the number if it's constant.
1366 Compute that first, then output what we've decided upon. */
1367 if (the_insn
.exp
.X_op
!= O_constant
)
1369 if (sparc_arch_size
== 32)
1371 /* When arch size is 32, we want setx to be equivalent
1372 to setuw for anything but constants. */
1373 the_insn
.exp
.X_add_number
&= 0xffffffff;
1374 synthetize_setuw (insn
);
1377 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1383 /* Reset X_add_number, we've extracted it as upper32/lower32.
1384 Otherwise fixup_segment will complain about not being able to
1385 write an 8 byte number in a 4 byte field. */
1386 the_insn
.exp
.X_add_number
= 0;
1388 /* Only need hh22 if `or' insn can't handle constant. */
1389 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1392 /* Does bottom part (after sethi) have bits? */
1393 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1394 /* No hh22, but does upper32 still have bits we can't set
1396 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1399 /* If the lower half is all zero, we build the upper half directly
1400 into the dst reg. */
1402 /* Need lower half if number is zero or 0xffffffff00000000. */
1403 || (! need_hh22_p
&& ! need_hm10_p
))
1405 /* No need for sethi if `or' insn can handle constant. */
1406 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1407 /* Note that we can't use a negative constant in the `or'
1408 insn unless the upper 32 bits are all ones. */
1409 || (lower32
< 0 && upper32
!= -1)
1410 || (lower32
>= 0 && upper32
== -1))
1413 if (need_hi22_p
&& upper32
== -1)
1416 /* Does bottom part (after sethi) have bits? */
1417 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1419 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1420 /* Need `or' if we didn't set anything else. */
1421 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1425 /* Output directly to dst reg if lower 32 bits are all zero. */
1426 upper_dstreg
= dstreg
;
1429 if (!upper_dstreg
&& dstreg
)
1430 as_warn (_("setx: illegal temporary register g0"));
1434 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1435 | ((upper32
>> 10) & 0x3fffff));
1436 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1437 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1438 output_insn (insn
, &the_insn
);
1443 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1444 | (((need_xor10_p
? ~lower32
: lower32
)
1445 >> 10) & 0x3fffff));
1446 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1447 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1448 output_insn (insn
, &the_insn
);
1453 the_insn
.opcode
= (OR_INSN
1454 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1457 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1458 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1459 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1460 output_insn (insn
, &the_insn
);
1465 /* FIXME: One nice optimization to do here is to OR the low part
1466 with the highpart if hi22 isn't needed and the low part is
1468 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1471 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1472 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1473 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1474 output_insn (insn
, &the_insn
);
1477 /* If we needed to build the upper part, shift it into place. */
1478 if (need_hh22_p
|| need_hm10_p
)
1480 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1482 the_insn
.reloc
= BFD_RELOC_NONE
;
1483 output_insn (insn
, &the_insn
);
1486 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1489 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1490 | 0x1c00 | (lower32
& 0x3ff));
1491 the_insn
.reloc
= BFD_RELOC_NONE
;
1492 output_insn (insn
, &the_insn
);
1495 /* If we needed to build both upper and lower parts, OR them together. */
1496 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1498 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1500 the_insn
.reloc
= BFD_RELOC_NONE
;
1501 output_insn (insn
, &the_insn
);
1505 /* Main entry point to assemble one instruction. */
1508 md_assemble (char *str
)
1510 const struct sparc_opcode
*insn
;
1514 special_case
= sparc_ip (str
, &insn
);
1518 /* Certain instructions may not appear on delay slots. Check for
1519 these situations. */
1520 if (last_insn
!= NULL
1521 && (last_insn
->flags
& F_DELAYED
) != 0)
1523 /* Before SPARC V9 the effect of having a delayed branch
1524 instruction in the delay slot of a conditional delayed branch
1527 In SPARC V9 DCTI couples are well defined.
1529 However, starting with the UltraSPARC Architecture 2005, DCTI
1530 couples (of all kind) are deprecated and should not be used,
1531 as they may be slow or behave differently to what the
1532 programmer expects. */
1533 if (dcti_couples_detect
1534 && (insn
->flags
& F_DELAYED
) != 0
1535 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1536 && (last_insn
->flags
& F_CONDBR
) != 0)
1537 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1538 as_warn (_("unpredictable DCTI couple"));
1541 /* We warn about attempts to put a floating point branch in a
1542 delay slot, unless the delay slot has been annulled. */
1543 if ((insn
->flags
& F_FBR
) != 0
1544 /* ??? This test isn't completely accurate. We assume anything with
1545 F_{UNBR,CONDBR,FBR} set is annullable. */
1546 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1547 || (last_opcode
& ANNUL
) == 0))
1548 as_warn (_("FP branch in delay slot"));
1551 /* SPARC before v9 does not allow a floating point compare
1552 directly before a floating point branch. Insert a nop
1553 instruction if needed, with a warning. */
1554 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1555 && last_insn
!= NULL
1556 && (insn
->flags
& F_FBR
) != 0
1557 && (last_insn
->flags
& F_FLOAT
) != 0
1558 && (last_insn
->match
& OP3 (0x35)) == OP3 (0x35))
1560 struct sparc_it nop_insn
;
1562 nop_insn
.opcode
= NOP_INSN
;
1563 nop_insn
.reloc
= BFD_RELOC_NONE
;
1564 output_insn (insn
, &nop_insn
);
1565 as_warn (_("FP branch preceded by FP compare; NOP inserted"));
1568 switch (special_case
)
1570 case SPECIAL_CASE_NONE
:
1572 output_insn (insn
, &the_insn
);
1575 case SPECIAL_CASE_SETSW
:
1576 synthetize_setsw (insn
);
1579 case SPECIAL_CASE_SET
:
1580 synthetize_setuw (insn
);
1583 case SPECIAL_CASE_SETX
:
1584 synthetize_setx (insn
);
1587 case SPECIAL_CASE_FDIV
:
1589 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1591 output_insn (insn
, &the_insn
);
1593 /* According to information leaked from Sun, the "fdiv" instructions
1594 on early SPARC machines would produce incorrect results sometimes.
1595 The workaround is to add an fmovs of the destination register to
1596 itself just after the instruction. This was true on machines
1597 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1598 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1599 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1600 output_insn (insn
, &the_insn
);
1605 as_fatal (_("failed special case insn sanity check"));
1610 get_hwcap_name (bfd_uint64_t mask
)
1612 if (mask
& HWCAP_MUL32
)
1614 if (mask
& HWCAP_DIV32
)
1616 if (mask
& HWCAP_FSMULD
)
1618 if (mask
& HWCAP_V8PLUS
)
1620 if (mask
& HWCAP_POPC
)
1622 if (mask
& HWCAP_VIS
)
1624 if (mask
& HWCAP_VIS2
)
1626 if (mask
& HWCAP_ASI_BLK_INIT
)
1627 return "ASIBlkInit";
1628 if (mask
& HWCAP_FMAF
)
1630 if (mask
& HWCAP_VIS3
)
1632 if (mask
& HWCAP_HPC
)
1634 if (mask
& HWCAP_RANDOM
)
1636 if (mask
& HWCAP_TRANS
)
1638 if (mask
& HWCAP_FJFMAU
)
1640 if (mask
& HWCAP_IMA
)
1642 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1644 if (mask
& HWCAP_AES
)
1646 if (mask
& HWCAP_DES
)
1648 if (mask
& HWCAP_KASUMI
)
1650 if (mask
& HWCAP_CAMELLIA
)
1652 if (mask
& HWCAP_MD5
)
1654 if (mask
& HWCAP_SHA1
)
1656 if (mask
& HWCAP_SHA256
)
1658 if (mask
& HWCAP_SHA512
)
1660 if (mask
& HWCAP_MPMUL
)
1662 if (mask
& HWCAP_MONT
)
1664 if (mask
& HWCAP_PAUSE
)
1666 if (mask
& HWCAP_CBCOND
)
1668 if (mask
& HWCAP_CRC32C
)
1672 if (mask
& HWCAP2_FJATHPLUS
)
1674 if (mask
& HWCAP2_VIS3B
)
1676 if (mask
& HWCAP2_ADP
)
1678 if (mask
& HWCAP2_SPARC5
)
1680 if (mask
& HWCAP2_MWAIT
)
1682 if (mask
& HWCAP2_XMPMUL
)
1684 if (mask
& HWCAP2_XMONT
)
1686 if (mask
& HWCAP2_NSEC
)
1688 if (mask
& HWCAP2_SPARC6
)
1690 if (mask
& HWCAP2_ONADDSUB
)
1692 if (mask
& HWCAP2_ONMUL
)
1694 if (mask
& HWCAP2_ONDIV
)
1696 if (mask
& HWCAP2_DICTUNP
)
1698 if (mask
& HWCAP2_FPCMPSHL
)
1700 if (mask
& HWCAP2_RLE
)
1702 if (mask
& HWCAP2_SHA3
)
1708 /* Subroutine of md_assemble to do the actual parsing. */
1711 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1713 const char *error_message
= "";
1717 const struct sparc_opcode
*insn
;
1719 unsigned long opcode
;
1720 unsigned int mask
= 0;
1724 int special_case
= SPECIAL_CASE_NONE
;
1725 const sparc_asi
*sasi
= NULL
;
1732 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1749 as_bad (_("Unknown opcode: `%s'"), str
);
1751 return special_case
;
1753 insn
= (struct sparc_opcode
*) str_hash_find (op_hash
, str
);
1757 as_bad (_("Unknown opcode: `%s'"), str
);
1758 return special_case
;
1768 opcode
= insn
->match
;
1769 memset (&the_insn
, '\0', sizeof (the_insn
));
1770 the_insn
.reloc
= BFD_RELOC_NONE
;
1773 /* Build the opcode, checking as we go to make sure that the
1775 for (args
= insn
->args
;; ++args
)
1783 /* Parse a series of masks. */
1790 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1793 error_message
= _(": invalid membar mask name");
1799 if (*s
== '|' || *s
== '+')
1807 if (! parse_const_expr_arg (&s
, &kmask
))
1809 error_message
= _(": invalid membar mask expression");
1812 if (kmask
< 0 || kmask
> 127)
1814 error_message
= _(": invalid membar mask number");
1819 opcode
|= MEMBAR (kmask
);
1827 if (! parse_const_expr_arg (&s
, &smask
))
1829 error_message
= _(": invalid siam mode expression");
1832 if (smask
< 0 || smask
> 7)
1834 error_message
= _(": invalid siam mode number");
1845 /* Parse a prefetch function. */
1848 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1850 error_message
= _(": invalid prefetch function name");
1856 if (! parse_const_expr_arg (&s
, &fcn
))
1858 error_message
= _(": invalid prefetch function expression");
1861 if (fcn
< 0 || fcn
> 31)
1863 error_message
= _(": invalid prefetch function number");
1873 /* Parse a sparc64 privileged register. */
1876 struct priv_reg_entry
*p
;
1877 unsigned int len
= 9999999; /* Init to make gcc happy. */
1880 for (p
= priv_reg_table
; p
->name
; p
++)
1881 if (p
->name
[0] == s
[0])
1883 len
= strlen (p
->name
);
1884 if (strncmp (p
->name
, s
, len
) == 0)
1890 error_message
= _(": unrecognizable privileged register");
1894 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1896 error_message
= _(": unrecognizable privileged register");
1905 error_message
= _(": unrecognizable privileged register");
1911 /* Parse a sparc64 hyperprivileged register. */
1914 struct priv_reg_entry
*p
;
1915 unsigned int len
= 9999999; /* Init to make gcc happy. */
1918 for (p
= hpriv_reg_table
; p
->name
; p
++)
1919 if (p
->name
[0] == s
[0])
1921 len
= strlen (p
->name
);
1922 if (strncmp (p
->name
, s
, len
) == 0)
1928 error_message
= _(": unrecognizable hyperprivileged register");
1932 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1934 error_message
= _(": unrecognizable hyperprivileged register");
1943 error_message
= _(": unrecognizable hyperprivileged register");
1949 /* Parse a v9a or later ancillary state register. */
1952 struct priv_reg_entry
*p
;
1953 unsigned int len
= 9999999; /* Init to make gcc happy. */
1956 for (p
= v9a_asr_table
; p
->name
; p
++)
1957 if (p
->name
[0] == s
[0])
1959 len
= strlen (p
->name
);
1960 if (strncmp (p
->name
, s
, len
) == 0)
1966 error_message
= _(": unrecognizable ancillary state register");
1970 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1972 error_message
= _(": unrecognizable ancillary state register");
1981 error_message
= _(": unrecognizable ancillary state register");
1987 if (strncmp (s
, "%asr", 4) == 0)
1995 while (ISDIGIT (*s
))
1997 num
= num
* 10 + *s
- '0';
2001 /* We used to check here for the asr number to
2002 be between 16 and 31 in V9 and later, as
2003 mandated by the section C.1.1 "Register
2004 Names" in the SPARC spec. However, we
2005 decided to remove this restriction as a) it
2006 introduces problems when new V9 asr registers
2007 are introduced, b) the Solaris assembler
2008 doesn't implement this restriction and c) the
2009 restriction will go away in future revisions
2010 of the Oracle SPARC Architecture. */
2012 if (num
< 0 || 31 < num
)
2014 error_message
= _(": asr number must be between 0 and 31");
2018 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2023 error_message
= _(": expecting %asrN");
2030 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2034 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2040 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2045 if (s
[0] == '0' && s
[1] == 'x')
2048 while (ISXDIGIT (*s
))
2051 num
|= hex_value (*s
);
2057 while (ISDIGIT (*s
))
2059 num
= num
* 10 + *s
- '0';
2063 if (num
< 0 || num
> 31)
2065 error_message
= _(": crypto immediate must be between 0 and 31");
2069 opcode
|= RS3 (num
);
2074 error_message
= _(": expecting crypto immediate");
2079 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2080 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2081 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2083 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2084 /* These fields are unsigned, but for upward compatibility,
2085 allow negative values as well. */
2089 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2090 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2091 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2093 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2094 /* These fields are unsigned, but for upward compatibility,
2095 allow negative values as well. */
2099 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2104 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2109 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2114 if (*s
== 'p' && s
[1] == 'n')
2122 if (*s
== 'p' && s
[1] == 't')
2134 if ((strncmp (s
, "%icc", 4) == 0)
2135 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2147 if ((strncmp (s
, "%xcc", 4) == 0)
2148 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2160 if (strncmp (s
, "%fcc0", 5) == 0)
2172 if (strncmp (s
, "%fcc1", 5) == 0)
2184 if (strncmp (s
, "%fcc2", 5) == 0)
2196 if (strncmp (s
, "%fcc3", 5) == 0)
2204 if (strncmp (s
, "%pc", 3) == 0)
2212 if (strncmp (s
, "%tick", 5) == 0)
2219 case '\0': /* End of args. */
2220 if (s
[0] == ',' && s
[1] == '%')
2224 const struct perc_entry
*p
;
2226 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2227 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2228 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2230 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2233 if (s
[p
->len
+ 2] != '(')
2235 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2236 return special_case
;
2239 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2240 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2242 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2244 return special_case
;
2247 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2248 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2249 || the_insn
.exp
.X_add_number
!= 0
2250 || the_insn
.exp
.X_add_symbol
2251 != symbol_find_or_make ("__tls_get_addr")))
2253 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2255 return special_case
;
2258 the_insn
.reloc
= p
->pop
->reloc
;
2259 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2262 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2265 else if (*s1
== ')')
2274 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2275 return special_case
;
2279 (void) get_expression (s
);
2299 case '[': /* These must match exactly. */
2307 case '#': /* Must be at least one digit. */
2310 while (ISDIGIT (*s
))
2318 case 'C': /* Coprocessor state register. */
2319 if (strncmp (s
, "%csr", 4) == 0)
2326 case 'b': /* Next operand is a coprocessor register. */
2329 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2334 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2348 opcode
|= mask
<< 14;
2356 opcode
|= mask
<< 25;
2362 case 'r': /* next operand must be a register */
2372 case 'f': /* frame pointer */
2380 case 'g': /* global register */
2389 case 'i': /* in register */
2393 mask
= c
- '0' + 24;
2398 case 'l': /* local register */
2402 mask
= (c
- '0' + 16);
2407 case 'o': /* out register */
2411 mask
= (c
- '0' + 8);
2416 case 's': /* stack pointer */
2424 case 'r': /* any register */
2425 if (!ISDIGIT ((c
= *s
++)))
2442 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2458 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2459 && no_undeclared_regs
&& ! globals
[mask
])
2460 as_bad (_("detected global register use not covered by .register pseudo-op"));
2462 /* Got the register, now figure out where
2463 it goes in the opcode. */
2467 opcode
|= mask
<< 14;
2475 opcode
|= mask
<< 25;
2479 opcode
|= (mask
<< 25) | (mask
<< 14);
2483 opcode
|= (mask
<< 25) | (mask
<< 0);
2489 case 'e': /* next operand is a floating point register */
2512 && ((format
= *s
) == 'f'
2517 for (mask
= 0; ISDIGIT (*s
); ++s
)
2519 mask
= 10 * mask
+ (*s
- '0');
2520 } /* read the number */
2530 /* register must be even numbered */
2540 /* register must be multiple of 4 */
2549 /* register must be multiple of 8 */
2553 if (*args
== '\'' && mask
< 48)
2555 /* register must be higher or equal than %f48 */
2561 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2562 error_message
= _(": There are only 64 f registers; [0-63]");
2564 error_message
= _(": There are only 32 f registers; [0-31]");
2567 else if (mask
>= 32)
2569 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2571 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2574 = _(": There are only 32 single precision f registers; [0-31]");
2578 mask
-= 31; /* wrap high bit */
2582 error_message
= _(": There are only 32 f registers; [0-31]");
2590 } /* if not an 'f' register. */
2592 if (*args
== '}' && mask
!= RS2 (opcode
))
2595 = _(": Instruction requires frs2 and frsd must be the same register");
2605 opcode
|= RS1 (mask
);
2612 opcode
|= RS2 (mask
);
2616 opcode
|= RS2 (mask
& 0xe);
2621 opcode
|= RS3 (mask
);
2629 opcode
|= RD (mask
);
2638 if (strncmp (s
, "%fsr", 4) == 0)
2646 if (strncmp (s
, "%efsr", 5) == 0)
2653 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2654 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2657 case 'l': /* 22 bit PC relative immediate */
2658 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2662 case 'L': /* 30 bit immediate */
2663 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2668 case 'n': /* 22 bit immediate */
2669 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2672 case 'i': /* 13 bit immediate */
2673 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2683 const char *op_arg
= NULL
;
2684 static expressionS op_exp
;
2685 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2687 /* Check for %hi, etc. */
2690 const struct perc_entry
*p
;
2692 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2693 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2694 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2696 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2699 if (s
[p
->len
+ 1] != '(')
2701 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2702 return special_case
;
2706 the_insn
.reloc
= p
->pop
->reloc
;
2708 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2711 /* Note that if the get_expression() fails, we will still
2712 have created U entries in the symbol table for the
2713 'symbols' in the input string. Try not to create U
2714 symbols for registers, etc. */
2716 /* This stuff checks to see if the expression ends in
2717 +%reg. If it does, it removes the register from
2718 the expression, and re-sets 's' to point to the
2725 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2728 else if (*s1
== ')')
2737 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2738 return special_case
;
2742 (void) get_expression (s
);
2746 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2747 return special_case
;
2750 if (*s
== ',' || *s
== ']' || !*s
)
2752 if (*s
!= '+' && *s
!= '-')
2754 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2755 return special_case
;
2759 op_exp
= the_insn
.exp
;
2760 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2763 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2766 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2768 if (s1
[-2] == '%' && s1
[-3] == '+')
2770 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2772 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2779 if (op_arg
&& s1
== s
+ 1)
2780 the_insn
.exp
.X_op
= O_absent
;
2782 (void) get_expression (s
);
2794 (void) get_expression (s
);
2802 the_insn
.exp2
= the_insn
.exp
;
2803 the_insn
.exp
= op_exp
;
2804 if (the_insn
.exp2
.X_op
== O_absent
)
2805 the_insn
.exp2
.X_op
= O_illegal
;
2806 else if (the_insn
.exp
.X_op
== O_absent
)
2808 the_insn
.exp
= the_insn
.exp2
;
2809 the_insn
.exp2
.X_op
= O_illegal
;
2811 else if (the_insn
.exp
.X_op
== O_constant
)
2813 valueT val
= the_insn
.exp
.X_add_number
;
2814 switch (the_insn
.reloc
)
2819 case BFD_RELOC_SPARC_HH22
:
2820 val
= BSR (val
, 32);
2823 case BFD_RELOC_SPARC_LM22
:
2824 case BFD_RELOC_HI22
:
2825 val
= (val
>> 10) & 0x3fffff;
2828 case BFD_RELOC_SPARC_HM10
:
2829 val
= BSR (val
, 32);
2832 case BFD_RELOC_LO10
:
2836 case BFD_RELOC_SPARC_H34
:
2841 case BFD_RELOC_SPARC_H44
:
2846 case BFD_RELOC_SPARC_M44
:
2851 case BFD_RELOC_SPARC_L44
:
2855 case BFD_RELOC_SPARC_HIX22
:
2857 val
= (val
>> 10) & 0x3fffff;
2860 case BFD_RELOC_SPARC_LOX10
:
2861 val
= (val
& 0x3ff) | 0x1c00;
2864 the_insn
.exp
= the_insn
.exp2
;
2865 the_insn
.exp
.X_add_number
+= val
;
2866 the_insn
.exp2
.X_op
= O_illegal
;
2867 the_insn
.reloc
= old_reloc
;
2869 else if (the_insn
.exp2
.X_op
!= O_constant
)
2871 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2872 return special_case
;
2876 if (old_reloc
!= BFD_RELOC_SPARC13
2877 || the_insn
.reloc
!= BFD_RELOC_LO10
2878 || sparc_arch_size
!= 64
2881 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2882 return special_case
;
2884 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2888 /* Check for constants that don't require emitting a reloc. */
2889 if (the_insn
.exp
.X_op
== O_constant
2890 && the_insn
.exp
.X_add_symbol
== 0
2891 && the_insn
.exp
.X_op_symbol
== 0)
2893 /* For pc-relative call instructions, we reject
2894 constants to get better code. */
2896 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2897 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2899 error_message
= _(": PC-relative operand can't be a constant");
2903 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2904 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2906 error_message
= _(": TLS operand can't be a constant");
2910 /* Constants that won't fit are checked in md_apply_fix
2911 and bfd_install_relocation.
2912 ??? It would be preferable to install the constants
2913 into the insn here and save having to create a fixS
2914 for each one. There already exists code to handle
2915 all the various cases (e.g. in md_apply_fix and
2916 bfd_install_relocation) so duplicating all that code
2917 here isn't right. */
2919 /* This is a special case to handle cbcond instructions
2920 properly, which can need two relocations. The first
2921 one is for the 5-bit immediate field and the latter
2922 is going to be for the WDISP10 branch part. We
2923 handle the R_SPARC_5 immediate directly here so that
2924 we don't need to add support for multiple relocations
2925 in one instruction just yet. */
2926 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
2927 && ((insn
->match
& OP(0x3)) == 0))
2929 valueT val
= the_insn
.exp
.X_add_number
;
2931 the_insn
.reloc
= BFD_RELOC_NONE
;
2932 if (! in_bitfield_range (val
, 0x1f))
2934 error_message
= _(": Immediate value in cbcond is out of range.");
2937 opcode
|= val
& 0x1f;
2958 if (! parse_sparc_asi (&s
, &sasi
))
2960 error_message
= _(": invalid ASI name");
2967 if (! parse_const_expr_arg (&s
, &asi
))
2969 error_message
= _(": invalid ASI expression");
2972 if (asi
< 0 || asi
> 255)
2974 error_message
= _(": invalid ASI number");
2978 opcode
|= ASI (asi
);
2980 } /* Alternate space. */
2983 if (strncmp (s
, "%psr", 4) == 0)
2990 case 'q': /* Floating point queue. */
2991 if (strncmp (s
, "%fq", 3) == 0)
2998 case 'Q': /* Coprocessor queue. */
2999 if (strncmp (s
, "%cq", 3) == 0)
3007 if (strcmp (str
, "set") == 0
3008 || strcmp (str
, "setuw") == 0)
3010 special_case
= SPECIAL_CASE_SET
;
3013 else if (strcmp (str
, "setsw") == 0)
3015 special_case
= SPECIAL_CASE_SETSW
;
3018 else if (strcmp (str
, "setx") == 0)
3020 special_case
= SPECIAL_CASE_SETX
;
3023 else if (strncmp (str
, "fdiv", 4) == 0)
3025 special_case
= SPECIAL_CASE_FDIV
;
3031 if (strncmp (s
, "%asi", 4) != 0)
3037 if (strncmp (s
, "%fprs", 5) != 0)
3043 if (strncmp (s
, "%mcdper",7) != 0)
3049 if (strncmp (s
, "%entropy", 8) != 0)
3055 if (strncmp (s
, "%ccr", 4) != 0)
3061 if (strncmp (s
, "%tbr", 4) != 0)
3067 if (strncmp (s
, "%wim", 4) != 0)
3076 /* Parse a 2-bit immediate. */
3077 if (! parse_const_expr_arg (&s
, &imm2
))
3079 error_message
= _(": non-immdiate imm2 operand");
3082 if ((imm2
& ~0x3) != 0)
3084 error_message
= _(": imm2 immediate operand out of range (0-3)");
3088 opcode
|= ((imm2
& 0x2) << 3) | (imm2
& 0x1);
3094 char *push
= input_line_pointer
;
3097 input_line_pointer
= s
;
3099 if (e
.X_op
== O_constant
)
3101 int n
= e
.X_add_number
;
3102 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3103 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3105 opcode
|= e
.X_add_number
<< 5;
3108 as_bad (_("non-immediate OPF operand, ignored"));
3109 s
= input_line_pointer
;
3110 input_line_pointer
= push
;
3115 if (strncmp (s
, "%y", 2) != 0)
3123 /* Parse a sparclet cpreg. */
3125 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3127 error_message
= _(": invalid cpreg name");
3130 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3135 as_fatal (_("failed sanity check."));
3136 } /* switch on arg code. */
3138 /* Break out of for() loop. */
3140 } /* For each arg that we expect. */
3145 /* Args don't match. */
3146 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3147 && (insn
->name
== insn
[1].name
3148 || !strcmp (insn
->name
, insn
[1].name
)))
3156 as_bad (_("Illegal operands%s"), error_message
);
3157 return special_case
;
3162 /* We have a match. Now see if the architecture is OK. */
3163 /* String to use in case of architecture warning. */
3164 const char *msg_str
= str
;
3165 int needed_arch_mask
= insn
->architecture
;
3167 /* Include the ASI architecture needed as well */
3168 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3170 needed_arch_mask
= sasi
->architecture
;
3171 msg_str
= sasi
->name
;
3175 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3179 hwcap_seen
|= hwcaps
;
3184 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3185 if (! needed_arch_mask
)
3187 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3190 if (needed_arch_mask
3191 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3194 /* Can we bump up the architecture? */
3195 else if (needed_arch_mask
3196 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3198 enum sparc_opcode_arch_val needed_architecture
=
3199 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3200 & needed_arch_mask
);
3202 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3204 && needed_architecture
> warn_after_architecture
)
3206 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3207 sparc_opcode_archs
[current_architecture
].name
,
3208 sparc_opcode_archs
[needed_architecture
].name
,
3210 warn_after_architecture
= needed_architecture
;
3212 current_architecture
= needed_architecture
;
3216 | (((bfd_uint64_t
) sparc_opcode_archs
[current_architecture
].hwcaps2
) << 32)
3217 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3220 /* ??? This seems to be a bit fragile. What if the next entry in
3221 the opcode table is the one we want and it is supported?
3222 It is possible to arrange the table today so that this can't
3223 happen but what about tomorrow? */
3226 int arch
, printed_one_p
= 0;
3228 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3230 /* Create a list of the architectures that support the insn. */
3231 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3233 arch
= sparc_ffs (needed_arch_mask
);
3234 while ((1 << arch
) <= needed_arch_mask
)
3236 if ((1 << arch
) & needed_arch_mask
)
3240 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3247 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3248 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3250 sparc_opcode_archs
[max_architecture
].name
);
3251 return special_case
;
3254 /* Make sure the hwcaps used by the instruction are
3255 currently enabled. */
3256 if (hwcaps
& ~hwcap_allowed
)
3258 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3260 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3262 return special_case
;
3264 } /* If no match. */
3267 } /* Forever looking for a match. */
3269 the_insn
.opcode
= opcode
;
3270 return special_case
;
3274 skip_over_keyword (char *q
)
3276 for (q
= q
+ (*q
== '#' || *q
== '%');
3277 ISALNUM (*q
) || *q
== '_';
3284 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3286 const sparc_asi
*value
;
3289 p
= *input_pointer_p
;
3290 q
= skip_over_keyword(p
);
3293 value
= sparc_encode_asi (p
);
3298 *input_pointer_p
= q
;
3302 /* Parse an argument that can be expressed as a keyword.
3303 (eg: #StoreStore or %ccfr).
3304 The result is a boolean indicating success.
3305 If successful, INPUT_POINTER is updated. */
3308 parse_keyword_arg (int (*lookup_fn
) (const char *),
3309 char **input_pointerP
,
3315 p
= *input_pointerP
;
3316 q
= skip_over_keyword(p
);
3319 value
= (*lookup_fn
) (p
);
3324 *input_pointerP
= q
;
3328 /* Parse an argument that is a constant expression.
3329 The result is a boolean indicating success. */
3332 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3334 char *save
= input_line_pointer
;
3337 input_line_pointer
= *input_pointerP
;
3338 /* The next expression may be something other than a constant
3339 (say if we're not processing the right variant of the insn).
3340 Don't call expression unless we're sure it will succeed as it will
3341 signal an error (which we want to defer until later). */
3342 /* FIXME: It might be better to define md_operand and have it recognize
3343 things like %asi, etc. but continuing that route through to the end
3344 is a lot of work. */
3345 if (*input_line_pointer
== '%')
3347 input_line_pointer
= save
;
3351 *input_pointerP
= input_line_pointer
;
3352 input_line_pointer
= save
;
3353 if (exp
.X_op
!= O_constant
)
3355 *valueP
= exp
.X_add_number
;
3359 /* Subroutine of sparc_ip to parse an expression. */
3362 get_expression (char *str
)
3367 save_in
= input_line_pointer
;
3368 input_line_pointer
= str
;
3369 seg
= expression (&the_insn
.exp
);
3370 if (seg
!= absolute_section
3371 && seg
!= text_section
3372 && seg
!= data_section
3373 && seg
!= bss_section
3374 && seg
!= undefined_section
)
3376 the_insn
.error
= _("bad segment");
3377 expr_end
= input_line_pointer
;
3378 input_line_pointer
= save_in
;
3381 expr_end
= input_line_pointer
;
3382 input_line_pointer
= save_in
;
3386 /* Subroutine of md_assemble to output one insn. */
3389 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3391 char *toP
= frag_more (4);
3393 /* Put out the opcode. */
3394 if (INSN_BIG_ENDIAN
)
3395 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3397 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3399 /* Put out the symbol-dependent stuff. */
3400 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3402 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3403 (toP
- frag_now
->fr_literal
), /* Where. */
3408 /* Turn off overflow checking in fixup_segment. We'll do our
3409 own overflow checking in md_apply_fix. This is necessary because
3410 the insn size is 4 and fixup_segment will signal an overflow for
3411 large 8 byte quantities. */
3412 fixP
->fx_no_overflow
= 1;
3413 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3414 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3418 last_opcode
= theinsn
->opcode
;
3420 dwarf2_emit_insn (4);
3424 md_atof (int type
, char *litP
, int *sizeP
)
3426 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3429 /* Write a value out to the object file, using the appropriate
3433 md_number_to_chars (char *buf
, valueT val
, int n
)
3435 if (target_big_endian
)
3436 number_to_chars_bigendian (buf
, val
, n
);
3437 else if (target_little_endian_data
3438 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3439 /* Output debug words, which are not in allocated sections, as big
3441 number_to_chars_bigendian (buf
, val
, n
);
3442 else if (target_little_endian_data
|| ! target_big_endian
)
3443 number_to_chars_littleendian (buf
, val
, n
);
3446 /* Apply a fixS to the frags, now that we know the value it ought to
3450 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3452 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3453 offsetT val
= * (offsetT
*) valP
;
3456 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3458 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3460 /* SPARC ELF relocations don't use an addend in the data field. */
3461 if (fixP
->fx_addsy
!= NULL
)
3463 switch (fixP
->fx_r_type
)
3465 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3466 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3467 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3468 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3469 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3470 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3471 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3472 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3473 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3474 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3475 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3476 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3477 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3478 case BFD_RELOC_SPARC_TLS_IE_LD
:
3479 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3480 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3481 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3482 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3483 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3484 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3485 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3486 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3487 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3488 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3489 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3498 /* This is a hack. There should be a better way to
3499 handle this. Probably in terms of howto fields, once
3500 we can look at these fixups in terms of howtos. */
3501 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3502 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3504 /* If this is a data relocation, just output VAL. */
3506 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3508 md_number_to_chars (buf
, val
, 1);
3510 else if (fixP
->fx_r_type
== BFD_RELOC_16
3511 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3513 md_number_to_chars (buf
, val
, 2);
3515 else if (fixP
->fx_r_type
== BFD_RELOC_32
3516 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3517 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3519 md_number_to_chars (buf
, val
, 4);
3521 else if (fixP
->fx_r_type
== BFD_RELOC_64
3522 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3524 md_number_to_chars (buf
, val
, 8);
3526 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3527 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3534 /* It's a relocation against an instruction. */
3536 if (INSN_BIG_ENDIAN
)
3537 insn
= bfd_getb32 ((unsigned char *) buf
);
3539 insn
= bfd_getl32 ((unsigned char *) buf
);
3541 switch (fixP
->fx_r_type
)
3543 case BFD_RELOC_32_PCREL_S2
:
3545 /* FIXME: This increment-by-one deserves a comment of why it's
3547 if (! sparc_pic_code
3548 || fixP
->fx_addsy
== NULL
3549 || symbol_section_p (fixP
->fx_addsy
))
3552 insn
|= val
& 0x3fffffff;
3554 /* See if we have a delay slot. In that case we attempt to
3555 optimize several cases transforming CALL instructions
3556 into branches. But we can only do that if the relocation
3557 can be completely resolved here, i.e. if no undefined
3558 symbol is associated with it. */
3559 if (sparc_relax
&& fixP
->fx_addsy
== NULL
3560 && fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3564 #define XCC (2 << 20)
3565 #define COND(x) (((x)&0xf)<<25)
3566 #define CONDA COND(0x8)
3567 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3568 #define INSN_BA (F2(0,2) | CONDA)
3569 #define INSN_OR F3(2, 0x2, 0)
3570 #define INSN_NOP F2(0,4)
3574 /* If the instruction is a call with either:
3576 arithmetic instruction with rd == %o7
3577 where rs1 != %o7 and rs2 if it is register != %o7
3578 then we can optimize if the call destination is near
3579 by changing the call into a branch always. */
3580 if (INSN_BIG_ENDIAN
)
3581 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3583 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3584 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3586 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3587 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3588 || ((delay
& RD (~0)) != RD (O7
))))
3590 if ((delay
& RS1 (~0)) == RS1 (O7
)
3591 || ((delay
& F3I (~0)) == 0
3592 && (delay
& RS2 (~0)) == RS2 (O7
)))
3594 /* Ensure the branch will fit into simm22. */
3595 if ((val
& 0x3fe00000)
3596 && (val
& 0x3fe00000) != 0x3fe00000)
3598 /* Check if the arch is v9 and branch will fit
3600 if (((val
& 0x3c0000) == 0
3601 || (val
& 0x3c0000) == 0x3c0000)
3602 && (sparc_arch_size
== 64
3603 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3605 insn
= INSN_BPA
| (val
& 0x7ffff);
3608 insn
= INSN_BA
| (val
& 0x3fffff);
3609 if (fixP
->fx_where
>= 4
3610 && ((delay
& (0xffffffff ^ RS1 (~0)))
3611 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3616 if (INSN_BIG_ENDIAN
)
3617 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3619 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3620 if ((setter
& (0xffffffff ^ RD (~0)))
3621 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3628 If call foo was replaced with ba, replace
3629 or %rN, %g0, %o7 with nop. */
3630 reg
= (delay
& RS1 (~0)) >> 14;
3631 if (reg
!= ((setter
& RD (~0)) >> 25)
3632 || reg
== G0
|| reg
== O7
)
3635 if (INSN_BIG_ENDIAN
)
3636 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3638 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3643 case BFD_RELOC_SPARC_11
:
3644 if (! in_signed_range (val
, 0x7ff))
3645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3646 _("relocation overflow"));
3647 insn
|= val
& 0x7ff;
3650 case BFD_RELOC_SPARC_10
:
3651 if (! in_signed_range (val
, 0x3ff))
3652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3653 _("relocation overflow"));
3654 insn
|= val
& 0x3ff;
3657 case BFD_RELOC_SPARC_7
:
3658 if (! in_bitfield_range (val
, 0x7f))
3659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3660 _("relocation overflow"));
3664 case BFD_RELOC_SPARC_6
:
3665 if (! in_bitfield_range (val
, 0x3f))
3666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3667 _("relocation overflow"));
3671 case BFD_RELOC_SPARC_5
:
3672 if (! in_bitfield_range (val
, 0x1f))
3673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3674 _("relocation overflow"));
3678 case BFD_RELOC_SPARC_WDISP10
:
3681 || val
<= -(offsetT
) 0x808)
3682 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3683 _("relocation overflow"));
3684 /* FIXME: The +1 deserves a comment. */
3685 val
= (val
>> 2) + 1;
3686 insn
|= ((val
& 0x300) << 11)
3687 | ((val
& 0xff) << 5);
3690 case BFD_RELOC_SPARC_WDISP16
:
3693 || val
<= -(offsetT
) 0x20008)
3694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3695 _("relocation overflow"));
3696 /* FIXME: The +1 deserves a comment. */
3697 val
= (val
>> 2) + 1;
3698 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3701 case BFD_RELOC_SPARC_WDISP19
:
3704 || val
<= -(offsetT
) 0x100008)
3705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3706 _("relocation overflow"));
3707 /* FIXME: The +1 deserves a comment. */
3708 val
= (val
>> 2) + 1;
3709 insn
|= val
& 0x7ffff;
3712 case BFD_RELOC_SPARC_HH22
:
3713 val
= BSR (val
, 32);
3716 case BFD_RELOC_SPARC_LM22
:
3717 case BFD_RELOC_HI22
:
3718 if (!fixP
->fx_addsy
)
3719 insn
|= (val
>> 10) & 0x3fffff;
3721 /* FIXME: Need comment explaining why we do this. */
3725 case BFD_RELOC_SPARC22
:
3726 if (val
& ~0x003fffff)
3727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3728 _("relocation overflow"));
3729 insn
|= (val
& 0x3fffff);
3732 case BFD_RELOC_SPARC_HM10
:
3733 val
= BSR (val
, 32);
3736 case BFD_RELOC_LO10
:
3737 if (!fixP
->fx_addsy
)
3738 insn
|= val
& 0x3ff;
3740 /* FIXME: Need comment explaining why we do this. */
3744 case BFD_RELOC_SPARC_OLO10
:
3746 val
+= fixP
->tc_fix_data
;
3749 case BFD_RELOC_SPARC13
:
3750 if (! in_signed_range (val
, 0x1fff))
3751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3752 _("relocation overflow"));
3753 insn
|= val
& 0x1fff;
3756 case BFD_RELOC_SPARC_WDISP22
:
3757 val
= (val
>> 2) + 1;
3759 case BFD_RELOC_SPARC_BASE22
:
3760 insn
|= val
& 0x3fffff;
3763 case BFD_RELOC_SPARC_H34
:
3764 if (!fixP
->fx_addsy
)
3768 insn
|= tval
& 0x3fffff;
3772 case BFD_RELOC_SPARC_H44
:
3773 if (!fixP
->fx_addsy
)
3777 insn
|= tval
& 0x3fffff;
3781 case BFD_RELOC_SPARC_M44
:
3782 if (!fixP
->fx_addsy
)
3783 insn
|= (val
>> 12) & 0x3ff;
3786 case BFD_RELOC_SPARC_L44
:
3787 if (!fixP
->fx_addsy
)
3788 insn
|= val
& 0xfff;
3791 case BFD_RELOC_SPARC_HIX22
:
3792 if (!fixP
->fx_addsy
)
3794 val
^= ~(offsetT
) 0;
3795 insn
|= (val
>> 10) & 0x3fffff;
3799 case BFD_RELOC_SPARC_LOX10
:
3800 if (!fixP
->fx_addsy
)
3801 insn
|= 0x1c00 | (val
& 0x3ff);
3804 case BFD_RELOC_NONE
:
3806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3807 _("bad or unhandled relocation type: 0x%02x"),
3812 if (INSN_BIG_ENDIAN
)
3813 bfd_putb32 (insn
, (unsigned char *) buf
);
3815 bfd_putl32 (insn
, (unsigned char *) buf
);
3818 /* Are we finished with this relocation now? */
3819 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3823 /* Translate internal representation of relocation info to BFD target
3827 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3829 static arelent
*relocs
[3];
3831 bfd_reloc_code_real_type code
;
3833 relocs
[0] = reloc
= XNEW (arelent
);
3836 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3837 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3838 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3840 switch (fixp
->fx_r_type
)
3848 switch (fixp
->fx_size
)
3851 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3852 _("can not do %d byte pc-relative relocation"),
3854 code
= fixp
->fx_r_type
;
3857 case 1: code
= BFD_RELOC_8_PCREL
; break;
3858 case 2: code
= BFD_RELOC_16_PCREL
; break;
3859 case 4: code
= BFD_RELOC_32_PCREL
; break;
3861 case 8: code
= BFD_RELOC_64_PCREL
; break;
3865 fixp
->fx_addnumber
= fixp
->fx_offset
;
3869 case BFD_RELOC_HI22
:
3870 case BFD_RELOC_LO10
:
3871 case BFD_RELOC_32_PCREL_S2
:
3872 case BFD_RELOC_SPARC13
:
3873 case BFD_RELOC_SPARC22
:
3874 case BFD_RELOC_SPARC_PC22
:
3875 case BFD_RELOC_SPARC_PC10
:
3876 case BFD_RELOC_SPARC_BASE13
:
3877 case BFD_RELOC_SPARC_WDISP10
:
3878 case BFD_RELOC_SPARC_WDISP16
:
3879 case BFD_RELOC_SPARC_WDISP19
:
3880 case BFD_RELOC_SPARC_WDISP22
:
3881 case BFD_RELOC_SPARC_5
:
3882 case BFD_RELOC_SPARC_6
:
3883 case BFD_RELOC_SPARC_7
:
3884 case BFD_RELOC_SPARC_10
:
3885 case BFD_RELOC_SPARC_11
:
3886 case BFD_RELOC_SPARC_HH22
:
3887 case BFD_RELOC_SPARC_HM10
:
3888 case BFD_RELOC_SPARC_LM22
:
3889 case BFD_RELOC_SPARC_PC_HH22
:
3890 case BFD_RELOC_SPARC_PC_HM10
:
3891 case BFD_RELOC_SPARC_PC_LM22
:
3892 case BFD_RELOC_SPARC_H34
:
3893 case BFD_RELOC_SPARC_H44
:
3894 case BFD_RELOC_SPARC_M44
:
3895 case BFD_RELOC_SPARC_L44
:
3896 case BFD_RELOC_SPARC_HIX22
:
3897 case BFD_RELOC_SPARC_LOX10
:
3898 case BFD_RELOC_SPARC_REV32
:
3899 case BFD_RELOC_SPARC_OLO10
:
3900 case BFD_RELOC_SPARC_UA16
:
3901 case BFD_RELOC_SPARC_UA32
:
3902 case BFD_RELOC_SPARC_UA64
:
3903 case BFD_RELOC_8_PCREL
:
3904 case BFD_RELOC_16_PCREL
:
3905 case BFD_RELOC_32_PCREL
:
3906 case BFD_RELOC_64_PCREL
:
3907 case BFD_RELOC_SPARC_PLT32
:
3908 case BFD_RELOC_SPARC_PLT64
:
3909 case BFD_RELOC_VTABLE_ENTRY
:
3910 case BFD_RELOC_VTABLE_INHERIT
:
3911 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3912 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3913 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3914 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3915 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3916 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3917 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3918 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3919 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3920 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3921 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3922 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3923 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3924 case BFD_RELOC_SPARC_TLS_IE_LD
:
3925 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3926 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3927 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3928 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3929 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3930 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3931 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3932 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3933 case BFD_RELOC_SPARC_GOTDATA_OP
:
3934 code
= fixp
->fx_r_type
;
3941 /* If we are generating PIC code, we need to generate a different
3944 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3946 #define GOTT_BASE "__GOTT_BASE__"
3947 #define GOTT_INDEX "__GOTT_INDEX__"
3950 /* This code must be parallel to tc_fix_adjustable. */
3956 case BFD_RELOC_32_PCREL_S2
:
3957 if (generic_force_reloc (fixp
))
3958 code
= BFD_RELOC_SPARC_WPLT30
;
3960 case BFD_RELOC_HI22
:
3961 code
= BFD_RELOC_SPARC_GOT22
;
3962 if (fixp
->fx_addsy
!= NULL
)
3964 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3965 code
= BFD_RELOC_SPARC_PC22
;
3967 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3968 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3969 code
= BFD_RELOC_HI22
; /* Unchanged. */
3973 case BFD_RELOC_LO10
:
3974 code
= BFD_RELOC_SPARC_GOT10
;
3975 if (fixp
->fx_addsy
!= NULL
)
3977 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3978 code
= BFD_RELOC_SPARC_PC10
;
3980 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3981 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3982 code
= BFD_RELOC_LO10
; /* Unchanged. */
3986 case BFD_RELOC_SPARC13
:
3987 code
= BFD_RELOC_SPARC_GOT13
;
3994 /* Nothing is aligned in DWARF debugging sections. */
3995 if (bfd_section_flags (section
) & SEC_DEBUGGING
)
3998 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3999 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4000 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4004 if (code
== BFD_RELOC_SPARC_OLO10
)
4005 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4007 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4008 if (reloc
->howto
== 0)
4010 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4011 _("internal error: can't export reloc type %d (`%s')"),
4012 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4018 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4019 if (code
!= BFD_RELOC_32_PCREL_S2
4020 && code
!= BFD_RELOC_SPARC_WDISP22
4021 && code
!= BFD_RELOC_SPARC_WDISP16
4022 && code
!= BFD_RELOC_SPARC_WDISP19
4023 && code
!= BFD_RELOC_SPARC_WDISP10
4024 && code
!= BFD_RELOC_SPARC_WPLT30
4025 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4026 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4027 reloc
->addend
= fixp
->fx_addnumber
;
4028 else if (symbol_section_p (fixp
->fx_addsy
))
4029 reloc
->addend
= (section
->vma
4030 + fixp
->fx_addnumber
4031 + md_pcrel_from (fixp
));
4033 reloc
->addend
= fixp
->fx_offset
;
4035 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4036 on the same location. */
4037 if (code
== BFD_RELOC_SPARC_OLO10
)
4039 relocs
[1] = reloc
= XNEW (arelent
);
4042 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4044 = symbol_get_bfdsym (section_symbol (absolute_section
));
4045 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4046 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4047 reloc
->addend
= fixp
->tc_fix_data
;
4053 /* We have no need to default values of symbols. */
4056 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4061 /* Round up a section size to the appropriate boundary. */
4064 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4069 /* Exactly what point is a PC-relative offset relative TO?
4070 On the sparc, they're relative to the address of the offset, plus
4071 its size. This gets us to the following instruction.
4072 (??? Is this right? FIXME-SOON) */
4074 md_pcrel_from (fixS
*fixP
)
4078 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4079 if (! sparc_pic_code
4080 || fixP
->fx_addsy
== NULL
4081 || symbol_section_p (fixP
->fx_addsy
))
4082 ret
+= fixP
->fx_size
;
4086 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4097 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4100 return (value
== 1) ? shift
: -1;
4103 /* Sort of like s_lcomm. */
4106 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4116 c
= get_symbol_name (&name
);
4117 p
= input_line_pointer
;
4119 SKIP_WHITESPACE_AFTER_NAME ();
4121 if (*input_line_pointer
!= ',')
4123 as_bad (_("Expected comma after name"));
4124 ignore_rest_of_line ();
4128 ++input_line_pointer
;
4130 if ((size
= get_absolute_expression ()) < 0)
4132 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4133 ignore_rest_of_line ();
4138 symbolP
= symbol_find_or_make (name
);
4141 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4142 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4144 as_bad (_("bad .reserve segment -- expected BSS segment"));
4148 if (input_line_pointer
[2] == '.')
4149 input_line_pointer
+= 7;
4151 input_line_pointer
+= 6;
4154 if (*input_line_pointer
== ',')
4156 ++input_line_pointer
;
4159 if (*input_line_pointer
== '\n')
4161 as_bad (_("missing alignment"));
4162 ignore_rest_of_line ();
4166 align
= (int) get_absolute_expression ();
4170 as_bad (_("negative alignment"));
4171 ignore_rest_of_line ();
4177 temp
= mylog2 (align
);
4180 as_bad (_("alignment not a power of 2"));
4181 ignore_rest_of_line ();
4188 record_alignment (bss_section
, align
);
4193 if (!S_IS_DEFINED (symbolP
))
4198 segT current_seg
= now_seg
;
4199 subsegT current_subseg
= now_subseg
;
4201 /* Switch to bss. */
4202 subseg_set (bss_section
, 1);
4206 frag_align (align
, 0, 0);
4208 /* Detach from old frag. */
4209 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4210 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4212 symbol_set_frag (symbolP
, frag_now
);
4213 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4214 (offsetT
) size
, (char *) 0);
4217 S_SET_SEGMENT (symbolP
, bss_section
);
4219 subseg_set (current_seg
, current_subseg
);
4221 S_SET_SIZE (symbolP
, size
);
4226 as_warn (_("Ignoring attempt to re-define symbol %s"),
4227 S_GET_NAME (symbolP
));
4230 demand_empty_rest_of_line ();
4234 s_common (int ignore ATTRIBUTE_UNUSED
)
4242 c
= get_symbol_name (&name
);
4243 /* Just after name is now '\0'. */
4244 p
= input_line_pointer
;
4246 SKIP_WHITESPACE_AFTER_NAME ();
4247 if (*input_line_pointer
!= ',')
4249 as_bad (_("Expected comma after symbol-name"));
4250 ignore_rest_of_line ();
4255 input_line_pointer
++;
4257 if ((temp
= get_absolute_expression ()) < 0)
4259 as_bad (_(".COMMon length (%lu) out of range ignored"),
4260 (unsigned long) temp
);
4261 ignore_rest_of_line ();
4266 symbolP
= symbol_find_or_make (name
);
4268 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4270 as_bad (_("Ignoring attempt to re-define symbol"));
4271 ignore_rest_of_line ();
4274 if (S_GET_VALUE (symbolP
) != 0)
4276 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4278 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4279 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4282 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4283 if (*input_line_pointer
!= ',')
4285 as_bad (_("Expected comma after common length"));
4286 ignore_rest_of_line ();
4289 input_line_pointer
++;
4291 if (*input_line_pointer
!= '"')
4293 temp
= get_absolute_expression ();
4297 as_bad (_("negative alignment"));
4298 ignore_rest_of_line ();
4302 if (symbol_get_obj (symbolP
)->local
)
4309 old_subsec
= now_subseg
;
4314 align
= mylog2 (temp
);
4318 as_bad (_("alignment not a power of 2"));
4319 ignore_rest_of_line ();
4323 record_alignment (bss_section
, align
);
4324 subseg_set (bss_section
, 0);
4326 frag_align (align
, 0, 0);
4327 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4328 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4329 symbol_set_frag (symbolP
, frag_now
);
4330 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4331 (offsetT
) size
, (char *) 0);
4333 S_SET_SEGMENT (symbolP
, bss_section
);
4334 S_CLEAR_EXTERNAL (symbolP
);
4335 S_SET_SIZE (symbolP
, size
);
4336 subseg_set (old_sec
, old_subsec
);
4341 S_SET_VALUE (symbolP
, (valueT
) size
);
4342 S_SET_ALIGN (symbolP
, temp
);
4343 S_SET_SIZE (symbolP
, size
);
4344 S_SET_EXTERNAL (symbolP
);
4345 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4350 input_line_pointer
++;
4351 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4352 if (*input_line_pointer
== '.')
4353 input_line_pointer
++;
4354 /* @@ Some say data, some say bss. */
4355 if (strncmp (input_line_pointer
, "bss\"", 4)
4356 && strncmp (input_line_pointer
, "data\"", 5))
4358 while (*--input_line_pointer
!= '"')
4360 input_line_pointer
--;
4361 goto bad_common_segment
;
4363 while (*input_line_pointer
++ != '"')
4365 goto allocate_common
;
4368 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4370 demand_empty_rest_of_line ();
4375 p
= input_line_pointer
;
4376 while (*p
&& *p
!= '\n')
4380 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4382 input_line_pointer
= p
;
4383 ignore_rest_of_line ();
4388 /* Handle the .empty pseudo-op. This suppresses the warnings about
4389 invalid delay slot usage. */
4392 s_empty (int ignore ATTRIBUTE_UNUSED
)
4394 /* The easy way to implement is to just forget about the last
4400 s_seg (int ignore ATTRIBUTE_UNUSED
)
4403 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4405 input_line_pointer
+= 6;
4409 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4411 input_line_pointer
+= 6;
4415 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4417 input_line_pointer
+= 7;
4421 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4423 input_line_pointer
+= 5;
4424 /* We only support 2 segments -- text and data -- for now, so
4425 things in the "bss segment" will have to go into data for now.
4426 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4427 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4430 as_bad (_("Unknown segment type"));
4431 demand_empty_rest_of_line ();
4437 subseg_set (data_section
, 1);
4438 demand_empty_rest_of_line ();
4442 s_proc (int ignore ATTRIBUTE_UNUSED
)
4444 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4446 ++input_line_pointer
;
4448 ++input_line_pointer
;
4451 /* This static variable is set by s_uacons to tell sparc_cons_align
4452 that the expression does not need to be aligned. */
4454 static int sparc_no_align_cons
= 0;
4456 /* This handles the unaligned space allocation pseudo-ops, such as
4457 .uaword. .uaword is just like .word, but the value does not need
4461 s_uacons (int bytes
)
4463 /* Tell sparc_cons_align not to align this value. */
4464 sparc_no_align_cons
= 1;
4466 sparc_no_align_cons
= 0;
4469 /* This handles the native word allocation pseudo-op .nword.
4470 For sparc_arch_size 32 it is equivalent to .word, for
4471 sparc_arch_size 64 it is equivalent to .xword. */
4474 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4476 cons (sparc_arch_size
== 32 ? 4 : 8);
4479 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4483 .register %g[2367],{#scratch|symbolname|#ignore}
4487 s_register (int ignore ATTRIBUTE_UNUSED
)
4494 if (input_line_pointer
[0] != '%'
4495 || input_line_pointer
[1] != 'g'
4496 || ((input_line_pointer
[2] & ~1) != '2'
4497 && (input_line_pointer
[2] & ~1) != '6')
4498 || input_line_pointer
[3] != ',')
4499 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4500 reg
= input_line_pointer
[2] - '0';
4501 input_line_pointer
+= 4;
4503 if (*input_line_pointer
== '#')
4505 ++input_line_pointer
;
4506 c
= get_symbol_name (®name
);
4507 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4508 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4509 if (regname
[0] == 'i')
4512 regname
= (char *) "";
4516 c
= get_symbol_name (®name
);
4519 if (sparc_arch_size
== 64)
4523 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4524 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4525 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4526 as_bad (_("redefinition of global register"));
4530 if (regname
== NULL
)
4531 globals
[reg
] = (symbolS
*) 1;
4536 if (symbol_find (regname
))
4537 as_bad (_("Register symbol %s already defined."),
4540 globals
[reg
] = symbol_make (regname
);
4541 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4543 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4544 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4545 flags
|= BSF_GLOBAL
;
4546 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4547 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4548 S_SET_ALIGN (globals
[reg
], reg
);
4549 S_SET_SIZE (globals
[reg
], 0);
4550 /* Although we actually want undefined_section here,
4551 we have to use absolute_section, because otherwise
4552 generic as code will make it a COM section.
4553 We fix this up in sparc_adjust_symtab. */
4554 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4555 S_SET_OTHER (globals
[reg
], 0);
4556 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4557 ->internal_elf_sym
.st_info
=
4558 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4559 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4560 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4565 (void) restore_line_pointer (c
);
4567 demand_empty_rest_of_line ();
4570 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4571 symbols which need it. */
4574 sparc_adjust_symtab (void)
4578 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4580 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4581 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4584 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4585 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4588 S_SET_SEGMENT (sym
, undefined_section
);
4592 /* If the --enforce-aligned-data option is used, we require .word,
4593 et. al., to be aligned correctly. We do it by setting up an
4594 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4595 no unexpected alignment was introduced.
4597 The SunOS and Solaris native assemblers enforce aligned data by
4598 default. We don't want to do that, because gcc can deliberately
4599 generate misaligned data if the packed attribute is used. Instead,
4600 we permit misaligned data by default, and permit the user to set an
4601 option to check for it. */
4604 sparc_cons_align (int nbytes
)
4608 /* Only do this if we are enforcing aligned data. */
4609 if (! enforce_aligned_data
)
4612 /* Don't align if this is an unaligned pseudo-op. */
4613 if (sparc_no_align_cons
)
4616 nalign
= mylog2 (nbytes
);
4620 gas_assert (nalign
> 0);
4622 if (now_seg
== absolute_section
)
4624 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4625 as_bad (_("misaligned data"));
4629 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4630 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4632 record_alignment (now_seg
, nalign
);
4635 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4638 sparc_handle_align (fragS
*fragp
)
4643 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4645 switch (fragp
->fr_type
)
4649 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4653 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4664 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4666 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4667 if (INSN_BIG_ENDIAN
)
4668 number_to_chars_bigendian (p
, wval
, 4);
4670 number_to_chars_littleendian (p
, wval
, 4);
4676 if (INSN_BIG_ENDIAN
)
4677 number_to_chars_bigendian (p
, 0x01000000, 4);
4679 number_to_chars_littleendian (p
, 0x01000000, 4);
4681 fragp
->fr_fix
+= fix
;
4690 /* Some special processing for a Sparc ELF file. */
4693 sparc_elf_final_processing (void)
4695 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4696 sort of BFD interface for this. */
4697 if (sparc_arch_size
== 64)
4699 switch (sparc_memory_model
)
4702 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4705 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4711 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4712 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4713 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4714 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4715 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4716 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4720 sparc_cons (expressionS
*exp
, int size
)
4723 const char *sparc_cons_special_reloc
= NULL
;
4726 save
= input_line_pointer
;
4727 if (input_line_pointer
[0] == '%'
4728 && input_line_pointer
[1] == 'r'
4729 && input_line_pointer
[2] == '_')
4731 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4733 input_line_pointer
+= 7;
4734 sparc_cons_special_reloc
= "disp";
4736 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4738 if (size
!= 4 && size
!= 8)
4739 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4742 input_line_pointer
+= 6;
4743 sparc_cons_special_reloc
= "plt";
4746 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4748 if (size
!= 4 && size
!= 8)
4749 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4752 input_line_pointer
+= 13;
4753 sparc_cons_special_reloc
= "tls_dtpoff";
4756 if (sparc_cons_special_reloc
)
4763 if (*input_line_pointer
!= '8')
4765 input_line_pointer
--;
4768 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4772 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4776 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4786 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4787 sparc_cons_special_reloc
, size
* 8, size
);
4791 input_line_pointer
+= 2;
4792 if (*input_line_pointer
!= '(')
4794 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4795 sparc_cons_special_reloc
, size
* 8);
4802 input_line_pointer
= save
;
4803 sparc_cons_special_reloc
= NULL
;
4808 char *end
= ++input_line_pointer
;
4811 while (! is_end_of_line
[(c
= *end
)])
4825 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4826 sparc_cons_special_reloc
, size
* 8);
4832 if (input_line_pointer
!= end
)
4834 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4835 sparc_cons_special_reloc
, size
* 8);
4839 input_line_pointer
++;
4841 c
= *input_line_pointer
;
4842 if (! is_end_of_line
[c
] && c
!= ',')
4843 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4844 sparc_cons_special_reloc
, size
* 8);
4850 if (sparc_cons_special_reloc
== NULL
)
4852 return sparc_cons_special_reloc
;
4855 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4856 reloc for a cons. We could use the definition there, except that
4857 we want to handle little endian relocs specially. */
4860 cons_fix_new_sparc (fragS
*frag
,
4862 unsigned int nbytes
,
4864 const char *sparc_cons_special_reloc
)
4866 bfd_reloc_code_real_type r
;
4868 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4869 (nbytes
== 2 ? BFD_RELOC_16
:
4870 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4872 if (target_little_endian_data
4874 && now_seg
->flags
& SEC_ALLOC
)
4875 r
= BFD_RELOC_SPARC_REV32
;
4878 /* The Solaris linker does not allow R_SPARC_UA64
4879 relocations for 32-bit executables. */
4880 if (!target_little_endian_data
4881 && sparc_arch_size
!= 64
4882 && r
== BFD_RELOC_64
)
4886 if (sparc_cons_special_reloc
)
4888 if (*sparc_cons_special_reloc
== 'd')
4891 case 1: r
= BFD_RELOC_8_PCREL
; break;
4892 case 2: r
= BFD_RELOC_16_PCREL
; break;
4893 case 4: r
= BFD_RELOC_32_PCREL
; break;
4894 case 8: r
= BFD_RELOC_64_PCREL
; break;
4897 else if (*sparc_cons_special_reloc
== 'p')
4900 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4901 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4906 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4907 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4910 else if (sparc_no_align_cons
4911 || /* PR 20803 - relocs in the .eh_frame section
4912 need to support unaligned access. */
4913 strcmp (now_seg
->name
, ".eh_frame") == 0)
4917 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4918 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4920 /* The Solaris linker does not allow R_SPARC_UA64
4921 relocations for 32-bit executables. */
4922 case 8: r
= sparc_arch_size
== 64 ?
4923 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
4925 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4931 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4935 sparc_cfi_frame_initial_instructions (void)
4937 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4941 sparc_regname_to_dw2regnum (char *regname
)
4951 case 'g': i
= 0; break;
4952 case 'o': i
= 1; break;
4953 case 'l': i
= 2; break;
4954 case 'i': i
= 3; break;
4955 default: i
= -1; break;
4959 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4961 return i
* 8 + regname
[1] - '0';
4963 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4965 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4967 if (regname
[0] == 'f' || regname
[0] == 'r')
4969 unsigned int regnum
;
4971 regnum
= strtoul (regname
+ 1, &q
, 10);
4972 if (q
== NULL
|| *q
)
4974 if (regnum
>= ((regname
[0] == 'f'
4975 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4978 if (regname
[0] == 'f')
4981 if (regnum
>= 64 && (regnum
& 1))
4990 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4992 sparc_no_align_cons
= 1;
4993 emit_expr_with_reloc (exp
, nbytes
, "disp");
4994 sparc_no_align_cons
= 0;