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Add support for SPARC T4 crypto instructions.
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "subsegs.h"
26
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
29
30 #ifdef OBJ_ELF
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
33 #endif
34
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
45
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
50 #ifndef DEFAULT_ARCH
51 #define DEFAULT_ARCH "sparclite"
52 #endif
53 static char *default_arch = DEFAULT_ARCH;
54
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 have been set. */
57 static int default_init_p;
58
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
68
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
74
75 #ifdef OBJ_ELF
76 /* The currently selected v9 memory model. Currently only used for
77 ELF. */
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
79
80 #ifndef TE_SOLARIS
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
84 #endif
85 #endif
86
87 static int hwcap_allowed;
88
89 static int architecture_requested;
90 static int warn_on_bump;
91
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
95
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
99
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
102
103 /* Non-zero if we are generating PIC code. */
104 int sparc_pic_code;
105
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
108
109 extern int target_big_endian;
110
111 static int target_little_endian_data;
112
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
115
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
118
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127 #endif
128
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
131
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
140 #ifdef OBJ_ELF
141 static void s_register (int);
142 #endif
143
144 const pseudo_typeS md_pseudo_table[] =
145 {
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
150 {"half", cons, 2},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
153 {"proc", s_proc, 0},
154 {"reserve", s_reserve, 0},
155 {"seg", s_seg, 0},
156 {"skip", s_space, 0},
157 {"word", cons, 4},
158 {"xword", cons, 8},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
162 #ifdef OBJ_ELF
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
168 #endif
169 {NULL, 0, 0},
170 };
171
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
175 comment_chars. */
176
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
186
187 const char line_separator_chars[] = ";";
188
189 /* Chars that can be used to separate mant from exp in floating point
190 nums. */
191 const char EXP_CHARS[] = "eE";
192
193 /* Chars that mean this number is a floating point constant.
194 As in 0f12.456
195 or 0d1.2345e12 */
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
197
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
201
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
203
204 struct sparc_it
205 {
206 char *error;
207 unsigned long opcode;
208 struct nlist *nlistp;
209 expressionS exp;
210 expressionS exp2;
211 int pcrel;
212 bfd_reloc_code_real_type reloc;
213 };
214
215 struct sparc_it the_insn, set_insn;
216
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
218 \f
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
222 and file formats. */
223
224 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
226
227 static struct sparc_arch {
228 char *name;
229 char *opcode_arch;
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
235 int user_option_p;
236 int hwcap_allowed;
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
248 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
249 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
250 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
254 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
255 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
256 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
257 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
258 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
259 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
260 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
261 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
262 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
263 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
264 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
265 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
266 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
269 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
270 { NULL, NULL, v8, 0, 0, 0 }
271 };
272
273 /* Variant of default_arch */
274 static enum sparc_arch_types default_arch_type;
275
276 static struct sparc_arch *
277 lookup_arch (char *name)
278 {
279 struct sparc_arch *sa;
280
281 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
282 if (strcmp (sa->name, name) == 0)
283 break;
284 if (sa->name == NULL)
285 return NULL;
286 return sa;
287 }
288
289 /* Initialize the default opcode arch and word size from the default
290 architecture name. */
291
292 static void
293 init_default_arch (void)
294 {
295 struct sparc_arch *sa = lookup_arch (default_arch);
296
297 if (sa == NULL
298 || sa->default_arch_size == 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
300
301 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
302 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size = sparc_arch_size = sa->default_arch_size;
305 default_init_p = 1;
306 default_arch_type = sa->arch_type;
307 }
308
309 /* Called by TARGET_FORMAT. */
310
311 const char *
312 sparc_target_format (void)
313 {
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p)
317 init_default_arch ();
318
319 #ifdef OBJ_AOUT
320 #ifdef TE_NetBSD
321 return "a.out-sparc-netbsd";
322 #else
323 #ifdef TE_SPARCAOUT
324 if (target_big_endian)
325 return "a.out-sunos-big";
326 else if (default_arch_type == sparc86x && target_little_endian_data)
327 return "a.out-sunos-big";
328 else
329 return "a.out-sparc-little";
330 #else
331 return "a.out-sunos-big";
332 #endif
333 #endif
334 #endif
335
336 #ifdef OBJ_BOUT
337 return "b.out.big";
338 #endif
339
340 #ifdef OBJ_COFF
341 #ifdef TE_LYNX
342 return "coff-sparc-lynx";
343 #else
344 return "coff-sparc";
345 #endif
346 #endif
347
348 #ifdef TE_VXWORKS
349 return "elf32-sparc-vxworks";
350 #endif
351
352 #ifdef OBJ_ELF
353 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
354 #endif
355
356 abort ();
357 }
358 \f
359 /* md_parse_option
360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
362 *
363 * -bump
364 * Warn on architecture bumps. See also -A.
365 *
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
368 * -Av9, -Av9a, -Av9b
369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
378 * assembler.
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
381 * assembler.
382 *
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
386 *
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
390 * -Av8plus{,a,b}.
391 *
392 * If -bump is specified, a warning is printing when bumping to
393 * higher levels.
394 *
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
400 *
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
406 * insns are seen.
407 *
408 * Note:
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
411 */
412
413 #ifdef OBJ_ELF
414 const char *md_shortopts = "A:K:VQ:sq";
415 #else
416 #ifdef OBJ_AOUT
417 const char *md_shortopts = "A:k";
418 #else
419 const char *md_shortopts = "A:";
420 #endif
421 #endif
422 struct option md_longopts[] = {
423 #define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument, NULL, OPTION_BUMP},
425 #define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument, NULL, OPTION_SPARC},
427 #define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument, NULL, OPTION_XARCH},
429 #ifdef OBJ_ELF
430 #define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument, NULL, OPTION_32},
432 #define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument, NULL, OPTION_64},
434 #define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument, NULL, OPTION_TSO},
436 #define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument, NULL, OPTION_PSO},
438 #define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument, NULL, OPTION_RMO},
440 #endif
441 #ifdef SPARC_BIENDIAN
442 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
444 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
446 #endif
447 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
449 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
451 #ifdef OBJ_ELF
452 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
454 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
456 #endif
457 #define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument, NULL, OPTION_RELAX},
459 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
461 {NULL, no_argument, NULL, 0}
462 };
463
464 size_t md_longopts_size = sizeof (md_longopts);
465
466 int
467 md_parse_option (int c, char *arg)
468 {
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p)
472 init_default_arch ();
473
474 switch (c)
475 {
476 case OPTION_BUMP:
477 warn_on_bump = 1;
478 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
479 break;
480
481 case OPTION_XARCH:
482 #ifdef OBJ_ELF
483 if (strncmp (arg, "v9", 2) != 0)
484 md_parse_option (OPTION_32, NULL);
485 else
486 md_parse_option (OPTION_64, NULL);
487 #endif
488 /* Fall through. */
489
490 case 'A':
491 {
492 struct sparc_arch *sa;
493 enum sparc_opcode_arch_val opcode_arch;
494
495 sa = lookup_arch (arg);
496 if (sa == NULL
497 || ! sa->user_option_p)
498 {
499 if (c == OPTION_XARCH)
500 as_bad (_("invalid architecture -xarch=%s"), arg);
501 else
502 as_bad (_("invalid architecture -A%s"), arg);
503 return 0;
504 }
505
506 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
507 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
508 as_fatal (_("Bad opcode table, broken assembler."));
509
510 if (!architecture_requested
511 || opcode_arch > max_architecture)
512 max_architecture = opcode_arch;
513 hwcap_allowed |= sa->hwcap_allowed;
514 architecture_requested = 1;
515 }
516 break;
517
518 case OPTION_SPARC:
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
520 break;
521
522 case OPTION_ENFORCE_ALIGNED_DATA:
523 enforce_aligned_data = 1;
524 break;
525
526 #ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN:
528 target_big_endian = 0;
529 if (default_arch_type != sparclet)
530 as_fatal ("This target does not support -EL");
531 break;
532 case OPTION_LITTLE_ENDIAN_DATA:
533 target_little_endian_data = 1;
534 target_big_endian = 0;
535 if (default_arch_type != sparc86x
536 && default_arch_type != v9)
537 as_fatal ("This target does not support --little-endian-data");
538 break;
539 case OPTION_BIG_ENDIAN:
540 target_big_endian = 1;
541 break;
542 #endif
543
544 #ifdef OBJ_AOUT
545 case 'k':
546 sparc_pic_code = 1;
547 break;
548 #endif
549
550 #ifdef OBJ_ELF
551 case OPTION_32:
552 case OPTION_64:
553 {
554 const char **list, **l;
555
556 sparc_arch_size = c == OPTION_32 ? 32 : 64;
557 list = bfd_target_list ();
558 for (l = list; *l != NULL; l++)
559 {
560 if (sparc_arch_size == 32)
561 {
562 if (CONST_STRNEQ (*l, "elf32-sparc"))
563 break;
564 }
565 else
566 {
567 if (CONST_STRNEQ (*l, "elf64-sparc"))
568 break;
569 }
570 }
571 if (*l == NULL)
572 as_fatal (_("No compiled in support for %d bit object file format"),
573 sparc_arch_size);
574 free (list);
575
576 if (sparc_arch_size == 64
577 && max_architecture < SPARC_OPCODE_ARCH_V9)
578 max_architecture = SPARC_OPCODE_ARCH_V9;
579 }
580 break;
581
582 case OPTION_TSO:
583 sparc_memory_model = MM_TSO;
584 break;
585
586 case OPTION_PSO:
587 sparc_memory_model = MM_PSO;
588 break;
589
590 case OPTION_RMO:
591 sparc_memory_model = MM_RMO;
592 break;
593
594 case 'V':
595 print_version_id ();
596 break;
597
598 case 'Q':
599 /* Qy - do emit .comment
600 Qn - do not emit .comment. */
601 break;
602
603 case 's':
604 /* Use .stab instead of .stab.excl. */
605 break;
606
607 case 'q':
608 /* quick -- Native assembler does fewer checks. */
609 break;
610
611 case 'K':
612 if (strcmp (arg, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
614 else
615 sparc_pic_code = 1;
616 break;
617
618 case OPTION_NO_UNDECLARED_REGS:
619 no_undeclared_regs = 1;
620 break;
621
622 case OPTION_UNDECLARED_REGS:
623 no_undeclared_regs = 0;
624 break;
625 #endif
626
627 case OPTION_RELAX:
628 sparc_relax = 1;
629 break;
630
631 case OPTION_NO_RELAX:
632 sparc_relax = 0;
633 break;
634
635 default:
636 return 0;
637 }
638
639 return 1;
640 }
641
642 void
643 md_show_usage (FILE *stream)
644 {
645 const struct sparc_arch *arch;
646 int column;
647
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p)
651 init_default_arch ();
652
653 fprintf (stream, _("SPARC options:\n"));
654 column = 0;
655 for (arch = &sparc_arch_table[0]; arch->name; arch++)
656 {
657 if (!arch->user_option_p)
658 continue;
659 if (arch != &sparc_arch_table[0])
660 fprintf (stream, " | ");
661 if (column + strlen (arch->name) > 70)
662 {
663 column = 0;
664 fputc ('\n', stream);
665 }
666 column += 5 + 2 + strlen (arch->name);
667 fprintf (stream, "-A%s", arch->name);
668 }
669 for (arch = &sparc_arch_table[0]; arch->name; arch++)
670 {
671 if (!arch->user_option_p)
672 continue;
673 fprintf (stream, " | ");
674 if (column + strlen (arch->name) > 65)
675 {
676 column = 0;
677 fputc ('\n', stream);
678 }
679 column += 5 + 7 + strlen (arch->name);
680 fprintf (stream, "-xarch=%s", arch->name);
681 }
682 fprintf (stream, _("\n\
683 specify variant of SPARC architecture\n\
684 -bump warn when assembler switches architectures\n\
685 -sparc ignored\n\
686 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
687 -relax relax jumps and branches (default)\n\
688 -no-relax avoid changing any jumps and branches\n"));
689 #ifdef OBJ_AOUT
690 fprintf (stream, _("\
691 -k generate PIC\n"));
692 #endif
693 #ifdef OBJ_ELF
694 fprintf (stream, _("\
695 -32 create 32 bit object file\n\
696 -64 create 64 bit object file\n"));
697 fprintf (stream, _("\
698 [default is %d]\n"), default_arch_size);
699 fprintf (stream, _("\
700 -TSO use Total Store Ordering\n\
701 -PSO use Partial Store Ordering\n\
702 -RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream, _("\
704 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
705 fprintf (stream, _("\
706 -KPIC generate PIC\n\
707 -V print assembler version number\n\
708 -undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710 -no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
712 -q ignored\n\
713 -Qy, -Qn ignored\n\
714 -s ignored\n"));
715 #endif
716 #ifdef SPARC_BIENDIAN
717 fprintf (stream, _("\
718 -EL generate code for a little endian machine\n\
719 -EB generate code for a big endian machine\n\
720 --little-endian-data generate code for a machine having big endian\n\
721 instructions and little endian data.\n"));
722 #endif
723 }
724 \f
725 /* Native operand size opcode translation. */
726 struct
727 {
728 char *name;
729 char *name32;
730 char *name64;
731 } native_op_table[] =
732 {
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
743 {NULL, NULL, NULL},
744 };
745 \f
746 /* sparc64 privileged and hyperprivileged registers. */
747
748 struct priv_reg_entry
749 {
750 char *name;
751 int regnum;
752 };
753
754 struct priv_reg_entry priv_reg_table[] =
755 {
756 {"tpc", 0},
757 {"tnpc", 1},
758 {"tstate", 2},
759 {"tt", 3},
760 {"tick", 4},
761 {"tba", 5},
762 {"pstate", 6},
763 {"tl", 7},
764 {"pil", 8},
765 {"cwp", 9},
766 {"cansave", 10},
767 {"canrestore", 11},
768 {"cleanwin", 12},
769 {"otherwin", 13},
770 {"wstate", 14},
771 {"fq", 15},
772 {"gl", 16},
773 {"ver", 31},
774 {"", -1}, /* End marker. */
775 };
776
777 struct priv_reg_entry hpriv_reg_table[] =
778 {
779 {"hpstate", 0},
780 {"htstate", 1},
781 {"hintp", 3},
782 {"htba", 5},
783 {"hver", 6},
784 {"hstick_cmpr", 31},
785 {"", -1}, /* End marker. */
786 };
787
788 /* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
790
791 struct priv_reg_entry v9a_asr_table[] =
792 {
793 {"tick_cmpr", 23},
794 {"sys_tick_cmpr", 25},
795 {"sys_tick", 24},
796 {"stick_cmpr", 25},
797 {"stick", 24},
798 {"softint_clear", 21},
799 {"softint_set", 20},
800 {"softint", 22},
801 {"set_softint", 20},
802 {"pic", 17},
803 {"pcr", 16},
804 {"gsr", 19},
805 {"dcr", 18},
806 {"cps", 28},
807 {"clear_softint", 21},
808 {"", -1}, /* End marker. */
809 };
810
811 static int
812 cmp_reg_entry (const void *parg, const void *qarg)
813 {
814 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
815 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
816
817 return strcmp (q->name, p->name);
818 }
819 \f
820 /* This function is called once, at assembler startup time. It should
821 set up all the tables, etc. that the MD part of the assembler will
822 need. */
823
824 void
825 md_begin (void)
826 {
827 register const char *retval = NULL;
828 int lose = 0;
829 register unsigned int i = 0;
830
831 /* We don't get a chance to initialize anything before md_parse_option
832 is called, and it may not be called, so handle default initialization
833 now if not already done. */
834 if (! default_init_p)
835 init_default_arch ();
836
837 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
838 op_hash = hash_new ();
839
840 while (i < (unsigned int) sparc_num_opcodes)
841 {
842 const char *name = sparc_opcodes[i].name;
843 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
844 if (retval != NULL)
845 {
846 as_bad (_("Internal error: can't hash `%s': %s\n"),
847 sparc_opcodes[i].name, retval);
848 lose = 1;
849 }
850 do
851 {
852 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
853 {
854 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
855 sparc_opcodes[i].name, sparc_opcodes[i].args);
856 lose = 1;
857 }
858 ++i;
859 }
860 while (i < (unsigned int) sparc_num_opcodes
861 && !strcmp (sparc_opcodes[i].name, name));
862 }
863
864 for (i = 0; native_op_table[i].name; i++)
865 {
866 const struct sparc_opcode *insn;
867 char *name = ((sparc_arch_size == 32)
868 ? native_op_table[i].name32
869 : native_op_table[i].name64);
870 insn = (struct sparc_opcode *) hash_find (op_hash, name);
871 if (insn == NULL)
872 {
873 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
874 name, native_op_table[i].name);
875 lose = 1;
876 }
877 else
878 {
879 retval = hash_insert (op_hash, native_op_table[i].name,
880 (void *) insn);
881 if (retval != NULL)
882 {
883 as_bad (_("Internal error: can't hash `%s': %s\n"),
884 sparc_opcodes[i].name, retval);
885 lose = 1;
886 }
887 }
888 }
889
890 if (lose)
891 as_fatal (_("Broken assembler. No assembly attempted."));
892
893 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
894 sizeof (priv_reg_table[0]), cmp_reg_entry);
895
896 /* If -bump, record the architecture level at which we start issuing
897 warnings. The behaviour is different depending upon whether an
898 architecture was explicitly specified. If it wasn't, we issue warnings
899 for all upwards bumps. If it was, we don't start issuing warnings until
900 we need to bump beyond the requested architecture or when we bump between
901 conflicting architectures. */
902
903 if (warn_on_bump
904 && architecture_requested)
905 {
906 /* `max_architecture' records the requested architecture.
907 Issue warnings if we go above it. */
908 warn_after_architecture = max_architecture;
909
910 /* Find the highest architecture level that doesn't conflict with
911 the requested one. */
912 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
913 max_architecture > warn_after_architecture;
914 --max_architecture)
915 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
916 warn_after_architecture))
917 break;
918 }
919 }
920
921 /* Called after all assembly has been done. */
922
923 void
924 sparc_md_end (void)
925 {
926 unsigned long mach = bfd_mach_sparc;
927
928 if (sparc_arch_size == 64)
929 switch (current_architecture)
930 {
931 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
932 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
933 default: mach = bfd_mach_sparc_v9; break;
934 }
935 else
936 switch (current_architecture)
937 {
938 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
939 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
940 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
941 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
942 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
943 be but for now it is (since that's the way it's always been
944 treated). */
945 default: break;
946 }
947 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
948
949 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
950 if (hwcap_seen)
951 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
952 #endif
953 }
954 \f
955 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
956
957 static inline int
958 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
959 {
960 if (max <= 0)
961 abort ();
962 /* Sign-extend the value from the architecture word size, so that
963 0xffffffff is always considered -1 on sparc32. */
964 if (sparc_arch_size == 32)
965 {
966 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
967 val = ((val & U0xffffffff) ^ sign) - sign;
968 }
969 if (val > max)
970 return 0;
971 if (val < ~max)
972 return 0;
973 return 1;
974 }
975
976 /* Return non-zero if VAL is in the range 0 to MAX. */
977
978 static inline int
979 in_unsigned_range (bfd_vma val, bfd_vma max)
980 {
981 if (val > max)
982 return 0;
983 return 1;
984 }
985
986 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
987 (e.g. -15 to +31). */
988
989 static inline int
990 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
991 {
992 if (max <= 0)
993 abort ();
994 if (val > max)
995 return 0;
996 if (val < ~(max >> 1))
997 return 0;
998 return 1;
999 }
1000
1001 static int
1002 sparc_ffs (unsigned int mask)
1003 {
1004 int i;
1005
1006 if (mask == 0)
1007 return -1;
1008
1009 for (i = 0; (mask & 1) == 0; ++i)
1010 mask >>= 1;
1011 return i;
1012 }
1013
1014 /* Implement big shift right. */
1015 static bfd_vma
1016 BSR (bfd_vma val, int amount)
1017 {
1018 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1019 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1020 return val >> amount;
1021 }
1022 \f
1023 /* For communication between sparc_ip and get_expression. */
1024 static char *expr_end;
1025
1026 /* Values for `special_case'.
1027 Instructions that require wierd handling because they're longer than
1028 4 bytes. */
1029 #define SPECIAL_CASE_NONE 0
1030 #define SPECIAL_CASE_SET 1
1031 #define SPECIAL_CASE_SETSW 2
1032 #define SPECIAL_CASE_SETX 3
1033 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1034 #define SPECIAL_CASE_FDIV 4
1035
1036 /* Bit masks of various insns. */
1037 #define NOP_INSN 0x01000000
1038 #define OR_INSN 0x80100000
1039 #define XOR_INSN 0x80180000
1040 #define FMOVS_INSN 0x81A00020
1041 #define SETHI_INSN 0x01000000
1042 #define SLLX_INSN 0x81281000
1043 #define SRA_INSN 0x81380000
1044
1045 /* The last instruction to be assembled. */
1046 static const struct sparc_opcode *last_insn;
1047 /* The assembled opcode of `last_insn'. */
1048 static unsigned long last_opcode;
1049 \f
1050 /* Handle the set and setuw synthetic instructions. */
1051
1052 static void
1053 synthetize_setuw (const struct sparc_opcode *insn)
1054 {
1055 int need_hi22_p = 0;
1056 int rd = (the_insn.opcode & RD (~0)) >> 25;
1057
1058 if (the_insn.exp.X_op == O_constant)
1059 {
1060 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1061 {
1062 if (sizeof (offsetT) > 4
1063 && (the_insn.exp.X_add_number < 0
1064 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1065 as_warn (_("set: number not in 0..4294967295 range"));
1066 }
1067 else
1068 {
1069 if (sizeof (offsetT) > 4
1070 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1071 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1072 as_warn (_("set: number not in -2147483648..4294967295 range"));
1073 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1074 }
1075 }
1076
1077 /* See if operand is absolute and small; skip sethi if so. */
1078 if (the_insn.exp.X_op != O_constant
1079 || the_insn.exp.X_add_number >= (1 << 12)
1080 || the_insn.exp.X_add_number < -(1 << 12))
1081 {
1082 the_insn.opcode = (SETHI_INSN | RD (rd)
1083 | ((the_insn.exp.X_add_number >> 10)
1084 & (the_insn.exp.X_op == O_constant
1085 ? 0x3fffff : 0)));
1086 the_insn.reloc = (the_insn.exp.X_op != O_constant
1087 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1088 output_insn (insn, &the_insn);
1089 need_hi22_p = 1;
1090 }
1091
1092 /* See if operand has no low-order bits; skip OR if so. */
1093 if (the_insn.exp.X_op != O_constant
1094 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1095 || ! need_hi22_p)
1096 {
1097 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1098 | RD (rd) | IMMED
1099 | (the_insn.exp.X_add_number
1100 & (the_insn.exp.X_op != O_constant
1101 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1102 the_insn.reloc = (the_insn.exp.X_op != O_constant
1103 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1104 output_insn (insn, &the_insn);
1105 }
1106 }
1107
1108 /* Handle the setsw synthetic instruction. */
1109
1110 static void
1111 synthetize_setsw (const struct sparc_opcode *insn)
1112 {
1113 int low32, rd, opc;
1114
1115 rd = (the_insn.opcode & RD (~0)) >> 25;
1116
1117 if (the_insn.exp.X_op != O_constant)
1118 {
1119 synthetize_setuw (insn);
1120
1121 /* Need to sign extend it. */
1122 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1123 the_insn.reloc = BFD_RELOC_NONE;
1124 output_insn (insn, &the_insn);
1125 return;
1126 }
1127
1128 if (sizeof (offsetT) > 4
1129 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1130 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1131 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1132
1133 low32 = the_insn.exp.X_add_number;
1134
1135 if (low32 >= 0)
1136 {
1137 synthetize_setuw (insn);
1138 return;
1139 }
1140
1141 opc = OR_INSN;
1142
1143 the_insn.reloc = BFD_RELOC_NONE;
1144 /* See if operand is absolute and small; skip sethi if so. */
1145 if (low32 < -(1 << 12))
1146 {
1147 the_insn.opcode = (SETHI_INSN | RD (rd)
1148 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1149 output_insn (insn, &the_insn);
1150 low32 = 0x1c00 | (low32 & 0x3ff);
1151 opc = RS1 (rd) | XOR_INSN;
1152 }
1153
1154 the_insn.opcode = (opc | RD (rd) | IMMED
1155 | (low32 & 0x1fff));
1156 output_insn (insn, &the_insn);
1157 }
1158
1159 /* Handle the setsw synthetic instruction. */
1160
1161 static void
1162 synthetize_setx (const struct sparc_opcode *insn)
1163 {
1164 int upper32, lower32;
1165 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1166 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1167 int upper_dstreg;
1168 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1169 int need_xor10_p = 0;
1170
1171 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1172 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1173 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1174 #undef SIGNEXT32
1175
1176 upper_dstreg = tmpreg;
1177 /* The tmp reg should not be the dst reg. */
1178 if (tmpreg == dstreg)
1179 as_warn (_("setx: temporary register same as destination register"));
1180
1181 /* ??? Obviously there are other optimizations we can do
1182 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1183 doing some of these. Later. If you do change things, try to
1184 change all of this to be table driven as well. */
1185 /* What to output depends on the number if it's constant.
1186 Compute that first, then output what we've decided upon. */
1187 if (the_insn.exp.X_op != O_constant)
1188 {
1189 if (sparc_arch_size == 32)
1190 {
1191 /* When arch size is 32, we want setx to be equivalent
1192 to setuw for anything but constants. */
1193 the_insn.exp.X_add_number &= 0xffffffff;
1194 synthetize_setuw (insn);
1195 return;
1196 }
1197 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1198 lower32 = 0;
1199 upper32 = 0;
1200 }
1201 else
1202 {
1203 /* Reset X_add_number, we've extracted it as upper32/lower32.
1204 Otherwise fixup_segment will complain about not being able to
1205 write an 8 byte number in a 4 byte field. */
1206 the_insn.exp.X_add_number = 0;
1207
1208 /* Only need hh22 if `or' insn can't handle constant. */
1209 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1210 need_hh22_p = 1;
1211
1212 /* Does bottom part (after sethi) have bits? */
1213 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1214 /* No hh22, but does upper32 still have bits we can't set
1215 from lower32? */
1216 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1217 need_hm10_p = 1;
1218
1219 /* If the lower half is all zero, we build the upper half directly
1220 into the dst reg. */
1221 if (lower32 != 0
1222 /* Need lower half if number is zero or 0xffffffff00000000. */
1223 || (! need_hh22_p && ! need_hm10_p))
1224 {
1225 /* No need for sethi if `or' insn can handle constant. */
1226 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1227 /* Note that we can't use a negative constant in the `or'
1228 insn unless the upper 32 bits are all ones. */
1229 || (lower32 < 0 && upper32 != -1)
1230 || (lower32 >= 0 && upper32 == -1))
1231 need_hi22_p = 1;
1232
1233 if (need_hi22_p && upper32 == -1)
1234 need_xor10_p = 1;
1235
1236 /* Does bottom part (after sethi) have bits? */
1237 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1238 /* No sethi. */
1239 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1240 /* Need `or' if we didn't set anything else. */
1241 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1242 need_lo10_p = 1;
1243 }
1244 else
1245 /* Output directly to dst reg if lower 32 bits are all zero. */
1246 upper_dstreg = dstreg;
1247 }
1248
1249 if (!upper_dstreg && dstreg)
1250 as_warn (_("setx: illegal temporary register g0"));
1251
1252 if (need_hh22_p)
1253 {
1254 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1255 | ((upper32 >> 10) & 0x3fffff));
1256 the_insn.reloc = (the_insn.exp.X_op != O_constant
1257 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1258 output_insn (insn, &the_insn);
1259 }
1260
1261 if (need_hi22_p)
1262 {
1263 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1264 | (((need_xor10_p ? ~lower32 : lower32)
1265 >> 10) & 0x3fffff));
1266 the_insn.reloc = (the_insn.exp.X_op != O_constant
1267 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1268 output_insn (insn, &the_insn);
1269 }
1270
1271 if (need_hm10_p)
1272 {
1273 the_insn.opcode = (OR_INSN
1274 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1275 | RD (upper_dstreg)
1276 | IMMED
1277 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1278 the_insn.reloc = (the_insn.exp.X_op != O_constant
1279 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1280 output_insn (insn, &the_insn);
1281 }
1282
1283 if (need_lo10_p)
1284 {
1285 /* FIXME: One nice optimization to do here is to OR the low part
1286 with the highpart if hi22 isn't needed and the low part is
1287 positive. */
1288 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1289 | RD (dstreg)
1290 | IMMED
1291 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1292 the_insn.reloc = (the_insn.exp.X_op != O_constant
1293 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1294 output_insn (insn, &the_insn);
1295 }
1296
1297 /* If we needed to build the upper part, shift it into place. */
1298 if (need_hh22_p || need_hm10_p)
1299 {
1300 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1301 | IMMED | 32);
1302 the_insn.reloc = BFD_RELOC_NONE;
1303 output_insn (insn, &the_insn);
1304 }
1305
1306 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1307 if (need_xor10_p)
1308 {
1309 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1310 | 0x1c00 | (lower32 & 0x3ff));
1311 the_insn.reloc = BFD_RELOC_NONE;
1312 output_insn (insn, &the_insn);
1313 }
1314
1315 /* If we needed to build both upper and lower parts, OR them together. */
1316 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1317 {
1318 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1319 | RD (dstreg));
1320 the_insn.reloc = BFD_RELOC_NONE;
1321 output_insn (insn, &the_insn);
1322 }
1323 }
1324 \f
1325 /* Main entry point to assemble one instruction. */
1326
1327 void
1328 md_assemble (char *str)
1329 {
1330 const struct sparc_opcode *insn;
1331 int special_case;
1332
1333 know (str);
1334 special_case = sparc_ip (str, &insn);
1335 if (insn == NULL)
1336 return;
1337
1338 /* We warn about attempts to put a floating point branch in a delay slot,
1339 unless the delay slot has been annulled. */
1340 if (last_insn != NULL
1341 && (insn->flags & F_FBR) != 0
1342 && (last_insn->flags & F_DELAYED) != 0
1343 /* ??? This test isn't completely accurate. We assume anything with
1344 F_{UNBR,CONDBR,FBR} set is annullable. */
1345 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1346 || (last_opcode & ANNUL) == 0))
1347 as_warn (_("FP branch in delay slot"));
1348
1349 /* SPARC before v9 requires a nop instruction between a floating
1350 point instruction and a floating point branch. We insert one
1351 automatically, with a warning. */
1352 if (max_architecture < SPARC_OPCODE_ARCH_V9
1353 && last_insn != NULL
1354 && (insn->flags & F_FBR) != 0
1355 && (last_insn->flags & F_FLOAT) != 0)
1356 {
1357 struct sparc_it nop_insn;
1358
1359 nop_insn.opcode = NOP_INSN;
1360 nop_insn.reloc = BFD_RELOC_NONE;
1361 output_insn (insn, &nop_insn);
1362 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1363 }
1364
1365 switch (special_case)
1366 {
1367 case SPECIAL_CASE_NONE:
1368 /* Normal insn. */
1369 output_insn (insn, &the_insn);
1370 break;
1371
1372 case SPECIAL_CASE_SETSW:
1373 synthetize_setsw (insn);
1374 break;
1375
1376 case SPECIAL_CASE_SET:
1377 synthetize_setuw (insn);
1378 break;
1379
1380 case SPECIAL_CASE_SETX:
1381 synthetize_setx (insn);
1382 break;
1383
1384 case SPECIAL_CASE_FDIV:
1385 {
1386 int rd = (the_insn.opcode >> 25) & 0x1f;
1387
1388 output_insn (insn, &the_insn);
1389
1390 /* According to information leaked from Sun, the "fdiv" instructions
1391 on early SPARC machines would produce incorrect results sometimes.
1392 The workaround is to add an fmovs of the destination register to
1393 itself just after the instruction. This was true on machines
1394 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1395 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1396 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1397 output_insn (insn, &the_insn);
1398 return;
1399 }
1400
1401 default:
1402 as_fatal (_("failed special case insn sanity check"));
1403 }
1404 }
1405
1406 static const char *
1407 get_hwcap_name (int mask)
1408 {
1409 if (mask & HWCAP_MUL32)
1410 return "mul32";
1411 if (mask & HWCAP_DIV32)
1412 return "div32";
1413 if (mask & HWCAP_FSMULD)
1414 return "fsmuld";
1415 if (mask & HWCAP_V8PLUS)
1416 return "v8plus";
1417 if (mask & HWCAP_POPC)
1418 return "popc";
1419 if (mask & HWCAP_VIS)
1420 return "vis";
1421 if (mask & HWCAP_VIS2)
1422 return "vis2";
1423 if (mask & HWCAP_ASI_BLK_INIT)
1424 return "ASIBlkInit";
1425 if (mask & HWCAP_FMAF)
1426 return "fmaf";
1427 if (mask & HWCAP_VIS3)
1428 return "vis3";
1429 if (mask & HWCAP_HPC)
1430 return "hpc";
1431 if (mask & HWCAP_RANDOM)
1432 return "random";
1433 if (mask & HWCAP_TRANS)
1434 return "trans";
1435 if (mask & HWCAP_FJFMAU)
1436 return "fjfmau";
1437 if (mask & HWCAP_IMA)
1438 return "ima";
1439 if (mask & HWCAP_ASI_CACHE_SPARING)
1440 return "cspare";
1441 if (mask & HWCAP_AES)
1442 return "aes";
1443 if (mask & HWCAP_DES)
1444 return "des";
1445 if (mask & HWCAP_KASUMI)
1446 return "kasumi";
1447 if (mask & HWCAP_CAMELLIA)
1448 return "camellia";
1449 if (mask & HWCAP_MD5)
1450 return "md5";
1451 if (mask & HWCAP_SHA1)
1452 return "sha1";
1453 if (mask & HWCAP_SHA256)
1454 return "sha256";
1455 if (mask & HWCAP_SHA512)
1456 return "sha512";
1457 if (mask & HWCAP_MPMUL)
1458 return "mpmul";
1459 if (mask & HWCAP_MONT)
1460 return "mont";
1461 if (mask & HWCAP_PAUSE)
1462 return "pause";
1463 if (mask & HWCAP_CBCOND)
1464 return "cbcond";
1465 if (mask & HWCAP_CRC32C)
1466 return "crc32c";
1467 return "UNKNOWN";
1468 }
1469
1470 /* Subroutine of md_assemble to do the actual parsing. */
1471
1472 static int
1473 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1474 {
1475 char *error_message = "";
1476 char *s;
1477 const char *args;
1478 char c;
1479 const struct sparc_opcode *insn;
1480 char *argsStart;
1481 unsigned long opcode;
1482 unsigned int mask = 0;
1483 int match = 0;
1484 int comma = 0;
1485 int v9_arg_p;
1486 int special_case = SPECIAL_CASE_NONE;
1487
1488 s = str;
1489 if (ISLOWER (*s))
1490 {
1491 do
1492 ++s;
1493 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1494 }
1495
1496 switch (*s)
1497 {
1498 case '\0':
1499 break;
1500
1501 case ',':
1502 comma = 1;
1503 /* Fall through. */
1504
1505 case ' ':
1506 *s++ = '\0';
1507 break;
1508
1509 default:
1510 as_bad (_("Unknown opcode: `%s'"), str);
1511 *pinsn = NULL;
1512 return special_case;
1513 }
1514 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1515 *pinsn = insn;
1516 if (insn == NULL)
1517 {
1518 as_bad (_("Unknown opcode: `%s'"), str);
1519 return special_case;
1520 }
1521 if (comma)
1522 {
1523 *--s = ',';
1524 }
1525
1526 argsStart = s;
1527 for (;;)
1528 {
1529 opcode = insn->match;
1530 memset (&the_insn, '\0', sizeof (the_insn));
1531 the_insn.reloc = BFD_RELOC_NONE;
1532 v9_arg_p = 0;
1533
1534 /* Build the opcode, checking as we go to make sure that the
1535 operands match. */
1536 for (args = insn->args;; ++args)
1537 {
1538 switch (*args)
1539 {
1540 case 'K':
1541 {
1542 int kmask = 0;
1543
1544 /* Parse a series of masks. */
1545 if (*s == '#')
1546 {
1547 while (*s == '#')
1548 {
1549 int jmask;
1550
1551 if (! parse_keyword_arg (sparc_encode_membar, &s,
1552 &jmask))
1553 {
1554 error_message = _(": invalid membar mask name");
1555 goto error;
1556 }
1557 kmask |= jmask;
1558 while (*s == ' ')
1559 ++s;
1560 if (*s == '|' || *s == '+')
1561 ++s;
1562 while (*s == ' ')
1563 ++s;
1564 }
1565 }
1566 else
1567 {
1568 if (! parse_const_expr_arg (&s, &kmask))
1569 {
1570 error_message = _(": invalid membar mask expression");
1571 goto error;
1572 }
1573 if (kmask < 0 || kmask > 127)
1574 {
1575 error_message = _(": invalid membar mask number");
1576 goto error;
1577 }
1578 }
1579
1580 opcode |= MEMBAR (kmask);
1581 continue;
1582 }
1583
1584 case '3':
1585 {
1586 int smask = 0;
1587
1588 if (! parse_const_expr_arg (&s, &smask))
1589 {
1590 error_message = _(": invalid siam mode expression");
1591 goto error;
1592 }
1593 if (smask < 0 || smask > 7)
1594 {
1595 error_message = _(": invalid siam mode number");
1596 goto error;
1597 }
1598 opcode |= smask;
1599 continue;
1600 }
1601
1602 case '*':
1603 {
1604 int fcn = 0;
1605
1606 /* Parse a prefetch function. */
1607 if (*s == '#')
1608 {
1609 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1610 {
1611 error_message = _(": invalid prefetch function name");
1612 goto error;
1613 }
1614 }
1615 else
1616 {
1617 if (! parse_const_expr_arg (&s, &fcn))
1618 {
1619 error_message = _(": invalid prefetch function expression");
1620 goto error;
1621 }
1622 if (fcn < 0 || fcn > 31)
1623 {
1624 error_message = _(": invalid prefetch function number");
1625 goto error;
1626 }
1627 }
1628 opcode |= RD (fcn);
1629 continue;
1630 }
1631
1632 case '!':
1633 case '?':
1634 /* Parse a sparc64 privileged register. */
1635 if (*s == '%')
1636 {
1637 struct priv_reg_entry *p = priv_reg_table;
1638 unsigned int len = 9999999; /* Init to make gcc happy. */
1639
1640 s += 1;
1641 while (p->name[0] > s[0])
1642 p++;
1643 while (p->name[0] == s[0])
1644 {
1645 len = strlen (p->name);
1646 if (strncmp (p->name, s, len) == 0)
1647 break;
1648 p++;
1649 }
1650 if (p->name[0] != s[0])
1651 {
1652 error_message = _(": unrecognizable privileged register");
1653 goto error;
1654 }
1655 if (*args == '?')
1656 opcode |= (p->regnum << 14);
1657 else
1658 opcode |= (p->regnum << 25);
1659 s += len;
1660 continue;
1661 }
1662 else
1663 {
1664 error_message = _(": unrecognizable privileged register");
1665 goto error;
1666 }
1667
1668 case '$':
1669 case '%':
1670 /* Parse a sparc64 hyperprivileged register. */
1671 if (*s == '%')
1672 {
1673 struct priv_reg_entry *p = hpriv_reg_table;
1674 unsigned int len = 9999999; /* Init to make gcc happy. */
1675
1676 s += 1;
1677 while (p->name[0] > s[0])
1678 p++;
1679 while (p->name[0] == s[0])
1680 {
1681 len = strlen (p->name);
1682 if (strncmp (p->name, s, len) == 0)
1683 break;
1684 p++;
1685 }
1686 if (p->name[0] != s[0])
1687 {
1688 error_message = _(": unrecognizable hyperprivileged register");
1689 goto error;
1690 }
1691 if (*args == '$')
1692 opcode |= (p->regnum << 14);
1693 else
1694 opcode |= (p->regnum << 25);
1695 s += len;
1696 continue;
1697 }
1698 else
1699 {
1700 error_message = _(": unrecognizable hyperprivileged register");
1701 goto error;
1702 }
1703
1704 case '_':
1705 case '/':
1706 /* Parse a v9a/v9b ancillary state register. */
1707 if (*s == '%')
1708 {
1709 struct priv_reg_entry *p = v9a_asr_table;
1710 unsigned int len = 9999999; /* Init to make gcc happy. */
1711
1712 s += 1;
1713 while (p->name[0] > s[0])
1714 p++;
1715 while (p->name[0] == s[0])
1716 {
1717 len = strlen (p->name);
1718 if (strncmp (p->name, s, len) == 0)
1719 break;
1720 p++;
1721 }
1722 if (p->name[0] != s[0])
1723 {
1724 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1725 goto error;
1726 }
1727 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1728 {
1729 error_message = _(": rd on write only ancillary state register");
1730 goto error;
1731 }
1732 if (p->regnum >= 24
1733 && (insn->architecture
1734 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1735 {
1736 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1737 error_message = _(": unrecognizable v9a ancillary state register");
1738 goto error;
1739 }
1740 if (*args == '/')
1741 opcode |= (p->regnum << 14);
1742 else
1743 opcode |= (p->regnum << 25);
1744 s += len;
1745 continue;
1746 }
1747 else
1748 {
1749 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1750 goto error;
1751 }
1752
1753 case 'M':
1754 case 'm':
1755 if (strncmp (s, "%asr", 4) == 0)
1756 {
1757 s += 4;
1758
1759 if (ISDIGIT (*s))
1760 {
1761 long num = 0;
1762
1763 while (ISDIGIT (*s))
1764 {
1765 num = num * 10 + *s - '0';
1766 ++s;
1767 }
1768
1769 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1770 {
1771 if (num < 16 || 31 < num)
1772 {
1773 error_message = _(": asr number must be between 16 and 31");
1774 goto error;
1775 }
1776 }
1777 else
1778 {
1779 if (num < 0 || 31 < num)
1780 {
1781 error_message = _(": asr number must be between 0 and 31");
1782 goto error;
1783 }
1784 }
1785
1786 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1787 continue;
1788 }
1789 else
1790 {
1791 error_message = _(": expecting %asrN");
1792 goto error;
1793 }
1794 } /* if %asr */
1795 break;
1796
1797 case 'I':
1798 the_insn.reloc = BFD_RELOC_SPARC_11;
1799 goto immediate;
1800
1801 case 'j':
1802 the_insn.reloc = BFD_RELOC_SPARC_10;
1803 goto immediate;
1804
1805 case ')':
1806 if (*s == ' ')
1807 s++;
1808 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1809 || ISDIGIT (*s))
1810 {
1811 long num = 0;
1812
1813 if (s[0] == '0' && s[1] == 'x')
1814 {
1815 s += 2;
1816 while (ISXDIGIT (*s))
1817 {
1818 num <<= 4;
1819 num |= hex_value (*s);
1820 ++s;
1821 }
1822 }
1823 else
1824 {
1825 while (ISDIGIT (*s))
1826 {
1827 num = num * 10 + *s - '0';
1828 ++s;
1829 }
1830 }
1831 if (num < 0 || num > 31)
1832 {
1833 error_message = _(": crypto immediate must be between 0 and 31");
1834 goto error;
1835 }
1836
1837 opcode |= RS3 (num);
1838 continue;
1839 }
1840 else
1841 {
1842 error_message = _(": expecting crypto immediate");
1843 goto error;
1844 }
1845
1846 case 'X':
1847 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1848 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1849 the_insn.reloc = BFD_RELOC_SPARC_5;
1850 else
1851 the_insn.reloc = BFD_RELOC_SPARC13;
1852 /* These fields are unsigned, but for upward compatibility,
1853 allow negative values as well. */
1854 goto immediate;
1855
1856 case 'Y':
1857 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1858 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1859 the_insn.reloc = BFD_RELOC_SPARC_6;
1860 else
1861 the_insn.reloc = BFD_RELOC_SPARC13;
1862 /* These fields are unsigned, but for upward compatibility,
1863 allow negative values as well. */
1864 goto immediate;
1865
1866 case 'k':
1867 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1868 the_insn.pcrel = 1;
1869 goto immediate;
1870
1871 case '=':
1872 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1873 the_insn.pcrel = 1;
1874 goto immediate;
1875
1876 case 'G':
1877 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1878 the_insn.pcrel = 1;
1879 goto immediate;
1880
1881 case 'N':
1882 if (*s == 'p' && s[1] == 'n')
1883 {
1884 s += 2;
1885 continue;
1886 }
1887 break;
1888
1889 case 'T':
1890 if (*s == 'p' && s[1] == 't')
1891 {
1892 s += 2;
1893 continue;
1894 }
1895 break;
1896
1897 case 'z':
1898 if (*s == ' ')
1899 {
1900 ++s;
1901 }
1902 if (strncmp (s, "%icc", 4) == 0)
1903 {
1904 s += 4;
1905 continue;
1906 }
1907 break;
1908
1909 case 'Z':
1910 if (*s == ' ')
1911 {
1912 ++s;
1913 }
1914 if (strncmp (s, "%xcc", 4) == 0)
1915 {
1916 s += 4;
1917 continue;
1918 }
1919 break;
1920
1921 case '6':
1922 if (*s == ' ')
1923 {
1924 ++s;
1925 }
1926 if (strncmp (s, "%fcc0", 5) == 0)
1927 {
1928 s += 5;
1929 continue;
1930 }
1931 break;
1932
1933 case '7':
1934 if (*s == ' ')
1935 {
1936 ++s;
1937 }
1938 if (strncmp (s, "%fcc1", 5) == 0)
1939 {
1940 s += 5;
1941 continue;
1942 }
1943 break;
1944
1945 case '8':
1946 if (*s == ' ')
1947 {
1948 ++s;
1949 }
1950 if (strncmp (s, "%fcc2", 5) == 0)
1951 {
1952 s += 5;
1953 continue;
1954 }
1955 break;
1956
1957 case '9':
1958 if (*s == ' ')
1959 {
1960 ++s;
1961 }
1962 if (strncmp (s, "%fcc3", 5) == 0)
1963 {
1964 s += 5;
1965 continue;
1966 }
1967 break;
1968
1969 case 'P':
1970 if (strncmp (s, "%pc", 3) == 0)
1971 {
1972 s += 3;
1973 continue;
1974 }
1975 break;
1976
1977 case 'W':
1978 if (strncmp (s, "%tick", 5) == 0)
1979 {
1980 s += 5;
1981 continue;
1982 }
1983 break;
1984
1985 case '\0': /* End of args. */
1986 if (s[0] == ',' && s[1] == '%')
1987 {
1988 static const struct ops
1989 {
1990 /* The name as it appears in assembler. */
1991 char *name;
1992 /* strlen (name), precomputed for speed */
1993 int len;
1994 /* The reloc this pseudo-op translates to. */
1995 int reloc;
1996 /* 1 if tls call. */
1997 int tls_call;
1998 }
1999 ops[] =
2000 {
2001 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2002 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2003 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2004 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2005 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2006 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2007 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2008 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2009 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2010 { NULL, 0, 0, 0 }
2011 };
2012 const struct ops *o;
2013 char *s1;
2014 int npar = 0;
2015
2016 for (o = ops; o->name; o++)
2017 if (strncmp (s + 2, o->name, o->len) == 0)
2018 break;
2019 if (o->name == NULL)
2020 break;
2021
2022 if (s[o->len + 2] != '(')
2023 {
2024 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2025 return special_case;
2026 }
2027
2028 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2029 {
2030 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2031 o->name);
2032 return special_case;
2033 }
2034
2035 if (o->tls_call
2036 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2037 || the_insn.exp.X_add_number != 0
2038 || the_insn.exp.X_add_symbol
2039 != symbol_find_or_make ("__tls_get_addr")))
2040 {
2041 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2042 o->name);
2043 return special_case;
2044 }
2045
2046 the_insn.reloc = o->reloc;
2047 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2048 s += o->len + 3;
2049
2050 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2051 if (*s1 == '(')
2052 npar++;
2053 else if (*s1 == ')')
2054 {
2055 if (!npar)
2056 break;
2057 npar--;
2058 }
2059
2060 if (*s1 != ')')
2061 {
2062 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2063 return special_case;
2064 }
2065
2066 *s1 = '\0';
2067 (void) get_expression (s);
2068 *s1 = ')';
2069 s = s1 + 1;
2070 }
2071 if (*s == '\0')
2072 match = 1;
2073 break;
2074
2075 case '+':
2076 if (*s == '+')
2077 {
2078 ++s;
2079 continue;
2080 }
2081 if (*s == '-')
2082 {
2083 continue;
2084 }
2085 break;
2086
2087 case '[': /* These must match exactly. */
2088 case ']':
2089 case ',':
2090 case ' ':
2091 if (*s++ == *args)
2092 continue;
2093 break;
2094
2095 case '#': /* Must be at least one digit. */
2096 if (ISDIGIT (*s++))
2097 {
2098 while (ISDIGIT (*s))
2099 {
2100 ++s;
2101 }
2102 continue;
2103 }
2104 break;
2105
2106 case 'C': /* Coprocessor state register. */
2107 if (strncmp (s, "%csr", 4) == 0)
2108 {
2109 s += 4;
2110 continue;
2111 }
2112 break;
2113
2114 case 'b': /* Next operand is a coprocessor register. */
2115 case 'c':
2116 case 'D':
2117 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2118 {
2119 mask = *s++;
2120 if (ISDIGIT (*s))
2121 {
2122 mask = 10 * (mask - '0') + (*s++ - '0');
2123 if (mask >= 32)
2124 {
2125 break;
2126 }
2127 }
2128 else
2129 {
2130 mask -= '0';
2131 }
2132 switch (*args)
2133 {
2134
2135 case 'b':
2136 opcode |= mask << 14;
2137 continue;
2138
2139 case 'c':
2140 opcode |= mask;
2141 continue;
2142
2143 case 'D':
2144 opcode |= mask << 25;
2145 continue;
2146 }
2147 }
2148 break;
2149
2150 case 'r': /* next operand must be a register */
2151 case 'O':
2152 case '1':
2153 case '2':
2154 case 'd':
2155 if (*s++ == '%')
2156 {
2157 switch (c = *s++)
2158 {
2159
2160 case 'f': /* frame pointer */
2161 if (*s++ == 'p')
2162 {
2163 mask = 0x1e;
2164 break;
2165 }
2166 goto error;
2167
2168 case 'g': /* global register */
2169 c = *s++;
2170 if (isoctal (c))
2171 {
2172 mask = c - '0';
2173 break;
2174 }
2175 goto error;
2176
2177 case 'i': /* in register */
2178 c = *s++;
2179 if (isoctal (c))
2180 {
2181 mask = c - '0' + 24;
2182 break;
2183 }
2184 goto error;
2185
2186 case 'l': /* local register */
2187 c = *s++;
2188 if (isoctal (c))
2189 {
2190 mask = (c - '0' + 16);
2191 break;
2192 }
2193 goto error;
2194
2195 case 'o': /* out register */
2196 c = *s++;
2197 if (isoctal (c))
2198 {
2199 mask = (c - '0' + 8);
2200 break;
2201 }
2202 goto error;
2203
2204 case 's': /* stack pointer */
2205 if (*s++ == 'p')
2206 {
2207 mask = 0xe;
2208 break;
2209 }
2210 goto error;
2211
2212 case 'r': /* any register */
2213 if (!ISDIGIT ((c = *s++)))
2214 {
2215 goto error;
2216 }
2217 /* FALLTHROUGH */
2218 case '0':
2219 case '1':
2220 case '2':
2221 case '3':
2222 case '4':
2223 case '5':
2224 case '6':
2225 case '7':
2226 case '8':
2227 case '9':
2228 if (ISDIGIT (*s))
2229 {
2230 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2231 {
2232 goto error;
2233 }
2234 }
2235 else
2236 {
2237 c -= '0';
2238 }
2239 mask = c;
2240 break;
2241
2242 default:
2243 goto error;
2244 }
2245
2246 if ((mask & ~1) == 2 && sparc_arch_size == 64
2247 && no_undeclared_regs && ! globals[mask])
2248 as_bad (_("detected global register use not covered by .register pseudo-op"));
2249
2250 /* Got the register, now figure out where
2251 it goes in the opcode. */
2252 switch (*args)
2253 {
2254 case '1':
2255 opcode |= mask << 14;
2256 continue;
2257
2258 case '2':
2259 opcode |= mask;
2260 continue;
2261
2262 case 'd':
2263 opcode |= mask << 25;
2264 continue;
2265
2266 case 'r':
2267 opcode |= (mask << 25) | (mask << 14);
2268 continue;
2269
2270 case 'O':
2271 opcode |= (mask << 25) | (mask << 0);
2272 continue;
2273 }
2274 }
2275 break;
2276
2277 case 'e': /* next operand is a floating point register */
2278 case 'v':
2279 case 'V':
2280
2281 case 'f':
2282 case 'B':
2283 case 'R':
2284
2285 case '4':
2286 case '5':
2287
2288 case 'g':
2289 case 'H':
2290 case 'J':
2291 {
2292 char format;
2293
2294 if (*s++ == '%'
2295 && ((format = *s) == 'f')
2296 && ISDIGIT (*++s))
2297 {
2298 for (mask = 0; ISDIGIT (*s); ++s)
2299 {
2300 mask = 10 * mask + (*s - '0');
2301 } /* read the number */
2302
2303 if ((*args == 'v'
2304 || *args == 'B'
2305 || *args == '5'
2306 || *args == 'H')
2307 && (mask & 1))
2308 {
2309 break;
2310 } /* register must be even numbered */
2311
2312 if ((*args == 'V'
2313 || *args == 'R'
2314 || *args == 'J')
2315 && (mask & 3))
2316 {
2317 break;
2318 } /* register must be multiple of 4 */
2319
2320 if (mask >= 64)
2321 {
2322 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2323 error_message = _(": There are only 64 f registers; [0-63]");
2324 else
2325 error_message = _(": There are only 32 f registers; [0-31]");
2326 goto error;
2327 } /* on error */
2328 else if (mask >= 32)
2329 {
2330 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2331 {
2332 if (*args == 'e' || *args == 'f' || *args == 'g')
2333 {
2334 error_message
2335 = _(": There are only 32 single precision f registers; [0-31]");
2336 goto error;
2337 }
2338 v9_arg_p = 1;
2339 mask -= 31; /* wrap high bit */
2340 }
2341 else
2342 {
2343 error_message = _(": There are only 32 f registers; [0-31]");
2344 goto error;
2345 }
2346 }
2347 }
2348 else
2349 {
2350 break;
2351 } /* if not an 'f' register. */
2352
2353 switch (*args)
2354 {
2355 case 'v':
2356 case 'V':
2357 case 'e':
2358 opcode |= RS1 (mask);
2359 continue;
2360
2361 case 'f':
2362 case 'B':
2363 case 'R':
2364 opcode |= RS2 (mask);
2365 continue;
2366
2367 case '4':
2368 case '5':
2369 opcode |= RS3 (mask);
2370 continue;
2371
2372 case 'g':
2373 case 'H':
2374 case 'J':
2375 opcode |= RD (mask);
2376 continue;
2377 } /* Pack it in. */
2378
2379 know (0);
2380 break;
2381 } /* float arg */
2382
2383 case 'F':
2384 if (strncmp (s, "%fsr", 4) == 0)
2385 {
2386 s += 4;
2387 continue;
2388 }
2389 break;
2390
2391 case '(':
2392 if (strncmp (s, "%efsr", 5) == 0)
2393 {
2394 s += 5;
2395 continue;
2396 }
2397 break;
2398
2399 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2400 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2401 goto immediate;
2402
2403 case 'l': /* 22 bit PC relative immediate */
2404 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2405 the_insn.pcrel = 1;
2406 goto immediate;
2407
2408 case 'L': /* 30 bit immediate */
2409 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2410 the_insn.pcrel = 1;
2411 goto immediate;
2412
2413 case 'h':
2414 case 'n': /* 22 bit immediate */
2415 the_insn.reloc = BFD_RELOC_SPARC22;
2416 goto immediate;
2417
2418 case 'i': /* 13 bit immediate */
2419 the_insn.reloc = BFD_RELOC_SPARC13;
2420
2421 /* fallthrough */
2422
2423 immediate:
2424 if (*s == ' ')
2425 s++;
2426
2427 {
2428 char *s1;
2429 char *op_arg = NULL;
2430 static expressionS op_exp;
2431 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2432
2433 /* Check for %hi, etc. */
2434 if (*s == '%')
2435 {
2436 static const struct ops {
2437 /* The name as it appears in assembler. */
2438 char *name;
2439 /* strlen (name), precomputed for speed */
2440 int len;
2441 /* The reloc this pseudo-op translates to. */
2442 int reloc;
2443 /* Non-zero if for v9 only. */
2444 int v9_p;
2445 /* Non-zero if can be used in pc-relative contexts. */
2446 int pcrel_p;/*FIXME:wip*/
2447 } ops[] = {
2448 /* hix/lox must appear before hi/lo so %hix won't be
2449 mistaken for %hi. */
2450 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2451 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2452 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2453 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2454 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2455 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2456 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2457 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2458 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2459 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2460 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2461 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2462 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2463 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2464 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2465 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2466 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2467 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2468 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2469 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2470 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2471 0 },
2472 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2473 0 },
2474 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2475 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2476 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2477 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2478 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2479 0, 0 },
2480 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2481 0, 0 },
2482 { NULL, 0, 0, 0, 0 }
2483 };
2484 const struct ops *o;
2485
2486 for (o = ops; o->name; o++)
2487 if (strncmp (s + 1, o->name, o->len) == 0)
2488 break;
2489 if (o->name == NULL)
2490 break;
2491
2492 if (s[o->len + 1] != '(')
2493 {
2494 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2495 return special_case;
2496 }
2497
2498 op_arg = o->name;
2499 the_insn.reloc = o->reloc;
2500 s += o->len + 2;
2501 v9_arg_p = o->v9_p;
2502 }
2503
2504 /* Note that if the get_expression() fails, we will still
2505 have created U entries in the symbol table for the
2506 'symbols' in the input string. Try not to create U
2507 symbols for registers, etc. */
2508
2509 /* This stuff checks to see if the expression ends in
2510 +%reg. If it does, it removes the register from
2511 the expression, and re-sets 's' to point to the
2512 right place. */
2513
2514 if (op_arg)
2515 {
2516 int npar = 0;
2517
2518 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2519 if (*s1 == '(')
2520 npar++;
2521 else if (*s1 == ')')
2522 {
2523 if (!npar)
2524 break;
2525 npar--;
2526 }
2527
2528 if (*s1 != ')')
2529 {
2530 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2531 return special_case;
2532 }
2533
2534 *s1 = '\0';
2535 (void) get_expression (s);
2536 *s1 = ')';
2537 s = s1 + 1;
2538 if (*s == ',' || *s == ']' || !*s)
2539 continue;
2540 if (*s != '+' && *s != '-')
2541 {
2542 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2543 return special_case;
2544 }
2545 *s1 = '0';
2546 s = s1;
2547 op_exp = the_insn.exp;
2548 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2549 }
2550
2551 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2552 ;
2553
2554 if (s1 != s && ISDIGIT (s1[-1]))
2555 {
2556 if (s1[-2] == '%' && s1[-3] == '+')
2557 s1 -= 3;
2558 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2559 s1 -= 4;
2560 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2561 s1 -= 5;
2562 else
2563 s1 = NULL;
2564 if (s1)
2565 {
2566 *s1 = '\0';
2567 if (op_arg && s1 == s + 1)
2568 the_insn.exp.X_op = O_absent;
2569 else
2570 (void) get_expression (s);
2571 *s1 = '+';
2572 if (op_arg)
2573 *s = ')';
2574 s = s1;
2575 }
2576 }
2577 else
2578 s1 = NULL;
2579
2580 if (!s1)
2581 {
2582 (void) get_expression (s);
2583 if (op_arg)
2584 *s = ')';
2585 s = expr_end;
2586 }
2587
2588 if (op_arg)
2589 {
2590 the_insn.exp2 = the_insn.exp;
2591 the_insn.exp = op_exp;
2592 if (the_insn.exp2.X_op == O_absent)
2593 the_insn.exp2.X_op = O_illegal;
2594 else if (the_insn.exp.X_op == O_absent)
2595 {
2596 the_insn.exp = the_insn.exp2;
2597 the_insn.exp2.X_op = O_illegal;
2598 }
2599 else if (the_insn.exp.X_op == O_constant)
2600 {
2601 valueT val = the_insn.exp.X_add_number;
2602 switch (the_insn.reloc)
2603 {
2604 default:
2605 break;
2606
2607 case BFD_RELOC_SPARC_HH22:
2608 val = BSR (val, 32);
2609 /* Fall through. */
2610
2611 case BFD_RELOC_SPARC_LM22:
2612 case BFD_RELOC_HI22:
2613 val = (val >> 10) & 0x3fffff;
2614 break;
2615
2616 case BFD_RELOC_SPARC_HM10:
2617 val = BSR (val, 32);
2618 /* Fall through. */
2619
2620 case BFD_RELOC_LO10:
2621 val &= 0x3ff;
2622 break;
2623
2624 case BFD_RELOC_SPARC_H34:
2625 val >>= 12;
2626 val &= 0x3fffff;
2627 break;
2628
2629 case BFD_RELOC_SPARC_H44:
2630 val >>= 22;
2631 val &= 0x3fffff;
2632 break;
2633
2634 case BFD_RELOC_SPARC_M44:
2635 val >>= 12;
2636 val &= 0x3ff;
2637 break;
2638
2639 case BFD_RELOC_SPARC_L44:
2640 val &= 0xfff;
2641 break;
2642
2643 case BFD_RELOC_SPARC_HIX22:
2644 val = ~val;
2645 val = (val >> 10) & 0x3fffff;
2646 break;
2647
2648 case BFD_RELOC_SPARC_LOX10:
2649 val = (val & 0x3ff) | 0x1c00;
2650 break;
2651 }
2652 the_insn.exp = the_insn.exp2;
2653 the_insn.exp.X_add_number += val;
2654 the_insn.exp2.X_op = O_illegal;
2655 the_insn.reloc = old_reloc;
2656 }
2657 else if (the_insn.exp2.X_op != O_constant)
2658 {
2659 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2660 return special_case;
2661 }
2662 else
2663 {
2664 if (old_reloc != BFD_RELOC_SPARC13
2665 || the_insn.reloc != BFD_RELOC_LO10
2666 || sparc_arch_size != 64
2667 || sparc_pic_code)
2668 {
2669 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2670 return special_case;
2671 }
2672 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2673 }
2674 }
2675 }
2676 /* Check for constants that don't require emitting a reloc. */
2677 if (the_insn.exp.X_op == O_constant
2678 && the_insn.exp.X_add_symbol == 0
2679 && the_insn.exp.X_op_symbol == 0)
2680 {
2681 /* For pc-relative call instructions, we reject
2682 constants to get better code. */
2683 if (the_insn.pcrel
2684 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2685 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2686 {
2687 error_message = _(": PC-relative operand can't be a constant");
2688 goto error;
2689 }
2690
2691 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2692 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2693 {
2694 error_message = _(": TLS operand can't be a constant");
2695 goto error;
2696 }
2697
2698 /* Constants that won't fit are checked in md_apply_fix
2699 and bfd_install_relocation.
2700 ??? It would be preferable to install the constants
2701 into the insn here and save having to create a fixS
2702 for each one. There already exists code to handle
2703 all the various cases (e.g. in md_apply_fix and
2704 bfd_install_relocation) so duplicating all that code
2705 here isn't right. */
2706 }
2707
2708 continue;
2709
2710 case 'a':
2711 if (*s++ == 'a')
2712 {
2713 opcode |= ANNUL;
2714 continue;
2715 }
2716 break;
2717
2718 case 'A':
2719 {
2720 int asi = 0;
2721
2722 /* Parse an asi. */
2723 if (*s == '#')
2724 {
2725 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2726 {
2727 error_message = _(": invalid ASI name");
2728 goto error;
2729 }
2730 }
2731 else
2732 {
2733 if (! parse_const_expr_arg (&s, &asi))
2734 {
2735 error_message = _(": invalid ASI expression");
2736 goto error;
2737 }
2738 if (asi < 0 || asi > 255)
2739 {
2740 error_message = _(": invalid ASI number");
2741 goto error;
2742 }
2743 }
2744 opcode |= ASI (asi);
2745 continue;
2746 } /* Alternate space. */
2747
2748 case 'p':
2749 if (strncmp (s, "%psr", 4) == 0)
2750 {
2751 s += 4;
2752 continue;
2753 }
2754 break;
2755
2756 case 'q': /* Floating point queue. */
2757 if (strncmp (s, "%fq", 3) == 0)
2758 {
2759 s += 3;
2760 continue;
2761 }
2762 break;
2763
2764 case 'Q': /* Coprocessor queue. */
2765 if (strncmp (s, "%cq", 3) == 0)
2766 {
2767 s += 3;
2768 continue;
2769 }
2770 break;
2771
2772 case 'S':
2773 if (strcmp (str, "set") == 0
2774 || strcmp (str, "setuw") == 0)
2775 {
2776 special_case = SPECIAL_CASE_SET;
2777 continue;
2778 }
2779 else if (strcmp (str, "setsw") == 0)
2780 {
2781 special_case = SPECIAL_CASE_SETSW;
2782 continue;
2783 }
2784 else if (strcmp (str, "setx") == 0)
2785 {
2786 special_case = SPECIAL_CASE_SETX;
2787 continue;
2788 }
2789 else if (strncmp (str, "fdiv", 4) == 0)
2790 {
2791 special_case = SPECIAL_CASE_FDIV;
2792 continue;
2793 }
2794 break;
2795
2796 case 'o':
2797 if (strncmp (s, "%asi", 4) != 0)
2798 break;
2799 s += 4;
2800 continue;
2801
2802 case 's':
2803 if (strncmp (s, "%fprs", 5) != 0)
2804 break;
2805 s += 5;
2806 continue;
2807
2808 case 'E':
2809 if (strncmp (s, "%ccr", 4) != 0)
2810 break;
2811 s += 4;
2812 continue;
2813
2814 case 't':
2815 if (strncmp (s, "%tbr", 4) != 0)
2816 break;
2817 s += 4;
2818 continue;
2819
2820 case 'w':
2821 if (strncmp (s, "%wim", 4) != 0)
2822 break;
2823 s += 4;
2824 continue;
2825
2826 case 'x':
2827 {
2828 char *push = input_line_pointer;
2829 expressionS e;
2830
2831 input_line_pointer = s;
2832 expression (&e);
2833 if (e.X_op == O_constant)
2834 {
2835 int n = e.X_add_number;
2836 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2837 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2838 else
2839 opcode |= e.X_add_number << 5;
2840 }
2841 else
2842 as_bad (_("non-immediate OPF operand, ignored"));
2843 s = input_line_pointer;
2844 input_line_pointer = push;
2845 continue;
2846 }
2847
2848 case 'y':
2849 if (strncmp (s, "%y", 2) != 0)
2850 break;
2851 s += 2;
2852 continue;
2853
2854 case 'u':
2855 case 'U':
2856 {
2857 /* Parse a sparclet cpreg. */
2858 int cpreg;
2859 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2860 {
2861 error_message = _(": invalid cpreg name");
2862 goto error;
2863 }
2864 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2865 continue;
2866 }
2867
2868 default:
2869 as_fatal (_("failed sanity check."));
2870 } /* switch on arg code. */
2871
2872 /* Break out of for() loop. */
2873 break;
2874 } /* For each arg that we expect. */
2875
2876 error:
2877 if (match == 0)
2878 {
2879 /* Args don't match. */
2880 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2881 && (insn->name == insn[1].name
2882 || !strcmp (insn->name, insn[1].name)))
2883 {
2884 ++insn;
2885 s = argsStart;
2886 continue;
2887 }
2888 else
2889 {
2890 as_bad (_("Illegal operands%s"), error_message);
2891 return special_case;
2892 }
2893 }
2894 else
2895 {
2896 /* We have a match. Now see if the architecture is OK. */
2897 int needed_arch_mask = insn->architecture;
2898 int hwcaps = insn->hwcaps;
2899
2900 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2901 if (hwcaps)
2902 hwcap_seen |= hwcaps;
2903 #endif
2904 if (v9_arg_p)
2905 {
2906 needed_arch_mask &=
2907 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2908 if (! needed_arch_mask)
2909 needed_arch_mask =
2910 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2911 }
2912
2913 if (needed_arch_mask
2914 & SPARC_OPCODE_SUPPORTED (current_architecture))
2915 /* OK. */
2916 ;
2917 /* Can we bump up the architecture? */
2918 else if (needed_arch_mask
2919 & SPARC_OPCODE_SUPPORTED (max_architecture))
2920 {
2921 enum sparc_opcode_arch_val needed_architecture =
2922 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2923 & needed_arch_mask);
2924
2925 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2926 if (warn_on_bump
2927 && needed_architecture > warn_after_architecture)
2928 {
2929 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2930 sparc_opcode_archs[current_architecture].name,
2931 sparc_opcode_archs[needed_architecture].name,
2932 str);
2933 warn_after_architecture = needed_architecture;
2934 }
2935 current_architecture = needed_architecture;
2936 }
2937 /* Conflict. */
2938 /* ??? This seems to be a bit fragile. What if the next entry in
2939 the opcode table is the one we want and it is supported?
2940 It is possible to arrange the table today so that this can't
2941 happen but what about tomorrow? */
2942 else
2943 {
2944 int arch, printed_one_p = 0;
2945 char *p;
2946 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2947
2948 /* Create a list of the architectures that support the insn. */
2949 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2950 p = required_archs;
2951 arch = sparc_ffs (needed_arch_mask);
2952 while ((1 << arch) <= needed_arch_mask)
2953 {
2954 if ((1 << arch) & needed_arch_mask)
2955 {
2956 if (printed_one_p)
2957 *p++ = '|';
2958 strcpy (p, sparc_opcode_archs[arch].name);
2959 p += strlen (p);
2960 printed_one_p = 1;
2961 }
2962 ++arch;
2963 }
2964
2965 as_bad (_("Architecture mismatch on \"%s\"."), str);
2966 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2967 required_archs,
2968 sparc_opcode_archs[max_architecture].name);
2969 return special_case;
2970 }
2971
2972 /* Make sure the the hwcaps used by the instruction are
2973 currently enabled. */
2974 if (hwcaps & ~hwcap_allowed)
2975 {
2976 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2977
2978 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
2979 hwcap_name, str);
2980 return special_case;
2981 }
2982 } /* If no match. */
2983
2984 break;
2985 } /* Forever looking for a match. */
2986
2987 the_insn.opcode = opcode;
2988 return special_case;
2989 }
2990
2991 /* Parse an argument that can be expressed as a keyword.
2992 (eg: #StoreStore or %ccfr).
2993 The result is a boolean indicating success.
2994 If successful, INPUT_POINTER is updated. */
2995
2996 static int
2997 parse_keyword_arg (int (*lookup_fn) (const char *),
2998 char **input_pointerP,
2999 int *valueP)
3000 {
3001 int value;
3002 char c, *p, *q;
3003
3004 p = *input_pointerP;
3005 for (q = p + (*p == '#' || *p == '%');
3006 ISALNUM (*q) || *q == '_';
3007 ++q)
3008 continue;
3009 c = *q;
3010 *q = 0;
3011 value = (*lookup_fn) (p);
3012 *q = c;
3013 if (value == -1)
3014 return 0;
3015 *valueP = value;
3016 *input_pointerP = q;
3017 return 1;
3018 }
3019
3020 /* Parse an argument that is a constant expression.
3021 The result is a boolean indicating success. */
3022
3023 static int
3024 parse_const_expr_arg (char **input_pointerP, int *valueP)
3025 {
3026 char *save = input_line_pointer;
3027 expressionS exp;
3028
3029 input_line_pointer = *input_pointerP;
3030 /* The next expression may be something other than a constant
3031 (say if we're not processing the right variant of the insn).
3032 Don't call expression unless we're sure it will succeed as it will
3033 signal an error (which we want to defer until later). */
3034 /* FIXME: It might be better to define md_operand and have it recognize
3035 things like %asi, etc. but continuing that route through to the end
3036 is a lot of work. */
3037 if (*input_line_pointer == '%')
3038 {
3039 input_line_pointer = save;
3040 return 0;
3041 }
3042 expression (&exp);
3043 *input_pointerP = input_line_pointer;
3044 input_line_pointer = save;
3045 if (exp.X_op != O_constant)
3046 return 0;
3047 *valueP = exp.X_add_number;
3048 return 1;
3049 }
3050
3051 /* Subroutine of sparc_ip to parse an expression. */
3052
3053 static int
3054 get_expression (char *str)
3055 {
3056 char *save_in;
3057 segT seg;
3058
3059 save_in = input_line_pointer;
3060 input_line_pointer = str;
3061 seg = expression (&the_insn.exp);
3062 if (seg != absolute_section
3063 && seg != text_section
3064 && seg != data_section
3065 && seg != bss_section
3066 && seg != undefined_section)
3067 {
3068 the_insn.error = _("bad segment");
3069 expr_end = input_line_pointer;
3070 input_line_pointer = save_in;
3071 return 1;
3072 }
3073 expr_end = input_line_pointer;
3074 input_line_pointer = save_in;
3075 return 0;
3076 }
3077
3078 /* Subroutine of md_assemble to output one insn. */
3079
3080 static void
3081 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3082 {
3083 char *toP = frag_more (4);
3084
3085 /* Put out the opcode. */
3086 if (INSN_BIG_ENDIAN)
3087 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3088 else
3089 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3090
3091 /* Put out the symbol-dependent stuff. */
3092 if (theinsn->reloc != BFD_RELOC_NONE)
3093 {
3094 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3095 (toP - frag_now->fr_literal), /* Where. */
3096 4, /* Size. */
3097 &theinsn->exp,
3098 theinsn->pcrel,
3099 theinsn->reloc);
3100 /* Turn off overflow checking in fixup_segment. We'll do our
3101 own overflow checking in md_apply_fix. This is necessary because
3102 the insn size is 4 and fixup_segment will signal an overflow for
3103 large 8 byte quantities. */
3104 fixP->fx_no_overflow = 1;
3105 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3106 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3107 }
3108
3109 last_insn = insn;
3110 last_opcode = theinsn->opcode;
3111
3112 #ifdef OBJ_ELF
3113 dwarf2_emit_insn (4);
3114 #endif
3115 }
3116 \f
3117 char *
3118 md_atof (int type, char *litP, int *sizeP)
3119 {
3120 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3121 }
3122
3123 /* Write a value out to the object file, using the appropriate
3124 endianness. */
3125
3126 void
3127 md_number_to_chars (char *buf, valueT val, int n)
3128 {
3129 if (target_big_endian)
3130 number_to_chars_bigendian (buf, val, n);
3131 else if (target_little_endian_data
3132 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3133 /* Output debug words, which are not in allocated sections, as big
3134 endian. */
3135 number_to_chars_bigendian (buf, val, n);
3136 else if (target_little_endian_data || ! target_big_endian)
3137 number_to_chars_littleendian (buf, val, n);
3138 }
3139 \f
3140 /* Apply a fixS to the frags, now that we know the value it ought to
3141 hold. */
3142
3143 void
3144 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3145 {
3146 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3147 offsetT val = * (offsetT *) valP;
3148 long insn;
3149
3150 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3151
3152 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3153
3154 #ifdef OBJ_ELF
3155 /* SPARC ELF relocations don't use an addend in the data field. */
3156 if (fixP->fx_addsy != NULL)
3157 {
3158 switch (fixP->fx_r_type)
3159 {
3160 case BFD_RELOC_SPARC_TLS_GD_HI22:
3161 case BFD_RELOC_SPARC_TLS_GD_LO10:
3162 case BFD_RELOC_SPARC_TLS_GD_ADD:
3163 case BFD_RELOC_SPARC_TLS_GD_CALL:
3164 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3165 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3166 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3167 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3168 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3169 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3170 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3171 case BFD_RELOC_SPARC_TLS_IE_HI22:
3172 case BFD_RELOC_SPARC_TLS_IE_LO10:
3173 case BFD_RELOC_SPARC_TLS_IE_LD:
3174 case BFD_RELOC_SPARC_TLS_IE_LDX:
3175 case BFD_RELOC_SPARC_TLS_IE_ADD:
3176 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3177 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3178 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3179 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3180 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3181 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3182 case BFD_RELOC_SPARC_TLS_TPOFF32:
3183 case BFD_RELOC_SPARC_TLS_TPOFF64:
3184 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3185
3186 default:
3187 break;
3188 }
3189
3190 return;
3191 }
3192 #endif
3193
3194 /* This is a hack. There should be a better way to
3195 handle this. Probably in terms of howto fields, once
3196 we can look at these fixups in terms of howtos. */
3197 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3198 val += fixP->fx_where + fixP->fx_frag->fr_address;
3199
3200 #ifdef OBJ_AOUT
3201 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3202 generate a reloc, then we just want to let the reloc addend set
3203 the value. We do not want to also stuff the addend into the
3204 object file. Including the addend in the object file works when
3205 doing a static link, because the linker will ignore the object
3206 file contents. However, the dynamic linker does not ignore the
3207 object file contents. */
3208 if (fixP->fx_addsy != NULL
3209 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3210 val = 0;
3211
3212 /* When generating PIC code, we do not want an addend for a reloc
3213 against a local symbol. We adjust fx_addnumber to cancel out the
3214 value already included in val, and to also cancel out the
3215 adjustment which bfd_install_relocation will create. */
3216 if (sparc_pic_code
3217 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3218 && fixP->fx_addsy != NULL
3219 && ! S_IS_COMMON (fixP->fx_addsy)
3220 && symbol_section_p (fixP->fx_addsy))
3221 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3222
3223 /* When generating PIC code, we need to fiddle to get
3224 bfd_install_relocation to do the right thing for a PC relative
3225 reloc against a local symbol which we are going to keep. */
3226 if (sparc_pic_code
3227 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3228 && fixP->fx_addsy != NULL
3229 && (S_IS_EXTERNAL (fixP->fx_addsy)
3230 || S_IS_WEAK (fixP->fx_addsy))
3231 && S_IS_DEFINED (fixP->fx_addsy)
3232 && ! S_IS_COMMON (fixP->fx_addsy))
3233 {
3234 val = 0;
3235 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3236 }
3237 #endif
3238
3239 /* If this is a data relocation, just output VAL. */
3240
3241 if (fixP->fx_r_type == BFD_RELOC_8)
3242 {
3243 md_number_to_chars (buf, val, 1);
3244 }
3245 else if (fixP->fx_r_type == BFD_RELOC_16
3246 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3247 {
3248 md_number_to_chars (buf, val, 2);
3249 }
3250 else if (fixP->fx_r_type == BFD_RELOC_32
3251 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3252 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3253 {
3254 md_number_to_chars (buf, val, 4);
3255 }
3256 else if (fixP->fx_r_type == BFD_RELOC_64
3257 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3258 {
3259 md_number_to_chars (buf, val, 8);
3260 }
3261 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3262 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3263 {
3264 fixP->fx_done = 0;
3265 return;
3266 }
3267 else
3268 {
3269 /* It's a relocation against an instruction. */
3270
3271 if (INSN_BIG_ENDIAN)
3272 insn = bfd_getb32 ((unsigned char *) buf);
3273 else
3274 insn = bfd_getl32 ((unsigned char *) buf);
3275
3276 switch (fixP->fx_r_type)
3277 {
3278 case BFD_RELOC_32_PCREL_S2:
3279 val = val >> 2;
3280 /* FIXME: This increment-by-one deserves a comment of why it's
3281 being done! */
3282 if (! sparc_pic_code
3283 || fixP->fx_addsy == NULL
3284 || symbol_section_p (fixP->fx_addsy))
3285 ++val;
3286
3287 insn |= val & 0x3fffffff;
3288
3289 /* See if we have a delay slot. */
3290 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3291 {
3292 #define G0 0
3293 #define O7 15
3294 #define XCC (2 << 20)
3295 #define COND(x) (((x)&0xf)<<25)
3296 #define CONDA COND(0x8)
3297 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3298 #define INSN_BA (F2(0,2) | CONDA)
3299 #define INSN_OR F3(2, 0x2, 0)
3300 #define INSN_NOP F2(0,4)
3301
3302 long delay;
3303
3304 /* If the instruction is a call with either:
3305 restore
3306 arithmetic instruction with rd == %o7
3307 where rs1 != %o7 and rs2 if it is register != %o7
3308 then we can optimize if the call destination is near
3309 by changing the call into a branch always. */
3310 if (INSN_BIG_ENDIAN)
3311 delay = bfd_getb32 ((unsigned char *) buf + 4);
3312 else
3313 delay = bfd_getl32 ((unsigned char *) buf + 4);
3314 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3315 break;
3316 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3317 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3318 || ((delay & RD (~0)) != RD (O7))))
3319 break;
3320 if ((delay & RS1 (~0)) == RS1 (O7)
3321 || ((delay & F3I (~0)) == 0
3322 && (delay & RS2 (~0)) == RS2 (O7)))
3323 break;
3324 /* Ensure the branch will fit into simm22. */
3325 if ((val & 0x3fe00000)
3326 && (val & 0x3fe00000) != 0x3fe00000)
3327 break;
3328 /* Check if the arch is v9 and branch will fit
3329 into simm19. */
3330 if (((val & 0x3c0000) == 0
3331 || (val & 0x3c0000) == 0x3c0000)
3332 && (sparc_arch_size == 64
3333 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3334 /* ba,pt %xcc */
3335 insn = INSN_BPA | (val & 0x7ffff);
3336 else
3337 /* ba */
3338 insn = INSN_BA | (val & 0x3fffff);
3339 if (fixP->fx_where >= 4
3340 && ((delay & (0xffffffff ^ RS1 (~0)))
3341 == (INSN_OR | RD (O7) | RS2 (G0))))
3342 {
3343 long setter;
3344 int reg;
3345
3346 if (INSN_BIG_ENDIAN)
3347 setter = bfd_getb32 ((unsigned char *) buf - 4);
3348 else
3349 setter = bfd_getl32 ((unsigned char *) buf - 4);
3350 if ((setter & (0xffffffff ^ RD (~0)))
3351 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3352 break;
3353 /* The sequence was
3354 or %o7, %g0, %rN
3355 call foo
3356 or %rN, %g0, %o7
3357
3358 If call foo was replaced with ba, replace
3359 or %rN, %g0, %o7 with nop. */
3360 reg = (delay & RS1 (~0)) >> 14;
3361 if (reg != ((setter & RD (~0)) >> 25)
3362 || reg == G0 || reg == O7)
3363 break;
3364
3365 if (INSN_BIG_ENDIAN)
3366 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3367 else
3368 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3369 }
3370 }
3371 break;
3372
3373 case BFD_RELOC_SPARC_11:
3374 if (! in_signed_range (val, 0x7ff))
3375 as_bad_where (fixP->fx_file, fixP->fx_line,
3376 _("relocation overflow"));
3377 insn |= val & 0x7ff;
3378 break;
3379
3380 case BFD_RELOC_SPARC_10:
3381 if (! in_signed_range (val, 0x3ff))
3382 as_bad_where (fixP->fx_file, fixP->fx_line,
3383 _("relocation overflow"));
3384 insn |= val & 0x3ff;
3385 break;
3386
3387 case BFD_RELOC_SPARC_7:
3388 if (! in_bitfield_range (val, 0x7f))
3389 as_bad_where (fixP->fx_file, fixP->fx_line,
3390 _("relocation overflow"));
3391 insn |= val & 0x7f;
3392 break;
3393
3394 case BFD_RELOC_SPARC_6:
3395 if (! in_bitfield_range (val, 0x3f))
3396 as_bad_where (fixP->fx_file, fixP->fx_line,
3397 _("relocation overflow"));
3398 insn |= val & 0x3f;
3399 break;
3400
3401 case BFD_RELOC_SPARC_5:
3402 if (! in_bitfield_range (val, 0x1f))
3403 as_bad_where (fixP->fx_file, fixP->fx_line,
3404 _("relocation overflow"));
3405 insn |= val & 0x1f;
3406 break;
3407
3408 case BFD_RELOC_SPARC_WDISP10:
3409 if ((val & 3)
3410 || val >= 0x007fc
3411 || val <= -(offsetT) 0x808)
3412 as_bad_where (fixP->fx_file, fixP->fx_line,
3413 _("relocation overflow"));
3414 /* FIXME: The +1 deserves a comment. */
3415 val = (val >> 2) + 1;
3416 insn |= ((val & 0x300) << 11)
3417 | ((val & 0xff) << 5);
3418 break;
3419
3420 case BFD_RELOC_SPARC_WDISP16:
3421 if ((val & 3)
3422 || val >= 0x1fffc
3423 || val <= -(offsetT) 0x20008)
3424 as_bad_where (fixP->fx_file, fixP->fx_line,
3425 _("relocation overflow"));
3426 /* FIXME: The +1 deserves a comment. */
3427 val = (val >> 2) + 1;
3428 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3429 break;
3430
3431 case BFD_RELOC_SPARC_WDISP19:
3432 if ((val & 3)
3433 || val >= 0xffffc
3434 || val <= -(offsetT) 0x100008)
3435 as_bad_where (fixP->fx_file, fixP->fx_line,
3436 _("relocation overflow"));
3437 /* FIXME: The +1 deserves a comment. */
3438 val = (val >> 2) + 1;
3439 insn |= val & 0x7ffff;
3440 break;
3441
3442 case BFD_RELOC_SPARC_HH22:
3443 val = BSR (val, 32);
3444 /* Fall through. */
3445
3446 case BFD_RELOC_SPARC_LM22:
3447 case BFD_RELOC_HI22:
3448 if (!fixP->fx_addsy)
3449 insn |= (val >> 10) & 0x3fffff;
3450 else
3451 /* FIXME: Need comment explaining why we do this. */
3452 insn &= ~0xffff;
3453 break;
3454
3455 case BFD_RELOC_SPARC22:
3456 if (val & ~0x003fffff)
3457 as_bad_where (fixP->fx_file, fixP->fx_line,
3458 _("relocation overflow"));
3459 insn |= (val & 0x3fffff);
3460 break;
3461
3462 case BFD_RELOC_SPARC_HM10:
3463 val = BSR (val, 32);
3464 /* Fall through. */
3465
3466 case BFD_RELOC_LO10:
3467 if (!fixP->fx_addsy)
3468 insn |= val & 0x3ff;
3469 else
3470 /* FIXME: Need comment explaining why we do this. */
3471 insn &= ~0xff;
3472 break;
3473
3474 case BFD_RELOC_SPARC_OLO10:
3475 val &= 0x3ff;
3476 val += fixP->tc_fix_data;
3477 /* Fall through. */
3478
3479 case BFD_RELOC_SPARC13:
3480 if (! in_signed_range (val, 0x1fff))
3481 as_bad_where (fixP->fx_file, fixP->fx_line,
3482 _("relocation overflow"));
3483 insn |= val & 0x1fff;
3484 break;
3485
3486 case BFD_RELOC_SPARC_WDISP22:
3487 val = (val >> 2) + 1;
3488 /* Fall through. */
3489 case BFD_RELOC_SPARC_BASE22:
3490 insn |= val & 0x3fffff;
3491 break;
3492
3493 case BFD_RELOC_SPARC_H34:
3494 if (!fixP->fx_addsy)
3495 {
3496 bfd_vma tval = val;
3497 tval >>= 12;
3498 insn |= tval & 0x3fffff;
3499 }
3500 break;
3501
3502 case BFD_RELOC_SPARC_H44:
3503 if (!fixP->fx_addsy)
3504 {
3505 bfd_vma tval = val;
3506 tval >>= 22;
3507 insn |= tval & 0x3fffff;
3508 }
3509 break;
3510
3511 case BFD_RELOC_SPARC_M44:
3512 if (!fixP->fx_addsy)
3513 insn |= (val >> 12) & 0x3ff;
3514 break;
3515
3516 case BFD_RELOC_SPARC_L44:
3517 if (!fixP->fx_addsy)
3518 insn |= val & 0xfff;
3519 break;
3520
3521 case BFD_RELOC_SPARC_HIX22:
3522 if (!fixP->fx_addsy)
3523 {
3524 val ^= ~(offsetT) 0;
3525 insn |= (val >> 10) & 0x3fffff;
3526 }
3527 break;
3528
3529 case BFD_RELOC_SPARC_LOX10:
3530 if (!fixP->fx_addsy)
3531 insn |= 0x1c00 | (val & 0x3ff);
3532 break;
3533
3534 case BFD_RELOC_NONE:
3535 default:
3536 as_bad_where (fixP->fx_file, fixP->fx_line,
3537 _("bad or unhandled relocation type: 0x%02x"),
3538 fixP->fx_r_type);
3539 break;
3540 }
3541
3542 if (INSN_BIG_ENDIAN)
3543 bfd_putb32 (insn, (unsigned char *) buf);
3544 else
3545 bfd_putl32 (insn, (unsigned char *) buf);
3546 }
3547
3548 /* Are we finished with this relocation now? */
3549 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3550 fixP->fx_done = 1;
3551 }
3552
3553 /* Translate internal representation of relocation info to BFD target
3554 format. */
3555
3556 arelent **
3557 tc_gen_reloc (asection *section, fixS *fixp)
3558 {
3559 static arelent *relocs[3];
3560 arelent *reloc;
3561 bfd_reloc_code_real_type code;
3562
3563 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3564 relocs[1] = NULL;
3565
3566 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3567 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3568 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3569
3570 switch (fixp->fx_r_type)
3571 {
3572 case BFD_RELOC_16:
3573 case BFD_RELOC_32:
3574 case BFD_RELOC_HI22:
3575 case BFD_RELOC_LO10:
3576 case BFD_RELOC_32_PCREL_S2:
3577 case BFD_RELOC_SPARC13:
3578 case BFD_RELOC_SPARC22:
3579 case BFD_RELOC_SPARC_PC22:
3580 case BFD_RELOC_SPARC_PC10:
3581 case BFD_RELOC_SPARC_BASE13:
3582 case BFD_RELOC_SPARC_WDISP10:
3583 case BFD_RELOC_SPARC_WDISP16:
3584 case BFD_RELOC_SPARC_WDISP19:
3585 case BFD_RELOC_SPARC_WDISP22:
3586 case BFD_RELOC_64:
3587 case BFD_RELOC_SPARC_5:
3588 case BFD_RELOC_SPARC_6:
3589 case BFD_RELOC_SPARC_7:
3590 case BFD_RELOC_SPARC_10:
3591 case BFD_RELOC_SPARC_11:
3592 case BFD_RELOC_SPARC_HH22:
3593 case BFD_RELOC_SPARC_HM10:
3594 case BFD_RELOC_SPARC_LM22:
3595 case BFD_RELOC_SPARC_PC_HH22:
3596 case BFD_RELOC_SPARC_PC_HM10:
3597 case BFD_RELOC_SPARC_PC_LM22:
3598 case BFD_RELOC_SPARC_H34:
3599 case BFD_RELOC_SPARC_H44:
3600 case BFD_RELOC_SPARC_M44:
3601 case BFD_RELOC_SPARC_L44:
3602 case BFD_RELOC_SPARC_HIX22:
3603 case BFD_RELOC_SPARC_LOX10:
3604 case BFD_RELOC_SPARC_REV32:
3605 case BFD_RELOC_SPARC_OLO10:
3606 case BFD_RELOC_SPARC_UA16:
3607 case BFD_RELOC_SPARC_UA32:
3608 case BFD_RELOC_SPARC_UA64:
3609 case BFD_RELOC_8_PCREL:
3610 case BFD_RELOC_16_PCREL:
3611 case BFD_RELOC_32_PCREL:
3612 case BFD_RELOC_64_PCREL:
3613 case BFD_RELOC_SPARC_PLT32:
3614 case BFD_RELOC_SPARC_PLT64:
3615 case BFD_RELOC_VTABLE_ENTRY:
3616 case BFD_RELOC_VTABLE_INHERIT:
3617 case BFD_RELOC_SPARC_TLS_GD_HI22:
3618 case BFD_RELOC_SPARC_TLS_GD_LO10:
3619 case BFD_RELOC_SPARC_TLS_GD_ADD:
3620 case BFD_RELOC_SPARC_TLS_GD_CALL:
3621 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3622 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3623 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3624 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3625 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3626 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3627 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3628 case BFD_RELOC_SPARC_TLS_IE_HI22:
3629 case BFD_RELOC_SPARC_TLS_IE_LO10:
3630 case BFD_RELOC_SPARC_TLS_IE_LD:
3631 case BFD_RELOC_SPARC_TLS_IE_LDX:
3632 case BFD_RELOC_SPARC_TLS_IE_ADD:
3633 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3634 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3635 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3636 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3637 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3638 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3639 case BFD_RELOC_SPARC_GOTDATA_OP:
3640 code = fixp->fx_r_type;
3641 break;
3642 default:
3643 abort ();
3644 return NULL;
3645 }
3646
3647 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3648 /* If we are generating PIC code, we need to generate a different
3649 set of relocs. */
3650
3651 #ifdef OBJ_ELF
3652 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3653 #else
3654 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3655 #endif
3656 #ifdef TE_VXWORKS
3657 #define GOTT_BASE "__GOTT_BASE__"
3658 #define GOTT_INDEX "__GOTT_INDEX__"
3659 #endif
3660
3661 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3662
3663 if (sparc_pic_code)
3664 {
3665 switch (code)
3666 {
3667 case BFD_RELOC_32_PCREL_S2:
3668 if (generic_force_reloc (fixp))
3669 code = BFD_RELOC_SPARC_WPLT30;
3670 break;
3671 case BFD_RELOC_HI22:
3672 code = BFD_RELOC_SPARC_GOT22;
3673 if (fixp->fx_addsy != NULL)
3674 {
3675 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3676 code = BFD_RELOC_SPARC_PC22;
3677 #ifdef TE_VXWORKS
3678 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3679 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3680 code = BFD_RELOC_HI22; /* Unchanged. */
3681 #endif
3682 }
3683 break;
3684 case BFD_RELOC_LO10:
3685 code = BFD_RELOC_SPARC_GOT10;
3686 if (fixp->fx_addsy != NULL)
3687 {
3688 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3689 code = BFD_RELOC_SPARC_PC10;
3690 #ifdef TE_VXWORKS
3691 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3692 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3693 code = BFD_RELOC_LO10; /* Unchanged. */
3694 #endif
3695 }
3696 break;
3697 case BFD_RELOC_SPARC13:
3698 code = BFD_RELOC_SPARC_GOT13;
3699 break;
3700 default:
3701 break;
3702 }
3703 }
3704 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3705
3706 /* Nothing is aligned in DWARF debugging sections. */
3707 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3708 switch (code)
3709 {
3710 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3711 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3712 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3713 default: break;
3714 }
3715
3716 if (code == BFD_RELOC_SPARC_OLO10)
3717 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3718 else
3719 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3720 if (reloc->howto == 0)
3721 {
3722 as_bad_where (fixp->fx_file, fixp->fx_line,
3723 _("internal error: can't export reloc type %d (`%s')"),
3724 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3725 xfree (reloc);
3726 relocs[0] = NULL;
3727 return relocs;
3728 }
3729
3730 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3731 #ifdef OBJ_AOUT
3732
3733 if (reloc->howto->pc_relative == 0
3734 || code == BFD_RELOC_SPARC_PC10
3735 || code == BFD_RELOC_SPARC_PC22)
3736 reloc->addend = fixp->fx_addnumber;
3737 else if (sparc_pic_code
3738 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3739 && fixp->fx_addsy != NULL
3740 && (S_IS_EXTERNAL (fixp->fx_addsy)
3741 || S_IS_WEAK (fixp->fx_addsy))
3742 && S_IS_DEFINED (fixp->fx_addsy)
3743 && ! S_IS_COMMON (fixp->fx_addsy))
3744 reloc->addend = fixp->fx_addnumber;
3745 else
3746 reloc->addend = fixp->fx_offset - reloc->address;
3747
3748 #else /* elf or coff */
3749
3750 if (code != BFD_RELOC_32_PCREL_S2
3751 && code != BFD_RELOC_SPARC_WDISP22
3752 && code != BFD_RELOC_SPARC_WDISP16
3753 && code != BFD_RELOC_SPARC_WDISP19
3754 && code != BFD_RELOC_SPARC_WDISP10
3755 && code != BFD_RELOC_SPARC_WPLT30
3756 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3757 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3758 reloc->addend = fixp->fx_addnumber;
3759 else if (symbol_section_p (fixp->fx_addsy))
3760 reloc->addend = (section->vma
3761 + fixp->fx_addnumber
3762 + md_pcrel_from (fixp));
3763 else
3764 reloc->addend = fixp->fx_offset;
3765 #endif
3766
3767 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3768 on the same location. */
3769 if (code == BFD_RELOC_SPARC_OLO10)
3770 {
3771 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3772 relocs[2] = NULL;
3773
3774 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3775 *reloc->sym_ptr_ptr
3776 = symbol_get_bfdsym (section_symbol (absolute_section));
3777 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3778 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3779 reloc->addend = fixp->tc_fix_data;
3780 }
3781
3782 return relocs;
3783 }
3784 \f
3785 /* We have no need to default values of symbols. */
3786
3787 symbolS *
3788 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3789 {
3790 return 0;
3791 }
3792
3793 /* Round up a section size to the appropriate boundary. */
3794
3795 valueT
3796 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3797 {
3798 #ifndef OBJ_ELF
3799 /* This is not right for ELF; a.out wants it, and COFF will force
3800 the alignment anyways. */
3801 valueT align = ((valueT) 1
3802 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3803 valueT newsize;
3804
3805 /* Turn alignment value into a mask. */
3806 align--;
3807 newsize = (size + align) & ~align;
3808 return newsize;
3809 #else
3810 return size;
3811 #endif
3812 }
3813
3814 /* Exactly what point is a PC-relative offset relative TO?
3815 On the sparc, they're relative to the address of the offset, plus
3816 its size. This gets us to the following instruction.
3817 (??? Is this right? FIXME-SOON) */
3818 long
3819 md_pcrel_from (fixS *fixP)
3820 {
3821 long ret;
3822
3823 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3824 if (! sparc_pic_code
3825 || fixP->fx_addsy == NULL
3826 || symbol_section_p (fixP->fx_addsy))
3827 ret += fixP->fx_size;
3828 return ret;
3829 }
3830 \f
3831 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3832 of two. */
3833
3834 static int
3835 mylog2 (int value)
3836 {
3837 int shift;
3838
3839 if (value <= 0)
3840 return -1;
3841
3842 for (shift = 0; (value & 1) == 0; value >>= 1)
3843 ++shift;
3844
3845 return (value == 1) ? shift : -1;
3846 }
3847
3848 /* Sort of like s_lcomm. */
3849
3850 #ifndef OBJ_ELF
3851 static int max_alignment = 15;
3852 #endif
3853
3854 static void
3855 s_reserve (int ignore ATTRIBUTE_UNUSED)
3856 {
3857 char *name;
3858 char *p;
3859 char c;
3860 int align;
3861 int size;
3862 int temp;
3863 symbolS *symbolP;
3864
3865 name = input_line_pointer;
3866 c = get_symbol_end ();
3867 p = input_line_pointer;
3868 *p = c;
3869 SKIP_WHITESPACE ();
3870
3871 if (*input_line_pointer != ',')
3872 {
3873 as_bad (_("Expected comma after name"));
3874 ignore_rest_of_line ();
3875 return;
3876 }
3877
3878 ++input_line_pointer;
3879
3880 if ((size = get_absolute_expression ()) < 0)
3881 {
3882 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3883 ignore_rest_of_line ();
3884 return;
3885 } /* Bad length. */
3886
3887 *p = 0;
3888 symbolP = symbol_find_or_make (name);
3889 *p = c;
3890
3891 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3892 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3893 {
3894 as_bad (_("bad .reserve segment -- expected BSS segment"));
3895 return;
3896 }
3897
3898 if (input_line_pointer[2] == '.')
3899 input_line_pointer += 7;
3900 else
3901 input_line_pointer += 6;
3902 SKIP_WHITESPACE ();
3903
3904 if (*input_line_pointer == ',')
3905 {
3906 ++input_line_pointer;
3907
3908 SKIP_WHITESPACE ();
3909 if (*input_line_pointer == '\n')
3910 {
3911 as_bad (_("missing alignment"));
3912 ignore_rest_of_line ();
3913 return;
3914 }
3915
3916 align = (int) get_absolute_expression ();
3917
3918 #ifndef OBJ_ELF
3919 if (align > max_alignment)
3920 {
3921 align = max_alignment;
3922 as_warn (_("alignment too large; assuming %d"), align);
3923 }
3924 #endif
3925
3926 if (align < 0)
3927 {
3928 as_bad (_("negative alignment"));
3929 ignore_rest_of_line ();
3930 return;
3931 }
3932
3933 if (align != 0)
3934 {
3935 temp = mylog2 (align);
3936 if (temp < 0)
3937 {
3938 as_bad (_("alignment not a power of 2"));
3939 ignore_rest_of_line ();
3940 return;
3941 }
3942
3943 align = temp;
3944 }
3945
3946 record_alignment (bss_section, align);
3947 }
3948 else
3949 align = 0;
3950
3951 if (!S_IS_DEFINED (symbolP)
3952 #ifdef OBJ_AOUT
3953 && S_GET_OTHER (symbolP) == 0
3954 && S_GET_DESC (symbolP) == 0
3955 #endif
3956 )
3957 {
3958 if (! need_pass_2)
3959 {
3960 char *pfrag;
3961 segT current_seg = now_seg;
3962 subsegT current_subseg = now_subseg;
3963
3964 /* Switch to bss. */
3965 subseg_set (bss_section, 1);
3966
3967 if (align)
3968 /* Do alignment. */
3969 frag_align (align, 0, 0);
3970
3971 /* Detach from old frag. */
3972 if (S_GET_SEGMENT (symbolP) == bss_section)
3973 symbol_get_frag (symbolP)->fr_symbol = NULL;
3974
3975 symbol_set_frag (symbolP, frag_now);
3976 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3977 (offsetT) size, (char *) 0);
3978 *pfrag = 0;
3979
3980 S_SET_SEGMENT (symbolP, bss_section);
3981
3982 subseg_set (current_seg, current_subseg);
3983
3984 #ifdef OBJ_ELF
3985 S_SET_SIZE (symbolP, size);
3986 #endif
3987 }
3988 }
3989 else
3990 {
3991 as_warn (_("Ignoring attempt to re-define symbol %s"),
3992 S_GET_NAME (symbolP));
3993 }
3994
3995 demand_empty_rest_of_line ();
3996 }
3997
3998 static void
3999 s_common (int ignore ATTRIBUTE_UNUSED)
4000 {
4001 char *name;
4002 char c;
4003 char *p;
4004 offsetT temp, size;
4005 symbolS *symbolP;
4006
4007 name = input_line_pointer;
4008 c = get_symbol_end ();
4009 /* Just after name is now '\0'. */
4010 p = input_line_pointer;
4011 *p = c;
4012 SKIP_WHITESPACE ();
4013 if (*input_line_pointer != ',')
4014 {
4015 as_bad (_("Expected comma after symbol-name"));
4016 ignore_rest_of_line ();
4017 return;
4018 }
4019
4020 /* Skip ','. */
4021 input_line_pointer++;
4022
4023 if ((temp = get_absolute_expression ()) < 0)
4024 {
4025 as_bad (_(".COMMon length (%lu) out of range ignored"),
4026 (unsigned long) temp);
4027 ignore_rest_of_line ();
4028 return;
4029 }
4030 size = temp;
4031 *p = 0;
4032 symbolP = symbol_find_or_make (name);
4033 *p = c;
4034 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4035 {
4036 as_bad (_("Ignoring attempt to re-define symbol"));
4037 ignore_rest_of_line ();
4038 return;
4039 }
4040 if (S_GET_VALUE (symbolP) != 0)
4041 {
4042 if (S_GET_VALUE (symbolP) != (valueT) size)
4043 {
4044 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4045 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4046 }
4047 }
4048 else
4049 {
4050 #ifndef OBJ_ELF
4051 S_SET_VALUE (symbolP, (valueT) size);
4052 S_SET_EXTERNAL (symbolP);
4053 #endif
4054 }
4055 know (symbol_get_frag (symbolP) == &zero_address_frag);
4056 if (*input_line_pointer != ',')
4057 {
4058 as_bad (_("Expected comma after common length"));
4059 ignore_rest_of_line ();
4060 return;
4061 }
4062 input_line_pointer++;
4063 SKIP_WHITESPACE ();
4064 if (*input_line_pointer != '"')
4065 {
4066 temp = get_absolute_expression ();
4067
4068 #ifndef OBJ_ELF
4069 if (temp > max_alignment)
4070 {
4071 temp = max_alignment;
4072 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4073 }
4074 #endif
4075
4076 if (temp < 0)
4077 {
4078 as_bad (_("negative alignment"));
4079 ignore_rest_of_line ();
4080 return;
4081 }
4082
4083 #ifdef OBJ_ELF
4084 if (symbol_get_obj (symbolP)->local)
4085 {
4086 segT old_sec;
4087 int old_subsec;
4088 int align;
4089
4090 old_sec = now_seg;
4091 old_subsec = now_subseg;
4092
4093 if (temp == 0)
4094 align = 0;
4095 else
4096 align = mylog2 (temp);
4097
4098 if (align < 0)
4099 {
4100 as_bad (_("alignment not a power of 2"));
4101 ignore_rest_of_line ();
4102 return;
4103 }
4104
4105 record_alignment (bss_section, align);
4106 subseg_set (bss_section, 0);
4107 if (align)
4108 frag_align (align, 0, 0);
4109 if (S_GET_SEGMENT (symbolP) == bss_section)
4110 symbol_get_frag (symbolP)->fr_symbol = 0;
4111 symbol_set_frag (symbolP, frag_now);
4112 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4113 (offsetT) size, (char *) 0);
4114 *p = 0;
4115 S_SET_SEGMENT (symbolP, bss_section);
4116 S_CLEAR_EXTERNAL (symbolP);
4117 S_SET_SIZE (symbolP, size);
4118 subseg_set (old_sec, old_subsec);
4119 }
4120 else
4121 #endif /* OBJ_ELF */
4122 {
4123 allocate_common:
4124 S_SET_VALUE (symbolP, (valueT) size);
4125 #ifdef OBJ_ELF
4126 S_SET_ALIGN (symbolP, temp);
4127 S_SET_SIZE (symbolP, size);
4128 #endif
4129 S_SET_EXTERNAL (symbolP);
4130 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4131 }
4132 }
4133 else
4134 {
4135 input_line_pointer++;
4136 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4137 if (*input_line_pointer == '.')
4138 input_line_pointer++;
4139 /* @@ Some say data, some say bss. */
4140 if (strncmp (input_line_pointer, "bss\"", 4)
4141 && strncmp (input_line_pointer, "data\"", 5))
4142 {
4143 while (*--input_line_pointer != '"')
4144 ;
4145 input_line_pointer--;
4146 goto bad_common_segment;
4147 }
4148 while (*input_line_pointer++ != '"')
4149 ;
4150 goto allocate_common;
4151 }
4152
4153 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4154
4155 demand_empty_rest_of_line ();
4156 return;
4157
4158 {
4159 bad_common_segment:
4160 p = input_line_pointer;
4161 while (*p && *p != '\n')
4162 p++;
4163 c = *p;
4164 *p = '\0';
4165 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4166 *p = c;
4167 input_line_pointer = p;
4168 ignore_rest_of_line ();
4169 return;
4170 }
4171 }
4172
4173 /* Handle the .empty pseudo-op. This suppresses the warnings about
4174 invalid delay slot usage. */
4175
4176 static void
4177 s_empty (int ignore ATTRIBUTE_UNUSED)
4178 {
4179 /* The easy way to implement is to just forget about the last
4180 instruction. */
4181 last_insn = NULL;
4182 }
4183
4184 static void
4185 s_seg (int ignore ATTRIBUTE_UNUSED)
4186 {
4187
4188 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4189 {
4190 input_line_pointer += 6;
4191 s_text (0);
4192 return;
4193 }
4194 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4195 {
4196 input_line_pointer += 6;
4197 s_data (0);
4198 return;
4199 }
4200 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4201 {
4202 input_line_pointer += 7;
4203 s_data1 ();
4204 return;
4205 }
4206 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4207 {
4208 input_line_pointer += 5;
4209 /* We only support 2 segments -- text and data -- for now, so
4210 things in the "bss segment" will have to go into data for now.
4211 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4212 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4213 return;
4214 }
4215 as_bad (_("Unknown segment type"));
4216 demand_empty_rest_of_line ();
4217 }
4218
4219 static void
4220 s_data1 (void)
4221 {
4222 subseg_set (data_section, 1);
4223 demand_empty_rest_of_line ();
4224 }
4225
4226 static void
4227 s_proc (int ignore ATTRIBUTE_UNUSED)
4228 {
4229 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4230 {
4231 ++input_line_pointer;
4232 }
4233 ++input_line_pointer;
4234 }
4235
4236 /* This static variable is set by s_uacons to tell sparc_cons_align
4237 that the expression does not need to be aligned. */
4238
4239 static int sparc_no_align_cons = 0;
4240
4241 /* This static variable is set by sparc_cons to emit requested types
4242 of relocations in cons_fix_new_sparc. */
4243
4244 static const char *sparc_cons_special_reloc;
4245
4246 /* This handles the unaligned space allocation pseudo-ops, such as
4247 .uaword. .uaword is just like .word, but the value does not need
4248 to be aligned. */
4249
4250 static void
4251 s_uacons (int bytes)
4252 {
4253 /* Tell sparc_cons_align not to align this value. */
4254 sparc_no_align_cons = 1;
4255 cons (bytes);
4256 sparc_no_align_cons = 0;
4257 }
4258
4259 /* This handles the native word allocation pseudo-op .nword.
4260 For sparc_arch_size 32 it is equivalent to .word, for
4261 sparc_arch_size 64 it is equivalent to .xword. */
4262
4263 static void
4264 s_ncons (int bytes ATTRIBUTE_UNUSED)
4265 {
4266 cons (sparc_arch_size == 32 ? 4 : 8);
4267 }
4268
4269 #ifdef OBJ_ELF
4270 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4271 global register.
4272 The syntax is:
4273
4274 .register %g[2367],{#scratch|symbolname|#ignore}
4275 */
4276
4277 static void
4278 s_register (int ignore ATTRIBUTE_UNUSED)
4279 {
4280 char c;
4281 int reg;
4282 int flags;
4283 const char *regname;
4284
4285 if (input_line_pointer[0] != '%'
4286 || input_line_pointer[1] != 'g'
4287 || ((input_line_pointer[2] & ~1) != '2'
4288 && (input_line_pointer[2] & ~1) != '6')
4289 || input_line_pointer[3] != ',')
4290 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4291 reg = input_line_pointer[2] - '0';
4292 input_line_pointer += 4;
4293
4294 if (*input_line_pointer == '#')
4295 {
4296 ++input_line_pointer;
4297 regname = input_line_pointer;
4298 c = get_symbol_end ();
4299 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4300 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4301 if (regname[0] == 'i')
4302 regname = NULL;
4303 else
4304 regname = "";
4305 }
4306 else
4307 {
4308 regname = input_line_pointer;
4309 c = get_symbol_end ();
4310 }
4311 if (sparc_arch_size == 64)
4312 {
4313 if (globals[reg])
4314 {
4315 if ((regname && globals[reg] != (symbolS *) 1
4316 && strcmp (S_GET_NAME (globals[reg]), regname))
4317 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4318 as_bad (_("redefinition of global register"));
4319 }
4320 else
4321 {
4322 if (regname == NULL)
4323 globals[reg] = (symbolS *) 1;
4324 else
4325 {
4326 if (*regname)
4327 {
4328 if (symbol_find (regname))
4329 as_bad (_("Register symbol %s already defined."),
4330 regname);
4331 }
4332 globals[reg] = symbol_make (regname);
4333 flags = symbol_get_bfdsym (globals[reg])->flags;
4334 if (! *regname)
4335 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4336 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4337 flags |= BSF_GLOBAL;
4338 symbol_get_bfdsym (globals[reg])->flags = flags;
4339 S_SET_VALUE (globals[reg], (valueT) reg);
4340 S_SET_ALIGN (globals[reg], reg);
4341 S_SET_SIZE (globals[reg], 0);
4342 /* Although we actually want undefined_section here,
4343 we have to use absolute_section, because otherwise
4344 generic as code will make it a COM section.
4345 We fix this up in sparc_adjust_symtab. */
4346 S_SET_SEGMENT (globals[reg], absolute_section);
4347 S_SET_OTHER (globals[reg], 0);
4348 elf_symbol (symbol_get_bfdsym (globals[reg]))
4349 ->internal_elf_sym.st_info =
4350 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4351 elf_symbol (symbol_get_bfdsym (globals[reg]))
4352 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4353 }
4354 }
4355 }
4356
4357 *input_line_pointer = c;
4358
4359 demand_empty_rest_of_line ();
4360 }
4361
4362 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4363 symbols which need it. */
4364
4365 void
4366 sparc_adjust_symtab (void)
4367 {
4368 symbolS *sym;
4369
4370 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4371 {
4372 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4373 ->internal_elf_sym.st_info) != STT_REGISTER)
4374 continue;
4375
4376 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4377 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4378 continue;
4379
4380 S_SET_SEGMENT (sym, undefined_section);
4381 }
4382 }
4383 #endif
4384
4385 /* If the --enforce-aligned-data option is used, we require .word,
4386 et. al., to be aligned correctly. We do it by setting up an
4387 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4388 no unexpected alignment was introduced.
4389
4390 The SunOS and Solaris native assemblers enforce aligned data by
4391 default. We don't want to do that, because gcc can deliberately
4392 generate misaligned data if the packed attribute is used. Instead,
4393 we permit misaligned data by default, and permit the user to set an
4394 option to check for it. */
4395
4396 void
4397 sparc_cons_align (int nbytes)
4398 {
4399 int nalign;
4400
4401 /* Only do this if we are enforcing aligned data. */
4402 if (! enforce_aligned_data)
4403 return;
4404
4405 /* Don't align if this is an unaligned pseudo-op. */
4406 if (sparc_no_align_cons)
4407 return;
4408
4409 nalign = mylog2 (nbytes);
4410 if (nalign == 0)
4411 return;
4412
4413 gas_assert (nalign > 0);
4414
4415 if (now_seg == absolute_section)
4416 {
4417 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4418 as_bad (_("misaligned data"));
4419 return;
4420 }
4421
4422 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4423 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4424
4425 record_alignment (now_seg, nalign);
4426 }
4427
4428 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4429
4430 void
4431 sparc_handle_align (fragS *fragp)
4432 {
4433 int count, fix;
4434 char *p;
4435
4436 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4437
4438 switch (fragp->fr_type)
4439 {
4440 case rs_align_test:
4441 if (count != 0)
4442 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4443 break;
4444
4445 case rs_align_code:
4446 p = fragp->fr_literal + fragp->fr_fix;
4447 fix = 0;
4448
4449 if (count & 3)
4450 {
4451 fix = count & 3;
4452 memset (p, 0, fix);
4453 p += fix;
4454 count -= fix;
4455 }
4456
4457 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4458 {
4459 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4460 if (INSN_BIG_ENDIAN)
4461 number_to_chars_bigendian (p, wval, 4);
4462 else
4463 number_to_chars_littleendian (p, wval, 4);
4464 p += 4;
4465 count -= 4;
4466 fix += 4;
4467 }
4468
4469 if (INSN_BIG_ENDIAN)
4470 number_to_chars_bigendian (p, 0x01000000, 4);
4471 else
4472 number_to_chars_littleendian (p, 0x01000000, 4);
4473
4474 fragp->fr_fix += fix;
4475 fragp->fr_var = 4;
4476 break;
4477
4478 default:
4479 break;
4480 }
4481 }
4482
4483 #ifdef OBJ_ELF
4484 /* Some special processing for a Sparc ELF file. */
4485
4486 void
4487 sparc_elf_final_processing (void)
4488 {
4489 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4490 sort of BFD interface for this. */
4491 if (sparc_arch_size == 64)
4492 {
4493 switch (sparc_memory_model)
4494 {
4495 case MM_RMO:
4496 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4497 break;
4498 case MM_PSO:
4499 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4500 break;
4501 default:
4502 break;
4503 }
4504 }
4505 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4506 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4507 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4508 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4509 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4510 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4511 }
4512
4513 void
4514 sparc_cons (expressionS *exp, int size)
4515 {
4516 char *save;
4517
4518 SKIP_WHITESPACE ();
4519 sparc_cons_special_reloc = NULL;
4520 save = input_line_pointer;
4521 if (input_line_pointer[0] == '%'
4522 && input_line_pointer[1] == 'r'
4523 && input_line_pointer[2] == '_')
4524 {
4525 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4526 {
4527 input_line_pointer += 7;
4528 sparc_cons_special_reloc = "disp";
4529 }
4530 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4531 {
4532 if (size != 4 && size != 8)
4533 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4534 else
4535 {
4536 input_line_pointer += 6;
4537 sparc_cons_special_reloc = "plt";
4538 }
4539 }
4540 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4541 {
4542 if (size != 4 && size != 8)
4543 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4544 else
4545 {
4546 input_line_pointer += 13;
4547 sparc_cons_special_reloc = "tls_dtpoff";
4548 }
4549 }
4550 if (sparc_cons_special_reloc)
4551 {
4552 int bad = 0;
4553
4554 switch (size)
4555 {
4556 case 1:
4557 if (*input_line_pointer != '8')
4558 bad = 1;
4559 input_line_pointer--;
4560 break;
4561 case 2:
4562 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4563 bad = 1;
4564 break;
4565 case 4:
4566 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4567 bad = 1;
4568 break;
4569 case 8:
4570 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4571 bad = 1;
4572 break;
4573 default:
4574 bad = 1;
4575 break;
4576 }
4577
4578 if (bad)
4579 {
4580 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4581 sparc_cons_special_reloc, size * 8, size);
4582 }
4583 else
4584 {
4585 input_line_pointer += 2;
4586 if (*input_line_pointer != '(')
4587 {
4588 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4589 sparc_cons_special_reloc, size * 8);
4590 bad = 1;
4591 }
4592 }
4593
4594 if (bad)
4595 {
4596 input_line_pointer = save;
4597 sparc_cons_special_reloc = NULL;
4598 }
4599 else
4600 {
4601 int c;
4602 char *end = ++input_line_pointer;
4603 int npar = 0;
4604
4605 while (! is_end_of_line[(c = *end)])
4606 {
4607 if (c == '(')
4608 npar++;
4609 else if (c == ')')
4610 {
4611 if (!npar)
4612 break;
4613 npar--;
4614 }
4615 end++;
4616 }
4617
4618 if (c != ')')
4619 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4620 sparc_cons_special_reloc, size * 8);
4621 else
4622 {
4623 *end = '\0';
4624 expression (exp);
4625 *end = c;
4626 if (input_line_pointer != end)
4627 {
4628 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4629 sparc_cons_special_reloc, size * 8);
4630 }
4631 else
4632 {
4633 input_line_pointer++;
4634 SKIP_WHITESPACE ();
4635 c = *input_line_pointer;
4636 if (! is_end_of_line[c] && c != ',')
4637 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4638 sparc_cons_special_reloc, size * 8);
4639 }
4640 }
4641 }
4642 }
4643 }
4644 if (sparc_cons_special_reloc == NULL)
4645 expression (exp);
4646 }
4647
4648 #endif
4649
4650 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4651 reloc for a cons. We could use the definition there, except that
4652 we want to handle little endian relocs specially. */
4653
4654 void
4655 cons_fix_new_sparc (fragS *frag,
4656 int where,
4657 unsigned int nbytes,
4658 expressionS *exp)
4659 {
4660 bfd_reloc_code_real_type r;
4661
4662 r = (nbytes == 1 ? BFD_RELOC_8 :
4663 (nbytes == 2 ? BFD_RELOC_16 :
4664 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4665
4666 if (target_little_endian_data
4667 && nbytes == 4
4668 && now_seg->flags & SEC_ALLOC)
4669 r = BFD_RELOC_SPARC_REV32;
4670
4671 if (sparc_cons_special_reloc)
4672 {
4673 if (*sparc_cons_special_reloc == 'd')
4674 switch (nbytes)
4675 {
4676 case 1: r = BFD_RELOC_8_PCREL; break;
4677 case 2: r = BFD_RELOC_16_PCREL; break;
4678 case 4: r = BFD_RELOC_32_PCREL; break;
4679 case 8: r = BFD_RELOC_64_PCREL; break;
4680 default: abort ();
4681 }
4682 else if (*sparc_cons_special_reloc == 'p')
4683 switch (nbytes)
4684 {
4685 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4686 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4687 }
4688 else
4689 switch (nbytes)
4690 {
4691 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4692 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4693 }
4694 }
4695 else if (sparc_no_align_cons)
4696 {
4697 switch (nbytes)
4698 {
4699 case 2: r = BFD_RELOC_SPARC_UA16; break;
4700 case 4: r = BFD_RELOC_SPARC_UA32; break;
4701 case 8: r = BFD_RELOC_SPARC_UA64; break;
4702 default: abort ();
4703 }
4704 }
4705
4706 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4707 sparc_cons_special_reloc = NULL;
4708 }
4709
4710 void
4711 sparc_cfi_frame_initial_instructions (void)
4712 {
4713 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4714 }
4715
4716 int
4717 sparc_regname_to_dw2regnum (char *regname)
4718 {
4719 char *p, *q;
4720
4721 if (!regname[0])
4722 return -1;
4723
4724 q = "goli";
4725 p = strchr (q, regname[0]);
4726 if (p)
4727 {
4728 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4729 return -1;
4730 return (p - q) * 8 + regname[1] - '0';
4731 }
4732 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4733 return 14;
4734 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4735 return 30;
4736 if (regname[0] == 'f' || regname[0] == 'r')
4737 {
4738 unsigned int regnum;
4739
4740 regnum = strtoul (regname + 1, &q, 10);
4741 if (p == q || *q)
4742 return -1;
4743 if (regnum >= ((regname[0] == 'f'
4744 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4745 ? 64 : 32))
4746 return -1;
4747 if (regname[0] == 'f')
4748 {
4749 regnum += 32;
4750 if (regnum >= 64 && (regnum & 1))
4751 return -1;
4752 }
4753 return regnum;
4754 }
4755 return -1;
4756 }
4757
4758 void
4759 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4760 {
4761 sparc_cons_special_reloc = "disp";
4762 sparc_no_align_cons = 1;
4763 emit_expr (exp, nbytes);
4764 sparc_no_align_cons = 0;
4765 sparc_cons_special_reloc = NULL;
4766 }
GDB Binutils - Deliverables
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