1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static const char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch
{
245 const char *opcode_arch
;
246 enum sparc_arch_types arch_type
;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size
;
250 /* Allowable arg to -A? */
254 } sparc_arch_table
[] = {
255 { "v6", "v6", v6
, 0, 1, 0, 0 },
256 { "v7", "v7", v7
, 0, 1, 0, 0 },
257 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
258 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
259 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
260 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
261 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
262 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
263 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
264 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
265 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
267 { "sparc4", "v9v", v9
, 0, 1, HWS_VV
, 0 },
268 { "sparc5", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
270 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
271 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
272 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
273 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
275 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
276 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
277 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
278 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
279 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
280 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
281 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
282 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
284 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
285 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
286 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
287 { "v9c", "v9c", v9
, 0, 1, HWS_VC
, 0 },
288 { "v9d", "v9d", v9
, 0, 1, HWS_VD
, 0 },
289 { "v9e", "v9e", v9
, 0, 1, HWS_VE
, 0 },
290 { "v9v", "v9v", v9
, 0, 1, HWS_VV
, 0 },
291 { "v9m", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
296 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type
;
302 static struct sparc_arch
*
303 lookup_arch (const char *name
)
305 struct sparc_arch
*sa
;
307 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
308 if (strcmp (sa
->name
, name
) == 0)
310 if (sa
->name
== NULL
)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch
*sa
= lookup_arch (default_arch
);
324 || sa
->default_arch_size
== 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
328 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
332 default_arch_type
= sa
->arch_type
;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p
)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian
)
351 return "a.out-sunos-big";
352 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts
= "A:K:VQ:sq";
443 const char *md_shortopts
= "A:k";
445 const char *md_shortopts
= "A:";
448 struct option md_longopts
[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument
, NULL
, OPTION_BUMP
},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument
, NULL
, OPTION_32
},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument
, NULL
, OPTION_64
},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument
, NULL
, OPTION_TSO
},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument
, NULL
, OPTION_PSO
},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument
, NULL
, OPTION_RMO
},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument
, NULL
, OPTION_RELAX
},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
487 {NULL
, no_argument
, NULL
, 0}
490 size_t md_longopts_size
= sizeof (md_longopts
);
493 md_parse_option (int c
, const char *arg
)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p
)
498 init_default_arch ();
504 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
509 if (!strncmp (arg
, "v9", 2))
510 md_parse_option (OPTION_64
, NULL
);
513 if (!strncmp (arg
, "v8", 2)
514 || !strncmp (arg
, "v7", 2)
515 || !strncmp (arg
, "v6", 2)
516 || !strcmp (arg
, "sparclet")
517 || !strcmp (arg
, "sparclite")
518 || !strcmp (arg
, "sparc86x"))
519 md_parse_option (OPTION_32
, NULL
);
526 struct sparc_arch
*sa
;
527 enum sparc_opcode_arch_val opcode_arch
;
529 sa
= lookup_arch (arg
);
531 || ! sa
->user_option_p
)
533 if (c
== OPTION_XARCH
)
534 as_bad (_("invalid architecture -xarch=%s"), arg
);
536 as_bad (_("invalid architecture -A%s"), arg
);
540 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
541 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch
> max_architecture
)
546 max_architecture
= opcode_arch
;
548 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
678 md_show_usage (FILE *stream
)
680 const struct sparc_arch
*arch
;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p
)
686 init_default_arch ();
688 fprintf (stream
, _("SPARC options:\n"));
690 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
692 if (!arch
->user_option_p
)
694 if (arch
!= &sparc_arch_table
[0])
695 fprintf (stream
, " | ");
696 if (column
+ strlen (arch
->name
) > 70)
699 fputc ('\n', stream
);
701 column
+= 5 + 2 + strlen (arch
->name
);
702 fprintf (stream
, "-A%s", arch
->name
);
704 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
706 if (!arch
->user_option_p
)
708 fprintf (stream
, " | ");
709 if (column
+ strlen (arch
->name
) > 65)
712 fputc ('\n', stream
);
714 column
+= 5 + 7 + strlen (arch
->name
);
715 fprintf (stream
, "-xarch=%s", arch
->name
);
717 fprintf (stream
, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream
, _("\
726 -k generate PIC\n"));
729 fprintf (stream
, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream
, _("\
733 [default is %d]\n"), default_arch_size
);
734 fprintf (stream
, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream
, _("\
739 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
740 fprintf (stream
, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream
, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table
[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table
[] =
810 {NULL
, -1}, /* End marker. */
813 struct priv_reg_entry hpriv_reg_table
[] =
823 {"hstick_offset", 28},
824 {"hstick_enable", 29},
826 {NULL
, -1}, /* End marker. */
829 /* v9a or later specific ancillary state registers. */
831 struct priv_reg_entry v9a_asr_table
[] =
834 {"sys_tick_cmpr", 25},
838 {"softint_clear", 21},
849 {"clear_softint", 21},
850 {NULL
, -1}, /* End marker. */
854 cmp_reg_entry (const void *parg
, const void *qarg
)
856 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
857 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
859 if (p
->name
== q
->name
)
861 else if (p
->name
== NULL
)
863 else if (q
->name
== NULL
)
866 return strcmp (q
->name
, p
->name
);
869 /* sparc %-pseudo-operations. */
872 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
873 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
875 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
876 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
878 instruction. (Generally they can appear
879 anywhere an immediate operand is
883 /* The name as it appears in assembler. */
885 /* The reloc this pseudo-op translates to. */
886 bfd_reloc_code_real_type reloc
;
887 /* Flags. See F_POP_* above. */
891 struct pop_entry pop_table
[] =
893 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
894 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
895 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
896 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
897 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
898 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
899 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
900 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
901 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
902 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
903 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
904 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
905 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
906 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
907 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
908 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
909 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
910 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
911 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
912 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
913 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
914 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
915 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
916 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
917 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
918 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
919 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
920 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
921 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
922 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
923 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
924 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
925 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
926 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
927 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
928 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
929 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
932 /* Table of %-names that can appear in a sparc assembly program. This
933 table is initialized in md_begin and contains entries for each
934 privileged/hyperprivileged/alternate register and %-pseudo-op. */
947 enum perc_entry_type type
;
948 /* Name of the %-entity. */
952 /* Value. Either a pop or a reg depending on type.*/
955 struct pop_entry
*pop
;
956 struct priv_reg_entry
*reg
;
960 #define NUM_PERC_ENTRIES \
961 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
962 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
963 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
964 + ARRAY_SIZE (pop_table) \
967 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
970 cmp_perc_entry (const void *parg
, const void *qarg
)
972 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
973 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
975 if (p
->name
== q
->name
)
977 else if (p
->name
== NULL
)
979 else if (q
->name
== NULL
)
982 return strcmp (q
->name
, p
->name
);
985 /* This function is called once, at assembler startup time. It should
986 set up all the tables, etc. that the MD part of the assembler will
992 const char *retval
= NULL
;
996 /* We don't get a chance to initialize anything before md_parse_option
997 is called, and it may not be called, so handle default initialization
998 now if not already done. */
999 if (! default_init_p
)
1000 init_default_arch ();
1002 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1003 op_hash
= hash_new ();
1005 while (i
< (unsigned int) sparc_num_opcodes
)
1007 const char *name
= sparc_opcodes
[i
].name
;
1008 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1011 as_bad (_("Internal error: can't hash `%s': %s\n"),
1012 sparc_opcodes
[i
].name
, retval
);
1017 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1019 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1020 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1025 while (i
< (unsigned int) sparc_num_opcodes
1026 && !strcmp (sparc_opcodes
[i
].name
, name
));
1029 for (i
= 0; native_op_table
[i
].name
; i
++)
1031 const struct sparc_opcode
*insn
;
1032 const char *name
= ((sparc_arch_size
== 32)
1033 ? native_op_table
[i
].name32
1034 : native_op_table
[i
].name64
);
1035 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1038 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1039 name
, native_op_table
[i
].name
);
1044 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1048 as_bad (_("Internal error: can't hash `%s': %s\n"),
1049 sparc_opcodes
[i
].name
, retval
);
1056 as_fatal (_("Broken assembler. No assembly attempted."));
1058 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1059 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1060 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1061 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1062 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1063 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1065 /* If -bump, record the architecture level at which we start issuing
1066 warnings. The behaviour is different depending upon whether an
1067 architecture was explicitly specified. If it wasn't, we issue warnings
1068 for all upwards bumps. If it was, we don't start issuing warnings until
1069 we need to bump beyond the requested architecture or when we bump between
1070 conflicting architectures. */
1073 && architecture_requested
)
1075 /* `max_architecture' records the requested architecture.
1076 Issue warnings if we go above it. */
1077 warn_after_architecture
= max_architecture
;
1080 /* Find the highest architecture level that doesn't conflict with
1081 the requested one. */
1084 || !architecture_requested
)
1086 enum sparc_opcode_arch_val current_max_architecture
1089 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1090 max_architecture
> warn_after_architecture
;
1092 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1093 current_max_architecture
))
1097 /* Prepare the tables of %-pseudo-ops. */
1099 struct priv_reg_entry
*reg_tables
[]
1100 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1101 struct priv_reg_entry
**reg_table
;
1104 /* Add registers. */
1105 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1107 struct priv_reg_entry
*reg
;
1108 for (reg
= *reg_table
; reg
->name
; reg
++)
1110 struct perc_entry
*p
= &perc_table
[entry
++];
1111 p
->type
= perc_entry_reg
;
1112 p
->name
= reg
->name
;
1113 p
->len
= strlen (reg
->name
);
1118 /* Add %-pseudo-ops. */
1119 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1121 struct perc_entry
*p
= &perc_table
[entry
++];
1122 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1123 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1124 p
->name
= pop_table
[i
].name
;
1125 p
->len
= strlen (pop_table
[i
].name
);
1126 p
->pop
= &pop_table
[i
];
1129 /* Last entry is the centinel. */
1130 perc_table
[entry
].type
= perc_entry_none
;
1132 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1133 sizeof (perc_table
[0]), cmp_perc_entry
);
1138 /* Called after all assembly has been done. */
1143 unsigned long mach
= bfd_mach_sparc
;
1144 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1145 int hwcaps
, hwcaps2
;
1148 if (sparc_arch_size
== 64)
1149 switch (current_architecture
)
1151 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1152 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1153 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1154 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1155 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1156 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1157 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1158 default: mach
= bfd_mach_sparc_v9
; break;
1161 switch (current_architecture
)
1163 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1164 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1165 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1166 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1167 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1168 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1169 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1170 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1171 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1172 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1173 be but for now it is (since that's the way it's always been
1177 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1179 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1180 hwcaps
= hwcap_seen
& U0xffffffff
;
1181 hwcaps2
= hwcap_seen
>> 32;
1184 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1186 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1190 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1193 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1197 /* Sign-extend the value from the architecture word size, so that
1198 0xffffffff is always considered -1 on sparc32. */
1199 if (sparc_arch_size
== 32)
1201 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1202 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1211 /* Return non-zero if VAL is in the range 0 to MAX. */
1214 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1221 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1222 (e.g. -15 to +31). */
1225 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1231 if (val
< ~(max
>> 1))
1237 sparc_ffs (unsigned int mask
)
1244 for (i
= 0; (mask
& 1) == 0; ++i
)
1249 /* Implement big shift right. */
1251 BSR (bfd_vma val
, int amount
)
1253 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1254 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1255 return val
>> amount
;
1258 /* For communication between sparc_ip and get_expression. */
1259 static char *expr_end
;
1261 /* Values for `special_case'.
1262 Instructions that require wierd handling because they're longer than
1264 #define SPECIAL_CASE_NONE 0
1265 #define SPECIAL_CASE_SET 1
1266 #define SPECIAL_CASE_SETSW 2
1267 #define SPECIAL_CASE_SETX 3
1268 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1269 #define SPECIAL_CASE_FDIV 4
1271 /* Bit masks of various insns. */
1272 #define NOP_INSN 0x01000000
1273 #define OR_INSN 0x80100000
1274 #define XOR_INSN 0x80180000
1275 #define FMOVS_INSN 0x81A00020
1276 #define SETHI_INSN 0x01000000
1277 #define SLLX_INSN 0x81281000
1278 #define SRA_INSN 0x81380000
1280 /* The last instruction to be assembled. */
1281 static const struct sparc_opcode
*last_insn
;
1282 /* The assembled opcode of `last_insn'. */
1283 static unsigned long last_opcode
;
1285 /* Handle the set and setuw synthetic instructions. */
1288 synthetize_setuw (const struct sparc_opcode
*insn
)
1290 int need_hi22_p
= 0;
1291 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1293 if (the_insn
.exp
.X_op
== O_constant
)
1295 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1297 if (sizeof (offsetT
) > 4
1298 && (the_insn
.exp
.X_add_number
< 0
1299 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1300 as_warn (_("set: number not in 0..4294967295 range"));
1304 if (sizeof (offsetT
) > 4
1305 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1306 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1307 as_warn (_("set: number not in -2147483648..4294967295 range"));
1308 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1312 /* See if operand is absolute and small; skip sethi if so. */
1313 if (the_insn
.exp
.X_op
!= O_constant
1314 || the_insn
.exp
.X_add_number
>= (1 << 12)
1315 || the_insn
.exp
.X_add_number
< -(1 << 12))
1317 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1318 | ((the_insn
.exp
.X_add_number
>> 10)
1319 & (the_insn
.exp
.X_op
== O_constant
1321 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1322 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1323 output_insn (insn
, &the_insn
);
1327 /* See if operand has no low-order bits; skip OR if so. */
1328 if (the_insn
.exp
.X_op
!= O_constant
1329 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1332 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1334 | (the_insn
.exp
.X_add_number
1335 & (the_insn
.exp
.X_op
!= O_constant
1336 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1337 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1338 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1339 output_insn (insn
, &the_insn
);
1343 /* Handle the setsw synthetic instruction. */
1346 synthetize_setsw (const struct sparc_opcode
*insn
)
1350 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1352 if (the_insn
.exp
.X_op
!= O_constant
)
1354 synthetize_setuw (insn
);
1356 /* Need to sign extend it. */
1357 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1358 the_insn
.reloc
= BFD_RELOC_NONE
;
1359 output_insn (insn
, &the_insn
);
1363 if (sizeof (offsetT
) > 4
1364 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1365 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1366 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1368 low32
= the_insn
.exp
.X_add_number
;
1372 synthetize_setuw (insn
);
1378 the_insn
.reloc
= BFD_RELOC_NONE
;
1379 /* See if operand is absolute and small; skip sethi if so. */
1380 if (low32
< -(1 << 12))
1382 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1383 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1384 output_insn (insn
, &the_insn
);
1385 low32
= 0x1c00 | (low32
& 0x3ff);
1386 opc
= RS1 (rd
) | XOR_INSN
;
1389 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1390 | (low32
& 0x1fff));
1391 output_insn (insn
, &the_insn
);
1394 /* Handle the setx synthetic instruction. */
1397 synthetize_setx (const struct sparc_opcode
*insn
)
1399 int upper32
, lower32
;
1400 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1401 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1403 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1404 int need_xor10_p
= 0;
1406 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1407 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1408 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1411 upper_dstreg
= tmpreg
;
1412 /* The tmp reg should not be the dst reg. */
1413 if (tmpreg
== dstreg
)
1414 as_warn (_("setx: temporary register same as destination register"));
1416 /* ??? Obviously there are other optimizations we can do
1417 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1418 doing some of these. Later. If you do change things, try to
1419 change all of this to be table driven as well. */
1420 /* What to output depends on the number if it's constant.
1421 Compute that first, then output what we've decided upon. */
1422 if (the_insn
.exp
.X_op
!= O_constant
)
1424 if (sparc_arch_size
== 32)
1426 /* When arch size is 32, we want setx to be equivalent
1427 to setuw for anything but constants. */
1428 the_insn
.exp
.X_add_number
&= 0xffffffff;
1429 synthetize_setuw (insn
);
1432 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1438 /* Reset X_add_number, we've extracted it as upper32/lower32.
1439 Otherwise fixup_segment will complain about not being able to
1440 write an 8 byte number in a 4 byte field. */
1441 the_insn
.exp
.X_add_number
= 0;
1443 /* Only need hh22 if `or' insn can't handle constant. */
1444 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1447 /* Does bottom part (after sethi) have bits? */
1448 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1449 /* No hh22, but does upper32 still have bits we can't set
1451 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1454 /* If the lower half is all zero, we build the upper half directly
1455 into the dst reg. */
1457 /* Need lower half if number is zero or 0xffffffff00000000. */
1458 || (! need_hh22_p
&& ! need_hm10_p
))
1460 /* No need for sethi if `or' insn can handle constant. */
1461 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1462 /* Note that we can't use a negative constant in the `or'
1463 insn unless the upper 32 bits are all ones. */
1464 || (lower32
< 0 && upper32
!= -1)
1465 || (lower32
>= 0 && upper32
== -1))
1468 if (need_hi22_p
&& upper32
== -1)
1471 /* Does bottom part (after sethi) have bits? */
1472 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1474 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1475 /* Need `or' if we didn't set anything else. */
1476 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1480 /* Output directly to dst reg if lower 32 bits are all zero. */
1481 upper_dstreg
= dstreg
;
1484 if (!upper_dstreg
&& dstreg
)
1485 as_warn (_("setx: illegal temporary register g0"));
1489 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1490 | ((upper32
>> 10) & 0x3fffff));
1491 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1492 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1493 output_insn (insn
, &the_insn
);
1498 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1499 | (((need_xor10_p
? ~lower32
: lower32
)
1500 >> 10) & 0x3fffff));
1501 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1502 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1503 output_insn (insn
, &the_insn
);
1508 the_insn
.opcode
= (OR_INSN
1509 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1512 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1513 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1514 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1515 output_insn (insn
, &the_insn
);
1520 /* FIXME: One nice optimization to do here is to OR the low part
1521 with the highpart if hi22 isn't needed and the low part is
1523 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1526 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1527 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1528 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1529 output_insn (insn
, &the_insn
);
1532 /* If we needed to build the upper part, shift it into place. */
1533 if (need_hh22_p
|| need_hm10_p
)
1535 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1537 the_insn
.reloc
= BFD_RELOC_NONE
;
1538 output_insn (insn
, &the_insn
);
1541 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1544 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1545 | 0x1c00 | (lower32
& 0x3ff));
1546 the_insn
.reloc
= BFD_RELOC_NONE
;
1547 output_insn (insn
, &the_insn
);
1550 /* If we needed to build both upper and lower parts, OR them together. */
1551 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1553 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1555 the_insn
.reloc
= BFD_RELOC_NONE
;
1556 output_insn (insn
, &the_insn
);
1560 /* Main entry point to assemble one instruction. */
1563 md_assemble (char *str
)
1565 const struct sparc_opcode
*insn
;
1569 special_case
= sparc_ip (str
, &insn
);
1573 /* We warn about attempts to put a floating point branch in a delay slot,
1574 unless the delay slot has been annulled. */
1575 if (last_insn
!= NULL
1576 && (insn
->flags
& F_FBR
) != 0
1577 && (last_insn
->flags
& F_DELAYED
) != 0
1578 /* ??? This test isn't completely accurate. We assume anything with
1579 F_{UNBR,CONDBR,FBR} set is annullable. */
1580 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1581 || (last_opcode
& ANNUL
) == 0))
1582 as_warn (_("FP branch in delay slot"));
1584 /* SPARC before v9 requires a nop instruction between a floating
1585 point instruction and a floating point branch. We insert one
1586 automatically, with a warning. */
1587 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1588 && last_insn
!= NULL
1589 && (insn
->flags
& F_FBR
) != 0
1590 && (last_insn
->flags
& F_FLOAT
) != 0)
1592 struct sparc_it nop_insn
;
1594 nop_insn
.opcode
= NOP_INSN
;
1595 nop_insn
.reloc
= BFD_RELOC_NONE
;
1596 output_insn (insn
, &nop_insn
);
1597 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1600 switch (special_case
)
1602 case SPECIAL_CASE_NONE
:
1604 output_insn (insn
, &the_insn
);
1607 case SPECIAL_CASE_SETSW
:
1608 synthetize_setsw (insn
);
1611 case SPECIAL_CASE_SET
:
1612 synthetize_setuw (insn
);
1615 case SPECIAL_CASE_SETX
:
1616 synthetize_setx (insn
);
1619 case SPECIAL_CASE_FDIV
:
1621 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1623 output_insn (insn
, &the_insn
);
1625 /* According to information leaked from Sun, the "fdiv" instructions
1626 on early SPARC machines would produce incorrect results sometimes.
1627 The workaround is to add an fmovs of the destination register to
1628 itself just after the instruction. This was true on machines
1629 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1630 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1631 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1632 output_insn (insn
, &the_insn
);
1637 as_fatal (_("failed special case insn sanity check"));
1642 get_hwcap_name (bfd_uint64_t mask
)
1644 if (mask
& HWCAP_MUL32
)
1646 if (mask
& HWCAP_DIV32
)
1648 if (mask
& HWCAP_FSMULD
)
1650 if (mask
& HWCAP_V8PLUS
)
1652 if (mask
& HWCAP_POPC
)
1654 if (mask
& HWCAP_VIS
)
1656 if (mask
& HWCAP_VIS2
)
1658 if (mask
& HWCAP_ASI_BLK_INIT
)
1659 return "ASIBlkInit";
1660 if (mask
& HWCAP_FMAF
)
1662 if (mask
& HWCAP_VIS3
)
1664 if (mask
& HWCAP_HPC
)
1666 if (mask
& HWCAP_RANDOM
)
1668 if (mask
& HWCAP_TRANS
)
1670 if (mask
& HWCAP_FJFMAU
)
1672 if (mask
& HWCAP_IMA
)
1674 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1676 if (mask
& HWCAP_AES
)
1678 if (mask
& HWCAP_DES
)
1680 if (mask
& HWCAP_KASUMI
)
1682 if (mask
& HWCAP_CAMELLIA
)
1684 if (mask
& HWCAP_MD5
)
1686 if (mask
& HWCAP_SHA1
)
1688 if (mask
& HWCAP_SHA256
)
1690 if (mask
& HWCAP_SHA512
)
1692 if (mask
& HWCAP_MPMUL
)
1694 if (mask
& HWCAP_MONT
)
1696 if (mask
& HWCAP_PAUSE
)
1698 if (mask
& HWCAP_CBCOND
)
1700 if (mask
& HWCAP_CRC32C
)
1704 if (mask
& HWCAP2_FJATHPLUS
)
1706 if (mask
& HWCAP2_VIS3B
)
1708 if (mask
& HWCAP2_ADP
)
1710 if (mask
& HWCAP2_SPARC5
)
1712 if (mask
& HWCAP2_MWAIT
)
1714 if (mask
& HWCAP2_XMPMUL
)
1716 if (mask
& HWCAP2_XMONT
)
1718 if (mask
& HWCAP2_NSEC
)
1724 /* Subroutine of md_assemble to do the actual parsing. */
1727 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1729 const char *error_message
= "";
1733 const struct sparc_opcode
*insn
;
1735 unsigned long opcode
;
1736 unsigned int mask
= 0;
1740 int special_case
= SPECIAL_CASE_NONE
;
1747 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1764 as_bad (_("Unknown opcode: `%s'"), str
);
1766 return special_case
;
1768 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1772 as_bad (_("Unknown opcode: `%s'"), str
);
1773 return special_case
;
1783 opcode
= insn
->match
;
1784 memset (&the_insn
, '\0', sizeof (the_insn
));
1785 the_insn
.reloc
= BFD_RELOC_NONE
;
1788 /* Build the opcode, checking as we go to make sure that the
1790 for (args
= insn
->args
;; ++args
)
1798 /* Parse a series of masks. */
1805 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1808 error_message
= _(": invalid membar mask name");
1814 if (*s
== '|' || *s
== '+')
1822 if (! parse_const_expr_arg (&s
, &kmask
))
1824 error_message
= _(": invalid membar mask expression");
1827 if (kmask
< 0 || kmask
> 127)
1829 error_message
= _(": invalid membar mask number");
1834 opcode
|= MEMBAR (kmask
);
1842 if (! parse_const_expr_arg (&s
, &smask
))
1844 error_message
= _(": invalid siam mode expression");
1847 if (smask
< 0 || smask
> 7)
1849 error_message
= _(": invalid siam mode number");
1860 /* Parse a prefetch function. */
1863 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1865 error_message
= _(": invalid prefetch function name");
1871 if (! parse_const_expr_arg (&s
, &fcn
))
1873 error_message
= _(": invalid prefetch function expression");
1876 if (fcn
< 0 || fcn
> 31)
1878 error_message
= _(": invalid prefetch function number");
1888 /* Parse a sparc64 privileged register. */
1891 struct priv_reg_entry
*p
;
1892 unsigned int len
= 9999999; /* Init to make gcc happy. */
1895 for (p
= priv_reg_table
; p
->name
; p
++)
1896 if (p
->name
[0] == s
[0])
1898 len
= strlen (p
->name
);
1899 if (strncmp (p
->name
, s
, len
) == 0)
1905 error_message
= _(": unrecognizable privileged register");
1909 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1911 error_message
= _(": unrecognizable privileged register");
1920 error_message
= _(": unrecognizable privileged register");
1926 /* Parse a sparc64 hyperprivileged register. */
1929 struct priv_reg_entry
*p
;
1930 unsigned int len
= 9999999; /* Init to make gcc happy. */
1933 for (p
= hpriv_reg_table
; p
->name
; p
++)
1934 if (p
->name
[0] == s
[0])
1936 len
= strlen (p
->name
);
1937 if (strncmp (p
->name
, s
, len
) == 0)
1943 error_message
= _(": unrecognizable hyperprivileged register");
1947 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1949 error_message
= _(": unrecognizable hyperprivileged register");
1958 error_message
= _(": unrecognizable hyperprivileged register");
1964 /* Parse a v9a or later ancillary state register. */
1967 struct priv_reg_entry
*p
;
1968 unsigned int len
= 9999999; /* Init to make gcc happy. */
1971 for (p
= v9a_asr_table
; p
->name
; p
++)
1972 if (p
->name
[0] == s
[0])
1974 len
= strlen (p
->name
);
1975 if (strncmp (p
->name
, s
, len
) == 0)
1981 error_message
= _(": unrecognizable ancillary state register");
1985 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1987 error_message
= _(": unrecognizable ancillary state register");
1996 error_message
= _(": unrecognizable ancillary state register");
2002 if (strncmp (s
, "%asr", 4) == 0)
2010 while (ISDIGIT (*s
))
2012 num
= num
* 10 + *s
- '0';
2016 /* We used to check here for the asr number to
2017 be between 16 and 31 in V9 and later, as
2018 mandated by the section C.1.1 "Register
2019 Names" in the SPARC spec. However, we
2020 decided to remove this restriction as a) it
2021 introduces problems when new V9 asr registers
2022 are introduced, b) the Solaris assembler
2023 doesn't implement this restriction and c) the
2024 restriction will go away in future revisions
2025 of the Oracle SPARC Architecture. */
2027 if (num
< 0 || 31 < num
)
2029 error_message
= _(": asr number must be between 0 and 31");
2033 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2038 error_message
= _(": expecting %asrN");
2045 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2049 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2055 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2060 if (s
[0] == '0' && s
[1] == 'x')
2063 while (ISXDIGIT (*s
))
2066 num
|= hex_value (*s
);
2072 while (ISDIGIT (*s
))
2074 num
= num
* 10 + *s
- '0';
2078 if (num
< 0 || num
> 31)
2080 error_message
= _(": crypto immediate must be between 0 and 31");
2084 opcode
|= RS3 (num
);
2089 error_message
= _(": expecting crypto immediate");
2094 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2095 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2096 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2098 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2099 /* These fields are unsigned, but for upward compatibility,
2100 allow negative values as well. */
2104 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2105 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2106 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2108 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2109 /* These fields are unsigned, but for upward compatibility,
2110 allow negative values as well. */
2114 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2119 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2124 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2129 if (*s
== 'p' && s
[1] == 'n')
2137 if (*s
== 'p' && s
[1] == 't')
2149 if ((strncmp (s
, "%icc", 4) == 0)
2150 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2162 if ((strncmp (s
, "%xcc", 4) == 0)
2163 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2175 if (strncmp (s
, "%fcc0", 5) == 0)
2187 if (strncmp (s
, "%fcc1", 5) == 0)
2199 if (strncmp (s
, "%fcc2", 5) == 0)
2211 if (strncmp (s
, "%fcc3", 5) == 0)
2219 if (strncmp (s
, "%pc", 3) == 0)
2227 if (strncmp (s
, "%tick", 5) == 0)
2234 case '\0': /* End of args. */
2235 if (s
[0] == ',' && s
[1] == '%')
2239 const struct perc_entry
*p
;
2241 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2242 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2243 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2245 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2248 if (s
[p
->len
+ 2] != '(')
2250 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2251 return special_case
;
2254 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2255 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2257 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2259 return special_case
;
2262 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2263 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2264 || the_insn
.exp
.X_add_number
!= 0
2265 || the_insn
.exp
.X_add_symbol
2266 != symbol_find_or_make ("__tls_get_addr")))
2268 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2270 return special_case
;
2273 the_insn
.reloc
= p
->pop
->reloc
;
2274 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2277 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2280 else if (*s1
== ')')
2289 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2290 return special_case
;
2294 (void) get_expression (s
);
2314 case '[': /* These must match exactly. */
2322 case '#': /* Must be at least one digit. */
2325 while (ISDIGIT (*s
))
2333 case 'C': /* Coprocessor state register. */
2334 if (strncmp (s
, "%csr", 4) == 0)
2341 case 'b': /* Next operand is a coprocessor register. */
2344 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2349 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2363 opcode
|= mask
<< 14;
2371 opcode
|= mask
<< 25;
2377 case 'r': /* next operand must be a register */
2387 case 'f': /* frame pointer */
2395 case 'g': /* global register */
2404 case 'i': /* in register */
2408 mask
= c
- '0' + 24;
2413 case 'l': /* local register */
2417 mask
= (c
- '0' + 16);
2422 case 'o': /* out register */
2426 mask
= (c
- '0' + 8);
2431 case 's': /* stack pointer */
2439 case 'r': /* any register */
2440 if (!ISDIGIT ((c
= *s
++)))
2457 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2473 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2474 && no_undeclared_regs
&& ! globals
[mask
])
2475 as_bad (_("detected global register use not covered by .register pseudo-op"));
2477 /* Got the register, now figure out where
2478 it goes in the opcode. */
2482 opcode
|= mask
<< 14;
2490 opcode
|= mask
<< 25;
2494 opcode
|= (mask
<< 25) | (mask
<< 14);
2498 opcode
|= (mask
<< 25) | (mask
<< 0);
2504 case 'e': /* next operand is a floating point register */
2523 && ((format
= *s
) == 'f'
2528 for (mask
= 0; ISDIGIT (*s
); ++s
)
2530 mask
= 10 * mask
+ (*s
- '0');
2531 } /* read the number */
2540 /* register must be even numbered */
2550 /* register must be multiple of 4 */
2556 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2557 error_message
= _(": There are only 64 f registers; [0-63]");
2559 error_message
= _(": There are only 32 f registers; [0-31]");
2562 else if (mask
>= 32)
2564 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2566 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2569 = _(": There are only 32 single precision f registers; [0-31]");
2573 mask
-= 31; /* wrap high bit */
2577 error_message
= _(": There are only 32 f registers; [0-31]");
2585 } /* if not an 'f' register. */
2587 if (*args
== '}' && mask
!= RS2 (opcode
))
2590 = _(": Instruction requires frs2 and frsd must be the same register");
2599 opcode
|= RS1 (mask
);
2605 opcode
|= RS2 (mask
);
2610 opcode
|= RS3 (mask
);
2617 opcode
|= RD (mask
);
2626 if (strncmp (s
, "%fsr", 4) == 0)
2634 if (strncmp (s
, "%efsr", 5) == 0)
2641 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2642 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2645 case 'l': /* 22 bit PC relative immediate */
2646 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2650 case 'L': /* 30 bit immediate */
2651 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2656 case 'n': /* 22 bit immediate */
2657 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2660 case 'i': /* 13 bit immediate */
2661 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2671 const char *op_arg
= NULL
;
2672 static expressionS op_exp
;
2673 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2675 /* Check for %hi, etc. */
2678 const struct perc_entry
*p
;
2680 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2681 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2682 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2684 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2687 if (s
[p
->len
+ 1] != '(')
2689 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2690 return special_case
;
2694 the_insn
.reloc
= p
->pop
->reloc
;
2696 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2699 /* Note that if the get_expression() fails, we will still
2700 have created U entries in the symbol table for the
2701 'symbols' in the input string. Try not to create U
2702 symbols for registers, etc. */
2704 /* This stuff checks to see if the expression ends in
2705 +%reg. If it does, it removes the register from
2706 the expression, and re-sets 's' to point to the
2713 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2716 else if (*s1
== ')')
2725 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2726 return special_case
;
2730 (void) get_expression (s
);
2734 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2735 return special_case
;
2738 if (*s
== ',' || *s
== ']' || !*s
)
2740 if (*s
!= '+' && *s
!= '-')
2742 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2743 return special_case
;
2747 op_exp
= the_insn
.exp
;
2748 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2751 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2754 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2756 if (s1
[-2] == '%' && s1
[-3] == '+')
2758 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2760 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2767 if (op_arg
&& s1
== s
+ 1)
2768 the_insn
.exp
.X_op
= O_absent
;
2770 (void) get_expression (s
);
2782 (void) get_expression (s
);
2790 the_insn
.exp2
= the_insn
.exp
;
2791 the_insn
.exp
= op_exp
;
2792 if (the_insn
.exp2
.X_op
== O_absent
)
2793 the_insn
.exp2
.X_op
= O_illegal
;
2794 else if (the_insn
.exp
.X_op
== O_absent
)
2796 the_insn
.exp
= the_insn
.exp2
;
2797 the_insn
.exp2
.X_op
= O_illegal
;
2799 else if (the_insn
.exp
.X_op
== O_constant
)
2801 valueT val
= the_insn
.exp
.X_add_number
;
2802 switch (the_insn
.reloc
)
2807 case BFD_RELOC_SPARC_HH22
:
2808 val
= BSR (val
, 32);
2811 case BFD_RELOC_SPARC_LM22
:
2812 case BFD_RELOC_HI22
:
2813 val
= (val
>> 10) & 0x3fffff;
2816 case BFD_RELOC_SPARC_HM10
:
2817 val
= BSR (val
, 32);
2820 case BFD_RELOC_LO10
:
2824 case BFD_RELOC_SPARC_H34
:
2829 case BFD_RELOC_SPARC_H44
:
2834 case BFD_RELOC_SPARC_M44
:
2839 case BFD_RELOC_SPARC_L44
:
2843 case BFD_RELOC_SPARC_HIX22
:
2845 val
= (val
>> 10) & 0x3fffff;
2848 case BFD_RELOC_SPARC_LOX10
:
2849 val
= (val
& 0x3ff) | 0x1c00;
2852 the_insn
.exp
= the_insn
.exp2
;
2853 the_insn
.exp
.X_add_number
+= val
;
2854 the_insn
.exp2
.X_op
= O_illegal
;
2855 the_insn
.reloc
= old_reloc
;
2857 else if (the_insn
.exp2
.X_op
!= O_constant
)
2859 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2860 return special_case
;
2864 if (old_reloc
!= BFD_RELOC_SPARC13
2865 || the_insn
.reloc
!= BFD_RELOC_LO10
2866 || sparc_arch_size
!= 64
2869 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2870 return special_case
;
2872 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2876 /* Check for constants that don't require emitting a reloc. */
2877 if (the_insn
.exp
.X_op
== O_constant
2878 && the_insn
.exp
.X_add_symbol
== 0
2879 && the_insn
.exp
.X_op_symbol
== 0)
2881 /* For pc-relative call instructions, we reject
2882 constants to get better code. */
2884 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2885 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2887 error_message
= _(": PC-relative operand can't be a constant");
2891 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2892 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2894 error_message
= _(": TLS operand can't be a constant");
2898 /* Constants that won't fit are checked in md_apply_fix
2899 and bfd_install_relocation.
2900 ??? It would be preferable to install the constants
2901 into the insn here and save having to create a fixS
2902 for each one. There already exists code to handle
2903 all the various cases (e.g. in md_apply_fix and
2904 bfd_install_relocation) so duplicating all that code
2905 here isn't right. */
2907 /* This is a special case to handle cbcond instructions
2908 properly, which can need two relocations. The first
2909 one is for the 5-bit immediate field and the latter
2910 is going to be for the WDISP10 branch part. We
2911 handle the R_SPARC_5 immediate directly here so that
2912 we don't need to add support for multiple relocations
2913 in one instruction just yet. */
2914 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2916 valueT val
= the_insn
.exp
.X_add_number
;
2918 if (! in_bitfield_range (val
, 0x1f))
2920 error_message
= _(": Immediate value in cbcond is out of range.");
2923 opcode
|= val
& 0x1f;
2924 the_insn
.reloc
= BFD_RELOC_NONE
;
2945 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2947 error_message
= _(": invalid ASI name");
2953 if (! parse_const_expr_arg (&s
, &asi
))
2955 error_message
= _(": invalid ASI expression");
2958 if (asi
< 0 || asi
> 255)
2960 error_message
= _(": invalid ASI number");
2964 opcode
|= ASI (asi
);
2966 } /* Alternate space. */
2969 if (strncmp (s
, "%psr", 4) == 0)
2976 case 'q': /* Floating point queue. */
2977 if (strncmp (s
, "%fq", 3) == 0)
2984 case 'Q': /* Coprocessor queue. */
2985 if (strncmp (s
, "%cq", 3) == 0)
2993 if (strcmp (str
, "set") == 0
2994 || strcmp (str
, "setuw") == 0)
2996 special_case
= SPECIAL_CASE_SET
;
2999 else if (strcmp (str
, "setsw") == 0)
3001 special_case
= SPECIAL_CASE_SETSW
;
3004 else if (strcmp (str
, "setx") == 0)
3006 special_case
= SPECIAL_CASE_SETX
;
3009 else if (strncmp (str
, "fdiv", 4) == 0)
3011 special_case
= SPECIAL_CASE_FDIV
;
3017 if (strncmp (s
, "%asi", 4) != 0)
3023 if (strncmp (s
, "%fprs", 5) != 0)
3029 if (strncmp (s
, "%mcdper",7) != 0)
3035 if (strncmp (s
, "%ccr", 4) != 0)
3041 if (strncmp (s
, "%tbr", 4) != 0)
3047 if (strncmp (s
, "%wim", 4) != 0)
3054 char *push
= input_line_pointer
;
3057 input_line_pointer
= s
;
3059 if (e
.X_op
== O_constant
)
3061 int n
= e
.X_add_number
;
3062 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3063 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3065 opcode
|= e
.X_add_number
<< 5;
3068 as_bad (_("non-immediate OPF operand, ignored"));
3069 s
= input_line_pointer
;
3070 input_line_pointer
= push
;
3075 if (strncmp (s
, "%y", 2) != 0)
3083 /* Parse a sparclet cpreg. */
3085 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3087 error_message
= _(": invalid cpreg name");
3090 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3095 as_fatal (_("failed sanity check."));
3096 } /* switch on arg code. */
3098 /* Break out of for() loop. */
3100 } /* For each arg that we expect. */
3105 /* Args don't match. */
3106 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3107 && (insn
->name
== insn
[1].name
3108 || !strcmp (insn
->name
, insn
[1].name
)))
3116 as_bad (_("Illegal operands%s"), error_message
);
3117 return special_case
;
3122 /* We have a match. Now see if the architecture is OK. */
3123 int needed_arch_mask
= insn
->architecture
;
3125 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3127 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3129 hwcap_seen
|= hwcaps
;
3134 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3135 if (! needed_arch_mask
)
3137 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3140 if (needed_arch_mask
3141 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3144 /* Can we bump up the architecture? */
3145 else if (needed_arch_mask
3146 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3148 enum sparc_opcode_arch_val needed_architecture
=
3149 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3150 & needed_arch_mask
);
3152 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3154 && needed_architecture
> warn_after_architecture
)
3156 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3157 sparc_opcode_archs
[current_architecture
].name
,
3158 sparc_opcode_archs
[needed_architecture
].name
,
3160 warn_after_architecture
= needed_architecture
;
3162 current_architecture
= needed_architecture
;
3163 hwcap_allowed
|= hwcaps
;
3166 /* ??? This seems to be a bit fragile. What if the next entry in
3167 the opcode table is the one we want and it is supported?
3168 It is possible to arrange the table today so that this can't
3169 happen but what about tomorrow? */
3172 int arch
, printed_one_p
= 0;
3174 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3176 /* Create a list of the architectures that support the insn. */
3177 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3179 arch
= sparc_ffs (needed_arch_mask
);
3180 while ((1 << arch
) <= needed_arch_mask
)
3182 if ((1 << arch
) & needed_arch_mask
)
3186 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3193 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3194 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3196 sparc_opcode_archs
[max_architecture
].name
);
3197 return special_case
;
3200 /* Make sure the hwcaps used by the instruction are
3201 currently enabled. */
3202 if (hwcaps
& ~hwcap_allowed
)
3204 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3206 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3208 return special_case
;
3210 } /* If no match. */
3213 } /* Forever looking for a match. */
3215 the_insn
.opcode
= opcode
;
3216 return special_case
;
3219 /* Parse an argument that can be expressed as a keyword.
3220 (eg: #StoreStore or %ccfr).
3221 The result is a boolean indicating success.
3222 If successful, INPUT_POINTER is updated. */
3225 parse_keyword_arg (int (*lookup_fn
) (const char *),
3226 char **input_pointerP
,
3232 p
= *input_pointerP
;
3233 for (q
= p
+ (*p
== '#' || *p
== '%');
3234 ISALNUM (*q
) || *q
== '_';
3239 value
= (*lookup_fn
) (p
);
3244 *input_pointerP
= q
;
3248 /* Parse an argument that is a constant expression.
3249 The result is a boolean indicating success. */
3252 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3254 char *save
= input_line_pointer
;
3257 input_line_pointer
= *input_pointerP
;
3258 /* The next expression may be something other than a constant
3259 (say if we're not processing the right variant of the insn).
3260 Don't call expression unless we're sure it will succeed as it will
3261 signal an error (which we want to defer until later). */
3262 /* FIXME: It might be better to define md_operand and have it recognize
3263 things like %asi, etc. but continuing that route through to the end
3264 is a lot of work. */
3265 if (*input_line_pointer
== '%')
3267 input_line_pointer
= save
;
3271 *input_pointerP
= input_line_pointer
;
3272 input_line_pointer
= save
;
3273 if (exp
.X_op
!= O_constant
)
3275 *valueP
= exp
.X_add_number
;
3279 /* Subroutine of sparc_ip to parse an expression. */
3282 get_expression (char *str
)
3287 save_in
= input_line_pointer
;
3288 input_line_pointer
= str
;
3289 seg
= expression (&the_insn
.exp
);
3290 if (seg
!= absolute_section
3291 && seg
!= text_section
3292 && seg
!= data_section
3293 && seg
!= bss_section
3294 && seg
!= undefined_section
)
3296 the_insn
.error
= _("bad segment");
3297 expr_end
= input_line_pointer
;
3298 input_line_pointer
= save_in
;
3301 expr_end
= input_line_pointer
;
3302 input_line_pointer
= save_in
;
3306 /* Subroutine of md_assemble to output one insn. */
3309 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3311 char *toP
= frag_more (4);
3313 /* Put out the opcode. */
3314 if (INSN_BIG_ENDIAN
)
3315 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3317 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3319 /* Put out the symbol-dependent stuff. */
3320 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3322 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3323 (toP
- frag_now
->fr_literal
), /* Where. */
3328 /* Turn off overflow checking in fixup_segment. We'll do our
3329 own overflow checking in md_apply_fix. This is necessary because
3330 the insn size is 4 and fixup_segment will signal an overflow for
3331 large 8 byte quantities. */
3332 fixP
->fx_no_overflow
= 1;
3333 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3334 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3338 last_opcode
= theinsn
->opcode
;
3341 dwarf2_emit_insn (4);
3346 md_atof (int type
, char *litP
, int *sizeP
)
3348 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3351 /* Write a value out to the object file, using the appropriate
3355 md_number_to_chars (char *buf
, valueT val
, int n
)
3357 if (target_big_endian
)
3358 number_to_chars_bigendian (buf
, val
, n
);
3359 else if (target_little_endian_data
3360 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3361 /* Output debug words, which are not in allocated sections, as big
3363 number_to_chars_bigendian (buf
, val
, n
);
3364 else if (target_little_endian_data
|| ! target_big_endian
)
3365 number_to_chars_littleendian (buf
, val
, n
);
3368 /* Apply a fixS to the frags, now that we know the value it ought to
3372 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3374 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3375 offsetT val
= * (offsetT
*) valP
;
3378 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3380 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3383 /* SPARC ELF relocations don't use an addend in the data field. */
3384 if (fixP
->fx_addsy
!= NULL
)
3386 switch (fixP
->fx_r_type
)
3388 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3389 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3390 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3391 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3392 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3393 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3394 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3395 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3396 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3397 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3398 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3399 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3400 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3401 case BFD_RELOC_SPARC_TLS_IE_LD
:
3402 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3403 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3404 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3405 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3406 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3407 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3408 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3409 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3410 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3411 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3412 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3422 /* This is a hack. There should be a better way to
3423 handle this. Probably in terms of howto fields, once
3424 we can look at these fixups in terms of howtos. */
3425 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3426 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3429 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3430 generate a reloc, then we just want to let the reloc addend set
3431 the value. We do not want to also stuff the addend into the
3432 object file. Including the addend in the object file works when
3433 doing a static link, because the linker will ignore the object
3434 file contents. However, the dynamic linker does not ignore the
3435 object file contents. */
3436 if (fixP
->fx_addsy
!= NULL
3437 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3440 /* When generating PIC code, we do not want an addend for a reloc
3441 against a local symbol. We adjust fx_addnumber to cancel out the
3442 value already included in val, and to also cancel out the
3443 adjustment which bfd_install_relocation will create. */
3445 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3446 && fixP
->fx_addsy
!= NULL
3447 && ! S_IS_COMMON (fixP
->fx_addsy
)
3448 && symbol_section_p (fixP
->fx_addsy
))
3449 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3451 /* When generating PIC code, we need to fiddle to get
3452 bfd_install_relocation to do the right thing for a PC relative
3453 reloc against a local symbol which we are going to keep. */
3455 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3456 && fixP
->fx_addsy
!= NULL
3457 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3458 || S_IS_WEAK (fixP
->fx_addsy
))
3459 && S_IS_DEFINED (fixP
->fx_addsy
)
3460 && ! S_IS_COMMON (fixP
->fx_addsy
))
3463 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3467 /* If this is a data relocation, just output VAL. */
3469 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3471 md_number_to_chars (buf
, val
, 1);
3473 else if (fixP
->fx_r_type
== BFD_RELOC_16
3474 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3476 md_number_to_chars (buf
, val
, 2);
3478 else if (fixP
->fx_r_type
== BFD_RELOC_32
3479 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3480 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3482 md_number_to_chars (buf
, val
, 4);
3484 else if (fixP
->fx_r_type
== BFD_RELOC_64
3485 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3487 md_number_to_chars (buf
, val
, 8);
3489 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3490 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3497 /* It's a relocation against an instruction. */
3499 if (INSN_BIG_ENDIAN
)
3500 insn
= bfd_getb32 ((unsigned char *) buf
);
3502 insn
= bfd_getl32 ((unsigned char *) buf
);
3504 switch (fixP
->fx_r_type
)
3506 case BFD_RELOC_32_PCREL_S2
:
3508 /* FIXME: This increment-by-one deserves a comment of why it's
3510 if (! sparc_pic_code
3511 || fixP
->fx_addsy
== NULL
3512 || symbol_section_p (fixP
->fx_addsy
))
3515 insn
|= val
& 0x3fffffff;
3517 /* See if we have a delay slot. */
3518 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3522 #define XCC (2 << 20)
3523 #define COND(x) (((x)&0xf)<<25)
3524 #define CONDA COND(0x8)
3525 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3526 #define INSN_BA (F2(0,2) | CONDA)
3527 #define INSN_OR F3(2, 0x2, 0)
3528 #define INSN_NOP F2(0,4)
3532 /* If the instruction is a call with either:
3534 arithmetic instruction with rd == %o7
3535 where rs1 != %o7 and rs2 if it is register != %o7
3536 then we can optimize if the call destination is near
3537 by changing the call into a branch always. */
3538 if (INSN_BIG_ENDIAN
)
3539 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3541 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3542 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3544 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3545 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3546 || ((delay
& RD (~0)) != RD (O7
))))
3548 if ((delay
& RS1 (~0)) == RS1 (O7
)
3549 || ((delay
& F3I (~0)) == 0
3550 && (delay
& RS2 (~0)) == RS2 (O7
)))
3552 /* Ensure the branch will fit into simm22. */
3553 if ((val
& 0x3fe00000)
3554 && (val
& 0x3fe00000) != 0x3fe00000)
3556 /* Check if the arch is v9 and branch will fit
3558 if (((val
& 0x3c0000) == 0
3559 || (val
& 0x3c0000) == 0x3c0000)
3560 && (sparc_arch_size
== 64
3561 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3563 insn
= INSN_BPA
| (val
& 0x7ffff);
3566 insn
= INSN_BA
| (val
& 0x3fffff);
3567 if (fixP
->fx_where
>= 4
3568 && ((delay
& (0xffffffff ^ RS1 (~0)))
3569 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3574 if (INSN_BIG_ENDIAN
)
3575 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3577 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3578 if ((setter
& (0xffffffff ^ RD (~0)))
3579 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3586 If call foo was replaced with ba, replace
3587 or %rN, %g0, %o7 with nop. */
3588 reg
= (delay
& RS1 (~0)) >> 14;
3589 if (reg
!= ((setter
& RD (~0)) >> 25)
3590 || reg
== G0
|| reg
== O7
)
3593 if (INSN_BIG_ENDIAN
)
3594 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3596 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3601 case BFD_RELOC_SPARC_11
:
3602 if (! in_signed_range (val
, 0x7ff))
3603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3604 _("relocation overflow"));
3605 insn
|= val
& 0x7ff;
3608 case BFD_RELOC_SPARC_10
:
3609 if (! in_signed_range (val
, 0x3ff))
3610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3611 _("relocation overflow"));
3612 insn
|= val
& 0x3ff;
3615 case BFD_RELOC_SPARC_7
:
3616 if (! in_bitfield_range (val
, 0x7f))
3617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3618 _("relocation overflow"));
3622 case BFD_RELOC_SPARC_6
:
3623 if (! in_bitfield_range (val
, 0x3f))
3624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3625 _("relocation overflow"));
3629 case BFD_RELOC_SPARC_5
:
3630 if (! in_bitfield_range (val
, 0x1f))
3631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3632 _("relocation overflow"));
3636 case BFD_RELOC_SPARC_WDISP10
:
3639 || val
<= -(offsetT
) 0x808)
3640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3641 _("relocation overflow"));
3642 /* FIXME: The +1 deserves a comment. */
3643 val
= (val
>> 2) + 1;
3644 insn
|= ((val
& 0x300) << 11)
3645 | ((val
& 0xff) << 5);
3648 case BFD_RELOC_SPARC_WDISP16
:
3651 || val
<= -(offsetT
) 0x20008)
3652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3653 _("relocation overflow"));
3654 /* FIXME: The +1 deserves a comment. */
3655 val
= (val
>> 2) + 1;
3656 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3659 case BFD_RELOC_SPARC_WDISP19
:
3662 || val
<= -(offsetT
) 0x100008)
3663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3664 _("relocation overflow"));
3665 /* FIXME: The +1 deserves a comment. */
3666 val
= (val
>> 2) + 1;
3667 insn
|= val
& 0x7ffff;
3670 case BFD_RELOC_SPARC_HH22
:
3671 val
= BSR (val
, 32);
3674 case BFD_RELOC_SPARC_LM22
:
3675 case BFD_RELOC_HI22
:
3676 if (!fixP
->fx_addsy
)
3677 insn
|= (val
>> 10) & 0x3fffff;
3679 /* FIXME: Need comment explaining why we do this. */
3683 case BFD_RELOC_SPARC22
:
3684 if (val
& ~0x003fffff)
3685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3686 _("relocation overflow"));
3687 insn
|= (val
& 0x3fffff);
3690 case BFD_RELOC_SPARC_HM10
:
3691 val
= BSR (val
, 32);
3694 case BFD_RELOC_LO10
:
3695 if (!fixP
->fx_addsy
)
3696 insn
|= val
& 0x3ff;
3698 /* FIXME: Need comment explaining why we do this. */
3702 case BFD_RELOC_SPARC_OLO10
:
3704 val
+= fixP
->tc_fix_data
;
3707 case BFD_RELOC_SPARC13
:
3708 if (! in_signed_range (val
, 0x1fff))
3709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3710 _("relocation overflow"));
3711 insn
|= val
& 0x1fff;
3714 case BFD_RELOC_SPARC_WDISP22
:
3715 val
= (val
>> 2) + 1;
3717 case BFD_RELOC_SPARC_BASE22
:
3718 insn
|= val
& 0x3fffff;
3721 case BFD_RELOC_SPARC_H34
:
3722 if (!fixP
->fx_addsy
)
3726 insn
|= tval
& 0x3fffff;
3730 case BFD_RELOC_SPARC_H44
:
3731 if (!fixP
->fx_addsy
)
3735 insn
|= tval
& 0x3fffff;
3739 case BFD_RELOC_SPARC_M44
:
3740 if (!fixP
->fx_addsy
)
3741 insn
|= (val
>> 12) & 0x3ff;
3744 case BFD_RELOC_SPARC_L44
:
3745 if (!fixP
->fx_addsy
)
3746 insn
|= val
& 0xfff;
3749 case BFD_RELOC_SPARC_HIX22
:
3750 if (!fixP
->fx_addsy
)
3752 val
^= ~(offsetT
) 0;
3753 insn
|= (val
>> 10) & 0x3fffff;
3757 case BFD_RELOC_SPARC_LOX10
:
3758 if (!fixP
->fx_addsy
)
3759 insn
|= 0x1c00 | (val
& 0x3ff);
3762 case BFD_RELOC_NONE
:
3764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3765 _("bad or unhandled relocation type: 0x%02x"),
3770 if (INSN_BIG_ENDIAN
)
3771 bfd_putb32 (insn
, (unsigned char *) buf
);
3773 bfd_putl32 (insn
, (unsigned char *) buf
);
3776 /* Are we finished with this relocation now? */
3777 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3781 /* Translate internal representation of relocation info to BFD target
3785 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3787 static arelent
*relocs
[3];
3789 bfd_reloc_code_real_type code
;
3791 relocs
[0] = reloc
= XNEW (arelent
);
3794 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3795 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3796 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3798 switch (fixp
->fx_r_type
)
3802 case BFD_RELOC_HI22
:
3803 case BFD_RELOC_LO10
:
3804 case BFD_RELOC_32_PCREL_S2
:
3805 case BFD_RELOC_SPARC13
:
3806 case BFD_RELOC_SPARC22
:
3807 case BFD_RELOC_SPARC_PC22
:
3808 case BFD_RELOC_SPARC_PC10
:
3809 case BFD_RELOC_SPARC_BASE13
:
3810 case BFD_RELOC_SPARC_WDISP10
:
3811 case BFD_RELOC_SPARC_WDISP16
:
3812 case BFD_RELOC_SPARC_WDISP19
:
3813 case BFD_RELOC_SPARC_WDISP22
:
3815 case BFD_RELOC_SPARC_5
:
3816 case BFD_RELOC_SPARC_6
:
3817 case BFD_RELOC_SPARC_7
:
3818 case BFD_RELOC_SPARC_10
:
3819 case BFD_RELOC_SPARC_11
:
3820 case BFD_RELOC_SPARC_HH22
:
3821 case BFD_RELOC_SPARC_HM10
:
3822 case BFD_RELOC_SPARC_LM22
:
3823 case BFD_RELOC_SPARC_PC_HH22
:
3824 case BFD_RELOC_SPARC_PC_HM10
:
3825 case BFD_RELOC_SPARC_PC_LM22
:
3826 case BFD_RELOC_SPARC_H34
:
3827 case BFD_RELOC_SPARC_H44
:
3828 case BFD_RELOC_SPARC_M44
:
3829 case BFD_RELOC_SPARC_L44
:
3830 case BFD_RELOC_SPARC_HIX22
:
3831 case BFD_RELOC_SPARC_LOX10
:
3832 case BFD_RELOC_SPARC_REV32
:
3833 case BFD_RELOC_SPARC_OLO10
:
3834 case BFD_RELOC_SPARC_UA16
:
3835 case BFD_RELOC_SPARC_UA32
:
3836 case BFD_RELOC_SPARC_UA64
:
3837 case BFD_RELOC_8_PCREL
:
3838 case BFD_RELOC_16_PCREL
:
3839 case BFD_RELOC_32_PCREL
:
3840 case BFD_RELOC_64_PCREL
:
3841 case BFD_RELOC_SPARC_PLT32
:
3842 case BFD_RELOC_SPARC_PLT64
:
3843 case BFD_RELOC_VTABLE_ENTRY
:
3844 case BFD_RELOC_VTABLE_INHERIT
:
3845 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3846 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3847 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3848 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3849 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3850 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3851 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3852 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3853 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3854 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3855 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3856 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3857 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3858 case BFD_RELOC_SPARC_TLS_IE_LD
:
3859 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3860 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3861 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3862 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3863 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3864 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3865 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3866 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3867 case BFD_RELOC_SPARC_GOTDATA_OP
:
3868 code
= fixp
->fx_r_type
;
3875 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3876 /* If we are generating PIC code, we need to generate a different
3880 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3882 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3885 #define GOTT_BASE "__GOTT_BASE__"
3886 #define GOTT_INDEX "__GOTT_INDEX__"
3889 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3895 case BFD_RELOC_32_PCREL_S2
:
3896 if (generic_force_reloc (fixp
))
3897 code
= BFD_RELOC_SPARC_WPLT30
;
3899 case BFD_RELOC_HI22
:
3900 code
= BFD_RELOC_SPARC_GOT22
;
3901 if (fixp
->fx_addsy
!= NULL
)
3903 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3904 code
= BFD_RELOC_SPARC_PC22
;
3906 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3907 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3908 code
= BFD_RELOC_HI22
; /* Unchanged. */
3912 case BFD_RELOC_LO10
:
3913 code
= BFD_RELOC_SPARC_GOT10
;
3914 if (fixp
->fx_addsy
!= NULL
)
3916 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3917 code
= BFD_RELOC_SPARC_PC10
;
3919 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3920 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3921 code
= BFD_RELOC_LO10
; /* Unchanged. */
3925 case BFD_RELOC_SPARC13
:
3926 code
= BFD_RELOC_SPARC_GOT13
;
3932 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3934 /* Nothing is aligned in DWARF debugging sections. */
3935 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3938 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3939 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3940 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3944 if (code
== BFD_RELOC_SPARC_OLO10
)
3945 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3947 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3948 if (reloc
->howto
== 0)
3950 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3951 _("internal error: can't export reloc type %d (`%s')"),
3952 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3958 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3961 if (reloc
->howto
->pc_relative
== 0
3962 || code
== BFD_RELOC_SPARC_PC10
3963 || code
== BFD_RELOC_SPARC_PC22
)
3964 reloc
->addend
= fixp
->fx_addnumber
;
3965 else if (sparc_pic_code
3966 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3967 && fixp
->fx_addsy
!= NULL
3968 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3969 || S_IS_WEAK (fixp
->fx_addsy
))
3970 && S_IS_DEFINED (fixp
->fx_addsy
)
3971 && ! S_IS_COMMON (fixp
->fx_addsy
))
3972 reloc
->addend
= fixp
->fx_addnumber
;
3974 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3976 #else /* elf or coff */
3978 if (code
!= BFD_RELOC_32_PCREL_S2
3979 && code
!= BFD_RELOC_SPARC_WDISP22
3980 && code
!= BFD_RELOC_SPARC_WDISP16
3981 && code
!= BFD_RELOC_SPARC_WDISP19
3982 && code
!= BFD_RELOC_SPARC_WDISP10
3983 && code
!= BFD_RELOC_SPARC_WPLT30
3984 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3985 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3986 reloc
->addend
= fixp
->fx_addnumber
;
3987 else if (symbol_section_p (fixp
->fx_addsy
))
3988 reloc
->addend
= (section
->vma
3989 + fixp
->fx_addnumber
3990 + md_pcrel_from (fixp
));
3992 reloc
->addend
= fixp
->fx_offset
;
3995 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3996 on the same location. */
3997 if (code
== BFD_RELOC_SPARC_OLO10
)
3999 relocs
[1] = reloc
= XNEW (arelent
);
4002 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4004 = symbol_get_bfdsym (section_symbol (absolute_section
));
4005 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4006 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4007 reloc
->addend
= fixp
->tc_fix_data
;
4013 /* We have no need to default values of symbols. */
4016 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4021 /* Round up a section size to the appropriate boundary. */
4024 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4027 /* This is not right for ELF; a.out wants it, and COFF will force
4028 the alignment anyways. */
4029 valueT align
= ((valueT
) 1
4030 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4033 /* Turn alignment value into a mask. */
4035 newsize
= (size
+ align
) & ~align
;
4042 /* Exactly what point is a PC-relative offset relative TO?
4043 On the sparc, they're relative to the address of the offset, plus
4044 its size. This gets us to the following instruction.
4045 (??? Is this right? FIXME-SOON) */
4047 md_pcrel_from (fixS
*fixP
)
4051 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4052 if (! sparc_pic_code
4053 || fixP
->fx_addsy
== NULL
4054 || symbol_section_p (fixP
->fx_addsy
))
4055 ret
+= fixP
->fx_size
;
4059 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4070 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4073 return (value
== 1) ? shift
: -1;
4076 /* Sort of like s_lcomm. */
4079 static int max_alignment
= 15;
4083 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4093 c
= get_symbol_name (&name
);
4094 p
= input_line_pointer
;
4096 SKIP_WHITESPACE_AFTER_NAME ();
4098 if (*input_line_pointer
!= ',')
4100 as_bad (_("Expected comma after name"));
4101 ignore_rest_of_line ();
4105 ++input_line_pointer
;
4107 if ((size
= get_absolute_expression ()) < 0)
4109 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4110 ignore_rest_of_line ();
4115 symbolP
= symbol_find_or_make (name
);
4118 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4119 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4121 as_bad (_("bad .reserve segment -- expected BSS segment"));
4125 if (input_line_pointer
[2] == '.')
4126 input_line_pointer
+= 7;
4128 input_line_pointer
+= 6;
4131 if (*input_line_pointer
== ',')
4133 ++input_line_pointer
;
4136 if (*input_line_pointer
== '\n')
4138 as_bad (_("missing alignment"));
4139 ignore_rest_of_line ();
4143 align
= (int) get_absolute_expression ();
4146 if (align
> max_alignment
)
4148 align
= max_alignment
;
4149 as_warn (_("alignment too large; assuming %d"), align
);
4155 as_bad (_("negative alignment"));
4156 ignore_rest_of_line ();
4162 temp
= mylog2 (align
);
4165 as_bad (_("alignment not a power of 2"));
4166 ignore_rest_of_line ();
4173 record_alignment (bss_section
, align
);
4178 if (!S_IS_DEFINED (symbolP
)
4180 && S_GET_OTHER (symbolP
) == 0
4181 && S_GET_DESC (symbolP
) == 0
4188 segT current_seg
= now_seg
;
4189 subsegT current_subseg
= now_subseg
;
4191 /* Switch to bss. */
4192 subseg_set (bss_section
, 1);
4196 frag_align (align
, 0, 0);
4198 /* Detach from old frag. */
4199 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4200 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4202 symbol_set_frag (symbolP
, frag_now
);
4203 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4204 (offsetT
) size
, (char *) 0);
4207 S_SET_SEGMENT (symbolP
, bss_section
);
4209 subseg_set (current_seg
, current_subseg
);
4212 S_SET_SIZE (symbolP
, size
);
4218 as_warn (_("Ignoring attempt to re-define symbol %s"),
4219 S_GET_NAME (symbolP
));
4222 demand_empty_rest_of_line ();
4226 s_common (int ignore ATTRIBUTE_UNUSED
)
4234 c
= get_symbol_name (&name
);
4235 /* Just after name is now '\0'. */
4236 p
= input_line_pointer
;
4238 SKIP_WHITESPACE_AFTER_NAME ();
4239 if (*input_line_pointer
!= ',')
4241 as_bad (_("Expected comma after symbol-name"));
4242 ignore_rest_of_line ();
4247 input_line_pointer
++;
4249 if ((temp
= get_absolute_expression ()) < 0)
4251 as_bad (_(".COMMon length (%lu) out of range ignored"),
4252 (unsigned long) temp
);
4253 ignore_rest_of_line ();
4258 symbolP
= symbol_find_or_make (name
);
4260 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4262 as_bad (_("Ignoring attempt to re-define symbol"));
4263 ignore_rest_of_line ();
4266 if (S_GET_VALUE (symbolP
) != 0)
4268 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4270 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4271 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4277 S_SET_VALUE (symbolP
, (valueT
) size
);
4278 S_SET_EXTERNAL (symbolP
);
4281 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4282 if (*input_line_pointer
!= ',')
4284 as_bad (_("Expected comma after common length"));
4285 ignore_rest_of_line ();
4288 input_line_pointer
++;
4290 if (*input_line_pointer
!= '"')
4292 temp
= get_absolute_expression ();
4295 if (temp
> max_alignment
)
4297 temp
= max_alignment
;
4298 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4304 as_bad (_("negative alignment"));
4305 ignore_rest_of_line ();
4310 if (symbol_get_obj (symbolP
)->local
)
4317 old_subsec
= now_subseg
;
4322 align
= mylog2 (temp
);
4326 as_bad (_("alignment not a power of 2"));
4327 ignore_rest_of_line ();
4331 record_alignment (bss_section
, align
);
4332 subseg_set (bss_section
, 0);
4334 frag_align (align
, 0, 0);
4335 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4336 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4337 symbol_set_frag (symbolP
, frag_now
);
4338 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4339 (offsetT
) size
, (char *) 0);
4341 S_SET_SEGMENT (symbolP
, bss_section
);
4342 S_CLEAR_EXTERNAL (symbolP
);
4343 S_SET_SIZE (symbolP
, size
);
4344 subseg_set (old_sec
, old_subsec
);
4347 #endif /* OBJ_ELF */
4350 S_SET_VALUE (symbolP
, (valueT
) size
);
4352 S_SET_ALIGN (symbolP
, temp
);
4353 S_SET_SIZE (symbolP
, size
);
4355 S_SET_EXTERNAL (symbolP
);
4356 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4361 input_line_pointer
++;
4362 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4363 if (*input_line_pointer
== '.')
4364 input_line_pointer
++;
4365 /* @@ Some say data, some say bss. */
4366 if (strncmp (input_line_pointer
, "bss\"", 4)
4367 && strncmp (input_line_pointer
, "data\"", 5))
4369 while (*--input_line_pointer
!= '"')
4371 input_line_pointer
--;
4372 goto bad_common_segment
;
4374 while (*input_line_pointer
++ != '"')
4376 goto allocate_common
;
4379 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4381 demand_empty_rest_of_line ();
4386 p
= input_line_pointer
;
4387 while (*p
&& *p
!= '\n')
4391 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4393 input_line_pointer
= p
;
4394 ignore_rest_of_line ();
4399 /* Handle the .empty pseudo-op. This suppresses the warnings about
4400 invalid delay slot usage. */
4403 s_empty (int ignore ATTRIBUTE_UNUSED
)
4405 /* The easy way to implement is to just forget about the last
4411 s_seg (int ignore ATTRIBUTE_UNUSED
)
4414 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4416 input_line_pointer
+= 6;
4420 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4422 input_line_pointer
+= 6;
4426 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4428 input_line_pointer
+= 7;
4432 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4434 input_line_pointer
+= 5;
4435 /* We only support 2 segments -- text and data -- for now, so
4436 things in the "bss segment" will have to go into data for now.
4437 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4438 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4441 as_bad (_("Unknown segment type"));
4442 demand_empty_rest_of_line ();
4448 subseg_set (data_section
, 1);
4449 demand_empty_rest_of_line ();
4453 s_proc (int ignore ATTRIBUTE_UNUSED
)
4455 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4457 ++input_line_pointer
;
4459 ++input_line_pointer
;
4462 /* This static variable is set by s_uacons to tell sparc_cons_align
4463 that the expression does not need to be aligned. */
4465 static int sparc_no_align_cons
= 0;
4467 /* This handles the unaligned space allocation pseudo-ops, such as
4468 .uaword. .uaword is just like .word, but the value does not need
4472 s_uacons (int bytes
)
4474 /* Tell sparc_cons_align not to align this value. */
4475 sparc_no_align_cons
= 1;
4477 sparc_no_align_cons
= 0;
4480 /* This handles the native word allocation pseudo-op .nword.
4481 For sparc_arch_size 32 it is equivalent to .word, for
4482 sparc_arch_size 64 it is equivalent to .xword. */
4485 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4487 cons (sparc_arch_size
== 32 ? 4 : 8);
4491 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4495 .register %g[2367],{#scratch|symbolname|#ignore}
4499 s_register (int ignore ATTRIBUTE_UNUSED
)
4506 if (input_line_pointer
[0] != '%'
4507 || input_line_pointer
[1] != 'g'
4508 || ((input_line_pointer
[2] & ~1) != '2'
4509 && (input_line_pointer
[2] & ~1) != '6')
4510 || input_line_pointer
[3] != ',')
4511 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4512 reg
= input_line_pointer
[2] - '0';
4513 input_line_pointer
+= 4;
4515 if (*input_line_pointer
== '#')
4517 ++input_line_pointer
;
4518 c
= get_symbol_name (®name
);
4519 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4520 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4521 if (regname
[0] == 'i')
4524 regname
= (char *) "";
4528 c
= get_symbol_name (®name
);
4531 if (sparc_arch_size
== 64)
4535 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4536 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4537 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4538 as_bad (_("redefinition of global register"));
4542 if (regname
== NULL
)
4543 globals
[reg
] = (symbolS
*) 1;
4548 if (symbol_find (regname
))
4549 as_bad (_("Register symbol %s already defined."),
4552 globals
[reg
] = symbol_make (regname
);
4553 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4555 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4556 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4557 flags
|= BSF_GLOBAL
;
4558 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4559 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4560 S_SET_ALIGN (globals
[reg
], reg
);
4561 S_SET_SIZE (globals
[reg
], 0);
4562 /* Although we actually want undefined_section here,
4563 we have to use absolute_section, because otherwise
4564 generic as code will make it a COM section.
4565 We fix this up in sparc_adjust_symtab. */
4566 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4567 S_SET_OTHER (globals
[reg
], 0);
4568 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4569 ->internal_elf_sym
.st_info
=
4570 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4571 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4572 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4577 (void) restore_line_pointer (c
);
4579 demand_empty_rest_of_line ();
4582 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4583 symbols which need it. */
4586 sparc_adjust_symtab (void)
4590 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4592 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4593 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4596 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4597 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4600 S_SET_SEGMENT (sym
, undefined_section
);
4605 /* If the --enforce-aligned-data option is used, we require .word,
4606 et. al., to be aligned correctly. We do it by setting up an
4607 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4608 no unexpected alignment was introduced.
4610 The SunOS and Solaris native assemblers enforce aligned data by
4611 default. We don't want to do that, because gcc can deliberately
4612 generate misaligned data if the packed attribute is used. Instead,
4613 we permit misaligned data by default, and permit the user to set an
4614 option to check for it. */
4617 sparc_cons_align (int nbytes
)
4621 /* Only do this if we are enforcing aligned data. */
4622 if (! enforce_aligned_data
)
4625 /* Don't align if this is an unaligned pseudo-op. */
4626 if (sparc_no_align_cons
)
4629 nalign
= mylog2 (nbytes
);
4633 gas_assert (nalign
> 0);
4635 if (now_seg
== absolute_section
)
4637 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4638 as_bad (_("misaligned data"));
4642 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4643 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4645 record_alignment (now_seg
, nalign
);
4648 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4651 sparc_handle_align (fragS
*fragp
)
4656 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4658 switch (fragp
->fr_type
)
4662 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4666 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4677 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4679 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4680 if (INSN_BIG_ENDIAN
)
4681 number_to_chars_bigendian (p
, wval
, 4);
4683 number_to_chars_littleendian (p
, wval
, 4);
4689 if (INSN_BIG_ENDIAN
)
4690 number_to_chars_bigendian (p
, 0x01000000, 4);
4692 number_to_chars_littleendian (p
, 0x01000000, 4);
4694 fragp
->fr_fix
+= fix
;
4704 /* Some special processing for a Sparc ELF file. */
4707 sparc_elf_final_processing (void)
4709 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4710 sort of BFD interface for this. */
4711 if (sparc_arch_size
== 64)
4713 switch (sparc_memory_model
)
4716 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4719 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4725 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4726 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4727 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4728 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4729 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4730 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4734 sparc_cons (expressionS
*exp
, int size
)
4737 const char *sparc_cons_special_reloc
= NULL
;
4740 save
= input_line_pointer
;
4741 if (input_line_pointer
[0] == '%'
4742 && input_line_pointer
[1] == 'r'
4743 && input_line_pointer
[2] == '_')
4745 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4747 input_line_pointer
+= 7;
4748 sparc_cons_special_reloc
= "disp";
4750 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4752 if (size
!= 4 && size
!= 8)
4753 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4756 input_line_pointer
+= 6;
4757 sparc_cons_special_reloc
= "plt";
4760 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4762 if (size
!= 4 && size
!= 8)
4763 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4766 input_line_pointer
+= 13;
4767 sparc_cons_special_reloc
= "tls_dtpoff";
4770 if (sparc_cons_special_reloc
)
4777 if (*input_line_pointer
!= '8')
4779 input_line_pointer
--;
4782 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4786 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4790 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4800 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4801 sparc_cons_special_reloc
, size
* 8, size
);
4805 input_line_pointer
+= 2;
4806 if (*input_line_pointer
!= '(')
4808 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4809 sparc_cons_special_reloc
, size
* 8);
4816 input_line_pointer
= save
;
4817 sparc_cons_special_reloc
= NULL
;
4822 char *end
= ++input_line_pointer
;
4825 while (! is_end_of_line
[(c
= *end
)])
4839 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4840 sparc_cons_special_reloc
, size
* 8);
4846 if (input_line_pointer
!= end
)
4848 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4849 sparc_cons_special_reloc
, size
* 8);
4853 input_line_pointer
++;
4855 c
= *input_line_pointer
;
4856 if (! is_end_of_line
[c
] && c
!= ',')
4857 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4858 sparc_cons_special_reloc
, size
* 8);
4864 if (sparc_cons_special_reloc
== NULL
)
4866 return sparc_cons_special_reloc
;
4871 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4872 reloc for a cons. We could use the definition there, except that
4873 we want to handle little endian relocs specially. */
4876 cons_fix_new_sparc (fragS
*frag
,
4878 unsigned int nbytes
,
4880 const char *sparc_cons_special_reloc
)
4882 bfd_reloc_code_real_type r
;
4884 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4885 (nbytes
== 2 ? BFD_RELOC_16
:
4886 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4888 if (target_little_endian_data
4890 && now_seg
->flags
& SEC_ALLOC
)
4891 r
= BFD_RELOC_SPARC_REV32
;
4894 /* The Solaris linker does not allow R_SPARC_UA64
4895 relocations for 32-bit executables. */
4896 if (!target_little_endian_data
4897 && sparc_arch_size
!= 64
4898 && r
== BFD_RELOC_64
)
4902 if (sparc_cons_special_reloc
)
4904 if (*sparc_cons_special_reloc
== 'd')
4907 case 1: r
= BFD_RELOC_8_PCREL
; break;
4908 case 2: r
= BFD_RELOC_16_PCREL
; break;
4909 case 4: r
= BFD_RELOC_32_PCREL
; break;
4910 case 8: r
= BFD_RELOC_64_PCREL
; break;
4913 else if (*sparc_cons_special_reloc
== 'p')
4916 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4917 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4922 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4923 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4926 else if (sparc_no_align_cons
)
4930 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4931 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4933 /* The Solaris linker does not allow R_SPARC_UA64
4934 relocations for 32-bit executables. */
4935 case 8: r
= sparc_arch_size
== 64 ?
4936 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
4938 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4944 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4948 sparc_cfi_frame_initial_instructions (void)
4950 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4954 sparc_regname_to_dw2regnum (char *regname
)
4964 case 'g': i
= 0; break;
4965 case 'o': i
= 1; break;
4966 case 'l': i
= 2; break;
4967 case 'i': i
= 3; break;
4968 default: i
= -1; break;
4972 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4974 return i
* 8 + regname
[1] - '0';
4976 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4978 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4980 if (regname
[0] == 'f' || regname
[0] == 'r')
4982 unsigned int regnum
;
4984 regnum
= strtoul (regname
+ 1, &q
, 10);
4985 if (q
== NULL
|| *q
)
4987 if (regnum
>= ((regname
[0] == 'f'
4988 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4991 if (regname
[0] == 'f')
4994 if (regnum
>= 64 && (regnum
& 1))
5003 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5005 sparc_no_align_cons
= 1;
5006 emit_expr_with_reloc (exp
, nbytes
, "disp");
5007 sparc_no_align_cons
= 0;