1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
30 #include "elf/sparc.h"
33 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
34 static void init_default_arch
PARAMS ((void));
35 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
36 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
37 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
38 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
39 static int sparc_ffs
PARAMS ((unsigned int));
40 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
41 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
42 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
43 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
44 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
45 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
46 static int parse_const_expr_arg
PARAMS ((char **, int *));
47 static int get_expression
PARAMS ((char *str
));
49 /* Default architecture. */
50 /* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
54 #define DEFAULT_ARCH "sparclite"
56 static char *default_arch
= DEFAULT_ARCH
;
58 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
60 static int default_init_p
;
62 /* Current architecture. We don't bump up unless necessary. */
63 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
65 /* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70 static enum sparc_opcode_arch_val max_architecture
;
72 /* Either 32 or 64, selects file format. */
73 static int sparc_arch_size
;
74 /* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76 static int default_arch_size
;
79 /* The currently selected v9 memory model. Currently only used for
81 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
84 static int architecture_requested
;
85 static int warn_on_bump
;
87 /* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89 static enum sparc_opcode_arch_val warn_after_architecture
;
91 /* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93 static int no_undeclared_regs
;
95 /* Non-zero if we should try to relax jumps and calls. */
96 static int sparc_relax
;
98 /* Non-zero if we are generating PIC code. */
101 /* Non-zero if we should give an error when misaligned data is seen. */
102 static int enforce_aligned_data
;
104 extern int target_big_endian
;
106 static int target_little_endian_data
;
108 /* Symbols for global registers on v9. */
109 static symbolS
*globals
[8];
111 /* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115 #ifndef INSN_BIG_ENDIAN
116 #define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
121 /* Handle of the OPCODE hash table. */
122 static struct hash_control
*op_hash
;
124 static int log2
PARAMS ((int));
125 static void s_data1
PARAMS ((void));
126 static void s_seg
PARAMS ((int));
127 static void s_proc
PARAMS ((int));
128 static void s_reserve
PARAMS ((int));
129 static void s_common
PARAMS ((int));
130 static void s_empty
PARAMS ((int));
131 static void s_uacons
PARAMS ((int));
132 static void s_ncons
PARAMS ((int));
133 static void s_register
PARAMS ((int));
135 const pseudo_typeS md_pseudo_table
[] =
137 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common
, 0},
139 {"empty", s_empty
, 0},
140 {"global", s_globl
, 0},
142 {"nword", s_ncons
, 0},
143 {"optim", s_ignore
, 0},
145 {"reserve", s_reserve
, 0},
147 {"skip", s_space
, 0},
150 {"uahalf", s_uacons
, 2},
151 {"uaword", s_uacons
, 4},
152 {"uaxword", s_uacons
, 8},
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons
, 2},
156 {"4byte", s_uacons
, 4},
157 {"8byte", s_uacons
, 8},
158 {"register", s_register
, 0},
163 /* Size of relocation record. */
164 const int md_reloc_size
= 12;
166 /* This array holds the chars that always start a comment. If the
167 pre-processor is disabled, these aren't very useful. */
168 const char comment_chars
[] = "!"; /* JF removed '|' from
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output. */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that comments started like this one will always
178 work if '/' isn't otherwise defined. */
179 const char line_comment_chars
[] = "#";
181 const char line_separator_chars
[] = ";";
183 /* Chars that can be used to separate mant from exp in floating point
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant.
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
196 #define isoctal(c) ((unsigned)((c) - '0') < '8')
201 unsigned long opcode
;
202 struct nlist
*nlistp
;
206 bfd_reloc_code_real_type reloc
;
209 struct sparc_it the_insn
, set_insn
;
211 static void output_insn
212 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
220 v8plusa
, v9
, v9a
, v9_64
};
222 static struct sparc_arch
{
225 enum sparc_arch_types arch_type
;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size
;
229 /* Allowable arg to -A? */
231 } sparc_arch_table
[] = {
232 { "v6", "v6", v6
, 0, 1 },
233 { "v7", "v7", v7
, 0, 1 },
234 { "v8", "v8", v8
, 32, 1 },
235 { "sparclet", "sparclet", sparclet
, 32, 1 },
236 { "sparclite", "sparclite", sparclite
, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
238 { "v8plus", "v9", v9
, 0, 1 },
239 { "v8plusa", "v9a", v9
, 0, 1 },
240 { "v9", "v9", v9
, 0, 1 },
241 { "v9a", "v9a", v9
, 0, 1 },
242 /* This exists to allow configure.in/Makefile.in to pass one
243 value to specify both the default machine and default word size. */
244 { "v9-64", "v9", v9
, 64, 0 },
245 { NULL
, NULL
, v8
, 0, 0 }
248 /* Variant of default_arch */
249 static enum sparc_arch_types default_arch_type
;
251 static struct sparc_arch
*
255 struct sparc_arch
*sa
;
257 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
258 if (strcmp (sa
->name
, name
) == 0)
260 if (sa
->name
== NULL
)
265 /* Initialize the default opcode arch and word size from the default
266 architecture name. */
271 struct sparc_arch
*sa
= lookup_arch (default_arch
);
274 || sa
->default_arch_size
== 0)
275 as_fatal (_("Invalid default architecture, broken assembler."));
277 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
278 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
279 as_fatal (_("Bad opcode table, broken assembler."));
280 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
282 default_arch_type
= sa
->arch_type
;
285 /* Called by TARGET_FORMAT. */
288 sparc_target_format ()
290 /* We don't get a chance to initialize anything before we're called,
291 so handle that now. */
292 if (! default_init_p
)
293 init_default_arch ();
297 return "a.out-sparc-netbsd";
300 if (target_big_endian
)
301 return "a.out-sunos-big";
302 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
303 return "a.out-sunos-big";
305 return "a.out-sparc-little";
307 return "a.out-sunos-big";
318 return "coff-sparc-lynx";
325 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
332 * Invocation line includes a switch not recognized by the base assembler.
333 * See if it's a processor-specific option. These are:
336 * Warn on architecture bumps. See also -A.
338 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
339 * Standard 32 bit architectures.
341 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
342 * This used to only mean 64 bits, but properly specifying it
343 * complicated gcc's ASM_SPECs, so now opcode selection is
344 * specified orthogonally to word size (except when specifying
345 * the default, but that is an internal implementation detail).
346 * -Av8plus, -Av8plusa
348 * -xarch=v8plus, -xarch=v8plusa
349 * Same as -Av8plus{,a} -32, for compatibility with Sun's
351 * -xarch=v9, -xarch=v9a
352 * Same as -Av9{,a} -64, for compatibility with Sun's assembler.
354 * Select the architecture and possibly the file format.
355 * Instructions or features not supported by the selected
356 * architecture cause fatal errors.
358 * The default is to start at v6, and bump the architecture up
359 * whenever an instruction is seen at a higher level. In 32 bit
360 * environments, v9 is not bumped up to, the user must pass
363 * If -bump is specified, a warning is printing when bumping to
366 * If an architecture is specified, all instructions must match
367 * that architecture. Any higher level instructions are flagged
368 * as errors. Note that in the 32 bit environment specifying
369 * -Av8plus does not automatically create a v8plus object file, a
370 * v9 insn must be seen.
372 * If both an architecture and -bump are specified, the
373 * architecture starts at the specified level, but bumps are
374 * warnings. Note that we can't set `current_architecture' to
375 * the requested level in this case: in the 32 bit environment,
376 * we still must avoid creating v8plus object files unless v9
380 * Bumping between incompatible architectures is always an
381 * error. For example, from sparclite to v9.
385 CONST
char *md_shortopts
= "A:K:VQ:sq";
388 CONST
char *md_shortopts
= "A:k";
390 CONST
char *md_shortopts
= "A:";
393 struct option md_longopts
[] = {
394 #define OPTION_BUMP (OPTION_MD_BASE)
395 {"bump", no_argument
, NULL
, OPTION_BUMP
},
396 #define OPTION_SPARC (OPTION_MD_BASE + 1)
397 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
398 #define OPTION_XARCH (OPTION_MD_BASE + 2)
399 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
401 #define OPTION_32 (OPTION_MD_BASE + 3)
402 {"32", no_argument
, NULL
, OPTION_32
},
403 #define OPTION_64 (OPTION_MD_BASE + 4)
404 {"64", no_argument
, NULL
, OPTION_64
},
405 #define OPTION_TSO (OPTION_MD_BASE + 5)
406 {"TSO", no_argument
, NULL
, OPTION_TSO
},
407 #define OPTION_PSO (OPTION_MD_BASE + 6)
408 {"PSO", no_argument
, NULL
, OPTION_PSO
},
409 #define OPTION_RMO (OPTION_MD_BASE + 7)
410 {"RMO", no_argument
, NULL
, OPTION_RMO
},
412 #ifdef SPARC_BIENDIAN
413 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
414 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
415 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
416 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
418 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
419 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
420 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
421 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
423 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
424 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
425 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
426 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
428 #define OPTION_RELAX (OPTION_MD_BASE + 14)
429 {"relax", no_argument
, NULL
, OPTION_RELAX
},
430 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
431 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
432 {NULL
, no_argument
, NULL
, 0}
435 size_t md_longopts_size
= sizeof (md_longopts
);
438 md_parse_option (c
, arg
)
442 /* We don't get a chance to initialize anything before we're called,
443 so handle that now. */
444 if (! default_init_p
)
445 init_default_arch ();
451 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
456 if (strncmp (arg
, "v9", 2) != 0)
457 md_parse_option (OPTION_32
, NULL
);
459 md_parse_option (OPTION_64
, NULL
);
465 struct sparc_arch
*sa
;
466 enum sparc_opcode_arch_val opcode_arch
;
468 sa
= lookup_arch (arg
);
470 || ! sa
->user_option_p
)
472 if (c
== OPTION_XARCH
)
473 as_bad (_("invalid architecture -xarch=%s"), arg
);
475 as_bad (_("invalid architecture -A%s"), arg
);
479 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
480 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
481 as_fatal (_("Bad opcode table, broken assembler."));
483 max_architecture
= opcode_arch
;
484 architecture_requested
= 1;
489 /* Ignore -sparc, used by SunOS make default .s.o rule. */
492 case OPTION_ENFORCE_ALIGNED_DATA
:
493 enforce_aligned_data
= 1;
496 #ifdef SPARC_BIENDIAN
497 case OPTION_LITTLE_ENDIAN
:
498 target_big_endian
= 0;
499 if (default_arch_type
!= sparclet
)
500 as_fatal ("This target does not support -EL");
502 case OPTION_LITTLE_ENDIAN_DATA
:
503 target_little_endian_data
= 1;
504 target_big_endian
= 0;
505 if (default_arch_type
!= sparc86x
506 && default_arch_type
!= v9
)
507 as_fatal ("This target does not support --little-endian-data");
509 case OPTION_BIG_ENDIAN
:
510 target_big_endian
= 1;
524 const char **list
, **l
;
526 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
527 list
= bfd_target_list ();
528 for (l
= list
; *l
!= NULL
; l
++)
530 if (sparc_arch_size
== 32)
532 if (strcmp (*l
, "elf32-sparc") == 0)
537 if (strcmp (*l
, "elf64-sparc") == 0)
542 as_fatal (_("No compiled in support for %d bit object file format"),
549 sparc_memory_model
= MM_TSO
;
553 sparc_memory_model
= MM_PSO
;
557 sparc_memory_model
= MM_RMO
;
565 /* Qy - do emit .comment
566 Qn - do not emit .comment. */
570 /* Use .stab instead of .stab.excl. */
574 /* quick -- Native assembler does fewer checks. */
578 if (strcmp (arg
, "PIC") != 0)
579 as_warn (_("Unrecognized option following -K"));
584 case OPTION_NO_UNDECLARED_REGS
:
585 no_undeclared_regs
= 1;
588 case OPTION_UNDECLARED_REGS
:
589 no_undeclared_regs
= 0;
597 case OPTION_NO_RELAX
:
609 md_show_usage (stream
)
612 const struct sparc_arch
*arch
;
615 /* We don't get a chance to initialize anything before we're called,
616 so handle that now. */
617 if (! default_init_p
)
618 init_default_arch ();
620 fprintf (stream
, _("SPARC options:\n"));
622 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
624 if (!arch
->user_option_p
)
626 if (arch
!= &sparc_arch_table
[0])
627 fprintf (stream
, " | ");
628 if (column
+ strlen(arch
->name
) > 70)
631 fputc ('\n', stream
);
633 column
+= 5 + 2 + strlen(arch
->name
);
634 fprintf (stream
, "-A%s", arch
->name
);
636 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
638 if (!arch
->user_option_p
)
640 fprintf (stream
, " | ");
641 if (column
+ strlen(arch
->name
) > 65)
644 fputc ('\n', stream
);
646 column
+= 5 + 7 + strlen(arch
->name
);
647 fprintf (stream
, "-xarch=%s", arch
->name
);
649 fprintf (stream
, _("\n\
650 specify variant of SPARC architecture\n\
651 -bump warn when assembler switches architectures\n\
653 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
654 -relax relax jumps and branches (default)\n\
655 -no-relax avoid changing any jumps and branches\n"));
657 fprintf (stream
, _("\
658 -k generate PIC\n"));
661 fprintf (stream
, _("\
662 -32 create 32 bit object file\n\
663 -64 create 64 bit object file\n"));
664 fprintf (stream
, _("\
665 [default is %d]\n"), default_arch_size
);
666 fprintf (stream
, _("\
667 -TSO use Total Store Ordering\n\
668 -PSO use Partial Store Ordering\n\
669 -RMO use Relaxed Memory Ordering\n"));
670 fprintf (stream
, _("\
671 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
672 fprintf (stream
, _("\
673 -KPIC generate PIC\n\
674 -V print assembler version number\n\
675 -undeclared-regs ignore application global register usage without\n\
676 appropriate .register directive (default)\n\
677 -no-undeclared-regs force error on application global register usage\n\
678 without appropriate .register directive\n\
683 #ifdef SPARC_BIENDIAN
684 fprintf (stream
, _("\
685 -EL generate code for a little endian machine\n\
686 -EB generate code for a big endian machine\n\
687 --little-endian-data generate code for a machine having big endian\n\
688 instructions and little endian data.\n"));
692 /* Native operand size opcode translation. */
698 } native_op_table
[] =
700 {"ldn", "ld", "ldx"},
701 {"ldna", "lda", "ldxa"},
702 {"stn", "st", "stx"},
703 {"stna", "sta", "stxa"},
704 {"slln", "sll", "sllx"},
705 {"srln", "srl", "srlx"},
706 {"sran", "sra", "srax"},
707 {"casn", "cas", "casx"},
708 {"casna", "casa", "casxa"},
709 {"clrn", "clr", "clrx"},
713 /* sparc64 priviledged registers. */
715 struct priv_reg_entry
721 struct priv_reg_entry priv_reg_table
[] =
740 {"", -1}, /* End marker. */
743 /* v9a specific asrs. */
745 struct priv_reg_entry v9a_asr_table
[] =
754 {"clear_softint", 21},
755 {"", -1}, /* End marker. */
759 cmp_reg_entry (parg
, qarg
)
763 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
764 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
766 return strcmp (q
->name
, p
->name
);
769 /* This function is called once, at assembler startup time. It should
770 set up all the tables, etc. that the MD part of the assembler will
776 register const char *retval
= NULL
;
778 register unsigned int i
= 0;
780 /* We don't get a chance to initialize anything before md_parse_option
781 is called, and it may not be called, so handle default initialization
782 now if not already done. */
783 if (! default_init_p
)
784 init_default_arch ();
786 op_hash
= hash_new ();
788 while (i
< (unsigned int) sparc_num_opcodes
)
790 const char *name
= sparc_opcodes
[i
].name
;
791 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
794 as_bad (_("Internal error: can't hash `%s': %s\n"),
795 sparc_opcodes
[i
].name
, retval
);
800 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
802 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
803 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
808 while (i
< (unsigned int) sparc_num_opcodes
809 && !strcmp (sparc_opcodes
[i
].name
, name
));
812 for (i
= 0; native_op_table
[i
].name
; i
++)
814 const struct sparc_opcode
*insn
;
815 char *name
= ((sparc_arch_size
== 32)
816 ? native_op_table
[i
].name32
817 : native_op_table
[i
].name64
);
818 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
821 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
822 name
, native_op_table
[i
].name
);
827 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
830 as_bad (_("Internal error: can't hash `%s': %s\n"),
831 sparc_opcodes
[i
].name
, retval
);
838 as_fatal (_("Broken assembler. No assembly attempted."));
840 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
841 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
843 /* If -bump, record the architecture level at which we start issuing
844 warnings. The behaviour is different depending upon whether an
845 architecture was explicitly specified. If it wasn't, we issue warnings
846 for all upwards bumps. If it was, we don't start issuing warnings until
847 we need to bump beyond the requested architecture or when we bump between
848 conflicting architectures. */
851 && architecture_requested
)
853 /* `max_architecture' records the requested architecture.
854 Issue warnings if we go above it. */
855 warn_after_architecture
= max_architecture
;
857 /* Find the highest architecture level that doesn't conflict with
858 the requested one. */
859 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
860 max_architecture
> warn_after_architecture
;
862 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
863 warn_after_architecture
))
868 /* Called after all assembly has been done. */
873 if (sparc_arch_size
== 64)
875 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
876 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
878 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
882 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
883 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
884 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
885 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
886 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
887 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
888 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
889 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclite_le
);
892 /* The sparclite is treated like a normal sparc. Perhaps it
893 shouldn't be but for now it is (since that's the way it's
894 always been treated). */
895 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
900 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
903 in_signed_range (val
, max
)
904 bfd_signed_vma val
, max
;
908 /* Sign-extend the value from the architecture word size, so that
909 0xffffffff is always considered -1 on sparc32. */
910 if (sparc_arch_size
== 32)
912 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
913 val
= ((val
& 0xffffffff) ^ sign
) - sign
;
922 /* Return non-zero if VAL is in the range 0 to MAX. */
925 in_unsigned_range (val
, max
)
933 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
934 (e.g. -15 to +31). */
937 in_bitfield_range (val
, max
)
938 bfd_signed_vma val
, max
;
944 if (val
< ~(max
>> 1))
958 for (i
= 0; (mask
& 1) == 0; ++i
)
963 /* Implement big shift right. */
969 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
970 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
971 return val
>> amount
;
974 /* For communication between sparc_ip and get_expression. */
975 static char *expr_end
;
977 /* Values for `special_case'.
978 Instructions that require wierd handling because they're longer than
980 #define SPECIAL_CASE_NONE 0
981 #define SPECIAL_CASE_SET 1
982 #define SPECIAL_CASE_SETSW 2
983 #define SPECIAL_CASE_SETX 3
984 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
985 #define SPECIAL_CASE_FDIV 4
987 /* Bit masks of various insns. */
988 #define NOP_INSN 0x01000000
989 #define OR_INSN 0x80100000
990 #define XOR_INSN 0x80180000
991 #define FMOVS_INSN 0x81A00020
992 #define SETHI_INSN 0x01000000
993 #define SLLX_INSN 0x81281000
994 #define SRA_INSN 0x81380000
996 /* The last instruction to be assembled. */
997 static const struct sparc_opcode
*last_insn
;
998 /* The assembled opcode of `last_insn'. */
999 static unsigned long last_opcode
;
1001 /* Handle the set and setuw synthetic instructions. */
1004 synthetize_setuw (insn
)
1005 const struct sparc_opcode
*insn
;
1007 int need_hi22_p
= 0;
1008 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1010 if (the_insn
.exp
.X_op
== O_constant
)
1012 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1014 if (sizeof (offsetT
) > 4
1015 && (the_insn
.exp
.X_add_number
< 0
1016 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1017 as_warn (_("set: number not in 0..4294967295 range"));
1021 if (sizeof (offsetT
) > 4
1022 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1023 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1024 as_warn (_("set: number not in -2147483648..4294967295 range"));
1025 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1029 /* See if operand is absolute and small; skip sethi if so. */
1030 if (the_insn
.exp
.X_op
!= O_constant
1031 || the_insn
.exp
.X_add_number
>= (1 << 12)
1032 || the_insn
.exp
.X_add_number
< -(1 << 12))
1034 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1035 | ((the_insn
.exp
.X_add_number
>> 10)
1036 & (the_insn
.exp
.X_op
== O_constant
1038 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1039 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1040 output_insn (insn
, &the_insn
);
1044 /* See if operand has no low-order bits; skip OR if so. */
1045 if (the_insn
.exp
.X_op
!= O_constant
1046 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1049 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1051 | (the_insn
.exp
.X_add_number
1052 & (the_insn
.exp
.X_op
!= O_constant
1053 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1054 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1055 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1056 output_insn (insn
, &the_insn
);
1060 /* Handle the setsw synthetic instruction. */
1063 synthetize_setsw (insn
)
1064 const struct sparc_opcode
*insn
;
1068 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1070 if (the_insn
.exp
.X_op
!= O_constant
)
1072 synthetize_setuw (insn
);
1074 /* Need to sign extend it. */
1075 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1076 the_insn
.reloc
= BFD_RELOC_NONE
;
1077 output_insn (insn
, &the_insn
);
1081 if (sizeof (offsetT
) > 4
1082 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1083 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1084 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1086 low32
= the_insn
.exp
.X_add_number
;
1090 synthetize_setuw (insn
);
1096 the_insn
.reloc
= BFD_RELOC_NONE
;
1097 /* See if operand is absolute and small; skip sethi if so. */
1098 if (low32
< -(1 << 12))
1100 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1101 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1102 output_insn (insn
, &the_insn
);
1103 low32
= 0x1c00 | (low32
& 0x3ff);
1104 opc
= RS1 (rd
) | XOR_INSN
;
1107 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1108 | (low32
& 0x1fff));
1109 output_insn (insn
, &the_insn
);
1112 /* Handle the setsw synthetic instruction. */
1115 synthetize_setx (insn
)
1116 const struct sparc_opcode
*insn
;
1118 int upper32
, lower32
;
1119 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1120 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1122 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1123 int need_xor10_p
= 0;
1125 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1126 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1127 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1130 upper_dstreg
= tmpreg
;
1131 /* The tmp reg should not be the dst reg. */
1132 if (tmpreg
== dstreg
)
1133 as_warn (_("setx: temporary register same as destination register"));
1135 /* ??? Obviously there are other optimizations we can do
1136 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1137 doing some of these. Later. If you do change things, try to
1138 change all of this to be table driven as well. */
1139 /* What to output depends on the number if it's constant.
1140 Compute that first, then output what we've decided upon. */
1141 if (the_insn
.exp
.X_op
!= O_constant
)
1143 if (sparc_arch_size
== 32)
1145 /* When arch size is 32, we want setx to be equivalent
1146 to setuw for anything but constants. */
1147 the_insn
.exp
.X_add_number
&= 0xffffffff;
1148 synthetize_setuw (insn
);
1151 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1157 /* Reset X_add_number, we've extracted it as upper32/lower32.
1158 Otherwise fixup_segment will complain about not being able to
1159 write an 8 byte number in a 4 byte field. */
1160 the_insn
.exp
.X_add_number
= 0;
1162 /* Only need hh22 if `or' insn can't handle constant. */
1163 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1166 /* Does bottom part (after sethi) have bits? */
1167 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1168 /* No hh22, but does upper32 still have bits we can't set
1170 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1173 /* If the lower half is all zero, we build the upper half directly
1174 into the dst reg. */
1176 /* Need lower half if number is zero or 0xffffffff00000000. */
1177 || (! need_hh22_p
&& ! need_hm10_p
))
1179 /* No need for sethi if `or' insn can handle constant. */
1180 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1181 /* Note that we can't use a negative constant in the `or'
1182 insn unless the upper 32 bits are all ones. */
1183 || (lower32
< 0 && upper32
!= -1)
1184 || (lower32
>= 0 && upper32
== -1))
1187 if (need_hi22_p
&& upper32
== -1)
1190 /* Does bottom part (after sethi) have bits? */
1191 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1193 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1194 /* Need `or' if we didn't set anything else. */
1195 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1199 /* Output directly to dst reg if lower 32 bits are all zero. */
1200 upper_dstreg
= dstreg
;
1203 if (!upper_dstreg
&& dstreg
)
1204 as_warn (_("setx: illegal temporary register g0"));
1208 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1209 | ((upper32
>> 10) & 0x3fffff));
1210 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1211 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1212 output_insn (insn
, &the_insn
);
1217 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1218 | (((need_xor10_p
? ~lower32
: lower32
)
1219 >> 10) & 0x3fffff));
1220 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1221 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1222 output_insn (insn
, &the_insn
);
1227 the_insn
.opcode
= (OR_INSN
1228 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1231 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1232 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1233 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1234 output_insn (insn
, &the_insn
);
1239 /* FIXME: One nice optimization to do here is to OR the low part
1240 with the highpart if hi22 isn't needed and the low part is
1242 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1245 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1246 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1247 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1248 output_insn (insn
, &the_insn
);
1251 /* If we needed to build the upper part, shift it into place. */
1252 if (need_hh22_p
|| need_hm10_p
)
1254 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1256 the_insn
.reloc
= BFD_RELOC_NONE
;
1257 output_insn (insn
, &the_insn
);
1260 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1263 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1264 | 0x1c00 | (lower32
& 0x3ff));
1265 the_insn
.reloc
= BFD_RELOC_NONE
;
1266 output_insn (insn
, &the_insn
);
1269 /* If we needed to build both upper and lower parts, OR them together. */
1270 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1272 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1274 the_insn
.reloc
= BFD_RELOC_NONE
;
1275 output_insn (insn
, &the_insn
);
1279 /* Main entry point to assemble one instruction. */
1285 const struct sparc_opcode
*insn
;
1289 special_case
= sparc_ip (str
, &insn
);
1291 /* We warn about attempts to put a floating point branch in a delay slot,
1292 unless the delay slot has been annulled. */
1294 && last_insn
!= NULL
1295 && (insn
->flags
& F_FBR
) != 0
1296 && (last_insn
->flags
& F_DELAYED
) != 0
1297 /* ??? This test isn't completely accurate. We assume anything with
1298 F_{UNBR,CONDBR,FBR} set is annullable. */
1299 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1300 || (last_opcode
& ANNUL
) == 0))
1301 as_warn (_("FP branch in delay slot"));
1303 /* SPARC before v9 requires a nop instruction between a floating
1304 point instruction and a floating point branch. We insert one
1305 automatically, with a warning. */
1306 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1308 && last_insn
!= NULL
1309 && (insn
->flags
& F_FBR
) != 0
1310 && (last_insn
->flags
& F_FLOAT
) != 0)
1312 struct sparc_it nop_insn
;
1314 nop_insn
.opcode
= NOP_INSN
;
1315 nop_insn
.reloc
= BFD_RELOC_NONE
;
1316 output_insn (insn
, &nop_insn
);
1317 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1320 switch (special_case
)
1322 case SPECIAL_CASE_NONE
:
1324 output_insn (insn
, &the_insn
);
1327 case SPECIAL_CASE_SETSW
:
1328 synthetize_setsw (insn
);
1331 case SPECIAL_CASE_SET
:
1332 synthetize_setuw (insn
);
1335 case SPECIAL_CASE_SETX
:
1336 synthetize_setx (insn
);
1339 case SPECIAL_CASE_FDIV
:
1341 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1343 output_insn (insn
, &the_insn
);
1345 /* According to information leaked from Sun, the "fdiv" instructions
1346 on early SPARC machines would produce incorrect results sometimes.
1347 The workaround is to add an fmovs of the destination register to
1348 itself just after the instruction. This was true on machines
1349 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1350 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1351 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1352 output_insn (insn
, &the_insn
);
1357 as_fatal (_("failed special case insn sanity check"));
1361 /* Subroutine of md_assemble to do the actual parsing. */
1364 sparc_ip (str
, pinsn
)
1366 const struct sparc_opcode
**pinsn
;
1368 char *error_message
= "";
1372 const struct sparc_opcode
*insn
;
1374 unsigned long opcode
;
1375 unsigned int mask
= 0;
1379 int special_case
= SPECIAL_CASE_NONE
;
1382 if (islower ((unsigned char) *s
))
1386 while (islower ((unsigned char) *s
) || isdigit ((unsigned char) *s
));
1403 as_fatal (_("Unknown opcode: `%s'"), str
);
1405 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1409 as_bad (_("Unknown opcode: `%s'"), str
);
1410 return special_case
;
1420 opcode
= insn
->match
;
1421 memset (&the_insn
, '\0', sizeof (the_insn
));
1422 the_insn
.reloc
= BFD_RELOC_NONE
;
1425 /* Build the opcode, checking as we go to make sure that the
1427 for (args
= insn
->args
;; ++args
)
1435 /* Parse a series of masks. */
1442 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1445 error_message
= _(": invalid membar mask name");
1451 if (*s
== '|' || *s
== '+')
1459 if (! parse_const_expr_arg (&s
, &kmask
))
1461 error_message
= _(": invalid membar mask expression");
1464 if (kmask
< 0 || kmask
> 127)
1466 error_message
= _(": invalid membar mask number");
1471 opcode
|= MEMBAR (kmask
);
1479 /* Parse a prefetch function. */
1482 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1484 error_message
= _(": invalid prefetch function name");
1490 if (! parse_const_expr_arg (&s
, &fcn
))
1492 error_message
= _(": invalid prefetch function expression");
1495 if (fcn
< 0 || fcn
> 31)
1497 error_message
= _(": invalid prefetch function number");
1507 /* Parse a sparc64 privileged register. */
1510 struct priv_reg_entry
*p
= priv_reg_table
;
1511 unsigned int len
= 9999999; /* Init to make gcc happy. */
1514 while (p
->name
[0] > s
[0])
1516 while (p
->name
[0] == s
[0])
1518 len
= strlen (p
->name
);
1519 if (strncmp (p
->name
, s
, len
) == 0)
1523 if (p
->name
[0] != s
[0])
1525 error_message
= _(": unrecognizable privileged register");
1529 opcode
|= (p
->regnum
<< 14);
1531 opcode
|= (p
->regnum
<< 25);
1537 error_message
= _(": unrecognizable privileged register");
1543 /* Parse a v9a ancillary state register. */
1546 struct priv_reg_entry
*p
= v9a_asr_table
;
1547 unsigned int len
= 9999999; /* Init to make gcc happy. */
1550 while (p
->name
[0] > s
[0])
1552 while (p
->name
[0] == s
[0])
1554 len
= strlen (p
->name
);
1555 if (strncmp (p
->name
, s
, len
) == 0)
1559 if (p
->name
[0] != s
[0])
1561 error_message
= _(": unrecognizable v9a ancillary state register");
1564 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1566 error_message
= _(": rd on write only ancillary state register");
1570 opcode
|= (p
->regnum
<< 14);
1572 opcode
|= (p
->regnum
<< 25);
1578 error_message
= _(": unrecognizable v9a ancillary state register");
1584 if (strncmp (s
, "%asr", 4) == 0)
1588 if (isdigit ((unsigned char) *s
))
1592 while (isdigit ((unsigned char) *s
))
1594 num
= num
* 10 + *s
- '0';
1598 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1600 if (num
< 16 || 31 < num
)
1602 error_message
= _(": asr number must be between 16 and 31");
1608 if (num
< 0 || 31 < num
)
1610 error_message
= _(": asr number must be between 0 and 31");
1615 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1620 error_message
= _(": expecting %asrN");
1627 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1631 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1635 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1636 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1637 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1639 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1640 /* These fields are unsigned, but for upward compatibility,
1641 allow negative values as well. */
1645 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1646 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1647 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1649 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1650 /* These fields are unsigned, but for upward compatibility,
1651 allow negative values as well. */
1655 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1660 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1665 if (*s
== 'p' && s
[1] == 'n')
1673 if (*s
== 'p' && s
[1] == 't')
1685 if (strncmp (s
, "%icc", 4) == 0)
1697 if (strncmp (s
, "%xcc", 4) == 0)
1709 if (strncmp (s
, "%fcc0", 5) == 0)
1721 if (strncmp (s
, "%fcc1", 5) == 0)
1733 if (strncmp (s
, "%fcc2", 5) == 0)
1745 if (strncmp (s
, "%fcc3", 5) == 0)
1753 if (strncmp (s
, "%pc", 3) == 0)
1761 if (strncmp (s
, "%tick", 5) == 0)
1768 case '\0': /* End of args. */
1787 case '[': /* These must match exactly. */
1795 case '#': /* Must be at least one digit. */
1796 if (isdigit ((unsigned char) *s
++))
1798 while (isdigit ((unsigned char) *s
))
1806 case 'C': /* Coprocessor state register. */
1807 if (strncmp (s
, "%csr", 4) == 0)
1814 case 'b': /* Next operand is a coprocessor register. */
1817 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1820 if (isdigit ((unsigned char) *s
))
1822 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1836 opcode
|= mask
<< 14;
1844 opcode
|= mask
<< 25;
1850 case 'r': /* next operand must be a register */
1860 case 'f': /* frame pointer */
1868 case 'g': /* global register */
1877 case 'i': /* in register */
1881 mask
= c
- '0' + 24;
1886 case 'l': /* local register */
1890 mask
= (c
- '0' + 16);
1895 case 'o': /* out register */
1899 mask
= (c
- '0' + 8);
1904 case 's': /* stack pointer */
1912 case 'r': /* any register */
1913 if (!isdigit ((unsigned char) (c
= *s
++)))
1928 if (isdigit ((unsigned char) *s
))
1930 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1946 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
1947 && no_undeclared_regs
&& ! globals
[mask
])
1948 as_bad (_("detected global register use not covered by .register pseudo-op"));
1950 /* Got the register, now figure out where
1951 it goes in the opcode. */
1955 opcode
|= mask
<< 14;
1963 opcode
|= mask
<< 25;
1967 opcode
|= (mask
<< 25) | (mask
<< 14);
1971 opcode
|= (mask
<< 25) | (mask
<< 0);
1977 case 'e': /* next operand is a floating point register */
1992 && ((format
= *s
) == 'f')
1993 && isdigit ((unsigned char) *++s
))
1995 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1997 mask
= 10 * mask
+ (*s
- '0');
1998 } /* read the number */
2006 } /* register must be even numbered */
2014 } /* register must be multiple of 4 */
2018 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2019 error_message
= _(": There are only 64 f registers; [0-63]");
2021 error_message
= _(": There are only 32 f registers; [0-31]");
2024 else if (mask
>= 32)
2026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2029 mask
-= 31; /* wrap high bit */
2033 error_message
= _(": There are only 32 f registers; [0-31]");
2041 } /* if not an 'f' register. */
2048 opcode
|= RS1 (mask
);
2054 opcode
|= RS2 (mask
);
2060 opcode
|= RD (mask
);
2069 if (strncmp (s
, "%fsr", 4) == 0)
2076 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2077 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2080 case 'l': /* 22 bit PC relative immediate */
2081 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2085 case 'L': /* 30 bit immediate */
2086 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2091 case 'n': /* 22 bit immediate */
2092 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2095 case 'i': /* 13 bit immediate */
2096 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2106 char *op_arg
= NULL
;
2108 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2110 /* Check for %hi, etc. */
2113 static const struct ops
{
2114 /* The name as it appears in assembler. */
2116 /* strlen (name), precomputed for speed */
2118 /* The reloc this pseudo-op translates to. */
2120 /* Non-zero if for v9 only. */
2122 /* Non-zero if can be used in pc-relative contexts. */
2123 int pcrel_p
;/*FIXME:wip*/
2125 /* hix/lox must appear before hi/lo so %hix won't be
2126 mistaken for %hi. */
2127 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2128 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2129 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2130 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2131 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2132 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2133 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2134 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2135 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2136 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2137 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2138 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2139 { NULL
, 0, 0, 0, 0 }
2141 const struct ops
*o
;
2143 for (o
= ops
; o
->name
; o
++)
2144 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2146 if (o
->name
== NULL
)
2149 if (s
[o
->len
+ 1] != '(')
2151 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2152 return special_case
;
2156 the_insn
.reloc
= o
->reloc
;
2161 /* Note that if the get_expression() fails, we will still
2162 have created U entries in the symbol table for the
2163 'symbols' in the input string. Try not to create U
2164 symbols for registers, etc. */
2166 /* This stuff checks to see if the expression ends in
2167 +%reg. If it does, it removes the register from
2168 the expression, and re-sets 's' to point to the
2175 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2178 else if (*s1
== ')')
2187 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2188 return special_case
;
2192 (void) get_expression (s
);
2195 if (*s
== ',' || *s
== ']' || !*s
)
2197 if (*s
!= '+' && *s
!= '-')
2199 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2200 return special_case
;
2204 op_exp
= the_insn
.exp
;
2205 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2208 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2211 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
2213 if (s1
[-2] == '%' && s1
[-3] == '+')
2215 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2222 if (op_arg
&& s1
== s
+ 1)
2223 the_insn
.exp
.X_op
= O_absent
;
2225 (void) get_expression (s
);
2237 (void) get_expression (s
);
2245 the_insn
.exp2
= the_insn
.exp
;
2246 the_insn
.exp
= op_exp
;
2247 if (the_insn
.exp2
.X_op
== O_absent
)
2248 the_insn
.exp2
.X_op
= O_illegal
;
2249 else if (the_insn
.exp
.X_op
== O_absent
)
2251 the_insn
.exp
= the_insn
.exp2
;
2252 the_insn
.exp2
.X_op
= O_illegal
;
2254 else if (the_insn
.exp
.X_op
== O_constant
)
2256 valueT val
= the_insn
.exp
.X_add_number
;
2257 switch (the_insn
.reloc
)
2262 case BFD_RELOC_SPARC_HH22
:
2263 val
= BSR (val
, 32);
2266 case BFD_RELOC_SPARC_LM22
:
2267 case BFD_RELOC_HI22
:
2268 val
= (val
>> 10) & 0x3fffff;
2271 case BFD_RELOC_SPARC_HM10
:
2272 val
= BSR (val
, 32);
2275 case BFD_RELOC_LO10
:
2279 case BFD_RELOC_SPARC_H44
:
2284 case BFD_RELOC_SPARC_M44
:
2289 case BFD_RELOC_SPARC_L44
:
2293 case BFD_RELOC_SPARC_HIX22
:
2295 val
= (val
>> 10) & 0x3fffff;
2298 case BFD_RELOC_SPARC_LOX10
:
2299 val
= (val
& 0x3ff) | 0x1c00;
2302 the_insn
.exp
= the_insn
.exp2
;
2303 the_insn
.exp
.X_add_number
+= val
;
2304 the_insn
.exp2
.X_op
= O_illegal
;
2305 the_insn
.reloc
= old_reloc
;
2307 else if (the_insn
.exp2
.X_op
!= O_constant
)
2309 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2310 return special_case
;
2314 if (old_reloc
!= BFD_RELOC_SPARC13
2315 || the_insn
.reloc
!= BFD_RELOC_LO10
2316 || sparc_arch_size
!= 64
2319 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2320 return special_case
;
2322 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2326 /* Check for constants that don't require emitting a reloc. */
2327 if (the_insn
.exp
.X_op
== O_constant
2328 && the_insn
.exp
.X_add_symbol
== 0
2329 && the_insn
.exp
.X_op_symbol
== 0)
2331 /* For pc-relative call instructions, we reject
2332 constants to get better code. */
2334 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2335 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2337 error_message
= _(": PC-relative operand can't be a constant");
2341 /* Constants that won't fit are checked in md_apply_fix3
2342 and bfd_install_relocation.
2343 ??? It would be preferable to install the constants
2344 into the insn here and save having to create a fixS
2345 for each one. There already exists code to handle
2346 all the various cases (e.g. in md_apply_fix3 and
2347 bfd_install_relocation) so duplicating all that code
2348 here isn't right. */
2368 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2370 error_message
= _(": invalid ASI name");
2376 if (! parse_const_expr_arg (&s
, &asi
))
2378 error_message
= _(": invalid ASI expression");
2381 if (asi
< 0 || asi
> 255)
2383 error_message
= _(": invalid ASI number");
2387 opcode
|= ASI (asi
);
2389 } /* Alternate space. */
2392 if (strncmp (s
, "%psr", 4) == 0)
2399 case 'q': /* Floating point queue. */
2400 if (strncmp (s
, "%fq", 3) == 0)
2407 case 'Q': /* Coprocessor queue. */
2408 if (strncmp (s
, "%cq", 3) == 0)
2416 if (strcmp (str
, "set") == 0
2417 || strcmp (str
, "setuw") == 0)
2419 special_case
= SPECIAL_CASE_SET
;
2422 else if (strcmp (str
, "setsw") == 0)
2424 special_case
= SPECIAL_CASE_SETSW
;
2427 else if (strcmp (str
, "setx") == 0)
2429 special_case
= SPECIAL_CASE_SETX
;
2432 else if (strncmp (str
, "fdiv", 4) == 0)
2434 special_case
= SPECIAL_CASE_FDIV
;
2440 if (strncmp (s
, "%asi", 4) != 0)
2446 if (strncmp (s
, "%fprs", 5) != 0)
2452 if (strncmp (s
, "%ccr", 4) != 0)
2458 if (strncmp (s
, "%tbr", 4) != 0)
2464 if (strncmp (s
, "%wim", 4) != 0)
2471 char *push
= input_line_pointer
;
2474 input_line_pointer
= s
;
2476 if (e
.X_op
== O_constant
)
2478 int n
= e
.X_add_number
;
2479 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2480 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2482 opcode
|= e
.X_add_number
<< 5;
2485 as_bad (_("non-immediate OPF operand, ignored"));
2486 s
= input_line_pointer
;
2487 input_line_pointer
= push
;
2492 if (strncmp (s
, "%y", 2) != 0)
2500 /* Parse a sparclet cpreg. */
2502 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2504 error_message
= _(": invalid cpreg name");
2507 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2512 as_fatal (_("failed sanity check."));
2513 } /* switch on arg code. */
2515 /* Break out of for() loop. */
2517 } /* For each arg that we expect. */
2522 /* Args don't match. */
2523 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2524 && (insn
->name
== insn
[1].name
2525 || !strcmp (insn
->name
, insn
[1].name
)))
2533 as_bad (_("Illegal operands%s"), error_message
);
2534 return special_case
;
2539 /* We have a match. Now see if the architecture is OK. */
2540 int needed_arch_mask
= insn
->architecture
;
2544 needed_arch_mask
&= ~((1 << SPARC_OPCODE_ARCH_V9
)
2545 | (1 << SPARC_OPCODE_ARCH_V9A
));
2546 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2549 if (needed_arch_mask
2550 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2553 /* Can we bump up the architecture? */
2554 else if (needed_arch_mask
2555 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2557 enum sparc_opcode_arch_val needed_architecture
=
2558 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2559 & needed_arch_mask
);
2561 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2563 && needed_architecture
> warn_after_architecture
)
2565 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2566 sparc_opcode_archs
[current_architecture
].name
,
2567 sparc_opcode_archs
[needed_architecture
].name
,
2569 warn_after_architecture
= needed_architecture
;
2571 current_architecture
= needed_architecture
;
2574 /* ??? This seems to be a bit fragile. What if the next entry in
2575 the opcode table is the one we want and it is supported?
2576 It is possible to arrange the table today so that this can't
2577 happen but what about tomorrow? */
2580 int arch
, printed_one_p
= 0;
2582 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2584 /* Create a list of the architectures that support the insn. */
2585 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2587 arch
= sparc_ffs (needed_arch_mask
);
2588 while ((1 << arch
) <= needed_arch_mask
)
2590 if ((1 << arch
) & needed_arch_mask
)
2594 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2601 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2602 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2604 sparc_opcode_archs
[max_architecture
].name
);
2605 return special_case
;
2607 } /* If no match. */
2610 } /* Forever looking for a match. */
2612 the_insn
.opcode
= opcode
;
2613 return special_case
;
2616 /* Parse an argument that can be expressed as a keyword.
2617 (eg: #StoreStore or %ccfr).
2618 The result is a boolean indicating success.
2619 If successful, INPUT_POINTER is updated. */
2622 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2623 int (*lookup_fn
) PARAMS ((const char *));
2624 char **input_pointerP
;
2630 p
= *input_pointerP
;
2631 for (q
= p
+ (*p
== '#' || *p
== '%');
2632 isalnum ((unsigned char) *q
) || *q
== '_';
2637 value
= (*lookup_fn
) (p
);
2642 *input_pointerP
= q
;
2646 /* Parse an argument that is a constant expression.
2647 The result is a boolean indicating success. */
2650 parse_const_expr_arg (input_pointerP
, valueP
)
2651 char **input_pointerP
;
2654 char *save
= input_line_pointer
;
2657 input_line_pointer
= *input_pointerP
;
2658 /* The next expression may be something other than a constant
2659 (say if we're not processing the right variant of the insn).
2660 Don't call expression unless we're sure it will succeed as it will
2661 signal an error (which we want to defer until later). */
2662 /* FIXME: It might be better to define md_operand and have it recognize
2663 things like %asi, etc. but continuing that route through to the end
2664 is a lot of work. */
2665 if (*input_line_pointer
== '%')
2667 input_line_pointer
= save
;
2671 *input_pointerP
= input_line_pointer
;
2672 input_line_pointer
= save
;
2673 if (exp
.X_op
!= O_constant
)
2675 *valueP
= exp
.X_add_number
;
2679 /* Subroutine of sparc_ip to parse an expression. */
2682 get_expression (str
)
2688 save_in
= input_line_pointer
;
2689 input_line_pointer
= str
;
2690 seg
= expression (&the_insn
.exp
);
2691 if (seg
!= absolute_section
2692 && seg
!= text_section
2693 && seg
!= data_section
2694 && seg
!= bss_section
2695 && seg
!= undefined_section
)
2697 the_insn
.error
= _("bad segment");
2698 expr_end
= input_line_pointer
;
2699 input_line_pointer
= save_in
;
2702 expr_end
= input_line_pointer
;
2703 input_line_pointer
= save_in
;
2707 /* Subroutine of md_assemble to output one insn. */
2710 output_insn (insn
, the_insn
)
2711 const struct sparc_opcode
*insn
;
2712 struct sparc_it
*the_insn
;
2714 char *toP
= frag_more (4);
2716 /* Put out the opcode. */
2717 if (INSN_BIG_ENDIAN
)
2718 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2720 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2722 /* Put out the symbol-dependent stuff. */
2723 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2725 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2726 (toP
- frag_now
->fr_literal
), /* Where. */
2731 /* Turn off overflow checking in fixup_segment. We'll do our
2732 own overflow checking in md_apply_fix3. This is necessary because
2733 the insn size is 4 and fixup_segment will signal an overflow for
2734 large 8 byte quantities. */
2735 fixP
->fx_no_overflow
= 1;
2736 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2737 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2741 last_opcode
= the_insn
->opcode
;
2744 /* This is identical to the md_atof in m68k.c. I think this is right,
2747 Turn a string in input_line_pointer into a floating point constant
2748 of type TYPE, and store the appropriate bytes in *LITP. The number
2749 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2750 returned, or NULL on OK. */
2752 /* Equal to MAX_PRECISION in atof-ieee.c. */
2753 #define MAX_LITTLENUMS 6
2756 md_atof (type
, litP
, sizeP
)
2762 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2793 return _("Bad call to MD_ATOF()");
2796 t
= atof_ieee (input_line_pointer
, type
, words
);
2798 input_line_pointer
= t
;
2799 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2801 if (target_big_endian
)
2803 for (i
= 0; i
< prec
; i
++)
2805 md_number_to_chars (litP
, (valueT
) words
[i
],
2806 sizeof (LITTLENUM_TYPE
));
2807 litP
+= sizeof (LITTLENUM_TYPE
);
2812 for (i
= prec
- 1; i
>= 0; i
--)
2814 md_number_to_chars (litP
, (valueT
) words
[i
],
2815 sizeof (LITTLENUM_TYPE
));
2816 litP
+= sizeof (LITTLENUM_TYPE
);
2823 /* Write a value out to the object file, using the appropriate
2827 md_number_to_chars (buf
, val
, n
)
2832 if (target_big_endian
)
2833 number_to_chars_bigendian (buf
, val
, n
);
2834 else if (target_little_endian_data
2835 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2836 /* Output debug words, which are not in allocated sections, as big
2838 number_to_chars_bigendian (buf
, val
, n
);
2839 else if (target_little_endian_data
|| ! target_big_endian
)
2840 number_to_chars_littleendian (buf
, val
, n
);
2843 /* Apply a fixS to the frags, now that we know the value it ought to
2847 md_apply_fix3 (fixP
, value
, segment
)
2852 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2858 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2860 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
2863 /* FIXME: SPARC ELF relocations don't use an addend in the data
2864 field itself. This whole approach should be somehow combined
2865 with the calls to bfd_install_relocation. Also, the value passed
2866 in by fixup_segment includes the value of a defined symbol. We
2867 don't want to include the value of an externally visible symbol. */
2868 if (fixP
->fx_addsy
!= NULL
)
2870 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
2871 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2872 || S_IS_WEAK (fixP
->fx_addsy
)
2873 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2874 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2875 && ((bfd_get_section_flags (stdoutput
,
2876 S_GET_SEGMENT (fixP
->fx_addsy
))
2877 & SEC_LINK_ONCE
) != 0
2878 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2880 sizeof ".gnu.linkonce" - 1) == 0)))
2881 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2882 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2883 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2884 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2889 /* This is a hack. There should be a better way to
2890 handle this. Probably in terms of howto fields, once
2891 we can look at these fixups in terms of howtos. */
2892 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2893 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2896 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2897 generate a reloc, then we just want to let the reloc addend set
2898 the value. We do not want to also stuff the addend into the
2899 object file. Including the addend in the object file works when
2900 doing a static link, because the linker will ignore the object
2901 file contents. However, the dynamic linker does not ignore the
2902 object file contents. */
2903 if (fixP
->fx_addsy
!= NULL
2904 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2907 /* When generating PIC code, we do not want an addend for a reloc
2908 against a local symbol. We adjust fx_addnumber to cancel out the
2909 value already included in val, and to also cancel out the
2910 adjustment which bfd_install_relocation will create. */
2912 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2913 && fixP
->fx_addsy
!= NULL
2914 && ! S_IS_COMMON (fixP
->fx_addsy
)
2915 && symbol_section_p (fixP
->fx_addsy
))
2916 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2918 /* When generating PIC code, we need to fiddle to get
2919 bfd_install_relocation to do the right thing for a PC relative
2920 reloc against a local symbol which we are going to keep. */
2922 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
2923 && fixP
->fx_addsy
!= NULL
2924 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2925 || S_IS_WEAK (fixP
->fx_addsy
))
2926 && S_IS_DEFINED (fixP
->fx_addsy
)
2927 && ! S_IS_COMMON (fixP
->fx_addsy
))
2930 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2934 /* If this is a data relocation, just output VAL. */
2936 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2938 md_number_to_chars (buf
, val
, 2);
2940 else if (fixP
->fx_r_type
== BFD_RELOC_32
2941 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
2943 md_number_to_chars (buf
, val
, 4);
2945 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2947 md_number_to_chars (buf
, val
, 8);
2949 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2950 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2957 /* It's a relocation against an instruction. */
2959 if (INSN_BIG_ENDIAN
)
2960 insn
= bfd_getb32 ((unsigned char *) buf
);
2962 insn
= bfd_getl32 ((unsigned char *) buf
);
2964 switch (fixP
->fx_r_type
)
2966 case BFD_RELOC_32_PCREL_S2
:
2968 /* FIXME: This increment-by-one deserves a comment of why it's
2970 if (! sparc_pic_code
2971 || fixP
->fx_addsy
== NULL
2972 || symbol_section_p (fixP
->fx_addsy
))
2975 insn
|= val
& 0x3fffffff;
2977 /* See if we have a delay slot. */
2978 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
2982 #define XCC (2 << 20)
2983 #define COND(x) (((x)&0xf)<<25)
2984 #define CONDA COND(0x8)
2985 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
2986 #define INSN_BA (F2(0,2) | CONDA)
2987 #define INSN_OR F3(2, 0x2, 0)
2988 #define INSN_NOP F2(0,4)
2992 /* If the instruction is a call with either:
2994 arithmetic instruction with rd == %o7
2995 where rs1 != %o7 and rs2 if it is register != %o7
2996 then we can optimize if the call destination is near
2997 by changing the call into a branch always. */
2998 if (INSN_BIG_ENDIAN
)
2999 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3001 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3002 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3004 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3005 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3006 || ((delay
& RD (~0)) != RD (O7
))))
3008 if ((delay
& RS1 (~0)) == RS1 (O7
)
3009 || ((delay
& F3I (~0)) == 0
3010 && (delay
& RS2 (~0)) == RS2 (O7
)))
3012 /* Ensure the branch will fit into simm22. */
3013 if ((val
& 0x3fe00000)
3014 && (val
& 0x3fe00000) != 0x3fe00000)
3016 /* Check if the arch is v9 and branch will fit
3018 if (((val
& 0x3c0000) == 0
3019 || (val
& 0x3c0000) == 0x3c0000)
3020 && (sparc_arch_size
== 64
3021 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3023 insn
= INSN_BPA
| (val
& 0x7ffff);
3026 insn
= INSN_BA
| (val
& 0x3fffff);
3027 if (fixP
->fx_where
>= 4
3028 && ((delay
& (0xffffffff ^ RS1 (~0)))
3029 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3034 if (INSN_BIG_ENDIAN
)
3035 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3037 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3038 if ((setter
& (0xffffffff ^ RD (~0)))
3039 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3046 If call foo was replaced with ba, replace
3047 or %rN, %g0, %o7 with nop. */
3048 reg
= (delay
& RS1 (~0)) >> 14;
3049 if (reg
!= ((setter
& RD (~0)) >> 25)
3050 || reg
== G0
|| reg
== O7
)
3053 if (INSN_BIG_ENDIAN
)
3054 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3056 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3061 case BFD_RELOC_SPARC_11
:
3062 if (! in_signed_range (val
, 0x7ff))
3063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3064 _("relocation overflow"));
3065 insn
|= val
& 0x7ff;
3068 case BFD_RELOC_SPARC_10
:
3069 if (! in_signed_range (val
, 0x3ff))
3070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3071 _("relocation overflow"));
3072 insn
|= val
& 0x3ff;
3075 case BFD_RELOC_SPARC_7
:
3076 if (! in_bitfield_range (val
, 0x7f))
3077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3078 _("relocation overflow"));
3082 case BFD_RELOC_SPARC_6
:
3083 if (! in_bitfield_range (val
, 0x3f))
3084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3085 _("relocation overflow"));
3089 case BFD_RELOC_SPARC_5
:
3090 if (! in_bitfield_range (val
, 0x1f))
3091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3092 _("relocation overflow"));
3096 case BFD_RELOC_SPARC_WDISP16
:
3097 /* FIXME: simplify. */
3098 if (((val
> 0) && (val
& ~0x3fffc))
3099 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
3100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3101 _("relocation overflow"));
3102 /* FIXME: The +1 deserves a comment. */
3103 val
= (val
>> 2) + 1;
3104 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3107 case BFD_RELOC_SPARC_WDISP19
:
3108 /* FIXME: simplify. */
3109 if (((val
> 0) && (val
& ~0x1ffffc))
3110 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
3111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3112 _("relocation overflow"));
3113 /* FIXME: The +1 deserves a comment. */
3114 val
= (val
>> 2) + 1;
3115 insn
|= val
& 0x7ffff;
3118 case BFD_RELOC_SPARC_HH22
:
3119 val
= BSR (val
, 32);
3122 case BFD_RELOC_SPARC_LM22
:
3123 case BFD_RELOC_HI22
:
3124 if (!fixP
->fx_addsy
)
3126 insn
|= (val
>> 10) & 0x3fffff;
3130 /* FIXME: Need comment explaining why we do this. */
3135 case BFD_RELOC_SPARC22
:
3136 if (val
& ~0x003fffff)
3137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3138 _("relocation overflow"));
3139 insn
|= (val
& 0x3fffff);
3142 case BFD_RELOC_SPARC_HM10
:
3143 val
= BSR (val
, 32);
3146 case BFD_RELOC_LO10
:
3147 if (!fixP
->fx_addsy
)
3149 insn
|= val
& 0x3ff;
3153 /* FIXME: Need comment explaining why we do this. */
3158 case BFD_RELOC_SPARC_OLO10
:
3160 val
+= fixP
->tc_fix_data
;
3163 case BFD_RELOC_SPARC13
:
3164 if (! in_signed_range (val
, 0x1fff))
3165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3166 _("relocation overflow"));
3167 insn
|= val
& 0x1fff;
3170 case BFD_RELOC_SPARC_WDISP22
:
3171 val
= (val
>> 2) + 1;
3173 case BFD_RELOC_SPARC_BASE22
:
3174 insn
|= val
& 0x3fffff;
3177 case BFD_RELOC_SPARC_H44
:
3178 if (!fixP
->fx_addsy
)
3182 insn
|= tval
& 0x3fffff;
3186 case BFD_RELOC_SPARC_M44
:
3187 if (!fixP
->fx_addsy
)
3188 insn
|= (val
>> 12) & 0x3ff;
3191 case BFD_RELOC_SPARC_L44
:
3192 if (!fixP
->fx_addsy
)
3193 insn
|= val
& 0xfff;
3196 case BFD_RELOC_SPARC_HIX22
:
3197 if (!fixP
->fx_addsy
)
3199 val
^= ~(offsetT
) 0;
3200 insn
|= (val
>> 10) & 0x3fffff;
3204 case BFD_RELOC_SPARC_LOX10
:
3205 if (!fixP
->fx_addsy
)
3206 insn
|= 0x1c00 | (val
& 0x3ff);
3209 case BFD_RELOC_NONE
:
3211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3212 _("bad or unhandled relocation type: 0x%02x"),
3217 if (INSN_BIG_ENDIAN
)
3218 bfd_putb32 (insn
, (unsigned char *) buf
);
3220 bfd_putl32 (insn
, (unsigned char *) buf
);
3223 /* Are we finished with this relocation now? */
3224 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3230 /* Translate internal representation of relocation info to BFD target
3234 tc_gen_reloc (section
, fixp
)
3238 static arelent
*relocs
[3];
3240 bfd_reloc_code_real_type code
;
3242 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3245 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3246 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3247 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3249 switch (fixp
->fx_r_type
)
3253 case BFD_RELOC_HI22
:
3254 case BFD_RELOC_LO10
:
3255 case BFD_RELOC_32_PCREL_S2
:
3256 case BFD_RELOC_SPARC13
:
3257 case BFD_RELOC_SPARC22
:
3258 case BFD_RELOC_SPARC_BASE13
:
3259 case BFD_RELOC_SPARC_WDISP16
:
3260 case BFD_RELOC_SPARC_WDISP19
:
3261 case BFD_RELOC_SPARC_WDISP22
:
3263 case BFD_RELOC_SPARC_5
:
3264 case BFD_RELOC_SPARC_6
:
3265 case BFD_RELOC_SPARC_7
:
3266 case BFD_RELOC_SPARC_10
:
3267 case BFD_RELOC_SPARC_11
:
3268 case BFD_RELOC_SPARC_HH22
:
3269 case BFD_RELOC_SPARC_HM10
:
3270 case BFD_RELOC_SPARC_LM22
:
3271 case BFD_RELOC_SPARC_PC_HH22
:
3272 case BFD_RELOC_SPARC_PC_HM10
:
3273 case BFD_RELOC_SPARC_PC_LM22
:
3274 case BFD_RELOC_SPARC_H44
:
3275 case BFD_RELOC_SPARC_M44
:
3276 case BFD_RELOC_SPARC_L44
:
3277 case BFD_RELOC_SPARC_HIX22
:
3278 case BFD_RELOC_SPARC_LOX10
:
3279 case BFD_RELOC_SPARC_REV32
:
3280 case BFD_RELOC_SPARC_OLO10
:
3281 case BFD_RELOC_VTABLE_ENTRY
:
3282 case BFD_RELOC_VTABLE_INHERIT
:
3283 code
= fixp
->fx_r_type
;
3290 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3291 /* If we are generating PIC code, we need to generate a different
3295 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3297 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3300 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3306 case BFD_RELOC_32_PCREL_S2
:
3307 if (! S_IS_DEFINED (fixp
->fx_addsy
)
3308 || S_IS_COMMON (fixp
->fx_addsy
)
3309 || S_IS_EXTERNAL (fixp
->fx_addsy
)
3310 || S_IS_WEAK (fixp
->fx_addsy
))
3311 code
= BFD_RELOC_SPARC_WPLT30
;
3313 case BFD_RELOC_HI22
:
3314 if (fixp
->fx_addsy
!= NULL
3315 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3316 code
= BFD_RELOC_SPARC_PC22
;
3318 code
= BFD_RELOC_SPARC_GOT22
;
3320 case BFD_RELOC_LO10
:
3321 if (fixp
->fx_addsy
!= NULL
3322 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3323 code
= BFD_RELOC_SPARC_PC10
;
3325 code
= BFD_RELOC_SPARC_GOT10
;
3327 case BFD_RELOC_SPARC13
:
3328 code
= BFD_RELOC_SPARC_GOT13
;
3334 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3336 if (code
== BFD_RELOC_SPARC_OLO10
)
3337 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3339 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3340 if (reloc
->howto
== 0)
3342 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3343 _("internal error: can't export reloc type %d (`%s')"),
3344 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3350 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3353 if (reloc
->howto
->pc_relative
== 0
3354 || code
== BFD_RELOC_SPARC_PC10
3355 || code
== BFD_RELOC_SPARC_PC22
)
3356 reloc
->addend
= fixp
->fx_addnumber
;
3357 else if (sparc_pic_code
3358 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3359 && fixp
->fx_addsy
!= NULL
3360 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3361 || S_IS_WEAK (fixp
->fx_addsy
))
3362 && S_IS_DEFINED (fixp
->fx_addsy
)
3363 && ! S_IS_COMMON (fixp
->fx_addsy
))
3364 reloc
->addend
= fixp
->fx_addnumber
;
3366 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3368 #else /* elf or coff */
3370 if (reloc
->howto
->pc_relative
== 0
3371 || code
== BFD_RELOC_SPARC_PC10
3372 || code
== BFD_RELOC_SPARC_PC22
)
3373 reloc
->addend
= fixp
->fx_addnumber
;
3374 else if (symbol_section_p (fixp
->fx_addsy
))
3375 reloc
->addend
= (section
->vma
3376 + fixp
->fx_addnumber
3377 + md_pcrel_from (fixp
));
3379 reloc
->addend
= fixp
->fx_offset
;
3382 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3383 on the same location. */
3384 if (code
== BFD_RELOC_SPARC_OLO10
)
3386 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3389 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3391 = symbol_get_bfdsym (section_symbol (absolute_section
));
3392 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3393 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3394 reloc
->addend
= fixp
->tc_fix_data
;
3400 /* We have no need to default values of symbols. */
3403 md_undefined_symbol (name
)
3404 char *name ATTRIBUTE_UNUSED
;
3409 /* Round up a section size to the appropriate boundary. */
3412 md_section_align (segment
, size
)
3413 segT segment ATTRIBUTE_UNUSED
;
3417 /* This is not right for ELF; a.out wants it, and COFF will force
3418 the alignment anyways. */
3419 valueT align
= ((valueT
) 1
3420 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3423 /* Turn alignment value into a mask. */
3425 newsize
= (size
+ align
) & ~align
;
3432 /* Exactly what point is a PC-relative offset relative TO?
3433 On the sparc, they're relative to the address of the offset, plus
3434 its size. This gets us to the following instruction.
3435 (??? Is this right? FIXME-SOON) */
3437 md_pcrel_from (fixP
)
3442 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3443 if (! sparc_pic_code
3444 || fixP
->fx_addsy
== NULL
3445 || symbol_section_p (fixP
->fx_addsy
))
3446 ret
+= fixP
->fx_size
;
3450 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3462 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3465 return (value
== 1) ? shift
: -1;
3468 /* Sort of like s_lcomm. */
3471 static int max_alignment
= 15;
3476 int ignore ATTRIBUTE_UNUSED
;
3486 name
= input_line_pointer
;
3487 c
= get_symbol_end ();
3488 p
= input_line_pointer
;
3492 if (*input_line_pointer
!= ',')
3494 as_bad (_("Expected comma after name"));
3495 ignore_rest_of_line ();
3499 ++input_line_pointer
;
3501 if ((size
= get_absolute_expression ()) < 0)
3503 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3504 ignore_rest_of_line ();
3509 symbolP
= symbol_find_or_make (name
);
3512 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3513 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3515 as_bad (_("bad .reserve segment -- expected BSS segment"));
3519 if (input_line_pointer
[2] == '.')
3520 input_line_pointer
+= 7;
3522 input_line_pointer
+= 6;
3525 if (*input_line_pointer
== ',')
3527 ++input_line_pointer
;
3530 if (*input_line_pointer
== '\n')
3532 as_bad (_("missing alignment"));
3533 ignore_rest_of_line ();
3537 align
= (int) get_absolute_expression ();
3540 if (align
> max_alignment
)
3542 align
= max_alignment
;
3543 as_warn (_("alignment too large; assuming %d"), align
);
3549 as_bad (_("negative alignment"));
3550 ignore_rest_of_line ();
3556 temp
= log2 (align
);
3559 as_bad (_("alignment not a power of 2"));
3560 ignore_rest_of_line ();
3567 record_alignment (bss_section
, align
);
3572 if (!S_IS_DEFINED (symbolP
)
3574 && S_GET_OTHER (symbolP
) == 0
3575 && S_GET_DESC (symbolP
) == 0
3582 segT current_seg
= now_seg
;
3583 subsegT current_subseg
= now_subseg
;
3585 /* Switch to bss. */
3586 subseg_set (bss_section
, 1);
3590 frag_align (align
, 0, 0);
3592 /* Detach from old frag. */
3593 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3594 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3596 symbol_set_frag (symbolP
, frag_now
);
3597 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3598 (offsetT
) size
, (char *) 0);
3601 S_SET_SEGMENT (symbolP
, bss_section
);
3603 subseg_set (current_seg
, current_subseg
);
3606 S_SET_SIZE (symbolP
, size
);
3612 as_warn ("Ignoring attempt to re-define symbol %s",
3613 S_GET_NAME (symbolP
));
3614 } /* if not redefining. */
3616 demand_empty_rest_of_line ();
3621 int ignore ATTRIBUTE_UNUSED
;
3629 name
= input_line_pointer
;
3630 c
= get_symbol_end ();
3631 /* Just after name is now '\0'. */
3632 p
= input_line_pointer
;
3635 if (*input_line_pointer
!= ',')
3637 as_bad (_("Expected comma after symbol-name"));
3638 ignore_rest_of_line ();
3643 input_line_pointer
++;
3645 if ((temp
= get_absolute_expression ()) < 0)
3647 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3648 ignore_rest_of_line ();
3653 symbolP
= symbol_find_or_make (name
);
3655 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3657 as_bad (_("Ignoring attempt to re-define symbol"));
3658 ignore_rest_of_line ();
3661 if (S_GET_VALUE (symbolP
) != 0)
3663 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3665 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3666 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3672 S_SET_VALUE (symbolP
, (valueT
) size
);
3673 S_SET_EXTERNAL (symbolP
);
3676 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3677 if (*input_line_pointer
!= ',')
3679 as_bad (_("Expected comma after common length"));
3680 ignore_rest_of_line ();
3683 input_line_pointer
++;
3685 if (*input_line_pointer
!= '"')
3687 temp
= get_absolute_expression ();
3690 if (temp
> max_alignment
)
3692 temp
= max_alignment
;
3693 as_warn (_("alignment too large; assuming %d"), temp
);
3699 as_bad (_("negative alignment"));
3700 ignore_rest_of_line ();
3705 if (symbol_get_obj (symbolP
)->local
)
3713 old_subsec
= now_subseg
;
3718 align
= log2 (temp
);
3722 as_bad (_("alignment not a power of 2"));
3723 ignore_rest_of_line ();
3727 record_alignment (bss_section
, align
);
3728 subseg_set (bss_section
, 0);
3730 frag_align (align
, 0, 0);
3731 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3732 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3733 symbol_set_frag (symbolP
, frag_now
);
3734 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3735 (offsetT
) size
, (char *) 0);
3737 S_SET_SEGMENT (symbolP
, bss_section
);
3738 S_CLEAR_EXTERNAL (symbolP
);
3739 S_SET_SIZE (symbolP
, size
);
3740 subseg_set (old_sec
, old_subsec
);
3743 #endif /* OBJ_ELF */
3746 S_SET_VALUE (symbolP
, (valueT
) size
);
3748 S_SET_ALIGN (symbolP
, temp
);
3749 S_SET_SIZE (symbolP
, size
);
3751 S_SET_EXTERNAL (symbolP
);
3752 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3757 input_line_pointer
++;
3758 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3759 if (*input_line_pointer
== '.')
3760 input_line_pointer
++;
3761 /* @@ Some say data, some say bss. */
3762 if (strncmp (input_line_pointer
, "bss\"", 4)
3763 && strncmp (input_line_pointer
, "data\"", 5))
3765 while (*--input_line_pointer
!= '"')
3767 input_line_pointer
--;
3768 goto bad_common_segment
;
3770 while (*input_line_pointer
++ != '"')
3772 goto allocate_common
;
3775 #ifdef BFD_ASSEMBLER
3776 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3779 demand_empty_rest_of_line ();
3784 p
= input_line_pointer
;
3785 while (*p
&& *p
!= '\n')
3789 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3791 input_line_pointer
= p
;
3792 ignore_rest_of_line ();
3797 /* Handle the .empty pseudo-op. This supresses the warnings about
3798 invalid delay slot usage. */
3802 int ignore ATTRIBUTE_UNUSED
;
3804 /* The easy way to implement is to just forget about the last
3811 int ignore ATTRIBUTE_UNUSED
;
3814 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3816 input_line_pointer
+= 6;
3820 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3822 input_line_pointer
+= 6;
3826 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3828 input_line_pointer
+= 7;
3832 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3834 input_line_pointer
+= 5;
3835 /* We only support 2 segments -- text and data -- for now, so
3836 things in the "bss segment" will have to go into data for now.
3837 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3838 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
3841 as_bad (_("Unknown segment type"));
3842 demand_empty_rest_of_line ();
3848 subseg_set (data_section
, 1);
3849 demand_empty_rest_of_line ();
3854 int ignore ATTRIBUTE_UNUSED
;
3856 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3858 ++input_line_pointer
;
3860 ++input_line_pointer
;
3863 /* This static variable is set by s_uacons to tell sparc_cons_align
3864 that the expession does not need to be aligned. */
3866 static int sparc_no_align_cons
= 0;
3868 /* This handles the unaligned space allocation pseudo-ops, such as
3869 .uaword. .uaword is just like .word, but the value does not need
3876 /* Tell sparc_cons_align not to align this value. */
3877 sparc_no_align_cons
= 1;
3881 /* This handles the native word allocation pseudo-op .nword.
3882 For sparc_arch_size 32 it is equivalent to .word, for
3883 sparc_arch_size 64 it is equivalent to .xword. */
3887 int bytes ATTRIBUTE_UNUSED
;
3889 cons (sparc_arch_size
== 32 ? 4 : 8);
3893 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3897 .register %g[2367],{#scratch|symbolname|#ignore}
3902 int ignore ATTRIBUTE_UNUSED
;
3907 const char *regname
;
3909 if (input_line_pointer
[0] != '%'
3910 || input_line_pointer
[1] != 'g'
3911 || ((input_line_pointer
[2] & ~1) != '2'
3912 && (input_line_pointer
[2] & ~1) != '6')
3913 || input_line_pointer
[3] != ',')
3914 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3915 reg
= input_line_pointer
[2] - '0';
3916 input_line_pointer
+= 4;
3918 if (*input_line_pointer
== '#')
3920 ++input_line_pointer
;
3921 regname
= input_line_pointer
;
3922 c
= get_symbol_end ();
3923 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
3924 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3925 if (regname
[0] == 'i')
3932 regname
= input_line_pointer
;
3933 c
= get_symbol_end ();
3935 if (sparc_arch_size
== 64)
3939 if ((regname
&& globals
[reg
] != (symbolS
*) 1
3940 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
3941 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
3942 as_bad (_("redefinition of global register"));
3946 if (regname
== NULL
)
3947 globals
[reg
] = (symbolS
*) 1;
3952 if (symbol_find (regname
))
3953 as_bad (_("Register symbol %s already defined."),
3956 globals
[reg
] = symbol_make (regname
);
3957 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
3959 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
3960 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
3961 flags
|= BSF_GLOBAL
;
3962 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
3963 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
3964 S_SET_ALIGN (globals
[reg
], reg
);
3965 S_SET_SIZE (globals
[reg
], 0);
3966 /* Although we actually want undefined_section here,
3967 we have to use absolute_section, because otherwise
3968 generic as code will make it a COM section.
3969 We fix this up in sparc_adjust_symtab. */
3970 S_SET_SEGMENT (globals
[reg
], absolute_section
);
3971 S_SET_OTHER (globals
[reg
], 0);
3972 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3973 ->internal_elf_sym
.st_info
=
3974 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
3975 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3976 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
3981 *input_line_pointer
= c
;
3983 demand_empty_rest_of_line ();
3986 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
3987 symbols which need it. */
3990 sparc_adjust_symtab ()
3994 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3996 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
3997 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4000 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4001 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4004 S_SET_SEGMENT (sym
, undefined_section
);
4009 /* If the --enforce-aligned-data option is used, we require .word,
4010 et. al., to be aligned correctly. We do it by setting up an
4011 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4012 no unexpected alignment was introduced.
4014 The SunOS and Solaris native assemblers enforce aligned data by
4015 default. We don't want to do that, because gcc can deliberately
4016 generate misaligned data if the packed attribute is used. Instead,
4017 we permit misaligned data by default, and permit the user to set an
4018 option to check for it. */
4021 sparc_cons_align (nbytes
)
4027 /* Only do this if we are enforcing aligned data. */
4028 if (! enforce_aligned_data
)
4031 if (sparc_no_align_cons
)
4033 /* This is an unaligned pseudo-op. */
4034 sparc_no_align_cons
= 0;
4038 nalign
= log2 (nbytes
);
4042 assert (nalign
> 0);
4044 if (now_seg
== absolute_section
)
4046 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4047 as_bad (_("misaligned data"));
4051 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
4052 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4054 record_alignment (now_seg
, nalign
);
4057 /* This is where we do the unexpected alignment check.
4058 This is called from HANDLE_ALIGN in tc-sparc.h. */
4061 sparc_handle_align (fragp
)
4064 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
4065 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
4066 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4067 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
4070 fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4075 && !((long) (fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
4077 unsigned *p
= (unsigned *) (fragp
->fr_literal
+ fragp
->fr_fix
);
4080 for (i
= 0; i
< count
; i
+= 4, p
++)
4081 if (INSN_BIG_ENDIAN
)
4083 number_to_chars_bigendian ((char *) p
, 0x01000000, 4);
4085 number_to_chars_littleendian ((char *) p
, 0x10000000, 4);
4087 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4089 char *waddr
= &fragp
->fr_literal
[fragp
->fr_fix
];
4090 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4091 if (INSN_BIG_ENDIAN
)
4092 number_to_chars_bigendian (waddr
, wval
, 4);
4094 number_to_chars_littleendian (waddr
, wval
, 4);
4096 fragp
->fr_var
= count
;
4102 /* Some special processing for a Sparc ELF file. */
4105 sparc_elf_final_processing ()
4107 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4108 sort of BFD interface for this. */
4109 if (sparc_arch_size
== 64)
4111 switch (sparc_memory_model
)
4114 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4117 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4123 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4124 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4125 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4126 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4130 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4131 reloc for a cons. We could use the definition there, except that
4132 we want to handle little endian relocs specially. */
4135 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4138 unsigned int nbytes
;
4141 bfd_reloc_code_real_type r
;
4143 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4144 (nbytes
== 2 ? BFD_RELOC_16
:
4145 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4147 if (target_little_endian_data
&& nbytes
== 4
4148 && now_seg
->flags
& SEC_ALLOC
)
4149 r
= BFD_RELOC_SPARC_REV32
;
4150 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4155 elf32_sparc_force_relocation (fixp
)
4158 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4159 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)