1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "xtensa-config.h"
31 #include "elf/xtensa.h"
33 /* Provide default values for new configuration settings. */
38 #ifndef XTENSA_MARCH_EARLIEST
39 #define XTENSA_MARCH_EARLIEST 0
43 #define uint32 unsigned int
46 #define int32 signed int
51 Naming conventions (used somewhat inconsistently):
52 The xtensa_ functions are exported
53 The xg_ functions are internal
55 We also have a couple of different extensibility mechanisms.
56 1) The idiom replacement:
57 This is used when a line is first parsed to
58 replace an instruction pattern with another instruction
59 It is currently limited to replacements of instructions
60 with constant operands.
61 2) The xtensa-relax.c mechanism that has stronger instruction
62 replacement patterns. When an instruction's immediate field
63 does not fit the next instruction sequence is attempted.
64 In addition, "narrow" opcodes are supported this way. */
67 /* Define characters with special meanings to GAS. */
68 const char comment_chars
[] = "#";
69 const char line_comment_chars
[] = "#";
70 const char line_separator_chars
[] = ";";
71 const char EXP_CHARS
[] = "eE";
72 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
75 /* Flags to indicate whether the hardware supports the density and
76 absolute literals options. */
78 bfd_boolean density_supported
;
79 bfd_boolean absolute_literals_supported
;
81 static unsigned microarch_earliest
;
83 static vliw_insn cur_vinsn
;
85 unsigned xtensa_num_pipe_stages
;
86 unsigned xtensa_fetch_width
;
88 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
90 /* Some functions are only valid in the front end. This variable
91 allows us to assert that we haven't crossed over into the
93 static bfd_boolean past_xtensa_end
= FALSE
;
95 /* Flags for properties of the last instruction in a segment. */
96 #define FLAG_IS_A0_WRITER 0x1
97 #define FLAG_IS_BAD_LOOPEND 0x2
100 /* We define a special segment names ".literal" to place literals
101 into. The .fini and .init sections are special because they
102 contain code that is moved together by the linker. We give them
103 their own special .fini.literal and .init.literal sections. */
105 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
106 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
107 #define INIT_SECTION_NAME xtensa_section_rename (".init")
108 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
111 /* This type is used for the directive_stack to keep track of the
112 state of the literal collection pools. If lit_prefix is set, it is
113 used to determine the literal section names; otherwise, the literal
114 sections are determined based on the current text section. The
115 lit_seg and lit4_seg fields cache these literal sections, with the
116 current_text_seg field used a tag to indicate whether the cached
119 typedef struct lit_state_struct
122 segT current_text_seg
;
127 static lit_state default_lit_sections
;
130 /* We keep a list of literal segments. The seg_list type is the node
131 for this list. The literal_head pointer is the head of the list,
132 with the literal_head_h dummy node at the start. */
134 typedef struct seg_list_struct
136 struct seg_list_struct
*next
;
140 static seg_list literal_head_h
;
141 static seg_list
*literal_head
= &literal_head_h
;
144 /* Lists of symbols. We keep a list of symbols that label the current
145 instruction, so that we can adjust the symbols when inserting alignment
146 for various instructions. We also keep a list of all the symbols on
147 literals, so that we can fix up those symbols when the literals are
148 later moved into the text sections. */
150 typedef struct sym_list_struct
152 struct sym_list_struct
*next
;
156 static sym_list
*insn_labels
= NULL
;
157 static sym_list
*free_insn_labels
= NULL
;
158 static sym_list
*saved_insn_labels
= NULL
;
160 static sym_list
*literal_syms
;
163 /* Flags to determine whether to prefer const16 or l32r
164 if both options are available. */
165 int prefer_const16
= 0;
168 /* Global flag to indicate when we are emitting literals. */
169 int generating_literals
= 0;
171 /* The following PROPERTY table definitions are copied from
172 <elf/xtensa.h> and must be kept in sync with the code there. */
174 /* Flags in the property tables to specify whether blocks of memory
175 are literals, instructions, data, or unreachable. For
176 instructions, blocks that begin loop targets and branch targets are
177 designated. Blocks that do not allow density, instruction
178 reordering or transformation are also specified. Finally, for
179 branch targets, branch target alignment priority is included.
180 Alignment of the next block is specified in the current block
181 and the size of the current block does not include any fill required
182 to align to the next block. */
184 #define XTENSA_PROP_LITERAL 0x00000001
185 #define XTENSA_PROP_INSN 0x00000002
186 #define XTENSA_PROP_DATA 0x00000004
187 #define XTENSA_PROP_UNREACHABLE 0x00000008
188 /* Instruction only properties at beginning of code. */
189 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
190 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
191 /* Instruction only properties about code. */
192 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
193 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
194 /* Historically, NO_TRANSFORM was a property of instructions,
195 but it should apply to literals under certain circumstances. */
196 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
198 /* Branch target alignment information. This transmits information
199 to the linker optimization about the priority of aligning a
200 particular block for branch target alignment: None, low priority,
201 high priority, or required. These only need to be checked in
202 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
205 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
206 case XTENSA_PROP_BT_ALIGN_NONE:
207 case XTENSA_PROP_BT_ALIGN_LOW:
208 case XTENSA_PROP_BT_ALIGN_HIGH:
209 case XTENSA_PROP_BT_ALIGN_REQUIRE:
211 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
213 /* No branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
215 /* Low priority branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
217 /* High priority branch target alignment. */
218 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
219 /* Required branch target alignment. */
220 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
222 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
223 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
224 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
227 /* Alignment is specified in the block BEFORE the one that needs
228 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
229 get the required alignment specified as a power of 2. Use
230 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
231 alignment. Be careful of side effects since the SET will evaluate
232 flags twice. Also, note that the SIZE of a block in the property
233 table does not include the alignment size, so the alignment fill
234 must be calculated to determine if two blocks are contiguous.
235 TEXT_ALIGN is not currently implemented but is a placeholder for a
236 possible future implementation. */
238 #define XTENSA_PROP_ALIGN 0x00000800
240 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357 #define O_pcrel O_md4 /* value is a PC-relative offset */
358 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
359 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
360 #define O_tlscall O_md7 /* TLS_CALL relocation */
361 #define O_tpoff O_md8 /* TPOFF relocation */
362 #define O_dtpoff O_md9 /* DTPOFF relocation */
364 struct suffix_reloc_map
368 bfd_reloc_code_real_type reloc
;
372 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
374 static struct suffix_reloc_map suffix_relocs
[] =
376 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
377 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
378 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
379 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
380 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
381 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
382 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
383 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
384 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
398 directive_literal_prefix
,
400 directive_absolute_literals
,
401 directive_last_directive
407 bfd_boolean can_be_negated
;
410 const directive_infoS directive_info
[] =
413 { "literal", FALSE
},
415 { "transform", TRUE
},
416 { "freeregs", FALSE
},
417 { "longcalls", TRUE
},
418 { "literal_prefix", FALSE
},
419 { "schedule", TRUE
},
420 { "absolute-literals", TRUE
}
423 bfd_boolean directive_state
[] =
428 TRUE
, /* transform */
429 FALSE
, /* freeregs */
430 FALSE
, /* longcalls */
431 FALSE
, /* literal_prefix */
432 FALSE
, /* schedule */
433 FALSE
/* absolute_literals */
436 /* A circular list of all potential and actual literal pool locations
440 struct litpool_frag
*next
;
441 struct litpool_frag
*prev
;
444 short priority
; /* 1, 2, or 3 -- 1 is highest */
445 short original_priority
;
449 /* Map a segment to its litpool_frag list. */
452 struct litpool_seg
*next
;
454 struct litpool_frag frag_list
;
455 int frag_count
; /* since last litpool location */
458 static struct litpool_seg litpool_seg_list
;
460 /* Limit maximal size of auto litpool by half of the j range. */
461 #define MAX_AUTO_POOL_LITERALS 16384
463 /* Limit maximal size of explicit literal pool by l32r range. */
464 #define MAX_EXPLICIT_POOL_LITERALS 65536
466 #define MAX_POOL_LITERALS \
467 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
469 /* Directive functions. */
471 static void xtensa_begin_directive (int);
472 static void xtensa_end_directive (int);
473 static void xtensa_literal_prefix (void);
474 static void xtensa_literal_position (int);
475 static void xtensa_literal_pseudo (int);
476 static void xtensa_frequency_pseudo (int);
477 static void xtensa_elf_cons (int);
478 static void xtensa_leb128 (int);
480 /* Parsing and Idiom Translation. */
482 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
484 /* Various Other Internal Functions. */
486 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
487 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
488 static void xtensa_mark_literal_pool_location (void);
489 static addressT
get_expanded_loop_offset (xtensa_opcode
);
490 static fragS
*get_literal_pool_location (segT
);
491 static void set_literal_pool_location (segT
, fragS
*);
492 static void xtensa_set_frag_assembly_state (fragS
*);
493 static void finish_vinsn (vliw_insn
*);
494 static bfd_boolean
emit_single_op (TInsn
*);
495 static int total_frag_text_expansion (fragS
*);
496 static bfd_boolean use_trampolines
= TRUE
;
497 static void xtensa_check_frag_count (void);
498 static void xtensa_create_trampoline_frag (bfd_boolean
);
499 static void xtensa_maybe_create_trampoline_frag (void);
500 struct trampoline_frag
;
501 static int init_trampoline_frag (fragS
*);
502 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
);
503 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
504 static bfd_boolean auto_litpools
= FALSE
;
505 static int auto_litpool_limit
= 0;
506 static bfd_boolean
xtensa_is_init_fini (segT seg
);
508 /* Alignment Functions. */
510 static int get_text_align_power (unsigned);
511 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
512 static int branch_align_power (segT
);
514 /* Helpers for xtensa_relax_frag(). */
516 static long relax_frag_add_nop (fragS
*);
518 /* Accessors for additional per-subsegment information. */
520 static unsigned get_last_insn_flags (segT
, subsegT
);
521 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
522 static float get_subseg_total_freq (segT
, subsegT
);
523 static float get_subseg_target_freq (segT
, subsegT
);
524 static void set_subseg_freq (segT
, subsegT
, float, float);
526 /* Segment list functions. */
528 static void xtensa_move_literals (void);
529 static void xtensa_reorder_segments (void);
530 static void xtensa_switch_to_literal_fragment (emit_state
*);
531 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
532 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
533 static void xtensa_restore_emit_state (emit_state
*);
534 static segT
cache_literal_section (bfd_boolean
);
536 /* op_placement_info functions. */
538 static void init_op_placement_info_table (void);
539 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
540 static int xg_get_single_size (xtensa_opcode
);
541 static xtensa_format
xg_get_single_format (xtensa_opcode
);
542 static int xg_get_single_slot (xtensa_opcode
);
544 /* TInsn and IStack functions. */
546 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
547 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
548 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
549 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
550 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
551 static void tinsn_from_chars (TInsn
*, char *, int);
552 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
553 static int get_num_stack_text_bytes (IStack
*);
554 static int get_num_stack_literal_bytes (IStack
*);
555 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
557 /* vliw_insn functions. */
559 static void xg_init_vinsn (vliw_insn
*);
560 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
561 static void xg_clear_vinsn (vliw_insn
*);
562 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
563 static void xg_free_vinsn (vliw_insn
*);
564 static bfd_boolean vinsn_to_insnbuf
565 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
566 static void vinsn_from_chars (vliw_insn
*, char *);
568 /* Expression Utilities. */
570 bfd_boolean
expr_is_const (const expressionS
*);
571 offsetT
get_expr_const (const expressionS
*);
572 void set_expr_const (expressionS
*, offsetT
);
573 bfd_boolean
expr_is_register (const expressionS
*);
574 offsetT
get_expr_register (const expressionS
*);
575 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
576 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
577 static void copy_expr (expressionS
*, const expressionS
*);
579 /* Section renaming. */
581 static void build_section_rename (const char *);
584 /* ISA imported from bfd. */
585 extern xtensa_isa xtensa_default_isa
;
587 extern int target_big_endian
;
589 static xtensa_opcode xtensa_addi_opcode
;
590 static xtensa_opcode xtensa_addmi_opcode
;
591 static xtensa_opcode xtensa_call0_opcode
;
592 static xtensa_opcode xtensa_call4_opcode
;
593 static xtensa_opcode xtensa_call8_opcode
;
594 static xtensa_opcode xtensa_call12_opcode
;
595 static xtensa_opcode xtensa_callx0_opcode
;
596 static xtensa_opcode xtensa_callx4_opcode
;
597 static xtensa_opcode xtensa_callx8_opcode
;
598 static xtensa_opcode xtensa_callx12_opcode
;
599 static xtensa_opcode xtensa_const16_opcode
;
600 static xtensa_opcode xtensa_entry_opcode
;
601 static xtensa_opcode xtensa_extui_opcode
;
602 static xtensa_opcode xtensa_movi_opcode
;
603 static xtensa_opcode xtensa_movi_n_opcode
;
604 static xtensa_opcode xtensa_isync_opcode
;
605 static xtensa_opcode xtensa_j_opcode
;
606 static xtensa_opcode xtensa_jx_opcode
;
607 static xtensa_opcode xtensa_l32r_opcode
;
608 static xtensa_opcode xtensa_loop_opcode
;
609 static xtensa_opcode xtensa_loopnez_opcode
;
610 static xtensa_opcode xtensa_loopgtz_opcode
;
611 static xtensa_opcode xtensa_nop_opcode
;
612 static xtensa_opcode xtensa_nop_n_opcode
;
613 static xtensa_opcode xtensa_or_opcode
;
614 static xtensa_opcode xtensa_ret_opcode
;
615 static xtensa_opcode xtensa_ret_n_opcode
;
616 static xtensa_opcode xtensa_retw_opcode
;
617 static xtensa_opcode xtensa_retw_n_opcode
;
618 static xtensa_opcode xtensa_rsr_lcount_opcode
;
619 static xtensa_opcode xtensa_waiti_opcode
;
620 static int config_max_slots
= 0;
623 /* Command-line Options. */
625 bfd_boolean use_literal_section
= TRUE
;
626 enum flix_level produce_flix
= FLIX_ALL
;
627 static bfd_boolean align_targets
= TRUE
;
628 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
629 static bfd_boolean has_a0_b_retw
= FALSE
;
630 static bfd_boolean workaround_a0_b_retw
= FALSE
;
631 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
632 static bfd_boolean workaround_short_loop
= FALSE
;
633 static bfd_boolean maybe_has_short_loop
= FALSE
;
634 static bfd_boolean workaround_close_loop_end
= FALSE
;
635 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
636 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
637 static bfd_boolean opt_linkrelax
= TRUE
;
639 /* When workaround_short_loops is TRUE, all loops with early exits must
640 have at least 3 instructions. workaround_all_short_loops is a modifier
641 to the workaround_short_loop flag. In addition to the
642 workaround_short_loop actions, all straightline loopgtz and loopnez
643 must have at least 3 instructions. */
645 static bfd_boolean workaround_all_short_loops
= FALSE
;
647 /* Generate individual property section for every section.
648 This option is defined in BDF library. */
649 extern bfd_boolean elf32xtensa_separate_props
;
652 xtensa_setup_hw_workarounds (int earliest
, int latest
)
654 if (earliest
> latest
)
655 as_fatal (_("illegal range of target hardware versions"));
657 /* Enable all workarounds for pre-T1050.0 hardware. */
658 if (earliest
< 105000 || latest
< 105000)
660 workaround_a0_b_retw
|= TRUE
;
661 workaround_b_j_loop_end
|= TRUE
;
662 workaround_short_loop
|= TRUE
;
663 workaround_close_loop_end
|= TRUE
;
664 workaround_all_short_loops
|= TRUE
;
665 enforce_three_byte_loop_align
= TRUE
;
672 option_density
= OPTION_MD_BASE
,
676 option_no_generate_flix
,
683 option_no_link_relax
,
691 option_text_section_literals
,
692 option_no_text_section_literals
,
694 option_absolute_literals
,
695 option_no_absolute_literals
,
697 option_align_targets
,
698 option_no_align_targets
,
700 option_warn_unaligned_targets
,
705 option_workaround_a0_b_retw
,
706 option_no_workaround_a0_b_retw
,
708 option_workaround_b_j_loop_end
,
709 option_no_workaround_b_j_loop_end
,
711 option_workaround_short_loop
,
712 option_no_workaround_short_loop
,
714 option_workaround_all_short_loops
,
715 option_no_workaround_all_short_loops
,
717 option_workaround_close_loop_end
,
718 option_no_workaround_close_loop_end
,
720 option_no_workarounds
,
722 option_rename_section_name
,
725 option_prefer_const16
,
727 option_target_hardware
,
730 option_no_trampolines
,
732 option_auto_litpools
,
733 option_no_auto_litpools
,
734 option_auto_litpool_limit
,
736 option_separate_props
,
737 option_no_separate_props
,
740 const char *md_shortopts
= "";
742 struct option md_longopts
[] =
744 { "density", no_argument
, NULL
, option_density
},
745 { "no-density", no_argument
, NULL
, option_no_density
},
747 { "flix", no_argument
, NULL
, option_flix
},
748 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
749 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
751 /* Both "relax" and "generics" are deprecated and treated as equivalent
752 to the "transform" option. */
753 { "relax", no_argument
, NULL
, option_relax
},
754 { "no-relax", no_argument
, NULL
, option_no_relax
},
755 { "generics", no_argument
, NULL
, option_generics
},
756 { "no-generics", no_argument
, NULL
, option_no_generics
},
758 { "transform", no_argument
, NULL
, option_transform
},
759 { "no-transform", no_argument
, NULL
, option_no_transform
},
760 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
761 { "no-text-section-literals", no_argument
, NULL
,
762 option_no_text_section_literals
},
763 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
764 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
765 /* This option was changed from -align-target to -target-align
766 because it conflicted with the "-al" option. */
767 { "target-align", no_argument
, NULL
, option_align_targets
},
768 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
769 { "warn-unaligned-targets", no_argument
, NULL
,
770 option_warn_unaligned_targets
},
771 { "longcalls", no_argument
, NULL
, option_longcalls
},
772 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
774 { "no-workaround-a0-b-retw", no_argument
, NULL
,
775 option_no_workaround_a0_b_retw
},
776 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
778 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
779 option_no_workaround_b_j_loop_end
},
780 { "workaround-b-j-loop-end", no_argument
, NULL
,
781 option_workaround_b_j_loop_end
},
783 { "no-workaround-short-loops", no_argument
, NULL
,
784 option_no_workaround_short_loop
},
785 { "workaround-short-loops", no_argument
, NULL
,
786 option_workaround_short_loop
},
788 { "no-workaround-all-short-loops", no_argument
, NULL
,
789 option_no_workaround_all_short_loops
},
790 { "workaround-all-short-loop", no_argument
, NULL
,
791 option_workaround_all_short_loops
},
793 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
794 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
796 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
798 { "no-workaround-close-loop-end", no_argument
, NULL
,
799 option_no_workaround_close_loop_end
},
800 { "workaround-close-loop-end", no_argument
, NULL
,
801 option_workaround_close_loop_end
},
803 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
805 { "link-relax", no_argument
, NULL
, option_link_relax
},
806 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
808 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
810 { "trampolines", no_argument
, NULL
, option_trampolines
},
811 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
813 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
814 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
815 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
817 { "separate-prop-tables", no_argument
, NULL
, option_separate_props
},
819 { NULL
, no_argument
, NULL
, 0 }
822 size_t md_longopts_size
= sizeof md_longopts
;
826 md_parse_option (int c
, const char *arg
)
831 as_warn (_("--density option is ignored"));
833 case option_no_density
:
834 as_warn (_("--no-density option is ignored"));
836 case option_link_relax
:
837 opt_linkrelax
= TRUE
;
839 case option_no_link_relax
:
840 opt_linkrelax
= FALSE
;
843 produce_flix
= FLIX_ALL
;
845 case option_no_generate_flix
:
846 produce_flix
= FLIX_NO_GENERATE
;
849 produce_flix
= FLIX_NONE
;
851 case option_generics
:
852 as_warn (_("--generics is deprecated; use --transform instead"));
853 return md_parse_option (option_transform
, arg
);
854 case option_no_generics
:
855 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
856 return md_parse_option (option_no_transform
, arg
);
858 as_warn (_("--relax is deprecated; use --transform instead"));
859 return md_parse_option (option_transform
, arg
);
860 case option_no_relax
:
861 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
862 return md_parse_option (option_no_transform
, arg
);
863 case option_longcalls
:
864 directive_state
[directive_longcalls
] = TRUE
;
866 case option_no_longcalls
:
867 directive_state
[directive_longcalls
] = FALSE
;
869 case option_text_section_literals
:
870 use_literal_section
= FALSE
;
872 case option_no_text_section_literals
:
873 use_literal_section
= TRUE
;
875 case option_absolute_literals
:
876 if (!absolute_literals_supported
)
878 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
881 directive_state
[directive_absolute_literals
] = TRUE
;
883 case option_no_absolute_literals
:
884 directive_state
[directive_absolute_literals
] = FALSE
;
887 case option_workaround_a0_b_retw
:
888 workaround_a0_b_retw
= TRUE
;
890 case option_no_workaround_a0_b_retw
:
891 workaround_a0_b_retw
= FALSE
;
893 case option_workaround_b_j_loop_end
:
894 workaround_b_j_loop_end
= TRUE
;
896 case option_no_workaround_b_j_loop_end
:
897 workaround_b_j_loop_end
= FALSE
;
900 case option_workaround_short_loop
:
901 workaround_short_loop
= TRUE
;
903 case option_no_workaround_short_loop
:
904 workaround_short_loop
= FALSE
;
907 case option_workaround_all_short_loops
:
908 workaround_all_short_loops
= TRUE
;
910 case option_no_workaround_all_short_loops
:
911 workaround_all_short_loops
= FALSE
;
914 case option_workaround_close_loop_end
:
915 workaround_close_loop_end
= TRUE
;
917 case option_no_workaround_close_loop_end
:
918 workaround_close_loop_end
= FALSE
;
921 case option_no_workarounds
:
922 workaround_a0_b_retw
= FALSE
;
923 workaround_b_j_loop_end
= FALSE
;
924 workaround_short_loop
= FALSE
;
925 workaround_all_short_loops
= FALSE
;
926 workaround_close_loop_end
= FALSE
;
929 case option_align_targets
:
930 align_targets
= TRUE
;
932 case option_no_align_targets
:
933 align_targets
= FALSE
;
936 case option_warn_unaligned_targets
:
937 warn_unaligned_branch_targets
= TRUE
;
940 case option_rename_section_name
:
941 build_section_rename (arg
);
945 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
946 should be emitted or not. FIXME: Not implemented. */
949 case option_prefer_l32r
:
951 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
955 case option_prefer_const16
:
957 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
961 case option_target_hardware
:
963 int earliest
, latest
= 0;
965 if (*arg
== 0 || *arg
== '-')
966 as_fatal (_("invalid target hardware version"));
968 earliest
= strtol (arg
, &end
, 0);
972 else if (*end
== '-')
975 as_fatal (_("invalid target hardware version"));
976 latest
= strtol (end
, &end
, 0);
979 as_fatal (_("invalid target hardware version"));
981 xtensa_setup_hw_workarounds (earliest
, latest
);
985 case option_transform
:
986 /* This option has no affect other than to use the defaults,
987 which are already set. */
990 case option_no_transform
:
991 /* This option turns off all transformations of any kind.
992 However, because we want to preserve the state of other
993 directives, we only change its own field. Thus, before
994 you perform any transformation, always check if transform
995 is available. If you use the functions we provide for this
996 purpose, you will be ok. */
997 directive_state
[directive_transform
] = FALSE
;
1000 case option_trampolines
:
1001 use_trampolines
= TRUE
;
1004 case option_no_trampolines
:
1005 use_trampolines
= FALSE
;
1008 case option_auto_litpools
:
1009 auto_litpools
= TRUE
;
1010 use_literal_section
= FALSE
;
1011 if (auto_litpool_limit
<= 0)
1012 auto_litpool_limit
= MAX_AUTO_POOL_LITERALS
/ 2;
1015 case option_no_auto_litpools
:
1016 auto_litpools
= FALSE
;
1017 auto_litpool_limit
= -1;
1020 case option_auto_litpool_limit
:
1024 if (auto_litpool_limit
< 0)
1025 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1026 if (*arg
== 0 || *arg
== '-')
1027 as_fatal (_("invalid auto-litpool-limit argument"));
1028 value
= strtol (arg
, &end
, 10);
1030 as_fatal (_("invalid auto-litpool-limit argument"));
1031 if (value
< 100 || value
> 10000)
1032 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1033 auto_litpool_limit
= value
;
1034 auto_litpools
= TRUE
;
1035 use_literal_section
= FALSE
;
1039 case option_separate_props
:
1040 elf32xtensa_separate_props
= TRUE
;
1043 case option_no_separate_props
:
1044 elf32xtensa_separate_props
= FALSE
;
1054 md_show_usage (FILE *stream
)
1058 --[no-]text-section-literals\n\
1059 [Do not] put literals in the text section\n\
1060 --[no-]absolute-literals\n\
1061 [Do not] default to use non-PC-relative literals\n\
1062 --[no-]target-align [Do not] try to align branch targets\n\
1063 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1064 --[no-]transform [Do not] transform instructions\n\
1065 --flix both allow hand-written and generate flix bundles\n\
1066 --no-generate-flix allow hand-written but do not generate\n\
1068 --no-allow-flix neither allow hand-written nor generate\n\
1070 --rename-section old=new Rename section 'old' to 'new'\n\
1071 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1072 when jumps do not reach their targets\n\
1073 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1074 --auto-litpool-limit=<value>\n\
1075 (range 100-10000) Maximum number of blocks of\n\
1076 instructions to emit between literal pool\n\
1077 locations; implies --auto-litpools flag\n\
1078 --[no-]separate-prop-tables\n\
1079 [Do not] place Xtensa property records into\n\
1080 individual property sections for each section.\n\
1081 Default is to generate single property section.\n", stream
);
1085 /* Functions related to the list of current label symbols. */
1088 xtensa_add_insn_label (symbolS
*sym
)
1092 if (!free_insn_labels
)
1093 l
= XNEW (sym_list
);
1096 l
= free_insn_labels
;
1097 free_insn_labels
= l
->next
;
1101 l
->next
= insn_labels
;
1107 xtensa_clear_insn_labels (void)
1111 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1119 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1123 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1125 symbolS
*lit_sym
= lit
->sym
;
1126 S_SET_VALUE (lit_sym
, new_offset
);
1127 symbol_set_frag (lit_sym
, new_frag
);
1132 /* Directive data and functions. */
1134 typedef struct state_stackS_struct
1136 directiveE directive
;
1137 bfd_boolean negated
;
1138 bfd_boolean old_state
;
1142 struct state_stackS_struct
*prev
;
1145 state_stackS
*directive_state_stack
;
1147 const pseudo_typeS md_pseudo_table
[] =
1149 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1150 { "literal_position", xtensa_literal_position
, 0 },
1151 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1152 { "long", xtensa_elf_cons
, 4 },
1153 { "word", xtensa_elf_cons
, 4 },
1154 { "4byte", xtensa_elf_cons
, 4 },
1155 { "short", xtensa_elf_cons
, 2 },
1156 { "2byte", xtensa_elf_cons
, 2 },
1157 { "sleb128", xtensa_leb128
, 1},
1158 { "uleb128", xtensa_leb128
, 0},
1159 { "begin", xtensa_begin_directive
, 0 },
1160 { "end", xtensa_end_directive
, 0 },
1161 { "literal", xtensa_literal_pseudo
, 0 },
1162 { "frequency", xtensa_frequency_pseudo
, 0 },
1168 use_transform (void)
1170 /* After md_end, you should be checking frag by frag, rather
1171 than state directives. */
1172 gas_assert (!past_xtensa_end
);
1173 return directive_state
[directive_transform
];
1178 do_align_targets (void)
1180 /* Do not use this function after md_end; just look at align_targets
1181 instead. There is no target-align directive, so alignment is either
1182 enabled for all frags or not done at all. */
1183 gas_assert (!past_xtensa_end
);
1184 return align_targets
&& use_transform ();
1189 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1193 state_stackS
*stack
= XNEW (state_stackS
);
1195 file
= as_where (&line
);
1197 stack
->directive
= directive
;
1198 stack
->negated
= negated
;
1199 stack
->old_state
= directive_state
[directive
];
1202 stack
->datum
= datum
;
1203 stack
->prev
= directive_state_stack
;
1204 directive_state_stack
= stack
;
1206 directive_state
[directive
] = !negated
;
1211 directive_pop (directiveE
*directive
,
1212 bfd_boolean
*negated
,
1217 state_stackS
*top
= directive_state_stack
;
1219 if (!directive_state_stack
)
1221 as_bad (_("unmatched .end directive"));
1222 *directive
= directive_none
;
1226 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1227 *directive
= top
->directive
;
1228 *negated
= top
->negated
;
1231 *datum
= top
->datum
;
1232 directive_state_stack
= top
->prev
;
1238 directive_balance (void)
1240 while (directive_state_stack
)
1242 directiveE directive
;
1243 bfd_boolean negated
;
1248 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1249 as_warn_where ((char *) file
, line
,
1250 _(".begin directive with no matching .end directive"));
1256 inside_directive (directiveE dir
)
1258 state_stackS
*top
= directive_state_stack
;
1260 while (top
&& top
->directive
!= dir
)
1263 return (top
!= NULL
);
1268 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1272 const char *directive_string
;
1274 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1279 input_line_pointer
+= 3;
1282 len
= strspn (input_line_pointer
,
1283 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1285 /* This code is a hack to make .begin [no-][generics|relax] exactly
1286 equivalent to .begin [no-]transform. We should remove it when
1287 we stop accepting those options. */
1289 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1291 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1292 directive_string
= "transform";
1294 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1296 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1297 directive_string
= "transform";
1300 directive_string
= input_line_pointer
;
1302 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1304 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1306 input_line_pointer
+= len
;
1307 *directive
= (directiveE
) i
;
1308 if (*negated
&& !directive_info
[i
].can_be_negated
)
1309 as_bad (_("directive %s cannot be negated"),
1310 directive_info
[i
].name
);
1315 as_bad (_("unknown directive"));
1316 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1321 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1323 directiveE directive
;
1324 bfd_boolean negated
;
1328 get_directive (&directive
, &negated
);
1329 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1331 discard_rest_of_line ();
1335 if (cur_vinsn
.inside_bundle
)
1336 as_bad (_("directives are not valid inside bundles"));
1340 case directive_literal
:
1341 if (!inside_directive (directive_literal
))
1343 /* Previous labels go with whatever follows this directive, not with
1344 the literal, so save them now. */
1345 saved_insn_labels
= insn_labels
;
1348 as_warn (_(".begin literal is deprecated; use .literal instead"));
1349 state
= XNEW (emit_state
);
1350 xtensa_switch_to_literal_fragment (state
);
1351 directive_push (directive_literal
, negated
, state
);
1354 case directive_literal_prefix
:
1355 /* Have to flush pending output because a movi relaxed to an l32r
1356 might produce a literal. */
1357 md_flush_pending_output ();
1358 /* Check to see if the current fragment is a literal
1359 fragment. If it is, then this operation is not allowed. */
1360 if (generating_literals
)
1362 as_bad (_("cannot set literal_prefix inside literal fragment"));
1366 /* Allocate the literal state for this section and push
1367 onto the directive stack. */
1368 ls
= XNEW (lit_state
);
1371 *ls
= default_lit_sections
;
1372 directive_push (directive_literal_prefix
, negated
, ls
);
1374 /* Process the new prefix. */
1375 xtensa_literal_prefix ();
1378 case directive_freeregs
:
1379 /* This information is currently unused, but we'll accept the statement
1380 and just discard the rest of the line. This won't check the syntax,
1381 but it will accept every correct freeregs directive. */
1382 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1383 directive_push (directive_freeregs
, negated
, 0);
1386 case directive_schedule
:
1387 md_flush_pending_output ();
1388 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1389 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1390 directive_push (directive_schedule
, negated
, 0);
1391 xtensa_set_frag_assembly_state (frag_now
);
1394 case directive_density
:
1395 as_warn (_(".begin [no-]density is ignored"));
1398 case directive_absolute_literals
:
1399 md_flush_pending_output ();
1400 if (!absolute_literals_supported
&& !negated
)
1402 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1405 xtensa_set_frag_assembly_state (frag_now
);
1406 directive_push (directive
, negated
, 0);
1410 md_flush_pending_output ();
1411 xtensa_set_frag_assembly_state (frag_now
);
1412 directive_push (directive
, negated
, 0);
1416 demand_empty_rest_of_line ();
1421 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1423 directiveE begin_directive
, end_directive
;
1424 bfd_boolean begin_negated
, end_negated
;
1428 emit_state
**state_ptr
;
1431 if (cur_vinsn
.inside_bundle
)
1432 as_bad (_("directives are not valid inside bundles"));
1434 get_directive (&end_directive
, &end_negated
);
1436 md_flush_pending_output ();
1438 switch ((int) end_directive
)
1440 case XTENSA_UNDEFINED
:
1441 discard_rest_of_line ();
1444 case (int) directive_density
:
1445 as_warn (_(".end [no-]density is ignored"));
1446 demand_empty_rest_of_line ();
1449 case (int) directive_absolute_literals
:
1450 if (!absolute_literals_supported
&& !end_negated
)
1452 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1453 demand_empty_rest_of_line ();
1462 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1463 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1464 (const void **) state_ptr
);
1466 if (begin_directive
!= directive_none
)
1468 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1470 as_bad (_("does not match begin %s%s at %s:%d"),
1471 begin_negated
? "no-" : "",
1472 directive_info
[begin_directive
].name
, file
, line
);
1476 switch (end_directive
)
1478 case directive_literal
:
1479 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1480 xtensa_restore_emit_state (state
);
1481 xtensa_set_frag_assembly_state (frag_now
);
1483 if (!inside_directive (directive_literal
))
1485 /* Restore the list of current labels. */
1486 xtensa_clear_insn_labels ();
1487 insn_labels
= saved_insn_labels
;
1491 case directive_literal_prefix
:
1492 /* Restore the default collection sections from saved state. */
1493 s
= (lit_state
*) state
;
1495 default_lit_sections
= *s
;
1497 /* Free the state storage. */
1498 free (s
->lit_prefix
);
1502 case directive_schedule
:
1503 case directive_freeregs
:
1507 xtensa_set_frag_assembly_state (frag_now
);
1513 demand_empty_rest_of_line ();
1517 /* Place an aligned literal fragment at the current location. */
1520 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1522 md_flush_pending_output ();
1524 if (inside_directive (directive_literal
))
1525 as_warn (_(".literal_position inside literal directive; ignoring"));
1526 xtensa_mark_literal_pool_location ();
1528 demand_empty_rest_of_line ();
1529 xtensa_clear_insn_labels ();
1533 /* Support .literal label, expr, ... */
1536 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1539 char *p
, *base_name
;
1542 if (inside_directive (directive_literal
))
1544 as_bad (_(".literal not allowed inside .begin literal region"));
1545 ignore_rest_of_line ();
1549 md_flush_pending_output ();
1551 /* Previous labels go with whatever follows this directive, not with
1552 the literal, so save them now. */
1553 saved_insn_labels
= insn_labels
;
1556 base_name
= input_line_pointer
;
1558 xtensa_switch_to_literal_fragment (&state
);
1560 /* All literals are aligned to four-byte boundaries. */
1561 frag_align (2, 0, 0);
1562 record_alignment (now_seg
, 2);
1564 c
= get_symbol_name (&base_name
);
1565 /* Just after name is now '\0'. */
1566 p
= input_line_pointer
;
1568 SKIP_WHITESPACE_AFTER_NAME ();
1570 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1572 as_bad (_("expected comma or colon after symbol name; "
1573 "rest of line ignored"));
1574 ignore_rest_of_line ();
1575 xtensa_restore_emit_state (&state
);
1583 input_line_pointer
++; /* skip ',' or ':' */
1585 xtensa_elf_cons (4);
1587 xtensa_restore_emit_state (&state
);
1589 /* Restore the list of current labels. */
1590 xtensa_clear_insn_labels ();
1591 insn_labels
= saved_insn_labels
;
1596 xtensa_literal_prefix (void)
1601 /* Parse the new prefix from the input_line_pointer. */
1603 len
= strspn (input_line_pointer
,
1604 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1605 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1607 /* Get a null-terminated copy of the name. */
1608 name
= xmemdup0 (input_line_pointer
, len
);
1610 /* Skip the name in the input line. */
1611 input_line_pointer
+= len
;
1613 default_lit_sections
.lit_prefix
= name
;
1615 /* Clear cached literal sections, since the prefix has changed. */
1616 default_lit_sections
.lit_seg
= NULL
;
1617 default_lit_sections
.lit4_seg
= NULL
;
1621 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1624 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1626 float fall_through_f
, target_f
;
1628 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1629 if (fall_through_f
< 0)
1631 as_bad (_("fall through frequency must be greater than 0"));
1632 ignore_rest_of_line ();
1636 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1639 as_bad (_("branch target frequency must be greater than 0"));
1640 ignore_rest_of_line ();
1644 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1646 demand_empty_rest_of_line ();
1650 /* Like normal .long/.short/.word, except support @plt, etc.
1651 Clobbers input_line_pointer, checks end-of-line. */
1654 xtensa_elf_cons (int nbytes
)
1657 bfd_reloc_code_real_type reloc
;
1659 md_flush_pending_output ();
1661 if (cur_vinsn
.inside_bundle
)
1662 as_bad (_("directives are not valid inside bundles"));
1664 if (is_it_end_of_statement ())
1666 demand_empty_rest_of_line ();
1673 if (exp
.X_op
== O_symbol
1674 && *input_line_pointer
== '@'
1675 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1678 reloc_howto_type
*reloc_howto
=
1679 bfd_reloc_type_lookup (stdoutput
, reloc
);
1681 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1682 as_bad (_("unsupported relocation"));
1683 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1684 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1685 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1686 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1687 as_bad (_("opcode-specific %s relocation used outside "
1688 "an instruction"), reloc_howto
->name
);
1689 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1690 as_bad (ngettext ("%s relocations do not fit in %d byte",
1691 "%s relocations do not fit in %d bytes",
1693 reloc_howto
->name
, nbytes
);
1694 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1695 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1696 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1697 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1700 char *p
= frag_more ((int) nbytes
);
1701 xtensa_set_frag_assembly_state (frag_now
);
1702 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1703 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1708 xtensa_set_frag_assembly_state (frag_now
);
1709 emit_expr (&exp
, (unsigned int) nbytes
);
1712 while (*input_line_pointer
++ == ',');
1714 input_line_pointer
--; /* Put terminator back into stream. */
1715 demand_empty_rest_of_line ();
1718 static bfd_boolean is_leb128_expr
;
1721 xtensa_leb128 (int sign
)
1723 is_leb128_expr
= TRUE
;
1725 is_leb128_expr
= FALSE
;
1729 /* Parsing and Idiom Translation. */
1731 /* Parse @plt, etc. and return the desired relocation. */
1732 static bfd_reloc_code_real_type
1733 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1743 return BFD_RELOC_NONE
;
1745 for (ch
= *str
, str2
= ident
;
1746 (str2
< ident
+ sizeof (ident
) - 1
1747 && (ISALNUM (ch
) || ch
== '@'));
1750 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1757 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1758 if (ch
== suffix_relocs
[i
].suffix
[0]
1759 && len
== suffix_relocs
[i
].length
1760 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1762 /* Now check for "identifier@suffix+constant". */
1763 if (*str
== '-' || *str
== '+')
1765 char *orig_line
= input_line_pointer
;
1766 expressionS new_exp
;
1768 input_line_pointer
= str
;
1769 expression (&new_exp
);
1770 if (new_exp
.X_op
== O_constant
)
1772 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1773 str
= input_line_pointer
;
1776 if (&input_line_pointer
!= str_p
)
1777 input_line_pointer
= orig_line
;
1781 return suffix_relocs
[i
].reloc
;
1784 return BFD_RELOC_UNUSED
;
1788 /* Find the matching operator type. */
1790 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1792 operatorT
operator = O_illegal
;
1795 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1797 if (suffix_relocs
[i
].reloc
== reloc
)
1799 operator = suffix_relocs
[i
].operator;
1803 gas_assert (operator != O_illegal
);
1808 /* Find the matching reloc type. */
1809 static bfd_reloc_code_real_type
1810 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1813 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1815 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1817 if (suffix_relocs
[i
].operator == operator)
1819 reloc
= suffix_relocs
[i
].reloc
;
1826 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1827 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1828 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1829 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1832 if (reloc
== BFD_RELOC_UNUSED
)
1833 return BFD_RELOC_32
;
1840 expression_end (const char *name
)
1863 #define ERROR_REG_NUM ((unsigned) -1)
1866 tc_get_register (const char *prefix
)
1869 const char *next_expr
;
1870 const char *old_line_pointer
;
1873 old_line_pointer
= input_line_pointer
;
1875 if (*input_line_pointer
== '$')
1876 ++input_line_pointer
;
1878 /* Accept "sp" as a synonym for "a1". */
1879 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1880 && expression_end (input_line_pointer
+ 2))
1882 input_line_pointer
+= 2;
1883 return 1; /* AR[1] */
1886 while (*input_line_pointer
++ == *prefix
++)
1888 --input_line_pointer
;
1893 as_bad (_("bad register name: %s"), old_line_pointer
);
1894 return ERROR_REG_NUM
;
1897 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1899 as_bad (_("bad register number: %s"), input_line_pointer
);
1900 return ERROR_REG_NUM
;
1905 while (ISDIGIT ((int) *input_line_pointer
))
1906 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1908 if (!(next_expr
= expression_end (input_line_pointer
)))
1910 as_bad (_("bad register name: %s"), old_line_pointer
);
1911 return ERROR_REG_NUM
;
1914 input_line_pointer
= (char *) next_expr
;
1921 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1923 xtensa_isa isa
= xtensa_default_isa
;
1925 /* Check if this is an immediate operand. */
1926 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1928 bfd_reloc_code_real_type reloc
;
1929 segT t
= expression (tok
);
1931 if (t
== absolute_section
1932 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1934 gas_assert (tok
->X_op
== O_constant
);
1935 tok
->X_op
= O_symbol
;
1936 tok
->X_add_symbol
= &abs_symbol
;
1939 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1940 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1945 case BFD_RELOC_LO16
:
1946 if (tok
->X_op
== O_constant
)
1948 tok
->X_add_number
&= 0xffff;
1952 case BFD_RELOC_HI16
:
1953 if (tok
->X_op
== O_constant
)
1955 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1959 case BFD_RELOC_UNUSED
:
1960 as_bad (_("unsupported relocation"));
1962 case BFD_RELOC_32_PCREL
:
1963 as_bad (_("pcrel relocation not allowed in an instruction"));
1968 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1973 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1974 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1976 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1979 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1980 as_bad (_("register number out of range"));
1983 tok
->X_op
= O_register
;
1984 tok
->X_add_symbol
= 0;
1985 tok
->X_add_number
= reg
;
1990 /* Split up the arguments for an opcode or pseudo-op. */
1993 tokenize_arguments (char **args
, char *str
)
1995 char *old_input_line_pointer
;
1996 bfd_boolean saw_comma
= FALSE
;
1997 bfd_boolean saw_arg
= FALSE
;
1998 bfd_boolean saw_colon
= FALSE
;
2000 char *arg_end
, *arg
;
2003 /* Save and restore input_line_pointer around this function. */
2004 old_input_line_pointer
= input_line_pointer
;
2005 input_line_pointer
= str
;
2007 while (*input_line_pointer
)
2010 switch (*input_line_pointer
)
2017 input_line_pointer
++;
2018 if (saw_comma
|| saw_colon
|| !saw_arg
)
2024 input_line_pointer
++;
2025 if (saw_comma
|| saw_colon
|| !saw_arg
)
2031 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2034 arg_end
= input_line_pointer
+ 1;
2035 while (!expression_end (arg_end
))
2038 arg_len
= arg_end
- input_line_pointer
;
2039 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2040 args
[num_args
] = arg
;
2044 strncpy (arg
, input_line_pointer
, arg_len
);
2045 arg
[arg_len
] = '\0';
2047 input_line_pointer
= arg_end
;
2057 if (saw_comma
|| saw_colon
)
2059 input_line_pointer
= old_input_line_pointer
;
2064 as_bad (_("extra comma"));
2066 as_bad (_("extra colon"));
2068 as_bad (_("missing argument"));
2070 as_bad (_("missing comma or colon"));
2071 input_line_pointer
= old_input_line_pointer
;
2076 /* Parse the arguments to an opcode. Return TRUE on error. */
2079 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2081 expressionS
*tok
, *last_tok
;
2082 xtensa_opcode opcode
= insn
->opcode
;
2083 bfd_boolean had_error
= TRUE
;
2084 xtensa_isa isa
= xtensa_default_isa
;
2085 int n
, num_regs
= 0;
2086 int opcode_operand_count
;
2087 int opnd_cnt
, last_opnd_cnt
;
2088 unsigned int next_reg
= 0;
2089 char *old_input_line_pointer
;
2091 if (insn
->insn_type
== ITYPE_LITERAL
)
2092 opcode_operand_count
= 1;
2094 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2097 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2099 /* Save and restore input_line_pointer around this function. */
2100 old_input_line_pointer
= input_line_pointer
;
2106 /* Skip invisible operands. */
2107 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2113 for (n
= 0; n
< num_args
; n
++)
2115 input_line_pointer
= arg_strings
[n
];
2116 if (*input_line_pointer
== ':')
2118 xtensa_regfile opnd_rf
;
2119 input_line_pointer
++;
2122 gas_assert (opnd_cnt
> 0);
2124 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2126 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2127 as_warn (_("incorrect register number, ignoring"));
2132 if (opnd_cnt
>= opcode_operand_count
)
2134 as_warn (_("too many arguments"));
2137 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2139 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2140 next_reg
= tok
->X_add_number
+ 1;
2142 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2144 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2146 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2147 /* minus 1 because we are seeing one right now */
2153 last_opnd_cnt
= opnd_cnt
;
2154 demand_empty_rest_of_line ();
2161 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2165 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2168 insn
->ntok
= tok
- insn
->tok
;
2172 input_line_pointer
= old_input_line_pointer
;
2178 get_invisible_operands (TInsn
*insn
)
2180 xtensa_isa isa
= xtensa_default_isa
;
2181 static xtensa_insnbuf slotbuf
= NULL
;
2183 xtensa_opcode opc
= insn
->opcode
;
2184 int slot
, opnd
, fmt_found
;
2188 slotbuf
= xtensa_insnbuf_alloc (isa
);
2190 /* Find format/slot where this can be encoded. */
2193 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2195 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2197 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2203 if (fmt_found
) break;
2208 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2212 /* First encode all the visible operands
2213 (to deal with shared field operands). */
2214 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2216 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2217 && (insn
->tok
[opnd
].X_op
== O_register
2218 || insn
->tok
[opnd
].X_op
== O_constant
))
2220 val
= insn
->tok
[opnd
].X_add_number
;
2221 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2222 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2226 /* Then pull out the values for the invisible ones. */
2227 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2229 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2231 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2232 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2233 insn
->tok
[opnd
].X_add_number
= val
;
2234 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2235 insn
->tok
[opnd
].X_op
= O_register
;
2237 insn
->tok
[opnd
].X_op
= O_constant
;
2246 xg_reverse_shift_count (char **cnt_argp
)
2248 char *cnt_arg
, *new_arg
;
2249 cnt_arg
= *cnt_argp
;
2251 /* replace the argument with "31-(argument)" */
2252 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2255 *cnt_argp
= new_arg
;
2259 /* If "arg" is a constant expression, return non-zero with the value
2263 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2266 char *save_ptr
= input_line_pointer
;
2268 input_line_pointer
= arg
;
2270 input_line_pointer
= save_ptr
;
2272 if (exp
.X_op
== O_constant
)
2274 *valp
= exp
.X_add_number
;
2283 xg_replace_opname (char **popname
, const char *newop
)
2286 *popname
= xstrdup (newop
);
2291 xg_check_num_args (int *pnum_args
,
2296 int num_args
= *pnum_args
;
2298 if (num_args
< expected_num
)
2300 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2301 num_args
, opname
, expected_num
);
2305 if (num_args
> expected_num
)
2307 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2308 num_args
, opname
, expected_num
);
2309 while (num_args
-- > expected_num
)
2311 free (arg_strings
[num_args
]);
2312 arg_strings
[num_args
] = 0;
2314 *pnum_args
= expected_num
;
2322 /* If the register is not specified as part of the opcode,
2323 then get it from the operand and move it to the opcode. */
2326 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2328 xtensa_isa isa
= xtensa_default_isa
;
2330 char *opname
, *new_opname
;
2331 const char *sr_name
;
2332 int is_user
, is_write
;
2337 is_user
= (opname
[1] == 'u');
2338 is_write
= (opname
[0] == 'w');
2340 /* Opname == [rw]ur or [rwx]sr... */
2342 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2345 /* Check if the argument is a symbolic register name. */
2346 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2347 /* Handle WSR to "INTSET" as a special case. */
2348 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2349 && !strcasecmp (arg_strings
[1], "intset"))
2350 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2351 if (sr
== XTENSA_UNDEFINED
2352 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2354 /* Maybe it's a register number.... */
2356 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2358 as_bad (_("invalid register '%s' for '%s' instruction"),
2359 arg_strings
[1], opname
);
2362 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2363 if (sr
== XTENSA_UNDEFINED
)
2365 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2366 (long) val
, opname
);
2371 /* Remove the last argument, which is now part of the opcode. */
2372 free (arg_strings
[1]);
2376 /* Translate the opcode. */
2377 sr_name
= xtensa_sysreg_name (isa
, sr
);
2378 /* Another special case for "WSR.INTSET".... */
2379 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2381 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2383 *popname
= new_opname
;
2390 xtensa_translate_old_userreg_ops (char **popname
)
2392 xtensa_isa isa
= xtensa_default_isa
;
2394 char *opname
, *new_opname
;
2395 const char *sr_name
;
2396 bfd_boolean has_underbar
= FALSE
;
2399 if (opname
[0] == '_')
2401 has_underbar
= TRUE
;
2405 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2406 if (sr
!= XTENSA_UNDEFINED
)
2408 /* The new default name ("nnn") is different from the old default
2409 name ("URnnn"). The old default is handled below, and we don't
2410 want to recognize [RW]nnn, so do nothing if the name is the (new)
2412 static char namebuf
[10];
2413 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2414 if (strcmp (namebuf
, opname
+ 1) == 0)
2422 /* Only continue if the reg name is "URnnn". */
2423 if (opname
[1] != 'u' || opname
[2] != 'r')
2425 val
= strtoul (opname
+ 3, &end
, 10);
2429 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2430 if (sr
== XTENSA_UNDEFINED
)
2432 as_bad (_("invalid register number (%ld) for '%s'"),
2433 (long) val
, opname
);
2438 /* Translate the opcode. */
2439 sr_name
= xtensa_sysreg_name (isa
, sr
);
2440 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2441 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2442 opname
[0], sr_name
);
2444 *popname
= new_opname
;
2451 xtensa_translate_zero_immed (const char *old_op
,
2461 gas_assert (opname
[0] != '_');
2463 if (strcmp (opname
, old_op
) != 0)
2466 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2468 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2470 xg_replace_opname (popname
, new_op
);
2471 free (arg_strings
[1]);
2472 arg_strings
[1] = arg_strings
[2];
2481 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2482 Returns non-zero if an error was found. */
2485 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2487 char *opname
= *popname
;
2488 bfd_boolean has_underbar
= FALSE
;
2492 has_underbar
= TRUE
;
2496 if (strcmp (opname
, "mov") == 0)
2498 if (use_transform () && !has_underbar
&& density_supported
)
2499 xg_replace_opname (popname
, "mov.n");
2502 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2504 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2505 arg_strings
[2] = xstrdup (arg_strings
[1]);
2511 /* Without an operand, this is given a default immediate operand of 0. */
2512 if ((strcmp (opname
, "simcall") == 0 && microarch_earliest
>= 280000))
2514 if (*pnum_args
== 0)
2516 arg_strings
[0] = (char *) xmalloc (2);
2517 strcpy (arg_strings
[0], "0");
2523 if (strcmp (opname
, "bbsi.l") == 0)
2525 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2527 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2528 if (target_big_endian
)
2529 xg_reverse_shift_count (&arg_strings
[1]);
2533 if (strcmp (opname
, "bbci.l") == 0)
2535 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2537 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2538 if (target_big_endian
)
2539 xg_reverse_shift_count (&arg_strings
[1]);
2543 /* Don't do anything special with NOPs inside FLIX instructions. They
2544 are handled elsewhere. Real NOP instructions are always available
2545 in configurations with FLIX, so this should never be an issue but
2546 check for it anyway. */
2547 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2548 && strcmp (opname
, "nop") == 0)
2550 if (use_transform () && !has_underbar
&& density_supported
)
2551 xg_replace_opname (popname
, "nop.n");
2554 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2556 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2557 arg_strings
[0] = xstrdup ("a1");
2558 arg_strings
[1] = xstrdup ("a1");
2559 arg_strings
[2] = xstrdup ("a1");
2565 /* Recognize [RW]UR and [RWX]SR. */
2566 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2567 && (opname
[1] == 'u' || opname
[1] == 's'))
2568 || (opname
[0] == 'x' && opname
[1] == 's'))
2570 && opname
[3] == '\0')
2571 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2573 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2574 [RW]<name> if <name> is the non-default name of a user register. */
2575 if ((opname
[0] == 'r' || opname
[0] == 'w')
2576 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2577 return xtensa_translate_old_userreg_ops (popname
);
2579 /* Relax branches that don't allow comparisons against an immediate value
2580 of zero to the corresponding branches with implicit zero immediates. */
2581 if (!has_underbar
&& use_transform ())
2583 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2584 pnum_args
, arg_strings
))
2587 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2588 pnum_args
, arg_strings
))
2591 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2592 pnum_args
, arg_strings
))
2595 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2596 pnum_args
, arg_strings
))
2604 /* Functions for dealing with the Xtensa ISA. */
2606 /* Currently the assembler only allows us to use a single target per
2607 fragment. Because of this, only one operand for a given
2608 instruction may be symbolic. If there is a PC-relative operand,
2609 the last one is chosen. Otherwise, the result is the number of the
2610 last immediate operand, and if there are none of those, we fail and
2614 get_relaxable_immed (xtensa_opcode opcode
)
2616 int last_immed
= -1;
2619 if (opcode
== XTENSA_UNDEFINED
)
2622 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2623 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2625 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2627 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2629 if (last_immed
== -1
2630 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2637 static xtensa_opcode
2638 get_opcode_from_buf (const char *buf
, int slot
)
2640 static xtensa_insnbuf insnbuf
= NULL
;
2641 static xtensa_insnbuf slotbuf
= NULL
;
2642 xtensa_isa isa
= xtensa_default_isa
;
2647 insnbuf
= xtensa_insnbuf_alloc (isa
);
2648 slotbuf
= xtensa_insnbuf_alloc (isa
);
2651 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2652 fmt
= xtensa_format_decode (isa
, insnbuf
);
2653 if (fmt
== XTENSA_UNDEFINED
)
2654 return XTENSA_UNDEFINED
;
2656 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2657 return XTENSA_UNDEFINED
;
2659 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2660 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2664 #ifdef TENSILICA_DEBUG
2666 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2669 xtensa_print_insn_table (void)
2671 int num_opcodes
, num_operands
;
2672 xtensa_opcode opcode
;
2673 xtensa_isa isa
= xtensa_default_isa
;
2675 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2676 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2679 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2680 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2681 for (opn
= 0; opn
< num_operands
; opn
++)
2683 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2685 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2687 xtensa_regfile opnd_rf
=
2688 xtensa_operand_regfile (isa
, opcode
, opn
);
2689 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2691 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2692 fputs ("[lLr] ", stderr
);
2694 fputs ("i ", stderr
);
2696 fprintf (stderr
, "\n");
2702 print_vliw_insn (xtensa_insnbuf vbuf
)
2704 xtensa_isa isa
= xtensa_default_isa
;
2705 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2706 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2709 fprintf (stderr
, "format = %d\n", f
);
2711 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2713 xtensa_opcode opcode
;
2717 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2718 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2719 opname
= xtensa_opcode_name (isa
, opcode
);
2721 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2722 fprintf (stderr
, " operands = ");
2724 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2728 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2730 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2731 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2732 fprintf (stderr
, "%d ", val
);
2734 fprintf (stderr
, "\n");
2736 xtensa_insnbuf_free (isa
, sbuf
);
2739 #endif /* TENSILICA_DEBUG */
2743 is_direct_call_opcode (xtensa_opcode opcode
)
2745 xtensa_isa isa
= xtensa_default_isa
;
2746 int n
, num_operands
;
2748 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2751 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2752 for (n
= 0; n
< num_operands
; n
++)
2754 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2755 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2762 /* Convert from BFD relocation type code to slot and operand number.
2763 Returns non-zero on failure. */
2766 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2768 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2769 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2771 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2774 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2775 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2777 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2787 /* Convert from slot number to BFD relocation type code for the
2788 standard PC-relative relocations. Return BFD_RELOC_NONE on
2791 static bfd_reloc_code_real_type
2792 encode_reloc (int slot
)
2794 if (slot
< 0 || slot
> 14)
2795 return BFD_RELOC_NONE
;
2797 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2801 /* Convert from slot numbers to BFD relocation type code for the
2802 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2804 static bfd_reloc_code_real_type
2805 encode_alt_reloc (int slot
)
2807 if (slot
< 0 || slot
> 14)
2808 return BFD_RELOC_NONE
;
2810 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2815 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2818 xtensa_opcode opcode
,
2824 uint32 valbuf
= value
;
2826 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2828 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2830 as_bad_where ((char *) file
, line
,
2831 _("operand %d of '%s' has out of range value '%u'"),
2833 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2836 as_bad_where ((char *) file
, line
,
2837 _("operand %d of '%s' has invalid value '%u'"),
2839 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2844 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2850 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2853 xtensa_opcode opcode
,
2857 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2858 fmt
, slot
, slotbuf
, &val
);
2859 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2864 /* Checks for rules from xtensa-relax tables. */
2866 /* The routine xg_instruction_matches_option_term must return TRUE
2867 when a given option term is true. The meaning of all of the option
2868 terms is given interpretation by this function. */
2871 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2873 if (strcmp (option
->option_name
, "realnop") == 0
2874 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2876 /* These conditions were evaluated statically when building the
2877 relaxation table. There's no need to reevaluate them now. */
2880 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2881 return insn
->extra_arg
.X_op
== O_register
;
2884 as_fatal (_("internal error: unknown option name '%s'"),
2885 option
->option_name
);
2891 xg_instruction_matches_or_options (TInsn
*insn
,
2892 const ReqOrOptionList
*or_option
)
2894 const ReqOrOption
*option
;
2895 /* Must match each of the AND terms. */
2896 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2898 if (xg_instruction_matches_option_term (insn
, option
))
2906 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2908 const ReqOption
*req_options
;
2909 /* Must match each of the AND terms. */
2910 for (req_options
= options
;
2911 req_options
!= NULL
;
2912 req_options
= req_options
->next
)
2914 /* Must match one of the OR clauses. */
2915 if (!xg_instruction_matches_or_options (insn
,
2916 req_options
->or_option_terms
))
2923 /* Return the transition rule that matches or NULL if none matches. */
2926 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2928 PreconditionList
*condition_l
;
2930 if (rule
->opcode
!= insn
->opcode
)
2933 for (condition_l
= rule
->conditions
;
2934 condition_l
!= NULL
;
2935 condition_l
= condition_l
->next
)
2939 Precondition
*cond
= condition_l
->precond
;
2944 /* The expression must be the constant. */
2945 gas_assert (cond
->op_num
< insn
->ntok
);
2946 exp1
= &insn
->tok
[cond
->op_num
];
2947 if (expr_is_const (exp1
))
2952 if (get_expr_const (exp1
) != cond
->op_data
)
2956 if (get_expr_const (exp1
) == cond
->op_data
)
2963 else if (expr_is_register (exp1
))
2968 if (get_expr_register (exp1
) != cond
->op_data
)
2972 if (get_expr_register (exp1
) == cond
->op_data
)
2984 gas_assert (cond
->op_num
< insn
->ntok
);
2985 gas_assert (cond
->op_data
< insn
->ntok
);
2986 exp1
= &insn
->tok
[cond
->op_num
];
2987 exp2
= &insn
->tok
[cond
->op_data
];
2992 if (!expr_is_equal (exp1
, exp2
))
2996 if (expr_is_equal (exp1
, exp2
))
3008 if (!xg_instruction_matches_options (insn
, rule
->options
))
3016 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
3018 bfd_boolean a_greater
= FALSE
;
3019 bfd_boolean b_greater
= FALSE
;
3021 ReqOptionList
*l_a
= a
->options
;
3022 ReqOptionList
*l_b
= b
->options
;
3024 /* We only care if they both are the same except for
3025 a const16 vs. an l32r. */
3027 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3029 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3030 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3031 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3033 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3035 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3037 /* This is the case we care about. */
3038 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3039 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3046 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3047 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3057 l_or_a
= l_or_a
->next
;
3058 l_or_b
= l_or_b
->next
;
3060 if (l_or_a
|| l_or_b
)
3069 /* Incomparable if the substitution was used differently in two cases. */
3070 if (a_greater
&& b_greater
)
3082 static TransitionRule
*
3083 xg_instruction_match (TInsn
*insn
)
3085 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3087 gas_assert (insn
->opcode
< table
->num_opcodes
);
3089 /* Walk through all of the possible transitions. */
3090 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3092 TransitionRule
*rule
= l
->rule
;
3093 if (xg_instruction_matches_rule (insn
, rule
))
3100 /* Various Other Internal Functions. */
3103 is_unique_insn_expansion (TransitionRule
*r
)
3105 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3107 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3113 /* Check if there is exactly one relaxation for INSN that converts it to
3114 another instruction of equal or larger size. If so, and if TARG is
3115 non-null, go ahead and generate the relaxed instruction into TARG. If
3116 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3117 instruction, i.e., ignore relaxations that convert to an instruction of
3118 equal size. In some contexts where this function is used, only
3119 a single widening is allowed and the NARROW_ONLY argument is used to
3120 exclude cases like ADDI being "widened" to an ADDMI, which may
3121 later be relaxed to an ADDMI/ADDI pair. */
3124 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3126 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3128 TransitionRule
*match
= 0;
3130 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3131 gas_assert (insn
->opcode
< table
->num_opcodes
);
3133 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3135 TransitionRule
*rule
= l
->rule
;
3137 if (xg_instruction_matches_rule (insn
, rule
)
3138 && is_unique_insn_expansion (rule
)
3139 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3140 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3151 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3156 /* Return the maximum number of bytes this opcode can expand to. */
3159 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3161 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3163 int max_size
= xg_get_single_size (opcode
);
3165 gas_assert (opcode
< table
->num_opcodes
);
3167 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3169 TransitionRule
*rule
= l
->rule
;
3170 BuildInstr
*build_list
;
3175 build_list
= rule
->to_instr
;
3176 if (is_unique_insn_expansion (rule
))
3178 gas_assert (build_list
->typ
== INSTR_INSTR
);
3179 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3182 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3184 switch (build_list
->typ
)
3187 this_size
+= xg_get_single_size (build_list
->opcode
);
3189 case INSTR_LITERAL_DEF
:
3190 case INSTR_LABEL_DEF
:
3195 if (this_size
> max_size
)
3196 max_size
= this_size
;
3202 /* Return the maximum number of literal bytes this opcode can generate. */
3205 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3207 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3211 gas_assert (opcode
< table
->num_opcodes
);
3213 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3215 TransitionRule
*rule
= l
->rule
;
3216 BuildInstr
*build_list
;
3221 build_list
= rule
->to_instr
;
3222 if (is_unique_insn_expansion (rule
))
3224 gas_assert (build_list
->typ
== INSTR_INSTR
);
3225 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3228 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3230 switch (build_list
->typ
)
3232 case INSTR_LITERAL_DEF
:
3233 /* Hard-coded 4-byte literal. */
3237 case INSTR_LABEL_DEF
:
3242 if (this_size
> max_size
)
3243 max_size
= this_size
;
3250 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3252 int steps_taken
= 0;
3253 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3256 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3257 gas_assert (insn
->opcode
< table
->num_opcodes
);
3259 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3261 TransitionRule
*rule
= l
->rule
;
3263 if (xg_instruction_matches_rule (insn
, rule
))
3265 if (steps_taken
== lateral_steps
)
3275 get_special_literal_symbol (void)
3277 static symbolS
*sym
= NULL
;
3280 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3286 get_special_label_symbol (void)
3288 static symbolS
*sym
= NULL
;
3291 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3297 xg_valid_literal_expression (const expressionS
*exp
)
3319 /* This will check to see if the value can be converted into the
3320 operand type. It will return TRUE if it does not fit. */
3323 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3325 uint32 valbuf
= value
;
3326 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3332 /* Assumes: All immeds are constants. Check that all constants fit
3333 into their immeds; return FALSE if not. */
3336 xg_immeds_fit (const TInsn
*insn
)
3338 xtensa_isa isa
= xtensa_default_isa
;
3342 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3343 for (i
= 0; i
< n
; ++i
)
3345 const expressionS
*exp
= &insn
->tok
[i
];
3347 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3354 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3359 /* The symbol should have a fixup associated with it. */
3368 /* This should only be called after we have an initial
3369 estimate of the addresses. */
3372 xg_symbolic_immeds_fit (const TInsn
*insn
,
3378 xtensa_isa isa
= xtensa_default_isa
;
3386 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3388 for (i
= 0; i
< n
; ++i
)
3390 const expressionS
*exp
= &insn
->tok
[i
];
3392 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3399 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3405 /* Check for the worst case. */
3406 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3411 /* We only allow symbols for PC-relative references.
3412 If pc_frag == 0, then we don't have frag locations yet. */
3414 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3417 /* If it is a weak symbol or a symbol in a different section,
3418 it cannot be known to fit at assembly time. */
3419 if (S_IS_WEAK (exp
->X_add_symbol
)
3420 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3422 /* For a direct call with --no-longcalls, be optimistic and
3423 assume it will be in range. If the symbol is weak and
3424 undefined, it may remain undefined at link-time, in which
3425 case it will have a zero value and almost certainly be out
3426 of range for a direct call; thus, relax for undefined weak
3427 symbols even if longcalls is not enabled. */
3428 if (is_direct_call_opcode (insn
->opcode
)
3429 && ! pc_frag
->tc_frag_data
.use_longcalls
3430 && (! S_IS_WEAK (exp
->X_add_symbol
)
3431 || S_IS_DEFINED (exp
->X_add_symbol
)))
3437 symbolP
= exp
->X_add_symbol
;
3438 sym_frag
= symbol_get_frag (symbolP
);
3439 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3440 pc
= pc_frag
->fr_address
+ pc_offset
;
3442 /* If frag has yet to be reached on this pass, assume it
3443 will move by STRETCH just as we did. If this is not so,
3444 it will be because some frag between grows, and that will
3445 force another pass. Beware zero-length frags. There
3446 should be a faster way to do this. */
3449 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3450 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3455 new_offset
= target
;
3456 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3457 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3462 /* The symbol should have a fixup associated with it. */
3471 /* Return TRUE on success. */
3474 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3480 targ
->debug_line
= insn
->debug_line
;
3481 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3486 targ
->opcode
= bi
->opcode
;
3487 targ
->insn_type
= ITYPE_INSN
;
3488 targ
->is_specific_opcode
= FALSE
;
3490 for (; op
!= NULL
; op
= op
->next
)
3492 int op_num
= op
->op_num
;
3493 int op_data
= op
->op_data
;
3495 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3497 if (targ
->ntok
<= op_num
)
3498 targ
->ntok
= op_num
+ 1;
3503 set_expr_const (&targ
->tok
[op_num
], op_data
);
3506 gas_assert (op_data
< insn
->ntok
);
3507 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3510 if (insn
->extra_arg
.X_op
!= O_register
)
3512 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3515 sym
= get_special_literal_symbol ();
3516 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3517 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3518 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3519 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3522 sym
= get_special_label_symbol ();
3523 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3525 case OP_OPERAND_HI16U
:
3526 case OP_OPERAND_LOW16U
:
3527 gas_assert (op_data
< insn
->ntok
);
3528 if (expr_is_const (&insn
->tok
[op_data
]))
3531 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3532 val
= xg_apply_userdef_op_fn (op
->typ
,
3535 targ
->tok
[op_num
].X_add_number
= val
;
3539 /* For const16 we can create relocations for these. */
3540 if (targ
->opcode
== XTENSA_UNDEFINED
3541 || (targ
->opcode
!= xtensa_const16_opcode
))
3543 gas_assert (op_data
< insn
->ntok
);
3544 /* Need to build a O_lo16 or O_hi16. */
3545 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3546 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3548 if (op
->typ
== OP_OPERAND_HI16U
)
3549 targ
->tok
[op_num
].X_op
= O_hi16
;
3550 else if (op
->typ
== OP_OPERAND_LOW16U
)
3551 targ
->tok
[op_num
].X_op
= O_lo16
;
3558 /* currently handles:
3561 OP_OPERAND_F32MINUS */
3562 if (xg_has_userdef_op_fn (op
->typ
))
3564 gas_assert (op_data
< insn
->ntok
);
3565 if (expr_is_const (&insn
->tok
[op_data
]))
3568 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3569 val
= xg_apply_userdef_op_fn (op
->typ
,
3572 targ
->tok
[op_num
].X_add_number
= val
;
3575 return FALSE
; /* We cannot use a relocation for this. */
3584 case INSTR_LITERAL_DEF
:
3586 targ
->opcode
= XTENSA_UNDEFINED
;
3587 targ
->insn_type
= ITYPE_LITERAL
;
3588 targ
->is_specific_opcode
= FALSE
;
3589 for (; op
!= NULL
; op
= op
->next
)
3591 int op_num
= op
->op_num
;
3592 int op_data
= op
->op_data
;
3593 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3595 if (targ
->ntok
<= op_num
)
3596 targ
->ntok
= op_num
+ 1;
3601 gas_assert (op_data
< insn
->ntok
);
3602 /* We can only pass resolvable literals through. */
3603 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3605 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3617 case INSTR_LABEL_DEF
:
3619 targ
->opcode
= XTENSA_UNDEFINED
;
3620 targ
->insn_type
= ITYPE_LABEL
;
3621 targ
->is_specific_opcode
= FALSE
;
3622 /* Literal with no ops is a label? */
3623 gas_assert (op
== NULL
);
3634 /* Return TRUE on success. */
3637 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3639 for (; bi
!= NULL
; bi
= bi
->next
)
3641 TInsn
*next_insn
= istack_push_space (istack
);
3643 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3650 /* Return TRUE on valid expansion. */
3653 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3655 int stack_size
= istack
->ninsn
;
3656 int steps_taken
= 0;
3657 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3660 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3661 gas_assert (insn
->opcode
< table
->num_opcodes
);
3663 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3665 TransitionRule
*rule
= l
->rule
;
3667 if (xg_instruction_matches_rule (insn
, rule
))
3669 if (lateral_steps
== steps_taken
)
3673 /* This is it. Expand the rule to the stack. */
3674 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3677 /* Check to see if it fits. */
3678 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3680 TInsn
*tinsn
= &istack
->insn
[i
];
3682 if (tinsn
->insn_type
== ITYPE_INSN
3683 && !tinsn_has_symbolic_operands (tinsn
)
3684 && !xg_immeds_fit (tinsn
))
3686 istack
->ninsn
= stack_size
;
3699 /* Relax the assembly instruction at least "min_steps".
3700 Return the number of steps taken.
3702 For relaxation to correctly terminate, every relaxation chain must
3703 terminate in one of two ways:
3705 1. If the chain from one instruction to the next consists entirely of
3706 single instructions, then the chain *must* handle all possible
3707 immediates without failing. It must not ever fail because an
3708 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3709 chain is one example. L32R loads 32 bits, and there cannot be an
3710 immediate larger than 32 bits, so it satisfies this condition.
3711 Single instruction relaxation chains are as defined by
3712 xg_is_single_relaxable_instruction.
3714 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3715 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3717 Strictly speaking, in most cases you can violate condition 1 and be OK
3718 -- in particular when the last two instructions have the same single
3719 size. But nevertheless, you should guarantee the above two conditions.
3721 We could fix this so that single-instruction expansions correctly
3722 terminate when they can't handle the range, but the error messages are
3723 worse, and it actually turns out that in every case but one (18-bit wide
3724 branches), you need a multi-instruction expansion to get the full range
3725 anyway. And because 18-bit branches are handled identically to 15-bit
3726 branches, there isn't any point in changing it. */
3729 xg_assembly_relax (IStack
*istack
,
3732 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3733 offsetT pc_offset
, /* offset in fragment */
3734 int min_steps
, /* minimum conversion steps */
3735 long stretch
) /* number of bytes stretched so far */
3737 int steps_taken
= 0;
3739 /* Some of its immeds don't fit. Try to build a relaxed version.
3740 This may go through a couple of stages of single instruction
3741 transformations before we get there. */
3743 TInsn single_target
;
3745 int lateral_steps
= 0;
3746 int istack_size
= istack
->ninsn
;
3748 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3749 && steps_taken
>= min_steps
)
3751 istack_push (istack
, insn
);
3754 current_insn
= *insn
;
3756 /* Walk through all of the single instruction expansions. */
3757 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3760 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3763 if (steps_taken
>= min_steps
)
3765 istack_push (istack
, &single_target
);
3769 current_insn
= single_target
;
3772 /* Now check for a multi-instruction expansion. */
3773 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3775 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3778 if (steps_taken
>= min_steps
)
3780 istack_push (istack
, ¤t_insn
);
3785 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3787 if (steps_taken
>= min_steps
)
3791 istack
->ninsn
= istack_size
;
3794 /* It's not going to work -- use the original. */
3795 istack_push (istack
, insn
);
3801 xg_finish_frag (char *last_insn
,
3802 enum xtensa_relax_statesE frag_state
,
3803 enum xtensa_relax_statesE slot0_state
,
3805 bfd_boolean is_insn
)
3807 /* Finish off this fragment so that it has at LEAST the desired
3808 max_growth. If it doesn't fit in this fragment, close this one
3809 and start a new one. In either case, return a pointer to the
3810 beginning of the growth area. */
3814 frag_grow (max_growth
);
3815 old_frag
= frag_now
;
3817 frag_now
->fr_opcode
= last_insn
;
3819 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3821 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3822 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3824 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3825 xtensa_set_frag_assembly_state (frag_now
);
3827 /* Just to make sure that we did not split it up. */
3828 gas_assert (old_frag
->fr_next
== frag_now
);
3832 /* Return TRUE if the target frag is one of the next non-empty frags. */
3835 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3840 for (; fragP
; fragP
= fragP
->fr_next
)
3842 if (fragP
== target
)
3844 if (fragP
->fr_fix
!= 0)
3846 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3848 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3849 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3851 if (fragP
->fr_type
== rs_space
)
3859 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3861 xtensa_isa isa
= xtensa_default_isa
;
3863 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3868 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3869 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3872 for (i
= 0; i
< num_ops
; i
++)
3874 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3880 if (target_op
== -1)
3883 if (insn
->ntok
<= target_op
)
3886 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3889 sym
= insn
->tok
[target_op
].X_add_symbol
;
3893 if (insn
->tok
[target_op
].X_add_number
!= 0)
3896 target_frag
= symbol_get_frag (sym
);
3897 if (target_frag
== NULL
)
3900 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3901 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3909 xg_add_branch_and_loop_targets (TInsn
*insn
)
3911 xtensa_isa isa
= xtensa_default_isa
;
3912 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3914 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3917 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3918 && insn
->tok
[i
].X_op
== O_symbol
)
3919 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3923 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3924 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3928 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3930 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3931 && insn
->tok
[i
].X_op
== O_symbol
)
3933 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3934 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3935 if (S_IS_DEFINED (sym
))
3936 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3943 /* Return FALSE if no error. */
3946 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3951 switch (instr_spec
->typ
)
3954 new_insn
->insn_type
= ITYPE_INSN
;
3955 new_insn
->opcode
= instr_spec
->opcode
;
3957 case INSTR_LITERAL_DEF
:
3958 new_insn
->insn_type
= ITYPE_LITERAL
;
3959 new_insn
->opcode
= XTENSA_UNDEFINED
;
3961 case INSTR_LABEL_DEF
:
3964 new_insn
->is_specific_opcode
= FALSE
;
3965 new_insn
->debug_line
= old_insn
->debug_line
;
3966 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3968 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3971 const expressionS
*src_exp
;
3977 /* The expression must be the constant. */
3978 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3979 exp
= &new_insn
->tok
[b_op
->op_num
];
3980 set_expr_const (exp
, b_op
->op_data
);
3984 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3985 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3986 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3987 exp
= &new_insn
->tok
[b_op
->op_num
];
3988 copy_expr (exp
, src_exp
);
3993 as_bad (_("can't handle generation of literal/labels yet"));
3997 as_bad (_("can't handle undefined OP TYPE"));
4002 new_insn
->ntok
= num_ops
;
4007 /* Return TRUE if it was simplified. */
4010 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
4012 TransitionRule
*rule
;
4013 BuildInstr
*insn_spec
;
4015 if (old_insn
->is_specific_opcode
|| !density_supported
)
4018 rule
= xg_instruction_match (old_insn
);
4022 insn_spec
= rule
->to_instr
;
4023 /* There should only be one. */
4024 gas_assert (insn_spec
!= NULL
);
4025 gas_assert (insn_spec
->next
== NULL
);
4026 if (insn_spec
->next
!= NULL
)
4029 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4035 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4036 l32i.n. (2) Check the number of operands. (3) Place the instruction
4037 tokens into the stack or relax it and place multiple
4038 instructions/literals onto the stack. Return FALSE if no error. */
4041 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4045 bfd_boolean do_expand
;
4047 tinsn_init (&new_insn
);
4049 /* Narrow it if we can. xg_simplify_insn now does all the
4050 appropriate checking (e.g., for the density option). */
4051 if (xg_simplify_insn (orig_insn
, &new_insn
))
4052 orig_insn
= &new_insn
;
4054 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4056 if (orig_insn
->ntok
< noperands
)
4058 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4059 "found %d operands for '%s': Expected %d",
4062 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4066 if (orig_insn
->ntok
> noperands
)
4067 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4068 "found %d operands for '%s': Expected %d",
4071 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4074 /* If there are not enough operands, we will assert above. If there
4075 are too many, just cut out the extras here. */
4076 orig_insn
->ntok
= noperands
;
4078 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4081 /* Special case for extui opcode which has constraints not handled
4082 by the ordinary operand encoding checks. The number of operands
4083 and related syntax issues have already been checked. */
4084 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4086 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4087 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4088 if (shiftimm
+ maskimm
> 32)
4090 as_bad (_("immediate operands sum to greater than 32"));
4095 /* If the instruction will definitely need to be relaxed, it is better
4096 to expand it now for better scheduling. Decide whether to expand
4098 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4100 /* Calls should be expanded to longcalls only in the backend relaxation
4101 so that the assembly scheduler will keep the L32R/CALLX instructions
4103 if (is_direct_call_opcode (orig_insn
->opcode
))
4106 if (tinsn_has_symbolic_operands (orig_insn
))
4108 /* The values of symbolic operands are not known yet, so only expand
4109 now if an operand is "complex" (e.g., difference of symbols) and
4110 will have to be stored as a literal regardless of the value. */
4111 if (!tinsn_has_complex_operands (orig_insn
))
4114 else if (xg_immeds_fit (orig_insn
))
4118 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4120 istack_push (istack
, orig_insn
);
4126 /* Return TRUE if the section flags are marked linkonce
4127 or the name is .gnu.linkonce.*. */
4129 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4132 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4134 flagword flags
, link_once_flags
;
4136 flags
= bfd_section_flags (sec
);
4137 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4139 /* Flags might not be set yet. */
4140 if (!link_once_flags
4141 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4142 link_once_flags
= SEC_LINK_ONCE
;
4144 return (link_once_flags
!= 0);
4149 xtensa_add_literal_sym (symbolS
*sym
)
4153 l
= XNEW (sym_list
);
4155 l
->next
= literal_syms
;
4161 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4163 static int lit_num
= 0;
4164 static char name
[256];
4167 sprintf (name
, ".L_lit_sym%d", lit_num
);
4169 /* Create a local symbol. If it is in a linkonce section, we have to
4170 be careful to make sure that if it is used in a relocation that the
4171 symbol will be in the output file. */
4172 if (get_is_linkonce_section (stdoutput
, sec
))
4174 symbolP
= symbol_new (name
, sec
, 0, frag
);
4175 S_CLEAR_EXTERNAL (symbolP
);
4176 /* symbolP->local = 1; */
4179 symbolP
= symbol_new (name
, sec
, 0, frag
);
4181 xtensa_add_literal_sym (symbolP
);
4188 /* Currently all literals that are generated here are 32-bit L32R targets. */
4191 xg_assemble_literal (/* const */ TInsn
*insn
)
4194 symbolS
*lit_sym
= NULL
;
4195 bfd_reloc_code_real_type reloc
;
4196 bfd_boolean pcrel
= FALSE
;
4199 /* size = 4 for L32R. It could easily be larger when we move to
4200 larger constants. Add a parameter later. */
4201 offsetT litsize
= 4;
4202 offsetT litalign
= 2; /* 2^2 = 4 */
4203 expressionS saved_loc
;
4204 expressionS
* emit_val
;
4206 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4208 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4209 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4211 xtensa_switch_to_literal_fragment (&state
);
4213 emit_val
= &insn
->tok
[0];
4214 if (emit_val
->X_op
== O_big
)
4216 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4219 /* This happens when someone writes a "movi a2, big_number". */
4220 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4221 _("invalid immediate"));
4222 xtensa_restore_emit_state (&state
);
4227 /* Force a 4-byte align here. Note that this opens a new frag, so all
4228 literals done with this function have a frag to themselves. That's
4229 important for the way text section literals work. */
4230 frag_align (litalign
, 0, 0);
4231 record_alignment (now_seg
, litalign
);
4233 switch (emit_val
->X_op
)
4243 p
= frag_more (litsize
);
4244 xtensa_set_frag_assembly_state (frag_now
);
4245 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4246 if (emit_val
->X_add_symbol
)
4247 emit_val
->X_op
= O_symbol
;
4249 emit_val
->X_op
= O_constant
;
4250 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4251 litsize
, emit_val
, pcrel
, reloc
);
4255 emit_expr (emit_val
, litsize
);
4259 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4260 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4261 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4262 lit_sym
= frag_now
->fr_symbol
;
4265 xtensa_restore_emit_state (&state
);
4271 xg_assemble_literal_space (/* const */ int size
, int slot
)
4274 /* We might have to do something about this alignment. It only
4275 takes effect if something is placed here. */
4276 offsetT litalign
= 2; /* 2^2 = 4 */
4277 fragS
*lit_saved_frag
;
4279 gas_assert (size
% 4 == 0);
4281 xtensa_switch_to_literal_fragment (&state
);
4283 /* Force a 4-byte align here. */
4284 frag_align (litalign
, 0, 0);
4285 record_alignment (now_seg
, litalign
);
4289 lit_saved_frag
= frag_now
;
4290 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4291 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4292 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4295 xtensa_restore_emit_state (&state
);
4296 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4300 /* Put in a fixup record based on the opcode.
4301 Return TRUE on success. */
4304 xg_add_opcode_fix (TInsn
*tinsn
,
4312 xtensa_opcode opcode
= tinsn
->opcode
;
4313 bfd_reloc_code_real_type reloc
;
4314 reloc_howto_type
*howto
;
4318 reloc
= BFD_RELOC_NONE
;
4320 /* First try the special cases for "alternate" relocs. */
4321 if (opcode
== xtensa_l32r_opcode
)
4323 if (fragP
->tc_frag_data
.use_absolute_literals
)
4324 reloc
= encode_alt_reloc (slot
);
4326 else if (opcode
== xtensa_const16_opcode
)
4328 if (exp
->X_op
== O_lo16
)
4330 reloc
= encode_reloc (slot
);
4331 exp
->X_op
= O_symbol
;
4333 else if (exp
->X_op
== O_hi16
)
4335 reloc
= encode_alt_reloc (slot
);
4336 exp
->X_op
= O_symbol
;
4340 if (opnum
!= get_relaxable_immed (opcode
))
4342 as_bad (_("invalid relocation for operand %i of '%s'"),
4343 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4347 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4348 into the symbol table where the generic portions of the assembler
4349 won't know what to do with them. */
4350 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4352 as_bad (_("invalid expression for operand %i of '%s'"),
4353 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4357 /* Next try the generic relocs. */
4358 if (reloc
== BFD_RELOC_NONE
)
4359 reloc
= encode_reloc (slot
);
4360 if (reloc
== BFD_RELOC_NONE
)
4362 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4366 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4369 as_bad (_("undefined symbol for opcode \"%s\""),
4370 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4374 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4375 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4376 howto
->pc_relative
, reloc
);
4377 the_fix
->fx_no_overflow
= 1;
4378 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4379 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4380 the_fix
->tc_fix_data
.slot
= slot
;
4387 xg_emit_insn_to_buf (TInsn
*tinsn
,
4391 bfd_boolean build_fix
)
4393 static xtensa_insnbuf insnbuf
= NULL
;
4394 bfd_boolean has_symbolic_immed
= FALSE
;
4395 bfd_boolean ok
= TRUE
;
4398 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4400 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4401 if (has_symbolic_immed
&& build_fix
)
4404 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4405 int slot
= xg_get_single_slot (tinsn
->opcode
);
4406 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4407 expressionS
*exp
= &tinsn
->tok
[opnum
];
4409 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4412 fragP
->tc_frag_data
.is_insn
= TRUE
;
4413 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4414 (unsigned char *) buf
, 0);
4420 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4422 symbolS
*sym
= get_special_literal_symbol ();
4426 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4427 for (i
= 0; i
< insn
->ntok
; i
++)
4428 if (insn
->tok
[i
].X_add_symbol
== sym
)
4429 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4435 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4437 symbolS
*sym
= get_special_label_symbol ();
4439 for (i
= 0; i
< insn
->ntok
; i
++)
4440 if (insn
->tok
[i
].X_add_symbol
== sym
)
4441 insn
->tok
[i
].X_add_symbol
= label_sym
;
4446 /* Return TRUE if the instruction can write to the specified
4447 integer register. */
4450 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4454 xtensa_isa isa
= xtensa_default_isa
;
4456 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4458 for (i
= 0; i
< num_ops
; i
++)
4461 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4462 if ((inout
== 'o' || inout
== 'm')
4463 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4465 xtensa_regfile opnd_rf
=
4466 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4467 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4469 if ((insn
->tok
[i
].X_op
== O_register
)
4470 && (insn
->tok
[i
].X_add_number
== regnum
))
4480 is_bad_loopend_opcode (const TInsn
*tinsn
)
4482 xtensa_opcode opcode
= tinsn
->opcode
;
4484 if (opcode
== XTENSA_UNDEFINED
)
4487 if (opcode
== xtensa_call0_opcode
4488 || opcode
== xtensa_callx0_opcode
4489 || opcode
== xtensa_call4_opcode
4490 || opcode
== xtensa_callx4_opcode
4491 || opcode
== xtensa_call8_opcode
4492 || opcode
== xtensa_callx8_opcode
4493 || opcode
== xtensa_call12_opcode
4494 || opcode
== xtensa_callx12_opcode
4495 || opcode
== xtensa_isync_opcode
4496 || opcode
== xtensa_ret_opcode
4497 || opcode
== xtensa_ret_n_opcode
4498 || opcode
== xtensa_retw_opcode
4499 || opcode
== xtensa_retw_n_opcode
4500 || opcode
== xtensa_waiti_opcode
4501 || opcode
== xtensa_rsr_lcount_opcode
)
4508 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4509 This allows the debugger to add unaligned labels.
4510 Also, the assembler generates stabs labels that need
4511 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4514 is_unaligned_label (symbolS
*sym
)
4516 const char *name
= S_GET_NAME (sym
);
4517 static size_t fake_size
= 0;
4521 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4524 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4526 fake_size
= strlen (FAKE_LABEL_NAME
);
4529 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4530 && (name
[fake_size
] == 'F'
4531 || name
[fake_size
] == 'L'
4532 || (name
[fake_size
] == 'e'
4533 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4541 next_non_empty_frag (const fragS
*fragP
)
4543 fragS
*next_fragP
= fragP
->fr_next
;
4545 /* Sometimes an empty will end up here due storage allocation issues.
4546 So we have to skip until we find something legit. */
4547 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4548 next_fragP
= next_fragP
->fr_next
;
4550 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4558 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4560 xtensa_opcode out_opcode
;
4561 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4563 if (next_fragP
== NULL
)
4566 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4567 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4569 *opcode
= out_opcode
;
4577 frag_format_size (const fragS
*fragP
)
4579 static xtensa_insnbuf insnbuf
= NULL
;
4580 xtensa_isa isa
= xtensa_default_isa
;
4585 insnbuf
= xtensa_insnbuf_alloc (isa
);
4588 return XTENSA_UNDEFINED
;
4590 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4591 (unsigned char *) fragP
->fr_literal
, 0);
4593 fmt
= xtensa_format_decode (isa
, insnbuf
);
4594 if (fmt
== XTENSA_UNDEFINED
)
4595 return XTENSA_UNDEFINED
;
4596 fmt_size
= xtensa_format_length (isa
, fmt
);
4598 /* If the next format won't be changing due to relaxation, just
4599 return the length of the first format. */
4600 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4603 /* If during relaxation we have to pull an instruction out of a
4604 multi-slot instruction, we will return the more conservative
4605 number. This works because alignment on bigger instructions
4606 is more restrictive than alignment on smaller instructions.
4607 This is more conservative than we would like, but it happens
4610 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4613 /* If we aren't doing one of our own relaxations or it isn't
4614 slot-based, then the insn size won't change. */
4615 if (fragP
->fr_type
!= rs_machine_dependent
)
4617 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4620 /* If an instruction is about to grow, return the longer size. */
4621 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4622 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4623 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4625 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4626 instruction in the relaxed version is of length 3. (The case
4627 where we have to pull the instruction out of a FLIX bundle
4628 is handled conservatively above.) However, frags with opcodes
4629 that are expanding to wide branches end up having formats that
4630 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4631 we can't tell directly what format the relaxer picked. This
4632 is a wart in the design of the relaxer that should someday be
4633 fixed, but would require major changes, or at least should
4634 be accompanied by major changes to make use of that data.
4636 In any event, we can tell that we are expanding from a single-slot
4637 format to a wider one with the logic below. */
4640 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4642 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4644 if (relaxed_size
== xtensa_format_length (isa
, i
))
4645 return relaxed_size
;
4651 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4652 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4659 next_frag_format_size (const fragS
*fragP
)
4661 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4662 return frag_format_size (next_fragP
);
4666 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4667 required two-byte instructions to be treated as three-byte instructions
4668 for loop instruction alignment. This restriction was removed beginning
4669 with Xtensa LX. Now the only requirement on loop instruction alignment
4670 is that the first instruction of the loop must appear at an address that
4671 does not cross a fetch boundary. */
4674 get_loop_align_size (int insn_size
)
4676 if (insn_size
== XTENSA_UNDEFINED
)
4677 return xtensa_fetch_width
;
4679 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4686 /* If the next legit fragment is an end-of-loop marker,
4687 switch its state so it will instantiate a NOP. */
4690 update_next_frag_state (fragS
*fragP
)
4692 fragS
*next_fragP
= fragP
->fr_next
;
4693 fragS
*new_target
= NULL
;
4697 /* We are guaranteed there will be one of these... */
4698 while (!(next_fragP
->fr_type
== rs_machine_dependent
4699 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4700 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4701 next_fragP
= next_fragP
->fr_next
;
4703 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4704 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4705 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4707 /* ...and one of these. */
4708 new_target
= next_fragP
->fr_next
;
4709 while (!(new_target
->fr_type
== rs_machine_dependent
4710 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4711 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4712 new_target
= new_target
->fr_next
;
4714 gas_assert (new_target
->fr_type
== rs_machine_dependent
4715 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4716 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4719 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4721 if (next_fragP
->fr_type
== rs_machine_dependent
4722 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4724 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4728 next_fragP
= next_fragP
->fr_next
;
4734 next_frag_is_branch_target (const fragS
*fragP
)
4736 /* Sometimes an empty will end up here due to storage allocation issues,
4737 so we have to skip until we find something legit. */
4738 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4740 if (fragP
->tc_frag_data
.is_branch_target
)
4742 if (fragP
->fr_fix
!= 0)
4750 next_frag_is_loop_target (const fragS
*fragP
)
4752 /* Sometimes an empty will end up here due storage allocation issues.
4753 So we have to skip until we find something legit. */
4754 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4756 if (fragP
->tc_frag_data
.is_loop_target
)
4758 if (fragP
->fr_fix
!= 0)
4765 /* As specified in the relaxation table, when a loop instruction is
4766 relaxed, there are 24 bytes between the loop instruction itself and
4767 the first instruction in the loop. */
4769 #define RELAXED_LOOP_INSN_BYTES 24
4772 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4774 const fragS
*next_fragp
= fragp
->fr_next
;
4775 xtensa_opcode next_opcode
;
4777 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4780 /* Sometimes an empty will end up here due to storage allocation issues,
4781 so we have to skip until we find something legit. */
4782 while (next_fragp
->fr_fix
== 0)
4783 next_fragp
= next_fragp
->fr_next
;
4785 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4788 /* There is some implicit knowledge encoded in here.
4789 The LOOP instructions that are NOT RELAX_IMMED have
4790 been relaxed. Note that we can assume that the LOOP
4791 instruction is in slot 0 because loops aren't bundleable. */
4792 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4793 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4799 /* Mark a location where we can later insert literal frags. Update
4800 the section's literal_pool_loc, so subsequent literals can be
4801 placed nearest to their use. */
4804 xtensa_mark_literal_pool_location (void)
4806 /* Any labels pointing to the current location need
4807 to be adjusted to after the literal pool. */
4808 fragS
*pool_location
;
4810 if (use_literal_section
)
4813 /* We stash info in these frags so we can later move the literal's
4814 fixes into this frchain's fix list. */
4815 pool_location
= frag_now
;
4816 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4817 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4818 /* Just record this frag. */
4819 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4820 frag_variant (rs_machine_dependent
, 0, 0,
4821 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4822 xtensa_set_frag_assembly_state (frag_now
);
4823 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4824 frag_variant (rs_machine_dependent
, 0, 0,
4825 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4826 xtensa_set_frag_assembly_state (frag_now
);
4828 set_literal_pool_location (now_seg
, pool_location
);
4832 /* Build a nop of the correct size into tinsn. */
4835 build_nop (TInsn
*tinsn
, int size
)
4841 tinsn
->opcode
= xtensa_nop_n_opcode
;
4843 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4844 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4848 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4850 tinsn
->opcode
= xtensa_or_opcode
;
4851 set_expr_const (&tinsn
->tok
[0], 1);
4852 set_expr_const (&tinsn
->tok
[1], 1);
4853 set_expr_const (&tinsn
->tok
[2], 1);
4857 tinsn
->opcode
= xtensa_nop_opcode
;
4859 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4864 /* Assemble a NOP of the requested size in the buffer. User must have
4865 allocated "buf" with at least "size" bytes. */
4868 assemble_nop (int size
, char *buf
)
4870 static xtensa_insnbuf insnbuf
= NULL
;
4873 build_nop (&tinsn
, size
);
4876 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4878 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4879 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4880 (unsigned char *) buf
, 0);
4884 /* Return the number of bytes for the offset of the expanded loop
4885 instruction. This should be incorporated into the relaxation
4886 specification but is hard-coded here. This is used to auto-align
4887 the loop instruction. It is invalid to call this function if the
4888 configuration does not have loops or if the opcode is not a loop
4892 get_expanded_loop_offset (xtensa_opcode opcode
)
4894 /* This is the OFFSET of the loop instruction in the expanded loop.
4895 This MUST correspond directly to the specification of the loop
4896 expansion. It will be validated on fragment conversion. */
4897 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4898 if (opcode
== xtensa_loop_opcode
)
4900 if (opcode
== xtensa_loopnez_opcode
)
4902 if (opcode
== xtensa_loopgtz_opcode
)
4904 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4910 get_literal_pool_location (segT seg
)
4914 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4915 struct litpool_frag
*lpf
;
4916 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4920 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4921 { /* Skip "candidates" for now. */
4922 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4926 /* Must convert a lower-priority pool. */
4927 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4929 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4932 /* Still no match -- try for a low priority pool. */
4933 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4935 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4940 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4945 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4947 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4951 /* Set frag assembly state should be called when a new frag is
4952 opened and after a frag has been closed. */
4955 xtensa_set_frag_assembly_state (fragS
*fragP
)
4957 if (!density_supported
)
4958 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4960 /* This function is called from subsegs_finish, which is called
4961 after xtensa_end, so we can't use "use_transform" or
4962 "use_schedule" here. */
4963 if (!directive_state
[directive_transform
])
4964 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4965 if (directive_state
[directive_longcalls
])
4966 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4967 fragP
->tc_frag_data
.use_absolute_literals
=
4968 directive_state
[directive_absolute_literals
];
4969 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4974 relaxable_section (asection
*sec
)
4976 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4977 && strcmp (sec
->name
, ".eh_frame") != 0);
4982 xtensa_mark_frags_for_org (void)
4986 /* Walk over each fragment of all of the current segments. If we find
4987 a .org frag in any of the segments, mark all frags prior to it as
4988 "no transform", which will prevent linker optimizations from messing
4989 up the .org distance. This should be done after
4990 xtensa_find_unmarked_state_frags, because we don't want to worry here
4991 about that function trashing the data we save here. */
4993 for (seclist
= &stdoutput
->sections
;
4994 seclist
&& *seclist
;
4995 seclist
= &(*seclist
)->next
)
4997 segT sec
= *seclist
;
4998 segment_info_type
*seginfo
;
5001 flags
= bfd_section_flags (sec
);
5002 if (flags
& SEC_DEBUGGING
)
5004 if (!(flags
& SEC_ALLOC
))
5007 seginfo
= seg_info (sec
);
5008 if (seginfo
&& seginfo
->frchainP
)
5010 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
5011 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5012 fragP
= fragP
->fr_next
)
5014 /* cvt_frag_to_fill has changed the fr_type of org frags to
5015 rs_fill, so use the value as cached in rs_subtype here. */
5016 if (fragP
->fr_subtype
== RELAX_ORG
)
5018 while (last_fragP
!= fragP
->fr_next
)
5020 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5021 last_fragP
= last_fragP
->fr_next
;
5031 xtensa_find_unmarked_state_frags (void)
5035 /* Walk over each fragment of all of the current segments. For each
5036 unmarked fragment, mark it with the same info as the previous
5038 for (seclist
= &stdoutput
->sections
;
5039 seclist
&& *seclist
;
5040 seclist
= &(*seclist
)->next
)
5042 segT sec
= *seclist
;
5043 segment_info_type
*seginfo
;
5046 flags
= bfd_section_flags (sec
);
5047 if (flags
& SEC_DEBUGGING
)
5049 if (!(flags
& SEC_ALLOC
))
5052 seginfo
= seg_info (sec
);
5053 if (seginfo
&& seginfo
->frchainP
)
5055 fragS
*last_fragP
= 0;
5056 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5057 fragP
= fragP
->fr_next
)
5059 if (fragP
->fr_fix
!= 0
5060 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5062 if (last_fragP
== 0)
5064 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5065 _("assembly state not set for first frag in section %s"),
5070 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5071 fragP
->tc_frag_data
.is_no_density
=
5072 last_fragP
->tc_frag_data
.is_no_density
;
5073 fragP
->tc_frag_data
.is_no_transform
=
5074 last_fragP
->tc_frag_data
.is_no_transform
;
5075 fragP
->tc_frag_data
.use_longcalls
=
5076 last_fragP
->tc_frag_data
.use_longcalls
;
5077 fragP
->tc_frag_data
.use_absolute_literals
=
5078 last_fragP
->tc_frag_data
.use_absolute_literals
;
5081 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5090 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5092 void *unused ATTRIBUTE_UNUSED
)
5094 flagword flags
= bfd_section_flags (sec
);
5095 segment_info_type
*seginfo
= seg_info (sec
);
5096 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5098 if (flags
& SEC_CODE
)
5100 xtensa_isa isa
= xtensa_default_isa
;
5101 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5102 while (frag
!= NULL
)
5104 if (frag
->tc_frag_data
.is_branch_target
)
5107 addressT branch_align
, frag_addr
;
5110 xtensa_insnbuf_from_chars
5111 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5112 fmt
= xtensa_format_decode (isa
, insnbuf
);
5113 op_size
= xtensa_format_length (isa
, fmt
);
5114 branch_align
= 1 << branch_align_power (sec
);
5115 frag_addr
= frag
->fr_address
% branch_align
;
5116 if (frag_addr
+ op_size
> branch_align
)
5117 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5118 _("unaligned branch target: %d bytes at 0x%lx"),
5119 op_size
, (long) frag
->fr_address
);
5121 frag
= frag
->fr_next
;
5123 xtensa_insnbuf_free (isa
, insnbuf
);
5129 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5131 void *unused ATTRIBUTE_UNUSED
)
5133 flagword flags
= bfd_section_flags (sec
);
5134 segment_info_type
*seginfo
= seg_info (sec
);
5135 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5136 xtensa_isa isa
= xtensa_default_isa
;
5138 if (flags
& SEC_CODE
)
5140 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5141 while (frag
!= NULL
)
5143 if (frag
->tc_frag_data
.is_first_loop_insn
)
5149 if (frag
->fr_fix
== 0)
5150 frag
= next_non_empty_frag (frag
);
5154 xtensa_insnbuf_from_chars
5155 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5156 fmt
= xtensa_format_decode (isa
, insnbuf
);
5157 op_size
= xtensa_format_length (isa
, fmt
);
5158 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5160 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5161 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5162 _("unaligned loop: %d bytes at 0x%lx"),
5163 op_size
, (long) frag
->fr_address
);
5166 frag
= frag
->fr_next
;
5168 xtensa_insnbuf_free (isa
, insnbuf
);
5174 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5176 xtensa_isa isa
= xtensa_default_isa
;
5177 static xtensa_insnbuf insnbuf
= NULL
;
5178 static xtensa_insnbuf slotbuf
= NULL
;
5181 bfd_boolean alt_reloc
;
5182 xtensa_opcode opcode
;
5183 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5185 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5187 as_fatal (_("unexpected fix"));
5191 insnbuf
= xtensa_insnbuf_alloc (isa
);
5192 slotbuf
= xtensa_insnbuf_alloc (isa
);
5195 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5196 fmt
= xtensa_format_decode (isa
, insnbuf
);
5197 if (fmt
== XTENSA_UNDEFINED
)
5198 as_fatal (_("undecodable fix"));
5199 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5200 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5201 if (opcode
== XTENSA_UNDEFINED
)
5202 as_fatal (_("undecodable fix"));
5204 /* CONST16 immediates are not PC-relative, despite the fact that we
5205 reuse the normal PC-relative operand relocations for the low part
5206 of a CONST16 operand. */
5207 if (opcode
== xtensa_const16_opcode
)
5210 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5211 get_relaxable_immed (opcode
), val
,
5212 fixP
->fx_file
, fixP
->fx_line
);
5214 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5215 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5221 /* External Functions and Other GAS Hooks. */
5224 xtensa_target_format (void)
5226 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5231 xtensa_file_arch_init (bfd
*abfd
)
5233 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5238 md_number_to_chars (char *buf
, valueT val
, int n
)
5240 if (target_big_endian
)
5241 number_to_chars_bigendian (buf
, val
, n
);
5243 number_to_chars_littleendian (buf
, val
, n
);
5247 xg_init_global_config (void)
5249 target_big_endian
= XCHAL_HAVE_BE
;
5251 density_supported
= XCHAL_HAVE_DENSITY
;
5252 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5253 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5255 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5256 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5258 microarch_earliest
= XTENSA_MARCH_EARLIEST
;
5262 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5264 xg_init_global_config ();
5267 /* This function is called once, at assembler startup time. It should
5268 set up all the tables, etc. that the MD part of the assembler will
5274 segT current_section
= now_seg
;
5275 int current_subsec
= now_subseg
;
5279 xtensa_default_isa
= xtensa_isa_init (0, 0);
5280 isa
= xtensa_default_isa
;
5282 linkrelax
= opt_linkrelax
;
5284 /* Set up the literal sections. */
5285 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5287 subseg_set (current_section
, current_subsec
);
5289 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5290 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5291 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5292 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5293 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5294 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5295 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5296 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5297 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5298 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5299 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5300 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5301 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5302 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5303 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5304 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5305 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5306 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5307 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5308 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5309 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5310 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5311 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5312 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5313 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5314 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5315 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5316 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5317 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5318 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5319 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5321 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5323 int format_slots
= xtensa_format_num_slots (isa
, i
);
5324 if (format_slots
> config_max_slots
)
5325 config_max_slots
= format_slots
;
5328 xg_init_vinsn (&cur_vinsn
);
5330 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5332 init_op_placement_info_table ();
5334 /* Set up the assembly state. */
5335 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5336 xtensa_set_frag_assembly_state (frag_now
);
5338 if (!use_literal_section
)
5339 xtensa_mark_literal_pool_location ();
5343 /* TC_INIT_FIX_DATA hook */
5346 xtensa_init_fix_data (fixS
*x
)
5348 x
->tc_fix_data
.slot
= 0;
5349 x
->tc_fix_data
.X_add_symbol
= NULL
;
5350 x
->tc_fix_data
.X_add_number
= 0;
5354 /* tc_frob_label hook */
5357 xtensa_frob_label (symbolS
*sym
)
5361 if (cur_vinsn
.inside_bundle
)
5363 as_bad (_("labels are not valid inside bundles"));
5367 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5369 /* Since the label was already attached to a frag associated with the
5370 previous basic block, it now needs to be reset to the current frag. */
5371 symbol_set_frag (sym
, frag_now
);
5372 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5374 if (generating_literals
)
5375 xtensa_add_literal_sym (sym
);
5377 xtensa_add_insn_label (sym
);
5379 if (symbol_get_tc (sym
)->is_loop_target
)
5381 if ((get_last_insn_flags (now_seg
, now_subseg
)
5382 & FLAG_IS_BAD_LOOPEND
) != 0)
5383 as_bad (_("invalid last instruction for a zero-overhead loop"));
5385 xtensa_set_frag_assembly_state (frag_now
);
5386 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5387 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5389 xtensa_set_frag_assembly_state (frag_now
);
5390 xtensa_move_labels (frag_now
, 0);
5393 /* No target aligning in the absolute section. */
5394 if (now_seg
!= absolute_section
5395 && !is_unaligned_label (sym
)
5396 && !generating_literals
)
5398 xtensa_set_frag_assembly_state (frag_now
);
5400 if (do_align_targets ())
5401 frag_var (rs_machine_dependent
, 0, (int) freq
,
5402 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5403 frag_now
->fr_offset
, NULL
);
5405 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5406 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5407 xtensa_set_frag_assembly_state (frag_now
);
5408 xtensa_move_labels (frag_now
, 0);
5411 /* We need to mark the following properties even if we aren't aligning. */
5413 /* If the label is already known to be a branch target, i.e., a
5414 forward branch, mark the frag accordingly. Backward branches
5415 are handled by xg_add_branch_and_loop_targets. */
5416 if (symbol_get_tc (sym
)->is_branch_target
)
5417 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5419 /* Loops only go forward, so they can be identified here. */
5420 if (symbol_get_tc (sym
)->is_loop_target
)
5421 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5423 dwarf2_emit_label (sym
);
5427 /* tc_unrecognized_line hook */
5430 xtensa_unrecognized_line (int ch
)
5435 if (cur_vinsn
.inside_bundle
== 0)
5437 /* PR8110: Cannot emit line number info inside a FLIX bundle
5438 when using --gstabs. Temporarily disable debug info. */
5439 generate_lineno_debug ();
5440 if (debug_type
== DEBUG_STABS
)
5442 xt_saved_debug_type
= debug_type
;
5443 debug_type
= DEBUG_NONE
;
5446 cur_vinsn
.inside_bundle
= 1;
5450 as_bad (_("extra opening brace"));
5456 if (cur_vinsn
.inside_bundle
)
5457 finish_vinsn (&cur_vinsn
);
5460 as_bad (_("extra closing brace"));
5465 as_bad (_("syntax error"));
5472 /* md_flush_pending_output hook */
5475 xtensa_flush_pending_output (void)
5477 /* This line fixes a bug where automatically generated gstabs info
5478 separates a function label from its entry instruction, ending up
5479 with the literal position between the function label and the entry
5480 instruction and crashing code. It only happens with --gstabs and
5481 --text-section-literals, and when several other obscure relaxation
5482 conditions are met. */
5483 if (outputting_stabs_line_debug
)
5486 if (cur_vinsn
.inside_bundle
)
5487 as_bad (_("missing closing brace"));
5489 /* If there is a non-zero instruction fragment, close it. */
5490 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5492 frag_wane (frag_now
);
5494 xtensa_set_frag_assembly_state (frag_now
);
5496 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5498 xtensa_clear_insn_labels ();
5502 /* We had an error while parsing an instruction. The string might look
5503 like this: "insn arg1, arg2 }". If so, we need to see the closing
5504 brace and reset some fields. Otherwise, the vinsn never gets closed
5505 and the num_slots field will grow past the end of the array of slots,
5506 and bad things happen. */
5509 error_reset_cur_vinsn (void)
5511 if (cur_vinsn
.inside_bundle
)
5513 if (*input_line_pointer
== '}'
5514 || *(input_line_pointer
- 1) == '}'
5515 || *(input_line_pointer
- 2) == '}')
5516 xg_clear_vinsn (&cur_vinsn
);
5522 md_assemble (char *str
)
5524 xtensa_isa isa
= xtensa_default_isa
;
5527 bfd_boolean has_underbar
= FALSE
;
5528 char *arg_strings
[MAX_INSN_ARGS
];
5530 TInsn orig_insn
; /* Original instruction from the input. */
5532 tinsn_init (&orig_insn
);
5534 /* Split off the opcode. */
5535 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5536 opname
= xstrndup (str
, opnamelen
);
5538 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5541 as_bad (_("syntax error"));
5545 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5548 /* Check for an underbar prefix. */
5551 has_underbar
= TRUE
;
5555 orig_insn
.insn_type
= ITYPE_INSN
;
5557 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5558 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5560 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5561 extra argument and set the opcode to "CALLXn". */
5562 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5563 && strncasecmp (opname
, "callx", 5) == 0)
5565 unsigned long window_size
;
5568 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5569 if (suffix
!= opname
+ 5
5570 && (window_size
== 0
5573 || window_size
== 12)
5574 && strcasecmp (suffix
, ".tls") == 0)
5576 switch (window_size
)
5578 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5579 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5580 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5581 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5585 as_bad (_("wrong number of operands for '%s'"), opname
);
5588 bfd_reloc_code_real_type reloc
;
5589 char *old_input_line_pointer
;
5590 expressionS
*tok
= &orig_insn
.extra_arg
;
5592 old_input_line_pointer
= input_line_pointer
;
5593 input_line_pointer
= arg_strings
[num_args
- 1];
5596 if (tok
->X_op
== O_symbol
5597 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5598 == BFD_RELOC_XTENSA_TLS_CALL
))
5599 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5601 as_bad (_("bad relocation expression for '%s'"), opname
);
5603 input_line_pointer
= old_input_line_pointer
;
5609 /* Special case: Check for "j.l" pseudo op. */
5610 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5611 && strncasecmp (opname
, "j.l", 3) == 0)
5614 as_bad (_("wrong number of operands for '%s'"), opname
);
5617 char *old_input_line_pointer
;
5618 expressionS
*tok
= &orig_insn
.extra_arg
;
5620 old_input_line_pointer
= input_line_pointer
;
5621 input_line_pointer
= arg_strings
[num_args
- 1];
5623 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5624 input_line_pointer
= old_input_line_pointer
;
5627 orig_insn
.opcode
= xtensa_j_opcode
;
5631 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5633 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5634 if (fmt
== XTENSA_UNDEFINED
)
5636 as_bad (_("unknown opcode or format name '%s'"), opname
);
5637 error_reset_cur_vinsn ();
5640 if (!cur_vinsn
.inside_bundle
)
5642 as_bad (_("format names only valid inside bundles"));
5643 error_reset_cur_vinsn ();
5646 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5647 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5649 cur_vinsn
.format
= fmt
;
5650 free (has_underbar
? opname
- 1 : opname
);
5651 error_reset_cur_vinsn ();
5655 /* Parse the arguments. */
5656 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5658 as_bad (_("syntax error"));
5659 error_reset_cur_vinsn ();
5663 /* Free the opcode and argument strings, now that they've been parsed. */
5664 free (has_underbar
? opname
- 1 : opname
);
5666 while (num_args
-- > 0)
5667 free (arg_strings
[num_args
]);
5669 /* Get expressions for invisible operands. */
5670 if (get_invisible_operands (&orig_insn
))
5672 error_reset_cur_vinsn ();
5676 /* Check for the right number and type of arguments. */
5677 if (tinsn_check_arguments (&orig_insn
))
5679 error_reset_cur_vinsn ();
5683 /* Record the line number for each TInsn, because a FLIX bundle may be
5684 spread across multiple input lines and individual instructions may be
5685 moved around in some cases. */
5686 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5687 dwarf2_where (&orig_insn
.debug_line
);
5688 dwarf2_consume_line_info ();
5690 xg_add_branch_and_loop_targets (&orig_insn
);
5692 /* Check that immediate value for ENTRY is >= 16. */
5693 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5695 expressionS
*exp
= &orig_insn
.tok
[2];
5696 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5697 as_warn (_("entry instruction with stack decrement < 16"));
5701 assemble_tokens (opcode, tok, ntok);
5702 expand the tokens from the orig_insn into the
5703 stack of instructions that will not expand
5704 unless required at relaxation time. */
5706 if (!cur_vinsn
.inside_bundle
)
5707 emit_single_op (&orig_insn
);
5708 else /* We are inside a bundle. */
5710 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5711 cur_vinsn
.num_slots
++;
5712 if (*input_line_pointer
== '}'
5713 || *(input_line_pointer
- 1) == '}'
5714 || *(input_line_pointer
- 2) == '}')
5715 finish_vinsn (&cur_vinsn
);
5718 /* We've just emitted a new instruction so clear the list of labels. */
5719 xtensa_clear_insn_labels ();
5721 xtensa_check_frag_count ();
5725 /* HANDLE_ALIGN hook */
5727 /* For a .align directive, we mark the previous block with the alignment
5728 information. This will be placed in the object file in the
5729 property section corresponding to this section. */
5732 xtensa_handle_align (fragS
*fragP
)
5735 && ! fragP
->tc_frag_data
.is_literal
5736 && (fragP
->fr_type
== rs_align
5737 || fragP
->fr_type
== rs_align_code
)
5738 && fragP
->fr_offset
> 0
5739 && now_seg
!= bss_section
)
5741 fragP
->tc_frag_data
.is_align
= TRUE
;
5742 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5745 if (fragP
->fr_type
== rs_align_test
)
5748 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5750 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5751 _("unaligned entry instruction"));
5754 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5755 fragP
->fr_subtype
= RELAX_ORG
;
5759 /* TC_FRAG_INIT hook */
5762 xtensa_frag_init (fragS
*frag
)
5764 xtensa_set_frag_assembly_state (frag
);
5769 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5775 /* Round up a section size to the appropriate boundary. */
5778 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5780 return size
; /* Byte alignment is fine. */
5785 md_pcrel_from (fixS
*fixP
)
5788 static xtensa_insnbuf insnbuf
= NULL
;
5789 static xtensa_insnbuf slotbuf
= NULL
;
5792 xtensa_opcode opcode
;
5795 xtensa_isa isa
= xtensa_default_isa
;
5796 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5797 bfd_boolean alt_reloc
;
5799 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5802 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5807 insnbuf
= xtensa_insnbuf_alloc (isa
);
5808 slotbuf
= xtensa_insnbuf_alloc (isa
);
5811 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5812 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5813 fmt
= xtensa_format_decode (isa
, insnbuf
);
5815 if (fmt
== XTENSA_UNDEFINED
)
5816 as_fatal (_("bad instruction format"));
5818 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5819 as_fatal (_("invalid relocation"));
5821 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5822 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5824 /* Check for "alternate" relocations (operand not specified). None
5825 of the current uses for these are really PC-relative. */
5826 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5828 if (opcode
!= xtensa_l32r_opcode
5829 && opcode
!= xtensa_const16_opcode
)
5830 as_fatal (_("invalid relocation for '%s' instruction"),
5831 xtensa_opcode_name (isa
, opcode
));
5835 opnum
= get_relaxable_immed (opcode
);
5837 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5838 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5840 as_bad_where (fixP
->fx_file
,
5842 _("invalid relocation for operand %d of '%s'"),
5843 opnum
, xtensa_opcode_name (isa
, opcode
));
5846 return 0 - opnd_value
;
5850 /* TC_FORCE_RELOCATION hook */
5853 xtensa_force_relocation (fixS
*fix
)
5855 switch (fix
->fx_r_type
)
5857 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5858 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5859 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5860 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5861 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5862 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5863 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5864 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5865 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5866 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5867 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5868 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5869 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5870 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5871 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5872 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5878 if (linkrelax
&& fix
->fx_addsy
5879 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5882 return generic_force_reloc (fix
);
5886 /* TC_VALIDATE_FIX_SUB hook */
5889 xtensa_validate_fix_sub (fixS
*fix
)
5891 segT add_symbol_segment
, sub_symbol_segment
;
5893 /* The difference of two symbols should be resolved by the assembler when
5894 linkrelax is not set. If the linker may relax the section containing
5895 the symbols, then an Xtensa DIFF relocation must be generated so that
5896 the linker knows to adjust the difference value. */
5897 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5900 /* Make sure both symbols are in the same segment, and that segment is
5901 "normal" and relaxable. If the segment is not "normal", then the
5902 fix is not valid. If the segment is not "relaxable", then the fix
5903 should have been handled earlier. */
5904 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5905 if (! SEG_NORMAL (add_symbol_segment
) ||
5906 ! relaxable_section (add_symbol_segment
))
5908 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5909 return (sub_symbol_segment
== add_symbol_segment
);
5913 /* NO_PSEUDO_DOT hook */
5915 /* This function has nothing to do with pseudo dots, but this is the
5916 nearest macro to where the check needs to take place. FIXME: This
5920 xtensa_check_inside_bundle (void)
5922 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5923 as_bad (_("directives are not valid inside bundles"));
5925 /* This function must always return FALSE because it is called via a
5926 macro that has nothing to do with bundling. */
5931 /* md_elf_section_change_hook */
5934 xtensa_elf_section_change_hook (void)
5936 /* Set up the assembly state. */
5937 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5938 xtensa_set_frag_assembly_state (frag_now
);
5940 if (!use_literal_section
5941 && seg_info (now_seg
)->tc_segment_info_data
.literal_pool_loc
== NULL
5942 && !xtensa_is_init_fini (now_seg
))
5943 xtensa_mark_literal_pool_location ();
5947 /* tc_fix_adjustable hook */
5950 xtensa_fix_adjustable (fixS
*fixP
)
5952 /* We need the symbol name for the VTABLE entries. */
5953 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5954 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5961 /* tc_symbol_new_hook */
5963 symbolS
*expr_symbols
= NULL
;
5966 xtensa_symbol_new_hook (symbolS
*sym
)
5968 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5970 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5977 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5979 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5982 /* Subtracted symbols are only allowed for a few relocation types, and
5983 unless linkrelax is enabled, they should not make it to this point. */
5984 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5985 || fixP
->fx_r_type
== BFD_RELOC_16
5986 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5989 switch (fixP
->fx_r_type
)
5991 case BFD_RELOC_32_PCREL
:
5997 bfd_boolean neg
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5998 < S_GET_VALUE (fixP
->fx_subsy
);
6000 switch (fixP
->fx_r_type
)
6003 fixP
->fx_r_type
= neg
6004 ? BFD_RELOC_XTENSA_NDIFF8
: BFD_RELOC_XTENSA_PDIFF8
;
6005 fixP
->fx_signed
= 0;
6008 fixP
->fx_r_type
= neg
6009 ? BFD_RELOC_XTENSA_NDIFF16
: BFD_RELOC_XTENSA_PDIFF16
;
6010 fixP
->fx_signed
= 0;
6013 fixP
->fx_r_type
= neg
6014 ? BFD_RELOC_XTENSA_NDIFF32
: BFD_RELOC_XTENSA_PDIFF32
;
6015 fixP
->fx_signed
= 0;
6021 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6022 - S_GET_VALUE (fixP
->fx_subsy
));
6024 /* The difference value gets written out, and the DIFF reloc
6025 identifies the address of the subtracted symbol (i.e., the one
6026 with the lowest address). */
6028 fixP
->fx_offset
-= val
;
6029 fixP
->fx_subsy
= NULL
;
6031 else if (! fixP
->fx_addsy
)
6036 else if (S_GET_SEGMENT (fixP
->fx_addsy
) == absolute_section
)
6038 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
6044 case BFD_RELOC_XTENSA_PLT
:
6045 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
6046 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6049 case BFD_RELOC_XTENSA_TLSDESC_FN
:
6050 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6051 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6052 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6053 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6054 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6055 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6058 case BFD_RELOC_XTENSA_SLOT0_OP
:
6059 case BFD_RELOC_XTENSA_SLOT1_OP
:
6060 case BFD_RELOC_XTENSA_SLOT2_OP
:
6061 case BFD_RELOC_XTENSA_SLOT3_OP
:
6062 case BFD_RELOC_XTENSA_SLOT4_OP
:
6063 case BFD_RELOC_XTENSA_SLOT5_OP
:
6064 case BFD_RELOC_XTENSA_SLOT6_OP
:
6065 case BFD_RELOC_XTENSA_SLOT7_OP
:
6066 case BFD_RELOC_XTENSA_SLOT8_OP
:
6067 case BFD_RELOC_XTENSA_SLOT9_OP
:
6068 case BFD_RELOC_XTENSA_SLOT10_OP
:
6069 case BFD_RELOC_XTENSA_SLOT11_OP
:
6070 case BFD_RELOC_XTENSA_SLOT12_OP
:
6071 case BFD_RELOC_XTENSA_SLOT13_OP
:
6072 case BFD_RELOC_XTENSA_SLOT14_OP
:
6075 /* Write the tentative value of a PC-relative relocation to a
6076 local symbol into the instruction. The value will be ignored
6077 by the linker, and it makes the object file disassembly
6078 readable when all branch targets are encoded in relocations. */
6080 gas_assert (fixP
->fx_addsy
);
6081 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6082 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6084 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6085 - md_pcrel_from (fixP
));
6086 (void) xg_apply_fix_value (fixP
, val
);
6089 else if (! fixP
->fx_addsy
)
6092 if (xg_apply_fix_value (fixP
, val
))
6097 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6098 case BFD_RELOC_XTENSA_TLS_FUNC
:
6099 case BFD_RELOC_XTENSA_TLS_ARG
:
6100 case BFD_RELOC_XTENSA_TLS_CALL
:
6101 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6102 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6103 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6104 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6105 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6106 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6107 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6108 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6109 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6110 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6111 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6112 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6113 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6114 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6115 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6116 /* These all need to be resolved at link-time. Do nothing now. */
6119 case BFD_RELOC_VTABLE_INHERIT
:
6120 case BFD_RELOC_VTABLE_ENTRY
:
6125 as_bad (_("unhandled local relocation fix %s"),
6126 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6132 md_atof (int type
, char *litP
, int *sizeP
)
6134 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6139 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6141 return total_frag_text_expansion (fragP
);
6145 /* Translate internal representation of relocation info to BFD target
6149 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6153 reloc
= XNEW (arelent
);
6154 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6155 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6156 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6158 /* Make sure none of our internal relocations make it this far.
6159 They'd better have been fully resolved by this point. */
6160 gas_assert ((int) fixp
->fx_r_type
> 0);
6162 reloc
->addend
= fixp
->fx_offset
;
6164 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6165 if (reloc
->howto
== NULL
)
6167 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6168 _("cannot represent `%s' relocation in object file"),
6169 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6170 free (reloc
->sym_ptr_ptr
);
6175 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6176 as_fatal (_("internal error; cannot generate `%s' relocation"),
6177 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6183 /* Checks for resource conflicts between instructions. */
6185 /* The func unit stuff could be implemented as bit-vectors rather
6186 than the iterative approach here. If it ends up being too
6187 slow, we will switch it. */
6190 new_resource_table (void *data
,
6193 unit_num_copies_func uncf
,
6194 opcode_num_units_func onuf
,
6195 opcode_funcUnit_use_unit_func ouuf
,
6196 opcode_funcUnit_use_stage_func ousf
)
6199 resource_table
*rt
= XNEW (resource_table
);
6201 rt
->cycles
= cycles
;
6202 rt
->allocated_cycles
= cycles
;
6204 rt
->unit_num_copies
= uncf
;
6205 rt
->opcode_num_units
= onuf
;
6206 rt
->opcode_unit_use
= ouuf
;
6207 rt
->opcode_unit_stage
= ousf
;
6209 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6210 for (i
= 0; i
< cycles
; i
++)
6211 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6218 clear_resource_table (resource_table
*rt
)
6221 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6222 for (j
= 0; j
< rt
->num_units
; j
++)
6223 rt
->units
[i
][j
] = 0;
6227 /* We never shrink it, just fake it into thinking so. */
6230 resize_resource_table (resource_table
*rt
, int cycles
)
6234 rt
->cycles
= cycles
;
6235 if (cycles
<= rt
->allocated_cycles
)
6238 old_cycles
= rt
->allocated_cycles
;
6239 rt
->allocated_cycles
= cycles
;
6241 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6242 for (i
= 0; i
< old_cycles
; i
++)
6243 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6244 for (i
= old_cycles
; i
< cycles
; i
++)
6245 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6250 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6253 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6255 for (i
= 0; i
< uses
; i
++)
6257 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6258 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6259 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6260 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6261 if (copies_in_use
>= copies
)
6269 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6272 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6274 for (i
= 0; i
< uses
; i
++)
6276 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6277 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6278 /* Note that this allows resources to be oversubscribed. That's
6279 essential to the way the optional scheduler works.
6280 resources_available reports when a resource is over-subscribed,
6281 so it's easy to tell. */
6282 rt
->units
[stage
+ cycle
][unit
]++;
6288 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6291 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6293 for (i
= 0; i
< uses
; i
++)
6295 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6296 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6297 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6298 rt
->units
[stage
+ cycle
][unit
]--;
6303 /* Wrapper functions make parameterized resource reservation
6307 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6309 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6315 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6317 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6322 /* Note that this function does not check issue constraints, but
6323 solely whether the hardware is available to execute the given
6324 instructions together. It also doesn't check if the tinsns
6325 write the same state, or access the same tieports. That is
6326 checked by check_t1_t2_reads_and_writes. */
6329 resources_conflict (vliw_insn
*vinsn
)
6332 static resource_table
*rt
= NULL
;
6334 /* This is the most common case by far. Optimize it. */
6335 if (vinsn
->num_slots
== 1)
6340 xtensa_isa isa
= xtensa_default_isa
;
6341 rt
= new_resource_table
6342 (isa
, xtensa_num_pipe_stages
,
6343 xtensa_isa_num_funcUnits (isa
),
6344 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6345 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6346 opcode_funcUnit_use_unit
,
6347 opcode_funcUnit_use_stage
);
6350 clear_resource_table (rt
);
6352 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6354 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6356 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6363 /* finish_vinsn, emit_single_op and helper functions. */
6365 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6366 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6367 static void xg_assemble_vliw_tokens (vliw_insn
*);
6370 /* We have reached the end of a bundle; emit into the frag. */
6373 finish_vinsn (vliw_insn
*vinsn
)
6379 if (find_vinsn_conflicts (vinsn
))
6381 xg_clear_vinsn (vinsn
);
6385 /* First, find a format that works. */
6386 if (vinsn
->format
== XTENSA_UNDEFINED
)
6387 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6389 slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6391 && produce_flix
== FLIX_NONE
)
6393 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6394 xg_clear_vinsn (vinsn
);
6398 if (vinsn
->format
== XTENSA_UNDEFINED
)
6400 as_bad (_("couldn't find a valid instruction format"));
6401 fprintf (stderr
, _(" ops were: "));
6402 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6403 fprintf (stderr
, _(" %s;"),
6404 xtensa_opcode_name (xtensa_default_isa
,
6405 vinsn
->slots
[i
].opcode
));
6406 fprintf (stderr
, _("\n"));
6407 xg_clear_vinsn (vinsn
);
6411 if (vinsn
->num_slots
!= slots
)
6413 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6414 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6415 slots
, vinsn
->num_slots
);
6416 xg_clear_vinsn (vinsn
);
6420 if (resources_conflict (vinsn
))
6422 as_bad (_("illegal resource usage in bundle"));
6423 fprintf (stderr
, " ops were: ");
6424 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6425 fprintf (stderr
, " %s;",
6426 xtensa_opcode_name (xtensa_default_isa
,
6427 vinsn
->slots
[i
].opcode
));
6428 fprintf (stderr
, "\n");
6429 xg_clear_vinsn (vinsn
);
6433 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6435 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6437 symbolS
*lit_sym
= NULL
;
6439 bfd_boolean e
= FALSE
;
6440 bfd_boolean saved_density
= density_supported
;
6442 /* We don't want to narrow ops inside multi-slot bundles. */
6443 if (vinsn
->num_slots
> 1)
6444 density_supported
= FALSE
;
6446 istack_init (&slotstack
);
6447 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6449 vinsn
->slots
[i
].opcode
=
6450 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6452 vinsn
->slots
[i
].ntok
= 0;
6455 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6461 density_supported
= saved_density
;
6465 xg_clear_vinsn (vinsn
);
6469 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6471 TInsn
*insn
= &slotstack
.insn
[j
];
6472 if (insn
->insn_type
== ITYPE_LITERAL
)
6474 gas_assert (lit_sym
== NULL
);
6475 lit_sym
= xg_assemble_literal (insn
);
6479 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6481 xg_resolve_literals (insn
, lit_sym
);
6482 if (j
!= slotstack
.ninsn
- 1)
6483 emit_single_op (insn
);
6487 if (vinsn
->num_slots
> 1)
6489 if (opcode_fits_format_slot
6490 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6493 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6497 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6498 if (vinsn
->format
== XTENSA_UNDEFINED
)
6499 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6501 vinsn
->slots
[i
].opcode
6502 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6505 vinsn
->slots
[i
].ntok
= 0;
6510 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6511 vinsn
->format
= XTENSA_UNDEFINED
;
6516 /* Now check resource conflicts on the modified bundle. */
6517 if (resources_conflict (vinsn
))
6519 as_bad (_("illegal resource usage in bundle"));
6520 fprintf (stderr
, " ops were: ");
6521 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6522 fprintf (stderr
, " %s;",
6523 xtensa_opcode_name (xtensa_default_isa
,
6524 vinsn
->slots
[i
].opcode
));
6525 fprintf (stderr
, "\n");
6526 xg_clear_vinsn (vinsn
);
6530 /* First, find a format that works. */
6531 if (vinsn
->format
== XTENSA_UNDEFINED
)
6532 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6534 xg_assemble_vliw_tokens (vinsn
);
6536 xg_clear_vinsn (vinsn
);
6538 xtensa_check_frag_count ();
6542 /* Given an vliw instruction, what conflicts are there in register
6543 usage and in writes to states and queues?
6545 This function does two things:
6546 1. Reports an error when a vinsn contains illegal combinations
6547 of writes to registers states or queues.
6548 2. Marks individual tinsns as not relaxable if the combination
6549 contains antidependencies.
6551 Job 2 handles things like swap semantics in instructions that need
6552 to be relaxed. For example,
6556 normally would be relaxed to
6561 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6563 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6565 then we can't relax it into
6568 { add a0, a1, a0 ; add a2, a0, a4 ; }
6570 because the value of a0 is trashed before the second add can read it. */
6572 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6575 find_vinsn_conflicts (vliw_insn
*vinsn
)
6579 xtensa_isa isa
= xtensa_default_isa
;
6581 gas_assert (!past_xtensa_end
);
6583 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6585 TInsn
*op1
= &vinsn
->slots
[i
];
6586 if (op1
->is_specific_opcode
)
6587 op1
->keep_wide
= TRUE
;
6589 op1
->keep_wide
= FALSE
;
6592 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6594 TInsn
*op1
= &vinsn
->slots
[i
];
6596 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6599 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6603 TInsn
*op2
= &vinsn
->slots
[j
];
6604 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6605 switch (conflict_type
)
6608 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6609 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6610 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6613 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6614 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6615 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6618 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6619 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6620 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6623 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6624 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6625 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6628 /* Everything is OK. */
6631 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6632 || conflict_type
== 'a');
6639 as_bad (_("multiple branches or jumps in the same bundle"));
6647 /* Check how the state used by t1 and t2 relate.
6650 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6651 case B: no relationship between what is read and written (both could
6652 read the same reg though)
6653 case C: t1 writes a register t2 writes (a register conflict within a
6655 case D: t1 writes a state that t2 also writes
6656 case E: t1 writes a tie queue that t2 also writes
6657 case F: two volatile queue accesses
6661 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6663 xtensa_isa isa
= xtensa_default_isa
;
6664 xtensa_regfile t1_regfile
, t2_regfile
;
6666 int t1_base_reg
, t1_last_reg
;
6667 int t2_base_reg
, t2_last_reg
;
6668 char t1_inout
, t2_inout
;
6670 char conflict
= 'b';
6675 bfd_boolean t1_volatile
= FALSE
;
6676 bfd_boolean t2_volatile
= FALSE
;
6678 /* Check registers. */
6679 for (j
= 0; j
< t2
->ntok
; j
++)
6681 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6684 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6685 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6686 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6688 for (i
= 0; i
< t1
->ntok
; i
++)
6690 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6693 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6695 if (t1_regfile
!= t2_regfile
)
6698 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6699 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6701 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6702 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6704 if (t1_inout
== 'm' || t1_inout
== 'o'
6705 || t2_inout
== 'm' || t2_inout
== 'o')
6712 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6713 t1_last_reg
= (t1_base_reg
6714 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6716 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6718 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6720 if (t1_reg
!= t2_reg
)
6723 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6729 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6735 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6743 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6744 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6745 for (j
= 0; j
< t2_states
; j
++)
6747 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6748 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6749 for (i
= 0; i
< t1_states
; i
++)
6751 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6752 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6753 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6756 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6762 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6768 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6773 /* Check tieports. */
6774 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6775 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6776 for (j
= 0; j
< t2_interfaces
; j
++)
6778 xtensa_interface t2_int
6779 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6780 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6782 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6783 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6786 for (i
= 0; i
< t1_interfaces
; i
++)
6788 xtensa_interface t1_int
6789 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6790 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6792 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6793 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6796 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6799 if (t1_int
!= t2_int
)
6802 if (t2_inout
== 'i' && t1_inout
== 'o')
6808 if (t1_inout
== 'i' && t2_inout
== 'o')
6814 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6823 static xtensa_format
6824 xg_find_narrowest_format (vliw_insn
*vinsn
)
6826 /* Right now we assume that the ops within the vinsn are properly
6827 ordered for the slots that the programmer wanted them in. In
6828 other words, we don't rearrange the ops in hopes of finding a
6829 better format. The scheduler handles that. */
6831 xtensa_isa isa
= xtensa_default_isa
;
6832 xtensa_format format
;
6833 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6835 if (vinsn
->num_slots
== 1)
6836 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6838 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6841 xg_copy_vinsn (&v_copy
, vinsn
);
6842 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6846 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6848 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6850 v_copy
.slots
[slot
].opcode
=
6851 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6852 v_copy
.slots
[slot
].ntok
= 0;
6855 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6858 else if (v_copy
.num_slots
> 1)
6861 /* Try the widened version. */
6862 if (!v_copy
.slots
[slot
].keep_wide
6863 && !v_copy
.slots
[slot
].is_specific_opcode
6864 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6866 && opcode_fits_format_slot (widened
.opcode
,
6869 v_copy
.slots
[slot
] = widened
;
6874 if (fit
== v_copy
.num_slots
)
6876 xg_copy_vinsn (vinsn
, &v_copy
);
6877 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6878 vinsn
->format
= format
;
6884 if (format
== xtensa_isa_num_formats (isa
))
6885 return XTENSA_UNDEFINED
;
6891 /* Return the additional space needed in a frag
6892 for possible relaxations of any ops in a VLIW insn.
6893 Also fill out the relaxations that might be required of
6894 each tinsn in the vinsn. */
6897 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6899 bfd_boolean finish_frag
= FALSE
;
6900 int extra_space
= 0;
6903 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6905 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6906 if (!tinsn_has_symbolic_operands (tinsn
))
6908 /* A narrow instruction could be widened later to help
6909 alignment issues. */
6910 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6911 && !tinsn
->is_specific_opcode
6912 && vinsn
->num_slots
== 1)
6914 /* Difference in bytes between narrow and wide insns... */
6916 tinsn
->subtype
= RELAX_NARROW
;
6921 if (workaround_b_j_loop_end
6922 && tinsn
->opcode
== xtensa_jx_opcode
6923 && use_transform ())
6925 /* Add 2 of these. */
6926 extra_space
+= 3; /* for the nop size */
6927 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6930 /* Need to assemble it with space for the relocation. */
6931 if (xg_is_relaxable_insn (tinsn
, 0)
6932 && !tinsn
->is_specific_opcode
)
6934 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6935 int max_literal_size
=
6936 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6938 tinsn
->literal_space
= max_literal_size
;
6940 tinsn
->subtype
= RELAX_IMMED
;
6941 extra_space
+= max_size
;
6945 /* A fix record will be added for this instruction prior
6946 to relaxation, so make it end the frag. */
6951 *pfinish_frag
= finish_frag
;
6957 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6959 xtensa_isa isa
= xtensa_default_isa
;
6960 int slot
, chosen_slot
;
6962 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6963 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6964 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6966 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6967 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6969 if (slot
== chosen_slot
)
6970 vinsn
->slots
[slot
] = *tinsn
;
6973 vinsn
->slots
[slot
].opcode
=
6974 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6975 vinsn
->slots
[slot
].ntok
= 0;
6976 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6983 emit_single_op (TInsn
*orig_insn
)
6986 IStack istack
; /* put instructions into here */
6987 symbolS
*lit_sym
= NULL
;
6988 symbolS
*label_sym
= NULL
;
6990 istack_init (&istack
);
6992 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6993 Because the scheduling and bundling characteristics of movi and
6994 l32r or const16 are so different, we can do much better if we relax
6995 it prior to scheduling and bundling, rather than after. */
6996 if ((orig_insn
->opcode
== xtensa_movi_opcode
6997 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6998 && !cur_vinsn
.inside_bundle
6999 && (orig_insn
->tok
[1].X_op
== O_symbol
7000 || orig_insn
->tok
[1].X_op
== O_pltrel
7001 || orig_insn
->tok
[1].X_op
== O_tlsfunc
7002 || orig_insn
->tok
[1].X_op
== O_tlsarg
7003 || orig_insn
->tok
[1].X_op
== O_tpoff
7004 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
7005 && !orig_insn
->is_specific_opcode
&& use_transform ())
7006 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
7008 if (xg_expand_assembly_insn (&istack
, orig_insn
))
7011 for (i
= 0; i
< istack
.ninsn
; i
++)
7013 TInsn
*insn
= &istack
.insn
[i
];
7014 switch (insn
->insn_type
)
7017 gas_assert (lit_sym
== NULL
);
7018 lit_sym
= xg_assemble_literal (insn
);
7022 static int relaxed_sym_idx
= 0;
7023 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
7024 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
7026 gas_assert (label_sym
== NULL
);
7027 label_sym
= symbol_find_or_make (label
);
7028 gas_assert (label_sym
);
7036 xg_resolve_literals (insn
, lit_sym
);
7038 xg_resolve_labels (insn
, label_sym
);
7040 bundle_tinsn (insn
, &v
);
7055 total_frag_text_expansion (fragS
*fragP
)
7058 int total_expansion
= 0;
7060 for (slot
= 0; slot
< config_max_slots
; slot
++)
7061 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7063 return total_expansion
;
7067 /* Emit a vliw instruction to the current fragment. */
7070 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7072 bfd_boolean finish_frag
;
7073 bfd_boolean is_jump
= FALSE
;
7074 bfd_boolean is_branch
= FALSE
;
7075 xtensa_isa isa
= xtensa_default_isa
;
7080 struct dwarf2_line_info debug_line
;
7081 bfd_boolean loc_directive_seen
= FALSE
;
7084 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7086 if (generating_literals
)
7088 static int reported
= 0;
7090 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7091 _("cannot assemble into a literal fragment"));
7098 if (frag_now_fix () != 0
7099 && (! frag_now
->tc_frag_data
.is_insn
7100 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7101 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7102 || (directive_state
[directive_longcalls
]
7103 != frag_now
->tc_frag_data
.use_longcalls
)
7104 || (directive_state
[directive_absolute_literals
]
7105 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7107 frag_wane (frag_now
);
7109 xtensa_set_frag_assembly_state (frag_now
);
7112 if (workaround_a0_b_retw
7113 && vinsn
->num_slots
== 1
7114 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7115 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7116 && use_transform ())
7118 has_a0_b_retw
= TRUE
;
7120 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7121 After the first assembly pass we will check all of them and
7122 add a nop if needed. */
7123 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7124 frag_var (rs_machine_dependent
, 4, 4,
7125 RELAX_ADD_NOP_IF_A0_B_RETW
,
7126 frag_now
->fr_symbol
,
7127 frag_now
->fr_offset
,
7129 xtensa_set_frag_assembly_state (frag_now
);
7130 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7131 frag_var (rs_machine_dependent
, 4, 4,
7132 RELAX_ADD_NOP_IF_A0_B_RETW
,
7133 frag_now
->fr_symbol
,
7134 frag_now
->fr_offset
,
7136 xtensa_set_frag_assembly_state (frag_now
);
7139 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7141 tinsn
= &vinsn
->slots
[slot
];
7143 /* See if the instruction implies an aligned section. */
7144 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7145 record_alignment (now_seg
, 2);
7147 /* Determine the best line number for debug info. */
7148 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7149 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7150 || tinsn
->debug_line
.line
< debug_line
.line
7151 || tinsn
->debug_line
.column
< debug_line
.column
))
7152 debug_line
= tinsn
->debug_line
;
7153 if (tinsn
->loc_directive_seen
)
7154 loc_directive_seen
= TRUE
;
7157 /* Special cases for instructions that force an alignment... */
7158 /* None of these opcodes are bundle-able. */
7159 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7163 /* Remember the symbol that marks the end of the loop in the frag
7164 that marks the start of the loop. This way we can easily find
7165 the end of the loop at the beginning, without adding special code
7166 to mark the loop instructions themselves. */
7167 symbolS
*target_sym
= NULL
;
7168 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7169 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7171 xtensa_set_frag_assembly_state (frag_now
);
7172 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7174 max_fill
= get_text_align_max_fill_size
7175 (get_text_align_power (xtensa_fetch_width
),
7176 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7178 if (use_transform ())
7179 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7180 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7182 frag_var (rs_machine_dependent
, 0, 0,
7183 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7184 xtensa_set_frag_assembly_state (frag_now
);
7187 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7188 && !vinsn
->slots
[0].is_specific_opcode
)
7190 xtensa_mark_literal_pool_location ();
7191 xtensa_move_labels (frag_now
, 0);
7192 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7195 if (vinsn
->num_slots
== 1)
7197 if (workaround_a0_b_retw
&& use_transform ())
7198 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7199 is_register_writer (&vinsn
->slots
[0], "a", 0));
7201 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7202 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7205 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7207 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7209 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7211 /* vinsn_to_insnbuf will produce the error. */
7212 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7214 f
= frag_more (insn_size
+ extra_space
);
7215 xtensa_set_frag_assembly_state (frag_now
);
7216 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7219 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7220 if (vinsn
->format
== XTENSA_UNDEFINED
)
7223 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7225 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7226 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7229 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7231 tinsn
= &vinsn
->slots
[slot
];
7232 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7233 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7234 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7235 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7236 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7237 frag_now
->tc_frag_data
.literal_frags
[slot
]
7238 = symbol_get_frag (tinsn
->tok
[1].X_add_symbol
);
7239 if (tinsn
->literal_space
!= 0)
7240 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7241 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7243 if (tinsn
->subtype
== RELAX_NARROW
)
7244 gas_assert (vinsn
->num_slots
== 1);
7245 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7247 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7250 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7251 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7255 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7256 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7260 frag_variant (rs_machine_dependent
,
7261 extra_space
, extra_space
, RELAX_SLOTS
,
7262 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7263 xtensa_set_frag_assembly_state (frag_now
);
7266 /* Special cases for loops:
7267 close_loop_end should be inserted AFTER short_loop.
7268 Make sure that CLOSE loops are processed BEFORE short_loops
7269 when converting them. */
7271 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7272 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7273 && !vinsn
->slots
[0].is_specific_opcode
)
7275 if (workaround_short_loop
&& use_transform ())
7277 maybe_has_short_loop
= TRUE
;
7278 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7279 frag_var (rs_machine_dependent
, 4, 4,
7280 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7281 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7282 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7283 frag_var (rs_machine_dependent
, 4, 4,
7284 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7285 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7288 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7289 loop at least 12 bytes away from another loop's end. */
7290 if (workaround_close_loop_end
&& use_transform ())
7292 maybe_has_close_loop_end
= TRUE
;
7293 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7294 frag_var (rs_machine_dependent
, 12, 12,
7295 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7296 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7300 if (use_transform ())
7304 gas_assert (finish_frag
);
7305 frag_var (rs_machine_dependent
,
7306 xtensa_fetch_width
, xtensa_fetch_width
,
7308 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7309 xtensa_set_frag_assembly_state (frag_now
);
7310 xtensa_maybe_create_trampoline_frag ();
7311 /* Always create one here. */
7312 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7314 else if (is_branch
&& do_align_targets ())
7316 gas_assert (finish_frag
);
7317 frag_var (rs_machine_dependent
,
7318 xtensa_fetch_width
, xtensa_fetch_width
,
7319 RELAX_MAYBE_UNREACHABLE
,
7320 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7321 xtensa_set_frag_assembly_state (frag_now
);
7322 frag_var (rs_machine_dependent
,
7324 RELAX_MAYBE_DESIRE_ALIGN
,
7325 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7326 xtensa_set_frag_assembly_state (frag_now
);
7330 /* Now, if the original opcode was a call... */
7331 if (do_align_targets ()
7332 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7334 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7335 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7336 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7337 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7338 xtensa_set_frag_assembly_state (frag_now
);
7341 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7343 frag_wane (frag_now
);
7345 xtensa_set_frag_assembly_state (frag_now
);
7350 /* xtensa_end and helper functions. */
7352 static void xtensa_cleanup_align_frags (void);
7353 static void xtensa_fix_target_frags (void);
7354 static void xtensa_mark_narrow_branches (void);
7355 static void xtensa_mark_zcl_first_insns (void);
7356 static void xtensa_mark_difference_of_two_symbols (void);
7357 static void xtensa_fix_a0_b_retw_frags (void);
7358 static void xtensa_fix_b_j_loop_end_frags (void);
7359 static void xtensa_fix_close_loop_end_frags (void);
7360 static void xtensa_fix_short_loop_frags (void);
7361 static void xtensa_sanity_check (void);
7362 static void xtensa_add_config_info (void);
7367 directive_balance ();
7368 xtensa_flush_pending_output ();
7370 past_xtensa_end
= TRUE
;
7372 xtensa_move_literals ();
7374 xtensa_reorder_segments ();
7375 xtensa_cleanup_align_frags ();
7376 xtensa_fix_target_frags ();
7377 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7378 xtensa_fix_a0_b_retw_frags ();
7379 if (workaround_b_j_loop_end
)
7380 xtensa_fix_b_j_loop_end_frags ();
7382 /* "close_loop_end" should be processed BEFORE "short_loop". */
7383 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7384 xtensa_fix_close_loop_end_frags ();
7386 if (workaround_short_loop
&& maybe_has_short_loop
)
7387 xtensa_fix_short_loop_frags ();
7389 xtensa_mark_narrow_branches ();
7390 xtensa_mark_zcl_first_insns ();
7392 xtensa_sanity_check ();
7394 xtensa_add_config_info ();
7396 xtensa_check_frag_count ();
7399 struct trampoline_chain_entry
7405 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7406 of locations of trampoline jumps leading there. Jumps are represented
7407 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7409 struct trampoline_chain
7411 struct trampoline_chain_entry target
;
7412 struct trampoline_chain_entry
*entry
;
7415 bfd_boolean needs_sorting
;
7418 struct trampoline_chain_index
7420 struct trampoline_chain
*entry
;
7423 bfd_boolean needs_sorting
;
7426 struct trampoline_index
7433 struct trampoline_seg
7435 struct trampoline_seg
*next
;
7437 /* Trampolines ordered by their frag fr_address */
7438 struct trampoline_index index
;
7439 /* Known trampoline chains ordered by (sym, offset) pair */
7440 struct trampoline_chain_index chain_index
;
7443 static struct trampoline_seg trampoline_seg_list
;
7444 #define J_RANGE (128 * 1024)
7445 #define J_MARGIN 4096
7447 static int unreachable_count
= 0;
7451 xtensa_maybe_create_trampoline_frag (void)
7453 if (!use_trampolines
)
7456 /* We create an area for possible trampolines every 10 unreachable frags.
7457 These are preferred over the ones not preceded by an unreachable frag,
7458 because we don't have to jump around them. This function is called after
7459 each RELAX_UNREACHABLE frag is created. */
7461 if (++unreachable_count
> 10)
7463 xtensa_create_trampoline_frag (FALSE
);
7464 clear_frag_count ();
7465 unreachable_count
= 0;
7470 xtensa_check_frag_count (void)
7472 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7475 /* We create an area for possible trampolines every 8000 frags or so. This
7476 is an estimate based on the max range of a "j" insn (+/-128K) divided
7477 by a typical frag byte count (16), minus a few for safety. This function
7478 is called after each source line is processed. */
7480 if (get_frag_count () > 8000)
7482 xtensa_create_trampoline_frag (TRUE
);
7483 clear_frag_count ();
7484 unreachable_count
= 0;
7487 /* We create an area for a possible literal pool every N (default 5000)
7489 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7492 static xtensa_insnbuf trampoline_buf
= NULL
;
7493 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7495 static xtensa_insnbuf litpool_buf
= NULL
;
7496 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7498 #define TRAMPOLINE_FRAG_SIZE 3000
7500 static struct trampoline_seg
*
7501 find_trampoline_seg (asection
*seg
)
7503 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7504 static struct trampoline_seg
*mr
;
7506 if (mr
&& mr
->seg
== seg
)
7509 for ( ; ts
; ts
= ts
->next
)
7521 static size_t xg_find_trampoline (const struct trampoline_index
*idx
,
7525 size_t b
= idx
->n_entries
;
7529 size_t c
= (a
+ b
) / 2;
7531 if (idx
->entry
[c
]->fr_address
<= addr
)
7539 static void xg_add_trampoline_to_index (struct trampoline_index
*idx
,
7542 if (idx
->n_entries
== idx
->n_max
)
7544 idx
->n_max
= (idx
->n_entries
+ 1) * 2;
7545 idx
->entry
= xrealloc (idx
->entry
,
7546 sizeof (*idx
->entry
) * idx
->n_max
);
7548 idx
->entry
[idx
->n_entries
] = fragP
;
7552 static void xg_remove_trampoline_from_index (struct trampoline_index
*idx
,
7555 gas_assert (i
< idx
->n_entries
);
7556 memmove (idx
->entry
+ i
, idx
->entry
+ i
+ 1,
7557 (idx
->n_entries
- i
- 1) * sizeof (*idx
->entry
));
7561 static void xg_add_trampoline_to_seg (struct trampoline_seg
*ts
,
7564 xg_add_trampoline_to_index (&ts
->index
, fragP
);
7568 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7570 /* Emit a frag where we can place intermediate jump instructions,
7571 in case we need to jump farther than 128K bytes.
7572 Each jump instruction takes three bytes.
7573 We allocate enough for 1000 trampolines in each frag.
7574 If that's not enough, oh well. */
7576 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
7579 int size
= TRAMPOLINE_FRAG_SIZE
;
7583 ts
= XCNEW(struct trampoline_seg
);
7584 ts
->next
= trampoline_seg_list
.next
;
7585 trampoline_seg_list
.next
= ts
;
7589 frag_wane (frag_now
);
7591 xtensa_set_frag_assembly_state (frag_now
);
7592 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7593 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7594 if (trampoline_buf
== NULL
)
7596 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7597 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7599 fragP
->tc_frag_data
.needs_jump_around
= needs_jump_around
;
7600 xg_add_trampoline_to_seg (ts
, fragP
);
7603 static bfd_boolean
xg_is_trampoline_frag_full (const fragS
*fragP
)
7605 return fragP
->fr_var
< 3;
7608 static int xg_order_trampoline_chain_entry (const void *a
, const void *b
)
7610 const struct trampoline_chain_entry
*pa
= a
;
7611 const struct trampoline_chain_entry
*pb
= b
;
7613 if (pa
->sym
!= pb
->sym
)
7615 valueT aval
= S_GET_VALUE (pa
->sym
);
7616 valueT bval
= S_GET_VALUE (pb
->sym
);
7619 return aval
< bval
? -1 : 1;
7621 if (pa
->offset
!= pb
->offset
)
7622 return pa
->offset
< pb
->offset
? -1 : 1;
7626 static void xg_sort_trampoline_chain (struct trampoline_chain
*tc
)
7628 qsort (tc
->entry
, tc
->n_entries
, sizeof (*tc
->entry
),
7629 xg_order_trampoline_chain_entry
);
7630 tc
->needs_sorting
= FALSE
;
7633 /* Find entry index in the given chain with maximal address <= source. */
7634 static size_t xg_find_chain_entry (struct trampoline_chain
*tc
,
7638 size_t b
= tc
->n_entries
;
7640 if (tc
->needs_sorting
)
7641 xg_sort_trampoline_chain (tc
);
7645 size_t c
= (a
+ b
) / 2;
7646 struct trampoline_chain_entry
*e
= tc
->entry
+ c
;
7648 if (S_GET_VALUE(e
->sym
) + e
->offset
<= source
)
7656 /* Find the best jump target for the source in the given trampoline chain.
7657 The best jump target is the one that results in the shortest path to the
7658 final target, it's the location of the jump closest to the final target,
7659 but within the J_RANGE - J_MARGIN from the source. */
7660 static struct trampoline_chain_entry
*
7661 xg_get_best_chain_entry (struct trampoline_chain
*tc
, addressT source
)
7663 addressT target
= S_GET_VALUE(tc
->target
.sym
) + tc
->target
.offset
;
7664 size_t i
= xg_find_chain_entry (tc
, source
);
7665 struct trampoline_chain_entry
*e
= tc
->entry
+ i
;
7666 int step
= target
< source
? -1 : 1;
7667 addressT chained_target
;
7670 if (target
> source
&&
7671 S_GET_VALUE(e
->sym
) + e
->offset
<= source
&&
7672 i
+ 1 < tc
->n_entries
)
7675 while (i
+ step
< tc
->n_entries
)
7677 struct trampoline_chain_entry
*next
= tc
->entry
+ i
+ step
;
7679 chained_target
= S_GET_VALUE(next
->sym
) + next
->offset
;
7680 off
= source
- chained_target
;
7682 if (labs (off
) >= J_RANGE
- J_MARGIN
)
7689 chained_target
= S_GET_VALUE(e
->sym
) + e
->offset
;
7690 off
= source
- chained_target
;
7692 if (labs (off
) < J_MARGIN
||
7693 labs (off
) >= J_RANGE
- J_MARGIN
)
7695 return tc
->entry
+ i
;
7698 static int xg_order_trampoline_chain (const void *a
, const void *b
)
7700 const struct trampoline_chain
*_pa
= a
;
7701 const struct trampoline_chain
*_pb
= b
;
7702 const struct trampoline_chain_entry
*pa
= &_pa
->target
;
7703 const struct trampoline_chain_entry
*pb
= &_pb
->target
;
7704 symbolS
*s1
= pa
->sym
;
7705 symbolS
*s2
= pb
->sym
;
7709 symbolS
*tmp
= symbol_symbolS (s1
);
7713 tmp
= symbol_symbolS (s2
);
7718 return s1
< s2
? -1 : 1;
7721 if (pa
->offset
!= pb
->offset
)
7722 return pa
->offset
< pb
->offset
? -1 : 1;
7726 static struct trampoline_chain
*
7727 xg_get_trampoline_chain (struct trampoline_seg
*ts
,
7731 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7732 struct trampoline_chain c
;
7734 if (idx
->needs_sorting
)
7736 qsort (idx
->entry
, idx
->n_entries
, sizeof (*idx
->entry
),
7737 xg_order_trampoline_chain
);
7738 idx
->needs_sorting
= FALSE
;
7741 c
.target
.offset
= offset
;
7742 return bsearch (&c
, idx
->entry
, idx
->n_entries
,
7743 sizeof (struct trampoline_chain
),
7744 xg_order_trampoline_chain
);
7747 /* Find trampoline chain in the given trampoline segment that is going
7748 to the *sym + *offset. If found, replace *sym and *offset with the
7749 best jump target in that chain. */
7750 static struct trampoline_chain
*
7751 xg_find_best_eq_target (struct trampoline_seg
*ts
,
7752 addressT source
, symbolS
**sym
,
7755 struct trampoline_chain
*tc
= xg_get_trampoline_chain (ts
, *sym
, *offset
);
7759 struct trampoline_chain_entry
*e
= xg_get_best_chain_entry (tc
, source
);
7762 *offset
= e
->offset
;
7767 static void xg_add_location_to_chain (struct trampoline_chain
*tc
,
7768 symbolS
*sym
, addressT offset
)
7770 struct trampoline_chain_entry
*e
;
7772 if (tc
->n_entries
== tc
->n_max
)
7774 tc
->n_max
= (tc
->n_max
+ 1) * 2;
7775 tc
->entry
= xrealloc (tc
->entry
, sizeof (*tc
->entry
) * tc
->n_max
);
7777 e
= tc
->entry
+ tc
->n_entries
;
7781 tc
->needs_sorting
= TRUE
;
7784 static struct trampoline_chain
*
7785 xg_create_trampoline_chain (struct trampoline_seg
*ts
,
7786 symbolS
*sym
, addressT offset
)
7788 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7789 struct trampoline_chain
*tc
;
7791 if (idx
->n_entries
== idx
->n_max
)
7793 idx
->n_max
= (idx
->n_max
+ 1) * 2;
7794 idx
->entry
= xrealloc (idx
->entry
,
7795 sizeof (*idx
->entry
) * idx
->n_max
);
7798 tc
= idx
->entry
+ idx
->n_entries
;
7799 tc
->target
.sym
= sym
;
7800 tc
->target
.offset
= offset
;
7804 xg_add_location_to_chain (tc
, sym
, offset
);
7807 idx
->needs_sorting
= TRUE
;
7812 void dump_trampolines (void);
7815 dump_trampolines (void)
7817 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7819 for ( ; ts
; ts
= ts
->next
)
7822 asection
*seg
= ts
->seg
;
7826 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7828 for (i
= 0; i
< ts
->index
.n_entries
; ++i
)
7830 fragS
*tf
= ts
->index
.entry
[i
];
7832 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7833 (int)tf
->fr_address
, (int)tf
->fr_fix
,
7834 tf
->tc_frag_data
.needs_jump_around
? "T" : "F");
7839 static void dump_litpools (void) __attribute__ ((unused
));
7842 dump_litpools (void)
7844 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7845 struct litpool_frag
*lpf
;
7847 for ( ; lps
; lps
= lps
->next
)
7849 printf("litpool seg %s\n", lps
->seg
->name
);
7850 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7852 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7854 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7856 if (litfrag
->fr_fix
== 4)
7858 litfrag
= litfrag
->fr_next
;
7860 printf(" %ld <%d:%d> (%d) [%d]: ",
7861 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7862 lpf
->fragP
->fr_line
, count
);
7863 //dump_frag(lpf->fragP);
7869 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7870 bfd_boolean only_if_needed
)
7872 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7874 struct litpool_frag
*lpf
;
7875 bfd_boolean needed
= FALSE
;
7877 if (use_literal_section
|| !auto_litpools
)
7880 for ( ; lps
; lps
= lps
->next
)
7882 if (lps
->seg
== now_seg
)
7888 lps
= XCNEW (struct litpool_seg
);
7889 lps
->next
= litpool_seg_list
.next
;
7890 litpool_seg_list
.next
= lps
;
7892 lps
->frag_list
.next
= &lps
->frag_list
;
7893 lps
->frag_list
.prev
= &lps
->frag_list
;
7894 /* Put candidate literal pool at the beginning of every section,
7895 so that even when section starts with literal load there's a
7896 literal pool available. */
7897 lps
->frag_count
= auto_litpool_limit
;
7906 if (past_xtensa_end
|| !use_transform() ||
7907 frag_now
->tc_frag_data
.is_no_transform
)
7911 if (auto_litpool_limit
<= 0)
7913 /* Don't create a litpool based only on frag count. */
7916 else if (lps
->frag_count
> auto_litpool_limit
)
7933 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7934 /* Create a potential site for a literal pool. */
7935 frag_wane (frag_now
);
7937 xtensa_set_frag_assembly_state (frag_now
);
7939 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7940 fragP
->tc_frag_data
.literal_frag
= fragP
;
7941 frag_var (rs_machine_dependent
, size
, size
,
7943 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7944 RELAX_LITERAL_POOL_BEGIN
,
7946 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7947 frag_variant (rs_machine_dependent
, 0, 0,
7948 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7949 xtensa_set_frag_assembly_state (frag_now
);
7953 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7954 just record it here. */
7958 lpf
= XNEW (struct litpool_frag
);
7959 /* Insert at tail of circular list. */
7961 lps
->frag_list
.prev
->next
= lpf
;
7962 lpf
->next
= &lps
->frag_list
;
7963 lpf
->prev
= lps
->frag_list
.prev
;
7964 lps
->frag_list
.prev
= lpf
;
7966 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7967 lpf
->original_priority
= lpf
->priority
;
7968 lpf
->literal_count
= 0;
7970 lps
->frag_count
= 0;
7974 xtensa_cleanup_align_frags (void)
7979 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7980 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7983 /* Walk over all of the fragments in a subsection. */
7984 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7986 if ((fragP
->fr_type
== rs_align
7987 || fragP
->fr_type
== rs_align_code
7988 || (fragP
->fr_type
== rs_machine_dependent
7989 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7990 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7991 && fragP
->fr_fix
== 0)
7993 fragS
*next
= fragP
->fr_next
;
7996 && next
->fr_fix
== 0
7997 && next
->fr_type
== rs_machine_dependent
7998 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8001 next
= next
->fr_next
;
8004 /* If we don't widen branch targets, then they
8005 will be easier to align. */
8006 if (fragP
->tc_frag_data
.is_branch_target
8007 && fragP
->fr_opcode
== fragP
->fr_literal
8008 && fragP
->fr_type
== rs_machine_dependent
8009 && fragP
->fr_subtype
== RELAX_SLOTS
8010 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8012 if (fragP
->fr_type
== rs_machine_dependent
8013 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
8014 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
8020 /* Re-process all of the fragments looking to convert all of the
8021 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
8022 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
8023 Otherwise, convert to a .fill 0. */
8026 xtensa_fix_target_frags (void)
8031 /* When this routine is called, all of the subsections are still intact
8032 so we walk over subsections instead of sections. */
8033 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8034 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8038 /* Walk over all of the fragments in a subsection. */
8039 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8041 if (fragP
->fr_type
== rs_machine_dependent
8042 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8044 if (next_frag_is_branch_target (fragP
))
8045 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
8054 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
8057 xtensa_mark_narrow_branches (void)
8062 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8063 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8066 /* Walk over all of the fragments in a subsection. */
8067 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8069 if (fragP
->fr_type
== rs_machine_dependent
8070 && fragP
->fr_subtype
== RELAX_SLOTS
8071 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8075 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
8076 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
8078 if (vinsn
.num_slots
== 1
8079 && xtensa_opcode_is_branch (xtensa_default_isa
,
8080 vinsn
.slots
[0].opcode
) == 1
8081 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
8082 && is_narrow_branch_guaranteed_in_range (fragP
,
8085 fragP
->fr_subtype
= RELAX_SLOTS
;
8086 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
8087 fragP
->tc_frag_data
.is_aligning_branch
= 1;
8095 /* A branch is typically widened only when its target is out of
8096 range. However, we would like to widen them to align a subsequent
8097 branch target when possible.
8099 Because the branch relaxation code is so convoluted, the optimal solution
8100 (combining the two cases) is difficult to get right in all circumstances.
8101 We therefore go with an "almost as good" solution, where we only
8102 use for alignment narrow branches that definitely will not expand to a
8103 jump and a branch. These functions find and mark these cases. */
8105 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8106 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8107 We start counting beginning with the frag after the 2-byte branch, so the
8108 maximum offset is (4 - 2) + 63 = 65. */
8109 #define MAX_IMMED6 65
8111 static offsetT
unrelaxed_frag_max_size (fragS
*);
8114 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
8116 const expressionS
*exp
= &tinsn
->tok
[1];
8117 symbolS
*symbolP
= exp
->X_add_symbol
;
8118 offsetT max_distance
= exp
->X_add_number
;
8121 if (exp
->X_op
!= O_symbol
)
8124 target_frag
= symbol_get_frag (symbolP
);
8126 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
8127 if (is_branch_jmp_to_next (tinsn
, fragP
))
8130 /* The branch doesn't branch over it's own frag,
8131 but over the subsequent ones. */
8132 fragP
= fragP
->fr_next
;
8133 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
8135 max_distance
+= unrelaxed_frag_max_size (fragP
);
8136 fragP
= fragP
->fr_next
;
8138 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
8145 xtensa_mark_zcl_first_insns (void)
8150 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8151 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8154 /* Walk over all of the fragments in a subsection. */
8155 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8157 if (fragP
->fr_type
== rs_machine_dependent
8158 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8159 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8161 /* Find the loop frag. */
8162 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8163 /* Find the first insn frag. */
8164 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
8166 /* Handle a corner case that comes up in hardware
8167 diagnostics. The original assembly looks like this:
8170 <empty_frag>--not found by next_non_empty_frag
8173 Depending on the start address, the assembler may or
8174 may not change it to look something like this:
8177 nop--frag isn't empty anymore
8180 So set up to check the alignment of the nop if it
8182 while (loop_frag
!= targ_frag
)
8184 if (loop_frag
->fr_type
== rs_machine_dependent
8185 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8186 || loop_frag
->fr_subtype
8187 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8188 targ_frag
= loop_frag
;
8190 loop_frag
= loop_frag
->fr_next
;
8193 /* Of course, sometimes (mostly for toy test cases) a
8194 zero-cost loop instruction is the last in a section. */
8197 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
8198 /* Do not widen a frag that is the first instruction of a
8199 zero-cost loop. It makes that loop harder to align. */
8200 if (targ_frag
->fr_type
== rs_machine_dependent
8201 && targ_frag
->fr_subtype
== RELAX_SLOTS
8202 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
8205 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
8206 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8209 frag_wane (targ_frag
);
8210 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
8214 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
8222 /* When a difference-of-symbols expression is encoded as a uleb128 or
8223 sleb128 value, the linker is unable to adjust that value to account for
8224 link-time relaxation. Mark all the code between such symbols so that
8225 its size cannot be changed by linker relaxation. */
8228 xtensa_mark_difference_of_two_symbols (void)
8232 for (expr_sym
= expr_symbols
; expr_sym
;
8233 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
8235 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
8237 if (exp
->X_op
== O_subtract
)
8239 symbolS
*left
= exp
->X_add_symbol
;
8240 symbolS
*right
= exp
->X_op_symbol
;
8242 /* Difference of two symbols not in the same section
8243 are handled with relocations in the linker. */
8244 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
8250 if (symbol_get_frag (left
)->fr_address
8251 <= symbol_get_frag (right
)->fr_address
)
8253 start
= symbol_get_frag (left
);
8254 end
= symbol_get_frag (right
);
8258 start
= symbol_get_frag (right
);
8259 end
= symbol_get_frag (left
);
8262 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
8263 walk
= start
->tc_frag_data
.no_transform_end
;
8268 walk
->tc_frag_data
.is_no_transform
= 1;
8269 walk
= walk
->fr_next
;
8271 while (walk
&& walk
->fr_address
< end
->fr_address
);
8273 start
->tc_frag_data
.no_transform_end
= walk
;
8280 /* Re-process all of the fragments looking to convert all of the
8281 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8282 conditional branch or a retw/retw.n, convert this frag to one that
8283 will generate a NOP. In any case close it off with a .fill 0. */
8285 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
8288 xtensa_fix_a0_b_retw_frags (void)
8293 /* When this routine is called, all of the subsections are still intact
8294 so we walk over subsections instead of sections. */
8295 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8296 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8300 /* Walk over all of the fragments in a subsection. */
8301 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8303 if (fragP
->fr_type
== rs_machine_dependent
8304 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
8306 if (next_instrs_are_b_retw (fragP
))
8308 if (fragP
->tc_frag_data
.is_no_transform
)
8309 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8311 relax_frag_add_nop (fragP
);
8321 next_instrs_are_b_retw (fragS
*fragP
)
8323 xtensa_opcode opcode
;
8325 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8326 static xtensa_insnbuf insnbuf
= NULL
;
8327 static xtensa_insnbuf slotbuf
= NULL
;
8328 xtensa_isa isa
= xtensa_default_isa
;
8329 unsigned int offset
= 0;
8331 bfd_boolean branch_seen
= FALSE
;
8335 insnbuf
= xtensa_insnbuf_alloc (isa
);
8336 slotbuf
= xtensa_insnbuf_alloc (isa
);
8339 if (next_fragP
== NULL
)
8342 /* Check for the conditional branch. */
8343 xtensa_insnbuf_from_chars
8344 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8345 fmt
= xtensa_format_decode (isa
, insnbuf
);
8346 if (fmt
== XTENSA_UNDEFINED
)
8349 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8351 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8352 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8354 branch_seen
= (branch_seen
8355 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8361 offset
+= xtensa_format_length (isa
, fmt
);
8362 if (offset
== next_fragP
->fr_fix
)
8364 next_fragP
= next_non_empty_frag (next_fragP
);
8368 if (next_fragP
== NULL
)
8371 /* Check for the retw/retw.n. */
8372 xtensa_insnbuf_from_chars
8373 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8374 fmt
= xtensa_format_decode (isa
, insnbuf
);
8376 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8377 have no problems. */
8378 if (fmt
== XTENSA_UNDEFINED
8379 || xtensa_format_num_slots (isa
, fmt
) != 1)
8382 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8383 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8385 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8392 /* Re-process all of the fragments looking to convert all of the
8393 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8394 loop end label, convert this frag to one that will generate a NOP.
8395 In any case close it off with a .fill 0. */
8397 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8400 xtensa_fix_b_j_loop_end_frags (void)
8405 /* When this routine is called, all of the subsections are still intact
8406 so we walk over subsections instead of sections. */
8407 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8408 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8412 /* Walk over all of the fragments in a subsection. */
8413 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8415 if (fragP
->fr_type
== rs_machine_dependent
8416 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8418 if (next_instr_is_loop_end (fragP
))
8420 if (fragP
->tc_frag_data
.is_no_transform
)
8421 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8423 relax_frag_add_nop (fragP
);
8433 next_instr_is_loop_end (fragS
*fragP
)
8435 const fragS
*next_fragP
;
8437 if (next_frag_is_loop_target (fragP
))
8440 next_fragP
= next_non_empty_frag (fragP
);
8441 if (next_fragP
== NULL
)
8444 if (!next_frag_is_loop_target (next_fragP
))
8447 /* If the size is >= 3 then there is more than one instruction here.
8448 The hardware bug will not fire. */
8449 if (next_fragP
->fr_fix
> 3)
8456 /* Re-process all of the fragments looking to convert all of the
8457 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8458 not MY loop's loop end within 12 bytes, add enough nops here to
8459 make it at least 12 bytes away. In any case close it off with a
8462 static offsetT min_bytes_to_other_loop_end
8463 (fragS
*, fragS
*, offsetT
);
8466 xtensa_fix_close_loop_end_frags (void)
8471 /* When this routine is called, all of the subsections are still intact
8472 so we walk over subsections instead of sections. */
8473 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8474 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8478 fragS
*current_target
= NULL
;
8480 /* Walk over all of the fragments in a subsection. */
8481 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8483 if (fragP
->fr_type
== rs_machine_dependent
8484 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8485 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8486 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8489 && fragP
->fr_type
== rs_machine_dependent
8490 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8493 int bytes_added
= 0;
8495 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8496 /* Max out at 12. */
8497 min_bytes
= min_bytes_to_other_loop_end
8498 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8500 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8502 if (fragP
->tc_frag_data
.is_no_transform
)
8503 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8506 while (min_bytes
+ bytes_added
8507 < REQUIRED_LOOP_DIVIDING_BYTES
)
8511 if (fragP
->fr_var
< length
)
8512 as_fatal (_("fr_var %lu < length %d"),
8513 (long) fragP
->fr_var
, length
);
8516 assemble_nop (length
,
8517 fragP
->fr_literal
+ fragP
->fr_fix
);
8518 fragP
->fr_fix
+= length
;
8519 fragP
->fr_var
-= length
;
8521 bytes_added
+= length
;
8527 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8528 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8534 static offsetT
unrelaxed_frag_min_size (fragS
*);
8537 min_bytes_to_other_loop_end (fragS
*fragP
,
8538 fragS
*current_target
,
8542 fragS
*current_fragP
;
8544 for (current_fragP
= fragP
;
8546 current_fragP
= current_fragP
->fr_next
)
8548 if (current_fragP
->tc_frag_data
.is_loop_target
8549 && current_fragP
!= current_target
)
8552 offset
+= unrelaxed_frag_min_size (current_fragP
);
8554 if (offset
>= max_size
)
8562 unrelaxed_frag_min_size (fragS
*fragP
)
8564 offsetT size
= fragP
->fr_fix
;
8566 /* Add fill size. */
8567 if (fragP
->fr_type
== rs_fill
)
8568 size
+= fragP
->fr_offset
;
8575 unrelaxed_frag_max_size (fragS
*fragP
)
8577 offsetT size
= fragP
->fr_fix
;
8578 switch (fragP
->fr_type
)
8581 /* Empty frags created by the obstack allocation scheme
8582 end up with type 0. */
8587 size
+= fragP
->fr_offset
;
8595 /* No further adjustments needed. */
8597 case rs_machine_dependent
:
8598 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8599 size
+= fragP
->fr_var
;
8602 /* We had darn well better know how big it is. */
8611 /* Re-process all of the fragments looking to convert all
8612 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8615 1) the instruction size count to the loop end label
8616 is too short (<= 2 instructions),
8617 2) loop has a jump or branch in it
8620 1) workaround_all_short_loops is TRUE
8621 2) The generating loop was a 'loopgtz' or 'loopnez'
8622 3) the instruction size count to the loop end label is too short
8624 then convert this frag (and maybe the next one) to generate a NOP.
8625 In any case close it off with a .fill 0. */
8627 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8628 static bfd_boolean
branch_before_loop_end (fragS
*);
8631 xtensa_fix_short_loop_frags (void)
8636 /* When this routine is called, all of the subsections are still intact
8637 so we walk over subsections instead of sections. */
8638 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8639 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8642 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8644 /* Walk over all of the fragments in a subsection. */
8645 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8647 if (fragP
->fr_type
== rs_machine_dependent
8648 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8649 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8652 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8653 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8654 current_opcode
= t_insn
.opcode
;
8655 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8656 current_opcode
) == 1);
8659 if (fragP
->fr_type
== rs_machine_dependent
8660 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8662 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8663 && (branch_before_loop_end (fragP
->fr_next
)
8664 || (workaround_all_short_loops
8665 && current_opcode
!= XTENSA_UNDEFINED
8666 && current_opcode
!= xtensa_loop_opcode
)))
8668 if (fragP
->tc_frag_data
.is_no_transform
)
8669 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8671 relax_frag_add_nop (fragP
);
8680 static int unrelaxed_frag_min_insn_count (fragS
*);
8683 count_insns_to_loop_end (fragS
*base_fragP
,
8684 bfd_boolean count_relax_add
,
8687 fragS
*fragP
= NULL
;
8692 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8694 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8695 if (insn_count
>= max_count
)
8698 if (count_relax_add
)
8700 if (fragP
->fr_type
== rs_machine_dependent
8701 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8703 /* In order to add the appropriate number of
8704 NOPs, we count an instruction for downstream
8707 if (insn_count
>= max_count
)
8717 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8719 xtensa_isa isa
= xtensa_default_isa
;
8720 static xtensa_insnbuf insnbuf
= NULL
;
8722 unsigned int offset
= 0;
8724 if (!fragP
->tc_frag_data
.is_insn
)
8728 insnbuf
= xtensa_insnbuf_alloc (isa
);
8730 /* Decode the fixed instructions. */
8731 while (offset
< fragP
->fr_fix
)
8735 xtensa_insnbuf_from_chars
8736 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8737 fmt
= xtensa_format_decode (isa
, insnbuf
);
8739 if (fmt
== XTENSA_UNDEFINED
)
8741 as_fatal (_("undecodable instruction in instruction frag"));
8744 offset
+= xtensa_format_length (isa
, fmt
);
8752 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8755 branch_before_loop_end (fragS
*base_fragP
)
8759 for (fragP
= base_fragP
;
8760 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8761 fragP
= fragP
->fr_next
)
8763 if (unrelaxed_frag_has_b_j (fragP
))
8771 unrelaxed_frag_has_b_j (fragS
*fragP
)
8773 static xtensa_insnbuf insnbuf
= NULL
;
8774 xtensa_isa isa
= xtensa_default_isa
;
8775 unsigned int offset
= 0;
8777 if (!fragP
->tc_frag_data
.is_insn
)
8781 insnbuf
= xtensa_insnbuf_alloc (isa
);
8783 /* Decode the fixed instructions. */
8784 while (offset
< fragP
->fr_fix
)
8789 xtensa_insnbuf_from_chars
8790 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8791 fmt
= xtensa_format_decode (isa
, insnbuf
);
8792 if (fmt
== XTENSA_UNDEFINED
)
8795 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8797 xtensa_opcode opcode
=
8798 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8799 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8800 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8803 offset
+= xtensa_format_length (isa
, fmt
);
8809 /* Checks to be made after initial assembly but before relaxation. */
8811 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8812 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8815 xtensa_sanity_check (void)
8817 const char *file_name
;
8822 file_name
= as_where (&line
);
8823 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8824 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8828 /* Walk over all of the fragments in a subsection. */
8829 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8831 if (fragP
->fr_type
== rs_machine_dependent
8832 && fragP
->fr_subtype
== RELAX_SLOTS
8833 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8835 static xtensa_insnbuf insnbuf
= NULL
;
8838 if (fragP
->fr_opcode
!= NULL
)
8841 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8842 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8843 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8845 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8846 t_insn
.opcode
) == 1)
8848 if (is_empty_loop (&t_insn
, fragP
))
8850 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8851 as_bad (_("invalid empty loop"));
8853 if (!is_local_forward_loop (&t_insn
, fragP
))
8855 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8856 as_bad (_("loop target does not follow "
8857 "loop instruction in section"));
8864 new_logical_line (file_name
, line
);
8868 #define LOOP_IMMED_OPN 1
8870 /* Return TRUE if the loop target is the next non-zero fragment. */
8873 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8875 const expressionS
*exp
;
8879 if (insn
->insn_type
!= ITYPE_INSN
)
8882 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8885 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8888 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8890 if (exp
->X_op
!= O_symbol
)
8893 symbolP
= exp
->X_add_symbol
;
8897 if (symbol_get_frag (symbolP
) == NULL
)
8900 if (S_GET_VALUE (symbolP
) != 0)
8903 /* Walk through the zero-size fragments from this one. If we find
8904 the target fragment, then this is a zero-size loop. */
8906 for (next_fragP
= fragP
->fr_next
;
8908 next_fragP
= next_fragP
->fr_next
)
8910 if (next_fragP
== symbol_get_frag (symbolP
))
8912 if (next_fragP
->fr_fix
!= 0)
8920 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8922 const expressionS
*exp
;
8926 if (insn
->insn_type
!= ITYPE_INSN
)
8929 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8932 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8935 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8937 if (exp
->X_op
!= O_symbol
)
8940 symbolP
= exp
->X_add_symbol
;
8944 if (symbol_get_frag (symbolP
) == NULL
)
8947 /* Walk through fragments until we find the target.
8948 If we do not find the target, then this is an invalid loop. */
8950 for (next_fragP
= fragP
->fr_next
;
8952 next_fragP
= next_fragP
->fr_next
)
8954 if (next_fragP
== symbol_get_frag (symbolP
))
8962 #define XTINFO_NAME "Xtensa_Info"
8963 #define XTINFO_NAMESZ 12
8964 #define XTINFO_TYPE 1
8967 xtensa_add_config_info (void)
8973 info_sec
= subseg_new (".xtensa.info", 0);
8974 bfd_set_section_flags (info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8976 data
= XNEWVEC (char, 100);
8977 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8978 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8979 sz
= strlen (data
) + 1;
8981 /* Add enough null terminators to pad to a word boundary. */
8984 while ((sz
& 3) != 0);
8986 /* Follow the standard note section layout:
8987 First write the length of the name string. */
8989 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8991 /* Next comes the length of the "descriptor", i.e., the actual data. */
8993 md_number_to_chars (p
, (valueT
) sz
, 4);
8995 /* Write the note type. */
8997 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8999 /* Write the name field. */
9000 p
= frag_more (XTINFO_NAMESZ
);
9001 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
9003 /* Finally, write the descriptor. */
9005 memcpy (p
, data
, sz
);
9011 /* Alignment Functions. */
9014 get_text_align_power (unsigned target_size
)
9016 if (target_size
<= 4)
9019 if (target_size
<= 8)
9022 if (target_size
<= 16)
9025 if (target_size
<= 32)
9028 if (target_size
<= 64)
9031 if (target_size
<= 128)
9034 if (target_size
<= 256)
9037 if (target_size
<= 512)
9040 if (target_size
<= 1024)
9049 get_text_align_max_fill_size (int align_pow
,
9050 bfd_boolean use_nops
,
9051 bfd_boolean use_no_density
)
9054 return (1 << align_pow
);
9056 return 3 * (1 << align_pow
);
9058 return 1 + (1 << align_pow
);
9062 /* Calculate the minimum bytes of fill needed at "address" to align a
9063 target instruction of size "target_size" so that it does not cross a
9064 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9065 the fill can be an arbitrary number of bytes. Otherwise, the space must
9066 be filled by NOP instructions. */
9069 get_text_align_fill_size (addressT address
,
9072 bfd_boolean use_nops
,
9073 bfd_boolean use_no_density
)
9075 addressT alignment
, fill
, fill_limit
, fill_step
;
9076 bfd_boolean skip_one
= FALSE
;
9078 alignment
= (1 << align_pow
);
9079 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
9083 fill_limit
= alignment
;
9086 else if (!use_no_density
)
9088 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9089 fill_limit
= alignment
* 2;
9095 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9096 fill_limit
= alignment
* 3;
9100 /* Try all fill sizes until finding one that works. */
9101 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
9103 if (skip_one
&& fill
== 1)
9105 if ((address
+ fill
) >> align_pow
9106 == (address
+ fill
+ target_size
- 1) >> align_pow
)
9115 branch_align_power (segT sec
)
9117 /* If the Xtensa processor has a fetch width of X, and
9118 the section is aligned to at least that boundary, then a branch
9119 target need only fit within that aligned block of memory to avoid
9120 a stall. Otherwise, try to fit branch targets within 4-byte
9121 aligned blocks (which may be insufficient, e.g., if the section
9122 has no alignment, but it's good enough). */
9123 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
9124 int sec_align
= get_recorded_alignment (sec
);
9126 if (sec_align
>= fetch_align
)
9133 /* This will assert if it is not possible. */
9136 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
9142 gas_assert (fill_size
% 3 == 0);
9143 return (fill_size
/ 3);
9146 gas_assert (fill_size
!= 1); /* Bad argument. */
9148 while (fill_size
> 1)
9151 if (fill_size
== 2 || fill_size
== 4)
9153 fill_size
-= insn_size
;
9156 gas_assert (fill_size
!= 1); /* Bad algorithm. */
9162 get_text_align_nth_nop_size (offsetT fill_size
,
9164 bfd_boolean use_no_density
)
9171 gas_assert (fill_size
!= 1); /* Bad argument. */
9173 while (fill_size
> 1)
9176 if (fill_size
== 2 || fill_size
== 4)
9178 fill_size
-= insn_size
;
9188 /* For the given fragment, find the appropriate address
9189 for it to begin at if we are using NOPs to align it. */
9192 get_noop_aligned_address (fragS
*fragP
, addressT address
)
9194 /* The rule is: get next fragment's FIRST instruction. Find
9195 the smallest number of bytes that need to be added to
9196 ensure that the next fragment's FIRST instruction will fit
9199 E.G., 2 bytes : 0, 1, 2 mod 4
9202 If the FIRST instruction MIGHT be relaxed,
9203 assume that it will become a 3-byte instruction.
9205 Note again here that LOOP instructions are not bundleable,
9206 and this relaxation only applies to LOOP opcodes. */
9209 int first_insn_size
;
9211 addressT pre_opcode_bytes
;
9214 xtensa_opcode opcode
;
9215 bfd_boolean is_loop
;
9217 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9218 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
9220 /* Find the loop frag. */
9221 first_insn
= next_non_empty_frag (fragP
);
9222 /* Now find the first insn frag. */
9223 first_insn
= next_non_empty_frag (first_insn
);
9225 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
9226 gas_assert (is_loop
);
9227 loop_insn_size
= xg_get_single_size (opcode
);
9229 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
9230 pre_opcode_bytes
+= loop_insn_size
;
9232 /* For loops, the alignment depends on the size of the
9233 instruction following the loop, not the LOOP instruction. */
9235 if (first_insn
== NULL
)
9236 first_insn_size
= xtensa_fetch_width
;
9238 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
9240 /* If it was 8, then we'll need a larger alignment for the section. */
9241 align_power
= get_text_align_power (first_insn_size
);
9242 record_alignment (now_seg
, align_power
);
9244 fill_size
= get_text_align_fill_size
9245 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
9246 fragP
->tc_frag_data
.is_no_density
);
9248 return address
+ fill_size
;
9252 /* 3 mechanisms for relaxing an alignment:
9254 Align to a power of 2.
9255 Align so the next fragment's instruction does not cross a word boundary.
9256 Align the current instruction so that if the next instruction
9257 were 3 bytes, it would not cross a word boundary.
9261 zeros - This is easy; always insert zeros.
9262 nops - 3-byte and 2-byte instructions
9266 >=5 : 3-byte instruction + fn (n-3)
9267 widening - widen previous instructions. */
9270 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
9272 addressT target_address
, loop_insn_offset
;
9274 xtensa_opcode loop_opcode
;
9275 bfd_boolean is_loop
;
9278 offsetT branch_align
;
9281 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9282 switch (fragP
->fr_subtype
)
9284 case RELAX_DESIRE_ALIGN
:
9285 target_size
= next_frag_format_size (fragP
);
9286 if (target_size
== XTENSA_UNDEFINED
)
9288 align_power
= branch_align_power (now_seg
);
9289 branch_align
= 1 << align_power
;
9290 /* Don't count on the section alignment being as large as the target. */
9291 if (target_size
> branch_align
)
9292 target_size
= branch_align
;
9293 opt_diff
= get_text_align_fill_size (address
, align_power
,
9294 target_size
, FALSE
, FALSE
);
9296 *max_diff
= (opt_diff
+ branch_align
9297 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
9298 gas_assert (*max_diff
>= opt_diff
);
9301 case RELAX_ALIGN_NEXT_OPCODE
:
9302 /* The next non-empty frag after this one holds the LOOP instruction
9303 that needs to be aligned. The required alignment depends on the
9304 size of the next non-empty frag after the loop frag, i.e., the
9305 first instruction in the loop. */
9306 loop_frag
= next_non_empty_frag (fragP
);
9307 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
9308 loop_insn_offset
= 0;
9309 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
9310 gas_assert (is_loop
);
9312 /* If the loop has been expanded then the LOOP instruction
9313 could be at an offset from this fragment. */
9314 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
9315 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
9317 /* In an ideal world, which is what we are shooting for here,
9318 we wouldn't need to use any NOPs immediately prior to the
9319 LOOP instruction. If this approach fails, relax_frag_loop_align
9320 will call get_noop_aligned_address. */
9322 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9323 align_power
= get_text_align_power (target_size
);
9324 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
9325 target_size
, FALSE
, FALSE
);
9327 *max_diff
= xtensa_fetch_width
9328 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9329 - target_size
+ opt_diff
;
9330 gas_assert (*max_diff
>= opt_diff
);
9341 /* md_relax_frag Hook and Helper Functions. */
9343 static long relax_frag_loop_align (fragS
*, long);
9344 static long relax_frag_for_align (fragS
*, long);
9345 static long relax_frag_immed
9346 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9348 /* Get projected address for the first fulcrum on a path from source to
9350 static addressT
xg_get_fulcrum (addressT source
, addressT target
)
9352 offsetT delta
= target
- source
;
9355 n
= (labs (delta
) + J_RANGE
- J_MARGIN
- 1) / (J_RANGE
- J_MARGIN
);
9356 return source
+ delta
/ n
;
9359 /* Given trampoline index, source and target of a jump find the best
9360 candidate trampoline for the first fulcrum. The best trampoline is
9361 the one in the reach of "j' instruction from the source, closest to
9362 the projected fulcrum address, and preferrably w/o a jump around or
9363 with already initialized jump around. */
9364 static size_t xg_find_best_trampoline (struct trampoline_index
*idx
,
9365 addressT source
, addressT target
)
9367 addressT fulcrum
= xg_get_fulcrum (source
, target
);
9370 size_t base_tr
= xg_find_trampoline (idx
, fulcrum
);
9373 /* Check trampoline frags around the base_tr to find the best. */
9374 for (dist
= 0; checked
; ++dist
)
9377 size_t tr
= base_tr
- dist
;
9381 /* Trampolines are checked in the following order:
9382 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9383 for (i
= 0; i
< 2; ++i
, tr
= base_tr
+ dist
+ 1)
9384 if (tr
< idx
->n_entries
)
9386 fragS
*trampoline_frag
= idx
->entry
[tr
];
9389 /* Don't check trampolines outside source - target interval. */
9390 if ((trampoline_frag
->fr_address
< source
&&
9391 trampoline_frag
->fr_address
< target
) ||
9392 (trampoline_frag
->fr_address
> source
&&
9393 trampoline_frag
->fr_address
> target
))
9396 /* Don't choose trampoline that contains the source. */
9397 if (source
>= trampoline_frag
->fr_address
9398 && source
<= trampoline_frag
->fr_address
+
9399 trampoline_frag
->fr_fix
)
9402 off
= trampoline_frag
->fr_address
- fulcrum
;
9403 /* Stop if some trampoline is found and the search is more than
9404 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9405 around is nice, but it shouldn't have much overhead. */
9406 if (best
< idx
->n_entries
&& labs (off
) > J_RANGE
/ 4)
9409 off
= trampoline_frag
->fr_address
- source
;
9410 if (labs (off
) < J_RANGE
- J_MARGIN
)
9413 /* Stop if a trampoline w/o jump around is found or initialized
9414 trampoline with jump around is found. */
9415 if (!trampoline_frag
->tc_frag_data
.needs_jump_around
||
9416 trampoline_frag
->fr_fix
)
9418 else if (best
>= idx
->n_entries
)
9424 if (best
< idx
->n_entries
)
9427 as_fatal (_("cannot find suitable trampoline"));
9430 static fixS
*xg_relax_fixup (struct trampoline_index
*idx
, fixS
*fixP
)
9432 symbolS
*s
= fixP
->fx_addsy
;
9433 addressT source
= fixP
->fx_frag
->fr_address
;
9434 addressT target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9435 size_t tr
= xg_find_best_trampoline (idx
, source
, target
);
9436 fragS
*trampoline_frag
= idx
->entry
[tr
];
9439 init_trampoline_frag (trampoline_frag
);
9440 newfixP
= xg_append_jump (trampoline_frag
,
9441 fixP
->fx_addsy
, fixP
->fx_offset
);
9443 /* Adjust the fixup for the original "j" instruction to
9444 point to the newly added jump. */
9445 fixP
->fx_addsy
= trampoline_frag
->fr_symbol
;
9446 fixP
->fx_offset
= trampoline_frag
->fr_fix
- 3;
9447 fixP
->tc_fix_data
.X_add_symbol
= trampoline_frag
->fr_symbol
;
9448 fixP
->tc_fix_data
.X_add_number
= trampoline_frag
->fr_fix
- 3;
9450 trampoline_frag
->tc_frag_data
.relax_seen
= FALSE
;
9452 if (xg_is_trampoline_frag_full (trampoline_frag
))
9453 xg_remove_trampoline_from_index (idx
, tr
);
9458 static bfd_boolean
xg_is_relaxable_fixup (fixS
*fixP
)
9460 xtensa_isa isa
= xtensa_default_isa
;
9461 addressT addr
= fixP
->fx_frag
->fr_address
;
9464 symbolS
*s
= fixP
->fx_addsy
;
9467 xtensa_opcode opcode
;
9469 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9470 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9473 target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9474 delta
= target
- addr
;
9476 if (labs (delta
) < J_RANGE
- J_MARGIN
)
9479 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9480 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9482 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9483 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9484 slot
= fixP
->tc_fix_data
.slot
;
9485 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9486 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9487 return opcode
== xtensa_j_opcode
;
9490 static void xg_relax_fixups (struct trampoline_seg
*ts
)
9492 struct trampoline_index
*idx
= &ts
->index
;
9493 segment_info_type
*seginfo
= seg_info (now_seg
);
9496 for (fx
= seginfo
->fix_root
; fx
; fx
= fx
->fx_next
)
9499 struct trampoline_chain
*tc
= NULL
;
9501 if (xg_is_relaxable_fixup (fixP
))
9503 tc
= xg_find_best_eq_target (ts
, fixP
->fx_frag
->fr_address
,
9504 &fixP
->fx_addsy
, &fixP
->fx_offset
);
9506 tc
= xg_create_trampoline_chain (ts
, fixP
->fx_addsy
,
9511 while (xg_is_relaxable_fixup (fixP
))
9513 fixP
= xg_relax_fixup (idx
, fixP
);
9514 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
9520 /* Given a trampoline frag relax all jumps that might want to use this
9521 trampoline. Only do real work once per relaxation cycle, when
9522 xg_relax_trampoline is called for the first trampoline in the now_seg.
9523 Don't use stretch, don't update new_stretch: place fulcrums with a
9524 slack to tolerate code movement. In the worst case if a jump between
9525 two trampolines wouldn't reach the next relaxation pass will fix it. */
9526 static void xg_relax_trampoline (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
,
9527 long *new_stretch ATTRIBUTE_UNUSED
)
9529 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9531 if (ts
->index
.n_entries
&& ts
->index
.entry
[0] == fragP
)
9532 xg_relax_fixups (ts
);
9535 /* Return the number of bytes added to this fragment, given that the
9536 input has been stretched already by "stretch". */
9539 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9541 xtensa_isa isa
= xtensa_default_isa
;
9542 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9543 long new_stretch
= 0;
9544 const char *file_name
;
9547 static xtensa_insnbuf vbuf
= NULL
;
9548 int slot
, num_slots
;
9551 file_name
= as_where (&line
);
9552 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9554 fragP
->tc_frag_data
.unreported_expansion
= 0;
9556 switch (fragP
->fr_subtype
)
9558 case RELAX_ALIGN_NEXT_OPCODE
:
9559 /* Always convert. */
9560 if (fragP
->tc_frag_data
.relax_seen
)
9561 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9564 case RELAX_LOOP_END
:
9568 case RELAX_LOOP_END_ADD_NOP
:
9569 /* Add a NOP and switch to .fill 0. */
9570 new_stretch
= relax_frag_add_nop (fragP
);
9574 case RELAX_DESIRE_ALIGN
:
9575 /* Do nothing. The narrowing before this frag will either align
9580 case RELAX_LITERAL_FINAL
:
9583 case RELAX_LITERAL_NR
:
9585 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9586 gas_assert (unreported
== lit_size
);
9587 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9588 fragP
->fr_var
-= lit_size
;
9589 fragP
->fr_fix
+= lit_size
;
9595 vbuf
= xtensa_insnbuf_alloc (isa
);
9597 xtensa_insnbuf_from_chars
9598 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9599 fmt
= xtensa_format_decode (isa
, vbuf
);
9600 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9602 for (slot
= 0; slot
< num_slots
; slot
++)
9604 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9607 if (fragP
->tc_frag_data
.relax_seen
)
9608 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9612 case RELAX_IMMED_STEP1
:
9613 case RELAX_IMMED_STEP2
:
9614 case RELAX_IMMED_STEP3
:
9615 /* Place the immediate. */
9616 new_stretch
+= relax_frag_immed
9617 (now_seg
, fragP
, stretch
,
9618 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9619 fmt
, slot
, stretched_p
, FALSE
);
9623 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9629 case RELAX_LITERAL_POOL_BEGIN
:
9630 if (fragP
->fr_var
!= 0)
9632 /* We have a converted "candidate" literal pool;
9633 assemble a jump around it. */
9635 if (!litpool_slotbuf
)
9637 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9638 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9641 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9642 fragP
->tc_frag_data
.is_insn
= TRUE
;
9644 insn
.insn_type
= ITYPE_INSN
;
9645 insn
.opcode
= xtensa_j_opcode
;
9647 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9649 fmt
= xg_get_single_format (xtensa_j_opcode
);
9650 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9651 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9652 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9653 (unsigned char *)fragP
->fr_literal
+
9658 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9659 BFD_RELOC_XTENSA_SLOT0_OP
);
9663 case RELAX_LITERAL_POOL_END
:
9664 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9665 case RELAX_MAYBE_UNREACHABLE
:
9666 case RELAX_MAYBE_DESIRE_ALIGN
:
9667 /* No relaxation required. */
9670 case RELAX_FILL_NOP
:
9671 case RELAX_UNREACHABLE
:
9672 if (fragP
->tc_frag_data
.relax_seen
)
9673 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9676 case RELAX_TRAMPOLINE
:
9677 if (fragP
->tc_frag_data
.relax_seen
)
9678 xg_relax_trampoline (fragP
, stretch
, &new_stretch
);
9682 as_bad (_("bad relaxation state"));
9685 /* Tell gas we need another relaxation pass. */
9686 if (! fragP
->tc_frag_data
.relax_seen
)
9688 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9692 new_logical_line (file_name
, line
);
9698 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9700 addressT old_address
, old_next_address
, old_size
;
9701 addressT new_address
, new_next_address
, new_size
;
9704 /* All the frags with relax_frag_for_alignment prior to this one in the
9705 section have been done, hopefully eliminating the need for a NOP here.
9706 But, this will put it in if necessary. */
9708 /* Calculate the old address of this fragment and the next fragment. */
9709 old_address
= fragP
->fr_address
- stretch
;
9710 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9711 fragP
->tc_frag_data
.text_expansion
[0]);
9712 old_size
= old_next_address
- old_address
;
9714 /* Calculate the new address of this fragment and the next fragment. */
9715 new_address
= fragP
->fr_address
;
9717 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9718 new_size
= new_next_address
- new_address
;
9720 growth
= new_size
- old_size
;
9722 /* Fix up the text_expansion field and return the new growth. */
9723 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9728 /* Add a NOP instruction. */
9731 relax_frag_add_nop (fragS
*fragP
)
9733 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9734 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9735 assemble_nop (length
, nop_buf
);
9736 fragP
->tc_frag_data
.is_insn
= TRUE
;
9738 if (fragP
->fr_var
< length
)
9740 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9744 fragP
->fr_fix
+= length
;
9745 fragP
->fr_var
-= length
;
9750 static long future_alignment_required (fragS
*, long);
9753 relax_frag_for_align (fragS
*fragP
, long stretch
)
9755 /* Overview of the relaxation procedure for alignment:
9756 We can widen with NOPs or by widening instructions or by filling
9757 bytes after jump instructions. Find the opportune places and widen
9758 them if necessary. */
9763 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9764 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9765 || (fragP
->fr_subtype
== RELAX_SLOTS
9766 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9768 stretch_me
= future_alignment_required (fragP
, stretch
);
9769 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9775 /* We expanded on a previous pass. Can we shrink now? */
9776 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9777 if (shrink
<= stretch
&& stretch
> 0)
9779 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9785 /* Below here, diff > 0. */
9786 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9792 /* Return the address of the next frag that should be aligned.
9794 By "address" we mean the address it _would_ be at if there
9795 is no action taken to align it between here and the target frag.
9796 In other words, if no narrows and no fill nops are used between
9797 here and the frag to align, _even_if_ some of the frags we use
9798 to align targets have already expanded on a previous relaxation
9801 Also, count each frag that may be used to help align the target.
9803 Return 0 if there are no frags left in the chain that need to be
9807 find_address_of_next_align_frag (fragS
**fragPP
,
9811 bfd_boolean
*paddable
)
9813 fragS
*fragP
= *fragPP
;
9814 addressT address
= fragP
->fr_address
;
9816 /* Do not reset the counts to 0. */
9820 /* Limit this to a small search. */
9821 if (*widens
>= (int) xtensa_fetch_width
)
9826 address
+= fragP
->fr_fix
;
9828 if (fragP
->fr_type
== rs_fill
)
9829 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9830 else if (fragP
->fr_type
== rs_machine_dependent
)
9832 switch (fragP
->fr_subtype
)
9834 case RELAX_UNREACHABLE
:
9838 case RELAX_FILL_NOP
:
9840 if (!fragP
->tc_frag_data
.is_no_density
)
9845 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9850 address
+= total_frag_text_expansion (fragP
);
9854 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9857 case RELAX_ALIGN_NEXT_OPCODE
:
9858 case RELAX_DESIRE_ALIGN
:
9862 case RELAX_MAYBE_UNREACHABLE
:
9863 case RELAX_MAYBE_DESIRE_ALIGN
:
9868 /* Just punt if we don't know the type. */
9875 /* Just punt if we don't know the type. */
9879 fragP
= fragP
->fr_next
;
9887 static long bytes_to_stretch (fragS
*, int, int, int, int);
9890 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9892 fragS
*this_frag
= fragP
;
9896 int narrow_nops
= 0;
9897 bfd_boolean paddable
= FALSE
;
9898 offsetT local_opt_diff
;
9901 int stretch_amount
= 0;
9902 int local_stretch_amount
;
9903 int global_stretch_amount
;
9905 address
= find_address_of_next_align_frag
9906 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9910 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9911 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9913 frag_wane (this_frag
);
9917 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9918 opt_diff
= local_opt_diff
;
9919 gas_assert (opt_diff
>= 0);
9920 gas_assert (max_diff
>= opt_diff
);
9925 fragP
= fragP
->fr_next
;
9927 while (fragP
&& opt_diff
< max_diff
&& address
)
9929 /* We only use these to determine if we can exit early
9930 because there will be plenty of ways to align future
9932 int glob_widens
= 0;
9935 bfd_boolean glob_pad
= 0;
9936 address
= find_address_of_next_align_frag
9937 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9938 /* If there is a padable portion, then skip. */
9939 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9944 offsetT next_m_diff
;
9945 offsetT next_o_diff
;
9947 /* Downrange frags haven't had stretch added to them yet. */
9950 /* The address also includes any text expansion from this
9951 frag in a previous pass, but we don't want that. */
9952 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9954 /* Assume we are going to move at least opt_diff. In
9955 reality, we might not be able to, but assuming that
9956 we will helps catch cases where moving opt_diff pushes
9957 the next target from aligned to unaligned. */
9958 address
+= opt_diff
;
9960 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9962 /* Now cleanup for the adjustments to address. */
9963 next_o_diff
+= opt_diff
;
9964 next_m_diff
+= opt_diff
;
9965 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9966 opt_diff
= next_o_diff
;
9967 if (next_m_diff
< max_diff
)
9968 max_diff
= next_m_diff
;
9969 fragP
= fragP
->fr_next
;
9973 /* If there are enough wideners in between, do it. */
9976 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9978 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9983 local_stretch_amount
9984 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9985 num_widens
, local_opt_diff
);
9986 global_stretch_amount
9987 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9988 num_widens
, opt_diff
);
9989 /* If the condition below is true, then the frag couldn't
9990 stretch the correct amount for the global case, so we just
9991 optimize locally. We'll rely on the subsequent frags to get
9992 the correct alignment in the global case. */
9993 if (global_stretch_amount
< local_stretch_amount
)
9994 stretch_amount
= local_stretch_amount
;
9996 stretch_amount
= global_stretch_amount
;
9998 if (this_frag
->fr_subtype
== RELAX_SLOTS
9999 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
10000 gas_assert (stretch_amount
<= 1);
10001 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10003 if (this_frag
->tc_frag_data
.is_no_density
)
10004 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
10006 gas_assert (stretch_amount
<= 3);
10009 return stretch_amount
;
10013 /* The idea: widen everything you can to get a target or loop aligned,
10014 then start using NOPs.
10016 wide_nops = the number of wide NOPs available for aligning
10017 narrow_nops = the number of narrow NOPs available for aligning
10018 (a subset of wide_nops)
10019 widens = the number of narrow instructions that should be widened
10024 bytes_to_stretch (fragS
*this_frag
,
10033 int bytes_short
= desired_diff
- num_widens
;
10035 gas_assert (desired_diff
>= 0
10036 && desired_diff
< (signed) xtensa_fetch_width
);
10037 if (desired_diff
== 0)
10040 gas_assert (wide_nops
> 0 || num_widens
> 0);
10042 /* Always prefer widening to NOP-filling. */
10043 if (bytes_short
< 0)
10045 /* There are enough RELAX_NARROW frags after this one
10046 to align the target without widening this frag in any way. */
10050 if (bytes_short
== 0)
10052 /* Widen every narrow between here and the align target
10053 and the align target will be properly aligned. */
10054 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10060 /* From here we will need at least one NOP to get an alignment.
10061 However, we may not be able to align at all, in which case,
10063 nops_needed
= desired_diff
/ 3;
10065 /* If there aren't enough nops, don't widen. */
10066 if (nops_needed
> wide_nops
)
10069 /* First try it with all wide nops. */
10070 nop_bytes
= nops_needed
* 3;
10071 extra_bytes
= desired_diff
- nop_bytes
;
10073 if (nop_bytes
+ num_widens
>= desired_diff
)
10075 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10077 else if (num_widens
== extra_bytes
)
10082 /* Add a narrow nop. */
10086 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
10089 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
10091 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10092 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10093 else if (num_widens
== extra_bytes
)
10098 /* Replace a wide nop with a narrow nop--we can get here if
10099 extra_bytes was negative in the previous conditional. */
10100 if (narrow_nops
== 1)
10104 if (nop_bytes
+ num_widens
>= desired_diff
)
10106 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10107 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10108 else if (num_widens
== extra_bytes
)
10113 /* If we can't satisfy any of the above cases, then we can't align
10114 using padding or fill nops. */
10120 xg_find_best_trampoline_for_tinsn (TInsn
*tinsn
, fragS
*fragP
)
10122 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
10123 addressT source
= fragP
->fr_address
;
10124 addressT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
10125 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10128 if (!ts
|| !ts
->index
.n_entries
)
10131 i
= xg_find_best_trampoline (&ts
->index
, source
, target
);
10133 return ts
->index
.entry
[i
];
10137 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10138 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10139 and finish the frag if it's full (but don't remove it from the trampoline
10140 frag index). Return fixup for the newly created jump. */
10141 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
)
10146 xtensa_isa isa
= xtensa_default_isa
;
10148 gas_assert (fragP
->fr_var
>= 3);
10149 tinsn_init (&insn
);
10150 insn
.insn_type
= ITYPE_INSN
;
10151 insn
.opcode
= xtensa_j_opcode
;
10153 set_expr_symbol_offset (&insn
.tok
[0], sym
, offset
);
10154 fmt
= xg_get_single_format (xtensa_j_opcode
);
10155 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10156 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10157 xtensa_insnbuf_to_chars (isa
, trampoline_buf
,
10158 (unsigned char *)fragP
->fr_literal
+ fragP
->fr_fix
, 3);
10159 fixP
= fix_new (fragP
, fragP
->fr_fix
, 3, sym
, offset
, TRUE
,
10160 BFD_RELOC_XTENSA_SLOT0_OP
);
10161 fixP
->tc_fix_data
.slot
= 0;
10163 fragP
->fr_fix
+= 3;
10164 fragP
->fr_var
-= 3;
10166 /* Adjust the jump around this trampoline (if present). */
10167 if (fragP
->tc_frag_data
.jump_around_fix
)
10168 fragP
->tc_frag_data
.jump_around_fix
->fx_offset
+= 3;
10170 /* Do we have room for more? */
10171 if (xg_is_trampoline_frag_full (fragP
))
10174 fragP
->fr_subtype
= 0;
10182 init_trampoline_frag (fragS
*fp
)
10186 if (fp
->fr_fix
== 0)
10189 char label
[10 + 2 * sizeof(fp
)];
10191 sprintf (label
, ".L0_TR_%p", fp
);
10192 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10193 fp
->fr_symbol
= lsym
;
10194 if (fp
->tc_frag_data
.needs_jump_around
)
10196 fp
->tc_frag_data
.jump_around_fix
= xg_append_jump (fp
, lsym
, 3);
10204 xg_get_single_symbol_slot (fragS
*fragP
)
10209 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10210 if (fragP
->tc_frag_data
.slot_symbols
[i
])
10212 gas_assert (slot
== -1);
10216 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10222 add_jump_to_trampoline (fragS
*tramp
, fragS
*origfrag
)
10224 int slot
= xg_get_single_symbol_slot (origfrag
);
10227 /* Assemble a jump to the target label in the trampoline frag. */
10228 fixP
= xg_append_jump (tramp
,
10229 origfrag
->tc_frag_data
.slot_symbols
[slot
],
10230 origfrag
->tc_frag_data
.slot_offsets
[slot
]);
10232 /* Modify the original j to point here. */
10233 origfrag
->tc_frag_data
.slot_symbols
[slot
] = tramp
->fr_symbol
;
10234 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10236 /* If trampoline is full, remove it from the list. */
10237 if (xg_is_trampoline_frag_full (tramp
))
10239 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10240 size_t tr
= xg_find_trampoline (&ts
->index
, tramp
->fr_address
);
10242 gas_assert (ts
->index
.entry
[tr
] == tramp
);
10243 xg_remove_trampoline_from_index (&ts
->index
, tr
);
10251 relax_frag_immed (segT segP
,
10258 bfd_boolean estimate_only
)
10262 bfd_boolean negatable_branch
= FALSE
;
10263 bfd_boolean branch_jmp_to_next
= FALSE
;
10264 bfd_boolean from_wide_insn
= FALSE
;
10265 xtensa_isa isa
= xtensa_default_isa
;
10267 offsetT frag_offset
;
10269 int num_text_bytes
, num_literal_bytes
;
10270 int literal_diff
, total_text_diff
, this_text_diff
;
10272 gas_assert (fragP
->fr_opcode
!= NULL
);
10274 xg_clear_vinsn (&cur_vinsn
);
10275 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10276 if (cur_vinsn
.num_slots
> 1)
10277 from_wide_insn
= TRUE
;
10279 tinsn
= cur_vinsn
.slots
[slot
];
10280 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10282 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10285 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10286 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10288 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10290 old_size
= xtensa_format_length (isa
, fmt
);
10292 /* Special case: replace a branch to the next instruction with a NOP.
10293 This is required to work around a hardware bug in T1040.0 and also
10294 serves as an optimization. */
10296 if (branch_jmp_to_next
10297 && ((old_size
== 2) || (old_size
== 3))
10298 && !next_frag_is_loop_target (fragP
))
10301 /* Here is the fun stuff: Get the immediate field from this
10302 instruction. If it fits, we are done. If not, find the next
10303 instruction sequence that fits. */
10305 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10306 istack_init (&istack
);
10307 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10308 min_steps
, stretch
);
10309 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10311 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10313 /* Figure out the number of bytes needed. */
10314 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10316 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10317 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10319 if (from_wide_insn
)
10322 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10325 num_text_bytes
+= old_size
;
10326 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10327 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10330 /* The first instruction in the relaxed sequence will go after
10331 the current wide instruction, and thus its symbolic immediates
10334 istack_init (&istack
);
10335 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10336 frag_offset
+ old_size
,
10337 min_steps
, stretch
+ old_size
);
10338 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10340 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10341 = (int) RELAX_IMMED
+ num_steps
;
10343 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10345 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10347 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10351 total_text_diff
= num_text_bytes
- old_size
;
10352 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10354 /* It MUST get larger. If not, we could get an infinite loop. */
10355 gas_assert (num_text_bytes
>= 0);
10356 gas_assert (literal_diff
>= 0);
10357 gas_assert (total_text_diff
>= 0);
10359 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10360 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10361 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10362 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10364 /* Find the associated expandable literal for this. */
10365 if (literal_diff
!= 0)
10367 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10370 gas_assert (literal_diff
== 4);
10371 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10373 /* We expect that the literal section state has NOT been
10375 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10376 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10377 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10379 /* We need to mark this section for another iteration
10385 if (negatable_branch
&& istack
.ninsn
> 1)
10386 update_next_frag_state (fragP
);
10388 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10389 if (istack
.ninsn
> 2 &&
10390 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10391 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10392 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10394 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10395 struct trampoline_seg
*ts
= find_trampoline_seg (segP
);
10396 struct trampoline_chain
*tc
= NULL
;
10399 !xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10402 int s
= xg_get_single_symbol_slot (fragP
);
10403 addressT offset
= fragP
->tc_frag_data
.slot_offsets
[s
];
10405 tc
= xg_find_best_eq_target (ts
, fragP
->fr_address
,
10406 &fragP
->tc_frag_data
.slot_symbols
[s
],
10410 tc
= xg_create_trampoline_chain (ts
,
10411 fragP
->tc_frag_data
.slot_symbols
[s
],
10413 fragP
->tc_frag_data
.slot_offsets
[s
] = offset
;
10414 tinsn_immed_from_frag (jinsn
, fragP
, s
);
10417 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10420 fragS
*tf
= xg_find_best_trampoline_for_tinsn (jinsn
, fragP
);
10426 this_text_diff
+= init_trampoline_frag (tf
) + 3;
10427 fixP
= add_jump_to_trampoline (tf
, fragP
);
10428 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
10430 fragP
->tc_frag_data
.relax_seen
= FALSE
;
10434 /* If target symbol is undefined, assume it will reach once linked. */
10435 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10437 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10439 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10440 _("jump target out of range; no usable trampoline found"));
10446 return this_text_diff
;
10450 /* md_convert_frag Hook and Helper Functions. */
10452 static void convert_frag_align_next_opcode (fragS
*);
10453 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10454 static void convert_frag_fill_nop (fragS
*);
10455 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10458 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10460 static xtensa_insnbuf vbuf
= NULL
;
10461 xtensa_isa isa
= xtensa_default_isa
;
10465 const char *file_name
;
10468 file_name
= as_where (&line
);
10469 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10471 switch (fragp
->fr_subtype
)
10473 case RELAX_ALIGN_NEXT_OPCODE
:
10474 /* Always convert. */
10475 convert_frag_align_next_opcode (fragp
);
10478 case RELAX_DESIRE_ALIGN
:
10479 /* Do nothing. If not aligned already, too bad. */
10482 case RELAX_LITERAL
:
10483 case RELAX_LITERAL_FINAL
:
10488 vbuf
= xtensa_insnbuf_alloc (isa
);
10490 xtensa_insnbuf_from_chars
10491 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10492 fmt
= xtensa_format_decode (isa
, vbuf
);
10493 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10495 for (slot
= 0; slot
< num_slots
; slot
++)
10497 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10500 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10504 case RELAX_IMMED_STEP1
:
10505 case RELAX_IMMED_STEP2
:
10506 case RELAX_IMMED_STEP3
:
10507 /* Place the immediate. */
10510 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10515 /* This is OK because some slots could have
10516 relaxations and others have none. */
10522 case RELAX_UNREACHABLE
:
10523 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10524 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10525 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10529 case RELAX_MAYBE_UNREACHABLE
:
10530 case RELAX_MAYBE_DESIRE_ALIGN
:
10534 case RELAX_FILL_NOP
:
10535 convert_frag_fill_nop (fragp
);
10538 case RELAX_LITERAL_NR
:
10539 if (use_literal_section
)
10541 /* This should have been handled during relaxation. When
10542 relaxing a code segment, literals sometimes need to be
10543 added to the corresponding literal segment. If that
10544 literal segment has already been relaxed, then we end up
10545 in this situation. Marking the literal segments as data
10546 would make this happen less often (since GAS always relaxes
10547 code before data), but we could still get into trouble if
10548 there are instructions in a segment that is not marked as
10549 containing code. Until we can implement a better solution,
10550 cheat and adjust the addresses of all the following frags.
10551 This could break subsequent alignments, but the linker's
10552 literal coalescing will do that anyway. */
10555 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10556 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10557 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10558 fragp
->fr_var
-= 4;
10559 fragp
->fr_fix
+= 4;
10560 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10561 f
->fr_address
+= 4;
10564 as_bad (_("invalid relaxation fragment result"));
10567 case RELAX_TRAMPOLINE
:
10572 new_logical_line (file_name
, line
);
10577 convert_frag_align_next_opcode (fragS
*fragp
)
10579 char *nop_buf
; /* Location for Writing. */
10580 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10581 addressT aligned_address
;
10583 int nop
, nop_count
;
10585 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10587 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10588 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10589 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10591 for (nop
= 0; nop
< nop_count
; nop
++)
10594 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10596 assemble_nop (nop_size
, nop_buf
);
10597 nop_buf
+= nop_size
;
10600 fragp
->fr_fix
+= fill_size
;
10601 fragp
->fr_var
-= fill_size
;
10606 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10608 TInsn tinsn
, single_target
;
10609 int size
, old_size
, diff
;
10610 offsetT frag_offset
;
10612 gas_assert (slot
== 0);
10613 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10615 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10617 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10618 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10619 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10624 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10626 /* No conversion. */
10631 gas_assert (fragP
->fr_opcode
!= NULL
);
10633 /* Frags in this relaxation state should only contain
10634 single instruction bundles. */
10635 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10637 /* Just convert it to a wide form.... */
10639 old_size
= xg_get_single_size (tinsn
.opcode
);
10641 tinsn_init (&single_target
);
10642 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10644 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10646 as_bad (_("unable to widen instruction"));
10650 size
= xg_get_single_size (single_target
.opcode
);
10651 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10652 frag_offset
, TRUE
);
10654 diff
= size
- old_size
;
10655 gas_assert (diff
>= 0);
10656 gas_assert (diff
<= fragP
->fr_var
);
10657 fragP
->fr_var
-= diff
;
10658 fragP
->fr_fix
+= diff
;
10666 convert_frag_fill_nop (fragS
*fragP
)
10668 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10669 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10670 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10671 - fragP
->fr_address
- fragP
->fr_fix
));
10674 /* No conversion. */
10678 assemble_nop (size
, loc
);
10679 fragP
->tc_frag_data
.is_insn
= TRUE
;
10680 fragP
->fr_var
-= size
;
10681 fragP
->fr_fix
+= size
;
10686 static fixS
*fix_new_exp_in_seg
10687 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10688 bfd_reloc_code_real_type
);
10691 convert_frag_immed (segT segP
,
10697 char *immed_instr
= fragP
->fr_opcode
;
10699 bfd_boolean expanded
= FALSE
;
10700 bfd_boolean branch_jmp_to_next
= FALSE
;
10701 char *fr_opcode
= fragP
->fr_opcode
;
10702 xtensa_isa isa
= xtensa_default_isa
;
10703 bfd_boolean from_wide_insn
= FALSE
;
10705 bfd_boolean is_loop
;
10707 gas_assert (fr_opcode
!= NULL
);
10709 xg_clear_vinsn (&cur_vinsn
);
10711 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10712 if (cur_vinsn
.num_slots
> 1)
10713 from_wide_insn
= TRUE
;
10715 orig_tinsn
= cur_vinsn
.slots
[slot
];
10716 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10718 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10720 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10721 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10723 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10725 /* Conversion just inserts a NOP and marks the fix as completed. */
10726 bytes
= xtensa_format_length (isa
, fmt
);
10729 cur_vinsn
.slots
[slot
].opcode
=
10730 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10731 cur_vinsn
.slots
[slot
].ntok
= 0;
10735 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10736 gas_assert (bytes
== 2 || bytes
== 3);
10737 build_nop (&cur_vinsn
.slots
[0], bytes
);
10738 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10740 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10741 xtensa_insnbuf_to_chars
10742 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10747 /* Here is the fun stuff: Get the immediate field from this
10748 instruction. If it fits, we're done. If not, find the next
10749 instruction sequence that fits. */
10753 symbolS
*lit_sym
= NULL
;
10754 int total_size
= 0;
10755 int target_offset
= 0;
10758 symbolS
*gen_label
= NULL
;
10759 offsetT frag_offset
;
10760 bfd_boolean first
= TRUE
;
10762 /* It does not fit. Find something that does and
10763 convert immediately. */
10764 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10765 istack_init (&istack
);
10766 xg_assembly_relax (&istack
, &orig_tinsn
,
10767 segP
, fragP
, frag_offset
, min_steps
, 0);
10769 old_size
= xtensa_format_length (isa
, fmt
);
10771 /* Assemble this right inline. */
10773 /* First, create the mapping from a label name to the REAL label. */
10775 for (i
= 0; i
< istack
.ninsn
; i
++)
10777 TInsn
*tinsn
= &istack
.insn
[i
];
10780 switch (tinsn
->insn_type
)
10782 case ITYPE_LITERAL
:
10783 if (lit_sym
!= NULL
)
10784 as_bad (_("multiple literals in expansion"));
10785 /* First find the appropriate space in the literal pool. */
10786 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10787 if (lit_frag
== NULL
)
10788 as_bad (_("no registered fragment for literal"));
10789 if (tinsn
->ntok
!= 1)
10790 as_bad (_("number of literal tokens != 1"));
10792 /* Set the literal symbol and add a fixup. */
10793 lit_sym
= lit_frag
->fr_symbol
;
10797 if (align_targets
&& !is_loop
)
10799 fragS
*unreach
= fragP
->fr_next
;
10800 while (!(unreach
->fr_type
== rs_machine_dependent
10801 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10802 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10804 unreach
= unreach
->fr_next
;
10807 gas_assert (unreach
->fr_type
== rs_machine_dependent
10808 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10809 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10811 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10813 gas_assert (gen_label
== NULL
);
10814 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10815 fr_opcode
- fragP
->fr_literal
10816 + target_offset
, fragP
);
10820 if (first
&& from_wide_insn
)
10822 target_offset
+= xtensa_format_length (isa
, fmt
);
10824 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10825 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10828 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10835 for (i
= 0; i
< istack
.ninsn
; i
++)
10837 TInsn
*tinsn
= &istack
.insn
[i
];
10841 bfd_reloc_code_real_type reloc_type
;
10843 switch (tinsn
->insn_type
)
10845 case ITYPE_LITERAL
:
10846 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10847 /* Already checked. */
10848 gas_assert (lit_frag
!= NULL
);
10849 gas_assert (lit_sym
!= NULL
);
10850 gas_assert (tinsn
->ntok
== 1);
10852 target_seg
= S_GET_SEGMENT (lit_sym
);
10853 gas_assert (target_seg
);
10854 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10855 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10856 &tinsn
->tok
[0], FALSE
, reloc_type
);
10863 xg_resolve_labels (tinsn
, gen_label
);
10864 xg_resolve_literals (tinsn
, lit_sym
);
10865 if (from_wide_insn
&& first
)
10868 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10870 cur_vinsn
.slots
[slot
] = *tinsn
;
10874 cur_vinsn
.slots
[slot
].opcode
=
10875 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10876 cur_vinsn
.slots
[slot
].ntok
= 0;
10878 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10879 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10880 (unsigned char *) immed_instr
, 0);
10881 fragP
->tc_frag_data
.is_insn
= TRUE
;
10882 size
= xtensa_format_length (isa
, fmt
);
10883 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10885 xg_emit_insn_to_buf
10886 (tinsn
, immed_instr
+ size
, fragP
,
10887 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10888 size
+= xg_get_single_size (tinsn
->opcode
);
10893 size
= xg_get_single_size (tinsn
->opcode
);
10894 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10895 immed_instr
- fragP
->fr_literal
, TRUE
);
10897 immed_instr
+= size
;
10898 total_size
+= size
;
10903 diff
= total_size
- old_size
;
10904 gas_assert (diff
>= 0);
10907 gas_assert (diff
<= fragP
->fr_var
);
10908 fragP
->fr_var
-= diff
;
10909 fragP
->fr_fix
+= diff
;
10912 /* Check for undefined immediates in LOOP instructions. */
10916 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10917 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10919 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10922 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10923 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10925 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10930 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10932 /* Add an expansion note on the expanded instruction. */
10933 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10934 &orig_tinsn
.tok
[0], TRUE
,
10935 BFD_RELOC_XTENSA_ASM_EXPAND
);
10940 /* Add a new fix expression into the desired segment. We have to
10941 switch to that segment to do this. */
10944 fix_new_exp_in_seg (segT new_seg
,
10945 subsegT new_subseg
,
10951 bfd_reloc_code_real_type r_type
)
10954 segT seg
= now_seg
;
10955 subsegT subseg
= now_subseg
;
10957 gas_assert (new_seg
!= 0);
10958 subseg_set (new_seg
, new_subseg
);
10960 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10961 subseg_set (seg
, subseg
);
10967 /* A map that keeps information on a per-subsegment basis. This is
10968 maintained during initial assembly, but is invalid once the
10969 subsegments are smashed together. I.E., it cannot be used during
10972 typedef struct subseg_map_struct
10980 float total_freq
; /* fall-through + branch target frequency */
10981 float target_freq
; /* branch target frequency alone */
10983 struct subseg_map_struct
*next
;
10987 static subseg_map
*sseg_map
= NULL
;
10989 static subseg_map
*
10990 get_subseg_info (segT seg
, subsegT subseg
)
10992 subseg_map
*subseg_e
;
10994 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10996 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
11003 static subseg_map
*
11004 add_subseg_info (segT seg
, subsegT subseg
)
11006 subseg_map
*subseg_e
= XNEW (subseg_map
);
11007 memset (subseg_e
, 0, sizeof (subseg_map
));
11008 subseg_e
->seg
= seg
;
11009 subseg_e
->subseg
= subseg
;
11010 subseg_e
->flags
= 0;
11011 /* Start off considering every branch target very important. */
11012 subseg_e
->target_freq
= 1.0;
11013 subseg_e
->total_freq
= 1.0;
11014 subseg_e
->next
= sseg_map
;
11015 sseg_map
= subseg_e
;
11021 get_last_insn_flags (segT seg
, subsegT subseg
)
11023 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11025 return subseg_e
->flags
;
11031 set_last_insn_flags (segT seg
,
11036 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11038 subseg_e
= add_subseg_info (seg
, subseg
);
11040 subseg_e
->flags
|= fl
;
11042 subseg_e
->flags
&= ~fl
;
11047 get_subseg_total_freq (segT seg
, subsegT subseg
)
11049 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11051 return subseg_e
->total_freq
;
11057 get_subseg_target_freq (segT seg
, subsegT subseg
)
11059 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11061 return subseg_e
->target_freq
;
11067 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11069 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11071 subseg_e
= add_subseg_info (seg
, subseg
);
11072 subseg_e
->total_freq
= total_f
;
11073 subseg_e
->target_freq
= target_f
;
11077 /* Segment Lists and emit_state Stuff. */
11080 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11085 segT literal_section
= head
->seg
;
11087 /* Move the literal section to the front of the section list. */
11088 gas_assert (literal_section
);
11089 if (literal_section
!= stdoutput
->sections
)
11091 bfd_section_list_remove (stdoutput
, literal_section
);
11092 bfd_section_list_prepend (stdoutput
, literal_section
);
11099 static void mark_literal_frags (seg_list
*);
11102 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11103 struct litpool_frag
*lp
)
11108 char label
[10 + 2 * sizeof (fragS
*)];
11110 poolbeg
= lp
->fragP
;
11112 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11113 poolend
= poolbeg
->fr_next
;
11114 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11115 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11116 /* Create a local symbol pointing to the
11117 end of the pool. */
11118 sprintf (label
, ".L0_LT_%p", poolbeg
);
11119 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11121 poolbeg
->fr_symbol
= lsym
;
11122 /* Rest is done in xtensa_relax_frag. */
11125 static struct litpool_frag
*xg_find_litpool (struct litpool_seg
*lps
,
11126 struct litpool_frag
*lpf
,
11129 struct litpool_frag
*lp
= lpf
->prev
;
11131 gas_assert (lp
->fragP
);
11133 while (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11136 if (lp
->fragP
== NULL
)
11138 /* End of list; have to bite the bullet.
11139 Take the nearest. */
11143 /* Does it (conservatively) reach? */
11144 if (addr
- lp
->addr
<= 128 * 1024)
11146 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
11147 lp
->literal_count
< MAX_POOL_LITERALS
)
11149 /* Found a good one. */
11152 else if (lp
->prev
->fragP
&&
11153 addr
- lp
->prev
->addr
> 128 * 1024 &&
11154 lp
->prev
->literal_count
< MAX_POOL_LITERALS
)
11156 /* This is still a "candidate" but the next one
11157 will be too far away, so revert to the nearest
11158 one, convert it and add the jump around. */
11165 if (lp
->literal_count
>= MAX_POOL_LITERALS
)
11168 while (lp
&& lp
->fragP
&& lp
->literal_count
>= MAX_POOL_LITERALS
)
11175 gas_assert (lp
&& lp
->fragP
&& lp
->literal_count
< MAX_POOL_LITERALS
);
11176 ++lp
->literal_count
;
11178 /* Convert candidate and add the jump around. */
11179 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11180 xg_promote_candidate_litpool (lps
, lp
);
11185 static bfd_boolean
xtensa_is_init_fini (segT seg
)
11189 return strcmp (segment_name (seg
), INIT_SECTION_NAME
) == 0
11190 || strcmp (segment_name (seg
), FINI_SECTION_NAME
) == 0;
11194 xtensa_assign_litpool_addresses (void)
11196 struct litpool_seg
*lps
;
11198 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11200 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11201 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11204 if (xtensa_is_init_fini (lps
->seg
))
11207 for ( ; frchP
; frchP
= frchP
->frch_next
)
11210 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11212 if (lpf
&& fragP
== lpf
->fragP
)
11214 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11215 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11216 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11217 /* Found a litpool location. */
11221 if (fragP
->fr_type
== rs_machine_dependent
&&
11222 fragP
->fr_subtype
== RELAX_SLOTS
)
11225 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11227 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11230 && litfrag
->tc_frag_data
.is_literal
11231 && !litfrag
->tc_frag_data
.literal_frag
)
11233 /* L32R referring .literal or generated as a result
11234 of relaxation. Point its literal to the nearest
11235 litpool preferring non-"candidate" positions to
11236 avoid the jump-around. */
11238 struct litpool_frag
*lp
;
11240 lp
= xg_find_litpool (lps
, lpf
, addr
);
11241 /* Take earliest use of this literal to avoid
11243 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11247 addr
+= fragP
->fr_fix
;
11248 if (fragP
->fr_type
== rs_fill
)
11249 addr
+= fragP
->fr_offset
;
11256 xtensa_move_literals (void)
11259 frchainS
*frchain_from
, *frchain_to
;
11260 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11261 fragS
**frag_splice
;
11264 fixS
*fix
, *next_fix
, **fix_splice
;
11266 const char *init_name
= INIT_SECTION_NAME
;
11267 const char *fini_name
= FINI_SECTION_NAME
;
11268 int init_name_len
= strlen(init_name
);
11269 int fini_name_len
= strlen(fini_name
);
11271 mark_literal_frags (literal_head
->next
);
11273 if (use_literal_section
)
11276 /* Assign addresses (rough estimates) to the potential literal pool locations
11277 and create new ones if the gaps are too large. */
11279 xtensa_assign_litpool_addresses ();
11281 /* Walk through the literal segments. */
11282 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11284 const char *seg_name
= segment_name (segment
->seg
);
11286 /* Keep the literals for .init and .fini in separate sections. */
11287 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11288 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11289 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11290 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11293 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11294 search_frag
= frchain_from
->frch_root
;
11295 literal_pool
= NULL
;
11297 frag_splice
= &(frchain_from
->frch_root
);
11299 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11301 gas_assert (search_frag
->fr_fix
== 0
11302 || search_frag
->fr_type
== rs_align
);
11303 search_frag
= search_frag
->fr_next
;
11309 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11310 == RELAX_LITERAL_POOL_BEGIN
);
11311 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11313 /* Make sure that all the frags in this series are closed, and
11314 that there is at least one left over of zero-size. This
11315 prevents us from making a segment with an frchain without any
11317 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11318 xtensa_set_frag_assembly_state (frag_now
);
11319 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11320 xtensa_set_frag_assembly_state (frag_now
);
11322 while (search_frag
!= frag_now
)
11324 next_frag
= search_frag
->fr_next
;
11325 if (search_frag
->tc_frag_data
.literal_frag
)
11327 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11328 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11329 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11330 gas_assert (frchain_to
);
11333 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11335 /* Skip empty fill frags. */
11336 *frag_splice
= next_frag
;
11337 search_frag
= next_frag
;
11341 if (search_frag
->fr_type
== rs_align
)
11343 /* Skip alignment frags, because the pool as a whole will be
11344 aligned if used, and we don't want to force alignment if the
11346 *frag_splice
= next_frag
;
11347 search_frag
= next_frag
;
11351 /* First, move the frag out of the literal section and
11352 to the appropriate place. */
11354 /* Insert an alignment frag at start of pool. */
11355 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11356 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11358 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11359 emit_state prev_state
;
11362 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11363 prev_frag
= frag_now
;
11364 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11365 align_frag
= frag_now
;
11366 frag_align (2, 0, 0);
11367 /* Splice it into the right place. */
11368 prev_frag
->fr_next
= align_frag
->fr_next
;
11369 align_frag
->fr_next
= literal_pool
->fr_next
;
11370 literal_pool
->fr_next
= align_frag
;
11371 /* Insert after this one. */
11372 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11373 xtensa_restore_emit_state (&prev_state
);
11375 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11376 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11377 /* Skip align frag. */
11378 if (insert_after
->fr_next
->fr_type
== rs_align
)
11380 insert_after
= insert_after
->fr_next
;
11383 *frag_splice
= next_frag
;
11384 search_frag
->fr_next
= insert_after
->fr_next
;
11385 insert_after
->fr_next
= search_frag
;
11386 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11387 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11389 /* Now move any fixups associated with this frag to the
11391 fix
= frchain_from
->fix_root
;
11392 fix_splice
= &(frchain_from
->fix_root
);
11395 next_fix
= fix
->fx_next
;
11396 if (fix
->fx_frag
== search_frag
)
11398 *fix_splice
= next_fix
;
11399 fix
->fx_next
= frchain_to
->fix_root
;
11400 frchain_to
->fix_root
= fix
;
11401 if (frchain_to
->fix_tail
== NULL
)
11402 frchain_to
->fix_tail
= fix
;
11405 fix_splice
= &(fix
->fx_next
);
11408 search_frag
= next_frag
;
11411 if (frchain_from
->fix_root
!= NULL
)
11413 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11414 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11416 gas_assert (frchain_from
->fix_root
== NULL
);
11418 frchain_from
->fix_tail
= NULL
;
11419 xtensa_restore_emit_state (&state
);
11422 /* Now fix up the SEGMENT value for all the literal symbols. */
11423 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11425 symbolS
*lit_sym
= lit
->sym
;
11426 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11428 S_SET_SEGMENT (lit_sym
, dseg
);
11433 /* Walk over all the frags for segments in a list and mark them as
11434 containing literals. As clunky as this is, we can't rely on frag_var
11435 and frag_variant to get called in all situations. */
11438 mark_literal_frags (seg_list
*segment
)
11440 frchainS
*frchain_from
;
11441 fragS
*search_frag
;
11445 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11446 search_frag
= frchain_from
->frch_root
;
11447 while (search_frag
)
11449 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11450 search_frag
= search_frag
->fr_next
;
11452 segment
= segment
->next
;
11458 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11460 /* Move all of the sections in the section list to come
11461 after "after" in the gnu segment list. */
11466 segT literal_section
= head
->seg
;
11468 /* Move the literal section after "after". */
11469 gas_assert (literal_section
);
11470 if (literal_section
!= after
)
11472 bfd_section_list_remove (stdoutput
, literal_section
);
11473 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11481 /* Push all the literal segments to the end of the gnu list. */
11484 xtensa_reorder_segments (void)
11491 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11497 /* Now that we have the last section, push all the literal
11498 sections to the end. */
11499 xtensa_reorder_seg_list (literal_head
, last_sec
);
11501 /* Now perform the final error check. */
11502 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11504 gas_assert (new_count
== old_count
);
11508 /* Change the emit state (seg, subseg, and frag related stuff) to the
11509 correct location. Return a emit_state which can be passed to
11510 xtensa_restore_emit_state to return to current fragment. */
11513 xtensa_switch_to_literal_fragment (emit_state
*result
)
11515 if (directive_state
[directive_absolute_literals
])
11517 segT lit4_seg
= cache_literal_section (TRUE
);
11518 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11521 xtensa_switch_to_non_abs_literal_fragment (result
);
11523 /* Do a 4-byte align here. */
11524 frag_align (2, 0, 0);
11525 record_alignment (now_seg
, 2);
11530 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11532 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11534 bfd_boolean is_init_fini
= xtensa_is_init_fini (now_seg
);
11536 if (pool_location
== NULL
11537 && !use_literal_section
11540 if (!auto_litpools
)
11542 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11544 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11545 pool_location
= get_literal_pool_location (now_seg
);
11548 lit_seg
= cache_literal_section (FALSE
);
11549 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11551 if (!use_literal_section
11553 && get_literal_pool_location (now_seg
) != pool_location
)
11555 /* Close whatever frag is there. */
11556 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11557 xtensa_set_frag_assembly_state (frag_now
);
11558 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11559 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11560 xtensa_set_frag_assembly_state (frag_now
);
11565 /* Call this function before emitting data into the literal section.
11566 This is a helper function for xtensa_switch_to_literal_fragment.
11567 This is similar to a .section new_now_seg subseg. */
11570 xtensa_switch_section_emit_state (emit_state
*state
,
11572 subsegT new_now_subseg
)
11574 state
->name
= now_seg
->name
;
11575 state
->now_seg
= now_seg
;
11576 state
->now_subseg
= now_subseg
;
11577 state
->generating_literals
= generating_literals
;
11578 generating_literals
++;
11579 subseg_set (new_now_seg
, new_now_subseg
);
11583 /* Use to restore the emitting into the normal place. */
11586 xtensa_restore_emit_state (emit_state
*state
)
11588 generating_literals
= state
->generating_literals
;
11589 subseg_set (state
->now_seg
, state
->now_subseg
);
11593 /* Predicate function used to look up a section in a particular group. */
11596 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11598 const char *gname
= inf
;
11599 const char *group_name
= elf_group_name (sec
);
11601 return (group_name
== gname
11602 || (group_name
!= NULL
11604 && strcmp (group_name
, gname
) == 0));
11608 /* Get the literal section to be used for the current text section.
11609 The result may be cached in the default_lit_sections structure. */
11612 cache_literal_section (bfd_boolean use_abs_literals
)
11614 const char *text_name
, *group_name
= 0;
11615 const char *base_name
, *suffix
;
11618 segT seg
, current_section
;
11619 int current_subsec
;
11620 bfd_boolean linkonce
= FALSE
;
11622 /* Save the current section/subsection. */
11623 current_section
= now_seg
;
11624 current_subsec
= now_subseg
;
11626 /* Clear the cached values if they are no longer valid. */
11627 if (now_seg
!= default_lit_sections
.current_text_seg
)
11629 default_lit_sections
.current_text_seg
= now_seg
;
11630 default_lit_sections
.lit_seg
= NULL
;
11631 default_lit_sections
.lit4_seg
= NULL
;
11634 /* Check if the literal section is already cached. */
11635 if (use_abs_literals
)
11636 pcached
= &default_lit_sections
.lit4_seg
;
11638 pcached
= &default_lit_sections
.lit_seg
;
11643 text_name
= default_lit_sections
.lit_prefix
;
11644 if (! text_name
|| ! *text_name
)
11646 text_name
= segment_name (current_section
);
11647 group_name
= elf_group_name (current_section
);
11648 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11651 base_name
= use_abs_literals
? ".lit4" : ".literal";
11654 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11656 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11658 suffix
= strchr (text_name
+ linkonce_len
, '.');
11660 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11666 /* If the section name begins or ends with ".text", then replace
11667 that portion instead of appending an additional suffix. */
11668 size_t len
= strlen (text_name
);
11670 && (strcmp (text_name
+ len
- 5, ".text") == 0
11671 || strncmp (text_name
, ".text", 5) == 0))
11674 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11675 if (strncmp (text_name
, ".text", 5) == 0)
11677 strcpy (name
, base_name
);
11678 strcat (name
, text_name
+ 5);
11682 strcpy (name
, text_name
);
11683 strcpy (name
+ len
, base_name
);
11687 /* Canonicalize section names to allow renaming literal sections.
11688 The group name, if any, came from the current text section and
11689 has already been canonicalized. */
11690 name
= tc_canonicalize_symbol_name (name
);
11692 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11693 (void *) group_name
);
11698 seg
= subseg_force_new (name
, 0);
11700 if (! use_abs_literals
)
11702 /* Add the newly created literal segment to the list. */
11703 seg_list
*n
= XNEW (seg_list
);
11705 n
->next
= literal_head
->next
;
11706 literal_head
->next
= n
;
11709 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11710 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11711 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11713 elf_group_name (seg
) = group_name
;
11715 bfd_set_section_flags (seg
, flags
);
11716 bfd_set_section_alignment (seg
, 2);
11720 subseg_set (current_section
, current_subsec
);
11725 /* Property Tables Stuff. */
11727 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11728 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11729 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11731 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11732 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11734 static bfd_boolean
get_frag_is_literal (const fragS
*);
11735 static void xtensa_create_property_segments
11736 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11737 static void xtensa_create_xproperty_segments
11738 (frag_flags_fn
, const char *, xt_section_type
);
11739 static bfd_boolean
exclude_section_from_property_tables (segT
);
11740 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11741 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11742 static void add_xt_block_frags
11743 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11744 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11745 static void xtensa_frag_flags_init (frag_flags
*);
11746 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11747 static flagword
frag_flags_to_number (const frag_flags
*);
11748 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11750 /* Set up property tables after relaxation. */
11753 xtensa_post_relax_hook (void)
11755 xtensa_move_seg_list_to_beginning (literal_head
);
11757 xtensa_find_unmarked_state_frags ();
11758 xtensa_mark_frags_for_org ();
11759 xtensa_mark_difference_of_two_symbols ();
11761 xtensa_create_property_segments (get_frag_is_literal
,
11763 XTENSA_LIT_SEC_NAME
,
11765 xtensa_create_xproperty_segments (get_frag_property_flags
,
11766 XTENSA_PROP_SEC_NAME
,
11769 if (warn_unaligned_branch_targets
)
11770 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11771 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11775 /* This function is only meaningful after xtensa_move_literals. */
11778 get_frag_is_literal (const fragS
*fragP
)
11780 gas_assert (fragP
!= NULL
);
11781 return fragP
->tc_frag_data
.is_literal
;
11786 xtensa_create_property_segments (frag_predicate property_function
,
11787 frag_predicate end_property_function
,
11788 const char *section_name_base
,
11789 xt_section_type sec_type
)
11793 /* Walk over all of the current segments.
11794 Walk over each fragment
11795 For each non-empty fragment,
11796 Build a property record (append where possible). */
11798 for (seclist
= &stdoutput
->sections
;
11799 seclist
&& *seclist
;
11800 seclist
= &(*seclist
)->next
)
11802 segT sec
= *seclist
;
11804 if (exclude_section_from_property_tables (sec
))
11807 if (section_has_property (sec
, property_function
))
11809 segment_info_type
*xt_seg_info
;
11810 xtensa_block_info
**xt_blocks
;
11811 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11813 prop_sec
->output_section
= prop_sec
;
11814 subseg_set (prop_sec
, 0);
11815 xt_seg_info
= seg_info (prop_sec
);
11816 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11818 /* Walk over all of the frchains here and add new sections. */
11819 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11820 end_property_function
);
11824 /* Now we fill them out.... */
11826 for (seclist
= &stdoutput
->sections
;
11827 seclist
&& *seclist
;
11828 seclist
= &(*seclist
)->next
)
11830 segment_info_type
*seginfo
;
11831 xtensa_block_info
*block
;
11832 segT sec
= *seclist
;
11834 seginfo
= seg_info (sec
);
11835 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11839 xtensa_block_info
*cur_block
;
11841 bfd_size_type rec_size
;
11843 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11846 rec_size
= num_recs
* 8;
11847 bfd_set_section_size (sec
, rec_size
);
11854 subseg_set (sec
, 0);
11855 frag_data
= frag_more (rec_size
);
11857 for (i
= 0; i
< num_recs
; i
++)
11861 /* Write the fixup. */
11862 gas_assert (cur_block
);
11863 fix
= fix_new (frag_now
, i
* 8, 4,
11864 section_symbol (cur_block
->sec
),
11866 FALSE
, BFD_RELOC_32
);
11867 fix
->fx_file
= "<internal>";
11870 /* Write the length. */
11871 md_number_to_chars (&frag_data
[4 + i
* 8],
11872 cur_block
->size
, 4);
11873 cur_block
= cur_block
->next
;
11875 frag_wane (frag_now
);
11877 frag_wane (frag_now
);
11885 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11886 const char *section_name_base
,
11887 xt_section_type sec_type
)
11891 /* Walk over all of the current segments.
11892 Walk over each fragment.
11893 For each fragment that has instructions,
11894 build an instruction record (append where possible). */
11896 for (seclist
= &stdoutput
->sections
;
11897 seclist
&& *seclist
;
11898 seclist
= &(*seclist
)->next
)
11900 segT sec
= *seclist
;
11902 if (exclude_section_from_property_tables (sec
))
11905 if (section_has_xproperty (sec
, flag_fn
))
11907 segment_info_type
*xt_seg_info
;
11908 xtensa_block_info
**xt_blocks
;
11909 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11911 prop_sec
->output_section
= prop_sec
;
11912 subseg_set (prop_sec
, 0);
11913 xt_seg_info
= seg_info (prop_sec
);
11914 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11916 /* Walk over all of the frchains here and add new sections. */
11917 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11921 /* Now we fill them out.... */
11923 for (seclist
= &stdoutput
->sections
;
11924 seclist
&& *seclist
;
11925 seclist
= &(*seclist
)->next
)
11927 segment_info_type
*seginfo
;
11928 xtensa_block_info
*block
;
11929 segT sec
= *seclist
;
11931 seginfo
= seg_info (sec
);
11932 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11936 xtensa_block_info
*cur_block
;
11938 bfd_size_type rec_size
;
11940 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11943 rec_size
= num_recs
* (8 + 4);
11944 bfd_set_section_size (sec
, rec_size
);
11945 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11952 subseg_set (sec
, 0);
11953 frag_data
= frag_more (rec_size
);
11955 for (i
= 0; i
< num_recs
; i
++)
11959 /* Write the fixup. */
11960 gas_assert (cur_block
);
11961 fix
= fix_new (frag_now
, i
* 12, 4,
11962 section_symbol (cur_block
->sec
),
11964 FALSE
, BFD_RELOC_32
);
11965 fix
->fx_file
= "<internal>";
11968 /* Write the length. */
11969 md_number_to_chars (&frag_data
[4 + i
* 12],
11970 cur_block
->size
, 4);
11971 md_number_to_chars (&frag_data
[8 + i
* 12],
11972 frag_flags_to_number (&cur_block
->flags
),
11973 sizeof (flagword
));
11974 cur_block
= cur_block
->next
;
11976 frag_wane (frag_now
);
11978 frag_wane (frag_now
);
11986 exclude_section_from_property_tables (segT sec
)
11988 flagword flags
= bfd_section_flags (sec
);
11990 /* Sections that don't contribute to the memory footprint are excluded. */
11991 if ((flags
& SEC_DEBUGGING
)
11992 || !(flags
& SEC_ALLOC
)
11993 || (flags
& SEC_MERGE
))
11996 /* Linker cie and fde optimizations mess up property entries for
11997 eh_frame sections, but there is nothing inside them relevant to
11998 property tables anyway. */
11999 if (strcmp (sec
->name
, ".eh_frame") == 0)
12007 section_has_property (segT sec
, frag_predicate property_function
)
12009 segment_info_type
*seginfo
= seg_info (sec
);
12012 if (seginfo
&& seginfo
->frchainP
)
12014 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12016 if (property_function (fragP
)
12017 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12026 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
12028 segment_info_type
*seginfo
= seg_info (sec
);
12031 if (seginfo
&& seginfo
->frchainP
)
12033 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12035 frag_flags prop_flags
;
12036 property_function (fragP
, &prop_flags
);
12037 if (!xtensa_frag_flags_is_empty (&prop_flags
))
12045 /* Two types of block sections exist right now: literal and insns. */
12048 add_xt_block_frags (segT sec
,
12049 xtensa_block_info
**xt_block
,
12050 frag_predicate property_function
,
12051 frag_predicate end_property_function
)
12055 /* Build it if needed. */
12056 while (*xt_block
!= NULL
)
12057 xt_block
= &(*xt_block
)->next
;
12058 /* We are either at NULL at the beginning or at the end. */
12060 /* Walk through the frags. */
12061 if (seg_info (sec
)->frchainP
)
12063 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
12065 fragP
= fragP
->fr_next
)
12067 if (property_function (fragP
)
12068 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12070 if (*xt_block
!= NULL
)
12072 if ((*xt_block
)->offset
+ (*xt_block
)->size
12073 == fragP
->fr_address
)
12074 (*xt_block
)->size
+= fragP
->fr_fix
;
12076 xt_block
= &((*xt_block
)->next
);
12078 if (*xt_block
== NULL
)
12080 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
12081 new_block
->sec
= sec
;
12082 new_block
->offset
= fragP
->fr_address
;
12083 new_block
->size
= fragP
->fr_fix
;
12084 new_block
->next
= NULL
;
12085 xtensa_frag_flags_init (&new_block
->flags
);
12086 *xt_block
= new_block
;
12088 if (end_property_function
12089 && end_property_function (fragP
))
12091 xt_block
= &((*xt_block
)->next
);
12099 /* Break the encapsulation of add_xt_prop_frags here. */
12102 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12104 if (prop_flags
->is_literal
12105 || prop_flags
->is_insn
12106 || prop_flags
->is_data
12107 || prop_flags
->is_unreachable
)
12114 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12116 memset (prop_flags
, 0, sizeof (frag_flags
));
12121 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12123 xtensa_frag_flags_init (prop_flags
);
12124 if (fragP
->tc_frag_data
.is_literal
)
12125 prop_flags
->is_literal
= TRUE
;
12126 if (fragP
->tc_frag_data
.is_specific_opcode
12127 || fragP
->tc_frag_data
.is_no_transform
)
12129 prop_flags
->is_no_transform
= TRUE
;
12130 if (xtensa_frag_flags_is_empty (prop_flags
))
12131 prop_flags
->is_data
= TRUE
;
12133 if (fragP
->tc_frag_data
.is_unreachable
)
12134 prop_flags
->is_unreachable
= TRUE
;
12135 else if (fragP
->tc_frag_data
.is_insn
)
12137 prop_flags
->is_insn
= TRUE
;
12138 if (fragP
->tc_frag_data
.is_loop_target
)
12139 prop_flags
->insn
.is_loop_target
= TRUE
;
12140 if (fragP
->tc_frag_data
.is_branch_target
)
12141 prop_flags
->insn
.is_branch_target
= TRUE
;
12142 if (fragP
->tc_frag_data
.is_no_density
)
12143 prop_flags
->insn
.is_no_density
= TRUE
;
12144 if (fragP
->tc_frag_data
.use_absolute_literals
)
12145 prop_flags
->insn
.is_abslit
= TRUE
;
12147 if (fragP
->tc_frag_data
.is_align
)
12149 prop_flags
->is_align
= TRUE
;
12150 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12151 if (xtensa_frag_flags_is_empty (prop_flags
))
12152 prop_flags
->is_data
= TRUE
;
12158 frag_flags_to_number (const frag_flags
*prop_flags
)
12161 if (prop_flags
->is_literal
)
12162 num
|= XTENSA_PROP_LITERAL
;
12163 if (prop_flags
->is_insn
)
12164 num
|= XTENSA_PROP_INSN
;
12165 if (prop_flags
->is_data
)
12166 num
|= XTENSA_PROP_DATA
;
12167 if (prop_flags
->is_unreachable
)
12168 num
|= XTENSA_PROP_UNREACHABLE
;
12169 if (prop_flags
->insn
.is_loop_target
)
12170 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12171 if (prop_flags
->insn
.is_branch_target
)
12173 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12174 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12177 if (prop_flags
->insn
.is_no_density
)
12178 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12179 if (prop_flags
->is_no_transform
)
12180 num
|= XTENSA_PROP_NO_TRANSFORM
;
12181 if (prop_flags
->insn
.is_no_reorder
)
12182 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12183 if (prop_flags
->insn
.is_abslit
)
12184 num
|= XTENSA_PROP_INSN_ABSLIT
;
12186 if (prop_flags
->is_align
)
12188 num
|= XTENSA_PROP_ALIGN
;
12189 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12197 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12198 const frag_flags
*prop_flags_2
)
12200 /* Cannot combine with an end marker. */
12202 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12204 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12206 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12209 if (prop_flags_1
->is_insn
)
12211 /* Properties of the beginning of the frag. */
12212 if (prop_flags_2
->insn
.is_loop_target
)
12214 if (prop_flags_2
->insn
.is_branch_target
)
12216 if (prop_flags_1
->insn
.is_no_density
!=
12217 prop_flags_2
->insn
.is_no_density
)
12219 if (prop_flags_1
->is_no_transform
!=
12220 prop_flags_2
->is_no_transform
)
12222 if (prop_flags_1
->insn
.is_no_reorder
!=
12223 prop_flags_2
->insn
.is_no_reorder
)
12225 if (prop_flags_1
->insn
.is_abslit
!=
12226 prop_flags_2
->insn
.is_abslit
)
12230 if (prop_flags_1
->is_align
)
12238 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12241 unsigned align_bits
;
12243 if (!xt_block
->flags
.is_align
)
12244 return xt_block
->size
;
12246 end_addr
= xt_block
->offset
+ xt_block
->size
;
12247 align_bits
= xt_block
->flags
.alignment
;
12248 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12249 return end_addr
- xt_block
->offset
;
12254 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12255 const xtensa_block_info
*xt_block_2
)
12257 if (xt_block
->sec
!= xt_block_2
->sec
)
12259 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12260 != xt_block_2
->offset
)
12263 if (xt_block_2
->size
== 0
12264 && (!xt_block_2
->flags
.is_unreachable
12265 || xt_block
->flags
.is_unreachable
))
12267 if (xt_block_2
->flags
.is_align
12268 && xt_block
->flags
.is_align
)
12270 /* Nothing needed. */
12271 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12276 if (xt_block_2
->flags
.is_align
)
12278 /* Push alignment to previous entry. */
12279 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12280 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12285 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12286 &xt_block_2
->flags
))
12289 xt_block
->size
+= xt_block_2
->size
;
12291 if (xt_block_2
->flags
.is_align
)
12293 xt_block
->flags
.is_align
= TRUE
;
12294 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12302 add_xt_prop_frags (segT sec
,
12303 xtensa_block_info
**xt_block
,
12304 frag_flags_fn property_function
)
12308 /* Build it if needed. */
12309 while (*xt_block
!= NULL
)
12311 xt_block
= &(*xt_block
)->next
;
12313 /* We are either at NULL at the beginning or at the end. */
12315 /* Walk through the frags. */
12316 if (seg_info (sec
)->frchainP
)
12318 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12319 fragP
= fragP
->fr_next
)
12321 xtensa_block_info tmp_block
;
12322 tmp_block
.sec
= sec
;
12323 tmp_block
.offset
= fragP
->fr_address
;
12324 tmp_block
.size
= fragP
->fr_fix
;
12325 tmp_block
.next
= NULL
;
12326 property_function (fragP
, &tmp_block
.flags
);
12328 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12329 /* && fragP->fr_fix != 0) */
12331 if ((*xt_block
) == NULL
12332 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12334 xtensa_block_info
*new_block
;
12335 if ((*xt_block
) != NULL
)
12336 xt_block
= &(*xt_block
)->next
;
12337 new_block
= XNEW (xtensa_block_info
);
12338 *new_block
= tmp_block
;
12339 *xt_block
= new_block
;
12347 /* op_placement_info_table */
12349 /* op_placement_info makes it easier to determine which
12350 ops can go in which slots. */
12353 init_op_placement_info_table (void)
12355 xtensa_isa isa
= xtensa_default_isa
;
12356 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12357 xtensa_opcode opcode
;
12360 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12362 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12363 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12365 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12367 op_placement_info
*opi
= &op_placement_table
[opcode
];
12368 /* FIXME: Make tinsn allocation dynamic. */
12369 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12370 as_fatal (_("too many operands in instruction"));
12371 opi
->narrowest
= XTENSA_UNDEFINED
;
12372 opi
->narrowest_size
= 0x7F;
12373 opi
->narrowest_slot
= 0;
12375 opi
->num_formats
= 0;
12377 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12379 opi
->slots
[fmt
] = 0;
12380 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12382 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12384 int fmt_length
= xtensa_format_length (isa
, fmt
);
12386 set_bit (fmt
, opi
->formats
);
12387 set_bit (slot
, opi
->slots
[fmt
]);
12388 if (fmt_length
< opi
->narrowest_size
12389 || (fmt_length
== opi
->narrowest_size
12390 && (xtensa_format_num_slots (isa
, fmt
)
12391 < xtensa_format_num_slots (isa
,
12394 opi
->narrowest
= fmt
;
12395 opi
->narrowest_size
= fmt_length
;
12396 opi
->narrowest_slot
= slot
;
12401 opi
->num_formats
++;
12404 xtensa_insnbuf_free (isa
, ibuf
);
12409 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12411 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12415 /* If the opcode is available in a single slot format, return its size. */
12418 xg_get_single_size (xtensa_opcode opcode
)
12420 return op_placement_table
[opcode
].narrowest_size
;
12424 static xtensa_format
12425 xg_get_single_format (xtensa_opcode opcode
)
12427 return op_placement_table
[opcode
].narrowest
;
12432 xg_get_single_slot (xtensa_opcode opcode
)
12434 return op_placement_table
[opcode
].narrowest_slot
;
12438 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12441 istack_init (IStack
*stack
)
12448 istack_empty (IStack
*stack
)
12450 return (stack
->ninsn
== 0);
12455 istack_full (IStack
*stack
)
12457 return (stack
->ninsn
== MAX_ISTACK
);
12461 /* Return a pointer to the top IStack entry.
12462 It is an error to call this if istack_empty () is TRUE. */
12465 istack_top (IStack
*stack
)
12467 int rec
= stack
->ninsn
- 1;
12468 gas_assert (!istack_empty (stack
));
12469 return &stack
->insn
[rec
];
12473 /* Add a new TInsn to an IStack.
12474 It is an error to call this if istack_full () is TRUE. */
12477 istack_push (IStack
*stack
, TInsn
*insn
)
12479 int rec
= stack
->ninsn
;
12480 gas_assert (!istack_full (stack
));
12481 stack
->insn
[rec
] = *insn
;
12486 /* Clear space for the next TInsn on the IStack and return a pointer
12487 to it. It is an error to call this if istack_full () is TRUE. */
12490 istack_push_space (IStack
*stack
)
12492 int rec
= stack
->ninsn
;
12494 gas_assert (!istack_full (stack
));
12495 insn
= &stack
->insn
[rec
];
12502 /* Remove the last pushed instruction. It is an error to call this if
12503 istack_empty () returns TRUE. */
12506 istack_pop (IStack
*stack
)
12508 int rec
= stack
->ninsn
- 1;
12509 gas_assert (!istack_empty (stack
));
12511 tinsn_init (&stack
->insn
[rec
]);
12515 /* TInsn functions. */
12518 tinsn_init (TInsn
*dst
)
12520 memset (dst
, 0, sizeof (TInsn
));
12524 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12527 tinsn_has_symbolic_operands (const TInsn
*insn
)
12530 int n
= insn
->ntok
;
12532 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12534 for (i
= 0; i
< n
; ++i
)
12536 switch (insn
->tok
[i
].X_op
)
12550 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12552 xtensa_isa isa
= xtensa_default_isa
;
12554 int n
= insn
->ntok
;
12556 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12558 for (i
= 0; i
< n
; ++i
)
12560 switch (insn
->tok
[i
].X_op
)
12568 /* Errors for these types are caught later. */
12573 /* Symbolic immediates are only allowed on the last immediate
12574 operand. At this time, CONST16 is the only opcode where we
12575 support non-PC-relative relocations. */
12576 if (i
!= get_relaxable_immed (insn
->opcode
)
12577 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12578 && insn
->opcode
!= xtensa_const16_opcode
))
12580 as_bad (_("invalid symbolic operand"));
12589 /* For assembly code with complex expressions (e.g. subtraction),
12590 we have to build them in the literal pool so that
12591 their results are calculated correctly after relaxation.
12592 The relaxation only handles expressions that
12593 boil down to SYMBOL + OFFSET. */
12596 tinsn_has_complex_operands (const TInsn
*insn
)
12599 int n
= insn
->ntok
;
12600 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12601 for (i
= 0; i
< n
; ++i
)
12603 switch (insn
->tok
[i
].X_op
)
12619 /* Encode a TInsn opcode and its constant operands into slotbuf.
12620 Return TRUE if there is a symbol in the immediate field. This
12621 function assumes that:
12622 1) The number of operands are correct.
12623 2) The insn_type is ITYPE_INSN.
12624 3) The opcode can be encoded in the specified format and slot.
12625 4) Operands are either O_constant or O_symbol, and all constants fit. */
12628 tinsn_to_slotbuf (xtensa_format fmt
,
12631 xtensa_insnbuf slotbuf
)
12633 xtensa_isa isa
= xtensa_default_isa
;
12634 xtensa_opcode opcode
= tinsn
->opcode
;
12635 bfd_boolean has_fixup
= FALSE
;
12636 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12639 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12640 if (noperands
!= tinsn
->ntok
)
12641 as_fatal (_("operand number mismatch"));
12643 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12645 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12646 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12650 for (i
= 0; i
< noperands
; i
++)
12652 expressionS
*exp
= &tinsn
->tok
[i
];
12655 const char *file_name
;
12661 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12663 /* The register number has already been checked in
12664 expression_maybe_register, so we don't need to check here. */
12665 opnd_value
= exp
->X_add_number
;
12666 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12667 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12670 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12674 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12676 file_name
= as_where (&line
);
12677 /* It is a constant and we called this function
12678 then we have to try to fit it. */
12679 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12680 exp
->X_add_number
, file_name
, line
);
12693 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12694 into a multi-slot instruction, fill the other slots with NOPs.
12695 Return TRUE if there is a symbol in the immediate field. See also the
12696 assumptions listed for tinsn_to_slotbuf. */
12699 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12701 static xtensa_insnbuf slotbuf
= 0;
12702 static vliw_insn vinsn
;
12703 xtensa_isa isa
= xtensa_default_isa
;
12704 bfd_boolean has_fixup
= FALSE
;
12709 slotbuf
= xtensa_insnbuf_alloc (isa
);
12710 xg_init_vinsn (&vinsn
);
12713 xg_clear_vinsn (&vinsn
);
12715 bundle_tinsn (tinsn
, &vinsn
);
12717 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12719 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12721 /* Only one slot may have a fix-up because the rest contains NOPs. */
12723 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12724 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12731 /* Check the instruction arguments. Return TRUE on failure. */
12734 tinsn_check_arguments (const TInsn
*insn
)
12736 xtensa_isa isa
= xtensa_default_isa
;
12737 xtensa_opcode opcode
= insn
->opcode
;
12738 xtensa_regfile t1_regfile
, t2_regfile
;
12739 int t1_reg
, t2_reg
;
12740 int t1_base_reg
, t1_last_reg
;
12741 int t2_base_reg
, t2_last_reg
;
12742 char t1_inout
, t2_inout
;
12745 if (opcode
== XTENSA_UNDEFINED
)
12747 as_bad (_("invalid opcode"));
12751 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12753 as_bad (_("too few operands"));
12757 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12759 as_bad (_("too many operands"));
12763 /* Check registers. */
12764 for (j
= 0; j
< insn
->ntok
; j
++)
12766 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12769 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12770 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12772 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12774 for (i
= 0; i
< insn
->ntok
; i
++)
12779 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12782 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12784 if (t1_regfile
!= t2_regfile
)
12787 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12788 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12790 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12791 t1_last_reg
= (t1_base_reg
12792 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12794 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12796 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12798 if (t1_reg
!= t2_reg
)
12801 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12803 as_bad (_("multiple writes to the same register"));
12814 /* Load an instruction from its encoded form. */
12817 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12821 xg_init_vinsn (&vinsn
);
12822 vinsn_from_chars (&vinsn
, f
);
12824 *tinsn
= vinsn
.slots
[slot
];
12825 xg_free_vinsn (&vinsn
);
12830 tinsn_from_insnbuf (TInsn
*tinsn
,
12831 xtensa_insnbuf slotbuf
,
12836 xtensa_isa isa
= xtensa_default_isa
;
12838 /* Find the immed. */
12839 tinsn_init (tinsn
);
12840 tinsn
->insn_type
= ITYPE_INSN
;
12841 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12842 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12843 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12844 for (i
= 0; i
< tinsn
->ntok
; i
++)
12846 set_expr_const (&tinsn
->tok
[i
],
12847 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12848 tinsn
->opcode
, i
));
12853 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12856 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12858 xtensa_opcode opcode
= tinsn
->opcode
;
12861 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12863 opnum
= get_relaxable_immed (opcode
);
12864 gas_assert (opnum
>= 0);
12865 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12866 fragP
->tc_frag_data
.slot_symbols
[slot
],
12867 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12869 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12874 get_num_stack_text_bytes (IStack
*istack
)
12877 int text_bytes
= 0;
12879 for (i
= 0; i
< istack
->ninsn
; i
++)
12881 TInsn
*tinsn
= &istack
->insn
[i
];
12882 if (tinsn
->insn_type
== ITYPE_INSN
)
12883 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12890 get_num_stack_literal_bytes (IStack
*istack
)
12895 for (i
= 0; i
< istack
->ninsn
; i
++)
12897 TInsn
*tinsn
= &istack
->insn
[i
];
12898 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12905 /* vliw_insn functions. */
12908 xg_init_vinsn (vliw_insn
*v
)
12911 xtensa_isa isa
= xtensa_default_isa
;
12913 xg_clear_vinsn (v
);
12915 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12916 if (v
->insnbuf
== NULL
)
12917 as_fatal (_("out of memory"));
12919 for (i
= 0; i
< config_max_slots
; i
++)
12921 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12922 if (v
->slotbuf
[i
] == NULL
)
12923 as_fatal (_("out of memory"));
12929 xg_clear_vinsn (vliw_insn
*v
)
12933 memset (v
, 0, offsetof (vliw_insn
, slots
)
12934 + sizeof(TInsn
) * config_max_slots
);
12936 v
->format
= XTENSA_UNDEFINED
;
12938 v
->inside_bundle
= FALSE
;
12940 if (xt_saved_debug_type
!= DEBUG_NONE
)
12941 debug_type
= xt_saved_debug_type
;
12943 for (i
= 0; i
< config_max_slots
; i
++)
12944 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12949 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12952 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12953 dst
->insnbuf
= src
->insnbuf
;
12954 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12959 vinsn_has_specific_opcodes (vliw_insn
*v
)
12963 for (i
= 0; i
< v
->num_slots
; i
++)
12965 if (v
->slots
[i
].is_specific_opcode
)
12973 xg_free_vinsn (vliw_insn
*v
)
12976 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12977 for (i
= 0; i
< config_max_slots
; i
++)
12978 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12982 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12983 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12986 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12989 bfd_boolean record_fixup
)
12991 xtensa_isa isa
= xtensa_default_isa
;
12992 xtensa_format fmt
= vinsn
->format
;
12993 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12995 bfd_boolean has_fixup
= FALSE
;
12997 xtensa_format_encode (isa
, fmt
, insnbuf
);
12999 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
13001 TInsn
*tinsn
= &vinsn
->slots
[slot
];
13002 expressionS
*extra_arg
= &tinsn
->extra_arg
;
13003 bfd_boolean tinsn_has_fixup
=
13004 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
13005 vinsn
->slotbuf
[slot
]);
13007 xtensa_format_set_slot (isa
, fmt
, slot
,
13008 insnbuf
, vinsn
->slotbuf
[slot
]);
13009 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
13011 if (vinsn
->num_slots
!= 1)
13012 as_bad (_("TLS relocation not allowed in FLIX bundle"));
13013 else if (record_fixup
)
13014 /* Instructions that generate TLS relocations should always be
13015 relaxed in the front-end. If "record_fixup" is set, then this
13016 function is being called during back-end relaxation, so flag
13017 the unexpected behavior as an error. */
13018 as_bad (_("unexpected TLS relocation"));
13020 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
13021 xtensa_format_length (isa
, fmt
),
13022 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
13023 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
13025 if (tinsn_has_fixup
)
13028 xtensa_opcode opcode
= tinsn
->opcode
;
13029 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
13032 for (i
= 0; i
< noperands
; i
++)
13034 expressionS
* exp
= &tinsn
->tok
[i
];
13040 if (get_relaxable_immed (opcode
) == i
)
13042 /* Add a fix record for the instruction, except if this
13043 function is being called prior to relaxation, i.e.,
13044 if record_fixup is false, and the instruction might
13045 be relaxed later. */
13047 || tinsn
->is_specific_opcode
13048 || !xg_is_relaxable_insn (tinsn
, 0))
13050 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
13051 frag_offset
- fragP
->fr_literal
);
13055 if (exp
->X_op
!= O_symbol
)
13056 as_bad (_("invalid operand"));
13057 tinsn
->symbol
= exp
->X_add_symbol
;
13058 tinsn
->offset
= exp
->X_add_number
;
13062 as_bad (_("symbolic operand not allowed"));
13070 as_bad (_("expression too complex"));
13082 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
13084 static xtensa_insnbuf insnbuf
= NULL
;
13085 static xtensa_insnbuf slotbuf
= NULL
;
13088 xtensa_isa isa
= xtensa_default_isa
;
13092 insnbuf
= xtensa_insnbuf_alloc (isa
);
13093 slotbuf
= xtensa_insnbuf_alloc (isa
);
13096 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13097 fmt
= xtensa_format_decode (isa
, insnbuf
);
13098 if (fmt
== XTENSA_UNDEFINED
)
13099 as_fatal (_("cannot decode instruction format"));
13100 vinsn
->format
= fmt
;
13101 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13103 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13105 TInsn
*tinsn
= &vinsn
->slots
[i
];
13106 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13107 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13112 /* Expression utilities. */
13114 /* Return TRUE if the expression is an integer constant. */
13117 expr_is_const (const expressionS
*s
)
13119 return (s
->X_op
== O_constant
);
13123 /* Get the expression constant.
13124 Calling this is illegal if expr_is_const () returns TRUE. */
13127 get_expr_const (const expressionS
*s
)
13129 gas_assert (expr_is_const (s
));
13130 return s
->X_add_number
;
13134 /* Set the expression to a constant value. */
13137 set_expr_const (expressionS
*s
, offsetT val
)
13139 s
->X_op
= O_constant
;
13140 s
->X_add_number
= val
;
13141 s
->X_add_symbol
= NULL
;
13142 s
->X_op_symbol
= NULL
;
13147 expr_is_register (const expressionS
*s
)
13149 return (s
->X_op
== O_register
);
13153 /* Get the expression constant.
13154 Calling this is illegal if expr_is_const () returns TRUE. */
13157 get_expr_register (const expressionS
*s
)
13159 gas_assert (expr_is_register (s
));
13160 return s
->X_add_number
;
13164 /* Set the expression to a symbol + constant offset. */
13167 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13169 s
->X_op
= O_symbol
;
13170 s
->X_add_symbol
= sym
;
13171 s
->X_op_symbol
= NULL
; /* unused */
13172 s
->X_add_number
= offset
;
13176 /* Return TRUE if the two expressions are equal. */
13179 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13181 if (s1
->X_op
!= s2
->X_op
)
13183 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13185 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13187 if (s1
->X_add_number
!= s2
->X_add_number
)
13194 copy_expr (expressionS
*dst
, const expressionS
*src
)
13196 memcpy (dst
, src
, sizeof (expressionS
));
13200 /* Support for the "--rename-section" option. */
13202 struct rename_section_struct
13204 const char *old_name
;
13206 struct rename_section_struct
*next
;
13209 static struct rename_section_struct
*section_rename
;
13212 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13213 entries to the section_rename list. Note: Specifying multiple
13214 renamings separated by colons is not documented and is retained only
13215 for backward compatibility. */
13218 build_section_rename (const char *arg
)
13220 struct rename_section_struct
*r
;
13221 char *this_arg
= NULL
;
13222 char *next_arg
= NULL
;
13224 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13226 char *old_name
, *new_name
;
13230 next_arg
= strchr (this_arg
, ':');
13238 old_name
= this_arg
;
13239 new_name
= strchr (this_arg
, '=');
13241 if (*old_name
== '\0')
13243 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13246 if (!new_name
|| new_name
[1] == '\0')
13248 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13255 /* Check for invalid section renaming. */
13256 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13258 if (strcmp (r
->old_name
, old_name
) == 0)
13259 as_bad (_("section %s renamed multiple times"), old_name
);
13260 if (strcmp (r
->new_name
, new_name
) == 0)
13261 as_bad (_("multiple sections remapped to output section %s"),
13266 r
= XNEW (struct rename_section_struct
);
13267 r
->old_name
= xstrdup (old_name
);
13268 r
->new_name
= xstrdup (new_name
);
13269 r
->next
= section_rename
;
13270 section_rename
= r
;
13276 xtensa_section_rename (const char *name
)
13278 struct rename_section_struct
*r
= section_rename
;
13280 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13282 if (strcmp (r
->old_name
, name
) == 0)
13283 return r
->new_name
;
13286 return (char *) name
;