1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
368 directive_literal_prefix
,
370 directive_absolute_literals
,
371 directive_last_directive
377 bfd_boolean can_be_negated
;
380 const directive_infoS directive_info
[] =
383 { "literal", FALSE
},
385 { "transform", TRUE
},
386 { "freeregs", FALSE
},
387 { "longcalls", TRUE
},
388 { "literal_prefix", FALSE
},
389 { "schedule", TRUE
},
390 { "absolute-literals", TRUE
}
393 bfd_boolean directive_state
[] =
397 #if !XCHAL_HAVE_DENSITY
402 TRUE
, /* transform */
403 FALSE
, /* freeregs */
404 FALSE
, /* longcalls */
405 FALSE
, /* literal_prefix */
407 #if XSHAL_USE_ABSOLUTE_LITERALS
408 TRUE
/* absolute_literals */
410 FALSE
/* absolute_literals */
415 /* Directive functions. */
417 static void xtensa_begin_directive (int);
418 static void xtensa_end_directive (int);
419 static void xtensa_literal_prefix (char const *, int);
420 static void xtensa_literal_position (int);
421 static void xtensa_literal_pseudo (int);
422 static void xtensa_frequency_pseudo (int);
423 static void xtensa_elf_cons (int);
425 /* Parsing and Idiom Translation. */
427 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
429 /* Various Other Internal Functions. */
431 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
432 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
433 static void xtensa_mark_literal_pool_location (void);
434 static addressT
get_expanded_loop_offset (xtensa_opcode
);
435 static fragS
*get_literal_pool_location (segT
);
436 static void set_literal_pool_location (segT
, fragS
*);
437 static void xtensa_set_frag_assembly_state (fragS
*);
438 static void finish_vinsn (vliw_insn
*);
439 static bfd_boolean
emit_single_op (TInsn
*);
440 static int total_frag_text_expansion (fragS
*);
442 /* Alignment Functions. */
444 static int get_text_align_power (unsigned);
445 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
446 static int branch_align_power (segT
);
448 /* Helpers for xtensa_relax_frag(). */
450 static long relax_frag_add_nop (fragS
*);
452 /* Accessors for additional per-subsegment information. */
454 static unsigned get_last_insn_flags (segT
, subsegT
);
455 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
456 static float get_subseg_total_freq (segT
, subsegT
);
457 static float get_subseg_target_freq (segT
, subsegT
);
458 static void set_subseg_freq (segT
, subsegT
, float, float);
460 /* Segment list functions. */
462 static void xtensa_move_literals (void);
463 static void xtensa_reorder_segments (void);
464 static void xtensa_switch_to_literal_fragment (emit_state
*);
465 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
466 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
467 static void xtensa_restore_emit_state (emit_state
*);
468 static void cache_literal_section
469 (seg_list
*, const char *, segT
*, bfd_boolean
);
471 /* Import from elf32-xtensa.c in BFD library. */
473 extern char *xtensa_get_property_section_name (asection
*, const char *);
475 /* op_placement_info functions. */
477 static void init_op_placement_info_table (void);
478 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
479 static int xg_get_single_size (xtensa_opcode
);
480 static xtensa_format
xg_get_single_format (xtensa_opcode
);
481 static int xg_get_single_slot (xtensa_opcode
);
483 /* TInsn and IStack functions. */
485 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
486 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
487 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
488 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
489 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
490 static void tinsn_from_chars (TInsn
*, char *, int);
491 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
492 static int get_num_stack_text_bytes (IStack
*);
493 static int get_num_stack_literal_bytes (IStack
*);
495 /* vliw_insn functions. */
497 static void xg_init_vinsn (vliw_insn
*);
498 static void xg_clear_vinsn (vliw_insn
*);
499 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
500 static void xg_free_vinsn (vliw_insn
*);
501 static bfd_boolean vinsn_to_insnbuf
502 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
503 static void vinsn_from_chars (vliw_insn
*, char *);
505 /* Expression Utilities. */
507 bfd_boolean
expr_is_const (const expressionS
*);
508 offsetT
get_expr_const (const expressionS
*);
509 void set_expr_const (expressionS
*, offsetT
);
510 bfd_boolean
expr_is_register (const expressionS
*);
511 offsetT
get_expr_register (const expressionS
*);
512 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
513 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
514 static void copy_expr (expressionS
*, const expressionS
*);
516 /* Section renaming. */
518 static void build_section_rename (const char *);
521 /* ISA imported from bfd. */
522 extern xtensa_isa xtensa_default_isa
;
524 extern int target_big_endian
;
526 static xtensa_opcode xtensa_addi_opcode
;
527 static xtensa_opcode xtensa_addmi_opcode
;
528 static xtensa_opcode xtensa_call0_opcode
;
529 static xtensa_opcode xtensa_call4_opcode
;
530 static xtensa_opcode xtensa_call8_opcode
;
531 static xtensa_opcode xtensa_call12_opcode
;
532 static xtensa_opcode xtensa_callx0_opcode
;
533 static xtensa_opcode xtensa_callx4_opcode
;
534 static xtensa_opcode xtensa_callx8_opcode
;
535 static xtensa_opcode xtensa_callx12_opcode
;
536 static xtensa_opcode xtensa_const16_opcode
;
537 static xtensa_opcode xtensa_entry_opcode
;
538 static xtensa_opcode xtensa_movi_opcode
;
539 static xtensa_opcode xtensa_movi_n_opcode
;
540 static xtensa_opcode xtensa_isync_opcode
;
541 static xtensa_opcode xtensa_jx_opcode
;
542 static xtensa_opcode xtensa_l32r_opcode
;
543 static xtensa_opcode xtensa_loop_opcode
;
544 static xtensa_opcode xtensa_loopnez_opcode
;
545 static xtensa_opcode xtensa_loopgtz_opcode
;
546 static xtensa_opcode xtensa_nop_opcode
;
547 static xtensa_opcode xtensa_nop_n_opcode
;
548 static xtensa_opcode xtensa_or_opcode
;
549 static xtensa_opcode xtensa_ret_opcode
;
550 static xtensa_opcode xtensa_ret_n_opcode
;
551 static xtensa_opcode xtensa_retw_opcode
;
552 static xtensa_opcode xtensa_retw_n_opcode
;
553 static xtensa_opcode xtensa_rsr_lcount_opcode
;
554 static xtensa_opcode xtensa_waiti_opcode
;
557 /* Command-line Options. */
559 bfd_boolean use_literal_section
= TRUE
;
560 static bfd_boolean align_targets
= TRUE
;
561 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
562 static bfd_boolean has_a0_b_retw
= FALSE
;
563 static bfd_boolean workaround_a0_b_retw
= FALSE
;
564 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
565 static bfd_boolean workaround_short_loop
= FALSE
;
566 static bfd_boolean maybe_has_short_loop
= FALSE
;
567 static bfd_boolean workaround_close_loop_end
= FALSE
;
568 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
569 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
571 /* When workaround_short_loops is TRUE, all loops with early exits must
572 have at least 3 instructions. workaround_all_short_loops is a modifier
573 to the workaround_short_loop flag. In addition to the
574 workaround_short_loop actions, all straightline loopgtz and loopnez
575 must have at least 3 instructions. */
577 static bfd_boolean workaround_all_short_loops
= FALSE
;
581 xtensa_setup_hw_workarounds (int earliest
, int latest
)
583 if (earliest
> latest
)
584 as_fatal (_("illegal range of target hardware versions"));
586 /* Enable all workarounds for pre-T1050.0 hardware. */
587 if (earliest
< 105000 || latest
< 105000)
589 workaround_a0_b_retw
|= TRUE
;
590 workaround_b_j_loop_end
|= TRUE
;
591 workaround_short_loop
|= TRUE
;
592 workaround_close_loop_end
|= TRUE
;
593 workaround_all_short_loops
|= TRUE
;
594 enforce_three_byte_loop_align
= TRUE
;
601 option_density
= OPTION_MD_BASE
,
608 option_no_link_relax
,
616 option_text_section_literals
,
617 option_no_text_section_literals
,
619 option_absolute_literals
,
620 option_no_absolute_literals
,
622 option_align_targets
,
623 option_no_align_targets
,
625 option_warn_unaligned_targets
,
630 option_workaround_a0_b_retw
,
631 option_no_workaround_a0_b_retw
,
633 option_workaround_b_j_loop_end
,
634 option_no_workaround_b_j_loop_end
,
636 option_workaround_short_loop
,
637 option_no_workaround_short_loop
,
639 option_workaround_all_short_loops
,
640 option_no_workaround_all_short_loops
,
642 option_workaround_close_loop_end
,
643 option_no_workaround_close_loop_end
,
645 option_no_workarounds
,
647 option_rename_section_name
,
650 option_prefer_const16
,
652 option_target_hardware
655 const char *md_shortopts
= "";
657 struct option md_longopts
[] =
659 { "density", no_argument
, NULL
, option_density
},
660 { "no-density", no_argument
, NULL
, option_no_density
},
662 /* Both "relax" and "generics" are deprecated and treated as equivalent
663 to the "transform" option. */
664 { "relax", no_argument
, NULL
, option_relax
},
665 { "no-relax", no_argument
, NULL
, option_no_relax
},
666 { "generics", no_argument
, NULL
, option_generics
},
667 { "no-generics", no_argument
, NULL
, option_no_generics
},
669 { "transform", no_argument
, NULL
, option_transform
},
670 { "no-transform", no_argument
, NULL
, option_no_transform
},
671 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
672 { "no-text-section-literals", no_argument
, NULL
,
673 option_no_text_section_literals
},
674 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
675 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
676 /* This option was changed from -align-target to -target-align
677 because it conflicted with the "-al" option. */
678 { "target-align", no_argument
, NULL
, option_align_targets
},
679 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
680 { "warn-unaligned-targets", no_argument
, NULL
,
681 option_warn_unaligned_targets
},
682 { "longcalls", no_argument
, NULL
, option_longcalls
},
683 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
685 { "no-workaround-a0-b-retw", no_argument
, NULL
,
686 option_no_workaround_a0_b_retw
},
687 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
689 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
690 option_no_workaround_b_j_loop_end
},
691 { "workaround-b-j-loop-end", no_argument
, NULL
,
692 option_workaround_b_j_loop_end
},
694 { "no-workaround-short-loops", no_argument
, NULL
,
695 option_no_workaround_short_loop
},
696 { "workaround-short-loops", no_argument
, NULL
,
697 option_workaround_short_loop
},
699 { "no-workaround-all-short-loops", no_argument
, NULL
,
700 option_no_workaround_all_short_loops
},
701 { "workaround-all-short-loop", no_argument
, NULL
,
702 option_workaround_all_short_loops
},
704 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
705 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
707 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
709 { "no-workaround-close-loop-end", no_argument
, NULL
,
710 option_no_workaround_close_loop_end
},
711 { "workaround-close-loop-end", no_argument
, NULL
,
712 option_workaround_close_loop_end
},
714 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
716 { "link-relax", no_argument
, NULL
, option_link_relax
},
717 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
719 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
721 { NULL
, no_argument
, NULL
, 0 }
724 size_t md_longopts_size
= sizeof md_longopts
;
728 md_parse_option (int c
, char *arg
)
733 as_warn (_("--density option is ignored"));
735 case option_no_density
:
736 as_warn (_("--no-density option is ignored"));
738 case option_link_relax
:
741 case option_no_link_relax
:
744 case option_generics
:
745 as_warn (_("--generics is deprecated; use --transform instead"));
746 return md_parse_option (option_transform
, arg
);
747 case option_no_generics
:
748 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
749 return md_parse_option (option_no_transform
, arg
);
751 as_warn (_("--relax is deprecated; use --transform instead"));
752 return md_parse_option (option_transform
, arg
);
753 case option_no_relax
:
754 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform
, arg
);
756 case option_longcalls
:
757 directive_state
[directive_longcalls
] = TRUE
;
759 case option_no_longcalls
:
760 directive_state
[directive_longcalls
] = FALSE
;
762 case option_text_section_literals
:
763 use_literal_section
= FALSE
;
765 case option_no_text_section_literals
:
766 use_literal_section
= TRUE
;
768 case option_absolute_literals
:
769 if (!absolute_literals_supported
)
771 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
774 directive_state
[directive_absolute_literals
] = TRUE
;
776 case option_no_absolute_literals
:
777 directive_state
[directive_absolute_literals
] = FALSE
;
780 case option_workaround_a0_b_retw
:
781 workaround_a0_b_retw
= TRUE
;
783 case option_no_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= FALSE
;
786 case option_workaround_b_j_loop_end
:
787 workaround_b_j_loop_end
= TRUE
;
789 case option_no_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= FALSE
;
793 case option_workaround_short_loop
:
794 workaround_short_loop
= TRUE
;
796 case option_no_workaround_short_loop
:
797 workaround_short_loop
= FALSE
;
800 case option_workaround_all_short_loops
:
801 workaround_all_short_loops
= TRUE
;
803 case option_no_workaround_all_short_loops
:
804 workaround_all_short_loops
= FALSE
;
807 case option_workaround_close_loop_end
:
808 workaround_close_loop_end
= TRUE
;
810 case option_no_workaround_close_loop_end
:
811 workaround_close_loop_end
= FALSE
;
814 case option_no_workarounds
:
815 workaround_a0_b_retw
= FALSE
;
816 workaround_b_j_loop_end
= FALSE
;
817 workaround_short_loop
= FALSE
;
818 workaround_all_short_loops
= FALSE
;
819 workaround_close_loop_end
= FALSE
;
822 case option_align_targets
:
823 align_targets
= TRUE
;
825 case option_no_align_targets
:
826 align_targets
= FALSE
;
829 case option_warn_unaligned_targets
:
830 warn_unaligned_branch_targets
= TRUE
;
833 case option_rename_section_name
:
834 build_section_rename (arg
);
838 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
839 should be emitted or not. FIXME: Not implemented. */
842 case option_prefer_l32r
:
844 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
848 case option_prefer_const16
:
850 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
854 case option_target_hardware
:
856 int earliest
, latest
= 0;
857 if (*arg
== 0 || *arg
== '-')
858 as_fatal (_("invalid target hardware version"));
860 earliest
= strtol (arg
, &arg
, 0);
864 else if (*arg
== '-')
867 as_fatal (_("invalid target hardware version"));
868 latest
= strtol (arg
, &arg
, 0);
871 as_fatal (_("invalid target hardware version"));
873 xtensa_setup_hw_workarounds (earliest
, latest
);
877 case option_transform
:
878 /* This option has no affect other than to use the defaults,
879 which are already set. */
882 case option_no_transform
:
883 /* This option turns off all transformations of any kind.
884 However, because we want to preserve the state of other
885 directives, we only change its own field. Thus, before
886 you perform any transformation, always check if transform
887 is available. If you use the functions we provide for this
888 purpose, you will be ok. */
889 directive_state
[directive_transform
] = FALSE
;
899 md_show_usage (FILE *stream
)
903 --[no-]text-section-literals\n\
904 [Do not] put literals in the text section\n\
905 --[no-]absolute-literals\n\
906 [Do not] default to use non-PC-relative literals\n\
907 --[no-]target-align [Do not] try to align branch targets\n\
908 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
909 --[no-]transform [Do not] transform instructions\n\
910 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
914 /* Functions related to the list of current label symbols. */
917 xtensa_add_insn_label (symbolS
*sym
)
921 if (!free_insn_labels
)
922 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
925 l
= free_insn_labels
;
926 free_insn_labels
= l
->next
;
930 l
->next
= insn_labels
;
936 xtensa_clear_insn_labels (void)
940 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
947 /* The "loops_ok" argument is provided to allow ignoring labels that
948 define loop ends. This fixes a bug where the NOPs to align a
949 loop opcode were included in a previous zero-cost loop:
968 This argument is used to prevent moving the NOP to before the
969 loop-end label, which is what you want in this special case. */
972 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
976 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
978 symbolS
*lit_sym
= lit
->sym
;
979 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
981 S_SET_VALUE (lit_sym
, new_offset
);
982 symbol_set_frag (lit_sym
, new_frag
);
988 /* Directive data and functions. */
990 typedef struct state_stackS_struct
992 directiveE directive
;
994 bfd_boolean old_state
;
998 struct state_stackS_struct
*prev
;
1001 state_stackS
*directive_state_stack
;
1003 const pseudo_typeS md_pseudo_table
[] =
1005 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1006 { "literal_position", xtensa_literal_position
, 0 },
1007 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1008 { "long", xtensa_elf_cons
, 4 },
1009 { "word", xtensa_elf_cons
, 4 },
1010 { "short", xtensa_elf_cons
, 2 },
1011 { "begin", xtensa_begin_directive
, 0 },
1012 { "end", xtensa_end_directive
, 0 },
1013 { "literal", xtensa_literal_pseudo
, 0 },
1014 { "frequency", xtensa_frequency_pseudo
, 0 },
1020 use_transform (void)
1022 /* After md_end, you should be checking frag by frag, rather
1023 than state directives. */
1024 assert (!past_xtensa_end
);
1025 return directive_state
[directive_transform
];
1030 do_align_targets (void)
1032 /* Do not use this function after md_end; just look at align_targets
1033 instead. There is no target-align directive, so alignment is either
1034 enabled for all frags or not done at all. */
1035 assert (!past_xtensa_end
);
1036 return align_targets
&& use_transform ();
1041 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1045 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1047 as_where (&file
, &line
);
1049 stack
->directive
= directive
;
1050 stack
->negated
= negated
;
1051 stack
->old_state
= directive_state
[directive
];
1054 stack
->datum
= datum
;
1055 stack
->prev
= directive_state_stack
;
1056 directive_state_stack
= stack
;
1058 directive_state
[directive
] = !negated
;
1063 directive_pop (directiveE
*directive
,
1064 bfd_boolean
*negated
,
1069 state_stackS
*top
= directive_state_stack
;
1071 if (!directive_state_stack
)
1073 as_bad (_("unmatched end directive"));
1074 *directive
= directive_none
;
1078 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1079 *directive
= top
->directive
;
1080 *negated
= top
->negated
;
1083 *datum
= top
->datum
;
1084 directive_state_stack
= top
->prev
;
1090 directive_balance (void)
1092 while (directive_state_stack
)
1094 directiveE directive
;
1095 bfd_boolean negated
;
1100 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1101 as_warn_where ((char *) file
, line
,
1102 _(".begin directive with no matching .end directive"));
1108 inside_directive (directiveE dir
)
1110 state_stackS
*top
= directive_state_stack
;
1112 while (top
&& top
->directive
!= dir
)
1115 return (top
!= NULL
);
1120 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1124 char *directive_string
;
1126 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1131 input_line_pointer
+= 3;
1134 len
= strspn (input_line_pointer
,
1135 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1137 /* This code is a hack to make .begin [no-][generics|relax] exactly
1138 equivalent to .begin [no-]transform. We should remove it when
1139 we stop accepting those options. */
1141 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1143 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1144 directive_string
= "transform";
1146 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1148 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1152 directive_string
= input_line_pointer
;
1154 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1156 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1158 input_line_pointer
+= len
;
1159 *directive
= (directiveE
) i
;
1160 if (*negated
&& !directive_info
[i
].can_be_negated
)
1161 as_bad (_("directive %s cannot be negated"),
1162 directive_info
[i
].name
);
1167 as_bad (_("unknown directive"));
1168 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1173 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1175 directiveE directive
;
1176 bfd_boolean negated
;
1181 get_directive (&directive
, &negated
);
1182 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1184 discard_rest_of_line ();
1188 if (cur_vinsn
.inside_bundle
)
1189 as_bad (_("directives are not valid inside bundles"));
1193 case directive_literal
:
1194 if (!inside_directive (directive_literal
))
1196 /* Previous labels go with whatever follows this directive, not with
1197 the literal, so save them now. */
1198 saved_insn_labels
= insn_labels
;
1201 as_warn (_(".begin literal is deprecated; use .literal instead"));
1202 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1203 xtensa_switch_to_literal_fragment (state
);
1204 directive_push (directive_literal
, negated
, state
);
1207 case directive_literal_prefix
:
1208 /* Have to flush pending output because a movi relaxed to an l32r
1209 might produce a literal. */
1210 md_flush_pending_output ();
1211 /* Check to see if the current fragment is a literal
1212 fragment. If it is, then this operation is not allowed. */
1213 if (generating_literals
)
1215 as_bad (_("cannot set literal_prefix inside literal fragment"));
1219 /* Allocate the literal state for this section and push
1220 onto the directive stack. */
1221 ls
= xmalloc (sizeof (lit_state
));
1224 *ls
= default_lit_sections
;
1226 directive_push (directive_literal_prefix
, negated
, ls
);
1228 /* Parse the new prefix from the input_line_pointer. */
1230 len
= strspn (input_line_pointer
,
1231 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1232 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1234 /* Process the new prefix. */
1235 xtensa_literal_prefix (input_line_pointer
, len
);
1237 /* Skip the name in the input line. */
1238 input_line_pointer
+= len
;
1241 case directive_freeregs
:
1242 /* This information is currently unused, but we'll accept the statement
1243 and just discard the rest of the line. This won't check the syntax,
1244 but it will accept every correct freeregs directive. */
1245 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1246 directive_push (directive_freeregs
, negated
, 0);
1249 case directive_schedule
:
1250 md_flush_pending_output ();
1251 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1252 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1253 directive_push (directive_schedule
, negated
, 0);
1254 xtensa_set_frag_assembly_state (frag_now
);
1257 case directive_density
:
1258 as_warn (_(".begin [no-]density is ignored"));
1261 case directive_absolute_literals
:
1262 md_flush_pending_output ();
1263 if (!absolute_literals_supported
&& !negated
)
1265 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1268 xtensa_set_frag_assembly_state (frag_now
);
1269 directive_push (directive
, negated
, 0);
1273 md_flush_pending_output ();
1274 xtensa_set_frag_assembly_state (frag_now
);
1275 directive_push (directive
, negated
, 0);
1279 demand_empty_rest_of_line ();
1284 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1286 directiveE begin_directive
, end_directive
;
1287 bfd_boolean begin_negated
, end_negated
;
1291 emit_state
**state_ptr
;
1294 if (cur_vinsn
.inside_bundle
)
1295 as_bad (_("directives are not valid inside bundles"));
1297 get_directive (&end_directive
, &end_negated
);
1299 md_flush_pending_output ();
1301 switch (end_directive
)
1303 case (directiveE
) XTENSA_UNDEFINED
:
1304 discard_rest_of_line ();
1307 case directive_density
:
1308 as_warn (_(".end [no-]density is ignored"));
1309 demand_empty_rest_of_line ();
1312 case directive_absolute_literals
:
1313 if (!absolute_literals_supported
&& !end_negated
)
1315 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1316 demand_empty_rest_of_line ();
1325 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1326 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1327 (const void **) state_ptr
);
1329 if (begin_directive
!= directive_none
)
1331 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1333 as_bad (_("does not match begin %s%s at %s:%d"),
1334 begin_negated
? "no-" : "",
1335 directive_info
[begin_directive
].name
, file
, line
);
1339 switch (end_directive
)
1341 case directive_literal
:
1342 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1343 xtensa_restore_emit_state (state
);
1344 xtensa_set_frag_assembly_state (frag_now
);
1346 if (!inside_directive (directive_literal
))
1348 /* Restore the list of current labels. */
1349 xtensa_clear_insn_labels ();
1350 insn_labels
= saved_insn_labels
;
1354 case directive_literal_prefix
:
1355 /* Restore the default collection sections from saved state. */
1356 s
= (lit_state
*) state
;
1359 default_lit_sections
= *s
;
1361 /* free the state storage */
1365 case directive_schedule
:
1366 case directive_freeregs
:
1370 xtensa_set_frag_assembly_state (frag_now
);
1376 demand_empty_rest_of_line ();
1380 /* Place an aligned literal fragment at the current location. */
1383 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1385 md_flush_pending_output ();
1387 if (inside_directive (directive_literal
))
1388 as_warn (_(".literal_position inside literal directive; ignoring"));
1389 xtensa_mark_literal_pool_location ();
1391 demand_empty_rest_of_line ();
1392 xtensa_clear_insn_labels ();
1396 /* Support .literal label, expr, ... */
1399 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1402 char *p
, *base_name
;
1406 if (inside_directive (directive_literal
))
1408 as_bad (_(".literal not allowed inside .begin literal region"));
1409 ignore_rest_of_line ();
1413 md_flush_pending_output ();
1415 /* Previous labels go with whatever follows this directive, not with
1416 the literal, so save them now. */
1417 saved_insn_labels
= insn_labels
;
1420 /* If we are using text-section literals, then this is the right value... */
1423 base_name
= input_line_pointer
;
1425 xtensa_switch_to_literal_fragment (&state
);
1427 /* ...but if we aren't using text-section-literals, then we
1428 need to put them in the section we just switched to. */
1429 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1432 /* All literals are aligned to four-byte boundaries. */
1433 frag_align (2, 0, 0);
1434 record_alignment (now_seg
, 2);
1436 c
= get_symbol_end ();
1437 /* Just after name is now '\0'. */
1438 p
= input_line_pointer
;
1442 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1444 as_bad (_("expected comma or colon after symbol name; "
1445 "rest of line ignored"));
1446 ignore_rest_of_line ();
1447 xtensa_restore_emit_state (&state
);
1455 input_line_pointer
++; /* skip ',' or ':' */
1457 xtensa_elf_cons (4);
1459 xtensa_restore_emit_state (&state
);
1461 /* Restore the list of current labels. */
1462 xtensa_clear_insn_labels ();
1463 insn_labels
= saved_insn_labels
;
1468 xtensa_literal_prefix (char const *start
, int len
)
1470 char *name
, *linkonce_suffix
;
1471 char *newname
, *newname4
;
1472 size_t linkonce_len
;
1474 /* Get a null-terminated copy of the name. */
1475 name
= xmalloc (len
+ 1);
1478 strncpy (name
, start
, len
);
1481 /* Allocate the sections (interesting note: the memory pointing to
1482 the name is actually used for the name by the new section). */
1484 newname
= xmalloc (len
+ strlen (".literal") + 1);
1485 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1487 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1488 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1489 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1491 strcpy (newname
, ".gnu.linkonce.literal");
1492 strcpy (newname4
, ".gnu.linkonce.lit4");
1494 strcat (newname
, linkonce_suffix
);
1495 strcat (newname4
, linkonce_suffix
);
1499 int suffix_pos
= len
;
1501 /* If the section name ends with ".text", then replace that suffix
1502 instead of appending an additional suffix. */
1503 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1506 strcpy (newname
, name
);
1507 strcpy (newname4
, name
);
1509 strcpy (newname
+ suffix_pos
, ".literal");
1510 strcpy (newname4
+ suffix_pos
, ".lit4");
1513 /* Note that cache_literal_section does not create a segment if
1514 it already exists. */
1515 default_lit_sections
.lit_seg
= NULL
;
1516 default_lit_sections
.lit4_seg
= NULL
;
1518 /* Canonicalizing section names allows renaming literal
1519 sections to occur correctly. */
1520 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1521 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1527 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1530 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1532 float fall_through_f
, target_f
;
1534 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1535 if (fall_through_f
< 0)
1537 as_bad (_("fall through frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1545 as_bad (_("branch target frequency must be greater than 0"));
1546 ignore_rest_of_line ();
1550 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1552 demand_empty_rest_of_line ();
1556 /* Like normal .long/.short/.word, except support @plt, etc.
1557 Clobbers input_line_pointer, checks end-of-line. */
1560 xtensa_elf_cons (int nbytes
)
1563 bfd_reloc_code_real_type reloc
;
1565 md_flush_pending_output ();
1567 if (cur_vinsn
.inside_bundle
)
1568 as_bad (_("directives are not valid inside bundles"));
1570 if (is_it_end_of_statement ())
1572 demand_empty_rest_of_line ();
1579 if (exp
.X_op
== O_symbol
1580 && *input_line_pointer
== '@'
1581 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1584 reloc_howto_type
*reloc_howto
=
1585 bfd_reloc_type_lookup (stdoutput
, reloc
);
1587 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1588 as_bad (_("unsupported relocation"));
1589 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1591 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1592 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1593 as_bad (_("opcode-specific %s relocation used outside "
1594 "an instruction"), reloc_howto
->name
);
1595 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1596 as_bad (_("%s relocations do not fit in %d bytes"),
1597 reloc_howto
->name
, nbytes
);
1600 char *p
= frag_more ((int) nbytes
);
1601 xtensa_set_frag_assembly_state (frag_now
);
1602 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1603 nbytes
, &exp
, 0, reloc
);
1607 emit_expr (&exp
, (unsigned int) nbytes
);
1609 while (*input_line_pointer
++ == ',');
1611 input_line_pointer
--; /* Put terminator back into stream. */
1612 demand_empty_rest_of_line ();
1616 /* Parsing and Idiom Translation. */
1618 /* Parse @plt, etc. and return the desired relocation. */
1619 static bfd_reloc_code_real_type
1620 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1626 bfd_reloc_code_real_type reloc
;
1634 struct map_bfd
*ptr
;
1636 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1638 static struct map_bfd mapping
[] =
1640 MAP ("l", BFD_RELOC_LO16
),
1641 MAP ("h", BFD_RELOC_HI16
),
1642 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1643 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1647 return BFD_RELOC_NONE
;
1649 for (ch
= *str
, str2
= ident
;
1650 (str2
< ident
+ sizeof (ident
) - 1
1651 && (ISALNUM (ch
) || ch
== '@'));
1654 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1661 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1662 if (ch
== ptr
->string
[0]
1663 && len
== ptr
->length
1664 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1666 /* Now check for "identifier@suffix+constant". */
1667 if (*str
== '-' || *str
== '+')
1669 char *orig_line
= input_line_pointer
;
1670 expressionS new_exp
;
1672 input_line_pointer
= str
;
1673 expression (&new_exp
);
1674 if (new_exp
.X_op
== O_constant
)
1676 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1677 str
= input_line_pointer
;
1680 if (&input_line_pointer
!= str_p
)
1681 input_line_pointer
= orig_line
;
1688 return BFD_RELOC_UNUSED
;
1693 expression_end (const char *name
)
1716 #define ERROR_REG_NUM ((unsigned) -1)
1719 tc_get_register (const char *prefix
)
1722 const char *next_expr
;
1723 const char *old_line_pointer
;
1726 old_line_pointer
= input_line_pointer
;
1728 if (*input_line_pointer
== '$')
1729 ++input_line_pointer
;
1731 /* Accept "sp" as a synonym for "a1". */
1732 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1733 && expression_end (input_line_pointer
+ 2))
1735 input_line_pointer
+= 2;
1736 return 1; /* AR[1] */
1739 while (*input_line_pointer
++ == *prefix
++)
1741 --input_line_pointer
;
1746 as_bad (_("bad register name: %s"), old_line_pointer
);
1747 return ERROR_REG_NUM
;
1750 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1752 as_bad (_("bad register number: %s"), input_line_pointer
);
1753 return ERROR_REG_NUM
;
1758 while (ISDIGIT ((int) *input_line_pointer
))
1759 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1761 if (!(next_expr
= expression_end (input_line_pointer
)))
1763 as_bad (_("bad register name: %s"), old_line_pointer
);
1764 return ERROR_REG_NUM
;
1767 input_line_pointer
= (char *) next_expr
;
1774 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1776 xtensa_isa isa
= xtensa_default_isa
;
1778 /* Check if this is an immediate operand. */
1779 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1781 bfd_reloc_code_real_type reloc
;
1782 segT t
= expression (tok
);
1783 if (t
== absolute_section
1784 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1786 assert (tok
->X_op
== O_constant
);
1787 tok
->X_op
= O_symbol
;
1788 tok
->X_add_symbol
= &abs_symbol
;
1791 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1792 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1793 && (reloc
!= BFD_RELOC_NONE
))
1798 case BFD_RELOC_UNUSED
:
1799 as_bad (_("unsupported relocation"));
1802 case BFD_RELOC_XTENSA_PLT
:
1803 tok
->X_op
= O_pltrel
;
1806 case BFD_RELOC_LO16
:
1807 if (tok
->X_op
== O_constant
)
1808 tok
->X_add_number
&= 0xffff;
1813 case BFD_RELOC_HI16
:
1814 if (tok
->X_op
== O_constant
)
1815 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1824 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1825 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1827 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1830 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1831 as_bad (_("register number out of range"));
1834 tok
->X_op
= O_register
;
1835 tok
->X_add_symbol
= 0;
1836 tok
->X_add_number
= reg
;
1841 /* Split up the arguments for an opcode or pseudo-op. */
1844 tokenize_arguments (char **args
, char *str
)
1846 char *old_input_line_pointer
;
1847 bfd_boolean saw_comma
= FALSE
;
1848 bfd_boolean saw_arg
= FALSE
;
1849 bfd_boolean saw_colon
= FALSE
;
1851 char *arg_end
, *arg
;
1854 /* Save and restore input_line_pointer around this function. */
1855 old_input_line_pointer
= input_line_pointer
;
1856 input_line_pointer
= str
;
1858 while (*input_line_pointer
)
1861 switch (*input_line_pointer
)
1868 input_line_pointer
++;
1869 if (saw_comma
|| saw_colon
|| !saw_arg
)
1875 input_line_pointer
++;
1876 if (saw_comma
|| saw_colon
|| !saw_arg
)
1882 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1885 arg_end
= input_line_pointer
+ 1;
1886 while (!expression_end (arg_end
))
1889 arg_len
= arg_end
- input_line_pointer
;
1890 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1891 args
[num_args
] = arg
;
1895 strncpy (arg
, input_line_pointer
, arg_len
);
1896 arg
[arg_len
] = '\0';
1898 input_line_pointer
= arg_end
;
1908 if (saw_comma
|| saw_colon
)
1910 input_line_pointer
= old_input_line_pointer
;
1915 as_bad (_("extra comma"));
1917 as_bad (_("extra colon"));
1919 as_bad (_("missing argument"));
1921 as_bad (_("missing comma or colon"));
1922 input_line_pointer
= old_input_line_pointer
;
1927 /* Parse the arguments to an opcode. Return TRUE on error. */
1930 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1932 expressionS
*tok
, *last_tok
;
1933 xtensa_opcode opcode
= insn
->opcode
;
1934 bfd_boolean had_error
= TRUE
;
1935 xtensa_isa isa
= xtensa_default_isa
;
1936 int n
, num_regs
= 0;
1937 int opcode_operand_count
;
1938 int opnd_cnt
, last_opnd_cnt
;
1939 unsigned int next_reg
= 0;
1940 char *old_input_line_pointer
;
1942 if (insn
->insn_type
== ITYPE_LITERAL
)
1943 opcode_operand_count
= 1;
1945 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1948 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1950 /* Save and restore input_line_pointer around this function. */
1951 old_input_line_pointer
= input_line_pointer
;
1957 /* Skip invisible operands. */
1958 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1964 for (n
= 0; n
< num_args
; n
++)
1966 input_line_pointer
= arg_strings
[n
];
1967 if (*input_line_pointer
== ':')
1969 xtensa_regfile opnd_rf
;
1970 input_line_pointer
++;
1973 assert (opnd_cnt
> 0);
1975 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1977 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1978 as_warn (_("incorrect register number, ignoring"));
1983 if (opnd_cnt
>= opcode_operand_count
)
1985 as_warn (_("too many arguments"));
1988 assert (opnd_cnt
< MAX_INSN_ARGS
);
1990 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1991 next_reg
= tok
->X_add_number
+ 1;
1993 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1995 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1997 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1998 /* minus 1 because we are seeing one right now */
2004 last_opnd_cnt
= opnd_cnt
;
2011 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2015 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2018 insn
->ntok
= tok
- insn
->tok
;
2022 input_line_pointer
= old_input_line_pointer
;
2028 get_invisible_operands (TInsn
*insn
)
2030 xtensa_isa isa
= xtensa_default_isa
;
2031 static xtensa_insnbuf slotbuf
= NULL
;
2033 xtensa_opcode opc
= insn
->opcode
;
2034 int slot
, opnd
, fmt_found
;
2038 slotbuf
= xtensa_insnbuf_alloc (isa
);
2040 /* Find format/slot where this can be encoded. */
2043 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2045 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2047 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2053 if (fmt_found
) break;
2058 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2062 /* First encode all the visible operands
2063 (to deal with shared field operands). */
2064 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2066 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2067 && (insn
->tok
[opnd
].X_op
== O_register
2068 || insn
->tok
[opnd
].X_op
== O_constant
))
2070 val
= insn
->tok
[opnd
].X_add_number
;
2071 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2072 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2076 /* Then pull out the values for the invisible ones. */
2077 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2079 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2081 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2082 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2083 insn
->tok
[opnd
].X_add_number
= val
;
2084 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2085 insn
->tok
[opnd
].X_op
= O_register
;
2087 insn
->tok
[opnd
].X_op
= O_constant
;
2096 xg_reverse_shift_count (char **cnt_argp
)
2098 char *cnt_arg
, *new_arg
;
2099 cnt_arg
= *cnt_argp
;
2101 /* replace the argument with "31-(argument)" */
2102 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2103 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2106 *cnt_argp
= new_arg
;
2110 /* If "arg" is a constant expression, return non-zero with the value
2114 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2117 char *save_ptr
= input_line_pointer
;
2119 input_line_pointer
= arg
;
2121 input_line_pointer
= save_ptr
;
2123 if (exp
.X_op
== O_constant
)
2125 *valp
= exp
.X_add_number
;
2134 xg_replace_opname (char **popname
, char *newop
)
2137 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2138 strcpy (*popname
, newop
);
2143 xg_check_num_args (int *pnum_args
,
2148 int num_args
= *pnum_args
;
2150 if (num_args
< expected_num
)
2152 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2153 num_args
, opname
, expected_num
);
2157 if (num_args
> expected_num
)
2159 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2160 num_args
, opname
, expected_num
);
2161 while (num_args
-- > expected_num
)
2163 free (arg_strings
[num_args
]);
2164 arg_strings
[num_args
] = 0;
2166 *pnum_args
= expected_num
;
2174 /* If the register is not specified as part of the opcode,
2175 then get it from the operand and move it to the opcode. */
2178 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2180 xtensa_isa isa
= xtensa_default_isa
;
2182 char *opname
, *new_opname
;
2183 const char *sr_name
;
2184 int is_user
, is_write
;
2189 is_user
= (opname
[1] == 'u');
2190 is_write
= (opname
[0] == 'w');
2192 /* Opname == [rw]ur or [rwx]sr... */
2194 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2197 /* Check if the argument is a symbolic register name. */
2198 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2199 /* Handle WSR to "INTSET" as a special case. */
2200 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2201 && !strcasecmp (arg_strings
[1], "intset"))
2202 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2203 if (sr
== XTENSA_UNDEFINED
2204 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2206 /* Maybe it's a register number.... */
2208 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2210 as_bad (_("invalid register '%s' for '%s' instruction"),
2211 arg_strings
[1], opname
);
2214 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2215 if (sr
== XTENSA_UNDEFINED
)
2217 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2218 (long) val
, opname
);
2223 /* Remove the last argument, which is now part of the opcode. */
2224 free (arg_strings
[1]);
2228 /* Translate the opcode. */
2229 sr_name
= xtensa_sysreg_name (isa
, sr
);
2230 /* Another special case for "WSR.INTSET".... */
2231 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2233 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2234 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2236 *popname
= new_opname
;
2243 xtensa_translate_old_userreg_ops (char **popname
)
2245 xtensa_isa isa
= xtensa_default_isa
;
2247 char *opname
, *new_opname
;
2248 const char *sr_name
;
2249 bfd_boolean has_underbar
= FALSE
;
2252 if (opname
[0] == '_')
2254 has_underbar
= TRUE
;
2258 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2259 if (sr
!= XTENSA_UNDEFINED
)
2261 /* The new default name ("nnn") is different from the old default
2262 name ("URnnn"). The old default is handled below, and we don't
2263 want to recognize [RW]nnn, so do nothing if the name is the (new)
2265 static char namebuf
[10];
2266 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2267 if (strcmp (namebuf
, opname
+ 1) == 0)
2275 /* Only continue if the reg name is "URnnn". */
2276 if (opname
[1] != 'u' || opname
[2] != 'r')
2278 val
= strtoul (opname
+ 3, &end
, 10);
2282 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2283 if (sr
== XTENSA_UNDEFINED
)
2285 as_bad (_("invalid register number (%ld) for '%s'"),
2286 (long) val
, opname
);
2291 /* Translate the opcode. */
2292 sr_name
= xtensa_sysreg_name (isa
, sr
);
2293 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2294 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2295 opname
[0], sr_name
);
2297 *popname
= new_opname
;
2304 xtensa_translate_zero_immed (char *old_op
,
2314 assert (opname
[0] != '_');
2316 if (strcmp (opname
, old_op
) != 0)
2319 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2321 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2323 xg_replace_opname (popname
, new_op
);
2324 free (arg_strings
[1]);
2325 arg_strings
[1] = arg_strings
[2];
2334 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2335 Returns non-zero if an error was found. */
2338 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2340 char *opname
= *popname
;
2341 bfd_boolean has_underbar
= FALSE
;
2343 if (cur_vinsn
.inside_bundle
)
2348 has_underbar
= TRUE
;
2352 if (strcmp (opname
, "mov") == 0)
2354 if (use_transform () && !has_underbar
&& density_supported
)
2355 xg_replace_opname (popname
, "mov.n");
2358 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2360 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2361 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2362 strcpy (arg_strings
[2], arg_strings
[1]);
2368 if (strcmp (opname
, "bbsi.l") == 0)
2370 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2373 if (target_big_endian
)
2374 xg_reverse_shift_count (&arg_strings
[1]);
2378 if (strcmp (opname
, "bbci.l") == 0)
2380 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2382 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2383 if (target_big_endian
)
2384 xg_reverse_shift_count (&arg_strings
[1]);
2388 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2389 && strcmp (opname
, "nop") == 0)
2391 if (use_transform () && !has_underbar
&& density_supported
)
2392 xg_replace_opname (popname
, "nop.n");
2395 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2397 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2398 arg_strings
[0] = (char *) xmalloc (3);
2399 arg_strings
[1] = (char *) xmalloc (3);
2400 arg_strings
[2] = (char *) xmalloc (3);
2401 strcpy (arg_strings
[0], "a1");
2402 strcpy (arg_strings
[1], "a1");
2403 strcpy (arg_strings
[2], "a1");
2409 /* Recognize [RW]UR and [RWX]SR. */
2410 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2411 && (opname
[1] == 'u' || opname
[1] == 's'))
2412 || (opname
[0] == 'x' && opname
[1] == 's'))
2414 && opname
[3] == '\0')
2415 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2417 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2418 [RW]<name> if <name> is the non-default name of a user register. */
2419 if ((opname
[0] == 'r' || opname
[0] == 'w')
2420 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2421 return xtensa_translate_old_userreg_ops (popname
);
2423 /* Relax branches that don't allow comparisons against an immediate value
2424 of zero to the corresponding branches with implicit zero immediates. */
2425 if (!has_underbar
&& use_transform ())
2427 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2428 pnum_args
, arg_strings
))
2431 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2432 pnum_args
, arg_strings
))
2435 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2436 pnum_args
, arg_strings
))
2439 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2440 pnum_args
, arg_strings
))
2448 /* Functions for dealing with the Xtensa ISA. */
2450 /* Currently the assembler only allows us to use a single target per
2451 fragment. Because of this, only one operand for a given
2452 instruction may be symbolic. If there is a PC-relative operand,
2453 the last one is chosen. Otherwise, the result is the number of the
2454 last immediate operand, and if there are none of those, we fail and
2458 get_relaxable_immed (xtensa_opcode opcode
)
2460 int last_immed
= -1;
2463 if (opcode
== XTENSA_UNDEFINED
)
2466 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2467 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2469 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2471 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2473 if (last_immed
== -1
2474 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2481 static xtensa_opcode
2482 get_opcode_from_buf (const char *buf
, int slot
)
2484 static xtensa_insnbuf insnbuf
= NULL
;
2485 static xtensa_insnbuf slotbuf
= NULL
;
2486 xtensa_isa isa
= xtensa_default_isa
;
2491 insnbuf
= xtensa_insnbuf_alloc (isa
);
2492 slotbuf
= xtensa_insnbuf_alloc (isa
);
2495 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2496 fmt
= xtensa_format_decode (isa
, insnbuf
);
2497 if (fmt
== XTENSA_UNDEFINED
)
2498 return XTENSA_UNDEFINED
;
2500 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2501 return XTENSA_UNDEFINED
;
2503 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2504 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2508 #ifdef TENSILICA_DEBUG
2510 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2513 xtensa_print_insn_table (void)
2515 int num_opcodes
, num_operands
;
2516 xtensa_opcode opcode
;
2517 xtensa_isa isa
= xtensa_default_isa
;
2519 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2520 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2523 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2524 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2525 for (opn
= 0; opn
< num_operands
; opn
++)
2527 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2529 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2531 xtensa_regfile opnd_rf
=
2532 xtensa_operand_regfile (isa
, opcode
, opn
);
2533 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2535 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2536 fputs ("[lLr] ", stderr
);
2538 fputs ("i ", stderr
);
2540 fprintf (stderr
, "\n");
2546 print_vliw_insn (xtensa_insnbuf vbuf
)
2548 xtensa_isa isa
= xtensa_default_isa
;
2549 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2550 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2553 fprintf (stderr
, "format = %d\n", f
);
2555 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2557 xtensa_opcode opcode
;
2561 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2562 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2563 opname
= xtensa_opcode_name (isa
, opcode
);
2565 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2566 fprintf (stderr
, " operands = ");
2568 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2572 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2574 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2575 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2576 fprintf (stderr
, "%d ", val
);
2578 fprintf (stderr
, "\n");
2580 xtensa_insnbuf_free (isa
, sbuf
);
2583 #endif /* TENSILICA_DEBUG */
2587 is_direct_call_opcode (xtensa_opcode opcode
)
2589 xtensa_isa isa
= xtensa_default_isa
;
2590 int n
, num_operands
;
2592 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2595 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2596 for (n
= 0; n
< num_operands
; n
++)
2598 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2599 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2606 /* Convert from BFD relocation type code to slot and operand number.
2607 Returns non-zero on failure. */
2610 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2612 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2613 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2615 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2618 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2619 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2621 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2631 /* Convert from slot number to BFD relocation type code for the
2632 standard PC-relative relocations. Return BFD_RELOC_NONE on
2635 static bfd_reloc_code_real_type
2636 encode_reloc (int slot
)
2638 if (slot
< 0 || slot
> 14)
2639 return BFD_RELOC_NONE
;
2641 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2645 /* Convert from slot numbers to BFD relocation type code for the
2646 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2648 static bfd_reloc_code_real_type
2649 encode_alt_reloc (int slot
)
2651 if (slot
< 0 || slot
> 14)
2652 return BFD_RELOC_NONE
;
2654 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2659 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2662 xtensa_opcode opcode
,
2668 uint32 valbuf
= value
;
2670 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2672 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2674 as_bad_where ((char *) file
, line
,
2675 _("operand %d of '%s' has out of range value '%u'"),
2677 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2680 as_bad_where ((char *) file
, line
,
2681 _("operand %d of '%s' has invalid value '%u'"),
2683 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2688 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2694 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2697 xtensa_opcode opcode
,
2701 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2702 fmt
, slot
, slotbuf
, &val
);
2703 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2708 /* Checks for rules from xtensa-relax tables. */
2710 /* The routine xg_instruction_matches_option_term must return TRUE
2711 when a given option term is true. The meaning of all of the option
2712 terms is given interpretation by this function. This is needed when
2713 an option depends on the state of a directive, but there are no such
2714 options in use right now. */
2717 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2718 const ReqOrOption
*option
)
2720 if (strcmp (option
->option_name
, "realnop") == 0
2721 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2723 /* These conditions were evaluated statically when building the
2724 relaxation table. There's no need to reevaluate them now. */
2729 as_fatal (_("internal error: unknown option name '%s'"),
2730 option
->option_name
);
2736 xg_instruction_matches_or_options (TInsn
*insn
,
2737 const ReqOrOptionList
*or_option
)
2739 const ReqOrOption
*option
;
2740 /* Must match each of the AND terms. */
2741 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2743 if (xg_instruction_matches_option_term (insn
, option
))
2751 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2753 const ReqOption
*req_options
;
2754 /* Must match each of the AND terms. */
2755 for (req_options
= options
;
2756 req_options
!= NULL
;
2757 req_options
= req_options
->next
)
2759 /* Must match one of the OR clauses. */
2760 if (!xg_instruction_matches_or_options (insn
,
2761 req_options
->or_option_terms
))
2768 /* Return the transition rule that matches or NULL if none matches. */
2771 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2773 PreconditionList
*condition_l
;
2775 if (rule
->opcode
!= insn
->opcode
)
2778 for (condition_l
= rule
->conditions
;
2779 condition_l
!= NULL
;
2780 condition_l
= condition_l
->next
)
2784 Precondition
*cond
= condition_l
->precond
;
2789 /* The expression must be the constant. */
2790 assert (cond
->op_num
< insn
->ntok
);
2791 exp1
= &insn
->tok
[cond
->op_num
];
2792 if (expr_is_const (exp1
))
2797 if (get_expr_const (exp1
) != cond
->op_data
)
2801 if (get_expr_const (exp1
) == cond
->op_data
)
2808 else if (expr_is_register (exp1
))
2813 if (get_expr_register (exp1
) != cond
->op_data
)
2817 if (get_expr_register (exp1
) == cond
->op_data
)
2829 assert (cond
->op_num
< insn
->ntok
);
2830 assert (cond
->op_data
< insn
->ntok
);
2831 exp1
= &insn
->tok
[cond
->op_num
];
2832 exp2
= &insn
->tok
[cond
->op_data
];
2837 if (!expr_is_equal (exp1
, exp2
))
2841 if (expr_is_equal (exp1
, exp2
))
2853 if (!xg_instruction_matches_options (insn
, rule
->options
))
2861 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2863 bfd_boolean a_greater
= FALSE
;
2864 bfd_boolean b_greater
= FALSE
;
2866 ReqOptionList
*l_a
= a
->options
;
2867 ReqOptionList
*l_b
= b
->options
;
2869 /* We only care if they both are the same except for
2870 a const16 vs. an l32r. */
2872 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2874 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2875 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2876 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2878 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2880 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2882 /* This is the case we care about. */
2883 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2884 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2891 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2892 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2902 l_or_a
= l_or_a
->next
;
2903 l_or_b
= l_or_b
->next
;
2905 if (l_or_a
|| l_or_b
)
2914 /* Incomparable if the substitution was used differently in two cases. */
2915 if (a_greater
&& b_greater
)
2927 static TransitionRule
*
2928 xg_instruction_match (TInsn
*insn
)
2930 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2932 assert (insn
->opcode
< table
->num_opcodes
);
2934 /* Walk through all of the possible transitions. */
2935 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2937 TransitionRule
*rule
= l
->rule
;
2938 if (xg_instruction_matches_rule (insn
, rule
))
2945 /* Various Other Internal Functions. */
2948 is_unique_insn_expansion (TransitionRule
*r
)
2950 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2952 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2958 /* Check if there is exactly one relaxation for INSN that converts it to
2959 another instruction of equal or larger size. If so, and if TARG is
2960 non-null, go ahead and generate the relaxed instruction into TARG. If
2961 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2962 instruction, i.e., ignore relaxations that convert to an instruction of
2963 equal size. In some contexts where this function is used, only
2964 a single widening is allowed and the NARROW_ONLY argument is used to
2965 exclude cases like ADDI being "widened" to an ADDMI, which may
2966 later be relaxed to an ADDMI/ADDI pair. */
2969 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2971 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2973 TransitionRule
*match
= 0;
2975 assert (insn
->insn_type
== ITYPE_INSN
);
2976 assert (insn
->opcode
< table
->num_opcodes
);
2978 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2980 TransitionRule
*rule
= l
->rule
;
2982 if (xg_instruction_matches_rule (insn
, rule
)
2983 && is_unique_insn_expansion (rule
)
2984 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2985 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2996 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3001 /* Return the maximum number of bytes this opcode can expand to. */
3004 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3008 int max_size
= xg_get_single_size (opcode
);
3010 assert (opcode
< table
->num_opcodes
);
3012 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3014 TransitionRule
*rule
= l
->rule
;
3015 BuildInstr
*build_list
;
3020 build_list
= rule
->to_instr
;
3021 if (is_unique_insn_expansion (rule
))
3023 assert (build_list
->typ
== INSTR_INSTR
);
3024 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3027 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3029 switch (build_list
->typ
)
3032 this_size
+= xg_get_single_size (build_list
->opcode
);
3034 case INSTR_LITERAL_DEF
:
3035 case INSTR_LABEL_DEF
:
3040 if (this_size
> max_size
)
3041 max_size
= this_size
;
3047 /* Return the maximum number of literal bytes this opcode can generate. */
3050 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3056 assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3077 case INSTR_LITERAL_DEF
:
3078 /* Hard-coded 4-byte literal. */
3082 case INSTR_LABEL_DEF
:
3087 if (this_size
> max_size
)
3088 max_size
= this_size
;
3095 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3097 int steps_taken
= 0;
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3101 assert (insn
->insn_type
== ITYPE_INSN
);
3102 assert (insn
->opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3108 if (xg_instruction_matches_rule (insn
, rule
))
3110 if (steps_taken
== lateral_steps
)
3120 get_special_literal_symbol (void)
3122 static symbolS
*sym
= NULL
;
3125 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3131 get_special_label_symbol (void)
3133 static symbolS
*sym
= NULL
;
3136 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3142 xg_valid_literal_expression (const expressionS
*exp
)
3159 /* This will check to see if the value can be converted into the
3160 operand type. It will return TRUE if it does not fit. */
3163 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3165 uint32 valbuf
= value
;
3166 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3172 /* Assumes: All immeds are constants. Check that all constants fit
3173 into their immeds; return FALSE if not. */
3176 xg_immeds_fit (const TInsn
*insn
)
3178 xtensa_isa isa
= xtensa_default_isa
;
3182 assert (insn
->insn_type
== ITYPE_INSN
);
3183 for (i
= 0; i
< n
; ++i
)
3185 const expressionS
*expr
= &insn
->tok
[i
];
3186 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3193 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3198 /* The symbol should have a fixup associated with it. */
3207 /* This should only be called after we have an initial
3208 estimate of the addresses. */
3211 xg_symbolic_immeds_fit (const TInsn
*insn
,
3217 xtensa_isa isa
= xtensa_default_isa
;
3225 assert (insn
->insn_type
== ITYPE_INSN
);
3227 for (i
= 0; i
< n
; ++i
)
3229 const expressionS
*expr
= &insn
->tok
[i
];
3230 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3237 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3243 /* Check for the worst case. */
3244 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3249 /* We only allow symbols for PC-relative references.
3250 If pc_frag == 0, then we don't have frag locations yet. */
3252 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3255 /* If it is a weak symbol, then assume it won't reach. */
3256 if (S_IS_WEAK (expr
->X_add_symbol
))
3259 if (is_direct_call_opcode (insn
->opcode
)
3260 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3262 /* If callee is undefined or in a different segment, be
3263 optimistic and assume it will be in range. */
3264 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3268 /* Only references within a segment can be known to fit in the
3269 operands at assembly time. */
3270 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3273 symbolP
= expr
->X_add_symbol
;
3274 sym_frag
= symbol_get_frag (symbolP
);
3275 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3276 pc
= pc_frag
->fr_address
+ pc_offset
;
3278 /* If frag has yet to be reached on this pass, assume it
3279 will move by STRETCH just as we did. If this is not so,
3280 it will be because some frag between grows, and that will
3281 force another pass. Beware zero-length frags. There
3282 should be a faster way to do this. */
3285 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3286 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3291 new_offset
= target
;
3292 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3293 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3298 /* The symbol should have a fixup associated with it. */
3307 /* Return TRUE on success. */
3310 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3315 memset (targ
, 0, sizeof (TInsn
));
3316 targ
->linenum
= insn
->linenum
;
3321 targ
->opcode
= bi
->opcode
;
3322 targ
->insn_type
= ITYPE_INSN
;
3323 targ
->is_specific_opcode
= FALSE
;
3325 for (; op
!= NULL
; op
= op
->next
)
3327 int op_num
= op
->op_num
;
3328 int op_data
= op
->op_data
;
3330 assert (op
->op_num
< MAX_INSN_ARGS
);
3332 if (targ
->ntok
<= op_num
)
3333 targ
->ntok
= op_num
+ 1;
3338 set_expr_const (&targ
->tok
[op_num
], op_data
);
3341 assert (op_data
< insn
->ntok
);
3342 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3345 sym
= get_special_literal_symbol ();
3346 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3349 sym
= get_special_label_symbol ();
3350 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3352 case OP_OPERAND_HI16U
:
3353 case OP_OPERAND_LOW16U
:
3354 assert (op_data
< insn
->ntok
);
3355 if (expr_is_const (&insn
->tok
[op_data
]))
3358 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3359 val
= xg_apply_userdef_op_fn (op
->typ
,
3362 targ
->tok
[op_num
].X_add_number
= val
;
3366 /* For const16 we can create relocations for these. */
3367 if (targ
->opcode
== XTENSA_UNDEFINED
3368 || (targ
->opcode
!= xtensa_const16_opcode
))
3370 assert (op_data
< insn
->ntok
);
3371 /* Need to build a O_lo16 or O_hi16. */
3372 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3373 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3375 if (op
->typ
== OP_OPERAND_HI16U
)
3376 targ
->tok
[op_num
].X_op
= O_hi16
;
3377 else if (op
->typ
== OP_OPERAND_LOW16U
)
3378 targ
->tok
[op_num
].X_op
= O_lo16
;
3385 /* currently handles:
3388 OP_OPERAND_F32MINUS */
3389 if (xg_has_userdef_op_fn (op
->typ
))
3391 assert (op_data
< insn
->ntok
);
3392 if (expr_is_const (&insn
->tok
[op_data
]))
3395 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3396 val
= xg_apply_userdef_op_fn (op
->typ
,
3399 targ
->tok
[op_num
].X_add_number
= val
;
3402 return FALSE
; /* We cannot use a relocation for this. */
3411 case INSTR_LITERAL_DEF
:
3413 targ
->opcode
= XTENSA_UNDEFINED
;
3414 targ
->insn_type
= ITYPE_LITERAL
;
3415 targ
->is_specific_opcode
= FALSE
;
3416 for (; op
!= NULL
; op
= op
->next
)
3418 int op_num
= op
->op_num
;
3419 int op_data
= op
->op_data
;
3420 assert (op
->op_num
< MAX_INSN_ARGS
);
3422 if (targ
->ntok
<= op_num
)
3423 targ
->ntok
= op_num
+ 1;
3428 assert (op_data
< insn
->ntok
);
3429 /* We can only pass resolvable literals through. */
3430 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3432 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3444 case INSTR_LABEL_DEF
:
3446 targ
->opcode
= XTENSA_UNDEFINED
;
3447 targ
->insn_type
= ITYPE_LABEL
;
3448 targ
->is_specific_opcode
= FALSE
;
3449 /* Literal with no ops is a label? */
3450 assert (op
== NULL
);
3461 /* Return TRUE on success. */
3464 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3466 for (; bi
!= NULL
; bi
= bi
->next
)
3468 TInsn
*next_insn
= istack_push_space (istack
);
3470 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3477 /* Return TRUE on valid expansion. */
3480 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3482 int stack_size
= istack
->ninsn
;
3483 int steps_taken
= 0;
3484 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3487 assert (insn
->insn_type
== ITYPE_INSN
);
3488 assert (insn
->opcode
< table
->num_opcodes
);
3490 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3492 TransitionRule
*rule
= l
->rule
;
3494 if (xg_instruction_matches_rule (insn
, rule
))
3496 if (lateral_steps
== steps_taken
)
3500 /* This is it. Expand the rule to the stack. */
3501 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3504 /* Check to see if it fits. */
3505 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3507 TInsn
*insn
= &istack
->insn
[i
];
3509 if (insn
->insn_type
== ITYPE_INSN
3510 && !tinsn_has_symbolic_operands (insn
)
3511 && !xg_immeds_fit (insn
))
3513 istack
->ninsn
= stack_size
;
3526 /* Relax the assembly instruction at least "min_steps".
3527 Return the number of steps taken. */
3530 xg_assembly_relax (IStack
*istack
,
3533 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3534 offsetT pc_offset
, /* offset in fragment */
3535 int min_steps
, /* minimum conversion steps */
3536 long stretch
) /* number of bytes stretched so far */
3538 int steps_taken
= 0;
3540 /* assert (has no symbolic operands)
3541 Some of its immeds don't fit.
3542 Try to build a relaxed version.
3543 This may go through a couple of stages
3544 of single instruction transformations before
3547 TInsn single_target
;
3549 int lateral_steps
= 0;
3550 int istack_size
= istack
->ninsn
;
3552 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3553 && steps_taken
>= min_steps
)
3555 istack_push (istack
, insn
);
3558 current_insn
= *insn
;
3560 /* Walk through all of the single instruction expansions. */
3561 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3564 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3567 if (steps_taken
>= min_steps
)
3569 istack_push (istack
, &single_target
);
3573 current_insn
= single_target
;
3576 /* Now check for a multi-instruction expansion. */
3577 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3579 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3582 if (steps_taken
>= min_steps
)
3584 istack_push (istack
, ¤t_insn
);
3589 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3591 if (steps_taken
>= min_steps
)
3595 istack
->ninsn
= istack_size
;
3598 /* It's not going to work -- use the original. */
3599 istack_push (istack
, insn
);
3605 xg_force_frag_space (int size
)
3607 /* This may have the side effect of creating a new fragment for the
3608 space to go into. I just do not like the name of the "frag"
3615 xg_finish_frag (char *last_insn
,
3616 enum xtensa_relax_statesE frag_state
,
3617 enum xtensa_relax_statesE slot0_state
,
3619 bfd_boolean is_insn
)
3621 /* Finish off this fragment so that it has at LEAST the desired
3622 max_growth. If it doesn't fit in this fragment, close this one
3623 and start a new one. In either case, return a pointer to the
3624 beginning of the growth area. */
3628 xg_force_frag_space (max_growth
);
3630 old_frag
= frag_now
;
3632 frag_now
->fr_opcode
= last_insn
;
3634 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3636 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3637 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3639 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3640 xtensa_set_frag_assembly_state (frag_now
);
3642 /* Just to make sure that we did not split it up. */
3643 assert (old_frag
->fr_next
== frag_now
);
3647 /* Return TRUE if the target frag is one of the next non-empty frags. */
3650 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3655 for (; fragP
; fragP
= fragP
->fr_next
)
3657 if (fragP
== target
)
3659 if (fragP
->fr_fix
!= 0)
3661 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3663 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3664 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3666 if (fragP
->fr_type
== rs_space
)
3674 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3676 xtensa_isa isa
= xtensa_default_isa
;
3678 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3683 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3684 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3687 for (i
= 0; i
< num_ops
; i
++)
3689 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3695 if (target_op
== -1)
3698 if (insn
->ntok
<= target_op
)
3701 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3704 sym
= insn
->tok
[target_op
].X_add_symbol
;
3708 if (insn
->tok
[target_op
].X_add_number
!= 0)
3711 target_frag
= symbol_get_frag (sym
);
3712 if (target_frag
== NULL
)
3715 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3716 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3724 xg_add_branch_and_loop_targets (TInsn
*insn
)
3726 xtensa_isa isa
= xtensa_default_isa
;
3727 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3729 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3732 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3733 && insn
->tok
[i
].X_op
== O_symbol
)
3734 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3738 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3739 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3743 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3745 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3746 && insn
->tok
[i
].X_op
== O_symbol
)
3748 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3749 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3750 if (S_IS_DEFINED (sym
))
3751 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3758 /* Return FALSE if no error. */
3761 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3766 switch (instr_spec
->typ
)
3769 new_insn
->insn_type
= ITYPE_INSN
;
3770 new_insn
->opcode
= instr_spec
->opcode
;
3771 new_insn
->is_specific_opcode
= FALSE
;
3772 new_insn
->linenum
= old_insn
->linenum
;
3774 case INSTR_LITERAL_DEF
:
3775 new_insn
->insn_type
= ITYPE_LITERAL
;
3776 new_insn
->opcode
= XTENSA_UNDEFINED
;
3777 new_insn
->is_specific_opcode
= FALSE
;
3778 new_insn
->linenum
= old_insn
->linenum
;
3780 case INSTR_LABEL_DEF
:
3781 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3785 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3788 const expressionS
*src_exp
;
3794 /* The expression must be the constant. */
3795 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3796 exp
= &new_insn
->tok
[b_op
->op_num
];
3797 set_expr_const (exp
, b_op
->op_data
);
3801 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3802 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3803 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3804 exp
= &new_insn
->tok
[b_op
->op_num
];
3805 copy_expr (exp
, src_exp
);
3810 as_bad (_("can't handle generation of literal/labels yet"));
3814 as_bad (_("can't handle undefined OP TYPE"));
3819 new_insn
->ntok
= num_ops
;
3824 /* Return TRUE if it was simplified. */
3827 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3829 TransitionRule
*rule
;
3830 BuildInstr
*insn_spec
;
3832 if (old_insn
->is_specific_opcode
|| !density_supported
)
3835 rule
= xg_instruction_match (old_insn
);
3839 insn_spec
= rule
->to_instr
;
3840 /* There should only be one. */
3841 assert (insn_spec
!= NULL
);
3842 assert (insn_spec
->next
== NULL
);
3843 if (insn_spec
->next
!= NULL
)
3846 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3852 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3853 l32i.n. (2) Check the number of operands. (3) Place the instruction
3854 tokens into the stack or relax it and place multiple
3855 instructions/literals onto the stack. Return FALSE if no error. */
3858 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3862 bfd_boolean do_expand
;
3864 memset (&new_insn
, 0, sizeof (TInsn
));
3866 /* Narrow it if we can. xg_simplify_insn now does all the
3867 appropriate checking (e.g., for the density option). */
3868 if (xg_simplify_insn (orig_insn
, &new_insn
))
3869 orig_insn
= &new_insn
;
3871 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3873 if (orig_insn
->ntok
< noperands
)
3875 as_bad (_("found %d operands for '%s': Expected %d"),
3877 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3881 if (orig_insn
->ntok
> noperands
)
3882 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3884 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3887 /* If there are not enough operands, we will assert above. If there
3888 are too many, just cut out the extras here. */
3889 orig_insn
->ntok
= noperands
;
3891 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3894 /* If the instruction will definitely need to be relaxed, it is better
3895 to expand it now for better scheduling. Decide whether to expand
3897 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3899 /* Calls should be expanded to longcalls only in the backend relaxation
3900 so that the assembly scheduler will keep the L32R/CALLX instructions
3902 if (is_direct_call_opcode (orig_insn
->opcode
))
3905 if (tinsn_has_symbolic_operands (orig_insn
))
3907 /* The values of symbolic operands are not known yet, so only expand
3908 now if an operand is "complex" (e.g., difference of symbols) and
3909 will have to be stored as a literal regardless of the value. */
3910 if (!tinsn_has_complex_operands (orig_insn
))
3913 else if (xg_immeds_fit (orig_insn
))
3917 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3919 istack_push (istack
, orig_insn
);
3925 /* Return TRUE if the section flags are marked linkonce
3926 or the name is .gnu.linkonce*. */
3929 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3931 flagword flags
, link_once_flags
;
3933 flags
= bfd_get_section_flags (abfd
, sec
);
3934 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3936 /* Flags might not be set yet. */
3937 if (!link_once_flags
)
3939 static size_t len
= sizeof ".gnu.linkonce.t.";
3941 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3942 link_once_flags
= SEC_LINK_ONCE
;
3944 return (link_once_flags
!= 0);
3949 xtensa_add_literal_sym (symbolS
*sym
)
3953 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3955 l
->next
= literal_syms
;
3961 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3963 static int lit_num
= 0;
3964 static char name
[256];
3967 sprintf (name
, ".L_lit_sym%d", lit_num
);
3969 /* Create a local symbol. If it is in a linkonce section, we have to
3970 be careful to make sure that if it is used in a relocation that the
3971 symbol will be in the output file. */
3972 if (get_is_linkonce_section (stdoutput
, sec
))
3974 symbolP
= symbol_new (name
, sec
, 0, frag
);
3975 S_CLEAR_EXTERNAL (symbolP
);
3976 /* symbolP->local = 1; */
3979 symbolP
= symbol_new (name
, sec
, 0, frag
);
3981 xtensa_add_literal_sym (symbolP
);
3988 /* Currently all literals that are generated here are 32-bit L32R targets. */
3991 xg_assemble_literal (/* const */ TInsn
*insn
)
3994 symbolS
*lit_sym
= NULL
;
3996 /* size = 4 for L32R. It could easily be larger when we move to
3997 larger constants. Add a parameter later. */
3998 offsetT litsize
= 4;
3999 offsetT litalign
= 2; /* 2^2 = 4 */
4000 expressionS saved_loc
;
4001 expressionS
* emit_val
;
4003 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4005 assert (insn
->insn_type
== ITYPE_LITERAL
);
4006 assert (insn
->ntok
== 1); /* must be only one token here */
4008 xtensa_switch_to_literal_fragment (&state
);
4010 emit_val
= &insn
->tok
[0];
4011 if (emit_val
->X_op
== O_big
)
4013 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4016 /* This happens when someone writes a "movi a2, big_number". */
4017 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4018 _("invalid immediate"));
4019 xtensa_restore_emit_state (&state
);
4024 /* Force a 4-byte align here. Note that this opens a new frag, so all
4025 literals done with this function have a frag to themselves. That's
4026 important for the way text section literals work. */
4027 frag_align (litalign
, 0, 0);
4028 record_alignment (now_seg
, litalign
);
4030 if (emit_val
->X_op
== O_pltrel
)
4032 char *p
= frag_more (litsize
);
4033 xtensa_set_frag_assembly_state (frag_now
);
4034 if (emit_val
->X_add_symbol
)
4035 emit_val
->X_op
= O_symbol
;
4037 emit_val
->X_op
= O_constant
;
4038 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4039 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4042 emit_expr (emit_val
, litsize
);
4044 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4045 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4046 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4047 lit_sym
= frag_now
->fr_symbol
;
4050 xtensa_restore_emit_state (&state
);
4056 xg_assemble_literal_space (/* const */ int size
, int slot
)
4059 /* We might have to do something about this alignment. It only
4060 takes effect if something is placed here. */
4061 offsetT litalign
= 2; /* 2^2 = 4 */
4062 fragS
*lit_saved_frag
;
4064 assert (size
% 4 == 0);
4066 xtensa_switch_to_literal_fragment (&state
);
4068 /* Force a 4-byte align here. */
4069 frag_align (litalign
, 0, 0);
4070 record_alignment (now_seg
, litalign
);
4072 xg_force_frag_space (size
);
4074 lit_saved_frag
= frag_now
;
4075 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4076 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4077 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4080 xtensa_restore_emit_state (&state
);
4081 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4085 /* Put in a fixup record based on the opcode.
4086 Return TRUE on success. */
4089 xg_add_opcode_fix (TInsn
*tinsn
,
4097 xtensa_opcode opcode
= tinsn
->opcode
;
4098 bfd_reloc_code_real_type reloc
;
4099 reloc_howto_type
*howto
;
4103 reloc
= BFD_RELOC_NONE
;
4105 /* First try the special cases for "alternate" relocs. */
4106 if (opcode
== xtensa_l32r_opcode
)
4108 if (fragP
->tc_frag_data
.use_absolute_literals
)
4109 reloc
= encode_alt_reloc (slot
);
4111 else if (opcode
== xtensa_const16_opcode
)
4113 if (expr
->X_op
== O_lo16
)
4115 reloc
= encode_reloc (slot
);
4116 expr
->X_op
= O_symbol
;
4118 else if (expr
->X_op
== O_hi16
)
4120 reloc
= encode_alt_reloc (slot
);
4121 expr
->X_op
= O_symbol
;
4125 if (opnum
!= get_relaxable_immed (opcode
))
4127 as_bad (_("invalid relocation for operand %i of '%s'"),
4128 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4132 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4133 into the symbol table where the generic portions of the assembler
4134 won't know what to do with them. */
4135 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4137 as_bad (_("invalid expression for operand %i of '%s'"),
4138 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4142 /* Next try the generic relocs. */
4143 if (reloc
== BFD_RELOC_NONE
)
4144 reloc
= encode_reloc (slot
);
4145 if (reloc
== BFD_RELOC_NONE
)
4147 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4151 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4154 as_bad (_("undefined symbol for opcode \"%s\""),
4155 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4159 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4160 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4161 howto
->pc_relative
, reloc
);
4162 the_fix
->fx_no_overflow
= 1;
4164 if (expr
->X_add_symbol
4165 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4166 || S_IS_WEAK (expr
->X_add_symbol
)))
4167 the_fix
->fx_plt
= TRUE
;
4169 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4170 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4171 the_fix
->tc_fix_data
.slot
= slot
;
4178 xg_emit_insn_to_buf (TInsn
*tinsn
,
4182 bfd_boolean build_fix
)
4184 static xtensa_insnbuf insnbuf
= NULL
;
4185 bfd_boolean has_symbolic_immed
= FALSE
;
4186 bfd_boolean ok
= TRUE
;
4189 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4191 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4192 if (has_symbolic_immed
&& build_fix
)
4195 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4196 int slot
= xg_get_single_slot (tinsn
->opcode
);
4197 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4198 expressionS
*exp
= &tinsn
->tok
[opnum
];
4200 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4203 fragP
->tc_frag_data
.is_insn
= TRUE
;
4204 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4205 (unsigned char *) buf
, 0);
4211 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4213 symbolS
*sym
= get_special_literal_symbol ();
4217 assert (insn
->insn_type
== ITYPE_INSN
);
4218 for (i
= 0; i
< insn
->ntok
; i
++)
4219 if (insn
->tok
[i
].X_add_symbol
== sym
)
4220 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4226 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4228 symbolS
*sym
= get_special_label_symbol ();
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= label_sym
;
4237 /* Return TRUE if the instruction can write to the specified
4238 integer register. */
4241 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4245 xtensa_isa isa
= xtensa_default_isa
;
4247 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4249 for (i
= 0; i
< num_ops
; i
++)
4252 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4253 if ((inout
== 'o' || inout
== 'm')
4254 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4256 xtensa_regfile opnd_rf
=
4257 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4258 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4260 if ((insn
->tok
[i
].X_op
== O_register
)
4261 && (insn
->tok
[i
].X_add_number
== regnum
))
4271 is_bad_loopend_opcode (const TInsn
*tinsn
)
4273 xtensa_opcode opcode
= tinsn
->opcode
;
4275 if (opcode
== XTENSA_UNDEFINED
)
4278 if (opcode
== xtensa_call0_opcode
4279 || opcode
== xtensa_callx0_opcode
4280 || opcode
== xtensa_call4_opcode
4281 || opcode
== xtensa_callx4_opcode
4282 || opcode
== xtensa_call8_opcode
4283 || opcode
== xtensa_callx8_opcode
4284 || opcode
== xtensa_call12_opcode
4285 || opcode
== xtensa_callx12_opcode
4286 || opcode
== xtensa_isync_opcode
4287 || opcode
== xtensa_ret_opcode
4288 || opcode
== xtensa_ret_n_opcode
4289 || opcode
== xtensa_retw_opcode
4290 || opcode
== xtensa_retw_n_opcode
4291 || opcode
== xtensa_waiti_opcode
4292 || opcode
== xtensa_rsr_lcount_opcode
)
4299 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4300 This allows the debugger to add unaligned labels.
4301 Also, the assembler generates stabs labels that need
4302 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4305 is_unaligned_label (symbolS
*sym
)
4307 const char *name
= S_GET_NAME (sym
);
4308 static size_t fake_size
= 0;
4312 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4315 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4317 fake_size
= strlen (FAKE_LABEL_NAME
);
4320 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4321 && (name
[fake_size
] == 'F'
4322 || name
[fake_size
] == 'L'
4323 || (name
[fake_size
] == 'e'
4324 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4332 next_non_empty_frag (const fragS
*fragP
)
4334 fragS
*next_fragP
= fragP
->fr_next
;
4336 /* Sometimes an empty will end up here due storage allocation issues.
4337 So we have to skip until we find something legit. */
4338 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4339 next_fragP
= next_fragP
->fr_next
;
4341 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4349 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4351 xtensa_opcode out_opcode
;
4352 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4354 if (next_fragP
== NULL
)
4357 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4358 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4360 *opcode
= out_opcode
;
4368 frag_format_size (const fragS
*fragP
)
4370 static xtensa_insnbuf insnbuf
= NULL
;
4371 xtensa_isa isa
= xtensa_default_isa
;
4376 insnbuf
= xtensa_insnbuf_alloc (isa
);
4379 return XTENSA_UNDEFINED
;
4381 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4382 (unsigned char *) fragP
->fr_literal
, 0);
4384 fmt
= xtensa_format_decode (isa
, insnbuf
);
4385 if (fmt
== XTENSA_UNDEFINED
)
4386 return XTENSA_UNDEFINED
;
4387 fmt_size
= xtensa_format_length (isa
, fmt
);
4389 /* If the next format won't be changing due to relaxation, just
4390 return the length of the first format. */
4391 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4394 /* If during relaxation we have to pull an instruction out of a
4395 multi-slot instruction, we will return the more conservative
4396 number. This works because alignment on bigger instructions
4397 is more restrictive than alignment on smaller instructions.
4398 This is more conservative than we would like, but it happens
4401 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4404 /* If we aren't doing one of our own relaxations or it isn't
4405 slot-based, then the insn size won't change. */
4406 if (fragP
->fr_type
!= rs_machine_dependent
)
4408 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4411 /* If an instruction is about to grow, return the longer size. */
4412 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4413 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4416 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4417 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4424 next_frag_format_size (const fragS
*fragP
)
4426 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4427 return frag_format_size (next_fragP
);
4431 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4432 required two-byte instructions to be treated as three-byte instructions
4433 for loop instruction alignment. This restriction was removed beginning
4434 with Xtensa LX. Now the only requirement on loop instruction alignment
4435 is that the first instruction of the loop must appear at an address that
4436 does not cross a fetch boundary. */
4439 get_loop_align_size (int insn_size
)
4441 if (insn_size
== XTENSA_UNDEFINED
)
4442 return xtensa_fetch_width
;
4444 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4451 /* If the next legit fragment is an end-of-loop marker,
4452 switch its state so it will instantiate a NOP. */
4455 update_next_frag_state (fragS
*fragP
)
4457 fragS
*next_fragP
= fragP
->fr_next
;
4458 fragS
*new_target
= NULL
;
4462 /* We are guaranteed there will be one of these... */
4463 while (!(next_fragP
->fr_type
== rs_machine_dependent
4464 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4465 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4466 next_fragP
= next_fragP
->fr_next
;
4468 assert (next_fragP
->fr_type
== rs_machine_dependent
4469 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4470 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4472 /* ...and one of these. */
4473 new_target
= next_fragP
->fr_next
;
4474 while (!(new_target
->fr_type
== rs_machine_dependent
4475 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4476 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4477 new_target
= new_target
->fr_next
;
4479 assert (new_target
->fr_type
== rs_machine_dependent
4480 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4481 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4484 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4486 if (next_fragP
->fr_type
== rs_machine_dependent
4487 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4489 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4493 next_fragP
= next_fragP
->fr_next
;
4499 next_frag_is_branch_target (const fragS
*fragP
)
4501 /* Sometimes an empty will end up here due to storage allocation issues,
4502 so we have to skip until we find something legit. */
4503 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4505 if (fragP
->tc_frag_data
.is_branch_target
)
4507 if (fragP
->fr_fix
!= 0)
4515 next_frag_is_loop_target (const fragS
*fragP
)
4517 /* Sometimes an empty will end up here due storage allocation issues.
4518 So we have to skip until we find something legit. */
4519 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4521 if (fragP
->tc_frag_data
.is_loop_target
)
4523 if (fragP
->fr_fix
!= 0)
4531 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4533 const fragS
*next_fragp
= fragp
->fr_next
;
4534 xtensa_opcode next_opcode
;
4536 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4539 /* Sometimes an empty will end up here due to storage allocation issues,
4540 so we have to skip until we find something legit. */
4541 while (next_fragp
->fr_fix
== 0)
4542 next_fragp
= next_fragp
->fr_next
;
4544 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4547 /* There is some implicit knowledge encoded in here.
4548 The LOOP instructions that are NOT RELAX_IMMED have
4549 been relaxed. Note that we can assume that the LOOP
4550 instruction is in slot 0 because loops aren't bundleable. */
4551 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4552 return get_expanded_loop_offset (next_opcode
);
4558 /* Mark a location where we can later insert literal frags. Update
4559 the section's literal_pool_loc, so subsequent literals can be
4560 placed nearest to their use. */
4563 xtensa_mark_literal_pool_location (void)
4565 /* Any labels pointing to the current location need
4566 to be adjusted to after the literal pool. */
4568 fragS
*pool_location
;
4570 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4573 frag_align (2, 0, 0);
4574 record_alignment (now_seg
, 2);
4576 /* We stash info in these frags so we can later move the literal's
4577 fixes into this frchain's fix list. */
4578 pool_location
= frag_now
;
4579 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4580 frag_variant (rs_machine_dependent
, 0, 0,
4581 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4582 xtensa_set_frag_assembly_state (frag_now
);
4583 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4584 frag_variant (rs_machine_dependent
, 0, 0,
4585 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4586 xtensa_set_frag_assembly_state (frag_now
);
4588 /* Now put a frag into the literal pool that points to this location. */
4589 set_literal_pool_location (now_seg
, pool_location
);
4590 xtensa_switch_to_non_abs_literal_fragment (&s
);
4591 frag_align (2, 0, 0);
4592 record_alignment (now_seg
, 2);
4594 /* Close whatever frag is there. */
4595 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4596 xtensa_set_frag_assembly_state (frag_now
);
4597 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4598 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4599 xtensa_restore_emit_state (&s
);
4600 xtensa_set_frag_assembly_state (frag_now
);
4604 /* Build a nop of the correct size into tinsn. */
4607 build_nop (TInsn
*tinsn
, int size
)
4613 tinsn
->opcode
= xtensa_nop_n_opcode
;
4615 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4616 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4620 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4622 tinsn
->opcode
= xtensa_or_opcode
;
4623 set_expr_const (&tinsn
->tok
[0], 1);
4624 set_expr_const (&tinsn
->tok
[1], 1);
4625 set_expr_const (&tinsn
->tok
[2], 1);
4629 tinsn
->opcode
= xtensa_nop_opcode
;
4631 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4636 /* Assemble a NOP of the requested size in the buffer. User must have
4637 allocated "buf" with at least "size" bytes. */
4640 assemble_nop (int size
, char *buf
)
4642 static xtensa_insnbuf insnbuf
= NULL
;
4645 build_nop (&tinsn
, size
);
4648 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4650 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4651 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4652 (unsigned char *) buf
, 0);
4656 /* Return the number of bytes for the offset of the expanded loop
4657 instruction. This should be incorporated into the relaxation
4658 specification but is hard-coded here. This is used to auto-align
4659 the loop instruction. It is invalid to call this function if the
4660 configuration does not have loops or if the opcode is not a loop
4664 get_expanded_loop_offset (xtensa_opcode opcode
)
4666 /* This is the OFFSET of the loop instruction in the expanded loop.
4667 This MUST correspond directly to the specification of the loop
4668 expansion. It will be validated on fragment conversion. */
4669 assert (opcode
!= XTENSA_UNDEFINED
);
4670 if (opcode
== xtensa_loop_opcode
)
4672 if (opcode
== xtensa_loopnez_opcode
)
4674 if (opcode
== xtensa_loopgtz_opcode
)
4676 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4682 get_literal_pool_location (segT seg
)
4684 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4689 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4691 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4695 /* Set frag assembly state should be called when a new frag is
4696 opened and after a frag has been closed. */
4699 xtensa_set_frag_assembly_state (fragS
*fragP
)
4701 if (!density_supported
)
4702 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4704 /* This function is called from subsegs_finish, which is called
4705 after xtensa_end, so we can't use "use_transform" or
4706 "use_schedule" here. */
4707 if (!directive_state
[directive_transform
])
4708 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4709 if (directive_state
[directive_longcalls
])
4710 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4711 fragP
->tc_frag_data
.use_absolute_literals
=
4712 directive_state
[directive_absolute_literals
];
4713 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4718 relaxable_section (asection
*sec
)
4720 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4725 xtensa_find_unmarked_state_frags (void)
4729 /* Walk over each fragment of all of the current segments. For each
4730 unmarked fragment, mark it with the same info as the previous
4732 for (seclist
= &stdoutput
->sections
;
4733 seclist
&& *seclist
;
4734 seclist
= &(*seclist
)->next
)
4736 segT sec
= *seclist
;
4737 segment_info_type
*seginfo
;
4740 flags
= bfd_get_section_flags (stdoutput
, sec
);
4741 if (flags
& SEC_DEBUGGING
)
4743 if (!(flags
& SEC_ALLOC
))
4746 seginfo
= seg_info (sec
);
4747 if (seginfo
&& seginfo
->frchainP
)
4749 fragS
*last_fragP
= 0;
4750 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4751 fragP
= fragP
->fr_next
)
4753 if (fragP
->fr_fix
!= 0
4754 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4756 if (last_fragP
== 0)
4758 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4759 _("assembly state not set for first frag in section %s"),
4764 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4765 fragP
->tc_frag_data
.is_no_density
=
4766 last_fragP
->tc_frag_data
.is_no_density
;
4767 fragP
->tc_frag_data
.is_no_transform
=
4768 last_fragP
->tc_frag_data
.is_no_transform
;
4769 fragP
->tc_frag_data
.use_longcalls
=
4770 last_fragP
->tc_frag_data
.use_longcalls
;
4771 fragP
->tc_frag_data
.use_absolute_literals
=
4772 last_fragP
->tc_frag_data
.use_absolute_literals
;
4775 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4784 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4786 void *unused ATTRIBUTE_UNUSED
)
4788 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4789 segment_info_type
*seginfo
= seg_info (sec
);
4790 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4792 if (flags
& SEC_CODE
)
4794 xtensa_isa isa
= xtensa_default_isa
;
4795 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4796 while (frag
!= NULL
)
4798 if (frag
->tc_frag_data
.is_branch_target
)
4801 addressT branch_align
, frag_addr
;
4804 xtensa_insnbuf_from_chars
4805 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4806 fmt
= xtensa_format_decode (isa
, insnbuf
);
4807 op_size
= xtensa_format_length (isa
, fmt
);
4808 branch_align
= 1 << branch_align_power (sec
);
4809 frag_addr
= frag
->fr_address
% branch_align
;
4810 if (frag_addr
+ op_size
> branch_align
)
4811 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4812 _("unaligned branch target: %d bytes at 0x%lx"),
4813 op_size
, (long) frag
->fr_address
);
4815 frag
= frag
->fr_next
;
4817 xtensa_insnbuf_free (isa
, insnbuf
);
4823 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4825 void *unused ATTRIBUTE_UNUSED
)
4827 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4828 segment_info_type
*seginfo
= seg_info (sec
);
4829 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4830 xtensa_isa isa
= xtensa_default_isa
;
4832 if (flags
& SEC_CODE
)
4834 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4835 while (frag
!= NULL
)
4837 if (frag
->tc_frag_data
.is_first_loop_insn
)
4843 xtensa_insnbuf_from_chars
4844 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4845 fmt
= xtensa_format_decode (isa
, insnbuf
);
4846 op_size
= xtensa_format_length (isa
, fmt
);
4847 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4849 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4850 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4851 _("unaligned loop: %d bytes at 0x%lx"),
4852 op_size
, (long) frag
->fr_address
);
4854 frag
= frag
->fr_next
;
4856 xtensa_insnbuf_free (isa
, insnbuf
);
4862 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4864 xtensa_isa isa
= xtensa_default_isa
;
4865 static xtensa_insnbuf insnbuf
= NULL
;
4866 static xtensa_insnbuf slotbuf
= NULL
;
4869 bfd_boolean alt_reloc
;
4870 xtensa_opcode opcode
;
4871 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4873 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4875 as_fatal (_("unexpected fix"));
4879 insnbuf
= xtensa_insnbuf_alloc (isa
);
4880 slotbuf
= xtensa_insnbuf_alloc (isa
);
4883 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4884 fmt
= xtensa_format_decode (isa
, insnbuf
);
4885 if (fmt
== XTENSA_UNDEFINED
)
4886 as_fatal (_("undecodable fix"));
4887 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4888 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4889 if (opcode
== XTENSA_UNDEFINED
)
4890 as_fatal (_("undecodable fix"));
4892 /* CONST16 immediates are not PC-relative, despite the fact that we
4893 reuse the normal PC-relative operand relocations for the low part
4894 of a CONST16 operand. */
4895 if (opcode
== xtensa_const16_opcode
)
4898 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4899 get_relaxable_immed (opcode
), val
,
4900 fixP
->fx_file
, fixP
->fx_line
);
4902 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4903 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4909 /* External Functions and Other GAS Hooks. */
4912 xtensa_target_format (void)
4914 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4919 xtensa_file_arch_init (bfd
*abfd
)
4921 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4926 md_number_to_chars (char *buf
, valueT val
, int n
)
4928 if (target_big_endian
)
4929 number_to_chars_bigendian (buf
, val
, n
);
4931 number_to_chars_littleendian (buf
, val
, n
);
4935 /* This function is called once, at assembler startup time. It should
4936 set up all the tables, etc. that the MD part of the assembler will
4942 segT current_section
= now_seg
;
4943 int current_subsec
= now_subseg
;
4946 xtensa_default_isa
= xtensa_isa_init (0, 0);
4947 isa
= xtensa_default_isa
;
4951 /* Set up the .literal, .fini.literal and .init.literal sections. */
4952 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4953 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4954 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4955 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4956 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4958 subseg_set (current_section
, current_subsec
);
4960 xg_init_vinsn (&cur_vinsn
);
4962 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4963 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4964 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4965 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4966 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4967 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4968 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4969 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4970 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4971 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4972 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4973 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4974 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4975 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4976 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4977 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4978 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4979 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4980 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4981 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4982 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4983 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4984 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4985 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4986 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4987 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4988 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4989 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4990 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4992 init_op_placement_info_table ();
4994 /* Set up the assembly state. */
4995 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4996 xtensa_set_frag_assembly_state (frag_now
);
5000 /* TC_INIT_FIX_DATA hook */
5003 xtensa_init_fix_data (fixS
*x
)
5005 x
->tc_fix_data
.slot
= 0;
5006 x
->tc_fix_data
.X_add_symbol
= NULL
;
5007 x
->tc_fix_data
.X_add_number
= 0;
5011 /* tc_frob_label hook */
5014 xtensa_frob_label (symbolS
*sym
)
5018 if (cur_vinsn
.inside_bundle
)
5020 as_bad (_("labels are not valid inside bundles"));
5024 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5026 /* Since the label was already attached to a frag associated with the
5027 previous basic block, it now needs to be reset to the current frag. */
5028 symbol_set_frag (sym
, frag_now
);
5029 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5031 if (generating_literals
)
5032 xtensa_add_literal_sym (sym
);
5034 xtensa_add_insn_label (sym
);
5036 if (symbol_get_tc (sym
)->is_loop_target
)
5038 if ((get_last_insn_flags (now_seg
, now_subseg
)
5039 & FLAG_IS_BAD_LOOPEND
) != 0)
5040 as_bad (_("invalid last instruction for a zero-overhead loop"));
5042 xtensa_set_frag_assembly_state (frag_now
);
5043 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5044 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5046 xtensa_set_frag_assembly_state (frag_now
);
5047 xtensa_move_labels (frag_now
, 0, TRUE
);
5050 /* No target aligning in the absolute section. */
5051 if (now_seg
!= absolute_section
5052 && do_align_targets ()
5053 && !is_unaligned_label (sym
)
5054 && !generating_literals
)
5056 xtensa_set_frag_assembly_state (frag_now
);
5058 frag_var (rs_machine_dependent
,
5060 RELAX_DESIRE_ALIGN_IF_TARGET
,
5061 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5062 xtensa_set_frag_assembly_state (frag_now
);
5063 xtensa_move_labels (frag_now
, 0, TRUE
);
5066 /* We need to mark the following properties even if we aren't aligning. */
5068 /* If the label is already known to be a branch target, i.e., a
5069 forward branch, mark the frag accordingly. Backward branches
5070 are handled by xg_add_branch_and_loop_targets. */
5071 if (symbol_get_tc (sym
)->is_branch_target
)
5072 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5074 /* Loops only go forward, so they can be identified here. */
5075 if (symbol_get_tc (sym
)->is_loop_target
)
5076 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5078 dwarf2_emit_label (sym
);
5082 /* tc_unrecognized_line hook */
5085 xtensa_unrecognized_line (int ch
)
5090 if (cur_vinsn
.inside_bundle
== 0)
5092 /* PR8110: Cannot emit line number info inside a FLIX bundle
5093 when using --gstabs. Temporarily disable debug info. */
5094 generate_lineno_debug ();
5095 if (debug_type
== DEBUG_STABS
)
5097 xt_saved_debug_type
= debug_type
;
5098 debug_type
= DEBUG_NONE
;
5101 cur_vinsn
.inside_bundle
= 1;
5105 as_bad (_("extra opening brace"));
5111 if (cur_vinsn
.inside_bundle
)
5112 finish_vinsn (&cur_vinsn
);
5115 as_bad (_("extra closing brace"));
5120 as_bad (_("syntax error"));
5127 /* md_flush_pending_output hook */
5130 xtensa_flush_pending_output (void)
5132 if (cur_vinsn
.inside_bundle
)
5133 as_bad (_("missing closing brace"));
5135 /* If there is a non-zero instruction fragment, close it. */
5136 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5138 frag_wane (frag_now
);
5140 xtensa_set_frag_assembly_state (frag_now
);
5142 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5144 xtensa_clear_insn_labels ();
5148 /* We had an error while parsing an instruction. The string might look
5149 like this: "insn arg1, arg2 }". If so, we need to see the closing
5150 brace and reset some fields. Otherwise, the vinsn never gets closed
5151 and the num_slots field will grow past the end of the array of slots,
5152 and bad things happen. */
5155 error_reset_cur_vinsn (void)
5157 if (cur_vinsn
.inside_bundle
)
5159 if (*input_line_pointer
== '}'
5160 || *(input_line_pointer
- 1) == '}'
5161 || *(input_line_pointer
- 2) == '}')
5162 xg_clear_vinsn (&cur_vinsn
);
5168 md_assemble (char *str
)
5170 xtensa_isa isa
= xtensa_default_isa
;
5171 char *opname
, *file_name
;
5173 bfd_boolean has_underbar
= FALSE
;
5174 char *arg_strings
[MAX_INSN_ARGS
];
5176 TInsn orig_insn
; /* Original instruction from the input. */
5178 tinsn_init (&orig_insn
);
5180 /* Split off the opcode. */
5181 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5182 opname
= xmalloc (opnamelen
+ 1);
5183 memcpy (opname
, str
, opnamelen
);
5184 opname
[opnamelen
] = '\0';
5186 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5189 as_bad (_("syntax error"));
5193 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5196 /* Check for an underbar prefix. */
5199 has_underbar
= TRUE
;
5203 orig_insn
.insn_type
= ITYPE_INSN
;
5205 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5207 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5208 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5210 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5211 if (fmt
== XTENSA_UNDEFINED
)
5213 as_bad (_("unknown opcode or format name '%s'"), opname
);
5214 error_reset_cur_vinsn ();
5217 if (!cur_vinsn
.inside_bundle
)
5219 as_bad (_("format names only valid inside bundles"));
5220 error_reset_cur_vinsn ();
5223 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5224 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5226 cur_vinsn
.format
= fmt
;
5227 free (has_underbar
? opname
- 1 : opname
);
5228 error_reset_cur_vinsn ();
5232 /* Parse the arguments. */
5233 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5235 as_bad (_("syntax error"));
5236 error_reset_cur_vinsn ();
5240 /* Free the opcode and argument strings, now that they've been parsed. */
5241 free (has_underbar
? opname
- 1 : opname
);
5243 while (num_args
-- > 0)
5244 free (arg_strings
[num_args
]);
5246 /* Get expressions for invisible operands. */
5247 if (get_invisible_operands (&orig_insn
))
5249 error_reset_cur_vinsn ();
5253 /* Check for the right number and type of arguments. */
5254 if (tinsn_check_arguments (&orig_insn
))
5256 error_reset_cur_vinsn ();
5260 /* A FLIX bundle may be spread across multiple input lines. We want to
5261 report the first such line in the debug information. Record the line
5262 number for each TInsn (assume the file name doesn't change), so the
5263 first line can be found later. */
5264 as_where (&file_name
, &orig_insn
.linenum
);
5266 xg_add_branch_and_loop_targets (&orig_insn
);
5268 /* Check that immediate value for ENTRY is >= 16. */
5269 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5271 expressionS
*exp
= &orig_insn
.tok
[2];
5272 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5273 as_warn (_("entry instruction with stack decrement < 16"));
5277 assemble_tokens (opcode, tok, ntok);
5278 expand the tokens from the orig_insn into the
5279 stack of instructions that will not expand
5280 unless required at relaxation time. */
5282 if (!cur_vinsn
.inside_bundle
)
5283 emit_single_op (&orig_insn
);
5284 else /* We are inside a bundle. */
5286 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5287 cur_vinsn
.num_slots
++;
5288 if (*input_line_pointer
== '}'
5289 || *(input_line_pointer
- 1) == '}'
5290 || *(input_line_pointer
- 2) == '}')
5291 finish_vinsn (&cur_vinsn
);
5294 /* We've just emitted a new instruction so clear the list of labels. */
5295 xtensa_clear_insn_labels ();
5299 /* HANDLE_ALIGN hook */
5301 /* For a .align directive, we mark the previous block with the alignment
5302 information. This will be placed in the object file in the
5303 property section corresponding to this section. */
5306 xtensa_handle_align (fragS
*fragP
)
5309 && ! fragP
->tc_frag_data
.is_literal
5310 && (fragP
->fr_type
== rs_align
5311 || fragP
->fr_type
== rs_align_code
)
5312 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5313 && fragP
->fr_offset
> 0
5314 && now_seg
!= bss_section
)
5316 fragP
->tc_frag_data
.is_align
= TRUE
;
5317 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5320 if (fragP
->fr_type
== rs_align_test
)
5323 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5325 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5326 _("unaligned entry instruction"));
5331 /* TC_FRAG_INIT hook */
5334 xtensa_frag_init (fragS
*frag
)
5336 xtensa_set_frag_assembly_state (frag
);
5341 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5347 /* Round up a section size to the appropriate boundary. */
5350 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5352 return size
; /* Byte alignment is fine. */
5357 md_pcrel_from (fixS
*fixP
)
5360 static xtensa_insnbuf insnbuf
= NULL
;
5361 static xtensa_insnbuf slotbuf
= NULL
;
5364 xtensa_opcode opcode
;
5367 xtensa_isa isa
= xtensa_default_isa
;
5368 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5369 bfd_boolean alt_reloc
;
5371 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5376 insnbuf
= xtensa_insnbuf_alloc (isa
);
5377 slotbuf
= xtensa_insnbuf_alloc (isa
);
5380 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5381 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5382 fmt
= xtensa_format_decode (isa
, insnbuf
);
5384 if (fmt
== XTENSA_UNDEFINED
)
5385 as_fatal (_("bad instruction format"));
5387 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5388 as_fatal (_("invalid relocation"));
5390 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5391 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5393 /* Check for "alternate" relocations (operand not specified). None
5394 of the current uses for these are really PC-relative. */
5395 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5397 if (opcode
!= xtensa_l32r_opcode
5398 && opcode
!= xtensa_const16_opcode
)
5399 as_fatal (_("invalid relocation for '%s' instruction"),
5400 xtensa_opcode_name (isa
, opcode
));
5404 opnum
= get_relaxable_immed (opcode
);
5406 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5407 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5409 as_bad_where (fixP
->fx_file
,
5411 _("invalid relocation for operand %d of '%s'"),
5412 opnum
, xtensa_opcode_name (isa
, opcode
));
5415 return 0 - opnd_value
;
5419 /* TC_FORCE_RELOCATION hook */
5422 xtensa_force_relocation (fixS
*fix
)
5424 switch (fix
->fx_r_type
)
5426 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5427 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5428 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5429 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5430 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5431 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5440 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5441 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5447 if (linkrelax
&& fix
->fx_addsy
5448 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5451 return generic_force_reloc (fix
);
5455 /* TC_VALIDATE_FIX_SUB hook */
5458 xtensa_validate_fix_sub (fixS
*fix
)
5460 segT add_symbol_segment
, sub_symbol_segment
;
5462 /* The difference of two symbols should be resolved by the assembler when
5463 linkrelax is not set. If the linker may relax the section containing
5464 the symbols, then an Xtensa DIFF relocation must be generated so that
5465 the linker knows to adjust the difference value. */
5466 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5469 /* Make sure both symbols are in the same segment, and that segment is
5470 "normal" and relaxable. If the segment is not "normal", then the
5471 fix is not valid. If the segment is not "relaxable", then the fix
5472 should have been handled earlier. */
5473 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5474 if (! SEG_NORMAL (add_symbol_segment
) ||
5475 ! relaxable_section (add_symbol_segment
))
5477 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5478 return (sub_symbol_segment
== add_symbol_segment
);
5482 /* NO_PSEUDO_DOT hook */
5484 /* This function has nothing to do with pseudo dots, but this is the
5485 nearest macro to where the check needs to take place. FIXME: This
5489 xtensa_check_inside_bundle (void)
5491 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5492 as_bad (_("directives are not valid inside bundles"));
5494 /* This function must always return FALSE because it is called via a
5495 macro that has nothing to do with bundling. */
5500 /* md_elf_section_change_hook */
5503 xtensa_elf_section_change_hook (void)
5505 /* Set up the assembly state. */
5506 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5507 xtensa_set_frag_assembly_state (frag_now
);
5511 /* tc_fix_adjustable hook */
5514 xtensa_fix_adjustable (fixS
*fixP
)
5516 /* An offset is not allowed in combination with the difference of two
5517 symbols, but that cannot be easily detected after a local symbol
5518 has been adjusted to a (section+offset) form. Return 0 so that such
5519 an fix will not be adjusted. */
5520 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5521 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5524 /* We need the symbol name for the VTABLE entries. */
5525 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5526 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5534 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5536 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5539 /* Subtracted symbols are only allowed for a few relocation types, and
5540 unless linkrelax is enabled, they should not make it to this point. */
5541 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5542 || fixP
->fx_r_type
== BFD_RELOC_16
5543 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5546 switch (fixP
->fx_r_type
)
5553 switch (fixP
->fx_r_type
)
5556 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5559 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5562 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5568 /* An offset is only allowed when it results from adjusting a
5569 local symbol into a section-relative offset. If the offset
5570 came from the original expression, tc_fix_adjustable will have
5571 prevented the fix from being converted to a section-relative
5572 form so that we can flag the error here. */
5573 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5575 _("cannot represent subtraction with an offset"));
5577 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5578 - S_GET_VALUE (fixP
->fx_subsy
));
5580 /* The difference value gets written out, and the DIFF reloc
5581 identifies the address of the subtracted symbol (i.e., the one
5582 with the lowest address). */
5584 fixP
->fx_offset
-= val
;
5585 fixP
->fx_subsy
= NULL
;
5587 else if (! fixP
->fx_addsy
)
5594 case BFD_RELOC_XTENSA_PLT
:
5595 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5596 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5599 case BFD_RELOC_XTENSA_SLOT0_OP
:
5600 case BFD_RELOC_XTENSA_SLOT1_OP
:
5601 case BFD_RELOC_XTENSA_SLOT2_OP
:
5602 case BFD_RELOC_XTENSA_SLOT3_OP
:
5603 case BFD_RELOC_XTENSA_SLOT4_OP
:
5604 case BFD_RELOC_XTENSA_SLOT5_OP
:
5605 case BFD_RELOC_XTENSA_SLOT6_OP
:
5606 case BFD_RELOC_XTENSA_SLOT7_OP
:
5607 case BFD_RELOC_XTENSA_SLOT8_OP
:
5608 case BFD_RELOC_XTENSA_SLOT9_OP
:
5609 case BFD_RELOC_XTENSA_SLOT10_OP
:
5610 case BFD_RELOC_XTENSA_SLOT11_OP
:
5611 case BFD_RELOC_XTENSA_SLOT12_OP
:
5612 case BFD_RELOC_XTENSA_SLOT13_OP
:
5613 case BFD_RELOC_XTENSA_SLOT14_OP
:
5616 /* Write the tentative value of a PC-relative relocation to a
5617 local symbol into the instruction. The value will be ignored
5618 by the linker, and it makes the object file disassembly
5619 readable when all branch targets are encoded in relocations. */
5621 assert (fixP
->fx_addsy
);
5622 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5623 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5625 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5626 - md_pcrel_from (fixP
));
5627 (void) xg_apply_fix_value (fixP
, val
);
5630 else if (! fixP
->fx_addsy
)
5633 if (xg_apply_fix_value (fixP
, val
))
5638 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5639 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5648 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5649 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5651 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5652 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5653 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5654 /* These all need to be resolved at link-time. Do nothing now. */
5657 case BFD_RELOC_VTABLE_INHERIT
:
5658 case BFD_RELOC_VTABLE_ENTRY
:
5663 as_bad (_("unhandled local relocation fix %s"),
5664 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5670 md_atof (int type
, char *litP
, int *sizeP
)
5673 LITTLENUM_TYPE words
[4];
5689 return "bad call to md_atof";
5692 t
= atof_ieee (input_line_pointer
, type
, words
);
5694 input_line_pointer
= t
;
5698 for (i
= prec
- 1; i
>= 0; i
--)
5701 if (target_big_endian
)
5702 idx
= (prec
- 1 - i
);
5704 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5713 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5715 return total_frag_text_expansion (fragP
);
5719 /* Translate internal representation of relocation info to BFD target
5723 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5727 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5728 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5729 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5730 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5732 /* Make sure none of our internal relocations make it this far.
5733 They'd better have been fully resolved by this point. */
5734 assert ((int) fixp
->fx_r_type
> 0);
5736 reloc
->addend
= fixp
->fx_offset
;
5738 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5739 if (reloc
->howto
== NULL
)
5741 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5742 _("cannot represent `%s' relocation in object file"),
5743 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5744 free (reloc
->sym_ptr_ptr
);
5749 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5750 as_fatal (_("internal error? cannot generate `%s' relocation"),
5751 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5757 /* Checks for resource conflicts between instructions. */
5759 /* The func unit stuff could be implemented as bit-vectors rather
5760 than the iterative approach here. If it ends up being too
5761 slow, we will switch it. */
5764 new_resource_table (void *data
,
5767 unit_num_copies_func uncf
,
5768 opcode_num_units_func onuf
,
5769 opcode_funcUnit_use_unit_func ouuf
,
5770 opcode_funcUnit_use_stage_func ousf
)
5773 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5775 rt
->cycles
= cycles
;
5776 rt
->allocated_cycles
= cycles
;
5778 rt
->unit_num_copies
= uncf
;
5779 rt
->opcode_num_units
= onuf
;
5780 rt
->opcode_unit_use
= ouuf
;
5781 rt
->opcode_unit_stage
= ousf
;
5783 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5784 for (i
= 0; i
< cycles
; i
++)
5785 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5792 clear_resource_table (resource_table
*rt
)
5795 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5796 for (j
= 0; j
< rt
->num_units
; j
++)
5797 rt
->units
[i
][j
] = 0;
5801 /* We never shrink it, just fake it into thinking so. */
5804 resize_resource_table (resource_table
*rt
, int cycles
)
5808 rt
->cycles
= cycles
;
5809 if (cycles
<= rt
->allocated_cycles
)
5812 old_cycles
= rt
->allocated_cycles
;
5813 rt
->allocated_cycles
= cycles
;
5815 rt
->units
= xrealloc (rt
->units
,
5816 rt
->allocated_cycles
* sizeof (unsigned char *));
5817 for (i
= 0; i
< old_cycles
; i
++)
5818 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5819 rt
->num_units
* sizeof (unsigned char));
5820 for (i
= old_cycles
; i
< cycles
; i
++)
5821 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5826 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5829 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5831 for (i
= 0; i
< uses
; i
++)
5833 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5834 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5835 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5836 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5837 if (copies_in_use
>= copies
)
5845 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5848 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5850 for (i
= 0; i
< uses
; i
++)
5852 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5853 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5854 /* Note that this allows resources to be oversubscribed. That's
5855 essential to the way the optional scheduler works.
5856 resources_available reports when a resource is over-subscribed,
5857 so it's easy to tell. */
5858 rt
->units
[stage
+ cycle
][unit
]++;
5864 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5867 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5869 for (i
= 0; i
< uses
; i
++)
5871 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5872 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5873 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5874 rt
->units
[stage
+ cycle
][unit
]--;
5879 /* Wrapper functions make parameterized resource reservation
5883 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5885 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5891 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5893 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5898 /* Note that this function does not check issue constraints, but
5899 solely whether the hardware is available to execute the given
5900 instructions together. It also doesn't check if the tinsns
5901 write the same state, or access the same tieports. That is
5902 checked by check_t1_t2_reads_and_writes. */
5905 resources_conflict (vliw_insn
*vinsn
)
5908 static resource_table
*rt
= NULL
;
5910 /* This is the most common case by far. Optimize it. */
5911 if (vinsn
->num_slots
== 1)
5916 xtensa_isa isa
= xtensa_default_isa
;
5917 rt
= new_resource_table
5918 (isa
, xtensa_isa_num_pipe_stages (isa
),
5919 xtensa_isa_num_funcUnits (isa
),
5920 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5921 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5922 opcode_funcUnit_use_unit
,
5923 opcode_funcUnit_use_stage
);
5926 clear_resource_table (rt
);
5928 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5930 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5932 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5939 /* finish_vinsn, emit_single_op and helper functions. */
5941 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5942 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5943 static void xg_assemble_vliw_tokens (vliw_insn
*);
5946 /* We have reached the end of a bundle; emit into the frag. */
5949 finish_vinsn (vliw_insn
*vinsn
)
5956 if (find_vinsn_conflicts (vinsn
))
5958 xg_clear_vinsn (vinsn
);
5962 /* First, find a format that works. */
5963 if (vinsn
->format
== XTENSA_UNDEFINED
)
5964 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5966 if (vinsn
->format
== XTENSA_UNDEFINED
)
5968 as_where (&file_name
, &line
);
5969 as_bad_where (file_name
, line
,
5970 _("couldn't find a valid instruction format"));
5971 fprintf (stderr
, _(" ops were: "));
5972 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5973 fprintf (stderr
, _(" %s;"),
5974 xtensa_opcode_name (xtensa_default_isa
,
5975 vinsn
->slots
[i
].opcode
));
5976 fprintf (stderr
, _("\n"));
5977 xg_clear_vinsn (vinsn
);
5981 if (vinsn
->num_slots
5982 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5984 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5985 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5986 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5988 xg_clear_vinsn (vinsn
);
5992 if (resources_conflict (vinsn
))
5994 as_where (&file_name
, &line
);
5995 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5996 fprintf (stderr
, " ops were: ");
5997 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5998 fprintf (stderr
, " %s;",
5999 xtensa_opcode_name (xtensa_default_isa
,
6000 vinsn
->slots
[i
].opcode
));
6001 fprintf (stderr
, "\n");
6002 xg_clear_vinsn (vinsn
);
6006 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6008 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6010 symbolS
*lit_sym
= NULL
;
6012 bfd_boolean e
= FALSE
;
6013 bfd_boolean saved_density
= density_supported
;
6015 /* We don't want to narrow ops inside multi-slot bundles. */
6016 if (vinsn
->num_slots
> 1)
6017 density_supported
= FALSE
;
6019 istack_init (&slotstack
);
6020 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6022 vinsn
->slots
[i
].opcode
=
6023 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6025 vinsn
->slots
[i
].ntok
= 0;
6028 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6034 density_supported
= saved_density
;
6038 xg_clear_vinsn (vinsn
);
6042 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6044 TInsn
*insn
= &slotstack
.insn
[j
];
6045 if (insn
->insn_type
== ITYPE_LITERAL
)
6047 assert (lit_sym
== NULL
);
6048 lit_sym
= xg_assemble_literal (insn
);
6052 assert (insn
->insn_type
== ITYPE_INSN
);
6054 xg_resolve_literals (insn
, lit_sym
);
6055 if (j
!= slotstack
.ninsn
- 1)
6056 emit_single_op (insn
);
6060 if (vinsn
->num_slots
> 1)
6062 if (opcode_fits_format_slot
6063 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6066 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6070 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6071 if (vinsn
->format
== XTENSA_UNDEFINED
)
6072 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6074 vinsn
->slots
[i
].opcode
6075 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6078 vinsn
->slots
[i
].ntok
= 0;
6083 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6084 vinsn
->format
= XTENSA_UNDEFINED
;
6089 /* Now check resource conflicts on the modified bundle. */
6090 if (resources_conflict (vinsn
))
6092 as_where (&file_name
, &line
);
6093 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6094 fprintf (stderr
, " ops were: ");
6095 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6096 fprintf (stderr
, " %s;",
6097 xtensa_opcode_name (xtensa_default_isa
,
6098 vinsn
->slots
[i
].opcode
));
6099 fprintf (stderr
, "\n");
6100 xg_clear_vinsn (vinsn
);
6104 /* First, find a format that works. */
6105 if (vinsn
->format
== XTENSA_UNDEFINED
)
6106 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6108 xg_assemble_vliw_tokens (vinsn
);
6110 xg_clear_vinsn (vinsn
);
6114 /* Given an vliw instruction, what conflicts are there in register
6115 usage and in writes to states and queues?
6117 This function does two things:
6118 1. Reports an error when a vinsn contains illegal combinations
6119 of writes to registers states or queues.
6120 2. Marks individual tinsns as not relaxable if the combination
6121 contains antidependencies.
6123 Job 2 handles things like swap semantics in instructions that need
6124 to be relaxed. For example,
6128 normally would be relaxed to
6133 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6135 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6137 then we can't relax it into
6140 { add a0, a1, a0 ; add a2, a0, a4 ; }
6142 because the value of a0 is trashed before the second add can read it. */
6144 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6147 find_vinsn_conflicts (vliw_insn
*vinsn
)
6151 xtensa_isa isa
= xtensa_default_isa
;
6153 assert (!past_xtensa_end
);
6155 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6157 TInsn
*op1
= &vinsn
->slots
[i
];
6158 if (op1
->is_specific_opcode
)
6159 op1
->keep_wide
= TRUE
;
6161 op1
->keep_wide
= FALSE
;
6164 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6166 TInsn
*op1
= &vinsn
->slots
[i
];
6168 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6171 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6175 TInsn
*op2
= &vinsn
->slots
[j
];
6176 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6177 switch (conflict_type
)
6180 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6181 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6182 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6185 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6186 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6187 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6190 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6191 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6192 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6195 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6196 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6197 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6200 /* Everything is OK. */
6203 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6204 || conflict_type
== 'a');
6211 as_bad (_("multiple branches or jumps in the same bundle"));
6219 /* Check how the state used by t1 and t2 relate.
6222 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6223 case B: no relationship between what is read and written (both could
6224 read the same reg though)
6225 case C: t1 writes a register t2 writes (a register conflict within a
6227 case D: t1 writes a state that t2 also writes
6228 case E: t1 writes a tie queue that t2 also writes
6229 case F: two volatile queue accesses
6233 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6235 xtensa_isa isa
= xtensa_default_isa
;
6236 xtensa_regfile t1_regfile
, t2_regfile
;
6238 int t1_base_reg
, t1_last_reg
;
6239 int t2_base_reg
, t2_last_reg
;
6240 char t1_inout
, t2_inout
;
6242 char conflict
= 'b';
6247 bfd_boolean t1_volatile
= FALSE
;
6248 bfd_boolean t2_volatile
= FALSE
;
6250 /* Check registers. */
6251 for (j
= 0; j
< t2
->ntok
; j
++)
6253 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6256 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6257 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6258 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6260 for (i
= 0; i
< t1
->ntok
; i
++)
6262 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6265 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6267 if (t1_regfile
!= t2_regfile
)
6270 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6271 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6273 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6274 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6276 if (t1_inout
== 'm' || t1_inout
== 'o'
6277 || t2_inout
== 'm' || t2_inout
== 'o')
6284 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6285 t1_last_reg
= (t1_base_reg
6286 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6288 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6290 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6292 if (t1_reg
!= t2_reg
)
6295 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6301 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6307 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6315 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6316 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6317 for (j
= 0; j
< t2_states
; j
++)
6319 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6320 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6321 for (i
= 0; i
< t1_states
; i
++)
6323 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6324 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6328 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6334 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6340 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6345 /* Check tieports. */
6346 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6347 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6348 for (j
= 0; j
< t2_interfaces
; j
++)
6350 xtensa_interface t2_int
6351 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6352 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6354 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6355 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6358 for (i
= 0; i
< t1_interfaces
; i
++)
6360 xtensa_interface t1_int
6361 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6362 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6364 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6365 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6368 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6371 if (t1_int
!= t2_int
)
6374 if (t2_inout
== 'i' && t1_inout
== 'o')
6380 if (t1_inout
== 'i' && t2_inout
== 'o')
6386 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6395 static xtensa_format
6396 xg_find_narrowest_format (vliw_insn
*vinsn
)
6398 /* Right now we assume that the ops within the vinsn are properly
6399 ordered for the slots that the programmer wanted them in. In
6400 other words, we don't rearrange the ops in hopes of finding a
6401 better format. The scheduler handles that. */
6403 xtensa_isa isa
= xtensa_default_isa
;
6404 xtensa_format format
;
6405 vliw_insn v_copy
= *vinsn
;
6406 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6408 if (vinsn
->num_slots
== 1)
6409 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6411 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6414 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6418 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6420 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6422 v_copy
.slots
[slot
].opcode
=
6423 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6424 v_copy
.slots
[slot
].ntok
= 0;
6427 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6430 else if (v_copy
.num_slots
> 1)
6433 /* Try the widened version. */
6434 if (!v_copy
.slots
[slot
].keep_wide
6435 && !v_copy
.slots
[slot
].is_specific_opcode
6436 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6438 && opcode_fits_format_slot (widened
.opcode
,
6441 v_copy
.slots
[slot
] = widened
;
6446 if (fit
== v_copy
.num_slots
)
6449 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6450 vinsn
->format
= format
;
6456 if (format
== xtensa_isa_num_formats (isa
))
6457 return XTENSA_UNDEFINED
;
6463 /* Return the additional space needed in a frag
6464 for possible relaxations of any ops in a VLIW insn.
6465 Also fill out the relaxations that might be required of
6466 each tinsn in the vinsn. */
6469 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6471 bfd_boolean finish_frag
= FALSE
;
6472 int extra_space
= 0;
6475 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6477 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6478 if (!tinsn_has_symbolic_operands (tinsn
))
6480 /* A narrow instruction could be widened later to help
6481 alignment issues. */
6482 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6483 && !tinsn
->is_specific_opcode
6484 && vinsn
->num_slots
== 1)
6486 /* Difference in bytes between narrow and wide insns... */
6488 tinsn
->subtype
= RELAX_NARROW
;
6493 if (workaround_b_j_loop_end
6494 && tinsn
->opcode
== xtensa_jx_opcode
6495 && use_transform ())
6497 /* Add 2 of these. */
6498 extra_space
+= 3; /* for the nop size */
6499 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6502 /* Need to assemble it with space for the relocation. */
6503 if (xg_is_relaxable_insn (tinsn
, 0)
6504 && !tinsn
->is_specific_opcode
)
6506 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6507 int max_literal_size
=
6508 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6510 tinsn
->literal_space
= max_literal_size
;
6512 tinsn
->subtype
= RELAX_IMMED
;
6513 extra_space
+= max_size
;
6517 /* A fix record will be added for this instruction prior
6518 to relaxation, so make it end the frag. */
6523 *pfinish_frag
= finish_frag
;
6529 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6531 xtensa_isa isa
= xtensa_default_isa
;
6532 int slot
, chosen_slot
;
6534 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6535 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6536 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6538 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6539 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6541 if (slot
== chosen_slot
)
6542 vinsn
->slots
[slot
] = *tinsn
;
6545 vinsn
->slots
[slot
].opcode
=
6546 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6547 vinsn
->slots
[slot
].ntok
= 0;
6548 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6555 emit_single_op (TInsn
*orig_insn
)
6558 IStack istack
; /* put instructions into here */
6559 symbolS
*lit_sym
= NULL
;
6560 symbolS
*label_sym
= NULL
;
6562 istack_init (&istack
);
6564 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6565 Because the scheduling and bundling characteristics of movi and
6566 l32r or const16 are so different, we can do much better if we relax
6567 it prior to scheduling and bundling, rather than after. */
6568 if ((orig_insn
->opcode
== xtensa_movi_opcode
6569 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6570 && !cur_vinsn
.inside_bundle
6571 && (orig_insn
->tok
[1].X_op
== O_symbol
6572 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6573 && !orig_insn
->is_specific_opcode
&& use_transform ())
6574 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6576 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6579 for (i
= 0; i
< istack
.ninsn
; i
++)
6581 TInsn
*insn
= &istack
.insn
[i
];
6582 switch (insn
->insn_type
)
6585 assert (lit_sym
== NULL
);
6586 lit_sym
= xg_assemble_literal (insn
);
6590 static int relaxed_sym_idx
= 0;
6591 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6592 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6594 assert (label_sym
== NULL
);
6595 label_sym
= symbol_find_or_make (label
);
6604 xg_resolve_literals (insn
, lit_sym
);
6606 xg_resolve_labels (insn
, label_sym
);
6608 bundle_tinsn (insn
, &v
);
6623 total_frag_text_expansion (fragS
*fragP
)
6626 int total_expansion
= 0;
6628 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6629 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6631 return total_expansion
;
6635 /* Emit a vliw instruction to the current fragment. */
6638 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6640 bfd_boolean finish_frag
;
6641 bfd_boolean is_jump
= FALSE
;
6642 bfd_boolean is_branch
= FALSE
;
6643 xtensa_isa isa
= xtensa_default_isa
;
6649 unsigned current_line
, best_linenum
;
6652 best_linenum
= UINT_MAX
;
6654 if (generating_literals
)
6656 static int reported
= 0;
6658 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6659 _("cannot assemble into a literal fragment"));
6666 if (frag_now_fix () != 0
6667 && (! frag_now
->tc_frag_data
.is_insn
6668 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6669 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6670 || (directive_state
[directive_longcalls
]
6671 != frag_now
->tc_frag_data
.use_longcalls
)
6672 || (directive_state
[directive_absolute_literals
]
6673 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6675 frag_wane (frag_now
);
6677 xtensa_set_frag_assembly_state (frag_now
);
6680 if (workaround_a0_b_retw
6681 && vinsn
->num_slots
== 1
6682 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6683 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6684 && use_transform ())
6686 has_a0_b_retw
= TRUE
;
6688 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6689 After the first assembly pass we will check all of them and
6690 add a nop if needed. */
6691 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6692 frag_var (rs_machine_dependent
, 4, 4,
6693 RELAX_ADD_NOP_IF_A0_B_RETW
,
6694 frag_now
->fr_symbol
,
6695 frag_now
->fr_offset
,
6697 xtensa_set_frag_assembly_state (frag_now
);
6698 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6699 frag_var (rs_machine_dependent
, 4, 4,
6700 RELAX_ADD_NOP_IF_A0_B_RETW
,
6701 frag_now
->fr_symbol
,
6702 frag_now
->fr_offset
,
6704 xtensa_set_frag_assembly_state (frag_now
);
6707 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6709 /* See if the instruction implies an aligned section. */
6710 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6711 record_alignment (now_seg
, 2);
6713 /* Also determine the best line number for debug info. */
6714 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6715 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6718 /* Special cases for instructions that force an alignment... */
6719 /* None of these opcodes are bundle-able. */
6720 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6724 /* Remember the symbol that marks the end of the loop in the frag
6725 that marks the start of the loop. This way we can easily find
6726 the end of the loop at the beginning, without adding special code
6727 to mark the loop instructions themselves. */
6728 symbolS
*target_sym
= NULL
;
6729 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6730 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6732 xtensa_set_frag_assembly_state (frag_now
);
6733 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6735 max_fill
= get_text_align_max_fill_size
6736 (get_text_align_power (xtensa_fetch_width
),
6737 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6739 if (use_transform ())
6740 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6741 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6743 frag_var (rs_machine_dependent
, 0, 0,
6744 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6745 xtensa_set_frag_assembly_state (frag_now
);
6747 xtensa_move_labels (frag_now
, 0, FALSE
);
6750 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6751 && !vinsn
->slots
[0].is_specific_opcode
)
6753 xtensa_mark_literal_pool_location ();
6754 xtensa_move_labels (frag_now
, 0, TRUE
);
6755 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6758 if (vinsn
->num_slots
== 1)
6760 if (workaround_a0_b_retw
&& use_transform ())
6761 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6762 is_register_writer (&vinsn
->slots
[0], "a", 0));
6764 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6765 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6768 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6770 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6772 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6774 /* vinsn_to_insnbuf will produce the error. */
6775 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6777 f
= frag_more (insn_size
+ extra_space
);
6778 xtensa_set_frag_assembly_state (frag_now
);
6779 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6782 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6783 if (vinsn
->format
== XTENSA_UNDEFINED
)
6786 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6788 /* Temporarily set the logical line number to the one we want to appear
6789 in the debug information. */
6790 as_where (¤t_file
, ¤t_line
);
6791 new_logical_line (current_file
, best_linenum
);
6792 dwarf2_emit_insn (insn_size
+ extra_space
);
6793 new_logical_line (current_file
, current_line
);
6795 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6797 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6798 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6799 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6800 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6801 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6802 if (tinsn
->literal_space
!= 0)
6803 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6805 if (tinsn
->subtype
== RELAX_NARROW
)
6806 assert (vinsn
->num_slots
== 1);
6807 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6809 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6812 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6813 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6817 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6818 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6822 frag_variant (rs_machine_dependent
,
6823 extra_space
, extra_space
, RELAX_SLOTS
,
6824 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6825 xtensa_set_frag_assembly_state (frag_now
);
6828 /* Special cases for loops:
6829 close_loop_end should be inserted AFTER short_loop.
6830 Make sure that CLOSE loops are processed BEFORE short_loops
6831 when converting them. */
6833 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6834 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6835 && !vinsn
->slots
[0].is_specific_opcode
)
6837 if (workaround_short_loop
&& use_transform ())
6839 maybe_has_short_loop
= TRUE
;
6840 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6841 frag_var (rs_machine_dependent
, 4, 4,
6842 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6843 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6844 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6845 frag_var (rs_machine_dependent
, 4, 4,
6846 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6847 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6850 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6851 loop at least 12 bytes away from another loop's end. */
6852 if (workaround_close_loop_end
&& use_transform ())
6854 maybe_has_close_loop_end
= TRUE
;
6855 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6856 frag_var (rs_machine_dependent
, 12, 12,
6857 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6858 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6862 if (use_transform ())
6866 assert (finish_frag
);
6867 frag_var (rs_machine_dependent
,
6868 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6870 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6871 xtensa_set_frag_assembly_state (frag_now
);
6873 else if (is_branch
&& do_align_targets ())
6875 assert (finish_frag
);
6876 frag_var (rs_machine_dependent
,
6877 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6878 RELAX_MAYBE_UNREACHABLE
,
6879 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6880 xtensa_set_frag_assembly_state (frag_now
);
6881 frag_var (rs_machine_dependent
,
6883 RELAX_MAYBE_DESIRE_ALIGN
,
6884 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6885 xtensa_set_frag_assembly_state (frag_now
);
6889 /* Now, if the original opcode was a call... */
6890 if (do_align_targets ()
6891 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6893 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6894 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6895 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6896 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6897 xtensa_set_frag_assembly_state (frag_now
);
6900 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6902 frag_wane (frag_now
);
6904 xtensa_set_frag_assembly_state (frag_now
);
6909 /* xtensa_end and helper functions. */
6911 static void xtensa_cleanup_align_frags (void);
6912 static void xtensa_fix_target_frags (void);
6913 static void xtensa_mark_narrow_branches (void);
6914 static void xtensa_mark_zcl_first_insns (void);
6915 static void xtensa_fix_a0_b_retw_frags (void);
6916 static void xtensa_fix_b_j_loop_end_frags (void);
6917 static void xtensa_fix_close_loop_end_frags (void);
6918 static void xtensa_fix_short_loop_frags (void);
6919 static void xtensa_sanity_check (void);
6924 directive_balance ();
6925 xtensa_flush_pending_output ();
6927 past_xtensa_end
= TRUE
;
6929 xtensa_move_literals ();
6931 xtensa_reorder_segments ();
6932 xtensa_cleanup_align_frags ();
6933 xtensa_fix_target_frags ();
6934 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6935 xtensa_fix_a0_b_retw_frags ();
6936 if (workaround_b_j_loop_end
)
6937 xtensa_fix_b_j_loop_end_frags ();
6939 /* "close_loop_end" should be processed BEFORE "short_loop". */
6940 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6941 xtensa_fix_close_loop_end_frags ();
6943 if (workaround_short_loop
&& maybe_has_short_loop
)
6944 xtensa_fix_short_loop_frags ();
6946 xtensa_mark_narrow_branches ();
6947 xtensa_mark_zcl_first_insns ();
6949 xtensa_sanity_check ();
6954 xtensa_cleanup_align_frags (void)
6959 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6960 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6963 /* Walk over all of the fragments in a subsection. */
6964 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6966 if ((fragP
->fr_type
== rs_align
6967 || fragP
->fr_type
== rs_align_code
6968 || (fragP
->fr_type
== rs_machine_dependent
6969 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6970 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6971 && fragP
->fr_fix
== 0)
6973 fragS
*next
= fragP
->fr_next
;
6976 && next
->fr_fix
== 0
6977 && next
->fr_type
== rs_machine_dependent
6978 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6981 next
= next
->fr_next
;
6984 /* If we don't widen branch targets, then they
6985 will be easier to align. */
6986 if (fragP
->tc_frag_data
.is_branch_target
6987 && fragP
->fr_opcode
== fragP
->fr_literal
6988 && fragP
->fr_type
== rs_machine_dependent
6989 && fragP
->fr_subtype
== RELAX_SLOTS
6990 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6992 if (fragP
->fr_type
== rs_machine_dependent
6993 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6994 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7000 /* Re-process all of the fragments looking to convert all of the
7001 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7002 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7003 Otherwise, convert to a .fill 0. */
7006 xtensa_fix_target_frags (void)
7011 /* When this routine is called, all of the subsections are still intact
7012 so we walk over subsections instead of sections. */
7013 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7014 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7018 /* Walk over all of the fragments in a subsection. */
7019 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7021 if (fragP
->fr_type
== rs_machine_dependent
7022 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7024 if (next_frag_is_branch_target (fragP
))
7025 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7034 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7037 xtensa_mark_narrow_branches (void)
7042 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7043 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7046 /* Walk over all of the fragments in a subsection. */
7047 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7049 if (fragP
->fr_type
== rs_machine_dependent
7050 && fragP
->fr_subtype
== RELAX_SLOTS
7051 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7055 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7056 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7058 if (vinsn
.num_slots
== 1
7059 && xtensa_opcode_is_branch (xtensa_default_isa
,
7060 vinsn
.slots
[0].opcode
) == 1
7061 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7062 && is_narrow_branch_guaranteed_in_range (fragP
,
7065 fragP
->fr_subtype
= RELAX_SLOTS
;
7066 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7067 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7075 /* A branch is typically widened only when its target is out of
7076 range. However, we would like to widen them to align a subsequent
7077 branch target when possible.
7079 Because the branch relaxation code is so convoluted, the optimal solution
7080 (combining the two cases) is difficult to get right in all circumstances.
7081 We therefore go with an "almost as good" solution, where we only
7082 use for alignment narrow branches that definitely will not expand to a
7083 jump and a branch. These functions find and mark these cases. */
7085 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7086 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7087 We start counting beginning with the frag after the 2-byte branch, so the
7088 maximum offset is (4 - 2) + 63 = 65. */
7089 #define MAX_IMMED6 65
7091 static offsetT
unrelaxed_frag_max_size (fragS
*);
7094 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7096 const expressionS
*expr
= &tinsn
->tok
[1];
7097 symbolS
*symbolP
= expr
->X_add_symbol
;
7098 offsetT max_distance
= expr
->X_add_number
;
7101 if (expr
->X_op
!= O_symbol
)
7104 target_frag
= symbol_get_frag (symbolP
);
7106 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7107 if (is_branch_jmp_to_next (tinsn
, fragP
))
7110 /* The branch doesn't branch over it's own frag,
7111 but over the subsequent ones. */
7112 fragP
= fragP
->fr_next
;
7113 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7115 max_distance
+= unrelaxed_frag_max_size (fragP
);
7116 fragP
= fragP
->fr_next
;
7118 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7125 xtensa_mark_zcl_first_insns (void)
7130 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7131 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7134 /* Walk over all of the fragments in a subsection. */
7135 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7137 if (fragP
->fr_type
== rs_machine_dependent
7138 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7139 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7141 /* Find the loop frag. */
7142 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7143 /* Find the first insn frag. */
7144 targ_frag
= next_non_empty_frag (targ_frag
);
7146 /* Of course, sometimes (mostly for toy test cases) a
7147 zero-cost loop instruction is the last in a section. */
7150 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7151 /* Do not widen a frag that is the first instruction of a
7152 zero-cost loop. It makes that loop harder to align. */
7153 if (targ_frag
->fr_type
== rs_machine_dependent
7154 && targ_frag
->fr_subtype
== RELAX_SLOTS
7155 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7158 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7159 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7162 frag_wane (targ_frag
);
7163 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7167 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7175 /* Re-process all of the fragments looking to convert all of the
7176 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7177 conditional branch or a retw/retw.n, convert this frag to one that
7178 will generate a NOP. In any case close it off with a .fill 0. */
7180 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7183 xtensa_fix_a0_b_retw_frags (void)
7188 /* When this routine is called, all of the subsections are still intact
7189 so we walk over subsections instead of sections. */
7190 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7191 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7195 /* Walk over all of the fragments in a subsection. */
7196 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7198 if (fragP
->fr_type
== rs_machine_dependent
7199 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7201 if (next_instrs_are_b_retw (fragP
))
7203 if (fragP
->tc_frag_data
.is_no_transform
)
7204 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7206 relax_frag_add_nop (fragP
);
7216 next_instrs_are_b_retw (fragS
*fragP
)
7218 xtensa_opcode opcode
;
7220 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7221 static xtensa_insnbuf insnbuf
= NULL
;
7222 static xtensa_insnbuf slotbuf
= NULL
;
7223 xtensa_isa isa
= xtensa_default_isa
;
7226 bfd_boolean branch_seen
= FALSE
;
7230 insnbuf
= xtensa_insnbuf_alloc (isa
);
7231 slotbuf
= xtensa_insnbuf_alloc (isa
);
7234 if (next_fragP
== NULL
)
7237 /* Check for the conditional branch. */
7238 xtensa_insnbuf_from_chars
7239 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7240 fmt
= xtensa_format_decode (isa
, insnbuf
);
7241 if (fmt
== XTENSA_UNDEFINED
)
7244 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7246 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7247 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7249 branch_seen
= (branch_seen
7250 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7256 offset
+= xtensa_format_length (isa
, fmt
);
7257 if (offset
== next_fragP
->fr_fix
)
7259 next_fragP
= next_non_empty_frag (next_fragP
);
7263 if (next_fragP
== NULL
)
7266 /* Check for the retw/retw.n. */
7267 xtensa_insnbuf_from_chars
7268 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7269 fmt
= xtensa_format_decode (isa
, insnbuf
);
7271 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7272 have no problems. */
7273 if (fmt
== XTENSA_UNDEFINED
7274 || xtensa_format_num_slots (isa
, fmt
) != 1)
7277 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7278 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7280 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7287 /* Re-process all of the fragments looking to convert all of the
7288 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7289 loop end label, convert this frag to one that will generate a NOP.
7290 In any case close it off with a .fill 0. */
7292 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7295 xtensa_fix_b_j_loop_end_frags (void)
7300 /* When this routine is called, all of the subsections are still intact
7301 so we walk over subsections instead of sections. */
7302 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7303 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7307 /* Walk over all of the fragments in a subsection. */
7308 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7310 if (fragP
->fr_type
== rs_machine_dependent
7311 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7313 if (next_instr_is_loop_end (fragP
))
7315 if (fragP
->tc_frag_data
.is_no_transform
)
7316 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7318 relax_frag_add_nop (fragP
);
7328 next_instr_is_loop_end (fragS
*fragP
)
7330 const fragS
*next_fragP
;
7332 if (next_frag_is_loop_target (fragP
))
7335 next_fragP
= next_non_empty_frag (fragP
);
7336 if (next_fragP
== NULL
)
7339 if (!next_frag_is_loop_target (next_fragP
))
7342 /* If the size is >= 3 then there is more than one instruction here.
7343 The hardware bug will not fire. */
7344 if (next_fragP
->fr_fix
> 3)
7351 /* Re-process all of the fragments looking to convert all of the
7352 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7353 not MY loop's loop end within 12 bytes, add enough nops here to
7354 make it at least 12 bytes away. In any case close it off with a
7357 static offsetT min_bytes_to_other_loop_end
7358 (fragS
*, fragS
*, offsetT
);
7361 xtensa_fix_close_loop_end_frags (void)
7366 /* When this routine is called, all of the subsections are still intact
7367 so we walk over subsections instead of sections. */
7368 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7369 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7373 fragS
*current_target
= NULL
;
7375 /* Walk over all of the fragments in a subsection. */
7376 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7378 if (fragP
->fr_type
== rs_machine_dependent
7379 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7380 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7381 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7384 && fragP
->fr_type
== rs_machine_dependent
7385 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7388 int bytes_added
= 0;
7390 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7391 /* Max out at 12. */
7392 min_bytes
= min_bytes_to_other_loop_end
7393 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7395 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7397 if (fragP
->tc_frag_data
.is_no_transform
)
7398 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7401 while (min_bytes
+ bytes_added
7402 < REQUIRED_LOOP_DIVIDING_BYTES
)
7406 if (fragP
->fr_var
< length
)
7407 as_fatal (_("fr_var %lu < length %d"),
7408 (long) fragP
->fr_var
, length
);
7411 assemble_nop (length
,
7412 fragP
->fr_literal
+ fragP
->fr_fix
);
7413 fragP
->fr_fix
+= length
;
7414 fragP
->fr_var
-= length
;
7416 bytes_added
+= length
;
7422 assert (fragP
->fr_type
!= rs_machine_dependent
7423 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7429 static offsetT
unrelaxed_frag_min_size (fragS
*);
7432 min_bytes_to_other_loop_end (fragS
*fragP
,
7433 fragS
*current_target
,
7437 fragS
*current_fragP
;
7439 for (current_fragP
= fragP
;
7441 current_fragP
= current_fragP
->fr_next
)
7443 if (current_fragP
->tc_frag_data
.is_loop_target
7444 && current_fragP
!= current_target
)
7447 offset
+= unrelaxed_frag_min_size (current_fragP
);
7449 if (offset
>= max_size
)
7457 unrelaxed_frag_min_size (fragS
*fragP
)
7459 offsetT size
= fragP
->fr_fix
;
7461 /* Add fill size. */
7462 if (fragP
->fr_type
== rs_fill
)
7463 size
+= fragP
->fr_offset
;
7470 unrelaxed_frag_max_size (fragS
*fragP
)
7472 offsetT size
= fragP
->fr_fix
;
7473 switch (fragP
->fr_type
)
7476 /* Empty frags created by the obstack allocation scheme
7477 end up with type 0. */
7482 size
+= fragP
->fr_offset
;
7490 /* No further adjustments needed. */
7492 case rs_machine_dependent
:
7493 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7494 size
+= fragP
->fr_var
;
7497 /* We had darn well better know how big it is. */
7506 /* Re-process all of the fragments looking to convert all
7507 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7510 1) the instruction size count to the loop end label
7511 is too short (<= 2 instructions),
7512 2) loop has a jump or branch in it
7515 1) workaround_all_short_loops is TRUE
7516 2) The generating loop was a 'loopgtz' or 'loopnez'
7517 3) the instruction size count to the loop end label is too short
7519 then convert this frag (and maybe the next one) to generate a NOP.
7520 In any case close it off with a .fill 0. */
7522 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7523 static bfd_boolean
branch_before_loop_end (fragS
*);
7526 xtensa_fix_short_loop_frags (void)
7531 /* When this routine is called, all of the subsections are still intact
7532 so we walk over subsections instead of sections. */
7533 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7534 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7537 fragS
*current_target
= NULL
;
7538 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7540 /* Walk over all of the fragments in a subsection. */
7541 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7543 if (fragP
->fr_type
== rs_machine_dependent
7544 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7545 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7548 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7549 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7550 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7551 current_opcode
= t_insn
.opcode
;
7552 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7553 current_opcode
) == 1);
7556 if (fragP
->fr_type
== rs_machine_dependent
7557 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7559 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7560 && (branch_before_loop_end (fragP
->fr_next
)
7561 || (workaround_all_short_loops
7562 && current_opcode
!= XTENSA_UNDEFINED
7563 && current_opcode
!= xtensa_loop_opcode
)))
7565 if (fragP
->tc_frag_data
.is_no_transform
)
7566 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7568 relax_frag_add_nop (fragP
);
7577 static int unrelaxed_frag_min_insn_count (fragS
*);
7580 count_insns_to_loop_end (fragS
*base_fragP
,
7581 bfd_boolean count_relax_add
,
7584 fragS
*fragP
= NULL
;
7589 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7591 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7592 if (insn_count
>= max_count
)
7595 if (count_relax_add
)
7597 if (fragP
->fr_type
== rs_machine_dependent
7598 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7600 /* In order to add the appropriate number of
7601 NOPs, we count an instruction for downstream
7604 if (insn_count
>= max_count
)
7614 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7616 xtensa_isa isa
= xtensa_default_isa
;
7617 static xtensa_insnbuf insnbuf
= NULL
;
7621 if (!fragP
->tc_frag_data
.is_insn
)
7625 insnbuf
= xtensa_insnbuf_alloc (isa
);
7627 /* Decode the fixed instructions. */
7628 while (offset
< fragP
->fr_fix
)
7632 xtensa_insnbuf_from_chars
7633 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7634 fmt
= xtensa_format_decode (isa
, insnbuf
);
7636 if (fmt
== XTENSA_UNDEFINED
)
7638 as_fatal (_("undecodable instruction in instruction frag"));
7641 offset
+= xtensa_format_length (isa
, fmt
);
7649 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7652 branch_before_loop_end (fragS
*base_fragP
)
7656 for (fragP
= base_fragP
;
7657 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7658 fragP
= fragP
->fr_next
)
7660 if (unrelaxed_frag_has_b_j (fragP
))
7668 unrelaxed_frag_has_b_j (fragS
*fragP
)
7670 static xtensa_insnbuf insnbuf
= NULL
;
7671 xtensa_isa isa
= xtensa_default_isa
;
7674 if (!fragP
->tc_frag_data
.is_insn
)
7678 insnbuf
= xtensa_insnbuf_alloc (isa
);
7680 /* Decode the fixed instructions. */
7681 while (offset
< fragP
->fr_fix
)
7686 xtensa_insnbuf_from_chars
7687 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7688 fmt
= xtensa_format_decode (isa
, insnbuf
);
7689 if (fmt
== XTENSA_UNDEFINED
)
7692 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7694 xtensa_opcode opcode
=
7695 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7696 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7697 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7700 offset
+= xtensa_format_length (isa
, fmt
);
7706 /* Checks to be made after initial assembly but before relaxation. */
7708 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7709 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7712 xtensa_sanity_check (void)
7719 as_where (&file_name
, &line
);
7720 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7721 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7725 /* Walk over all of the fragments in a subsection. */
7726 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7728 /* Currently we only check for empty loops here. */
7729 if (fragP
->fr_type
== rs_machine_dependent
7730 && fragP
->fr_subtype
== RELAX_IMMED
)
7732 static xtensa_insnbuf insnbuf
= NULL
;
7735 if (fragP
->fr_opcode
!= NULL
)
7738 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7739 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7740 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7742 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7743 t_insn
.opcode
) == 1)
7745 if (is_empty_loop (&t_insn
, fragP
))
7747 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7748 as_bad (_("invalid empty loop"));
7750 if (!is_local_forward_loop (&t_insn
, fragP
))
7752 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7753 as_bad (_("loop target does not follow "
7754 "loop instruction in section"));
7761 new_logical_line (file_name
, line
);
7765 #define LOOP_IMMED_OPN 1
7767 /* Return TRUE if the loop target is the next non-zero fragment. */
7770 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7772 const expressionS
*expr
;
7776 if (insn
->insn_type
!= ITYPE_INSN
)
7779 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7782 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7785 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7787 if (expr
->X_op
!= O_symbol
)
7790 symbolP
= expr
->X_add_symbol
;
7794 if (symbol_get_frag (symbolP
) == NULL
)
7797 if (S_GET_VALUE (symbolP
) != 0)
7800 /* Walk through the zero-size fragments from this one. If we find
7801 the target fragment, then this is a zero-size loop. */
7803 for (next_fragP
= fragP
->fr_next
;
7805 next_fragP
= next_fragP
->fr_next
)
7807 if (next_fragP
== symbol_get_frag (symbolP
))
7809 if (next_fragP
->fr_fix
!= 0)
7817 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7819 const expressionS
*expr
;
7823 if (insn
->insn_type
!= ITYPE_INSN
)
7826 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7829 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7832 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7834 if (expr
->X_op
!= O_symbol
)
7837 symbolP
= expr
->X_add_symbol
;
7841 if (symbol_get_frag (symbolP
) == NULL
)
7844 /* Walk through fragments until we find the target.
7845 If we do not find the target, then this is an invalid loop. */
7847 for (next_fragP
= fragP
->fr_next
;
7849 next_fragP
= next_fragP
->fr_next
)
7851 if (next_fragP
== symbol_get_frag (symbolP
))
7859 /* Alignment Functions. */
7862 get_text_align_power (unsigned target_size
)
7864 if (target_size
<= 4)
7866 assert (target_size
== 8);
7872 get_text_align_max_fill_size (int align_pow
,
7873 bfd_boolean use_nops
,
7874 bfd_boolean use_no_density
)
7877 return (1 << align_pow
);
7879 return 3 * (1 << align_pow
);
7881 return 1 + (1 << align_pow
);
7885 /* Calculate the minimum bytes of fill needed at "address" to align a
7886 target instruction of size "target_size" so that it does not cross a
7887 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7888 the fill can be an arbitrary number of bytes. Otherwise, the space must
7889 be filled by NOP instructions. */
7892 get_text_align_fill_size (addressT address
,
7895 bfd_boolean use_nops
,
7896 bfd_boolean use_no_density
)
7898 addressT alignment
, fill
, fill_limit
, fill_step
;
7899 bfd_boolean skip_one
= FALSE
;
7901 alignment
= (1 << align_pow
);
7902 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7906 fill_limit
= alignment
;
7909 else if (!use_no_density
)
7911 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7912 fill_limit
= alignment
* 2;
7918 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7919 fill_limit
= alignment
* 3;
7923 /* Try all fill sizes until finding one that works. */
7924 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7926 if (skip_one
&& fill
== 1)
7928 if ((address
+ fill
) >> align_pow
7929 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7938 branch_align_power (segT sec
)
7940 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7941 is aligned to at least an 8-byte boundary, then a branch target need
7942 only fit within an 8-byte aligned block of memory to avoid a stall.
7943 Otherwise, try to fit branch targets within 4-byte aligned blocks
7944 (which may be insufficient, e.g., if the section has no alignment, but
7945 it's good enough). */
7946 if (xtensa_fetch_width
== 8)
7948 if (get_recorded_alignment (sec
) >= 3)
7952 assert (xtensa_fetch_width
== 4);
7958 /* This will assert if it is not possible. */
7961 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7967 assert (fill_size
% 3 == 0);
7968 return (fill_size
/ 3);
7971 assert (fill_size
!= 1); /* Bad argument. */
7973 while (fill_size
> 1)
7976 if (fill_size
== 2 || fill_size
== 4)
7978 fill_size
-= insn_size
;
7981 assert (fill_size
!= 1); /* Bad algorithm. */
7987 get_text_align_nth_nop_size (offsetT fill_size
,
7989 bfd_boolean use_no_density
)
7996 assert (fill_size
!= 1); /* Bad argument. */
7998 while (fill_size
> 1)
8001 if (fill_size
== 2 || fill_size
== 4)
8003 fill_size
-= insn_size
;
8013 /* For the given fragment, find the appropriate address
8014 for it to begin at if we are using NOPs to align it. */
8017 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8019 /* The rule is: get next fragment's FIRST instruction. Find
8020 the smallest number of bytes that need to be added to
8021 ensure that the next fragment's FIRST instruction will fit
8024 E.G., 2 bytes : 0, 1, 2 mod 4
8027 If the FIRST instruction MIGHT be relaxed,
8028 assume that it will become a 3-byte instruction.
8030 Note again here that LOOP instructions are not bundleable,
8031 and this relaxation only applies to LOOP opcodes. */
8034 int first_insn_size
;
8036 addressT pre_opcode_bytes
;
8039 xtensa_opcode opcode
;
8040 bfd_boolean is_loop
;
8042 assert (fragP
->fr_type
== rs_machine_dependent
);
8043 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8045 /* Find the loop frag. */
8046 first_insn
= next_non_empty_frag (fragP
);
8047 /* Now find the first insn frag. */
8048 first_insn
= next_non_empty_frag (first_insn
);
8050 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8052 loop_insn_size
= xg_get_single_size (opcode
);
8054 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8055 pre_opcode_bytes
+= loop_insn_size
;
8057 /* For loops, the alignment depends on the size of the
8058 instruction following the loop, not the LOOP instruction. */
8060 if (first_insn
== NULL
)
8061 first_insn_size
= xtensa_fetch_width
;
8063 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8065 /* If it was 8, then we'll need a larger alignment for the section. */
8066 align_power
= get_text_align_power (first_insn_size
);
8067 record_alignment (now_seg
, align_power
);
8069 fill_size
= get_text_align_fill_size
8070 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8071 fragP
->tc_frag_data
.is_no_density
);
8073 return address
+ fill_size
;
8077 /* 3 mechanisms for relaxing an alignment:
8079 Align to a power of 2.
8080 Align so the next fragment's instruction does not cross a word boundary.
8081 Align the current instruction so that if the next instruction
8082 were 3 bytes, it would not cross a word boundary.
8086 zeros - This is easy; always insert zeros.
8087 nops - 3-byte and 2-byte instructions
8091 >=5 : 3-byte instruction + fn (n-3)
8092 widening - widen previous instructions. */
8095 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8097 addressT target_address
, loop_insn_offset
;
8099 xtensa_opcode loop_opcode
;
8100 bfd_boolean is_loop
;
8103 offsetT branch_align
;
8105 assert (fragP
->fr_type
== rs_machine_dependent
);
8106 switch (fragP
->fr_subtype
)
8108 case RELAX_DESIRE_ALIGN
:
8109 target_size
= next_frag_format_size (fragP
);
8110 if (target_size
== XTENSA_UNDEFINED
)
8112 align_power
= branch_align_power (now_seg
);
8113 branch_align
= 1 << align_power
;
8114 /* Don't count on the section alignment being as large as the target. */
8115 if (target_size
> branch_align
)
8116 target_size
= branch_align
;
8117 opt_diff
= get_text_align_fill_size (address
, align_power
,
8118 target_size
, FALSE
, FALSE
);
8120 *max_diff
= (opt_diff
+ branch_align
8121 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8122 assert (*max_diff
>= opt_diff
);
8125 case RELAX_ALIGN_NEXT_OPCODE
:
8126 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8127 loop_insn_offset
= 0;
8128 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8131 /* If the loop has been expanded then the LOOP instruction
8132 could be at an offset from this fragment. */
8133 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8135 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8137 /* In an ideal world, which is what we are shooting for here,
8138 we wouldn't need to use any NOPs immediately prior to the
8139 LOOP instruction. If this approach fails, relax_frag_loop_align
8140 will call get_noop_aligned_address. */
8142 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8143 align_power
= get_text_align_power (target_size
),
8144 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8145 target_size
, FALSE
, FALSE
);
8147 *max_diff
= xtensa_fetch_width
8148 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8149 - target_size
+ opt_diff
;
8150 assert (*max_diff
>= opt_diff
);
8161 /* md_relax_frag Hook and Helper Functions. */
8163 static long relax_frag_loop_align (fragS
*, long);
8164 static long relax_frag_for_align (fragS
*, long);
8165 static long relax_frag_immed
8166 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8169 /* Return the number of bytes added to this fragment, given that the
8170 input has been stretched already by "stretch". */
8173 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8175 xtensa_isa isa
= xtensa_default_isa
;
8176 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8177 long new_stretch
= 0;
8181 static xtensa_insnbuf vbuf
= NULL
;
8182 int slot
, num_slots
;
8185 as_where (&file_name
, &line
);
8186 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8188 fragP
->tc_frag_data
.unreported_expansion
= 0;
8190 switch (fragP
->fr_subtype
)
8192 case RELAX_ALIGN_NEXT_OPCODE
:
8193 /* Always convert. */
8194 if (fragP
->tc_frag_data
.relax_seen
)
8195 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8198 case RELAX_LOOP_END
:
8202 case RELAX_LOOP_END_ADD_NOP
:
8203 /* Add a NOP and switch to .fill 0. */
8204 new_stretch
= relax_frag_add_nop (fragP
);
8208 case RELAX_DESIRE_ALIGN
:
8209 /* Do nothing. The narrowing before this frag will either align
8214 case RELAX_LITERAL_FINAL
:
8217 case RELAX_LITERAL_NR
:
8219 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8220 assert (unreported
== lit_size
);
8221 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8222 fragP
->fr_var
-= lit_size
;
8223 fragP
->fr_fix
+= lit_size
;
8229 vbuf
= xtensa_insnbuf_alloc (isa
);
8231 xtensa_insnbuf_from_chars
8232 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8233 fmt
= xtensa_format_decode (isa
, vbuf
);
8234 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8236 for (slot
= 0; slot
< num_slots
; slot
++)
8238 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8241 if (fragP
->tc_frag_data
.relax_seen
)
8242 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8246 case RELAX_IMMED_STEP1
:
8247 case RELAX_IMMED_STEP2
:
8248 /* Place the immediate. */
8249 new_stretch
+= relax_frag_immed
8250 (now_seg
, fragP
, stretch
,
8251 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8252 fmt
, slot
, stretched_p
, FALSE
);
8256 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8262 case RELAX_LITERAL_POOL_BEGIN
:
8263 case RELAX_LITERAL_POOL_END
:
8264 case RELAX_MAYBE_UNREACHABLE
:
8265 case RELAX_MAYBE_DESIRE_ALIGN
:
8266 /* No relaxation required. */
8269 case RELAX_FILL_NOP
:
8270 case RELAX_UNREACHABLE
:
8271 if (fragP
->tc_frag_data
.relax_seen
)
8272 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8276 as_bad (_("bad relaxation state"));
8279 /* Tell gas we need another relaxation pass. */
8280 if (! fragP
->tc_frag_data
.relax_seen
)
8282 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8286 new_logical_line (file_name
, line
);
8292 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8294 addressT old_address
, old_next_address
, old_size
;
8295 addressT new_address
, new_next_address
, new_size
;
8298 /* All the frags with relax_frag_for_alignment prior to this one in the
8299 section have been done, hopefully eliminating the need for a NOP here.
8300 But, this will put it in if necessary. */
8302 /* Calculate the old address of this fragment and the next fragment. */
8303 old_address
= fragP
->fr_address
- stretch
;
8304 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8305 fragP
->tc_frag_data
.text_expansion
[0]);
8306 old_size
= old_next_address
- old_address
;
8308 /* Calculate the new address of this fragment and the next fragment. */
8309 new_address
= fragP
->fr_address
;
8311 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8312 new_size
= new_next_address
- new_address
;
8314 growth
= new_size
- old_size
;
8316 /* Fix up the text_expansion field and return the new growth. */
8317 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8322 /* Add a NOP instruction. */
8325 relax_frag_add_nop (fragS
*fragP
)
8327 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8328 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8329 assemble_nop (length
, nop_buf
);
8330 fragP
->tc_frag_data
.is_insn
= TRUE
;
8332 if (fragP
->fr_var
< length
)
8334 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8338 fragP
->fr_fix
+= length
;
8339 fragP
->fr_var
-= length
;
8344 static long future_alignment_required (fragS
*, long);
8347 relax_frag_for_align (fragS
*fragP
, long stretch
)
8349 /* Overview of the relaxation procedure for alignment:
8350 We can widen with NOPs or by widening instructions or by filling
8351 bytes after jump instructions. Find the opportune places and widen
8352 them if necessary. */
8357 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8358 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8359 || (fragP
->fr_subtype
== RELAX_SLOTS
8360 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8362 stretch_me
= future_alignment_required (fragP
, stretch
);
8363 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8369 /* We expanded on a previous pass. Can we shrink now? */
8370 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8371 if (shrink
<= stretch
&& stretch
> 0)
8373 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8379 /* Below here, diff > 0. */
8380 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8386 /* Return the address of the next frag that should be aligned.
8388 By "address" we mean the address it _would_ be at if there
8389 is no action taken to align it between here and the target frag.
8390 In other words, if no narrows and no fill nops are used between
8391 here and the frag to align, _even_if_ some of the frags we use
8392 to align targets have already expanded on a previous relaxation
8395 Also, count each frag that may be used to help align the target.
8397 Return 0 if there are no frags left in the chain that need to be
8401 find_address_of_next_align_frag (fragS
**fragPP
,
8405 bfd_boolean
*paddable
)
8407 fragS
*fragP
= *fragPP
;
8408 addressT address
= fragP
->fr_address
;
8410 /* Do not reset the counts to 0. */
8414 /* Limit this to a small search. */
8415 if (*widens
>= (int) xtensa_fetch_width
)
8420 address
+= fragP
->fr_fix
;
8422 if (fragP
->fr_type
== rs_fill
)
8423 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8424 else if (fragP
->fr_type
== rs_machine_dependent
)
8426 switch (fragP
->fr_subtype
)
8428 case RELAX_UNREACHABLE
:
8432 case RELAX_FILL_NOP
:
8434 if (!fragP
->tc_frag_data
.is_no_density
)
8439 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8444 address
+= total_frag_text_expansion (fragP
);;
8448 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8451 case RELAX_ALIGN_NEXT_OPCODE
:
8452 case RELAX_DESIRE_ALIGN
:
8456 case RELAX_MAYBE_UNREACHABLE
:
8457 case RELAX_MAYBE_DESIRE_ALIGN
:
8462 /* Just punt if we don't know the type. */
8469 /* Just punt if we don't know the type. */
8473 fragP
= fragP
->fr_next
;
8481 static long bytes_to_stretch (fragS
*, int, int, int, int);
8484 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8486 fragS
*this_frag
= fragP
;
8490 int narrow_nops
= 0;
8491 bfd_boolean paddable
= FALSE
;
8492 offsetT local_opt_diff
;
8495 int stretch_amount
= 0;
8496 int local_stretch_amount
;
8497 int global_stretch_amount
;
8499 address
= find_address_of_next_align_frag
8500 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8504 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8505 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8507 frag_wane (this_frag
);
8511 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8512 opt_diff
= local_opt_diff
;
8513 assert (opt_diff
>= 0);
8514 assert (max_diff
>= opt_diff
);
8519 fragP
= fragP
->fr_next
;
8521 while (fragP
&& opt_diff
< max_diff
&& address
)
8523 /* We only use these to determine if we can exit early
8524 because there will be plenty of ways to align future
8526 int glob_widens
= 0;
8529 bfd_boolean glob_pad
= 0;
8530 address
= find_address_of_next_align_frag
8531 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8532 /* If there is a padable portion, then skip. */
8533 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8538 offsetT next_m_diff
;
8539 offsetT next_o_diff
;
8541 /* Downrange frags haven't had stretch added to them yet. */
8544 /* The address also includes any text expansion from this
8545 frag in a previous pass, but we don't want that. */
8546 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8548 /* Assume we are going to move at least opt_diff. In
8549 reality, we might not be able to, but assuming that
8550 we will helps catch cases where moving opt_diff pushes
8551 the next target from aligned to unaligned. */
8552 address
+= opt_diff
;
8554 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8556 /* Now cleanup for the adjustments to address. */
8557 next_o_diff
+= opt_diff
;
8558 next_m_diff
+= opt_diff
;
8559 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8560 opt_diff
= next_o_diff
;
8561 if (next_m_diff
< max_diff
)
8562 max_diff
= next_m_diff
;
8563 fragP
= fragP
->fr_next
;
8567 /* If there are enough wideners in between, do it. */
8570 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8572 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8577 local_stretch_amount
8578 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8579 num_widens
, local_opt_diff
);
8580 global_stretch_amount
8581 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8582 num_widens
, opt_diff
);
8583 /* If the condition below is true, then the frag couldn't
8584 stretch the correct amount for the global case, so we just
8585 optimize locally. We'll rely on the subsequent frags to get
8586 the correct alignment in the global case. */
8587 if (global_stretch_amount
< local_stretch_amount
)
8588 stretch_amount
= local_stretch_amount
;
8590 stretch_amount
= global_stretch_amount
;
8592 if (this_frag
->fr_subtype
== RELAX_SLOTS
8593 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8594 assert (stretch_amount
<= 1);
8595 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8597 if (this_frag
->tc_frag_data
.is_no_density
)
8598 assert (stretch_amount
== 3 || stretch_amount
== 0);
8600 assert (stretch_amount
<= 3);
8603 return stretch_amount
;
8607 /* The idea: widen everything you can to get a target or loop aligned,
8608 then start using NOPs.
8610 When we must have a NOP, here is a table of how we decide
8611 (so you don't have to fight through the control flow below):
8613 wide_nops = the number of wide NOPs available for aligning
8614 narrow_nops = the number of narrow NOPs available for aligning
8615 (a subset of wide_nops)
8616 widens = the number of narrow instructions that should be widened
8623 b 0 1 1 (case 3a makes this case unnecessary)
8626 c 0 1 2 (case 4a makes this case unnecessary)
8629 c 0 2 1 (case 5b makes this case unnecessary)
8632 c 0 1 4 (case 6b makes this case unnecessary)
8633 d 1 1 1 (case 6a makes this case unnecessary)
8634 e 0 2 2 (case 6a makes this case unnecessary)
8635 f 0 3 0 (case 6a makes this case unnecessary)
8638 c 1 1 2 (case 7b makes this case unnecessary)
8639 d 0 1 5 (case 7a makes this case unnecessary)
8640 e 0 2 3 (case 7b makes this case unnecessary)
8641 f 0 3 1 (case 7b makes this case unnecessary)
8642 g 1 2 1 (case 7b makes this case unnecessary)
8646 bytes_to_stretch (fragS
*this_frag
,
8652 int bytes_short
= desired_diff
- num_widens
;
8654 assert (desired_diff
>= 0 && desired_diff
< 8);
8655 if (desired_diff
== 0)
8658 assert (wide_nops
> 0 || num_widens
> 0);
8660 /* Always prefer widening to NOP-filling. */
8661 if (bytes_short
< 0)
8663 /* There are enough RELAX_NARROW frags after this one
8664 to align the target without widening this frag in any way. */
8668 if (bytes_short
== 0)
8670 /* Widen every narrow between here and the align target
8671 and the align target will be properly aligned. */
8672 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8678 /* From here we will need at least one NOP to get an alignment.
8679 However, we may not be able to align at all, in which case,
8681 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8683 switch (desired_diff
)
8688 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8689 return 2; /* case 2 */
8695 return 3; /* case 3a */
8697 if (num_widens
>= 1 && wide_nops
== 1)
8698 return 3; /* case 4a */
8699 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8700 return 2; /* case 4b */
8703 if (num_widens
>= 2 && wide_nops
== 1)
8704 return 3; /* case 5a */
8705 /* We will need two nops. Are there enough nops
8706 between here and the align target? */
8707 if (wide_nops
< 2 || narrow_nops
== 0)
8709 /* Are there other nops closer that can serve instead? */
8710 if (wide_nops
> 2 && narrow_nops
> 1)
8712 /* Take the density one first, because there might not be
8713 another density one available. */
8714 if (!this_frag
->tc_frag_data
.is_no_density
)
8715 return 2; /* case 5b narrow */
8717 return 3; /* case 5b wide */
8721 return 3; /* case 6a */
8722 else if (num_widens
>= 3 && wide_nops
== 1)
8723 return 3; /* case 6b */
8726 if (wide_nops
== 1 && num_widens
>= 4)
8727 return 3; /* case 7a */
8728 else if (wide_nops
== 2 && num_widens
>= 1)
8729 return 3; /* case 7b */
8737 /* We will need a NOP no matter what, but should we widen
8738 this instruction to help?
8740 This is a RELAX_NARROW frag. */
8741 switch (desired_diff
)
8750 if (wide_nops
>= 1 && num_widens
== 1)
8751 return 1; /* case 4a */
8754 if (wide_nops
>= 1 && num_widens
== 2)
8755 return 1; /* case 5a */
8759 return 0; /* case 6a */
8760 else if (wide_nops
>= 1 && num_widens
== 3)
8761 return 1; /* case 6b */
8764 if (wide_nops
>= 1 && num_widens
== 4)
8765 return 1; /* case 7a */
8766 else if (wide_nops
>= 2 && num_widens
== 1)
8767 return 1; /* case 7b */
8780 relax_frag_immed (segT segP
,
8787 bfd_boolean estimate_only
)
8791 bfd_boolean negatable_branch
= FALSE
;
8792 bfd_boolean branch_jmp_to_next
= FALSE
;
8793 bfd_boolean wide_insn
= FALSE
;
8794 xtensa_isa isa
= xtensa_default_isa
;
8796 offsetT frag_offset
;
8799 int num_text_bytes
, num_literal_bytes
;
8800 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8802 assert (fragP
->fr_opcode
!= NULL
);
8804 xg_clear_vinsn (&cur_vinsn
);
8805 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8806 if (cur_vinsn
.num_slots
> 1)
8809 tinsn
= cur_vinsn
.slots
[slot
];
8810 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8812 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8815 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8816 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8818 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8820 old_size
= xtensa_format_length (isa
, fmt
);
8822 /* Special case: replace a branch to the next instruction with a NOP.
8823 This is required to work around a hardware bug in T1040.0 and also
8824 serves as an optimization. */
8826 if (branch_jmp_to_next
8827 && ((old_size
== 2) || (old_size
== 3))
8828 && !next_frag_is_loop_target (fragP
))
8831 /* Here is the fun stuff: Get the immediate field from this
8832 instruction. If it fits, we are done. If not, find the next
8833 instruction sequence that fits. */
8835 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8836 istack_init (&istack
);
8837 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8838 min_steps
, stretch
);
8839 if (num_steps
< min_steps
)
8841 as_fatal (_("internal error: relaxation failed"));
8845 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8847 as_fatal (_("internal error: relaxation requires too many steps"));
8851 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8853 /* Figure out the number of bytes needed. */
8855 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8857 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8859 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8861 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8864 num_text_bytes
+= old_size
;
8865 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8866 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8868 total_text_diff
= num_text_bytes
- old_size
;
8869 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8871 /* It MUST get larger. If not, we could get an infinite loop. */
8872 assert (num_text_bytes
>= 0);
8873 assert (literal_diff
>= 0);
8874 assert (total_text_diff
>= 0);
8876 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8877 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8878 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8879 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8881 /* Find the associated expandable literal for this. */
8882 if (literal_diff
!= 0)
8884 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8887 assert (literal_diff
== 4);
8888 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8890 /* We expect that the literal section state has NOT been
8892 assert (lit_fragP
->fr_type
== rs_machine_dependent
8893 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8894 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8896 /* We need to mark this section for another iteration
8902 if (negatable_branch
&& istack
.ninsn
> 1)
8903 update_next_frag_state (fragP
);
8905 return this_text_diff
;
8909 /* md_convert_frag Hook and Helper Functions. */
8911 static void convert_frag_align_next_opcode (fragS
*);
8912 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8913 static void convert_frag_fill_nop (fragS
*);
8914 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8917 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8919 static xtensa_insnbuf vbuf
= NULL
;
8920 xtensa_isa isa
= xtensa_default_isa
;
8927 as_where (&file_name
, &line
);
8928 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8930 switch (fragp
->fr_subtype
)
8932 case RELAX_ALIGN_NEXT_OPCODE
:
8933 /* Always convert. */
8934 convert_frag_align_next_opcode (fragp
);
8937 case RELAX_DESIRE_ALIGN
:
8938 /* Do nothing. If not aligned already, too bad. */
8942 case RELAX_LITERAL_FINAL
:
8947 vbuf
= xtensa_insnbuf_alloc (isa
);
8949 xtensa_insnbuf_from_chars
8950 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8951 fmt
= xtensa_format_decode (isa
, vbuf
);
8952 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8954 for (slot
= 0; slot
< num_slots
; slot
++)
8956 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8959 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8963 case RELAX_IMMED_STEP1
:
8964 case RELAX_IMMED_STEP2
:
8965 /* Place the immediate. */
8968 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8973 /* This is OK because some slots could have
8974 relaxations and others have none. */
8980 case RELAX_UNREACHABLE
:
8981 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8982 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8983 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8987 case RELAX_MAYBE_UNREACHABLE
:
8988 case RELAX_MAYBE_DESIRE_ALIGN
:
8992 case RELAX_FILL_NOP
:
8993 convert_frag_fill_nop (fragp
);
8996 case RELAX_LITERAL_NR
:
8997 if (use_literal_section
)
8999 /* This should have been handled during relaxation. When
9000 relaxing a code segment, literals sometimes need to be
9001 added to the corresponding literal segment. If that
9002 literal segment has already been relaxed, then we end up
9003 in this situation. Marking the literal segments as data
9004 would make this happen less often (since GAS always relaxes
9005 code before data), but we could still get into trouble if
9006 there are instructions in a segment that is not marked as
9007 containing code. Until we can implement a better solution,
9008 cheat and adjust the addresses of all the following frags.
9009 This could break subsequent alignments, but the linker's
9010 literal coalescing will do that anyway. */
9013 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9014 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9015 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9018 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9022 as_bad (_("invalid relaxation fragment result"));
9027 new_logical_line (file_name
, line
);
9032 convert_frag_align_next_opcode (fragS
*fragp
)
9034 char *nop_buf
; /* Location for Writing. */
9035 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9036 addressT aligned_address
;
9040 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9042 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9043 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9044 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9046 for (nop
= 0; nop
< nop_count
; nop
++)
9049 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9051 assemble_nop (nop_size
, nop_buf
);
9052 nop_buf
+= nop_size
;
9055 fragp
->fr_fix
+= fill_size
;
9056 fragp
->fr_var
-= fill_size
;
9061 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9063 TInsn tinsn
, single_target
;
9064 int size
, old_size
, diff
;
9065 offsetT frag_offset
;
9068 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9070 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9072 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9073 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9074 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9079 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9081 /* No conversion. */
9086 assert (fragP
->fr_opcode
!= NULL
);
9088 /* Frags in this relaxation state should only contain
9089 single instruction bundles. */
9090 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9092 /* Just convert it to a wide form.... */
9094 old_size
= xg_get_single_size (tinsn
.opcode
);
9096 tinsn_init (&single_target
);
9097 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9099 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9101 as_bad (_("unable to widen instruction"));
9105 size
= xg_get_single_size (single_target
.opcode
);
9106 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9109 diff
= size
- old_size
;
9111 assert (diff
<= fragP
->fr_var
);
9112 fragP
->fr_var
-= diff
;
9113 fragP
->fr_fix
+= diff
;
9121 convert_frag_fill_nop (fragS
*fragP
)
9123 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9124 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9125 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9126 - fragP
->fr_address
- fragP
->fr_fix
));
9129 /* No conversion. */
9133 assemble_nop (size
, loc
);
9134 fragP
->tc_frag_data
.is_insn
= TRUE
;
9135 fragP
->fr_var
-= size
;
9136 fragP
->fr_fix
+= size
;
9141 static fixS
*fix_new_exp_in_seg
9142 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9143 bfd_reloc_code_real_type
);
9144 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9147 convert_frag_immed (segT segP
,
9153 char *immed_instr
= fragP
->fr_opcode
;
9155 bfd_boolean expanded
= FALSE
;
9156 bfd_boolean branch_jmp_to_next
= FALSE
;
9157 char *fr_opcode
= fragP
->fr_opcode
;
9158 xtensa_isa isa
= xtensa_default_isa
;
9159 bfd_boolean wide_insn
= FALSE
;
9161 bfd_boolean is_loop
;
9163 assert (fr_opcode
!= NULL
);
9165 xg_clear_vinsn (&cur_vinsn
);
9167 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9168 if (cur_vinsn
.num_slots
> 1)
9171 orig_tinsn
= cur_vinsn
.slots
[slot
];
9172 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9174 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9176 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9177 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9179 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9181 /* Conversion just inserts a NOP and marks the fix as completed. */
9182 bytes
= xtensa_format_length (isa
, fmt
);
9185 cur_vinsn
.slots
[slot
].opcode
=
9186 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9187 cur_vinsn
.slots
[slot
].ntok
= 0;
9191 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9192 assert (bytes
== 2 || bytes
== 3);
9193 build_nop (&cur_vinsn
.slots
[0], bytes
);
9194 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9196 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9197 xtensa_insnbuf_to_chars
9198 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9203 /* Here is the fun stuff: Get the immediate field from this
9204 instruction. If it fits, we're done. If not, find the next
9205 instruction sequence that fits. */
9209 symbolS
*lit_sym
= NULL
;
9211 int target_offset
= 0;
9214 symbolS
*gen_label
= NULL
;
9215 offsetT frag_offset
;
9216 bfd_boolean first
= TRUE
;
9217 bfd_boolean last_is_jump
;
9219 /* It does not fit. Find something that does and
9220 convert immediately. */
9221 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9222 istack_init (&istack
);
9223 xg_assembly_relax (&istack
, &orig_tinsn
,
9224 segP
, fragP
, frag_offset
, min_steps
, 0);
9226 old_size
= xtensa_format_length (isa
, fmt
);
9228 /* Assemble this right inline. */
9230 /* First, create the mapping from a label name to the REAL label. */
9232 for (i
= 0; i
< istack
.ninsn
; i
++)
9234 TInsn
*tinsn
= &istack
.insn
[i
];
9237 switch (tinsn
->insn_type
)
9240 if (lit_sym
!= NULL
)
9241 as_bad (_("multiple literals in expansion"));
9242 /* First find the appropriate space in the literal pool. */
9243 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9244 if (lit_frag
== NULL
)
9245 as_bad (_("no registered fragment for literal"));
9246 if (tinsn
->ntok
!= 1)
9247 as_bad (_("number of literal tokens != 1"));
9249 /* Set the literal symbol and add a fixup. */
9250 lit_sym
= lit_frag
->fr_symbol
;
9254 if (align_targets
&& !is_loop
)
9256 fragS
*unreach
= fragP
->fr_next
;
9257 while (!(unreach
->fr_type
== rs_machine_dependent
9258 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9259 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9261 unreach
= unreach
->fr_next
;
9264 assert (unreach
->fr_type
== rs_machine_dependent
9265 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9266 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9268 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9270 assert (gen_label
== NULL
);
9271 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9272 fr_opcode
- fragP
->fr_literal
9273 + target_offset
, fragP
);
9277 if (first
&& wide_insn
)
9279 target_offset
+= xtensa_format_length (isa
, fmt
);
9281 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9282 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9285 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9292 last_is_jump
= FALSE
;
9293 for (i
= 0; i
< istack
.ninsn
; i
++)
9295 TInsn
*tinsn
= &istack
.insn
[i
];
9299 bfd_reloc_code_real_type reloc_type
;
9301 switch (tinsn
->insn_type
)
9304 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9305 /* Already checked. */
9306 assert (lit_frag
!= NULL
);
9307 assert (lit_sym
!= NULL
);
9308 assert (tinsn
->ntok
== 1);
9310 target_seg
= S_GET_SEGMENT (lit_sym
);
9311 assert (target_seg
);
9312 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9313 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9315 reloc_type
= BFD_RELOC_32
;
9316 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9317 &tinsn
->tok
[0], FALSE
, reloc_type
);
9324 xg_resolve_labels (tinsn
, gen_label
);
9325 xg_resolve_literals (tinsn
, lit_sym
);
9326 if (wide_insn
&& first
)
9329 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9331 cur_vinsn
.slots
[slot
] = *tinsn
;
9335 cur_vinsn
.slots
[slot
].opcode
=
9336 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9337 cur_vinsn
.slots
[slot
].ntok
= 0;
9339 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9340 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9341 (unsigned char *) immed_instr
, 0);
9342 fragP
->tc_frag_data
.is_insn
= TRUE
;
9343 size
= xtensa_format_length (isa
, fmt
);
9344 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9347 (tinsn
, immed_instr
+ size
, fragP
,
9348 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9349 size
+= xg_get_single_size (tinsn
->opcode
);
9354 size
= xg_get_single_size (tinsn
->opcode
);
9355 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9356 immed_instr
- fragP
->fr_literal
, TRUE
);
9358 immed_instr
+= size
;
9364 diff
= total_size
- old_size
;
9368 assert (diff
<= fragP
->fr_var
);
9369 fragP
->fr_var
-= diff
;
9370 fragP
->fr_fix
+= diff
;
9373 /* Check for undefined immediates in LOOP instructions. */
9377 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9378 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9380 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9383 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9384 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9386 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9391 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9392 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9394 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9396 /* Add an expansion note on the expanded instruction. */
9397 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9398 &orig_tinsn
.tok
[0], TRUE
,
9399 BFD_RELOC_XTENSA_ASM_EXPAND
);
9404 /* Add a new fix expression into the desired segment. We have to
9405 switch to that segment to do this. */
9408 fix_new_exp_in_seg (segT new_seg
,
9415 bfd_reloc_code_real_type r_type
)
9419 subsegT subseg
= now_subseg
;
9421 assert (new_seg
!= 0);
9422 subseg_set (new_seg
, new_subseg
);
9424 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9425 subseg_set (seg
, subseg
);
9430 /* Relax a loop instruction so that it can span loop >256 bytes.
9436 addi as, as, lo8 (label-.L1)
9437 addmi as, as, mid8 (label-.L1)
9448 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9453 unsigned long target
;
9454 static xtensa_insnbuf insnbuf
= NULL
;
9455 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9456 xtensa_isa isa
= xtensa_default_isa
;
9457 addressT loop_offset
;
9458 addressT addi_offset
= 9;
9459 addressT addmi_offset
= 12;
9464 insnbuf
= xtensa_insnbuf_alloc (isa
);
9466 /* Get the loop offset. */
9467 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9469 /* Validate that there really is a LOOP at the loop_offset. Because
9470 loops are not bundleable, we can assume that the instruction will be
9472 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9473 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9475 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9476 addi_offset
+= loop_offset
;
9477 addmi_offset
+= loop_offset
;
9479 assert (tinsn
->ntok
== 2);
9480 if (tinsn
->tok
[1].X_op
== O_constant
)
9481 target
= tinsn
->tok
[1].X_add_number
;
9482 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9484 /* Find the fragment. */
9485 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9486 assert (S_GET_SEGMENT (sym
) == segP
9487 || S_GET_SEGMENT (sym
) == absolute_section
);
9488 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9492 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9497 know (symbolP
->sy_frag
);
9498 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9499 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9501 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9502 loop_length_hi
= loop_length
& ~0x0ff;
9503 loop_length_lo
= loop_length
& 0x0ff;
9504 if (loop_length_lo
>= 128)
9506 loop_length_lo
-= 256;
9507 loop_length_hi
+= 256;
9510 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9511 32512. If the loop is larger than that, then we just fail. */
9512 if (loop_length_hi
> 32512)
9513 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9514 _("loop too long for LOOP instruction"));
9516 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9517 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9519 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9520 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9522 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9523 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9525 fragP
->tc_frag_data
.is_insn
= TRUE
;
9526 xtensa_insnbuf_to_chars
9527 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9529 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9530 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9531 xtensa_insnbuf_to_chars
9532 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9534 /* Walk through all of the frags from here to the loop end
9535 and mark them as no_transform to keep them from being modified
9536 by the linker. If we ever have a relocation for the
9537 addi/addmi of the difference of two symbols we can remove this. */
9540 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9541 next_fragP
= next_fragP
->fr_next
)
9543 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9544 if (next_fragP
->tc_frag_data
.is_loop_target
)
9546 if (target_count
== 2)
9552 /* A map that keeps information on a per-subsegment basis. This is
9553 maintained during initial assembly, but is invalid once the
9554 subsegments are smashed together. I.E., it cannot be used during
9557 typedef struct subseg_map_struct
9565 float total_freq
; /* fall-through + branch target frequency */
9566 float target_freq
; /* branch target frequency alone */
9568 struct subseg_map_struct
*next
;
9572 static subseg_map
*sseg_map
= NULL
;
9575 get_subseg_info (segT seg
, subsegT subseg
)
9577 subseg_map
*subseg_e
;
9579 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9581 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9589 add_subseg_info (segT seg
, subsegT subseg
)
9591 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9592 memset (subseg_e
, 0, sizeof (subseg_map
));
9593 subseg_e
->seg
= seg
;
9594 subseg_e
->subseg
= subseg
;
9595 subseg_e
->flags
= 0;
9596 /* Start off considering every branch target very important. */
9597 subseg_e
->target_freq
= 1.0;
9598 subseg_e
->total_freq
= 1.0;
9599 subseg_e
->next
= sseg_map
;
9600 sseg_map
= subseg_e
;
9606 get_last_insn_flags (segT seg
, subsegT subseg
)
9608 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9610 return subseg_e
->flags
;
9616 set_last_insn_flags (segT seg
,
9621 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9623 subseg_e
= add_subseg_info (seg
, subseg
);
9625 subseg_e
->flags
|= fl
;
9627 subseg_e
->flags
&= ~fl
;
9632 get_subseg_total_freq (segT seg
, subsegT subseg
)
9634 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9636 return subseg_e
->total_freq
;
9642 get_subseg_target_freq (segT seg
, subsegT subseg
)
9644 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9646 return subseg_e
->target_freq
;
9652 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9654 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9656 subseg_e
= add_subseg_info (seg
, subseg
);
9657 subseg_e
->total_freq
= total_f
;
9658 subseg_e
->target_freq
= target_f
;
9662 /* Segment Lists and emit_state Stuff. */
9665 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9670 segT literal_section
= head
->seg
;
9672 /* Move the literal section to the front of the section list. */
9673 assert (literal_section
);
9674 if (literal_section
!= stdoutput
->sections
)
9676 bfd_section_list_remove (stdoutput
, literal_section
);
9677 bfd_section_list_prepend (stdoutput
, literal_section
);
9684 static void mark_literal_frags (seg_list
*);
9687 xtensa_move_literals (void)
9690 frchainS
*frchain_from
, *frchain_to
;
9691 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9692 fragS
**frag_splice
;
9695 fixS
*fix
, *next_fix
, **fix_splice
;
9698 mark_literal_frags (literal_head
->next
);
9699 mark_literal_frags (init_literal_head
->next
);
9700 mark_literal_frags (fini_literal_head
->next
);
9702 if (use_literal_section
)
9705 segment
= literal_head
->next
;
9708 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9709 search_frag
= frchain_from
->frch_root
;
9710 literal_pool
= NULL
;
9712 frag_splice
= &(frchain_from
->frch_root
);
9714 while (!search_frag
->tc_frag_data
.literal_frag
)
9716 assert (search_frag
->fr_fix
== 0
9717 || search_frag
->fr_type
== rs_align
);
9718 search_frag
= search_frag
->fr_next
;
9721 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9722 == RELAX_LITERAL_POOL_BEGIN
);
9723 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9725 /* Make sure that all the frags in this series are closed, and
9726 that there is at least one left over of zero-size. This
9727 prevents us from making a segment with an frchain without any
9729 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9730 xtensa_set_frag_assembly_state (frag_now
);
9731 last_frag
= frag_now
;
9732 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9733 xtensa_set_frag_assembly_state (frag_now
);
9735 while (search_frag
!= frag_now
)
9737 next_frag
= search_frag
->fr_next
;
9739 /* First, move the frag out of the literal section and
9740 to the appropriate place. */
9741 if (search_frag
->tc_frag_data
.literal_frag
)
9743 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9744 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9745 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9746 assert (frchain_to
);
9748 insert_after
= literal_pool
;
9750 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9751 insert_after
= insert_after
->fr_next
;
9753 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9755 *frag_splice
= next_frag
;
9756 search_frag
->fr_next
= insert_after
->fr_next
;
9757 insert_after
->fr_next
= search_frag
;
9758 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9760 /* Now move any fixups associated with this frag to the
9762 fix
= frchain_from
->fix_root
;
9763 fix_splice
= &(frchain_from
->fix_root
);
9766 next_fix
= fix
->fx_next
;
9767 if (fix
->fx_frag
== search_frag
)
9769 *fix_splice
= next_fix
;
9770 fix
->fx_next
= frchain_to
->fix_root
;
9771 frchain_to
->fix_root
= fix
;
9772 if (frchain_to
->fix_tail
== NULL
)
9773 frchain_to
->fix_tail
= fix
;
9776 fix_splice
= &(fix
->fx_next
);
9779 search_frag
= next_frag
;
9782 if (frchain_from
->fix_root
!= NULL
)
9784 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9785 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9787 assert (frchain_from
->fix_root
== NULL
);
9789 frchain_from
->fix_tail
= NULL
;
9790 xtensa_restore_emit_state (&state
);
9791 segment
= segment
->next
;
9794 /* Now fix up the SEGMENT value for all the literal symbols. */
9795 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9797 symbolS
*lit_sym
= lit
->sym
;
9798 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9800 S_SET_SEGMENT (lit_sym
, dest_seg
);
9805 /* Walk over all the frags for segments in a list and mark them as
9806 containing literals. As clunky as this is, we can't rely on frag_var
9807 and frag_variant to get called in all situations. */
9810 mark_literal_frags (seg_list
*segment
)
9812 frchainS
*frchain_from
;
9817 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9818 search_frag
= frchain_from
->frch_root
;
9821 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9822 search_frag
= search_frag
->fr_next
;
9824 segment
= segment
->next
;
9830 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9832 /* Move all of the sections in the section list to come
9833 after "after" in the gnu segment list. */
9838 segT literal_section
= head
->seg
;
9840 /* Move the literal section after "after". */
9841 assert (literal_section
);
9842 if (literal_section
!= after
)
9844 bfd_section_list_remove (stdoutput
, literal_section
);
9845 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9853 /* Push all the literal segments to the end of the gnu list. */
9856 xtensa_reorder_segments (void)
9863 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9869 /* Now that we have the last section, push all the literal
9870 sections to the end. */
9871 xtensa_reorder_seg_list (literal_head
, last_sec
);
9872 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9873 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9875 /* Now perform the final error check. */
9876 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9878 assert (new_count
== old_count
);
9882 /* Change the emit state (seg, subseg, and frag related stuff) to the
9883 correct location. Return a emit_state which can be passed to
9884 xtensa_restore_emit_state to return to current fragment. */
9887 xtensa_switch_to_literal_fragment (emit_state
*result
)
9889 if (directive_state
[directive_absolute_literals
])
9891 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9892 &default_lit_sections
.lit4_seg
, FALSE
);
9893 xtensa_switch_section_emit_state (result
,
9894 default_lit_sections
.lit4_seg
, 0);
9897 xtensa_switch_to_non_abs_literal_fragment (result
);
9899 /* Do a 4-byte align here. */
9900 frag_align (2, 0, 0);
9901 record_alignment (now_seg
, 2);
9906 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9908 /* When we mark a literal pool location, we want to put a frag in
9909 the literal pool that points to it. But to do that, we want to
9910 switch_to_literal_fragment. But literal sections don't have
9911 literal pools, so their location is always null, so we would
9912 recurse forever. This is kind of hacky, but it works. */
9914 static bfd_boolean recursive
= FALSE
;
9915 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9916 bfd_boolean is_init
=
9917 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9919 bfd_boolean is_fini
=
9920 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9922 if (pool_location
== NULL
9923 && !use_literal_section
9925 && !is_init
&& ! is_fini
)
9927 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9929 xtensa_mark_literal_pool_location ();
9933 /* Special case: If we are in the ".fini" or ".init" section, then
9934 we will ALWAYS be generating to the ".fini.literal" and
9935 ".init.literal" sections. */
9939 cache_literal_section (init_literal_head
,
9940 default_lit_sections
.init_lit_seg_name
,
9941 &default_lit_sections
.init_lit_seg
, TRUE
);
9942 xtensa_switch_section_emit_state (result
,
9943 default_lit_sections
.init_lit_seg
, 0);
9947 cache_literal_section (fini_literal_head
,
9948 default_lit_sections
.fini_lit_seg_name
,
9949 &default_lit_sections
.fini_lit_seg
, TRUE
);
9950 xtensa_switch_section_emit_state (result
,
9951 default_lit_sections
.fini_lit_seg
, 0);
9955 cache_literal_section (literal_head
,
9956 default_lit_sections
.lit_seg_name
,
9957 &default_lit_sections
.lit_seg
, TRUE
);
9958 xtensa_switch_section_emit_state (result
,
9959 default_lit_sections
.lit_seg
, 0);
9962 if (!use_literal_section
9963 && !is_init
&& !is_fini
9964 && get_literal_pool_location (now_seg
) != pool_location
)
9966 /* Close whatever frag is there. */
9967 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9968 xtensa_set_frag_assembly_state (frag_now
);
9969 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9970 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9971 xtensa_set_frag_assembly_state (frag_now
);
9976 /* Call this function before emitting data into the literal section.
9977 This is a helper function for xtensa_switch_to_literal_fragment.
9978 This is similar to a .section new_now_seg subseg. */
9981 xtensa_switch_section_emit_state (emit_state
*state
,
9983 subsegT new_now_subseg
)
9985 state
->name
= now_seg
->name
;
9986 state
->now_seg
= now_seg
;
9987 state
->now_subseg
= now_subseg
;
9988 state
->generating_literals
= generating_literals
;
9989 generating_literals
++;
9990 subseg_set (new_now_seg
, new_now_subseg
);
9994 /* Use to restore the emitting into the normal place. */
9997 xtensa_restore_emit_state (emit_state
*state
)
9999 generating_literals
= state
->generating_literals
;
10000 subseg_set (state
->now_seg
, state
->now_subseg
);
10004 /* Get a segment of a given name. If the segment is already
10005 present, return it; otherwise, create a new one. */
10008 cache_literal_section (seg_list
*head
,
10011 bfd_boolean is_code
)
10013 segT current_section
= now_seg
;
10014 int current_subsec
= now_subseg
;
10020 /* Check if the named section exists. */
10021 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10023 if (!strcmp (segment_name (seg
), name
))
10029 /* Create a new literal section. */
10030 seg
= subseg_new (name
, (subsegT
) 0);
10033 /* Add the newly created literal segment to the specified list. */
10034 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10036 n
->next
= head
->next
;
10039 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10040 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10041 | (is_code
? SEC_CODE
: SEC_DATA
));
10042 bfd_set_section_alignment (stdoutput
, seg
, 2);
10046 subseg_set (current_section
, current_subsec
);
10050 /* Property Tables Stuff. */
10052 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10053 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10054 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10056 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10057 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10059 static bfd_boolean
get_frag_is_literal (const fragS
*);
10060 static void xtensa_create_property_segments
10061 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10062 static void xtensa_create_xproperty_segments
10063 (frag_flags_fn
, const char *, xt_section_type
);
10064 static segment_info_type
*retrieve_segment_info (segT
);
10065 static segT
retrieve_xtensa_section (char *);
10066 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10067 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10068 static void add_xt_block_frags
10069 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10070 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10071 static void xtensa_frag_flags_init (frag_flags
*);
10072 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10073 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10074 static void add_xt_prop_frags
10075 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10077 /* Set up property tables after relaxation. */
10080 xtensa_post_relax_hook (void)
10082 xtensa_move_seg_list_to_beginning (literal_head
);
10083 xtensa_move_seg_list_to_beginning (init_literal_head
);
10084 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10086 xtensa_find_unmarked_state_frags ();
10088 xtensa_create_property_segments (get_frag_is_literal
,
10090 XTENSA_LIT_SEC_NAME
,
10092 xtensa_create_xproperty_segments (get_frag_property_flags
,
10093 XTENSA_PROP_SEC_NAME
,
10096 if (warn_unaligned_branch_targets
)
10097 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10098 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10102 /* This function is only meaningful after xtensa_move_literals. */
10105 get_frag_is_literal (const fragS
*fragP
)
10107 assert (fragP
!= NULL
);
10108 return fragP
->tc_frag_data
.is_literal
;
10113 xtensa_create_property_segments (frag_predicate property_function
,
10114 frag_predicate end_property_function
,
10115 const char *section_name_base
,
10116 xt_section_type sec_type
)
10120 /* Walk over all of the current segments.
10121 Walk over each fragment
10122 For each non-empty fragment,
10123 Build a property record (append where possible). */
10125 for (seclist
= &stdoutput
->sections
;
10126 seclist
&& *seclist
;
10127 seclist
= &(*seclist
)->next
)
10129 segT sec
= *seclist
;
10132 flags
= bfd_get_section_flags (stdoutput
, sec
);
10133 if (flags
& SEC_DEBUGGING
)
10135 if (!(flags
& SEC_ALLOC
))
10138 if (section_has_property (sec
, property_function
))
10140 char *property_section_name
=
10141 xtensa_get_property_section_name (sec
, section_name_base
);
10142 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10143 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10144 xtensa_block_info
**xt_blocks
=
10145 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10146 /* Walk over all of the frchains here and add new sections. */
10147 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10148 end_property_function
);
10152 /* Now we fill them out.... */
10154 for (seclist
= &stdoutput
->sections
;
10155 seclist
&& *seclist
;
10156 seclist
= &(*seclist
)->next
)
10158 segment_info_type
*seginfo
;
10159 xtensa_block_info
*block
;
10160 segT sec
= *seclist
;
10162 seginfo
= seg_info (sec
);
10163 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10167 xtensa_block_info
*cur_block
;
10168 /* This is a section with some data. */
10170 bfd_size_type rec_size
;
10172 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10175 rec_size
= num_recs
* 8;
10176 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10178 /* In order to make this work with the assembler, we have to
10179 build some frags and then build the "fixups" for it. It
10180 would be easier to just set the contents then set the
10185 /* Allocate a fragment and leak it. */
10187 bfd_size_type frag_size
;
10189 frchainS
*frchainP
;
10193 frag_size
= sizeof (fragS
) + rec_size
;
10194 fragP
= (fragS
*) xmalloc (frag_size
);
10196 memset (fragP
, 0, frag_size
);
10197 fragP
->fr_address
= 0;
10198 fragP
->fr_next
= NULL
;
10199 fragP
->fr_fix
= rec_size
;
10201 fragP
->fr_type
= rs_fill
;
10202 /* The rest are zeros. */
10204 frchainP
= seginfo
->frchainP
;
10205 frchainP
->frch_root
= fragP
;
10206 frchainP
->frch_last
= fragP
;
10208 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10209 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10211 seginfo
->fix_root
= fixes
;
10212 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10214 frag_data
= &fragP
->fr_literal
[0];
10215 for (i
= 0; i
< num_recs
; i
++)
10217 fixS
*fix
= &fixes
[i
];
10218 assert (cur_block
);
10220 /* Write the fixup. */
10221 if (i
!= num_recs
- 1)
10222 fix
->fx_next
= &fixes
[i
+ 1];
10224 fix
->fx_next
= NULL
;
10227 fix
->fx_frag
= fragP
;
10228 fix
->fx_where
= i
* 8;
10229 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10230 fix
->fx_offset
= cur_block
->offset
;
10231 fix
->fx_r_type
= BFD_RELOC_32
;
10232 fix
->fx_file
= "Internal Assembly";
10235 /* Write the length. */
10236 md_number_to_chars (&frag_data
[4 + 8 * i
],
10237 cur_block
->size
, 4);
10238 cur_block
= cur_block
->next
;
10247 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10248 const char *section_name_base
,
10249 xt_section_type sec_type
)
10253 /* Walk over all of the current segments.
10254 Walk over each fragment.
10255 For each fragment that has instructions,
10256 build an instruction record (append where possible). */
10258 for (seclist
= &stdoutput
->sections
;
10259 seclist
&& *seclist
;
10260 seclist
= &(*seclist
)->next
)
10262 segT sec
= *seclist
;
10265 flags
= bfd_get_section_flags (stdoutput
, sec
);
10266 if ((flags
& SEC_DEBUGGING
)
10267 || !(flags
& SEC_ALLOC
)
10268 || (flags
& SEC_MERGE
))
10271 if (section_has_xproperty (sec
, flag_fn
))
10273 char *property_section_name
=
10274 xtensa_get_property_section_name (sec
, section_name_base
);
10275 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10276 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10277 xtensa_block_info
**xt_blocks
=
10278 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10279 /* Walk over all of the frchains here and add new sections. */
10280 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10284 /* Now we fill them out.... */
10286 for (seclist
= &stdoutput
->sections
;
10287 seclist
&& *seclist
;
10288 seclist
= &(*seclist
)->next
)
10290 segment_info_type
*seginfo
;
10291 xtensa_block_info
*block
;
10292 segT sec
= *seclist
;
10294 seginfo
= seg_info (sec
);
10295 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10299 xtensa_block_info
*cur_block
;
10300 /* This is a section with some data. */
10302 bfd_size_type rec_size
;
10304 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10307 rec_size
= num_recs
* (8 + 4);
10308 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10310 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10312 /* In order to make this work with the assembler, we have to build
10313 some frags then build the "fixups" for it. It would be easier to
10314 just set the contents then set the arlents. */
10318 /* Allocate a fragment and (unfortunately) leak it. */
10320 bfd_size_type frag_size
;
10322 frchainS
*frchainP
;
10326 frag_size
= sizeof (fragS
) + rec_size
;
10327 fragP
= (fragS
*) xmalloc (frag_size
);
10329 memset (fragP
, 0, frag_size
);
10330 fragP
->fr_address
= 0;
10331 fragP
->fr_next
= NULL
;
10332 fragP
->fr_fix
= rec_size
;
10334 fragP
->fr_type
= rs_fill
;
10335 /* The rest are zeros. */
10337 frchainP
= seginfo
->frchainP
;
10338 frchainP
->frch_root
= fragP
;
10339 frchainP
->frch_last
= fragP
;
10341 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10342 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10344 seginfo
->fix_root
= fixes
;
10345 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10347 frag_data
= &fragP
->fr_literal
[0];
10348 for (i
= 0; i
< num_recs
; i
++)
10350 fixS
*fix
= &fixes
[i
];
10351 assert (cur_block
);
10353 /* Write the fixup. */
10354 if (i
!= num_recs
- 1)
10355 fix
->fx_next
= &fixes
[i
+ 1];
10357 fix
->fx_next
= NULL
;
10360 fix
->fx_frag
= fragP
;
10361 fix
->fx_where
= i
* (8 + 4);
10362 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10363 fix
->fx_offset
= cur_block
->offset
;
10364 fix
->fx_r_type
= BFD_RELOC_32
;
10365 fix
->fx_file
= "Internal Assembly";
10368 /* Write the length. */
10369 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10370 cur_block
->size
, 4);
10371 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10372 frag_flags_to_number (&cur_block
->flags
),
10374 cur_block
= cur_block
->next
;
10382 static segment_info_type
*
10383 retrieve_segment_info (segT seg
)
10385 segment_info_type
*seginfo
;
10386 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10389 frchainS
*frchainP
;
10391 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10392 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10393 seginfo
->fix_root
= NULL
;
10394 seginfo
->fix_tail
= NULL
;
10395 seginfo
->bfd_section
= seg
;
10397 /* We will not be dealing with these, only our special ones. */
10398 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10400 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10401 frchainP
->frch_root
= NULL
;
10402 frchainP
->frch_last
= NULL
;
10403 frchainP
->frch_next
= NULL
;
10404 frchainP
->frch_subseg
= 0;
10405 frchainP
->fix_root
= NULL
;
10406 frchainP
->fix_tail
= NULL
;
10407 /* Do not init the objstack. */
10408 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10409 /* frchainP->frch_frag_now = fragP; */
10410 frchainP
->frch_frag_now
= NULL
;
10412 seginfo
->frchainP
= frchainP
;
10420 retrieve_xtensa_section (char *sec_name
)
10422 bfd
*abfd
= stdoutput
;
10423 flagword flags
, out_flags
, link_once_flags
;
10426 flags
= bfd_get_section_flags (abfd
, now_seg
);
10427 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10428 if (link_once_flags
)
10429 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10430 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10432 s
= bfd_make_section_old_way (abfd
, sec_name
);
10434 as_bad (_("could not create section %s"), sec_name
);
10435 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10436 as_bad (_("invalid flag combination on section %s"), sec_name
);
10443 section_has_property (segT sec
, frag_predicate property_function
)
10445 segment_info_type
*seginfo
= seg_info (sec
);
10448 if (seginfo
&& seginfo
->frchainP
)
10450 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10452 if (property_function (fragP
)
10453 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10462 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10464 segment_info_type
*seginfo
= seg_info (sec
);
10467 if (seginfo
&& seginfo
->frchainP
)
10469 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10471 frag_flags prop_flags
;
10472 property_function (fragP
, &prop_flags
);
10473 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10481 /* Two types of block sections exist right now: literal and insns. */
10484 add_xt_block_frags (segT sec
,
10486 xtensa_block_info
**xt_block
,
10487 frag_predicate property_function
,
10488 frag_predicate end_property_function
)
10490 segment_info_type
*seg_info
;
10491 segment_info_type
*xt_seg_info
;
10492 bfd_vma seg_offset
;
10495 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10496 seg_info
= retrieve_segment_info (sec
);
10498 /* Build it if needed. */
10499 while (*xt_block
!= NULL
)
10500 xt_block
= &(*xt_block
)->next
;
10501 /* We are either at NULL at the beginning or at the end. */
10503 /* Walk through the frags. */
10506 if (seg_info
->frchainP
)
10508 for (fragP
= seg_info
->frchainP
->frch_root
;
10510 fragP
= fragP
->fr_next
)
10512 if (property_function (fragP
)
10513 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10515 if (*xt_block
!= NULL
)
10517 if ((*xt_block
)->offset
+ (*xt_block
)->size
10518 == fragP
->fr_address
)
10519 (*xt_block
)->size
+= fragP
->fr_fix
;
10521 xt_block
= &((*xt_block
)->next
);
10523 if (*xt_block
== NULL
)
10525 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10526 xmalloc (sizeof (xtensa_block_info
));
10527 new_block
->sec
= sec
;
10528 new_block
->offset
= fragP
->fr_address
;
10529 new_block
->size
= fragP
->fr_fix
;
10530 new_block
->next
= NULL
;
10531 xtensa_frag_flags_init (&new_block
->flags
);
10532 *xt_block
= new_block
;
10534 if (end_property_function
10535 && end_property_function (fragP
))
10537 xt_block
= &((*xt_block
)->next
);
10545 /* Break the encapsulation of add_xt_prop_frags here. */
10548 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10550 if (prop_flags
->is_literal
10551 || prop_flags
->is_insn
10552 || prop_flags
->is_data
10553 || prop_flags
->is_unreachable
)
10560 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10562 memset (prop_flags
, 0, sizeof (frag_flags
));
10567 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10569 xtensa_frag_flags_init (prop_flags
);
10570 if (fragP
->tc_frag_data
.is_literal
)
10571 prop_flags
->is_literal
= TRUE
;
10572 if (fragP
->tc_frag_data
.is_unreachable
)
10573 prop_flags
->is_unreachable
= TRUE
;
10574 else if (fragP
->tc_frag_data
.is_insn
)
10576 prop_flags
->is_insn
= TRUE
;
10577 if (fragP
->tc_frag_data
.is_loop_target
)
10578 prop_flags
->insn
.is_loop_target
= TRUE
;
10579 if (fragP
->tc_frag_data
.is_branch_target
)
10580 prop_flags
->insn
.is_branch_target
= TRUE
;
10581 if (fragP
->tc_frag_data
.is_specific_opcode
10582 || fragP
->tc_frag_data
.is_no_transform
)
10583 prop_flags
->insn
.is_no_transform
= TRUE
;
10584 if (fragP
->tc_frag_data
.is_no_density
)
10585 prop_flags
->insn
.is_no_density
= TRUE
;
10586 if (fragP
->tc_frag_data
.use_absolute_literals
)
10587 prop_flags
->insn
.is_abslit
= TRUE
;
10589 if (fragP
->tc_frag_data
.is_align
)
10591 prop_flags
->is_align
= TRUE
;
10592 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10593 if (xtensa_frag_flags_is_empty (prop_flags
))
10594 prop_flags
->is_data
= TRUE
;
10600 frag_flags_to_number (const frag_flags
*prop_flags
)
10603 if (prop_flags
->is_literal
)
10604 num
|= XTENSA_PROP_LITERAL
;
10605 if (prop_flags
->is_insn
)
10606 num
|= XTENSA_PROP_INSN
;
10607 if (prop_flags
->is_data
)
10608 num
|= XTENSA_PROP_DATA
;
10609 if (prop_flags
->is_unreachable
)
10610 num
|= XTENSA_PROP_UNREACHABLE
;
10611 if (prop_flags
->insn
.is_loop_target
)
10612 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10613 if (prop_flags
->insn
.is_branch_target
)
10615 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10616 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10619 if (prop_flags
->insn
.is_no_density
)
10620 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10621 if (prop_flags
->insn
.is_no_transform
)
10622 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10623 if (prop_flags
->insn
.is_no_reorder
)
10624 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10625 if (prop_flags
->insn
.is_abslit
)
10626 num
|= XTENSA_PROP_INSN_ABSLIT
;
10628 if (prop_flags
->is_align
)
10630 num
|= XTENSA_PROP_ALIGN
;
10631 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10639 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10640 const frag_flags
*prop_flags_2
)
10642 /* Cannot combine with an end marker. */
10644 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10646 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10648 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10651 if (prop_flags_1
->is_insn
)
10653 /* Properties of the beginning of the frag. */
10654 if (prop_flags_2
->insn
.is_loop_target
)
10656 if (prop_flags_2
->insn
.is_branch_target
)
10658 if (prop_flags_1
->insn
.is_no_density
!=
10659 prop_flags_2
->insn
.is_no_density
)
10661 if (prop_flags_1
->insn
.is_no_transform
!=
10662 prop_flags_2
->insn
.is_no_transform
)
10664 if (prop_flags_1
->insn
.is_no_reorder
!=
10665 prop_flags_2
->insn
.is_no_reorder
)
10667 if (prop_flags_1
->insn
.is_abslit
!=
10668 prop_flags_2
->insn
.is_abslit
)
10672 if (prop_flags_1
->is_align
)
10680 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10683 unsigned align_bits
;
10685 if (!xt_block
->flags
.is_align
)
10686 return xt_block
->size
;
10688 end_addr
= xt_block
->offset
+ xt_block
->size
;
10689 align_bits
= xt_block
->flags
.alignment
;
10690 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10691 return end_addr
- xt_block
->offset
;
10696 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10697 const xtensa_block_info
*xt_block_2
)
10699 if (xt_block
->sec
!= xt_block_2
->sec
)
10701 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10702 != xt_block_2
->offset
)
10705 if (xt_block_2
->size
== 0
10706 && (!xt_block_2
->flags
.is_unreachable
10707 || xt_block
->flags
.is_unreachable
))
10709 if (xt_block_2
->flags
.is_align
10710 && xt_block
->flags
.is_align
)
10712 /* Nothing needed. */
10713 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10718 if (xt_block_2
->flags
.is_align
)
10720 /* Push alignment to previous entry. */
10721 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10722 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10727 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10728 &xt_block_2
->flags
))
10731 xt_block
->size
+= xt_block_2
->size
;
10733 if (xt_block_2
->flags
.is_align
)
10735 xt_block
->flags
.is_align
= TRUE
;
10736 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10744 add_xt_prop_frags (segT sec
,
10746 xtensa_block_info
**xt_block
,
10747 frag_flags_fn property_function
)
10749 segment_info_type
*seg_info
;
10750 segment_info_type
*xt_seg_info
;
10751 bfd_vma seg_offset
;
10754 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10755 seg_info
= retrieve_segment_info (sec
);
10756 /* Build it if needed. */
10757 while (*xt_block
!= NULL
)
10759 xt_block
= &(*xt_block
)->next
;
10761 /* We are either at NULL at the beginning or at the end. */
10763 /* Walk through the frags. */
10766 if (seg_info
->frchainP
)
10768 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10769 fragP
= fragP
->fr_next
)
10771 xtensa_block_info tmp_block
;
10772 tmp_block
.sec
= sec
;
10773 tmp_block
.offset
= fragP
->fr_address
;
10774 tmp_block
.size
= fragP
->fr_fix
;
10775 tmp_block
.next
= NULL
;
10776 property_function (fragP
, &tmp_block
.flags
);
10778 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10779 /* && fragP->fr_fix != 0) */
10781 if ((*xt_block
) == NULL
10782 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10784 xtensa_block_info
*new_block
;
10785 if ((*xt_block
) != NULL
)
10786 xt_block
= &(*xt_block
)->next
;
10787 new_block
= (xtensa_block_info
*)
10788 xmalloc (sizeof (xtensa_block_info
));
10789 *new_block
= tmp_block
;
10790 *xt_block
= new_block
;
10798 /* op_placement_info_table */
10800 /* op_placement_info makes it easier to determine which
10801 ops can go in which slots. */
10804 init_op_placement_info_table (void)
10806 xtensa_isa isa
= xtensa_default_isa
;
10807 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10808 xtensa_opcode opcode
;
10811 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10813 op_placement_table
= (op_placement_info_table
)
10814 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10815 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10817 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10819 op_placement_info
*opi
= &op_placement_table
[opcode
];
10820 /* FIXME: Make tinsn allocation dynamic. */
10821 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10822 as_fatal (_("too many operands in instruction"));
10823 opi
->narrowest
= XTENSA_UNDEFINED
;
10824 opi
->narrowest_size
= 0x7F;
10825 opi
->narrowest_slot
= 0;
10827 opi
->num_formats
= 0;
10829 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10831 opi
->slots
[fmt
] = 0;
10832 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10834 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10836 int fmt_length
= xtensa_format_length (isa
, fmt
);
10838 set_bit (fmt
, opi
->formats
);
10839 set_bit (slot
, opi
->slots
[fmt
]);
10840 if (fmt_length
< opi
->narrowest_size
10841 || (fmt_length
== opi
->narrowest_size
10842 && (xtensa_format_num_slots (isa
, fmt
)
10843 < xtensa_format_num_slots (isa
,
10846 opi
->narrowest
= fmt
;
10847 opi
->narrowest_size
= fmt_length
;
10848 opi
->narrowest_slot
= slot
;
10853 opi
->num_formats
++;
10856 xtensa_insnbuf_free (isa
, ibuf
);
10861 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10863 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10867 /* If the opcode is available in a single slot format, return its size. */
10870 xg_get_single_size (xtensa_opcode opcode
)
10872 return op_placement_table
[opcode
].narrowest_size
;
10876 static xtensa_format
10877 xg_get_single_format (xtensa_opcode opcode
)
10879 return op_placement_table
[opcode
].narrowest
;
10884 xg_get_single_slot (xtensa_opcode opcode
)
10886 return op_placement_table
[opcode
].narrowest_slot
;
10890 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10893 istack_init (IStack
*stack
)
10895 memset (stack
, 0, sizeof (IStack
));
10901 istack_empty (IStack
*stack
)
10903 return (stack
->ninsn
== 0);
10908 istack_full (IStack
*stack
)
10910 return (stack
->ninsn
== MAX_ISTACK
);
10914 /* Return a pointer to the top IStack entry.
10915 It is an error to call this if istack_empty () is TRUE. */
10918 istack_top (IStack
*stack
)
10920 int rec
= stack
->ninsn
- 1;
10921 assert (!istack_empty (stack
));
10922 return &stack
->insn
[rec
];
10926 /* Add a new TInsn to an IStack.
10927 It is an error to call this if istack_full () is TRUE. */
10930 istack_push (IStack
*stack
, TInsn
*insn
)
10932 int rec
= stack
->ninsn
;
10933 assert (!istack_full (stack
));
10934 stack
->insn
[rec
] = *insn
;
10939 /* Clear space for the next TInsn on the IStack and return a pointer
10940 to it. It is an error to call this if istack_full () is TRUE. */
10943 istack_push_space (IStack
*stack
)
10945 int rec
= stack
->ninsn
;
10947 assert (!istack_full (stack
));
10948 insn
= &stack
->insn
[rec
];
10949 memset (insn
, 0, sizeof (TInsn
));
10955 /* Remove the last pushed instruction. It is an error to call this if
10956 istack_empty () returns TRUE. */
10959 istack_pop (IStack
*stack
)
10961 int rec
= stack
->ninsn
- 1;
10962 assert (!istack_empty (stack
));
10964 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10968 /* TInsn functions. */
10971 tinsn_init (TInsn
*dst
)
10973 memset (dst
, 0, sizeof (TInsn
));
10977 /* Get the ``num''th token of the TInsn.
10978 It is illegal to call this if num > insn->ntoks. */
10981 tinsn_get_tok (TInsn
*insn
, int num
)
10983 assert (num
< insn
->ntok
);
10984 return &insn
->tok
[num
];
10988 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10991 tinsn_has_symbolic_operands (const TInsn
*insn
)
10994 int n
= insn
->ntok
;
10996 assert (insn
->insn_type
== ITYPE_INSN
);
10998 for (i
= 0; i
< n
; ++i
)
11000 switch (insn
->tok
[i
].X_op
)
11014 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11016 xtensa_isa isa
= xtensa_default_isa
;
11018 int n
= insn
->ntok
;
11020 assert (insn
->insn_type
== ITYPE_INSN
);
11022 for (i
= 0; i
< n
; ++i
)
11024 switch (insn
->tok
[i
].X_op
)
11032 /* Errors for these types are caught later. */
11037 /* Symbolic immediates are only allowed on the last immediate
11038 operand. At this time, CONST16 is the only opcode where we
11039 support non-PC-relative relocations. */
11040 if (i
!= get_relaxable_immed (insn
->opcode
)
11041 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11042 && insn
->opcode
!= xtensa_const16_opcode
))
11044 as_bad (_("invalid symbolic operand"));
11053 /* For assembly code with complex expressions (e.g. subtraction),
11054 we have to build them in the literal pool so that
11055 their results are calculated correctly after relaxation.
11056 The relaxation only handles expressions that
11057 boil down to SYMBOL + OFFSET. */
11060 tinsn_has_complex_operands (const TInsn
*insn
)
11063 int n
= insn
->ntok
;
11064 assert (insn
->insn_type
== ITYPE_INSN
);
11065 for (i
= 0; i
< n
; ++i
)
11067 switch (insn
->tok
[i
].X_op
)
11083 /* Encode a TInsn opcode and its constant operands into slotbuf.
11084 Return TRUE if there is a symbol in the immediate field. This
11085 function assumes that:
11086 1) The number of operands are correct.
11087 2) The insn_type is ITYPE_INSN.
11088 3) The opcode can be encoded in the specified format and slot.
11089 4) Operands are either O_constant or O_symbol, and all constants fit. */
11092 tinsn_to_slotbuf (xtensa_format fmt
,
11095 xtensa_insnbuf slotbuf
)
11097 xtensa_isa isa
= xtensa_default_isa
;
11098 xtensa_opcode opcode
= tinsn
->opcode
;
11099 bfd_boolean has_fixup
= FALSE
;
11100 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11103 assert (tinsn
->insn_type
== ITYPE_INSN
);
11104 if (noperands
!= tinsn
->ntok
)
11105 as_fatal (_("operand number mismatch"));
11107 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11109 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11110 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11114 for (i
= 0; i
< noperands
; i
++)
11116 expressionS
*expr
= &tinsn
->tok
[i
];
11122 switch (expr
->X_op
)
11125 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11127 /* The register number has already been checked in
11128 expression_maybe_register, so we don't need to check here. */
11129 opnd_value
= expr
->X_add_number
;
11130 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11131 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11134 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11138 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11140 as_where (&file_name
, &line
);
11141 /* It is a constant and we called this function
11142 then we have to try to fit it. */
11143 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11144 expr
->X_add_number
, file_name
, line
);
11157 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11158 into a multi-slot instruction, fill the other slots with NOPs.
11159 Return TRUE if there is a symbol in the immediate field. See also the
11160 assumptions listed for tinsn_to_slotbuf. */
11163 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11165 static xtensa_insnbuf slotbuf
= 0;
11166 static vliw_insn vinsn
;
11167 xtensa_isa isa
= xtensa_default_isa
;
11168 bfd_boolean has_fixup
= FALSE
;
11173 slotbuf
= xtensa_insnbuf_alloc (isa
);
11174 xg_init_vinsn (&vinsn
);
11177 xg_clear_vinsn (&vinsn
);
11179 bundle_tinsn (tinsn
, &vinsn
);
11181 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11183 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11185 /* Only one slot may have a fix-up because the rest contains NOPs. */
11187 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11188 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11195 /* Check the instruction arguments. Return TRUE on failure. */
11198 tinsn_check_arguments (const TInsn
*insn
)
11200 xtensa_isa isa
= xtensa_default_isa
;
11201 xtensa_opcode opcode
= insn
->opcode
;
11203 if (opcode
== XTENSA_UNDEFINED
)
11205 as_bad (_("invalid opcode"));
11209 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11211 as_bad (_("too few operands"));
11215 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11217 as_bad (_("too many operands"));
11224 /* Load an instruction from its encoded form. */
11227 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11231 xg_init_vinsn (&vinsn
);
11232 vinsn_from_chars (&vinsn
, f
);
11234 *tinsn
= vinsn
.slots
[slot
];
11235 xg_free_vinsn (&vinsn
);
11240 tinsn_from_insnbuf (TInsn
*tinsn
,
11241 xtensa_insnbuf slotbuf
,
11246 xtensa_isa isa
= xtensa_default_isa
;
11248 /* Find the immed. */
11249 tinsn_init (tinsn
);
11250 tinsn
->insn_type
= ITYPE_INSN
;
11251 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11252 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11253 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11254 for (i
= 0; i
< tinsn
->ntok
; i
++)
11256 set_expr_const (&tinsn
->tok
[i
],
11257 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11258 tinsn
->opcode
, i
));
11263 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11266 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11268 xtensa_opcode opcode
= tinsn
->opcode
;
11271 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11273 opnum
= get_relaxable_immed (opcode
);
11274 assert (opnum
>= 0);
11275 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11276 fragP
->tc_frag_data
.slot_symbols
[slot
],
11277 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11283 get_num_stack_text_bytes (IStack
*istack
)
11286 int text_bytes
= 0;
11288 for (i
= 0; i
< istack
->ninsn
; i
++)
11290 TInsn
*tinsn
= &istack
->insn
[i
];
11291 if (tinsn
->insn_type
== ITYPE_INSN
)
11292 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11299 get_num_stack_literal_bytes (IStack
*istack
)
11304 for (i
= 0; i
< istack
->ninsn
; i
++)
11306 TInsn
*tinsn
= &istack
->insn
[i
];
11307 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11314 /* vliw_insn functions. */
11317 xg_init_vinsn (vliw_insn
*v
)
11320 xtensa_isa isa
= xtensa_default_isa
;
11322 xg_clear_vinsn (v
);
11324 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11325 if (v
->insnbuf
== NULL
)
11326 as_fatal (_("out of memory"));
11328 for (i
= 0; i
< MAX_SLOTS
; i
++)
11330 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11331 if (v
->slotbuf
[i
] == NULL
)
11332 as_fatal (_("out of memory"));
11338 xg_clear_vinsn (vliw_insn
*v
)
11342 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11344 v
->format
= XTENSA_UNDEFINED
;
11346 v
->inside_bundle
= FALSE
;
11348 if (xt_saved_debug_type
!= DEBUG_NONE
)
11349 debug_type
= xt_saved_debug_type
;
11351 for (i
= 0; i
< MAX_SLOTS
; i
++)
11352 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11357 vinsn_has_specific_opcodes (vliw_insn
*v
)
11361 for (i
= 0; i
< v
->num_slots
; i
++)
11363 if (v
->slots
[i
].is_specific_opcode
)
11371 xg_free_vinsn (vliw_insn
*v
)
11374 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11375 for (i
= 0; i
< MAX_SLOTS
; i
++)
11376 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11380 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11381 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11384 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11387 bfd_boolean record_fixup
)
11389 xtensa_isa isa
= xtensa_default_isa
;
11390 xtensa_format fmt
= vinsn
->format
;
11391 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11393 bfd_boolean has_fixup
= FALSE
;
11395 xtensa_format_encode (isa
, fmt
, insnbuf
);
11397 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11399 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11400 bfd_boolean tinsn_has_fixup
=
11401 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11402 vinsn
->slotbuf
[slot
]);
11404 xtensa_format_set_slot (isa
, fmt
, slot
,
11405 insnbuf
, vinsn
->slotbuf
[slot
]);
11406 if (tinsn_has_fixup
)
11409 xtensa_opcode opcode
= tinsn
->opcode
;
11410 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11413 for (i
= 0; i
< noperands
; i
++)
11415 expressionS
* expr
= &tinsn
->tok
[i
];
11416 switch (expr
->X_op
)
11421 if (get_relaxable_immed (opcode
) == i
)
11423 /* Add a fix record for the instruction, except if this
11424 function is being called prior to relaxation, i.e.,
11425 if record_fixup is false, and the instruction might
11426 be relaxed later. */
11428 || tinsn
->is_specific_opcode
11429 || !xg_is_relaxable_insn (tinsn
, 0))
11431 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11432 frag_offset
- fragP
->fr_literal
);
11436 if (expr
->X_op
!= O_symbol
)
11437 as_bad (_("invalid operand"));
11438 tinsn
->symbol
= expr
->X_add_symbol
;
11439 tinsn
->offset
= expr
->X_add_number
;
11443 as_bad (_("symbolic operand not allowed"));
11451 as_bad (_("expression too complex"));
11463 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11465 static xtensa_insnbuf insnbuf
= NULL
;
11466 static xtensa_insnbuf slotbuf
= NULL
;
11469 xtensa_isa isa
= xtensa_default_isa
;
11473 insnbuf
= xtensa_insnbuf_alloc (isa
);
11474 slotbuf
= xtensa_insnbuf_alloc (isa
);
11477 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11478 fmt
= xtensa_format_decode (isa
, insnbuf
);
11479 if (fmt
== XTENSA_UNDEFINED
)
11480 as_fatal (_("cannot decode instruction format"));
11481 vinsn
->format
= fmt
;
11482 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11484 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11486 TInsn
*tinsn
= &vinsn
->slots
[i
];
11487 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11488 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11493 /* Expression utilities. */
11495 /* Return TRUE if the expression is an integer constant. */
11498 expr_is_const (const expressionS
*s
)
11500 return (s
->X_op
== O_constant
);
11504 /* Get the expression constant.
11505 Calling this is illegal if expr_is_const () returns TRUE. */
11508 get_expr_const (const expressionS
*s
)
11510 assert (expr_is_const (s
));
11511 return s
->X_add_number
;
11515 /* Set the expression to a constant value. */
11518 set_expr_const (expressionS
*s
, offsetT val
)
11520 s
->X_op
= O_constant
;
11521 s
->X_add_number
= val
;
11522 s
->X_add_symbol
= NULL
;
11523 s
->X_op_symbol
= NULL
;
11528 expr_is_register (const expressionS
*s
)
11530 return (s
->X_op
== O_register
);
11534 /* Get the expression constant.
11535 Calling this is illegal if expr_is_const () returns TRUE. */
11538 get_expr_register (const expressionS
*s
)
11540 assert (expr_is_register (s
));
11541 return s
->X_add_number
;
11545 /* Set the expression to a symbol + constant offset. */
11548 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11550 s
->X_op
= O_symbol
;
11551 s
->X_add_symbol
= sym
;
11552 s
->X_op_symbol
= NULL
; /* unused */
11553 s
->X_add_number
= offset
;
11557 /* Return TRUE if the two expressions are equal. */
11560 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11562 if (s1
->X_op
!= s2
->X_op
)
11564 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11566 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11568 if (s1
->X_add_number
!= s2
->X_add_number
)
11575 copy_expr (expressionS
*dst
, const expressionS
*src
)
11577 memcpy (dst
, src
, sizeof (expressionS
));
11581 /* Support for the "--rename-section" option. */
11583 struct rename_section_struct
11587 struct rename_section_struct
*next
;
11590 static struct rename_section_struct
*section_rename
;
11593 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11594 entries to the section_rename list. Note: Specifying multiple
11595 renamings separated by colons is not documented and is retained only
11596 for backward compatibility. */
11599 build_section_rename (const char *arg
)
11601 struct rename_section_struct
*r
;
11602 char *this_arg
= NULL
;
11603 char *next_arg
= NULL
;
11605 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11607 char *old_name
, *new_name
;
11611 next_arg
= strchr (this_arg
, ':');
11619 old_name
= this_arg
;
11620 new_name
= strchr (this_arg
, '=');
11622 if (*old_name
== '\0')
11624 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11627 if (!new_name
|| new_name
[1] == '\0')
11629 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11636 /* Check for invalid section renaming. */
11637 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11639 if (strcmp (r
->old_name
, old_name
) == 0)
11640 as_bad (_("section %s renamed multiple times"), old_name
);
11641 if (strcmp (r
->new_name
, new_name
) == 0)
11642 as_bad (_("multiple sections remapped to output section %s"),
11647 r
= (struct rename_section_struct
*)
11648 xmalloc (sizeof (struct rename_section_struct
));
11649 r
->old_name
= xstrdup (old_name
);
11650 r
->new_name
= xstrdup (new_name
);
11651 r
->next
= section_rename
;
11652 section_rename
= r
;
11658 xtensa_section_rename (char *name
)
11660 struct rename_section_struct
*r
= section_rename
;
11662 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11664 if (strcmp (r
->old_name
, name
) == 0)
11665 return r
->new_name
;