1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static size_t get_text_align_power (int);
450 static addressT
get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS
*);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT
, subsegT
);
459 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
460 static float get_subseg_total_freq (segT
, subsegT
);
461 static float get_subseg_target_freq (segT
, subsegT
);
462 static void set_subseg_freq (segT
, subsegT
, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state
*);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
470 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
471 static void xtensa_restore_emit_state (emit_state
*);
472 static void cache_literal_section
473 (seg_list
*, const char *, segT
*, bfd_boolean
);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection
*, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
483 static int xg_get_single_size (xtensa_opcode
);
484 static xtensa_format
xg_get_single_format (xtensa_opcode
);
486 /* TInsn and IStack functions. */
488 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
491 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
492 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
493 static void tinsn_from_chars (TInsn
*, char *, int);
494 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
495 static int get_num_stack_text_bytes (IStack
*);
496 static int get_num_stack_literal_bytes (IStack
*);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn
*);
501 static void xg_clear_vinsn (vliw_insn
*);
502 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
503 static void xg_free_vinsn (vliw_insn
*);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
506 static void vinsn_from_chars (vliw_insn
*, char *);
508 /* Expression Utilities. */
510 bfd_boolean
expr_is_const (const expressionS
*);
511 offsetT
get_expr_const (const expressionS
*);
512 void set_expr_const (expressionS
*, offsetT
);
513 bfd_boolean
expr_is_register (const expressionS
*);
514 offsetT
get_expr_register (const expressionS
*);
515 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
516 static void set_expr_symbol_offset_diff
517 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
518 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
519 static void copy_expr (expressionS
*, const expressionS
*);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 option_rename_section_name
,
653 option_prefer_const16
,
655 option_target_hardware
658 const char *md_shortopts
= "";
660 struct option md_longopts
[] =
662 { "density", no_argument
, NULL
, option_density
},
663 { "no-density", no_argument
, NULL
, option_no_density
},
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument
, NULL
, option_relax
},
668 { "no-relax", no_argument
, NULL
, option_no_relax
},
669 { "generics", no_argument
, NULL
, option_generics
},
670 { "no-generics", no_argument
, NULL
, option_no_generics
},
672 { "transform", no_argument
, NULL
, option_transform
},
673 { "no-transform", no_argument
, NULL
, option_no_transform
},
674 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
675 { "no-text-section-literals", no_argument
, NULL
,
676 option_no_text_section_literals
},
677 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
678 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument
, NULL
, option_align_targets
},
682 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
683 { "warn-unaligned-targets", no_argument
, NULL
,
684 option_warn_unaligned_targets
},
685 { "longcalls", no_argument
, NULL
, option_longcalls
},
686 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
688 { "no-workaround-a0-b-retw", no_argument
, NULL
,
689 option_no_workaround_a0_b_retw
},
690 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
692 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
693 option_no_workaround_b_j_loop_end
},
694 { "workaround-b-j-loop-end", no_argument
, NULL
,
695 option_workaround_b_j_loop_end
},
697 { "no-workaround-short-loops", no_argument
, NULL
,
698 option_no_workaround_short_loop
},
699 { "workaround-short-loops", no_argument
, NULL
,
700 option_workaround_short_loop
},
702 { "no-workaround-all-short-loops", no_argument
, NULL
,
703 option_no_workaround_all_short_loops
},
704 { "workaround-all-short-loop", no_argument
, NULL
,
705 option_workaround_all_short_loops
},
707 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
708 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
710 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
712 { "no-workaround-close-loop-end", no_argument
, NULL
,
713 option_no_workaround_close_loop_end
},
714 { "workaround-close-loop-end", no_argument
, NULL
,
715 option_workaround_close_loop_end
},
717 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
719 { "link-relax", no_argument
, NULL
, option_link_relax
},
720 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
722 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
724 { NULL
, no_argument
, NULL
, 0 }
727 size_t md_longopts_size
= sizeof md_longopts
;
731 md_parse_option (int c
, char *arg
)
736 as_warn (_("--density option is ignored"));
738 case option_no_density
:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax
:
744 case option_no_link_relax
:
747 case option_generics
:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_generics
:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform
, arg
);
756 case option_no_relax
:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform
, arg
);
759 case option_longcalls
:
760 directive_state
[directive_longcalls
] = TRUE
;
762 case option_no_longcalls
:
763 directive_state
[directive_longcalls
] = FALSE
;
765 case option_text_section_literals
:
766 use_literal_section
= FALSE
;
768 case option_no_text_section_literals
:
769 use_literal_section
= TRUE
;
771 case option_absolute_literals
:
772 if (!absolute_literals_supported
)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state
[directive_absolute_literals
] = TRUE
;
779 case option_no_absolute_literals
:
780 directive_state
[directive_absolute_literals
] = FALSE
;
783 case option_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= TRUE
;
786 case option_no_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= FALSE
;
789 case option_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= TRUE
;
792 case option_no_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= FALSE
;
796 case option_workaround_short_loop
:
797 workaround_short_loop
= TRUE
;
799 case option_no_workaround_short_loop
:
800 workaround_short_loop
= FALSE
;
803 case option_workaround_all_short_loops
:
804 workaround_all_short_loops
= TRUE
;
806 case option_no_workaround_all_short_loops
:
807 workaround_all_short_loops
= FALSE
;
810 case option_workaround_close_loop_end
:
811 workaround_close_loop_end
= TRUE
;
813 case option_no_workaround_close_loop_end
:
814 workaround_close_loop_end
= FALSE
;
817 case option_no_workarounds
:
818 workaround_a0_b_retw
= FALSE
;
819 workaround_b_j_loop_end
= FALSE
;
820 workaround_short_loop
= FALSE
;
821 workaround_all_short_loops
= FALSE
;
822 workaround_close_loop_end
= FALSE
;
825 case option_align_targets
:
826 align_targets
= TRUE
;
828 case option_no_align_targets
:
829 align_targets
= FALSE
;
832 case option_warn_unaligned_targets
:
833 warn_unaligned_branch_targets
= TRUE
;
836 case option_rename_section_name
:
837 build_section_rename (arg
);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r
:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16
:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware
:
859 int earliest
, latest
= 0;
860 if (*arg
== 0 || *arg
== '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest
= strtol (arg
, &arg
, 0);
867 else if (*arg
== '-')
870 as_fatal (_("invalid target hardware version"));
871 latest
= strtol (arg
, &arg
, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest
, latest
);
880 case option_transform
:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform
:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state
[directive_transform
] = FALSE
;
902 md_show_usage (FILE *stream
)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS
*sym
)
924 if (!free_insn_labels
)
925 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
928 l
= free_insn_labels
;
929 free_insn_labels
= l
->next
;
933 l
->next
= insn_labels
;
939 xtensa_clear_insn_labels (void)
943 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
979 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
981 symbolS
*lit_sym
= lit
->sym
;
982 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
984 S_SET_VALUE (lit_sym
, new_offset
);
985 symbol_set_frag (lit_sym
, new_frag
);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive
;
997 bfd_boolean old_state
;
1001 struct state_stackS_struct
*prev
;
1004 state_stackS
*directive_state_stack
;
1006 const pseudo_typeS md_pseudo_table
[] =
1008 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position
, 0 },
1010 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons
, 4 },
1012 { "word", xtensa_elf_cons
, 4 },
1013 { "short", xtensa_elf_cons
, 2 },
1014 { "begin", xtensa_begin_directive
, 0 },
1015 { "end", xtensa_end_directive
, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1017 { "literal", xtensa_literal_pseudo
, 0 },
1018 { "frequency", xtensa_frequency_pseudo
, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end
);
1029 return directive_state
[directive_transform
];
1034 use_longcalls (void)
1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end
);
1039 return directive_state
[directive_longcalls
] && use_transform ();
1044 do_align_targets (void)
1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end
);
1049 return align_targets
&& use_transform ();
1054 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1058 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1060 as_where (&file
, &line
);
1062 stack
->directive
= directive
;
1063 stack
->negated
= negated
;
1064 stack
->old_state
= directive_state
[directive
];
1067 stack
->datum
= datum
;
1068 stack
->prev
= directive_state_stack
;
1069 directive_state_stack
= stack
;
1071 directive_state
[directive
] = !negated
;
1076 directive_pop (directiveE
*directive
,
1077 bfd_boolean
*negated
,
1082 state_stackS
*top
= directive_state_stack
;
1084 if (!directive_state_stack
)
1086 as_bad (_("unmatched end directive"));
1087 *directive
= directive_none
;
1091 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1092 *directive
= top
->directive
;
1093 *negated
= top
->negated
;
1096 *datum
= top
->datum
;
1097 directive_state_stack
= top
->prev
;
1103 directive_balance (void)
1105 while (directive_state_stack
)
1107 directiveE directive
;
1108 bfd_boolean negated
;
1113 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1114 as_warn_where ((char *) file
, line
,
1115 _(".begin directive with no matching .end directive"));
1121 inside_directive (directiveE dir
)
1123 state_stackS
*top
= directive_state_stack
;
1125 while (top
&& top
->directive
!= dir
)
1128 return (top
!= NULL
);
1133 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1137 char *directive_string
;
1139 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1144 input_line_pointer
+= 3;
1147 len
= strspn (input_line_pointer
,
1148 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1150 /* This code is a hack to make .begin [no-][generics|relax] exactly
1151 equivalent to .begin [no-]transform. We should remove it when
1152 we stop accepting those options. */
1154 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1156 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1157 directive_string
= "transform";
1159 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1161 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1162 directive_string
= "transform";
1165 directive_string
= input_line_pointer
;
1167 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1169 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1171 input_line_pointer
+= len
;
1172 *directive
= (directiveE
) i
;
1173 if (*negated
&& !directive_info
[i
].can_be_negated
)
1174 as_bad (_("directive %s cannot be negated"),
1175 directive_info
[i
].name
);
1180 as_bad (_("unknown directive"));
1181 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1186 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1188 directiveE directive
;
1189 bfd_boolean negated
;
1194 get_directive (&directive
, &negated
);
1195 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1197 discard_rest_of_line ();
1201 if (cur_vinsn
.inside_bundle
)
1202 as_bad (_("directives are not valid inside bundles"));
1206 case directive_literal
:
1207 if (!inside_directive (directive_literal
))
1209 /* Previous labels go with whatever follows this directive, not with
1210 the literal, so save them now. */
1211 saved_insn_labels
= insn_labels
;
1214 as_warn (_(".begin literal is deprecated; use .literal instead"));
1215 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1216 xtensa_switch_to_literal_fragment (state
);
1217 directive_push (directive_literal
, negated
, state
);
1220 case directive_literal_prefix
:
1221 /* Have to flush pending output because a movi relaxed to an l32r
1222 might produce a literal. */
1223 md_flush_pending_output ();
1224 /* Check to see if the current fragment is a literal
1225 fragment. If it is, then this operation is not allowed. */
1226 if (generating_literals
)
1228 as_bad (_("cannot set literal_prefix inside literal fragment"));
1232 /* Allocate the literal state for this section and push
1233 onto the directive stack. */
1234 ls
= xmalloc (sizeof (lit_state
));
1237 *ls
= default_lit_sections
;
1239 directive_push (directive_literal_prefix
, negated
, ls
);
1241 /* Parse the new prefix from the input_line_pointer. */
1243 len
= strspn (input_line_pointer
,
1244 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1245 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1247 /* Process the new prefix. */
1248 xtensa_literal_prefix (input_line_pointer
, len
);
1250 /* Skip the name in the input line. */
1251 input_line_pointer
+= len
;
1254 case directive_freeregs
:
1255 /* This information is currently unused, but we'll accept the statement
1256 and just discard the rest of the line. This won't check the syntax,
1257 but it will accept every correct freeregs directive. */
1258 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1259 directive_push (directive_freeregs
, negated
, 0);
1262 case directive_schedule
:
1263 md_flush_pending_output ();
1264 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1265 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1266 directive_push (directive_schedule
, negated
, 0);
1267 xtensa_set_frag_assembly_state (frag_now
);
1270 case directive_density
:
1271 as_warn (_(".begin [no-]density is ignored"));
1274 case directive_absolute_literals
:
1275 md_flush_pending_output ();
1276 if (!absolute_literals_supported
&& !negated
)
1278 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1281 xtensa_set_frag_assembly_state (frag_now
);
1282 directive_push (directive
, negated
, 0);
1286 md_flush_pending_output ();
1287 xtensa_set_frag_assembly_state (frag_now
);
1288 directive_push (directive
, negated
, 0);
1292 demand_empty_rest_of_line ();
1297 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1299 directiveE begin_directive
, end_directive
;
1300 bfd_boolean begin_negated
, end_negated
;
1304 emit_state
**state_ptr
;
1307 if (cur_vinsn
.inside_bundle
)
1308 as_bad (_("directives are not valid inside bundles"));
1310 get_directive (&end_directive
, &end_negated
);
1312 md_flush_pending_output ();
1314 switch (end_directive
)
1316 case (directiveE
) XTENSA_UNDEFINED
:
1317 discard_rest_of_line ();
1320 case directive_density
:
1321 as_warn (_(".end [no-]density is ignored"));
1322 demand_empty_rest_of_line ();
1325 case directive_absolute_literals
:
1326 if (!absolute_literals_supported
&& !end_negated
)
1328 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1329 demand_empty_rest_of_line ();
1338 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1339 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1340 (const void **) state_ptr
);
1342 if (begin_directive
!= directive_none
)
1344 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1346 as_bad (_("does not match begin %s%s at %s:%d"),
1347 begin_negated
? "no-" : "",
1348 directive_info
[begin_directive
].name
, file
, line
);
1352 switch (end_directive
)
1354 case directive_literal
:
1355 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1356 xtensa_restore_emit_state (state
);
1357 xtensa_set_frag_assembly_state (frag_now
);
1359 if (!inside_directive (directive_literal
))
1361 /* Restore the list of current labels. */
1362 xtensa_clear_insn_labels ();
1363 insn_labels
= saved_insn_labels
;
1367 case directive_literal_prefix
:
1368 /* Restore the default collection sections from saved state. */
1369 s
= (lit_state
*) state
;
1372 if (use_literal_section
)
1373 default_lit_sections
= *s
;
1375 /* free the state storage */
1379 case directive_schedule
:
1380 case directive_freeregs
:
1384 xtensa_set_frag_assembly_state (frag_now
);
1390 demand_empty_rest_of_line ();
1394 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1396 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1399 xtensa_dwarf2_directive_loc (int x
)
1401 xtensa_loc_directive_seen
= TRUE
;
1402 dwarf2_directive_loc (x
);
1407 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1409 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1411 xtensa_loc_directive_seen
= FALSE
;
1412 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1416 /* Place an aligned literal fragment at the current location. */
1419 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1421 md_flush_pending_output ();
1423 if (inside_directive (directive_literal
))
1424 as_warn (_(".literal_position inside literal directive; ignoring"));
1425 xtensa_mark_literal_pool_location ();
1427 demand_empty_rest_of_line ();
1428 xtensa_clear_insn_labels ();
1432 /* Support .literal label, expr, ... */
1435 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1438 char *p
, *base_name
;
1442 if (inside_directive (directive_literal
))
1444 as_bad (_(".literal not allowed inside .begin literal region"));
1445 ignore_rest_of_line ();
1449 md_flush_pending_output ();
1451 /* Previous labels go with whatever follows this directive, not with
1452 the literal, so save them now. */
1453 saved_insn_labels
= insn_labels
;
1456 /* If we are using text-section literals, then this is the right value... */
1459 base_name
= input_line_pointer
;
1461 xtensa_switch_to_literal_fragment (&state
);
1463 /* ...but if we aren't using text-section-literals, then we
1464 need to put them in the section we just switched to. */
1465 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1468 /* All literals are aligned to four-byte boundaries. */
1469 frag_align (2, 0, 0);
1470 record_alignment (now_seg
, 2);
1472 c
= get_symbol_end ();
1473 /* Just after name is now '\0'. */
1474 p
= input_line_pointer
;
1478 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1480 as_bad (_("expected comma or colon after symbol name; "
1481 "rest of line ignored"));
1482 ignore_rest_of_line ();
1483 xtensa_restore_emit_state (&state
);
1491 input_line_pointer
++; /* skip ',' or ':' */
1493 xtensa_elf_cons (4);
1495 xtensa_restore_emit_state (&state
);
1497 /* Restore the list of current labels. */
1498 xtensa_clear_insn_labels ();
1499 insn_labels
= saved_insn_labels
;
1504 xtensa_literal_prefix (char const *start
, int len
)
1506 char *name
, *linkonce_suffix
;
1507 char *newname
, *newname4
;
1508 size_t linkonce_len
;
1510 /* Get a null-terminated copy of the name. */
1511 name
= xmalloc (len
+ 1);
1514 strncpy (name
, start
, len
);
1517 /* Allocate the sections (interesting note: the memory pointing to
1518 the name is actually used for the name by the new section). */
1520 newname
= xmalloc (len
+ strlen (".literal") + 1);
1521 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1523 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1524 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1525 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1527 strcpy (newname
, ".gnu.linkonce.literal");
1528 strcpy (newname4
, ".gnu.linkonce.lit4");
1530 strcat (newname
, linkonce_suffix
);
1531 strcat (newname4
, linkonce_suffix
);
1535 int suffix_pos
= len
;
1537 /* If the section name ends with ".text", then replace that suffix
1538 instead of appending an additional suffix. */
1539 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1542 strcpy (newname
, name
);
1543 strcpy (newname4
, name
);
1545 strcpy (newname
+ suffix_pos
, ".literal");
1546 strcpy (newname4
+ suffix_pos
, ".lit4");
1549 /* Note that cache_literal_section does not create a segment if
1550 it already exists. */
1551 default_lit_sections
.lit_seg
= NULL
;
1552 default_lit_sections
.lit4_seg
= NULL
;
1554 /* Canonicalizing section names allows renaming literal
1555 sections to occur correctly. */
1556 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1557 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1563 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1566 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1568 float fall_through_f
, target_f
;
1570 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1571 if (fall_through_f
< 0)
1573 as_bad (_("fall through frequency must be greater than 0"));
1574 ignore_rest_of_line ();
1578 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1581 as_bad (_("branch target frequency must be greater than 0"));
1582 ignore_rest_of_line ();
1586 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1588 demand_empty_rest_of_line ();
1592 /* Like normal .long/.short/.word, except support @plt, etc.
1593 Clobbers input_line_pointer, checks end-of-line. */
1596 xtensa_elf_cons (int nbytes
)
1599 bfd_reloc_code_real_type reloc
;
1601 md_flush_pending_output ();
1603 if (cur_vinsn
.inside_bundle
)
1604 as_bad (_("directives are not valid inside bundles"));
1606 if (is_it_end_of_statement ())
1608 demand_empty_rest_of_line ();
1615 if (exp
.X_op
== O_symbol
1616 && *input_line_pointer
== '@'
1617 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1620 reloc_howto_type
*reloc_howto
=
1621 bfd_reloc_type_lookup (stdoutput
, reloc
);
1623 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1624 as_bad (_("unsupported relocation"));
1625 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1626 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1627 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1628 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1629 as_bad (_("opcode-specific %s relocation used outside "
1630 "an instruction"), reloc_howto
->name
);
1631 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1632 as_bad (_("%s relocations do not fit in %d bytes"),
1633 reloc_howto
->name
, nbytes
);
1636 char *p
= frag_more ((int) nbytes
);
1637 xtensa_set_frag_assembly_state (frag_now
);
1638 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1639 nbytes
, &exp
, 0, reloc
);
1643 emit_expr (&exp
, (unsigned int) nbytes
);
1645 while (*input_line_pointer
++ == ',');
1647 input_line_pointer
--; /* Put terminator back into stream. */
1648 demand_empty_rest_of_line ();
1652 /* Parsing and Idiom Translation. */
1654 /* Parse @plt, etc. and return the desired relocation. */
1655 static bfd_reloc_code_real_type
1656 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1662 bfd_reloc_code_real_type reloc
;
1670 struct map_bfd
*ptr
;
1672 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1674 static struct map_bfd mapping
[] =
1676 MAP ("l", BFD_RELOC_LO16
),
1677 MAP ("h", BFD_RELOC_HI16
),
1678 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1679 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1683 return BFD_RELOC_NONE
;
1685 for (ch
= *str
, str2
= ident
;
1686 (str2
< ident
+ sizeof (ident
) - 1
1687 && (ISALNUM (ch
) || ch
== '@'));
1690 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1697 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1698 if (ch
== ptr
->string
[0]
1699 && len
== ptr
->length
1700 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1702 /* Now check for "identifier@suffix+constant". */
1703 if (*str
== '-' || *str
== '+')
1705 char *orig_line
= input_line_pointer
;
1706 expressionS new_exp
;
1708 input_line_pointer
= str
;
1709 expression (&new_exp
);
1710 if (new_exp
.X_op
== O_constant
)
1712 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1713 str
= input_line_pointer
;
1716 if (&input_line_pointer
!= str_p
)
1717 input_line_pointer
= orig_line
;
1724 return BFD_RELOC_UNUSED
;
1729 expression_end (const char *name
)
1752 #define ERROR_REG_NUM ((unsigned) -1)
1755 tc_get_register (const char *prefix
)
1758 const char *next_expr
;
1759 const char *old_line_pointer
;
1762 old_line_pointer
= input_line_pointer
;
1764 if (*input_line_pointer
== '$')
1765 ++input_line_pointer
;
1767 /* Accept "sp" as a synonym for "a1". */
1768 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1769 && expression_end (input_line_pointer
+ 2))
1771 input_line_pointer
+= 2;
1772 return 1; /* AR[1] */
1775 while (*input_line_pointer
++ == *prefix
++)
1777 --input_line_pointer
;
1782 as_bad (_("bad register name: %s"), old_line_pointer
);
1783 return ERROR_REG_NUM
;
1786 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1788 as_bad (_("bad register number: %s"), input_line_pointer
);
1789 return ERROR_REG_NUM
;
1794 while (ISDIGIT ((int) *input_line_pointer
))
1795 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1797 if (!(next_expr
= expression_end (input_line_pointer
)))
1799 as_bad (_("bad register name: %s"), old_line_pointer
);
1800 return ERROR_REG_NUM
;
1803 input_line_pointer
= (char *) next_expr
;
1810 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1812 xtensa_isa isa
= xtensa_default_isa
;
1814 /* Check if this is an immediate operand. */
1815 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1817 bfd_reloc_code_real_type reloc
;
1818 segT t
= expression (tok
);
1819 if (t
== absolute_section
1820 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1822 assert (tok
->X_op
== O_constant
);
1823 tok
->X_op
= O_symbol
;
1824 tok
->X_add_symbol
= &abs_symbol
;
1827 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1828 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1829 && (reloc
!= BFD_RELOC_NONE
))
1834 case BFD_RELOC_UNUSED
:
1835 as_bad (_("unsupported relocation"));
1838 case BFD_RELOC_XTENSA_PLT
:
1839 tok
->X_op
= O_pltrel
;
1842 case BFD_RELOC_LO16
:
1843 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1849 case BFD_RELOC_HI16
:
1850 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1860 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1861 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1863 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1866 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1867 as_bad (_("register number out of range"));
1870 tok
->X_op
= O_register
;
1871 tok
->X_add_symbol
= 0;
1872 tok
->X_add_number
= reg
;
1877 /* Split up the arguments for an opcode or pseudo-op. */
1880 tokenize_arguments (char **args
, char *str
)
1882 char *old_input_line_pointer
;
1883 bfd_boolean saw_comma
= FALSE
;
1884 bfd_boolean saw_arg
= FALSE
;
1885 bfd_boolean saw_colon
= FALSE
;
1887 char *arg_end
, *arg
;
1890 /* Save and restore input_line_pointer around this function. */
1891 old_input_line_pointer
= input_line_pointer
;
1892 input_line_pointer
= str
;
1894 while (*input_line_pointer
)
1897 switch (*input_line_pointer
)
1904 input_line_pointer
++;
1905 if (saw_comma
|| saw_colon
|| !saw_arg
)
1911 input_line_pointer
++;
1912 if (saw_comma
|| saw_colon
|| !saw_arg
)
1918 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1921 arg_end
= input_line_pointer
+ 1;
1922 while (!expression_end (arg_end
))
1925 arg_len
= arg_end
- input_line_pointer
;
1926 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1927 args
[num_args
] = arg
;
1931 strncpy (arg
, input_line_pointer
, arg_len
);
1932 arg
[arg_len
] = '\0';
1934 input_line_pointer
= arg_end
;
1944 if (saw_comma
|| saw_colon
)
1946 input_line_pointer
= old_input_line_pointer
;
1951 as_bad (_("extra comma"));
1953 as_bad (_("extra colon"));
1955 as_bad (_("missing argument"));
1957 as_bad (_("missing comma or colon"));
1958 input_line_pointer
= old_input_line_pointer
;
1963 /* Parse the arguments to an opcode. Return TRUE on error. */
1966 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1968 expressionS
*tok
, *last_tok
;
1969 xtensa_opcode opcode
= insn
->opcode
;
1970 bfd_boolean had_error
= TRUE
;
1971 xtensa_isa isa
= xtensa_default_isa
;
1972 int n
, num_regs
= 0;
1973 int opcode_operand_count
;
1974 int opnd_cnt
, last_opnd_cnt
;
1975 unsigned int next_reg
= 0;
1976 char *old_input_line_pointer
;
1978 if (insn
->insn_type
== ITYPE_LITERAL
)
1979 opcode_operand_count
= 1;
1981 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1984 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1986 /* Save and restore input_line_pointer around this function. */
1987 old_input_line_pointer
= input_line_pointer
;
1993 /* Skip invisible operands. */
1994 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2000 for (n
= 0; n
< num_args
; n
++)
2002 input_line_pointer
= arg_strings
[n
];
2003 if (*input_line_pointer
== ':')
2005 xtensa_regfile opnd_rf
;
2006 input_line_pointer
++;
2009 assert (opnd_cnt
> 0);
2011 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2013 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2014 as_warn (_("incorrect register number, ignoring"));
2019 if (opnd_cnt
>= opcode_operand_count
)
2021 as_warn (_("too many arguments"));
2024 assert (opnd_cnt
< MAX_INSN_ARGS
);
2026 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2027 next_reg
= tok
->X_add_number
+ 1;
2029 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2031 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2033 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2034 /* minus 1 because we are seeing one right now */
2040 last_opnd_cnt
= opnd_cnt
;
2047 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2051 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2054 insn
->ntok
= tok
- insn
->tok
;
2058 input_line_pointer
= old_input_line_pointer
;
2064 get_invisible_operands (TInsn
*insn
)
2066 xtensa_isa isa
= xtensa_default_isa
;
2067 static xtensa_insnbuf slotbuf
= NULL
;
2069 xtensa_opcode opc
= insn
->opcode
;
2070 int slot
, opnd
, fmt_found
;
2074 slotbuf
= xtensa_insnbuf_alloc (isa
);
2076 /* Find format/slot where this can be encoded. */
2079 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2081 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2083 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2089 if (fmt_found
) break;
2094 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2098 /* First encode all the visible operands
2099 (to deal with shared field operands). */
2100 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2102 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2103 && (insn
->tok
[opnd
].X_op
== O_register
2104 || insn
->tok
[opnd
].X_op
== O_constant
))
2106 val
= insn
->tok
[opnd
].X_add_number
;
2107 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2108 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2112 /* Then pull out the values for the invisible ones. */
2113 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2115 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2117 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2118 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2119 insn
->tok
[opnd
].X_add_number
= val
;
2120 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2121 insn
->tok
[opnd
].X_op
= O_register
;
2123 insn
->tok
[opnd
].X_op
= O_constant
;
2132 xg_reverse_shift_count (char **cnt_argp
)
2134 char *cnt_arg
, *new_arg
;
2135 cnt_arg
= *cnt_argp
;
2137 /* replace the argument with "31-(argument)" */
2138 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2139 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2142 *cnt_argp
= new_arg
;
2146 /* If "arg" is a constant expression, return non-zero with the value
2150 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2153 char *save_ptr
= input_line_pointer
;
2155 input_line_pointer
= arg
;
2157 input_line_pointer
= save_ptr
;
2159 if (exp
.X_op
== O_constant
)
2161 *valp
= exp
.X_add_number
;
2170 xg_replace_opname (char **popname
, char *newop
)
2173 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2174 strcpy (*popname
, newop
);
2179 xg_check_num_args (int *pnum_args
,
2184 int num_args
= *pnum_args
;
2186 if (num_args
< expected_num
)
2188 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2189 num_args
, opname
, expected_num
);
2193 if (num_args
> expected_num
)
2195 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2196 num_args
, opname
, expected_num
);
2197 while (num_args
-- > expected_num
)
2199 free (arg_strings
[num_args
]);
2200 arg_strings
[num_args
] = 0;
2202 *pnum_args
= expected_num
;
2210 /* If the register is not specified as part of the opcode,
2211 then get it from the operand and move it to the opcode. */
2214 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2216 xtensa_isa isa
= xtensa_default_isa
;
2218 char *opname
, *new_opname
;
2219 const char *sr_name
;
2220 int is_user
, is_write
;
2221 bfd_boolean has_underbar
= FALSE
;
2226 has_underbar
= TRUE
;
2229 is_user
= (opname
[1] == 'u');
2230 is_write
= (opname
[0] == 'w');
2232 /* Opname == [rw]ur or [rwx]sr... */
2234 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2237 /* Check if the argument is a symbolic register name. */
2238 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2239 /* Handle WSR to "INTSET" as a special case. */
2240 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2241 && !strcasecmp (arg_strings
[1], "intset"))
2242 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2243 if (sr
== XTENSA_UNDEFINED
2244 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2246 /* Maybe it's a register number.... */
2248 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2250 as_bad (_("invalid register '%s' for '%s' instruction"),
2251 arg_strings
[1], opname
);
2254 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2255 if (sr
== XTENSA_UNDEFINED
)
2257 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2263 /* Remove the last argument, which is now part of the opcode. */
2264 free (arg_strings
[1]);
2268 /* Translate the opcode. */
2269 sr_name
= xtensa_sysreg_name (isa
, sr
);
2270 /* Another special case for "WSR.INTSET".... */
2271 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2273 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2274 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2277 *popname
= new_opname
;
2284 xtensa_translate_old_userreg_ops (char **popname
)
2286 xtensa_isa isa
= xtensa_default_isa
;
2288 char *opname
, *new_opname
;
2289 const char *sr_name
;
2290 bfd_boolean has_underbar
= FALSE
;
2293 if (opname
[0] == '_')
2295 has_underbar
= TRUE
;
2299 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2300 if (sr
!= XTENSA_UNDEFINED
)
2302 /* The new default name ("nnn") is different from the old default
2303 name ("URnnn"). The old default is handled below, and we don't
2304 want to recognize [RW]nnn, so do nothing if the name is the (new)
2306 static char namebuf
[10];
2307 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2308 if (strcmp (namebuf
, opname
+ 1) == 0)
2316 /* Only continue if the reg name is "URnnn". */
2317 if (opname
[1] != 'u' || opname
[2] != 'r')
2319 val
= strtoul (opname
+ 3, &end
, 10);
2323 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2324 if (sr
== XTENSA_UNDEFINED
)
2326 as_bad (_("invalid register number (%ld) for '%s'"),
2332 /* Translate the opcode. */
2333 sr_name
= xtensa_sysreg_name (isa
, sr
);
2334 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2335 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2336 opname
[0], sr_name
);
2338 *popname
= new_opname
;
2345 xtensa_translate_zero_immed (char *old_op
,
2355 assert (opname
[0] != '_');
2357 if (strcmp (opname
, old_op
) != 0)
2360 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2362 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2364 xg_replace_opname (popname
, new_op
);
2365 free (arg_strings
[1]);
2366 arg_strings
[1] = arg_strings
[2];
2375 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2376 Returns non-zero if an error was found. */
2379 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2381 char *opname
= *popname
;
2382 bfd_boolean has_underbar
= FALSE
;
2384 if (cur_vinsn
.inside_bundle
)
2389 has_underbar
= TRUE
;
2393 if (strcmp (opname
, "mov") == 0)
2395 if (use_transform () && !has_underbar
&& density_supported
)
2396 xg_replace_opname (popname
, "mov.n");
2399 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2401 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2402 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2403 strcpy (arg_strings
[2], arg_strings
[1]);
2409 if (strcmp (opname
, "bbsi.l") == 0)
2411 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2413 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2414 if (target_big_endian
)
2415 xg_reverse_shift_count (&arg_strings
[1]);
2419 if (strcmp (opname
, "bbci.l") == 0)
2421 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2423 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2424 if (target_big_endian
)
2425 xg_reverse_shift_count (&arg_strings
[1]);
2429 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2430 && strcmp (opname
, "nop") == 0)
2432 if (use_transform () && !has_underbar
&& density_supported
)
2433 xg_replace_opname (popname
, "nop.n");
2436 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2438 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2439 arg_strings
[0] = (char *) xmalloc (3);
2440 arg_strings
[1] = (char *) xmalloc (3);
2441 arg_strings
[2] = (char *) xmalloc (3);
2442 strcpy (arg_strings
[0], "a1");
2443 strcpy (arg_strings
[1], "a1");
2444 strcpy (arg_strings
[2], "a1");
2450 /* Recognize [RW]UR and [RWX]SR. */
2451 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2452 && (opname
[1] == 'u' || opname
[1] == 's'))
2453 || (opname
[0] == 'x' && opname
[1] == 's'))
2455 && opname
[3] == '\0')
2456 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2458 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2459 [RW]<name> if <name> is the non-default name of a user register. */
2460 if ((opname
[0] == 'r' || opname
[0] == 'w')
2461 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2462 return xtensa_translate_old_userreg_ops (popname
);
2464 /* Relax branches that don't allow comparisons against an immediate value
2465 of zero to the corresponding branches with implicit zero immediates. */
2466 if (!has_underbar
&& use_transform ())
2468 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2469 pnum_args
, arg_strings
))
2472 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2473 pnum_args
, arg_strings
))
2476 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2477 pnum_args
, arg_strings
))
2480 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2481 pnum_args
, arg_strings
))
2489 /* Functions for dealing with the Xtensa ISA. */
2491 /* Currently the assembler only allows us to use a single target per
2492 fragment. Because of this, only one operand for a given
2493 instruction may be symbolic. If there is a PC-relative operand,
2494 the last one is chosen. Otherwise, the result is the number of the
2495 last immediate operand, and if there are none of those, we fail and
2499 get_relaxable_immed (xtensa_opcode opcode
)
2501 int last_immed
= -1;
2504 if (opcode
== XTENSA_UNDEFINED
)
2507 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2508 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2510 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2512 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2514 if (last_immed
== -1
2515 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2522 static xtensa_opcode
2523 get_opcode_from_buf (const char *buf
, int slot
)
2525 static xtensa_insnbuf insnbuf
= NULL
;
2526 static xtensa_insnbuf slotbuf
= NULL
;
2527 xtensa_isa isa
= xtensa_default_isa
;
2532 insnbuf
= xtensa_insnbuf_alloc (isa
);
2533 slotbuf
= xtensa_insnbuf_alloc (isa
);
2536 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2537 fmt
= xtensa_format_decode (isa
, insnbuf
);
2538 if (fmt
== XTENSA_UNDEFINED
)
2539 return XTENSA_UNDEFINED
;
2541 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2542 return XTENSA_UNDEFINED
;
2544 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2545 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2549 #ifdef TENSILICA_DEBUG
2551 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2554 xtensa_print_insn_table (void)
2556 int num_opcodes
, num_operands
;
2557 xtensa_opcode opcode
;
2558 xtensa_isa isa
= xtensa_default_isa
;
2560 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2561 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2564 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2565 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2566 for (opn
= 0; opn
< num_operands
; opn
++)
2568 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2570 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2572 xtensa_regfile opnd_rf
=
2573 xtensa_operand_regfile (isa
, opcode
, opn
);
2574 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2576 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2577 fputs ("[lLr] ", stderr
);
2579 fputs ("i ", stderr
);
2581 fprintf (stderr
, "\n");
2587 print_vliw_insn (xtensa_insnbuf vbuf
)
2589 xtensa_isa isa
= xtensa_default_isa
;
2590 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2591 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2594 fprintf (stderr
, "format = %d\n", f
);
2596 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2598 xtensa_opcode opcode
;
2602 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2603 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2604 opname
= xtensa_opcode_name (isa
, opcode
);
2606 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2607 fprintf (stderr
, " operands = ");
2609 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2613 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2615 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2616 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2617 fprintf (stderr
, "%d ", val
);
2619 fprintf (stderr
, "\n");
2621 xtensa_insnbuf_free (isa
, sbuf
);
2624 #endif /* TENSILICA_DEBUG */
2628 is_direct_call_opcode (xtensa_opcode opcode
)
2630 xtensa_isa isa
= xtensa_default_isa
;
2631 int n
, num_operands
;
2633 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2636 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2637 for (n
= 0; n
< num_operands
; n
++)
2639 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2640 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2647 /* Convert from BFD relocation type code to slot and operand number.
2648 Returns non-zero on failure. */
2651 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2653 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2654 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2656 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2659 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2672 /* Convert from slot number to BFD relocation type code for the
2673 standard PC-relative relocations. Return BFD_RELOC_NONE on
2676 static bfd_reloc_code_real_type
2677 encode_reloc (int slot
)
2679 if (slot
< 0 || slot
> 14)
2680 return BFD_RELOC_NONE
;
2682 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2686 /* Convert from slot numbers to BFD relocation type code for the
2687 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2689 static bfd_reloc_code_real_type
2690 encode_alt_reloc (int slot
)
2692 if (slot
< 0 || slot
> 14)
2693 return BFD_RELOC_NONE
;
2695 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2700 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2703 xtensa_opcode opcode
,
2709 uint32 valbuf
= value
;
2711 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2713 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2715 as_bad_where ((char *) file
, line
,
2716 _("operand %u is out of range for '%s'"), value
,
2717 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2719 as_bad_where ((char *) file
, line
,
2720 _("operand %u is invalid for '%s'"), value
,
2721 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2725 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2731 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2734 xtensa_opcode opcode
,
2738 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2739 fmt
, slot
, slotbuf
, &val
);
2740 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2745 /* Checks for rules from xtensa-relax tables. */
2747 /* The routine xg_instruction_matches_option_term must return TRUE
2748 when a given option term is true. The meaning of all of the option
2749 terms is given interpretation by this function. This is needed when
2750 an option depends on the state of a directive, but there are no such
2751 options in use right now. */
2754 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2755 const ReqOrOption
*option
)
2757 if (strcmp (option
->option_name
, "realnop") == 0
2758 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2760 /* These conditions were evaluated statically when building the
2761 relaxation table. There's no need to reevaluate them now. */
2766 as_fatal (_("internal error: unknown option name '%s'"),
2767 option
->option_name
);
2773 xg_instruction_matches_or_options (TInsn
*insn
,
2774 const ReqOrOptionList
*or_option
)
2776 const ReqOrOption
*option
;
2777 /* Must match each of the AND terms. */
2778 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2780 if (xg_instruction_matches_option_term (insn
, option
))
2788 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2790 const ReqOption
*req_options
;
2791 /* Must match each of the AND terms. */
2792 for (req_options
= options
;
2793 req_options
!= NULL
;
2794 req_options
= req_options
->next
)
2796 /* Must match one of the OR clauses. */
2797 if (!xg_instruction_matches_or_options (insn
,
2798 req_options
->or_option_terms
))
2805 /* Return the transition rule that matches or NULL if none matches. */
2808 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2810 PreconditionList
*condition_l
;
2812 if (rule
->opcode
!= insn
->opcode
)
2815 for (condition_l
= rule
->conditions
;
2816 condition_l
!= NULL
;
2817 condition_l
= condition_l
->next
)
2821 Precondition
*cond
= condition_l
->precond
;
2826 /* The expression must be the constant. */
2827 assert (cond
->op_num
< insn
->ntok
);
2828 exp1
= &insn
->tok
[cond
->op_num
];
2829 if (expr_is_const (exp1
))
2834 if (get_expr_const (exp1
) != cond
->op_data
)
2838 if (get_expr_const (exp1
) == cond
->op_data
)
2845 else if (expr_is_register (exp1
))
2850 if (get_expr_register (exp1
) != cond
->op_data
)
2854 if (get_expr_register (exp1
) == cond
->op_data
)
2866 assert (cond
->op_num
< insn
->ntok
);
2867 assert (cond
->op_data
< insn
->ntok
);
2868 exp1
= &insn
->tok
[cond
->op_num
];
2869 exp2
= &insn
->tok
[cond
->op_data
];
2874 if (!expr_is_equal (exp1
, exp2
))
2878 if (expr_is_equal (exp1
, exp2
))
2890 if (!xg_instruction_matches_options (insn
, rule
->options
))
2898 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2900 bfd_boolean a_greater
= FALSE
;
2901 bfd_boolean b_greater
= FALSE
;
2903 ReqOptionList
*l_a
= a
->options
;
2904 ReqOptionList
*l_b
= b
->options
;
2906 /* We only care if they both are the same except for
2907 a const16 vs. an l32r. */
2909 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2911 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2912 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2913 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2915 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2917 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2919 /* This is the case we care about. */
2920 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2921 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2928 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2929 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2939 l_or_a
= l_or_a
->next
;
2940 l_or_b
= l_or_b
->next
;
2942 if (l_or_a
|| l_or_b
)
2951 /* Incomparable if the substitution was used differently in two cases. */
2952 if (a_greater
&& b_greater
)
2964 static TransitionRule
*
2965 xg_instruction_match (TInsn
*insn
)
2967 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2969 assert (insn
->opcode
< table
->num_opcodes
);
2971 /* Walk through all of the possible transitions. */
2972 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2974 TransitionRule
*rule
= l
->rule
;
2975 if (xg_instruction_matches_rule (insn
, rule
))
2982 /* Various Other Internal Functions. */
2985 is_unique_insn_expansion (TransitionRule
*r
)
2987 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2989 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2996 xg_get_build_instr_size (BuildInstr
*insn
)
2998 assert (insn
->typ
== INSTR_INSTR
);
2999 return xg_get_single_size (insn
->opcode
);
3004 xg_is_narrow_insn (TInsn
*insn
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3009 assert (insn
->insn_type
== ITYPE_INSN
);
3010 assert (insn
->opcode
< table
->num_opcodes
);
3012 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3014 TransitionRule
*rule
= l
->rule
;
3016 if (xg_instruction_matches_rule (insn
, rule
)
3017 && is_unique_insn_expansion (rule
))
3019 /* It only generates one instruction... */
3020 assert (insn
->insn_type
== ITYPE_INSN
);
3021 /* ...and it is a larger instruction. */
3022 if (xg_get_single_size (insn
->opcode
)
3023 < xg_get_build_instr_size (rule
->to_instr
))
3031 return (num_match
== 1);
3036 xg_is_single_relaxable_insn (TInsn
*insn
)
3038 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3041 assert (insn
->insn_type
== ITYPE_INSN
);
3042 assert (insn
->opcode
< table
->num_opcodes
);
3044 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3046 TransitionRule
*rule
= l
->rule
;
3048 if (xg_instruction_matches_rule (insn
, rule
)
3049 && is_unique_insn_expansion (rule
))
3051 /* It only generates one instruction... */
3052 assert (insn
->insn_type
== ITYPE_INSN
);
3053 /* ... and it is a larger instruction. */
3054 if (xg_get_single_size (insn
->opcode
)
3055 <= xg_get_build_instr_size (rule
->to_instr
))
3063 return (num_match
== 1);
3067 /* Return the maximum number of bytes this opcode can expand to. */
3070 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3072 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3074 int max_size
= xg_get_single_size (opcode
);
3076 assert (opcode
< table
->num_opcodes
);
3078 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3080 TransitionRule
*rule
= l
->rule
;
3081 BuildInstr
*build_list
;
3086 build_list
= rule
->to_instr
;
3087 if (is_unique_insn_expansion (rule
))
3089 assert (build_list
->typ
== INSTR_INSTR
);
3090 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3093 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3095 switch (build_list
->typ
)
3098 this_size
+= xg_get_single_size (build_list
->opcode
);
3100 case INSTR_LITERAL_DEF
:
3101 case INSTR_LABEL_DEF
:
3106 if (this_size
> max_size
)
3107 max_size
= this_size
;
3113 /* Return the maximum number of literal bytes this opcode can generate. */
3116 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3118 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3122 assert (opcode
< table
->num_opcodes
);
3124 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3126 TransitionRule
*rule
= l
->rule
;
3127 BuildInstr
*build_list
;
3132 build_list
= rule
->to_instr
;
3133 if (is_unique_insn_expansion (rule
))
3135 assert (build_list
->typ
== INSTR_INSTR
);
3136 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3139 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3141 switch (build_list
->typ
)
3143 case INSTR_LITERAL_DEF
:
3144 /* Hard-coded 4-byte literal. */
3148 case INSTR_LABEL_DEF
:
3153 if (this_size
> max_size
)
3154 max_size
= this_size
;
3161 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3163 int steps_taken
= 0;
3164 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3167 assert (insn
->insn_type
== ITYPE_INSN
);
3168 assert (insn
->opcode
< table
->num_opcodes
);
3170 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3172 TransitionRule
*rule
= l
->rule
;
3174 if (xg_instruction_matches_rule (insn
, rule
))
3176 if (steps_taken
== lateral_steps
)
3186 get_special_literal_symbol (void)
3188 static symbolS
*sym
= NULL
;
3191 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3197 get_special_label_symbol (void)
3199 static symbolS
*sym
= NULL
;
3202 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3208 xg_valid_literal_expression (const expressionS
*exp
)
3225 /* This will check to see if the value can be converted into the
3226 operand type. It will return TRUE if it does not fit. */
3229 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3231 uint32 valbuf
= value
;
3232 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3238 /* Assumes: All immeds are constants. Check that all constants fit
3239 into their immeds; return FALSE if not. */
3242 xg_immeds_fit (const TInsn
*insn
)
3244 xtensa_isa isa
= xtensa_default_isa
;
3248 assert (insn
->insn_type
== ITYPE_INSN
);
3249 for (i
= 0; i
< n
; ++i
)
3251 const expressionS
*expr
= &insn
->tok
[i
];
3252 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3259 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3264 /* The symbol should have a fixup associated with it. */
3273 /* This should only be called after we have an initial
3274 estimate of the addresses. */
3277 xg_symbolic_immeds_fit (const TInsn
*insn
,
3283 xtensa_isa isa
= xtensa_default_isa
;
3291 assert (insn
->insn_type
== ITYPE_INSN
);
3293 for (i
= 0; i
< n
; ++i
)
3295 const expressionS
*expr
= &insn
->tok
[i
];
3296 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3303 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3309 /* Check for the worst case. */
3310 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3315 /* We only allow symbols for pc-relative stuff.
3316 If pc_frag == 0, then we don't have frag locations yet. */
3320 /* If it is PC-relative and the symbol is not in the same
3321 segment as the PC.... */
3322 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0
3323 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3326 /* If it is a weak symbol, then assume it won't reach. This will
3327 only affect calls when longcalls are enabled, because if
3328 longcalls are disabled, then the call is marked as a specific
3330 if (S_IS_WEAK (expr
->X_add_symbol
))
3333 symbolP
= expr
->X_add_symbol
;
3334 sym_frag
= symbol_get_frag (symbolP
);
3335 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3336 pc
= pc_frag
->fr_address
+ pc_offset
;
3338 /* If frag has yet to be reached on this pass, assume it
3339 will move by STRETCH just as we did. If this is not so,
3340 it will be because some frag between grows, and that will
3341 force another pass. Beware zero-length frags. There
3342 should be a faster way to do this. */
3345 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3346 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3351 new_offset
= target
;
3352 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3353 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3358 /* The symbol should have a fixup associated with it. */
3367 /* Return TRUE on success. */
3370 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3375 memset (targ
, 0, sizeof (TInsn
));
3376 targ
->loc
= insn
->loc
;
3381 targ
->opcode
= bi
->opcode
;
3382 targ
->insn_type
= ITYPE_INSN
;
3383 targ
->is_specific_opcode
= FALSE
;
3385 for (; op
!= NULL
; op
= op
->next
)
3387 int op_num
= op
->op_num
;
3388 int op_data
= op
->op_data
;
3390 assert (op
->op_num
< MAX_INSN_ARGS
);
3392 if (targ
->ntok
<= op_num
)
3393 targ
->ntok
= op_num
+ 1;
3398 set_expr_const (&targ
->tok
[op_num
], op_data
);
3401 assert (op_data
< insn
->ntok
);
3402 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3405 sym
= get_special_literal_symbol ();
3406 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3409 sym
= get_special_label_symbol ();
3410 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3412 case OP_OPERAND_HI16U
:
3413 case OP_OPERAND_LOW16U
:
3414 assert (op_data
< insn
->ntok
);
3415 if (expr_is_const (&insn
->tok
[op_data
]))
3418 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3419 val
= xg_apply_userdef_op_fn (op
->typ
,
3422 targ
->tok
[op_num
].X_add_number
= val
;
3426 /* For const16 we can create relocations for these. */
3427 if (targ
->opcode
== XTENSA_UNDEFINED
3428 || (targ
->opcode
!= xtensa_const16_opcode
))
3430 assert (op_data
< insn
->ntok
);
3431 /* Need to build a O_lo16 or O_hi16. */
3432 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3433 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3435 if (op
->typ
== OP_OPERAND_HI16U
)
3436 targ
->tok
[op_num
].X_op
= O_hi16
;
3437 else if (op
->typ
== OP_OPERAND_LOW16U
)
3438 targ
->tok
[op_num
].X_op
= O_lo16
;
3445 /* currently handles:
3448 OP_OPERAND_F32MINUS */
3449 if (xg_has_userdef_op_fn (op
->typ
))
3451 assert (op_data
< insn
->ntok
);
3452 if (expr_is_const (&insn
->tok
[op_data
]))
3455 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3456 val
= xg_apply_userdef_op_fn (op
->typ
,
3459 targ
->tok
[op_num
].X_add_number
= val
;
3462 return FALSE
; /* We cannot use a relocation for this. */
3471 case INSTR_LITERAL_DEF
:
3473 targ
->opcode
= XTENSA_UNDEFINED
;
3474 targ
->insn_type
= ITYPE_LITERAL
;
3475 targ
->is_specific_opcode
= FALSE
;
3476 for (; op
!= NULL
; op
= op
->next
)
3478 int op_num
= op
->op_num
;
3479 int op_data
= op
->op_data
;
3480 assert (op
->op_num
< MAX_INSN_ARGS
);
3482 if (targ
->ntok
<= op_num
)
3483 targ
->ntok
= op_num
+ 1;
3488 assert (op_data
< insn
->ntok
);
3489 /* We can only pass resolvable literals through. */
3490 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3492 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3504 case INSTR_LABEL_DEF
:
3506 targ
->opcode
= XTENSA_UNDEFINED
;
3507 targ
->insn_type
= ITYPE_LABEL
;
3508 targ
->is_specific_opcode
= FALSE
;
3509 /* Literal with no ops is a label? */
3510 assert (op
== NULL
);
3521 /* Return TRUE on success. */
3524 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3526 for (; bi
!= NULL
; bi
= bi
->next
)
3528 TInsn
*next_insn
= istack_push_space (istack
);
3530 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3537 /* Return TRUE on valid expansion. */
3540 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3542 int stack_size
= istack
->ninsn
;
3543 int steps_taken
= 0;
3544 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3547 assert (insn
->insn_type
== ITYPE_INSN
);
3548 assert (insn
->opcode
< table
->num_opcodes
);
3550 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3552 TransitionRule
*rule
= l
->rule
;
3554 if (xg_instruction_matches_rule (insn
, rule
))
3556 if (lateral_steps
== steps_taken
)
3560 /* This is it. Expand the rule to the stack. */
3561 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3564 /* Check to see if it fits. */
3565 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3567 TInsn
*insn
= &istack
->insn
[i
];
3569 if (insn
->insn_type
== ITYPE_INSN
3570 && !tinsn_has_symbolic_operands (insn
)
3571 && !xg_immeds_fit (insn
))
3573 istack
->ninsn
= stack_size
;
3587 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3589 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3592 assert (insn
->insn_type
== ITYPE_INSN
);
3593 assert (insn
->opcode
< table
->num_opcodes
);
3595 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3597 TransitionRule
*rule
= l
->rule
;
3598 if (xg_instruction_matches_rule (insn
, rule
)
3599 && is_unique_insn_expansion (rule
))
3601 /* Is it a larger instruction? */
3602 if (xg_get_single_size (insn
->opcode
)
3603 <= xg_get_build_instr_size (rule
->to_instr
))
3605 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3614 /* Relax the assembly instruction at least "min_steps".
3615 Return the number of steps taken. */
3618 xg_assembly_relax (IStack
*istack
,
3621 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3622 offsetT pc_offset
, /* offset in fragment */
3623 int min_steps
, /* minimum conversion steps */
3624 long stretch
) /* number of bytes stretched so far */
3626 int steps_taken
= 0;
3628 /* assert (has no symbolic operands)
3629 Some of its immeds don't fit.
3630 Try to build a relaxed version.
3631 This may go through a couple of stages
3632 of single instruction transformations before
3635 TInsn single_target
;
3637 int lateral_steps
= 0;
3638 int istack_size
= istack
->ninsn
;
3640 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3641 && steps_taken
>= min_steps
)
3643 istack_push (istack
, insn
);
3646 current_insn
= *insn
;
3648 /* Walk through all of the single instruction expansions. */
3649 while (xg_is_single_relaxable_insn (¤t_insn
))
3651 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3653 assert (!error_val
);
3655 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3659 if (steps_taken
>= min_steps
)
3661 istack_push (istack
, &single_target
);
3665 current_insn
= single_target
;
3668 /* Now check for a multi-instruction expansion. */
3669 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3671 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3674 if (steps_taken
>= min_steps
)
3676 istack_push (istack
, ¤t_insn
);
3681 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3683 if (steps_taken
>= min_steps
)
3687 istack
->ninsn
= istack_size
;
3690 /* It's not going to work -- use the original. */
3691 istack_push (istack
, insn
);
3697 xg_force_frag_space (int size
)
3699 /* This may have the side effect of creating a new fragment for the
3700 space to go into. I just do not like the name of the "frag"
3707 xg_finish_frag (char *last_insn
,
3708 enum xtensa_relax_statesE frag_state
,
3709 enum xtensa_relax_statesE slot0_state
,
3711 bfd_boolean is_insn
)
3713 /* Finish off this fragment so that it has at LEAST the desired
3714 max_growth. If it doesn't fit in this fragment, close this one
3715 and start a new one. In either case, return a pointer to the
3716 beginning of the growth area. */
3720 xg_force_frag_space (max_growth
);
3722 old_frag
= frag_now
;
3724 frag_now
->fr_opcode
= last_insn
;
3726 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3728 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3729 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3731 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3732 xtensa_set_frag_assembly_state (frag_now
);
3734 /* Just to make sure that we did not split it up. */
3735 assert (old_frag
->fr_next
== frag_now
);
3739 /* Return TRUE if the target frag is one of the next non-empty frags. */
3742 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3747 for (; fragP
; fragP
= fragP
->fr_next
)
3749 if (fragP
== target
)
3751 if (fragP
->fr_fix
!= 0)
3753 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3755 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3756 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3758 if (fragP
->fr_type
== rs_space
)
3766 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3768 xtensa_isa isa
= xtensa_default_isa
;
3770 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3775 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3776 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3779 for (i
= 0; i
< num_ops
; i
++)
3781 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3787 if (target_op
== -1)
3790 if (insn
->ntok
<= target_op
)
3793 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3796 sym
= insn
->tok
[target_op
].X_add_symbol
;
3800 if (insn
->tok
[target_op
].X_add_number
!= 0)
3803 target_frag
= symbol_get_frag (sym
);
3804 if (target_frag
== NULL
)
3807 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3808 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3816 xg_add_branch_and_loop_targets (TInsn
*insn
)
3818 xtensa_isa isa
= xtensa_default_isa
;
3819 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3821 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3824 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3825 && insn
->tok
[i
].X_op
== O_symbol
)
3826 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3830 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3831 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3835 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3837 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3838 && insn
->tok
[i
].X_op
== O_symbol
)
3840 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3841 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3842 if (S_IS_DEFINED (sym
))
3843 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3850 /* Return FALSE if no error. */
3853 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3858 switch (instr_spec
->typ
)
3861 new_insn
->insn_type
= ITYPE_INSN
;
3862 new_insn
->opcode
= instr_spec
->opcode
;
3863 new_insn
->is_specific_opcode
= FALSE
;
3864 new_insn
->loc
= old_insn
->loc
;
3866 case INSTR_LITERAL_DEF
:
3867 new_insn
->insn_type
= ITYPE_LITERAL
;
3868 new_insn
->opcode
= XTENSA_UNDEFINED
;
3869 new_insn
->is_specific_opcode
= FALSE
;
3870 new_insn
->loc
= old_insn
->loc
;
3872 case INSTR_LABEL_DEF
:
3873 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3877 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3880 const expressionS
*src_exp
;
3886 /* The expression must be the constant. */
3887 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3888 exp
= &new_insn
->tok
[b_op
->op_num
];
3889 set_expr_const (exp
, b_op
->op_data
);
3893 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3894 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3895 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3896 exp
= &new_insn
->tok
[b_op
->op_num
];
3897 copy_expr (exp
, src_exp
);
3902 as_bad (_("can't handle generation of literal/labels yet"));
3906 as_bad (_("can't handle undefined OP TYPE"));
3911 new_insn
->ntok
= num_ops
;
3916 /* Return TRUE if it was simplified. */
3919 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3921 TransitionRule
*rule
;
3922 BuildInstr
*insn_spec
;
3924 if (old_insn
->is_specific_opcode
|| !density_supported
)
3927 rule
= xg_instruction_match (old_insn
);
3931 insn_spec
= rule
->to_instr
;
3932 /* There should only be one. */
3933 assert (insn_spec
!= NULL
);
3934 assert (insn_spec
->next
== NULL
);
3935 if (insn_spec
->next
!= NULL
)
3938 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3944 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3945 l32i.n. (2) Check the number of operands. (3) Place the instruction
3946 tokens into the stack or if we can relax it at assembly time, place
3947 multiple instructions/literals onto the stack. Return FALSE if no
3951 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3955 memset (&new_insn
, 0, sizeof (TInsn
));
3957 /* Narrow it if we can. xg_simplify_insn now does all the
3958 appropriate checking (e.g., for the density option). */
3959 if (xg_simplify_insn (orig_insn
, &new_insn
))
3960 orig_insn
= &new_insn
;
3962 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3964 if (orig_insn
->ntok
< noperands
)
3966 as_bad (_("found %d operands for '%s': Expected %d"),
3968 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3972 if (orig_insn
->ntok
> noperands
)
3973 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3975 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3978 /* If there are not enough operands, we will assert above. If there
3979 are too many, just cut out the extras here. */
3981 orig_insn
->ntok
= noperands
;
3985 Instructions with all constant immeds:
3986 Assemble them and relax the instruction if possible.
3987 Give error if not possible; no fixup needed.
3989 Instructions with symbolic immeds:
3990 Assemble them with a Fix up (that may cause instruction expansion).
3991 Also close out the fragment if the fixup may cause instruction expansion.
3993 There are some other special cases where we need alignment.
3994 1) before certain instructions with required alignment (OPCODE_ALIGN)
3995 2) before labels that have jumps (LABEL_ALIGN)
3996 3) after call instructions (RETURN_ALIGN)
3997 Multiple of these may be possible on the same fragment.
3998 If so, make sure to satisfy the required alignment.
3999 Then try to get the desired alignment. */
4001 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4004 if (orig_insn
->is_specific_opcode
|| !use_transform ())
4006 istack_push (istack
, orig_insn
);
4010 if (tinsn_has_symbolic_operands (orig_insn
))
4012 if (tinsn_has_complex_operands (orig_insn
))
4013 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4015 istack_push (istack
, orig_insn
);
4019 if (xg_immeds_fit (orig_insn
))
4020 istack_push (istack
, orig_insn
);
4022 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4029 /* Return TRUE if the section flags are marked linkonce
4030 or the name is .gnu.linkonce*. */
4033 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4035 flagword flags
, link_once_flags
;
4037 flags
= bfd_get_section_flags (abfd
, sec
);
4038 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4040 /* Flags might not be set yet. */
4041 if (!link_once_flags
)
4043 static size_t len
= sizeof ".gnu.linkonce.t.";
4045 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4046 link_once_flags
= SEC_LINK_ONCE
;
4048 return (link_once_flags
!= 0);
4053 xtensa_add_literal_sym (symbolS
*sym
)
4057 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4059 l
->next
= literal_syms
;
4065 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4067 static int lit_num
= 0;
4068 static char name
[256];
4071 sprintf (name
, ".L_lit_sym%d", lit_num
);
4073 /* Create a local symbol. If it is in a linkonce section, we have to
4074 be careful to make sure that if it is used in a relocation that the
4075 symbol will be in the output file. */
4076 if (get_is_linkonce_section (stdoutput
, sec
))
4078 symbolP
= symbol_new (name
, sec
, 0, frag
);
4079 S_CLEAR_EXTERNAL (symbolP
);
4080 /* symbolP->local = 1; */
4083 symbolP
= symbol_new (name
, sec
, 0, frag
);
4085 xtensa_add_literal_sym (symbolP
);
4087 frag
->tc_frag_data
.is_literal
= TRUE
;
4093 /* Currently all literals that are generated here are 32-bit L32R targets. */
4096 xg_assemble_literal (/* const */ TInsn
*insn
)
4099 symbolS
*lit_sym
= NULL
;
4101 /* size = 4 for L32R. It could easily be larger when we move to
4102 larger constants. Add a parameter later. */
4103 offsetT litsize
= 4;
4104 offsetT litalign
= 2; /* 2^2 = 4 */
4105 expressionS saved_loc
;
4106 expressionS
* emit_val
;
4108 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4110 assert (insn
->insn_type
== ITYPE_LITERAL
);
4111 assert (insn
->ntok
== 1); /* must be only one token here */
4113 xtensa_switch_to_literal_fragment (&state
);
4115 emit_val
= &insn
->tok
[0];
4116 if (emit_val
->X_op
== O_big
)
4118 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4121 /* This happens when someone writes a "movi a2, big_number". */
4122 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4123 _("invalid immediate"));
4124 xtensa_restore_emit_state (&state
);
4129 /* Force a 4-byte align here. Note that this opens a new frag, so all
4130 literals done with this function have a frag to themselves. That's
4131 important for the way text section literals work. */
4132 frag_align (litalign
, 0, 0);
4133 record_alignment (now_seg
, litalign
);
4135 if (emit_val
->X_op
== O_pltrel
)
4137 char *p
= frag_more (litsize
);
4138 xtensa_set_frag_assembly_state (frag_now
);
4139 if (emit_val
->X_add_symbol
)
4140 emit_val
->X_op
= O_symbol
;
4142 emit_val
->X_op
= O_constant
;
4143 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4144 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4147 emit_expr (emit_val
, litsize
);
4149 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4150 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4151 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4152 lit_sym
= frag_now
->fr_symbol
;
4153 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4156 xtensa_restore_emit_state (&state
);
4162 xg_assemble_literal_space (/* const */ int size
, int slot
)
4165 /* We might have to do something about this alignment. It only
4166 takes effect if something is placed here. */
4167 offsetT litalign
= 2; /* 2^2 = 4 */
4168 fragS
*lit_saved_frag
;
4170 assert (size
% 4 == 0);
4172 xtensa_switch_to_literal_fragment (&state
);
4174 /* Force a 4-byte align here. */
4175 frag_align (litalign
, 0, 0);
4176 record_alignment (now_seg
, litalign
);
4178 xg_force_frag_space (size
);
4180 lit_saved_frag
= frag_now
;
4181 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4182 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4183 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4184 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4187 xtensa_restore_emit_state (&state
);
4188 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4192 /* Put in a fixup record based on the opcode.
4193 Return TRUE on success. */
4196 xg_add_opcode_fix (TInsn
*tinsn
,
4204 xtensa_opcode opcode
= tinsn
->opcode
;
4205 bfd_reloc_code_real_type reloc
;
4206 reloc_howto_type
*howto
;
4210 reloc
= BFD_RELOC_NONE
;
4212 /* First try the special cases for "alternate" relocs. */
4213 if (opcode
== xtensa_l32r_opcode
)
4215 if (fragP
->tc_frag_data
.use_absolute_literals
)
4216 reloc
= encode_alt_reloc (slot
);
4218 else if (opcode
== xtensa_const16_opcode
)
4220 if (expr
->X_op
== O_lo16
)
4222 reloc
= encode_reloc (slot
);
4223 expr
->X_op
= O_symbol
;
4225 else if (expr
->X_op
== O_hi16
)
4227 reloc
= encode_alt_reloc (slot
);
4228 expr
->X_op
= O_symbol
;
4232 if (opnum
!= get_relaxable_immed (opcode
))
4234 as_bad (_("invalid relocation for operand %i of '%s'"),
4235 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4239 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4240 into the symbol table where the generic portions of the assembler
4241 won't know what to do with them. */
4242 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4244 as_bad (_("invalid expression for operand %i of '%s'"),
4245 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4249 /* Next try the generic relocs. */
4250 if (reloc
== BFD_RELOC_NONE
)
4251 reloc
= encode_reloc (slot
);
4252 if (reloc
== BFD_RELOC_NONE
)
4254 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4258 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4261 as_bad (_("undefined symbol for opcode \"%s\""),
4262 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4266 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4267 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4268 howto
->pc_relative
, reloc
);
4270 if (expr
->X_add_symbol
4271 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4272 || S_IS_WEAK (expr
->X_add_symbol
)))
4273 the_fix
->fx_plt
= TRUE
;
4275 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4276 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4277 the_fix
->tc_fix_data
.slot
= slot
;
4284 xg_emit_insn_to_buf (TInsn
*tinsn
,
4289 bfd_boolean build_fix
)
4291 static xtensa_insnbuf insnbuf
= NULL
;
4292 bfd_boolean has_symbolic_immed
= FALSE
;
4293 bfd_boolean ok
= TRUE
;
4295 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4297 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4298 if (has_symbolic_immed
&& build_fix
)
4301 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4302 expressionS
*exp
= &tinsn
->tok
[opnum
];
4304 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4307 fragP
->tc_frag_data
.is_insn
= TRUE
;
4308 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4314 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4316 symbolS
*sym
= get_special_literal_symbol ();
4320 assert (insn
->insn_type
== ITYPE_INSN
);
4321 for (i
= 0; i
< insn
->ntok
; i
++)
4322 if (insn
->tok
[i
].X_add_symbol
== sym
)
4323 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4329 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4331 symbolS
*sym
= get_special_label_symbol ();
4333 /* assert (!insn->is_literal); */
4334 for (i
= 0; i
< insn
->ntok
; i
++)
4335 if (insn
->tok
[i
].X_add_symbol
== sym
)
4336 insn
->tok
[i
].X_add_symbol
= label_sym
;
4341 /* Return TRUE if the instruction can write to the specified
4342 integer register. */
4345 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4349 xtensa_isa isa
= xtensa_default_isa
;
4351 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4353 for (i
= 0; i
< num_ops
; i
++)
4356 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4357 if ((inout
== 'o' || inout
== 'm')
4358 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4360 xtensa_regfile opnd_rf
=
4361 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4362 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4364 if ((insn
->tok
[i
].X_op
== O_register
)
4365 && (insn
->tok
[i
].X_add_number
== regnum
))
4375 is_bad_loopend_opcode (const TInsn
*tinsn
)
4377 xtensa_opcode opcode
= tinsn
->opcode
;
4379 if (opcode
== XTENSA_UNDEFINED
)
4382 if (opcode
== xtensa_call0_opcode
4383 || opcode
== xtensa_callx0_opcode
4384 || opcode
== xtensa_call4_opcode
4385 || opcode
== xtensa_callx4_opcode
4386 || opcode
== xtensa_call8_opcode
4387 || opcode
== xtensa_callx8_opcode
4388 || opcode
== xtensa_call12_opcode
4389 || opcode
== xtensa_callx12_opcode
4390 || opcode
== xtensa_isync_opcode
4391 || opcode
== xtensa_ret_opcode
4392 || opcode
== xtensa_ret_n_opcode
4393 || opcode
== xtensa_retw_opcode
4394 || opcode
== xtensa_retw_n_opcode
4395 || opcode
== xtensa_waiti_opcode
4396 || opcode
== xtensa_rsr_lcount_opcode
)
4403 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4404 This allows the debugger to add unaligned labels.
4405 Also, the assembler generates stabs labels that need
4406 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4409 is_unaligned_label (symbolS
*sym
)
4411 const char *name
= S_GET_NAME (sym
);
4412 static size_t fake_size
= 0;
4416 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4419 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4421 fake_size
= strlen (FAKE_LABEL_NAME
);
4424 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4425 && (name
[fake_size
] == 'F'
4426 || name
[fake_size
] == 'L'
4427 || (name
[fake_size
] == 'e'
4428 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4436 next_non_empty_frag (const fragS
*fragP
)
4438 fragS
*next_fragP
= fragP
->fr_next
;
4440 /* Sometimes an empty will end up here due storage allocation issues.
4441 So we have to skip until we find something legit. */
4442 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4443 next_fragP
= next_fragP
->fr_next
;
4445 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4453 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4455 xtensa_opcode out_opcode
;
4456 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4458 if (next_fragP
== NULL
)
4461 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4462 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4464 *opcode
= out_opcode
;
4472 frag_format_size (const fragS
*fragP
)
4474 static xtensa_insnbuf insnbuf
= NULL
;
4475 xtensa_isa isa
= xtensa_default_isa
;
4480 insnbuf
= xtensa_insnbuf_alloc (isa
);
4483 return XTENSA_UNDEFINED
;
4485 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
4487 fmt
= xtensa_format_decode (isa
, insnbuf
);
4488 if (fmt
== XTENSA_UNDEFINED
)
4489 return XTENSA_UNDEFINED
;
4490 fmt_size
= xtensa_format_length (isa
, fmt
);
4492 /* If the next format won't be changing due to relaxation, just
4493 return the length of the first format. */
4494 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4497 /* If during relaxation we have to pull an instruction out of a
4498 multi-slot instruction, we will return the more conservative
4499 number. This works because alignment on bigger instructions
4500 is more restrictive than alignment on smaller instructions.
4501 This is more conservative than we would like, but it happens
4504 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4507 /* If we aren't doing one of our own relaxations or it isn't
4508 slot-based, then the insn size won't change. */
4509 if (fragP
->fr_type
!= rs_machine_dependent
)
4511 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4514 /* If an instruction is about to grow, return the longer size. */
4515 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4516 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4519 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4520 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4527 next_frag_format_size (const fragS
*fragP
)
4529 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4530 return frag_format_size (next_fragP
);
4534 /* If the next legit fragment is an end-of-loop marker,
4535 switch its state so it will instantiate a NOP. */
4538 update_next_frag_state (fragS
*fragP
)
4540 fragS
*next_fragP
= fragP
->fr_next
;
4541 fragS
*new_target
= NULL
;
4545 /* We are guaranteed there will be one of these... */
4546 while (!(next_fragP
->fr_type
== rs_machine_dependent
4547 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4548 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4549 next_fragP
= next_fragP
->fr_next
;
4551 assert (next_fragP
->fr_type
== rs_machine_dependent
4552 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4553 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4555 /* ...and one of these. */
4556 new_target
= next_fragP
->fr_next
;
4557 while (!(new_target
->fr_type
== rs_machine_dependent
4558 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4559 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4560 new_target
= new_target
->fr_next
;
4562 assert (new_target
->fr_type
== rs_machine_dependent
4563 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4564 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4567 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4569 if (next_fragP
->fr_type
== rs_machine_dependent
4570 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4572 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4576 next_fragP
= next_fragP
->fr_next
;
4582 next_frag_is_branch_target (const fragS
*fragP
)
4584 /* Sometimes an empty will end up here due to storage allocation issues,
4585 so we have to skip until we find something legit. */
4586 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4588 if (fragP
->tc_frag_data
.is_branch_target
)
4590 if (fragP
->fr_fix
!= 0)
4598 next_frag_is_loop_target (const fragS
*fragP
)
4600 /* Sometimes an empty will end up here due storage allocation issues.
4601 So we have to skip until we find something legit. */
4602 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4604 if (fragP
->tc_frag_data
.is_loop_target
)
4606 if (fragP
->fr_fix
!= 0)
4614 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4616 const fragS
*next_fragp
= fragp
->fr_next
;
4617 xtensa_opcode next_opcode
;
4619 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4622 /* Sometimes an empty will end up here due to storage allocation issues,
4623 so we have to skip until we find something legit. */
4624 while (next_fragp
->fr_fix
== 0)
4625 next_fragp
= next_fragp
->fr_next
;
4627 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4630 /* There is some implicit knowledge encoded in here.
4631 The LOOP instructions that are NOT RELAX_IMMED have
4632 been relaxed. Note that we can assume that the LOOP
4633 instruction is in slot 0 because loops aren't bundleable. */
4634 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4635 return get_expanded_loop_offset (next_opcode
);
4641 /* Mark a location where we can later insert literal frags. Update
4642 the section's literal_pool_loc, so subsequent literals can be
4643 placed nearest to their use. */
4646 xtensa_mark_literal_pool_location (void)
4648 /* Any labels pointing to the current location need
4649 to be adjusted to after the literal pool. */
4651 fragS
*pool_location
;
4653 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4656 frag_align (2, 0, 0);
4657 record_alignment (now_seg
, 2);
4659 /* We stash info in the fr_var of these frags
4660 so we can later move the literal's fixes into this
4661 frchain's fix list. We can use fr_var because fr_var's
4662 interpretation depends solely on the fr_type and subtype. */
4663 pool_location
= frag_now
;
4664 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4665 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4666 xtensa_set_frag_assembly_state (frag_now
);
4667 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4668 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4669 xtensa_set_frag_assembly_state (frag_now
);
4671 /* Now put a frag into the literal pool that points to this location. */
4672 set_literal_pool_location (now_seg
, pool_location
);
4673 xtensa_switch_to_non_abs_literal_fragment (&s
);
4674 frag_align (2, 0, 0);
4675 record_alignment (now_seg
, 2);
4677 /* Close whatever frag is there. */
4678 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4679 xtensa_set_frag_assembly_state (frag_now
);
4680 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4681 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4682 xtensa_restore_emit_state (&s
);
4683 xtensa_set_frag_assembly_state (frag_now
);
4687 /* Build a nop of the correct size into tinsn. */
4690 build_nop (TInsn
*tinsn
, int size
)
4696 tinsn
->opcode
= xtensa_nop_n_opcode
;
4698 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4699 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4703 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4705 tinsn
->opcode
= xtensa_or_opcode
;
4706 set_expr_const (&tinsn
->tok
[0], 1);
4707 set_expr_const (&tinsn
->tok
[1], 1);
4708 set_expr_const (&tinsn
->tok
[2], 1);
4712 tinsn
->opcode
= xtensa_nop_opcode
;
4714 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4719 /* Assemble a NOP of the requested size in the buffer. User must have
4720 allocated "buf" with at least "size" bytes. */
4723 assemble_nop (size_t size
, char *buf
)
4725 static xtensa_insnbuf insnbuf
= NULL
;
4728 build_nop (&tinsn
, size
);
4731 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4733 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4734 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4738 /* Return the number of bytes for the offset of the expanded loop
4739 instruction. This should be incorporated into the relaxation
4740 specification but is hard-coded here. This is used to auto-align
4741 the loop instruction. It is invalid to call this function if the
4742 configuration does not have loops or if the opcode is not a loop
4746 get_expanded_loop_offset (xtensa_opcode opcode
)
4748 /* This is the OFFSET of the loop instruction in the expanded loop.
4749 This MUST correspond directly to the specification of the loop
4750 expansion. It will be validated on fragment conversion. */
4751 assert (opcode
!= XTENSA_UNDEFINED
);
4752 if (opcode
== xtensa_loop_opcode
)
4754 if (opcode
== xtensa_loopnez_opcode
)
4756 if (opcode
== xtensa_loopgtz_opcode
)
4758 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4764 get_literal_pool_location (segT seg
)
4766 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4771 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4773 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4777 /* Set frag assembly state should be called when a new frag is
4778 opened and after a frag has been closed. */
4781 xtensa_set_frag_assembly_state (fragS
*fragP
)
4783 if (!density_supported
)
4784 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4786 /* This function is called from subsegs_finish, which is called
4787 after xtensa_end, so we can't use "use_transform" or
4788 "use_schedule" here. */
4789 if (!directive_state
[directive_transform
])
4790 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4791 fragP
->tc_frag_data
.use_absolute_literals
=
4792 directive_state
[directive_absolute_literals
];
4793 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4798 relaxable_section (asection
*sec
)
4800 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4805 xtensa_find_unmarked_state_frags (void)
4809 /* Walk over each fragment of all of the current segments. For each
4810 unmarked fragment, mark it with the same info as the previous
4812 for (seclist
= &stdoutput
->sections
;
4813 seclist
&& *seclist
;
4814 seclist
= &(*seclist
)->next
)
4816 segT sec
= *seclist
;
4817 segment_info_type
*seginfo
;
4820 flags
= bfd_get_section_flags (stdoutput
, sec
);
4821 if (flags
& SEC_DEBUGGING
)
4823 if (!(flags
& SEC_ALLOC
))
4826 seginfo
= seg_info (sec
);
4827 if (seginfo
&& seginfo
->frchainP
)
4829 fragS
*last_fragP
= 0;
4830 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4831 fragP
= fragP
->fr_next
)
4833 if (fragP
->fr_fix
!= 0
4834 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4836 if (last_fragP
== 0)
4838 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4839 _("assembly state not set for first frag in section %s"),
4844 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4845 fragP
->tc_frag_data
.is_no_density
=
4846 last_fragP
->tc_frag_data
.is_no_density
;
4847 fragP
->tc_frag_data
.is_no_transform
=
4848 last_fragP
->tc_frag_data
.is_no_transform
;
4849 fragP
->tc_frag_data
.use_absolute_literals
=
4850 last_fragP
->tc_frag_data
.use_absolute_literals
;
4853 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4862 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4864 void *unused ATTRIBUTE_UNUSED
)
4866 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4867 segment_info_type
*seginfo
= seg_info (sec
);
4868 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4870 if (flags
& SEC_CODE
)
4872 xtensa_isa isa
= xtensa_default_isa
;
4873 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4874 while (frag
!= NULL
)
4876 if (frag
->tc_frag_data
.is_branch_target
)
4882 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4883 fmt
= xtensa_format_decode (isa
, insnbuf
);
4884 op_size
= xtensa_format_length (isa
, fmt
);
4885 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4886 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
4887 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4888 _("unaligned branch target: %d bytes at 0x%lx"),
4889 op_size
, frag
->fr_address
);
4891 frag
= frag
->fr_next
;
4893 xtensa_insnbuf_free (isa
, insnbuf
);
4899 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4901 void *unused ATTRIBUTE_UNUSED
)
4903 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4904 segment_info_type
*seginfo
= seg_info (sec
);
4905 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4906 xtensa_isa isa
= xtensa_default_isa
;
4908 if (flags
& SEC_CODE
)
4910 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4911 while (frag
!= NULL
)
4913 if (frag
->tc_frag_data
.is_first_loop_insn
)
4919 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4920 fmt
= xtensa_format_decode (isa
, insnbuf
);
4921 op_size
= xtensa_format_length (isa
, fmt
);
4922 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4924 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
4925 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4926 _("unaligned loop: %d bytes at 0x%lx"),
4927 op_size
, frag
->fr_address
);
4929 frag
= frag
->fr_next
;
4931 xtensa_insnbuf_free (isa
, insnbuf
);
4937 xg_apply_tentative_value (fixS
*fixP
, valueT val
)
4939 xtensa_isa isa
= xtensa_default_isa
;
4940 static xtensa_insnbuf insnbuf
= NULL
;
4941 static xtensa_insnbuf slotbuf
= NULL
;
4944 bfd_boolean alt_reloc
;
4945 xtensa_opcode opcode
;
4946 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4948 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4950 as_fatal (_("unexpected fix"));
4954 insnbuf
= xtensa_insnbuf_alloc (isa
);
4955 slotbuf
= xtensa_insnbuf_alloc (isa
);
4958 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
4959 fmt
= xtensa_format_decode (isa
, insnbuf
);
4960 if (fmt
== XTENSA_UNDEFINED
)
4961 as_fatal (_("undecodable fix"));
4962 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4963 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4964 if (opcode
== XTENSA_UNDEFINED
)
4965 as_fatal (_("undecodable fix"));
4967 /* CONST16 immediates are not PC-relative, despite the fact that we
4968 reuse the normal PC-relative operand relocations for the low part
4969 of a CONST16 operand. The code in tc_gen_reloc does not decode
4970 the opcodes so it is more convenient to detect this special case
4972 if (opcode
== xtensa_const16_opcode
)
4975 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4976 get_relaxable_immed (opcode
), val
,
4977 fixP
->fx_file
, fixP
->fx_line
);
4979 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4980 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
4984 /* External Functions and Other GAS Hooks. */
4987 xtensa_target_format (void)
4989 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4994 xtensa_file_arch_init (bfd
*abfd
)
4996 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5001 md_number_to_chars (char *buf
, valueT val
, int n
)
5003 if (target_big_endian
)
5004 number_to_chars_bigendian (buf
, val
, n
);
5006 number_to_chars_littleendian (buf
, val
, n
);
5010 /* This function is called once, at assembler startup time. It should
5011 set up all the tables, etc. that the MD part of the assembler will
5017 segT current_section
= now_seg
;
5018 int current_subsec
= now_subseg
;
5021 xtensa_default_isa
= xtensa_isa_init (0, 0);
5022 isa
= xtensa_default_isa
;
5026 /* Set up the .literal, .fini.literal and .init.literal sections. */
5027 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5028 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5029 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5030 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5031 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5033 subseg_set (current_section
, current_subsec
);
5035 xg_init_vinsn (&cur_vinsn
);
5037 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5038 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5039 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5040 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5041 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5042 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5043 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5044 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5045 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5046 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5047 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5048 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5049 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5050 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5051 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5052 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5053 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5054 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5055 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5056 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5057 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5058 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5059 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5060 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5061 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5062 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5063 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5064 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5065 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5067 init_op_placement_info_table ();
5069 /* Set up the assembly state. */
5070 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5071 xtensa_set_frag_assembly_state (frag_now
);
5075 /* TC_INIT_FIX_DATA hook */
5078 xtensa_init_fix_data (fixS
*x
)
5080 x
->tc_fix_data
.slot
= 0;
5081 x
->tc_fix_data
.X_add_symbol
= NULL
;
5082 x
->tc_fix_data
.X_add_number
= 0;
5086 /* tc_frob_label hook */
5089 xtensa_frob_label (symbolS
*sym
)
5091 /* Since the label was already attached to a frag associated with the
5092 previous basic block, it now needs to be reset to the current frag. */
5093 symbol_set_frag (sym
, frag_now
);
5094 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5096 if (generating_literals
)
5097 xtensa_add_literal_sym (sym
);
5099 xtensa_add_insn_label (sym
);
5101 if (symbol_get_tc (sym
)->is_loop_target
5102 && (get_last_insn_flags (now_seg
, now_subseg
)
5103 & FLAG_IS_BAD_LOOPEND
) != 0)
5104 as_bad (_("invalid last instruction for a zero-overhead loop"));
5106 /* No target aligning in the absolute section. */
5107 if (now_seg
!= absolute_section
5108 && do_align_targets ()
5109 && !is_unaligned_label (sym
)
5110 && !generating_literals
)
5112 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 /* The only time this type of frag grows is when there is a
5116 negatable branch that needs to be relaxed as the last
5117 instruction in a zero-overhead loop. Because alignment frags
5118 are so common, marking them all as possibly growing four
5119 bytes makes any worst-case analysis appear much worse than it
5120 is. So, we make fr_var not actually reflect the amount of
5121 memory allocated at the end of this frag, but rather the
5122 amount of memory this frag might grow. The "4, 0" below
5123 allocates four bytes at the end of the frag for room to grow
5124 if we need to relax a loop end with a NOP. Frags prior to
5125 this one might grow to align this one, but the frag itself
5126 won't grow unless it meets the condition above. */
5128 #define RELAX_LOOP_END_BYTES 4
5130 frag_var (rs_machine_dependent
,
5131 RELAX_LOOP_END_BYTES
, (int) freq
,
5132 RELAX_DESIRE_ALIGN_IF_TARGET
,
5133 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5134 xtensa_set_frag_assembly_state (frag_now
);
5135 xtensa_move_labels (frag_now
, 0, TRUE
);
5138 /* We need to mark the following properties even if we aren't aligning. */
5140 /* If the label is already known to be a branch target, i.e., a
5141 forward branch, mark the frag accordingly. Backward branches
5142 are handled by xg_add_branch_and_loop_targets. */
5143 if (symbol_get_tc (sym
)->is_branch_target
)
5144 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5146 /* Loops only go forward, so they can be identified here. */
5147 if (symbol_get_tc (sym
)->is_loop_target
)
5148 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5152 /* tc_unrecognized_line hook */
5155 xtensa_unrecognized_line (int ch
)
5160 if (cur_vinsn
.inside_bundle
== 0)
5162 /* PR8110: Cannot emit line number info inside a FLIX bundle
5163 when using --gstabs. Temporarily disable debug info. */
5164 generate_lineno_debug ();
5165 if (debug_type
== DEBUG_STABS
)
5167 xt_saved_debug_type
= debug_type
;
5168 debug_type
= DEBUG_NONE
;
5171 cur_vinsn
.inside_bundle
= 1;
5175 as_bad (_("extra opening brace"));
5181 if (cur_vinsn
.inside_bundle
)
5182 finish_vinsn (&cur_vinsn
);
5185 as_bad (_("extra closing brace"));
5190 as_bad (_("syntax error"));
5197 /* md_flush_pending_output hook */
5200 xtensa_flush_pending_output (void)
5202 if (cur_vinsn
.inside_bundle
)
5203 as_bad (_("missing closing brace"));
5205 /* If there is a non-zero instruction fragment, close it. */
5206 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5208 frag_wane (frag_now
);
5210 xtensa_set_frag_assembly_state (frag_now
);
5212 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5214 xtensa_clear_insn_labels ();
5218 /* We had an error while parsing an instruction. The string might look
5219 like this: "insn arg1, arg2 }". If so, we need to see the closing
5220 brace and reset some fields. Otherwise, the vinsn never gets closed
5221 and the num_slots field will grow past the end of the array of slots,
5222 and bad things happen. */
5225 error_reset_cur_vinsn (void)
5227 if (cur_vinsn
.inside_bundle
)
5229 if (*input_line_pointer
== '}'
5230 || *(input_line_pointer
- 1) == '}'
5231 || *(input_line_pointer
- 2) == '}')
5232 xg_clear_vinsn (&cur_vinsn
);
5238 md_assemble (char *str
)
5240 xtensa_isa isa
= xtensa_default_isa
;
5243 bfd_boolean has_underbar
= FALSE
;
5244 char *arg_strings
[MAX_INSN_ARGS
];
5246 TInsn orig_insn
; /* Original instruction from the input. */
5248 tinsn_init (&orig_insn
);
5250 /* Split off the opcode. */
5251 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5252 opname
= xmalloc (opnamelen
+ 1);
5253 memcpy (opname
, str
, opnamelen
);
5254 opname
[opnamelen
] = '\0';
5256 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5259 as_bad (_("syntax error"));
5263 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5266 /* Check for an underbar prefix. */
5269 has_underbar
= TRUE
;
5273 orig_insn
.insn_type
= ITYPE_INSN
;
5275 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5277 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5278 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5280 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5281 if (fmt
== XTENSA_UNDEFINED
)
5283 as_bad (_("unknown opcode or format name '%s'"), opname
);
5284 error_reset_cur_vinsn ();
5287 if (!cur_vinsn
.inside_bundle
)
5289 as_bad (_("format names only valid inside bundles"));
5290 error_reset_cur_vinsn ();
5293 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5294 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5296 cur_vinsn
.format
= fmt
;
5297 free (has_underbar
? opname
- 1 : opname
);
5298 error_reset_cur_vinsn ();
5302 /* Special case: The call instructions should be marked "specific opcode"
5303 to keep them from expanding. */
5304 if (!use_longcalls () && is_direct_call_opcode (orig_insn
.opcode
))
5305 orig_insn
.is_specific_opcode
= TRUE
;
5307 /* Parse the arguments. */
5308 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5310 as_bad (_("syntax error"));
5311 error_reset_cur_vinsn ();
5315 /* Free the opcode and argument strings, now that they've been parsed. */
5316 free (has_underbar
? opname
- 1 : opname
);
5318 while (num_args
-- > 0)
5319 free (arg_strings
[num_args
]);
5321 /* Get expressions for invisible operands. */
5322 if (get_invisible_operands (&orig_insn
))
5324 error_reset_cur_vinsn ();
5328 /* Check for the right number and type of arguments. */
5329 if (tinsn_check_arguments (&orig_insn
))
5331 error_reset_cur_vinsn ();
5335 dwarf2_where (&orig_insn
.loc
);
5337 xg_add_branch_and_loop_targets (&orig_insn
);
5339 /* Special-case for "entry" instruction. */
5340 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5342 /* Check that the third opcode (#2) is >= 16. */
5343 if (orig_insn
.ntok
>= 3)
5345 expressionS
*exp
= &orig_insn
.tok
[2];
5349 if (exp
->X_add_number
< 16)
5350 as_warn (_("entry instruction with stack decrement < 16"));
5354 as_warn (_("entry instruction with non-constant decrement"));
5360 assemble_tokens (opcode, tok, ntok);
5361 expand the tokens from the orig_insn into the
5362 stack of instructions that will not expand
5363 unless required at relaxation time. */
5365 if (!cur_vinsn
.inside_bundle
)
5366 emit_single_op (&orig_insn
);
5367 else /* We are inside a bundle. */
5369 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5370 cur_vinsn
.num_slots
++;
5371 if (*input_line_pointer
== '}'
5372 || *(input_line_pointer
- 1) == '}'
5373 || *(input_line_pointer
- 2) == '}')
5374 finish_vinsn (&cur_vinsn
);
5377 /* We've just emitted a new instruction so clear the list of labels. */
5378 xtensa_clear_insn_labels ();
5382 /* HANDLE_ALIGN hook */
5384 /* For a .align directive, we mark the previous block with the alignment
5385 information. This will be placed in the object file in the
5386 property section corresponding to this section. */
5389 xtensa_handle_align (fragS
*fragP
)
5392 && ! fragP
->tc_frag_data
.is_literal
5393 && (fragP
->fr_type
== rs_align
5394 || fragP
->fr_type
== rs_align_code
)
5395 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5396 && fragP
->fr_offset
> 0
5397 && now_seg
!= bss_section
)
5399 fragP
->tc_frag_data
.is_align
= TRUE
;
5400 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5403 if (fragP
->fr_type
== rs_align_test
)
5406 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5408 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5409 _("unaligned entry instruction"));
5414 /* TC_FRAG_INIT hook */
5417 xtensa_frag_init (fragS
*frag
)
5419 xtensa_set_frag_assembly_state (frag
);
5424 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5430 /* Round up a section size to the appropriate boundary. */
5433 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5435 return size
; /* Byte alignment is fine. */
5440 md_pcrel_from (fixS
*fixP
)
5443 static xtensa_insnbuf insnbuf
= NULL
;
5444 static xtensa_insnbuf slotbuf
= NULL
;
5447 xtensa_opcode opcode
;
5450 xtensa_isa isa
= xtensa_default_isa
;
5451 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5452 bfd_boolean alt_reloc
;
5457 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5462 insnbuf
= xtensa_insnbuf_alloc (isa
);
5463 slotbuf
= xtensa_insnbuf_alloc (isa
);
5466 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5467 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
5468 fmt
= xtensa_format_decode (isa
, insnbuf
);
5470 if (fmt
== XTENSA_UNDEFINED
)
5471 as_fatal (_("bad instruction format"));
5473 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5474 as_fatal (_("invalid relocation"));
5476 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5477 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5479 /* Check for "alternate" relocation (operand not specified). */
5480 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5482 if (opcode
!= xtensa_l32r_opcode
5483 && opcode
!= xtensa_const16_opcode
)
5484 as_fatal (_("invalid relocation for '%s' instruction"),
5485 xtensa_opcode_name (isa
, opcode
));
5489 opnum
= get_relaxable_immed (opcode
);
5491 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5492 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5494 as_bad_where (fixP
->fx_file
,
5496 _("invalid relocation for operand %d of '%s'"),
5497 opnum
, xtensa_opcode_name (isa
, opcode
));
5500 return 0 - opnd_value
;
5504 /* TC_FORCE_RELOCATION hook */
5507 xtensa_force_relocation (fixS
*fix
)
5509 switch (fix
->fx_r_type
)
5511 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5512 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5513 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5514 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5515 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5516 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5517 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5518 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5519 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5520 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5521 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5522 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5523 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5524 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5525 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5526 case BFD_RELOC_VTABLE_INHERIT
:
5527 case BFD_RELOC_VTABLE_ENTRY
:
5533 if (linkrelax
&& fix
->fx_addsy
5534 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5537 return generic_force_reloc (fix
);
5541 /* NO_PSEUDO_DOT hook */
5543 /* This function has nothing to do with pseudo dots, but this is the
5544 nearest macro to where the check needs to take place. FIXME: This
5548 xtensa_check_inside_bundle (void)
5550 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5551 as_bad (_("directives are not valid inside bundles"));
5553 /* This function must always return FALSE because it is called via a
5554 macro that has nothing to do with bundling. */
5559 /* md_elf_section_change_hook */
5562 xtensa_elf_section_change_hook (void)
5564 /* Set up the assembly state. */
5565 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5566 xtensa_set_frag_assembly_state (frag_now
);
5570 /* tc_fix_adjustable hook */
5573 xtensa_fix_adjustable (fixS
*fixP
)
5575 /* An offset is not allowed in combination with the difference of two
5576 symbols, but that cannot be easily detected after a local symbol
5577 has been adjusted to a (section+offset) form. Return 0 so that such
5578 an fix will not be adjusted. */
5579 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5580 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5583 /* We need the symbol name for the VTABLE entries. */
5584 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5585 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5589 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || S_IS_WEAK (fixP
->fx_addsy
)))
5593 /* We may someday want to enable this code to preserve relocations for
5594 non-PC-relative fixes, possibly under control of a PIC flag. */
5595 return (fixP
->fx_pcrel
5596 || (fixP
->fx_subsy
!= NULL
5597 && (S_GET_SEGMENT (fixP
->fx_subsy
)
5598 == S_GET_SEGMENT (fixP
->fx_addsy
)))
5599 || S_IS_LOCAL (fixP
->fx_addsy
));
5607 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
5609 if (fixP
->fx_pcrel
== 0 && fixP
->fx_addsy
== 0)
5611 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5613 switch (fixP
->fx_r_type
)
5615 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5619 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5620 as_bad (_("unhandled local relocation fix %s"),
5621 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5627 /* The only one we support that isn't an instruction field. */
5628 md_number_to_chars (fixpos
, *valP
, fixP
->fx_size
);
5632 case BFD_RELOC_VTABLE_INHERIT
:
5633 case BFD_RELOC_VTABLE_ENTRY
:
5638 as_bad (_("unhandled local relocation fix %s"),
5639 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5646 md_atof (int type
, char *litP
, int *sizeP
)
5649 LITTLENUM_TYPE words
[4];
5665 return "bad call to md_atof";
5668 t
= atof_ieee (input_line_pointer
, type
, words
);
5670 input_line_pointer
= t
;
5674 for (i
= prec
- 1; i
>= 0; i
--)
5677 if (target_big_endian
)
5678 idx
= (prec
- 1 - i
);
5680 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5689 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5691 return total_frag_text_expansion (fragP
);
5695 /* Translate internal representation of relocation info to BFD target
5699 tc_gen_reloc (asection
*section
, fixS
*fixp
)
5702 bfd_boolean apply_tentative_value
= FALSE
;
5704 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5705 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5706 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5707 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5709 /* Make sure none of our internal relocations make it this far.
5710 They'd better have been fully resolved by this point. */
5711 assert ((int) fixp
->fx_r_type
> 0);
5713 if (linkrelax
&& fixp
->fx_subsy
5714 && (fixp
->fx_r_type
== BFD_RELOC_8
5715 || fixp
->fx_r_type
== BFD_RELOC_16
5716 || fixp
->fx_r_type
== BFD_RELOC_32
))
5719 bfd_vma diff_value
, diff_mask
= 0;
5721 switch (fixp
->fx_r_type
)
5724 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5729 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5734 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5736 diff_mask
= 0xffffffff;
5742 /* An offset is only allowed when it results from adjusting a local
5743 symbol into a section-relative offset. If the offset came from the
5744 original expression, tc_fix_adjustable will have prevented the fix
5745 from being converted to a section-relative form so that we can flag
5747 if (fixp
->fx_offset
!= 0 && !symbol_section_p (fixp
->fx_addsy
))
5749 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5750 _("cannot represent subtraction with an offset"));
5751 free (reloc
->sym_ptr_ptr
);
5756 assert (S_GET_SEGMENT (fixp
->fx_addsy
)
5757 == S_GET_SEGMENT (fixp
->fx_subsy
));
5759 diff_value
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5760 - S_GET_VALUE (fixp
->fx_subsy
));
5762 /* Check for overflow. */
5763 if ((diff_value
& ~diff_mask
) != 0)
5765 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5766 _("value of %ld too large"), diff_value
);
5767 free (reloc
->sym_ptr_ptr
);
5772 md_number_to_chars (fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
,
5773 diff_value
, diff_size
);
5774 reloc
->addend
= fixp
->fx_offset
- diff_value
;
5778 reloc
->addend
= fixp
->fx_offset
;
5780 switch (fixp
->fx_r_type
)
5782 case BFD_RELOC_XTENSA_SLOT0_OP
:
5783 case BFD_RELOC_XTENSA_SLOT1_OP
:
5784 case BFD_RELOC_XTENSA_SLOT2_OP
:
5785 case BFD_RELOC_XTENSA_SLOT3_OP
:
5786 case BFD_RELOC_XTENSA_SLOT4_OP
:
5787 case BFD_RELOC_XTENSA_SLOT5_OP
:
5788 case BFD_RELOC_XTENSA_SLOT6_OP
:
5789 case BFD_RELOC_XTENSA_SLOT7_OP
:
5790 case BFD_RELOC_XTENSA_SLOT8_OP
:
5791 case BFD_RELOC_XTENSA_SLOT9_OP
:
5792 case BFD_RELOC_XTENSA_SLOT10_OP
:
5793 case BFD_RELOC_XTENSA_SLOT11_OP
:
5794 case BFD_RELOC_XTENSA_SLOT12_OP
:
5795 case BFD_RELOC_XTENSA_SLOT13_OP
:
5796 case BFD_RELOC_XTENSA_SLOT14_OP
:
5797 /* As a special case, the immediate value for a CONST16 opcode
5798 should not be applied, since this kind of relocation is
5799 handled specially for CONST16 and is not really PC-relative.
5800 Rather than decode the opcode here, just wait and handle it
5801 in xg_apply_tentative_value. */
5802 apply_tentative_value
= TRUE
;
5805 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5806 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5807 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5808 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5809 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5810 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5811 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5812 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5813 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5814 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5815 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5816 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5817 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5818 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5819 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5820 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5822 case BFD_RELOC_XTENSA_PLT
:
5823 case BFD_RELOC_VTABLE_INHERIT
:
5824 case BFD_RELOC_VTABLE_ENTRY
:
5827 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5828 as_warn (_("emitting simplification relocation"));
5832 as_warn (_("emitting unknown relocation"));
5836 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5837 if (reloc
->howto
== NULL
)
5839 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5840 _("cannot represent `%s' relocation in object file"),
5841 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5842 free (reloc
->sym_ptr_ptr
);
5847 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5848 as_fatal (_("internal error? cannot generate `%s' relocation"),
5849 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5851 /* Write the tentative value of a PC-relative relocation to a local symbol
5852 into the instruction. The value will be ignored by the linker, and it
5853 makes the object file disassembly readable when the linkrelax flag is
5854 set and all branch targets are encoded in relocations. */
5856 if (linkrelax
&& apply_tentative_value
&& fixp
->fx_pcrel
)
5859 assert (fixp
->fx_addsy
);
5860 if (S_GET_SEGMENT (fixp
->fx_addsy
) == section
&& !fixp
->fx_plt
5861 && !S_FORCE_RELOC (fixp
->fx_addsy
, 1))
5863 val
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5864 - md_pcrel_from (fixp
));
5865 xg_apply_tentative_value (fixp
, val
);
5873 /* Checks for resource conflicts between instructions. */
5875 /* The func unit stuff could be implemented as bit-vectors rather
5876 than the iterative approach here. If it ends up being too
5877 slow, we will switch it. */
5880 new_resource_table (void *data
,
5883 unit_num_copies_func uncf
,
5884 opcode_num_units_func onuf
,
5885 opcode_funcUnit_use_unit_func ouuf
,
5886 opcode_funcUnit_use_stage_func ousf
)
5889 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5891 rt
->cycles
= cycles
;
5892 rt
->allocated_cycles
= cycles
;
5894 rt
->unit_num_copies
= uncf
;
5895 rt
->opcode_num_units
= onuf
;
5896 rt
->opcode_unit_use
= ouuf
;
5897 rt
->opcode_unit_stage
= ousf
;
5899 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5900 for (i
= 0; i
< cycles
; i
++)
5901 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5908 clear_resource_table (resource_table
*rt
)
5911 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5912 for (j
= 0; j
< rt
->num_units
; j
++)
5913 rt
->units
[i
][j
] = 0;
5917 /* We never shrink it, just fake it into thinking so. */
5920 resize_resource_table (resource_table
*rt
, int cycles
)
5924 rt
->cycles
= cycles
;
5925 if (cycles
<= rt
->allocated_cycles
)
5928 old_cycles
= rt
->allocated_cycles
;
5929 rt
->allocated_cycles
= cycles
;
5931 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5932 for (i
= 0; i
< old_cycles
; i
++)
5933 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5934 for (i
= old_cycles
; i
< cycles
; i
++)
5935 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5940 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5943 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5945 for (i
= 0; i
< uses
; i
++)
5947 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5948 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5949 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5950 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5951 if (copies_in_use
>= copies
)
5959 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5962 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5964 for (i
= 0; i
< uses
; i
++)
5966 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5967 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5968 /* Note that this allows resources to be oversubscribed. That's
5969 essential to the way the optional scheduler works.
5970 resources_available reports when a resource is over-subscribed,
5971 so it's easy to tell. */
5972 rt
->units
[stage
+ cycle
][unit
]++;
5978 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5981 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5983 for (i
= 0; i
< uses
; i
++)
5985 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5986 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5987 rt
->units
[stage
+ cycle
][unit
]--;
5988 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5993 /* Wrapper functions make parameterized resource reservation
5997 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5999 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6005 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6007 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6012 /* Note that this function does not check issue constraints, but
6013 solely whether the hardware is available to execute the given
6014 instructions together. It also doesn't check if the tinsns
6015 write the same state, or access the same tieports. That is
6016 checked by check_t1_t2_reads_and_writes. */
6019 resources_conflict (vliw_insn
*vinsn
)
6022 static resource_table
*rt
= NULL
;
6024 /* This is the most common case by far. Optimize it. */
6025 if (vinsn
->num_slots
== 1)
6030 xtensa_isa isa
= xtensa_default_isa
;
6031 rt
= new_resource_table
6032 (isa
, xtensa_isa_num_pipe_stages (isa
),
6033 xtensa_isa_num_funcUnits (isa
),
6034 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6035 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6036 opcode_funcUnit_use_unit
,
6037 opcode_funcUnit_use_stage
);
6040 clear_resource_table (rt
);
6042 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6044 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6046 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6053 /* finish_vinsn, emit_single_op and helper functions. */
6055 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6056 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6057 static void bundle_single_op (TInsn
*);
6058 static void xg_assemble_vliw_tokens (vliw_insn
*);
6061 /* We have reached the end of a bundle; emit into the frag. */
6064 finish_vinsn (vliw_insn
*vinsn
)
6071 if (find_vinsn_conflicts (vinsn
))
6073 xg_clear_vinsn (vinsn
);
6077 /* First, find a format that works. */
6078 if (vinsn
->format
== XTENSA_UNDEFINED
)
6079 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6081 if (vinsn
->format
== XTENSA_UNDEFINED
)
6083 as_where (&file_name
, &line
);
6084 as_bad_where (file_name
, line
,
6085 _("couldn't find a valid instruction format"));
6086 fprintf (stderr
, _(" ops were: "));
6087 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6088 fprintf (stderr
, _(" %s;"),
6089 xtensa_opcode_name (xtensa_default_isa
,
6090 vinsn
->slots
[i
].opcode
));
6091 fprintf (stderr
, _("\n"));
6092 xg_clear_vinsn (vinsn
);
6096 if (vinsn
->num_slots
6097 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6099 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6100 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6101 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6103 xg_clear_vinsn (vinsn
);
6107 if (resources_conflict (vinsn
))
6109 as_where (&file_name
, &line
);
6110 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6111 fprintf (stderr
, " ops were: ");
6112 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6113 fprintf (stderr
, " %s;",
6114 xtensa_opcode_name (xtensa_default_isa
,
6115 vinsn
->slots
[i
].opcode
));
6116 fprintf (stderr
, "\n");
6117 xg_clear_vinsn (vinsn
);
6121 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6123 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6125 symbolS
*lit_sym
= NULL
;
6127 bfd_boolean e
= FALSE
;
6128 bfd_boolean saved_density
= density_supported
;
6130 /* We don't want to narrow ops inside multi-slot bundles. */
6131 if (vinsn
->num_slots
> 1)
6132 density_supported
= FALSE
;
6134 istack_init (&slotstack
);
6135 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6137 vinsn
->slots
[i
].opcode
=
6138 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6140 vinsn
->slots
[i
].ntok
= 0;
6143 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6149 density_supported
= saved_density
;
6153 xg_clear_vinsn (vinsn
);
6157 for (j
= 0; j
< slotstack
.ninsn
- 1; j
++)
6159 TInsn
*insn
= &slotstack
.insn
[j
];
6160 if (insn
->insn_type
== ITYPE_LITERAL
)
6162 assert (lit_sym
== NULL
);
6163 lit_sym
= xg_assemble_literal (insn
);
6168 xg_resolve_literals (insn
, lit_sym
);
6169 emit_single_op (insn
);
6173 if (vinsn
->num_slots
> 1)
6175 if (opcode_fits_format_slot
6176 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6179 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6183 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6184 if (vinsn
->format
== XTENSA_UNDEFINED
)
6185 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6187 vinsn
->slots
[i
].opcode
6188 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6191 vinsn
->slots
[i
].ntok
= 0;
6196 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6197 vinsn
->format
= XTENSA_UNDEFINED
;
6202 /* Now check resource conflicts on the modified bundle. */
6203 if (resources_conflict (vinsn
))
6205 as_where (&file_name
, &line
);
6206 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6207 fprintf (stderr
, " ops were: ");
6208 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6209 fprintf (stderr
, " %s;",
6210 xtensa_opcode_name (xtensa_default_isa
,
6211 vinsn
->slots
[i
].opcode
));
6212 fprintf (stderr
, "\n");
6213 xg_clear_vinsn (vinsn
);
6217 /* First, find a format that works. */
6218 if (vinsn
->format
== XTENSA_UNDEFINED
)
6219 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6221 xg_assemble_vliw_tokens (vinsn
);
6223 xg_clear_vinsn (vinsn
);
6227 /* Given an vliw instruction, what conflicts are there in register
6228 usage and in writes to states and queues?
6230 This function does two things:
6231 1. Reports an error when a vinsn contains illegal combinations
6232 of writes to registers states or queues.
6233 2. Marks individual tinsns as not relaxable if the combination
6234 contains antidependencies.
6236 Job 2 handles things like swap semantics in instructions that need
6237 to be relaxed. For example,
6241 normally would be relaxed to
6246 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6248 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6250 then we can't relax it into
6253 { add a0, a1, a0 ; add a2, a0, a4 ; }
6255 because the value of a0 is trashed before the second add can read it. */
6257 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6260 find_vinsn_conflicts (vliw_insn
*vinsn
)
6264 xtensa_isa isa
= xtensa_default_isa
;
6266 assert (!past_xtensa_end
);
6268 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6270 TInsn
*op1
= &vinsn
->slots
[i
];
6271 if (op1
->is_specific_opcode
)
6272 op1
->keep_wide
= TRUE
;
6274 op1
->keep_wide
= FALSE
;
6277 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6279 TInsn
*op1
= &vinsn
->slots
[i
];
6281 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6284 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6288 TInsn
*op2
= &vinsn
->slots
[j
];
6289 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6290 switch (conflict_type
)
6293 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6294 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6295 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6298 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6299 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6300 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6303 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6304 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6305 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6308 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6309 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6310 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6313 /* Everything is OK. */
6316 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6317 || conflict_type
== 'a');
6324 as_bad (_("multiple branches or jumps in the same bundle"));
6332 /* Check how the state used by t1 and t2 relate.
6335 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6336 case B: no relationship between what is read and written (both could
6337 read the same reg though)
6338 case C: t1 writes a register t2 writes (a register conflict within a
6340 case D: t1 writes a state that t2 also writes
6341 case E: t1 writes a tie queue that t2 also writes
6342 case F: two volatile queue accesses
6346 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6348 xtensa_isa isa
= xtensa_default_isa
;
6349 xtensa_regfile t1_regfile
, t2_regfile
;
6351 int t1_base_reg
, t1_last_reg
;
6352 int t2_base_reg
, t2_last_reg
;
6353 char t1_inout
, t2_inout
;
6355 char conflict
= 'b';
6360 bfd_boolean t1_volatile
= FALSE
;
6361 bfd_boolean t2_volatile
= FALSE
;
6363 /* Check registers. */
6364 for (j
= 0; j
< t2
->ntok
; j
++)
6366 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6369 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6370 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6371 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6373 for (i
= 0; i
< t1
->ntok
; i
++)
6375 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6378 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6380 if (t1_regfile
!= t2_regfile
)
6383 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6384 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6386 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6387 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6389 if (t1_inout
== 'm' || t1_inout
== 'o'
6390 || t2_inout
== 'm' || t2_inout
== 'o')
6397 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6398 t1_last_reg
= (t1_base_reg
6399 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6401 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6403 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6405 if (t1_reg
!= t2_reg
)
6408 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6414 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6420 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6428 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6429 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6430 for (j
= 0; j
< t2_states
; j
++)
6432 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6433 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6434 for (i
= 0; i
< t1_states
; i
++)
6436 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6437 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6441 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6447 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6453 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6458 /* Check tieports. */
6459 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6460 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6461 for (j
= 0; j
< t2_interfaces
; j
++)
6463 xtensa_interface t2_int
6464 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6465 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6467 t2_inout
= xtensa_interface_inout (isa
, j
);
6468 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6471 for (i
= 0; i
< t1_interfaces
; i
++)
6473 xtensa_interface t1_int
6474 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6475 int t1_class
= xtensa_interface_class_id (isa
, t2_int
);
6477 t1_inout
= xtensa_interface_inout (isa
, i
);
6478 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6481 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6484 if (t1_int
!= t2_int
)
6487 if (t2_inout
== 'i' && t1_inout
== 'o')
6493 if (t1_inout
== 'i' && t2_inout
== 'o')
6499 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6508 static xtensa_format
6509 xg_find_narrowest_format (vliw_insn
*vinsn
)
6511 /* Right now we assume that the ops within the vinsn are properly
6512 ordered for the slots that the programmer wanted them in. In
6513 other words, we don't rearrange the ops in hopes of finding a
6514 better format. The scheduler handles that. */
6516 xtensa_isa isa
= xtensa_default_isa
;
6517 xtensa_format format
;
6518 vliw_insn v_copy
= *vinsn
;
6519 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6521 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6524 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6528 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6530 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6532 v_copy
.slots
[slot
].opcode
=
6533 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6534 v_copy
.slots
[slot
].ntok
= 0;
6537 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6540 else if (v_copy
.num_slots
> 1)
6543 /* Try the widened version. */
6544 if (!v_copy
.slots
[slot
].keep_wide
6545 && !v_copy
.slots
[slot
].is_specific_opcode
6546 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6547 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6548 && opcode_fits_format_slot (widened
.opcode
,
6551 /* The xg_is_narrow clause requires some explanation:
6553 addi can be "widened" to an addmi, which is then
6554 expanded to an addmi/addi pair if the immediate
6555 requires it, but here we must have a single widen
6558 xg_is_narrow tells us that addi isn't really
6559 narrow. The widen_spec_list says that there are
6562 v_copy
.slots
[slot
] = widened
;
6567 if (fit
== v_copy
.num_slots
)
6570 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6571 vinsn
->format
= format
;
6577 if (format
== xtensa_isa_num_formats (isa
))
6578 return XTENSA_UNDEFINED
;
6584 /* Return the additional space needed in a frag
6585 for possible relaxations of any ops in a VLIW insn.
6586 Also fill out the relaxations that might be required of
6587 each tinsn in the vinsn. */
6590 relaxation_requirements (vliw_insn
*vinsn
)
6592 int extra_space
= 0;
6595 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6597 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6598 if (!tinsn_has_symbolic_operands (tinsn
))
6600 /* A narrow instruction could be widened later to help
6601 alignment issues. */
6602 if (xg_is_narrow_insn (tinsn
)
6603 && !tinsn
->is_specific_opcode
6604 && vinsn
->num_slots
== 1)
6606 /* Difference in bytes between narrow and wide insns... */
6608 tinsn
->subtype
= RELAX_NARROW
;
6609 tinsn
->record_fix
= TRUE
;
6614 tinsn
->record_fix
= FALSE
;
6615 /* No extra_space needed. */
6620 if (workaround_b_j_loop_end
6621 && tinsn
->opcode
== xtensa_jx_opcode
6622 && use_transform ())
6624 /* Add 2 of these. */
6625 extra_space
+= 3; /* for the nop size */
6626 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6629 /* Need to assemble it with space for the relocation. */
6630 if (xg_is_relaxable_insn (tinsn
, 0)
6631 && !tinsn
->is_specific_opcode
)
6633 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6634 int max_literal_size
=
6635 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6637 tinsn
->literal_space
= max_literal_size
;
6639 tinsn
->subtype
= RELAX_IMMED
;
6640 tinsn
->record_fix
= FALSE
;
6641 extra_space
+= max_size
;
6645 tinsn
->record_fix
= TRUE
;
6646 /* No extra space needed. */
6655 bundle_single_op (TInsn
*orig_insn
)
6657 xtensa_isa isa
= xtensa_default_isa
;
6662 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6663 assert (v
.format
!= XTENSA_UNDEFINED
);
6664 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6667 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6670 v
.slots
[slot
].opcode
=
6671 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6672 v
.slots
[slot
].ntok
= 0;
6673 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6676 v
.slots
[slot
] = *orig_insn
;
6679 for ( ; slot
< v
.num_slots
; slot
++)
6681 v
.slots
[slot
].opcode
=
6682 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6683 v
.slots
[slot
].ntok
= 0;
6684 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6693 emit_single_op (TInsn
*orig_insn
)
6696 IStack istack
; /* put instructions into here */
6697 symbolS
*lit_sym
= NULL
;
6698 symbolS
*label_sym
= NULL
;
6700 istack_init (&istack
);
6702 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6703 Because the scheduling and bundling characteristics of movi and
6704 l32r or const16 are so different, we can do much better if we relax
6705 it prior to scheduling and bundling, rather than after. */
6706 if ((orig_insn
->opcode
== xtensa_movi_opcode
6707 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6708 && !cur_vinsn
.inside_bundle
6709 && (orig_insn
->tok
[1].X_op
== O_symbol
6710 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6711 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6713 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6716 for (i
= 0; i
< istack
.ninsn
; i
++)
6718 TInsn
*insn
= &istack
.insn
[i
];
6719 switch (insn
->insn_type
)
6722 assert (lit_sym
== NULL
);
6723 lit_sym
= xg_assemble_literal (insn
);
6727 static int relaxed_sym_idx
= 0;
6728 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6729 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6731 assert (label_sym
== NULL
);
6732 label_sym
= symbol_find_or_make (label
);
6739 xg_resolve_literals (insn
, lit_sym
);
6741 xg_resolve_labels (insn
, label_sym
);
6742 bundle_single_op (insn
);
6754 total_frag_text_expansion (fragS
*fragP
)
6757 int total_expansion
= 0;
6759 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6760 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6762 return total_expansion
;
6766 /* Emit a vliw instruction to the current fragment. */
6769 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6771 bfd_boolean finish_frag
= FALSE
;
6772 bfd_boolean is_jump
= FALSE
;
6773 bfd_boolean is_branch
= FALSE
;
6774 xtensa_isa isa
= xtensa_default_isa
;
6780 struct dwarf2_line_info best_loc
;
6782 best_loc
.line
= INT_MAX
;
6784 if (generating_literals
)
6786 static int reported
= 0;
6788 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6789 _("cannot assemble into a literal fragment"));
6796 if (frag_now_fix () != 0
6797 && (! frag_now
->tc_frag_data
.is_insn
6798 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6799 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6800 || (directive_state
[directive_absolute_literals
]
6801 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6803 frag_wane (frag_now
);
6805 xtensa_set_frag_assembly_state (frag_now
);
6808 if (workaround_a0_b_retw
6809 && vinsn
->num_slots
== 1
6810 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6811 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6812 && use_transform ())
6814 has_a0_b_retw
= TRUE
;
6816 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6817 After the first assembly pass we will check all of them and
6818 add a nop if needed. */
6819 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6820 frag_var (rs_machine_dependent
, 4, 4,
6821 RELAX_ADD_NOP_IF_A0_B_RETW
,
6822 frag_now
->fr_symbol
,
6823 frag_now
->fr_offset
,
6825 xtensa_set_frag_assembly_state (frag_now
);
6826 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6827 frag_var (rs_machine_dependent
, 4, 4,
6828 RELAX_ADD_NOP_IF_A0_B_RETW
,
6829 frag_now
->fr_symbol
,
6830 frag_now
->fr_offset
,
6832 xtensa_set_frag_assembly_state (frag_now
);
6835 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6837 /* See if the instruction implies an aligned section. */
6838 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6839 record_alignment (now_seg
, 2);
6841 /* Also determine the best line number for debug info. */
6842 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6843 ? vinsn
->slots
[i
].loc
: best_loc
;
6846 /* Special cases for instructions that force an alignment... */
6847 /* None of these opcodes are bundle-able. */
6848 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6852 xtensa_set_frag_assembly_state (frag_now
);
6853 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6855 max_fill
= get_text_align_max_fill_size
6856 (get_text_align_power (xtensa_fetch_width
),
6857 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6859 if (use_transform ())
6860 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6861 RELAX_ALIGN_NEXT_OPCODE
,
6862 frag_now
->fr_symbol
,
6863 frag_now
->fr_offset
,
6866 frag_var (rs_machine_dependent
, 0, 0,
6867 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6868 xtensa_set_frag_assembly_state (frag_now
);
6870 xtensa_move_labels (frag_now
, 0, FALSE
);
6873 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6874 && !vinsn
->slots
[0].is_specific_opcode
)
6876 xtensa_mark_literal_pool_location ();
6877 xtensa_move_labels (frag_now
, 0, TRUE
);
6878 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6881 if (vinsn
->num_slots
== 1)
6883 if (workaround_a0_b_retw
&& use_transform ())
6884 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6885 is_register_writer (&vinsn
->slots
[0], "a", 0));
6887 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6888 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6891 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6893 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6895 extra_space
= relaxation_requirements (vinsn
);
6897 /* vinsn_to_insnbuf will produce the error. */
6898 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6900 f
= (char *) frag_more (insn_size
+ extra_space
);
6901 xtensa_set_frag_assembly_state (frag_now
);
6902 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6905 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6906 if (vinsn
->format
== XTENSA_UNDEFINED
)
6909 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
6911 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6913 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6915 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6916 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6917 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6918 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6919 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6920 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6921 if (tinsn
->literal_space
!= 0)
6922 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6924 if (tinsn
->subtype
== RELAX_NARROW
)
6925 assert (vinsn
->num_slots
== 1);
6926 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6928 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6931 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6932 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6936 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6937 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6941 frag_variant (rs_machine_dependent
,
6942 extra_space
, extra_space
, RELAX_SLOTS
,
6943 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6944 xtensa_set_frag_assembly_state (frag_now
);
6947 /* Special cases for loops:
6948 close_loop_end should be inserted AFTER short_loop.
6949 Make sure that CLOSE loops are processed BEFORE short_loops
6950 when converting them. */
6952 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6953 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6954 && !vinsn
->slots
[0].is_specific_opcode
)
6956 if (workaround_short_loop
&& use_transform ())
6958 maybe_has_short_loop
= TRUE
;
6959 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6960 frag_var (rs_machine_dependent
, 4, 4,
6961 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6962 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6963 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6964 frag_var (rs_machine_dependent
, 4, 4,
6965 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6966 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6969 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6970 loop at least 12 bytes away from another loop's end. */
6971 if (workaround_close_loop_end
&& use_transform ())
6973 maybe_has_close_loop_end
= TRUE
;
6974 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6975 frag_var (rs_machine_dependent
, 12, 12,
6976 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6977 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6981 if (use_transform ())
6985 assert (finish_frag
);
6986 frag_var (rs_machine_dependent
,
6987 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6989 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6990 xtensa_set_frag_assembly_state (frag_now
);
6992 else if (is_branch
&& align_targets
)
6994 assert (finish_frag
);
6995 frag_var (rs_machine_dependent
,
6996 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6997 RELAX_MAYBE_UNREACHABLE
,
6998 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6999 xtensa_set_frag_assembly_state (frag_now
);
7000 frag_var (rs_machine_dependent
,
7002 RELAX_MAYBE_DESIRE_ALIGN
,
7003 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7004 xtensa_set_frag_assembly_state (frag_now
);
7008 /* Now, if the original opcode was a call... */
7009 if (do_align_targets ()
7010 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7012 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7013 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7014 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7015 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7016 xtensa_set_frag_assembly_state (frag_now
);
7019 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7021 frag_wane (frag_now
);
7023 xtensa_set_frag_assembly_state (frag_now
);
7028 /* xtensa_end and helper functions. */
7030 static void xtensa_cleanup_align_frags (void);
7031 static void xtensa_fix_target_frags (void);
7032 static void xtensa_mark_narrow_branches (void);
7033 static void xtensa_mark_zcl_first_insns (void);
7034 static void xtensa_fix_a0_b_retw_frags (void);
7035 static void xtensa_fix_b_j_loop_end_frags (void);
7036 static void xtensa_fix_close_loop_end_frags (void);
7037 static void xtensa_fix_short_loop_frags (void);
7038 static void xtensa_sanity_check (void);
7043 directive_balance ();
7044 xtensa_flush_pending_output ();
7046 past_xtensa_end
= TRUE
;
7048 xtensa_move_literals ();
7050 xtensa_reorder_segments ();
7051 xtensa_cleanup_align_frags ();
7052 xtensa_fix_target_frags ();
7053 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7054 xtensa_fix_a0_b_retw_frags ();
7055 if (workaround_b_j_loop_end
)
7056 xtensa_fix_b_j_loop_end_frags ();
7058 /* "close_loop_end" should be processed BEFORE "short_loop". */
7059 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7060 xtensa_fix_close_loop_end_frags ();
7062 if (workaround_short_loop
&& maybe_has_short_loop
)
7063 xtensa_fix_short_loop_frags ();
7064 xtensa_mark_narrow_branches ();
7065 xtensa_mark_zcl_first_insns ();
7067 xtensa_sanity_check ();
7072 xtensa_cleanup_align_frags (void)
7076 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7079 /* Walk over all of the fragments in a subsection. */
7080 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7082 if ((fragP
->fr_type
== rs_align
7083 || fragP
->fr_type
== rs_align_code
7084 || (fragP
->fr_type
== rs_machine_dependent
7085 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7086 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7087 && fragP
->fr_fix
== 0)
7089 fragS
*next
= fragP
->fr_next
;
7092 && next
->fr_fix
== 0
7093 && next
->fr_type
== rs_machine_dependent
7094 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7097 next
= next
->fr_next
;
7100 /* If we don't widen branch targets, then they
7101 will be easier to align. */
7102 if (fragP
->tc_frag_data
.is_branch_target
7103 && fragP
->fr_opcode
== fragP
->fr_literal
7104 && fragP
->fr_type
== rs_machine_dependent
7105 && fragP
->fr_subtype
== RELAX_SLOTS
7106 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7108 if (fragP
->fr_type
== rs_machine_dependent
7109 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7110 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7116 /* Re-process all of the fragments looking to convert all of the
7117 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7118 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7119 If the next fragment starts with a loop target, AND the previous
7120 fragment can be expanded to negate the branch, convert this to a
7121 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7123 static bfd_boolean
frag_can_negate_branch (fragS
*);
7126 xtensa_fix_target_frags (void)
7130 /* When this routine is called, all of the subsections are still intact
7131 so we walk over subsections instead of sections. */
7132 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7134 bfd_boolean prev_frag_can_negate_branch
= FALSE
;
7137 /* Walk over all of the fragments in a subsection. */
7138 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7140 if (fragP
->fr_type
== rs_machine_dependent
7141 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7143 if (next_frag_is_loop_target (fragP
))
7145 if (prev_frag_can_negate_branch
)
7147 fragP
->fr_subtype
= RELAX_LOOP_END
;
7148 /* See the comment near the frag_var with a
7149 RELAX_DESIRE_ALIGN to see why we do this. */
7150 fragP
->fr_var
= RELAX_LOOP_END_BYTES
;
7154 if (next_frag_is_branch_target (fragP
))
7155 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7160 else if (next_frag_is_branch_target (fragP
))
7161 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7165 if (fragP
->fr_fix
!= 0)
7166 prev_frag_can_negate_branch
= FALSE
;
7167 if (frag_can_negate_branch (fragP
))
7168 prev_frag_can_negate_branch
= TRUE
;
7175 frag_can_negate_branch (fragS
*fragP
)
7177 xtensa_isa isa
= xtensa_default_isa
;
7181 if (fragP
->fr_type
!= rs_machine_dependent
7182 || fragP
->fr_subtype
!= RELAX_SLOTS
)
7185 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7187 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, vinsn
.format
); slot
++)
7189 if ((fragP
->tc_frag_data
.slot_subtypes
[slot
] == RELAX_IMMED
)
7190 && xtensa_opcode_is_branch (isa
, vinsn
.slots
[slot
].opcode
) == 1)
7198 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7201 xtensa_mark_narrow_branches (void)
7205 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7208 /* Walk over all of the fragments in a subsection. */
7209 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7211 if (fragP
->fr_type
== rs_machine_dependent
7212 && fragP
->fr_subtype
== RELAX_SLOTS
7213 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7216 const expressionS
*expr
;
7219 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7220 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7222 expr
= &vinsn
.slots
[0].tok
[1];
7223 symbolP
= expr
->X_add_symbol
;
7225 if (vinsn
.num_slots
== 1
7226 && xtensa_opcode_is_branch (xtensa_default_isa
,
7227 vinsn
.slots
[0].opcode
)
7228 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7229 && is_narrow_branch_guaranteed_in_range (fragP
,
7232 fragP
->fr_subtype
= RELAX_SLOTS
;
7233 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7241 /* A branch is typically widened only when its target is out of
7242 range. However, we would like to widen them to align a subsequent
7243 branch target when possible.
7245 Because the branch relaxation code is so convoluted, the optimal solution
7246 (combining the two cases) is difficult to get right in all circumstances.
7247 We therefore go with an "almost as good" solution, where we only
7248 use for alignment narrow branches that definitely will not expand to a
7249 jump and a branch. These functions find and mark these cases. */
7251 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7252 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7253 We start counting beginning with the frag after the 2-byte branch, so the
7254 maximum offset is (4 - 2) + 63 = 65. */
7255 #define MAX_IMMED6 65
7257 static size_t unrelaxed_frag_max_size (fragS
*);
7260 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7262 const expressionS
*expr
= &tinsn
->tok
[1];
7263 symbolS
*symbolP
= expr
->X_add_symbol
;
7264 fragS
*target_frag
= symbol_get_frag (symbolP
);
7265 size_t max_distance
= expr
->X_add_number
;
7266 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7267 if (is_branch_jmp_to_next (tinsn
, fragP
))
7270 /* The branch doesn't branch over it's own frag,
7271 but over the subsequent ones. */
7272 fragP
= fragP
->fr_next
;
7273 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7275 max_distance
+= unrelaxed_frag_max_size (fragP
);
7276 fragP
= fragP
->fr_next
;
7278 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7285 xtensa_mark_zcl_first_insns (void)
7289 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7292 /* Walk over all of the fragments in a subsection. */
7293 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7295 if (fragP
->fr_type
== rs_machine_dependent
7296 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7297 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7299 /* Find the loop frag. */
7300 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7301 /* Find the first insn frag. */
7302 targ_frag
= next_non_empty_frag (targ_frag
);
7304 /* Of course, sometimes (mostly for toy test cases) a
7305 zero-cost loop instruction is the last in a section. */
7308 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7309 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7318 /* Re-process all of the fragments looking to convert all of the
7319 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7320 conditional branch or a retw/retw.n, convert this frag to one that
7321 will generate a NOP. In any case close it off with a .fill 0. */
7323 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7326 xtensa_fix_a0_b_retw_frags (void)
7330 /* When this routine is called, all of the subsections are still intact
7331 so we walk over subsections instead of sections. */
7332 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7336 /* Walk over all of the fragments in a subsection. */
7337 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7339 if (fragP
->fr_type
== rs_machine_dependent
7340 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7342 if (next_instrs_are_b_retw (fragP
))
7344 if (fragP
->tc_frag_data
.is_no_transform
)
7345 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7347 relax_frag_add_nop (fragP
);
7357 next_instrs_are_b_retw (fragS
*fragP
)
7359 xtensa_opcode opcode
;
7361 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7362 static xtensa_insnbuf insnbuf
= NULL
;
7363 static xtensa_insnbuf slotbuf
= NULL
;
7364 xtensa_isa isa
= xtensa_default_isa
;
7367 bfd_boolean branch_seen
= FALSE
;
7371 insnbuf
= xtensa_insnbuf_alloc (isa
);
7372 slotbuf
= xtensa_insnbuf_alloc (isa
);
7375 if (next_fragP
== NULL
)
7378 /* Check for the conditional branch. */
7379 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7380 fmt
= xtensa_format_decode (isa
, insnbuf
);
7381 if (fmt
== XTENSA_UNDEFINED
)
7384 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7386 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7387 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7389 branch_seen
= (branch_seen
7390 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7396 offset
+= xtensa_format_length (isa
, fmt
);
7397 if (offset
== next_fragP
->fr_fix
)
7399 next_fragP
= next_non_empty_frag (next_fragP
);
7403 if (next_fragP
== NULL
)
7406 /* Check for the retw/retw.n. */
7407 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7408 fmt
= xtensa_format_decode (isa
, insnbuf
);
7410 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7411 have no problems. */
7412 if (fmt
== XTENSA_UNDEFINED
7413 || xtensa_format_num_slots (isa
, fmt
) != 1)
7416 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7417 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7419 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7426 /* Re-process all of the fragments looking to convert all of the
7427 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7428 loop end label, convert this frag to one that will generate a NOP.
7429 In any case close it off with a .fill 0. */
7431 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7434 xtensa_fix_b_j_loop_end_frags (void)
7438 /* When this routine is called, all of the subsections are still intact
7439 so we walk over subsections instead of sections. */
7440 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7444 /* Walk over all of the fragments in a subsection. */
7445 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7447 if (fragP
->fr_type
== rs_machine_dependent
7448 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7450 if (next_instr_is_loop_end (fragP
))
7452 if (fragP
->tc_frag_data
.is_no_transform
)
7453 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7455 relax_frag_add_nop (fragP
);
7465 next_instr_is_loop_end (fragS
*fragP
)
7467 const fragS
*next_fragP
;
7469 if (next_frag_is_loop_target (fragP
))
7472 next_fragP
= next_non_empty_frag (fragP
);
7473 if (next_fragP
== NULL
)
7476 if (!next_frag_is_loop_target (next_fragP
))
7479 /* If the size is >= 3 then there is more than one instruction here.
7480 The hardware bug will not fire. */
7481 if (next_fragP
->fr_fix
> 3)
7488 /* Re-process all of the fragments looking to convert all of the
7489 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7490 not MY loop's loop end within 12 bytes, add enough nops here to
7491 make it at least 12 bytes away. In any case close it off with a
7494 static size_t min_bytes_to_other_loop_end (fragS
*, fragS
*, offsetT
, size_t);
7497 xtensa_fix_close_loop_end_frags (void)
7501 /* When this routine is called, all of the subsections are still intact
7502 so we walk over subsections instead of sections. */
7503 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7507 fragS
*current_target
= NULL
;
7508 offsetT current_offset
= 0;
7510 /* Walk over all of the fragments in a subsection. */
7511 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7513 if (fragP
->fr_type
== rs_machine_dependent
7514 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7515 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7516 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7519 /* Read it. If the instruction is a loop, get the target. */
7521 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7522 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7523 t_insn
.opcode
) == 1)
7525 /* Get the current fragment target. */
7526 if (fragP
->tc_frag_data
.slot_symbols
[0])
7528 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7529 current_target
= symbol_get_frag (sym
);
7530 current_offset
= fragP
->fr_offset
;
7536 && fragP
->fr_type
== rs_machine_dependent
7537 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7540 size_t bytes_added
= 0;
7542 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7543 /* Max out at 12. */
7544 min_bytes
= min_bytes_to_other_loop_end
7545 (fragP
->fr_next
, current_target
, current_offset
,
7546 REQUIRED_LOOP_DIVIDING_BYTES
);
7548 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7550 if (fragP
->tc_frag_data
.is_no_transform
)
7551 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7554 while (min_bytes
+ bytes_added
7555 < REQUIRED_LOOP_DIVIDING_BYTES
)
7559 if (fragP
->fr_var
< length
)
7560 as_fatal (_("fr_var %lu < length %d"),
7561 fragP
->fr_var
, length
);
7564 assemble_nop (length
,
7565 fragP
->fr_literal
+ fragP
->fr_fix
);
7566 fragP
->fr_fix
+= length
;
7567 fragP
->fr_var
-= length
;
7569 bytes_added
+= length
;
7575 assert (fragP
->fr_type
!= rs_machine_dependent
7576 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7582 static size_t unrelaxed_frag_min_size (fragS
*);
7585 min_bytes_to_other_loop_end (fragS
*fragP
,
7586 fragS
*current_target
,
7587 offsetT current_offset
,
7591 fragS
*current_fragP
;
7593 for (current_fragP
= fragP
;
7595 current_fragP
= current_fragP
->fr_next
)
7597 if (current_fragP
->tc_frag_data
.is_loop_target
7598 && current_fragP
!= current_target
)
7599 return offset
+ current_offset
;
7601 offset
+= unrelaxed_frag_min_size (current_fragP
);
7603 if (offset
+ current_offset
>= max_size
)
7611 unrelaxed_frag_min_size (fragS
*fragP
)
7613 size_t size
= fragP
->fr_fix
;
7616 if (fragP
->fr_type
== rs_fill
)
7617 size
+= fragP
->fr_offset
;
7624 unrelaxed_frag_max_size (fragS
*fragP
)
7626 size_t size
= fragP
->fr_fix
;
7627 switch (fragP
->fr_type
)
7630 /* Empty frags created by the obstack allocation scheme
7631 end up with type 0. */
7636 size
+= fragP
->fr_offset
;
7644 /* No further adjustments needed. */
7646 case rs_machine_dependent
:
7647 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7648 size
+= fragP
->fr_var
;
7651 /* We had darn well better know how big it is. */
7660 /* Re-process all of the fragments looking to convert all
7661 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7664 1) the instruction size count to the loop end label
7665 is too short (<= 2 instructions),
7666 2) loop has a jump or branch in it
7669 1) workaround_all_short_loops is TRUE
7670 2) The generating loop was a 'loopgtz' or 'loopnez'
7671 3) the instruction size count to the loop end label is too short
7673 then convert this frag (and maybe the next one) to generate a NOP.
7674 In any case close it off with a .fill 0. */
7676 static size_t count_insns_to_loop_end (fragS
*, bfd_boolean
, size_t);
7677 static bfd_boolean
branch_before_loop_end (fragS
*);
7680 xtensa_fix_short_loop_frags (void)
7684 /* When this routine is called, all of the subsections are still intact
7685 so we walk over subsections instead of sections. */
7686 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7689 fragS
*current_target
= NULL
;
7690 offsetT current_offset
= 0;
7691 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7693 /* Walk over all of the fragments in a subsection. */
7694 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7696 /* Check on the current loop. */
7697 if (fragP
->fr_type
== rs_machine_dependent
7698 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7699 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7700 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7705 /* Read it. If the instruction is a loop, get the target. */
7706 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7707 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7708 t_insn
.opcode
) == 1)
7710 /* Get the current fragment target. */
7711 if (fragP
->tc_frag_data
.slot_symbols
[0])
7713 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7714 current_target
= symbol_get_frag (sym
);
7715 current_offset
= fragP
->fr_offset
;
7716 current_opcode
= t_insn
.opcode
;
7721 if (fragP
->fr_type
== rs_machine_dependent
7722 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7725 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
7727 && (branch_before_loop_end (fragP
->fr_next
)
7728 || (workaround_all_short_loops
7729 && current_opcode
!= XTENSA_UNDEFINED
7730 && current_opcode
!= xtensa_loop_opcode
)))
7732 if (fragP
->tc_frag_data
.is_no_transform
)
7733 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7735 relax_frag_add_nop (fragP
);
7744 static size_t unrelaxed_frag_min_insn_count (fragS
*);
7747 count_insns_to_loop_end (fragS
*base_fragP
,
7748 bfd_boolean count_relax_add
,
7751 fragS
*fragP
= NULL
;
7752 size_t insn_count
= 0;
7756 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7758 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7759 if (insn_count
>= max_count
)
7762 if (count_relax_add
)
7764 if (fragP
->fr_type
== rs_machine_dependent
7765 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7767 /* In order to add the appropriate number of
7768 NOPs, we count an instruction for downstream
7771 if (insn_count
>= max_count
)
7781 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7783 xtensa_isa isa
= xtensa_default_isa
;
7784 static xtensa_insnbuf insnbuf
= NULL
;
7785 size_t insn_count
= 0;
7788 if (!fragP
->tc_frag_data
.is_insn
)
7792 insnbuf
= xtensa_insnbuf_alloc (isa
);
7794 /* Decode the fixed instructions. */
7795 while (offset
< fragP
->fr_fix
)
7799 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7800 fmt
= xtensa_format_decode (isa
, insnbuf
);
7802 if (fmt
== XTENSA_UNDEFINED
)
7804 as_fatal (_("undecodable instruction in instruction frag"));
7807 offset
+= xtensa_format_length (isa
, fmt
);
7815 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7818 branch_before_loop_end (fragS
*base_fragP
)
7822 for (fragP
= base_fragP
;
7823 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7824 fragP
= fragP
->fr_next
)
7826 if (unrelaxed_frag_has_b_j (fragP
))
7834 unrelaxed_frag_has_b_j (fragS
*fragP
)
7836 static xtensa_insnbuf insnbuf
= NULL
;
7837 xtensa_isa isa
= xtensa_default_isa
;
7840 if (!fragP
->tc_frag_data
.is_insn
)
7844 insnbuf
= xtensa_insnbuf_alloc (isa
);
7846 /* Decode the fixed instructions. */
7847 while (offset
< fragP
->fr_fix
)
7852 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7853 fmt
= xtensa_format_decode (isa
, insnbuf
);
7854 if (fmt
== XTENSA_UNDEFINED
)
7857 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7859 xtensa_opcode opcode
=
7860 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7861 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7862 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7865 offset
+= xtensa_format_length (isa
, fmt
);
7871 /* Checks to be made after initial assembly but before relaxation. */
7873 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7874 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7877 xtensa_sanity_check (void)
7884 as_where (&file_name
, &line
);
7885 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7889 /* Walk over all of the fragments in a subsection. */
7890 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7892 /* Currently we only check for empty loops here. */
7893 if (fragP
->fr_type
== rs_machine_dependent
7894 && fragP
->fr_subtype
== RELAX_IMMED
)
7896 static xtensa_insnbuf insnbuf
= NULL
;
7899 if (fragP
->fr_opcode
!= NULL
)
7902 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7903 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7904 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7906 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7907 t_insn
.opcode
) == 1)
7909 if (is_empty_loop (&t_insn
, fragP
))
7911 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7912 as_bad (_("invalid empty loop"));
7914 if (!is_local_forward_loop (&t_insn
, fragP
))
7916 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7917 as_bad (_("loop target does not follow "
7918 "loop instruction in section"));
7925 new_logical_line (file_name
, line
);
7929 #define LOOP_IMMED_OPN 1
7931 /* Return TRUE if the loop target is the next non-zero fragment. */
7934 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7936 const expressionS
*expr
;
7940 if (insn
->insn_type
!= ITYPE_INSN
)
7943 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7946 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7949 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7951 if (expr
->X_op
!= O_symbol
)
7954 symbolP
= expr
->X_add_symbol
;
7958 if (symbol_get_frag (symbolP
) == NULL
)
7961 if (S_GET_VALUE (symbolP
) != 0)
7964 /* Walk through the zero-size fragments from this one. If we find
7965 the target fragment, then this is a zero-size loop. */
7967 for (next_fragP
= fragP
->fr_next
;
7969 next_fragP
= next_fragP
->fr_next
)
7971 if (next_fragP
== symbol_get_frag (symbolP
))
7973 if (next_fragP
->fr_fix
!= 0)
7981 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7983 const expressionS
*expr
;
7987 if (insn
->insn_type
!= ITYPE_INSN
)
7990 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7993 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7996 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7998 if (expr
->X_op
!= O_symbol
)
8001 symbolP
= expr
->X_add_symbol
;
8005 if (symbol_get_frag (symbolP
) == NULL
)
8008 /* Walk through fragments until we find the target.
8009 If we do not find the target, then this is an invalid loop. */
8011 for (next_fragP
= fragP
->fr_next
;
8013 next_fragP
= next_fragP
->fr_next
)
8015 if (next_fragP
== symbol_get_frag (symbolP
))
8023 /* Alignment Functions. */
8026 get_text_align_power (int target_size
)
8029 for (i
= 0; i
< sizeof (size_t); i
++)
8031 if (target_size
<= (1 << i
))
8040 get_text_align_max_fill_size (int align_pow
,
8041 bfd_boolean use_nops
,
8042 bfd_boolean use_no_density
)
8045 return (1 << align_pow
);
8047 return 3 * (1 << align_pow
);
8049 return 1 + (1 << align_pow
);
8053 /* get_text_align_fill_size ()
8057 target_size = size of next instruction
8058 align_pow = get_text_align_power (target_size).
8062 address = current address + loop instruction size;
8063 target_size = 3 (for 2 or 3 byte target)
8064 = 4 (for 4 byte target)
8065 = 8 (for 8 byte target)
8066 align_pow = get_text_align_power (target_size);
8068 use_no_density = set appropriately
8070 address = current address + loop instruction size;
8072 align_pow = get_text_align_power (target_size);
8074 use_no_density = 0. */
8077 get_text_align_fill_size (addressT address
,
8080 bfd_boolean use_nops
,
8081 bfd_boolean use_no_density
)
8085 align_pow: log2 (required alignment).
8087 target_size: alignment must allow the new_address and
8088 new_address+target_size-1.
8090 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8092 use_no_density: if use_nops and use_no_density, we can only use
8095 Usually the align_pow is the power of 2 that is greater than
8096 or equal to the target_size. This handles the 2-byte, 3-byte
8097 and 8-byte instructions.
8101 (1) aligning an instruction properly, but without using NOPs.
8102 E.G.: a 3-byte instruction can go on any address where address mod 4
8103 is zero or one. The aligner uses this case to find the optimal
8104 number of fill bytes for relax_frag_for_align.
8106 (2) aligning an instruction properly, but where we might need to use
8107 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8108 or similar to get the optimal location. */
8110 size_t alignment
= (1 << align_pow
);
8112 assert (target_size
!= 0);
8116 unsigned fill_bytes
;
8117 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8119 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8120 addressT start_address
= address
+ fill_bytes
;
8121 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8127 /* This is the slightly harder case. */
8128 assert ((int) alignment
>= target_size
);
8129 assert (target_size
> 0);
8130 if (!use_no_density
)
8133 for (i
= 0; i
< alignment
* 2; i
++)
8137 if ((address
+ i
) >> align_pow
8138 == (address
+ i
+ target_size
- 1) >> align_pow
)
8146 /* Can only fill multiples of 3. */
8147 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8149 if ((address
+ i
) >> align_pow
8150 == (address
+ i
+ target_size
- 1) >> align_pow
)
8159 /* This will assert if it is not possible. */
8162 get_text_align_nop_count (size_t fill_size
, bfd_boolean use_no_density
)
8167 assert (fill_size
% 3 == 0);
8168 return (fill_size
/ 3);
8171 assert (fill_size
!= 1); /* Bad argument. */
8173 while (fill_size
> 1)
8175 size_t insn_size
= 3;
8176 if (fill_size
== 2 || fill_size
== 4)
8178 fill_size
-= insn_size
;
8181 assert (fill_size
!= 1); /* Bad algorithm. */
8187 get_text_align_nth_nop_size (size_t fill_size
,
8189 bfd_boolean use_no_density
)
8193 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8198 while (fill_size
> 1)
8200 size_t insn_size
= 3;
8201 if (fill_size
== 2 || fill_size
== 4)
8203 fill_size
-= insn_size
;
8213 /* For the given fragment, find the appropriate address
8214 for it to begin at if we are using NOPs to align it. */
8217 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8219 /* The rule is: get next fragment's FIRST instruction. Find
8220 the smallest number of bytes that need to be added to
8221 ensure that the next fragment's FIRST instruction will fit
8224 E.G., 2 bytes : 0, 1, 2 mod 4
8227 If the FIRST instruction MIGHT be relaxed,
8228 assume that it will become a 3-byte instruction.
8230 Note again here that LOOP instructions are not bundleable,
8231 and this relaxation only applies to LOOP opcodes. */
8233 size_t fill_size
= 0;
8234 int first_insn_size
;
8236 addressT pre_opcode_bytes
;
8239 xtensa_opcode opcode
;
8240 bfd_boolean is_loop
;
8242 assert (fragP
->fr_type
== rs_machine_dependent
);
8243 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8245 /* Find the loop frag. */
8246 first_insn
= next_non_empty_frag (fragP
);
8247 /* Now find the first insn frag. */
8248 first_insn
= next_non_empty_frag (first_insn
);
8250 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8252 loop_insn_size
= xg_get_single_size (opcode
);
8254 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8255 pre_opcode_bytes
+= loop_insn_size
;
8257 /* For loops, the alignment depends on the size of the
8258 instruction following the loop, not the LOOP instruction. */
8260 if (first_insn
== NULL
)
8263 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8265 first_insn_size
= frag_format_size (first_insn
);
8267 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8268 first_insn_size
= 3; /* ISA specifies this */
8270 /* If it was 8, then we'll need a larger alignment for the section. */
8271 alignment
= get_text_align_power (first_insn_size
);
8273 /* Is now_seg valid? */
8274 record_alignment (now_seg
, alignment
);
8276 fill_size
= get_text_align_fill_size
8277 (address
+ pre_opcode_bytes
,
8278 get_text_align_power (first_insn_size
),
8279 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
8281 return address
+ fill_size
;
8285 /* 3 mechanisms for relaxing an alignment:
8287 Align to a power of 2.
8288 Align so the next fragment's instruction does not cross a word boundary.
8289 Align the current instruction so that if the next instruction
8290 were 3 bytes, it would not cross a word boundary.
8294 zeros - This is easy; always insert zeros.
8295 nops - 3-byte and 2-byte instructions
8299 >=5 : 3-byte instruction + fn (n-3)
8300 widening - widen previous instructions. */
8303 get_aligned_diff (fragS
*fragP
, addressT address
, addressT
*max_diff
)
8305 addressT target_address
, loop_insn_offset
;
8307 xtensa_opcode loop_opcode
;
8308 bfd_boolean is_loop
;
8309 int text_align_power
;
8312 assert (fragP
->fr_type
== rs_machine_dependent
);
8313 switch (fragP
->fr_subtype
)
8315 case RELAX_DESIRE_ALIGN
:
8316 target_size
= next_frag_format_size (fragP
);
8317 if (target_size
== XTENSA_UNDEFINED
)
8319 text_align_power
= get_text_align_power (xtensa_fetch_width
);
8320 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
8321 target_size
, FALSE
, FALSE
);
8323 *max_diff
= opt_diff
+ xtensa_fetch_width
8324 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
8325 assert (*max_diff
>= opt_diff
);
8328 case RELAX_ALIGN_NEXT_OPCODE
:
8329 target_size
= next_frag_format_size (fragP
);
8330 loop_insn_offset
= 0;
8331 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8334 /* If the loop has been expanded then the LOOP instruction
8335 could be at an offset from this fragment. */
8336 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8338 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8340 if (target_size
== 2)
8341 target_size
= 3; /* ISA specifies this */
8343 /* In an ideal world, which is what we are shooting for here,
8344 we wouldn't need to use any NOPs immediately prior to the
8345 LOOP instruction. If this approach fails, relax_frag_loop_align
8346 will call get_noop_aligned_address. */
8348 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8349 text_align_power
= get_text_align_power (target_size
),
8350 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
8351 target_size
, FALSE
, FALSE
);
8353 *max_diff
= xtensa_fetch_width
8354 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8355 - target_size
+ opt_diff
;
8356 assert (*max_diff
>= opt_diff
);
8367 /* md_relax_frag Hook and Helper Functions. */
8369 static long relax_frag_loop_align (fragS
*, long);
8370 static long relax_frag_for_align (fragS
*, long);
8371 static long relax_frag_immed
8372 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8375 /* Return the number of bytes added to this fragment, given that the
8376 input has been stretched already by "stretch". */
8379 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8381 xtensa_isa isa
= xtensa_default_isa
;
8382 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8383 long new_stretch
= 0;
8386 static xtensa_insnbuf vbuf
= NULL
;
8387 int slot
, num_slots
;
8390 as_where (&file_name
, &line
);
8391 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8393 fragP
->tc_frag_data
.unreported_expansion
= 0;
8395 switch (fragP
->fr_subtype
)
8397 case RELAX_ALIGN_NEXT_OPCODE
:
8398 /* Always convert. */
8399 if (fragP
->tc_frag_data
.relax_seen
)
8400 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8403 case RELAX_LOOP_END
:
8407 case RELAX_LOOP_END_ADD_NOP
:
8408 /* Add a NOP and switch to .fill 0. */
8409 new_stretch
= relax_frag_add_nop (fragP
);
8413 case RELAX_DESIRE_ALIGN
:
8414 /* Do nothing. The narrowing before this frag will either align
8419 case RELAX_LITERAL_FINAL
:
8422 case RELAX_LITERAL_NR
:
8424 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8425 assert (unreported
== lit_size
);
8426 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8427 fragP
->fr_var
-= lit_size
;
8428 fragP
->fr_fix
+= lit_size
;
8434 vbuf
= xtensa_insnbuf_alloc (isa
);
8436 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
8437 fmt
= xtensa_format_decode (isa
, vbuf
);
8438 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8440 for (slot
= 0; slot
< num_slots
; slot
++)
8442 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8445 if (fragP
->tc_frag_data
.relax_seen
)
8446 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8450 case RELAX_IMMED_STEP1
:
8451 case RELAX_IMMED_STEP2
:
8452 /* Place the immediate. */
8453 new_stretch
+= relax_frag_immed
8454 (now_seg
, fragP
, stretch
,
8455 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8456 fmt
, slot
, stretched_p
, FALSE
);
8460 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8466 case RELAX_LITERAL_POOL_BEGIN
:
8467 case RELAX_LITERAL_POOL_END
:
8468 case RELAX_MAYBE_UNREACHABLE
:
8469 case RELAX_MAYBE_DESIRE_ALIGN
:
8470 /* No relaxation required. */
8473 case RELAX_FILL_NOP
:
8474 case RELAX_UNREACHABLE
:
8475 if (fragP
->tc_frag_data
.relax_seen
)
8476 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8480 as_bad (_("bad relaxation state"));
8483 /* Tell gas we need another relaxation pass. */
8484 if (! fragP
->tc_frag_data
.relax_seen
)
8486 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8490 new_logical_line (file_name
, line
);
8496 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8498 addressT old_address
, old_next_address
, old_size
;
8499 addressT new_address
, new_next_address
, new_size
;
8502 /* All the frags with relax_frag_for_alignment prior to this one in the
8503 section have been done, hopefully eliminating the need for a NOP here.
8504 But, this will put it in if necessary. */
8506 /* Calculate the old address of this fragment and the next fragment. */
8507 old_address
= fragP
->fr_address
- stretch
;
8508 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8509 fragP
->tc_frag_data
.text_expansion
[0]);
8510 old_size
= old_next_address
- old_address
;
8512 /* Calculate the new address of this fragment and the next fragment. */
8513 new_address
= fragP
->fr_address
;
8515 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8516 new_size
= new_next_address
- new_address
;
8518 growth
= new_size
- old_size
;
8520 /* Fix up the text_expansion field and return the new growth. */
8521 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8526 /* Add a NOP instruction. */
8529 relax_frag_add_nop (fragS
*fragP
)
8531 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8532 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8533 assemble_nop (length
, nop_buf
);
8534 fragP
->tc_frag_data
.is_insn
= TRUE
;
8536 if (fragP
->fr_var
< length
)
8538 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8542 fragP
->fr_fix
+= length
;
8543 fragP
->fr_var
-= length
;
8548 static long future_alignment_required (fragS
*, long);
8551 relax_frag_for_align (fragS
*fragP
, long stretch
)
8553 /* Overview of the relaxation procedure for alignment:
8554 We can widen with NOPs or by widening instructions or by filling
8555 bytes after jump instructions. Find the opportune places and widen
8556 them if necessary. */
8561 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8562 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8563 || (fragP
->fr_subtype
== RELAX_SLOTS
8564 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8566 stretch_me
= future_alignment_required (fragP
, stretch
);
8567 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8573 /* We expanded on a previous pass. Can we shrink now? */
8574 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8575 if (shrink
<= stretch
&& stretch
> 0)
8577 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8583 /* Below here, diff > 0. */
8584 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8590 /* Return the address of the next frag that should be aligned.
8592 By "address" we mean the address it _would_ be at if there
8593 is no action taken to align it between here and the target frag.
8594 In other words, if no narrows and no fill nops are used between
8595 here and the frag to align, _even_if_ some of the frags we use
8596 to align targets have already expanded on a previous relaxation
8599 Also, count each frag that may be used to help align the target.
8601 Return 0 if there are no frags left in the chain that need to be
8605 find_address_of_next_align_frag (fragS
**fragPP
,
8609 bfd_boolean
*paddable
)
8611 fragS
*fragP
= *fragPP
;
8612 addressT address
= fragP
->fr_address
;
8614 /* Do not reset the counts to 0. */
8618 /* Limit this to a small search. */
8624 address
+= fragP
->fr_fix
;
8626 if (fragP
->fr_type
== rs_fill
)
8627 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8628 else if (fragP
->fr_type
== rs_machine_dependent
)
8630 switch (fragP
->fr_subtype
)
8632 case RELAX_UNREACHABLE
:
8636 case RELAX_FILL_NOP
:
8638 if (!fragP
->tc_frag_data
.is_no_density
)
8643 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8648 address
+= total_frag_text_expansion (fragP
);;
8652 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8655 case RELAX_ALIGN_NEXT_OPCODE
:
8656 case RELAX_DESIRE_ALIGN
:
8660 case RELAX_MAYBE_UNREACHABLE
:
8661 case RELAX_MAYBE_DESIRE_ALIGN
:
8666 /* Just punt if we don't know the type. */
8673 /* Just punt if we don't know the type. */
8677 fragP
= fragP
->fr_next
;
8685 static long bytes_to_stretch (fragS
*, int, int, int, int);
8687 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8688 I'll leave this in until I am more confident this works. */
8690 #define LOOKAHEAD_ALIGNER 1
8693 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8695 fragS
*this_frag
= fragP
;
8699 int narrow_nops
= 0;
8700 bfd_boolean paddable
= FALSE
;
8701 offsetT local_opt_diff
;
8704 int stretch_amount
= 0;
8705 int local_stretch_amount
;
8706 int global_stretch_amount
;
8708 address
= find_address_of_next_align_frag
8709 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8713 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8714 opt_diff
= local_opt_diff
;
8715 assert (opt_diff
>= 0);
8716 assert (max_diff
>= opt_diff
);
8719 #ifdef LOOKAHEAD_ALIGNER
8721 fragP
= fragP
->fr_next
;
8723 while (fragP
&& opt_diff
< max_diff
&& address
)
8725 /* We only use these to determine if we can exit early
8726 because there will be plenty of ways to align future
8728 unsigned int glob_widens
= 0;
8731 bfd_boolean glob_pad
= 0;
8732 address
= find_address_of_next_align_frag
8733 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8734 /* If there is a padable portion, then skip. */
8735 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
8740 offsetT next_m_diff
;
8741 offsetT next_o_diff
;
8743 /* Downrange frags haven't had stretch added to them yet. */
8746 /* The address also includes any text expansion from this
8747 frag in a previous pass, but we don't want that. */
8748 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8750 /* Assume we are going to move at least opt_diff. In
8751 reality, we might not be able to, but assuming that
8752 we will helps catch cases where moving opt_diff pushes
8753 the next target from aligned to unaligned. */
8754 address
+= opt_diff
;
8756 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8758 /* Now cleanup for the adjustments to address. */
8759 next_o_diff
+= opt_diff
;
8760 next_m_diff
+= opt_diff
;
8761 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8762 opt_diff
= next_o_diff
;
8763 if (next_m_diff
< max_diff
)
8764 max_diff
= next_m_diff
;
8765 fragP
= fragP
->fr_next
;
8768 #endif /* LOOKAHEAD_ALIGNER */
8769 /* If there are enough wideners in between, do it. */
8772 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8774 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8779 local_stretch_amount
8780 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8781 num_widens
, local_opt_diff
);
8782 #ifdef LOOKAHEAD_ALIGNER
8783 global_stretch_amount
8784 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8785 num_widens
, opt_diff
);
8786 /* If the condition below is true, then the frag couldn't
8787 stretch the correct amount for the global case, so we just
8788 optimize locally. We'll rely on the subsequent frags to get
8789 the correct alignment in the global case. */
8790 if (global_stretch_amount
< local_stretch_amount
)
8791 stretch_amount
= local_stretch_amount
;
8793 stretch_amount
= global_stretch_amount
;
8794 #else /* ! LOOKAHEAD_ALIGNER */
8795 stretch_amount
= local_stretch_amount
;
8796 #endif /* ! LOOKAHEAD_ALIGNER */
8797 if (this_frag
->fr_subtype
== RELAX_SLOTS
8798 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8799 assert (stretch_amount
<= 1);
8800 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8802 if (this_frag
->tc_frag_data
.is_no_density
)
8803 assert (stretch_amount
== 3 || stretch_amount
== 0);
8805 assert (stretch_amount
<= 3);
8808 return stretch_amount
;
8812 /* The idea: widen everything you can to get a target or loop aligned,
8813 then start using NOPs.
8815 When we must have a NOP, here is a table of how we decide
8816 (so you don't have to fight through the control flow below):
8818 wide_nops = the number of wide NOPs available for aligning
8819 narrow_nops = the number of narrow NOPs available for aligning
8820 (a subset of wide_nops)
8821 widens = the number of narrow instructions that should be widened
8828 b 0 1 1 (case 3a makes this case unnecessary)
8831 c 0 1 2 (case 4a makes this case unnecessary)
8834 c 0 2 1 (case 5b makes this case unnecessary)
8837 c 0 1 4 (case 6b makes this case unneccesary)
8838 d 1 1 1 (case 6a makes this case unnecessary)
8839 e 0 2 2 (case 6a makes this case unnecessary)
8840 f 0 3 0 (case 6a makes this case unnecessary)
8843 c 1 1 2 (case 7b makes this case unnecessary)
8844 d 0 1 5 (case 7a makes this case unnecessary)
8845 e 0 2 3 (case 7b makes this case unnecessary)
8846 f 0 3 1 (case 7b makes this case unnecessary)
8847 g 1 2 1 (case 7b makes this case unnecessary)
8851 bytes_to_stretch (fragS
*this_frag
,
8857 int bytes_short
= desired_diff
- num_widens
;
8859 assert (desired_diff
>= 0 && desired_diff
< 8);
8860 if (desired_diff
== 0)
8863 assert (wide_nops
> 0 || num_widens
> 0);
8865 /* Always prefer widening to NOP-filling. */
8866 if (bytes_short
< 0)
8868 /* There are enough RELAX_NARROW frags after this one
8869 to align the target without widening this frag in any way. */
8873 if (bytes_short
== 0)
8875 /* Widen every narrow between here and the align target
8876 and the align target will be properly aligned. */
8877 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8883 /* From here we will need at least one NOP to get an alignment.
8884 However, we may not be able to align at all, in which case,
8886 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8888 switch (desired_diff
)
8893 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8894 return 2; /* case 2 */
8900 return 3; /* case 3a */
8902 if (num_widens
>= 1 && wide_nops
== 1)
8903 return 3; /* case 4a */
8904 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8905 return 2; /* case 4b */
8908 if (num_widens
>= 2 && wide_nops
== 1)
8909 return 3; /* case 5a */
8910 /* We will need two nops. Are there enough nops
8911 between here and the align target? */
8912 if (wide_nops
< 2 || narrow_nops
== 0)
8914 /* Are there other nops closer that can serve instead? */
8915 if (wide_nops
> 2 && narrow_nops
> 1)
8917 /* Take the density one first, because there might not be
8918 another density one available. */
8919 if (!this_frag
->tc_frag_data
.is_no_density
)
8920 return 2; /* case 5b narrow */
8922 return 3; /* case 5b wide */
8926 return 3; /* case 6a */
8927 else if (num_widens
>= 3 && wide_nops
== 1)
8928 return 3; /* case 6b */
8931 if (wide_nops
== 1 && num_widens
>= 4)
8932 return 3; /* case 7a */
8933 else if (wide_nops
== 2 && num_widens
>= 1)
8934 return 3; /* case 7b */
8942 /* We will need a NOP no matter what, but should we widen
8943 this instruction to help?
8945 This is a RELAX_FRAG_NARROW frag. */
8946 switch (desired_diff
)
8955 if (wide_nops
>= 1 && num_widens
== 1)
8956 return 1; /* case 4a */
8959 if (wide_nops
>= 1 && num_widens
== 2)
8960 return 1; /* case 5a */
8964 return 0; /* case 6a */
8965 else if (wide_nops
>= 1 && num_widens
== 3)
8966 return 1; /* case 6b */
8969 if (wide_nops
>= 1 && num_widens
== 4)
8970 return 1; /* case 7a */
8971 else if (wide_nops
>= 2 && num_widens
== 1)
8972 return 1; /* case 7b */
8985 relax_frag_immed (segT segP
,
8992 bfd_boolean estimate_only
)
8995 vliw_insn orig_vinsn
;
8997 bfd_boolean negatable_branch
= FALSE
;
8998 bfd_boolean branch_jmp_to_next
= FALSE
;
8999 bfd_boolean wide_insn
= FALSE
;
9000 xtensa_isa isa
= xtensa_default_isa
;
9002 offsetT frag_offset
;
9005 int num_text_bytes
, num_literal_bytes
;
9006 int literal_diff
, total_text_diff
, this_text_diff
, first
;
9008 assert (fragP
->fr_opcode
!= NULL
);
9010 xg_init_vinsn (&orig_vinsn
);
9011 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
9012 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9015 tinsn
= orig_vinsn
.slots
[slot
];
9016 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9018 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
9021 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9022 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9024 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9026 old_size
= xtensa_format_length (isa
, fmt
);
9028 /* Special case: replace a branch to the next instruction with a NOP.
9029 This is required to work around a hardware bug in T1040.0 and also
9030 serves as an optimization. */
9032 if (branch_jmp_to_next
9033 && ((old_size
== 2) || (old_size
== 3))
9034 && !next_frag_is_loop_target (fragP
))
9037 /* Here is the fun stuff: Get the immediate field from this
9038 instruction. If it fits, we are done. If not, find the next
9039 instruction sequence that fits. */
9041 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9042 istack_init (&istack
);
9043 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9044 min_steps
, stretch
);
9045 if (num_steps
< min_steps
)
9047 as_fatal (_("internal error: relaxation failed"));
9051 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9053 as_fatal (_("internal error: relaxation requires too many steps"));
9057 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9059 /* Figure out the number of bytes needed. */
9061 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9063 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9065 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9067 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9070 num_text_bytes
+= old_size
;
9071 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9072 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9074 total_text_diff
= num_text_bytes
- old_size
;
9075 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9077 /* It MUST get larger. If not, we could get an infinite loop. */
9078 assert (num_text_bytes
>= 0);
9079 assert (literal_diff
>= 0);
9080 assert (total_text_diff
>= 0);
9082 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9083 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9084 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9085 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9087 /* Find the associated expandable literal for this. */
9088 if (literal_diff
!= 0)
9090 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9093 assert (literal_diff
== 4);
9094 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9096 /* We expect that the literal section state has NOT been
9098 assert (lit_fragP
->fr_type
== rs_machine_dependent
9099 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9100 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9102 /* We need to mark this section for another iteration
9108 if (negatable_branch
&& istack
.ninsn
> 1)
9109 update_next_frag_state (fragP
);
9111 return this_text_diff
;
9115 /* md_convert_frag Hook and Helper Functions. */
9117 static void convert_frag_align_next_opcode (fragS
*);
9118 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9119 static void convert_frag_fill_nop (fragS
*);
9120 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9123 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9125 static xtensa_insnbuf vbuf
= NULL
;
9126 xtensa_isa isa
= xtensa_default_isa
;
9133 as_where (&file_name
, &line
);
9134 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9136 switch (fragp
->fr_subtype
)
9138 case RELAX_ALIGN_NEXT_OPCODE
:
9139 /* Always convert. */
9140 convert_frag_align_next_opcode (fragp
);
9143 case RELAX_DESIRE_ALIGN
:
9144 /* Do nothing. If not aligned already, too bad. */
9148 case RELAX_LITERAL_FINAL
:
9153 vbuf
= xtensa_insnbuf_alloc (isa
);
9155 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9156 fmt
= xtensa_format_decode (isa
, vbuf
);
9157 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9159 for (slot
= 0; slot
< num_slots
; slot
++)
9161 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9164 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9168 case RELAX_IMMED_STEP1
:
9169 case RELAX_IMMED_STEP2
:
9170 /* Place the immediate. */
9173 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9178 /* This is OK because some slots could have
9179 relaxations and others have none. */
9185 case RELAX_UNREACHABLE
:
9186 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9187 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9188 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9192 case RELAX_MAYBE_UNREACHABLE
:
9193 case RELAX_MAYBE_DESIRE_ALIGN
:
9197 case RELAX_FILL_NOP
:
9198 convert_frag_fill_nop (fragp
);
9201 case RELAX_LITERAL_NR
:
9202 if (use_literal_section
)
9204 /* This should have been handled during relaxation. When
9205 relaxing a code segment, literals sometimes need to be
9206 added to the corresponding literal segment. If that
9207 literal segment has already been relaxed, then we end up
9208 in this situation. Marking the literal segments as data
9209 would make this happen less often (since GAS always relaxes
9210 code before data), but we could still get into trouble if
9211 there are instructions in a segment that is not marked as
9212 containing code. Until we can implement a better solution,
9213 cheat and adjust the addresses of all the following frags.
9214 This could break subsequent alignments, but the linker's
9215 literal coalescing will do that anyway. */
9218 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9219 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9220 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9223 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9227 as_bad (_("invalid relaxation fragment result"));
9232 new_logical_line (file_name
, line
);
9237 convert_frag_align_next_opcode (fragS
*fragp
)
9239 char *nop_buf
; /* Location for Writing. */
9242 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9243 addressT aligned_address
;
9244 size_t fill_size
, nop_count
;
9246 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9248 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9249 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9250 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9252 for (i
= 0; i
< nop_count
; i
++)
9255 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
9257 assemble_nop (nop_size
, nop_buf
);
9258 nop_buf
+= nop_size
;
9261 fragp
->fr_fix
+= fill_size
;
9262 fragp
->fr_var
-= fill_size
;
9267 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9269 TInsn tinsn
, single_target
;
9270 xtensa_format single_fmt
;
9271 int size
, old_size
, diff
, error_val
;
9272 offsetT frag_offset
;
9275 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9277 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9279 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9280 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9281 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9286 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9288 /* No conversion. */
9293 assert (fragP
->fr_opcode
!= NULL
);
9295 /* Frags in this relaxation state should only contain
9296 single instruction bundles. */
9297 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9299 /* Just convert it to a wide form.... */
9301 old_size
= xg_get_single_size (tinsn
.opcode
);
9303 tinsn_init (&single_target
);
9304 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9306 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9309 as_bad (_("unable to widen instruction"));
9313 size
= xg_get_single_size (single_target
.opcode
);
9314 single_fmt
= xg_get_single_format (single_target
.opcode
);
9316 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9317 fragP
, frag_offset
, TRUE
);
9319 diff
= size
- old_size
;
9321 assert (diff
<= fragP
->fr_var
);
9322 fragP
->fr_var
-= diff
;
9323 fragP
->fr_fix
+= diff
;
9331 convert_frag_fill_nop (fragS
*fragP
)
9333 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9334 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9335 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9336 - fragP
->fr_address
- fragP
->fr_fix
));
9339 /* No conversion. */
9343 assemble_nop (size
, loc
);
9344 fragP
->tc_frag_data
.is_insn
= TRUE
;
9345 fragP
->fr_var
-= size
;
9346 fragP
->fr_fix
+= size
;
9351 static fixS
*fix_new_exp_in_seg
9352 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9353 bfd_reloc_code_real_type
);
9354 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9357 convert_frag_immed (segT segP
,
9363 char *immed_instr
= fragP
->fr_opcode
;
9365 bfd_boolean expanded
= FALSE
;
9366 bfd_boolean branch_jmp_to_next
= FALSE
;
9367 char *fr_opcode
= fragP
->fr_opcode
;
9368 vliw_insn orig_vinsn
;
9369 xtensa_isa isa
= xtensa_default_isa
;
9370 bfd_boolean wide_insn
= FALSE
;
9372 bfd_boolean is_loop
;
9374 assert (fr_opcode
!= NULL
);
9376 xg_init_vinsn (&orig_vinsn
);
9378 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9379 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9382 orig_tinsn
= orig_vinsn
.slots
[slot
];
9383 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9385 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9387 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9388 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9390 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9392 /* Conversion just inserts a NOP and marks the fix as completed. */
9393 bytes
= xtensa_format_length (isa
, fmt
);
9396 orig_vinsn
.slots
[slot
].opcode
=
9397 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9398 orig_vinsn
.slots
[slot
].ntok
= 0;
9402 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9403 assert (bytes
== 2 || bytes
== 3);
9404 build_nop (&orig_vinsn
.slots
[0], bytes
);
9405 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9407 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9408 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
9411 else if (!orig_tinsn
.is_specific_opcode
)
9413 /* Here is the fun stuff: Get the immediate field from this
9414 instruction. If it fits, we're done. If not, find the next
9415 instruction sequence that fits. */
9419 symbolS
*lit_sym
= NULL
;
9421 int target_offset
= 0;
9424 symbolS
*gen_label
= NULL
;
9425 offsetT frag_offset
;
9426 bfd_boolean first
= TRUE
;
9427 bfd_boolean last_is_jump
;
9429 /* It does not fit. Find something that does and
9430 convert immediately. */
9431 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9432 istack_init (&istack
);
9433 xg_assembly_relax (&istack
, &orig_tinsn
,
9434 segP
, fragP
, frag_offset
, min_steps
, 0);
9436 old_size
= xtensa_format_length (isa
, fmt
);
9438 /* Assemble this right inline. */
9440 /* First, create the mapping from a label name to the REAL label. */
9442 for (i
= 0; i
< istack
.ninsn
; i
++)
9444 TInsn
*tinsn
= &istack
.insn
[i
];
9447 switch (tinsn
->insn_type
)
9450 if (lit_sym
!= NULL
)
9451 as_bad (_("multiple literals in expansion"));
9452 /* First find the appropriate space in the literal pool. */
9453 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9454 if (lit_frag
== NULL
)
9455 as_bad (_("no registered fragment for literal"));
9456 if (tinsn
->ntok
!= 1)
9457 as_bad (_("number of literal tokens != 1"));
9459 /* Set the literal symbol and add a fixup. */
9460 lit_sym
= lit_frag
->fr_symbol
;
9464 if (align_targets
&& !is_loop
)
9466 fragS
*unreach
= fragP
->fr_next
;
9467 while (!(unreach
->fr_type
== rs_machine_dependent
9468 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9469 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9471 unreach
= unreach
->fr_next
;
9474 assert (unreach
->fr_type
== rs_machine_dependent
9475 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9476 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9478 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9480 assert (gen_label
== NULL
);
9481 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9482 fr_opcode
- fragP
->fr_literal
9483 + target_offset
, fragP
);
9487 if (first
&& wide_insn
)
9489 target_offset
+= xtensa_format_length (isa
, fmt
);
9491 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9492 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9495 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9502 last_is_jump
= FALSE
;
9503 for (i
= 0; i
< istack
.ninsn
; i
++)
9505 TInsn
*tinsn
= &istack
.insn
[i
];
9509 bfd_reloc_code_real_type reloc_type
;
9511 switch (tinsn
->insn_type
)
9514 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9515 /* Already checked. */
9516 assert (lit_frag
!= NULL
);
9517 assert (lit_sym
!= NULL
);
9518 assert (tinsn
->ntok
== 1);
9520 target_seg
= S_GET_SEGMENT (lit_sym
);
9521 assert (target_seg
);
9522 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9523 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9525 reloc_type
= BFD_RELOC_32
;
9526 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9527 &tinsn
->tok
[0], FALSE
, reloc_type
);
9534 xg_resolve_labels (tinsn
, gen_label
);
9535 xg_resolve_literals (tinsn
, lit_sym
);
9536 if (wide_insn
&& first
)
9539 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9541 tinsn
->record_fix
= TRUE
;
9542 orig_vinsn
.slots
[slot
] = *tinsn
;
9546 orig_vinsn
.slots
[slot
].opcode
=
9547 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9548 orig_vinsn
.slots
[slot
].ntok
= 0;
9549 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9551 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9552 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9554 fragP
->tc_frag_data
.is_insn
= TRUE
;
9555 size
= xtensa_format_length (isa
, fmt
);
9556 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9558 xtensa_format single_fmt
=
9559 xg_get_single_format (tinsn
->opcode
);
9562 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9563 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9564 size
+= xg_get_single_size (tinsn
->opcode
);
9569 xtensa_format single_format
;
9570 size
= xg_get_single_size (tinsn
->opcode
);
9571 single_format
= xg_get_single_format (tinsn
->opcode
);
9572 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9574 immed_instr
- fragP
->fr_literal
, TRUE
);
9576 /* Code to recognize branch-around expansion
9577 so the fragment is properly marked as ending in a
9579 if ((((i
== istack
.ninsn
- 2)
9580 && (istack
.insn
[istack
.ninsn
-1].insn_type
9582 || i
== istack
.ninsn
-1)
9583 && xtensa_opcode_is_jump (xtensa_default_isa
,
9585 && fragP
->fr_next
!= NULL
9586 && ! fragP
->fr_next
->tc_frag_data
.is_unreachable
)
9588 /* Create a new unreachable frag of zero size. */
9589 size_t frag_size
= sizeof (fragS
);
9590 fragS
*new_fragP
= (fragS
*) xmalloc (frag_size
);
9591 memset (new_fragP
, 0, frag_size
);
9592 new_fragP
->fr_address
= fragP
->fr_next
->fr_address
;
9593 new_fragP
->fr_next
= fragP
->fr_next
;
9594 new_fragP
->fr_fix
= 0;
9595 new_fragP
->fr_var
= 0;
9596 new_fragP
->fr_type
= rs_fill
;
9597 new_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
9598 /* The rest are zeros.... */
9599 /* Link it in to the chain. */
9600 fragP
->fr_next
= new_fragP
;
9604 immed_instr
+= size
;
9610 diff
= total_size
- old_size
;
9614 assert (diff
<= fragP
->fr_var
);
9615 fragP
->fr_var
-= diff
;
9616 fragP
->fr_fix
+= diff
;
9620 xg_free_vinsn (&orig_vinsn
);
9622 /* Check for undefined immediates in LOOP instructions. */
9626 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9627 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9629 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9632 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9633 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9635 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9640 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9641 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9643 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9645 /* Add an expansion note on the expanded instruction. */
9646 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9647 &orig_tinsn
.tok
[0], TRUE
,
9648 BFD_RELOC_XTENSA_ASM_EXPAND
);
9653 /* Add a new fix expression into the desired segment. We have to
9654 switch to that segment to do this. */
9657 fix_new_exp_in_seg (segT new_seg
,
9664 bfd_reloc_code_real_type r_type
)
9668 subsegT subseg
= now_subseg
;
9670 assert (new_seg
!= 0);
9671 subseg_set (new_seg
, new_subseg
);
9673 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9674 subseg_set (seg
, subseg
);
9679 /* Relax a loop instruction so that it can span loop >256 bytes.
9685 addi as, as, lo8 (label-.L1)
9686 addmi as, as, mid8 (label-.L1)
9697 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9702 unsigned long target
;
9703 static xtensa_insnbuf insnbuf
= NULL
;
9704 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9705 xtensa_isa isa
= xtensa_default_isa
;
9706 addressT loop_offset
;
9707 addressT addi_offset
= 9;
9708 addressT addmi_offset
= 12;
9710 size_t target_count
;
9713 insnbuf
= xtensa_insnbuf_alloc (isa
);
9715 /* Get the loop offset. */
9716 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9718 /* Validate that there really is a LOOP at the loop_offset. Because
9719 loops are not bundleable, we can assume that the instruction will be
9721 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9722 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9724 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9725 addi_offset
+= loop_offset
;
9726 addmi_offset
+= loop_offset
;
9728 assert (tinsn
->ntok
== 2);
9729 if (tinsn
->tok
[1].X_op
== O_constant
)
9730 target
= tinsn
->tok
[1].X_add_number
;
9731 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9733 /* Find the fragment. */
9734 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9735 assert (S_GET_SEGMENT (sym
) == segP
9736 || S_GET_SEGMENT (sym
) == absolute_section
);
9737 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9741 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9746 know (symbolP
->sy_frag
);
9747 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9748 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9750 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9751 loop_length_hi
= loop_length
& ~0x0ff;
9752 loop_length_lo
= loop_length
& 0x0ff;
9753 if (loop_length_lo
>= 128)
9755 loop_length_lo
-= 256;
9756 loop_length_hi
+= 256;
9759 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9760 32512. If the loop is larger than that, then we just fail. */
9761 if (loop_length_hi
> 32512)
9762 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9763 _("loop too long for LOOP instruction"));
9765 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9766 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9768 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9769 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9771 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9772 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9774 fragP
->tc_frag_data
.is_insn
= TRUE
;
9775 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
9777 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9778 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9779 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
9781 /* Walk through all of the frags from here to the loop end
9782 and mark them as no_transform to keep them from being modified
9783 by the linker. If we ever have a relocation for the
9784 addi/addmi of the difference of two symbols we can remove this. */
9787 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9788 next_fragP
= next_fragP
->fr_next
)
9790 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9791 if (next_fragP
->tc_frag_data
.is_loop_target
)
9793 if (target_count
== 2)
9799 /* A map that keeps information on a per-subsegment basis. This is
9800 maintained during initial assembly, but is invalid once the
9801 subsegments are smashed together. I.E., it cannot be used during
9804 typedef struct subseg_map_struct
9812 float total_freq
; /* fall-through + branch target frequency */
9813 float target_freq
; /* branch target frequency alone */
9815 struct subseg_map_struct
*next
;
9819 static subseg_map
*sseg_map
= NULL
;
9822 get_subseg_info (segT seg
, subsegT subseg
)
9824 subseg_map
*subseg_e
;
9826 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9828 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9836 add_subseg_info (segT seg
, subsegT subseg
)
9838 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9839 memset (subseg_e
, 0, sizeof (subseg_map
));
9840 subseg_e
->seg
= seg
;
9841 subseg_e
->subseg
= subseg
;
9842 subseg_e
->flags
= 0;
9843 /* Start off considering every branch target very important. */
9844 subseg_e
->target_freq
= 1.0;
9845 subseg_e
->total_freq
= 1.0;
9846 subseg_e
->next
= sseg_map
;
9847 sseg_map
= subseg_e
;
9853 get_last_insn_flags (segT seg
, subsegT subseg
)
9855 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9857 return subseg_e
->flags
;
9863 set_last_insn_flags (segT seg
,
9868 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9870 subseg_e
= add_subseg_info (seg
, subseg
);
9872 subseg_e
->flags
|= fl
;
9874 subseg_e
->flags
&= ~fl
;
9879 get_subseg_total_freq (segT seg
, subsegT subseg
)
9881 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9883 return subseg_e
->total_freq
;
9889 get_subseg_target_freq (segT seg
, subsegT subseg
)
9891 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9893 return subseg_e
->target_freq
;
9899 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9901 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9903 subseg_e
= add_subseg_info (seg
, subseg
);
9904 subseg_e
->total_freq
= total_f
;
9905 subseg_e
->target_freq
= target_f
;
9909 /* Segment Lists and emit_state Stuff. */
9911 /* Remove the segment from the global sections list. */
9914 xtensa_remove_section (segT sec
)
9916 /* Handle brain-dead bfd_section_list_remove macro, which
9917 expect the address of the prior section's "next" field, not
9918 just the address of the section to remove. */
9920 segT
*ps_next_ptr
= &stdoutput
->sections
;
9921 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9922 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9924 assert (*ps_next_ptr
!= NULL
);
9926 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9931 xtensa_insert_section (segT after_sec
, segT sec
)
9933 segT
*after_sec_next
;
9934 if (after_sec
== NULL
)
9935 after_sec_next
= &stdoutput
->sections
;
9937 after_sec_next
= &after_sec
->next
;
9939 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9944 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9949 segT literal_section
= head
->seg
;
9951 /* Move the literal section to the front of the section list. */
9952 assert (literal_section
);
9953 xtensa_remove_section (literal_section
);
9954 xtensa_insert_section (NULL
, literal_section
);
9961 static void mark_literal_frags (seg_list
*);
9964 xtensa_move_literals (void)
9967 frchainS
*frchain_from
, *frchain_to
;
9968 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9969 fragS
**frag_splice
;
9972 fixS
*fix
, *next_fix
, **fix_splice
;
9975 mark_literal_frags (literal_head
->next
);
9976 mark_literal_frags (init_literal_head
->next
);
9977 mark_literal_frags (fini_literal_head
->next
);
9979 if (use_literal_section
)
9982 segment
= literal_head
->next
;
9985 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9986 search_frag
= frchain_from
->frch_root
;
9987 literal_pool
= NULL
;
9989 frag_splice
= &(frchain_from
->frch_root
);
9991 while (!search_frag
->tc_frag_data
.literal_frag
)
9993 assert (search_frag
->fr_fix
== 0
9994 || search_frag
->fr_type
== rs_align
);
9995 search_frag
= search_frag
->fr_next
;
9998 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9999 == RELAX_LITERAL_POOL_BEGIN
);
10000 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10002 /* Make sure that all the frags in this series are closed, and
10003 that there is at least one left over of zero-size. This
10004 prevents us from making a segment with an frchain without any
10006 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10007 xtensa_set_frag_assembly_state (frag_now
);
10008 last_frag
= frag_now
;
10009 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10010 xtensa_set_frag_assembly_state (frag_now
);
10012 while (search_frag
!= frag_now
)
10014 next_frag
= search_frag
->fr_next
;
10016 /* First, move the frag out of the literal section and
10017 to the appropriate place. */
10018 if (search_frag
->tc_frag_data
.literal_frag
)
10020 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10021 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10022 /* Note that we set this fr_var to be a fix
10023 chain when we created the literal pool location
10024 as RELAX_LITERAL_POOL_BEGIN. */
10025 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
10027 insert_after
= literal_pool
;
10029 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
10030 insert_after
= insert_after
->fr_next
;
10032 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
10034 *frag_splice
= next_frag
;
10035 search_frag
->fr_next
= insert_after
->fr_next
;
10036 insert_after
->fr_next
= search_frag
;
10037 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10039 /* Now move any fixups associated with this frag to the
10041 fix
= frchain_from
->fix_root
;
10042 fix_splice
= &(frchain_from
->fix_root
);
10045 next_fix
= fix
->fx_next
;
10046 if (fix
->fx_frag
== search_frag
)
10048 *fix_splice
= next_fix
;
10049 fix
->fx_next
= frchain_to
->fix_root
;
10050 frchain_to
->fix_root
= fix
;
10051 if (frchain_to
->fix_tail
== NULL
)
10052 frchain_to
->fix_tail
= fix
;
10055 fix_splice
= &(fix
->fx_next
);
10058 search_frag
= next_frag
;
10061 if (frchain_from
->fix_root
!= NULL
)
10063 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10064 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10066 assert (frchain_from
->fix_root
== NULL
);
10068 frchain_from
->fix_tail
= NULL
;
10069 xtensa_restore_emit_state (&state
);
10070 segment
= segment
->next
;
10073 /* Now fix up the SEGMENT value for all the literal symbols. */
10074 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10076 symbolS
*lit_sym
= lit
->sym
;
10077 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10079 S_SET_SEGMENT (lit_sym
, dest_seg
);
10084 /* Walk over all the frags for segments in a list and mark them as
10085 containing literals. As clunky as this is, we can't rely on frag_var
10086 and frag_variant to get called in all situations. */
10089 mark_literal_frags (seg_list
*segment
)
10091 frchainS
*frchain_from
;
10092 fragS
*search_frag
;
10096 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10097 search_frag
= frchain_from
->frch_root
;
10098 while (search_frag
)
10100 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10101 search_frag
= search_frag
->fr_next
;
10103 segment
= segment
->next
;
10109 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10111 /* Move all of the sections in the section list to come
10112 after "after" in the gnu segment list. */
10117 segT literal_section
= head
->seg
;
10119 /* Move the literal section after "after". */
10120 assert (literal_section
);
10121 if (literal_section
!= after
)
10123 xtensa_remove_section (literal_section
);
10124 xtensa_insert_section (after
, literal_section
);
10132 /* Push all the literal segments to the end of the gnu list. */
10135 xtensa_reorder_segments (void)
10142 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10148 /* Now that we have the last section, push all the literal
10149 sections to the end. */
10150 xtensa_reorder_seg_list (literal_head
, last_sec
);
10151 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10152 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10154 /* Now perform the final error check. */
10155 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10157 assert (new_count
== old_count
);
10161 /* Change the emit state (seg, subseg, and frag related stuff) to the
10162 correct location. Return a emit_state which can be passed to
10163 xtensa_restore_emit_state to return to current fragment. */
10166 xtensa_switch_to_literal_fragment (emit_state
*result
)
10168 if (directive_state
[directive_absolute_literals
])
10170 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10171 &default_lit_sections
.lit4_seg
, FALSE
);
10172 xtensa_switch_section_emit_state (result
,
10173 default_lit_sections
.lit4_seg
, 0);
10176 xtensa_switch_to_non_abs_literal_fragment (result
);
10178 /* Do a 4-byte align here. */
10179 frag_align (2, 0, 0);
10180 record_alignment (now_seg
, 2);
10185 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10187 /* When we mark a literal pool location, we want to put a frag in
10188 the literal pool that points to it. But to do that, we want to
10189 switch_to_literal_fragment. But literal sections don't have
10190 literal pools, so their location is always null, so we would
10191 recurse forever. This is kind of hacky, but it works. */
10193 static bfd_boolean recursive
= FALSE
;
10194 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10195 bfd_boolean is_init
=
10196 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10198 bfd_boolean is_fini
=
10199 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10201 if (pool_location
== NULL
10202 && !use_literal_section
10204 && !is_init
&& ! is_fini
)
10206 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10208 xtensa_mark_literal_pool_location ();
10212 /* Special case: If we are in the ".fini" or ".init" section, then
10213 we will ALWAYS be generating to the ".fini.literal" and
10214 ".init.literal" sections. */
10218 cache_literal_section (init_literal_head
,
10219 default_lit_sections
.init_lit_seg_name
,
10220 &default_lit_sections
.init_lit_seg
, TRUE
);
10221 xtensa_switch_section_emit_state (result
,
10222 default_lit_sections
.init_lit_seg
, 0);
10226 cache_literal_section (fini_literal_head
,
10227 default_lit_sections
.fini_lit_seg_name
,
10228 &default_lit_sections
.fini_lit_seg
, TRUE
);
10229 xtensa_switch_section_emit_state (result
,
10230 default_lit_sections
.fini_lit_seg
, 0);
10234 cache_literal_section (literal_head
,
10235 default_lit_sections
.lit_seg_name
,
10236 &default_lit_sections
.lit_seg
, TRUE
);
10237 xtensa_switch_section_emit_state (result
,
10238 default_lit_sections
.lit_seg
, 0);
10241 if (!use_literal_section
10242 && !is_init
&& !is_fini
10243 && get_literal_pool_location (now_seg
) != pool_location
)
10245 /* Close whatever frag is there. */
10246 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10247 xtensa_set_frag_assembly_state (frag_now
);
10248 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10249 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10250 xtensa_set_frag_assembly_state (frag_now
);
10255 /* Call this function before emitting data into the literal section.
10256 This is a helper function for xtensa_switch_to_literal_fragment.
10257 This is similar to a .section new_now_seg subseg. */
10260 xtensa_switch_section_emit_state (emit_state
*state
,
10262 subsegT new_now_subseg
)
10264 state
->name
= now_seg
->name
;
10265 state
->now_seg
= now_seg
;
10266 state
->now_subseg
= now_subseg
;
10267 state
->generating_literals
= generating_literals
;
10268 generating_literals
++;
10269 subseg_new (segment_name (new_now_seg
), new_now_subseg
);
10273 /* Use to restore the emitting into the normal place. */
10276 xtensa_restore_emit_state (emit_state
*state
)
10278 generating_literals
= state
->generating_literals
;
10279 subseg_new (state
->name
, state
->now_subseg
);
10283 /* Get a segment of a given name. If the segment is already
10284 present, return it; otherwise, create a new one. */
10287 cache_literal_section (seg_list
*head
,
10290 bfd_boolean is_code
)
10292 segT current_section
= now_seg
;
10293 int current_subsec
= now_subseg
;
10299 /* Check if the named section exists. */
10300 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10302 if (!strcmp (segment_name (seg
), name
))
10308 /* Create a new literal section. */
10309 seg
= subseg_new (name
, (subsegT
) 0);
10312 /* Add the newly created literal segment to the specified list. */
10313 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10315 n
->next
= head
->next
;
10318 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10319 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10320 | (is_code
? SEC_CODE
: SEC_DATA
));
10321 bfd_set_section_alignment (stdoutput
, seg
, 2);
10325 subseg_set (current_section
, current_subsec
);
10329 /* Property Tables Stuff. */
10331 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10332 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10333 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10335 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10336 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10338 static bfd_boolean
get_frag_is_literal (const fragS
*);
10339 static void xtensa_create_property_segments
10340 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10341 static void xtensa_create_xproperty_segments
10342 (frag_flags_fn
, const char *, xt_section_type
);
10343 static segment_info_type
*retrieve_segment_info (segT
);
10344 static segT
retrieve_xtensa_section (char *);
10345 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10346 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10347 static void add_xt_block_frags
10348 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10349 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10350 static void xtensa_frag_flags_init (frag_flags
*);
10351 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10352 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10353 static void add_xt_prop_frags
10354 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10356 /* Set up property tables after relaxation. */
10359 xtensa_post_relax_hook (void)
10361 xtensa_move_seg_list_to_beginning (literal_head
);
10362 xtensa_move_seg_list_to_beginning (init_literal_head
);
10363 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10365 xtensa_find_unmarked_state_frags ();
10367 if (use_literal_section
)
10368 xtensa_create_property_segments (get_frag_is_literal
,
10370 XTENSA_LIT_SEC_NAME
,
10372 xtensa_create_xproperty_segments (get_frag_property_flags
,
10373 XTENSA_PROP_SEC_NAME
,
10376 if (warn_unaligned_branch_targets
)
10377 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10378 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10382 /* This function is only meaningful after xtensa_move_literals. */
10385 get_frag_is_literal (const fragS
*fragP
)
10387 assert (fragP
!= NULL
);
10388 return fragP
->tc_frag_data
.is_literal
;
10393 xtensa_create_property_segments (frag_predicate property_function
,
10394 frag_predicate end_property_function
,
10395 const char *section_name_base
,
10396 xt_section_type sec_type
)
10400 /* Walk over all of the current segments.
10401 Walk over each fragment
10402 For each non-empty fragment,
10403 Build a property record (append where possible). */
10405 for (seclist
= &stdoutput
->sections
;
10406 seclist
&& *seclist
;
10407 seclist
= &(*seclist
)->next
)
10409 segT sec
= *seclist
;
10412 flags
= bfd_get_section_flags (stdoutput
, sec
);
10413 if (flags
& SEC_DEBUGGING
)
10415 if (!(flags
& SEC_ALLOC
))
10418 if (section_has_property (sec
, property_function
))
10420 char *property_section_name
=
10421 xtensa_get_property_section_name (sec
, section_name_base
);
10422 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10423 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10424 xtensa_block_info
**xt_blocks
=
10425 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10426 /* Walk over all of the frchains here and add new sections. */
10427 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10428 end_property_function
);
10432 /* Now we fill them out.... */
10434 for (seclist
= &stdoutput
->sections
;
10435 seclist
&& *seclist
;
10436 seclist
= &(*seclist
)->next
)
10438 segment_info_type
*seginfo
;
10439 xtensa_block_info
*block
;
10440 segT sec
= *seclist
;
10442 seginfo
= seg_info (sec
);
10443 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10447 xtensa_block_info
*cur_block
;
10448 /* This is a section with some data. */
10452 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10455 rec_size
= num_recs
* 8;
10456 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10458 /* In order to make this work with the assembler, we have to
10459 build some frags and then build the "fixups" for it. It
10460 would be easier to just set the contents then set the
10465 /* Allocate a fragment and leak it. */
10469 frchainS
*frchainP
;
10473 frag_size
= sizeof (fragS
) + rec_size
;
10474 fragP
= (fragS
*) xmalloc (frag_size
);
10476 memset (fragP
, 0, frag_size
);
10477 fragP
->fr_address
= 0;
10478 fragP
->fr_next
= NULL
;
10479 fragP
->fr_fix
= rec_size
;
10481 fragP
->fr_type
= rs_fill
;
10482 /* The rest are zeros. */
10484 frchainP
= seginfo
->frchainP
;
10485 frchainP
->frch_root
= fragP
;
10486 frchainP
->frch_last
= fragP
;
10488 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10489 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10491 seginfo
->fix_root
= fixes
;
10492 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10494 frag_data
= &fragP
->fr_literal
[0];
10495 for (i
= 0; i
< num_recs
; i
++)
10497 fixS
*fix
= &fixes
[i
];
10498 assert (cur_block
);
10500 /* Write the fixup. */
10501 if (i
!= num_recs
- 1)
10502 fix
->fx_next
= &fixes
[i
+ 1];
10504 fix
->fx_next
= NULL
;
10507 fix
->fx_frag
= fragP
;
10508 fix
->fx_where
= i
* 8;
10509 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10510 fix
->fx_offset
= cur_block
->offset
;
10511 fix
->fx_r_type
= BFD_RELOC_32
;
10512 fix
->fx_file
= "Internal Assembly";
10515 /* Write the length. */
10516 md_number_to_chars (&frag_data
[4 + 8 * i
],
10517 cur_block
->size
, 4);
10518 cur_block
= cur_block
->next
;
10527 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10528 const char *section_name_base
,
10529 xt_section_type sec_type
)
10533 /* Walk over all of the current segments.
10534 Walk over each fragment.
10535 For each fragment that has instructions,
10536 build an instruction record (append where possible). */
10538 for (seclist
= &stdoutput
->sections
;
10539 seclist
&& *seclist
;
10540 seclist
= &(*seclist
)->next
)
10542 segT sec
= *seclist
;
10545 flags
= bfd_get_section_flags (stdoutput
, sec
);
10546 if (flags
& SEC_DEBUGGING
)
10548 if (!(flags
& SEC_ALLOC
))
10551 if (section_has_xproperty (sec
, flag_fn
))
10553 char *property_section_name
=
10554 xtensa_get_property_section_name (sec
, section_name_base
);
10555 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10556 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10557 xtensa_block_info
**xt_blocks
=
10558 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10559 /* Walk over all of the frchains here and add new sections. */
10560 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10564 /* Now we fill them out.... */
10566 for (seclist
= &stdoutput
->sections
;
10567 seclist
&& *seclist
;
10568 seclist
= &(*seclist
)->next
)
10570 segment_info_type
*seginfo
;
10571 xtensa_block_info
*block
;
10572 segT sec
= *seclist
;
10574 seginfo
= seg_info (sec
);
10575 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10579 xtensa_block_info
*cur_block
;
10580 /* This is a section with some data. */
10584 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10587 rec_size
= num_recs
* (8 + 4);
10588 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10590 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10592 /* In order to make this work with the assembler, we have to build
10593 some frags then build the "fixups" for it. It would be easier to
10594 just set the contents then set the arlents. */
10598 /* Allocate a fragment and (unfortunately) leak it. */
10602 frchainS
*frchainP
;
10606 frag_size
= sizeof (fragS
) + rec_size
;
10607 fragP
= (fragS
*) xmalloc (frag_size
);
10609 memset (fragP
, 0, frag_size
);
10610 fragP
->fr_address
= 0;
10611 fragP
->fr_next
= NULL
;
10612 fragP
->fr_fix
= rec_size
;
10614 fragP
->fr_type
= rs_fill
;
10615 /* The rest are zeros. */
10617 frchainP
= seginfo
->frchainP
;
10618 frchainP
->frch_root
= fragP
;
10619 frchainP
->frch_last
= fragP
;
10621 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10622 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10624 seginfo
->fix_root
= fixes
;
10625 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10627 frag_data
= &fragP
->fr_literal
[0];
10628 for (i
= 0; i
< num_recs
; i
++)
10630 fixS
*fix
= &fixes
[i
];
10631 assert (cur_block
);
10633 /* Write the fixup. */
10634 if (i
!= num_recs
- 1)
10635 fix
->fx_next
= &fixes
[i
+ 1];
10637 fix
->fx_next
= NULL
;
10640 fix
->fx_frag
= fragP
;
10641 fix
->fx_where
= i
* (8 + 4);
10642 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10643 fix
->fx_offset
= cur_block
->offset
;
10644 fix
->fx_r_type
= BFD_RELOC_32
;
10645 fix
->fx_file
= "Internal Assembly";
10648 /* Write the length. */
10649 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10650 cur_block
->size
, 4);
10651 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10652 frag_flags_to_number (&cur_block
->flags
),
10654 cur_block
= cur_block
->next
;
10662 static segment_info_type
*
10663 retrieve_segment_info (segT seg
)
10665 segment_info_type
*seginfo
;
10666 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10669 frchainS
*frchainP
;
10671 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10672 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10673 seginfo
->fix_root
= NULL
;
10674 seginfo
->fix_tail
= NULL
;
10675 seginfo
->bfd_section
= seg
;
10677 /* We will not be dealing with these, only our special ones. */
10679 if (seg
== bfd_abs_section_ptr
)
10680 abs_seg_info
= seginfo
;
10681 else if (seg
== bfd_und_section_ptr
)
10682 und_seg_info
= seginfo
;
10685 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10687 seg_fix_rootP
= &segment_info
[seg
].fix_root
;
10688 seg_fix_tailP
= &segment_info
[seg
].fix_tail
;
10691 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10692 frchainP
->frch_root
= NULL
;
10693 frchainP
->frch_last
= NULL
;
10694 frchainP
->frch_next
= NULL
;
10695 frchainP
->frch_seg
= seg
;
10696 frchainP
->frch_subseg
= 0;
10697 frchainP
->fix_root
= NULL
;
10698 frchainP
->fix_tail
= NULL
;
10699 /* Do not init the objstack. */
10700 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10701 /* frchainP->frch_frag_now = fragP; */
10702 frchainP
->frch_frag_now
= NULL
;
10704 seginfo
->frchainP
= frchainP
;
10712 retrieve_xtensa_section (char *sec_name
)
10714 bfd
*abfd
= stdoutput
;
10715 flagword flags
, out_flags
, link_once_flags
;
10718 flags
= bfd_get_section_flags (abfd
, now_seg
);
10719 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10720 if (link_once_flags
)
10721 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10722 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10724 s
= bfd_make_section_old_way (abfd
, sec_name
);
10726 as_bad (_("could not create section %s"), sec_name
);
10727 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10728 as_bad (_("invalid flag combination on section %s"), sec_name
);
10735 section_has_property (segT sec
, frag_predicate property_function
)
10737 segment_info_type
*seginfo
= seg_info (sec
);
10740 if (seginfo
&& seginfo
->frchainP
)
10742 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10744 if (property_function (fragP
)
10745 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10754 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10756 segment_info_type
*seginfo
= seg_info (sec
);
10759 if (seginfo
&& seginfo
->frchainP
)
10761 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10763 frag_flags prop_flags
;
10764 property_function (fragP
, &prop_flags
);
10765 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10773 /* Two types of block sections exist right now: literal and insns. */
10776 add_xt_block_frags (segT sec
,
10778 xtensa_block_info
**xt_block
,
10779 frag_predicate property_function
,
10780 frag_predicate end_property_function
)
10782 segment_info_type
*seg_info
;
10783 segment_info_type
*xt_seg_info
;
10784 bfd_vma seg_offset
;
10787 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10788 seg_info
= retrieve_segment_info (sec
);
10790 /* Build it if needed. */
10791 while (*xt_block
!= NULL
)
10792 xt_block
= &(*xt_block
)->next
;
10793 /* We are either at NULL at the beginning or at the end. */
10795 /* Walk through the frags. */
10798 if (seg_info
->frchainP
)
10800 for (fragP
= seg_info
->frchainP
->frch_root
;
10802 fragP
= fragP
->fr_next
)
10804 if (property_function (fragP
)
10805 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10807 if (*xt_block
!= NULL
)
10809 if ((*xt_block
)->offset
+ (*xt_block
)->size
10810 == fragP
->fr_address
)
10811 (*xt_block
)->size
+= fragP
->fr_fix
;
10813 xt_block
= &((*xt_block
)->next
);
10815 if (*xt_block
== NULL
)
10817 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10818 xmalloc (sizeof (xtensa_block_info
));
10819 new_block
->sec
= sec
;
10820 new_block
->offset
= fragP
->fr_address
;
10821 new_block
->size
= fragP
->fr_fix
;
10822 new_block
->next
= NULL
;
10823 xtensa_frag_flags_init (&new_block
->flags
);
10824 *xt_block
= new_block
;
10826 if (end_property_function
10827 && end_property_function (fragP
))
10829 xt_block
= &((*xt_block
)->next
);
10837 /* Break the encapsulation of add_xt_prop_frags here. */
10840 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10842 if (prop_flags
->is_literal
10843 || prop_flags
->is_insn
10844 || prop_flags
->is_data
10845 || prop_flags
->is_unreachable
)
10852 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10854 memset (prop_flags
, 0, sizeof (frag_flags
));
10859 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10861 xtensa_frag_flags_init (prop_flags
);
10862 if (fragP
->tc_frag_data
.is_literal
)
10863 prop_flags
->is_literal
= TRUE
;
10864 if (fragP
->tc_frag_data
.is_unreachable
)
10865 prop_flags
->is_unreachable
= TRUE
;
10866 else if (fragP
->tc_frag_data
.is_insn
)
10868 prop_flags
->is_insn
= TRUE
;
10869 if (fragP
->tc_frag_data
.is_loop_target
)
10870 prop_flags
->insn
.is_loop_target
= TRUE
;
10871 if (fragP
->tc_frag_data
.is_branch_target
)
10872 prop_flags
->insn
.is_branch_target
= TRUE
;
10873 if (fragP
->tc_frag_data
.is_specific_opcode
10874 || fragP
->tc_frag_data
.is_no_transform
)
10875 prop_flags
->insn
.is_no_transform
= TRUE
;
10876 if (fragP
->tc_frag_data
.is_no_density
)
10877 prop_flags
->insn
.is_no_density
= TRUE
;
10878 if (fragP
->tc_frag_data
.use_absolute_literals
)
10879 prop_flags
->insn
.is_abslit
= TRUE
;
10881 if (fragP
->tc_frag_data
.is_align
)
10883 prop_flags
->is_align
= TRUE
;
10884 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10885 if (xtensa_frag_flags_is_empty (prop_flags
))
10886 prop_flags
->is_data
= TRUE
;
10892 frag_flags_to_number (const frag_flags
*prop_flags
)
10895 if (prop_flags
->is_literal
)
10896 num
|= XTENSA_PROP_LITERAL
;
10897 if (prop_flags
->is_insn
)
10898 num
|= XTENSA_PROP_INSN
;
10899 if (prop_flags
->is_data
)
10900 num
|= XTENSA_PROP_DATA
;
10901 if (prop_flags
->is_unreachable
)
10902 num
|= XTENSA_PROP_UNREACHABLE
;
10903 if (prop_flags
->insn
.is_loop_target
)
10904 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10905 if (prop_flags
->insn
.is_branch_target
)
10907 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10908 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10911 if (prop_flags
->insn
.is_no_density
)
10912 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10913 if (prop_flags
->insn
.is_no_transform
)
10914 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10915 if (prop_flags
->insn
.is_no_reorder
)
10916 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10917 if (prop_flags
->insn
.is_abslit
)
10918 num
|= XTENSA_PROP_INSN_ABSLIT
;
10920 if (prop_flags
->is_align
)
10922 num
|= XTENSA_PROP_ALIGN
;
10923 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10931 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10932 const frag_flags
*prop_flags_2
)
10934 /* Cannot combine with an end marker. */
10936 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10938 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10940 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10943 if (prop_flags_1
->is_insn
)
10945 /* Properties of the beginning of the frag. */
10946 if (prop_flags_2
->insn
.is_loop_target
)
10948 if (prop_flags_2
->insn
.is_branch_target
)
10950 if (prop_flags_1
->insn
.is_no_density
!=
10951 prop_flags_2
->insn
.is_no_density
)
10953 if (prop_flags_1
->insn
.is_no_transform
!=
10954 prop_flags_2
->insn
.is_no_transform
)
10956 if (prop_flags_1
->insn
.is_no_reorder
!=
10957 prop_flags_2
->insn
.is_no_reorder
)
10959 if (prop_flags_1
->insn
.is_abslit
!=
10960 prop_flags_2
->insn
.is_abslit
)
10964 if (prop_flags_1
->is_align
)
10972 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10977 if (!xt_block
->flags
.is_align
)
10978 return xt_block
->size
;
10980 end_addr
= xt_block
->offset
+ xt_block
->size
;
10981 align_bits
= xt_block
->flags
.alignment
;
10982 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10983 return end_addr
- xt_block
->offset
;
10988 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10989 const xtensa_block_info
*xt_block_2
)
10991 if (xt_block
->sec
!= xt_block_2
->sec
)
10993 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10994 != xt_block_2
->offset
)
10997 if (xt_block_2
->size
== 0
10998 && (!xt_block_2
->flags
.is_unreachable
10999 || xt_block
->flags
.is_unreachable
))
11001 if (xt_block_2
->flags
.is_align
11002 && xt_block
->flags
.is_align
)
11004 /* Nothing needed. */
11005 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11010 if (xt_block_2
->flags
.is_align
)
11012 /* Push alignment to previous entry. */
11013 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11014 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11019 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11020 &xt_block_2
->flags
))
11023 xt_block
->size
+= xt_block_2
->size
;
11025 if (xt_block_2
->flags
.is_align
)
11027 xt_block
->flags
.is_align
= TRUE
;
11028 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11036 add_xt_prop_frags (segT sec
,
11038 xtensa_block_info
**xt_block
,
11039 frag_flags_fn property_function
)
11041 segment_info_type
*seg_info
;
11042 segment_info_type
*xt_seg_info
;
11043 bfd_vma seg_offset
;
11046 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
11047 seg_info
= retrieve_segment_info (sec
);
11048 /* Build it if needed. */
11049 while (*xt_block
!= NULL
)
11051 xt_block
= &(*xt_block
)->next
;
11053 /* We are either at NULL at the beginning or at the end. */
11055 /* Walk through the frags. */
11058 if (seg_info
->frchainP
)
11060 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
11061 fragP
= fragP
->fr_next
)
11063 xtensa_block_info tmp_block
;
11064 tmp_block
.sec
= sec
;
11065 tmp_block
.offset
= fragP
->fr_address
;
11066 tmp_block
.size
= fragP
->fr_fix
;
11067 tmp_block
.next
= NULL
;
11068 property_function (fragP
, &tmp_block
.flags
);
11070 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11071 /* && fragP->fr_fix != 0) */
11073 if ((*xt_block
) == NULL
11074 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11076 xtensa_block_info
*new_block
;
11077 if ((*xt_block
) != NULL
)
11078 xt_block
= &(*xt_block
)->next
;
11079 new_block
= (xtensa_block_info
*)
11080 xmalloc (sizeof (xtensa_block_info
));
11081 *new_block
= tmp_block
;
11082 *xt_block
= new_block
;
11090 /* op_placement_info_table */
11092 /* op_placement_info makes it easier to determine which
11093 ops can go in which slots. */
11096 init_op_placement_info_table (void)
11098 xtensa_isa isa
= xtensa_default_isa
;
11099 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11100 xtensa_opcode opcode
;
11103 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11105 op_placement_table
= (op_placement_info_table
)
11106 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11107 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11109 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11111 op_placement_info
*opi
= &op_placement_table
[opcode
];
11112 /* FIXME: Make tinsn allocation dynamic. */
11113 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
11114 as_fatal (_("too many operands in instruction"));
11115 opi
->single
= XTENSA_UNDEFINED
;
11116 opi
->single_size
= 0;
11117 opi
->widest
= XTENSA_UNDEFINED
;
11118 opi
->widest_size
= 0;
11119 opi
->narrowest
= XTENSA_UNDEFINED
;
11120 opi
->narrowest_size
= 0x7F;
11122 opi
->num_formats
= 0;
11124 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11126 opi
->slots
[fmt
] = 0;
11127 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11129 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11131 int fmt_length
= xtensa_format_length (isa
, fmt
);
11133 set_bit (fmt
, opi
->formats
);
11134 set_bit (slot
, opi
->slots
[fmt
]);
11135 /* opi->slot_count[fmt]++; */
11136 if (fmt_length
< opi
->narrowest_size
)
11138 opi
->narrowest
= fmt
;
11139 opi
->narrowest_size
= fmt_length
;
11141 if (fmt_length
> opi
->widest_size
)
11144 opi
->widest_size
= fmt_length
;
11146 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11148 if (opi
->single_size
== 0
11149 || fmt_length
< opi
->single_size
)
11152 opi
->single_size
= fmt_length
;
11158 opi
->num_formats
++;
11161 xtensa_insnbuf_free (isa
, ibuf
);
11166 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11168 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11172 /* If the opcode is available in a single slot format, return its size. */
11175 xg_get_single_size (xtensa_opcode opcode
)
11177 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11178 return op_placement_table
[opcode
].single_size
;
11182 static xtensa_format
11183 xg_get_single_format (xtensa_opcode opcode
)
11185 return op_placement_table
[opcode
].single
;
11189 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11192 istack_init (IStack
*stack
)
11194 memset (stack
, 0, sizeof (IStack
));
11200 istack_empty (IStack
*stack
)
11202 return (stack
->ninsn
== 0);
11207 istack_full (IStack
*stack
)
11209 return (stack
->ninsn
== MAX_ISTACK
);
11213 /* Return a pointer to the top IStack entry.
11214 It is an error to call this if istack_empty () is TRUE. */
11217 istack_top (IStack
*stack
)
11219 int rec
= stack
->ninsn
- 1;
11220 assert (!istack_empty (stack
));
11221 return &stack
->insn
[rec
];
11225 /* Add a new TInsn to an IStack.
11226 It is an error to call this if istack_full () is TRUE. */
11229 istack_push (IStack
*stack
, TInsn
*insn
)
11231 int rec
= stack
->ninsn
;
11232 assert (!istack_full (stack
));
11233 stack
->insn
[rec
] = *insn
;
11238 /* Clear space for the next TInsn on the IStack and return a pointer
11239 to it. It is an error to call this if istack_full () is TRUE. */
11242 istack_push_space (IStack
*stack
)
11244 int rec
= stack
->ninsn
;
11246 assert (!istack_full (stack
));
11247 insn
= &stack
->insn
[rec
];
11248 memset (insn
, 0, sizeof (TInsn
));
11254 /* Remove the last pushed instruction. It is an error to call this if
11255 istack_empty () returns TRUE. */
11258 istack_pop (IStack
*stack
)
11260 int rec
= stack
->ninsn
- 1;
11261 assert (!istack_empty (stack
));
11263 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11267 /* TInsn functions. */
11270 tinsn_init (TInsn
*dst
)
11272 memset (dst
, 0, sizeof (TInsn
));
11276 /* Get the ``num''th token of the TInsn.
11277 It is illegal to call this if num > insn->ntoks. */
11280 tinsn_get_tok (TInsn
*insn
, int num
)
11282 assert (num
< insn
->ntok
);
11283 return &insn
->tok
[num
];
11287 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11290 tinsn_has_symbolic_operands (const TInsn
*insn
)
11293 int n
= insn
->ntok
;
11295 assert (insn
->insn_type
== ITYPE_INSN
);
11297 for (i
= 0; i
< n
; ++i
)
11299 switch (insn
->tok
[i
].X_op
)
11313 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11315 xtensa_isa isa
= xtensa_default_isa
;
11317 int n
= insn
->ntok
;
11319 assert (insn
->insn_type
== ITYPE_INSN
);
11321 for (i
= 0; i
< n
; ++i
)
11323 switch (insn
->tok
[i
].X_op
)
11331 /* Errors for these types are caught later. */
11336 /* Symbolic immediates are only allowed on the last immediate
11337 operand. At this time, CONST16 is the only opcode where we
11338 support non-PC-relative relocations. (It isn't necessary
11339 to complain about non-PC-relative relocations here, but
11340 otherwise, no error is reported until the relocations are
11341 generated, and the assembler won't get that far if there
11342 are any other errors. It's nice to see all the problems
11344 if (i
!= get_relaxable_immed (insn
->opcode
)
11345 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11346 && insn
->opcode
!= xtensa_const16_opcode
))
11348 as_bad (_("invalid symbolic operand %d on '%s'"),
11349 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11358 /* For assembly code with complex expressions (e.g. subtraction),
11359 we have to build them in the literal pool so that
11360 their results are calculated correctly after relaxation.
11361 The relaxation only handles expressions that
11362 boil down to SYMBOL + OFFSET. */
11365 tinsn_has_complex_operands (const TInsn
*insn
)
11368 int n
= insn
->ntok
;
11369 assert (insn
->insn_type
== ITYPE_INSN
);
11370 for (i
= 0; i
< n
; ++i
)
11372 switch (insn
->tok
[i
].X_op
)
11388 /* Convert the constant operands in the tinsn to insnbuf.
11389 Return TRUE if there is a symbol in the immediate field.
11391 Before this is called,
11392 1) the number of operands are correct
11393 2) the tinsn is a ITYPE_INSN
11394 3) ONLY the relaxable_ is built
11395 4) All operands are O_constant, O_symbol. All constants fit
11396 The return value tells whether there are any remaining O_symbols. */
11399 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11401 static xtensa_insnbuf slotbuf
= 0;
11402 xtensa_isa isa
= xtensa_default_isa
;
11403 xtensa_opcode opcode
= tinsn
->opcode
;
11404 xtensa_format fmt
= xg_get_single_format (opcode
);
11405 bfd_boolean has_fixup
= FALSE
;
11406 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11413 slotbuf
= xtensa_insnbuf_alloc (isa
);
11415 assert (tinsn
->insn_type
== ITYPE_INSN
);
11416 if (noperands
!= tinsn
->ntok
)
11417 as_fatal (_("operand number mismatch"));
11419 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11420 as_fatal (_("cannot encode opcode"));
11422 for (i
= 0; i
< noperands
; ++i
)
11424 expressionS
*expr
= &tinsn
->tok
[i
];
11425 switch (expr
->X_op
)
11428 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11430 /* The register number has already been checked in
11431 expression_maybe_register, so we don't need to check here. */
11432 opnd_value
= expr
->X_add_number
;
11433 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11434 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11435 slotbuf
, opnd_value
);
11439 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11441 as_where (&file_name
, &line
);
11442 /* It is a constant and we called this function,
11443 then we have to try to fit it. */
11444 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11445 expr
->X_add_number
, file_name
, line
);
11454 xtensa_format_encode (isa
, fmt
, insnbuf
);
11455 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11461 /* Convert the constant operands in the tinsn to slotbuf.
11462 Return TRUE if there is a symbol in the immediate field.
11463 (Eventually this should replace tinsn_to_insnbuf.) */
11465 /* Before this is called,
11466 1) the number of operands are correct
11467 2) the tinsn is a ITYPE_INSN
11468 3) ONLY the relaxable_ is built
11469 4) All operands are
11470 O_constant, O_symbol
11473 The return value tells whether there are any remaining O_symbols. */
11476 tinsn_to_slotbuf (xtensa_format fmt
,
11479 xtensa_insnbuf slotbuf
)
11481 xtensa_isa isa
= xtensa_default_isa
;
11482 xtensa_opcode opcode
= tinsn
->opcode
;
11483 bfd_boolean has_fixup
= FALSE
;
11484 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11487 *((int *) &slotbuf
[0]) = 0;
11488 *((int *) &slotbuf
[1]) = 0;
11489 assert (tinsn
->insn_type
== ITYPE_INSN
);
11490 if (noperands
!= tinsn
->ntok
)
11491 as_fatal (_("operand number mismatch"));
11493 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11495 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11496 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11500 for (i
= 0; i
< noperands
; i
++)
11502 expressionS
*expr
= &tinsn
->tok
[i
];
11507 switch (expr
->X_op
)
11510 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11512 /* The register number has already been checked in
11513 expression_maybe_register, so we don't need to check here. */
11514 opnd_value
= expr
->X_add_number
;
11515 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11516 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11519 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11523 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11525 as_where (&file_name
, &line
);
11526 /* It is a constant and we called this function
11527 then we have to try to fit it. */
11528 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11529 expr
->X_add_number
, file_name
, line
);
11542 /* Check the instruction arguments. Return TRUE on failure. */
11545 tinsn_check_arguments (const TInsn
*insn
)
11547 xtensa_isa isa
= xtensa_default_isa
;
11548 xtensa_opcode opcode
= insn
->opcode
;
11550 if (opcode
== XTENSA_UNDEFINED
)
11552 as_bad (_("invalid opcode"));
11556 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11558 as_bad (_("too few operands"));
11562 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11564 as_bad (_("too many operands"));
11571 /* Load an instruction from its encoded form. */
11574 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11578 xg_init_vinsn (&vinsn
);
11579 vinsn_from_chars (&vinsn
, f
);
11581 *tinsn
= vinsn
.slots
[slot
];
11582 xg_free_vinsn (&vinsn
);
11587 tinsn_from_insnbuf (TInsn
*tinsn
,
11588 xtensa_insnbuf slotbuf
,
11593 xtensa_isa isa
= xtensa_default_isa
;
11595 /* Find the immed. */
11596 tinsn_init (tinsn
);
11597 tinsn
->insn_type
= ITYPE_INSN
;
11598 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11599 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11600 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11601 for (i
= 0; i
< tinsn
->ntok
; i
++)
11603 set_expr_const (&tinsn
->tok
[i
],
11604 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11605 tinsn
->opcode
, i
));
11610 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11613 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11615 xtensa_opcode opcode
= tinsn
->opcode
;
11618 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11620 opnum
= get_relaxable_immed (opcode
);
11621 assert (opnum
>= 0);
11622 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11624 set_expr_symbol_offset_diff
11625 (&tinsn
->tok
[opnum
],
11626 fragP
->tc_frag_data
.slot_symbols
[slot
],
11627 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11628 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11632 set_expr_symbol_offset
11633 (&tinsn
->tok
[opnum
],
11634 fragP
->tc_frag_data
.slot_symbols
[slot
],
11635 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11642 get_num_stack_text_bytes (IStack
*istack
)
11645 int text_bytes
= 0;
11647 for (i
= 0; i
< istack
->ninsn
; i
++)
11649 TInsn
*tinsn
= &istack
->insn
[i
];
11650 if (tinsn
->insn_type
== ITYPE_INSN
)
11651 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11658 get_num_stack_literal_bytes (IStack
*istack
)
11663 for (i
= 0; i
< istack
->ninsn
; i
++)
11665 TInsn
*tinsn
= &istack
->insn
[i
];
11666 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11673 /* vliw_insn functions. */
11676 xg_init_vinsn (vliw_insn
*v
)
11679 xtensa_isa isa
= xtensa_default_isa
;
11681 xg_clear_vinsn (v
);
11683 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11684 if (v
->insnbuf
== NULL
)
11685 as_fatal (_("out of memory"));
11687 for (i
= 0; i
< MAX_SLOTS
; i
++)
11689 tinsn_init (&v
->slots
[i
]);
11690 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11691 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11692 if (v
->slotbuf
[i
] == NULL
)
11693 as_fatal (_("out of memory"));
11699 xg_clear_vinsn (vliw_insn
*v
)
11702 v
->format
= XTENSA_UNDEFINED
;
11704 v
->inside_bundle
= FALSE
;
11706 if (xt_saved_debug_type
!= DEBUG_NONE
)
11707 debug_type
= xt_saved_debug_type
;
11709 for (i
= 0; i
< MAX_SLOTS
; i
++)
11711 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11712 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11718 vinsn_has_specific_opcodes (vliw_insn
*v
)
11722 for (i
= 0; i
< v
->num_slots
; i
++)
11724 if (v
->slots
[i
].is_specific_opcode
)
11732 xg_free_vinsn (vliw_insn
*v
)
11735 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11736 for (i
= 0; i
< MAX_SLOTS
; i
++)
11737 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11741 /* Before this is called, we should have
11742 filled out the following fields:
11744 1) the number of operands for each opcode are correct
11745 2) the tinsn in the slots are ITYPE_INSN
11746 3) ONLY the relaxable_ is built
11747 4) All operands are
11748 O_constant, O_symbol
11751 The return value tells whether there are any remaining O_symbols. */
11754 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11757 bfd_boolean record_fixup
)
11759 xtensa_isa isa
= xtensa_default_isa
;
11760 xtensa_format fmt
= vinsn
->format
;
11761 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11763 bfd_boolean has_fixup
= FALSE
;
11765 xtensa_format_encode (isa
, fmt
, insnbuf
);
11767 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11769 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11770 bfd_boolean tinsn_has_fixup
=
11771 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11772 vinsn
->slotbuf
[slot
]);
11774 xtensa_format_set_slot (isa
, fmt
, slot
,
11775 insnbuf
, vinsn
->slotbuf
[slot
]);
11776 /* tinsn_has_fixup tracks if there is a fixup at all.
11777 record_fixup controls globally. I.E., we use this
11778 function from several places, some of which are after
11779 fixups have already been recorded. Finally,
11780 tinsn->record_fixup controls based on the individual ops,
11781 which may or may not need it based on the relaxation
11783 if (tinsn_has_fixup
&& record_fixup
)
11786 xtensa_opcode opcode
= tinsn
->opcode
;
11787 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11790 for (i
= 0; i
< noperands
; i
++)
11792 expressionS
* expr
= &tinsn
->tok
[i
];
11793 switch (expr
->X_op
)
11798 if (get_relaxable_immed (opcode
) == i
)
11800 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11802 if (!xg_add_opcode_fix
11803 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11804 frag_offset
- fragP
->fr_literal
))
11805 as_bad (_("instruction with constant operands does not fit"));
11809 tinsn
->symbol
= expr
->X_add_symbol
;
11810 tinsn
->offset
= expr
->X_add_number
;
11814 as_bad (_("invalid operand %d on '%s'"),
11815 i
, xtensa_opcode_name (isa
, opcode
));
11823 if (get_relaxable_immed (opcode
) == i
)
11825 if (tinsn
->record_fix
)
11826 as_bad (_("invalid subtract operand"));
11829 tinsn
->symbol
= expr
->X_add_symbol
;
11830 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11831 tinsn
->offset
= expr
->X_add_number
;
11835 as_bad (_("invalid operand %d on '%s'"),
11836 i
, xtensa_opcode_name (isa
, opcode
));
11840 as_bad (_("invalid expression for operand %d on '%s'"),
11841 i
, xtensa_opcode_name (isa
, opcode
));
11853 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11855 static xtensa_insnbuf insnbuf
= NULL
;
11856 static xtensa_insnbuf slotbuf
= NULL
;
11859 xtensa_isa isa
= xtensa_default_isa
;
11863 insnbuf
= xtensa_insnbuf_alloc (isa
);
11864 slotbuf
= xtensa_insnbuf_alloc (isa
);
11867 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
11868 fmt
= xtensa_format_decode (isa
, insnbuf
);
11869 if (fmt
== XTENSA_UNDEFINED
)
11870 as_fatal (_("cannot decode instruction format"));
11871 vinsn
->format
= fmt
;
11872 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11874 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11876 TInsn
*tinsn
= &vinsn
->slots
[i
];
11877 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11878 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11883 /* Expression utilities. */
11885 /* Return TRUE if the expression is an integer constant. */
11888 expr_is_const (const expressionS
*s
)
11890 return (s
->X_op
== O_constant
);
11894 /* Get the expression constant.
11895 Calling this is illegal if expr_is_const () returns TRUE. */
11898 get_expr_const (const expressionS
*s
)
11900 assert (expr_is_const (s
));
11901 return s
->X_add_number
;
11905 /* Set the expression to a constant value. */
11908 set_expr_const (expressionS
*s
, offsetT val
)
11910 s
->X_op
= O_constant
;
11911 s
->X_add_number
= val
;
11912 s
->X_add_symbol
= NULL
;
11913 s
->X_op_symbol
= NULL
;
11918 expr_is_register (const expressionS
*s
)
11920 return (s
->X_op
== O_register
);
11924 /* Get the expression constant.
11925 Calling this is illegal if expr_is_const () returns TRUE. */
11928 get_expr_register (const expressionS
*s
)
11930 assert (expr_is_register (s
));
11931 return s
->X_add_number
;
11935 /* Set the expression to a symbol + constant offset. */
11938 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11940 s
->X_op
= O_symbol
;
11941 s
->X_add_symbol
= sym
;
11942 s
->X_op_symbol
= NULL
; /* unused */
11943 s
->X_add_number
= offset
;
11947 /* Set the expression to symbol - minus_sym + offset. */
11950 set_expr_symbol_offset_diff (expressionS
*s
,
11952 symbolS
*minus_sym
,
11955 s
->X_op
= O_subtract
;
11956 s
->X_add_symbol
= sym
;
11957 s
->X_op_symbol
= minus_sym
; /* unused */
11958 s
->X_add_number
= offset
;
11962 /* Return TRUE if the two expressions are equal. */
11965 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11967 if (s1
->X_op
!= s2
->X_op
)
11969 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11971 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11973 if (s1
->X_add_number
!= s2
->X_add_number
)
11980 copy_expr (expressionS
*dst
, const expressionS
*src
)
11982 memcpy (dst
, src
, sizeof (expressionS
));
11986 /* Support for the "--rename-section" option. */
11988 struct rename_section_struct
11992 struct rename_section_struct
*next
;
11995 static struct rename_section_struct
*section_rename
;
11998 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11999 entries to the section_rename list. Note: Specifying multiple
12000 renamings separated by colons is not documented and is retained only
12001 for backward compatibility. */
12004 build_section_rename (const char *arg
)
12006 struct rename_section_struct
*r
;
12007 char *this_arg
= NULL
;
12008 char *next_arg
= NULL
;
12010 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12012 char *old_name
, *new_name
;
12016 next_arg
= strchr (this_arg
, ':');
12024 old_name
= this_arg
;
12025 new_name
= strchr (this_arg
, '=');
12027 if (*old_name
== '\0')
12029 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12032 if (!new_name
|| new_name
[1] == '\0')
12034 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12041 /* Check for invalid section renaming. */
12042 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12044 if (strcmp (r
->old_name
, old_name
) == 0)
12045 as_bad (_("section %s renamed multiple times"), old_name
);
12046 if (strcmp (r
->new_name
, new_name
) == 0)
12047 as_bad (_("multiple sections remapped to output section %s"),
12052 r
= (struct rename_section_struct
*)
12053 xmalloc (sizeof (struct rename_section_struct
));
12054 r
->old_name
= xstrdup (old_name
);
12055 r
->new_name
= xstrdup (new_name
);
12056 r
->next
= section_rename
;
12057 section_rename
= r
;
12063 xtensa_section_rename (char *name
)
12065 struct rename_section_struct
*r
= section_rename
;
12067 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12069 if (strcmp (r
->old_name
, name
) == 0)
12070 return r
->new_name
;