1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static void error_reset_cur_vinsn
PARAMS ((void));
78 static vliw_insn cur_vinsn
;
80 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
104 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. */
110 typedef struct lit_state_struct
112 const char *lit_seg_name
;
113 const char *lit4_seg_name
;
114 const char *init_lit_seg_name
;
115 const char *fini_lit_seg_name
;
122 static lit_state default_lit_sections
;
125 /* We keep lists of literal segments. The seg_list type is the node
126 for such a list. The *_literal_head locals are the heads of the
127 various lists. All of these lists have a dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
137 static seg_list init_literal_head_h
;
138 static seg_list
*init_literal_head
= &init_literal_head_h
;
139 static seg_list fini_literal_head_h
;
140 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
143 /* Lists of symbols. We keep a list of symbols that label the current
144 instruction, so that we can adjust the symbols when inserting alignment
145 for various instructions. We also keep a list of all the symbols on
146 literals, so that we can fix up those symbols when the literals are
147 later moved into the text sections. */
149 typedef struct sym_list_struct
151 struct sym_list_struct
*next
;
155 static sym_list
*insn_labels
= NULL
;
156 static sym_list
*free_insn_labels
= NULL
;
157 static sym_list
*saved_insn_labels
= NULL
;
159 static sym_list
*literal_syms
;
162 /* Flags to determine whether to prefer const16 or l32r
163 if both options are available. */
164 int prefer_const16
= 0;
167 /* Global flag to indicate when we are emitting literals. */
168 int generating_literals
= 0;
170 /* The following PROPERTY table definitions are copied from
171 <elf/xtensa.h> and must be kept in sync with the code there. */
173 /* Flags in the property tables to specify whether blocks of memory
174 are literals, instructions, data, or unreachable. For
175 instructions, blocks that begin loop targets and branch targets are
176 designated. Blocks that do not allow density, instruction
177 reordering or transformation are also specified. Finally, for
178 branch targets, branch target alignment priority is included.
179 Alignment of the next block is specified in the current block
180 and the size of the current block does not include any fill required
181 to align to the next block. */
183 #define XTENSA_PROP_LITERAL 0x00000001
184 #define XTENSA_PROP_INSN 0x00000002
185 #define XTENSA_PROP_DATA 0x00000004
186 #define XTENSA_PROP_UNREACHABLE 0x00000008
187 /* Instruction only properties at beginning of code. */
188 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
189 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
190 /* Instruction only properties about code. */
191 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
192 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
193 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
195 /* Branch target alignment information. This transmits information
196 to the linker optimization about the priority of aligning a
197 particular block for branch target alignment: None, low priority,
198 high priority, or required. These only need to be checked in
199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
202 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
203 case XTENSA_PROP_BT_ALIGN_NONE:
204 case XTENSA_PROP_BT_ALIGN_LOW:
205 case XTENSA_PROP_BT_ALIGN_HIGH:
206 case XTENSA_PROP_BT_ALIGN_REQUIRE:
208 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
210 /* No branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
212 /* Low priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
214 /* High priority branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
216 /* Required branch target alignment. */
217 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
219 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
221 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
226 /* Alignment is specified in the block BEFORE the one that needs
227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
228 get the required alignment specified as a power of 2. Use
229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
230 alignment. Be careful of side effects since the SET will evaluate
231 flags twice. Also, note that the SIZE of a block in the property
232 table does not include the alignment size, so the alignment fill
233 must be calculated to determine if two blocks are contiguous.
234 TEXT_ALIGN is not currently implemented but is a placeholder for a
235 possible future implementation. */
237 #define XTENSA_PROP_ALIGN 0x00000800
239 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
241 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
243 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
247 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
250 /* Structure for saving instruction and alignment per-fragment data
251 that will be written to the object file. This structure is
252 equivalent to the actual data that will be written out to the file
253 but is easier to use. We provide a conversion to file flags
254 in frag_flags_to_number. */
256 typedef struct frag_flags_struct frag_flags
;
258 struct frag_flags_struct
260 /* is_literal should only be used after xtensa_move_literals.
261 If you need to check if you are generating a literal fragment,
262 then use the generating_literals global. */
264 unsigned is_literal
: 1;
265 unsigned is_insn
: 1;
266 unsigned is_data
: 1;
267 unsigned is_unreachable
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
277 /* is_specific_opcode implies no_transform. */
278 unsigned is_no_transform
: 1;
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* A map that keeps information on a per-subsegment basis. This is
313 maintained during initial assembly, but is invalid once the
314 subsegments are smashed together. I.E., it cannot be used during
317 typedef struct subseg_map_struct
325 /* the fall-through frequency + the branch target frequency
326 typically used for the instruction after a call */
327 float cur_total_freq
;
328 /* the branch target frequency alone */
329 float cur_target_freq
;
331 struct subseg_map_struct
*next
;
335 /* Opcode placement information */
337 typedef unsigned long long bitfield
;
338 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
339 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
340 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
342 #define MAX_FORMATS 32
344 typedef struct op_placement_info_struct
347 /* A number describing how restrictive the issue is for this
348 opcode. For example, an opcode that fits lots of different
349 formats has a high freedom, as does an opcode that fits
350 only one format but many slots in that format. The most
351 restrictive is the opcode that fits only one slot in one
354 /* The single format (i.e., if the op can live in a bundle by itself),
355 narrowest format, and widest format the op can be bundled in
357 xtensa_format single
;
358 xtensa_format narrowest
;
359 xtensa_format widest
;
364 /* formats is a bitfield with the Nth bit set
365 if the opcode fits in the Nth xtensa_format. */
368 /* slots[N]'s Mth bit is set if the op fits in the
369 Mth slot of the Nth xtensa_format. */
370 bitfield slots
[MAX_FORMATS
];
372 /* A count of the number of slots in a given format
373 an op can fit (i.e., the bitcount of the slot field above). */
374 char slots_in_format
[MAX_FORMATS
];
376 } op_placement_info
, *op_placement_info_table
;
378 op_placement_info_table op_placement_table
;
381 /* Extra expression types. */
383 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
384 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
385 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
398 directive_literal_prefix
,
400 directive_absolute_literals
,
401 directive_last_directive
407 bfd_boolean can_be_negated
;
410 const directive_infoS directive_info
[] =
413 { "literal", FALSE
},
415 { "transform", TRUE
},
416 { "freeregs", FALSE
},
417 { "longcalls", TRUE
},
418 { "literal_prefix", FALSE
},
419 { "schedule", TRUE
},
420 { "absolute-literals", TRUE
}
423 bfd_boolean directive_state
[] =
427 #if !XCHAL_HAVE_DENSITY
432 TRUE
, /* transform */
433 FALSE
, /* freeregs */
434 FALSE
, /* longcalls */
435 FALSE
, /* literal_prefix */
437 #if XSHAL_USE_ABSOLUTE_LITERALS
438 TRUE
/* absolute_literals */
440 FALSE
/* absolute_literals */
444 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
445 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
447 /* Command-line option functions. */
448 static void xtensa_setup_hw_workarounds
PARAMS ((int, int));
450 /* Directive functions. */
452 static bfd_boolean use_transform
454 static bfd_boolean use_longcalls
456 static bfd_boolean do_align_targets
458 static void directive_push
459 PARAMS ((directiveE
, bfd_boolean
, const void *));
460 static void directive_pop
461 PARAMS ((directiveE
*, bfd_boolean
*, const char **,
462 unsigned int *, const void **));
463 static void directive_balance
465 static bfd_boolean inside_directive
466 PARAMS ((directiveE
));
467 static void get_directive
468 PARAMS ((directiveE
*, bfd_boolean
*));
469 static void xtensa_begin_directive
471 static void xtensa_end_directive
473 static void xtensa_dwarf2_directive_loc
475 static void xtensa_dwarf2_emit_insn
476 PARAMS ((int, struct dwarf2_line_info
*));
477 static void xtensa_literal_prefix
478 PARAMS ((char const *, int));
479 static void xtensa_literal_position
481 static void xtensa_literal_pseudo
483 static void xtensa_frequency_pseudo
485 static void xtensa_elf_cons
487 static bfd_reloc_code_real_type xtensa_elf_suffix
488 PARAMS ((char **, expressionS
*));
490 /* Parsing and Idiom Translation Functions. */
492 static const char *expression_end
493 PARAMS ((const char *));
494 static unsigned tc_get_register
495 PARAMS ((const char *));
496 static void expression_maybe_register
497 PARAMS ((xtensa_opcode
, int, expressionS
*));
498 static int tokenize_arguments
499 PARAMS ((char **, char *));
500 static bfd_boolean parse_arguments
501 PARAMS ((TInsn
*, int, char **));
502 static int get_invisible_operands
504 static int xg_translate_idioms
505 PARAMS ((char **, int *, char **));
506 static int xg_translate_sysreg_op
507 PARAMS ((char **, int *, char **));
508 static int xtensa_translate_old_userreg_ops
510 static int xtensa_translate_zero_immed
511 PARAMS ((char *, char *, char **, int *, char **));
512 static void xg_reverse_shift_count
514 static int xg_arg_is_constant
515 PARAMS ((char *, offsetT
*));
516 static void xg_replace_opname
517 PARAMS ((char **, char *));
518 static int xg_check_num_args
519 PARAMS ((int *, int, char *, char **));
521 /* Functions for dealing with the Xtensa ISA. */
523 static int get_relaxable_immed
524 PARAMS ((xtensa_opcode
));
525 static xtensa_opcode get_opcode_from_buf
526 PARAMS ((const char *, int));
527 #ifdef TENSILICA_DEBUG
528 static void xtensa_print_insn_table
530 static void print_vliw_insn
531 PARAMS ((xtensa_insnbuf
));
533 static bfd_boolean is_direct_call_opcode
534 PARAMS ((xtensa_opcode
));
535 static bfd_boolean is_entry_opcode
536 PARAMS ((xtensa_opcode
));
537 static bfd_boolean is_movi_opcode
538 PARAMS ((xtensa_opcode
));
539 static bfd_boolean is_the_loop_opcode
540 PARAMS ((xtensa_opcode
));
541 static bfd_boolean is_jx_opcode
542 PARAMS ((xtensa_opcode
));
543 static bfd_boolean is_windowed_return_opcode
544 PARAMS ((xtensa_opcode
));
545 static int decode_reloc
546 PARAMS ((bfd_reloc_code_real_type
, int *, bfd_boolean
*));
547 static bfd_reloc_code_real_type encode_reloc
549 static bfd_reloc_code_real_type encode_alt_reloc
551 static void xtensa_insnbuf_set_operand
552 PARAMS ((xtensa_insnbuf
, xtensa_format
, int, xtensa_opcode
, int, uint32
,
553 const char *, unsigned int));
554 static uint32 xtensa_insnbuf_get_operand
555 PARAMS ((xtensa_insnbuf
, xtensa_format
, int, xtensa_opcode
, int));
557 /* Various Other Internal Functions. */
559 static bfd_boolean is_unique_insn_expansion
560 PARAMS ((TransitionRule
*));
561 static int xg_get_build_instr_size
562 PARAMS ((BuildInstr
*));
563 static bfd_boolean xg_is_narrow_insn
565 static bfd_boolean xg_is_single_relaxable_insn
567 static int xg_get_max_insn_widen_size
568 PARAMS ((xtensa_opcode
));
569 static int xg_get_max_insn_widen_literal_size
570 PARAMS ((xtensa_opcode
));
571 static bfd_boolean xg_is_relaxable_insn
572 PARAMS ((TInsn
*, int));
573 static symbolS
*get_special_literal_symbol
575 static symbolS
*get_special_label_symbol
577 static bfd_boolean xg_build_to_insn
578 PARAMS ((TInsn
*, TInsn
*, BuildInstr
*));
579 static bfd_boolean xg_build_to_stack
580 PARAMS ((IStack
*, TInsn
*, BuildInstr
*));
581 static bfd_boolean xg_expand_to_stack
582 PARAMS ((IStack
*, TInsn
*, int));
583 static bfd_boolean xg_expand_narrow
584 PARAMS ((TInsn
*, TInsn
*));
585 static bfd_boolean xg_immeds_fit
586 PARAMS ((const TInsn
*));
587 static bfd_boolean xg_symbolic_immeds_fit
588 PARAMS ((const TInsn
*, segT
, fragS
*, offsetT
, long));
589 static bfd_boolean xg_check_operand
590 PARAMS ((int32
, xtensa_opcode
, int));
591 static int xg_assembly_relax
592 PARAMS ((IStack
*, TInsn
*, segT
, fragS
*, offsetT
, int, long));
593 static void xg_force_frag_space
595 static void xg_finish_frag
596 PARAMS ((char *, enum xtensa_relax_statesE
, enum xtensa_relax_statesE
,
598 static bfd_boolean is_branch_jmp_to_next
599 PARAMS ((TInsn
*, fragS
*));
600 static void xg_add_branch_and_loop_targets
602 static bfd_boolean xg_instruction_matches_options
603 PARAMS ((TInsn
*, const ReqOption
*));
604 static bfd_boolean xg_instruction_matches_or_options
605 PARAMS ((TInsn
*, const ReqOrOptionList
*));
606 static bfd_boolean xg_instruction_matches_option_term
607 PARAMS ((TInsn
*, const ReqOrOption
*));
608 static bfd_boolean xg_instruction_matches_rule
609 PARAMS ((TInsn
*, TransitionRule
*));
610 static TransitionRule
*xg_instruction_match
612 static int transition_rule_cmp
613 PARAMS ((const TransitionRule
*, const TransitionRule
*));
614 static bfd_boolean xg_build_token_insn
615 PARAMS ((BuildInstr
*, TInsn
*, TInsn
*));
616 static bfd_boolean xg_simplify_insn
617 PARAMS ((TInsn
*, TInsn
*));
618 static bfd_boolean xg_expand_assembly_insn
619 PARAMS ((IStack
*, TInsn
*));
620 static symbolS
*xg_assemble_literal
622 static bfd_boolean xg_valid_literal_expression
623 PARAMS ((const expressionS
*));
624 static void xg_assemble_literal_space
626 static symbolS
*xtensa_create_literal_symbol
627 PARAMS ((segT
, fragS
*));
628 static void xtensa_add_literal_sym
629 PARAMS ((symbolS
*));
630 static void xtensa_add_insn_label
631 PARAMS ((symbolS
*));
632 static void xtensa_clear_insn_labels
634 static bfd_boolean get_is_linkonce_section
635 PARAMS ((bfd
*, segT
));
636 static bfd_boolean xg_emit_insn_to_buf
637 PARAMS ((TInsn
*, xtensa_format
, char *, fragS
*, offsetT
, bfd_boolean
));
638 static bfd_boolean xg_add_opcode_fix
639 PARAMS ((TInsn
*, int, xtensa_format
, int, expressionS
*, fragS
*, offsetT
));
640 static void xg_resolve_literals
641 PARAMS ((TInsn
*, symbolS
*));
642 static void xg_resolve_labels
643 PARAMS ((TInsn
*, symbolS
*));
644 static bfd_boolean is_register_writer
645 PARAMS ((const TInsn
*, const char *, int));
646 static bfd_boolean is_bad_loopend_opcode
647 PARAMS ((const TInsn
*));
648 static bfd_boolean is_unaligned_label
649 PARAMS ((symbolS
*));
650 static fragS
*next_non_empty_frag
651 PARAMS ((const fragS
*));
652 static bfd_boolean next_frag_opcode_is_loop
653 PARAMS ((const fragS
*, xtensa_opcode
*));
654 static int next_frag_format_size
655 PARAMS ((const fragS
*));
656 static int frag_format_size
657 PARAMS ((const fragS
*));
658 static void update_next_frag_state
659 PARAMS ((fragS
*, bfd_boolean
));
660 static bfd_boolean next_frag_is_branch_target
661 PARAMS ((const fragS
*));
662 static bfd_boolean next_frag_is_loop_target
663 PARAMS ((const fragS
*));
664 static addressT next_frag_pre_opcode_bytes
665 PARAMS ((const fragS
*));
666 static bfd_boolean is_next_frag_target
667 PARAMS ((const fragS
*, const fragS
*));
668 static void xtensa_mark_literal_pool_location
670 static void xtensa_move_labels
671 PARAMS ((fragS
*, valueT
, bfd_boolean
));
672 static void assemble_nop
673 PARAMS ((size_t, char *));
674 static void build_nop
675 PARAMS ((TInsn
*, int));
676 static addressT get_expanded_loop_offset
677 PARAMS ((xtensa_opcode
));
678 static fragS
*get_literal_pool_location
680 static void set_literal_pool_location
681 PARAMS ((segT
, fragS
*));
682 static void xtensa_set_frag_assembly_state
684 static bfd_boolean relaxable_section
685 PARAMS ((asection
*));
686 static void xtensa_find_unmarked_state_frags
688 static void xtensa_find_unaligned_branch_targets
689 PARAMS ((bfd
*, asection
*, PTR
));
690 static void xtensa_find_unaligned_loops
691 PARAMS ((bfd
*, asection
*, PTR
));
692 static void xg_apply_tentative_value
693 PARAMS ((fixS
*, valueT
));
694 static void finish_vinsn
695 PARAMS ((vliw_insn
*));
696 static bfd_boolean find_vinsn_conflicts
697 PARAMS ((vliw_insn
*));
698 static char check_t1_t2_reads_and_writes
699 PARAMS ((TInsn
*, TInsn
*));
700 static bfd_boolean resources_conflict
701 PARAMS ((vliw_insn
*));
702 static xtensa_format xg_find_narrowest_format
703 PARAMS ((vliw_insn
*));
704 static int relaxation_requirements
705 PARAMS ((vliw_insn
*));
706 static void bundle_single_op
708 static bfd_boolean emit_single_op
710 static void xg_assemble_vliw_tokens
711 PARAMS ((vliw_insn
*));
713 /* Helpers for xtensa_end(). */
715 static void xtensa_cleanup_align_frags
717 static void xtensa_fix_target_frags
719 static bfd_boolean frag_can_negate_branch
721 static void xtensa_mark_narrow_branches
723 static bfd_boolean is_narrow_branch_guaranteed_in_range
724 PARAMS ((fragS
*, TInsn
*));
725 static void xtensa_mark_zcl_first_insns
727 static void xtensa_fix_a0_b_retw_frags
729 static bfd_boolean next_instrs_are_b_retw
731 static void xtensa_fix_b_j_loop_end_frags
733 static bfd_boolean next_instr_is_loop_end
735 static void xtensa_fix_close_loop_end_frags
737 static size_t min_bytes_to_other_loop_end
738 PARAMS ((fragS
*, fragS
*, offsetT
, size_t));
739 static size_t unrelaxed_frag_min_size
741 static size_t unrelaxed_frag_max_size
743 static void xtensa_fix_short_loop_frags
745 static size_t count_insns_to_loop_end
746 PARAMS ((fragS
*, bfd_boolean
, size_t));
747 static size_t unrelaxed_frag_min_insn_count
749 static bfd_boolean branch_before_loop_end
751 static bfd_boolean unrelaxed_frag_has_b_j
753 static void xtensa_sanity_check
755 static bfd_boolean is_empty_loop
756 PARAMS ((const TInsn
*, fragS
*));
757 static bfd_boolean is_local_forward_loop
758 PARAMS ((const TInsn
*, fragS
*));
760 /* Alignment Functions. */
762 static size_t get_text_align_power
764 static addressT get_text_align_max_fill_size
765 PARAMS ((int, bfd_boolean
, bfd_boolean
));
766 static addressT get_text_align_fill_size
767 PARAMS ((addressT
, int, int, bfd_boolean
, bfd_boolean
));
768 static size_t get_text_align_nop_count
769 PARAMS ((size_t, bfd_boolean
));
770 static size_t get_text_align_nth_nop_size
771 PARAMS ((size_t, size_t, bfd_boolean
));
772 static addressT get_noop_aligned_address
773 PARAMS ((fragS
*, addressT
));
774 static addressT get_aligned_diff
775 PARAMS ((fragS
*, addressT
, addressT
*));
777 /* Helpers for xtensa_relax_frag(). */
779 static long relax_frag_loop_align
780 PARAMS ((fragS
*, long));
781 static long relax_frag_add_nop
783 static long relax_frag_for_align
784 PARAMS ((fragS
*, long));
785 static long future_alignment_required
786 PARAMS ((fragS
*, long));
787 static addressT find_address_of_next_align_frag
788 PARAMS ((fragS
**, int *, int *, int *, bfd_boolean
*));
789 static long bytes_to_stretch
790 PARAMS ((fragS
*, int, int, int, int));
791 static long relax_frag_immed
792 PARAMS ((segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
));
794 /* Helpers for md_convert_frag(). */
796 static void convert_frag_align_next_opcode
798 static void convert_frag_narrow
799 PARAMS ((segT
, fragS
*, xtensa_format
, int));
800 static void convert_frag_fill_nop
802 static void convert_frag_immed
803 PARAMS ((segT
, fragS
*, int, xtensa_format
, int));
804 static fixS
*fix_new_exp_in_seg
805 PARAMS ((segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
806 bfd_reloc_code_real_type
));
807 static void convert_frag_immed_finish_loop
808 PARAMS ((segT
, fragS
*, TInsn
*));
809 static offsetT get_expression_value
810 PARAMS ((segT
, expressionS
*));
812 /* Flags for the Last Instruction in Each Subsegment. */
814 static unsigned get_last_insn_flags
815 PARAMS ((segT
, subsegT
));
816 static void set_last_insn_flags
817 PARAMS ((segT
, subsegT
, unsigned, bfd_boolean
));
819 /* Segment list functions. */
821 static void xtensa_remove_section
823 static void xtensa_insert_section
824 PARAMS ((segT
, segT
));
825 static void xtensa_move_seg_list_to_beginning
826 PARAMS ((seg_list
*));
827 static subseg_map
*get_subseg_info
828 PARAMS ((segT
, subsegT
));
829 static void xtensa_move_literals
831 static void mark_literal_frags
832 PARAMS ((seg_list
*));
833 static void xtensa_reorder_seg_list
834 PARAMS ((seg_list
*, segT
));
835 static void xtensa_reorder_segments
837 static segT get_last_sec
839 static void xtensa_switch_to_literal_fragment
840 PARAMS ((emit_state
*));
841 static void xtensa_switch_to_non_abs_literal_fragment
842 PARAMS ((emit_state
*));
843 static void xtensa_switch_section_emit_state
844 PARAMS ((emit_state
*, segT
, subsegT
));
845 static void xtensa_restore_emit_state
846 PARAMS ((emit_state
*));
847 static void cache_literal_section
848 PARAMS ((seg_list
*, const char *, segT
*, bfd_boolean
));
849 static segT retrieve_literal_seg
850 PARAMS ((seg_list
*, const char *, bfd_boolean
));
851 static segT seg_present
852 PARAMS ((const char *));
853 static void add_seg_list
854 PARAMS ((seg_list
*, segT
));
856 /* Property flags on fragments and conversion to object file flags. */
858 static bfd_boolean get_frag_is_literal
859 PARAMS ((const fragS
*));
860 static bfd_boolean get_frag_is_insn
861 PARAMS ((const fragS
*));
862 static bfd_boolean get_frag_is_no_transform
864 static void set_frag_is_specific_opcode
865 PARAMS ((fragS
*, bfd_boolean
));
866 static void set_frag_is_no_transform
867 PARAMS ((fragS
*, bfd_boolean
));
868 static void xtensa_create_property_segments
869 PARAMS ((frag_predicate
, frag_predicate
, const char *, xt_section_type
));
870 static void xtensa_create_xproperty_segments
871 PARAMS ((frag_flags_fn
, const char *, xt_section_type
));
872 static segment_info_type
*retrieve_segment_info
874 static segT retrieve_xtensa_section
876 static bfd_boolean section_has_property
877 PARAMS ((segT
, frag_predicate
));
878 static bfd_boolean section_has_xproperty
879 PARAMS ((segT
, frag_flags_fn
));
880 static void add_xt_block_frags
881 PARAMS ((segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
));
882 static bfd_boolean xtensa_frag_flags_is_empty
883 PARAMS ((const frag_flags
*));
884 static void xtensa_frag_flags_init
885 PARAMS ((frag_flags
*));
886 static void get_frag_property_flags
887 PARAMS ((const fragS
*, frag_flags
*));
888 static bfd_vma frag_flags_to_number
889 PARAMS ((const frag_flags
*));
890 static bfd_boolean xtensa_frag_flags_combinable
891 PARAMS ((const frag_flags
*, const frag_flags
*));
892 static bfd_vma xt_block_aligned_size
893 PARAMS ((const xtensa_block_info
*));
894 static bfd_boolean xtensa_xt_block_combine
895 PARAMS ((xtensa_block_info
*, const xtensa_block_info
*));
896 static void add_xt_prop_frags
897 PARAMS ((segT
, segT
, xtensa_block_info
**, frag_flags_fn
));
899 /* Import from elf32-xtensa.c in BFD library. */
901 extern char *xtensa_get_property_section_name
902 PARAMS ((asection
*, const char *));
904 /* op_placement_info functions. */
906 static void init_op_placement_info_table
908 extern bfd_boolean opcode_fits_format_slot
909 PARAMS ((xtensa_opcode
, xtensa_format
, int));
910 static int xg_get_single_size
911 PARAMS ((xtensa_opcode
));
912 static xtensa_format xg_get_single_format
913 PARAMS ((xtensa_opcode
));
915 /* TInsn and IStack functions. */
917 static bfd_boolean tinsn_has_symbolic_operands
918 PARAMS ((const TInsn
*));
919 static bfd_boolean tinsn_has_invalid_symbolic_operands
920 PARAMS ((const TInsn
*));
921 static bfd_boolean tinsn_has_complex_operands
922 PARAMS ((const TInsn
*));
923 static bfd_boolean tinsn_to_insnbuf
924 PARAMS ((TInsn
*, xtensa_insnbuf
));
925 static bfd_boolean tinsn_to_slotbuf
926 PARAMS ((xtensa_format
, int, TInsn
*, xtensa_insnbuf
));
927 static bfd_boolean tinsn_check_arguments
928 PARAMS ((const TInsn
*));
929 static void tinsn_from_chars
930 PARAMS ((TInsn
*, char *, int));
931 static void tinsn_from_insnbuf
932 PARAMS ((TInsn
*, xtensa_insnbuf
, xtensa_format
, int));
933 static void tinsn_immed_from_frag
934 PARAMS ((TInsn
*, fragS
*, int));
935 static int get_num_stack_text_bytes
937 static int get_num_stack_literal_bytes
940 /* vliw_insn functions. */
942 static void xg_init_vinsn
943 PARAMS ((vliw_insn
*));
944 static void xg_clear_vinsn
945 PARAMS ((vliw_insn
*));
946 static bfd_boolean vinsn_has_specific_opcodes
947 PARAMS ((vliw_insn
*));
948 static void xg_free_vinsn
949 PARAMS ((vliw_insn
*));
950 static bfd_boolean vinsn_to_insnbuf
951 PARAMS ((vliw_insn
*, char *, fragS
*, bfd_boolean
));
952 static void vinsn_from_chars
953 PARAMS ((vliw_insn
*, char *));
955 /* Expression Utilities. */
957 bfd_boolean expr_is_const
958 PARAMS ((const expressionS
*));
959 offsetT get_expr_const
960 PARAMS ((const expressionS
*));
962 PARAMS ((expressionS
*, offsetT
));
963 bfd_boolean expr_is_register
964 PARAMS ((const expressionS
*));
965 offsetT get_expr_register
966 PARAMS ((const expressionS
*));
967 void set_expr_symbol_offset
968 PARAMS ((expressionS
*, symbolS
*, offsetT
));
969 static void set_expr_symbol_offset_diff
970 PARAMS ((expressionS
*, symbolS
*, symbolS
*, offsetT
));
971 bfd_boolean expr_is_equal
972 PARAMS ((expressionS
*, expressionS
*));
973 static void copy_expr
974 PARAMS ((expressionS
*, const expressionS
*));
976 #ifdef XTENSA_SECTION_RENAME
977 static void build_section_rename
978 PARAMS ((const char *));
979 static void add_section_rename
980 PARAMS ((char *, char *));
984 /* ISA imported from bfd. */
985 extern xtensa_isa xtensa_default_isa
;
987 extern int target_big_endian
;
989 static xtensa_opcode xtensa_addi_opcode
;
990 static xtensa_opcode xtensa_addmi_opcode
;
991 static xtensa_opcode xtensa_call0_opcode
;
992 static xtensa_opcode xtensa_call4_opcode
;
993 static xtensa_opcode xtensa_call8_opcode
;
994 static xtensa_opcode xtensa_call12_opcode
;
995 static xtensa_opcode xtensa_callx0_opcode
;
996 static xtensa_opcode xtensa_callx4_opcode
;
997 static xtensa_opcode xtensa_callx8_opcode
;
998 static xtensa_opcode xtensa_callx12_opcode
;
999 static xtensa_opcode xtensa_const16_opcode
;
1000 static xtensa_opcode xtensa_entry_opcode
;
1001 static xtensa_opcode xtensa_movi_opcode
;
1002 static xtensa_opcode xtensa_movi_n_opcode
;
1003 static xtensa_opcode xtensa_isync_opcode
;
1004 static xtensa_opcode xtensa_jx_opcode
;
1005 static xtensa_opcode xtensa_l32r_opcode
;
1006 static xtensa_opcode xtensa_loop_opcode
;
1007 static xtensa_opcode xtensa_loopnez_opcode
;
1008 static xtensa_opcode xtensa_loopgtz_opcode
;
1009 static xtensa_opcode xtensa_nop_opcode
;
1010 static xtensa_opcode xtensa_nop_n_opcode
;
1011 static xtensa_opcode xtensa_or_opcode
;
1012 static xtensa_opcode xtensa_ret_opcode
;
1013 static xtensa_opcode xtensa_ret_n_opcode
;
1014 static xtensa_opcode xtensa_retw_opcode
;
1015 static xtensa_opcode xtensa_retw_n_opcode
;
1016 static xtensa_opcode xtensa_rsr_lcount_opcode
;
1017 static xtensa_opcode xtensa_waiti_opcode
;
1020 /* Command-line Options. */
1022 bfd_boolean use_literal_section
= TRUE
;
1023 static bfd_boolean align_targets
= TRUE
;
1024 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
1025 static bfd_boolean has_a0_b_retw
= FALSE
;
1026 static bfd_boolean workaround_a0_b_retw
= FALSE
;
1027 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
1028 static bfd_boolean workaround_short_loop
= FALSE
;
1029 static bfd_boolean maybe_has_short_loop
= FALSE
;
1030 static bfd_boolean workaround_close_loop_end
= FALSE
;
1031 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
1033 /* When workaround_short_loops is TRUE, all loops with early exits must
1034 have at least 3 instructions. workaround_all_short_loops is a modifier
1035 to the workaround_short_loop flag. In addition to the
1036 workaround_short_loop actions, all straightline loopgtz and loopnez
1037 must have at least 3 instructions. */
1039 static bfd_boolean workaround_all_short_loops
= FALSE
;
1043 option_density
= OPTION_MD_BASE
,
1050 option_no_link_relax
,
1056 option_no_transform
,
1058 option_text_section_literals
,
1059 option_no_text_section_literals
,
1061 option_absolute_literals
,
1062 option_no_absolute_literals
,
1064 option_align_targets
,
1065 option_no_align_targets
,
1067 option_warn_unaligned_targets
,
1070 option_no_longcalls
,
1072 option_workaround_a0_b_retw
,
1073 option_no_workaround_a0_b_retw
,
1075 option_workaround_b_j_loop_end
,
1076 option_no_workaround_b_j_loop_end
,
1078 option_workaround_short_loop
,
1079 option_no_workaround_short_loop
,
1081 option_workaround_all_short_loops
,
1082 option_no_workaround_all_short_loops
,
1084 option_workaround_close_loop_end
,
1085 option_no_workaround_close_loop_end
,
1087 option_no_workarounds
,
1089 #ifdef XTENSA_SECTION_RENAME
1090 option_rename_section_name
,
1094 option_prefer_const16
,
1096 option_target_hardware
1099 const char *md_shortopts
= "";
1101 struct option md_longopts
[] =
1103 { "density", no_argument
, NULL
, option_density
},
1104 { "no-density", no_argument
, NULL
, option_no_density
},
1106 /* Both "relax" and "generics" are deprecated and treated as equivalent
1107 to the "transform" option. */
1108 { "relax", no_argument
, NULL
, option_relax
},
1109 { "no-relax", no_argument
, NULL
, option_no_relax
},
1110 { "generics", no_argument
, NULL
, option_generics
},
1111 { "no-generics", no_argument
, NULL
, option_no_generics
},
1113 { "transform", no_argument
, NULL
, option_transform
},
1114 { "no-transform", no_argument
, NULL
, option_no_transform
},
1115 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
1116 { "no-text-section-literals", no_argument
, NULL
,
1117 option_no_text_section_literals
},
1118 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
1119 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
1120 /* This option was changed from -align-target to -target-align
1121 because it conflicted with the "-al" option. */
1122 { "target-align", no_argument
, NULL
, option_align_targets
},
1123 { "no-target-align", no_argument
, NULL
,
1124 option_no_align_targets
},
1125 { "warn-unaligned-targets", no_argument
, NULL
, option_warn_unaligned_targets
},
1126 { "longcalls", no_argument
, NULL
, option_longcalls
},
1127 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
1129 { "no-workaround-a0-b-retw", no_argument
, NULL
,
1130 option_no_workaround_a0_b_retw
},
1131 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
1133 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
1134 option_no_workaround_b_j_loop_end
},
1135 { "workaround-b-j-loop-end", no_argument
, NULL
,
1136 option_workaround_b_j_loop_end
},
1138 { "no-workaround-short-loops", no_argument
, NULL
,
1139 option_no_workaround_short_loop
},
1140 { "workaround-short-loops", no_argument
, NULL
, option_workaround_short_loop
},
1142 { "no-workaround-all-short-loops", no_argument
, NULL
,
1143 option_no_workaround_all_short_loops
},
1144 { "workaround-all-short-loop", no_argument
, NULL
,
1145 option_workaround_all_short_loops
},
1147 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
1148 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
1150 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
1152 { "no-workaround-close-loop-end", no_argument
, NULL
,
1153 option_no_workaround_close_loop_end
},
1154 { "workaround-close-loop-end", no_argument
, NULL
,
1155 option_workaround_close_loop_end
},
1157 #ifdef XTENSA_SECTION_RENAME
1158 { "rename-section", required_argument
, NULL
,
1159 option_rename_section_name
},
1160 #endif /* XTENSA_SECTION_RENAME */
1162 { "link-relax", no_argument
, NULL
, option_link_relax
},
1163 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
1165 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
1167 { NULL
, no_argument
, NULL
, 0 }
1170 size_t md_longopts_size
= sizeof md_longopts
;
1174 md_parse_option (c
, arg
)
1180 case option_density
:
1181 as_warn (_("--density option is ignored"));
1183 case option_no_density
:
1184 as_warn (_("--no-density option is ignored"));
1186 case option_link_relax
:
1189 case option_no_link_relax
:
1192 case option_generics
:
1193 as_warn (_("--generics is deprecated; use --transform instead"));
1194 return md_parse_option (option_transform
, arg
);
1195 case option_no_generics
:
1196 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
1197 return md_parse_option (option_no_transform
, arg
);
1199 as_warn (_("--relax is deprecated; use --transform instead"));
1200 return md_parse_option (option_transform
, arg
);
1201 case option_no_relax
:
1202 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
1203 return md_parse_option (option_no_transform
, arg
);
1204 case option_longcalls
:
1205 directive_state
[directive_longcalls
] = TRUE
;
1207 case option_no_longcalls
:
1208 directive_state
[directive_longcalls
] = FALSE
;
1210 case option_text_section_literals
:
1211 use_literal_section
= FALSE
;
1213 case option_no_text_section_literals
:
1214 use_literal_section
= TRUE
;
1216 case option_absolute_literals
:
1217 if (!absolute_literals_supported
)
1219 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
1222 directive_state
[directive_absolute_literals
] = TRUE
;
1224 case option_no_absolute_literals
:
1225 directive_state
[directive_absolute_literals
] = FALSE
;
1228 case option_workaround_a0_b_retw
:
1229 workaround_a0_b_retw
= TRUE
;
1231 case option_no_workaround_a0_b_retw
:
1232 workaround_a0_b_retw
= FALSE
;
1234 case option_workaround_b_j_loop_end
:
1235 workaround_b_j_loop_end
= TRUE
;
1237 case option_no_workaround_b_j_loop_end
:
1238 workaround_b_j_loop_end
= FALSE
;
1241 case option_workaround_short_loop
:
1242 workaround_short_loop
= TRUE
;
1244 case option_no_workaround_short_loop
:
1245 workaround_short_loop
= FALSE
;
1248 case option_workaround_all_short_loops
:
1249 workaround_all_short_loops
= TRUE
;
1251 case option_no_workaround_all_short_loops
:
1252 workaround_all_short_loops
= FALSE
;
1255 case option_workaround_close_loop_end
:
1256 workaround_close_loop_end
= TRUE
;
1258 case option_no_workaround_close_loop_end
:
1259 workaround_close_loop_end
= FALSE
;
1262 case option_no_workarounds
:
1263 workaround_a0_b_retw
= FALSE
;
1264 workaround_b_j_loop_end
= FALSE
;
1265 workaround_short_loop
= FALSE
;
1266 workaround_all_short_loops
= FALSE
;
1267 workaround_close_loop_end
= FALSE
;
1270 case option_align_targets
:
1271 align_targets
= TRUE
;
1273 case option_no_align_targets
:
1274 align_targets
= FALSE
;
1277 case option_warn_unaligned_targets
:
1278 warn_unaligned_branch_targets
= TRUE
;
1281 #ifdef XTENSA_SECTION_RENAME
1282 case option_rename_section_name
:
1283 build_section_rename (arg
);
1285 #endif /* XTENSA_SECTION_RENAME */
1288 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1289 should be emitted or not. FIXME: Not implemented. */
1292 case option_prefer_l32r
:
1294 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
1298 case option_prefer_const16
:
1300 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
1304 case option_target_hardware
:
1306 int earliest
, latest
= 0;
1307 if (*arg
== 0 || *arg
== '-')
1308 as_fatal (_("invalid target hardware version"));
1310 earliest
= strtol (arg
, &arg
, 0);
1314 else if (*arg
== '-')
1317 as_fatal (_("invalid target hardware version"));
1318 latest
= strtol (arg
, &arg
, 0);
1321 as_fatal (_("invalid target hardware version"));
1323 xtensa_setup_hw_workarounds (earliest
, latest
);
1327 case option_transform
:
1328 /* This option has no affect other than to use the defaults,
1329 which are already set. */
1332 case option_no_transform
:
1333 /* This option turns off all transformations of any kind.
1334 However, because we want to preserve the state of other
1335 directives, we only change its own field. Thus, before
1336 you perform any transformation, always check if transform
1337 is available. If you use the functions we provide for this
1338 purpose, you will be ok. */
1339 directive_state
[directive_transform
] = FALSE
;
1349 md_show_usage (stream
)
1354 --[no-]text-section-literals\n\
1355 [Do not] put literals in the text section\n\
1356 --[no-]absolute-literals\n\
1357 [Do not] default to use non-PC-relative literals\n\
1358 --[no-]target-align [Do not] try to align branch targets\n\
1359 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1360 --[no-]transform [Do not] transform instructions\n"
1361 #ifdef XTENSA_SECTION_RENAME
1362 "--rename-section old=new(:old1=new1)*\n\
1363 Rename section 'old' to 'new'\n"
1364 #endif /* XTENSA_SECTION_RENAME */
1370 xtensa_setup_hw_workarounds (earliest
, latest
)
1374 if (earliest
> latest
)
1375 as_fatal (_("illegal range of target hardware versions"));
1377 /* Enable all workarounds for pre-T1050.0 hardware. */
1378 if (earliest
< 105000 || latest
< 105000)
1380 workaround_a0_b_retw
|= TRUE
;
1381 workaround_b_j_loop_end
|= TRUE
;
1382 workaround_short_loop
|= TRUE
;
1383 workaround_close_loop_end
|= TRUE
;
1384 workaround_all_short_loops
|= TRUE
;
1389 /* Directive data and functions. */
1391 typedef struct state_stackS_struct
1393 directiveE directive
;
1394 bfd_boolean negated
;
1395 bfd_boolean old_state
;
1399 struct state_stackS_struct
*prev
;
1402 state_stackS
*directive_state_stack
;
1404 const pseudo_typeS md_pseudo_table
[] =
1406 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1407 { "literal_position", xtensa_literal_position
, 0 },
1408 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1409 { "long", xtensa_elf_cons
, 4 },
1410 { "word", xtensa_elf_cons
, 4 },
1411 { "short", xtensa_elf_cons
, 2 },
1412 { "begin", xtensa_begin_directive
, 0 },
1413 { "end", xtensa_end_directive
, 0 },
1414 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1415 { "literal", xtensa_literal_pseudo
, 0 },
1416 { "frequency", xtensa_frequency_pseudo
, 0 },
1424 /* After md_end, you should be checking frag by frag, rather
1425 than state directives. */
1426 assert (!past_xtensa_end
);
1427 return directive_state
[directive_transform
];
1434 /* After md_end, you should be checking frag by frag, rather
1435 than state directives. */
1436 assert (!past_xtensa_end
);
1437 return directive_state
[directive_longcalls
] && use_transform ();
1444 /* After md_end, you should be checking frag by frag, rather
1445 than state directives. */
1446 assert (!past_xtensa_end
);
1447 return align_targets
&& use_transform ();
1452 directive_push (directive
, negated
, datum
)
1453 directiveE directive
;
1454 bfd_boolean negated
;
1459 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1461 as_where (&file
, &line
);
1463 stack
->directive
= directive
;
1464 stack
->negated
= negated
;
1465 stack
->old_state
= directive_state
[directive
];
1468 stack
->datum
= datum
;
1469 stack
->prev
= directive_state_stack
;
1470 directive_state_stack
= stack
;
1472 directive_state
[directive
] = !negated
;
1476 directive_pop (directive
, negated
, file
, line
, datum
)
1477 directiveE
*directive
;
1478 bfd_boolean
*negated
;
1483 state_stackS
*top
= directive_state_stack
;
1485 if (!directive_state_stack
)
1487 as_bad (_("unmatched end directive"));
1488 *directive
= directive_none
;
1492 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1493 *directive
= top
->directive
;
1494 *negated
= top
->negated
;
1497 *datum
= top
->datum
;
1498 directive_state_stack
= top
->prev
;
1504 directive_balance ()
1506 while (directive_state_stack
)
1508 directiveE directive
;
1509 bfd_boolean negated
;
1514 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1515 as_warn_where ((char *) file
, line
,
1516 _(".begin directive with no matching .end directive"));
1522 inside_directive (dir
)
1525 state_stackS
*top
= directive_state_stack
;
1527 while (top
&& top
->directive
!= dir
)
1530 return (top
!= NULL
);
1535 get_directive (directive
, negated
)
1536 directiveE
*directive
;
1537 bfd_boolean
*negated
;
1541 char *directive_string
;
1543 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1548 input_line_pointer
+= 3;
1551 len
= strspn (input_line_pointer
,
1552 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1554 /* This code is a hack to make .begin [no-][generics|relax] exactly
1555 equivalent to .begin [no-]transform. We should remove it when
1556 we stop accepting those options. */
1558 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1560 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1561 directive_string
= "transform";
1563 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1565 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1566 directive_string
= "transform";
1569 directive_string
= input_line_pointer
;
1571 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1573 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1575 input_line_pointer
+= len
;
1576 *directive
= (directiveE
) i
;
1577 if (*negated
&& !directive_info
[i
].can_be_negated
)
1578 as_bad (_("directive %s cannot be negated"),
1579 directive_info
[i
].name
);
1584 as_bad (_("unknown directive"));
1585 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1590 xtensa_begin_directive (ignore
)
1591 int ignore ATTRIBUTE_UNUSED
;
1593 directiveE directive
;
1594 bfd_boolean negated
;
1599 get_directive (&directive
, &negated
);
1600 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1602 discard_rest_of_line ();
1606 if (cur_vinsn
.inside_bundle
)
1607 as_bad (_("directives are not valid inside bundles"));
1611 case directive_literal
:
1612 if (!inside_directive (directive_literal
))
1614 /* Previous labels go with whatever follows this directive, not with
1615 the literal, so save them now. */
1616 saved_insn_labels
= insn_labels
;
1619 as_warn (_(".begin literal is deprecated; use .literal instead"));
1620 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1621 xtensa_switch_to_literal_fragment (state
);
1622 directive_push (directive_literal
, negated
, state
);
1625 case directive_literal_prefix
:
1626 /* Have to flush pending output because a movi relaxed to an l32r
1627 might produce a literal. */
1628 md_flush_pending_output ();
1629 /* Check to see if the current fragment is a literal
1630 fragment. If it is, then this operation is not allowed. */
1631 if (generating_literals
)
1633 as_bad (_("cannot set literal_prefix inside literal fragment"));
1637 /* Allocate the literal state for this section and push
1638 onto the directive stack. */
1639 ls
= xmalloc (sizeof (lit_state
));
1642 *ls
= default_lit_sections
;
1644 directive_push (directive_literal_prefix
, negated
, ls
);
1646 /* Parse the new prefix from the input_line_pointer. */
1648 len
= strspn (input_line_pointer
,
1649 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1650 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1652 /* Process the new prefix. */
1653 xtensa_literal_prefix (input_line_pointer
, len
);
1655 /* Skip the name in the input line. */
1656 input_line_pointer
+= len
;
1659 case directive_freeregs
:
1660 /* This information is currently unused, but we'll accept the statement
1661 and just discard the rest of the line. This won't check the syntax,
1662 but it will accept every correct freeregs directive. */
1663 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1664 directive_push (directive_freeregs
, negated
, 0);
1667 case directive_schedule
:
1668 md_flush_pending_output ();
1669 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1670 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1671 directive_push (directive_schedule
, negated
, 0);
1672 xtensa_set_frag_assembly_state (frag_now
);
1675 case directive_density
:
1676 as_warn (_(".begin [no-]density is ignored"));
1679 case directive_absolute_literals
:
1680 md_flush_pending_output ();
1681 if (!absolute_literals_supported
&& !negated
)
1683 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1686 xtensa_set_frag_assembly_state (frag_now
);
1687 directive_push (directive
, negated
, 0);
1691 md_flush_pending_output ();
1692 xtensa_set_frag_assembly_state (frag_now
);
1693 directive_push (directive
, negated
, 0);
1697 demand_empty_rest_of_line ();
1702 xtensa_end_directive (ignore
)
1703 int ignore ATTRIBUTE_UNUSED
;
1705 directiveE begin_directive
, end_directive
;
1706 bfd_boolean begin_negated
, end_negated
;
1710 emit_state
**state_ptr
;
1713 if (cur_vinsn
.inside_bundle
)
1714 as_bad (_("directives are not valid inside bundles"));
1716 get_directive (&end_directive
, &end_negated
);
1718 md_flush_pending_output ();
1720 switch (end_directive
)
1722 case (directiveE
) XTENSA_UNDEFINED
:
1723 discard_rest_of_line ();
1726 case directive_density
:
1727 as_warn (_(".end [no-]density is ignored"));
1728 demand_empty_rest_of_line ();
1731 case directive_absolute_literals
:
1732 if (!absolute_literals_supported
&& !end_negated
)
1734 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1735 demand_empty_rest_of_line ();
1744 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1745 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1746 (const void **) state_ptr
);
1748 if (begin_directive
!= directive_none
)
1750 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1752 as_bad (_("does not match begin %s%s at %s:%d"),
1753 begin_negated
? "no-" : "",
1754 directive_info
[begin_directive
].name
, file
, line
);
1758 switch (end_directive
)
1760 case directive_literal
:
1761 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1762 xtensa_restore_emit_state (state
);
1763 xtensa_set_frag_assembly_state (frag_now
);
1765 if (!inside_directive (directive_literal
))
1767 /* Restore the list of current labels. */
1768 xtensa_clear_insn_labels ();
1769 insn_labels
= saved_insn_labels
;
1773 case directive_literal_prefix
:
1774 /* Restore the default collection sections from saved state. */
1775 s
= (lit_state
*) state
;
1778 if (use_literal_section
)
1779 default_lit_sections
= *s
;
1781 /* free the state storage */
1785 case directive_schedule
:
1786 case directive_freeregs
:
1790 xtensa_set_frag_assembly_state (frag_now
);
1796 demand_empty_rest_of_line ();
1800 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1802 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1805 xtensa_dwarf2_directive_loc (x
)
1808 xtensa_loc_directive_seen
= TRUE
;
1809 dwarf2_directive_loc (x
);
1814 xtensa_dwarf2_emit_insn (size
, loc
)
1816 struct dwarf2_line_info
*loc
;
1818 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1820 xtensa_loc_directive_seen
= FALSE
;
1821 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1825 /* Place an aligned literal fragment at the current location. */
1828 xtensa_literal_position (ignore
)
1829 int ignore ATTRIBUTE_UNUSED
;
1831 md_flush_pending_output ();
1833 if (inside_directive (directive_literal
))
1834 as_warn (_(".literal_position inside literal directive; ignoring"));
1835 xtensa_mark_literal_pool_location ();
1837 demand_empty_rest_of_line ();
1838 xtensa_clear_insn_labels ();
1842 /* Support .literal label, expr, ... */
1845 xtensa_literal_pseudo (ignored
)
1846 int ignored ATTRIBUTE_UNUSED
;
1849 char *p
, *base_name
;
1853 if (inside_directive (directive_literal
))
1855 as_bad (_(".literal not allowed inside .begin literal region"));
1856 ignore_rest_of_line ();
1860 md_flush_pending_output ();
1862 /* Previous labels go with whatever follows this directive, not with
1863 the literal, so save them now. */
1864 saved_insn_labels
= insn_labels
;
1867 /* If we are using text-section literals, then this is the right value... */
1870 base_name
= input_line_pointer
;
1872 xtensa_switch_to_literal_fragment (&state
);
1874 /* ...but if we aren't using text-section-literals, then we
1875 need to put them in the section we just switched to. */
1876 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1879 /* All literals are aligned to four-byte boundaries. */
1880 frag_align (2, 0, 0);
1881 record_alignment (now_seg
, 2);
1883 c
= get_symbol_end ();
1884 /* Just after name is now '\0'. */
1885 p
= input_line_pointer
;
1889 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1891 as_bad (_("expected comma or colon after symbol name; "
1892 "rest of line ignored"));
1893 ignore_rest_of_line ();
1894 xtensa_restore_emit_state (&state
);
1902 input_line_pointer
++; /* skip ',' or ':' */
1904 xtensa_elf_cons (4);
1906 xtensa_restore_emit_state (&state
);
1908 /* Restore the list of current labels. */
1909 xtensa_clear_insn_labels ();
1910 insn_labels
= saved_insn_labels
;
1915 xtensa_literal_prefix (start
, len
)
1919 char *name
, *linkonce_suffix
;
1920 char *newname
, *newname4
;
1921 size_t linkonce_len
;
1923 /* Get a null-terminated copy of the name. */
1924 name
= xmalloc (len
+ 1);
1927 strncpy (name
, start
, len
);
1930 /* Allocate the sections (interesting note: the memory pointing to
1931 the name is actually used for the name by the new section). */
1933 newname
= xmalloc (len
+ strlen (".literal") + 1);
1934 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1936 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1937 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1938 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1940 strcpy (newname
, ".gnu.linkonce.literal");
1941 strcpy (newname4
, ".gnu.linkonce.lit4");
1943 strcat (newname
, linkonce_suffix
);
1944 strcat (newname4
, linkonce_suffix
);
1948 int suffix_pos
= len
;
1950 /* If the section name ends with ".text", then replace that suffix
1951 instead of appending an additional suffix. */
1952 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1955 strcpy (newname
, name
);
1956 strcpy (newname4
, name
);
1958 strcpy (newname
+ suffix_pos
, ".literal");
1959 strcpy (newname4
+ suffix_pos
, ".lit4");
1962 /* Note that retrieve_literal_seg does not create a segment if
1963 it already exists. */
1964 default_lit_sections
.lit_seg
= NULL
;
1965 default_lit_sections
.lit4_seg
= NULL
;
1967 /* Canonicalizing section names allows renaming literal
1968 sections to occur correctly. */
1969 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1970 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1976 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1979 xtensa_frequency_pseudo (ignored
)
1980 int ignored ATTRIBUTE_UNUSED
;
1982 float fall_through_f
, target_f
;
1983 subseg_map
*seginfo
;
1985 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1986 if (fall_through_f
< 0)
1988 as_bad (_("fall through frequency must be greater than 0"));
1989 ignore_rest_of_line ();
1993 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1996 as_bad (_("branch target frequency must be greater than 0"));
1997 ignore_rest_of_line ();
2001 seginfo
= get_subseg_info (now_seg
, now_subseg
);
2002 seginfo
->cur_target_freq
= target_f
;
2003 seginfo
->cur_total_freq
= target_f
+ fall_through_f
;
2005 demand_empty_rest_of_line ();
2009 /* Like normal .long/.short/.word, except support @plt, etc.
2010 Clobbers input_line_pointer, checks end-of-line. */
2013 xtensa_elf_cons (nbytes
)
2017 bfd_reloc_code_real_type reloc
;
2019 md_flush_pending_output ();
2021 if (cur_vinsn
.inside_bundle
)
2022 as_bad (_("directives are not valid inside bundles"));
2024 if (is_it_end_of_statement ())
2026 demand_empty_rest_of_line ();
2033 if (exp
.X_op
== O_symbol
2034 && *input_line_pointer
== '@'
2035 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
2038 reloc_howto_type
*reloc_howto
=
2039 bfd_reloc_type_lookup (stdoutput
, reloc
);
2041 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
2042 as_bad (_("unsupported relocation"));
2043 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2044 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2045 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2046 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
2047 as_bad (_("opcode-specific %s relocation used outside "
2048 "an instruction"), reloc_howto
->name
);
2049 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
2050 as_bad (_("%s relocations do not fit in %d bytes"),
2051 reloc_howto
->name
, nbytes
);
2054 char *p
= frag_more ((int) nbytes
);
2055 xtensa_set_frag_assembly_state (frag_now
);
2056 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
2057 nbytes
, &exp
, 0, reloc
);
2061 emit_expr (&exp
, (unsigned int) nbytes
);
2063 while (*input_line_pointer
++ == ',');
2065 input_line_pointer
--; /* Put terminator back into stream. */
2066 demand_empty_rest_of_line ();
2070 /* Parse @plt, etc. and return the desired relocation. */
2071 static bfd_reloc_code_real_type
2072 xtensa_elf_suffix (str_p
, exp_p
)
2080 bfd_reloc_code_real_type reloc
;
2088 struct map_bfd
*ptr
;
2090 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
2092 static struct map_bfd mapping
[] =
2094 MAP ("l", BFD_RELOC_LO16
),
2095 MAP ("h", BFD_RELOC_HI16
),
2096 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
2097 { (char *) 0, 0, BFD_RELOC_UNUSED
}
2101 return BFD_RELOC_NONE
;
2103 for (ch
= *str
, str2
= ident
;
2104 (str2
< ident
+ sizeof (ident
) - 1
2105 && (ISALNUM (ch
) || ch
== '@'));
2108 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
2115 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
2116 if (ch
== ptr
->string
[0]
2117 && len
== ptr
->length
2118 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
2120 /* Now check for "identifier@suffix+constant". */
2121 if (*str
== '-' || *str
== '+')
2123 char *orig_line
= input_line_pointer
;
2124 expressionS new_exp
;
2126 input_line_pointer
= str
;
2127 expression (&new_exp
);
2128 if (new_exp
.X_op
== O_constant
)
2130 exp_p
->X_add_number
+= new_exp
.X_add_number
;
2131 str
= input_line_pointer
;
2134 if (&input_line_pointer
!= str_p
)
2135 input_line_pointer
= orig_line
;
2142 return BFD_RELOC_UNUSED
;
2146 /* Parsing and Idiom Translation. */
2149 expression_end (name
)
2173 #define ERROR_REG_NUM ((unsigned) -1)
2176 tc_get_register (prefix
)
2180 const char *next_expr
;
2181 const char *old_line_pointer
;
2184 old_line_pointer
= input_line_pointer
;
2186 if (*input_line_pointer
== '$')
2187 ++input_line_pointer
;
2189 /* Accept "sp" as a synonym for "a1". */
2190 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
2191 && expression_end (input_line_pointer
+ 2))
2193 input_line_pointer
+= 2;
2194 return 1; /* AR[1] */
2197 while (*input_line_pointer
++ == *prefix
++)
2199 --input_line_pointer
;
2204 as_bad (_("bad register name: %s"), old_line_pointer
);
2205 return ERROR_REG_NUM
;
2208 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
2210 as_bad (_("bad register number: %s"), input_line_pointer
);
2211 return ERROR_REG_NUM
;
2216 while (ISDIGIT ((int) *input_line_pointer
))
2217 reg
= reg
* 10 + *input_line_pointer
++ - '0';
2219 if (!(next_expr
= expression_end (input_line_pointer
)))
2221 as_bad (_("bad register name: %s"), old_line_pointer
);
2222 return ERROR_REG_NUM
;
2225 input_line_pointer
= (char *) next_expr
;
2232 expression_maybe_register (opc
, opnd
, tok
)
2237 xtensa_isa isa
= xtensa_default_isa
;
2239 /* Check if this is an immediate operand. */
2240 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
2242 bfd_reloc_code_real_type reloc
;
2243 segT t
= expression (tok
);
2244 if (t
== absolute_section
2245 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
2247 assert (tok
->X_op
== O_constant
);
2248 tok
->X_op
= O_symbol
;
2249 tok
->X_add_symbol
= &abs_symbol
;
2252 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
2253 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
2254 && (reloc
!= BFD_RELOC_NONE
))
2259 case BFD_RELOC_UNUSED
:
2260 as_bad (_("unsupported relocation"));
2263 case BFD_RELOC_XTENSA_PLT
:
2264 tok
->X_op
= O_pltrel
;
2267 case BFD_RELOC_LO16
:
2268 if (tok
->X_op
== O_constant
)
2269 tok
->X_add_number
&= 0xffff;
2274 case BFD_RELOC_HI16
:
2275 if (tok
->X_op
== O_constant
)
2276 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
2285 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
2286 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
2288 if (reg
!= ERROR_REG_NUM
) /* Already errored */
2291 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
2292 as_bad (_("register number out of range"));
2295 tok
->X_op
= O_register
;
2296 tok
->X_add_symbol
= 0;
2297 tok
->X_add_number
= reg
;
2302 /* Split up the arguments for an opcode or pseudo-op. */
2305 tokenize_arguments (args
, str
)
2309 char *old_input_line_pointer
;
2310 bfd_boolean saw_comma
= FALSE
;
2311 bfd_boolean saw_arg
= FALSE
;
2312 bfd_boolean saw_colon
= FALSE
;
2314 char *arg_end
, *arg
;
2317 /* Save and restore input_line_pointer around this function. */
2318 old_input_line_pointer
= input_line_pointer
;
2319 input_line_pointer
= str
;
2321 while (*input_line_pointer
)
2324 switch (*input_line_pointer
)
2331 input_line_pointer
++;
2332 if (saw_comma
|| saw_colon
|| !saw_arg
)
2338 input_line_pointer
++;
2339 if (saw_comma
|| saw_colon
|| !saw_arg
)
2345 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2348 arg_end
= input_line_pointer
+ 1;
2349 while (!expression_end (arg_end
))
2352 arg_len
= arg_end
- input_line_pointer
;
2353 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
2354 args
[num_args
] = arg
;
2358 strncpy (arg
, input_line_pointer
, arg_len
);
2359 arg
[arg_len
] = '\0';
2361 input_line_pointer
= arg_end
;
2371 if (saw_comma
|| saw_colon
)
2373 input_line_pointer
= old_input_line_pointer
;
2378 as_bad (_("extra comma"));
2380 as_bad (_("extra colon"));
2382 as_bad (_("missing argument"));
2384 as_bad (_("missing comma or colon"));
2385 input_line_pointer
= old_input_line_pointer
;
2390 /* Parse the arguments to an opcode. Return TRUE on error. */
2393 parse_arguments (insn
, num_args
, arg_strings
)
2398 expressionS
*tok
, *last_tok
;
2399 xtensa_opcode opcode
= insn
->opcode
;
2400 bfd_boolean had_error
= TRUE
;
2401 xtensa_isa isa
= xtensa_default_isa
;
2402 int n
, num_regs
= 0;
2403 int opcode_operand_count
;
2404 int opnd_cnt
, last_opnd_cnt
;
2405 unsigned int next_reg
= 0;
2406 char *old_input_line_pointer
;
2408 if (insn
->insn_type
== ITYPE_LITERAL
)
2409 opcode_operand_count
= 1;
2411 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2414 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2416 /* Save and restore input_line_pointer around this function. */
2417 old_input_line_pointer
= input_line_pointer
;
2423 /* Skip invisible operands. */
2424 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2430 for (n
= 0; n
< num_args
; n
++)
2432 input_line_pointer
= arg_strings
[n
];
2433 if (*input_line_pointer
== ':')
2435 xtensa_regfile opnd_rf
;
2436 input_line_pointer
++;
2439 assert (opnd_cnt
> 0);
2441 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2443 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2444 as_warn (_("incorrect register number, ignoring"));
2449 if (opnd_cnt
>= opcode_operand_count
)
2451 as_warn (_("too many arguments"));
2454 assert (opnd_cnt
< MAX_INSN_ARGS
);
2456 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2457 next_reg
= tok
->X_add_number
+ 1;
2459 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2461 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2463 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2464 /* minus 1 because we are seeing one right now */
2470 last_opnd_cnt
= opnd_cnt
;
2477 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2481 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2484 insn
->ntok
= tok
- insn
->tok
;
2488 input_line_pointer
= old_input_line_pointer
;
2494 get_invisible_operands (insn
)
2497 xtensa_isa isa
= xtensa_default_isa
;
2498 static xtensa_insnbuf slotbuf
= NULL
;
2500 xtensa_opcode opc
= insn
->opcode
;
2501 int slot
, opnd
, fmt_found
;
2505 slotbuf
= xtensa_insnbuf_alloc (isa
);
2507 /* Find format/slot where this can be encoded. */
2510 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2512 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2514 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2520 if (fmt_found
) break;
2525 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2529 /* First encode all the visible operands
2530 (to deal with shared field operands). */
2531 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2533 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2534 && (insn
->tok
[opnd
].X_op
== O_register
2535 || insn
->tok
[opnd
].X_op
== O_constant
))
2537 val
= insn
->tok
[opnd
].X_add_number
;
2538 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2539 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2543 /* Then pull out the values for the invisible ones. */
2544 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2546 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2548 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2549 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2550 insn
->tok
[opnd
].X_add_number
= val
;
2551 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2552 insn
->tok
[opnd
].X_op
= O_register
;
2554 insn
->tok
[opnd
].X_op
= O_constant
;
2563 xg_reverse_shift_count (cnt_argp
)
2566 char *cnt_arg
, *new_arg
;
2567 cnt_arg
= *cnt_argp
;
2569 /* replace the argument with "31-(argument)" */
2570 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2571 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2574 *cnt_argp
= new_arg
;
2578 /* If "arg" is a constant expression, return non-zero with the value
2582 xg_arg_is_constant (arg
, valp
)
2587 char *save_ptr
= input_line_pointer
;
2589 input_line_pointer
= arg
;
2591 input_line_pointer
= save_ptr
;
2593 if (exp
.X_op
== O_constant
)
2595 *valp
= exp
.X_add_number
;
2604 xg_replace_opname (popname
, newop
)
2609 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2610 strcpy (*popname
, newop
);
2615 xg_check_num_args (pnum_args
, expected_num
, opname
, arg_strings
)
2621 int num_args
= *pnum_args
;
2623 if (num_args
< expected_num
)
2625 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2626 num_args
, opname
, expected_num
);
2630 if (num_args
> expected_num
)
2632 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2633 num_args
, opname
, expected_num
);
2634 while (num_args
-- > expected_num
)
2636 free (arg_strings
[num_args
]);
2637 arg_strings
[num_args
] = 0;
2639 *pnum_args
= expected_num
;
2647 /* If the register is not specified as part of the opcode,
2648 then get it from the operand and move it to the opcode. */
2651 xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
)
2656 xtensa_isa isa
= xtensa_default_isa
;
2658 char *opname
, *new_opname
;
2659 const char *sr_name
;
2660 int is_user
, is_write
;
2661 bfd_boolean has_underbar
= FALSE
;
2666 has_underbar
= TRUE
;
2669 is_user
= (opname
[1] == 'u');
2670 is_write
= (opname
[0] == 'w');
2672 /* Opname == [rw]ur or [rwx]sr... */
2674 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2677 /* Check if the argument is a symbolic register name. */
2678 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2679 /* Handle WSR to "INTSET" as a special case. */
2680 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2681 && !strcasecmp (arg_strings
[1], "intset"))
2682 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2683 if (sr
== XTENSA_UNDEFINED
2684 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2686 /* Maybe it's a register number.... */
2688 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2690 as_bad (_("invalid register '%s' for '%s' instruction"),
2691 arg_strings
[1], opname
);
2694 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2695 if (sr
== XTENSA_UNDEFINED
)
2697 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2703 /* Remove the last argument, which is now part of the opcode. */
2704 free (arg_strings
[1]);
2708 /* Translate the opcode. */
2709 sr_name
= xtensa_sysreg_name (isa
, sr
);
2710 /* Another special case for "WSR.INTSET".... */
2711 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2713 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2714 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2717 *popname
= new_opname
;
2724 xtensa_translate_old_userreg_ops (popname
)
2727 xtensa_isa isa
= xtensa_default_isa
;
2729 char *opname
, *new_opname
;
2730 const char *sr_name
;
2731 bfd_boolean has_underbar
= FALSE
;
2734 if (opname
[0] == '_')
2736 has_underbar
= TRUE
;
2740 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2741 if (sr
!= XTENSA_UNDEFINED
)
2743 /* The new default name ("nnn") is different from the old default
2744 name ("URnnn"). The old default is handled below, and we don't
2745 want to recognize [RW]nnn, so do nothing if the name is the (new)
2747 static char namebuf
[10];
2748 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2749 if (strcmp (namebuf
, opname
+ 1) == 0)
2757 /* Only continue if the reg name is "URnnn". */
2758 if (opname
[1] != 'u' || opname
[2] != 'r')
2760 val
= strtoul (opname
+ 3, &end
, 10);
2764 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2765 if (sr
== XTENSA_UNDEFINED
)
2767 as_bad (_("invalid register number (%ld) for '%s'"),
2773 /* Translate the opcode. */
2774 sr_name
= xtensa_sysreg_name (isa
, sr
);
2775 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2776 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2777 opname
[0], sr_name
);
2779 *popname
= new_opname
;
2786 xtensa_translate_zero_immed (old_op
, new_op
, popname
, pnum_args
, arg_strings
)
2797 assert (opname
[0] != '_');
2799 if (strcmp (opname
, old_op
) != 0)
2802 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2804 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2806 xg_replace_opname (popname
, new_op
);
2807 free (arg_strings
[1]);
2808 arg_strings
[1] = arg_strings
[2];
2817 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2818 Returns non-zero if an error was found. */
2821 xg_translate_idioms (popname
, pnum_args
, arg_strings
)
2826 char *opname
= *popname
;
2827 bfd_boolean has_underbar
= FALSE
;
2829 if (cur_vinsn
.inside_bundle
)
2834 has_underbar
= TRUE
;
2838 if (strcmp (opname
, "mov") == 0)
2840 if (use_transform () && !has_underbar
&& density_supported
)
2841 xg_replace_opname (popname
, "mov.n");
2844 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2846 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2847 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2848 strcpy (arg_strings
[2], arg_strings
[1]);
2854 if (strcmp (opname
, "bbsi.l") == 0)
2856 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2858 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2859 if (target_big_endian
)
2860 xg_reverse_shift_count (&arg_strings
[1]);
2864 if (strcmp (opname
, "bbci.l") == 0)
2866 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2868 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2869 if (target_big_endian
)
2870 xg_reverse_shift_count (&arg_strings
[1]);
2874 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2875 && strcmp (opname
, "nop") == 0)
2877 if (use_transform () && !has_underbar
&& density_supported
)
2878 xg_replace_opname (popname
, "nop.n");
2881 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2883 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2884 arg_strings
[0] = (char *) xmalloc (3);
2885 arg_strings
[1] = (char *) xmalloc (3);
2886 arg_strings
[2] = (char *) xmalloc (3);
2887 strcpy (arg_strings
[0], "a1");
2888 strcpy (arg_strings
[1], "a1");
2889 strcpy (arg_strings
[2], "a1");
2895 /* Recognize [RW]UR and [RWX]SR. */
2896 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2897 && (opname
[1] == 'u' || opname
[1] == 's'))
2898 || (opname
[0] == 'x' && opname
[1] == 's'))
2900 && opname
[3] == '\0')
2901 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2903 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2904 [RW]<name> if <name> is the non-default name of a user register. */
2905 if ((opname
[0] == 'r' || opname
[0] == 'w')
2906 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2907 return xtensa_translate_old_userreg_ops (popname
);
2909 /* Relax branches that don't allow comparisons against an immediate value
2910 of zero to the corresponding branches with implicit zero immediates. */
2911 if (!has_underbar
&& use_transform ())
2913 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2914 pnum_args
, arg_strings
))
2917 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2918 pnum_args
, arg_strings
))
2921 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2922 pnum_args
, arg_strings
))
2925 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2926 pnum_args
, arg_strings
))
2934 /* Functions for dealing with the Xtensa ISA. */
2936 /* Currently the assembler only allows us to use a single target per
2937 fragment. Because of this, only one operand for a given
2938 instruction may be symbolic. If there is a PC-relative operand,
2939 the last one is chosen. Otherwise, the result is the number of the
2940 last immediate operand, and if there are none of those, we fail and
2944 get_relaxable_immed (opcode
)
2945 xtensa_opcode opcode
;
2947 int last_immed
= -1;
2950 if (opcode
== XTENSA_UNDEFINED
)
2953 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2954 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2956 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2958 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2960 if (last_immed
== -1
2961 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2968 static xtensa_opcode
2969 get_opcode_from_buf (buf
, slot
)
2973 static xtensa_insnbuf insnbuf
= NULL
;
2974 static xtensa_insnbuf slotbuf
= NULL
;
2975 xtensa_isa isa
= xtensa_default_isa
;
2980 insnbuf
= xtensa_insnbuf_alloc (isa
);
2981 slotbuf
= xtensa_insnbuf_alloc (isa
);
2984 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2985 fmt
= xtensa_format_decode (isa
, insnbuf
);
2986 if (fmt
== XTENSA_UNDEFINED
)
2987 return XTENSA_UNDEFINED
;
2989 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2990 return XTENSA_UNDEFINED
;
2992 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2993 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2997 #ifdef TENSILICA_DEBUG
2999 /* For debugging, print out the mapping of opcode numbers to opcodes. */
3002 xtensa_print_insn_table ()
3004 int num_opcodes
, num_operands
;
3005 xtensa_opcode opcode
;
3006 xtensa_isa isa
= xtensa_default_isa
;
3008 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
3009 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
3012 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
3013 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
3014 for (opn
= 0; opn
< num_operands
; opn
++)
3016 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
3018 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
3020 xtensa_regfile opnd_rf
=
3021 xtensa_operand_regfile (isa
, opcode
, opn
);
3022 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
3024 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
3025 fputs ("[lLr] ", stderr
);
3027 fputs ("i ", stderr
);
3029 fprintf (stderr
, "\n");
3035 print_vliw_insn (vbuf
)
3036 xtensa_insnbuf vbuf
;
3038 xtensa_isa isa
= xtensa_default_isa
;
3039 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
3040 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
3043 fprintf (stderr
, "format = %d\n", f
);
3045 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
3047 xtensa_opcode opcode
;
3051 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
3052 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
3053 opname
= xtensa_opcode_name (isa
, opcode
);
3055 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
3056 fprintf (stderr
, " operands = ");
3058 operands
< xtensa_opcode_num_operands (isa
, opcode
);
3062 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
3064 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
3065 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
3066 fprintf (stderr
, "%d ", val
);
3068 fprintf (stderr
, "\n");
3070 xtensa_insnbuf_free (isa
, sbuf
);
3073 #endif /* TENSILICA_DEBUG */
3077 is_direct_call_opcode (opcode
)
3078 xtensa_opcode opcode
;
3080 xtensa_isa isa
= xtensa_default_isa
;
3081 int n
, num_operands
;
3083 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
3086 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
3087 for (n
= 0; n
< num_operands
; n
++)
3089 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
3090 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
3097 /* Return TRUE if the opcode is an entry opcode. This is used because
3098 "entry" adds an implicit ".align 4" and also the entry instruction
3099 has an extra check for an operand value. */
3102 is_entry_opcode (opcode
)
3103 xtensa_opcode opcode
;
3105 if (opcode
== XTENSA_UNDEFINED
)
3108 return (opcode
== xtensa_entry_opcode
);
3112 /* Return TRUE if the opcode is a movi or movi.n opcode. This is
3113 so we can relax "movi aX, foo" in the front end. */
3116 is_movi_opcode (opcode
)
3117 xtensa_opcode opcode
;
3119 if (opcode
== XTENSA_UNDEFINED
)
3122 return (opcode
== xtensa_movi_opcode
)
3123 || (opcode
== xtensa_movi_n_opcode
);
3128 is_the_loop_opcode (opcode
)
3129 xtensa_opcode opcode
;
3131 if (opcode
== XTENSA_UNDEFINED
)
3134 return (opcode
== xtensa_loop_opcode
);
3139 is_jx_opcode (opcode
)
3140 xtensa_opcode opcode
;
3142 if (opcode
== XTENSA_UNDEFINED
)
3145 return (opcode
== xtensa_jx_opcode
);
3149 /* Return TRUE if the opcode is a retw or retw.n.
3150 Needed to add nops to avoid a hardware interlock issue. */
3153 is_windowed_return_opcode (opcode
)
3154 xtensa_opcode opcode
;
3156 if (opcode
== XTENSA_UNDEFINED
)
3159 return (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
);
3163 /* Convert from BFD relocation type code to slot and operand number.
3164 Returns non-zero on failure. */
3167 decode_reloc (reloc
, slot
, is_alt
)
3168 bfd_reloc_code_real_type reloc
;
3170 bfd_boolean
*is_alt
;
3172 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
3173 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
3175 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
3178 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
3179 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
3181 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
3191 /* Convert from slot number to BFD relocation type code for the
3192 standard PC-relative relocations. Return BFD_RELOC_NONE on
3195 static bfd_reloc_code_real_type
3199 if (slot
< 0 || slot
> 14)
3200 return BFD_RELOC_NONE
;
3202 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
3206 /* Convert from slot numbers to BFD relocation type code for the
3207 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
3209 static bfd_reloc_code_real_type
3210 encode_alt_reloc (slot
)
3213 if (slot
< 0 || slot
> 14)
3214 return BFD_RELOC_NONE
;
3216 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
3221 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, operand
, value
,
3223 xtensa_insnbuf slotbuf
;
3226 xtensa_opcode opcode
;
3232 uint32 valbuf
= value
;
3234 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3236 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
3238 as_bad_where ((char *) file
, line
,
3239 _("operand %u is out of range for '%s'"), value
,
3240 xtensa_opcode_name (xtensa_default_isa
, opcode
));
3242 as_bad_where ((char *) file
, line
,
3243 _("operand %u is invalid for '%s'"), value
,
3244 xtensa_opcode_name (xtensa_default_isa
, opcode
));
3248 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
3254 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
, opcode
, opnum
)
3255 xtensa_insnbuf slotbuf
;
3258 xtensa_opcode opcode
;
3262 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
3263 fmt
, slot
, slotbuf
, &val
);
3264 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
3269 /* Various Other Internal Functions. */
3272 is_unique_insn_expansion (r
)
3275 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3277 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3284 xg_get_build_instr_size (insn
)
3287 assert (insn
->typ
== INSTR_INSTR
);
3288 return xg_get_single_size (insn
->opcode
);
3293 xg_is_narrow_insn (insn
)
3296 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3299 assert (insn
->insn_type
== ITYPE_INSN
);
3300 assert (insn
->opcode
< table
->num_opcodes
);
3302 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3304 TransitionRule
*rule
= l
->rule
;
3306 if (xg_instruction_matches_rule (insn
, rule
)
3307 && is_unique_insn_expansion (rule
))
3309 /* It only generates one instruction... */
3310 assert (insn
->insn_type
== ITYPE_INSN
);
3311 /* ...and it is a larger instruction. */
3312 if (xg_get_single_size (insn
->opcode
)
3313 < xg_get_build_instr_size (rule
->to_instr
))
3321 return (num_match
== 1);
3326 xg_is_single_relaxable_insn (insn
)
3329 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3332 assert (insn
->insn_type
== ITYPE_INSN
);
3333 assert (insn
->opcode
< table
->num_opcodes
);
3335 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3337 TransitionRule
*rule
= l
->rule
;
3339 if (xg_instruction_matches_rule (insn
, rule
)
3340 && is_unique_insn_expansion (rule
))
3342 /* It only generates one instruction... */
3343 assert (insn
->insn_type
== ITYPE_INSN
);
3344 /* ... and it is a larger instruction. */
3345 if (xg_get_single_size (insn
->opcode
)
3346 <= xg_get_build_instr_size (rule
->to_instr
))
3354 return (num_match
== 1);
3358 /* Return the maximum number of bytes this opcode can expand to. */
3361 xg_get_max_insn_widen_size (opcode
)
3362 xtensa_opcode opcode
;
3364 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3366 int max_size
= xg_get_single_size (opcode
);
3368 assert (opcode
< table
->num_opcodes
);
3370 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3372 TransitionRule
*rule
= l
->rule
;
3373 BuildInstr
*build_list
;
3378 build_list
= rule
->to_instr
;
3379 if (is_unique_insn_expansion (rule
))
3381 assert (build_list
->typ
== INSTR_INSTR
);
3382 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3385 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3387 switch (build_list
->typ
)
3390 this_size
+= xg_get_single_size (build_list
->opcode
);
3392 case INSTR_LITERAL_DEF
:
3393 case INSTR_LABEL_DEF
:
3398 if (this_size
> max_size
)
3399 max_size
= this_size
;
3405 /* Return the maximum number of literal bytes this opcode can generate. */
3408 xg_get_max_insn_widen_literal_size (opcode
)
3409 xtensa_opcode opcode
;
3411 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3415 assert (opcode
< table
->num_opcodes
);
3417 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3419 TransitionRule
*rule
= l
->rule
;
3420 BuildInstr
*build_list
;
3425 build_list
= rule
->to_instr
;
3426 if (is_unique_insn_expansion (rule
))
3428 assert (build_list
->typ
== INSTR_INSTR
);
3429 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3432 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3434 switch (build_list
->typ
)
3436 case INSTR_LITERAL_DEF
:
3437 /* Hard-coded 4-byte literal. */
3441 case INSTR_LABEL_DEF
:
3446 if (this_size
> max_size
)
3447 max_size
= this_size
;
3454 xg_is_relaxable_insn (insn
, lateral_steps
)
3458 int steps_taken
= 0;
3459 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3462 assert (insn
->insn_type
== ITYPE_INSN
);
3463 assert (insn
->opcode
< table
->num_opcodes
);
3465 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3467 TransitionRule
*rule
= l
->rule
;
3469 if (xg_instruction_matches_rule (insn
, rule
))
3471 if (steps_taken
== lateral_steps
)
3481 get_special_literal_symbol ()
3483 static symbolS
*sym
= NULL
;
3486 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3492 get_special_label_symbol ()
3494 static symbolS
*sym
= NULL
;
3497 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3502 /* Return TRUE on success. */
3505 xg_build_to_insn (targ
, insn
, bi
)
3513 memset (targ
, 0, sizeof (TInsn
));
3514 targ
->loc
= insn
->loc
;
3519 targ
->opcode
= bi
->opcode
;
3520 targ
->insn_type
= ITYPE_INSN
;
3521 targ
->is_specific_opcode
= FALSE
;
3523 for (; op
!= NULL
; op
= op
->next
)
3525 int op_num
= op
->op_num
;
3526 int op_data
= op
->op_data
;
3528 assert (op
->op_num
< MAX_INSN_ARGS
);
3530 if (targ
->ntok
<= op_num
)
3531 targ
->ntok
= op_num
+ 1;
3536 set_expr_const (&targ
->tok
[op_num
], op_data
);
3539 assert (op_data
< insn
->ntok
);
3540 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3543 sym
= get_special_literal_symbol ();
3544 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3547 sym
= get_special_label_symbol ();
3548 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3550 case OP_OPERAND_HI16U
:
3551 case OP_OPERAND_LOW16U
:
3552 assert (op_data
< insn
->ntok
);
3553 if (expr_is_const (&insn
->tok
[op_data
]))
3556 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3557 val
= xg_apply_userdef_op_fn (op
->typ
,
3560 targ
->tok
[op_num
].X_add_number
= val
;
3564 /* For const16 we can create relocations for these. */
3565 if (targ
->opcode
== XTENSA_UNDEFINED
3566 || (targ
->opcode
!= xtensa_const16_opcode
))
3568 assert (op_data
< insn
->ntok
);
3569 /* Need to build a O_lo16 or O_hi16. */
3570 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3571 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3573 if (op
->typ
== OP_OPERAND_HI16U
)
3574 targ
->tok
[op_num
].X_op
= O_hi16
;
3575 else if (op
->typ
== OP_OPERAND_LOW16U
)
3576 targ
->tok
[op_num
].X_op
= O_lo16
;
3583 /* currently handles:
3586 OP_OPERAND_F32MINUS */
3587 if (xg_has_userdef_op_fn (op
->typ
))
3589 assert (op_data
< insn
->ntok
);
3590 if (expr_is_const (&insn
->tok
[op_data
]))
3593 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3594 val
= xg_apply_userdef_op_fn (op
->typ
,
3597 targ
->tok
[op_num
].X_add_number
= val
;
3600 return FALSE
; /* We cannot use a relocation for this. */
3609 case INSTR_LITERAL_DEF
:
3611 targ
->opcode
= XTENSA_UNDEFINED
;
3612 targ
->insn_type
= ITYPE_LITERAL
;
3613 targ
->is_specific_opcode
= FALSE
;
3614 for (; op
!= NULL
; op
= op
->next
)
3616 int op_num
= op
->op_num
;
3617 int op_data
= op
->op_data
;
3618 assert (op
->op_num
< MAX_INSN_ARGS
);
3620 if (targ
->ntok
<= op_num
)
3621 targ
->ntok
= op_num
+ 1;
3626 assert (op_data
< insn
->ntok
);
3627 /* We can only pass resolvable literals through. */
3628 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3630 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3642 case INSTR_LABEL_DEF
:
3644 targ
->opcode
= XTENSA_UNDEFINED
;
3645 targ
->insn_type
= ITYPE_LABEL
;
3646 targ
->is_specific_opcode
= FALSE
;
3647 /* Literal with no ops is a label? */
3648 assert (op
== NULL
);
3659 /* Return TRUE on success. */
3662 xg_build_to_stack (istack
, insn
, bi
)
3667 for (; bi
!= NULL
; bi
= bi
->next
)
3669 TInsn
*next_insn
= istack_push_space (istack
);
3671 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3678 /* Return TRUE on valid expansion. */
3681 xg_expand_to_stack (istack
, insn
, lateral_steps
)
3686 int stack_size
= istack
->ninsn
;
3687 int steps_taken
= 0;
3688 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3691 assert (insn
->insn_type
== ITYPE_INSN
);
3692 assert (insn
->opcode
< table
->num_opcodes
);
3694 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3696 TransitionRule
*rule
= l
->rule
;
3698 if (xg_instruction_matches_rule (insn
, rule
))
3700 if (lateral_steps
== steps_taken
)
3704 /* This is it. Expand the rule to the stack. */
3705 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3708 /* Check to see if it fits. */
3709 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3711 TInsn
*insn
= &istack
->insn
[i
];
3713 if (insn
->insn_type
== ITYPE_INSN
3714 && !tinsn_has_symbolic_operands (insn
)
3715 && !xg_immeds_fit (insn
))
3717 istack
->ninsn
= stack_size
;
3731 xg_expand_narrow (targ
, insn
)
3735 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3738 assert (insn
->insn_type
== ITYPE_INSN
);
3739 assert (insn
->opcode
< table
->num_opcodes
);
3741 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3743 TransitionRule
*rule
= l
->rule
;
3744 if (xg_instruction_matches_rule (insn
, rule
)
3745 && is_unique_insn_expansion (rule
))
3747 /* Is it a larger instruction? */
3748 if (xg_get_single_size (insn
->opcode
)
3749 <= xg_get_build_instr_size (rule
->to_instr
))
3751 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3760 /* Assumes: All immeds are constants. Check that all constants fit
3761 into their immeds; return FALSE if not. */
3764 xg_immeds_fit (insn
)
3767 xtensa_isa isa
= xtensa_default_isa
;
3771 assert (insn
->insn_type
== ITYPE_INSN
);
3772 for (i
= 0; i
< n
; ++i
)
3774 const expressionS
*expr
= &insn
->tok
[i
];
3775 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3782 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3787 /* The symbol should have a fixup associated with it. */
3796 /* This should only be called after we have an initial
3797 estimate of the addresses. */
3800 xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3807 xtensa_isa isa
= xtensa_default_isa
;
3815 assert (insn
->insn_type
== ITYPE_INSN
);
3817 for (i
= 0; i
< n
; ++i
)
3819 const expressionS
*expr
= &insn
->tok
[i
];
3820 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3827 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3833 /* Check for the worst case. */
3834 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3839 /* We only allow symbols for pc-relative stuff.
3840 If pc_frag == 0, then we don't have frag locations yet. */
3844 /* If it is PC-relative and the symbol is not in the same
3845 segment as the PC.... */
3846 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0
3847 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3850 /* If it is a weak symbol, then assume it won't reach. This will
3851 only affect calls when longcalls are enabled, because if
3852 longcalls are disabled, then the call is marked as a specific
3854 if (S_IS_WEAK (expr
->X_add_symbol
))
3857 symbolP
= expr
->X_add_symbol
;
3858 sym_frag
= symbol_get_frag (symbolP
);
3859 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3860 pc
= pc_frag
->fr_address
+ pc_offset
;
3862 /* If frag has yet to be reached on this pass, assume it
3863 will move by STRETCH just as we did. If this is not so,
3864 it will be because some frag between grows, and that will
3865 force another pass. Beware zero-length frags. There
3866 should be a faster way to do this. */
3869 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3870 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3875 new_offset
= target
;
3876 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3877 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3882 /* The symbol should have a fixup associated with it. */
3891 /* This will check to see if the value can be converted into the
3892 operand type. It will return TRUE if it does not fit. */
3895 xg_check_operand (value
, opcode
, operand
)
3897 xtensa_opcode opcode
;
3900 uint32 valbuf
= value
;
3901 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3908 /* Relax the assembly instruction at least "min_steps".
3909 Return the number of steps taken. */
3912 xg_assembly_relax (istack
, insn
, pc_seg
, pc_frag
, pc_offset
, min_steps
,
3917 fragS
*pc_frag
; /* if pc_frag == 0, then no pc-relative */
3918 offsetT pc_offset
; /* offset in fragment */
3919 int min_steps
; /* minimum number of conversion steps */
3920 long stretch
; /* number of bytes stretched so far */
3922 int steps_taken
= 0;
3924 /* assert (has no symbolic operands)
3925 Some of its immeds don't fit.
3926 Try to build a relaxed version.
3927 This may go through a couple of stages
3928 of single instruction transformations before
3931 TInsn single_target
;
3933 int lateral_steps
= 0;
3934 int istack_size
= istack
->ninsn
;
3936 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3937 && steps_taken
>= min_steps
)
3939 istack_push (istack
, insn
);
3942 current_insn
= *insn
;
3944 /* Walk through all of the single instruction expansions. */
3945 while (xg_is_single_relaxable_insn (¤t_insn
))
3947 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3949 assert (!error_val
);
3951 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3955 if (steps_taken
>= min_steps
)
3957 istack_push (istack
, &single_target
);
3961 current_insn
= single_target
;
3964 /* Now check for a multi-instruction expansion. */
3965 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3967 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3970 if (steps_taken
>= min_steps
)
3972 istack_push (istack
, ¤t_insn
);
3977 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3979 if (steps_taken
>= min_steps
)
3983 istack
->ninsn
= istack_size
;
3986 /* It's not going to work -- use the original. */
3987 istack_push (istack
, insn
);
3993 xg_force_frag_space (size
)
3996 /* This may have the side effect of creating a new fragment for the
3997 space to go into. I just do not like the name of the "frag"
4004 xg_finish_frag (last_insn
, frag_state
, slot0_state
, max_growth
, is_insn
)
4006 enum xtensa_relax_statesE frag_state
;
4007 enum xtensa_relax_statesE slot0_state
;
4009 bfd_boolean is_insn
;
4011 /* Finish off this fragment so that it has at LEAST the desired
4012 max_growth. If it doesn't fit in this fragment, close this one
4013 and start a new one. In either case, return a pointer to the
4014 beginning of the growth area. */
4018 xg_force_frag_space (max_growth
);
4020 old_frag
= frag_now
;
4022 frag_now
->fr_opcode
= last_insn
;
4024 frag_now
->tc_frag_data
.is_insn
= TRUE
;
4026 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
4027 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
4029 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
4030 xtensa_set_frag_assembly_state (frag_now
);
4032 /* Just to make sure that we did not split it up. */
4033 assert (old_frag
->fr_next
== frag_now
);
4038 is_branch_jmp_to_next (insn
, fragP
)
4042 xtensa_isa isa
= xtensa_default_isa
;
4044 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4049 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
4050 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
4053 for (i
= 0; i
< num_ops
; i
++)
4055 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
4061 if (target_op
== -1)
4064 if (insn
->ntok
<= target_op
)
4067 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
4070 sym
= insn
->tok
[target_op
].X_add_symbol
;
4074 if (insn
->tok
[target_op
].X_add_number
!= 0)
4077 target_frag
= symbol_get_frag (sym
);
4078 if (target_frag
== NULL
)
4081 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
4082 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
4090 xg_add_branch_and_loop_targets (insn
)
4093 xtensa_isa isa
= xtensa_default_isa
;
4094 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4096 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
4099 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
4100 && insn
->tok
[i
].X_op
== O_symbol
)
4101 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
4105 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
4106 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
4110 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
4112 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
4113 && insn
->tok
[i
].X_op
== O_symbol
)
4115 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
4116 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
4117 if (S_IS_DEFINED (sym
))
4118 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
4125 /* The routine xg_instruction_matches_option_term must return TRUE
4126 when a given option term is true. The meaning of all of the option
4127 terms is given interpretation by this function. This is needed when
4128 an option depends on the state of a directive, but there are no such
4129 options in use right now. */
4132 xg_instruction_matches_option_term (insn
, option
)
4133 TInsn
*insn ATTRIBUTE_UNUSED
;
4134 const ReqOrOption
*option
;
4136 if (strcmp (option
->option_name
, "realnop") == 0
4137 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
4139 /* These conditions were evaluated statically when building the
4140 relaxation table. There's no need to reevaluate them now. */
4145 as_fatal (_("internal error: unknown option name '%s'"),
4146 option
->option_name
);
4152 xg_instruction_matches_or_options (insn
, or_option
)
4154 const ReqOrOptionList
*or_option
;
4156 const ReqOrOption
*option
;
4157 /* Must match each of the AND terms. */
4158 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
4160 if (xg_instruction_matches_option_term (insn
, option
))
4168 xg_instruction_matches_options (insn
, options
)
4170 const ReqOptionList
*options
;
4172 const ReqOption
*req_options
;
4173 /* Must match each of the AND terms. */
4174 for (req_options
= options
;
4175 req_options
!= NULL
;
4176 req_options
= req_options
->next
)
4178 /* Must match one of the OR clauses. */
4179 if (!xg_instruction_matches_or_options (insn
,
4180 req_options
->or_option_terms
))
4187 /* Return the transition rule that matches or NULL if none matches. */
4190 xg_instruction_matches_rule (insn
, rule
)
4192 TransitionRule
*rule
;
4194 PreconditionList
*condition_l
;
4196 if (rule
->opcode
!= insn
->opcode
)
4199 for (condition_l
= rule
->conditions
;
4200 condition_l
!= NULL
;
4201 condition_l
= condition_l
->next
)
4205 Precondition
*cond
= condition_l
->precond
;
4210 /* The expression must be the constant. */
4211 assert (cond
->op_num
< insn
->ntok
);
4212 exp1
= &insn
->tok
[cond
->op_num
];
4213 if (expr_is_const (exp1
))
4218 if (get_expr_const (exp1
) != cond
->op_data
)
4222 if (get_expr_const (exp1
) == cond
->op_data
)
4229 else if (expr_is_register (exp1
))
4234 if (get_expr_register (exp1
) != cond
->op_data
)
4238 if (get_expr_register (exp1
) == cond
->op_data
)
4250 assert (cond
->op_num
< insn
->ntok
);
4251 assert (cond
->op_data
< insn
->ntok
);
4252 exp1
= &insn
->tok
[cond
->op_num
];
4253 exp2
= &insn
->tok
[cond
->op_data
];
4258 if (!expr_is_equal (exp1
, exp2
))
4262 if (expr_is_equal (exp1
, exp2
))
4274 if (!xg_instruction_matches_options (insn
, rule
->options
))
4282 transition_rule_cmp (a
, b
)
4283 const TransitionRule
*a
;
4284 const TransitionRule
*b
;
4286 bfd_boolean a_greater
= FALSE
;
4287 bfd_boolean b_greater
= FALSE
;
4289 ReqOptionList
*l_a
= a
->options
;
4290 ReqOptionList
*l_b
= b
->options
;
4292 /* We only care if they both are the same except for
4293 a const16 vs. an l32r. */
4295 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
4297 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
4298 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
4299 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
4301 if (l_or_a
->is_true
!= l_or_b
->is_true
)
4303 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
4305 /* This is the case we care about. */
4306 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
4307 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
4314 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
4315 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
4325 l_or_a
= l_or_a
->next
;
4326 l_or_b
= l_or_b
->next
;
4328 if (l_or_a
|| l_or_b
)
4337 /* Incomparable if the substitution was used differently in two cases. */
4338 if (a_greater
&& b_greater
)
4351 xg_instruction_match (insn
)
4354 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
4356 assert (insn
->opcode
< table
->num_opcodes
);
4358 /* Walk through all of the possible transitions. */
4359 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
4361 TransitionRule
*rule
= l
->rule
;
4362 if (xg_instruction_matches_rule (insn
, rule
))
4369 /* Return FALSE if no error. */
4372 xg_build_token_insn (instr_spec
, old_insn
, new_insn
)
4373 BuildInstr
*instr_spec
;
4380 switch (instr_spec
->typ
)
4383 new_insn
->insn_type
= ITYPE_INSN
;
4384 new_insn
->opcode
= instr_spec
->opcode
;
4385 new_insn
->is_specific_opcode
= FALSE
;
4386 new_insn
->loc
= old_insn
->loc
;
4388 case INSTR_LITERAL_DEF
:
4389 new_insn
->insn_type
= ITYPE_LITERAL
;
4390 new_insn
->opcode
= XTENSA_UNDEFINED
;
4391 new_insn
->is_specific_opcode
= FALSE
;
4392 new_insn
->loc
= old_insn
->loc
;
4394 case INSTR_LABEL_DEF
:
4395 as_bad (_("INSTR_LABEL_DEF not supported yet"));
4399 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
4402 const expressionS
*src_exp
;
4408 /* The expression must be the constant. */
4409 assert (b_op
->op_num
< MAX_INSN_ARGS
);
4410 exp
= &new_insn
->tok
[b_op
->op_num
];
4411 set_expr_const (exp
, b_op
->op_data
);
4415 assert (b_op
->op_num
< MAX_INSN_ARGS
);
4416 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
4417 src_exp
= &old_insn
->tok
[b_op
->op_data
];
4418 exp
= &new_insn
->tok
[b_op
->op_num
];
4419 copy_expr (exp
, src_exp
);
4424 as_bad (_("can't handle generation of literal/labels yet"));
4428 as_bad (_("can't handle undefined OP TYPE"));
4433 new_insn
->ntok
= num_ops
;
4438 /* Return TRUE if it was simplified. */
4441 xg_simplify_insn (old_insn
, new_insn
)
4445 TransitionRule
*rule
;
4446 BuildInstr
*insn_spec
;
4448 if (old_insn
->is_specific_opcode
|| !density_supported
)
4451 rule
= xg_instruction_match (old_insn
);
4455 insn_spec
= rule
->to_instr
;
4456 /* There should only be one. */
4457 assert (insn_spec
!= NULL
);
4458 assert (insn_spec
->next
== NULL
);
4459 if (insn_spec
->next
!= NULL
)
4462 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4468 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4469 l32i.n. (2) Check the number of operands. (3) Place the instruction
4470 tokens into the stack or if we can relax it at assembly time, place
4471 multiple instructions/literals onto the stack. Return FALSE if no
4475 xg_expand_assembly_insn (istack
, orig_insn
)
4481 memset (&new_insn
, 0, sizeof (TInsn
));
4483 /* Narrow it if we can. xg_simplify_insn now does all the
4484 appropriate checking (e.g., for the density option). */
4485 if (xg_simplify_insn (orig_insn
, &new_insn
))
4486 orig_insn
= &new_insn
;
4488 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4490 if (orig_insn
->ntok
< noperands
)
4492 as_bad (_("found %d operands for '%s': Expected %d"),
4494 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4498 if (orig_insn
->ntok
> noperands
)
4499 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
4501 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4504 /* If there are not enough operands, we will assert above. If there
4505 are too many, just cut out the extras here. */
4507 orig_insn
->ntok
= noperands
;
4511 Instructions with all constant immeds:
4512 Assemble them and relax the instruction if possible.
4513 Give error if not possible; no fixup needed.
4515 Instructions with symbolic immeds:
4516 Assemble them with a Fix up (that may cause instruction expansion).
4517 Also close out the fragment if the fixup may cause instruction expansion.
4519 There are some other special cases where we need alignment.
4520 1) before certain instructions with required alignment (OPCODE_ALIGN)
4521 2) before labels that have jumps (LABEL_ALIGN)
4522 3) after call instructions (RETURN_ALIGN)
4523 Multiple of these may be possible on the same fragment.
4524 If so, make sure to satisfy the required alignment.
4525 Then try to get the desired alignment. */
4527 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4530 if (orig_insn
->is_specific_opcode
|| !use_transform ())
4532 istack_push (istack
, orig_insn
);
4536 if (tinsn_has_symbolic_operands (orig_insn
))
4538 if (tinsn_has_complex_operands (orig_insn
))
4539 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4541 istack_push (istack
, orig_insn
);
4545 if (xg_immeds_fit (orig_insn
))
4546 istack_push (istack
, orig_insn
);
4548 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4555 /* Currently all literals that are generated here are 32-bit L32R targets. */
4558 xg_assemble_literal (insn
)
4559 /* const */ TInsn
*insn
;
4562 symbolS
*lit_sym
= NULL
;
4564 /* size = 4 for L32R. It could easily be larger when we move to
4565 larger constants. Add a parameter later. */
4566 offsetT litsize
= 4;
4567 offsetT litalign
= 2; /* 2^2 = 4 */
4568 expressionS saved_loc
;
4569 expressionS
* emit_val
;
4571 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4573 assert (insn
->insn_type
== ITYPE_LITERAL
);
4574 assert (insn
->ntok
== 1); /* must be only one token here */
4576 xtensa_switch_to_literal_fragment (&state
);
4578 emit_val
= &insn
->tok
[0];
4579 if (emit_val
->X_op
== O_big
)
4581 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4584 /* This happens when someone writes a "movi a2, big_number". */
4585 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4586 _("invalid immediate"));
4587 xtensa_restore_emit_state (&state
);
4592 /* Force a 4-byte align here. Note that this opens a new frag, so all
4593 literals done with this function have a frag to themselves. That's
4594 important for the way text section literals work. */
4595 frag_align (litalign
, 0, 0);
4596 record_alignment (now_seg
, litalign
);
4598 if (emit_val
->X_op
== O_pltrel
)
4600 char *p
= frag_more (litsize
);
4601 xtensa_set_frag_assembly_state (frag_now
);
4602 if (emit_val
->X_add_symbol
)
4603 emit_val
->X_op
= O_symbol
;
4605 emit_val
->X_op
= O_constant
;
4606 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4607 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4610 emit_expr (emit_val
, litsize
);
4612 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4613 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4614 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4615 lit_sym
= frag_now
->fr_symbol
;
4616 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4619 xtensa_restore_emit_state (&state
);
4625 xg_valid_literal_expression (exp
)
4626 const expressionS
*exp
;
4644 xg_assemble_literal_space (size
, slot
)
4645 /* const */ int size
;
4649 /* We might have to do something about this alignment. It only
4650 takes effect if something is placed here. */
4651 offsetT litalign
= 2; /* 2^2 = 4 */
4652 fragS
*lit_saved_frag
;
4654 assert (size
% 4 == 0);
4656 xtensa_switch_to_literal_fragment (&state
);
4658 /* Force a 4-byte align here. */
4659 frag_align (litalign
, 0, 0);
4660 record_alignment (now_seg
, litalign
);
4662 xg_force_frag_space (size
);
4664 lit_saved_frag
= frag_now
;
4665 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4666 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4667 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4668 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4671 xtensa_restore_emit_state (&state
);
4672 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4677 xtensa_create_literal_symbol (sec
, frag
)
4681 static int lit_num
= 0;
4682 static char name
[256];
4685 sprintf (name
, ".L_lit_sym%d", lit_num
);
4687 /* Create a local symbol. If it is in a linkonce section, we have to
4688 be careful to make sure that if it is used in a relocation that the
4689 symbol will be in the output file. */
4690 if (get_is_linkonce_section (stdoutput
, sec
))
4692 symbolP
= symbol_new (name
, sec
, 0, frag
);
4693 S_CLEAR_EXTERNAL (symbolP
);
4694 /* symbolP->local = 1; */
4697 symbolP
= symbol_new (name
, sec
, 0, frag
);
4699 xtensa_add_literal_sym (symbolP
);
4701 frag
->tc_frag_data
.is_literal
= TRUE
;
4708 xtensa_add_literal_sym (sym
)
4713 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4715 l
->next
= literal_syms
;
4721 xtensa_add_insn_label (sym
)
4726 if (!free_insn_labels
)
4727 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4730 l
= free_insn_labels
;
4731 free_insn_labels
= l
->next
;
4735 l
->next
= insn_labels
;
4741 xtensa_clear_insn_labels (void)
4745 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
4752 /* Return TRUE if the section flags are marked linkonce
4753 or the name is .gnu.linkonce*. */
4756 get_is_linkonce_section (abfd
, sec
)
4757 bfd
*abfd ATTRIBUTE_UNUSED
;
4760 flagword flags
, link_once_flags
;
4762 flags
= bfd_get_section_flags (abfd
, sec
);
4763 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4765 /* Flags might not be set yet. */
4766 if (!link_once_flags
)
4768 static size_t len
= sizeof ".gnu.linkonce.t.";
4770 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4771 link_once_flags
= SEC_LINK_ONCE
;
4773 return (link_once_flags
!= 0);
4778 xg_emit_insn_to_buf (tinsn
, fmt
, buf
, fragP
, offset
, build_fix
)
4784 bfd_boolean build_fix
;
4786 static xtensa_insnbuf insnbuf
= NULL
;
4787 bfd_boolean has_symbolic_immed
= FALSE
;
4788 bfd_boolean ok
= TRUE
;
4790 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4792 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4793 if (has_symbolic_immed
&& build_fix
)
4796 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4797 expressionS
*exp
= &tinsn
->tok
[opnum
];
4799 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4802 fragP
->tc_frag_data
.is_insn
= TRUE
;
4803 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4808 /* Put in a fixup record based on the opcode.
4809 Return TRUE on success. */
4812 xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, expr
, fragP
, offset
)
4821 xtensa_opcode opcode
= tinsn
->opcode
;
4822 bfd_reloc_code_real_type reloc
;
4823 reloc_howto_type
*howto
;
4827 reloc
= BFD_RELOC_NONE
;
4829 /* First try the special cases for "alternate" relocs. */
4830 if (opcode
== xtensa_l32r_opcode
)
4832 if (fragP
->tc_frag_data
.use_absolute_literals
)
4833 reloc
= encode_alt_reloc (slot
);
4835 else if (opcode
== xtensa_const16_opcode
)
4837 if (expr
->X_op
== O_lo16
)
4839 reloc
= encode_reloc (slot
);
4840 expr
->X_op
= O_symbol
;
4842 else if (expr
->X_op
== O_hi16
)
4844 reloc
= encode_alt_reloc (slot
);
4845 expr
->X_op
= O_symbol
;
4849 if (opnum
!= get_relaxable_immed (opcode
))
4851 as_bad (_("invalid relocation for operand %i of '%s'"),
4852 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4856 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4857 into the symbol table where the generic portions of the assembler
4858 won't know what to do with them. */
4859 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4861 as_bad (_("invalid expression for operand %i of '%s'"),
4862 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4866 /* Next try the generic relocs. */
4867 if (reloc
== BFD_RELOC_NONE
)
4868 reloc
= encode_reloc (slot
);
4869 if (reloc
== BFD_RELOC_NONE
)
4871 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4875 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4878 as_bad (_("undefined symbol for opcode \"%s\""),
4879 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4883 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4884 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4885 howto
->pc_relative
, reloc
);
4887 if (expr
->X_add_symbol
4888 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4889 || S_IS_WEAK (expr
->X_add_symbol
)))
4890 the_fix
->fx_plt
= TRUE
;
4892 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4893 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4894 the_fix
->tc_fix_data
.slot
= slot
;
4901 xg_resolve_literals (insn
, lit_sym
)
4905 symbolS
*sym
= get_special_literal_symbol ();
4909 assert (insn
->insn_type
== ITYPE_INSN
);
4910 for (i
= 0; i
< insn
->ntok
; i
++)
4911 if (insn
->tok
[i
].X_add_symbol
== sym
)
4912 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4918 xg_resolve_labels (insn
, label_sym
)
4922 symbolS
*sym
= get_special_label_symbol ();
4924 /* assert (!insn->is_literal); */
4925 for (i
= 0; i
< insn
->ntok
; i
++)
4926 if (insn
->tok
[i
].X_add_symbol
== sym
)
4927 insn
->tok
[i
].X_add_symbol
= label_sym
;
4932 /* Return TRUE if the instruction can write to the specified
4933 integer register. */
4936 is_register_writer (insn
, regset
, regnum
)
4943 xtensa_isa isa
= xtensa_default_isa
;
4945 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4947 for (i
= 0; i
< num_ops
; i
++)
4950 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4951 if ((inout
== 'o' || inout
== 'm')
4952 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4954 xtensa_regfile opnd_rf
=
4955 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4956 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4958 if ((insn
->tok
[i
].X_op
== O_register
)
4959 && (insn
->tok
[i
].X_add_number
== regnum
))
4969 is_bad_loopend_opcode (tinsn
)
4970 const TInsn
* tinsn
;
4972 xtensa_opcode opcode
= tinsn
->opcode
;
4974 if (opcode
== XTENSA_UNDEFINED
)
4977 if (opcode
== xtensa_call0_opcode
4978 || opcode
== xtensa_callx0_opcode
4979 || opcode
== xtensa_call4_opcode
4980 || opcode
== xtensa_callx4_opcode
4981 || opcode
== xtensa_call8_opcode
4982 || opcode
== xtensa_callx8_opcode
4983 || opcode
== xtensa_call12_opcode
4984 || opcode
== xtensa_callx12_opcode
4985 || opcode
== xtensa_isync_opcode
4986 || opcode
== xtensa_ret_opcode
4987 || opcode
== xtensa_ret_n_opcode
4988 || opcode
== xtensa_retw_opcode
4989 || opcode
== xtensa_retw_n_opcode
4990 || opcode
== xtensa_waiti_opcode
4991 || opcode
== xtensa_rsr_lcount_opcode
)
4998 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4999 This allows the debugger to add unaligned labels.
5000 Also, the assembler generates stabs labels that need
5001 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
5004 is_unaligned_label (sym
)
5007 const char *name
= S_GET_NAME (sym
);
5008 static size_t fake_size
= 0;
5012 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
5015 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
5017 fake_size
= strlen (FAKE_LABEL_NAME
);
5020 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
5021 && (name
[fake_size
] == 'F'
5022 || name
[fake_size
] == 'L'
5023 || (name
[fake_size
] == 'e'
5024 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
5032 next_non_empty_frag (fragP
)
5035 fragS
*next_fragP
= fragP
->fr_next
;
5037 /* Sometimes an empty will end up here due storage allocation issues.
5038 So we have to skip until we find something legit. */
5039 while (next_fragP
&& next_fragP
->fr_fix
== 0)
5040 next_fragP
= next_fragP
->fr_next
;
5042 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
5050 next_frag_opcode_is_loop (fragP
, opcode
)
5052 xtensa_opcode
*opcode
;
5054 xtensa_opcode out_opcode
;
5055 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
5057 if (next_fragP
== NULL
)
5060 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
5061 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
5063 *opcode
= out_opcode
;
5071 next_frag_format_size (fragP
)
5074 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
5075 return frag_format_size (next_fragP
);
5080 frag_format_size (fragP
)
5081 const fragS
* fragP
;
5083 static xtensa_insnbuf insnbuf
= NULL
;
5084 xtensa_isa isa
= xtensa_default_isa
;
5089 insnbuf
= xtensa_insnbuf_alloc (isa
);
5092 return XTENSA_UNDEFINED
;
5094 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
5096 fmt
= xtensa_format_decode (isa
, insnbuf
);
5097 if (fmt
== XTENSA_UNDEFINED
)
5098 return XTENSA_UNDEFINED
;
5099 fmt_size
= xtensa_format_length (isa
, fmt
);
5101 /* If the next format won't be changing due to relaxation, just
5102 return the length of the first format. */
5103 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
5106 /* If during relaxation we have to pull an instruction out of a
5107 multi-slot instruction, we will return the more conservative
5108 number. This works because alignment on bigger instructions
5109 is more restrictive than alignment on smaller instructions.
5110 This is more conservative than we would like, but it happens
5113 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
5116 /* If we aren't doing one of our own relaxations or it isn't
5117 slot-based, then the insn size won't change. */
5118 if (fragP
->fr_type
!= rs_machine_dependent
)
5120 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
5123 /* If an instruction is about to grow, return the longer size. */
5124 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
5125 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
5128 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
5129 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
5135 /* Return TRUE if the target frag is one of the next non-empty frags. */
5138 is_next_frag_target (fragP
, target
)
5140 const fragS
*target
;
5145 for (; fragP
; fragP
= fragP
->fr_next
)
5147 if (fragP
== target
)
5149 if (fragP
->fr_fix
!= 0)
5151 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
5153 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
5154 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
5156 if (fragP
->fr_type
== rs_space
)
5163 /* If the next legit fragment is an end-of-loop marker,
5164 switch its state so it will instantiate a NOP. */
5167 update_next_frag_state (fragP
, unreachable
)
5169 bfd_boolean unreachable
;
5171 fragS
*next_fragP
= fragP
->fr_next
;
5172 fragS
*new_target
= NULL
;
5176 /* We are guaranteed there will be one of these... */
5177 while (!(next_fragP
->fr_type
== rs_machine_dependent
5178 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
5179 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
5180 next_fragP
= next_fragP
->fr_next
;
5182 assert (next_fragP
->fr_type
== rs_machine_dependent
5183 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
5184 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
5186 /* ...and one of these. */
5187 new_target
= next_fragP
->fr_next
;
5188 while (!(new_target
->fr_type
== rs_machine_dependent
5189 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
5190 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
5191 new_target
= new_target
->fr_next
;
5193 assert (new_target
->fr_type
== rs_machine_dependent
5194 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
5195 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
5201 next_fragP
->fr_subtype
= RELAX_UNREACHABLE
;
5202 next_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
5203 new_target
->fr_subtype
= RELAX_DESIRE_ALIGN
;
5204 new_target
->tc_frag_data
.is_branch_target
= TRUE
;
5206 while (next_fragP
&& next_fragP
->fr_fix
== 0)
5208 if (next_fragP
->fr_type
== rs_machine_dependent
5209 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
5211 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
5215 next_fragP
= next_fragP
->fr_next
;
5222 next_fragP
->fr_subtype
= RELAX_MAYBE_UNREACHABLE
;
5223 next_fragP
->tc_frag_data
.is_unreachable
= FALSE
;
5224 new_target
->fr_subtype
= RELAX_MAYBE_DESIRE_ALIGN
;
5225 new_target
->tc_frag_data
.is_branch_target
= FALSE
;
5232 next_frag_is_branch_target (fragP
)
5235 /* Sometimes an empty will end up here due to storage allocation issues,
5236 so we have to skip until we find something legit. */
5237 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
5239 if (fragP
->tc_frag_data
.is_branch_target
)
5241 if (fragP
->fr_fix
!= 0)
5249 next_frag_is_loop_target (fragP
)
5252 /* Sometimes an empty will end up here due storage allocation issues.
5253 So we have to skip until we find something legit. */
5254 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
5256 if (fragP
->tc_frag_data
.is_loop_target
)
5258 if (fragP
->fr_fix
!= 0)
5266 next_frag_pre_opcode_bytes (fragp
)
5269 const fragS
*next_fragp
= fragp
->fr_next
;
5270 xtensa_opcode next_opcode
;
5272 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
5275 /* Sometimes an empty will end up here due to storage allocation issues,
5276 so we have to skip until we find something legit. */
5277 while (next_fragp
->fr_fix
== 0)
5278 next_fragp
= next_fragp
->fr_next
;
5280 if (next_fragp
->fr_type
!= rs_machine_dependent
)
5283 /* There is some implicit knowledge encoded in here.
5284 The LOOP instructions that are NOT RELAX_IMMED have
5285 been relaxed. Note that we can assume that the LOOP
5286 instruction is in slot 0 because loops aren't bundleable. */
5287 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
5288 return get_expanded_loop_offset (next_opcode
);
5294 /* Mark a location where we can later insert literal frags. Update
5295 the section's literal_pool_loc, so subsequent literals can be
5296 placed nearest to their use. */
5299 xtensa_mark_literal_pool_location ()
5301 /* Any labels pointing to the current location need
5302 to be adjusted to after the literal pool. */
5304 fragS
*pool_location
;
5306 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
5309 frag_align (2, 0, 0);
5310 record_alignment (now_seg
, 2);
5312 /* We stash info in the fr_var of these frags
5313 so we can later move the literal's fixes into this
5314 frchain's fix list. We can use fr_var because fr_var's
5315 interpretation depends solely on the fr_type and subtype. */
5316 pool_location
= frag_now
;
5317 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
5318 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
5319 xtensa_set_frag_assembly_state (frag_now
);
5320 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
5321 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
5322 xtensa_set_frag_assembly_state (frag_now
);
5324 /* Now put a frag into the literal pool that points to this location. */
5325 set_literal_pool_location (now_seg
, pool_location
);
5326 xtensa_switch_to_non_abs_literal_fragment (&s
);
5327 frag_align (2, 0, 0);
5328 record_alignment (now_seg
, 2);
5330 /* Close whatever frag is there. */
5331 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
5332 xtensa_set_frag_assembly_state (frag_now
);
5333 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
5334 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
5335 xtensa_restore_emit_state (&s
);
5336 xtensa_set_frag_assembly_state (frag_now
);
5340 /* The "loops_ok" argument is provided to allow ignoring labels that
5341 define loop ends. This fixes a bug where the NOPs to align a
5342 loop opcode were included in a previous zero-cost loop:
5361 This argument is used to prevent moving the NOP to before the
5362 loop-end label, which is what you want in this special case. */
5365 xtensa_move_labels (new_frag
, new_offset
, loops_ok
)
5368 bfd_boolean loops_ok
;
5372 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
5374 symbolS
*lit_sym
= lit
->sym
;
5375 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
5377 S_SET_VALUE (lit_sym
, new_offset
);
5378 symbol_set_frag (lit_sym
, new_frag
);
5384 /* Build a nop of the correct size into tinsn. */
5387 build_nop (tinsn
, size
)
5395 tinsn
->opcode
= xtensa_nop_n_opcode
;
5397 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
5398 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
5402 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
5404 tinsn
->opcode
= xtensa_or_opcode
;
5405 set_expr_const (&tinsn
->tok
[0], 1);
5406 set_expr_const (&tinsn
->tok
[1], 1);
5407 set_expr_const (&tinsn
->tok
[2], 1);
5411 tinsn
->opcode
= xtensa_nop_opcode
;
5413 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
5418 /* Assemble a NOP of the requested size in the buffer. User must have
5419 allocated "buf" with at least "size" bytes. */
5422 assemble_nop (size
, buf
)
5426 static xtensa_insnbuf insnbuf
= NULL
;
5429 build_nop (&tinsn
, size
);
5432 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
5434 tinsn_to_insnbuf (&tinsn
, insnbuf
);
5435 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
5439 /* Return the number of bytes for the offset of the expanded loop
5440 instruction. This should be incorporated into the relaxation
5441 specification but is hard-coded here. This is used to auto-align
5442 the loop instruction. It is invalid to call this function if the
5443 configuration does not have loops or if the opcode is not a loop
5447 get_expanded_loop_offset (opcode
)
5448 xtensa_opcode opcode
;
5450 /* This is the OFFSET of the loop instruction in the expanded loop.
5451 This MUST correspond directly to the specification of the loop
5452 expansion. It will be validated on fragment conversion. */
5453 assert (opcode
!= XTENSA_UNDEFINED
);
5454 if (opcode
== xtensa_loop_opcode
)
5456 if (opcode
== xtensa_loopnez_opcode
)
5458 if (opcode
== xtensa_loopgtz_opcode
)
5460 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
5466 get_literal_pool_location (seg
)
5469 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
5474 set_literal_pool_location (seg
, literal_pool_loc
)
5476 fragS
*literal_pool_loc
;
5478 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
5482 /* Set frag assembly state should be called when a new frag is
5483 opened and after a frag has been closed. */
5486 xtensa_set_frag_assembly_state (fragP
)
5489 if (!density_supported
)
5490 fragP
->tc_frag_data
.is_no_density
= TRUE
;
5492 /* This function is called from subsegs_finish, which is called
5493 after xtensa_end, so we can't use "use_transform" or
5494 "use_schedule" here. */
5495 if (!directive_state
[directive_transform
])
5496 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5497 fragP
->tc_frag_data
.use_absolute_literals
=
5498 directive_state
[directive_absolute_literals
];
5499 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5504 relaxable_section (sec
)
5507 return (sec
->flags
& SEC_DEBUGGING
) == 0;
5512 xtensa_find_unmarked_state_frags ()
5516 /* Walk over each fragment of all of the current segments. For each
5517 unmarked fragment, mark it with the same info as the previous
5519 for (seclist
= &stdoutput
->sections
;
5520 seclist
&& *seclist
;
5521 seclist
= &(*seclist
)->next
)
5523 segT sec
= *seclist
;
5524 segment_info_type
*seginfo
;
5527 flags
= bfd_get_section_flags (stdoutput
, sec
);
5528 if (flags
& SEC_DEBUGGING
)
5530 if (!(flags
& SEC_ALLOC
))
5533 seginfo
= seg_info (sec
);
5534 if (seginfo
&& seginfo
->frchainP
)
5536 fragS
*last_fragP
= 0;
5537 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5538 fragP
= fragP
->fr_next
)
5540 if (fragP
->fr_fix
!= 0
5541 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5543 if (last_fragP
== 0)
5545 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5546 _("assembly state not set for first frag in section %s"),
5551 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5552 fragP
->tc_frag_data
.is_no_density
=
5553 last_fragP
->tc_frag_data
.is_no_density
;
5554 fragP
->tc_frag_data
.is_no_transform
=
5555 last_fragP
->tc_frag_data
.is_no_transform
;
5556 fragP
->tc_frag_data
.use_absolute_literals
=
5557 last_fragP
->tc_frag_data
.use_absolute_literals
;
5560 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5569 xtensa_find_unaligned_branch_targets (abfd
, sec
, unused
)
5570 bfd
*abfd ATTRIBUTE_UNUSED
;
5572 PTR unused ATTRIBUTE_UNUSED
;
5574 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5575 segment_info_type
*seginfo
= seg_info (sec
);
5576 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5578 if (flags
& SEC_CODE
)
5580 xtensa_isa isa
= xtensa_default_isa
;
5581 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5582 while (frag
!= NULL
)
5584 if (frag
->tc_frag_data
.is_branch_target
)
5590 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
5591 fmt
= xtensa_format_decode (isa
, insnbuf
);
5592 op_size
= xtensa_format_length (isa
, fmt
);
5593 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5594 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
5595 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5596 _("unaligned branch target: %d bytes at 0x%lx"),
5597 op_size
, frag
->fr_address
);
5599 frag
= frag
->fr_next
;
5601 xtensa_insnbuf_free (isa
, insnbuf
);
5607 xtensa_find_unaligned_loops (abfd
, sec
, unused
)
5608 bfd
*abfd ATTRIBUTE_UNUSED
;
5610 PTR unused ATTRIBUTE_UNUSED
;
5612 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5613 segment_info_type
*seginfo
= seg_info (sec
);
5614 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5615 xtensa_isa isa
= xtensa_default_isa
;
5617 if (flags
& SEC_CODE
)
5619 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5620 while (frag
!= NULL
)
5622 if (frag
->tc_frag_data
.is_first_loop_insn
)
5628 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
5629 fmt
= xtensa_format_decode (isa
, insnbuf
);
5630 op_size
= xtensa_format_length (isa
, fmt
);
5631 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5633 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
5634 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5635 _("unaligned loop: %d bytes at 0x%lx"),
5636 op_size
, frag
->fr_address
);
5638 frag
= frag
->fr_next
;
5640 xtensa_insnbuf_free (isa
, insnbuf
);
5646 xg_apply_tentative_value (fixP
, val
)
5650 xtensa_isa isa
= xtensa_default_isa
;
5651 static xtensa_insnbuf insnbuf
= NULL
;
5652 static xtensa_insnbuf slotbuf
= NULL
;
5655 bfd_boolean alt_reloc
;
5656 xtensa_opcode opcode
;
5657 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5659 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
5661 as_fatal (_("unexpected fix"));
5665 insnbuf
= xtensa_insnbuf_alloc (isa
);
5666 slotbuf
= xtensa_insnbuf_alloc (isa
);
5669 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
5670 fmt
= xtensa_format_decode (isa
, insnbuf
);
5671 if (fmt
== XTENSA_UNDEFINED
)
5672 as_fatal (_("undecodable fix"));
5673 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5674 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5675 if (opcode
== XTENSA_UNDEFINED
)
5676 as_fatal (_("undecodable fix"));
5678 /* CONST16 immediates are not PC-relative, despite the fact that we
5679 reuse the normal PC-relative operand relocations for the low part
5680 of a CONST16 operand. The code in tc_gen_reloc does not decode
5681 the opcodes so it is more convenient to detect this special case
5683 if (opcode
== xtensa_const16_opcode
)
5686 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5687 get_relaxable_immed (opcode
), val
,
5688 fixP
->fx_file
, fixP
->fx_line
);
5690 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5691 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
5695 /* External Functions and Other GAS Hooks. */
5698 xtensa_target_format ()
5700 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5705 xtensa_file_arch_init (abfd
)
5708 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5713 md_number_to_chars (buf
, val
, n
)
5718 if (target_big_endian
)
5719 number_to_chars_bigendian (buf
, val
, n
);
5721 number_to_chars_littleendian (buf
, val
, n
);
5725 /* This function is called once, at assembler startup time. It should
5726 set up all the tables, etc. that the MD part of the assembler will
5732 segT current_section
= now_seg
;
5733 int current_subsec
= now_subseg
;
5736 xtensa_default_isa
= xtensa_isa_init (0, 0);
5737 isa
= xtensa_default_isa
;
5741 /* Set up the .literal, .fini.literal and .init.literal sections. */
5742 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5743 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5744 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5745 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5746 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5748 subseg_set (current_section
, current_subsec
);
5750 xg_init_vinsn (&cur_vinsn
);
5752 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5753 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5754 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5755 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5756 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5757 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5758 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5759 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5760 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5761 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5762 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5763 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5764 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5765 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5766 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5767 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5768 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5769 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5770 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5771 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5772 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5773 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5774 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5775 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5776 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5777 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5778 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5779 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5780 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5782 init_op_placement_info_table ();
5784 /* Set up the assembly state. */
5785 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5786 xtensa_set_frag_assembly_state (frag_now
);
5790 /* TC_INIT_FIX_DATA hook */
5793 xtensa_init_fix_data (x
)
5796 x
->tc_fix_data
.slot
= 0;
5797 x
->tc_fix_data
.X_add_symbol
= NULL
;
5798 x
->tc_fix_data
.X_add_number
= 0;
5802 /* tc_frob_label hook */
5805 xtensa_frob_label (sym
)
5808 /* Since the label was already attached to a frag associated with the
5809 previous basic block, it now needs to be reset to the current frag. */
5810 symbol_set_frag (sym
, frag_now
);
5811 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5813 if (generating_literals
)
5814 xtensa_add_literal_sym (sym
);
5816 xtensa_add_insn_label (sym
);
5818 if (symbol_get_tc (sym
)->is_loop_target
5819 && (get_last_insn_flags (now_seg
, now_subseg
)
5820 & FLAG_IS_BAD_LOOPEND
) != 0)
5821 as_bad (_("invalid last instruction for a zero-overhead loop"));
5823 /* No target aligning in the absolute section. */
5824 if (now_seg
!= absolute_section
5825 && do_align_targets ()
5826 && !is_unaligned_label (sym
)
5827 && !generating_literals
)
5829 float freq
= get_subseg_info (now_seg
, now_subseg
)->cur_target_freq
;
5830 xtensa_set_frag_assembly_state (frag_now
);
5832 /* The only time this type of frag grows is when there is a
5833 negatable branch that needs to be relaxed as the last
5834 instruction in a zero-overhead loop. Because alignment frags
5835 are so common, marking them all as possibly growing four
5836 bytes makes any worst-case analysis appear much worse than it
5837 is. So, we make fr_var not actually reflect the amount of
5838 memory allocated at the end of this frag, but rather the
5839 amount of memory this frag might grow. The "4, 0" below
5840 allocates four bytes at the end of the frag for room to grow
5841 if we need to relax a loop end with a NOP. Frags prior to
5842 this one might grow to align this one, but the frag itself
5843 won't grow unless it meets the condition above. */
5845 #define RELAX_LOOP_END_BYTES 4
5847 frag_var (rs_machine_dependent
,
5848 RELAX_LOOP_END_BYTES
, (int) freq
,
5849 RELAX_DESIRE_ALIGN_IF_TARGET
,
5850 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5851 xtensa_set_frag_assembly_state (frag_now
);
5852 xtensa_move_labels (frag_now
, 0, TRUE
);
5855 /* We need to mark the following properties even if we aren't aligning. */
5857 /* If the label is already known to be a branch target, i.e., a
5858 forward branch, mark the frag accordingly. Backward branches
5859 are handled by xg_add_branch_and_loop_targets. */
5860 if (symbol_get_tc (sym
)->is_branch_target
)
5861 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5863 /* Loops only go forward, so they can be identified here. */
5864 if (symbol_get_tc (sym
)->is_loop_target
)
5865 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5869 /* tc_unrecognized_line hook */
5872 xtensa_unrecognized_line (ch
)
5878 if (cur_vinsn
.inside_bundle
== 0)
5880 /* PR8110: Cannot emit line number info inside a FLIX bundle
5881 when using --gstabs. Temporarily disable debug info. */
5882 generate_lineno_debug ();
5883 if (debug_type
== DEBUG_STABS
)
5885 xt_saved_debug_type
= debug_type
;
5886 debug_type
= DEBUG_NONE
;
5889 cur_vinsn
.inside_bundle
= 1;
5893 as_bad (_("extra opening brace"));
5899 if (cur_vinsn
.inside_bundle
)
5900 finish_vinsn (&cur_vinsn
);
5903 as_bad (_("extra closing brace"));
5908 as_bad (_("syntax error"));
5915 /* md_flush_pending_output hook */
5918 xtensa_flush_pending_output ()
5920 if (cur_vinsn
.inside_bundle
)
5921 as_bad (_("missing closing brace"));
5923 /* If there is a non-zero instruction fragment, close it. */
5924 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5926 frag_wane (frag_now
);
5928 xtensa_set_frag_assembly_state (frag_now
);
5930 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5932 xtensa_clear_insn_labels ();
5936 /* We had an error while parsing an instruction. The string might look
5937 like this: "insn arg1, arg2 }". If so, we need to see the closing
5938 brace and reset some fields. Otherwise, the vinsn never gets closed
5939 and the num_slots field will grow past the end of the array of slots,
5940 and bad things happen. */
5943 error_reset_cur_vinsn ()
5945 if (cur_vinsn
.inside_bundle
)
5947 if (*input_line_pointer
== '}'
5948 || *(input_line_pointer
- 1) == '}'
5949 || *(input_line_pointer
- 2) == '}')
5950 xg_clear_vinsn (&cur_vinsn
);
5959 xtensa_isa isa
= xtensa_default_isa
;
5962 bfd_boolean has_underbar
= FALSE
;
5963 char *arg_strings
[MAX_INSN_ARGS
];
5965 TInsn orig_insn
; /* Original instruction from the input. */
5967 tinsn_init (&orig_insn
);
5969 /* Split off the opcode. */
5970 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5971 opname
= xmalloc (opnamelen
+ 1);
5972 memcpy (opname
, str
, opnamelen
);
5973 opname
[opnamelen
] = '\0';
5975 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5978 as_bad (_("syntax error"));
5982 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5985 /* Check for an underbar prefix. */
5988 has_underbar
= TRUE
;
5992 orig_insn
.insn_type
= ITYPE_INSN
;
5994 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5996 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5997 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5999 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
6000 if (fmt
== XTENSA_UNDEFINED
)
6002 as_bad (_("unknown opcode or format name '%s'"), opname
);
6003 error_reset_cur_vinsn ();
6006 if (!cur_vinsn
.inside_bundle
)
6008 as_bad (_("format names only valid inside bundles"));
6009 error_reset_cur_vinsn ();
6012 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
6013 as_warn (_("multiple formats specified for one bundle; using '%s'"),
6015 cur_vinsn
.format
= fmt
;
6016 free (has_underbar
? opname
- 1 : opname
);
6017 error_reset_cur_vinsn ();
6021 /* Special case: The call instructions should be marked "specific opcode"
6022 to keep them from expanding. */
6023 if (!use_longcalls () && is_direct_call_opcode (orig_insn
.opcode
))
6024 orig_insn
.is_specific_opcode
= TRUE
;
6026 /* Parse the arguments. */
6027 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
6029 as_bad (_("syntax error"));
6030 error_reset_cur_vinsn ();
6034 /* Free the opcode and argument strings, now that they've been parsed. */
6035 free (has_underbar
? opname
- 1 : opname
);
6037 while (num_args
-- > 0)
6038 free (arg_strings
[num_args
]);
6040 /* Get expressions for invisible operands. */
6041 if (get_invisible_operands (&orig_insn
))
6043 error_reset_cur_vinsn ();
6047 /* Check for the right number and type of arguments. */
6048 if (tinsn_check_arguments (&orig_insn
))
6050 error_reset_cur_vinsn ();
6054 dwarf2_where (&orig_insn
.loc
);
6056 xg_add_branch_and_loop_targets (&orig_insn
);
6058 /* Special-case for "entry" instruction. */
6059 if (is_entry_opcode (orig_insn
.opcode
))
6061 /* Check that the third opcode (#2) is >= 16. */
6062 if (orig_insn
.ntok
>= 3)
6064 expressionS
*exp
= &orig_insn
.tok
[2];
6068 if (exp
->X_add_number
< 16)
6069 as_warn (_("entry instruction with stack decrement < 16"));
6073 as_warn (_("entry instruction with non-constant decrement"));
6079 assemble_tokens (opcode, tok, ntok);
6080 expand the tokens from the orig_insn into the
6081 stack of instructions that will not expand
6082 unless required at relaxation time. */
6084 if (!cur_vinsn
.inside_bundle
)
6085 emit_single_op (&orig_insn
);
6086 else /* We are inside a bundle. */
6088 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
6089 cur_vinsn
.num_slots
++;
6090 if (*input_line_pointer
== '}'
6091 || *(input_line_pointer
- 1) == '}'
6092 || *(input_line_pointer
- 2) == '}')
6093 finish_vinsn (&cur_vinsn
);
6096 /* We've just emitted a new instruction so clear the list of labels. */
6097 xtensa_clear_insn_labels ();
6101 /* HANDLE_ALIGN hook */
6103 /* For a .align directive, we mark the previous block with the alignment
6104 information. This will be placed in the object file in the
6105 property section corresponding to this section. */
6108 xtensa_handle_align (fragP
)
6112 && !get_frag_is_literal (fragP
)
6113 && (fragP
->fr_type
== rs_align
6114 || fragP
->fr_type
== rs_align_code
)
6115 && fragP
->fr_address
+ fragP
->fr_fix
> 0
6116 && fragP
->fr_offset
> 0
6117 && now_seg
!= bss_section
)
6119 fragP
->tc_frag_data
.is_align
= TRUE
;
6120 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
6123 if (fragP
->fr_type
== rs_align_test
)
6126 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6128 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6129 _("unaligned entry instruction"));
6134 /* TC_FRAG_INIT hook */
6137 xtensa_frag_init (frag
)
6140 xtensa_set_frag_assembly_state (frag
);
6145 md_undefined_symbol (name
)
6146 char *name ATTRIBUTE_UNUSED
;
6152 /* Round up a section size to the appropriate boundary. */
6155 md_section_align (segment
, size
)
6156 segT segment ATTRIBUTE_UNUSED
;
6159 return size
; /* Byte alignment is fine. */
6164 md_pcrel_from (fixP
)
6168 static xtensa_insnbuf insnbuf
= NULL
;
6169 static xtensa_insnbuf slotbuf
= NULL
;
6172 xtensa_opcode opcode
;
6175 xtensa_isa isa
= xtensa_default_isa
;
6176 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6177 bfd_boolean alt_reloc
;
6182 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
6187 insnbuf
= xtensa_insnbuf_alloc (isa
);
6188 slotbuf
= xtensa_insnbuf_alloc (isa
);
6191 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
6192 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
6193 fmt
= xtensa_format_decode (isa
, insnbuf
);
6195 if (fmt
== XTENSA_UNDEFINED
)
6196 as_fatal (_("bad instruction format"));
6198 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
6199 as_fatal (_("invalid relocation"));
6201 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
6202 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
6204 /* Check for "alternate" relocation (operand not specified). */
6205 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
6207 if (opcode
!= xtensa_l32r_opcode
6208 && opcode
!= xtensa_const16_opcode
)
6209 as_fatal (_("invalid relocation for '%s' instruction"),
6210 xtensa_opcode_name (isa
, opcode
));
6214 opnum
= get_relaxable_immed (opcode
);
6216 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
6217 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
6219 as_bad_where (fixP
->fx_file
,
6221 _("invalid relocation for operand %d of '%s'"),
6222 opnum
, xtensa_opcode_name (isa
, opcode
));
6225 return 0 - opnd_value
;
6229 /* TC_FORCE_RELOCATION hook */
6232 xtensa_force_relocation (fix
)
6235 switch (fix
->fx_r_type
)
6237 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6238 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6239 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6240 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6241 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6242 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6243 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6244 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6245 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6246 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6247 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6248 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6249 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6250 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6251 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6252 case BFD_RELOC_VTABLE_INHERIT
:
6253 case BFD_RELOC_VTABLE_ENTRY
:
6259 if (linkrelax
&& fix
->fx_addsy
6260 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
6263 return generic_force_reloc (fix
);
6267 /* NO_PSEUDO_DOT hook */
6269 /* This function has nothing to do with pseudo dots, but this is the
6270 nearest macro to where the check needs to take place. FIXME: This
6274 xtensa_check_inside_bundle ()
6276 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
6277 as_bad (_("directives are not valid inside bundles"));
6279 /* This function must always return FALSE because it is called via a
6280 macro that has nothing to do with bundling. */
6285 /* md_elf_section_change_hook */
6288 xtensa_elf_section_change_hook ()
6290 /* Set up the assembly state. */
6291 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
6292 xtensa_set_frag_assembly_state (frag_now
);
6296 /* tc_fix_adjustable hook */
6299 xtensa_fix_adjustable (fixP
)
6302 /* An offset is not allowed in combination with the difference of two
6303 symbols, but that cannot be easily detected after a local symbol
6304 has been adjusted to a (section+offset) form. Return 0 so that such
6305 an fix will not be adjusted. */
6306 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
6307 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
6310 /* We need the symbol name for the VTABLE entries. */
6311 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
6312 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6316 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || S_IS_WEAK (fixP
->fx_addsy
)))
6320 /* We may someday want to enable this code to preserve relocations for
6321 non-PC-relative fixes, possibly under control of a PIC flag. */
6322 return (fixP
->fx_pcrel
6323 || (fixP
->fx_subsy
!= NULL
6324 && (S_GET_SEGMENT (fixP
->fx_subsy
)
6325 == S_GET_SEGMENT (fixP
->fx_addsy
)))
6326 || S_IS_LOCAL (fixP
->fx_addsy
));
6334 md_apply_fix3 (fixP
, valP
, seg
)
6337 segT seg ATTRIBUTE_UNUSED
;
6339 if (fixP
->fx_pcrel
== 0 && fixP
->fx_addsy
== 0)
6341 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6343 switch (fixP
->fx_r_type
)
6345 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6349 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
6350 as_bad (_("unhandled local relocation fix %s"),
6351 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6357 /* The only one we support that isn't an instruction field. */
6358 md_number_to_chars (fixpos
, *valP
, fixP
->fx_size
);
6362 case BFD_RELOC_VTABLE_INHERIT
:
6363 case BFD_RELOC_VTABLE_ENTRY
:
6368 as_bad (_("unhandled local relocation fix %s"),
6369 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6376 md_atof (type
, litP
, sizeP
)
6382 LITTLENUM_TYPE words
[4];
6398 return "bad call to md_atof";
6401 t
= atof_ieee (input_line_pointer
, type
, words
);
6403 input_line_pointer
= t
;
6407 for (i
= prec
- 1; i
>= 0; i
--)
6410 if (target_big_endian
)
6411 idx
= (prec
- 1 - i
);
6413 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
6422 md_estimate_size_before_relax (fragP
, seg
)
6424 segT seg ATTRIBUTE_UNUSED
;
6426 return fragP
->tc_frag_data
.text_expansion
[0];
6430 /* Translate internal representation of relocation info to BFD target
6434 tc_gen_reloc (section
, fixp
)
6439 bfd_boolean apply_tentative_value
= FALSE
;
6441 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
6442 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6443 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6444 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6446 /* Make sure none of our internal relocations make it this far.
6447 They'd better have been fully resolved by this point. */
6448 assert ((int) fixp
->fx_r_type
> 0);
6450 if (linkrelax
&& fixp
->fx_subsy
6451 && (fixp
->fx_r_type
== BFD_RELOC_8
6452 || fixp
->fx_r_type
== BFD_RELOC_16
6453 || fixp
->fx_r_type
== BFD_RELOC_32
))
6456 bfd_vma diff_value
, diff_mask
= 0;
6458 switch (fixp
->fx_r_type
)
6461 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
6466 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
6471 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
6473 diff_mask
= 0xffffffff;
6479 /* An offset is only allowed when it results from adjusting a local
6480 symbol into a section-relative offset. If the offset came from the
6481 original expression, tc_fix_adjustable will have prevented the fix
6482 from being converted to a section-relative form so that we can flag
6484 if (fixp
->fx_offset
!= 0 && !symbol_section_p (fixp
->fx_addsy
))
6486 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6487 _("cannot represent subtraction with an offset"));
6488 free (reloc
->sym_ptr_ptr
);
6493 assert (S_GET_SEGMENT (fixp
->fx_addsy
)
6494 == S_GET_SEGMENT (fixp
->fx_subsy
));
6496 diff_value
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
6497 - S_GET_VALUE (fixp
->fx_subsy
));
6499 /* Check for overflow. */
6500 if ((diff_value
& ~diff_mask
) != 0)
6502 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6503 _("value of %ld too large"), diff_value
);
6504 free (reloc
->sym_ptr_ptr
);
6509 md_number_to_chars (fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
,
6510 diff_value
, diff_size
);
6511 reloc
->addend
= fixp
->fx_offset
- diff_value
;
6515 reloc
->addend
= fixp
->fx_offset
;
6517 switch (fixp
->fx_r_type
)
6519 case BFD_RELOC_XTENSA_SLOT0_OP
:
6520 case BFD_RELOC_XTENSA_SLOT1_OP
:
6521 case BFD_RELOC_XTENSA_SLOT2_OP
:
6522 case BFD_RELOC_XTENSA_SLOT3_OP
:
6523 case BFD_RELOC_XTENSA_SLOT4_OP
:
6524 case BFD_RELOC_XTENSA_SLOT5_OP
:
6525 case BFD_RELOC_XTENSA_SLOT6_OP
:
6526 case BFD_RELOC_XTENSA_SLOT7_OP
:
6527 case BFD_RELOC_XTENSA_SLOT8_OP
:
6528 case BFD_RELOC_XTENSA_SLOT9_OP
:
6529 case BFD_RELOC_XTENSA_SLOT10_OP
:
6530 case BFD_RELOC_XTENSA_SLOT11_OP
:
6531 case BFD_RELOC_XTENSA_SLOT12_OP
:
6532 case BFD_RELOC_XTENSA_SLOT13_OP
:
6533 case BFD_RELOC_XTENSA_SLOT14_OP
:
6534 /* As a special case, the immediate value for a CONST16 opcode
6535 should not be applied, since this kind of relocation is
6536 handled specially for CONST16 and is not really PC-relative.
6537 Rather than decode the opcode here, just wait and handle it
6538 in xg_apply_tentative_value. */
6539 apply_tentative_value
= TRUE
;
6542 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6543 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6544 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6545 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6546 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6547 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6548 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6549 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6550 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6551 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6552 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6553 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6554 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6555 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6556 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6557 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6559 case BFD_RELOC_XTENSA_PLT
:
6560 case BFD_RELOC_VTABLE_INHERIT
:
6561 case BFD_RELOC_VTABLE_ENTRY
:
6564 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
6565 as_warn (_("emitting simplification relocation"));
6569 as_warn (_("emitting unknown relocation"));
6573 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6574 if (reloc
->howto
== NULL
)
6576 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6577 _("cannot represent `%s' relocation in object file"),
6578 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6579 free (reloc
->sym_ptr_ptr
);
6584 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6585 as_fatal (_("internal error? cannot generate `%s' relocation"),
6586 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6588 /* Write the tentative value of a PC-relative relocation to a local symbol
6589 into the instruction. The value will be ignored by the linker, and it
6590 makes the object file disassembly readable when the linkrelax flag is
6591 set and all branch targets are encoded in relocations. */
6593 if (linkrelax
&& apply_tentative_value
&& fixp
->fx_pcrel
)
6596 assert (fixp
->fx_addsy
);
6597 if (S_GET_SEGMENT (fixp
->fx_addsy
) == section
&& !fixp
->fx_plt
6598 && !S_FORCE_RELOC (fixp
->fx_addsy
, 1))
6600 val
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
6601 - md_pcrel_from (fixp
));
6602 xg_apply_tentative_value (fixp
, val
);
6610 /* md_post_relax_hook */
6612 #define XTENSA_INSN_SEC_NAME ".xt.insn"
6613 #define XTENSA_LIT_SEC_NAME ".xt.lit"
6614 #define XTENSA_PROP_SEC_NAME ".xt.prop"
6617 xtensa_post_relax_hook ()
6619 xtensa_move_seg_list_to_beginning (literal_head
);
6620 xtensa_move_seg_list_to_beginning (init_literal_head
);
6621 xtensa_move_seg_list_to_beginning (fini_literal_head
);
6623 xtensa_find_unmarked_state_frags ();
6625 if (use_literal_section
)
6626 xtensa_create_property_segments (get_frag_is_literal
,
6628 XTENSA_LIT_SEC_NAME
,
6630 xtensa_create_xproperty_segments (get_frag_property_flags
,
6631 XTENSA_PROP_SEC_NAME
,
6634 if (warn_unaligned_branch_targets
)
6635 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
6636 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
6640 /* We have reached the end of a bundle; emit into the frag. */
6643 finish_vinsn (vinsn
)
6651 if (find_vinsn_conflicts (vinsn
))
6654 /* First, find a format that works. */
6655 if (vinsn
->format
== XTENSA_UNDEFINED
)
6656 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6658 if (vinsn
->format
== XTENSA_UNDEFINED
)
6660 as_where (&file_name
, &line
);
6661 as_bad_where (file_name
, line
,
6662 _("couldn't find a valid instruction format"));
6663 fprintf (stderr
, _(" ops were: "));
6664 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6665 fprintf (stderr
, _(" %s;"),
6666 xtensa_opcode_name (xtensa_default_isa
,
6667 vinsn
->slots
[i
].opcode
));
6668 fprintf (stderr
, _("\n"));
6669 xg_clear_vinsn (vinsn
);
6673 if (vinsn
->num_slots
6674 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6676 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6677 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6678 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6680 xg_clear_vinsn (vinsn
);
6684 if (resources_conflict (vinsn
))
6686 as_where (&file_name
, &line
);
6687 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6688 fprintf (stderr
, " ops were: ");
6689 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6690 fprintf (stderr
, " %s;",
6691 xtensa_opcode_name (xtensa_default_isa
,
6692 vinsn
->slots
[i
].opcode
));
6693 fprintf (stderr
, "\n");
6694 xg_clear_vinsn (vinsn
);
6698 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6700 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6702 symbolS
*lit_sym
= NULL
;
6704 bfd_boolean e
= FALSE
;
6705 bfd_boolean saved_density
= density_supported
;
6707 /* We don't want to narrow ops inside multi-slot bundles. */
6708 if (vinsn
->num_slots
> 1)
6709 density_supported
= FALSE
;
6711 istack_init (&slotstack
);
6712 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6714 vinsn
->slots
[i
].opcode
=
6715 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6717 vinsn
->slots
[i
].ntok
= 0;
6720 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6726 density_supported
= saved_density
;
6730 xg_clear_vinsn (vinsn
);
6734 for (j
= 0; j
< slotstack
.ninsn
- 1; j
++)
6736 TInsn
*insn
= &slotstack
.insn
[j
];
6737 if (insn
->insn_type
== ITYPE_LITERAL
)
6739 assert (lit_sym
== NULL
);
6740 lit_sym
= xg_assemble_literal (insn
);
6745 xg_resolve_literals (insn
, lit_sym
);
6746 emit_single_op (insn
);
6750 if (vinsn
->num_slots
> 1)
6752 if (opcode_fits_format_slot
6753 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6756 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6760 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6761 if (vinsn
->format
== XTENSA_UNDEFINED
)
6762 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6764 vinsn
->slots
[i
].opcode
6765 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6768 vinsn
->slots
[i
].ntok
= 0;
6773 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6774 vinsn
->format
= XTENSA_UNDEFINED
;
6779 /* Now check resource conflicts on the modified bundle. */
6780 if (resources_conflict (vinsn
))
6782 as_where (&file_name
, &line
);
6783 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6784 fprintf (stderr
, " ops were: ");
6785 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6786 fprintf (stderr
, " %s;",
6787 xtensa_opcode_name (xtensa_default_isa
,
6788 vinsn
->slots
[i
].opcode
));
6789 fprintf (stderr
, "\n");
6790 xg_clear_vinsn (vinsn
);
6794 /* First, find a format that works. */
6795 if (vinsn
->format
== XTENSA_UNDEFINED
)
6796 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6798 xg_assemble_vliw_tokens (vinsn
);
6800 xg_clear_vinsn (vinsn
);
6804 /* Given an vliw instruction, what conflicts are there in register
6805 usage and in writes to states and queues?
6807 This function does two things:
6808 1. Reports an error when a vinsn contains illegal combinations
6809 of writes to registers states or queues.
6810 2. Marks individual tinsns as not relaxable if the combination
6811 contains antidependencies.
6813 Job 2 handles things like swap semantics in instructions that need
6814 to be relaxed. For example,
6818 normally would be relaxed to
6823 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6825 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6827 then we can't relax it into
6830 { add a0, a1, a0 ; add a2, a0, a4 ; }
6832 because the value of a0 is trashed before the second add can read it. */
6835 find_vinsn_conflicts (vinsn
)
6840 xtensa_isa isa
= xtensa_default_isa
;
6842 assert (!past_xtensa_end
);
6844 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6846 TInsn
*op1
= &vinsn
->slots
[i
];
6847 if (op1
->is_specific_opcode
)
6848 op1
->keep_wide
= TRUE
;
6850 op1
->keep_wide
= FALSE
;
6853 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6855 TInsn
*op1
= &vinsn
->slots
[i
];
6857 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6860 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6864 TInsn
*op2
= &vinsn
->slots
[j
];
6865 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6866 switch (conflict_type
)
6869 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6870 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6871 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6874 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6875 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6876 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6879 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6880 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6881 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6884 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6885 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6886 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6889 /* Everything is OK. */
6892 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6893 || conflict_type
== 'a');
6900 as_bad (_("multiple branches or jumps in the same bundle"));
6908 /* Check how the result registers of t1 and t2 relate.
6911 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6912 case B: no relationship between what is read and written (both could
6913 read the same reg though)
6914 case C: t1 writes a register t2 writes (a register conflict within a
6916 case D: t1 writes a state that t2 also writes
6917 case E: t1 writes a tie queue that t2 also writes
6918 case F: two volatile queue writes
6922 check_t1_t2_reads_and_writes (t1
, t2
)
6926 xtensa_isa isa
= xtensa_default_isa
;
6927 xtensa_regfile t1_regfile
, t2_regfile
;
6929 int t1_base_reg
, t1_last_reg
;
6930 int t2_base_reg
, t2_last_reg
;
6931 char t1_inout
, t2_inout
;
6933 char conflict
= 'b';
6938 bfd_boolean t1_volatile
= FALSE
;
6939 bfd_boolean t2_volatile
= FALSE
;
6941 /* Check registers. */
6942 for (j
= 0; j
< t2
->ntok
; j
++)
6944 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6947 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6948 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6949 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6951 for (i
= 0; i
< t1
->ntok
; i
++)
6953 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6956 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6958 if (t1_regfile
!= t2_regfile
)
6961 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6962 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6964 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6965 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6967 if (t1_inout
== 'm' || t1_inout
== 'o'
6968 || t2_inout
== 'm' || t2_inout
== 'o')
6975 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6976 t1_last_reg
= (t1_base_reg
6977 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6979 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6981 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6983 if (t1_reg
!= t2_reg
)
6986 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6992 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6998 if (t1_inout
!= 'i' && t2_inout
!= 'i')
7006 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
7007 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
7008 for (j
= 0; j
< t2_states
; j
++)
7010 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
7011 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
7012 for (i
= 0; i
< t1_states
; i
++)
7014 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
7015 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
7019 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
7025 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
7031 if (t1_inout
!= 'i' && t2_inout
!= 'i')
7036 /* Check tieports. */
7037 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
7038 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
7039 for (j
= 0; j
< t2_interfaces
; j
++)
7041 xtensa_interface t2_int
7042 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
7043 t2_inout
= xtensa_interface_inout (isa
, j
);
7044 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1
7047 for (i
= 0; i
< t1_interfaces
; i
++)
7049 xtensa_interface t1_int
7050 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
7051 t1_inout
= xtensa_interface_inout (isa
, i
);
7052 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1
7056 if (t1_int
!= t2_int
)
7059 if (t2_inout
== 'i' && t1_inout
== 'o')
7065 if (t1_inout
== 'i' && t2_inout
== 'o')
7071 if (t1_inout
!= 'i' && t2_inout
!= 'i')
7076 if (t1_volatile
&& t2_volatile
)
7083 /* The func unit stuff could be implemented as bit-vectors rather
7084 than the iterative approach here. If it ends up being too
7085 slow, we will switch it. */
7088 new_resource_table (data
, cycles
, nu
, uncf
, onuf
, ouuf
, ousf
)
7092 unit_num_copies_func uncf
;
7093 opcode_num_units_func onuf
;
7094 opcode_funcUnit_use_unit_func ouuf
;
7095 opcode_funcUnit_use_stage_func ousf
;
7098 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
7100 rt
->cycles
= cycles
;
7101 rt
->allocated_cycles
= cycles
;
7103 rt
->unit_num_copies
= uncf
;
7104 rt
->opcode_num_units
= onuf
;
7105 rt
->opcode_unit_use
= ouuf
;
7106 rt
->opcode_unit_stage
= ousf
;
7108 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
7109 for (i
= 0; i
< cycles
; i
++)
7110 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
7117 clear_resource_table (rt
)
7121 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
7122 for (j
= 0; j
< rt
->num_units
; j
++)
7123 rt
->units
[i
][j
] = 0;
7127 /* We never shrink it, just fake it into thinking so. */
7130 resize_resource_table (rt
, cycles
)
7136 rt
->cycles
= cycles
;
7137 if (cycles
<= rt
->allocated_cycles
)
7140 old_cycles
= rt
->allocated_cycles
;
7141 rt
->allocated_cycles
= cycles
;
7143 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
7144 for (i
= 0; i
< old_cycles
; i
++)
7145 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
7146 for (i
= old_cycles
; i
< cycles
; i
++)
7147 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
7152 resources_available (rt
, opcode
, cycle
)
7154 xtensa_opcode opcode
;
7158 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
7160 for (i
= 0; i
< uses
; i
++)
7162 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
7163 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
7164 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
7165 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
7166 if (copies_in_use
>= copies
)
7174 reserve_resources (rt
, opcode
, cycle
)
7176 xtensa_opcode opcode
;
7180 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
7182 for (i
= 0; i
< uses
; i
++)
7184 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
7185 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
7186 /* Note that this allows resources to be oversubscribed. That's
7187 essential to the way the optional scheduler works.
7188 resources_available reports when a resource is over-subscribed,
7189 so it's easy to tell. */
7190 rt
->units
[stage
+ cycle
][unit
]++;
7196 release_resources (rt
, opcode
, cycle
)
7198 xtensa_opcode opcode
;
7202 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
7204 for (i
= 0; i
< uses
; i
++)
7206 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
7207 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
7208 rt
->units
[stage
+ cycle
][unit
]--;
7209 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
7214 /* Wrapper functions make parameterized resource reservation
7218 opcode_funcUnit_use_unit (data
, opcode
, idx
)
7220 xtensa_opcode opcode
;
7223 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
7229 opcode_funcUnit_use_stage (data
, opcode
, idx
)
7231 xtensa_opcode opcode
;
7234 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
7239 /* Note that this function does not check issue constraints, but
7240 solely whether the hardware is available to execute the given
7241 instructions together. It also doesn't check if the tinsns
7242 write the same state, or access the same tieports. That is
7243 checked by check_t1_t2_read_write. */
7246 resources_conflict (vinsn
)
7250 static resource_table
*rt
= NULL
;
7252 /* This is the most common case by far. Optimize it. */
7253 if (vinsn
->num_slots
== 1)
7258 xtensa_isa isa
= xtensa_default_isa
;
7259 rt
= new_resource_table
7260 (isa
, xtensa_isa_num_pipe_stages (isa
),
7261 xtensa_isa_num_funcUnits (isa
),
7262 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
7263 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
7264 opcode_funcUnit_use_unit
,
7265 opcode_funcUnit_use_stage
);
7268 clear_resource_table (rt
);
7270 for (i
= 0; i
< vinsn
->num_slots
; i
++)
7272 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
7274 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
7281 static xtensa_format
7282 xg_find_narrowest_format (vinsn
)
7285 /* Right now we assume that the ops within the vinsn are properly
7286 ordered for the slots that the programmer wanted them in. In
7287 other words, we don't rearrange the ops in hopes of finding a
7288 better format. The scheduler handles that. */
7290 xtensa_isa isa
= xtensa_default_isa
;
7291 xtensa_format format
;
7292 vliw_insn v_copy
= *vinsn
;
7293 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
7295 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
7298 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
7302 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
7304 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
7306 v_copy
.slots
[slot
].opcode
=
7307 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
7308 v_copy
.slots
[slot
].ntok
= 0;
7311 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
7316 if (v_copy
.num_slots
> 1)
7319 /* Try the widened version. */
7320 if (!v_copy
.slots
[slot
].keep_wide
7321 && !v_copy
.slots
[slot
].is_specific_opcode
7322 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
7323 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
7324 && opcode_fits_format_slot (widened
.opcode
,
7327 /* The xg_is_narrow clause requires some explanation:
7329 addi can be "widened" to an addmi, which is then
7330 expanded to an addmi/addi pair if the immediate
7331 requires it, but here we must have a single widen
7334 xg_is_narrow tells us that addi isn't really
7335 narrow. The widen_spec_list says that there are
7338 v_copy
.slots
[slot
] = widened
;
7344 if (fit
== v_copy
.num_slots
)
7347 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
7348 vinsn
->format
= format
;
7354 if (format
== xtensa_isa_num_formats (isa
))
7355 return XTENSA_UNDEFINED
;
7361 /* Return the additional space needed in a frag
7362 for possible relaxations of any ops in a VLIW insn.
7363 Also fill out the relaxations that might be required of
7364 each tinsn in the vinsn. */
7367 relaxation_requirements (vinsn
)
7370 int extra_space
= 0;
7373 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7375 TInsn
*tinsn
= &vinsn
->slots
[slot
];
7376 if (!tinsn_has_symbolic_operands (tinsn
))
7378 /* A narrow instruction could be widened later to help
7379 alignment issues. */
7380 if (xg_is_narrow_insn (tinsn
)
7381 && !tinsn
->is_specific_opcode
7382 && vinsn
->num_slots
== 1)
7384 /* Difference in bytes between narrow and wide insns... */
7386 tinsn
->subtype
= RELAX_NARROW
;
7387 tinsn
->record_fix
= TRUE
;
7392 tinsn
->record_fix
= FALSE
;
7393 /* No extra_space needed. */
7398 if (workaround_b_j_loop_end
&& is_jx_opcode (tinsn
->opcode
)
7399 && use_transform ())
7401 /* Add 2 of these. */
7402 extra_space
+= 3; /* for the nop size */
7403 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
7406 /* Need to assemble it with space for the relocation. */
7407 if (xg_is_relaxable_insn (tinsn
, 0)
7408 && !tinsn
->is_specific_opcode
)
7410 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
7411 int max_literal_size
=
7412 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
7414 tinsn
->literal_space
= max_literal_size
;
7416 tinsn
->subtype
= RELAX_IMMED
;
7417 tinsn
->record_fix
= FALSE
;
7418 extra_space
+= max_size
;
7422 tinsn
->record_fix
= TRUE
;
7423 /* No extra space needed. */
7432 bundle_single_op (orig_insn
)
7435 xtensa_isa isa
= xtensa_default_isa
;
7440 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
7441 assert (v
.format
!= XTENSA_UNDEFINED
);
7442 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
7445 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
7448 v
.slots
[slot
].opcode
=
7449 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
7450 v
.slots
[slot
].ntok
= 0;
7451 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
7454 v
.slots
[slot
] = *orig_insn
;
7457 for ( ; slot
< v
.num_slots
; slot
++)
7459 v
.slots
[slot
].opcode
=
7460 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
7461 v
.slots
[slot
].ntok
= 0;
7462 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
7471 emit_single_op (orig_insn
)
7475 IStack istack
; /* put instructions into here */
7476 symbolS
*lit_sym
= NULL
;
7477 symbolS
*label_sym
= NULL
;
7479 istack_init (&istack
);
7481 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
7482 Because the scheduling and bundling characteristics of movi and
7483 l32r or const16 are so different, we can do much better if we relax
7484 it prior to scheduling and bundling, rather than after. */
7485 if (is_movi_opcode (orig_insn
->opcode
) && !cur_vinsn
.inside_bundle
7486 && (orig_insn
->tok
[1].X_op
== O_symbol
7487 || orig_insn
->tok
[1].X_op
== O_pltrel
))
7488 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
7490 if (xg_expand_assembly_insn (&istack
, orig_insn
))
7493 for (i
= 0; i
< istack
.ninsn
; i
++)
7495 TInsn
*insn
= &istack
.insn
[i
];
7496 switch (insn
->insn_type
)
7499 assert (lit_sym
== NULL
);
7500 lit_sym
= xg_assemble_literal (insn
);
7504 static int relaxed_sym_idx
= 0;
7505 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
7506 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
7508 assert (label_sym
== NULL
);
7509 label_sym
= symbol_find_or_make (label
);
7516 xg_resolve_literals (insn
, lit_sym
);
7518 xg_resolve_labels (insn
, label_sym
);
7519 bundle_single_op (insn
);
7530 /* Emit a vliw instruction to the current fragment. */
7533 xg_assemble_vliw_tokens (vinsn
)
7536 bfd_boolean finish_frag
= FALSE
;
7537 bfd_boolean is_jump
= FALSE
;
7538 bfd_boolean is_branch
= FALSE
;
7539 xtensa_isa isa
= xtensa_default_isa
;
7545 struct dwarf2_line_info best_loc
;
7547 best_loc
.line
= INT_MAX
;
7549 if (generating_literals
)
7551 static int reported
= 0;
7553 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7554 _("cannot assemble into a literal fragment"));
7561 if (frag_now_fix () != 0
7562 && (!get_frag_is_insn (frag_now
)
7563 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7564 || !use_transform () != get_frag_is_no_transform (frag_now
)
7565 || (directive_state
[directive_absolute_literals
]
7566 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7568 frag_wane (frag_now
);
7570 xtensa_set_frag_assembly_state (frag_now
);
7573 if (workaround_a0_b_retw
7574 && vinsn
->num_slots
== 1
7575 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7576 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7577 && use_transform ())
7579 has_a0_b_retw
= TRUE
;
7581 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7582 After the first assembly pass we will check all of them and
7583 add a nop if needed. */
7584 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7585 frag_var (rs_machine_dependent
, 4, 4,
7586 RELAX_ADD_NOP_IF_A0_B_RETW
,
7587 frag_now
->fr_symbol
,
7588 frag_now
->fr_offset
,
7590 xtensa_set_frag_assembly_state (frag_now
);
7591 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7592 frag_var (rs_machine_dependent
, 4, 4,
7593 RELAX_ADD_NOP_IF_A0_B_RETW
,
7594 frag_now
->fr_symbol
,
7595 frag_now
->fr_offset
,
7597 xtensa_set_frag_assembly_state (frag_now
);
7600 for (i
= 0; i
< vinsn
->num_slots
; i
++)
7602 /* See if the instruction implies an aligned section. */
7603 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
7604 record_alignment (now_seg
, 2);
7606 /* Also determine the best line number for debug info. */
7607 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
7608 ? vinsn
->slots
[i
].loc
: best_loc
;
7611 /* Special cases for instructions that force an alignment... */
7612 /* None of these opcodes are bundle-able. */
7613 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7617 xtensa_set_frag_assembly_state (frag_now
);
7618 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7620 max_fill
= get_text_align_max_fill_size
7621 (get_text_align_power (xtensa_fetch_width
),
7622 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7624 if (use_transform ())
7625 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7626 RELAX_ALIGN_NEXT_OPCODE
,
7627 frag_now
->fr_symbol
,
7628 frag_now
->fr_offset
,
7631 frag_var (rs_machine_dependent
, 0, 0,
7632 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
7633 xtensa_set_frag_assembly_state (frag_now
);
7635 xtensa_move_labels (frag_now
, 0, FALSE
);
7638 if (is_entry_opcode (vinsn
->slots
[0].opcode
)
7639 && !vinsn
->slots
[0].is_specific_opcode
)
7641 xtensa_mark_literal_pool_location ();
7642 xtensa_move_labels (frag_now
, 0, TRUE
);
7643 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7646 if (vinsn
->num_slots
== 1)
7648 if (workaround_a0_b_retw
&& use_transform ())
7649 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7650 is_register_writer (&vinsn
->slots
[0], "a", 0));
7652 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7653 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7656 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7658 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7660 extra_space
= relaxation_requirements (vinsn
);
7662 /* vinsn_to_insnbuf will produce the error. */
7663 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7665 f
= (char *) frag_more (insn_size
+ extra_space
);
7666 xtensa_set_frag_assembly_state (frag_now
);
7667 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7670 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
7671 if (vinsn
->format
== XTENSA_UNDEFINED
)
7674 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
7676 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
7678 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7680 TInsn
*tinsn
= &vinsn
->slots
[slot
];
7681 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7682 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7683 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
7684 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7685 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7686 if (tinsn
->literal_space
!= 0)
7687 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7689 if (tinsn
->subtype
== RELAX_NARROW
)
7690 assert (vinsn
->num_slots
== 1);
7691 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7693 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7696 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
7697 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
7701 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7702 set_frag_is_specific_opcode (frag_now
, TRUE
);
7706 frag_variant (rs_machine_dependent
,
7707 extra_space
, extra_space
, RELAX_SLOTS
,
7708 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7709 xtensa_set_frag_assembly_state (frag_now
);
7712 /* Special cases for loops:
7713 close_loop_end should be inserted AFTER short_loop.
7714 Make sure that CLOSE loops are processed BEFORE short_loops
7715 when converting them. */
7717 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7718 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
7719 && !vinsn
->slots
[0].is_specific_opcode
)
7721 if (workaround_short_loop
&& use_transform ())
7723 maybe_has_short_loop
= TRUE
;
7724 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7725 frag_var (rs_machine_dependent
, 4, 4,
7726 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7727 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7728 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7729 frag_var (rs_machine_dependent
, 4, 4,
7730 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7731 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7734 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7735 loop at least 12 bytes away from another loop's end. */
7736 if (workaround_close_loop_end
&& use_transform ())
7738 maybe_has_close_loop_end
= TRUE
;
7739 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7740 frag_var (rs_machine_dependent
, 12, 12,
7741 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7742 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7746 if (use_transform ())
7750 assert (finish_frag
);
7751 frag_var (rs_machine_dependent
,
7752 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7754 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7755 xtensa_set_frag_assembly_state (frag_now
);
7757 else if (is_branch
&& align_targets
)
7759 assert (finish_frag
);
7760 frag_var (rs_machine_dependent
,
7761 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7762 RELAX_MAYBE_UNREACHABLE
,
7763 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7764 xtensa_set_frag_assembly_state (frag_now
);
7765 frag_var (rs_machine_dependent
,
7767 RELAX_MAYBE_DESIRE_ALIGN
,
7768 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7769 xtensa_set_frag_assembly_state (frag_now
);
7773 /* Now, if the original opcode was a call... */
7774 if (do_align_targets ()
7775 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7777 float freq
= get_subseg_info (now_seg
, now_subseg
)->cur_total_freq
;
7778 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7779 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7780 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7781 xtensa_set_frag_assembly_state (frag_now
);
7784 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7786 frag_wane (frag_now
);
7788 xtensa_set_frag_assembly_state (frag_now
);
7796 directive_balance ();
7797 xtensa_flush_pending_output ();
7799 past_xtensa_end
= TRUE
;
7801 xtensa_move_literals ();
7803 xtensa_reorder_segments ();
7804 xtensa_cleanup_align_frags ();
7805 xtensa_fix_target_frags ();
7806 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7807 xtensa_fix_a0_b_retw_frags ();
7808 if (workaround_b_j_loop_end
)
7809 xtensa_fix_b_j_loop_end_frags ();
7811 /* "close_loop_end" should be processed BEFORE "short_loop". */
7812 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7813 xtensa_fix_close_loop_end_frags ();
7815 if (workaround_short_loop
&& maybe_has_short_loop
)
7816 xtensa_fix_short_loop_frags ();
7817 xtensa_mark_narrow_branches ();
7818 xtensa_mark_zcl_first_insns ();
7820 xtensa_sanity_check ();
7825 xtensa_cleanup_align_frags ()
7829 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7832 /* Walk over all of the fragments in a subsection. */
7833 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7835 if ((fragP
->fr_type
== rs_align
7836 || fragP
->fr_type
== rs_align_code
7837 || (fragP
->fr_type
== rs_machine_dependent
7838 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7839 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7840 && fragP
->fr_fix
== 0)
7842 fragS
*next
= fragP
->fr_next
;
7845 && next
->fr_fix
== 0
7846 && next
->fr_type
== rs_machine_dependent
7847 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7850 next
= next
->fr_next
;
7853 /* If we don't widen branch targets, then they
7854 will be easier to align. */
7855 if (fragP
->tc_frag_data
.is_branch_target
7856 && fragP
->fr_opcode
== fragP
->fr_literal
7857 && fragP
->fr_type
== rs_machine_dependent
7858 && fragP
->fr_subtype
== RELAX_SLOTS
7859 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7861 if (fragP
->fr_type
== rs_machine_dependent
7862 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7863 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7869 /* Re-process all of the fragments looking to convert all of the
7870 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7871 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7872 If the next fragment starts with a loop target, AND the previous
7873 fragment can be expanded to negate the branch, convert this to a
7874 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7877 xtensa_fix_target_frags ()
7881 /* When this routine is called, all of the subsections are still intact
7882 so we walk over subsections instead of sections. */
7883 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7885 bfd_boolean prev_frag_can_negate_branch
= FALSE
;
7888 /* Walk over all of the fragments in a subsection. */
7889 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7891 if (fragP
->fr_type
== rs_machine_dependent
7892 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7894 if (next_frag_is_loop_target (fragP
))
7896 if (prev_frag_can_negate_branch
)
7898 fragP
->fr_subtype
= RELAX_LOOP_END
;
7899 /* See the comment near the frag_var with a
7900 RELAX_DESIRE_ALIGN to see why we do this. */
7901 fragP
->fr_var
= RELAX_LOOP_END_BYTES
;
7905 if (next_frag_is_branch_target (fragP
))
7906 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7911 else if (next_frag_is_branch_target (fragP
))
7912 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7916 if (fragP
->fr_fix
!= 0)
7917 prev_frag_can_negate_branch
= FALSE
;
7918 if (frag_can_negate_branch (fragP
))
7919 prev_frag_can_negate_branch
= TRUE
;
7926 frag_can_negate_branch (fragP
)
7929 xtensa_isa isa
= xtensa_default_isa
;
7933 if (fragP
->fr_type
!= rs_machine_dependent
7934 || fragP
->fr_subtype
!= RELAX_SLOTS
)
7937 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7939 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, vinsn
.format
); slot
++)
7941 if ((fragP
->tc_frag_data
.slot_subtypes
[slot
] == RELAX_IMMED
)
7942 && xtensa_opcode_is_branch (isa
, vinsn
.slots
[slot
].opcode
) == 1)
7951 xtensa_mark_narrow_branches ()
7955 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7958 /* Walk over all of the fragments in a subsection. */
7959 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7961 if (fragP
->fr_type
== rs_machine_dependent
7962 && fragP
->fr_subtype
== RELAX_SLOTS
7963 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7966 const expressionS
*expr
;
7969 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7970 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7972 expr
= &vinsn
.slots
[0].tok
[1];
7973 symbolP
= expr
->X_add_symbol
;
7975 if (vinsn
.num_slots
== 1
7976 && xtensa_opcode_is_branch (xtensa_default_isa
,
7977 vinsn
.slots
[0].opcode
)
7978 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7979 && is_narrow_branch_guaranteed_in_range (fragP
,
7982 fragP
->fr_subtype
= RELAX_SLOTS
;
7983 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7991 /* A branch is typically widened only when its target is out of
7992 range. However, we would like to widen them to align a subsequent
7993 branch target when possible.
7995 Because the branch relaxation code is so convoluted, the optimal solution
7996 (combining the two cases) is difficult to get right in all circumstances.
7997 We therefore go with an "almost as good" solution, where we only
7998 use for alignment narrow branches that definitely will not expand to a
7999 jump and a branch. These functions find and mark these cases. */
8001 /* the range in bytes of a bnez.n and beqz.n */
8002 #define MAX_IMMED6 68
8005 is_narrow_branch_guaranteed_in_range (fragP
, tinsn
)
8009 const expressionS
*expr
= &tinsn
->tok
[1];
8010 symbolS
*symbolP
= expr
->X_add_symbol
;
8011 fragS
*target_frag
= symbol_get_frag (symbolP
);
8012 size_t max_distance
= expr
->X_add_number
;
8013 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
8014 if (is_branch_jmp_to_next (tinsn
, fragP
))
8017 /* The branch doesn't branch over it's own frag,
8018 but over the subsequent ones. */
8019 fragP
= fragP
->fr_next
;
8020 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
8022 max_distance
+= unrelaxed_frag_max_size (fragP
);
8023 fragP
= fragP
->fr_next
;
8025 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
8032 xtensa_mark_zcl_first_insns ()
8036 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8039 /* Walk over all of the fragments in a subsection. */
8040 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8042 if (fragP
->fr_type
== rs_machine_dependent
8043 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8044 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8046 /* Find the loop frag. */
8047 fragS
*targ_frag
= next_non_empty_frag (fragP
);
8048 /* Find the first insn frag. */
8049 targ_frag
= next_non_empty_frag (targ_frag
);
8051 /* Of course, sometimes (mostly for toy test cases) a
8052 zero-cost loop instruction is the last in a section. */
8055 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
8056 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
8065 /* Re-process all of the fragments looking to convert all of the
8066 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8067 conditional branch or a retw/retw.n, convert this frag to one that
8068 will generate a NOP. In any case close it off with a .fill 0. */
8071 xtensa_fix_a0_b_retw_frags ()
8075 /* When this routine is called, all of the subsections are still intact
8076 so we walk over subsections instead of sections. */
8077 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8081 /* Walk over all of the fragments in a subsection. */
8082 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8084 if (fragP
->fr_type
== rs_machine_dependent
8085 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
8087 if (next_instrs_are_b_retw (fragP
))
8089 if (get_frag_is_no_transform (fragP
))
8090 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8092 relax_frag_add_nop (fragP
);
8102 next_instrs_are_b_retw (fragP
)
8105 xtensa_opcode opcode
;
8107 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8108 static xtensa_insnbuf insnbuf
= NULL
;
8109 static xtensa_insnbuf slotbuf
= NULL
;
8110 xtensa_isa isa
= xtensa_default_isa
;
8113 bfd_boolean branch_seen
= FALSE
;
8117 insnbuf
= xtensa_insnbuf_alloc (isa
);
8118 slotbuf
= xtensa_insnbuf_alloc (isa
);
8121 if (next_fragP
== NULL
)
8124 /* Check for the conditional branch. */
8125 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
8126 fmt
= xtensa_format_decode (isa
, insnbuf
);
8127 if (fmt
== XTENSA_UNDEFINED
)
8130 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8132 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8133 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8135 branch_seen
= (branch_seen
8136 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8142 offset
+= xtensa_format_length (isa
, fmt
);
8143 if (offset
== next_fragP
->fr_fix
)
8145 next_fragP
= next_non_empty_frag (next_fragP
);
8149 if (next_fragP
== NULL
)
8152 /* Check for the retw/retw.n. */
8153 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
8154 fmt
= xtensa_format_decode (isa
, insnbuf
);
8156 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8157 have no problems. */
8158 if (fmt
== XTENSA_UNDEFINED
8159 || xtensa_format_num_slots (isa
, fmt
) != 1)
8162 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8163 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8165 if (is_windowed_return_opcode (opcode
))
8172 /* Re-process all of the fragments looking to convert all of the
8173 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8174 loop end label, convert this frag to one that will generate a NOP.
8175 In any case close it off with a .fill 0. */
8178 xtensa_fix_b_j_loop_end_frags ()
8182 /* When this routine is called, all of the subsections are still intact
8183 so we walk over subsections instead of sections. */
8184 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8188 /* Walk over all of the fragments in a subsection. */
8189 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8191 if (fragP
->fr_type
== rs_machine_dependent
8192 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8194 if (next_instr_is_loop_end (fragP
))
8196 if (get_frag_is_no_transform (fragP
))
8197 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8199 relax_frag_add_nop (fragP
);
8209 next_instr_is_loop_end (fragP
)
8212 const fragS
*next_fragP
;
8214 if (next_frag_is_loop_target (fragP
))
8217 next_fragP
= next_non_empty_frag (fragP
);
8218 if (next_fragP
== NULL
)
8221 if (!next_frag_is_loop_target (next_fragP
))
8224 /* If the size is >= 3 then there is more than one instruction here.
8225 The hardware bug will not fire. */
8226 if (next_fragP
->fr_fix
> 3)
8233 /* Re-process all of the fragments looking to convert all of the
8234 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8235 not MY loop's loop end within 12 bytes, add enough nops here to
8236 make it at least 12 bytes away. In any case close it off with a
8240 xtensa_fix_close_loop_end_frags ()
8244 /* When this routine is called, all of the subsections are still intact
8245 so we walk over subsections instead of sections. */
8246 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8250 fragS
*current_target
= NULL
;
8251 offsetT current_offset
= 0;
8253 /* Walk over all of the fragments in a subsection. */
8254 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8256 if (fragP
->fr_type
== rs_machine_dependent
8257 && ((fragP
->fr_subtype
== RELAX_IMMED
)
8258 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
8259 && (fragP
->tc_frag_data
.slot_subtypes
[0]
8262 /* Read it. If the instruction is a loop, get the target. */
8264 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8265 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8266 t_insn
.opcode
) == 1)
8268 /* Get the current fragment target. */
8269 if (fragP
->tc_frag_data
.slot_symbols
[0])
8271 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
8272 current_target
= symbol_get_frag (sym
);
8273 current_offset
= fragP
->fr_offset
;
8279 && fragP
->fr_type
== rs_machine_dependent
8280 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8283 size_t bytes_added
= 0;
8285 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8286 /* Max out at 12. */
8287 min_bytes
= min_bytes_to_other_loop_end
8288 (fragP
->fr_next
, current_target
, current_offset
,
8289 REQUIRED_LOOP_DIVIDING_BYTES
);
8291 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8293 if (get_frag_is_no_transform (fragP
))
8294 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8297 while (min_bytes
+ bytes_added
8298 < REQUIRED_LOOP_DIVIDING_BYTES
)
8302 if (fragP
->fr_var
< length
)
8303 as_fatal (_("fr_var %lu < length %d"),
8304 fragP
->fr_var
, length
);
8307 assemble_nop (length
,
8308 fragP
->fr_literal
+ fragP
->fr_fix
);
8309 fragP
->fr_fix
+= length
;
8310 fragP
->fr_var
-= length
;
8312 bytes_added
+= length
;
8318 assert (fragP
->fr_type
!= rs_machine_dependent
8319 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8326 min_bytes_to_other_loop_end (fragP
, current_target
, current_offset
, max_size
)
8328 fragS
*current_target
;
8329 offsetT current_offset
;
8333 fragS
*current_fragP
;
8335 for (current_fragP
= fragP
;
8337 current_fragP
= current_fragP
->fr_next
)
8339 if (current_fragP
->tc_frag_data
.is_loop_target
8340 && current_fragP
!= current_target
)
8341 return offset
+ current_offset
;
8343 offset
+= unrelaxed_frag_min_size (current_fragP
);
8345 if (offset
+ current_offset
>= max_size
)
8353 unrelaxed_frag_min_size (fragP
)
8356 size_t size
= fragP
->fr_fix
;
8359 if (fragP
->fr_type
== rs_fill
)
8360 size
+= fragP
->fr_offset
;
8367 unrelaxed_frag_max_size (fragP
)
8370 size_t size
= fragP
->fr_fix
;
8371 switch (fragP
->fr_type
)
8374 /* Empty frags created by the obstack allocation scheme
8375 end up with type 0. */
8380 size
+= fragP
->fr_offset
;
8388 /* No further adjustments needed. */
8390 case rs_machine_dependent
:
8391 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8392 size
+= fragP
->fr_var
;
8395 /* We had darn well better know how big it is. */
8404 /* Re-process all of the fragments looking to convert all
8405 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8408 1) the instruction size count to the loop end label
8409 is too short (<= 2 instructions),
8410 2) loop has a jump or branch in it
8413 1) workaround_all_short_loops is TRUE
8414 2) The generating loop was a 'loopgtz' or 'loopnez'
8415 3) the instruction size count to the loop end label is too short
8417 then convert this frag (and maybe the next one) to generate a NOP.
8418 In any case close it off with a .fill 0. */
8421 xtensa_fix_short_loop_frags ()
8425 /* When this routine is called, all of the subsections are still intact
8426 so we walk over subsections instead of sections. */
8427 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8430 fragS
*current_target
= NULL
;
8431 offsetT current_offset
= 0;
8432 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8434 /* Walk over all of the fragments in a subsection. */
8435 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8437 /* Check on the current loop. */
8438 if (fragP
->fr_type
== rs_machine_dependent
8439 && ((fragP
->fr_subtype
== RELAX_IMMED
)
8440 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
8441 && (fragP
->tc_frag_data
.slot_subtypes
[0]
8446 /* Read it. If the instruction is a loop, get the target. */
8447 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8448 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8449 t_insn
.opcode
) == 1)
8451 /* Get the current fragment target. */
8452 if (fragP
->tc_frag_data
.slot_symbols
[0])
8454 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
8455 current_target
= symbol_get_frag (sym
);
8456 current_offset
= fragP
->fr_offset
;
8457 current_opcode
= t_insn
.opcode
;
8462 if (fragP
->fr_type
== rs_machine_dependent
8463 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8466 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
8468 && (branch_before_loop_end (fragP
->fr_next
)
8469 || (workaround_all_short_loops
8470 && current_opcode
!= XTENSA_UNDEFINED
8471 && !is_the_loop_opcode (current_opcode
))))
8473 if (get_frag_is_no_transform (fragP
))
8474 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8476 relax_frag_add_nop (fragP
);
8486 count_insns_to_loop_end (base_fragP
, count_relax_add
, max_count
)
8488 bfd_boolean count_relax_add
;
8491 fragS
*fragP
= NULL
;
8492 size_t insn_count
= 0;
8496 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8498 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8499 if (insn_count
>= max_count
)
8502 if (count_relax_add
)
8504 if (fragP
->fr_type
== rs_machine_dependent
8505 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8507 /* In order to add the appropriate number of
8508 NOPs, we count an instruction for downstream
8511 if (insn_count
>= max_count
)
8521 unrelaxed_frag_min_insn_count (fragP
)
8524 xtensa_isa isa
= xtensa_default_isa
;
8525 static xtensa_insnbuf insnbuf
= NULL
;
8526 size_t insn_count
= 0;
8529 if (!fragP
->tc_frag_data
.is_insn
)
8533 insnbuf
= xtensa_insnbuf_alloc (isa
);
8535 /* Decode the fixed instructions. */
8536 while (offset
< fragP
->fr_fix
)
8540 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
8541 fmt
= xtensa_format_decode (isa
, insnbuf
);
8543 if (fmt
== XTENSA_UNDEFINED
)
8545 as_fatal (_("undecodable instruction in instruction frag"));
8548 offset
+= xtensa_format_length (isa
, fmt
);
8557 branch_before_loop_end (base_fragP
)
8562 for (fragP
= base_fragP
;
8563 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8564 fragP
= fragP
->fr_next
)
8566 if (unrelaxed_frag_has_b_j (fragP
))
8574 unrelaxed_frag_has_b_j (fragP
)
8577 static xtensa_insnbuf insnbuf
= NULL
;
8578 xtensa_isa isa
= xtensa_default_isa
;
8581 if (!fragP
->tc_frag_data
.is_insn
)
8585 insnbuf
= xtensa_insnbuf_alloc (isa
);
8587 /* Decode the fixed instructions. */
8588 while (offset
< fragP
->fr_fix
)
8593 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
8594 fmt
= xtensa_format_decode (isa
, insnbuf
);
8595 if (fmt
== XTENSA_UNDEFINED
)
8598 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8600 xtensa_opcode opcode
=
8601 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8602 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8603 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8606 offset
+= xtensa_format_length (isa
, fmt
);
8612 /* Checks to be made after initial assembly but before relaxation. */
8615 xtensa_sanity_check ()
8622 as_where (&file_name
, &line
);
8623 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
8627 /* Walk over all of the fragments in a subsection. */
8628 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8630 /* Currently we only check for empty loops here. */
8631 if (fragP
->fr_type
== rs_machine_dependent
8632 && fragP
->fr_subtype
== RELAX_IMMED
)
8634 static xtensa_insnbuf insnbuf
= NULL
;
8637 if (fragP
->fr_opcode
!= NULL
)
8640 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8641 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8642 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8644 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8645 t_insn
.opcode
) == 1)
8647 if (is_empty_loop (&t_insn
, fragP
))
8649 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8650 as_bad (_("invalid empty loop"));
8652 if (!is_local_forward_loop (&t_insn
, fragP
))
8654 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8655 as_bad (_("loop target does not follow "
8656 "loop instruction in section"));
8663 new_logical_line (file_name
, line
);
8667 #define LOOP_IMMED_OPN 1
8669 /* Return TRUE if the loop target is the next non-zero fragment. */
8672 is_empty_loop (insn
, fragP
)
8676 const expressionS
*expr
;
8680 if (insn
->insn_type
!= ITYPE_INSN
)
8683 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8686 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8689 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8691 if (expr
->X_op
!= O_symbol
)
8694 symbolP
= expr
->X_add_symbol
;
8698 if (symbol_get_frag (symbolP
) == NULL
)
8701 if (S_GET_VALUE (symbolP
) != 0)
8704 /* Walk through the zero-size fragments from this one. If we find
8705 the target fragment, then this is a zero-size loop. */
8707 for (next_fragP
= fragP
->fr_next
;
8709 next_fragP
= next_fragP
->fr_next
)
8711 if (next_fragP
== symbol_get_frag (symbolP
))
8713 if (next_fragP
->fr_fix
!= 0)
8721 is_local_forward_loop (insn
, fragP
)
8725 const expressionS
*expr
;
8729 if (insn
->insn_type
!= ITYPE_INSN
)
8732 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
8735 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8738 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8740 if (expr
->X_op
!= O_symbol
)
8743 symbolP
= expr
->X_add_symbol
;
8747 if (symbol_get_frag (symbolP
) == NULL
)
8750 /* Walk through fragments until we find the target.
8751 If we do not find the target, then this is an invalid loop. */
8753 for (next_fragP
= fragP
->fr_next
;
8755 next_fragP
= next_fragP
->fr_next
)
8757 if (next_fragP
== symbol_get_frag (symbolP
))
8765 /* Alignment Functions. */
8768 get_text_align_power (target_size
)
8772 for (i
= 0; i
< sizeof (size_t); i
++)
8774 if (target_size
<= (1 << i
))
8783 get_text_align_max_fill_size (align_pow
, use_nops
, use_no_density
)
8785 bfd_boolean use_nops
;
8786 bfd_boolean use_no_density
;
8789 return (1 << align_pow
);
8791 return 3 * (1 << align_pow
);
8793 return 1 + (1 << align_pow
);
8797 /* get_text_align_fill_size ()
8801 target_size = size of next instruction
8802 align_pow = get_text_align_power (target_size).
8806 address = current address + loop instruction size;
8807 target_size = 3 (for 2 or 3 byte target)
8808 = 4 (for 4 byte target)
8809 = 8 (for 8 byte target)
8810 align_pow = get_text_align_power (target_size);
8812 use_no_density = set appropriately
8814 address = current address + loop instruction size;
8816 align_pow = get_text_align_power (target_size);
8818 use_no_density = 0. */
8821 get_text_align_fill_size (address
, align_pow
, target_size
,
8822 use_nops
, use_no_density
)
8826 bfd_boolean use_nops
;
8827 bfd_boolean use_no_density
;
8831 align_pow: log2 (required alignment).
8833 target_size: alignment must allow the new_address and
8834 new_address+target_size-1.
8836 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8838 use_no_density: if use_nops and use_no_density, we can only use
8841 Usually the align_pow is the power of 2 that is greater than
8842 or equal to the target_size. This handles the 2-byte, 3-byte
8843 and 8-byte instructions.
8847 (1) aligning an instruction properly, but without using NOPs.
8848 E.G.: a 3-byte instruction can go on any address where address mod 4
8849 is zero or one. The aligner uses this case to find the optimal
8850 number of fill bytes for relax_frag_for_align.
8852 (2) aligning an instruction properly, but where we might need to use
8853 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8854 or similar to get the optimal location. */
8856 size_t alignment
= (1 << align_pow
);
8858 assert (target_size
!= 0);
8862 unsigned fill_bytes
;
8863 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8865 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8866 addressT start_address
= address
+ fill_bytes
;
8867 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8873 /* This is the slightly harder case. */
8874 assert ((int) alignment
>= target_size
);
8875 assert (target_size
> 0);
8876 if (!use_no_density
)
8879 for (i
= 0; i
< alignment
* 2; i
++)
8883 if ((address
+ i
) >> align_pow
8884 == (address
+ i
+ target_size
- 1) >> align_pow
)
8892 /* Can only fill multiples of 3. */
8893 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8895 if ((address
+ i
) >> align_pow
8896 == (address
+ i
+ target_size
- 1) >> align_pow
)
8905 /* This will assert if it is not possible. */
8908 get_text_align_nop_count (fill_size
, use_no_density
)
8910 bfd_boolean use_no_density
;
8915 assert (fill_size
% 3 == 0);
8916 return (fill_size
/ 3);
8919 assert (fill_size
!= 1); /* Bad argument. */
8921 while (fill_size
> 1)
8923 size_t insn_size
= 3;
8924 if (fill_size
== 2 || fill_size
== 4)
8926 fill_size
-= insn_size
;
8929 assert (fill_size
!= 1); /* Bad algorithm. */
8935 get_text_align_nth_nop_size (fill_size
, n
, use_no_density
)
8938 bfd_boolean use_no_density
;
8942 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8947 while (fill_size
> 1)
8949 size_t insn_size
= 3;
8950 if (fill_size
== 2 || fill_size
== 4)
8952 fill_size
-= insn_size
;
8962 /* For the given fragment, find the appropriate address
8963 for it to begin at if we are using NOPs to align it. */
8966 get_noop_aligned_address (fragP
, address
)
8970 /* The rule is: get next fragment's FIRST instruction. Find
8971 the smallest number of bytes that need to be added to
8972 ensure that the next fragment's FIRST instruction will fit
8975 E.G., 2 bytes : 0, 1, 2 mod 4
8978 If the FIRST instruction MIGHT be relaxed,
8979 assume that it will become a 3-byte instruction.
8981 Note again here that LOOP instructions are not bundleable,
8982 and this relaxation only applies to LOOP opcodes. */
8984 size_t fill_size
= 0;
8985 int first_insn_size
;
8987 addressT pre_opcode_bytes
;
8990 xtensa_opcode opcode
;
8991 bfd_boolean is_loop
;
8993 assert (fragP
->fr_type
== rs_machine_dependent
);
8994 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8996 /* Find the loop frag. */
8997 first_insn
= next_non_empty_frag (fragP
);
8998 /* Now find the first insn frag. */
8999 first_insn
= next_non_empty_frag (first_insn
);
9001 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
9003 loop_insn_size
= xg_get_single_size (opcode
);
9005 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
9006 pre_opcode_bytes
+= loop_insn_size
;
9008 /* For loops, the alignment depends on the size of the
9009 instruction following the loop, not the LOOP instruction. */
9011 if (first_insn
== NULL
)
9014 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
9016 first_insn_size
= frag_format_size (first_insn
);
9018 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
9019 first_insn_size
= 3; /* ISA specifies this */
9021 /* If it was 8, then we'll need a larger alignment for the section. */
9022 alignment
= get_text_align_power (first_insn_size
);
9024 /* Is now_seg valid? */
9025 record_alignment (now_seg
, alignment
);
9027 fill_size
= get_text_align_fill_size
9028 (address
+ pre_opcode_bytes
,
9029 get_text_align_power (first_insn_size
),
9030 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
9032 return address
+ fill_size
;
9036 /* 3 mechanisms for relaxing an alignment:
9038 Align to a power of 2.
9039 Align so the next fragment's instruction does not cross a word boundary.
9040 Align the current instruction so that if the next instruction
9041 were 3 bytes, it would not cross a word boundary.
9045 zeros - This is easy; always insert zeros.
9046 nops - 3-byte and 2-byte instructions
9050 >=5 : 3-byte instruction + fn (n-3)
9051 widening - widen previous instructions. */
9054 get_aligned_diff (fragP
, address
, max_diff
)
9059 addressT target_address
, loop_insn_offset
;
9061 xtensa_opcode loop_opcode
;
9062 bfd_boolean is_loop
;
9063 int text_align_power
;
9066 assert (fragP
->fr_type
== rs_machine_dependent
);
9067 switch (fragP
->fr_subtype
)
9069 case RELAX_DESIRE_ALIGN
:
9070 target_size
= next_frag_format_size (fragP
);
9071 if (target_size
== XTENSA_UNDEFINED
)
9073 text_align_power
= get_text_align_power (xtensa_fetch_width
);
9074 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
9075 target_size
, FALSE
, FALSE
);
9077 *max_diff
= opt_diff
+ xtensa_fetch_width
9078 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
9079 assert (*max_diff
>= opt_diff
);
9082 case RELAX_ALIGN_NEXT_OPCODE
:
9083 target_size
= next_frag_format_size (fragP
);
9084 loop_insn_offset
= 0;
9085 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
9088 /* If the loop has been expanded then the LOOP instruction
9089 could be at an offset from this fragment. */
9090 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
9092 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
9094 if (target_size
== 2)
9095 target_size
= 3; /* ISA specifies this */
9097 /* In an ideal world, which is what we are shooting for here,
9098 we wouldn't need to use any NOPs immediately prior to the
9099 LOOP instruction. If this approach fails, relax_frag_loop_align
9100 will call get_noop_aligned_address. */
9102 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9103 text_align_power
= get_text_align_power (target_size
),
9104 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
9105 target_size
, FALSE
, FALSE
);
9107 *max_diff
= xtensa_fetch_width
9108 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9109 - target_size
+ opt_diff
;
9110 assert (*max_diff
>= opt_diff
);
9121 /* md_relax_frag Hook and Helper Functions. */
9123 /* Return the number of bytes added to this fragment, given that the
9124 input has been stretched already by "stretch". */
9127 xtensa_relax_frag (fragP
, stretch
, stretched_p
)
9132 xtensa_isa isa
= xtensa_default_isa
;
9133 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9134 long new_stretch
= 0;
9137 static xtensa_insnbuf vbuf
= NULL
;
9138 int slot
, num_slots
;
9141 as_where (&file_name
, &line
);
9142 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9144 fragP
->tc_frag_data
.unreported_expansion
= 0;
9146 switch (fragP
->fr_subtype
)
9148 case RELAX_ALIGN_NEXT_OPCODE
:
9149 /* Always convert. */
9150 if (fragP
->tc_frag_data
.relax_seen
)
9151 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9154 case RELAX_LOOP_END
:
9158 case RELAX_LOOP_END_ADD_NOP
:
9159 /* Add a NOP and switch to .fill 0. */
9160 new_stretch
= relax_frag_add_nop (fragP
);
9164 case RELAX_DESIRE_ALIGN
:
9165 /* Do nothing. The narrowing before this frag will either align
9170 case RELAX_LITERAL_FINAL
:
9173 case RELAX_LITERAL_NR
:
9175 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9176 assert (unreported
== lit_size
);
9177 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9178 fragP
->fr_var
-= lit_size
;
9179 fragP
->fr_fix
+= lit_size
;
9185 vbuf
= xtensa_insnbuf_alloc (isa
);
9187 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
9188 fmt
= xtensa_format_decode (isa
, vbuf
);
9189 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9191 for (slot
= 0; slot
< num_slots
; slot
++)
9193 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9196 if (fragP
->tc_frag_data
.relax_seen
)
9197 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9201 case RELAX_IMMED_STEP1
:
9202 case RELAX_IMMED_STEP2
:
9203 /* Place the immediate. */
9204 new_stretch
+= relax_frag_immed
9205 (now_seg
, fragP
, stretch
,
9206 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9207 fmt
, slot
, stretched_p
, FALSE
);
9211 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9217 case RELAX_LITERAL_POOL_BEGIN
:
9218 case RELAX_LITERAL_POOL_END
:
9219 case RELAX_MAYBE_UNREACHABLE
:
9220 case RELAX_MAYBE_DESIRE_ALIGN
:
9221 /* No relaxation required. */
9224 case RELAX_FILL_NOP
:
9225 case RELAX_UNREACHABLE
:
9226 if (fragP
->tc_frag_data
.relax_seen
)
9227 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9231 as_bad (_("bad relaxation state"));
9234 /* Tell gas we need another relaxation pass. */
9235 if (! fragP
->tc_frag_data
.relax_seen
)
9237 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9241 new_logical_line (file_name
, line
);
9247 relax_frag_loop_align (fragP
, stretch
)
9251 addressT old_address
, old_next_address
, old_size
;
9252 addressT new_address
, new_next_address
, new_size
;
9255 /* All the frags with relax_frag_for_alignment prior to this one in the
9256 section have been done, hopefully eliminating the need for a NOP here.
9257 But, this will put it in if necessary. */
9259 /* Calculate the old address of this fragment and the next fragment. */
9260 old_address
= fragP
->fr_address
- stretch
;
9261 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9262 fragP
->tc_frag_data
.text_expansion
[0]);
9263 old_size
= old_next_address
- old_address
;
9265 /* Calculate the new address of this fragment and the next fragment. */
9266 new_address
= fragP
->fr_address
;
9268 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9269 new_size
= new_next_address
- new_address
;
9271 growth
= new_size
- old_size
;
9273 /* Fix up the text_expansion field and return the new growth. */
9274 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9279 /* Add a NOP instruction. */
9282 relax_frag_add_nop (fragP
)
9285 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9286 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9287 assemble_nop (length
, nop_buf
);
9288 fragP
->tc_frag_data
.is_insn
= TRUE
;
9290 if (fragP
->fr_var
< length
)
9292 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
9296 fragP
->fr_fix
+= length
;
9297 fragP
->fr_var
-= length
;
9303 relax_frag_for_align (fragP
, stretch
)
9307 /* Overview of the relaxation procedure for alignment:
9308 We can widen with NOPs or by widening instructions or by filling
9309 bytes after jump instructions. Find the opportune places and widen
9310 them if necessary. */
9315 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9316 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9317 || (fragP
->fr_subtype
== RELAX_SLOTS
9318 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9320 stretch_me
= future_alignment_required (fragP
, stretch
);
9321 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9327 /* We expanded on a previous pass. Can we shrink now? */
9328 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9329 if (shrink
<= stretch
&& stretch
> 0)
9331 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9337 /* Below here, diff > 0. */
9338 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9344 /* Return the address of the next frag that should be aligned.
9346 By "address" we mean the address it _would_ be at if there
9347 is no action taken to align it between here and the target frag.
9348 In other words, if no narrows and no fill nops are used between
9349 here and the frag to align, _even_if_ some of the frags we use
9350 to align targets have already expanded on a previous relaxation
9353 Also, count each frag that may be used to help align the target.
9355 Return 0 if there are no frags left in the chain that need to be
9359 find_address_of_next_align_frag (fragPP
, wide_nops
, narrow_nops
,
9365 bfd_boolean
*paddable
;
9367 fragS
*fragP
= *fragPP
;
9368 addressT address
= fragP
->fr_address
;
9370 /* Do not reset the counts to 0. */
9374 /* Limit this to a small search. */
9380 address
+= fragP
->fr_fix
;
9382 if (fragP
->fr_type
== rs_fill
)
9383 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9384 else if (fragP
->fr_type
== rs_machine_dependent
)
9386 switch (fragP
->fr_subtype
)
9388 case RELAX_UNREACHABLE
:
9392 case RELAX_FILL_NOP
:
9394 if (!fragP
->tc_frag_data
.is_no_density
)
9399 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9404 /* FIXME: shouldn't this add the expansion of all slots? */
9405 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9409 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9412 case RELAX_ALIGN_NEXT_OPCODE
:
9413 case RELAX_DESIRE_ALIGN
:
9417 case RELAX_MAYBE_UNREACHABLE
:
9418 case RELAX_MAYBE_DESIRE_ALIGN
:
9423 /* Just punt if we don't know the type. */
9430 /* Just punt if we don't know the type. */
9434 fragP
= fragP
->fr_next
;
9442 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
9443 I'll leave this in until I am more confident this works. */
9445 #define LOOKAHEAD_ALIGNER 1
9448 future_alignment_required (fragP
, stretch
)
9450 long stretch ATTRIBUTE_UNUSED
;
9452 fragS
*this_frag
= fragP
;
9456 int narrow_nops
= 0;
9457 bfd_boolean paddable
= FALSE
;
9458 offsetT local_opt_diff
;
9461 int stretch_amount
= 0;
9462 int local_stretch_amount
;
9463 int global_stretch_amount
;
9466 = find_address_of_next_align_frag (&fragP
, &wide_nops
, &narrow_nops
,
9467 &num_widens
, &paddable
);
9471 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9472 opt_diff
= local_opt_diff
;
9473 assert (opt_diff
>= 0);
9474 assert (max_diff
>= opt_diff
);
9477 #ifdef LOOKAHEAD_ALIGNER
9479 fragP
= fragP
->fr_next
;
9481 while (fragP
&& opt_diff
< max_diff
&& address
)
9483 /* We only use these to determine if we can exit early
9484 because there will be plenty of ways to align future
9486 unsigned int glob_widens
= 0;
9489 bfd_boolean glob_pad
= 0;
9491 find_address_of_next_align_frag (&fragP
, &glob_widens
,
9492 &dnn
, &dw
, &glob_pad
);
9493 /* If there is a padable portion, then skip. */
9494 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
9499 offsetT next_m_diff
;
9500 offsetT next_o_diff
;
9502 /* Downrange frags haven't had stretch added to them yet. */
9505 /* The address also includes any text expansion from this
9506 frag in a previous pass, but we don't want that. */
9507 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9509 /* Assume we are going to move at least opt_diff. In
9510 reality, we might not be able to, but assuming that
9511 we will helps catch cases where moving opt_diff pushes
9512 the next target from aligned to unaligned. */
9513 address
+= opt_diff
;
9515 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9517 /* Now cleanup for the adjustments to address. */
9518 next_o_diff
+= opt_diff
;
9519 next_m_diff
+= opt_diff
;
9520 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9521 opt_diff
= next_o_diff
;
9522 if (next_m_diff
< max_diff
)
9523 max_diff
= next_m_diff
;
9524 fragP
= fragP
->fr_next
;
9527 #endif /* LOOKAHEAD_ALIGNER */
9528 /* If there are enough wideners in between, do it. */
9531 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9533 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
9538 local_stretch_amount
9539 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9540 num_widens
, local_opt_diff
);
9541 #ifdef LOOKAHEAD_ALIGNER
9542 global_stretch_amount
9543 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9544 num_widens
, opt_diff
);
9545 /* If the condition below is true, then the frag couldn't
9546 stretch the correct amount for the global case, so we just
9547 optimize locally. We'll rely on the subsequent frags to get
9548 the correct alignment in the global case. */
9549 if (global_stretch_amount
< local_stretch_amount
)
9550 stretch_amount
= local_stretch_amount
;
9552 stretch_amount
= global_stretch_amount
;
9553 #else /* ! LOOKAHEAD_ALIGNER */
9554 stretch_amount
= local_stretch_amount
;
9555 #endif /* ! LOOKAHEAD_ALIGNER */
9556 if (this_frag
->fr_subtype
== RELAX_SLOTS
9557 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9558 assert (stretch_amount
<= 1);
9559 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9561 if (this_frag
->tc_frag_data
.is_no_density
)
9562 assert (stretch_amount
== 3 || stretch_amount
== 0);
9564 assert (stretch_amount
<= 3);
9567 return stretch_amount
;
9571 /* The idea: widen everything you can to get a target or loop aligned,
9572 then start using NOPs.
9574 When we must have a NOP, here is a table of how we decide
9575 (so you don't have to fight through the control flow below):
9577 wide_nops = the number of wide NOPs available for aligning
9578 narrow_nops = the number of narrow NOPs available for aligning
9579 (a subset of wide_nops)
9580 widens = the number of narrow instructions that should be widened
9587 b 0 1 1 (case 3a makes this case unnecessary)
9590 c 0 1 2 (case 4a makes this case unnecessary)
9593 c 0 2 1 (case 5b makes this case unnecessary)
9596 c 0 1 4 (case 6b makes this case unneccesary)
9597 d 1 1 1 (case 6a makes this case unnecessary)
9598 e 0 2 2 (case 6a makes this case unnecessary)
9599 f 0 3 0 (case 6a makes this case unnecessary)
9602 c 1 1 2 (case 7b makes this case unnecessary)
9603 d 0 1 5 (case 7a makes this case unnecessary)
9604 e 0 2 3 (case 7b makes this case unnecessary)
9605 f 0 3 1 (case 7b makes this case unnecessary)
9606 g 1 2 1 (case 7b makes this case unnecessary)
9610 bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
, num_widens
, desired_diff
)
9617 int bytes_short
= desired_diff
- num_widens
;
9619 assert (desired_diff
>= 0 && desired_diff
< 8);
9620 if (desired_diff
== 0)
9623 assert (wide_nops
> 0 || num_widens
> 0);
9625 /* Always prefer widening to NOP-filling. */
9626 if (bytes_short
< 0)
9628 /* There are enough RELAX_NARROW frags after this one
9629 to align the target without widening this frag in any way. */
9633 if (bytes_short
== 0)
9635 /* Widen every narrow between here and the align target
9636 and the align target will be properly aligned. */
9637 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9643 /* From here we will need at least one NOP to get an alignment.
9644 However, we may not be able to align at all, in which case,
9646 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9648 switch (desired_diff
)
9653 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
9654 return 2; /* case 2 */
9660 return 3; /* case 3a */
9662 if (num_widens
>= 1 && wide_nops
== 1)
9663 return 3; /* case 4a */
9664 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
9665 return 2; /* case 4b */
9668 if (num_widens
>= 2 && wide_nops
== 1)
9669 return 3; /* case 5a */
9670 /* We will need two nops. Are there enough nops
9671 between here and the align target? */
9672 if (wide_nops
< 2 || narrow_nops
== 0)
9674 /* Are there other nops closer that can serve instead? */
9675 if (wide_nops
> 2 && narrow_nops
> 1)
9677 /* Take the density one first, because there might not be
9678 another density one available. */
9679 if (!this_frag
->tc_frag_data
.is_no_density
)
9680 return 2; /* case 5b narrow */
9682 return 3; /* case 5b wide */
9686 return 3; /* case 6a */
9687 else if (num_widens
>= 3 && wide_nops
== 1)
9688 return 3; /* case 6b */
9691 if (wide_nops
== 1 && num_widens
>= 4)
9692 return 3; /* case 7a */
9693 else if (wide_nops
== 2 && num_widens
>= 1)
9694 return 3; /* case 7b */
9702 /* We will need a NOP no matter what, but should we widen
9703 this instruction to help?
9705 This is a RELAX_FRAG_NARROW frag. */
9706 switch (desired_diff
)
9715 if (wide_nops
>= 1 && num_widens
== 1)
9716 return 1; /* case 4a */
9719 if (wide_nops
>= 1 && num_widens
== 2)
9720 return 1; /* case 5a */
9724 return 0; /* case 6a */
9725 else if (wide_nops
>= 1 && num_widens
== 3)
9726 return 1; /* case 6b */
9729 if (wide_nops
>= 1 && num_widens
== 4)
9730 return 1; /* case 7a */
9731 else if (wide_nops
>= 2 && num_widens
== 1)
9732 return 1; /* case 7b */
9745 relax_frag_immed (segP
, fragP
, stretch
, min_steps
, fmt
, slot
, stretched_p
,
9754 bfd_boolean estimate_only
;
9757 vliw_insn orig_vinsn
;
9759 bfd_boolean negatable_branch
= FALSE
;
9760 bfd_boolean branch_jmp_to_next
= FALSE
;
9761 bfd_boolean wide_insn
= FALSE
;
9762 xtensa_isa isa
= xtensa_default_isa
;
9764 offsetT frag_offset
;
9767 int num_text_bytes
, num_literal_bytes
;
9768 int literal_diff
, total_text_diff
, this_text_diff
, first
;
9770 assert (fragP
->fr_opcode
!= NULL
);
9772 xg_init_vinsn (&orig_vinsn
);
9773 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
9774 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9777 tinsn
= orig_vinsn
.slots
[slot
];
9778 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9780 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
9783 if (workaround_b_j_loop_end
&& !get_frag_is_no_transform (fragP
))
9784 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9786 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9788 old_size
= xtensa_format_length (isa
, fmt
);
9790 /* Special case: replace a branch to the next instruction with a NOP.
9791 This is required to work around a hardware bug in T1040.0 and also
9792 serves as an optimization. */
9794 if (branch_jmp_to_next
9795 && ((old_size
== 2) || (old_size
== 3))
9796 && !next_frag_is_loop_target (fragP
))
9799 /* Here is the fun stuff: Get the immediate field from this
9800 instruction. If it fits, we are done. If not, find the next
9801 instruction sequence that fits. */
9803 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9804 istack_init (&istack
);
9805 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9806 min_steps
, stretch
);
9807 if (num_steps
< min_steps
)
9809 as_fatal (_("internal error: relaxation failed"));
9813 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9815 as_fatal (_("internal error: relaxation requires too many steps"));
9819 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9821 /* Figure out the number of bytes needed. */
9823 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9825 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9827 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9829 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9832 num_text_bytes
+= old_size
;
9833 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9834 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9836 total_text_diff
= num_text_bytes
- old_size
;
9837 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9839 /* It MUST get larger. If not, we could get an infinite loop. */
9840 assert (num_text_bytes
>= 0);
9841 assert (literal_diff
>= 0);
9842 assert (total_text_diff
>= 0);
9844 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9845 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9846 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9847 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9849 /* Find the associated expandable literal for this. */
9850 if (literal_diff
!= 0)
9852 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9855 assert (literal_diff
== 4);
9856 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9858 /* We expect that the literal section state has NOT been
9860 assert (lit_fragP
->fr_type
== rs_machine_dependent
9861 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9862 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9864 /* We need to mark this section for another iteration
9870 /* FIXME: When a negatable branch expands and then contracts in a
9871 subsequent pass, update_next_frag_state correctly updates the
9872 type of the frag to RELAX_MAYBE_UNREACHABLE, but it doesn't undo
9873 any expansion relax_frag_for_align may have expected it to. For
9874 now, change back to only call it when the branch expands. */
9875 if (negatable_branch
&& istack
.ninsn
> 1)
9876 update_next_frag_state (fragP
, FALSE
/* istack.ninsn > 1 */);
9878 return this_text_diff
;
9882 /* md_convert_frag Hook and Helper Functions. */
9885 md_convert_frag (abfd
, sec
, fragp
)
9886 bfd
*abfd ATTRIBUTE_UNUSED
;
9890 static xtensa_insnbuf vbuf
= NULL
;
9891 xtensa_isa isa
= xtensa_default_isa
;
9898 as_where (&file_name
, &line
);
9899 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9901 switch (fragp
->fr_subtype
)
9903 case RELAX_ALIGN_NEXT_OPCODE
:
9904 /* Always convert. */
9905 convert_frag_align_next_opcode (fragp
);
9908 case RELAX_DESIRE_ALIGN
:
9909 /* Do nothing. If not aligned already, too bad. */
9913 case RELAX_LITERAL_FINAL
:
9918 vbuf
= xtensa_insnbuf_alloc (isa
);
9920 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9921 fmt
= xtensa_format_decode (isa
, vbuf
);
9922 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9924 for (slot
= 0; slot
< num_slots
; slot
++)
9926 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9929 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9933 case RELAX_IMMED_STEP1
:
9934 case RELAX_IMMED_STEP2
:
9935 /* Place the immediate. */
9938 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9943 /* This is OK because some slots could have
9944 relaxations and others have none. */
9950 case RELAX_UNREACHABLE
:
9951 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9952 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9953 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9957 case RELAX_MAYBE_UNREACHABLE
:
9958 case RELAX_MAYBE_DESIRE_ALIGN
:
9962 case RELAX_FILL_NOP
:
9963 convert_frag_fill_nop (fragp
);
9966 case RELAX_LITERAL_NR
:
9967 if (use_literal_section
)
9969 /* This should have been handled during relaxation. When
9970 relaxing a code segment, literals sometimes need to be
9971 added to the corresponding literal segment. If that
9972 literal segment has already been relaxed, then we end up
9973 in this situation. Marking the literal segments as data
9974 would make this happen less often (since GAS always relaxes
9975 code before data), but we could still get into trouble if
9976 there are instructions in a segment that is not marked as
9977 containing code. Until we can implement a better solution,
9978 cheat and adjust the addresses of all the following frags.
9979 This could break subsequent alignments, but the linker's
9980 literal coalescing will do that anyway. */
9983 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9984 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9985 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9988 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9992 as_bad (_("invalid relaxation fragment result"));
9997 new_logical_line (file_name
, line
);
10002 convert_frag_align_next_opcode (fragp
)
10005 char *nop_buf
; /* Location for Writing. */
10008 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10009 addressT aligned_address
;
10010 size_t fill_size
, nop_count
;
10012 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10014 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10015 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10016 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10018 for (i
= 0; i
< nop_count
; i
++)
10021 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
10023 assemble_nop (nop_size
, nop_buf
);
10024 nop_buf
+= nop_size
;
10027 fragp
->fr_fix
+= fill_size
;
10028 fragp
->fr_var
-= fill_size
;
10033 convert_frag_narrow (segP
, fragP
, fmt
, slot
)
10039 TInsn tinsn
, single_target
;
10040 xtensa_format single_fmt
;
10041 int size
, old_size
, diff
, error_val
;
10042 offsetT frag_offset
;
10044 assert (slot
== 0);
10045 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10047 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
10049 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10050 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10051 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10056 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10058 /* No conversion. */
10063 assert (fragP
->fr_opcode
!= NULL
);
10065 /* Frags in this relaxation state should only contain
10066 single instruction bundles. */
10067 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10069 /* Just convert it to a wide form.... */
10071 old_size
= xg_get_single_size (tinsn
.opcode
);
10073 tinsn_init (&single_target
);
10074 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10076 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
10079 as_bad (_("unable to widen instruction"));
10083 size
= xg_get_single_size (single_target
.opcode
);
10084 single_fmt
= xg_get_single_format (single_target
.opcode
);
10086 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
10087 fragP
, frag_offset
, TRUE
);
10089 diff
= size
- old_size
;
10090 assert (diff
>= 0);
10091 assert (diff
<= fragP
->fr_var
);
10092 fragP
->fr_var
-= diff
;
10093 fragP
->fr_fix
+= diff
;
10101 convert_frag_fill_nop (fragP
)
10104 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10105 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10106 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10107 - fragP
->fr_address
- fragP
->fr_fix
));
10110 /* No conversion. */
10114 assemble_nop (size
, loc
);
10115 fragP
->tc_frag_data
.is_insn
= TRUE
;
10116 fragP
->fr_var
-= size
;
10117 fragP
->fr_fix
+= size
;
10123 convert_frag_immed (segP
, fragP
, min_steps
, fmt
, slot
)
10130 char *immed_instr
= fragP
->fr_opcode
;
10132 bfd_boolean expanded
= FALSE
;
10133 bfd_boolean branch_jmp_to_next
= FALSE
;
10134 char *fr_opcode
= fragP
->fr_opcode
;
10135 vliw_insn orig_vinsn
;
10136 xtensa_isa isa
= xtensa_default_isa
;
10137 bfd_boolean wide_insn
= FALSE
;
10139 bfd_boolean is_loop
;
10141 assert (fr_opcode
!= NULL
);
10143 xg_init_vinsn (&orig_vinsn
);
10145 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
10146 if (xtensa_format_num_slots (isa
, fmt
) > 1)
10149 orig_tinsn
= orig_vinsn
.slots
[slot
];
10150 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10152 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10154 if (workaround_b_j_loop_end
&& !get_frag_is_no_transform (fragP
))
10155 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10157 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10159 /* Conversion just inserts a NOP and marks the fix as completed. */
10160 bytes
= xtensa_format_length (isa
, fmt
);
10163 orig_vinsn
.slots
[slot
].opcode
=
10164 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
10165 orig_vinsn
.slots
[slot
].ntok
= 0;
10169 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10170 assert (bytes
== 2 || bytes
== 3);
10171 build_nop (&orig_vinsn
.slots
[0], bytes
);
10172 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10174 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
10175 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
10178 else if (!orig_tinsn
.is_specific_opcode
)
10180 /* Here is the fun stuff: Get the immediate field from this
10181 instruction. If it fits, we're done. If not, find the next
10182 instruction sequence that fits. */
10186 symbolS
*lit_sym
= NULL
;
10187 int total_size
= 0;
10188 int target_offset
= 0;
10191 symbolS
*gen_label
= NULL
;
10192 offsetT frag_offset
;
10193 bfd_boolean first
= TRUE
;
10194 bfd_boolean last_is_jump
;
10196 /* It does not fit. Find something that does and
10197 convert immediately. */
10198 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10199 istack_init (&istack
);
10200 xg_assembly_relax (&istack
, &orig_tinsn
,
10201 segP
, fragP
, frag_offset
, min_steps
, 0);
10203 old_size
= xtensa_format_length (isa
, fmt
);
10205 /* Assemble this right inline. */
10207 /* First, create the mapping from a label name to the REAL label. */
10209 for (i
= 0; i
< istack
.ninsn
; i
++)
10211 TInsn
*tinsn
= &istack
.insn
[i
];
10214 switch (tinsn
->insn_type
)
10216 case ITYPE_LITERAL
:
10217 if (lit_sym
!= NULL
)
10218 as_bad (_("multiple literals in expansion"));
10219 /* First find the appropriate space in the literal pool. */
10220 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10221 if (lit_frag
== NULL
)
10222 as_bad (_("no registered fragment for literal"));
10223 if (tinsn
->ntok
!= 1)
10224 as_bad (_("number of literal tokens != 1"));
10226 /* Set the literal symbol and add a fixup. */
10227 lit_sym
= lit_frag
->fr_symbol
;
10231 if (align_targets
&& !is_loop
)
10233 fragS
*unreach
= fragP
->fr_next
;
10234 while (!(unreach
->fr_type
== rs_machine_dependent
10235 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10236 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10238 unreach
= unreach
->fr_next
;
10241 assert (unreach
->fr_type
== rs_machine_dependent
10242 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10243 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10245 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10247 assert (gen_label
== NULL
);
10248 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10249 fr_opcode
- fragP
->fr_literal
10250 + target_offset
, fragP
);
10254 if (first
&& wide_insn
)
10256 target_offset
+= xtensa_format_length (isa
, fmt
);
10258 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10259 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10262 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10269 last_is_jump
= FALSE
;
10270 for (i
= 0; i
< istack
.ninsn
; i
++)
10272 TInsn
*tinsn
= &istack
.insn
[i
];
10276 bfd_reloc_code_real_type reloc_type
;
10278 switch (tinsn
->insn_type
)
10280 case ITYPE_LITERAL
:
10281 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10282 /* Already checked. */
10283 assert (lit_frag
!= NULL
);
10284 assert (lit_sym
!= NULL
);
10285 assert (tinsn
->ntok
== 1);
10287 target_seg
= S_GET_SEGMENT (lit_sym
);
10288 assert (target_seg
);
10289 if (tinsn
->tok
[0].X_op
== O_pltrel
)
10290 reloc_type
= BFD_RELOC_XTENSA_PLT
;
10292 reloc_type
= BFD_RELOC_32
;
10293 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10294 &tinsn
->tok
[0], FALSE
, reloc_type
);
10301 xg_resolve_labels (tinsn
, gen_label
);
10302 xg_resolve_literals (tinsn
, lit_sym
);
10303 if (wide_insn
&& first
)
10306 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10308 tinsn
->record_fix
= TRUE
;
10309 orig_vinsn
.slots
[slot
] = *tinsn
;
10313 orig_vinsn
.slots
[slot
].opcode
=
10314 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10315 orig_vinsn
.slots
[slot
].ntok
= 0;
10316 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
10318 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
10319 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
10321 fragP
->tc_frag_data
.is_insn
= TRUE
;
10322 size
= xtensa_format_length (isa
, fmt
);
10323 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10325 xtensa_format single_fmt
=
10326 xg_get_single_format (tinsn
->opcode
);
10328 xg_emit_insn_to_buf
10329 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
10330 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10331 size
+= xg_get_single_size (tinsn
->opcode
);
10336 xtensa_format single_format
;
10337 size
= xg_get_single_size (tinsn
->opcode
);
10338 single_format
= xg_get_single_format (tinsn
->opcode
);
10339 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
10341 immed_instr
- fragP
->fr_literal
, TRUE
);
10343 /* Code to recognize branch-around expansion
10344 so the fragment is properly marked as ending in a
10346 if ((((i
== istack
.ninsn
- 2)
10347 && (istack
.insn
[istack
.ninsn
-1].insn_type
10349 || i
== istack
.ninsn
-1)
10350 && xtensa_opcode_is_jump (xtensa_default_isa
,
10351 tinsn
->opcode
) == 1
10352 && fragP
->fr_next
!= NULL
10353 && ! fragP
->fr_next
->tc_frag_data
.is_unreachable
)
10355 /* Create a new unreachable frag of zero size. */
10356 size_t frag_size
= sizeof (fragS
);
10357 fragS
*new_fragP
= (fragS
*) xmalloc (frag_size
);
10358 memset (new_fragP
, 0, frag_size
);
10359 new_fragP
->fr_address
= fragP
->fr_next
->fr_address
;
10360 new_fragP
->fr_next
= fragP
->fr_next
;
10361 new_fragP
->fr_fix
= 0;
10362 new_fragP
->fr_var
= 0;
10363 new_fragP
->fr_type
= rs_fill
;
10364 new_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
10365 /* The rest are zeros.... */
10366 /* Link it in to the chain. */
10367 fragP
->fr_next
= new_fragP
;
10371 immed_instr
+= size
;
10372 total_size
+= size
;
10377 diff
= total_size
- old_size
;
10378 assert (diff
>= 0);
10381 assert (diff
<= fragP
->fr_var
);
10382 fragP
->fr_var
-= diff
;
10383 fragP
->fr_fix
+= diff
;
10387 xg_free_vinsn (&orig_vinsn
);
10389 /* Check for undefined immediates in LOOP instructions. */
10393 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10394 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10396 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10399 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10400 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10402 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10407 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10408 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10410 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10412 /* Add an expansion note on the expanded instruction. */
10413 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10414 &orig_tinsn
.tok
[0], TRUE
,
10415 BFD_RELOC_XTENSA_ASM_EXPAND
);
10420 /* Add a new fix expression into the desired segment. We have to
10421 switch to that segment to do this. */
10424 fix_new_exp_in_seg (new_seg
, new_subseg
,
10425 frag
, where
, size
, exp
, pcrel
, r_type
)
10427 subsegT new_subseg
;
10433 bfd_reloc_code_real_type r_type
;
10436 segT seg
= now_seg
;
10437 subsegT subseg
= now_subseg
;
10439 assert (new_seg
!= 0);
10440 subseg_set (new_seg
, new_subseg
);
10442 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10443 subseg_set (seg
, subseg
);
10448 /* Relax a loop instruction so that it can span loop >256 bytes.
10454 addi as, as, lo8 (label-.L1)
10455 addmi as, as, mid8 (label-.L1)
10466 convert_frag_immed_finish_loop (segP
, fragP
, tinsn
)
10474 unsigned long target
;
10475 static xtensa_insnbuf insnbuf
= NULL
;
10476 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10477 xtensa_isa isa
= xtensa_default_isa
;
10478 addressT loop_offset
;
10479 addressT addi_offset
= 9;
10480 addressT addmi_offset
= 12;
10482 size_t target_count
;
10485 insnbuf
= xtensa_insnbuf_alloc (isa
);
10487 /* Get the loop offset. */
10488 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10490 /* Validate that there really is a LOOP at the loop_offset. Because
10491 loops are not bundleable, we can assume that the instruction will be
10493 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10494 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10496 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10497 addi_offset
+= loop_offset
;
10498 addmi_offset
+= loop_offset
;
10500 assert (tinsn
->ntok
== 2);
10501 target
= get_expression_value (segP
, &tinsn
->tok
[1]);
10504 know (symbolP
->sy_frag
);
10505 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
10506 || symbol_get_frag (symbolP
) == &zero_address_frag
);
10508 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10509 loop_length_hi
= loop_length
& ~0x0ff;
10510 loop_length_lo
= loop_length
& 0x0ff;
10511 if (loop_length_lo
>= 128)
10513 loop_length_lo
-= 256;
10514 loop_length_hi
+= 256;
10517 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10518 32512. If the loop is larger than that, then we just fail. */
10519 if (loop_length_hi
> 32512)
10520 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10521 _("loop too long for LOOP instruction"));
10523 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10524 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10526 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10527 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10529 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10530 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10532 fragP
->tc_frag_data
.is_insn
= TRUE
;
10533 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
10535 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10536 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10537 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
10539 /* Walk through all of the frags from here to the loop end
10540 and mark them as no_transform to keep them from being modified
10541 by the linker. If we ever have a relocation for the
10542 addi/addmi of the difference of two symbols we can remove this. */
10545 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10546 next_fragP
= next_fragP
->fr_next
)
10548 set_frag_is_no_transform (next_fragP
, TRUE
);
10549 if (next_fragP
->tc_frag_data
.is_loop_target
)
10551 if (target_count
== 2)
10558 get_expression_value (segP
, exp
)
10562 if (exp
->X_op
== O_constant
)
10563 return exp
->X_add_number
;
10564 if (exp
->X_op
== O_symbol
)
10566 /* Find the fragment. */
10567 symbolS
*sym
= exp
->X_add_symbol
;
10569 assert (S_GET_SEGMENT (sym
) == segP
10570 || S_GET_SEGMENT (sym
) == absolute_section
);
10572 return (S_GET_VALUE (sym
) + exp
->X_add_number
);
10574 as_bad (_("invalid expression evaluation type %d"), exp
->X_op
);
10579 static subseg_map
*sseg_map
= NULL
;
10583 get_last_insn_flags (seg
, subseg
)
10587 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10588 return subseg_e
->flags
;
10592 static subseg_map
*
10593 get_subseg_info (seg
, subseg
)
10597 subseg_map
*subseg_e
;
10599 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10601 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10605 subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
10606 memset (subseg_e
, 0, sizeof (subseg_map
));
10607 subseg_e
->seg
= seg
;
10608 subseg_e
->subseg
= subseg
;
10609 subseg_e
->flags
= 0;
10610 /* Start off considering every branch target very important. */
10611 subseg_e
->cur_target_freq
= 1.0;
10612 subseg_e
->cur_total_freq
= 1.0;
10613 subseg_e
->next
= sseg_map
;
10614 sseg_map
= subseg_e
;
10620 set_last_insn_flags (seg
, subseg
, fl
, val
)
10626 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10628 subseg_e
->flags
|= fl
;
10630 subseg_e
->flags
&= ~fl
;
10634 /* Segment Lists and emit_state Stuff. */
10636 /* Remove the segment from the global sections list. */
10639 xtensa_remove_section (sec
)
10642 /* Handle brain-dead bfd_section_list_remove macro, which
10643 expect the address of the prior section's "next" field, not
10644 just the address of the section to remove. */
10646 segT
*ps_next_ptr
= &stdoutput
->sections
;
10647 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
10648 ps_next_ptr
= &(*ps_next_ptr
)->next
;
10650 assert (*ps_next_ptr
!= NULL
);
10652 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
10657 xtensa_insert_section (after_sec
, sec
)
10661 segT
*after_sec_next
;
10662 if (after_sec
== NULL
)
10663 after_sec_next
= &stdoutput
->sections
;
10665 after_sec_next
= &after_sec
->next
;
10667 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
10672 xtensa_move_seg_list_to_beginning (head
)
10678 segT literal_section
= head
->seg
;
10680 /* Move the literal section to the front of the section list. */
10681 assert (literal_section
);
10682 xtensa_remove_section (literal_section
);
10683 xtensa_insert_section (NULL
, literal_section
);
10691 xtensa_move_literals ()
10694 frchainS
*frchain_from
, *frchain_to
;
10695 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10696 fragS
**frag_splice
;
10699 fixS
*fix
, *next_fix
, **fix_splice
;
10702 mark_literal_frags (literal_head
->next
);
10703 mark_literal_frags (init_literal_head
->next
);
10704 mark_literal_frags (fini_literal_head
->next
);
10706 if (use_literal_section
)
10709 segment
= literal_head
->next
;
10712 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10713 search_frag
= frchain_from
->frch_root
;
10714 literal_pool
= NULL
;
10716 frag_splice
= &(frchain_from
->frch_root
);
10718 while (!search_frag
->tc_frag_data
.literal_frag
)
10720 assert (search_frag
->fr_fix
== 0
10721 || search_frag
->fr_type
== rs_align
);
10722 search_frag
= search_frag
->fr_next
;
10725 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10726 == RELAX_LITERAL_POOL_BEGIN
);
10727 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10729 /* Make sure that all the frags in this series are closed, and
10730 that there is at least one left over of zero-size. This
10731 prevents us from making a segment with an frchain without any
10733 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10734 xtensa_set_frag_assembly_state (frag_now
);
10735 last_frag
= frag_now
;
10736 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10737 xtensa_set_frag_assembly_state (frag_now
);
10739 while (search_frag
!= frag_now
)
10741 next_frag
= search_frag
->fr_next
;
10743 /* First, move the frag out of the literal section and
10744 to the appropriate place. */
10745 if (search_frag
->tc_frag_data
.literal_frag
)
10747 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10748 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10749 /* Note that we set this fr_var to be a fix
10750 chain when we created the literal pool location
10751 as RELAX_LITERAL_POOL_BEGIN. */
10752 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
10754 insert_after
= literal_pool
;
10756 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
10757 insert_after
= insert_after
->fr_next
;
10759 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
10761 *frag_splice
= next_frag
;
10762 search_frag
->fr_next
= insert_after
->fr_next
;
10763 insert_after
->fr_next
= search_frag
;
10764 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10766 /* Now move any fixups associated with this frag to the
10768 fix
= frchain_from
->fix_root
;
10769 fix_splice
= &(frchain_from
->fix_root
);
10772 next_fix
= fix
->fx_next
;
10773 if (fix
->fx_frag
== search_frag
)
10775 *fix_splice
= next_fix
;
10776 fix
->fx_next
= frchain_to
->fix_root
;
10777 frchain_to
->fix_root
= fix
;
10778 if (frchain_to
->fix_tail
== NULL
)
10779 frchain_to
->fix_tail
= fix
;
10782 fix_splice
= &(fix
->fx_next
);
10785 search_frag
= next_frag
;
10788 if (frchain_from
->fix_root
!= NULL
)
10790 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10791 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10793 assert (frchain_from
->fix_root
== NULL
);
10795 frchain_from
->fix_tail
= NULL
;
10796 xtensa_restore_emit_state (&state
);
10797 segment
= segment
->next
;
10800 /* Now fix up the SEGMENT value for all the literal symbols. */
10801 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10803 symbolS
*lit_sym
= lit
->sym
;
10804 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10806 S_SET_SEGMENT (lit_sym
, dest_seg
);
10811 /* Walk over all the frags for segments in a list and mark them as
10812 containing literals. As clunky as this is, we can't rely on frag_var
10813 and frag_variant to get called in all situations. */
10816 mark_literal_frags (segment
)
10819 frchainS
*frchain_from
;
10820 fragS
*search_frag
;
10824 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10825 search_frag
= frchain_from
->frch_root
;
10826 while (search_frag
)
10828 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10829 search_frag
= search_frag
->fr_next
;
10831 segment
= segment
->next
;
10837 xtensa_reorder_seg_list (head
, after
)
10841 /* Move all of the sections in the section list to come
10842 after "after" in the gnu segment list. */
10847 segT literal_section
= head
->seg
;
10849 /* Move the literal section after "after". */
10850 assert (literal_section
);
10851 if (literal_section
!= after
)
10853 xtensa_remove_section (literal_section
);
10854 xtensa_insert_section (after
, literal_section
);
10862 /* Push all the literal segments to the end of the gnu list. */
10865 xtensa_reorder_segments ()
10872 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10875 /* Now that we have the last section, push all the literal
10876 sections to the end. */
10877 last_sec
= get_last_sec ();
10878 xtensa_reorder_seg_list (literal_head
, last_sec
);
10879 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10880 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10882 /* Now perform the final error check. */
10883 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10885 assert (new_count
== old_count
);
10892 segT last_sec
= stdoutput
->sections
;
10893 while (last_sec
->next
!= NULL
)
10894 last_sec
= last_sec
->next
;
10900 /* Change the emit state (seg, subseg, and frag related stuff) to the
10901 correct location. Return a emit_state which can be passed to
10902 xtensa_restore_emit_state to return to current fragment. */
10905 xtensa_switch_to_literal_fragment (result
)
10906 emit_state
*result
;
10908 if (directive_state
[directive_absolute_literals
])
10910 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10911 &default_lit_sections
.lit4_seg
, FALSE
);
10912 xtensa_switch_section_emit_state (result
,
10913 default_lit_sections
.lit4_seg
, 0);
10916 xtensa_switch_to_non_abs_literal_fragment (result
);
10918 /* Do a 4-byte align here. */
10919 frag_align (2, 0, 0);
10920 record_alignment (now_seg
, 2);
10925 xtensa_switch_to_non_abs_literal_fragment (result
)
10926 emit_state
*result
;
10928 /* When we mark a literal pool location, we want to put a frag in
10929 the literal pool that points to it. But to do that, we want to
10930 switch_to_literal_fragment. But literal sections don't have
10931 literal pools, so their location is always null, so we would
10932 recurse forever. This is kind of hacky, but it works. */
10934 static bfd_boolean recursive
= FALSE
;
10935 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10936 bfd_boolean is_init
=
10937 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10939 bfd_boolean is_fini
=
10940 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10942 if (pool_location
== NULL
10943 && !use_literal_section
10945 && !is_init
&& ! is_fini
)
10947 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10949 xtensa_mark_literal_pool_location ();
10953 /* Special case: If we are in the ".fini" or ".init" section, then
10954 we will ALWAYS be generating to the ".fini.literal" and
10955 ".init.literal" sections. */
10959 cache_literal_section (init_literal_head
,
10960 default_lit_sections
.init_lit_seg_name
,
10961 &default_lit_sections
.init_lit_seg
, TRUE
);
10962 xtensa_switch_section_emit_state (result
,
10963 default_lit_sections
.init_lit_seg
, 0);
10967 cache_literal_section (fini_literal_head
,
10968 default_lit_sections
.fini_lit_seg_name
,
10969 &default_lit_sections
.fini_lit_seg
, TRUE
);
10970 xtensa_switch_section_emit_state (result
,
10971 default_lit_sections
.fini_lit_seg
, 0);
10975 cache_literal_section (literal_head
,
10976 default_lit_sections
.lit_seg_name
,
10977 &default_lit_sections
.lit_seg
, TRUE
);
10978 xtensa_switch_section_emit_state (result
,
10979 default_lit_sections
.lit_seg
, 0);
10982 if (!use_literal_section
10983 && !is_init
&& !is_fini
10984 && get_literal_pool_location (now_seg
) != pool_location
)
10986 /* Close whatever frag is there. */
10987 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10988 xtensa_set_frag_assembly_state (frag_now
);
10989 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10990 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10991 xtensa_set_frag_assembly_state (frag_now
);
10996 /* Call this function before emitting data into the literal section.
10997 This is a helper function for xtensa_switch_to_literal_fragment.
10998 This is similar to a .section new_now_seg subseg. */
11001 xtensa_switch_section_emit_state (state
, new_now_seg
, new_now_subseg
)
11004 subsegT new_now_subseg
;
11006 state
->name
= now_seg
->name
;
11007 state
->now_seg
= now_seg
;
11008 state
->now_subseg
= now_subseg
;
11009 state
->generating_literals
= generating_literals
;
11010 generating_literals
++;
11011 subseg_new (segment_name (new_now_seg
), new_now_subseg
);
11015 /* Use to restore the emitting into the normal place. */
11018 xtensa_restore_emit_state (state
)
11021 generating_literals
= state
->generating_literals
;
11022 subseg_new (state
->name
, state
->now_subseg
);
11026 /* Get a segment of a given name. If the segment is already
11027 present, return it; otherwise, create a new one. */
11030 cache_literal_section (head
, name
, seg
, is_code
)
11034 bfd_boolean is_code
;
11036 segT current_section
= now_seg
;
11037 int current_subsec
= now_subseg
;
11041 *seg
= retrieve_literal_seg (head
, name
, is_code
);
11042 subseg_set (current_section
, current_subsec
);
11046 /* Get a segment of a given name. If the segment is already
11047 present, return it; otherwise, create a new one. */
11050 retrieve_literal_seg (head
, name
, is_code
)
11053 bfd_boolean is_code
;
11057 ret
= seg_present (name
);
11060 ret
= subseg_new (name
, (subsegT
) 0);
11062 add_seg_list (head
, ret
);
11063 bfd_set_section_flags (stdoutput
, ret
, SEC_HAS_CONTENTS
|
11064 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11065 | (is_code
? SEC_CODE
: SEC_DATA
));
11066 bfd_set_section_alignment (stdoutput
, ret
, 2);
11073 /* Return a segment of a given name if it is present. */
11080 seg
= stdoutput
->sections
;
11084 if (!strcmp (segment_name (seg
), name
))
11093 /* Add a segment to a segment list. */
11096 add_seg_list (head
, seg
)
11101 n
= (seg_list
*) xmalloc (sizeof (seg_list
));
11105 n
->next
= head
->next
;
11110 /* Property Tables Stuff. */
11112 /* This function is only meaningful after xtensa_move_literals. */
11115 get_frag_is_literal (fragP
)
11116 const fragS
*fragP
;
11118 assert (fragP
!= NULL
);
11119 return fragP
->tc_frag_data
.is_literal
;
11124 get_frag_is_insn (fragP
)
11125 const fragS
*fragP
;
11127 assert (fragP
!= NULL
);
11128 return fragP
->tc_frag_data
.is_insn
;
11133 get_frag_is_no_transform (fragP
)
11136 return fragP
->tc_frag_data
.is_no_transform
;
11141 set_frag_is_specific_opcode (fragP
, is_specific_opcode
)
11143 bfd_boolean is_specific_opcode
;
11145 fragP
->tc_frag_data
.is_specific_opcode
= is_specific_opcode
;
11150 set_frag_is_no_transform (fragP
, is_no_transform
)
11152 bfd_boolean is_no_transform
;
11154 fragP
->tc_frag_data
.is_no_transform
= is_no_transform
;
11159 xtensa_create_property_segments (property_function
, end_property_function
,
11160 section_name_base
, sec_type
)
11161 frag_predicate property_function
;
11162 frag_predicate end_property_function
;
11163 const char *section_name_base
;
11164 xt_section_type sec_type
;
11168 /* Walk over all of the current segments.
11169 Walk over each fragment
11170 For each non-empty fragment,
11171 Build a property record (append where possible). */
11173 for (seclist
= &stdoutput
->sections
;
11174 seclist
&& *seclist
;
11175 seclist
= &(*seclist
)->next
)
11177 segT sec
= *seclist
;
11180 flags
= bfd_get_section_flags (stdoutput
, sec
);
11181 if (flags
& SEC_DEBUGGING
)
11183 if (!(flags
& SEC_ALLOC
))
11186 if (section_has_property (sec
, property_function
))
11188 char *property_section_name
=
11189 xtensa_get_property_section_name (sec
, section_name_base
);
11190 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
11191 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
11192 xtensa_block_info
**xt_blocks
=
11193 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11194 /* Walk over all of the frchains here and add new sections. */
11195 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
11196 end_property_function
);
11200 /* Now we fill them out.... */
11202 for (seclist
= &stdoutput
->sections
;
11203 seclist
&& *seclist
;
11204 seclist
= &(*seclist
)->next
)
11206 segment_info_type
*seginfo
;
11207 xtensa_block_info
*block
;
11208 segT sec
= *seclist
;
11210 seginfo
= seg_info (sec
);
11211 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11215 xtensa_block_info
*cur_block
;
11216 /* This is a section with some data. */
11220 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11223 rec_size
= num_recs
* 8;
11224 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11226 /* In order to make this work with the assembler, we have to
11227 build some frags and then build the "fixups" for it. It
11228 would be easier to just set the contents then set the
11233 /* Allocate a fragment and leak it. */
11237 frchainS
*frchainP
;
11241 frag_size
= sizeof (fragS
) + rec_size
;
11242 fragP
= (fragS
*) xmalloc (frag_size
);
11244 memset (fragP
, 0, frag_size
);
11245 fragP
->fr_address
= 0;
11246 fragP
->fr_next
= NULL
;
11247 fragP
->fr_fix
= rec_size
;
11249 fragP
->fr_type
= rs_fill
;
11250 /* The rest are zeros. */
11252 frchainP
= seginfo
->frchainP
;
11253 frchainP
->frch_root
= fragP
;
11254 frchainP
->frch_last
= fragP
;
11256 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
11257 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
11259 seginfo
->fix_root
= fixes
;
11260 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
11262 frag_data
= &fragP
->fr_literal
[0];
11263 for (i
= 0; i
< num_recs
; i
++)
11265 fixS
*fix
= &fixes
[i
];
11266 assert (cur_block
);
11268 /* Write the fixup. */
11269 if (i
!= num_recs
- 1)
11270 fix
->fx_next
= &fixes
[i
+ 1];
11272 fix
->fx_next
= NULL
;
11275 fix
->fx_frag
= fragP
;
11276 fix
->fx_where
= i
* 8;
11277 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
11278 fix
->fx_offset
= cur_block
->offset
;
11279 fix
->fx_r_type
= BFD_RELOC_32
;
11280 fix
->fx_file
= "Internal Assembly";
11283 /* Write the length. */
11284 md_number_to_chars (&frag_data
[4 + 8 * i
],
11285 cur_block
->size
, 4);
11286 cur_block
= cur_block
->next
;
11295 xtensa_create_xproperty_segments (flag_fn
, section_name_base
, sec_type
)
11296 frag_flags_fn flag_fn
;
11297 const char *section_name_base
;
11298 xt_section_type sec_type
;
11302 /* Walk over all of the current segments.
11303 Walk over each fragment.
11304 For each fragment that has instructions,
11305 build an instruction record (append where possible). */
11307 for (seclist
= &stdoutput
->sections
;
11308 seclist
&& *seclist
;
11309 seclist
= &(*seclist
)->next
)
11311 segT sec
= *seclist
;
11314 flags
= bfd_get_section_flags (stdoutput
, sec
);
11315 if (flags
& SEC_DEBUGGING
)
11317 if (!(flags
& SEC_ALLOC
))
11320 if (section_has_xproperty (sec
, flag_fn
))
11322 char *property_section_name
=
11323 xtensa_get_property_section_name (sec
, section_name_base
);
11324 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
11325 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
11326 xtensa_block_info
**xt_blocks
=
11327 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11328 /* Walk over all of the frchains here and add new sections. */
11329 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
11333 /* Now we fill them out.... */
11335 for (seclist
= &stdoutput
->sections
;
11336 seclist
&& *seclist
;
11337 seclist
= &(*seclist
)->next
)
11339 segment_info_type
*seginfo
;
11340 xtensa_block_info
*block
;
11341 segT sec
= *seclist
;
11343 seginfo
= seg_info (sec
);
11344 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11348 xtensa_block_info
*cur_block
;
11349 /* This is a section with some data. */
11353 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11356 rec_size
= num_recs
* (8 + 4);
11357 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11359 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11361 /* In order to make this work with the assembler, we have to build
11362 some frags then build the "fixups" for it. It would be easier to
11363 just set the contents then set the arlents. */
11367 /* Allocate a fragment and (unfortunately) leak it. */
11371 frchainS
*frchainP
;
11375 frag_size
= sizeof (fragS
) + rec_size
;
11376 fragP
= (fragS
*) xmalloc (frag_size
);
11378 memset (fragP
, 0, frag_size
);
11379 fragP
->fr_address
= 0;
11380 fragP
->fr_next
= NULL
;
11381 fragP
->fr_fix
= rec_size
;
11383 fragP
->fr_type
= rs_fill
;
11384 /* The rest are zeros. */
11386 frchainP
= seginfo
->frchainP
;
11387 frchainP
->frch_root
= fragP
;
11388 frchainP
->frch_last
= fragP
;
11390 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
11391 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
11393 seginfo
->fix_root
= fixes
;
11394 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
11396 frag_data
= &fragP
->fr_literal
[0];
11397 for (i
= 0; i
< num_recs
; i
++)
11399 fixS
*fix
= &fixes
[i
];
11400 assert (cur_block
);
11402 /* Write the fixup. */
11403 if (i
!= num_recs
- 1)
11404 fix
->fx_next
= &fixes
[i
+ 1];
11406 fix
->fx_next
= NULL
;
11409 fix
->fx_frag
= fragP
;
11410 fix
->fx_where
= i
* (8 + 4);
11411 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
11412 fix
->fx_offset
= cur_block
->offset
;
11413 fix
->fx_r_type
= BFD_RELOC_32
;
11414 fix
->fx_file
= "Internal Assembly";
11417 /* Write the length. */
11418 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
11419 cur_block
->size
, 4);
11420 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
11421 frag_flags_to_number (&cur_block
->flags
),
11423 cur_block
= cur_block
->next
;
11431 segment_info_type
*
11432 retrieve_segment_info (seg
)
11435 segment_info_type
*seginfo
;
11436 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
11439 frchainS
*frchainP
;
11441 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
11442 memset ((PTR
) seginfo
, 0, sizeof (*seginfo
));
11443 seginfo
->fix_root
= NULL
;
11444 seginfo
->fix_tail
= NULL
;
11445 seginfo
->bfd_section
= seg
;
11447 /* We will not be dealing with these, only our special ones. */
11449 if (seg
== bfd_abs_section_ptr
)
11450 abs_seg_info
= seginfo
;
11451 else if (seg
== bfd_und_section_ptr
)
11452 und_seg_info
= seginfo
;
11455 bfd_set_section_userdata (stdoutput
, seg
, (PTR
) seginfo
);
11457 seg_fix_rootP
= &segment_info
[seg
].fix_root
;
11458 seg_fix_tailP
= &segment_info
[seg
].fix_tail
;
11461 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
11462 frchainP
->frch_root
= NULL
;
11463 frchainP
->frch_last
= NULL
;
11464 frchainP
->frch_next
= NULL
;
11465 frchainP
->frch_seg
= seg
;
11466 frchainP
->frch_subseg
= 0;
11467 frchainP
->fix_root
= NULL
;
11468 frchainP
->fix_tail
= NULL
;
11469 /* Do not init the objstack. */
11470 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
11471 /* frchainP->frch_frag_now = fragP; */
11472 frchainP
->frch_frag_now
= NULL
;
11474 seginfo
->frchainP
= frchainP
;
11482 retrieve_xtensa_section (sec_name
)
11485 bfd
*abfd
= stdoutput
;
11486 flagword flags
, out_flags
, link_once_flags
;
11489 flags
= bfd_get_section_flags (abfd
, now_seg
);
11490 link_once_flags
= (flags
& SEC_LINK_ONCE
);
11491 if (link_once_flags
)
11492 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
11493 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
11495 s
= bfd_make_section_old_way (abfd
, sec_name
);
11497 as_bad (_("could not create section %s"), sec_name
);
11498 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
11499 as_bad (_("invalid flag combination on section %s"), sec_name
);
11506 section_has_property (sec
, property_function
)
11508 frag_predicate property_function
;
11510 segment_info_type
*seginfo
= seg_info (sec
);
11513 if (seginfo
&& seginfo
->frchainP
)
11515 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11517 if (property_function (fragP
)
11518 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11527 section_has_xproperty (sec
, property_function
)
11529 frag_flags_fn property_function
;
11531 segment_info_type
*seginfo
= seg_info (sec
);
11534 if (seginfo
&& seginfo
->frchainP
)
11536 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11538 frag_flags prop_flags
;
11539 property_function (fragP
, &prop_flags
);
11540 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11548 /* Two types of block sections exist right now: literal and insns. */
11551 add_xt_block_frags (sec
, xt_block_sec
, xt_block
, property_function
,
11552 end_property_function
)
11555 xtensa_block_info
**xt_block
;
11556 frag_predicate property_function
;
11557 frag_predicate end_property_function
;
11559 segment_info_type
*seg_info
;
11560 segment_info_type
*xt_seg_info
;
11561 bfd_vma seg_offset
;
11564 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
11565 seg_info
= retrieve_segment_info (sec
);
11567 /* Build it if needed. */
11568 while (*xt_block
!= NULL
)
11569 xt_block
= &(*xt_block
)->next
;
11570 /* We are either at NULL at the beginning or at the end. */
11572 /* Walk through the frags. */
11575 if (seg_info
->frchainP
)
11577 for (fragP
= seg_info
->frchainP
->frch_root
;
11579 fragP
= fragP
->fr_next
)
11581 if (property_function (fragP
)
11582 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11584 if (*xt_block
!= NULL
)
11586 if ((*xt_block
)->offset
+ (*xt_block
)->size
11587 == fragP
->fr_address
)
11588 (*xt_block
)->size
+= fragP
->fr_fix
;
11590 xt_block
= &((*xt_block
)->next
);
11592 if (*xt_block
== NULL
)
11594 xtensa_block_info
*new_block
= (xtensa_block_info
*)
11595 xmalloc (sizeof (xtensa_block_info
));
11596 new_block
->sec
= sec
;
11597 new_block
->offset
= fragP
->fr_address
;
11598 new_block
->size
= fragP
->fr_fix
;
11599 new_block
->next
= NULL
;
11600 xtensa_frag_flags_init (&new_block
->flags
);
11601 *xt_block
= new_block
;
11603 if (end_property_function
11604 && end_property_function (fragP
))
11606 xt_block
= &((*xt_block
)->next
);
11614 /* Break the encapsulation of add_xt_prop_frags here. */
11617 xtensa_frag_flags_is_empty (prop_flags
)
11618 const frag_flags
*prop_flags
;
11620 if (prop_flags
->is_literal
11621 || prop_flags
->is_insn
11622 || prop_flags
->is_data
11623 || prop_flags
->is_unreachable
)
11630 xtensa_frag_flags_init (prop_flags
)
11631 frag_flags
*prop_flags
;
11633 memset (prop_flags
, 0, sizeof (frag_flags
));
11638 get_frag_property_flags (fragP
, prop_flags
)
11639 const fragS
*fragP
;
11640 frag_flags
*prop_flags
;
11642 xtensa_frag_flags_init (prop_flags
);
11643 if (fragP
->tc_frag_data
.is_literal
)
11644 prop_flags
->is_literal
= TRUE
;
11645 if (fragP
->tc_frag_data
.is_unreachable
)
11647 prop_flags
->is_unreachable
= TRUE
;
11649 else if (fragP
->tc_frag_data
.is_insn
)
11651 prop_flags
->is_insn
= TRUE
;
11652 if (fragP
->tc_frag_data
.is_loop_target
)
11653 prop_flags
->insn
.is_loop_target
= TRUE
;
11654 if (fragP
->tc_frag_data
.is_branch_target
)
11655 prop_flags
->insn
.is_branch_target
= TRUE
;
11656 if (fragP
->tc_frag_data
.is_specific_opcode
11657 || fragP
->tc_frag_data
.is_no_transform
)
11658 prop_flags
->insn
.is_no_transform
= TRUE
;
11659 if (fragP
->tc_frag_data
.is_no_density
)
11660 prop_flags
->insn
.is_no_density
= TRUE
;
11661 if (fragP
->tc_frag_data
.use_absolute_literals
)
11662 prop_flags
->insn
.is_abslit
= TRUE
;
11664 if (fragP
->tc_frag_data
.is_align
)
11666 prop_flags
->is_align
= TRUE
;
11667 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
11668 if (xtensa_frag_flags_is_empty (prop_flags
))
11669 prop_flags
->is_data
= TRUE
;
11675 frag_flags_to_number (prop_flags
)
11676 const frag_flags
*prop_flags
;
11679 if (prop_flags
->is_literal
)
11680 num
|= XTENSA_PROP_LITERAL
;
11681 if (prop_flags
->is_insn
)
11682 num
|= XTENSA_PROP_INSN
;
11683 if (prop_flags
->is_data
)
11684 num
|= XTENSA_PROP_DATA
;
11685 if (prop_flags
->is_unreachable
)
11686 num
|= XTENSA_PROP_UNREACHABLE
;
11687 if (prop_flags
->insn
.is_loop_target
)
11688 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
11689 if (prop_flags
->insn
.is_branch_target
)
11691 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
11692 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
11695 if (prop_flags
->insn
.is_no_density
)
11696 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
11697 if (prop_flags
->insn
.is_no_transform
)
11698 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
11699 if (prop_flags
->insn
.is_no_reorder
)
11700 num
|= XTENSA_PROP_INSN_NO_REORDER
;
11701 if (prop_flags
->insn
.is_abslit
)
11702 num
|= XTENSA_PROP_INSN_ABSLIT
;
11704 if (prop_flags
->is_align
)
11706 num
|= XTENSA_PROP_ALIGN
;
11707 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
11715 xtensa_frag_flags_combinable (prop_flags_1
, prop_flags_2
)
11716 const frag_flags
*prop_flags_1
;
11717 const frag_flags
*prop_flags_2
;
11719 /* Cannot combine with an end marker. */
11721 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
11723 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
11725 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
11728 if (prop_flags_1
->is_insn
)
11730 /* Properties of the beginning of the frag. */
11731 if (prop_flags_2
->insn
.is_loop_target
)
11733 if (prop_flags_2
->insn
.is_branch_target
)
11735 if (prop_flags_1
->insn
.is_no_density
!=
11736 prop_flags_2
->insn
.is_no_density
)
11738 if (prop_flags_1
->insn
.is_no_transform
!=
11739 prop_flags_2
->insn
.is_no_transform
)
11741 if (prop_flags_1
->insn
.is_no_reorder
!=
11742 prop_flags_2
->insn
.is_no_reorder
)
11744 if (prop_flags_1
->insn
.is_abslit
!=
11745 prop_flags_2
->insn
.is_abslit
)
11749 if (prop_flags_1
->is_align
)
11757 xt_block_aligned_size (xt_block
)
11758 const xtensa_block_info
*xt_block
;
11763 if (!xt_block
->flags
.is_align
)
11764 return xt_block
->size
;
11766 end_addr
= xt_block
->offset
+ xt_block
->size
;
11767 align_bits
= xt_block
->flags
.alignment
;
11768 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11769 return end_addr
- xt_block
->offset
;
11774 xtensa_xt_block_combine (xt_block
, xt_block_2
)
11775 xtensa_block_info
*xt_block
;
11776 const xtensa_block_info
*xt_block_2
;
11778 if (xt_block
->sec
!= xt_block_2
->sec
)
11780 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11781 != xt_block_2
->offset
)
11784 if (xt_block_2
->size
== 0
11785 && (!xt_block_2
->flags
.is_unreachable
11786 || xt_block
->flags
.is_unreachable
))
11788 if (xt_block_2
->flags
.is_align
11789 && xt_block
->flags
.is_align
)
11791 /* Nothing needed. */
11792 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11797 if (xt_block_2
->flags
.is_align
)
11799 /* Push alignment to previous entry. */
11800 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11801 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11806 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11807 &xt_block_2
->flags
))
11810 xt_block
->size
+= xt_block_2
->size
;
11812 if (xt_block_2
->flags
.is_align
)
11814 xt_block
->flags
.is_align
= TRUE
;
11815 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11823 add_xt_prop_frags (sec
, xt_block_sec
, xt_block
, property_function
)
11826 xtensa_block_info
**xt_block
;
11827 frag_flags_fn property_function
;
11829 segment_info_type
*seg_info
;
11830 segment_info_type
*xt_seg_info
;
11831 bfd_vma seg_offset
;
11834 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
11835 seg_info
= retrieve_segment_info (sec
);
11836 /* Build it if needed. */
11837 while (*xt_block
!= NULL
)
11839 xt_block
= &(*xt_block
)->next
;
11841 /* We are either at NULL at the beginning or at the end. */
11843 /* Walk through the frags. */
11846 if (seg_info
->frchainP
)
11848 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
11849 fragP
= fragP
->fr_next
)
11851 xtensa_block_info tmp_block
;
11852 tmp_block
.sec
= sec
;
11853 tmp_block
.offset
= fragP
->fr_address
;
11854 tmp_block
.size
= fragP
->fr_fix
;
11855 tmp_block
.next
= NULL
;
11856 property_function (fragP
, &tmp_block
.flags
);
11858 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11859 /* && fragP->fr_fix != 0) */
11861 if ((*xt_block
) == NULL
11862 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11864 xtensa_block_info
*new_block
;
11865 if ((*xt_block
) != NULL
)
11866 xt_block
= &(*xt_block
)->next
;
11867 new_block
= (xtensa_block_info
*)
11868 xmalloc (sizeof (xtensa_block_info
));
11869 *new_block
= tmp_block
;
11870 *xt_block
= new_block
;
11878 /* op_placement_info_table */
11880 /* op_placement_info makes it easier to determine which
11881 ops can go in which slots. */
11884 init_op_placement_info_table ()
11886 xtensa_isa isa
= xtensa_default_isa
;
11887 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11888 xtensa_opcode opcode
;
11891 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11893 op_placement_table
= (op_placement_info_table
)
11894 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11895 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11897 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11899 op_placement_info
*opi
= &op_placement_table
[opcode
];
11900 /* FIXME: Make tinsn allocation dynamic. */
11901 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
11902 as_fatal (_("too many operands in instruction"));
11903 opi
->single
= XTENSA_UNDEFINED
;
11904 opi
->single_size
= 0;
11905 opi
->widest
= XTENSA_UNDEFINED
;
11906 opi
->widest_size
= 0;
11907 opi
->narrowest
= XTENSA_UNDEFINED
;
11908 opi
->narrowest_size
= 0x7F;
11910 opi
->num_formats
= 0;
11912 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11914 opi
->slots
[fmt
] = 0;
11915 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11917 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11919 int fmt_length
= xtensa_format_length (isa
, fmt
);
11921 set_bit (fmt
, opi
->formats
);
11922 set_bit (slot
, opi
->slots
[fmt
]);
11923 /* opi->slot_count[fmt]++; */
11924 if (fmt_length
< opi
->narrowest_size
)
11926 opi
->narrowest
= fmt
;
11927 opi
->narrowest_size
= fmt_length
;
11929 if (fmt_length
> opi
->widest_size
)
11932 opi
->widest_size
= fmt_length
;
11934 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11936 if (opi
->single_size
== 0
11937 || fmt_length
< opi
->single_size
)
11940 opi
->single_size
= fmt_length
;
11946 opi
->num_formats
++;
11949 xtensa_insnbuf_free (isa
, ibuf
);
11954 opcode_fits_format_slot (opcode
, fmt
, slot
)
11955 xtensa_opcode opcode
;
11959 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11963 /* If the opcode is available in a single slot format, return its size. */
11966 xg_get_single_size (opcode
)
11967 xtensa_opcode opcode
;
11969 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11970 return op_placement_table
[opcode
].single_size
;
11975 xg_get_single_format (opcode
)
11976 xtensa_opcode opcode
;
11978 return op_placement_table
[opcode
].single
;
11982 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11985 istack_init (stack
)
11988 memset (stack
, 0, sizeof (IStack
));
11994 istack_empty (stack
)
11997 return (stack
->ninsn
== 0);
12002 istack_full (stack
)
12005 return (stack
->ninsn
== MAX_ISTACK
);
12009 /* Return a pointer to the top IStack entry.
12010 It is an error to call this if istack_empty () is TRUE. */
12016 int rec
= stack
->ninsn
- 1;
12017 assert (!istack_empty (stack
));
12018 return &stack
->insn
[rec
];
12022 /* Add a new TInsn to an IStack.
12023 It is an error to call this if istack_full () is TRUE. */
12026 istack_push (stack
, insn
)
12030 int rec
= stack
->ninsn
;
12031 assert (!istack_full (stack
));
12032 stack
->insn
[rec
] = *insn
;
12037 /* Clear space for the next TInsn on the IStack and return a pointer
12038 to it. It is an error to call this if istack_full () is TRUE. */
12041 istack_push_space (stack
)
12044 int rec
= stack
->ninsn
;
12046 assert (!istack_full (stack
));
12047 insn
= &stack
->insn
[rec
];
12048 memset (insn
, 0, sizeof (TInsn
));
12054 /* Remove the last pushed instruction. It is an error to call this if
12055 istack_empty () returns TRUE. */
12061 int rec
= stack
->ninsn
- 1;
12062 assert (!istack_empty (stack
));
12064 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
12068 /* TInsn functions. */
12074 memset (dst
, 0, sizeof (TInsn
));
12078 /* Get the ``num''th token of the TInsn.
12079 It is illegal to call this if num > insn->ntoks. */
12082 tinsn_get_tok (insn
, num
)
12086 assert (num
< insn
->ntok
);
12087 return &insn
->tok
[num
];
12091 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12094 tinsn_has_symbolic_operands (insn
)
12098 int n
= insn
->ntok
;
12100 assert (insn
->insn_type
== ITYPE_INSN
);
12102 for (i
= 0; i
< n
; ++i
)
12104 switch (insn
->tok
[i
].X_op
)
12118 tinsn_has_invalid_symbolic_operands (insn
)
12121 xtensa_isa isa
= xtensa_default_isa
;
12123 int n
= insn
->ntok
;
12125 assert (insn
->insn_type
== ITYPE_INSN
);
12127 for (i
= 0; i
< n
; ++i
)
12129 switch (insn
->tok
[i
].X_op
)
12137 /* Errors for these types are caught later. */
12142 /* Symbolic immediates are only allowed on the last immediate
12143 operand. At this time, CONST16 is the only opcode where we
12144 support non-PC-relative relocations. (It isn't necessary
12145 to complain about non-PC-relative relocations here, but
12146 otherwise, no error is reported until the relocations are
12147 generated, and the assembler won't get that far if there
12148 are any other errors. It's nice to see all the problems
12150 if (i
!= get_relaxable_immed (insn
->opcode
)
12151 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12152 && insn
->opcode
!= xtensa_const16_opcode
))
12154 as_bad (_("invalid symbolic operand %d on '%s'"),
12155 i
, xtensa_opcode_name (isa
, insn
->opcode
));
12164 /* For assembly code with complex expressions (e.g. subtraction),
12165 we have to build them in the literal pool so that
12166 their results are calculated correctly after relaxation.
12167 The relaxation only handles expressions that
12168 boil down to SYMBOL + OFFSET. */
12171 tinsn_has_complex_operands (insn
)
12175 int n
= insn
->ntok
;
12176 assert (insn
->insn_type
== ITYPE_INSN
);
12177 for (i
= 0; i
< n
; ++i
)
12179 switch (insn
->tok
[i
].X_op
)
12195 /* Convert the constant operands in the tinsn to insnbuf.
12196 Return TRUE if there is a symbol in the immediate field.
12198 Before this is called,
12199 1) the number of operands are correct
12200 2) the tinsn is a ITYPE_INSN
12201 3) ONLY the relaxable_ is built
12202 4) All operands are O_constant, O_symbol. All constants fit
12203 The return value tells whether there are any remaining O_symbols. */
12206 tinsn_to_insnbuf (tinsn
, insnbuf
)
12208 xtensa_insnbuf insnbuf
;
12210 static xtensa_insnbuf slotbuf
= 0;
12211 xtensa_isa isa
= xtensa_default_isa
;
12212 xtensa_opcode opcode
= tinsn
->opcode
;
12213 xtensa_format fmt
= xg_get_single_format (opcode
);
12214 bfd_boolean has_fixup
= FALSE
;
12215 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12222 slotbuf
= xtensa_insnbuf_alloc (isa
);
12224 assert (tinsn
->insn_type
== ITYPE_INSN
);
12225 if (noperands
!= tinsn
->ntok
)
12226 as_fatal (_("operand number mismatch"));
12228 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
12229 as_fatal (_("cannot encode opcode"));
12231 for (i
= 0; i
< noperands
; ++i
)
12233 expressionS
*expr
= &tinsn
->tok
[i
];
12234 switch (expr
->X_op
)
12237 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12239 /* The register number has already been checked in
12240 expression_maybe_register, so we don't need to check here. */
12241 opnd_value
= expr
->X_add_number
;
12242 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12243 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
12244 slotbuf
, opnd_value
);
12248 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12250 as_where (&file_name
, &line
);
12251 /* It is a constant and we called this function,
12252 then we have to try to fit it. */
12253 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
12254 expr
->X_add_number
, file_name
, line
);
12263 xtensa_format_encode (isa
, fmt
, insnbuf
);
12264 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
12270 /* Convert the constant operands in the tinsn to slotbuf.
12271 Return TRUE if there is a symbol in the immediate field.
12272 (Eventually this should replace tinsn_to_insnbuf.) */
12274 /* Before this is called,
12275 1) the number of operands are correct
12276 2) the tinsn is a ITYPE_INSN
12277 3) ONLY the relaxable_ is built
12278 4) All operands are
12279 O_constant, O_symbol
12282 The return value tells whether there are any remaining O_symbols. */
12285 tinsn_to_slotbuf (fmt
, slot
, tinsn
, slotbuf
)
12289 xtensa_insnbuf slotbuf
;
12291 xtensa_isa isa
= xtensa_default_isa
;
12292 xtensa_opcode opcode
= tinsn
->opcode
;
12293 bfd_boolean has_fixup
= FALSE
;
12294 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12297 *((int *) &slotbuf
[0]) = 0;
12298 *((int *) &slotbuf
[1]) = 0;
12299 assert (tinsn
->insn_type
== ITYPE_INSN
);
12300 if (noperands
!= tinsn
->ntok
)
12301 as_fatal (_("operand number mismatch"));
12303 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12305 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12306 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12310 for (i
= 0; i
< noperands
; i
++)
12312 expressionS
*expr
= &tinsn
->tok
[i
];
12317 switch (expr
->X_op
)
12320 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12322 /* The register number has already been checked in
12323 expression_maybe_register, so we don't need to check here. */
12324 opnd_value
= expr
->X_add_number
;
12325 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12326 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12329 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12333 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12335 as_where (&file_name
, &line
);
12336 /* It is a constant and we called this function
12337 then we have to try to fit it. */
12338 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12339 expr
->X_add_number
, file_name
, line
);
12352 /* Check the instruction arguments. Return TRUE on failure. */
12355 tinsn_check_arguments (insn
)
12358 xtensa_isa isa
= xtensa_default_isa
;
12359 xtensa_opcode opcode
= insn
->opcode
;
12361 if (opcode
== XTENSA_UNDEFINED
)
12363 as_bad (_("invalid opcode"));
12367 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12369 as_bad (_("too few operands"));
12373 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12375 as_bad (_("too many operands"));
12382 /* Load an instruction from its encoded form. */
12385 tinsn_from_chars (tinsn
, f
, slot
)
12392 xg_init_vinsn (&vinsn
);
12393 vinsn_from_chars (&vinsn
, f
);
12395 *tinsn
= vinsn
.slots
[slot
];
12396 xg_free_vinsn (&vinsn
);
12401 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, slot
)
12403 xtensa_insnbuf slotbuf
;
12408 xtensa_isa isa
= xtensa_default_isa
;
12410 /* Find the immed. */
12411 tinsn_init (tinsn
);
12412 tinsn
->insn_type
= ITYPE_INSN
;
12413 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12414 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12415 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12416 for (i
= 0; i
< tinsn
->ntok
; i
++)
12418 set_expr_const (&tinsn
->tok
[i
],
12419 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12420 tinsn
->opcode
, i
));
12425 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12428 tinsn_immed_from_frag (tinsn
, fragP
, slot
)
12433 xtensa_opcode opcode
= tinsn
->opcode
;
12436 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12438 opnum
= get_relaxable_immed (opcode
);
12439 assert (opnum
>= 0);
12440 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
12442 set_expr_symbol_offset_diff
12443 (&tinsn
->tok
[opnum
],
12444 fragP
->tc_frag_data
.slot_symbols
[slot
],
12445 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
12446 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12450 set_expr_symbol_offset
12451 (&tinsn
->tok
[opnum
],
12452 fragP
->tc_frag_data
.slot_symbols
[slot
],
12453 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12460 get_num_stack_text_bytes (istack
)
12464 int text_bytes
= 0;
12466 for (i
= 0; i
< istack
->ninsn
; i
++)
12468 TInsn
*tinsn
= &istack
->insn
[i
];
12469 if (tinsn
->insn_type
== ITYPE_INSN
)
12470 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12477 get_num_stack_literal_bytes (istack
)
12483 for (i
= 0; i
< istack
->ninsn
; i
++)
12485 TInsn
*tinsn
= &istack
->insn
[i
];
12486 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12493 /* vliw_insn functions. */
12500 xtensa_isa isa
= xtensa_default_isa
;
12502 xg_clear_vinsn (v
);
12504 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12505 if (v
->insnbuf
== NULL
)
12506 as_fatal (_("out of memory"));
12508 for (i
= 0; i
< MAX_SLOTS
; i
++)
12510 tinsn_init (&v
->slots
[i
]);
12511 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12512 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12513 if (v
->slotbuf
[i
] == NULL
)
12514 as_fatal (_("out of memory"));
12524 v
->format
= XTENSA_UNDEFINED
;
12526 v
->inside_bundle
= FALSE
;
12528 if (xt_saved_debug_type
!= DEBUG_NONE
)
12529 debug_type
= xt_saved_debug_type
;
12531 for (i
= 0; i
< MAX_SLOTS
; i
++)
12533 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
12534 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12540 vinsn_has_specific_opcodes (v
)
12545 for (i
= 0; i
< v
->num_slots
; i
++)
12547 if (v
->slots
[i
].is_specific_opcode
)
12559 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12560 for (i
= 0; i
< MAX_SLOTS
; i
++)
12561 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12565 /* Before this is called, we should have
12566 filled out the following fields:
12568 1) the number of operands for each opcode are correct
12569 2) the tinsn in the slots are ITYPE_INSN
12570 3) ONLY the relaxable_ is built
12571 4) All operands are
12572 O_constant, O_symbol
12575 The return value tells whether there are any remaining O_symbols. */
12578 vinsn_to_insnbuf (vinsn
, frag_offset
, fragP
, record_fixup
)
12582 bfd_boolean record_fixup
;
12584 xtensa_isa isa
= xtensa_default_isa
;
12585 xtensa_format fmt
= vinsn
->format
;
12586 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12588 bfd_boolean has_fixup
= FALSE
;
12590 xtensa_format_encode (isa
, fmt
, insnbuf
);
12592 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12594 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12595 bfd_boolean tinsn_has_fixup
=
12596 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12597 vinsn
->slotbuf
[slot
]);
12599 xtensa_format_set_slot (isa
, fmt
, slot
,
12600 insnbuf
, vinsn
->slotbuf
[slot
]);
12601 /* tinsn_has_fixup tracks if there is a fixup at all.
12602 record_fixup controls globally. I.E., we use this
12603 function from several places, some of which are after
12604 fixups have already been recorded. Finally,
12605 tinsn->record_fixup controls based on the individual ops,
12606 which may or may not need it based on the relaxation
12608 if (tinsn_has_fixup
&& record_fixup
)
12611 xtensa_opcode opcode
= tinsn
->opcode
;
12612 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12615 for (i
= 0; i
< noperands
; i
++)
12617 expressionS
* expr
= &tinsn
->tok
[i
];
12618 switch (expr
->X_op
)
12623 if (get_relaxable_immed (opcode
) == i
)
12625 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
12627 if (!xg_add_opcode_fix
12628 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
12629 frag_offset
- fragP
->fr_literal
))
12630 as_bad (_("instruction with constant operands does not fit"));
12634 tinsn
->symbol
= expr
->X_add_symbol
;
12635 tinsn
->offset
= expr
->X_add_number
;
12639 as_bad (_("invalid operand %d on '%s'"),
12640 i
, xtensa_opcode_name (isa
, opcode
));
12648 if (get_relaxable_immed (opcode
) == i
)
12650 if (tinsn
->record_fix
)
12651 as_bad (_("invalid subtract operand"));
12654 tinsn
->symbol
= expr
->X_add_symbol
;
12655 tinsn
->sub_symbol
= expr
->X_op_symbol
;
12656 tinsn
->offset
= expr
->X_add_number
;
12660 as_bad (_("invalid operand %d on '%s'"),
12661 i
, xtensa_opcode_name (isa
, opcode
));
12665 as_bad (_("invalid expression for operand %d on '%s'"),
12666 i
, xtensa_opcode_name (isa
, opcode
));
12678 vinsn_from_chars (vinsn
, f
)
12682 static xtensa_insnbuf insnbuf
= NULL
;
12683 static xtensa_insnbuf slotbuf
= NULL
;
12686 xtensa_isa isa
= xtensa_default_isa
;
12690 insnbuf
= xtensa_insnbuf_alloc (isa
);
12691 slotbuf
= xtensa_insnbuf_alloc (isa
);
12694 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
12695 fmt
= xtensa_format_decode (isa
, insnbuf
);
12696 if (fmt
== XTENSA_UNDEFINED
)
12697 as_fatal (_("cannot decode instruction format"));
12698 vinsn
->format
= fmt
;
12699 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12701 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12703 TInsn
*tinsn
= &vinsn
->slots
[i
];
12704 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
12705 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
12710 /* Expression utilities. */
12712 /* Return TRUE if the expression is an integer constant. */
12716 const expressionS
*s
;
12718 return (s
->X_op
== O_constant
);
12722 /* Get the expression constant.
12723 Calling this is illegal if expr_is_const () returns TRUE. */
12727 const expressionS
*s
;
12729 assert (expr_is_const (s
));
12730 return s
->X_add_number
;
12734 /* Set the expression to a constant value. */
12737 set_expr_const (s
, val
)
12741 s
->X_op
= O_constant
;
12742 s
->X_add_number
= val
;
12743 s
->X_add_symbol
= NULL
;
12744 s
->X_op_symbol
= NULL
;
12749 expr_is_register (s
)
12750 const expressionS
*s
;
12752 return (s
->X_op
== O_register
);
12756 /* Get the expression constant.
12757 Calling this is illegal if expr_is_const () returns TRUE. */
12760 get_expr_register (s
)
12761 const expressionS
*s
;
12763 assert (expr_is_register (s
));
12764 return s
->X_add_number
;
12768 /* Set the expression to a symbol + constant offset. */
12771 set_expr_symbol_offset (s
, sym
, offset
)
12776 s
->X_op
= O_symbol
;
12777 s
->X_add_symbol
= sym
;
12778 s
->X_op_symbol
= NULL
; /* unused */
12779 s
->X_add_number
= offset
;
12783 /* Set the expression to symbol - minus_sym + offset. */
12786 set_expr_symbol_offset_diff (s
, sym
, minus_sym
, offset
)
12789 symbolS
*minus_sym
;
12792 s
->X_op
= O_subtract
;
12793 s
->X_add_symbol
= sym
;
12794 s
->X_op_symbol
= minus_sym
; /* unused */
12795 s
->X_add_number
= offset
;
12799 /* Return TRUE if the two expressions are equal. */
12802 expr_is_equal (s1
, s2
)
12806 if (s1
->X_op
!= s2
->X_op
)
12808 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
12810 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
12812 if (s1
->X_add_number
!= s2
->X_add_number
)
12819 copy_expr (dst
, src
)
12821 const expressionS
*src
;
12823 memcpy (dst
, src
, sizeof (expressionS
));
12827 /* Support for Tensilica's "--rename-section" option. */
12829 #ifdef XTENSA_SECTION_RENAME
12831 struct rename_section_struct
12835 struct rename_section_struct
*next
;
12838 static struct rename_section_struct
*section_rename
;
12841 /* Parse the string oldname=new_name:oldname2=new_name2
12842 and call add_section_rename. */
12845 build_section_rename (arg
)
12848 char *this_arg
= NULL
;
12849 char *next_arg
= NULL
;
12851 for (this_arg
= strdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12855 next_arg
= strchr (this_arg
, ':');
12863 char *old_name
= this_arg
;
12864 char *new_name
= strchr (this_arg
, '=');
12866 if (*old_name
== '\0')
12868 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12871 if (!new_name
|| new_name
[1] == '\0')
12873 as_warn (_("ignoring invalid '-rename-section' "
12874 "specification: '%s'"), old_name
);
12879 add_section_rename (old_name
, new_name
);
12886 add_section_rename (old_name
, new_name
)
12890 struct rename_section_struct
*r
= section_rename
;
12892 /* Check for invalid section renaming. */
12893 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12895 if (strcmp (r
->old_name
, old_name
) == 0)
12896 as_bad (_("section %s renamed multiple times"), old_name
);
12897 if (strcmp (r
->new_name
, new_name
) == 0)
12898 as_bad (_("multiple sections remapped to output section %s"),
12903 r
= (struct rename_section_struct
*)
12904 xmalloc (sizeof (struct rename_section_struct
));
12905 r
->old_name
= strdup (old_name
);
12906 r
->new_name
= strdup (new_name
);
12907 r
->next
= section_rename
;
12908 section_rename
= r
;
12913 xtensa_section_rename (name
)
12916 struct rename_section_struct
*r
= section_rename
;
12918 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12920 if (strcmp (r
->old_name
, name
) == 0)
12921 return r
->new_name
;
12927 #endif /* XTENSA_SECTION_RENAME */