1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "xtensa-config.h"
31 #include "elf/xtensa.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
;
75 bfd_boolean absolute_literals_supported
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
217 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
218 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
221 /* Alignment is specified in the block BEFORE the one that needs
222 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
223 get the required alignment specified as a power of 2. Use
224 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
225 alignment. Be careful of side effects since the SET will evaluate
226 flags twice. Also, note that the SIZE of a block in the property
227 table does not include the alignment size, so the alignment fill
228 must be calculated to determine if two blocks are contiguous.
229 TEXT_ALIGN is not currently implemented but is a placeholder for a
230 possible future implementation. */
232 #define XTENSA_PROP_ALIGN 0x00000800
234 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
236 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
237 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
238 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
240 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
243 /* Structure for saving instruction and alignment per-fragment data
244 that will be written to the object file. This structure is
245 equivalent to the actual data that will be written out to the file
246 but is easier to use. We provide a conversion to file flags
247 in frag_flags_to_number. */
249 typedef struct frag_flags_struct frag_flags
;
251 struct frag_flags_struct
253 /* is_literal should only be used after xtensa_move_literals.
254 If you need to check if you are generating a literal fragment,
255 then use the generating_literals global. */
257 unsigned is_literal
: 1;
258 unsigned is_insn
: 1;
259 unsigned is_data
: 1;
260 unsigned is_unreachable
: 1;
262 /* is_specific_opcode implies no_transform. */
263 unsigned is_no_transform
: 1;
267 unsigned is_loop_target
: 1;
268 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
269 unsigned bt_align_priority
: 2;
271 unsigned is_no_density
: 1;
272 /* no_longcalls flag does not need to be placed in the object file. */
274 unsigned is_no_reorder
: 1;
276 /* Uses absolute literal addressing for l32r. */
277 unsigned is_abslit
: 1;
279 unsigned is_align
: 1;
280 unsigned alignment
: 5;
284 /* Structure for saving information about a block of property data
285 for frags that have the same flags. */
286 struct xtensa_block_info_struct
292 struct xtensa_block_info_struct
*next
;
296 /* Structure for saving the current state before emitting literals. */
297 typedef struct emit_state_struct
302 int generating_literals
;
306 /* Opcode placement information */
308 typedef unsigned long long bitfield
;
309 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
310 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
311 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
313 #define MAX_FORMATS 32
315 typedef struct op_placement_info_struct
318 /* A number describing how restrictive the issue is for this
319 opcode. For example, an opcode that fits lots of different
320 formats has a high freedom, as does an opcode that fits
321 only one format but many slots in that format. The most
322 restrictive is the opcode that fits only one slot in one
325 xtensa_format narrowest
;
329 /* formats is a bitfield with the Nth bit set
330 if the opcode fits in the Nth xtensa_format. */
333 /* slots[N]'s Mth bit is set if the op fits in the
334 Mth slot of the Nth xtensa_format. */
335 bitfield slots
[MAX_FORMATS
];
337 /* A count of the number of slots in a given format
338 an op can fit (i.e., the bitcount of the slot field above). */
339 char slots_in_format
[MAX_FORMATS
];
341 } op_placement_info
, *op_placement_info_table
;
343 op_placement_info_table op_placement_table
;
346 /* Extra expression types. */
348 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
349 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
350 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
351 #define O_pcrel O_md4 /* value is a PC-relative offset */
352 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
353 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
354 #define O_tlscall O_md7 /* TLS_CALL relocation */
355 #define O_tpoff O_md8 /* TPOFF relocation */
356 #define O_dtpoff O_md9 /* DTPOFF relocation */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
374 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
375 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
376 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
377 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
378 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
392 directive_literal_prefix
,
394 directive_absolute_literals
,
395 directive_last_directive
401 bfd_boolean can_be_negated
;
404 const directive_infoS directive_info
[] =
407 { "literal", FALSE
},
409 { "transform", TRUE
},
410 { "freeregs", FALSE
},
411 { "longcalls", TRUE
},
412 { "literal_prefix", FALSE
},
413 { "schedule", TRUE
},
414 { "absolute-literals", TRUE
}
417 bfd_boolean directive_state
[] =
422 TRUE
, /* transform */
423 FALSE
, /* freeregs */
424 FALSE
, /* longcalls */
425 FALSE
, /* literal_prefix */
426 FALSE
, /* schedule */
427 FALSE
/* absolute_literals */
430 /* A circular list of all potential and actual literal pool locations
434 struct litpool_frag
*next
;
435 struct litpool_frag
*prev
;
438 short priority
; /* 1, 2, or 3 -- 1 is highest */
439 short original_priority
;
443 /* Map a segment to its litpool_frag list. */
446 struct litpool_seg
*next
;
448 struct litpool_frag frag_list
;
449 int frag_count
; /* since last litpool location */
452 static struct litpool_seg litpool_seg_list
;
454 /* Limit maximal size of auto litpool by half of the j range. */
455 #define MAX_AUTO_POOL_LITERALS 16384
457 /* Limit maximal size of explicit literal pool by l32r range. */
458 #define MAX_EXPLICIT_POOL_LITERALS 65536
460 #define MAX_POOL_LITERALS \
461 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
463 /* Directive functions. */
465 static void xtensa_begin_directive (int);
466 static void xtensa_end_directive (int);
467 static void xtensa_literal_prefix (void);
468 static void xtensa_literal_position (int);
469 static void xtensa_literal_pseudo (int);
470 static void xtensa_frequency_pseudo (int);
471 static void xtensa_elf_cons (int);
472 static void xtensa_leb128 (int);
474 /* Parsing and Idiom Translation. */
476 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
478 /* Various Other Internal Functions. */
480 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
481 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
482 static void xtensa_mark_literal_pool_location (void);
483 static addressT
get_expanded_loop_offset (xtensa_opcode
);
484 static fragS
*get_literal_pool_location (segT
);
485 static void set_literal_pool_location (segT
, fragS
*);
486 static void xtensa_set_frag_assembly_state (fragS
*);
487 static void finish_vinsn (vliw_insn
*);
488 static bfd_boolean
emit_single_op (TInsn
*);
489 static int total_frag_text_expansion (fragS
*);
490 static bfd_boolean use_trampolines
= TRUE
;
491 static void xtensa_check_frag_count (void);
492 static void xtensa_create_trampoline_frag (bfd_boolean
);
493 static void xtensa_maybe_create_trampoline_frag (void);
494 struct trampoline_frag
;
495 static int init_trampoline_frag (fragS
*);
496 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
);
497 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
498 static bfd_boolean auto_litpools
= FALSE
;
499 static int auto_litpool_limit
= 0;
501 /* Alignment Functions. */
503 static int get_text_align_power (unsigned);
504 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
505 static int branch_align_power (segT
);
507 /* Helpers for xtensa_relax_frag(). */
509 static long relax_frag_add_nop (fragS
*);
511 /* Accessors for additional per-subsegment information. */
513 static unsigned get_last_insn_flags (segT
, subsegT
);
514 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
515 static float get_subseg_total_freq (segT
, subsegT
);
516 static float get_subseg_target_freq (segT
, subsegT
);
517 static void set_subseg_freq (segT
, subsegT
, float, float);
519 /* Segment list functions. */
521 static void xtensa_move_literals (void);
522 static void xtensa_reorder_segments (void);
523 static void xtensa_switch_to_literal_fragment (emit_state
*);
524 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
525 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
526 static void xtensa_restore_emit_state (emit_state
*);
527 static segT
cache_literal_section (bfd_boolean
);
529 /* op_placement_info functions. */
531 static void init_op_placement_info_table (void);
532 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
533 static int xg_get_single_size (xtensa_opcode
);
534 static xtensa_format
xg_get_single_format (xtensa_opcode
);
535 static int xg_get_single_slot (xtensa_opcode
);
537 /* TInsn and IStack functions. */
539 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
540 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
541 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
542 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
543 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
544 static void tinsn_from_chars (TInsn
*, char *, int);
545 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
546 static int get_num_stack_text_bytes (IStack
*);
547 static int get_num_stack_literal_bytes (IStack
*);
548 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
550 /* vliw_insn functions. */
552 static void xg_init_vinsn (vliw_insn
*);
553 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
554 static void xg_clear_vinsn (vliw_insn
*);
555 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
556 static void xg_free_vinsn (vliw_insn
*);
557 static bfd_boolean vinsn_to_insnbuf
558 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
559 static void vinsn_from_chars (vliw_insn
*, char *);
561 /* Expression Utilities. */
563 bfd_boolean
expr_is_const (const expressionS
*);
564 offsetT
get_expr_const (const expressionS
*);
565 void set_expr_const (expressionS
*, offsetT
);
566 bfd_boolean
expr_is_register (const expressionS
*);
567 offsetT
get_expr_register (const expressionS
*);
568 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
569 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
570 static void copy_expr (expressionS
*, const expressionS
*);
572 /* Section renaming. */
574 static void build_section_rename (const char *);
577 /* ISA imported from bfd. */
578 extern xtensa_isa xtensa_default_isa
;
580 extern int target_big_endian
;
582 static xtensa_opcode xtensa_addi_opcode
;
583 static xtensa_opcode xtensa_addmi_opcode
;
584 static xtensa_opcode xtensa_call0_opcode
;
585 static xtensa_opcode xtensa_call4_opcode
;
586 static xtensa_opcode xtensa_call8_opcode
;
587 static xtensa_opcode xtensa_call12_opcode
;
588 static xtensa_opcode xtensa_callx0_opcode
;
589 static xtensa_opcode xtensa_callx4_opcode
;
590 static xtensa_opcode xtensa_callx8_opcode
;
591 static xtensa_opcode xtensa_callx12_opcode
;
592 static xtensa_opcode xtensa_const16_opcode
;
593 static xtensa_opcode xtensa_entry_opcode
;
594 static xtensa_opcode xtensa_extui_opcode
;
595 static xtensa_opcode xtensa_movi_opcode
;
596 static xtensa_opcode xtensa_movi_n_opcode
;
597 static xtensa_opcode xtensa_isync_opcode
;
598 static xtensa_opcode xtensa_j_opcode
;
599 static xtensa_opcode xtensa_jx_opcode
;
600 static xtensa_opcode xtensa_l32r_opcode
;
601 static xtensa_opcode xtensa_loop_opcode
;
602 static xtensa_opcode xtensa_loopnez_opcode
;
603 static xtensa_opcode xtensa_loopgtz_opcode
;
604 static xtensa_opcode xtensa_nop_opcode
;
605 static xtensa_opcode xtensa_nop_n_opcode
;
606 static xtensa_opcode xtensa_or_opcode
;
607 static xtensa_opcode xtensa_ret_opcode
;
608 static xtensa_opcode xtensa_ret_n_opcode
;
609 static xtensa_opcode xtensa_retw_opcode
;
610 static xtensa_opcode xtensa_retw_n_opcode
;
611 static xtensa_opcode xtensa_rsr_lcount_opcode
;
612 static xtensa_opcode xtensa_waiti_opcode
;
613 static int config_max_slots
= 0;
616 /* Command-line Options. */
618 bfd_boolean use_literal_section
= TRUE
;
619 enum flix_level produce_flix
= FLIX_ALL
;
620 static bfd_boolean align_targets
= TRUE
;
621 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
622 static bfd_boolean has_a0_b_retw
= FALSE
;
623 static bfd_boolean workaround_a0_b_retw
= FALSE
;
624 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
625 static bfd_boolean workaround_short_loop
= FALSE
;
626 static bfd_boolean maybe_has_short_loop
= FALSE
;
627 static bfd_boolean workaround_close_loop_end
= FALSE
;
628 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
629 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
631 /* When workaround_short_loops is TRUE, all loops with early exits must
632 have at least 3 instructions. workaround_all_short_loops is a modifier
633 to the workaround_short_loop flag. In addition to the
634 workaround_short_loop actions, all straightline loopgtz and loopnez
635 must have at least 3 instructions. */
637 static bfd_boolean workaround_all_short_loops
= FALSE
;
639 /* Generate individual property section for every section.
640 This option is defined in BDF library. */
641 extern bfd_boolean elf32xtensa_separate_props
;
644 xtensa_setup_hw_workarounds (int earliest
, int latest
)
646 if (earliest
> latest
)
647 as_fatal (_("illegal range of target hardware versions"));
649 /* Enable all workarounds for pre-T1050.0 hardware. */
650 if (earliest
< 105000 || latest
< 105000)
652 workaround_a0_b_retw
|= TRUE
;
653 workaround_b_j_loop_end
|= TRUE
;
654 workaround_short_loop
|= TRUE
;
655 workaround_close_loop_end
|= TRUE
;
656 workaround_all_short_loops
|= TRUE
;
657 enforce_three_byte_loop_align
= TRUE
;
664 option_density
= OPTION_MD_BASE
,
668 option_no_generate_flix
,
675 option_no_link_relax
,
683 option_text_section_literals
,
684 option_no_text_section_literals
,
686 option_absolute_literals
,
687 option_no_absolute_literals
,
689 option_align_targets
,
690 option_no_align_targets
,
692 option_warn_unaligned_targets
,
697 option_workaround_a0_b_retw
,
698 option_no_workaround_a0_b_retw
,
700 option_workaround_b_j_loop_end
,
701 option_no_workaround_b_j_loop_end
,
703 option_workaround_short_loop
,
704 option_no_workaround_short_loop
,
706 option_workaround_all_short_loops
,
707 option_no_workaround_all_short_loops
,
709 option_workaround_close_loop_end
,
710 option_no_workaround_close_loop_end
,
712 option_no_workarounds
,
714 option_rename_section_name
,
717 option_prefer_const16
,
719 option_target_hardware
,
722 option_no_trampolines
,
724 option_auto_litpools
,
725 option_no_auto_litpools
,
726 option_auto_litpool_limit
,
728 option_separate_props
,
729 option_no_separate_props
,
732 const char *md_shortopts
= "";
734 struct option md_longopts
[] =
736 { "density", no_argument
, NULL
, option_density
},
737 { "no-density", no_argument
, NULL
, option_no_density
},
739 { "flix", no_argument
, NULL
, option_flix
},
740 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
741 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
743 /* Both "relax" and "generics" are deprecated and treated as equivalent
744 to the "transform" option. */
745 { "relax", no_argument
, NULL
, option_relax
},
746 { "no-relax", no_argument
, NULL
, option_no_relax
},
747 { "generics", no_argument
, NULL
, option_generics
},
748 { "no-generics", no_argument
, NULL
, option_no_generics
},
750 { "transform", no_argument
, NULL
, option_transform
},
751 { "no-transform", no_argument
, NULL
, option_no_transform
},
752 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
753 { "no-text-section-literals", no_argument
, NULL
,
754 option_no_text_section_literals
},
755 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
756 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
757 /* This option was changed from -align-target to -target-align
758 because it conflicted with the "-al" option. */
759 { "target-align", no_argument
, NULL
, option_align_targets
},
760 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
761 { "warn-unaligned-targets", no_argument
, NULL
,
762 option_warn_unaligned_targets
},
763 { "longcalls", no_argument
, NULL
, option_longcalls
},
764 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
766 { "no-workaround-a0-b-retw", no_argument
, NULL
,
767 option_no_workaround_a0_b_retw
},
768 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
770 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
771 option_no_workaround_b_j_loop_end
},
772 { "workaround-b-j-loop-end", no_argument
, NULL
,
773 option_workaround_b_j_loop_end
},
775 { "no-workaround-short-loops", no_argument
, NULL
,
776 option_no_workaround_short_loop
},
777 { "workaround-short-loops", no_argument
, NULL
,
778 option_workaround_short_loop
},
780 { "no-workaround-all-short-loops", no_argument
, NULL
,
781 option_no_workaround_all_short_loops
},
782 { "workaround-all-short-loop", no_argument
, NULL
,
783 option_workaround_all_short_loops
},
785 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
786 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
788 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
790 { "no-workaround-close-loop-end", no_argument
, NULL
,
791 option_no_workaround_close_loop_end
},
792 { "workaround-close-loop-end", no_argument
, NULL
,
793 option_workaround_close_loop_end
},
795 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
797 { "link-relax", no_argument
, NULL
, option_link_relax
},
798 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
800 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
802 { "trampolines", no_argument
, NULL
, option_trampolines
},
803 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
805 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
806 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
807 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
809 { "separate-prop-tables", no_argument
, NULL
, option_separate_props
},
811 { NULL
, no_argument
, NULL
, 0 }
814 size_t md_longopts_size
= sizeof md_longopts
;
818 md_parse_option (int c
, const char *arg
)
823 as_warn (_("--density option is ignored"));
825 case option_no_density
:
826 as_warn (_("--no-density option is ignored"));
828 case option_link_relax
:
831 case option_no_link_relax
:
835 produce_flix
= FLIX_ALL
;
837 case option_no_generate_flix
:
838 produce_flix
= FLIX_NO_GENERATE
;
841 produce_flix
= FLIX_NONE
;
843 case option_generics
:
844 as_warn (_("--generics is deprecated; use --transform instead"));
845 return md_parse_option (option_transform
, arg
);
846 case option_no_generics
:
847 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
848 return md_parse_option (option_no_transform
, arg
);
850 as_warn (_("--relax is deprecated; use --transform instead"));
851 return md_parse_option (option_transform
, arg
);
852 case option_no_relax
:
853 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
854 return md_parse_option (option_no_transform
, arg
);
855 case option_longcalls
:
856 directive_state
[directive_longcalls
] = TRUE
;
858 case option_no_longcalls
:
859 directive_state
[directive_longcalls
] = FALSE
;
861 case option_text_section_literals
:
862 use_literal_section
= FALSE
;
864 case option_no_text_section_literals
:
865 use_literal_section
= TRUE
;
867 case option_absolute_literals
:
868 if (!absolute_literals_supported
)
870 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
873 directive_state
[directive_absolute_literals
] = TRUE
;
875 case option_no_absolute_literals
:
876 directive_state
[directive_absolute_literals
] = FALSE
;
879 case option_workaround_a0_b_retw
:
880 workaround_a0_b_retw
= TRUE
;
882 case option_no_workaround_a0_b_retw
:
883 workaround_a0_b_retw
= FALSE
;
885 case option_workaround_b_j_loop_end
:
886 workaround_b_j_loop_end
= TRUE
;
888 case option_no_workaround_b_j_loop_end
:
889 workaround_b_j_loop_end
= FALSE
;
892 case option_workaround_short_loop
:
893 workaround_short_loop
= TRUE
;
895 case option_no_workaround_short_loop
:
896 workaround_short_loop
= FALSE
;
899 case option_workaround_all_short_loops
:
900 workaround_all_short_loops
= TRUE
;
902 case option_no_workaround_all_short_loops
:
903 workaround_all_short_loops
= FALSE
;
906 case option_workaround_close_loop_end
:
907 workaround_close_loop_end
= TRUE
;
909 case option_no_workaround_close_loop_end
:
910 workaround_close_loop_end
= FALSE
;
913 case option_no_workarounds
:
914 workaround_a0_b_retw
= FALSE
;
915 workaround_b_j_loop_end
= FALSE
;
916 workaround_short_loop
= FALSE
;
917 workaround_all_short_loops
= FALSE
;
918 workaround_close_loop_end
= FALSE
;
921 case option_align_targets
:
922 align_targets
= TRUE
;
924 case option_no_align_targets
:
925 align_targets
= FALSE
;
928 case option_warn_unaligned_targets
:
929 warn_unaligned_branch_targets
= TRUE
;
932 case option_rename_section_name
:
933 build_section_rename (arg
);
937 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
938 should be emitted or not. FIXME: Not implemented. */
941 case option_prefer_l32r
:
943 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
947 case option_prefer_const16
:
949 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
953 case option_target_hardware
:
955 int earliest
, latest
= 0;
957 if (*arg
== 0 || *arg
== '-')
958 as_fatal (_("invalid target hardware version"));
960 earliest
= strtol (arg
, &end
, 0);
964 else if (*end
== '-')
967 as_fatal (_("invalid target hardware version"));
968 latest
= strtol (end
, &end
, 0);
971 as_fatal (_("invalid target hardware version"));
973 xtensa_setup_hw_workarounds (earliest
, latest
);
977 case option_transform
:
978 /* This option has no affect other than to use the defaults,
979 which are already set. */
982 case option_no_transform
:
983 /* This option turns off all transformations of any kind.
984 However, because we want to preserve the state of other
985 directives, we only change its own field. Thus, before
986 you perform any transformation, always check if transform
987 is available. If you use the functions we provide for this
988 purpose, you will be ok. */
989 directive_state
[directive_transform
] = FALSE
;
992 case option_trampolines
:
993 use_trampolines
= TRUE
;
996 case option_no_trampolines
:
997 use_trampolines
= FALSE
;
1000 case option_auto_litpools
:
1001 auto_litpools
= TRUE
;
1002 use_literal_section
= FALSE
;
1003 if (auto_litpool_limit
<= 0)
1004 auto_litpool_limit
= MAX_AUTO_POOL_LITERALS
/ 2;
1007 case option_no_auto_litpools
:
1008 auto_litpools
= FALSE
;
1009 auto_litpool_limit
= -1;
1012 case option_auto_litpool_limit
:
1016 if (auto_litpool_limit
< 0)
1017 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1018 if (*arg
== 0 || *arg
== '-')
1019 as_fatal (_("invalid auto-litpool-limit argument"));
1020 value
= strtol (arg
, &end
, 10);
1022 as_fatal (_("invalid auto-litpool-limit argument"));
1023 if (value
< 100 || value
> 10000)
1024 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1025 auto_litpool_limit
= value
;
1026 auto_litpools
= TRUE
;
1027 use_literal_section
= FALSE
;
1031 case option_separate_props
:
1032 elf32xtensa_separate_props
= TRUE
;
1035 case option_no_separate_props
:
1036 elf32xtensa_separate_props
= FALSE
;
1046 md_show_usage (FILE *stream
)
1050 --[no-]text-section-literals\n\
1051 [Do not] put literals in the text section\n\
1052 --[no-]absolute-literals\n\
1053 [Do not] default to use non-PC-relative literals\n\
1054 --[no-]target-align [Do not] try to align branch targets\n\
1055 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1056 --[no-]transform [Do not] transform instructions\n\
1057 --flix both allow hand-written and generate flix bundles\n\
1058 --no-generate-flix allow hand-written but do not generate\n\
1060 --no-allow-flix neither allow hand-written nor generate\n\
1062 --rename-section old=new Rename section 'old' to 'new'\n\
1063 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1064 when jumps do not reach their targets\n\
1065 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1066 --auto-litpool-limit=<value>\n\
1067 (range 100-10000) Maximum number of blocks of\n\
1068 instructions to emit between literal pool\n\
1069 locations; implies --auto-litpools flag\n\
1070 --[no-]separate-prop-tables\n\
1071 [Do not] place Xtensa property records into\n\
1072 individual property sections for each section.\n\
1073 Default is to generate single property section.\n", stream
);
1077 /* Functions related to the list of current label symbols. */
1080 xtensa_add_insn_label (symbolS
*sym
)
1084 if (!free_insn_labels
)
1085 l
= XNEW (sym_list
);
1088 l
= free_insn_labels
;
1089 free_insn_labels
= l
->next
;
1093 l
->next
= insn_labels
;
1099 xtensa_clear_insn_labels (void)
1103 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1111 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1115 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1117 symbolS
*lit_sym
= lit
->sym
;
1118 S_SET_VALUE (lit_sym
, new_offset
);
1119 symbol_set_frag (lit_sym
, new_frag
);
1124 /* Directive data and functions. */
1126 typedef struct state_stackS_struct
1128 directiveE directive
;
1129 bfd_boolean negated
;
1130 bfd_boolean old_state
;
1134 struct state_stackS_struct
*prev
;
1137 state_stackS
*directive_state_stack
;
1139 const pseudo_typeS md_pseudo_table
[] =
1141 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1142 { "literal_position", xtensa_literal_position
, 0 },
1143 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1144 { "long", xtensa_elf_cons
, 4 },
1145 { "word", xtensa_elf_cons
, 4 },
1146 { "4byte", xtensa_elf_cons
, 4 },
1147 { "short", xtensa_elf_cons
, 2 },
1148 { "2byte", xtensa_elf_cons
, 2 },
1149 { "sleb128", xtensa_leb128
, 1},
1150 { "uleb128", xtensa_leb128
, 0},
1151 { "begin", xtensa_begin_directive
, 0 },
1152 { "end", xtensa_end_directive
, 0 },
1153 { "literal", xtensa_literal_pseudo
, 0 },
1154 { "frequency", xtensa_frequency_pseudo
, 0 },
1160 use_transform (void)
1162 /* After md_end, you should be checking frag by frag, rather
1163 than state directives. */
1164 gas_assert (!past_xtensa_end
);
1165 return directive_state
[directive_transform
];
1170 do_align_targets (void)
1172 /* Do not use this function after md_end; just look at align_targets
1173 instead. There is no target-align directive, so alignment is either
1174 enabled for all frags or not done at all. */
1175 gas_assert (!past_xtensa_end
);
1176 return align_targets
&& use_transform ();
1181 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1185 state_stackS
*stack
= XNEW (state_stackS
);
1187 file
= as_where (&line
);
1189 stack
->directive
= directive
;
1190 stack
->negated
= negated
;
1191 stack
->old_state
= directive_state
[directive
];
1194 stack
->datum
= datum
;
1195 stack
->prev
= directive_state_stack
;
1196 directive_state_stack
= stack
;
1198 directive_state
[directive
] = !negated
;
1203 directive_pop (directiveE
*directive
,
1204 bfd_boolean
*negated
,
1209 state_stackS
*top
= directive_state_stack
;
1211 if (!directive_state_stack
)
1213 as_bad (_("unmatched .end directive"));
1214 *directive
= directive_none
;
1218 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1219 *directive
= top
->directive
;
1220 *negated
= top
->negated
;
1223 *datum
= top
->datum
;
1224 directive_state_stack
= top
->prev
;
1230 directive_balance (void)
1232 while (directive_state_stack
)
1234 directiveE directive
;
1235 bfd_boolean negated
;
1240 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1241 as_warn_where ((char *) file
, line
,
1242 _(".begin directive with no matching .end directive"));
1248 inside_directive (directiveE dir
)
1250 state_stackS
*top
= directive_state_stack
;
1252 while (top
&& top
->directive
!= dir
)
1255 return (top
!= NULL
);
1260 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1264 const char *directive_string
;
1266 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1271 input_line_pointer
+= 3;
1274 len
= strspn (input_line_pointer
,
1275 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1277 /* This code is a hack to make .begin [no-][generics|relax] exactly
1278 equivalent to .begin [no-]transform. We should remove it when
1279 we stop accepting those options. */
1281 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1283 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1284 directive_string
= "transform";
1286 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1288 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1289 directive_string
= "transform";
1292 directive_string
= input_line_pointer
;
1294 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1296 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1298 input_line_pointer
+= len
;
1299 *directive
= (directiveE
) i
;
1300 if (*negated
&& !directive_info
[i
].can_be_negated
)
1301 as_bad (_("directive %s cannot be negated"),
1302 directive_info
[i
].name
);
1307 as_bad (_("unknown directive"));
1308 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1313 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1315 directiveE directive
;
1316 bfd_boolean negated
;
1320 get_directive (&directive
, &negated
);
1321 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1323 discard_rest_of_line ();
1327 if (cur_vinsn
.inside_bundle
)
1328 as_bad (_("directives are not valid inside bundles"));
1332 case directive_literal
:
1333 if (!inside_directive (directive_literal
))
1335 /* Previous labels go with whatever follows this directive, not with
1336 the literal, so save them now. */
1337 saved_insn_labels
= insn_labels
;
1340 as_warn (_(".begin literal is deprecated; use .literal instead"));
1341 state
= XNEW (emit_state
);
1342 xtensa_switch_to_literal_fragment (state
);
1343 directive_push (directive_literal
, negated
, state
);
1346 case directive_literal_prefix
:
1347 /* Have to flush pending output because a movi relaxed to an l32r
1348 might produce a literal. */
1349 md_flush_pending_output ();
1350 /* Check to see if the current fragment is a literal
1351 fragment. If it is, then this operation is not allowed. */
1352 if (generating_literals
)
1354 as_bad (_("cannot set literal_prefix inside literal fragment"));
1358 /* Allocate the literal state for this section and push
1359 onto the directive stack. */
1360 ls
= XNEW (lit_state
);
1363 *ls
= default_lit_sections
;
1364 directive_push (directive_literal_prefix
, negated
, ls
);
1366 /* Process the new prefix. */
1367 xtensa_literal_prefix ();
1370 case directive_freeregs
:
1371 /* This information is currently unused, but we'll accept the statement
1372 and just discard the rest of the line. This won't check the syntax,
1373 but it will accept every correct freeregs directive. */
1374 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1375 directive_push (directive_freeregs
, negated
, 0);
1378 case directive_schedule
:
1379 md_flush_pending_output ();
1380 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1381 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1382 directive_push (directive_schedule
, negated
, 0);
1383 xtensa_set_frag_assembly_state (frag_now
);
1386 case directive_density
:
1387 as_warn (_(".begin [no-]density is ignored"));
1390 case directive_absolute_literals
:
1391 md_flush_pending_output ();
1392 if (!absolute_literals_supported
&& !negated
)
1394 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1397 xtensa_set_frag_assembly_state (frag_now
);
1398 directive_push (directive
, negated
, 0);
1402 md_flush_pending_output ();
1403 xtensa_set_frag_assembly_state (frag_now
);
1404 directive_push (directive
, negated
, 0);
1408 demand_empty_rest_of_line ();
1413 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1415 directiveE begin_directive
, end_directive
;
1416 bfd_boolean begin_negated
, end_negated
;
1420 emit_state
**state_ptr
;
1423 if (cur_vinsn
.inside_bundle
)
1424 as_bad (_("directives are not valid inside bundles"));
1426 get_directive (&end_directive
, &end_negated
);
1428 md_flush_pending_output ();
1430 switch ((int) end_directive
)
1432 case XTENSA_UNDEFINED
:
1433 discard_rest_of_line ();
1436 case (int) directive_density
:
1437 as_warn (_(".end [no-]density is ignored"));
1438 demand_empty_rest_of_line ();
1441 case (int) directive_absolute_literals
:
1442 if (!absolute_literals_supported
&& !end_negated
)
1444 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1445 demand_empty_rest_of_line ();
1454 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1455 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1456 (const void **) state_ptr
);
1458 if (begin_directive
!= directive_none
)
1460 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1462 as_bad (_("does not match begin %s%s at %s:%d"),
1463 begin_negated
? "no-" : "",
1464 directive_info
[begin_directive
].name
, file
, line
);
1468 switch (end_directive
)
1470 case directive_literal
:
1471 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1472 xtensa_restore_emit_state (state
);
1473 xtensa_set_frag_assembly_state (frag_now
);
1475 if (!inside_directive (directive_literal
))
1477 /* Restore the list of current labels. */
1478 xtensa_clear_insn_labels ();
1479 insn_labels
= saved_insn_labels
;
1483 case directive_literal_prefix
:
1484 /* Restore the default collection sections from saved state. */
1485 s
= (lit_state
*) state
;
1487 default_lit_sections
= *s
;
1489 /* Free the state storage. */
1490 free (s
->lit_prefix
);
1494 case directive_schedule
:
1495 case directive_freeregs
:
1499 xtensa_set_frag_assembly_state (frag_now
);
1505 demand_empty_rest_of_line ();
1509 /* Place an aligned literal fragment at the current location. */
1512 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1514 md_flush_pending_output ();
1516 if (inside_directive (directive_literal
))
1517 as_warn (_(".literal_position inside literal directive; ignoring"));
1518 xtensa_mark_literal_pool_location ();
1520 demand_empty_rest_of_line ();
1521 xtensa_clear_insn_labels ();
1525 /* Support .literal label, expr, ... */
1528 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1531 char *p
, *base_name
;
1535 if (inside_directive (directive_literal
))
1537 as_bad (_(".literal not allowed inside .begin literal region"));
1538 ignore_rest_of_line ();
1542 md_flush_pending_output ();
1544 /* Previous labels go with whatever follows this directive, not with
1545 the literal, so save them now. */
1546 saved_insn_labels
= insn_labels
;
1549 /* If we are using text-section literals, then this is the right value... */
1552 base_name
= input_line_pointer
;
1554 xtensa_switch_to_literal_fragment (&state
);
1556 /* ...but if we aren't using text-section-literals, then we
1557 need to put them in the section we just switched to. */
1558 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1561 /* FIXME, despite the previous comments, dest_seg is unused... */
1564 /* All literals are aligned to four-byte boundaries. */
1565 frag_align (2, 0, 0);
1566 record_alignment (now_seg
, 2);
1568 c
= get_symbol_name (&base_name
);
1569 /* Just after name is now '\0'. */
1570 p
= input_line_pointer
;
1572 SKIP_WHITESPACE_AFTER_NAME ();
1574 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1576 as_bad (_("expected comma or colon after symbol name; "
1577 "rest of line ignored"));
1578 ignore_rest_of_line ();
1579 xtensa_restore_emit_state (&state
);
1587 input_line_pointer
++; /* skip ',' or ':' */
1589 xtensa_elf_cons (4);
1591 xtensa_restore_emit_state (&state
);
1593 /* Restore the list of current labels. */
1594 xtensa_clear_insn_labels ();
1595 insn_labels
= saved_insn_labels
;
1600 xtensa_literal_prefix (void)
1605 /* Parse the new prefix from the input_line_pointer. */
1607 len
= strspn (input_line_pointer
,
1608 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1609 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1611 /* Get a null-terminated copy of the name. */
1612 name
= xmemdup0 (input_line_pointer
, len
);
1614 /* Skip the name in the input line. */
1615 input_line_pointer
+= len
;
1617 default_lit_sections
.lit_prefix
= name
;
1619 /* Clear cached literal sections, since the prefix has changed. */
1620 default_lit_sections
.lit_seg
= NULL
;
1621 default_lit_sections
.lit4_seg
= NULL
;
1625 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1628 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1630 float fall_through_f
, target_f
;
1632 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1633 if (fall_through_f
< 0)
1635 as_bad (_("fall through frequency must be greater than 0"));
1636 ignore_rest_of_line ();
1640 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1643 as_bad (_("branch target frequency must be greater than 0"));
1644 ignore_rest_of_line ();
1648 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1650 demand_empty_rest_of_line ();
1654 /* Like normal .long/.short/.word, except support @plt, etc.
1655 Clobbers input_line_pointer, checks end-of-line. */
1658 xtensa_elf_cons (int nbytes
)
1661 bfd_reloc_code_real_type reloc
;
1663 md_flush_pending_output ();
1665 if (cur_vinsn
.inside_bundle
)
1666 as_bad (_("directives are not valid inside bundles"));
1668 if (is_it_end_of_statement ())
1670 demand_empty_rest_of_line ();
1677 if (exp
.X_op
== O_symbol
1678 && *input_line_pointer
== '@'
1679 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1682 reloc_howto_type
*reloc_howto
=
1683 bfd_reloc_type_lookup (stdoutput
, reloc
);
1685 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1686 as_bad (_("unsupported relocation"));
1687 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1688 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1689 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1690 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1691 as_bad (_("opcode-specific %s relocation used outside "
1692 "an instruction"), reloc_howto
->name
);
1693 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1694 as_bad (ngettext ("%s relocations do not fit in %d byte",
1695 "%s relocations do not fit in %d bytes",
1697 reloc_howto
->name
, nbytes
);
1698 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1699 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1700 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1701 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1704 char *p
= frag_more ((int) nbytes
);
1705 xtensa_set_frag_assembly_state (frag_now
);
1706 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1707 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1712 xtensa_set_frag_assembly_state (frag_now
);
1713 emit_expr (&exp
, (unsigned int) nbytes
);
1716 while (*input_line_pointer
++ == ',');
1718 input_line_pointer
--; /* Put terminator back into stream. */
1719 demand_empty_rest_of_line ();
1722 static bfd_boolean is_leb128_expr
;
1725 xtensa_leb128 (int sign
)
1727 is_leb128_expr
= TRUE
;
1729 is_leb128_expr
= FALSE
;
1733 /* Parsing and Idiom Translation. */
1735 /* Parse @plt, etc. and return the desired relocation. */
1736 static bfd_reloc_code_real_type
1737 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1747 return BFD_RELOC_NONE
;
1749 for (ch
= *str
, str2
= ident
;
1750 (str2
< ident
+ sizeof (ident
) - 1
1751 && (ISALNUM (ch
) || ch
== '@'));
1754 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1761 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1762 if (ch
== suffix_relocs
[i
].suffix
[0]
1763 && len
== suffix_relocs
[i
].length
1764 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1766 /* Now check for "identifier@suffix+constant". */
1767 if (*str
== '-' || *str
== '+')
1769 char *orig_line
= input_line_pointer
;
1770 expressionS new_exp
;
1772 input_line_pointer
= str
;
1773 expression (&new_exp
);
1774 if (new_exp
.X_op
== O_constant
)
1776 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1777 str
= input_line_pointer
;
1780 if (&input_line_pointer
!= str_p
)
1781 input_line_pointer
= orig_line
;
1785 return suffix_relocs
[i
].reloc
;
1788 return BFD_RELOC_UNUSED
;
1792 /* Find the matching operator type. */
1794 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1796 operatorT
operator = O_illegal
;
1799 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1801 if (suffix_relocs
[i
].reloc
== reloc
)
1803 operator = suffix_relocs
[i
].operator;
1807 gas_assert (operator != O_illegal
);
1812 /* Find the matching reloc type. */
1813 static bfd_reloc_code_real_type
1814 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1817 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1819 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1821 if (suffix_relocs
[i
].operator == operator)
1823 reloc
= suffix_relocs
[i
].reloc
;
1830 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1831 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1832 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1833 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1836 if (reloc
== BFD_RELOC_UNUSED
)
1837 return BFD_RELOC_32
;
1844 expression_end (const char *name
)
1867 #define ERROR_REG_NUM ((unsigned) -1)
1870 tc_get_register (const char *prefix
)
1873 const char *next_expr
;
1874 const char *old_line_pointer
;
1877 old_line_pointer
= input_line_pointer
;
1879 if (*input_line_pointer
== '$')
1880 ++input_line_pointer
;
1882 /* Accept "sp" as a synonym for "a1". */
1883 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1884 && expression_end (input_line_pointer
+ 2))
1886 input_line_pointer
+= 2;
1887 return 1; /* AR[1] */
1890 while (*input_line_pointer
++ == *prefix
++)
1892 --input_line_pointer
;
1897 as_bad (_("bad register name: %s"), old_line_pointer
);
1898 return ERROR_REG_NUM
;
1901 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1903 as_bad (_("bad register number: %s"), input_line_pointer
);
1904 return ERROR_REG_NUM
;
1909 while (ISDIGIT ((int) *input_line_pointer
))
1910 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1912 if (!(next_expr
= expression_end (input_line_pointer
)))
1914 as_bad (_("bad register name: %s"), old_line_pointer
);
1915 return ERROR_REG_NUM
;
1918 input_line_pointer
= (char *) next_expr
;
1925 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1927 xtensa_isa isa
= xtensa_default_isa
;
1929 /* Check if this is an immediate operand. */
1930 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1932 bfd_reloc_code_real_type reloc
;
1933 segT t
= expression (tok
);
1935 if (t
== absolute_section
1936 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1938 gas_assert (tok
->X_op
== O_constant
);
1939 tok
->X_op
= O_symbol
;
1940 tok
->X_add_symbol
= &abs_symbol
;
1943 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1944 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1949 case BFD_RELOC_LO16
:
1950 if (tok
->X_op
== O_constant
)
1952 tok
->X_add_number
&= 0xffff;
1956 case BFD_RELOC_HI16
:
1957 if (tok
->X_op
== O_constant
)
1959 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1963 case BFD_RELOC_UNUSED
:
1964 as_bad (_("unsupported relocation"));
1966 case BFD_RELOC_32_PCREL
:
1967 as_bad (_("pcrel relocation not allowed in an instruction"));
1972 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1977 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1978 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1980 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1983 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1984 as_bad (_("register number out of range"));
1987 tok
->X_op
= O_register
;
1988 tok
->X_add_symbol
= 0;
1989 tok
->X_add_number
= reg
;
1994 /* Split up the arguments for an opcode or pseudo-op. */
1997 tokenize_arguments (char **args
, char *str
)
1999 char *old_input_line_pointer
;
2000 bfd_boolean saw_comma
= FALSE
;
2001 bfd_boolean saw_arg
= FALSE
;
2002 bfd_boolean saw_colon
= FALSE
;
2004 char *arg_end
, *arg
;
2007 /* Save and restore input_line_pointer around this function. */
2008 old_input_line_pointer
= input_line_pointer
;
2009 input_line_pointer
= str
;
2011 while (*input_line_pointer
)
2014 switch (*input_line_pointer
)
2021 input_line_pointer
++;
2022 if (saw_comma
|| saw_colon
|| !saw_arg
)
2028 input_line_pointer
++;
2029 if (saw_comma
|| saw_colon
|| !saw_arg
)
2035 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2038 arg_end
= input_line_pointer
+ 1;
2039 while (!expression_end (arg_end
))
2042 arg_len
= arg_end
- input_line_pointer
;
2043 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2044 args
[num_args
] = arg
;
2048 strncpy (arg
, input_line_pointer
, arg_len
);
2049 arg
[arg_len
] = '\0';
2051 input_line_pointer
= arg_end
;
2061 if (saw_comma
|| saw_colon
)
2063 input_line_pointer
= old_input_line_pointer
;
2068 as_bad (_("extra comma"));
2070 as_bad (_("extra colon"));
2072 as_bad (_("missing argument"));
2074 as_bad (_("missing comma or colon"));
2075 input_line_pointer
= old_input_line_pointer
;
2080 /* Parse the arguments to an opcode. Return TRUE on error. */
2083 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2085 expressionS
*tok
, *last_tok
;
2086 xtensa_opcode opcode
= insn
->opcode
;
2087 bfd_boolean had_error
= TRUE
;
2088 xtensa_isa isa
= xtensa_default_isa
;
2089 int n
, num_regs
= 0;
2090 int opcode_operand_count
;
2091 int opnd_cnt
, last_opnd_cnt
;
2092 unsigned int next_reg
= 0;
2093 char *old_input_line_pointer
;
2095 if (insn
->insn_type
== ITYPE_LITERAL
)
2096 opcode_operand_count
= 1;
2098 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2101 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2103 /* Save and restore input_line_pointer around this function. */
2104 old_input_line_pointer
= input_line_pointer
;
2110 /* Skip invisible operands. */
2111 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2117 for (n
= 0; n
< num_args
; n
++)
2119 input_line_pointer
= arg_strings
[n
];
2120 if (*input_line_pointer
== ':')
2122 xtensa_regfile opnd_rf
;
2123 input_line_pointer
++;
2126 gas_assert (opnd_cnt
> 0);
2128 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2130 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2131 as_warn (_("incorrect register number, ignoring"));
2136 if (opnd_cnt
>= opcode_operand_count
)
2138 as_warn (_("too many arguments"));
2141 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2143 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2144 next_reg
= tok
->X_add_number
+ 1;
2146 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2148 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2150 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2151 /* minus 1 because we are seeing one right now */
2157 last_opnd_cnt
= opnd_cnt
;
2158 demand_empty_rest_of_line ();
2165 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2169 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2172 insn
->ntok
= tok
- insn
->tok
;
2176 input_line_pointer
= old_input_line_pointer
;
2182 get_invisible_operands (TInsn
*insn
)
2184 xtensa_isa isa
= xtensa_default_isa
;
2185 static xtensa_insnbuf slotbuf
= NULL
;
2187 xtensa_opcode opc
= insn
->opcode
;
2188 int slot
, opnd
, fmt_found
;
2192 slotbuf
= xtensa_insnbuf_alloc (isa
);
2194 /* Find format/slot where this can be encoded. */
2197 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2199 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2201 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2207 if (fmt_found
) break;
2212 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2216 /* First encode all the visible operands
2217 (to deal with shared field operands). */
2218 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2220 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2221 && (insn
->tok
[opnd
].X_op
== O_register
2222 || insn
->tok
[opnd
].X_op
== O_constant
))
2224 val
= insn
->tok
[opnd
].X_add_number
;
2225 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2226 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2230 /* Then pull out the values for the invisible ones. */
2231 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2233 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2235 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2236 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2237 insn
->tok
[opnd
].X_add_number
= val
;
2238 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2239 insn
->tok
[opnd
].X_op
= O_register
;
2241 insn
->tok
[opnd
].X_op
= O_constant
;
2250 xg_reverse_shift_count (char **cnt_argp
)
2252 char *cnt_arg
, *new_arg
;
2253 cnt_arg
= *cnt_argp
;
2255 /* replace the argument with "31-(argument)" */
2256 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2259 *cnt_argp
= new_arg
;
2263 /* If "arg" is a constant expression, return non-zero with the value
2267 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2270 char *save_ptr
= input_line_pointer
;
2272 input_line_pointer
= arg
;
2274 input_line_pointer
= save_ptr
;
2276 if (exp
.X_op
== O_constant
)
2278 *valp
= exp
.X_add_number
;
2287 xg_replace_opname (char **popname
, const char *newop
)
2290 *popname
= xstrdup (newop
);
2295 xg_check_num_args (int *pnum_args
,
2300 int num_args
= *pnum_args
;
2302 if (num_args
< expected_num
)
2304 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2305 num_args
, opname
, expected_num
);
2309 if (num_args
> expected_num
)
2311 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2312 num_args
, opname
, expected_num
);
2313 while (num_args
-- > expected_num
)
2315 free (arg_strings
[num_args
]);
2316 arg_strings
[num_args
] = 0;
2318 *pnum_args
= expected_num
;
2326 /* If the register is not specified as part of the opcode,
2327 then get it from the operand and move it to the opcode. */
2330 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2332 xtensa_isa isa
= xtensa_default_isa
;
2334 char *opname
, *new_opname
;
2335 const char *sr_name
;
2336 int is_user
, is_write
;
2341 is_user
= (opname
[1] == 'u');
2342 is_write
= (opname
[0] == 'w');
2344 /* Opname == [rw]ur or [rwx]sr... */
2346 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2349 /* Check if the argument is a symbolic register name. */
2350 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2351 /* Handle WSR to "INTSET" as a special case. */
2352 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2353 && !strcasecmp (arg_strings
[1], "intset"))
2354 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2355 if (sr
== XTENSA_UNDEFINED
2356 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2358 /* Maybe it's a register number.... */
2360 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2362 as_bad (_("invalid register '%s' for '%s' instruction"),
2363 arg_strings
[1], opname
);
2366 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2367 if (sr
== XTENSA_UNDEFINED
)
2369 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2370 (long) val
, opname
);
2375 /* Remove the last argument, which is now part of the opcode. */
2376 free (arg_strings
[1]);
2380 /* Translate the opcode. */
2381 sr_name
= xtensa_sysreg_name (isa
, sr
);
2382 /* Another special case for "WSR.INTSET".... */
2383 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2385 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2387 *popname
= new_opname
;
2394 xtensa_translate_old_userreg_ops (char **popname
)
2396 xtensa_isa isa
= xtensa_default_isa
;
2398 char *opname
, *new_opname
;
2399 const char *sr_name
;
2400 bfd_boolean has_underbar
= FALSE
;
2403 if (opname
[0] == '_')
2405 has_underbar
= TRUE
;
2409 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2410 if (sr
!= XTENSA_UNDEFINED
)
2412 /* The new default name ("nnn") is different from the old default
2413 name ("URnnn"). The old default is handled below, and we don't
2414 want to recognize [RW]nnn, so do nothing if the name is the (new)
2416 static char namebuf
[10];
2417 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2418 if (strcmp (namebuf
, opname
+ 1) == 0)
2426 /* Only continue if the reg name is "URnnn". */
2427 if (opname
[1] != 'u' || opname
[2] != 'r')
2429 val
= strtoul (opname
+ 3, &end
, 10);
2433 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2434 if (sr
== XTENSA_UNDEFINED
)
2436 as_bad (_("invalid register number (%ld) for '%s'"),
2437 (long) val
, opname
);
2442 /* Translate the opcode. */
2443 sr_name
= xtensa_sysreg_name (isa
, sr
);
2444 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2445 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2446 opname
[0], sr_name
);
2448 *popname
= new_opname
;
2455 xtensa_translate_zero_immed (const char *old_op
,
2465 gas_assert (opname
[0] != '_');
2467 if (strcmp (opname
, old_op
) != 0)
2470 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2472 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2474 xg_replace_opname (popname
, new_op
);
2475 free (arg_strings
[1]);
2476 arg_strings
[1] = arg_strings
[2];
2485 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2486 Returns non-zero if an error was found. */
2489 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2491 char *opname
= *popname
;
2492 bfd_boolean has_underbar
= FALSE
;
2496 has_underbar
= TRUE
;
2500 if (strcmp (opname
, "mov") == 0)
2502 if (use_transform () && !has_underbar
&& density_supported
)
2503 xg_replace_opname (popname
, "mov.n");
2506 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2508 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2509 arg_strings
[2] = xstrdup (arg_strings
[1]);
2515 if (strcmp (opname
, "bbsi.l") == 0)
2517 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2519 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2520 if (target_big_endian
)
2521 xg_reverse_shift_count (&arg_strings
[1]);
2525 if (strcmp (opname
, "bbci.l") == 0)
2527 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2529 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2530 if (target_big_endian
)
2531 xg_reverse_shift_count (&arg_strings
[1]);
2535 /* Don't do anything special with NOPs inside FLIX instructions. They
2536 are handled elsewhere. Real NOP instructions are always available
2537 in configurations with FLIX, so this should never be an issue but
2538 check for it anyway. */
2539 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2540 && strcmp (opname
, "nop") == 0)
2542 if (use_transform () && !has_underbar
&& density_supported
)
2543 xg_replace_opname (popname
, "nop.n");
2546 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2548 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2549 arg_strings
[0] = xstrdup ("a1");
2550 arg_strings
[1] = xstrdup ("a1");
2551 arg_strings
[2] = xstrdup ("a1");
2557 /* Recognize [RW]UR and [RWX]SR. */
2558 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2559 && (opname
[1] == 'u' || opname
[1] == 's'))
2560 || (opname
[0] == 'x' && opname
[1] == 's'))
2562 && opname
[3] == '\0')
2563 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2565 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2566 [RW]<name> if <name> is the non-default name of a user register. */
2567 if ((opname
[0] == 'r' || opname
[0] == 'w')
2568 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2569 return xtensa_translate_old_userreg_ops (popname
);
2571 /* Relax branches that don't allow comparisons against an immediate value
2572 of zero to the corresponding branches with implicit zero immediates. */
2573 if (!has_underbar
&& use_transform ())
2575 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2576 pnum_args
, arg_strings
))
2579 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2580 pnum_args
, arg_strings
))
2583 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2584 pnum_args
, arg_strings
))
2587 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2588 pnum_args
, arg_strings
))
2596 /* Functions for dealing with the Xtensa ISA. */
2598 /* Currently the assembler only allows us to use a single target per
2599 fragment. Because of this, only one operand for a given
2600 instruction may be symbolic. If there is a PC-relative operand,
2601 the last one is chosen. Otherwise, the result is the number of the
2602 last immediate operand, and if there are none of those, we fail and
2606 get_relaxable_immed (xtensa_opcode opcode
)
2608 int last_immed
= -1;
2611 if (opcode
== XTENSA_UNDEFINED
)
2614 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2615 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2617 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2619 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2621 if (last_immed
== -1
2622 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2629 static xtensa_opcode
2630 get_opcode_from_buf (const char *buf
, int slot
)
2632 static xtensa_insnbuf insnbuf
= NULL
;
2633 static xtensa_insnbuf slotbuf
= NULL
;
2634 xtensa_isa isa
= xtensa_default_isa
;
2639 insnbuf
= xtensa_insnbuf_alloc (isa
);
2640 slotbuf
= xtensa_insnbuf_alloc (isa
);
2643 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2644 fmt
= xtensa_format_decode (isa
, insnbuf
);
2645 if (fmt
== XTENSA_UNDEFINED
)
2646 return XTENSA_UNDEFINED
;
2648 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2649 return XTENSA_UNDEFINED
;
2651 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2652 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2656 #ifdef TENSILICA_DEBUG
2658 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2661 xtensa_print_insn_table (void)
2663 int num_opcodes
, num_operands
;
2664 xtensa_opcode opcode
;
2665 xtensa_isa isa
= xtensa_default_isa
;
2667 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2668 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2671 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2672 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2673 for (opn
= 0; opn
< num_operands
; opn
++)
2675 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2677 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2679 xtensa_regfile opnd_rf
=
2680 xtensa_operand_regfile (isa
, opcode
, opn
);
2681 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2683 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2684 fputs ("[lLr] ", stderr
);
2686 fputs ("i ", stderr
);
2688 fprintf (stderr
, "\n");
2694 print_vliw_insn (xtensa_insnbuf vbuf
)
2696 xtensa_isa isa
= xtensa_default_isa
;
2697 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2698 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2701 fprintf (stderr
, "format = %d\n", f
);
2703 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2705 xtensa_opcode opcode
;
2709 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2710 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2711 opname
= xtensa_opcode_name (isa
, opcode
);
2713 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2714 fprintf (stderr
, " operands = ");
2716 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2720 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2722 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2723 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2724 fprintf (stderr
, "%d ", val
);
2726 fprintf (stderr
, "\n");
2728 xtensa_insnbuf_free (isa
, sbuf
);
2731 #endif /* TENSILICA_DEBUG */
2735 is_direct_call_opcode (xtensa_opcode opcode
)
2737 xtensa_isa isa
= xtensa_default_isa
;
2738 int n
, num_operands
;
2740 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2743 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2744 for (n
= 0; n
< num_operands
; n
++)
2746 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2747 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2754 /* Convert from BFD relocation type code to slot and operand number.
2755 Returns non-zero on failure. */
2758 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2760 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2761 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2763 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2766 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2767 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2769 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2779 /* Convert from slot number to BFD relocation type code for the
2780 standard PC-relative relocations. Return BFD_RELOC_NONE on
2783 static bfd_reloc_code_real_type
2784 encode_reloc (int slot
)
2786 if (slot
< 0 || slot
> 14)
2787 return BFD_RELOC_NONE
;
2789 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2793 /* Convert from slot numbers to BFD relocation type code for the
2794 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2796 static bfd_reloc_code_real_type
2797 encode_alt_reloc (int slot
)
2799 if (slot
< 0 || slot
> 14)
2800 return BFD_RELOC_NONE
;
2802 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2807 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2810 xtensa_opcode opcode
,
2816 uint32 valbuf
= value
;
2818 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2820 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2822 as_bad_where ((char *) file
, line
,
2823 _("operand %d of '%s' has out of range value '%u'"),
2825 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2828 as_bad_where ((char *) file
, line
,
2829 _("operand %d of '%s' has invalid value '%u'"),
2831 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2836 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2842 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2845 xtensa_opcode opcode
,
2849 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2850 fmt
, slot
, slotbuf
, &val
);
2851 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2856 /* Checks for rules from xtensa-relax tables. */
2858 /* The routine xg_instruction_matches_option_term must return TRUE
2859 when a given option term is true. The meaning of all of the option
2860 terms is given interpretation by this function. */
2863 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2865 if (strcmp (option
->option_name
, "realnop") == 0
2866 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2868 /* These conditions were evaluated statically when building the
2869 relaxation table. There's no need to reevaluate them now. */
2872 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2873 return insn
->extra_arg
.X_op
== O_register
;
2876 as_fatal (_("internal error: unknown option name '%s'"),
2877 option
->option_name
);
2883 xg_instruction_matches_or_options (TInsn
*insn
,
2884 const ReqOrOptionList
*or_option
)
2886 const ReqOrOption
*option
;
2887 /* Must match each of the AND terms. */
2888 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2890 if (xg_instruction_matches_option_term (insn
, option
))
2898 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2900 const ReqOption
*req_options
;
2901 /* Must match each of the AND terms. */
2902 for (req_options
= options
;
2903 req_options
!= NULL
;
2904 req_options
= req_options
->next
)
2906 /* Must match one of the OR clauses. */
2907 if (!xg_instruction_matches_or_options (insn
,
2908 req_options
->or_option_terms
))
2915 /* Return the transition rule that matches or NULL if none matches. */
2918 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2920 PreconditionList
*condition_l
;
2922 if (rule
->opcode
!= insn
->opcode
)
2925 for (condition_l
= rule
->conditions
;
2926 condition_l
!= NULL
;
2927 condition_l
= condition_l
->next
)
2931 Precondition
*cond
= condition_l
->precond
;
2936 /* The expression must be the constant. */
2937 gas_assert (cond
->op_num
< insn
->ntok
);
2938 exp1
= &insn
->tok
[cond
->op_num
];
2939 if (expr_is_const (exp1
))
2944 if (get_expr_const (exp1
) != cond
->op_data
)
2948 if (get_expr_const (exp1
) == cond
->op_data
)
2955 else if (expr_is_register (exp1
))
2960 if (get_expr_register (exp1
) != cond
->op_data
)
2964 if (get_expr_register (exp1
) == cond
->op_data
)
2976 gas_assert (cond
->op_num
< insn
->ntok
);
2977 gas_assert (cond
->op_data
< insn
->ntok
);
2978 exp1
= &insn
->tok
[cond
->op_num
];
2979 exp2
= &insn
->tok
[cond
->op_data
];
2984 if (!expr_is_equal (exp1
, exp2
))
2988 if (expr_is_equal (exp1
, exp2
))
3000 if (!xg_instruction_matches_options (insn
, rule
->options
))
3008 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
3010 bfd_boolean a_greater
= FALSE
;
3011 bfd_boolean b_greater
= FALSE
;
3013 ReqOptionList
*l_a
= a
->options
;
3014 ReqOptionList
*l_b
= b
->options
;
3016 /* We only care if they both are the same except for
3017 a const16 vs. an l32r. */
3019 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3021 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3022 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3023 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3025 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3027 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3029 /* This is the case we care about. */
3030 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3031 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3038 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3039 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3049 l_or_a
= l_or_a
->next
;
3050 l_or_b
= l_or_b
->next
;
3052 if (l_or_a
|| l_or_b
)
3061 /* Incomparable if the substitution was used differently in two cases. */
3062 if (a_greater
&& b_greater
)
3074 static TransitionRule
*
3075 xg_instruction_match (TInsn
*insn
)
3077 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3079 gas_assert (insn
->opcode
< table
->num_opcodes
);
3081 /* Walk through all of the possible transitions. */
3082 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3084 TransitionRule
*rule
= l
->rule
;
3085 if (xg_instruction_matches_rule (insn
, rule
))
3092 /* Various Other Internal Functions. */
3095 is_unique_insn_expansion (TransitionRule
*r
)
3097 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3099 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3105 /* Check if there is exactly one relaxation for INSN that converts it to
3106 another instruction of equal or larger size. If so, and if TARG is
3107 non-null, go ahead and generate the relaxed instruction into TARG. If
3108 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3109 instruction, i.e., ignore relaxations that convert to an instruction of
3110 equal size. In some contexts where this function is used, only
3111 a single widening is allowed and the NARROW_ONLY argument is used to
3112 exclude cases like ADDI being "widened" to an ADDMI, which may
3113 later be relaxed to an ADDMI/ADDI pair. */
3116 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3118 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3120 TransitionRule
*match
= 0;
3122 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3123 gas_assert (insn
->opcode
< table
->num_opcodes
);
3125 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3127 TransitionRule
*rule
= l
->rule
;
3129 if (xg_instruction_matches_rule (insn
, rule
)
3130 && is_unique_insn_expansion (rule
)
3131 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3132 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3143 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3148 /* Return the maximum number of bytes this opcode can expand to. */
3151 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3153 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3155 int max_size
= xg_get_single_size (opcode
);
3157 gas_assert (opcode
< table
->num_opcodes
);
3159 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3161 TransitionRule
*rule
= l
->rule
;
3162 BuildInstr
*build_list
;
3167 build_list
= rule
->to_instr
;
3168 if (is_unique_insn_expansion (rule
))
3170 gas_assert (build_list
->typ
== INSTR_INSTR
);
3171 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3174 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3176 switch (build_list
->typ
)
3179 this_size
+= xg_get_single_size (build_list
->opcode
);
3181 case INSTR_LITERAL_DEF
:
3182 case INSTR_LABEL_DEF
:
3187 if (this_size
> max_size
)
3188 max_size
= this_size
;
3194 /* Return the maximum number of literal bytes this opcode can generate. */
3197 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3199 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3203 gas_assert (opcode
< table
->num_opcodes
);
3205 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3207 TransitionRule
*rule
= l
->rule
;
3208 BuildInstr
*build_list
;
3213 build_list
= rule
->to_instr
;
3214 if (is_unique_insn_expansion (rule
))
3216 gas_assert (build_list
->typ
== INSTR_INSTR
);
3217 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3220 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3222 switch (build_list
->typ
)
3224 case INSTR_LITERAL_DEF
:
3225 /* Hard-coded 4-byte literal. */
3229 case INSTR_LABEL_DEF
:
3234 if (this_size
> max_size
)
3235 max_size
= this_size
;
3242 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3244 int steps_taken
= 0;
3245 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3248 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3249 gas_assert (insn
->opcode
< table
->num_opcodes
);
3251 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3253 TransitionRule
*rule
= l
->rule
;
3255 if (xg_instruction_matches_rule (insn
, rule
))
3257 if (steps_taken
== lateral_steps
)
3267 get_special_literal_symbol (void)
3269 static symbolS
*sym
= NULL
;
3272 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3278 get_special_label_symbol (void)
3280 static symbolS
*sym
= NULL
;
3283 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3289 xg_valid_literal_expression (const expressionS
*exp
)
3311 /* This will check to see if the value can be converted into the
3312 operand type. It will return TRUE if it does not fit. */
3315 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3317 uint32 valbuf
= value
;
3318 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3324 /* Assumes: All immeds are constants. Check that all constants fit
3325 into their immeds; return FALSE if not. */
3328 xg_immeds_fit (const TInsn
*insn
)
3330 xtensa_isa isa
= xtensa_default_isa
;
3334 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3335 for (i
= 0; i
< n
; ++i
)
3337 const expressionS
*exp
= &insn
->tok
[i
];
3339 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3346 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3351 /* The symbol should have a fixup associated with it. */
3360 /* This should only be called after we have an initial
3361 estimate of the addresses. */
3364 xg_symbolic_immeds_fit (const TInsn
*insn
,
3370 xtensa_isa isa
= xtensa_default_isa
;
3378 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3380 for (i
= 0; i
< n
; ++i
)
3382 const expressionS
*exp
= &insn
->tok
[i
];
3384 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3391 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3397 /* Check for the worst case. */
3398 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3403 /* We only allow symbols for PC-relative references.
3404 If pc_frag == 0, then we don't have frag locations yet. */
3406 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3409 /* If it is a weak symbol or a symbol in a different section,
3410 it cannot be known to fit at assembly time. */
3411 if (S_IS_WEAK (exp
->X_add_symbol
)
3412 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3414 /* For a direct call with --no-longcalls, be optimistic and
3415 assume it will be in range. If the symbol is weak and
3416 undefined, it may remain undefined at link-time, in which
3417 case it will have a zero value and almost certainly be out
3418 of range for a direct call; thus, relax for undefined weak
3419 symbols even if longcalls is not enabled. */
3420 if (is_direct_call_opcode (insn
->opcode
)
3421 && ! pc_frag
->tc_frag_data
.use_longcalls
3422 && (! S_IS_WEAK (exp
->X_add_symbol
)
3423 || S_IS_DEFINED (exp
->X_add_symbol
)))
3429 symbolP
= exp
->X_add_symbol
;
3430 sym_frag
= symbol_get_frag (symbolP
);
3431 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3432 pc
= pc_frag
->fr_address
+ pc_offset
;
3434 /* If frag has yet to be reached on this pass, assume it
3435 will move by STRETCH just as we did. If this is not so,
3436 it will be because some frag between grows, and that will
3437 force another pass. Beware zero-length frags. There
3438 should be a faster way to do this. */
3441 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3442 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3447 new_offset
= target
;
3448 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3449 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3454 /* The symbol should have a fixup associated with it. */
3463 /* Return TRUE on success. */
3466 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3472 targ
->debug_line
= insn
->debug_line
;
3473 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3478 targ
->opcode
= bi
->opcode
;
3479 targ
->insn_type
= ITYPE_INSN
;
3480 targ
->is_specific_opcode
= FALSE
;
3482 for (; op
!= NULL
; op
= op
->next
)
3484 int op_num
= op
->op_num
;
3485 int op_data
= op
->op_data
;
3487 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3489 if (targ
->ntok
<= op_num
)
3490 targ
->ntok
= op_num
+ 1;
3495 set_expr_const (&targ
->tok
[op_num
], op_data
);
3498 gas_assert (op_data
< insn
->ntok
);
3499 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3502 if (insn
->extra_arg
.X_op
!= O_register
)
3504 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3507 sym
= get_special_literal_symbol ();
3508 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3509 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3510 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3511 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3514 sym
= get_special_label_symbol ();
3515 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3517 case OP_OPERAND_HI16U
:
3518 case OP_OPERAND_LOW16U
:
3519 gas_assert (op_data
< insn
->ntok
);
3520 if (expr_is_const (&insn
->tok
[op_data
]))
3523 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3524 val
= xg_apply_userdef_op_fn (op
->typ
,
3527 targ
->tok
[op_num
].X_add_number
= val
;
3531 /* For const16 we can create relocations for these. */
3532 if (targ
->opcode
== XTENSA_UNDEFINED
3533 || (targ
->opcode
!= xtensa_const16_opcode
))
3535 gas_assert (op_data
< insn
->ntok
);
3536 /* Need to build a O_lo16 or O_hi16. */
3537 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3538 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3540 if (op
->typ
== OP_OPERAND_HI16U
)
3541 targ
->tok
[op_num
].X_op
= O_hi16
;
3542 else if (op
->typ
== OP_OPERAND_LOW16U
)
3543 targ
->tok
[op_num
].X_op
= O_lo16
;
3550 /* currently handles:
3553 OP_OPERAND_F32MINUS */
3554 if (xg_has_userdef_op_fn (op
->typ
))
3556 gas_assert (op_data
< insn
->ntok
);
3557 if (expr_is_const (&insn
->tok
[op_data
]))
3560 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3561 val
= xg_apply_userdef_op_fn (op
->typ
,
3564 targ
->tok
[op_num
].X_add_number
= val
;
3567 return FALSE
; /* We cannot use a relocation for this. */
3576 case INSTR_LITERAL_DEF
:
3578 targ
->opcode
= XTENSA_UNDEFINED
;
3579 targ
->insn_type
= ITYPE_LITERAL
;
3580 targ
->is_specific_opcode
= FALSE
;
3581 for (; op
!= NULL
; op
= op
->next
)
3583 int op_num
= op
->op_num
;
3584 int op_data
= op
->op_data
;
3585 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3587 if (targ
->ntok
<= op_num
)
3588 targ
->ntok
= op_num
+ 1;
3593 gas_assert (op_data
< insn
->ntok
);
3594 /* We can only pass resolvable literals through. */
3595 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3597 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3609 case INSTR_LABEL_DEF
:
3611 targ
->opcode
= XTENSA_UNDEFINED
;
3612 targ
->insn_type
= ITYPE_LABEL
;
3613 targ
->is_specific_opcode
= FALSE
;
3614 /* Literal with no ops is a label? */
3615 gas_assert (op
== NULL
);
3626 /* Return TRUE on success. */
3629 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3631 for (; bi
!= NULL
; bi
= bi
->next
)
3633 TInsn
*next_insn
= istack_push_space (istack
);
3635 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3642 /* Return TRUE on valid expansion. */
3645 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3647 int stack_size
= istack
->ninsn
;
3648 int steps_taken
= 0;
3649 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3652 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3653 gas_assert (insn
->opcode
< table
->num_opcodes
);
3655 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3657 TransitionRule
*rule
= l
->rule
;
3659 if (xg_instruction_matches_rule (insn
, rule
))
3661 if (lateral_steps
== steps_taken
)
3665 /* This is it. Expand the rule to the stack. */
3666 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3669 /* Check to see if it fits. */
3670 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3672 TInsn
*tinsn
= &istack
->insn
[i
];
3674 if (tinsn
->insn_type
== ITYPE_INSN
3675 && !tinsn_has_symbolic_operands (tinsn
)
3676 && !xg_immeds_fit (tinsn
))
3678 istack
->ninsn
= stack_size
;
3691 /* Relax the assembly instruction at least "min_steps".
3692 Return the number of steps taken.
3694 For relaxation to correctly terminate, every relaxation chain must
3695 terminate in one of two ways:
3697 1. If the chain from one instruction to the next consists entirely of
3698 single instructions, then the chain *must* handle all possible
3699 immediates without failing. It must not ever fail because an
3700 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3701 chain is one example. L32R loads 32 bits, and there cannot be an
3702 immediate larger than 32 bits, so it satisfies this condition.
3703 Single instruction relaxation chains are as defined by
3704 xg_is_single_relaxable_instruction.
3706 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3707 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3709 Strictly speaking, in most cases you can violate condition 1 and be OK
3710 -- in particular when the last two instructions have the same single
3711 size. But nevertheless, you should guarantee the above two conditions.
3713 We could fix this so that single-instruction expansions correctly
3714 terminate when they can't handle the range, but the error messages are
3715 worse, and it actually turns out that in every case but one (18-bit wide
3716 branches), you need a multi-instruction expansion to get the full range
3717 anyway. And because 18-bit branches are handled identically to 15-bit
3718 branches, there isn't any point in changing it. */
3721 xg_assembly_relax (IStack
*istack
,
3724 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3725 offsetT pc_offset
, /* offset in fragment */
3726 int min_steps
, /* minimum conversion steps */
3727 long stretch
) /* number of bytes stretched so far */
3729 int steps_taken
= 0;
3731 /* Some of its immeds don't fit. Try to build a relaxed version.
3732 This may go through a couple of stages of single instruction
3733 transformations before we get there. */
3735 TInsn single_target
;
3737 int lateral_steps
= 0;
3738 int istack_size
= istack
->ninsn
;
3740 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3741 && steps_taken
>= min_steps
)
3743 istack_push (istack
, insn
);
3746 current_insn
= *insn
;
3748 /* Walk through all of the single instruction expansions. */
3749 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3752 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3755 if (steps_taken
>= min_steps
)
3757 istack_push (istack
, &single_target
);
3761 current_insn
= single_target
;
3764 /* Now check for a multi-instruction expansion. */
3765 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3767 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3770 if (steps_taken
>= min_steps
)
3772 istack_push (istack
, ¤t_insn
);
3777 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3779 if (steps_taken
>= min_steps
)
3783 istack
->ninsn
= istack_size
;
3786 /* It's not going to work -- use the original. */
3787 istack_push (istack
, insn
);
3793 xg_finish_frag (char *last_insn
,
3794 enum xtensa_relax_statesE frag_state
,
3795 enum xtensa_relax_statesE slot0_state
,
3797 bfd_boolean is_insn
)
3799 /* Finish off this fragment so that it has at LEAST the desired
3800 max_growth. If it doesn't fit in this fragment, close this one
3801 and start a new one. In either case, return a pointer to the
3802 beginning of the growth area. */
3806 frag_grow (max_growth
);
3807 old_frag
= frag_now
;
3809 frag_now
->fr_opcode
= last_insn
;
3811 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3813 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3814 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3816 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3817 xtensa_set_frag_assembly_state (frag_now
);
3819 /* Just to make sure that we did not split it up. */
3820 gas_assert (old_frag
->fr_next
== frag_now
);
3824 /* Return TRUE if the target frag is one of the next non-empty frags. */
3827 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3832 for (; fragP
; fragP
= fragP
->fr_next
)
3834 if (fragP
== target
)
3836 if (fragP
->fr_fix
!= 0)
3838 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3840 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3841 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3843 if (fragP
->fr_type
== rs_space
)
3851 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3853 xtensa_isa isa
= xtensa_default_isa
;
3855 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3860 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3861 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3864 for (i
= 0; i
< num_ops
; i
++)
3866 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3872 if (target_op
== -1)
3875 if (insn
->ntok
<= target_op
)
3878 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3881 sym
= insn
->tok
[target_op
].X_add_symbol
;
3885 if (insn
->tok
[target_op
].X_add_number
!= 0)
3888 target_frag
= symbol_get_frag (sym
);
3889 if (target_frag
== NULL
)
3892 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3893 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3901 xg_add_branch_and_loop_targets (TInsn
*insn
)
3903 xtensa_isa isa
= xtensa_default_isa
;
3904 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3906 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3909 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3910 && insn
->tok
[i
].X_op
== O_symbol
)
3911 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3915 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3916 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3920 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3922 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3923 && insn
->tok
[i
].X_op
== O_symbol
)
3925 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3926 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3927 if (S_IS_DEFINED (sym
))
3928 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3935 /* Return FALSE if no error. */
3938 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3943 switch (instr_spec
->typ
)
3946 new_insn
->insn_type
= ITYPE_INSN
;
3947 new_insn
->opcode
= instr_spec
->opcode
;
3949 case INSTR_LITERAL_DEF
:
3950 new_insn
->insn_type
= ITYPE_LITERAL
;
3951 new_insn
->opcode
= XTENSA_UNDEFINED
;
3953 case INSTR_LABEL_DEF
:
3956 new_insn
->is_specific_opcode
= FALSE
;
3957 new_insn
->debug_line
= old_insn
->debug_line
;
3958 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3960 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3963 const expressionS
*src_exp
;
3969 /* The expression must be the constant. */
3970 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3971 exp
= &new_insn
->tok
[b_op
->op_num
];
3972 set_expr_const (exp
, b_op
->op_data
);
3976 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3977 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3978 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3979 exp
= &new_insn
->tok
[b_op
->op_num
];
3980 copy_expr (exp
, src_exp
);
3985 as_bad (_("can't handle generation of literal/labels yet"));
3989 as_bad (_("can't handle undefined OP TYPE"));
3994 new_insn
->ntok
= num_ops
;
3999 /* Return TRUE if it was simplified. */
4002 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
4004 TransitionRule
*rule
;
4005 BuildInstr
*insn_spec
;
4007 if (old_insn
->is_specific_opcode
|| !density_supported
)
4010 rule
= xg_instruction_match (old_insn
);
4014 insn_spec
= rule
->to_instr
;
4015 /* There should only be one. */
4016 gas_assert (insn_spec
!= NULL
);
4017 gas_assert (insn_spec
->next
== NULL
);
4018 if (insn_spec
->next
!= NULL
)
4021 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4027 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4028 l32i.n. (2) Check the number of operands. (3) Place the instruction
4029 tokens into the stack or relax it and place multiple
4030 instructions/literals onto the stack. Return FALSE if no error. */
4033 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4037 bfd_boolean do_expand
;
4039 tinsn_init (&new_insn
);
4041 /* Narrow it if we can. xg_simplify_insn now does all the
4042 appropriate checking (e.g., for the density option). */
4043 if (xg_simplify_insn (orig_insn
, &new_insn
))
4044 orig_insn
= &new_insn
;
4046 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4048 if (orig_insn
->ntok
< noperands
)
4050 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4051 "found %d operands for '%s': Expected %d",
4054 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4058 if (orig_insn
->ntok
> noperands
)
4059 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4060 "found %d operands for '%s': Expected %d",
4063 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4066 /* If there are not enough operands, we will assert above. If there
4067 are too many, just cut out the extras here. */
4068 orig_insn
->ntok
= noperands
;
4070 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4073 /* Special case for extui opcode which has constraints not handled
4074 by the ordinary operand encoding checks. The number of operands
4075 and related syntax issues have already been checked. */
4076 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4078 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4079 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4080 if (shiftimm
+ maskimm
> 32)
4082 as_bad (_("immediate operands sum to greater than 32"));
4087 /* If the instruction will definitely need to be relaxed, it is better
4088 to expand it now for better scheduling. Decide whether to expand
4090 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4092 /* Calls should be expanded to longcalls only in the backend relaxation
4093 so that the assembly scheduler will keep the L32R/CALLX instructions
4095 if (is_direct_call_opcode (orig_insn
->opcode
))
4098 if (tinsn_has_symbolic_operands (orig_insn
))
4100 /* The values of symbolic operands are not known yet, so only expand
4101 now if an operand is "complex" (e.g., difference of symbols) and
4102 will have to be stored as a literal regardless of the value. */
4103 if (!tinsn_has_complex_operands (orig_insn
))
4106 else if (xg_immeds_fit (orig_insn
))
4110 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4112 istack_push (istack
, orig_insn
);
4118 /* Return TRUE if the section flags are marked linkonce
4119 or the name is .gnu.linkonce.*. */
4121 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4124 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4126 flagword flags
, link_once_flags
;
4128 flags
= bfd_get_section_flags (abfd
, sec
);
4129 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4131 /* Flags might not be set yet. */
4132 if (!link_once_flags
4133 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4134 link_once_flags
= SEC_LINK_ONCE
;
4136 return (link_once_flags
!= 0);
4141 xtensa_add_literal_sym (symbolS
*sym
)
4145 l
= XNEW (sym_list
);
4147 l
->next
= literal_syms
;
4153 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4155 static int lit_num
= 0;
4156 static char name
[256];
4159 sprintf (name
, ".L_lit_sym%d", lit_num
);
4161 /* Create a local symbol. If it is in a linkonce section, we have to
4162 be careful to make sure that if it is used in a relocation that the
4163 symbol will be in the output file. */
4164 if (get_is_linkonce_section (stdoutput
, sec
))
4166 symbolP
= symbol_new (name
, sec
, 0, frag
);
4167 S_CLEAR_EXTERNAL (symbolP
);
4168 /* symbolP->local = 1; */
4171 symbolP
= symbol_new (name
, sec
, 0, frag
);
4173 xtensa_add_literal_sym (symbolP
);
4180 /* Currently all literals that are generated here are 32-bit L32R targets. */
4183 xg_assemble_literal (/* const */ TInsn
*insn
)
4186 symbolS
*lit_sym
= NULL
;
4187 bfd_reloc_code_real_type reloc
;
4188 bfd_boolean pcrel
= FALSE
;
4191 /* size = 4 for L32R. It could easily be larger when we move to
4192 larger constants. Add a parameter later. */
4193 offsetT litsize
= 4;
4194 offsetT litalign
= 2; /* 2^2 = 4 */
4195 expressionS saved_loc
;
4196 expressionS
* emit_val
;
4198 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4200 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4201 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4203 xtensa_switch_to_literal_fragment (&state
);
4205 emit_val
= &insn
->tok
[0];
4206 if (emit_val
->X_op
== O_big
)
4208 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4211 /* This happens when someone writes a "movi a2, big_number". */
4212 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4213 _("invalid immediate"));
4214 xtensa_restore_emit_state (&state
);
4219 /* Force a 4-byte align here. Note that this opens a new frag, so all
4220 literals done with this function have a frag to themselves. That's
4221 important for the way text section literals work. */
4222 frag_align (litalign
, 0, 0);
4223 record_alignment (now_seg
, litalign
);
4225 switch (emit_val
->X_op
)
4235 p
= frag_more (litsize
);
4236 xtensa_set_frag_assembly_state (frag_now
);
4237 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4238 if (emit_val
->X_add_symbol
)
4239 emit_val
->X_op
= O_symbol
;
4241 emit_val
->X_op
= O_constant
;
4242 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4243 litsize
, emit_val
, pcrel
, reloc
);
4247 emit_expr (emit_val
, litsize
);
4251 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4252 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4253 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4254 lit_sym
= frag_now
->fr_symbol
;
4257 xtensa_restore_emit_state (&state
);
4263 xg_assemble_literal_space (/* const */ int size
, int slot
)
4266 /* We might have to do something about this alignment. It only
4267 takes effect if something is placed here. */
4268 offsetT litalign
= 2; /* 2^2 = 4 */
4269 fragS
*lit_saved_frag
;
4271 gas_assert (size
% 4 == 0);
4273 xtensa_switch_to_literal_fragment (&state
);
4275 /* Force a 4-byte align here. */
4276 frag_align (litalign
, 0, 0);
4277 record_alignment (now_seg
, litalign
);
4281 lit_saved_frag
= frag_now
;
4282 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4283 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4284 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4287 xtensa_restore_emit_state (&state
);
4288 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4292 /* Put in a fixup record based on the opcode.
4293 Return TRUE on success. */
4296 xg_add_opcode_fix (TInsn
*tinsn
,
4304 xtensa_opcode opcode
= tinsn
->opcode
;
4305 bfd_reloc_code_real_type reloc
;
4306 reloc_howto_type
*howto
;
4310 reloc
= BFD_RELOC_NONE
;
4312 /* First try the special cases for "alternate" relocs. */
4313 if (opcode
== xtensa_l32r_opcode
)
4315 if (fragP
->tc_frag_data
.use_absolute_literals
)
4316 reloc
= encode_alt_reloc (slot
);
4318 else if (opcode
== xtensa_const16_opcode
)
4320 if (exp
->X_op
== O_lo16
)
4322 reloc
= encode_reloc (slot
);
4323 exp
->X_op
= O_symbol
;
4325 else if (exp
->X_op
== O_hi16
)
4327 reloc
= encode_alt_reloc (slot
);
4328 exp
->X_op
= O_symbol
;
4332 if (opnum
!= get_relaxable_immed (opcode
))
4334 as_bad (_("invalid relocation for operand %i of '%s'"),
4335 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4339 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4340 into the symbol table where the generic portions of the assembler
4341 won't know what to do with them. */
4342 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4344 as_bad (_("invalid expression for operand %i of '%s'"),
4345 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4349 /* Next try the generic relocs. */
4350 if (reloc
== BFD_RELOC_NONE
)
4351 reloc
= encode_reloc (slot
);
4352 if (reloc
== BFD_RELOC_NONE
)
4354 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4358 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4361 as_bad (_("undefined symbol for opcode \"%s\""),
4362 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4366 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4367 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4368 howto
->pc_relative
, reloc
);
4369 the_fix
->fx_no_overflow
= 1;
4370 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4371 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4372 the_fix
->tc_fix_data
.slot
= slot
;
4379 xg_emit_insn_to_buf (TInsn
*tinsn
,
4383 bfd_boolean build_fix
)
4385 static xtensa_insnbuf insnbuf
= NULL
;
4386 bfd_boolean has_symbolic_immed
= FALSE
;
4387 bfd_boolean ok
= TRUE
;
4390 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4392 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4393 if (has_symbolic_immed
&& build_fix
)
4396 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4397 int slot
= xg_get_single_slot (tinsn
->opcode
);
4398 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4399 expressionS
*exp
= &tinsn
->tok
[opnum
];
4401 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4404 fragP
->tc_frag_data
.is_insn
= TRUE
;
4405 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4406 (unsigned char *) buf
, 0);
4412 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4414 symbolS
*sym
= get_special_literal_symbol ();
4418 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4419 for (i
= 0; i
< insn
->ntok
; i
++)
4420 if (insn
->tok
[i
].X_add_symbol
== sym
)
4421 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4427 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4429 symbolS
*sym
= get_special_label_symbol ();
4431 for (i
= 0; i
< insn
->ntok
; i
++)
4432 if (insn
->tok
[i
].X_add_symbol
== sym
)
4433 insn
->tok
[i
].X_add_symbol
= label_sym
;
4438 /* Return TRUE if the instruction can write to the specified
4439 integer register. */
4442 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4446 xtensa_isa isa
= xtensa_default_isa
;
4448 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4450 for (i
= 0; i
< num_ops
; i
++)
4453 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4454 if ((inout
== 'o' || inout
== 'm')
4455 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4457 xtensa_regfile opnd_rf
=
4458 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4459 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4461 if ((insn
->tok
[i
].X_op
== O_register
)
4462 && (insn
->tok
[i
].X_add_number
== regnum
))
4472 is_bad_loopend_opcode (const TInsn
*tinsn
)
4474 xtensa_opcode opcode
= tinsn
->opcode
;
4476 if (opcode
== XTENSA_UNDEFINED
)
4479 if (opcode
== xtensa_call0_opcode
4480 || opcode
== xtensa_callx0_opcode
4481 || opcode
== xtensa_call4_opcode
4482 || opcode
== xtensa_callx4_opcode
4483 || opcode
== xtensa_call8_opcode
4484 || opcode
== xtensa_callx8_opcode
4485 || opcode
== xtensa_call12_opcode
4486 || opcode
== xtensa_callx12_opcode
4487 || opcode
== xtensa_isync_opcode
4488 || opcode
== xtensa_ret_opcode
4489 || opcode
== xtensa_ret_n_opcode
4490 || opcode
== xtensa_retw_opcode
4491 || opcode
== xtensa_retw_n_opcode
4492 || opcode
== xtensa_waiti_opcode
4493 || opcode
== xtensa_rsr_lcount_opcode
)
4500 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4501 This allows the debugger to add unaligned labels.
4502 Also, the assembler generates stabs labels that need
4503 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4506 is_unaligned_label (symbolS
*sym
)
4508 const char *name
= S_GET_NAME (sym
);
4509 static size_t fake_size
= 0;
4513 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4516 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4518 fake_size
= strlen (FAKE_LABEL_NAME
);
4521 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4522 && (name
[fake_size
] == 'F'
4523 || name
[fake_size
] == 'L'
4524 || (name
[fake_size
] == 'e'
4525 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4533 next_non_empty_frag (const fragS
*fragP
)
4535 fragS
*next_fragP
= fragP
->fr_next
;
4537 /* Sometimes an empty will end up here due storage allocation issues.
4538 So we have to skip until we find something legit. */
4539 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4540 next_fragP
= next_fragP
->fr_next
;
4542 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4550 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4552 xtensa_opcode out_opcode
;
4553 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4555 if (next_fragP
== NULL
)
4558 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4559 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4561 *opcode
= out_opcode
;
4569 frag_format_size (const fragS
*fragP
)
4571 static xtensa_insnbuf insnbuf
= NULL
;
4572 xtensa_isa isa
= xtensa_default_isa
;
4577 insnbuf
= xtensa_insnbuf_alloc (isa
);
4580 return XTENSA_UNDEFINED
;
4582 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4583 (unsigned char *) fragP
->fr_literal
, 0);
4585 fmt
= xtensa_format_decode (isa
, insnbuf
);
4586 if (fmt
== XTENSA_UNDEFINED
)
4587 return XTENSA_UNDEFINED
;
4588 fmt_size
= xtensa_format_length (isa
, fmt
);
4590 /* If the next format won't be changing due to relaxation, just
4591 return the length of the first format. */
4592 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4595 /* If during relaxation we have to pull an instruction out of a
4596 multi-slot instruction, we will return the more conservative
4597 number. This works because alignment on bigger instructions
4598 is more restrictive than alignment on smaller instructions.
4599 This is more conservative than we would like, but it happens
4602 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4605 /* If we aren't doing one of our own relaxations or it isn't
4606 slot-based, then the insn size won't change. */
4607 if (fragP
->fr_type
!= rs_machine_dependent
)
4609 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4612 /* If an instruction is about to grow, return the longer size. */
4613 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4614 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4615 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4617 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4618 instruction in the relaxed version is of length 3. (The case
4619 where we have to pull the instruction out of a FLIX bundle
4620 is handled conservatively above.) However, frags with opcodes
4621 that are expanding to wide branches end up having formats that
4622 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4623 we can't tell directly what format the relaxer picked. This
4624 is a wart in the design of the relaxer that should someday be
4625 fixed, but would require major changes, or at least should
4626 be accompanied by major changes to make use of that data.
4628 In any event, we can tell that we are expanding from a single-slot
4629 format to a wider one with the logic below. */
4632 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4634 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4636 if (relaxed_size
== xtensa_format_length (isa
, i
))
4637 return relaxed_size
;
4643 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4644 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4651 next_frag_format_size (const fragS
*fragP
)
4653 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4654 return frag_format_size (next_fragP
);
4658 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4659 required two-byte instructions to be treated as three-byte instructions
4660 for loop instruction alignment. This restriction was removed beginning
4661 with Xtensa LX. Now the only requirement on loop instruction alignment
4662 is that the first instruction of the loop must appear at an address that
4663 does not cross a fetch boundary. */
4666 get_loop_align_size (int insn_size
)
4668 if (insn_size
== XTENSA_UNDEFINED
)
4669 return xtensa_fetch_width
;
4671 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4678 /* If the next legit fragment is an end-of-loop marker,
4679 switch its state so it will instantiate a NOP. */
4682 update_next_frag_state (fragS
*fragP
)
4684 fragS
*next_fragP
= fragP
->fr_next
;
4685 fragS
*new_target
= NULL
;
4689 /* We are guaranteed there will be one of these... */
4690 while (!(next_fragP
->fr_type
== rs_machine_dependent
4691 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4692 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4693 next_fragP
= next_fragP
->fr_next
;
4695 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4696 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4697 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4699 /* ...and one of these. */
4700 new_target
= next_fragP
->fr_next
;
4701 while (!(new_target
->fr_type
== rs_machine_dependent
4702 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4703 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4704 new_target
= new_target
->fr_next
;
4706 gas_assert (new_target
->fr_type
== rs_machine_dependent
4707 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4708 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4711 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4713 if (next_fragP
->fr_type
== rs_machine_dependent
4714 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4716 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4720 next_fragP
= next_fragP
->fr_next
;
4726 next_frag_is_branch_target (const fragS
*fragP
)
4728 /* Sometimes an empty will end up here due to storage allocation issues,
4729 so we have to skip until we find something legit. */
4730 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4732 if (fragP
->tc_frag_data
.is_branch_target
)
4734 if (fragP
->fr_fix
!= 0)
4742 next_frag_is_loop_target (const fragS
*fragP
)
4744 /* Sometimes an empty will end up here due storage allocation issues.
4745 So we have to skip until we find something legit. */
4746 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4748 if (fragP
->tc_frag_data
.is_loop_target
)
4750 if (fragP
->fr_fix
!= 0)
4757 /* As specified in the relaxation table, when a loop instruction is
4758 relaxed, there are 24 bytes between the loop instruction itself and
4759 the first instruction in the loop. */
4761 #define RELAXED_LOOP_INSN_BYTES 24
4764 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4766 const fragS
*next_fragp
= fragp
->fr_next
;
4767 xtensa_opcode next_opcode
;
4769 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4772 /* Sometimes an empty will end up here due to storage allocation issues,
4773 so we have to skip until we find something legit. */
4774 while (next_fragp
->fr_fix
== 0)
4775 next_fragp
= next_fragp
->fr_next
;
4777 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4780 /* There is some implicit knowledge encoded in here.
4781 The LOOP instructions that are NOT RELAX_IMMED have
4782 been relaxed. Note that we can assume that the LOOP
4783 instruction is in slot 0 because loops aren't bundleable. */
4784 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4785 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4791 /* Mark a location where we can later insert literal frags. Update
4792 the section's literal_pool_loc, so subsequent literals can be
4793 placed nearest to their use. */
4796 xtensa_mark_literal_pool_location (void)
4798 /* Any labels pointing to the current location need
4799 to be adjusted to after the literal pool. */
4801 fragS
*pool_location
;
4803 if (use_literal_section
)
4806 /* We stash info in these frags so we can later move the literal's
4807 fixes into this frchain's fix list. */
4808 pool_location
= frag_now
;
4809 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4810 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4811 /* Just record this frag. */
4812 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4813 frag_variant (rs_machine_dependent
, 0, 0,
4814 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4815 xtensa_set_frag_assembly_state (frag_now
);
4816 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4817 frag_variant (rs_machine_dependent
, 0, 0,
4818 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4819 xtensa_set_frag_assembly_state (frag_now
);
4821 /* Now put a frag into the literal pool that points to this location. */
4822 set_literal_pool_location (now_seg
, pool_location
);
4823 xtensa_switch_to_non_abs_literal_fragment (&s
);
4824 frag_align (2, 0, 0);
4825 record_alignment (now_seg
, 2);
4827 /* Close whatever frag is there. */
4828 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4829 xtensa_set_frag_assembly_state (frag_now
);
4830 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4831 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4832 xtensa_restore_emit_state (&s
);
4833 xtensa_set_frag_assembly_state (frag_now
);
4837 /* Build a nop of the correct size into tinsn. */
4840 build_nop (TInsn
*tinsn
, int size
)
4846 tinsn
->opcode
= xtensa_nop_n_opcode
;
4848 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4849 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4853 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4855 tinsn
->opcode
= xtensa_or_opcode
;
4856 set_expr_const (&tinsn
->tok
[0], 1);
4857 set_expr_const (&tinsn
->tok
[1], 1);
4858 set_expr_const (&tinsn
->tok
[2], 1);
4862 tinsn
->opcode
= xtensa_nop_opcode
;
4864 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4869 /* Assemble a NOP of the requested size in the buffer. User must have
4870 allocated "buf" with at least "size" bytes. */
4873 assemble_nop (int size
, char *buf
)
4875 static xtensa_insnbuf insnbuf
= NULL
;
4878 build_nop (&tinsn
, size
);
4881 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4883 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4884 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4885 (unsigned char *) buf
, 0);
4889 /* Return the number of bytes for the offset of the expanded loop
4890 instruction. This should be incorporated into the relaxation
4891 specification but is hard-coded here. This is used to auto-align
4892 the loop instruction. It is invalid to call this function if the
4893 configuration does not have loops or if the opcode is not a loop
4897 get_expanded_loop_offset (xtensa_opcode opcode
)
4899 /* This is the OFFSET of the loop instruction in the expanded loop.
4900 This MUST correspond directly to the specification of the loop
4901 expansion. It will be validated on fragment conversion. */
4902 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4903 if (opcode
== xtensa_loop_opcode
)
4905 if (opcode
== xtensa_loopnez_opcode
)
4907 if (opcode
== xtensa_loopgtz_opcode
)
4909 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4915 get_literal_pool_location (segT seg
)
4917 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4918 struct litpool_frag
*lpf
;
4919 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4923 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4924 { /* Skip "candidates" for now. */
4925 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4929 /* Must convert a lower-priority pool. */
4930 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4932 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4935 /* Still no match -- try for a low priority pool. */
4936 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4938 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4942 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4947 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4949 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4953 /* Set frag assembly state should be called when a new frag is
4954 opened and after a frag has been closed. */
4957 xtensa_set_frag_assembly_state (fragS
*fragP
)
4959 if (!density_supported
)
4960 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4962 /* This function is called from subsegs_finish, which is called
4963 after xtensa_end, so we can't use "use_transform" or
4964 "use_schedule" here. */
4965 if (!directive_state
[directive_transform
])
4966 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4967 if (directive_state
[directive_longcalls
])
4968 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4969 fragP
->tc_frag_data
.use_absolute_literals
=
4970 directive_state
[directive_absolute_literals
];
4971 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4976 relaxable_section (asection
*sec
)
4978 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4979 && strcmp (sec
->name
, ".eh_frame") != 0);
4984 xtensa_mark_frags_for_org (void)
4988 /* Walk over each fragment of all of the current segments. If we find
4989 a .org frag in any of the segments, mark all frags prior to it as
4990 "no transform", which will prevent linker optimizations from messing
4991 up the .org distance. This should be done after
4992 xtensa_find_unmarked_state_frags, because we don't want to worry here
4993 about that function trashing the data we save here. */
4995 for (seclist
= &stdoutput
->sections
;
4996 seclist
&& *seclist
;
4997 seclist
= &(*seclist
)->next
)
4999 segT sec
= *seclist
;
5000 segment_info_type
*seginfo
;
5003 flags
= bfd_get_section_flags (stdoutput
, sec
);
5004 if (flags
& SEC_DEBUGGING
)
5006 if (!(flags
& SEC_ALLOC
))
5009 seginfo
= seg_info (sec
);
5010 if (seginfo
&& seginfo
->frchainP
)
5012 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
5013 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5014 fragP
= fragP
->fr_next
)
5016 /* cvt_frag_to_fill has changed the fr_type of org frags to
5017 rs_fill, so use the value as cached in rs_subtype here. */
5018 if (fragP
->fr_subtype
== RELAX_ORG
)
5020 while (last_fragP
!= fragP
->fr_next
)
5022 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5023 last_fragP
= last_fragP
->fr_next
;
5033 xtensa_find_unmarked_state_frags (void)
5037 /* Walk over each fragment of all of the current segments. For each
5038 unmarked fragment, mark it with the same info as the previous
5040 for (seclist
= &stdoutput
->sections
;
5041 seclist
&& *seclist
;
5042 seclist
= &(*seclist
)->next
)
5044 segT sec
= *seclist
;
5045 segment_info_type
*seginfo
;
5048 flags
= bfd_get_section_flags (stdoutput
, sec
);
5049 if (flags
& SEC_DEBUGGING
)
5051 if (!(flags
& SEC_ALLOC
))
5054 seginfo
= seg_info (sec
);
5055 if (seginfo
&& seginfo
->frchainP
)
5057 fragS
*last_fragP
= 0;
5058 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5059 fragP
= fragP
->fr_next
)
5061 if (fragP
->fr_fix
!= 0
5062 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5064 if (last_fragP
== 0)
5066 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5067 _("assembly state not set for first frag in section %s"),
5072 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5073 fragP
->tc_frag_data
.is_no_density
=
5074 last_fragP
->tc_frag_data
.is_no_density
;
5075 fragP
->tc_frag_data
.is_no_transform
=
5076 last_fragP
->tc_frag_data
.is_no_transform
;
5077 fragP
->tc_frag_data
.use_longcalls
=
5078 last_fragP
->tc_frag_data
.use_longcalls
;
5079 fragP
->tc_frag_data
.use_absolute_literals
=
5080 last_fragP
->tc_frag_data
.use_absolute_literals
;
5083 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5092 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5094 void *unused ATTRIBUTE_UNUSED
)
5096 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5097 segment_info_type
*seginfo
= seg_info (sec
);
5098 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5100 if (flags
& SEC_CODE
)
5102 xtensa_isa isa
= xtensa_default_isa
;
5103 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5104 while (frag
!= NULL
)
5106 if (frag
->tc_frag_data
.is_branch_target
)
5109 addressT branch_align
, frag_addr
;
5112 xtensa_insnbuf_from_chars
5113 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5114 fmt
= xtensa_format_decode (isa
, insnbuf
);
5115 op_size
= xtensa_format_length (isa
, fmt
);
5116 branch_align
= 1 << branch_align_power (sec
);
5117 frag_addr
= frag
->fr_address
% branch_align
;
5118 if (frag_addr
+ op_size
> branch_align
)
5119 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5120 _("unaligned branch target: %d bytes at 0x%lx"),
5121 op_size
, (long) frag
->fr_address
);
5123 frag
= frag
->fr_next
;
5125 xtensa_insnbuf_free (isa
, insnbuf
);
5131 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5133 void *unused ATTRIBUTE_UNUSED
)
5135 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5136 segment_info_type
*seginfo
= seg_info (sec
);
5137 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5138 xtensa_isa isa
= xtensa_default_isa
;
5140 if (flags
& SEC_CODE
)
5142 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5143 while (frag
!= NULL
)
5145 if (frag
->tc_frag_data
.is_first_loop_insn
)
5151 if (frag
->fr_fix
== 0)
5152 frag
= next_non_empty_frag (frag
);
5156 xtensa_insnbuf_from_chars
5157 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5158 fmt
= xtensa_format_decode (isa
, insnbuf
);
5159 op_size
= xtensa_format_length (isa
, fmt
);
5160 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5162 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5163 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5164 _("unaligned loop: %d bytes at 0x%lx"),
5165 op_size
, (long) frag
->fr_address
);
5168 frag
= frag
->fr_next
;
5170 xtensa_insnbuf_free (isa
, insnbuf
);
5176 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5178 xtensa_isa isa
= xtensa_default_isa
;
5179 static xtensa_insnbuf insnbuf
= NULL
;
5180 static xtensa_insnbuf slotbuf
= NULL
;
5183 bfd_boolean alt_reloc
;
5184 xtensa_opcode opcode
;
5185 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5187 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5189 as_fatal (_("unexpected fix"));
5193 insnbuf
= xtensa_insnbuf_alloc (isa
);
5194 slotbuf
= xtensa_insnbuf_alloc (isa
);
5197 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5198 fmt
= xtensa_format_decode (isa
, insnbuf
);
5199 if (fmt
== XTENSA_UNDEFINED
)
5200 as_fatal (_("undecodable fix"));
5201 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5202 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5203 if (opcode
== XTENSA_UNDEFINED
)
5204 as_fatal (_("undecodable fix"));
5206 /* CONST16 immediates are not PC-relative, despite the fact that we
5207 reuse the normal PC-relative operand relocations for the low part
5208 of a CONST16 operand. */
5209 if (opcode
== xtensa_const16_opcode
)
5212 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5213 get_relaxable_immed (opcode
), val
,
5214 fixP
->fx_file
, fixP
->fx_line
);
5216 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5217 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5223 /* External Functions and Other GAS Hooks. */
5226 xtensa_target_format (void)
5228 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5233 xtensa_file_arch_init (bfd
*abfd
)
5235 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5240 md_number_to_chars (char *buf
, valueT val
, int n
)
5242 if (target_big_endian
)
5243 number_to_chars_bigendian (buf
, val
, n
);
5245 number_to_chars_littleendian (buf
, val
, n
);
5249 xg_init_global_config (void)
5251 target_big_endian
= XCHAL_HAVE_BE
;
5253 density_supported
= XCHAL_HAVE_DENSITY
;
5254 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5255 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5257 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5258 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5262 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5264 xg_init_global_config ();
5267 /* This function is called once, at assembler startup time. It should
5268 set up all the tables, etc. that the MD part of the assembler will
5274 segT current_section
= now_seg
;
5275 int current_subsec
= now_subseg
;
5279 xtensa_default_isa
= xtensa_isa_init (0, 0);
5280 isa
= xtensa_default_isa
;
5284 /* Set up the literal sections. */
5285 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5287 subseg_set (current_section
, current_subsec
);
5289 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5290 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5291 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5292 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5293 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5294 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5295 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5296 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5297 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5298 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5299 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5300 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5301 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5302 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5303 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5304 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5305 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5306 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5307 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5308 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5309 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5310 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5311 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5312 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5313 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5314 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5315 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5316 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5317 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5318 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5319 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5321 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5323 int format_slots
= xtensa_format_num_slots (isa
, i
);
5324 if (format_slots
> config_max_slots
)
5325 config_max_slots
= format_slots
;
5328 xg_init_vinsn (&cur_vinsn
);
5330 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5332 init_op_placement_info_table ();
5334 /* Set up the assembly state. */
5335 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5336 xtensa_set_frag_assembly_state (frag_now
);
5340 /* TC_INIT_FIX_DATA hook */
5343 xtensa_init_fix_data (fixS
*x
)
5345 x
->tc_fix_data
.slot
= 0;
5346 x
->tc_fix_data
.X_add_symbol
= NULL
;
5347 x
->tc_fix_data
.X_add_number
= 0;
5351 /* tc_frob_label hook */
5354 xtensa_frob_label (symbolS
*sym
)
5358 if (cur_vinsn
.inside_bundle
)
5360 as_bad (_("labels are not valid inside bundles"));
5364 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5366 /* Since the label was already attached to a frag associated with the
5367 previous basic block, it now needs to be reset to the current frag. */
5368 symbol_set_frag (sym
, frag_now
);
5369 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5371 if (generating_literals
)
5372 xtensa_add_literal_sym (sym
);
5374 xtensa_add_insn_label (sym
);
5376 if (symbol_get_tc (sym
)->is_loop_target
)
5378 if ((get_last_insn_flags (now_seg
, now_subseg
)
5379 & FLAG_IS_BAD_LOOPEND
) != 0)
5380 as_bad (_("invalid last instruction for a zero-overhead loop"));
5382 xtensa_set_frag_assembly_state (frag_now
);
5383 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5384 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5386 xtensa_set_frag_assembly_state (frag_now
);
5387 xtensa_move_labels (frag_now
, 0);
5390 /* No target aligning in the absolute section. */
5391 if (now_seg
!= absolute_section
5392 && !is_unaligned_label (sym
)
5393 && !generating_literals
)
5395 xtensa_set_frag_assembly_state (frag_now
);
5397 if (do_align_targets ())
5398 frag_var (rs_machine_dependent
, 0, (int) freq
,
5399 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5400 frag_now
->fr_offset
, NULL
);
5402 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5403 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5404 xtensa_set_frag_assembly_state (frag_now
);
5405 xtensa_move_labels (frag_now
, 0);
5408 /* We need to mark the following properties even if we aren't aligning. */
5410 /* If the label is already known to be a branch target, i.e., a
5411 forward branch, mark the frag accordingly. Backward branches
5412 are handled by xg_add_branch_and_loop_targets. */
5413 if (symbol_get_tc (sym
)->is_branch_target
)
5414 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5416 /* Loops only go forward, so they can be identified here. */
5417 if (symbol_get_tc (sym
)->is_loop_target
)
5418 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5420 dwarf2_emit_label (sym
);
5424 /* tc_unrecognized_line hook */
5427 xtensa_unrecognized_line (int ch
)
5432 if (cur_vinsn
.inside_bundle
== 0)
5434 /* PR8110: Cannot emit line number info inside a FLIX bundle
5435 when using --gstabs. Temporarily disable debug info. */
5436 generate_lineno_debug ();
5437 if (debug_type
== DEBUG_STABS
)
5439 xt_saved_debug_type
= debug_type
;
5440 debug_type
= DEBUG_NONE
;
5443 cur_vinsn
.inside_bundle
= 1;
5447 as_bad (_("extra opening brace"));
5453 if (cur_vinsn
.inside_bundle
)
5454 finish_vinsn (&cur_vinsn
);
5457 as_bad (_("extra closing brace"));
5462 as_bad (_("syntax error"));
5469 /* md_flush_pending_output hook */
5472 xtensa_flush_pending_output (void)
5474 /* This line fixes a bug where automatically generated gstabs info
5475 separates a function label from its entry instruction, ending up
5476 with the literal position between the function label and the entry
5477 instruction and crashing code. It only happens with --gstabs and
5478 --text-section-literals, and when several other obscure relaxation
5479 conditions are met. */
5480 if (outputting_stabs_line_debug
)
5483 if (cur_vinsn
.inside_bundle
)
5484 as_bad (_("missing closing brace"));
5486 /* If there is a non-zero instruction fragment, close it. */
5487 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5489 frag_wane (frag_now
);
5491 xtensa_set_frag_assembly_state (frag_now
);
5493 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5495 xtensa_clear_insn_labels ();
5499 /* We had an error while parsing an instruction. The string might look
5500 like this: "insn arg1, arg2 }". If so, we need to see the closing
5501 brace and reset some fields. Otherwise, the vinsn never gets closed
5502 and the num_slots field will grow past the end of the array of slots,
5503 and bad things happen. */
5506 error_reset_cur_vinsn (void)
5508 if (cur_vinsn
.inside_bundle
)
5510 if (*input_line_pointer
== '}'
5511 || *(input_line_pointer
- 1) == '}'
5512 || *(input_line_pointer
- 2) == '}')
5513 xg_clear_vinsn (&cur_vinsn
);
5519 md_assemble (char *str
)
5521 xtensa_isa isa
= xtensa_default_isa
;
5524 bfd_boolean has_underbar
= FALSE
;
5525 char *arg_strings
[MAX_INSN_ARGS
];
5527 TInsn orig_insn
; /* Original instruction from the input. */
5529 tinsn_init (&orig_insn
);
5531 /* Split off the opcode. */
5532 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5533 opname
= xstrndup (str
, opnamelen
);
5535 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5538 as_bad (_("syntax error"));
5542 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5545 /* Check for an underbar prefix. */
5548 has_underbar
= TRUE
;
5552 orig_insn
.insn_type
= ITYPE_INSN
;
5554 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5555 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5557 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5558 extra argument and set the opcode to "CALLXn". */
5559 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5560 && strncasecmp (opname
, "callx", 5) == 0)
5562 unsigned long window_size
;
5565 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5566 if (suffix
!= opname
+ 5
5567 && (window_size
== 0
5570 || window_size
== 12)
5571 && strcasecmp (suffix
, ".tls") == 0)
5573 switch (window_size
)
5575 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5576 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5577 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5578 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5582 as_bad (_("wrong number of operands for '%s'"), opname
);
5585 bfd_reloc_code_real_type reloc
;
5586 char *old_input_line_pointer
;
5587 expressionS
*tok
= &orig_insn
.extra_arg
;
5589 old_input_line_pointer
= input_line_pointer
;
5590 input_line_pointer
= arg_strings
[num_args
- 1];
5593 if (tok
->X_op
== O_symbol
5594 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5595 == BFD_RELOC_XTENSA_TLS_CALL
))
5596 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5598 as_bad (_("bad relocation expression for '%s'"), opname
);
5600 input_line_pointer
= old_input_line_pointer
;
5606 /* Special case: Check for "j.l" pseudo op. */
5607 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5608 && strncasecmp (opname
, "j.l", 3) == 0)
5611 as_bad (_("wrong number of operands for '%s'"), opname
);
5614 char *old_input_line_pointer
;
5615 expressionS
*tok
= &orig_insn
.extra_arg
;
5617 old_input_line_pointer
= input_line_pointer
;
5618 input_line_pointer
= arg_strings
[num_args
- 1];
5620 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5621 input_line_pointer
= old_input_line_pointer
;
5624 orig_insn
.opcode
= xtensa_j_opcode
;
5628 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5630 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5631 if (fmt
== XTENSA_UNDEFINED
)
5633 as_bad (_("unknown opcode or format name '%s'"), opname
);
5634 error_reset_cur_vinsn ();
5637 if (!cur_vinsn
.inside_bundle
)
5639 as_bad (_("format names only valid inside bundles"));
5640 error_reset_cur_vinsn ();
5643 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5644 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5646 cur_vinsn
.format
= fmt
;
5647 free (has_underbar
? opname
- 1 : opname
);
5648 error_reset_cur_vinsn ();
5652 /* Parse the arguments. */
5653 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5655 as_bad (_("syntax error"));
5656 error_reset_cur_vinsn ();
5660 /* Free the opcode and argument strings, now that they've been parsed. */
5661 free (has_underbar
? opname
- 1 : opname
);
5663 while (num_args
-- > 0)
5664 free (arg_strings
[num_args
]);
5666 /* Get expressions for invisible operands. */
5667 if (get_invisible_operands (&orig_insn
))
5669 error_reset_cur_vinsn ();
5673 /* Check for the right number and type of arguments. */
5674 if (tinsn_check_arguments (&orig_insn
))
5676 error_reset_cur_vinsn ();
5680 /* Record the line number for each TInsn, because a FLIX bundle may be
5681 spread across multiple input lines and individual instructions may be
5682 moved around in some cases. */
5683 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5684 dwarf2_where (&orig_insn
.debug_line
);
5685 dwarf2_consume_line_info ();
5687 xg_add_branch_and_loop_targets (&orig_insn
);
5689 /* Check that immediate value for ENTRY is >= 16. */
5690 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5692 expressionS
*exp
= &orig_insn
.tok
[2];
5693 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5694 as_warn (_("entry instruction with stack decrement < 16"));
5698 assemble_tokens (opcode, tok, ntok);
5699 expand the tokens from the orig_insn into the
5700 stack of instructions that will not expand
5701 unless required at relaxation time. */
5703 if (!cur_vinsn
.inside_bundle
)
5704 emit_single_op (&orig_insn
);
5705 else /* We are inside a bundle. */
5707 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5708 cur_vinsn
.num_slots
++;
5709 if (*input_line_pointer
== '}'
5710 || *(input_line_pointer
- 1) == '}'
5711 || *(input_line_pointer
- 2) == '}')
5712 finish_vinsn (&cur_vinsn
);
5715 /* We've just emitted a new instruction so clear the list of labels. */
5716 xtensa_clear_insn_labels ();
5718 xtensa_check_frag_count ();
5722 /* HANDLE_ALIGN hook */
5724 /* For a .align directive, we mark the previous block with the alignment
5725 information. This will be placed in the object file in the
5726 property section corresponding to this section. */
5729 xtensa_handle_align (fragS
*fragP
)
5732 && ! fragP
->tc_frag_data
.is_literal
5733 && (fragP
->fr_type
== rs_align
5734 || fragP
->fr_type
== rs_align_code
)
5735 && fragP
->fr_offset
> 0
5736 && now_seg
!= bss_section
)
5738 fragP
->tc_frag_data
.is_align
= TRUE
;
5739 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5742 if (fragP
->fr_type
== rs_align_test
)
5745 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5747 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5748 _("unaligned entry instruction"));
5751 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5752 fragP
->fr_subtype
= RELAX_ORG
;
5756 /* TC_FRAG_INIT hook */
5759 xtensa_frag_init (fragS
*frag
)
5761 xtensa_set_frag_assembly_state (frag
);
5766 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5772 /* Round up a section size to the appropriate boundary. */
5775 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5777 return size
; /* Byte alignment is fine. */
5782 md_pcrel_from (fixS
*fixP
)
5785 static xtensa_insnbuf insnbuf
= NULL
;
5786 static xtensa_insnbuf slotbuf
= NULL
;
5789 xtensa_opcode opcode
;
5792 xtensa_isa isa
= xtensa_default_isa
;
5793 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5794 bfd_boolean alt_reloc
;
5796 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5799 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5804 insnbuf
= xtensa_insnbuf_alloc (isa
);
5805 slotbuf
= xtensa_insnbuf_alloc (isa
);
5808 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5809 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5810 fmt
= xtensa_format_decode (isa
, insnbuf
);
5812 if (fmt
== XTENSA_UNDEFINED
)
5813 as_fatal (_("bad instruction format"));
5815 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5816 as_fatal (_("invalid relocation"));
5818 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5819 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5821 /* Check for "alternate" relocations (operand not specified). None
5822 of the current uses for these are really PC-relative. */
5823 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5825 if (opcode
!= xtensa_l32r_opcode
5826 && opcode
!= xtensa_const16_opcode
)
5827 as_fatal (_("invalid relocation for '%s' instruction"),
5828 xtensa_opcode_name (isa
, opcode
));
5832 opnum
= get_relaxable_immed (opcode
);
5834 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5835 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5837 as_bad_where (fixP
->fx_file
,
5839 _("invalid relocation for operand %d of '%s'"),
5840 opnum
, xtensa_opcode_name (isa
, opcode
));
5843 return 0 - opnd_value
;
5847 /* TC_FORCE_RELOCATION hook */
5850 xtensa_force_relocation (fixS
*fix
)
5852 switch (fix
->fx_r_type
)
5854 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5855 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5856 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5857 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5858 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5859 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5860 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5861 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5862 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5863 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5864 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5865 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5866 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5867 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5868 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5869 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5875 if (linkrelax
&& fix
->fx_addsy
5876 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5879 return generic_force_reloc (fix
);
5883 /* TC_VALIDATE_FIX_SUB hook */
5886 xtensa_validate_fix_sub (fixS
*fix
)
5888 segT add_symbol_segment
, sub_symbol_segment
;
5890 /* The difference of two symbols should be resolved by the assembler when
5891 linkrelax is not set. If the linker may relax the section containing
5892 the symbols, then an Xtensa DIFF relocation must be generated so that
5893 the linker knows to adjust the difference value. */
5894 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5897 /* Make sure both symbols are in the same segment, and that segment is
5898 "normal" and relaxable. If the segment is not "normal", then the
5899 fix is not valid. If the segment is not "relaxable", then the fix
5900 should have been handled earlier. */
5901 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5902 if (! SEG_NORMAL (add_symbol_segment
) ||
5903 ! relaxable_section (add_symbol_segment
))
5905 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5906 return (sub_symbol_segment
== add_symbol_segment
);
5910 /* NO_PSEUDO_DOT hook */
5912 /* This function has nothing to do with pseudo dots, but this is the
5913 nearest macro to where the check needs to take place. FIXME: This
5917 xtensa_check_inside_bundle (void)
5919 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5920 as_bad (_("directives are not valid inside bundles"));
5922 /* This function must always return FALSE because it is called via a
5923 macro that has nothing to do with bundling. */
5928 /* md_elf_section_change_hook */
5931 xtensa_elf_section_change_hook (void)
5933 /* Set up the assembly state. */
5934 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5935 xtensa_set_frag_assembly_state (frag_now
);
5939 /* tc_fix_adjustable hook */
5942 xtensa_fix_adjustable (fixS
*fixP
)
5944 /* We need the symbol name for the VTABLE entries. */
5945 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5946 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5953 /* tc_symbol_new_hook */
5955 symbolS
*expr_symbols
= NULL
;
5958 xtensa_symbol_new_hook (symbolS
*sym
)
5960 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5962 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5969 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5971 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5974 /* Subtracted symbols are only allowed for a few relocation types, and
5975 unless linkrelax is enabled, they should not make it to this point. */
5976 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5977 || fixP
->fx_r_type
== BFD_RELOC_16
5978 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5981 switch (fixP
->fx_r_type
)
5983 case BFD_RELOC_32_PCREL
:
5989 switch (fixP
->fx_r_type
)
5992 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5993 fixP
->fx_signed
= 0;
5996 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5997 fixP
->fx_signed
= 0;
6000 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
6001 fixP
->fx_signed
= 0;
6007 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6008 - S_GET_VALUE (fixP
->fx_subsy
));
6010 /* The difference value gets written out, and the DIFF reloc
6011 identifies the address of the subtracted symbol (i.e., the one
6012 with the lowest address). */
6014 fixP
->fx_offset
-= val
;
6015 fixP
->fx_subsy
= NULL
;
6017 else if (! fixP
->fx_addsy
)
6024 case BFD_RELOC_XTENSA_PLT
:
6025 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
6026 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6029 case BFD_RELOC_XTENSA_TLSDESC_FN
:
6030 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6031 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6032 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6033 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6034 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6035 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6038 case BFD_RELOC_XTENSA_SLOT0_OP
:
6039 case BFD_RELOC_XTENSA_SLOT1_OP
:
6040 case BFD_RELOC_XTENSA_SLOT2_OP
:
6041 case BFD_RELOC_XTENSA_SLOT3_OP
:
6042 case BFD_RELOC_XTENSA_SLOT4_OP
:
6043 case BFD_RELOC_XTENSA_SLOT5_OP
:
6044 case BFD_RELOC_XTENSA_SLOT6_OP
:
6045 case BFD_RELOC_XTENSA_SLOT7_OP
:
6046 case BFD_RELOC_XTENSA_SLOT8_OP
:
6047 case BFD_RELOC_XTENSA_SLOT9_OP
:
6048 case BFD_RELOC_XTENSA_SLOT10_OP
:
6049 case BFD_RELOC_XTENSA_SLOT11_OP
:
6050 case BFD_RELOC_XTENSA_SLOT12_OP
:
6051 case BFD_RELOC_XTENSA_SLOT13_OP
:
6052 case BFD_RELOC_XTENSA_SLOT14_OP
:
6055 /* Write the tentative value of a PC-relative relocation to a
6056 local symbol into the instruction. The value will be ignored
6057 by the linker, and it makes the object file disassembly
6058 readable when all branch targets are encoded in relocations. */
6060 gas_assert (fixP
->fx_addsy
);
6061 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6062 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6064 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6065 - md_pcrel_from (fixP
));
6066 (void) xg_apply_fix_value (fixP
, val
);
6069 else if (! fixP
->fx_addsy
)
6072 if (xg_apply_fix_value (fixP
, val
))
6077 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6078 case BFD_RELOC_XTENSA_TLS_FUNC
:
6079 case BFD_RELOC_XTENSA_TLS_ARG
:
6080 case BFD_RELOC_XTENSA_TLS_CALL
:
6081 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6082 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6083 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6084 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6085 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6086 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6087 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6088 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6089 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6090 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6091 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6092 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6093 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6094 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6095 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6096 /* These all need to be resolved at link-time. Do nothing now. */
6099 case BFD_RELOC_VTABLE_INHERIT
:
6100 case BFD_RELOC_VTABLE_ENTRY
:
6105 as_bad (_("unhandled local relocation fix %s"),
6106 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6112 md_atof (int type
, char *litP
, int *sizeP
)
6114 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6119 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6121 return total_frag_text_expansion (fragP
);
6125 /* Translate internal representation of relocation info to BFD target
6129 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6133 reloc
= XNEW (arelent
);
6134 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6135 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6136 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6138 /* Make sure none of our internal relocations make it this far.
6139 They'd better have been fully resolved by this point. */
6140 gas_assert ((int) fixp
->fx_r_type
> 0);
6142 reloc
->addend
= fixp
->fx_offset
;
6144 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6145 if (reloc
->howto
== NULL
)
6147 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6148 _("cannot represent `%s' relocation in object file"),
6149 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6150 free (reloc
->sym_ptr_ptr
);
6155 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6156 as_fatal (_("internal error; cannot generate `%s' relocation"),
6157 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6163 /* Checks for resource conflicts between instructions. */
6165 /* The func unit stuff could be implemented as bit-vectors rather
6166 than the iterative approach here. If it ends up being too
6167 slow, we will switch it. */
6170 new_resource_table (void *data
,
6173 unit_num_copies_func uncf
,
6174 opcode_num_units_func onuf
,
6175 opcode_funcUnit_use_unit_func ouuf
,
6176 opcode_funcUnit_use_stage_func ousf
)
6179 resource_table
*rt
= XNEW (resource_table
);
6181 rt
->cycles
= cycles
;
6182 rt
->allocated_cycles
= cycles
;
6184 rt
->unit_num_copies
= uncf
;
6185 rt
->opcode_num_units
= onuf
;
6186 rt
->opcode_unit_use
= ouuf
;
6187 rt
->opcode_unit_stage
= ousf
;
6189 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6190 for (i
= 0; i
< cycles
; i
++)
6191 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6198 clear_resource_table (resource_table
*rt
)
6201 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6202 for (j
= 0; j
< rt
->num_units
; j
++)
6203 rt
->units
[i
][j
] = 0;
6207 /* We never shrink it, just fake it into thinking so. */
6210 resize_resource_table (resource_table
*rt
, int cycles
)
6214 rt
->cycles
= cycles
;
6215 if (cycles
<= rt
->allocated_cycles
)
6218 old_cycles
= rt
->allocated_cycles
;
6219 rt
->allocated_cycles
= cycles
;
6221 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6222 for (i
= 0; i
< old_cycles
; i
++)
6223 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6224 for (i
= old_cycles
; i
< cycles
; i
++)
6225 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6230 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6233 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6235 for (i
= 0; i
< uses
; i
++)
6237 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6238 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6239 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6240 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6241 if (copies_in_use
>= copies
)
6249 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6252 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6254 for (i
= 0; i
< uses
; i
++)
6256 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6257 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6258 /* Note that this allows resources to be oversubscribed. That's
6259 essential to the way the optional scheduler works.
6260 resources_available reports when a resource is over-subscribed,
6261 so it's easy to tell. */
6262 rt
->units
[stage
+ cycle
][unit
]++;
6268 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6271 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6273 for (i
= 0; i
< uses
; i
++)
6275 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6276 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6277 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6278 rt
->units
[stage
+ cycle
][unit
]--;
6283 /* Wrapper functions make parameterized resource reservation
6287 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6289 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6295 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6297 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6302 /* Note that this function does not check issue constraints, but
6303 solely whether the hardware is available to execute the given
6304 instructions together. It also doesn't check if the tinsns
6305 write the same state, or access the same tieports. That is
6306 checked by check_t1_t2_reads_and_writes. */
6309 resources_conflict (vliw_insn
*vinsn
)
6312 static resource_table
*rt
= NULL
;
6314 /* This is the most common case by far. Optimize it. */
6315 if (vinsn
->num_slots
== 1)
6320 xtensa_isa isa
= xtensa_default_isa
;
6321 rt
= new_resource_table
6322 (isa
, xtensa_num_pipe_stages
,
6323 xtensa_isa_num_funcUnits (isa
),
6324 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6325 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6326 opcode_funcUnit_use_unit
,
6327 opcode_funcUnit_use_stage
);
6330 clear_resource_table (rt
);
6332 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6334 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6336 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6343 /* finish_vinsn, emit_single_op and helper functions. */
6345 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6346 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6347 static void xg_assemble_vliw_tokens (vliw_insn
*);
6350 /* We have reached the end of a bundle; emit into the frag. */
6353 finish_vinsn (vliw_insn
*vinsn
)
6359 if (find_vinsn_conflicts (vinsn
))
6361 xg_clear_vinsn (vinsn
);
6365 /* First, find a format that works. */
6366 if (vinsn
->format
== XTENSA_UNDEFINED
)
6367 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6369 slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6371 && produce_flix
== FLIX_NONE
)
6373 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6374 xg_clear_vinsn (vinsn
);
6378 if (vinsn
->format
== XTENSA_UNDEFINED
)
6380 as_bad (_("couldn't find a valid instruction format"));
6381 fprintf (stderr
, _(" ops were: "));
6382 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6383 fprintf (stderr
, _(" %s;"),
6384 xtensa_opcode_name (xtensa_default_isa
,
6385 vinsn
->slots
[i
].opcode
));
6386 fprintf (stderr
, _("\n"));
6387 xg_clear_vinsn (vinsn
);
6391 if (vinsn
->num_slots
!= slots
)
6393 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6394 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6395 slots
, vinsn
->num_slots
);
6396 xg_clear_vinsn (vinsn
);
6400 if (resources_conflict (vinsn
))
6402 as_bad (_("illegal resource usage in bundle"));
6403 fprintf (stderr
, " ops were: ");
6404 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6405 fprintf (stderr
, " %s;",
6406 xtensa_opcode_name (xtensa_default_isa
,
6407 vinsn
->slots
[i
].opcode
));
6408 fprintf (stderr
, "\n");
6409 xg_clear_vinsn (vinsn
);
6413 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6415 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6417 symbolS
*lit_sym
= NULL
;
6419 bfd_boolean e
= FALSE
;
6420 bfd_boolean saved_density
= density_supported
;
6422 /* We don't want to narrow ops inside multi-slot bundles. */
6423 if (vinsn
->num_slots
> 1)
6424 density_supported
= FALSE
;
6426 istack_init (&slotstack
);
6427 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6429 vinsn
->slots
[i
].opcode
=
6430 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6432 vinsn
->slots
[i
].ntok
= 0;
6435 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6441 density_supported
= saved_density
;
6445 xg_clear_vinsn (vinsn
);
6449 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6451 TInsn
*insn
= &slotstack
.insn
[j
];
6452 if (insn
->insn_type
== ITYPE_LITERAL
)
6454 gas_assert (lit_sym
== NULL
);
6455 lit_sym
= xg_assemble_literal (insn
);
6459 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6461 xg_resolve_literals (insn
, lit_sym
);
6462 if (j
!= slotstack
.ninsn
- 1)
6463 emit_single_op (insn
);
6467 if (vinsn
->num_slots
> 1)
6469 if (opcode_fits_format_slot
6470 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6473 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6477 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6478 if (vinsn
->format
== XTENSA_UNDEFINED
)
6479 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6481 vinsn
->slots
[i
].opcode
6482 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6485 vinsn
->slots
[i
].ntok
= 0;
6490 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6491 vinsn
->format
= XTENSA_UNDEFINED
;
6496 /* Now check resource conflicts on the modified bundle. */
6497 if (resources_conflict (vinsn
))
6499 as_bad (_("illegal resource usage in bundle"));
6500 fprintf (stderr
, " ops were: ");
6501 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6502 fprintf (stderr
, " %s;",
6503 xtensa_opcode_name (xtensa_default_isa
,
6504 vinsn
->slots
[i
].opcode
));
6505 fprintf (stderr
, "\n");
6506 xg_clear_vinsn (vinsn
);
6510 /* First, find a format that works. */
6511 if (vinsn
->format
== XTENSA_UNDEFINED
)
6512 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6514 xg_assemble_vliw_tokens (vinsn
);
6516 xg_clear_vinsn (vinsn
);
6518 xtensa_check_frag_count ();
6522 /* Given an vliw instruction, what conflicts are there in register
6523 usage and in writes to states and queues?
6525 This function does two things:
6526 1. Reports an error when a vinsn contains illegal combinations
6527 of writes to registers states or queues.
6528 2. Marks individual tinsns as not relaxable if the combination
6529 contains antidependencies.
6531 Job 2 handles things like swap semantics in instructions that need
6532 to be relaxed. For example,
6536 normally would be relaxed to
6541 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6543 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6545 then we can't relax it into
6548 { add a0, a1, a0 ; add a2, a0, a4 ; }
6550 because the value of a0 is trashed before the second add can read it. */
6552 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6555 find_vinsn_conflicts (vliw_insn
*vinsn
)
6559 xtensa_isa isa
= xtensa_default_isa
;
6561 gas_assert (!past_xtensa_end
);
6563 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6565 TInsn
*op1
= &vinsn
->slots
[i
];
6566 if (op1
->is_specific_opcode
)
6567 op1
->keep_wide
= TRUE
;
6569 op1
->keep_wide
= FALSE
;
6572 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6574 TInsn
*op1
= &vinsn
->slots
[i
];
6576 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6579 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6583 TInsn
*op2
= &vinsn
->slots
[j
];
6584 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6585 switch (conflict_type
)
6588 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6589 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6590 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6593 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6594 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6595 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6598 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6599 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6600 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6603 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6604 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6605 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6608 /* Everything is OK. */
6611 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6612 || conflict_type
== 'a');
6619 as_bad (_("multiple branches or jumps in the same bundle"));
6627 /* Check how the state used by t1 and t2 relate.
6630 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6631 case B: no relationship between what is read and written (both could
6632 read the same reg though)
6633 case C: t1 writes a register t2 writes (a register conflict within a
6635 case D: t1 writes a state that t2 also writes
6636 case E: t1 writes a tie queue that t2 also writes
6637 case F: two volatile queue accesses
6641 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6643 xtensa_isa isa
= xtensa_default_isa
;
6644 xtensa_regfile t1_regfile
, t2_regfile
;
6646 int t1_base_reg
, t1_last_reg
;
6647 int t2_base_reg
, t2_last_reg
;
6648 char t1_inout
, t2_inout
;
6650 char conflict
= 'b';
6655 bfd_boolean t1_volatile
= FALSE
;
6656 bfd_boolean t2_volatile
= FALSE
;
6658 /* Check registers. */
6659 for (j
= 0; j
< t2
->ntok
; j
++)
6661 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6664 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6665 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6666 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6668 for (i
= 0; i
< t1
->ntok
; i
++)
6670 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6673 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6675 if (t1_regfile
!= t2_regfile
)
6678 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6679 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6681 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6682 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6684 if (t1_inout
== 'm' || t1_inout
== 'o'
6685 || t2_inout
== 'm' || t2_inout
== 'o')
6692 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6693 t1_last_reg
= (t1_base_reg
6694 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6696 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6698 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6700 if (t1_reg
!= t2_reg
)
6703 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6709 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6715 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6723 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6724 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6725 for (j
= 0; j
< t2_states
; j
++)
6727 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6728 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6729 for (i
= 0; i
< t1_states
; i
++)
6731 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6732 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6733 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6736 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6742 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6748 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6753 /* Check tieports. */
6754 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6755 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6756 for (j
= 0; j
< t2_interfaces
; j
++)
6758 xtensa_interface t2_int
6759 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6760 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6762 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6763 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6766 for (i
= 0; i
< t1_interfaces
; i
++)
6768 xtensa_interface t1_int
6769 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6770 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6772 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6773 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6776 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6779 if (t1_int
!= t2_int
)
6782 if (t2_inout
== 'i' && t1_inout
== 'o')
6788 if (t1_inout
== 'i' && t2_inout
== 'o')
6794 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6803 static xtensa_format
6804 xg_find_narrowest_format (vliw_insn
*vinsn
)
6806 /* Right now we assume that the ops within the vinsn are properly
6807 ordered for the slots that the programmer wanted them in. In
6808 other words, we don't rearrange the ops in hopes of finding a
6809 better format. The scheduler handles that. */
6811 xtensa_isa isa
= xtensa_default_isa
;
6812 xtensa_format format
;
6813 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6815 if (vinsn
->num_slots
== 1)
6816 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6818 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6821 xg_copy_vinsn (&v_copy
, vinsn
);
6822 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6826 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6828 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6830 v_copy
.slots
[slot
].opcode
=
6831 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6832 v_copy
.slots
[slot
].ntok
= 0;
6835 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6838 else if (v_copy
.num_slots
> 1)
6841 /* Try the widened version. */
6842 if (!v_copy
.slots
[slot
].keep_wide
6843 && !v_copy
.slots
[slot
].is_specific_opcode
6844 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6846 && opcode_fits_format_slot (widened
.opcode
,
6849 v_copy
.slots
[slot
] = widened
;
6854 if (fit
== v_copy
.num_slots
)
6856 xg_copy_vinsn (vinsn
, &v_copy
);
6857 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6858 vinsn
->format
= format
;
6864 if (format
== xtensa_isa_num_formats (isa
))
6865 return XTENSA_UNDEFINED
;
6871 /* Return the additional space needed in a frag
6872 for possible relaxations of any ops in a VLIW insn.
6873 Also fill out the relaxations that might be required of
6874 each tinsn in the vinsn. */
6877 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6879 bfd_boolean finish_frag
= FALSE
;
6880 int extra_space
= 0;
6883 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6885 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6886 if (!tinsn_has_symbolic_operands (tinsn
))
6888 /* A narrow instruction could be widened later to help
6889 alignment issues. */
6890 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6891 && !tinsn
->is_specific_opcode
6892 && vinsn
->num_slots
== 1)
6894 /* Difference in bytes between narrow and wide insns... */
6896 tinsn
->subtype
= RELAX_NARROW
;
6901 if (workaround_b_j_loop_end
6902 && tinsn
->opcode
== xtensa_jx_opcode
6903 && use_transform ())
6905 /* Add 2 of these. */
6906 extra_space
+= 3; /* for the nop size */
6907 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6910 /* Need to assemble it with space for the relocation. */
6911 if (xg_is_relaxable_insn (tinsn
, 0)
6912 && !tinsn
->is_specific_opcode
)
6914 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6915 int max_literal_size
=
6916 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6918 tinsn
->literal_space
= max_literal_size
;
6920 tinsn
->subtype
= RELAX_IMMED
;
6921 extra_space
+= max_size
;
6925 /* A fix record will be added for this instruction prior
6926 to relaxation, so make it end the frag. */
6931 *pfinish_frag
= finish_frag
;
6937 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6939 xtensa_isa isa
= xtensa_default_isa
;
6940 int slot
, chosen_slot
;
6942 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6943 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6944 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6946 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6947 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6949 if (slot
== chosen_slot
)
6950 vinsn
->slots
[slot
] = *tinsn
;
6953 vinsn
->slots
[slot
].opcode
=
6954 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6955 vinsn
->slots
[slot
].ntok
= 0;
6956 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6963 emit_single_op (TInsn
*orig_insn
)
6966 IStack istack
; /* put instructions into here */
6967 symbolS
*lit_sym
= NULL
;
6968 symbolS
*label_sym
= NULL
;
6970 istack_init (&istack
);
6972 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6973 Because the scheduling and bundling characteristics of movi and
6974 l32r or const16 are so different, we can do much better if we relax
6975 it prior to scheduling and bundling, rather than after. */
6976 if ((orig_insn
->opcode
== xtensa_movi_opcode
6977 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6978 && !cur_vinsn
.inside_bundle
6979 && (orig_insn
->tok
[1].X_op
== O_symbol
6980 || orig_insn
->tok
[1].X_op
== O_pltrel
6981 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6982 || orig_insn
->tok
[1].X_op
== O_tlsarg
6983 || orig_insn
->tok
[1].X_op
== O_tpoff
6984 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6985 && !orig_insn
->is_specific_opcode
&& use_transform ())
6986 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6988 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6991 for (i
= 0; i
< istack
.ninsn
; i
++)
6993 TInsn
*insn
= &istack
.insn
[i
];
6994 switch (insn
->insn_type
)
6997 gas_assert (lit_sym
== NULL
);
6998 lit_sym
= xg_assemble_literal (insn
);
7002 static int relaxed_sym_idx
= 0;
7003 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
7004 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
7006 gas_assert (label_sym
== NULL
);
7007 label_sym
= symbol_find_or_make (label
);
7008 gas_assert (label_sym
);
7016 xg_resolve_literals (insn
, lit_sym
);
7018 xg_resolve_labels (insn
, label_sym
);
7020 bundle_tinsn (insn
, &v
);
7035 total_frag_text_expansion (fragS
*fragP
)
7038 int total_expansion
= 0;
7040 for (slot
= 0; slot
< config_max_slots
; slot
++)
7041 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7043 return total_expansion
;
7047 /* Emit a vliw instruction to the current fragment. */
7050 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7052 bfd_boolean finish_frag
;
7053 bfd_boolean is_jump
= FALSE
;
7054 bfd_boolean is_branch
= FALSE
;
7055 xtensa_isa isa
= xtensa_default_isa
;
7060 struct dwarf2_line_info debug_line
;
7061 bfd_boolean loc_directive_seen
= FALSE
;
7064 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7066 if (generating_literals
)
7068 static int reported
= 0;
7070 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7071 _("cannot assemble into a literal fragment"));
7078 if (frag_now_fix () != 0
7079 && (! frag_now
->tc_frag_data
.is_insn
7080 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7081 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7082 || (directive_state
[directive_longcalls
]
7083 != frag_now
->tc_frag_data
.use_longcalls
)
7084 || (directive_state
[directive_absolute_literals
]
7085 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7087 frag_wane (frag_now
);
7089 xtensa_set_frag_assembly_state (frag_now
);
7092 if (workaround_a0_b_retw
7093 && vinsn
->num_slots
== 1
7094 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7095 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7096 && use_transform ())
7098 has_a0_b_retw
= TRUE
;
7100 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7101 After the first assembly pass we will check all of them and
7102 add a nop if needed. */
7103 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7104 frag_var (rs_machine_dependent
, 4, 4,
7105 RELAX_ADD_NOP_IF_A0_B_RETW
,
7106 frag_now
->fr_symbol
,
7107 frag_now
->fr_offset
,
7109 xtensa_set_frag_assembly_state (frag_now
);
7110 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7111 frag_var (rs_machine_dependent
, 4, 4,
7112 RELAX_ADD_NOP_IF_A0_B_RETW
,
7113 frag_now
->fr_symbol
,
7114 frag_now
->fr_offset
,
7116 xtensa_set_frag_assembly_state (frag_now
);
7119 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7121 tinsn
= &vinsn
->slots
[slot
];
7123 /* See if the instruction implies an aligned section. */
7124 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7125 record_alignment (now_seg
, 2);
7127 /* Determine the best line number for debug info. */
7128 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7129 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7130 || tinsn
->debug_line
.line
< debug_line
.line
7131 || tinsn
->debug_line
.column
< debug_line
.column
))
7132 debug_line
= tinsn
->debug_line
;
7133 if (tinsn
->loc_directive_seen
)
7134 loc_directive_seen
= TRUE
;
7137 /* Special cases for instructions that force an alignment... */
7138 /* None of these opcodes are bundle-able. */
7139 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7143 /* Remember the symbol that marks the end of the loop in the frag
7144 that marks the start of the loop. This way we can easily find
7145 the end of the loop at the beginning, without adding special code
7146 to mark the loop instructions themselves. */
7147 symbolS
*target_sym
= NULL
;
7148 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7149 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7151 xtensa_set_frag_assembly_state (frag_now
);
7152 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7154 max_fill
= get_text_align_max_fill_size
7155 (get_text_align_power (xtensa_fetch_width
),
7156 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7158 if (use_transform ())
7159 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7160 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7162 frag_var (rs_machine_dependent
, 0, 0,
7163 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7164 xtensa_set_frag_assembly_state (frag_now
);
7167 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7168 && !vinsn
->slots
[0].is_specific_opcode
)
7170 xtensa_mark_literal_pool_location ();
7171 xtensa_move_labels (frag_now
, 0);
7172 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7175 if (vinsn
->num_slots
== 1)
7177 if (workaround_a0_b_retw
&& use_transform ())
7178 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7179 is_register_writer (&vinsn
->slots
[0], "a", 0));
7181 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7182 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7185 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7187 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7189 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7191 /* vinsn_to_insnbuf will produce the error. */
7192 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7194 f
= frag_more (insn_size
+ extra_space
);
7195 xtensa_set_frag_assembly_state (frag_now
);
7196 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7199 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7200 if (vinsn
->format
== XTENSA_UNDEFINED
)
7203 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7205 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7206 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7209 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7211 tinsn
= &vinsn
->slots
[slot
];
7212 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7213 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7214 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7215 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7216 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7217 frag_now
->tc_frag_data
.literal_frags
[slot
]
7218 = symbol_get_frag (tinsn
->tok
[1].X_add_symbol
);
7219 if (tinsn
->literal_space
!= 0)
7220 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7221 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7223 if (tinsn
->subtype
== RELAX_NARROW
)
7224 gas_assert (vinsn
->num_slots
== 1);
7225 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7227 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7230 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7231 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7235 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7236 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7240 frag_variant (rs_machine_dependent
,
7241 extra_space
, extra_space
, RELAX_SLOTS
,
7242 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7243 xtensa_set_frag_assembly_state (frag_now
);
7246 /* Special cases for loops:
7247 close_loop_end should be inserted AFTER short_loop.
7248 Make sure that CLOSE loops are processed BEFORE short_loops
7249 when converting them. */
7251 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7252 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7253 && !vinsn
->slots
[0].is_specific_opcode
)
7255 if (workaround_short_loop
&& use_transform ())
7257 maybe_has_short_loop
= TRUE
;
7258 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7259 frag_var (rs_machine_dependent
, 4, 4,
7260 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7261 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7262 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7263 frag_var (rs_machine_dependent
, 4, 4,
7264 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7265 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7268 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7269 loop at least 12 bytes away from another loop's end. */
7270 if (workaround_close_loop_end
&& use_transform ())
7272 maybe_has_close_loop_end
= TRUE
;
7273 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7274 frag_var (rs_machine_dependent
, 12, 12,
7275 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7276 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7280 if (use_transform ())
7284 gas_assert (finish_frag
);
7285 frag_var (rs_machine_dependent
,
7286 xtensa_fetch_width
, xtensa_fetch_width
,
7288 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7289 xtensa_set_frag_assembly_state (frag_now
);
7290 xtensa_maybe_create_trampoline_frag ();
7291 /* Always create one here. */
7292 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7294 else if (is_branch
&& do_align_targets ())
7296 gas_assert (finish_frag
);
7297 frag_var (rs_machine_dependent
,
7298 xtensa_fetch_width
, xtensa_fetch_width
,
7299 RELAX_MAYBE_UNREACHABLE
,
7300 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7301 xtensa_set_frag_assembly_state (frag_now
);
7302 frag_var (rs_machine_dependent
,
7304 RELAX_MAYBE_DESIRE_ALIGN
,
7305 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7306 xtensa_set_frag_assembly_state (frag_now
);
7310 /* Now, if the original opcode was a call... */
7311 if (do_align_targets ()
7312 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7314 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7315 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7316 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7317 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7318 xtensa_set_frag_assembly_state (frag_now
);
7321 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7323 frag_wane (frag_now
);
7325 xtensa_set_frag_assembly_state (frag_now
);
7330 /* xtensa_end and helper functions. */
7332 static void xtensa_cleanup_align_frags (void);
7333 static void xtensa_fix_target_frags (void);
7334 static void xtensa_mark_narrow_branches (void);
7335 static void xtensa_mark_zcl_first_insns (void);
7336 static void xtensa_mark_difference_of_two_symbols (void);
7337 static void xtensa_fix_a0_b_retw_frags (void);
7338 static void xtensa_fix_b_j_loop_end_frags (void);
7339 static void xtensa_fix_close_loop_end_frags (void);
7340 static void xtensa_fix_short_loop_frags (void);
7341 static void xtensa_sanity_check (void);
7342 static void xtensa_add_config_info (void);
7347 directive_balance ();
7348 xtensa_flush_pending_output ();
7350 past_xtensa_end
= TRUE
;
7352 xtensa_move_literals ();
7354 xtensa_reorder_segments ();
7355 xtensa_cleanup_align_frags ();
7356 xtensa_fix_target_frags ();
7357 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7358 xtensa_fix_a0_b_retw_frags ();
7359 if (workaround_b_j_loop_end
)
7360 xtensa_fix_b_j_loop_end_frags ();
7362 /* "close_loop_end" should be processed BEFORE "short_loop". */
7363 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7364 xtensa_fix_close_loop_end_frags ();
7366 if (workaround_short_loop
&& maybe_has_short_loop
)
7367 xtensa_fix_short_loop_frags ();
7369 xtensa_mark_narrow_branches ();
7370 xtensa_mark_zcl_first_insns ();
7372 xtensa_sanity_check ();
7374 xtensa_add_config_info ();
7376 xtensa_check_frag_count ();
7379 struct trampoline_chain_entry
7385 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7386 of locations of trampoline jumps leading there. Jumps are represented
7387 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7389 struct trampoline_chain
7391 struct trampoline_chain_entry target
;
7392 struct trampoline_chain_entry
*entry
;
7395 bfd_boolean needs_sorting
;
7398 struct trampoline_chain_index
7400 struct trampoline_chain
*entry
;
7403 bfd_boolean needs_sorting
;
7406 struct trampoline_index
7413 struct trampoline_seg
7415 struct trampoline_seg
*next
;
7417 /* Trampolines ordered by their frag fr_address */
7418 struct trampoline_index index
;
7419 /* Known trampoline chains ordered by (sym, offset) pair */
7420 struct trampoline_chain_index chain_index
;
7423 static struct trampoline_seg trampoline_seg_list
;
7424 #define J_RANGE (128 * 1024)
7425 #define J_MARGIN 4096
7427 static int unreachable_count
= 0;
7431 xtensa_maybe_create_trampoline_frag (void)
7433 if (!use_trampolines
)
7436 /* We create an area for possible trampolines every 10 unreachable frags.
7437 These are preferred over the ones not preceded by an unreachable frag,
7438 because we don't have to jump around them. This function is called after
7439 each RELAX_UNREACHABLE frag is created. */
7441 if (++unreachable_count
> 10)
7443 xtensa_create_trampoline_frag (FALSE
);
7444 clear_frag_count ();
7445 unreachable_count
= 0;
7450 xtensa_check_frag_count (void)
7452 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7455 /* We create an area for possible trampolines every 8000 frags or so. This
7456 is an estimate based on the max range of a "j" insn (+/-128K) divided
7457 by a typical frag byte count (16), minus a few for safety. This function
7458 is called after each source line is processed. */
7460 if (get_frag_count () > 8000)
7462 xtensa_create_trampoline_frag (TRUE
);
7463 clear_frag_count ();
7464 unreachable_count
= 0;
7467 /* We create an area for a possible literal pool every N (default 5000)
7469 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7472 static xtensa_insnbuf trampoline_buf
= NULL
;
7473 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7475 static xtensa_insnbuf litpool_buf
= NULL
;
7476 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7478 #define TRAMPOLINE_FRAG_SIZE 3000
7480 static struct trampoline_seg
*
7481 find_trampoline_seg (asection
*seg
)
7483 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7484 static struct trampoline_seg
*mr
;
7486 if (mr
&& mr
->seg
== seg
)
7489 for ( ; ts
; ts
= ts
->next
)
7501 static size_t xg_find_trampoline (const struct trampoline_index
*idx
,
7505 size_t b
= idx
->n_entries
;
7509 size_t c
= (a
+ b
) / 2;
7511 if (idx
->entry
[c
]->fr_address
<= addr
)
7519 static void xg_add_trampoline_to_index (struct trampoline_index
*idx
,
7522 if (idx
->n_entries
== idx
->n_max
)
7524 idx
->n_max
= (idx
->n_entries
+ 1) * 2;
7525 idx
->entry
= xrealloc (idx
->entry
,
7526 sizeof (*idx
->entry
) * idx
->n_max
);
7528 idx
->entry
[idx
->n_entries
] = fragP
;
7532 static void xg_remove_trampoline_from_index (struct trampoline_index
*idx
,
7535 gas_assert (i
< idx
->n_entries
);
7536 memmove (idx
->entry
+ i
, idx
->entry
+ i
+ 1,
7537 (idx
->n_entries
- i
- 1) * sizeof (*idx
->entry
));
7541 static void xg_add_trampoline_to_seg (struct trampoline_seg
*ts
,
7544 xg_add_trampoline_to_index (&ts
->index
, fragP
);
7548 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7550 /* Emit a frag where we can place intermediate jump instructions,
7551 in case we need to jump farther than 128K bytes.
7552 Each jump instruction takes three bytes.
7553 We allocate enough for 1000 trampolines in each frag.
7554 If that's not enough, oh well. */
7556 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
7559 int size
= TRAMPOLINE_FRAG_SIZE
;
7563 ts
= XCNEW(struct trampoline_seg
);
7564 ts
->next
= trampoline_seg_list
.next
;
7565 trampoline_seg_list
.next
= ts
;
7569 frag_wane (frag_now
);
7571 xtensa_set_frag_assembly_state (frag_now
);
7572 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7573 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7574 if (trampoline_buf
== NULL
)
7576 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7577 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7579 fragP
->tc_frag_data
.needs_jump_around
= needs_jump_around
;
7580 xg_add_trampoline_to_seg (ts
, fragP
);
7583 static bfd_boolean
xg_is_trampoline_frag_full (const fragS
*fragP
)
7585 return fragP
->fr_var
< 3;
7588 static int xg_order_trampoline_chain_entry (const void *a
, const void *b
)
7590 const struct trampoline_chain_entry
*pa
= a
;
7591 const struct trampoline_chain_entry
*pb
= b
;
7593 if (pa
->sym
== pb
->sym
||
7594 S_GET_VALUE (pa
->sym
) == S_GET_VALUE (pb
->sym
))
7595 if (pa
->offset
== pb
->offset
)
7598 return pa
->offset
< pb
->offset
? -1 : 1;
7600 return S_GET_VALUE (pa
->sym
) < S_GET_VALUE (pb
->sym
) ? -1 : 1;
7603 static void xg_sort_trampoline_chain (struct trampoline_chain
*tc
)
7605 qsort (tc
->entry
, tc
->n_entries
, sizeof (*tc
->entry
),
7606 xg_order_trampoline_chain_entry
);
7607 tc
->needs_sorting
= FALSE
;
7610 /* Find entry index in the given chain with maximal address <= source. */
7611 static size_t xg_find_chain_entry (struct trampoline_chain
*tc
,
7615 size_t b
= tc
->n_entries
;
7617 if (tc
->needs_sorting
)
7618 xg_sort_trampoline_chain (tc
);
7622 size_t c
= (a
+ b
) / 2;
7623 struct trampoline_chain_entry
*e
= tc
->entry
+ c
;
7625 if (S_GET_VALUE(e
->sym
) + e
->offset
<= source
)
7633 /* Find the best jump target for the source in the given trampoline chain.
7634 The best jump target is the one that results in the shortest path to the
7635 final target, it's the location of the jump closest to the final target,
7636 but within the J_RANGE - J_MARGIN from the source. */
7637 static struct trampoline_chain_entry
*
7638 xg_get_best_chain_entry (struct trampoline_chain
*tc
, addressT source
)
7640 addressT target
= S_GET_VALUE(tc
->target
.sym
) + tc
->target
.offset
;
7641 size_t i
= xg_find_chain_entry (tc
, source
);
7642 struct trampoline_chain_entry
*e
= tc
->entry
+ i
;
7643 int step
= target
< source
? -1 : 1;
7644 addressT chained_target
;
7647 if (target
> source
&&
7648 S_GET_VALUE(e
->sym
) + e
->offset
<= source
&&
7649 i
+ 1 < tc
->n_entries
)
7652 while (i
+ step
< tc
->n_entries
)
7654 struct trampoline_chain_entry
*next
= tc
->entry
+ i
+ step
;
7656 chained_target
= S_GET_VALUE(next
->sym
) + next
->offset
;
7657 off
= source
- chained_target
;
7659 if (labs (off
) >= J_RANGE
- J_MARGIN
)
7666 chained_target
= S_GET_VALUE(e
->sym
) + e
->offset
;
7667 off
= source
- chained_target
;
7669 if (labs (off
) < J_MARGIN
||
7670 labs (off
) >= J_RANGE
- J_MARGIN
)
7672 return tc
->entry
+ i
;
7675 static int xg_order_trampoline_chain (const void *a
, const void *b
)
7677 const struct trampoline_chain
*_pa
= a
;
7678 const struct trampoline_chain
*_pb
= b
;
7679 const struct trampoline_chain_entry
*pa
= &_pa
->target
;
7680 const struct trampoline_chain_entry
*pb
= &_pb
->target
;
7681 symbolS
*s1
= pa
->sym
;
7682 symbolS
*s2
= pb
->sym
;
7685 tmp
= symbol_symbolS (s1
);
7689 tmp
= symbol_symbolS (s2
);
7694 if (pa
->offset
== pb
->offset
)
7697 return pa
->offset
< pb
->offset
? -1 : 1;
7699 return s1
< s2
? -1 : 1;
7702 static struct trampoline_chain
*
7703 xg_get_trampoline_chain (struct trampoline_seg
*ts
,
7707 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7708 struct trampoline_chain c
;
7710 if (idx
->needs_sorting
)
7712 qsort (idx
->entry
, idx
->n_entries
, sizeof (*idx
->entry
),
7713 xg_order_trampoline_chain
);
7714 idx
->needs_sorting
= FALSE
;
7717 c
.target
.offset
= offset
;
7718 return bsearch (&c
, idx
->entry
, idx
->n_entries
,
7719 sizeof (struct trampoline_chain
),
7720 xg_order_trampoline_chain
);
7723 /* Find trampoline chain in the given trampoline segment that is going
7724 to the *sym + *offset. If found, replace *sym and *offset with the
7725 best jump target in that chain. */
7726 static struct trampoline_chain
*
7727 xg_find_best_eq_target (struct trampoline_seg
*ts
,
7728 addressT source
, symbolS
**sym
,
7731 struct trampoline_chain
*tc
= xg_get_trampoline_chain (ts
, *sym
, *offset
);
7735 struct trampoline_chain_entry
*e
= xg_get_best_chain_entry (tc
, source
);
7738 *offset
= e
->offset
;
7743 static void xg_add_location_to_chain (struct trampoline_chain
*tc
,
7744 symbolS
*sym
, addressT offset
)
7746 struct trampoline_chain_entry
*e
;
7748 if (tc
->n_entries
== tc
->n_max
)
7750 tc
->n_max
= (tc
->n_max
+ 1) * 2;
7751 tc
->entry
= xrealloc (tc
->entry
, sizeof (*tc
->entry
) * tc
->n_max
);
7753 e
= tc
->entry
+ tc
->n_entries
;
7757 tc
->needs_sorting
= TRUE
;
7760 static struct trampoline_chain
*
7761 xg_create_trampoline_chain (struct trampoline_seg
*ts
,
7762 symbolS
*sym
, addressT offset
)
7764 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7765 struct trampoline_chain
*tc
;
7767 if (idx
->n_entries
== idx
->n_max
)
7769 idx
->n_max
= (idx
->n_max
+ 1) * 2;
7770 idx
->entry
= xrealloc (idx
->entry
,
7771 sizeof (*idx
->entry
) * idx
->n_max
);
7774 tc
= idx
->entry
+ idx
->n_entries
;
7775 tc
->target
.sym
= sym
;
7776 tc
->target
.offset
= offset
;
7780 xg_add_location_to_chain (tc
, sym
, offset
);
7783 idx
->needs_sorting
= TRUE
;
7788 void dump_trampolines (void);
7791 dump_trampolines (void)
7793 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7795 for ( ; ts
; ts
= ts
->next
)
7798 asection
*seg
= ts
->seg
;
7802 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7804 for (i
= 0; i
< ts
->index
.n_entries
; ++i
)
7806 fragS
*tf
= ts
->index
.entry
[i
];
7808 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7809 (int)tf
->fr_address
, (int)tf
->fr_fix
,
7810 tf
->tc_frag_data
.needs_jump_around
? "T" : "F");
7815 static void dump_litpools (void) __attribute__ ((unused
));
7818 dump_litpools (void)
7820 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7821 struct litpool_frag
*lpf
;
7823 for ( ; lps
; lps
= lps
->next
)
7825 printf("litpool seg %s\n", lps
->seg
->name
);
7826 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7828 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7830 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7832 if (litfrag
->fr_fix
== 4)
7834 litfrag
= litfrag
->fr_next
;
7836 printf(" %ld <%d:%d> (%d) [%d]: ",
7837 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7838 lpf
->fragP
->fr_line
, count
);
7839 //dump_frag(lpf->fragP);
7845 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7846 bfd_boolean only_if_needed
)
7848 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7850 struct litpool_frag
*lpf
;
7851 bfd_boolean needed
= FALSE
;
7853 if (use_literal_section
|| !auto_litpools
)
7856 for ( ; lps
; lps
= lps
->next
)
7858 if (lps
->seg
== now_seg
)
7864 lps
= XCNEW (struct litpool_seg
);
7865 lps
->next
= litpool_seg_list
.next
;
7866 litpool_seg_list
.next
= lps
;
7868 lps
->frag_list
.next
= &lps
->frag_list
;
7869 lps
->frag_list
.prev
= &lps
->frag_list
;
7870 /* Put candidate literal pool at the beginning of every section,
7871 so that even when section starts with literal load there's a
7872 literal pool available. */
7873 lps
->frag_count
= auto_litpool_limit
;
7882 if (past_xtensa_end
|| !use_transform() ||
7883 frag_now
->tc_frag_data
.is_no_transform
)
7887 if (auto_litpool_limit
<= 0)
7889 /* Don't create a litpool based only on frag count. */
7892 else if (lps
->frag_count
> auto_litpool_limit
)
7909 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7910 /* Create a potential site for a literal pool. */
7911 frag_wane (frag_now
);
7913 xtensa_set_frag_assembly_state (frag_now
);
7915 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7916 fragP
->tc_frag_data
.literal_frag
= fragP
;
7917 frag_var (rs_machine_dependent
, size
, size
,
7919 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7920 RELAX_LITERAL_POOL_BEGIN
,
7922 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7923 frag_variant (rs_machine_dependent
, 0, 0,
7924 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7925 xtensa_set_frag_assembly_state (frag_now
);
7929 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7930 just record it here. */
7934 lpf
= XNEW (struct litpool_frag
);
7935 /* Insert at tail of circular list. */
7937 lps
->frag_list
.prev
->next
= lpf
;
7938 lpf
->next
= &lps
->frag_list
;
7939 lpf
->prev
= lps
->frag_list
.prev
;
7940 lps
->frag_list
.prev
= lpf
;
7942 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7943 lpf
->original_priority
= lpf
->priority
;
7944 lpf
->literal_count
= 0;
7946 lps
->frag_count
= 0;
7950 xtensa_cleanup_align_frags (void)
7955 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7956 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7959 /* Walk over all of the fragments in a subsection. */
7960 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7962 if ((fragP
->fr_type
== rs_align
7963 || fragP
->fr_type
== rs_align_code
7964 || (fragP
->fr_type
== rs_machine_dependent
7965 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7966 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7967 && fragP
->fr_fix
== 0)
7969 fragS
*next
= fragP
->fr_next
;
7972 && next
->fr_fix
== 0
7973 && next
->fr_type
== rs_machine_dependent
7974 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7977 next
= next
->fr_next
;
7980 /* If we don't widen branch targets, then they
7981 will be easier to align. */
7982 if (fragP
->tc_frag_data
.is_branch_target
7983 && fragP
->fr_opcode
== fragP
->fr_literal
7984 && fragP
->fr_type
== rs_machine_dependent
7985 && fragP
->fr_subtype
== RELAX_SLOTS
7986 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7988 if (fragP
->fr_type
== rs_machine_dependent
7989 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7990 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7996 /* Re-process all of the fragments looking to convert all of the
7997 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7998 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7999 Otherwise, convert to a .fill 0. */
8002 xtensa_fix_target_frags (void)
8007 /* When this routine is called, all of the subsections are still intact
8008 so we walk over subsections instead of sections. */
8009 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8010 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8014 /* Walk over all of the fragments in a subsection. */
8015 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8017 if (fragP
->fr_type
== rs_machine_dependent
8018 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8020 if (next_frag_is_branch_target (fragP
))
8021 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
8030 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
8033 xtensa_mark_narrow_branches (void)
8038 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8039 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8042 /* Walk over all of the fragments in a subsection. */
8043 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8045 if (fragP
->fr_type
== rs_machine_dependent
8046 && fragP
->fr_subtype
== RELAX_SLOTS
8047 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8051 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
8052 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
8054 if (vinsn
.num_slots
== 1
8055 && xtensa_opcode_is_branch (xtensa_default_isa
,
8056 vinsn
.slots
[0].opcode
) == 1
8057 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
8058 && is_narrow_branch_guaranteed_in_range (fragP
,
8061 fragP
->fr_subtype
= RELAX_SLOTS
;
8062 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
8063 fragP
->tc_frag_data
.is_aligning_branch
= 1;
8071 /* A branch is typically widened only when its target is out of
8072 range. However, we would like to widen them to align a subsequent
8073 branch target when possible.
8075 Because the branch relaxation code is so convoluted, the optimal solution
8076 (combining the two cases) is difficult to get right in all circumstances.
8077 We therefore go with an "almost as good" solution, where we only
8078 use for alignment narrow branches that definitely will not expand to a
8079 jump and a branch. These functions find and mark these cases. */
8081 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8082 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8083 We start counting beginning with the frag after the 2-byte branch, so the
8084 maximum offset is (4 - 2) + 63 = 65. */
8085 #define MAX_IMMED6 65
8087 static offsetT
unrelaxed_frag_max_size (fragS
*);
8090 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
8092 const expressionS
*exp
= &tinsn
->tok
[1];
8093 symbolS
*symbolP
= exp
->X_add_symbol
;
8094 offsetT max_distance
= exp
->X_add_number
;
8097 if (exp
->X_op
!= O_symbol
)
8100 target_frag
= symbol_get_frag (symbolP
);
8102 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
8103 if (is_branch_jmp_to_next (tinsn
, fragP
))
8106 /* The branch doesn't branch over it's own frag,
8107 but over the subsequent ones. */
8108 fragP
= fragP
->fr_next
;
8109 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
8111 max_distance
+= unrelaxed_frag_max_size (fragP
);
8112 fragP
= fragP
->fr_next
;
8114 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
8121 xtensa_mark_zcl_first_insns (void)
8126 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8127 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8130 /* Walk over all of the fragments in a subsection. */
8131 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8133 if (fragP
->fr_type
== rs_machine_dependent
8134 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8135 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8137 /* Find the loop frag. */
8138 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8139 /* Find the first insn frag. */
8140 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
8142 /* Handle a corner case that comes up in hardware
8143 diagnostics. The original assembly looks like this:
8146 <empty_frag>--not found by next_non_empty_frag
8149 Depending on the start address, the assembler may or
8150 may not change it to look something like this:
8153 nop--frag isn't empty anymore
8156 So set up to check the alignment of the nop if it
8158 while (loop_frag
!= targ_frag
)
8160 if (loop_frag
->fr_type
== rs_machine_dependent
8161 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8162 || loop_frag
->fr_subtype
8163 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8164 targ_frag
= loop_frag
;
8166 loop_frag
= loop_frag
->fr_next
;
8169 /* Of course, sometimes (mostly for toy test cases) a
8170 zero-cost loop instruction is the last in a section. */
8173 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
8174 /* Do not widen a frag that is the first instruction of a
8175 zero-cost loop. It makes that loop harder to align. */
8176 if (targ_frag
->fr_type
== rs_machine_dependent
8177 && targ_frag
->fr_subtype
== RELAX_SLOTS
8178 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
8181 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
8182 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8185 frag_wane (targ_frag
);
8186 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
8190 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
8198 /* When a difference-of-symbols expression is encoded as a uleb128 or
8199 sleb128 value, the linker is unable to adjust that value to account for
8200 link-time relaxation. Mark all the code between such symbols so that
8201 its size cannot be changed by linker relaxation. */
8204 xtensa_mark_difference_of_two_symbols (void)
8208 for (expr_sym
= expr_symbols
; expr_sym
;
8209 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
8211 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
8213 if (exp
->X_op
== O_subtract
)
8215 symbolS
*left
= exp
->X_add_symbol
;
8216 symbolS
*right
= exp
->X_op_symbol
;
8218 /* Difference of two symbols not in the same section
8219 are handled with relocations in the linker. */
8220 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
8226 if (symbol_get_frag (left
)->fr_address
8227 <= symbol_get_frag (right
)->fr_address
)
8229 start
= symbol_get_frag (left
);
8230 end
= symbol_get_frag (right
);
8234 start
= symbol_get_frag (right
);
8235 end
= symbol_get_frag (left
);
8238 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
8239 walk
= start
->tc_frag_data
.no_transform_end
;
8244 walk
->tc_frag_data
.is_no_transform
= 1;
8245 walk
= walk
->fr_next
;
8247 while (walk
&& walk
->fr_address
< end
->fr_address
);
8249 start
->tc_frag_data
.no_transform_end
= walk
;
8256 /* Re-process all of the fragments looking to convert all of the
8257 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8258 conditional branch or a retw/retw.n, convert this frag to one that
8259 will generate a NOP. In any case close it off with a .fill 0. */
8261 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
8264 xtensa_fix_a0_b_retw_frags (void)
8269 /* When this routine is called, all of the subsections are still intact
8270 so we walk over subsections instead of sections. */
8271 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8272 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8276 /* Walk over all of the fragments in a subsection. */
8277 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8279 if (fragP
->fr_type
== rs_machine_dependent
8280 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
8282 if (next_instrs_are_b_retw (fragP
))
8284 if (fragP
->tc_frag_data
.is_no_transform
)
8285 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8287 relax_frag_add_nop (fragP
);
8297 next_instrs_are_b_retw (fragS
*fragP
)
8299 xtensa_opcode opcode
;
8301 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8302 static xtensa_insnbuf insnbuf
= NULL
;
8303 static xtensa_insnbuf slotbuf
= NULL
;
8304 xtensa_isa isa
= xtensa_default_isa
;
8307 bfd_boolean branch_seen
= FALSE
;
8311 insnbuf
= xtensa_insnbuf_alloc (isa
);
8312 slotbuf
= xtensa_insnbuf_alloc (isa
);
8315 if (next_fragP
== NULL
)
8318 /* Check for the conditional branch. */
8319 xtensa_insnbuf_from_chars
8320 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8321 fmt
= xtensa_format_decode (isa
, insnbuf
);
8322 if (fmt
== XTENSA_UNDEFINED
)
8325 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8327 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8328 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8330 branch_seen
= (branch_seen
8331 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8337 offset
+= xtensa_format_length (isa
, fmt
);
8338 if (offset
== next_fragP
->fr_fix
)
8340 next_fragP
= next_non_empty_frag (next_fragP
);
8344 if (next_fragP
== NULL
)
8347 /* Check for the retw/retw.n. */
8348 xtensa_insnbuf_from_chars
8349 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8350 fmt
= xtensa_format_decode (isa
, insnbuf
);
8352 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8353 have no problems. */
8354 if (fmt
== XTENSA_UNDEFINED
8355 || xtensa_format_num_slots (isa
, fmt
) != 1)
8358 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8359 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8361 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8368 /* Re-process all of the fragments looking to convert all of the
8369 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8370 loop end label, convert this frag to one that will generate a NOP.
8371 In any case close it off with a .fill 0. */
8373 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8376 xtensa_fix_b_j_loop_end_frags (void)
8381 /* When this routine is called, all of the subsections are still intact
8382 so we walk over subsections instead of sections. */
8383 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8384 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8388 /* Walk over all of the fragments in a subsection. */
8389 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8391 if (fragP
->fr_type
== rs_machine_dependent
8392 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8394 if (next_instr_is_loop_end (fragP
))
8396 if (fragP
->tc_frag_data
.is_no_transform
)
8397 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8399 relax_frag_add_nop (fragP
);
8409 next_instr_is_loop_end (fragS
*fragP
)
8411 const fragS
*next_fragP
;
8413 if (next_frag_is_loop_target (fragP
))
8416 next_fragP
= next_non_empty_frag (fragP
);
8417 if (next_fragP
== NULL
)
8420 if (!next_frag_is_loop_target (next_fragP
))
8423 /* If the size is >= 3 then there is more than one instruction here.
8424 The hardware bug will not fire. */
8425 if (next_fragP
->fr_fix
> 3)
8432 /* Re-process all of the fragments looking to convert all of the
8433 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8434 not MY loop's loop end within 12 bytes, add enough nops here to
8435 make it at least 12 bytes away. In any case close it off with a
8438 static offsetT min_bytes_to_other_loop_end
8439 (fragS
*, fragS
*, offsetT
);
8442 xtensa_fix_close_loop_end_frags (void)
8447 /* When this routine is called, all of the subsections are still intact
8448 so we walk over subsections instead of sections. */
8449 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8450 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8454 fragS
*current_target
= NULL
;
8456 /* Walk over all of the fragments in a subsection. */
8457 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8459 if (fragP
->fr_type
== rs_machine_dependent
8460 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8461 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8462 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8465 && fragP
->fr_type
== rs_machine_dependent
8466 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8469 int bytes_added
= 0;
8471 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8472 /* Max out at 12. */
8473 min_bytes
= min_bytes_to_other_loop_end
8474 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8476 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8478 if (fragP
->tc_frag_data
.is_no_transform
)
8479 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8482 while (min_bytes
+ bytes_added
8483 < REQUIRED_LOOP_DIVIDING_BYTES
)
8487 if (fragP
->fr_var
< length
)
8488 as_fatal (_("fr_var %lu < length %d"),
8489 (long) fragP
->fr_var
, length
);
8492 assemble_nop (length
,
8493 fragP
->fr_literal
+ fragP
->fr_fix
);
8494 fragP
->fr_fix
+= length
;
8495 fragP
->fr_var
-= length
;
8497 bytes_added
+= length
;
8503 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8504 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8510 static offsetT
unrelaxed_frag_min_size (fragS
*);
8513 min_bytes_to_other_loop_end (fragS
*fragP
,
8514 fragS
*current_target
,
8518 fragS
*current_fragP
;
8520 for (current_fragP
= fragP
;
8522 current_fragP
= current_fragP
->fr_next
)
8524 if (current_fragP
->tc_frag_data
.is_loop_target
8525 && current_fragP
!= current_target
)
8528 offset
+= unrelaxed_frag_min_size (current_fragP
);
8530 if (offset
>= max_size
)
8538 unrelaxed_frag_min_size (fragS
*fragP
)
8540 offsetT size
= fragP
->fr_fix
;
8542 /* Add fill size. */
8543 if (fragP
->fr_type
== rs_fill
)
8544 size
+= fragP
->fr_offset
;
8551 unrelaxed_frag_max_size (fragS
*fragP
)
8553 offsetT size
= fragP
->fr_fix
;
8554 switch (fragP
->fr_type
)
8557 /* Empty frags created by the obstack allocation scheme
8558 end up with type 0. */
8563 size
+= fragP
->fr_offset
;
8571 /* No further adjustments needed. */
8573 case rs_machine_dependent
:
8574 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8575 size
+= fragP
->fr_var
;
8578 /* We had darn well better know how big it is. */
8587 /* Re-process all of the fragments looking to convert all
8588 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8591 1) the instruction size count to the loop end label
8592 is too short (<= 2 instructions),
8593 2) loop has a jump or branch in it
8596 1) workaround_all_short_loops is TRUE
8597 2) The generating loop was a 'loopgtz' or 'loopnez'
8598 3) the instruction size count to the loop end label is too short
8600 then convert this frag (and maybe the next one) to generate a NOP.
8601 In any case close it off with a .fill 0. */
8603 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8604 static bfd_boolean
branch_before_loop_end (fragS
*);
8607 xtensa_fix_short_loop_frags (void)
8612 /* When this routine is called, all of the subsections are still intact
8613 so we walk over subsections instead of sections. */
8614 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8615 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8618 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8620 /* Walk over all of the fragments in a subsection. */
8621 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8623 if (fragP
->fr_type
== rs_machine_dependent
8624 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8625 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8628 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8629 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8630 current_opcode
= t_insn
.opcode
;
8631 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8632 current_opcode
) == 1);
8635 if (fragP
->fr_type
== rs_machine_dependent
8636 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8638 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8639 && (branch_before_loop_end (fragP
->fr_next
)
8640 || (workaround_all_short_loops
8641 && current_opcode
!= XTENSA_UNDEFINED
8642 && current_opcode
!= xtensa_loop_opcode
)))
8644 if (fragP
->tc_frag_data
.is_no_transform
)
8645 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8647 relax_frag_add_nop (fragP
);
8656 static int unrelaxed_frag_min_insn_count (fragS
*);
8659 count_insns_to_loop_end (fragS
*base_fragP
,
8660 bfd_boolean count_relax_add
,
8663 fragS
*fragP
= NULL
;
8668 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8670 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8671 if (insn_count
>= max_count
)
8674 if (count_relax_add
)
8676 if (fragP
->fr_type
== rs_machine_dependent
8677 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8679 /* In order to add the appropriate number of
8680 NOPs, we count an instruction for downstream
8683 if (insn_count
>= max_count
)
8693 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8695 xtensa_isa isa
= xtensa_default_isa
;
8696 static xtensa_insnbuf insnbuf
= NULL
;
8700 if (!fragP
->tc_frag_data
.is_insn
)
8704 insnbuf
= xtensa_insnbuf_alloc (isa
);
8706 /* Decode the fixed instructions. */
8707 while (offset
< fragP
->fr_fix
)
8711 xtensa_insnbuf_from_chars
8712 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8713 fmt
= xtensa_format_decode (isa
, insnbuf
);
8715 if (fmt
== XTENSA_UNDEFINED
)
8717 as_fatal (_("undecodable instruction in instruction frag"));
8720 offset
+= xtensa_format_length (isa
, fmt
);
8728 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8731 branch_before_loop_end (fragS
*base_fragP
)
8735 for (fragP
= base_fragP
;
8736 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8737 fragP
= fragP
->fr_next
)
8739 if (unrelaxed_frag_has_b_j (fragP
))
8747 unrelaxed_frag_has_b_j (fragS
*fragP
)
8749 static xtensa_insnbuf insnbuf
= NULL
;
8750 xtensa_isa isa
= xtensa_default_isa
;
8753 if (!fragP
->tc_frag_data
.is_insn
)
8757 insnbuf
= xtensa_insnbuf_alloc (isa
);
8759 /* Decode the fixed instructions. */
8760 while (offset
< fragP
->fr_fix
)
8765 xtensa_insnbuf_from_chars
8766 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8767 fmt
= xtensa_format_decode (isa
, insnbuf
);
8768 if (fmt
== XTENSA_UNDEFINED
)
8771 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8773 xtensa_opcode opcode
=
8774 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8775 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8776 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8779 offset
+= xtensa_format_length (isa
, fmt
);
8785 /* Checks to be made after initial assembly but before relaxation. */
8787 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8788 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8791 xtensa_sanity_check (void)
8793 const char *file_name
;
8798 file_name
= as_where (&line
);
8799 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8800 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8804 /* Walk over all of the fragments in a subsection. */
8805 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8807 if (fragP
->fr_type
== rs_machine_dependent
8808 && fragP
->fr_subtype
== RELAX_SLOTS
8809 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8811 static xtensa_insnbuf insnbuf
= NULL
;
8814 if (fragP
->fr_opcode
!= NULL
)
8817 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8818 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8819 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8821 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8822 t_insn
.opcode
) == 1)
8824 if (is_empty_loop (&t_insn
, fragP
))
8826 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8827 as_bad (_("invalid empty loop"));
8829 if (!is_local_forward_loop (&t_insn
, fragP
))
8831 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8832 as_bad (_("loop target does not follow "
8833 "loop instruction in section"));
8840 new_logical_line (file_name
, line
);
8844 #define LOOP_IMMED_OPN 1
8846 /* Return TRUE if the loop target is the next non-zero fragment. */
8849 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8851 const expressionS
*exp
;
8855 if (insn
->insn_type
!= ITYPE_INSN
)
8858 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8861 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8864 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8866 if (exp
->X_op
!= O_symbol
)
8869 symbolP
= exp
->X_add_symbol
;
8873 if (symbol_get_frag (symbolP
) == NULL
)
8876 if (S_GET_VALUE (symbolP
) != 0)
8879 /* Walk through the zero-size fragments from this one. If we find
8880 the target fragment, then this is a zero-size loop. */
8882 for (next_fragP
= fragP
->fr_next
;
8884 next_fragP
= next_fragP
->fr_next
)
8886 if (next_fragP
== symbol_get_frag (symbolP
))
8888 if (next_fragP
->fr_fix
!= 0)
8896 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8898 const expressionS
*exp
;
8902 if (insn
->insn_type
!= ITYPE_INSN
)
8905 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8908 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8911 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8913 if (exp
->X_op
!= O_symbol
)
8916 symbolP
= exp
->X_add_symbol
;
8920 if (symbol_get_frag (symbolP
) == NULL
)
8923 /* Walk through fragments until we find the target.
8924 If we do not find the target, then this is an invalid loop. */
8926 for (next_fragP
= fragP
->fr_next
;
8928 next_fragP
= next_fragP
->fr_next
)
8930 if (next_fragP
== symbol_get_frag (symbolP
))
8938 #define XTINFO_NAME "Xtensa_Info"
8939 #define XTINFO_NAMESZ 12
8940 #define XTINFO_TYPE 1
8943 xtensa_add_config_info (void)
8949 info_sec
= subseg_new (".xtensa.info", 0);
8950 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8952 data
= XNEWVEC (char, 100);
8953 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8954 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8955 sz
= strlen (data
) + 1;
8957 /* Add enough null terminators to pad to a word boundary. */
8960 while ((sz
& 3) != 0);
8962 /* Follow the standard note section layout:
8963 First write the length of the name string. */
8965 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8967 /* Next comes the length of the "descriptor", i.e., the actual data. */
8969 md_number_to_chars (p
, (valueT
) sz
, 4);
8971 /* Write the note type. */
8973 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8975 /* Write the name field. */
8976 p
= frag_more (XTINFO_NAMESZ
);
8977 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8979 /* Finally, write the descriptor. */
8981 memcpy (p
, data
, sz
);
8987 /* Alignment Functions. */
8990 get_text_align_power (unsigned target_size
)
8992 if (target_size
<= 4)
8995 if (target_size
<= 8)
8998 if (target_size
<= 16)
9001 if (target_size
<= 32)
9004 if (target_size
<= 64)
9007 if (target_size
<= 128)
9010 if (target_size
<= 256)
9013 if (target_size
<= 512)
9016 if (target_size
<= 1024)
9025 get_text_align_max_fill_size (int align_pow
,
9026 bfd_boolean use_nops
,
9027 bfd_boolean use_no_density
)
9030 return (1 << align_pow
);
9032 return 3 * (1 << align_pow
);
9034 return 1 + (1 << align_pow
);
9038 /* Calculate the minimum bytes of fill needed at "address" to align a
9039 target instruction of size "target_size" so that it does not cross a
9040 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9041 the fill can be an arbitrary number of bytes. Otherwise, the space must
9042 be filled by NOP instructions. */
9045 get_text_align_fill_size (addressT address
,
9048 bfd_boolean use_nops
,
9049 bfd_boolean use_no_density
)
9051 addressT alignment
, fill
, fill_limit
, fill_step
;
9052 bfd_boolean skip_one
= FALSE
;
9054 alignment
= (1 << align_pow
);
9055 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
9059 fill_limit
= alignment
;
9062 else if (!use_no_density
)
9064 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9065 fill_limit
= alignment
* 2;
9071 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9072 fill_limit
= alignment
* 3;
9076 /* Try all fill sizes until finding one that works. */
9077 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
9079 if (skip_one
&& fill
== 1)
9081 if ((address
+ fill
) >> align_pow
9082 == (address
+ fill
+ target_size
- 1) >> align_pow
)
9091 branch_align_power (segT sec
)
9093 /* If the Xtensa processor has a fetch width of X, and
9094 the section is aligned to at least that boundary, then a branch
9095 target need only fit within that aligned block of memory to avoid
9096 a stall. Otherwise, try to fit branch targets within 4-byte
9097 aligned blocks (which may be insufficient, e.g., if the section
9098 has no alignment, but it's good enough). */
9099 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
9100 int sec_align
= get_recorded_alignment (sec
);
9102 if (sec_align
>= fetch_align
)
9109 /* This will assert if it is not possible. */
9112 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
9118 gas_assert (fill_size
% 3 == 0);
9119 return (fill_size
/ 3);
9122 gas_assert (fill_size
!= 1); /* Bad argument. */
9124 while (fill_size
> 1)
9127 if (fill_size
== 2 || fill_size
== 4)
9129 fill_size
-= insn_size
;
9132 gas_assert (fill_size
!= 1); /* Bad algorithm. */
9138 get_text_align_nth_nop_size (offsetT fill_size
,
9140 bfd_boolean use_no_density
)
9147 gas_assert (fill_size
!= 1); /* Bad argument. */
9149 while (fill_size
> 1)
9152 if (fill_size
== 2 || fill_size
== 4)
9154 fill_size
-= insn_size
;
9164 /* For the given fragment, find the appropriate address
9165 for it to begin at if we are using NOPs to align it. */
9168 get_noop_aligned_address (fragS
*fragP
, addressT address
)
9170 /* The rule is: get next fragment's FIRST instruction. Find
9171 the smallest number of bytes that need to be added to
9172 ensure that the next fragment's FIRST instruction will fit
9175 E.G., 2 bytes : 0, 1, 2 mod 4
9178 If the FIRST instruction MIGHT be relaxed,
9179 assume that it will become a 3-byte instruction.
9181 Note again here that LOOP instructions are not bundleable,
9182 and this relaxation only applies to LOOP opcodes. */
9185 int first_insn_size
;
9187 addressT pre_opcode_bytes
;
9190 xtensa_opcode opcode
;
9191 bfd_boolean is_loop
;
9193 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9194 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
9196 /* Find the loop frag. */
9197 first_insn
= next_non_empty_frag (fragP
);
9198 /* Now find the first insn frag. */
9199 first_insn
= next_non_empty_frag (first_insn
);
9201 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
9202 gas_assert (is_loop
);
9203 loop_insn_size
= xg_get_single_size (opcode
);
9205 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
9206 pre_opcode_bytes
+= loop_insn_size
;
9208 /* For loops, the alignment depends on the size of the
9209 instruction following the loop, not the LOOP instruction. */
9211 if (first_insn
== NULL
)
9212 first_insn_size
= xtensa_fetch_width
;
9214 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
9216 /* If it was 8, then we'll need a larger alignment for the section. */
9217 align_power
= get_text_align_power (first_insn_size
);
9218 record_alignment (now_seg
, align_power
);
9220 fill_size
= get_text_align_fill_size
9221 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
9222 fragP
->tc_frag_data
.is_no_density
);
9224 return address
+ fill_size
;
9228 /* 3 mechanisms for relaxing an alignment:
9230 Align to a power of 2.
9231 Align so the next fragment's instruction does not cross a word boundary.
9232 Align the current instruction so that if the next instruction
9233 were 3 bytes, it would not cross a word boundary.
9237 zeros - This is easy; always insert zeros.
9238 nops - 3-byte and 2-byte instructions
9242 >=5 : 3-byte instruction + fn (n-3)
9243 widening - widen previous instructions. */
9246 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
9248 addressT target_address
, loop_insn_offset
;
9250 xtensa_opcode loop_opcode
;
9251 bfd_boolean is_loop
;
9254 offsetT branch_align
;
9257 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9258 switch (fragP
->fr_subtype
)
9260 case RELAX_DESIRE_ALIGN
:
9261 target_size
= next_frag_format_size (fragP
);
9262 if (target_size
== XTENSA_UNDEFINED
)
9264 align_power
= branch_align_power (now_seg
);
9265 branch_align
= 1 << align_power
;
9266 /* Don't count on the section alignment being as large as the target. */
9267 if (target_size
> branch_align
)
9268 target_size
= branch_align
;
9269 opt_diff
= get_text_align_fill_size (address
, align_power
,
9270 target_size
, FALSE
, FALSE
);
9272 *max_diff
= (opt_diff
+ branch_align
9273 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
9274 gas_assert (*max_diff
>= opt_diff
);
9277 case RELAX_ALIGN_NEXT_OPCODE
:
9278 /* The next non-empty frag after this one holds the LOOP instruction
9279 that needs to be aligned. The required alignment depends on the
9280 size of the next non-empty frag after the loop frag, i.e., the
9281 first instruction in the loop. */
9282 loop_frag
= next_non_empty_frag (fragP
);
9283 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
9284 loop_insn_offset
= 0;
9285 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
9286 gas_assert (is_loop
);
9288 /* If the loop has been expanded then the LOOP instruction
9289 could be at an offset from this fragment. */
9290 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
9291 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
9293 /* In an ideal world, which is what we are shooting for here,
9294 we wouldn't need to use any NOPs immediately prior to the
9295 LOOP instruction. If this approach fails, relax_frag_loop_align
9296 will call get_noop_aligned_address. */
9298 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9299 align_power
= get_text_align_power (target_size
);
9300 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
9301 target_size
, FALSE
, FALSE
);
9303 *max_diff
= xtensa_fetch_width
9304 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9305 - target_size
+ opt_diff
;
9306 gas_assert (*max_diff
>= opt_diff
);
9317 /* md_relax_frag Hook and Helper Functions. */
9319 static long relax_frag_loop_align (fragS
*, long);
9320 static long relax_frag_for_align (fragS
*, long);
9321 static long relax_frag_immed
9322 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9324 /* Get projected address for the first fulcrum on a path from source to
9326 static addressT
xg_get_fulcrum (addressT source
, addressT target
)
9328 offsetT delta
= target
- source
;
9331 n
= (labs (delta
) + J_RANGE
- J_MARGIN
- 1) / (J_RANGE
- J_MARGIN
);
9332 return source
+ delta
/ n
;
9335 /* Given trampoline index, source and target of a jump find the best
9336 candidate trampoline for the first fulcrum. The best trampoline is
9337 the one in the reach of "j' instruction from the source, closest to
9338 the projected fulcrum address, and preferrably w/o a jump around or
9339 with already initialized jump around. */
9340 static size_t xg_find_best_trampoline (struct trampoline_index
*idx
,
9341 addressT source
, addressT target
)
9343 addressT fulcrum
= xg_get_fulcrum (source
, target
);
9346 size_t base_tr
= xg_find_trampoline (idx
, fulcrum
);
9349 /* Check trampoline frags around the base_tr to find the best. */
9350 for (dist
= 0; checked
; ++dist
)
9353 size_t tr
= base_tr
- dist
;
9357 /* Trampolines are checked in the following order:
9358 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9359 for (i
= 0; i
< 2; ++i
, tr
= base_tr
+ dist
+ 1)
9360 if (tr
< idx
->n_entries
)
9362 fragS
*trampoline_frag
= idx
->entry
[tr
];
9365 /* Don't check trampolines outside source - target interval. */
9366 if ((trampoline_frag
->fr_address
< source
&&
9367 trampoline_frag
->fr_address
< target
) ||
9368 (trampoline_frag
->fr_address
> source
&&
9369 trampoline_frag
->fr_address
> target
))
9372 /* Don't choose trampoline that contains the source. */
9373 if (source
>= trampoline_frag
->fr_address
9374 && source
<= trampoline_frag
->fr_address
+
9375 trampoline_frag
->fr_fix
)
9378 off
= trampoline_frag
->fr_address
- fulcrum
;
9379 /* Stop if some trampoline is found and the search is more than
9380 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9381 around is nice, but it shouldn't have much overhead. */
9382 if (best
< idx
->n_entries
&& labs (off
) > J_RANGE
/ 4)
9385 off
= trampoline_frag
->fr_address
- source
;
9386 if (labs (off
) < J_RANGE
- J_MARGIN
)
9389 /* Stop if a trampoline w/o jump around is found or initialized
9390 trampoline with jump around is found. */
9391 if (!trampoline_frag
->tc_frag_data
.needs_jump_around
||
9392 trampoline_frag
->fr_fix
)
9394 else if (best
>= idx
->n_entries
)
9400 if (best
< idx
->n_entries
)
9403 as_fatal (_("cannot find suitable trampoline"));
9406 static fixS
*xg_relax_fixup (struct trampoline_index
*idx
, fixS
*fixP
)
9408 symbolS
*s
= fixP
->fx_addsy
;
9409 addressT source
= fixP
->fx_frag
->fr_address
;
9410 addressT target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9411 size_t tr
= xg_find_best_trampoline (idx
, source
, target
);
9412 fragS
*trampoline_frag
= idx
->entry
[tr
];
9415 init_trampoline_frag (trampoline_frag
);
9416 newfixP
= xg_append_jump (trampoline_frag
,
9417 fixP
->fx_addsy
, fixP
->fx_offset
);
9419 /* Adjust the fixup for the original "j" instruction to
9420 point to the newly added jump. */
9421 fixP
->fx_addsy
= trampoline_frag
->fr_symbol
;
9422 fixP
->fx_offset
= trampoline_frag
->fr_fix
- 3;
9423 fixP
->tc_fix_data
.X_add_symbol
= trampoline_frag
->fr_symbol
;
9424 fixP
->tc_fix_data
.X_add_number
= trampoline_frag
->fr_fix
- 3;
9426 trampoline_frag
->tc_frag_data
.relax_seen
= FALSE
;
9428 if (xg_is_trampoline_frag_full (trampoline_frag
))
9429 xg_remove_trampoline_from_index (idx
, tr
);
9434 static bfd_boolean
xg_is_relaxable_fixup (fixS
*fixP
)
9436 xtensa_isa isa
= xtensa_default_isa
;
9437 addressT addr
= fixP
->fx_frag
->fr_address
;
9440 symbolS
*s
= fixP
->fx_addsy
;
9443 xtensa_opcode opcode
;
9445 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9446 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9449 target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9450 delta
= target
- addr
;
9452 if (labs (delta
) < J_RANGE
- J_MARGIN
)
9455 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9456 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9458 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9459 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9460 slot
= fixP
->tc_fix_data
.slot
;
9461 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9462 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9463 return opcode
== xtensa_j_opcode
;
9466 static void xg_relax_fixups (struct trampoline_seg
*ts
)
9468 struct trampoline_index
*idx
= &ts
->index
;
9469 segment_info_type
*seginfo
= seg_info (now_seg
);
9472 for (fx
= seginfo
->fix_root
; fx
; fx
= fx
->fx_next
)
9475 struct trampoline_chain
*tc
= NULL
;
9477 if (xg_is_relaxable_fixup (fixP
))
9479 tc
= xg_find_best_eq_target (ts
, fixP
->fx_frag
->fr_address
,
9480 &fixP
->fx_addsy
, &fixP
->fx_offset
);
9482 tc
= xg_create_trampoline_chain (ts
, fixP
->fx_addsy
,
9487 while (xg_is_relaxable_fixup (fixP
))
9489 fixP
= xg_relax_fixup (idx
, fixP
);
9490 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
9496 /* Given a trampoline frag relax all jumps that might want to use this
9497 trampoline. Only do real work once per relaxation cycle, when
9498 xg_relax_trampoline is called for the first trampoline in the now_seg.
9499 Don't use stretch, don't update new_stretch: place fulcrums with a
9500 slack to tolerate code movement. In the worst case if a jump between
9501 two trampolines wouldn't reach the next relaxation pass will fix it. */
9502 static void xg_relax_trampoline (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
,
9503 long *new_stretch ATTRIBUTE_UNUSED
)
9505 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9507 if (ts
->index
.n_entries
&& ts
->index
.entry
[0] == fragP
)
9508 xg_relax_fixups (ts
);
9511 /* Return the number of bytes added to this fragment, given that the
9512 input has been stretched already by "stretch". */
9515 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9517 xtensa_isa isa
= xtensa_default_isa
;
9518 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9519 long new_stretch
= 0;
9520 const char *file_name
;
9523 static xtensa_insnbuf vbuf
= NULL
;
9524 int slot
, num_slots
;
9527 file_name
= as_where (&line
);
9528 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9530 fragP
->tc_frag_data
.unreported_expansion
= 0;
9532 switch (fragP
->fr_subtype
)
9534 case RELAX_ALIGN_NEXT_OPCODE
:
9535 /* Always convert. */
9536 if (fragP
->tc_frag_data
.relax_seen
)
9537 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9540 case RELAX_LOOP_END
:
9544 case RELAX_LOOP_END_ADD_NOP
:
9545 /* Add a NOP and switch to .fill 0. */
9546 new_stretch
= relax_frag_add_nop (fragP
);
9550 case RELAX_DESIRE_ALIGN
:
9551 /* Do nothing. The narrowing before this frag will either align
9556 case RELAX_LITERAL_FINAL
:
9559 case RELAX_LITERAL_NR
:
9561 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9562 gas_assert (unreported
== lit_size
);
9563 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9564 fragP
->fr_var
-= lit_size
;
9565 fragP
->fr_fix
+= lit_size
;
9571 vbuf
= xtensa_insnbuf_alloc (isa
);
9573 xtensa_insnbuf_from_chars
9574 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9575 fmt
= xtensa_format_decode (isa
, vbuf
);
9576 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9578 for (slot
= 0; slot
< num_slots
; slot
++)
9580 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9583 if (fragP
->tc_frag_data
.relax_seen
)
9584 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9588 case RELAX_IMMED_STEP1
:
9589 case RELAX_IMMED_STEP2
:
9590 case RELAX_IMMED_STEP3
:
9591 /* Place the immediate. */
9592 new_stretch
+= relax_frag_immed
9593 (now_seg
, fragP
, stretch
,
9594 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9595 fmt
, slot
, stretched_p
, FALSE
);
9599 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9605 case RELAX_LITERAL_POOL_BEGIN
:
9606 if (fragP
->fr_var
!= 0)
9608 /* We have a converted "candidate" literal pool;
9609 assemble a jump around it. */
9611 if (!litpool_slotbuf
)
9613 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9614 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9617 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9618 fragP
->tc_frag_data
.is_insn
= TRUE
;
9620 insn
.insn_type
= ITYPE_INSN
;
9621 insn
.opcode
= xtensa_j_opcode
;
9623 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9625 fmt
= xg_get_single_format (xtensa_j_opcode
);
9626 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9627 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9628 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9629 (unsigned char *)fragP
->fr_literal
+
9634 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9635 BFD_RELOC_XTENSA_SLOT0_OP
);
9639 case RELAX_LITERAL_POOL_END
:
9640 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9641 case RELAX_MAYBE_UNREACHABLE
:
9642 case RELAX_MAYBE_DESIRE_ALIGN
:
9643 /* No relaxation required. */
9646 case RELAX_FILL_NOP
:
9647 case RELAX_UNREACHABLE
:
9648 if (fragP
->tc_frag_data
.relax_seen
)
9649 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9652 case RELAX_TRAMPOLINE
:
9653 if (fragP
->tc_frag_data
.relax_seen
)
9654 xg_relax_trampoline (fragP
, stretch
, &new_stretch
);
9658 as_bad (_("bad relaxation state"));
9661 /* Tell gas we need another relaxation pass. */
9662 if (! fragP
->tc_frag_data
.relax_seen
)
9664 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9668 new_logical_line (file_name
, line
);
9674 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9676 addressT old_address
, old_next_address
, old_size
;
9677 addressT new_address
, new_next_address
, new_size
;
9680 /* All the frags with relax_frag_for_alignment prior to this one in the
9681 section have been done, hopefully eliminating the need for a NOP here.
9682 But, this will put it in if necessary. */
9684 /* Calculate the old address of this fragment and the next fragment. */
9685 old_address
= fragP
->fr_address
- stretch
;
9686 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9687 fragP
->tc_frag_data
.text_expansion
[0]);
9688 old_size
= old_next_address
- old_address
;
9690 /* Calculate the new address of this fragment and the next fragment. */
9691 new_address
= fragP
->fr_address
;
9693 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9694 new_size
= new_next_address
- new_address
;
9696 growth
= new_size
- old_size
;
9698 /* Fix up the text_expansion field and return the new growth. */
9699 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9704 /* Add a NOP instruction. */
9707 relax_frag_add_nop (fragS
*fragP
)
9709 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9710 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9711 assemble_nop (length
, nop_buf
);
9712 fragP
->tc_frag_data
.is_insn
= TRUE
;
9714 if (fragP
->fr_var
< length
)
9716 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9720 fragP
->fr_fix
+= length
;
9721 fragP
->fr_var
-= length
;
9726 static long future_alignment_required (fragS
*, long);
9729 relax_frag_for_align (fragS
*fragP
, long stretch
)
9731 /* Overview of the relaxation procedure for alignment:
9732 We can widen with NOPs or by widening instructions or by filling
9733 bytes after jump instructions. Find the opportune places and widen
9734 them if necessary. */
9739 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9740 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9741 || (fragP
->fr_subtype
== RELAX_SLOTS
9742 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9744 stretch_me
= future_alignment_required (fragP
, stretch
);
9745 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9751 /* We expanded on a previous pass. Can we shrink now? */
9752 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9753 if (shrink
<= stretch
&& stretch
> 0)
9755 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9761 /* Below here, diff > 0. */
9762 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9768 /* Return the address of the next frag that should be aligned.
9770 By "address" we mean the address it _would_ be at if there
9771 is no action taken to align it between here and the target frag.
9772 In other words, if no narrows and no fill nops are used between
9773 here and the frag to align, _even_if_ some of the frags we use
9774 to align targets have already expanded on a previous relaxation
9777 Also, count each frag that may be used to help align the target.
9779 Return 0 if there are no frags left in the chain that need to be
9783 find_address_of_next_align_frag (fragS
**fragPP
,
9787 bfd_boolean
*paddable
)
9789 fragS
*fragP
= *fragPP
;
9790 addressT address
= fragP
->fr_address
;
9792 /* Do not reset the counts to 0. */
9796 /* Limit this to a small search. */
9797 if (*widens
>= (int) xtensa_fetch_width
)
9802 address
+= fragP
->fr_fix
;
9804 if (fragP
->fr_type
== rs_fill
)
9805 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9806 else if (fragP
->fr_type
== rs_machine_dependent
)
9808 switch (fragP
->fr_subtype
)
9810 case RELAX_UNREACHABLE
:
9814 case RELAX_FILL_NOP
:
9816 if (!fragP
->tc_frag_data
.is_no_density
)
9821 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9826 address
+= total_frag_text_expansion (fragP
);
9830 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9833 case RELAX_ALIGN_NEXT_OPCODE
:
9834 case RELAX_DESIRE_ALIGN
:
9838 case RELAX_MAYBE_UNREACHABLE
:
9839 case RELAX_MAYBE_DESIRE_ALIGN
:
9844 /* Just punt if we don't know the type. */
9851 /* Just punt if we don't know the type. */
9855 fragP
= fragP
->fr_next
;
9863 static long bytes_to_stretch (fragS
*, int, int, int, int);
9866 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9868 fragS
*this_frag
= fragP
;
9872 int narrow_nops
= 0;
9873 bfd_boolean paddable
= FALSE
;
9874 offsetT local_opt_diff
;
9877 int stretch_amount
= 0;
9878 int local_stretch_amount
;
9879 int global_stretch_amount
;
9881 address
= find_address_of_next_align_frag
9882 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9886 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9887 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9889 frag_wane (this_frag
);
9893 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9894 opt_diff
= local_opt_diff
;
9895 gas_assert (opt_diff
>= 0);
9896 gas_assert (max_diff
>= opt_diff
);
9901 fragP
= fragP
->fr_next
;
9903 while (fragP
&& opt_diff
< max_diff
&& address
)
9905 /* We only use these to determine if we can exit early
9906 because there will be plenty of ways to align future
9908 int glob_widens
= 0;
9911 bfd_boolean glob_pad
= 0;
9912 address
= find_address_of_next_align_frag
9913 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9914 /* If there is a padable portion, then skip. */
9915 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9920 offsetT next_m_diff
;
9921 offsetT next_o_diff
;
9923 /* Downrange frags haven't had stretch added to them yet. */
9926 /* The address also includes any text expansion from this
9927 frag in a previous pass, but we don't want that. */
9928 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9930 /* Assume we are going to move at least opt_diff. In
9931 reality, we might not be able to, but assuming that
9932 we will helps catch cases where moving opt_diff pushes
9933 the next target from aligned to unaligned. */
9934 address
+= opt_diff
;
9936 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9938 /* Now cleanup for the adjustments to address. */
9939 next_o_diff
+= opt_diff
;
9940 next_m_diff
+= opt_diff
;
9941 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9942 opt_diff
= next_o_diff
;
9943 if (next_m_diff
< max_diff
)
9944 max_diff
= next_m_diff
;
9945 fragP
= fragP
->fr_next
;
9949 /* If there are enough wideners in between, do it. */
9952 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9954 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9959 local_stretch_amount
9960 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9961 num_widens
, local_opt_diff
);
9962 global_stretch_amount
9963 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9964 num_widens
, opt_diff
);
9965 /* If the condition below is true, then the frag couldn't
9966 stretch the correct amount for the global case, so we just
9967 optimize locally. We'll rely on the subsequent frags to get
9968 the correct alignment in the global case. */
9969 if (global_stretch_amount
< local_stretch_amount
)
9970 stretch_amount
= local_stretch_amount
;
9972 stretch_amount
= global_stretch_amount
;
9974 if (this_frag
->fr_subtype
== RELAX_SLOTS
9975 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9976 gas_assert (stretch_amount
<= 1);
9977 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9979 if (this_frag
->tc_frag_data
.is_no_density
)
9980 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9982 gas_assert (stretch_amount
<= 3);
9985 return stretch_amount
;
9989 /* The idea: widen everything you can to get a target or loop aligned,
9990 then start using NOPs.
9992 wide_nops = the number of wide NOPs available for aligning
9993 narrow_nops = the number of narrow NOPs available for aligning
9994 (a subset of wide_nops)
9995 widens = the number of narrow instructions that should be widened
10000 bytes_to_stretch (fragS
*this_frag
,
10009 int bytes_short
= desired_diff
- num_widens
;
10011 gas_assert (desired_diff
>= 0
10012 && desired_diff
< (signed) xtensa_fetch_width
);
10013 if (desired_diff
== 0)
10016 gas_assert (wide_nops
> 0 || num_widens
> 0);
10018 /* Always prefer widening to NOP-filling. */
10019 if (bytes_short
< 0)
10021 /* There are enough RELAX_NARROW frags after this one
10022 to align the target without widening this frag in any way. */
10026 if (bytes_short
== 0)
10028 /* Widen every narrow between here and the align target
10029 and the align target will be properly aligned. */
10030 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10036 /* From here we will need at least one NOP to get an alignment.
10037 However, we may not be able to align at all, in which case,
10039 nops_needed
= desired_diff
/ 3;
10041 /* If there aren't enough nops, don't widen. */
10042 if (nops_needed
> wide_nops
)
10045 /* First try it with all wide nops. */
10046 nop_bytes
= nops_needed
* 3;
10047 extra_bytes
= desired_diff
- nop_bytes
;
10049 if (nop_bytes
+ num_widens
>= desired_diff
)
10051 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10053 else if (num_widens
== extra_bytes
)
10058 /* Add a narrow nop. */
10062 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
10065 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
10067 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10068 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10069 else if (num_widens
== extra_bytes
)
10074 /* Replace a wide nop with a narrow nop--we can get here if
10075 extra_bytes was negative in the previous conditional. */
10076 if (narrow_nops
== 1)
10080 if (nop_bytes
+ num_widens
>= desired_diff
)
10082 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10083 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10084 else if (num_widens
== extra_bytes
)
10089 /* If we can't satisfy any of the above cases, then we can't align
10090 using padding or fill nops. */
10096 xg_find_best_trampoline_for_tinsn (TInsn
*tinsn
, fragS
*fragP
)
10098 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
10099 addressT source
= fragP
->fr_address
;
10100 addressT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
10101 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10104 if (!ts
|| !ts
->index
.n_entries
)
10107 i
= xg_find_best_trampoline (&ts
->index
, source
, target
);
10109 return ts
->index
.entry
[i
];
10113 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10114 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10115 and finish the frag if it's full (but don't remove it from the trampoline
10116 frag index). Return fixup for the newly created jump. */
10117 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
)
10122 xtensa_isa isa
= xtensa_default_isa
;
10124 gas_assert (fragP
->fr_var
>= 3);
10125 tinsn_init (&insn
);
10126 insn
.insn_type
= ITYPE_INSN
;
10127 insn
.opcode
= xtensa_j_opcode
;
10129 set_expr_symbol_offset (&insn
.tok
[0], sym
, offset
);
10130 fmt
= xg_get_single_format (xtensa_j_opcode
);
10131 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10132 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10133 xtensa_insnbuf_to_chars (isa
, trampoline_buf
,
10134 (unsigned char *)fragP
->fr_literal
+ fragP
->fr_fix
, 3);
10135 fixP
= fix_new (fragP
, fragP
->fr_fix
, 3, sym
, offset
, TRUE
,
10136 BFD_RELOC_XTENSA_SLOT0_OP
);
10137 fixP
->tc_fix_data
.slot
= 0;
10139 fragP
->fr_fix
+= 3;
10140 fragP
->fr_var
-= 3;
10142 /* Adjust the jump around this trampoline (if present). */
10143 if (fragP
->tc_frag_data
.jump_around_fix
)
10144 fragP
->tc_frag_data
.jump_around_fix
->fx_offset
+= 3;
10146 /* Do we have room for more? */
10147 if (xg_is_trampoline_frag_full (fragP
))
10150 fragP
->fr_subtype
= 0;
10158 init_trampoline_frag (fragS
*fp
)
10162 if (fp
->fr_fix
== 0)
10165 char label
[10 + 2 * sizeof(fp
)];
10167 sprintf (label
, ".L0_TR_%p", fp
);
10168 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10169 fp
->fr_symbol
= lsym
;
10170 if (fp
->tc_frag_data
.needs_jump_around
)
10172 fp
->tc_frag_data
.jump_around_fix
= xg_append_jump (fp
, lsym
, 3);
10180 xg_get_single_symbol_slot (fragS
*fragP
)
10185 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10186 if (fragP
->tc_frag_data
.slot_symbols
[i
])
10188 gas_assert (slot
== -1);
10192 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10198 add_jump_to_trampoline (fragS
*tramp
, fragS
*origfrag
)
10200 int slot
= xg_get_single_symbol_slot (origfrag
);
10203 /* Assemble a jump to the target label in the trampoline frag. */
10204 fixP
= xg_append_jump (tramp
,
10205 origfrag
->tc_frag_data
.slot_symbols
[slot
],
10206 origfrag
->tc_frag_data
.slot_offsets
[slot
]);
10208 /* Modify the original j to point here. */
10209 origfrag
->tc_frag_data
.slot_symbols
[slot
] = tramp
->fr_symbol
;
10210 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10212 /* If trampoline is full, remove it from the list. */
10213 if (xg_is_trampoline_frag_full (tramp
))
10215 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10216 size_t tr
= xg_find_trampoline (&ts
->index
, tramp
->fr_address
);
10218 gas_assert (ts
->index
.entry
[tr
] == tramp
);
10219 xg_remove_trampoline_from_index (&ts
->index
, tr
);
10227 relax_frag_immed (segT segP
,
10234 bfd_boolean estimate_only
)
10238 bfd_boolean negatable_branch
= FALSE
;
10239 bfd_boolean branch_jmp_to_next
= FALSE
;
10240 bfd_boolean from_wide_insn
= FALSE
;
10241 xtensa_isa isa
= xtensa_default_isa
;
10243 offsetT frag_offset
;
10245 int num_text_bytes
, num_literal_bytes
;
10246 int literal_diff
, total_text_diff
, this_text_diff
;
10248 gas_assert (fragP
->fr_opcode
!= NULL
);
10250 xg_clear_vinsn (&cur_vinsn
);
10251 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10252 if (cur_vinsn
.num_slots
> 1)
10253 from_wide_insn
= TRUE
;
10255 tinsn
= cur_vinsn
.slots
[slot
];
10256 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10258 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10261 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10262 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10264 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10266 old_size
= xtensa_format_length (isa
, fmt
);
10268 /* Special case: replace a branch to the next instruction with a NOP.
10269 This is required to work around a hardware bug in T1040.0 and also
10270 serves as an optimization. */
10272 if (branch_jmp_to_next
10273 && ((old_size
== 2) || (old_size
== 3))
10274 && !next_frag_is_loop_target (fragP
))
10277 /* Here is the fun stuff: Get the immediate field from this
10278 instruction. If it fits, we are done. If not, find the next
10279 instruction sequence that fits. */
10281 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10282 istack_init (&istack
);
10283 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10284 min_steps
, stretch
);
10285 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10287 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10289 /* Figure out the number of bytes needed. */
10290 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10292 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10293 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10295 if (from_wide_insn
)
10298 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10301 num_text_bytes
+= old_size
;
10302 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10303 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10306 /* The first instruction in the relaxed sequence will go after
10307 the current wide instruction, and thus its symbolic immediates
10310 istack_init (&istack
);
10311 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10312 frag_offset
+ old_size
,
10313 min_steps
, stretch
+ old_size
);
10314 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10316 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10317 = (int) RELAX_IMMED
+ num_steps
;
10319 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10321 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10323 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10327 total_text_diff
= num_text_bytes
- old_size
;
10328 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10330 /* It MUST get larger. If not, we could get an infinite loop. */
10331 gas_assert (num_text_bytes
>= 0);
10332 gas_assert (literal_diff
>= 0);
10333 gas_assert (total_text_diff
>= 0);
10335 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10336 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10337 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10338 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10340 /* Find the associated expandable literal for this. */
10341 if (literal_diff
!= 0)
10343 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10346 gas_assert (literal_diff
== 4);
10347 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10349 /* We expect that the literal section state has NOT been
10351 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10352 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10353 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10355 /* We need to mark this section for another iteration
10361 if (negatable_branch
&& istack
.ninsn
> 1)
10362 update_next_frag_state (fragP
);
10364 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10365 if (istack
.ninsn
> 2 &&
10366 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10367 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10368 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10370 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10371 struct trampoline_seg
*ts
= find_trampoline_seg (segP
);
10372 struct trampoline_chain
*tc
= NULL
;
10375 !xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10378 int s
= xg_get_single_symbol_slot (fragP
);
10379 addressT offset
= fragP
->tc_frag_data
.slot_offsets
[s
];
10381 tc
= xg_find_best_eq_target (ts
, fragP
->fr_address
,
10382 &fragP
->tc_frag_data
.slot_symbols
[s
],
10386 tc
= xg_create_trampoline_chain (ts
,
10387 fragP
->tc_frag_data
.slot_symbols
[s
],
10389 fragP
->tc_frag_data
.slot_offsets
[s
] = offset
;
10390 tinsn_immed_from_frag (jinsn
, fragP
, s
);
10393 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10396 fragS
*tf
= xg_find_best_trampoline_for_tinsn (jinsn
, fragP
);
10402 this_text_diff
+= init_trampoline_frag (tf
) + 3;
10403 fixP
= add_jump_to_trampoline (tf
, fragP
);
10404 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
10406 fragP
->tc_frag_data
.relax_seen
= FALSE
;
10410 /* If target symbol is undefined, assume it will reach once linked. */
10411 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10413 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10415 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10416 _("jump target out of range; no usable trampoline found"));
10422 return this_text_diff
;
10426 /* md_convert_frag Hook and Helper Functions. */
10428 static void convert_frag_align_next_opcode (fragS
*);
10429 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10430 static void convert_frag_fill_nop (fragS
*);
10431 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10434 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10436 static xtensa_insnbuf vbuf
= NULL
;
10437 xtensa_isa isa
= xtensa_default_isa
;
10441 const char *file_name
;
10444 file_name
= as_where (&line
);
10445 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10447 switch (fragp
->fr_subtype
)
10449 case RELAX_ALIGN_NEXT_OPCODE
:
10450 /* Always convert. */
10451 convert_frag_align_next_opcode (fragp
);
10454 case RELAX_DESIRE_ALIGN
:
10455 /* Do nothing. If not aligned already, too bad. */
10458 case RELAX_LITERAL
:
10459 case RELAX_LITERAL_FINAL
:
10464 vbuf
= xtensa_insnbuf_alloc (isa
);
10466 xtensa_insnbuf_from_chars
10467 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10468 fmt
= xtensa_format_decode (isa
, vbuf
);
10469 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10471 for (slot
= 0; slot
< num_slots
; slot
++)
10473 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10476 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10480 case RELAX_IMMED_STEP1
:
10481 case RELAX_IMMED_STEP2
:
10482 case RELAX_IMMED_STEP3
:
10483 /* Place the immediate. */
10486 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10491 /* This is OK because some slots could have
10492 relaxations and others have none. */
10498 case RELAX_UNREACHABLE
:
10499 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10500 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10501 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10505 case RELAX_MAYBE_UNREACHABLE
:
10506 case RELAX_MAYBE_DESIRE_ALIGN
:
10510 case RELAX_FILL_NOP
:
10511 convert_frag_fill_nop (fragp
);
10514 case RELAX_LITERAL_NR
:
10515 if (use_literal_section
)
10517 /* This should have been handled during relaxation. When
10518 relaxing a code segment, literals sometimes need to be
10519 added to the corresponding literal segment. If that
10520 literal segment has already been relaxed, then we end up
10521 in this situation. Marking the literal segments as data
10522 would make this happen less often (since GAS always relaxes
10523 code before data), but we could still get into trouble if
10524 there are instructions in a segment that is not marked as
10525 containing code. Until we can implement a better solution,
10526 cheat and adjust the addresses of all the following frags.
10527 This could break subsequent alignments, but the linker's
10528 literal coalescing will do that anyway. */
10531 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10532 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10533 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10534 fragp
->fr_var
-= 4;
10535 fragp
->fr_fix
+= 4;
10536 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10537 f
->fr_address
+= 4;
10540 as_bad (_("invalid relaxation fragment result"));
10543 case RELAX_TRAMPOLINE
:
10548 new_logical_line (file_name
, line
);
10553 convert_frag_align_next_opcode (fragS
*fragp
)
10555 char *nop_buf
; /* Location for Writing. */
10556 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10557 addressT aligned_address
;
10559 int nop
, nop_count
;
10561 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10563 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10564 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10565 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10567 for (nop
= 0; nop
< nop_count
; nop
++)
10570 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10572 assemble_nop (nop_size
, nop_buf
);
10573 nop_buf
+= nop_size
;
10576 fragp
->fr_fix
+= fill_size
;
10577 fragp
->fr_var
-= fill_size
;
10582 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10584 TInsn tinsn
, single_target
;
10585 int size
, old_size
, diff
;
10586 offsetT frag_offset
;
10588 gas_assert (slot
== 0);
10589 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10591 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10593 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10594 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10595 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10600 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10602 /* No conversion. */
10607 gas_assert (fragP
->fr_opcode
!= NULL
);
10609 /* Frags in this relaxation state should only contain
10610 single instruction bundles. */
10611 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10613 /* Just convert it to a wide form.... */
10615 old_size
= xg_get_single_size (tinsn
.opcode
);
10617 tinsn_init (&single_target
);
10618 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10620 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10622 as_bad (_("unable to widen instruction"));
10626 size
= xg_get_single_size (single_target
.opcode
);
10627 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10628 frag_offset
, TRUE
);
10630 diff
= size
- old_size
;
10631 gas_assert (diff
>= 0);
10632 gas_assert (diff
<= fragP
->fr_var
);
10633 fragP
->fr_var
-= diff
;
10634 fragP
->fr_fix
+= diff
;
10642 convert_frag_fill_nop (fragS
*fragP
)
10644 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10645 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10646 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10647 - fragP
->fr_address
- fragP
->fr_fix
));
10650 /* No conversion. */
10654 assemble_nop (size
, loc
);
10655 fragP
->tc_frag_data
.is_insn
= TRUE
;
10656 fragP
->fr_var
-= size
;
10657 fragP
->fr_fix
+= size
;
10662 static fixS
*fix_new_exp_in_seg
10663 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10664 bfd_reloc_code_real_type
);
10665 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10668 convert_frag_immed (segT segP
,
10674 char *immed_instr
= fragP
->fr_opcode
;
10676 bfd_boolean expanded
= FALSE
;
10677 bfd_boolean branch_jmp_to_next
= FALSE
;
10678 char *fr_opcode
= fragP
->fr_opcode
;
10679 xtensa_isa isa
= xtensa_default_isa
;
10680 bfd_boolean from_wide_insn
= FALSE
;
10682 bfd_boolean is_loop
;
10684 gas_assert (fr_opcode
!= NULL
);
10686 xg_clear_vinsn (&cur_vinsn
);
10688 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10689 if (cur_vinsn
.num_slots
> 1)
10690 from_wide_insn
= TRUE
;
10692 orig_tinsn
= cur_vinsn
.slots
[slot
];
10693 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10695 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10697 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10698 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10700 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10702 /* Conversion just inserts a NOP and marks the fix as completed. */
10703 bytes
= xtensa_format_length (isa
, fmt
);
10706 cur_vinsn
.slots
[slot
].opcode
=
10707 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10708 cur_vinsn
.slots
[slot
].ntok
= 0;
10712 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10713 gas_assert (bytes
== 2 || bytes
== 3);
10714 build_nop (&cur_vinsn
.slots
[0], bytes
);
10715 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10717 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10718 xtensa_insnbuf_to_chars
10719 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10724 /* Here is the fun stuff: Get the immediate field from this
10725 instruction. If it fits, we're done. If not, find the next
10726 instruction sequence that fits. */
10730 symbolS
*lit_sym
= NULL
;
10731 int total_size
= 0;
10732 int target_offset
= 0;
10735 symbolS
*gen_label
= NULL
;
10736 offsetT frag_offset
;
10737 bfd_boolean first
= TRUE
;
10739 /* It does not fit. Find something that does and
10740 convert immediately. */
10741 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10742 istack_init (&istack
);
10743 xg_assembly_relax (&istack
, &orig_tinsn
,
10744 segP
, fragP
, frag_offset
, min_steps
, 0);
10746 old_size
= xtensa_format_length (isa
, fmt
);
10748 /* Assemble this right inline. */
10750 /* First, create the mapping from a label name to the REAL label. */
10752 for (i
= 0; i
< istack
.ninsn
; i
++)
10754 TInsn
*tinsn
= &istack
.insn
[i
];
10757 switch (tinsn
->insn_type
)
10759 case ITYPE_LITERAL
:
10760 if (lit_sym
!= NULL
)
10761 as_bad (_("multiple literals in expansion"));
10762 /* First find the appropriate space in the literal pool. */
10763 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10764 if (lit_frag
== NULL
)
10765 as_bad (_("no registered fragment for literal"));
10766 if (tinsn
->ntok
!= 1)
10767 as_bad (_("number of literal tokens != 1"));
10769 /* Set the literal symbol and add a fixup. */
10770 lit_sym
= lit_frag
->fr_symbol
;
10774 if (align_targets
&& !is_loop
)
10776 fragS
*unreach
= fragP
->fr_next
;
10777 while (!(unreach
->fr_type
== rs_machine_dependent
10778 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10779 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10781 unreach
= unreach
->fr_next
;
10784 gas_assert (unreach
->fr_type
== rs_machine_dependent
10785 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10786 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10788 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10790 gas_assert (gen_label
== NULL
);
10791 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10792 fr_opcode
- fragP
->fr_literal
10793 + target_offset
, fragP
);
10797 if (first
&& from_wide_insn
)
10799 target_offset
+= xtensa_format_length (isa
, fmt
);
10801 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10802 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10805 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10812 for (i
= 0; i
< istack
.ninsn
; i
++)
10814 TInsn
*tinsn
= &istack
.insn
[i
];
10818 bfd_reloc_code_real_type reloc_type
;
10820 switch (tinsn
->insn_type
)
10822 case ITYPE_LITERAL
:
10823 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10824 /* Already checked. */
10825 gas_assert (lit_frag
!= NULL
);
10826 gas_assert (lit_sym
!= NULL
);
10827 gas_assert (tinsn
->ntok
== 1);
10829 target_seg
= S_GET_SEGMENT (lit_sym
);
10830 gas_assert (target_seg
);
10831 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10832 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10833 &tinsn
->tok
[0], FALSE
, reloc_type
);
10840 xg_resolve_labels (tinsn
, gen_label
);
10841 xg_resolve_literals (tinsn
, lit_sym
);
10842 if (from_wide_insn
&& first
)
10845 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10847 cur_vinsn
.slots
[slot
] = *tinsn
;
10851 cur_vinsn
.slots
[slot
].opcode
=
10852 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10853 cur_vinsn
.slots
[slot
].ntok
= 0;
10855 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10856 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10857 (unsigned char *) immed_instr
, 0);
10858 fragP
->tc_frag_data
.is_insn
= TRUE
;
10859 size
= xtensa_format_length (isa
, fmt
);
10860 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10862 xg_emit_insn_to_buf
10863 (tinsn
, immed_instr
+ size
, fragP
,
10864 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10865 size
+= xg_get_single_size (tinsn
->opcode
);
10870 size
= xg_get_single_size (tinsn
->opcode
);
10871 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10872 immed_instr
- fragP
->fr_literal
, TRUE
);
10874 immed_instr
+= size
;
10875 total_size
+= size
;
10880 diff
= total_size
- old_size
;
10881 gas_assert (diff
>= 0);
10884 gas_assert (diff
<= fragP
->fr_var
);
10885 fragP
->fr_var
-= diff
;
10886 fragP
->fr_fix
+= diff
;
10889 /* Check for undefined immediates in LOOP instructions. */
10893 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10894 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10896 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10899 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10900 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10902 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10907 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10908 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10910 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10912 /* Add an expansion note on the expanded instruction. */
10913 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10914 &orig_tinsn
.tok
[0], TRUE
,
10915 BFD_RELOC_XTENSA_ASM_EXPAND
);
10920 /* Add a new fix expression into the desired segment. We have to
10921 switch to that segment to do this. */
10924 fix_new_exp_in_seg (segT new_seg
,
10925 subsegT new_subseg
,
10931 bfd_reloc_code_real_type r_type
)
10934 segT seg
= now_seg
;
10935 subsegT subseg
= now_subseg
;
10937 gas_assert (new_seg
!= 0);
10938 subseg_set (new_seg
, new_subseg
);
10940 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10941 subseg_set (seg
, subseg
);
10946 /* Relax a loop instruction so that it can span loop >256 bytes.
10952 addi as, as, lo8 (label-.L1)
10953 addmi as, as, mid8 (label-.L1)
10964 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10969 unsigned long target
;
10970 static xtensa_insnbuf insnbuf
= NULL
;
10971 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10972 xtensa_isa isa
= xtensa_default_isa
;
10973 addressT loop_offset
;
10974 addressT addi_offset
= 9;
10975 addressT addmi_offset
= 12;
10980 insnbuf
= xtensa_insnbuf_alloc (isa
);
10982 /* Get the loop offset. */
10983 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10985 /* Validate that there really is a LOOP at the loop_offset. Because
10986 loops are not bundleable, we can assume that the instruction will be
10988 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10989 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10991 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10992 addi_offset
+= loop_offset
;
10993 addmi_offset
+= loop_offset
;
10995 gas_assert (tinsn
->ntok
== 2);
10996 if (tinsn
->tok
[1].X_op
== O_constant
)
10997 target
= tinsn
->tok
[1].X_add_number
;
10998 else if (tinsn
->tok
[1].X_op
== O_symbol
)
11000 /* Find the fragment. */
11001 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
11002 gas_assert (S_GET_SEGMENT (sym
) == segP
11003 || S_GET_SEGMENT (sym
) == absolute_section
);
11004 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
11008 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
11012 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
11013 loop_length_hi
= loop_length
& ~0x0ff;
11014 loop_length_lo
= loop_length
& 0x0ff;
11015 if (loop_length_lo
>= 128)
11017 loop_length_lo
-= 256;
11018 loop_length_hi
+= 256;
11021 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
11022 32512. If the loop is larger than that, then we just fail. */
11023 if (loop_length_hi
> 32512)
11024 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11025 _("loop too long for LOOP instruction"));
11027 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
11028 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
11030 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
11031 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
11033 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
11034 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
11036 fragP
->tc_frag_data
.is_insn
= TRUE
;
11037 xtensa_insnbuf_to_chars
11038 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
11040 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
11041 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
11042 xtensa_insnbuf_to_chars
11043 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
11045 /* Walk through all of the frags from here to the loop end
11046 and mark them as no_transform to keep them from being modified
11047 by the linker. If we ever have a relocation for the
11048 addi/addmi of the difference of two symbols we can remove this. */
11051 for (next_fragP
= fragP
; next_fragP
!= NULL
;
11052 next_fragP
= next_fragP
->fr_next
)
11054 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
11055 if (next_fragP
->tc_frag_data
.is_loop_target
)
11057 if (target_count
== 2)
11063 /* A map that keeps information on a per-subsegment basis. This is
11064 maintained during initial assembly, but is invalid once the
11065 subsegments are smashed together. I.E., it cannot be used during
11068 typedef struct subseg_map_struct
11076 float total_freq
; /* fall-through + branch target frequency */
11077 float target_freq
; /* branch target frequency alone */
11079 struct subseg_map_struct
*next
;
11083 static subseg_map
*sseg_map
= NULL
;
11085 static subseg_map
*
11086 get_subseg_info (segT seg
, subsegT subseg
)
11088 subseg_map
*subseg_e
;
11090 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
11092 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
11099 static subseg_map
*
11100 add_subseg_info (segT seg
, subsegT subseg
)
11102 subseg_map
*subseg_e
= XNEW (subseg_map
);
11103 memset (subseg_e
, 0, sizeof (subseg_map
));
11104 subseg_e
->seg
= seg
;
11105 subseg_e
->subseg
= subseg
;
11106 subseg_e
->flags
= 0;
11107 /* Start off considering every branch target very important. */
11108 subseg_e
->target_freq
= 1.0;
11109 subseg_e
->total_freq
= 1.0;
11110 subseg_e
->next
= sseg_map
;
11111 sseg_map
= subseg_e
;
11117 get_last_insn_flags (segT seg
, subsegT subseg
)
11119 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11121 return subseg_e
->flags
;
11127 set_last_insn_flags (segT seg
,
11132 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11134 subseg_e
= add_subseg_info (seg
, subseg
);
11136 subseg_e
->flags
|= fl
;
11138 subseg_e
->flags
&= ~fl
;
11143 get_subseg_total_freq (segT seg
, subsegT subseg
)
11145 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11147 return subseg_e
->total_freq
;
11153 get_subseg_target_freq (segT seg
, subsegT subseg
)
11155 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11157 return subseg_e
->target_freq
;
11163 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11165 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11167 subseg_e
= add_subseg_info (seg
, subseg
);
11168 subseg_e
->total_freq
= total_f
;
11169 subseg_e
->target_freq
= target_f
;
11173 /* Segment Lists and emit_state Stuff. */
11176 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11181 segT literal_section
= head
->seg
;
11183 /* Move the literal section to the front of the section list. */
11184 gas_assert (literal_section
);
11185 if (literal_section
!= stdoutput
->sections
)
11187 bfd_section_list_remove (stdoutput
, literal_section
);
11188 bfd_section_list_prepend (stdoutput
, literal_section
);
11195 static void mark_literal_frags (seg_list
*);
11198 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11199 struct litpool_frag
*lp
)
11204 char label
[10 + 2 * sizeof (fragS
*)];
11206 poolbeg
= lp
->fragP
;
11208 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11209 poolend
= poolbeg
->fr_next
;
11210 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11211 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11212 /* Create a local symbol pointing to the
11213 end of the pool. */
11214 sprintf (label
, ".L0_LT_%p", poolbeg
);
11215 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11217 poolbeg
->fr_symbol
= lsym
;
11218 /* Rest is done in xtensa_relax_frag. */
11221 static struct litpool_frag
*xg_find_litpool (struct litpool_seg
*lps
,
11222 struct litpool_frag
*lpf
,
11225 struct litpool_frag
*lp
= lpf
->prev
;
11227 gas_assert (lp
->fragP
);
11229 while (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11232 if (lp
->fragP
== NULL
)
11234 /* End of list; have to bite the bullet.
11235 Take the nearest. */
11239 /* Does it (conservatively) reach? */
11240 if (addr
- lp
->addr
<= 128 * 1024)
11242 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
11243 lp
->literal_count
< MAX_POOL_LITERALS
)
11245 /* Found a good one. */
11248 else if (lp
->prev
->fragP
&&
11249 addr
- lp
->prev
->addr
> 128 * 1024 &&
11250 lp
->prev
->literal_count
< MAX_POOL_LITERALS
)
11252 /* This is still a "candidate" but the next one
11253 will be too far away, so revert to the nearest
11254 one, convert it and add the jump around. */
11261 if (lp
->literal_count
>= MAX_POOL_LITERALS
)
11264 while (lp
&& lp
->fragP
&& lp
->literal_count
>= MAX_POOL_LITERALS
)
11271 gas_assert (lp
&& lp
->fragP
&& lp
->literal_count
< MAX_POOL_LITERALS
);
11272 ++lp
->literal_count
;
11274 /* Convert candidate and add the jump around. */
11275 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11276 xg_promote_candidate_litpool (lps
, lp
);
11281 static bfd_boolean
xtensa_is_init_fini (segT seg
)
11285 return strcmp (segment_name (seg
), INIT_SECTION_NAME
) == 0
11286 || strcmp (segment_name (seg
), FINI_SECTION_NAME
) == 0;
11290 xtensa_move_literals (void)
11293 frchainS
*frchain_from
, *frchain_to
;
11294 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11295 fragS
**frag_splice
;
11298 fixS
*fix
, *next_fix
, **fix_splice
;
11300 struct litpool_seg
*lps
;
11301 const char *init_name
= INIT_SECTION_NAME
;
11302 const char *fini_name
= FINI_SECTION_NAME
;
11303 int init_name_len
= strlen(init_name
);
11304 int fini_name_len
= strlen(fini_name
);
11306 mark_literal_frags (literal_head
->next
);
11308 if (use_literal_section
)
11311 /* Assign addresses (rough estimates) to the potential literal pool locations
11312 and create new ones if the gaps are too large. */
11314 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11316 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11317 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11320 if (xtensa_is_init_fini (lps
->seg
))
11323 for ( ; frchP
; frchP
= frchP
->frch_next
)
11326 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11328 if (lpf
&& fragP
== lpf
->fragP
)
11330 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11331 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11332 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11333 /* Found a litpool location. */
11337 if (fragP
->fr_type
== rs_machine_dependent
&&
11338 fragP
->fr_subtype
== RELAX_SLOTS
)
11341 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11343 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11346 && litfrag
->tc_frag_data
.is_literal
11347 && !litfrag
->tc_frag_data
.literal_frag
)
11349 /* L32R referring .literal or generated as a result
11350 of relaxation. Point its literal to the nearest
11351 litpool preferring non-"candidate" positions to
11352 avoid the jump-around. */
11354 struct litpool_frag
*lp
;
11356 lp
= xg_find_litpool (lps
, lpf
, addr
);
11357 /* Take earliest use of this literal to avoid
11359 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11363 addr
+= fragP
->fr_fix
;
11364 if (fragP
->fr_type
== rs_fill
)
11365 addr
+= fragP
->fr_offset
;
11370 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11372 const char *seg_name
= segment_name (segment
->seg
);
11374 /* Keep the literals for .init and .fini in separate sections. */
11375 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11376 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11377 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11378 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11381 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11382 search_frag
= frchain_from
->frch_root
;
11383 literal_pool
= NULL
;
11385 frag_splice
= &(frchain_from
->frch_root
);
11387 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11389 gas_assert (search_frag
->fr_fix
== 0
11390 || search_frag
->fr_type
== rs_align
);
11391 search_frag
= search_frag
->fr_next
;
11396 search_frag
= frchain_from
->frch_root
;
11397 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11398 _("literal pool location required for text-section-literals; specify with .literal_position"));
11402 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11403 == RELAX_LITERAL_POOL_BEGIN
);
11404 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11406 /* Make sure that all the frags in this series are closed, and
11407 that there is at least one left over of zero-size. This
11408 prevents us from making a segment with an frchain without any
11410 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11411 xtensa_set_frag_assembly_state (frag_now
);
11412 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11413 xtensa_set_frag_assembly_state (frag_now
);
11415 while (search_frag
!= frag_now
)
11417 next_frag
= search_frag
->fr_next
;
11418 if (search_frag
->tc_frag_data
.literal_frag
)
11420 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11421 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11422 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11423 gas_assert (frchain_to
);
11426 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11428 /* Skip empty fill frags. */
11429 *frag_splice
= next_frag
;
11430 search_frag
= next_frag
;
11434 if (search_frag
->fr_type
== rs_align
)
11436 /* Skip alignment frags, because the pool as a whole will be
11437 aligned if used, and we don't want to force alignment if the
11439 *frag_splice
= next_frag
;
11440 search_frag
= next_frag
;
11444 /* First, move the frag out of the literal section and
11445 to the appropriate place. */
11447 /* Insert an alignment frag at start of pool. */
11448 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11449 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11451 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11452 emit_state prev_state
;
11455 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11456 prev_frag
= frag_now
;
11457 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11458 align_frag
= frag_now
;
11459 frag_align (2, 0, 0);
11460 /* Splice it into the right place. */
11461 prev_frag
->fr_next
= align_frag
->fr_next
;
11462 align_frag
->fr_next
= literal_pool
->fr_next
;
11463 literal_pool
->fr_next
= align_frag
;
11464 /* Insert after this one. */
11465 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11466 xtensa_restore_emit_state (&prev_state
);
11468 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11469 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11470 /* Skip align frag. */
11471 if (insert_after
->fr_next
->fr_type
== rs_align
)
11473 insert_after
= insert_after
->fr_next
;
11476 *frag_splice
= next_frag
;
11477 search_frag
->fr_next
= insert_after
->fr_next
;
11478 insert_after
->fr_next
= search_frag
;
11479 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11480 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11482 /* Now move any fixups associated with this frag to the
11484 fix
= frchain_from
->fix_root
;
11485 fix_splice
= &(frchain_from
->fix_root
);
11488 next_fix
= fix
->fx_next
;
11489 if (fix
->fx_frag
== search_frag
)
11491 *fix_splice
= next_fix
;
11492 fix
->fx_next
= frchain_to
->fix_root
;
11493 frchain_to
->fix_root
= fix
;
11494 if (frchain_to
->fix_tail
== NULL
)
11495 frchain_to
->fix_tail
= fix
;
11498 fix_splice
= &(fix
->fx_next
);
11501 search_frag
= next_frag
;
11504 if (frchain_from
->fix_root
!= NULL
)
11506 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11507 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11509 gas_assert (frchain_from
->fix_root
== NULL
);
11511 frchain_from
->fix_tail
= NULL
;
11512 xtensa_restore_emit_state (&state
);
11515 /* Now fix up the SEGMENT value for all the literal symbols. */
11516 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11518 symbolS
*lit_sym
= lit
->sym
;
11519 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11521 S_SET_SEGMENT (lit_sym
, dseg
);
11526 /* Walk over all the frags for segments in a list and mark them as
11527 containing literals. As clunky as this is, we can't rely on frag_var
11528 and frag_variant to get called in all situations. */
11531 mark_literal_frags (seg_list
*segment
)
11533 frchainS
*frchain_from
;
11534 fragS
*search_frag
;
11538 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11539 search_frag
= frchain_from
->frch_root
;
11540 while (search_frag
)
11542 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11543 search_frag
= search_frag
->fr_next
;
11545 segment
= segment
->next
;
11551 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11553 /* Move all of the sections in the section list to come
11554 after "after" in the gnu segment list. */
11559 segT literal_section
= head
->seg
;
11561 /* Move the literal section after "after". */
11562 gas_assert (literal_section
);
11563 if (literal_section
!= after
)
11565 bfd_section_list_remove (stdoutput
, literal_section
);
11566 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11574 /* Push all the literal segments to the end of the gnu list. */
11577 xtensa_reorder_segments (void)
11584 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11590 /* Now that we have the last section, push all the literal
11591 sections to the end. */
11592 xtensa_reorder_seg_list (literal_head
, last_sec
);
11594 /* Now perform the final error check. */
11595 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11597 gas_assert (new_count
== old_count
);
11601 /* Change the emit state (seg, subseg, and frag related stuff) to the
11602 correct location. Return a emit_state which can be passed to
11603 xtensa_restore_emit_state to return to current fragment. */
11606 xtensa_switch_to_literal_fragment (emit_state
*result
)
11608 if (directive_state
[directive_absolute_literals
])
11610 segT lit4_seg
= cache_literal_section (TRUE
);
11611 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11614 xtensa_switch_to_non_abs_literal_fragment (result
);
11616 /* Do a 4-byte align here. */
11617 frag_align (2, 0, 0);
11618 record_alignment (now_seg
, 2);
11623 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11625 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11627 bfd_boolean is_init_fini
= xtensa_is_init_fini (now_seg
);
11629 if (pool_location
== NULL
11630 && !use_literal_section
11633 if (!auto_litpools
)
11635 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11637 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11638 pool_location
= get_literal_pool_location (now_seg
);
11641 lit_seg
= cache_literal_section (FALSE
);
11642 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11644 if (!use_literal_section
11646 && get_literal_pool_location (now_seg
) != pool_location
)
11648 /* Close whatever frag is there. */
11649 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11650 xtensa_set_frag_assembly_state (frag_now
);
11651 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11652 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11653 xtensa_set_frag_assembly_state (frag_now
);
11658 /* Call this function before emitting data into the literal section.
11659 This is a helper function for xtensa_switch_to_literal_fragment.
11660 This is similar to a .section new_now_seg subseg. */
11663 xtensa_switch_section_emit_state (emit_state
*state
,
11665 subsegT new_now_subseg
)
11667 state
->name
= now_seg
->name
;
11668 state
->now_seg
= now_seg
;
11669 state
->now_subseg
= now_subseg
;
11670 state
->generating_literals
= generating_literals
;
11671 generating_literals
++;
11672 subseg_set (new_now_seg
, new_now_subseg
);
11676 /* Use to restore the emitting into the normal place. */
11679 xtensa_restore_emit_state (emit_state
*state
)
11681 generating_literals
= state
->generating_literals
;
11682 subseg_set (state
->now_seg
, state
->now_subseg
);
11686 /* Predicate function used to look up a section in a particular group. */
11689 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11691 const char *gname
= inf
;
11692 const char *group_name
= elf_group_name (sec
);
11694 return (group_name
== gname
11695 || (group_name
!= NULL
11697 && strcmp (group_name
, gname
) == 0));
11701 /* Get the literal section to be used for the current text section.
11702 The result may be cached in the default_lit_sections structure. */
11705 cache_literal_section (bfd_boolean use_abs_literals
)
11707 const char *text_name
, *group_name
= 0;
11708 const char *base_name
, *suffix
;
11711 segT seg
, current_section
;
11712 int current_subsec
;
11713 bfd_boolean linkonce
= FALSE
;
11715 /* Save the current section/subsection. */
11716 current_section
= now_seg
;
11717 current_subsec
= now_subseg
;
11719 /* Clear the cached values if they are no longer valid. */
11720 if (now_seg
!= default_lit_sections
.current_text_seg
)
11722 default_lit_sections
.current_text_seg
= now_seg
;
11723 default_lit_sections
.lit_seg
= NULL
;
11724 default_lit_sections
.lit4_seg
= NULL
;
11727 /* Check if the literal section is already cached. */
11728 if (use_abs_literals
)
11729 pcached
= &default_lit_sections
.lit4_seg
;
11731 pcached
= &default_lit_sections
.lit_seg
;
11736 text_name
= default_lit_sections
.lit_prefix
;
11737 if (! text_name
|| ! *text_name
)
11739 text_name
= segment_name (current_section
);
11740 group_name
= elf_group_name (current_section
);
11741 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11744 base_name
= use_abs_literals
? ".lit4" : ".literal";
11747 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11749 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11751 suffix
= strchr (text_name
+ linkonce_len
, '.');
11753 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11759 /* If the section name begins or ends with ".text", then replace
11760 that portion instead of appending an additional suffix. */
11761 size_t len
= strlen (text_name
);
11763 && (strcmp (text_name
+ len
- 5, ".text") == 0
11764 || strncmp (text_name
, ".text", 5) == 0))
11767 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11768 if (strncmp (text_name
, ".text", 5) == 0)
11770 strcpy (name
, base_name
);
11771 strcat (name
, text_name
+ 5);
11775 strcpy (name
, text_name
);
11776 strcpy (name
+ len
, base_name
);
11780 /* Canonicalize section names to allow renaming literal sections.
11781 The group name, if any, came from the current text section and
11782 has already been canonicalized. */
11783 name
= tc_canonicalize_symbol_name (name
);
11785 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11786 (void *) group_name
);
11791 seg
= subseg_force_new (name
, 0);
11793 if (! use_abs_literals
)
11795 /* Add the newly created literal segment to the list. */
11796 seg_list
*n
= XNEW (seg_list
);
11798 n
->next
= literal_head
->next
;
11799 literal_head
->next
= n
;
11802 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11803 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11804 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11806 elf_group_name (seg
) = group_name
;
11808 bfd_set_section_flags (stdoutput
, seg
, flags
);
11809 bfd_set_section_alignment (stdoutput
, seg
, 2);
11813 subseg_set (current_section
, current_subsec
);
11818 /* Property Tables Stuff. */
11820 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11821 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11822 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11824 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11825 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11827 static bfd_boolean
get_frag_is_literal (const fragS
*);
11828 static void xtensa_create_property_segments
11829 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11830 static void xtensa_create_xproperty_segments
11831 (frag_flags_fn
, const char *, xt_section_type
);
11832 static bfd_boolean
exclude_section_from_property_tables (segT
);
11833 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11834 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11835 static void add_xt_block_frags
11836 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11837 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11838 static void xtensa_frag_flags_init (frag_flags
*);
11839 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11840 static flagword
frag_flags_to_number (const frag_flags
*);
11841 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11843 /* Set up property tables after relaxation. */
11846 xtensa_post_relax_hook (void)
11848 xtensa_move_seg_list_to_beginning (literal_head
);
11850 xtensa_find_unmarked_state_frags ();
11851 xtensa_mark_frags_for_org ();
11852 xtensa_mark_difference_of_two_symbols ();
11854 xtensa_create_property_segments (get_frag_is_literal
,
11856 XTENSA_LIT_SEC_NAME
,
11858 xtensa_create_xproperty_segments (get_frag_property_flags
,
11859 XTENSA_PROP_SEC_NAME
,
11862 if (warn_unaligned_branch_targets
)
11863 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11864 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11868 /* This function is only meaningful after xtensa_move_literals. */
11871 get_frag_is_literal (const fragS
*fragP
)
11873 gas_assert (fragP
!= NULL
);
11874 return fragP
->tc_frag_data
.is_literal
;
11879 xtensa_create_property_segments (frag_predicate property_function
,
11880 frag_predicate end_property_function
,
11881 const char *section_name_base
,
11882 xt_section_type sec_type
)
11886 /* Walk over all of the current segments.
11887 Walk over each fragment
11888 For each non-empty fragment,
11889 Build a property record (append where possible). */
11891 for (seclist
= &stdoutput
->sections
;
11892 seclist
&& *seclist
;
11893 seclist
= &(*seclist
)->next
)
11895 segT sec
= *seclist
;
11897 if (exclude_section_from_property_tables (sec
))
11900 if (section_has_property (sec
, property_function
))
11902 segment_info_type
*xt_seg_info
;
11903 xtensa_block_info
**xt_blocks
;
11904 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11906 prop_sec
->output_section
= prop_sec
;
11907 subseg_set (prop_sec
, 0);
11908 xt_seg_info
= seg_info (prop_sec
);
11909 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11911 /* Walk over all of the frchains here and add new sections. */
11912 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11913 end_property_function
);
11917 /* Now we fill them out.... */
11919 for (seclist
= &stdoutput
->sections
;
11920 seclist
&& *seclist
;
11921 seclist
= &(*seclist
)->next
)
11923 segment_info_type
*seginfo
;
11924 xtensa_block_info
*block
;
11925 segT sec
= *seclist
;
11927 seginfo
= seg_info (sec
);
11928 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11932 xtensa_block_info
*cur_block
;
11934 bfd_size_type rec_size
;
11936 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11939 rec_size
= num_recs
* 8;
11940 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11947 subseg_set (sec
, 0);
11948 frag_data
= frag_more (rec_size
);
11950 for (i
= 0; i
< num_recs
; i
++)
11954 /* Write the fixup. */
11955 gas_assert (cur_block
);
11956 fix
= fix_new (frag_now
, i
* 8, 4,
11957 section_symbol (cur_block
->sec
),
11959 FALSE
, BFD_RELOC_32
);
11960 fix
->fx_file
= "<internal>";
11963 /* Write the length. */
11964 md_number_to_chars (&frag_data
[4 + i
* 8],
11965 cur_block
->size
, 4);
11966 cur_block
= cur_block
->next
;
11968 frag_wane (frag_now
);
11970 frag_wane (frag_now
);
11978 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11979 const char *section_name_base
,
11980 xt_section_type sec_type
)
11984 /* Walk over all of the current segments.
11985 Walk over each fragment.
11986 For each fragment that has instructions,
11987 build an instruction record (append where possible). */
11989 for (seclist
= &stdoutput
->sections
;
11990 seclist
&& *seclist
;
11991 seclist
= &(*seclist
)->next
)
11993 segT sec
= *seclist
;
11995 if (exclude_section_from_property_tables (sec
))
11998 if (section_has_xproperty (sec
, flag_fn
))
12000 segment_info_type
*xt_seg_info
;
12001 xtensa_block_info
**xt_blocks
;
12002 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
12004 prop_sec
->output_section
= prop_sec
;
12005 subseg_set (prop_sec
, 0);
12006 xt_seg_info
= seg_info (prop_sec
);
12007 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
12009 /* Walk over all of the frchains here and add new sections. */
12010 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
12014 /* Now we fill them out.... */
12016 for (seclist
= &stdoutput
->sections
;
12017 seclist
&& *seclist
;
12018 seclist
= &(*seclist
)->next
)
12020 segment_info_type
*seginfo
;
12021 xtensa_block_info
*block
;
12022 segT sec
= *seclist
;
12024 seginfo
= seg_info (sec
);
12025 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
12029 xtensa_block_info
*cur_block
;
12031 bfd_size_type rec_size
;
12033 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
12036 rec_size
= num_recs
* (8 + 4);
12037 bfd_set_section_size (stdoutput
, sec
, rec_size
);
12038 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
12045 subseg_set (sec
, 0);
12046 frag_data
= frag_more (rec_size
);
12048 for (i
= 0; i
< num_recs
; i
++)
12052 /* Write the fixup. */
12053 gas_assert (cur_block
);
12054 fix
= fix_new (frag_now
, i
* 12, 4,
12055 section_symbol (cur_block
->sec
),
12057 FALSE
, BFD_RELOC_32
);
12058 fix
->fx_file
= "<internal>";
12061 /* Write the length. */
12062 md_number_to_chars (&frag_data
[4 + i
* 12],
12063 cur_block
->size
, 4);
12064 md_number_to_chars (&frag_data
[8 + i
* 12],
12065 frag_flags_to_number (&cur_block
->flags
),
12066 sizeof (flagword
));
12067 cur_block
= cur_block
->next
;
12069 frag_wane (frag_now
);
12071 frag_wane (frag_now
);
12079 exclude_section_from_property_tables (segT sec
)
12081 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
12083 /* Sections that don't contribute to the memory footprint are excluded. */
12084 if ((flags
& SEC_DEBUGGING
)
12085 || !(flags
& SEC_ALLOC
)
12086 || (flags
& SEC_MERGE
))
12089 /* Linker cie and fde optimizations mess up property entries for
12090 eh_frame sections, but there is nothing inside them relevant to
12091 property tables anyway. */
12092 if (strcmp (sec
->name
, ".eh_frame") == 0)
12100 section_has_property (segT sec
, frag_predicate property_function
)
12102 segment_info_type
*seginfo
= seg_info (sec
);
12105 if (seginfo
&& seginfo
->frchainP
)
12107 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12109 if (property_function (fragP
)
12110 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12119 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
12121 segment_info_type
*seginfo
= seg_info (sec
);
12124 if (seginfo
&& seginfo
->frchainP
)
12126 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12128 frag_flags prop_flags
;
12129 property_function (fragP
, &prop_flags
);
12130 if (!xtensa_frag_flags_is_empty (&prop_flags
))
12138 /* Two types of block sections exist right now: literal and insns. */
12141 add_xt_block_frags (segT sec
,
12142 xtensa_block_info
**xt_block
,
12143 frag_predicate property_function
,
12144 frag_predicate end_property_function
)
12148 /* Build it if needed. */
12149 while (*xt_block
!= NULL
)
12150 xt_block
= &(*xt_block
)->next
;
12151 /* We are either at NULL at the beginning or at the end. */
12153 /* Walk through the frags. */
12154 if (seg_info (sec
)->frchainP
)
12156 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
12158 fragP
= fragP
->fr_next
)
12160 if (property_function (fragP
)
12161 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12163 if (*xt_block
!= NULL
)
12165 if ((*xt_block
)->offset
+ (*xt_block
)->size
12166 == fragP
->fr_address
)
12167 (*xt_block
)->size
+= fragP
->fr_fix
;
12169 xt_block
= &((*xt_block
)->next
);
12171 if (*xt_block
== NULL
)
12173 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
12174 new_block
->sec
= sec
;
12175 new_block
->offset
= fragP
->fr_address
;
12176 new_block
->size
= fragP
->fr_fix
;
12177 new_block
->next
= NULL
;
12178 xtensa_frag_flags_init (&new_block
->flags
);
12179 *xt_block
= new_block
;
12181 if (end_property_function
12182 && end_property_function (fragP
))
12184 xt_block
= &((*xt_block
)->next
);
12192 /* Break the encapsulation of add_xt_prop_frags here. */
12195 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12197 if (prop_flags
->is_literal
12198 || prop_flags
->is_insn
12199 || prop_flags
->is_data
12200 || prop_flags
->is_unreachable
)
12207 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12209 memset (prop_flags
, 0, sizeof (frag_flags
));
12214 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12216 xtensa_frag_flags_init (prop_flags
);
12217 if (fragP
->tc_frag_data
.is_literal
)
12218 prop_flags
->is_literal
= TRUE
;
12219 if (fragP
->tc_frag_data
.is_specific_opcode
12220 || fragP
->tc_frag_data
.is_no_transform
)
12222 prop_flags
->is_no_transform
= TRUE
;
12223 if (xtensa_frag_flags_is_empty (prop_flags
))
12224 prop_flags
->is_data
= TRUE
;
12226 if (fragP
->tc_frag_data
.is_unreachable
)
12227 prop_flags
->is_unreachable
= TRUE
;
12228 else if (fragP
->tc_frag_data
.is_insn
)
12230 prop_flags
->is_insn
= TRUE
;
12231 if (fragP
->tc_frag_data
.is_loop_target
)
12232 prop_flags
->insn
.is_loop_target
= TRUE
;
12233 if (fragP
->tc_frag_data
.is_branch_target
)
12234 prop_flags
->insn
.is_branch_target
= TRUE
;
12235 if (fragP
->tc_frag_data
.is_no_density
)
12236 prop_flags
->insn
.is_no_density
= TRUE
;
12237 if (fragP
->tc_frag_data
.use_absolute_literals
)
12238 prop_flags
->insn
.is_abslit
= TRUE
;
12240 if (fragP
->tc_frag_data
.is_align
)
12242 prop_flags
->is_align
= TRUE
;
12243 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12244 if (xtensa_frag_flags_is_empty (prop_flags
))
12245 prop_flags
->is_data
= TRUE
;
12251 frag_flags_to_number (const frag_flags
*prop_flags
)
12254 if (prop_flags
->is_literal
)
12255 num
|= XTENSA_PROP_LITERAL
;
12256 if (prop_flags
->is_insn
)
12257 num
|= XTENSA_PROP_INSN
;
12258 if (prop_flags
->is_data
)
12259 num
|= XTENSA_PROP_DATA
;
12260 if (prop_flags
->is_unreachable
)
12261 num
|= XTENSA_PROP_UNREACHABLE
;
12262 if (prop_flags
->insn
.is_loop_target
)
12263 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12264 if (prop_flags
->insn
.is_branch_target
)
12266 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12267 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12270 if (prop_flags
->insn
.is_no_density
)
12271 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12272 if (prop_flags
->is_no_transform
)
12273 num
|= XTENSA_PROP_NO_TRANSFORM
;
12274 if (prop_flags
->insn
.is_no_reorder
)
12275 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12276 if (prop_flags
->insn
.is_abslit
)
12277 num
|= XTENSA_PROP_INSN_ABSLIT
;
12279 if (prop_flags
->is_align
)
12281 num
|= XTENSA_PROP_ALIGN
;
12282 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12290 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12291 const frag_flags
*prop_flags_2
)
12293 /* Cannot combine with an end marker. */
12295 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12297 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12299 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12302 if (prop_flags_1
->is_insn
)
12304 /* Properties of the beginning of the frag. */
12305 if (prop_flags_2
->insn
.is_loop_target
)
12307 if (prop_flags_2
->insn
.is_branch_target
)
12309 if (prop_flags_1
->insn
.is_no_density
!=
12310 prop_flags_2
->insn
.is_no_density
)
12312 if (prop_flags_1
->is_no_transform
!=
12313 prop_flags_2
->is_no_transform
)
12315 if (prop_flags_1
->insn
.is_no_reorder
!=
12316 prop_flags_2
->insn
.is_no_reorder
)
12318 if (prop_flags_1
->insn
.is_abslit
!=
12319 prop_flags_2
->insn
.is_abslit
)
12323 if (prop_flags_1
->is_align
)
12331 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12334 unsigned align_bits
;
12336 if (!xt_block
->flags
.is_align
)
12337 return xt_block
->size
;
12339 end_addr
= xt_block
->offset
+ xt_block
->size
;
12340 align_bits
= xt_block
->flags
.alignment
;
12341 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12342 return end_addr
- xt_block
->offset
;
12347 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12348 const xtensa_block_info
*xt_block_2
)
12350 if (xt_block
->sec
!= xt_block_2
->sec
)
12352 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12353 != xt_block_2
->offset
)
12356 if (xt_block_2
->size
== 0
12357 && (!xt_block_2
->flags
.is_unreachable
12358 || xt_block
->flags
.is_unreachable
))
12360 if (xt_block_2
->flags
.is_align
12361 && xt_block
->flags
.is_align
)
12363 /* Nothing needed. */
12364 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12369 if (xt_block_2
->flags
.is_align
)
12371 /* Push alignment to previous entry. */
12372 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12373 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12378 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12379 &xt_block_2
->flags
))
12382 xt_block
->size
+= xt_block_2
->size
;
12384 if (xt_block_2
->flags
.is_align
)
12386 xt_block
->flags
.is_align
= TRUE
;
12387 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12395 add_xt_prop_frags (segT sec
,
12396 xtensa_block_info
**xt_block
,
12397 frag_flags_fn property_function
)
12401 /* Build it if needed. */
12402 while (*xt_block
!= NULL
)
12404 xt_block
= &(*xt_block
)->next
;
12406 /* We are either at NULL at the beginning or at the end. */
12408 /* Walk through the frags. */
12409 if (seg_info (sec
)->frchainP
)
12411 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12412 fragP
= fragP
->fr_next
)
12414 xtensa_block_info tmp_block
;
12415 tmp_block
.sec
= sec
;
12416 tmp_block
.offset
= fragP
->fr_address
;
12417 tmp_block
.size
= fragP
->fr_fix
;
12418 tmp_block
.next
= NULL
;
12419 property_function (fragP
, &tmp_block
.flags
);
12421 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12422 /* && fragP->fr_fix != 0) */
12424 if ((*xt_block
) == NULL
12425 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12427 xtensa_block_info
*new_block
;
12428 if ((*xt_block
) != NULL
)
12429 xt_block
= &(*xt_block
)->next
;
12430 new_block
= XNEW (xtensa_block_info
);
12431 *new_block
= tmp_block
;
12432 *xt_block
= new_block
;
12440 /* op_placement_info_table */
12442 /* op_placement_info makes it easier to determine which
12443 ops can go in which slots. */
12446 init_op_placement_info_table (void)
12448 xtensa_isa isa
= xtensa_default_isa
;
12449 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12450 xtensa_opcode opcode
;
12453 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12455 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12456 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12458 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12460 op_placement_info
*opi
= &op_placement_table
[opcode
];
12461 /* FIXME: Make tinsn allocation dynamic. */
12462 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12463 as_fatal (_("too many operands in instruction"));
12464 opi
->narrowest
= XTENSA_UNDEFINED
;
12465 opi
->narrowest_size
= 0x7F;
12466 opi
->narrowest_slot
= 0;
12468 opi
->num_formats
= 0;
12470 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12472 opi
->slots
[fmt
] = 0;
12473 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12475 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12477 int fmt_length
= xtensa_format_length (isa
, fmt
);
12479 set_bit (fmt
, opi
->formats
);
12480 set_bit (slot
, opi
->slots
[fmt
]);
12481 if (fmt_length
< opi
->narrowest_size
12482 || (fmt_length
== opi
->narrowest_size
12483 && (xtensa_format_num_slots (isa
, fmt
)
12484 < xtensa_format_num_slots (isa
,
12487 opi
->narrowest
= fmt
;
12488 opi
->narrowest_size
= fmt_length
;
12489 opi
->narrowest_slot
= slot
;
12494 opi
->num_formats
++;
12497 xtensa_insnbuf_free (isa
, ibuf
);
12502 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12504 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12508 /* If the opcode is available in a single slot format, return its size. */
12511 xg_get_single_size (xtensa_opcode opcode
)
12513 return op_placement_table
[opcode
].narrowest_size
;
12517 static xtensa_format
12518 xg_get_single_format (xtensa_opcode opcode
)
12520 return op_placement_table
[opcode
].narrowest
;
12525 xg_get_single_slot (xtensa_opcode opcode
)
12527 return op_placement_table
[opcode
].narrowest_slot
;
12531 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12534 istack_init (IStack
*stack
)
12541 istack_empty (IStack
*stack
)
12543 return (stack
->ninsn
== 0);
12548 istack_full (IStack
*stack
)
12550 return (stack
->ninsn
== MAX_ISTACK
);
12554 /* Return a pointer to the top IStack entry.
12555 It is an error to call this if istack_empty () is TRUE. */
12558 istack_top (IStack
*stack
)
12560 int rec
= stack
->ninsn
- 1;
12561 gas_assert (!istack_empty (stack
));
12562 return &stack
->insn
[rec
];
12566 /* Add a new TInsn to an IStack.
12567 It is an error to call this if istack_full () is TRUE. */
12570 istack_push (IStack
*stack
, TInsn
*insn
)
12572 int rec
= stack
->ninsn
;
12573 gas_assert (!istack_full (stack
));
12574 stack
->insn
[rec
] = *insn
;
12579 /* Clear space for the next TInsn on the IStack and return a pointer
12580 to it. It is an error to call this if istack_full () is TRUE. */
12583 istack_push_space (IStack
*stack
)
12585 int rec
= stack
->ninsn
;
12587 gas_assert (!istack_full (stack
));
12588 insn
= &stack
->insn
[rec
];
12595 /* Remove the last pushed instruction. It is an error to call this if
12596 istack_empty () returns TRUE. */
12599 istack_pop (IStack
*stack
)
12601 int rec
= stack
->ninsn
- 1;
12602 gas_assert (!istack_empty (stack
));
12604 tinsn_init (&stack
->insn
[rec
]);
12608 /* TInsn functions. */
12611 tinsn_init (TInsn
*dst
)
12613 memset (dst
, 0, sizeof (TInsn
));
12617 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12620 tinsn_has_symbolic_operands (const TInsn
*insn
)
12623 int n
= insn
->ntok
;
12625 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12627 for (i
= 0; i
< n
; ++i
)
12629 switch (insn
->tok
[i
].X_op
)
12643 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12645 xtensa_isa isa
= xtensa_default_isa
;
12647 int n
= insn
->ntok
;
12649 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12651 for (i
= 0; i
< n
; ++i
)
12653 switch (insn
->tok
[i
].X_op
)
12661 /* Errors for these types are caught later. */
12666 /* Symbolic immediates are only allowed on the last immediate
12667 operand. At this time, CONST16 is the only opcode where we
12668 support non-PC-relative relocations. */
12669 if (i
!= get_relaxable_immed (insn
->opcode
)
12670 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12671 && insn
->opcode
!= xtensa_const16_opcode
))
12673 as_bad (_("invalid symbolic operand"));
12682 /* For assembly code with complex expressions (e.g. subtraction),
12683 we have to build them in the literal pool so that
12684 their results are calculated correctly after relaxation.
12685 The relaxation only handles expressions that
12686 boil down to SYMBOL + OFFSET. */
12689 tinsn_has_complex_operands (const TInsn
*insn
)
12692 int n
= insn
->ntok
;
12693 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12694 for (i
= 0; i
< n
; ++i
)
12696 switch (insn
->tok
[i
].X_op
)
12712 /* Encode a TInsn opcode and its constant operands into slotbuf.
12713 Return TRUE if there is a symbol in the immediate field. This
12714 function assumes that:
12715 1) The number of operands are correct.
12716 2) The insn_type is ITYPE_INSN.
12717 3) The opcode can be encoded in the specified format and slot.
12718 4) Operands are either O_constant or O_symbol, and all constants fit. */
12721 tinsn_to_slotbuf (xtensa_format fmt
,
12724 xtensa_insnbuf slotbuf
)
12726 xtensa_isa isa
= xtensa_default_isa
;
12727 xtensa_opcode opcode
= tinsn
->opcode
;
12728 bfd_boolean has_fixup
= FALSE
;
12729 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12732 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12733 if (noperands
!= tinsn
->ntok
)
12734 as_fatal (_("operand number mismatch"));
12736 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12738 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12739 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12743 for (i
= 0; i
< noperands
; i
++)
12745 expressionS
*exp
= &tinsn
->tok
[i
];
12748 const char *file_name
;
12754 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12756 /* The register number has already been checked in
12757 expression_maybe_register, so we don't need to check here. */
12758 opnd_value
= exp
->X_add_number
;
12759 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12760 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12763 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12767 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12769 file_name
= as_where (&line
);
12770 /* It is a constant and we called this function
12771 then we have to try to fit it. */
12772 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12773 exp
->X_add_number
, file_name
, line
);
12786 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12787 into a multi-slot instruction, fill the other slots with NOPs.
12788 Return TRUE if there is a symbol in the immediate field. See also the
12789 assumptions listed for tinsn_to_slotbuf. */
12792 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12794 static xtensa_insnbuf slotbuf
= 0;
12795 static vliw_insn vinsn
;
12796 xtensa_isa isa
= xtensa_default_isa
;
12797 bfd_boolean has_fixup
= FALSE
;
12802 slotbuf
= xtensa_insnbuf_alloc (isa
);
12803 xg_init_vinsn (&vinsn
);
12806 xg_clear_vinsn (&vinsn
);
12808 bundle_tinsn (tinsn
, &vinsn
);
12810 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12812 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12814 /* Only one slot may have a fix-up because the rest contains NOPs. */
12816 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12817 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12824 /* Check the instruction arguments. Return TRUE on failure. */
12827 tinsn_check_arguments (const TInsn
*insn
)
12829 xtensa_isa isa
= xtensa_default_isa
;
12830 xtensa_opcode opcode
= insn
->opcode
;
12831 xtensa_regfile t1_regfile
, t2_regfile
;
12832 int t1_reg
, t2_reg
;
12833 int t1_base_reg
, t1_last_reg
;
12834 int t2_base_reg
, t2_last_reg
;
12835 char t1_inout
, t2_inout
;
12838 if (opcode
== XTENSA_UNDEFINED
)
12840 as_bad (_("invalid opcode"));
12844 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12846 as_bad (_("too few operands"));
12850 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12852 as_bad (_("too many operands"));
12856 /* Check registers. */
12857 for (j
= 0; j
< insn
->ntok
; j
++)
12859 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12862 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12863 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12865 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12867 for (i
= 0; i
< insn
->ntok
; i
++)
12872 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12875 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12877 if (t1_regfile
!= t2_regfile
)
12880 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12881 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12883 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12884 t1_last_reg
= (t1_base_reg
12885 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12887 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12889 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12891 if (t1_reg
!= t2_reg
)
12894 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12896 as_bad (_("multiple writes to the same register"));
12907 /* Load an instruction from its encoded form. */
12910 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12914 xg_init_vinsn (&vinsn
);
12915 vinsn_from_chars (&vinsn
, f
);
12917 *tinsn
= vinsn
.slots
[slot
];
12918 xg_free_vinsn (&vinsn
);
12923 tinsn_from_insnbuf (TInsn
*tinsn
,
12924 xtensa_insnbuf slotbuf
,
12929 xtensa_isa isa
= xtensa_default_isa
;
12931 /* Find the immed. */
12932 tinsn_init (tinsn
);
12933 tinsn
->insn_type
= ITYPE_INSN
;
12934 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12935 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12936 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12937 for (i
= 0; i
< tinsn
->ntok
; i
++)
12939 set_expr_const (&tinsn
->tok
[i
],
12940 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12941 tinsn
->opcode
, i
));
12946 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12949 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12951 xtensa_opcode opcode
= tinsn
->opcode
;
12954 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12956 opnum
= get_relaxable_immed (opcode
);
12957 gas_assert (opnum
>= 0);
12958 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12959 fragP
->tc_frag_data
.slot_symbols
[slot
],
12960 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12962 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12967 get_num_stack_text_bytes (IStack
*istack
)
12970 int text_bytes
= 0;
12972 for (i
= 0; i
< istack
->ninsn
; i
++)
12974 TInsn
*tinsn
= &istack
->insn
[i
];
12975 if (tinsn
->insn_type
== ITYPE_INSN
)
12976 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12983 get_num_stack_literal_bytes (IStack
*istack
)
12988 for (i
= 0; i
< istack
->ninsn
; i
++)
12990 TInsn
*tinsn
= &istack
->insn
[i
];
12991 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12998 /* vliw_insn functions. */
13001 xg_init_vinsn (vliw_insn
*v
)
13004 xtensa_isa isa
= xtensa_default_isa
;
13006 xg_clear_vinsn (v
);
13008 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
13009 if (v
->insnbuf
== NULL
)
13010 as_fatal (_("out of memory"));
13012 for (i
= 0; i
< config_max_slots
; i
++)
13014 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
13015 if (v
->slotbuf
[i
] == NULL
)
13016 as_fatal (_("out of memory"));
13022 xg_clear_vinsn (vliw_insn
*v
)
13026 memset (v
, 0, offsetof (vliw_insn
, slots
)
13027 + sizeof(TInsn
) * config_max_slots
);
13029 v
->format
= XTENSA_UNDEFINED
;
13031 v
->inside_bundle
= FALSE
;
13033 if (xt_saved_debug_type
!= DEBUG_NONE
)
13034 debug_type
= xt_saved_debug_type
;
13036 for (i
= 0; i
< config_max_slots
; i
++)
13037 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
13042 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
13045 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
13046 dst
->insnbuf
= src
->insnbuf
;
13047 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
13052 vinsn_has_specific_opcodes (vliw_insn
*v
)
13056 for (i
= 0; i
< v
->num_slots
; i
++)
13058 if (v
->slots
[i
].is_specific_opcode
)
13066 xg_free_vinsn (vliw_insn
*v
)
13069 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
13070 for (i
= 0; i
< config_max_slots
; i
++)
13071 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
13075 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
13076 operands. See also the assumptions listed for tinsn_to_slotbuf. */
13079 vinsn_to_insnbuf (vliw_insn
*vinsn
,
13082 bfd_boolean record_fixup
)
13084 xtensa_isa isa
= xtensa_default_isa
;
13085 xtensa_format fmt
= vinsn
->format
;
13086 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
13088 bfd_boolean has_fixup
= FALSE
;
13090 xtensa_format_encode (isa
, fmt
, insnbuf
);
13092 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
13094 TInsn
*tinsn
= &vinsn
->slots
[slot
];
13095 expressionS
*extra_arg
= &tinsn
->extra_arg
;
13096 bfd_boolean tinsn_has_fixup
=
13097 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
13098 vinsn
->slotbuf
[slot
]);
13100 xtensa_format_set_slot (isa
, fmt
, slot
,
13101 insnbuf
, vinsn
->slotbuf
[slot
]);
13102 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
13104 if (vinsn
->num_slots
!= 1)
13105 as_bad (_("TLS relocation not allowed in FLIX bundle"));
13106 else if (record_fixup
)
13107 /* Instructions that generate TLS relocations should always be
13108 relaxed in the front-end. If "record_fixup" is set, then this
13109 function is being called during back-end relaxation, so flag
13110 the unexpected behavior as an error. */
13111 as_bad (_("unexpected TLS relocation"));
13113 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
13114 xtensa_format_length (isa
, fmt
),
13115 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
13116 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
13118 if (tinsn_has_fixup
)
13121 xtensa_opcode opcode
= tinsn
->opcode
;
13122 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
13125 for (i
= 0; i
< noperands
; i
++)
13127 expressionS
* exp
= &tinsn
->tok
[i
];
13133 if (get_relaxable_immed (opcode
) == i
)
13135 /* Add a fix record for the instruction, except if this
13136 function is being called prior to relaxation, i.e.,
13137 if record_fixup is false, and the instruction might
13138 be relaxed later. */
13140 || tinsn
->is_specific_opcode
13141 || !xg_is_relaxable_insn (tinsn
, 0))
13143 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
13144 frag_offset
- fragP
->fr_literal
);
13148 if (exp
->X_op
!= O_symbol
)
13149 as_bad (_("invalid operand"));
13150 tinsn
->symbol
= exp
->X_add_symbol
;
13151 tinsn
->offset
= exp
->X_add_number
;
13155 as_bad (_("symbolic operand not allowed"));
13163 as_bad (_("expression too complex"));
13175 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
13177 static xtensa_insnbuf insnbuf
= NULL
;
13178 static xtensa_insnbuf slotbuf
= NULL
;
13181 xtensa_isa isa
= xtensa_default_isa
;
13185 insnbuf
= xtensa_insnbuf_alloc (isa
);
13186 slotbuf
= xtensa_insnbuf_alloc (isa
);
13189 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13190 fmt
= xtensa_format_decode (isa
, insnbuf
);
13191 if (fmt
== XTENSA_UNDEFINED
)
13192 as_fatal (_("cannot decode instruction format"));
13193 vinsn
->format
= fmt
;
13194 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13196 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13198 TInsn
*tinsn
= &vinsn
->slots
[i
];
13199 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13200 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13205 /* Expression utilities. */
13207 /* Return TRUE if the expression is an integer constant. */
13210 expr_is_const (const expressionS
*s
)
13212 return (s
->X_op
== O_constant
);
13216 /* Get the expression constant.
13217 Calling this is illegal if expr_is_const () returns TRUE. */
13220 get_expr_const (const expressionS
*s
)
13222 gas_assert (expr_is_const (s
));
13223 return s
->X_add_number
;
13227 /* Set the expression to a constant value. */
13230 set_expr_const (expressionS
*s
, offsetT val
)
13232 s
->X_op
= O_constant
;
13233 s
->X_add_number
= val
;
13234 s
->X_add_symbol
= NULL
;
13235 s
->X_op_symbol
= NULL
;
13240 expr_is_register (const expressionS
*s
)
13242 return (s
->X_op
== O_register
);
13246 /* Get the expression constant.
13247 Calling this is illegal if expr_is_const () returns TRUE. */
13250 get_expr_register (const expressionS
*s
)
13252 gas_assert (expr_is_register (s
));
13253 return s
->X_add_number
;
13257 /* Set the expression to a symbol + constant offset. */
13260 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13262 s
->X_op
= O_symbol
;
13263 s
->X_add_symbol
= sym
;
13264 s
->X_op_symbol
= NULL
; /* unused */
13265 s
->X_add_number
= offset
;
13269 /* Return TRUE if the two expressions are equal. */
13272 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13274 if (s1
->X_op
!= s2
->X_op
)
13276 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13278 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13280 if (s1
->X_add_number
!= s2
->X_add_number
)
13287 copy_expr (expressionS
*dst
, const expressionS
*src
)
13289 memcpy (dst
, src
, sizeof (expressionS
));
13293 /* Support for the "--rename-section" option. */
13295 struct rename_section_struct
13297 const char *old_name
;
13299 struct rename_section_struct
*next
;
13302 static struct rename_section_struct
*section_rename
;
13305 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13306 entries to the section_rename list. Note: Specifying multiple
13307 renamings separated by colons is not documented and is retained only
13308 for backward compatibility. */
13311 build_section_rename (const char *arg
)
13313 struct rename_section_struct
*r
;
13314 char *this_arg
= NULL
;
13315 char *next_arg
= NULL
;
13317 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13319 char *old_name
, *new_name
;
13323 next_arg
= strchr (this_arg
, ':');
13331 old_name
= this_arg
;
13332 new_name
= strchr (this_arg
, '=');
13334 if (*old_name
== '\0')
13336 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13339 if (!new_name
|| new_name
[1] == '\0')
13341 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13348 /* Check for invalid section renaming. */
13349 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13351 if (strcmp (r
->old_name
, old_name
) == 0)
13352 as_bad (_("section %s renamed multiple times"), old_name
);
13353 if (strcmp (r
->new_name
, new_name
) == 0)
13354 as_bad (_("multiple sections remapped to output section %s"),
13359 r
= XNEW (struct rename_section_struct
);
13360 r
->old_name
= xstrdup (old_name
);
13361 r
->new_name
= xstrdup (new_name
);
13362 r
->next
= section_rename
;
13363 section_rename
= r
;
13369 xtensa_section_rename (const char *name
)
13371 struct rename_section_struct
*r
= section_rename
;
13373 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13375 if (strcmp (r
->old_name
, name
) == 0)
13376 return r
->new_name
;
13379 return (char *) name
;