1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
368 directive_literal_prefix
,
370 directive_absolute_literals
,
371 directive_last_directive
377 bfd_boolean can_be_negated
;
380 const directive_infoS directive_info
[] =
383 { "literal", FALSE
},
385 { "transform", TRUE
},
386 { "freeregs", FALSE
},
387 { "longcalls", TRUE
},
388 { "literal_prefix", FALSE
},
389 { "schedule", TRUE
},
390 { "absolute-literals", TRUE
}
393 bfd_boolean directive_state
[] =
397 #if !XCHAL_HAVE_DENSITY
402 TRUE
, /* transform */
403 FALSE
, /* freeregs */
404 FALSE
, /* longcalls */
405 FALSE
, /* literal_prefix */
407 #if XSHAL_USE_ABSOLUTE_LITERALS
408 TRUE
/* absolute_literals */
410 FALSE
/* absolute_literals */
415 /* Directive functions. */
417 static void xtensa_begin_directive (int);
418 static void xtensa_end_directive (int);
419 static void xtensa_literal_prefix (char const *, int);
420 static void xtensa_literal_position (int);
421 static void xtensa_literal_pseudo (int);
422 static void xtensa_frequency_pseudo (int);
423 static void xtensa_elf_cons (int);
425 /* Parsing and Idiom Translation. */
427 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
429 /* Various Other Internal Functions. */
431 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
432 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
433 static void xtensa_mark_literal_pool_location (void);
434 static addressT
get_expanded_loop_offset (xtensa_opcode
);
435 static fragS
*get_literal_pool_location (segT
);
436 static void set_literal_pool_location (segT
, fragS
*);
437 static void xtensa_set_frag_assembly_state (fragS
*);
438 static void finish_vinsn (vliw_insn
*);
439 static bfd_boolean
emit_single_op (TInsn
*);
440 static int total_frag_text_expansion (fragS
*);
442 /* Alignment Functions. */
444 static int get_text_align_power (unsigned);
445 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
446 static int branch_align_power (segT
);
448 /* Helpers for xtensa_relax_frag(). */
450 static long relax_frag_add_nop (fragS
*);
452 /* Accessors for additional per-subsegment information. */
454 static unsigned get_last_insn_flags (segT
, subsegT
);
455 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
456 static float get_subseg_total_freq (segT
, subsegT
);
457 static float get_subseg_target_freq (segT
, subsegT
);
458 static void set_subseg_freq (segT
, subsegT
, float, float);
460 /* Segment list functions. */
462 static void xtensa_move_literals (void);
463 static void xtensa_reorder_segments (void);
464 static void xtensa_switch_to_literal_fragment (emit_state
*);
465 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
466 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
467 static void xtensa_restore_emit_state (emit_state
*);
468 static void cache_literal_section
469 (seg_list
*, const char *, segT
*, bfd_boolean
);
471 /* Import from elf32-xtensa.c in BFD library. */
473 extern char *xtensa_get_property_section_name (asection
*, const char *);
475 /* op_placement_info functions. */
477 static void init_op_placement_info_table (void);
478 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
479 static int xg_get_single_size (xtensa_opcode
);
480 static xtensa_format
xg_get_single_format (xtensa_opcode
);
481 static int xg_get_single_slot (xtensa_opcode
);
483 /* TInsn and IStack functions. */
485 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
486 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
487 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
488 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
489 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
490 static void tinsn_from_chars (TInsn
*, char *, int);
491 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
492 static int get_num_stack_text_bytes (IStack
*);
493 static int get_num_stack_literal_bytes (IStack
*);
495 /* vliw_insn functions. */
497 static void xg_init_vinsn (vliw_insn
*);
498 static void xg_clear_vinsn (vliw_insn
*);
499 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
500 static void xg_free_vinsn (vliw_insn
*);
501 static bfd_boolean vinsn_to_insnbuf
502 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
503 static void vinsn_from_chars (vliw_insn
*, char *);
505 /* Expression Utilities. */
507 bfd_boolean
expr_is_const (const expressionS
*);
508 offsetT
get_expr_const (const expressionS
*);
509 void set_expr_const (expressionS
*, offsetT
);
510 bfd_boolean
expr_is_register (const expressionS
*);
511 offsetT
get_expr_register (const expressionS
*);
512 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
513 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
514 static void copy_expr (expressionS
*, const expressionS
*);
516 /* Section renaming. */
518 static void build_section_rename (const char *);
521 /* ISA imported from bfd. */
522 extern xtensa_isa xtensa_default_isa
;
524 extern int target_big_endian
;
526 static xtensa_opcode xtensa_addi_opcode
;
527 static xtensa_opcode xtensa_addmi_opcode
;
528 static xtensa_opcode xtensa_call0_opcode
;
529 static xtensa_opcode xtensa_call4_opcode
;
530 static xtensa_opcode xtensa_call8_opcode
;
531 static xtensa_opcode xtensa_call12_opcode
;
532 static xtensa_opcode xtensa_callx0_opcode
;
533 static xtensa_opcode xtensa_callx4_opcode
;
534 static xtensa_opcode xtensa_callx8_opcode
;
535 static xtensa_opcode xtensa_callx12_opcode
;
536 static xtensa_opcode xtensa_const16_opcode
;
537 static xtensa_opcode xtensa_entry_opcode
;
538 static xtensa_opcode xtensa_movi_opcode
;
539 static xtensa_opcode xtensa_movi_n_opcode
;
540 static xtensa_opcode xtensa_isync_opcode
;
541 static xtensa_opcode xtensa_jx_opcode
;
542 static xtensa_opcode xtensa_l32r_opcode
;
543 static xtensa_opcode xtensa_loop_opcode
;
544 static xtensa_opcode xtensa_loopnez_opcode
;
545 static xtensa_opcode xtensa_loopgtz_opcode
;
546 static xtensa_opcode xtensa_nop_opcode
;
547 static xtensa_opcode xtensa_nop_n_opcode
;
548 static xtensa_opcode xtensa_or_opcode
;
549 static xtensa_opcode xtensa_ret_opcode
;
550 static xtensa_opcode xtensa_ret_n_opcode
;
551 static xtensa_opcode xtensa_retw_opcode
;
552 static xtensa_opcode xtensa_retw_n_opcode
;
553 static xtensa_opcode xtensa_rsr_lcount_opcode
;
554 static xtensa_opcode xtensa_waiti_opcode
;
557 /* Command-line Options. */
559 bfd_boolean use_literal_section
= TRUE
;
560 static bfd_boolean align_targets
= TRUE
;
561 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
562 static bfd_boolean has_a0_b_retw
= FALSE
;
563 static bfd_boolean workaround_a0_b_retw
= FALSE
;
564 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
565 static bfd_boolean workaround_short_loop
= FALSE
;
566 static bfd_boolean maybe_has_short_loop
= FALSE
;
567 static bfd_boolean workaround_close_loop_end
= FALSE
;
568 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
569 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
571 /* When workaround_short_loops is TRUE, all loops with early exits must
572 have at least 3 instructions. workaround_all_short_loops is a modifier
573 to the workaround_short_loop flag. In addition to the
574 workaround_short_loop actions, all straightline loopgtz and loopnez
575 must have at least 3 instructions. */
577 static bfd_boolean workaround_all_short_loops
= FALSE
;
581 xtensa_setup_hw_workarounds (int earliest
, int latest
)
583 if (earliest
> latest
)
584 as_fatal (_("illegal range of target hardware versions"));
586 /* Enable all workarounds for pre-T1050.0 hardware. */
587 if (earliest
< 105000 || latest
< 105000)
589 workaround_a0_b_retw
|= TRUE
;
590 workaround_b_j_loop_end
|= TRUE
;
591 workaround_short_loop
|= TRUE
;
592 workaround_close_loop_end
|= TRUE
;
593 workaround_all_short_loops
|= TRUE
;
594 enforce_three_byte_loop_align
= TRUE
;
601 option_density
= OPTION_MD_BASE
,
608 option_no_link_relax
,
616 option_text_section_literals
,
617 option_no_text_section_literals
,
619 option_absolute_literals
,
620 option_no_absolute_literals
,
622 option_align_targets
,
623 option_no_align_targets
,
625 option_warn_unaligned_targets
,
630 option_workaround_a0_b_retw
,
631 option_no_workaround_a0_b_retw
,
633 option_workaround_b_j_loop_end
,
634 option_no_workaround_b_j_loop_end
,
636 option_workaround_short_loop
,
637 option_no_workaround_short_loop
,
639 option_workaround_all_short_loops
,
640 option_no_workaround_all_short_loops
,
642 option_workaround_close_loop_end
,
643 option_no_workaround_close_loop_end
,
645 option_no_workarounds
,
647 option_rename_section_name
,
650 option_prefer_const16
,
652 option_target_hardware
655 const char *md_shortopts
= "";
657 struct option md_longopts
[] =
659 { "density", no_argument
, NULL
, option_density
},
660 { "no-density", no_argument
, NULL
, option_no_density
},
662 /* Both "relax" and "generics" are deprecated and treated as equivalent
663 to the "transform" option. */
664 { "relax", no_argument
, NULL
, option_relax
},
665 { "no-relax", no_argument
, NULL
, option_no_relax
},
666 { "generics", no_argument
, NULL
, option_generics
},
667 { "no-generics", no_argument
, NULL
, option_no_generics
},
669 { "transform", no_argument
, NULL
, option_transform
},
670 { "no-transform", no_argument
, NULL
, option_no_transform
},
671 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
672 { "no-text-section-literals", no_argument
, NULL
,
673 option_no_text_section_literals
},
674 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
675 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
676 /* This option was changed from -align-target to -target-align
677 because it conflicted with the "-al" option. */
678 { "target-align", no_argument
, NULL
, option_align_targets
},
679 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
680 { "warn-unaligned-targets", no_argument
, NULL
,
681 option_warn_unaligned_targets
},
682 { "longcalls", no_argument
, NULL
, option_longcalls
},
683 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
685 { "no-workaround-a0-b-retw", no_argument
, NULL
,
686 option_no_workaround_a0_b_retw
},
687 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
689 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
690 option_no_workaround_b_j_loop_end
},
691 { "workaround-b-j-loop-end", no_argument
, NULL
,
692 option_workaround_b_j_loop_end
},
694 { "no-workaround-short-loops", no_argument
, NULL
,
695 option_no_workaround_short_loop
},
696 { "workaround-short-loops", no_argument
, NULL
,
697 option_workaround_short_loop
},
699 { "no-workaround-all-short-loops", no_argument
, NULL
,
700 option_no_workaround_all_short_loops
},
701 { "workaround-all-short-loop", no_argument
, NULL
,
702 option_workaround_all_short_loops
},
704 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
705 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
707 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
709 { "no-workaround-close-loop-end", no_argument
, NULL
,
710 option_no_workaround_close_loop_end
},
711 { "workaround-close-loop-end", no_argument
, NULL
,
712 option_workaround_close_loop_end
},
714 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
716 { "link-relax", no_argument
, NULL
, option_link_relax
},
717 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
719 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
721 { NULL
, no_argument
, NULL
, 0 }
724 size_t md_longopts_size
= sizeof md_longopts
;
728 md_parse_option (int c
, char *arg
)
733 as_warn (_("--density option is ignored"));
735 case option_no_density
:
736 as_warn (_("--no-density option is ignored"));
738 case option_link_relax
:
741 case option_no_link_relax
:
744 case option_generics
:
745 as_warn (_("--generics is deprecated; use --transform instead"));
746 return md_parse_option (option_transform
, arg
);
747 case option_no_generics
:
748 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
749 return md_parse_option (option_no_transform
, arg
);
751 as_warn (_("--relax is deprecated; use --transform instead"));
752 return md_parse_option (option_transform
, arg
);
753 case option_no_relax
:
754 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform
, arg
);
756 case option_longcalls
:
757 directive_state
[directive_longcalls
] = TRUE
;
759 case option_no_longcalls
:
760 directive_state
[directive_longcalls
] = FALSE
;
762 case option_text_section_literals
:
763 use_literal_section
= FALSE
;
765 case option_no_text_section_literals
:
766 use_literal_section
= TRUE
;
768 case option_absolute_literals
:
769 if (!absolute_literals_supported
)
771 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
774 directive_state
[directive_absolute_literals
] = TRUE
;
776 case option_no_absolute_literals
:
777 directive_state
[directive_absolute_literals
] = FALSE
;
780 case option_workaround_a0_b_retw
:
781 workaround_a0_b_retw
= TRUE
;
783 case option_no_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= FALSE
;
786 case option_workaround_b_j_loop_end
:
787 workaround_b_j_loop_end
= TRUE
;
789 case option_no_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= FALSE
;
793 case option_workaround_short_loop
:
794 workaround_short_loop
= TRUE
;
796 case option_no_workaround_short_loop
:
797 workaround_short_loop
= FALSE
;
800 case option_workaround_all_short_loops
:
801 workaround_all_short_loops
= TRUE
;
803 case option_no_workaround_all_short_loops
:
804 workaround_all_short_loops
= FALSE
;
807 case option_workaround_close_loop_end
:
808 workaround_close_loop_end
= TRUE
;
810 case option_no_workaround_close_loop_end
:
811 workaround_close_loop_end
= FALSE
;
814 case option_no_workarounds
:
815 workaround_a0_b_retw
= FALSE
;
816 workaround_b_j_loop_end
= FALSE
;
817 workaround_short_loop
= FALSE
;
818 workaround_all_short_loops
= FALSE
;
819 workaround_close_loop_end
= FALSE
;
822 case option_align_targets
:
823 align_targets
= TRUE
;
825 case option_no_align_targets
:
826 align_targets
= FALSE
;
829 case option_warn_unaligned_targets
:
830 warn_unaligned_branch_targets
= TRUE
;
833 case option_rename_section_name
:
834 build_section_rename (arg
);
838 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
839 should be emitted or not. FIXME: Not implemented. */
842 case option_prefer_l32r
:
844 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
848 case option_prefer_const16
:
850 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
854 case option_target_hardware
:
856 int earliest
, latest
= 0;
857 if (*arg
== 0 || *arg
== '-')
858 as_fatal (_("invalid target hardware version"));
860 earliest
= strtol (arg
, &arg
, 0);
864 else if (*arg
== '-')
867 as_fatal (_("invalid target hardware version"));
868 latest
= strtol (arg
, &arg
, 0);
871 as_fatal (_("invalid target hardware version"));
873 xtensa_setup_hw_workarounds (earliest
, latest
);
877 case option_transform
:
878 /* This option has no affect other than to use the defaults,
879 which are already set. */
882 case option_no_transform
:
883 /* This option turns off all transformations of any kind.
884 However, because we want to preserve the state of other
885 directives, we only change its own field. Thus, before
886 you perform any transformation, always check if transform
887 is available. If you use the functions we provide for this
888 purpose, you will be ok. */
889 directive_state
[directive_transform
] = FALSE
;
899 md_show_usage (FILE *stream
)
903 --[no-]text-section-literals\n\
904 [Do not] put literals in the text section\n\
905 --[no-]absolute-literals\n\
906 [Do not] default to use non-PC-relative literals\n\
907 --[no-]target-align [Do not] try to align branch targets\n\
908 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
909 --[no-]transform [Do not] transform instructions\n\
910 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
914 /* Functions related to the list of current label symbols. */
917 xtensa_add_insn_label (symbolS
*sym
)
921 if (!free_insn_labels
)
922 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
925 l
= free_insn_labels
;
926 free_insn_labels
= l
->next
;
930 l
->next
= insn_labels
;
936 xtensa_clear_insn_labels (void)
940 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
947 /* The "loops_ok" argument is provided to allow ignoring labels that
948 define loop ends. This fixes a bug where the NOPs to align a
949 loop opcode were included in a previous zero-cost loop:
968 This argument is used to prevent moving the NOP to before the
969 loop-end label, which is what you want in this special case. */
972 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
976 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
978 symbolS
*lit_sym
= lit
->sym
;
979 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
981 S_SET_VALUE (lit_sym
, new_offset
);
982 symbol_set_frag (lit_sym
, new_frag
);
988 /* Directive data and functions. */
990 typedef struct state_stackS_struct
992 directiveE directive
;
994 bfd_boolean old_state
;
998 struct state_stackS_struct
*prev
;
1001 state_stackS
*directive_state_stack
;
1003 const pseudo_typeS md_pseudo_table
[] =
1005 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1006 { "literal_position", xtensa_literal_position
, 0 },
1007 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1008 { "long", xtensa_elf_cons
, 4 },
1009 { "word", xtensa_elf_cons
, 4 },
1010 { "short", xtensa_elf_cons
, 2 },
1011 { "begin", xtensa_begin_directive
, 0 },
1012 { "end", xtensa_end_directive
, 0 },
1013 { "literal", xtensa_literal_pseudo
, 0 },
1014 { "frequency", xtensa_frequency_pseudo
, 0 },
1020 use_transform (void)
1022 /* After md_end, you should be checking frag by frag, rather
1023 than state directives. */
1024 assert (!past_xtensa_end
);
1025 return directive_state
[directive_transform
];
1030 do_align_targets (void)
1032 /* Do not use this function after md_end; just look at align_targets
1033 instead. There is no target-align directive, so alignment is either
1034 enabled for all frags or not done at all. */
1035 assert (!past_xtensa_end
);
1036 return align_targets
&& use_transform ();
1041 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1045 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1047 as_where (&file
, &line
);
1049 stack
->directive
= directive
;
1050 stack
->negated
= negated
;
1051 stack
->old_state
= directive_state
[directive
];
1054 stack
->datum
= datum
;
1055 stack
->prev
= directive_state_stack
;
1056 directive_state_stack
= stack
;
1058 directive_state
[directive
] = !negated
;
1063 directive_pop (directiveE
*directive
,
1064 bfd_boolean
*negated
,
1069 state_stackS
*top
= directive_state_stack
;
1071 if (!directive_state_stack
)
1073 as_bad (_("unmatched end directive"));
1074 *directive
= directive_none
;
1078 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1079 *directive
= top
->directive
;
1080 *negated
= top
->negated
;
1083 *datum
= top
->datum
;
1084 directive_state_stack
= top
->prev
;
1090 directive_balance (void)
1092 while (directive_state_stack
)
1094 directiveE directive
;
1095 bfd_boolean negated
;
1100 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1101 as_warn_where ((char *) file
, line
,
1102 _(".begin directive with no matching .end directive"));
1108 inside_directive (directiveE dir
)
1110 state_stackS
*top
= directive_state_stack
;
1112 while (top
&& top
->directive
!= dir
)
1115 return (top
!= NULL
);
1120 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1124 char *directive_string
;
1126 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1131 input_line_pointer
+= 3;
1134 len
= strspn (input_line_pointer
,
1135 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1137 /* This code is a hack to make .begin [no-][generics|relax] exactly
1138 equivalent to .begin [no-]transform. We should remove it when
1139 we stop accepting those options. */
1141 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1143 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1144 directive_string
= "transform";
1146 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1148 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1152 directive_string
= input_line_pointer
;
1154 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1156 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1158 input_line_pointer
+= len
;
1159 *directive
= (directiveE
) i
;
1160 if (*negated
&& !directive_info
[i
].can_be_negated
)
1161 as_bad (_("directive %s cannot be negated"),
1162 directive_info
[i
].name
);
1167 as_bad (_("unknown directive"));
1168 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1173 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1175 directiveE directive
;
1176 bfd_boolean negated
;
1181 get_directive (&directive
, &negated
);
1182 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1184 discard_rest_of_line ();
1188 if (cur_vinsn
.inside_bundle
)
1189 as_bad (_("directives are not valid inside bundles"));
1193 case directive_literal
:
1194 if (!inside_directive (directive_literal
))
1196 /* Previous labels go with whatever follows this directive, not with
1197 the literal, so save them now. */
1198 saved_insn_labels
= insn_labels
;
1201 as_warn (_(".begin literal is deprecated; use .literal instead"));
1202 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1203 xtensa_switch_to_literal_fragment (state
);
1204 directive_push (directive_literal
, negated
, state
);
1207 case directive_literal_prefix
:
1208 /* Have to flush pending output because a movi relaxed to an l32r
1209 might produce a literal. */
1210 md_flush_pending_output ();
1211 /* Check to see if the current fragment is a literal
1212 fragment. If it is, then this operation is not allowed. */
1213 if (generating_literals
)
1215 as_bad (_("cannot set literal_prefix inside literal fragment"));
1219 /* Allocate the literal state for this section and push
1220 onto the directive stack. */
1221 ls
= xmalloc (sizeof (lit_state
));
1224 *ls
= default_lit_sections
;
1226 directive_push (directive_literal_prefix
, negated
, ls
);
1228 /* Parse the new prefix from the input_line_pointer. */
1230 len
= strspn (input_line_pointer
,
1231 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1232 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1234 /* Process the new prefix. */
1235 xtensa_literal_prefix (input_line_pointer
, len
);
1237 /* Skip the name in the input line. */
1238 input_line_pointer
+= len
;
1241 case directive_freeregs
:
1242 /* This information is currently unused, but we'll accept the statement
1243 and just discard the rest of the line. This won't check the syntax,
1244 but it will accept every correct freeregs directive. */
1245 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1246 directive_push (directive_freeregs
, negated
, 0);
1249 case directive_schedule
:
1250 md_flush_pending_output ();
1251 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1252 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1253 directive_push (directive_schedule
, negated
, 0);
1254 xtensa_set_frag_assembly_state (frag_now
);
1257 case directive_density
:
1258 as_warn (_(".begin [no-]density is ignored"));
1261 case directive_absolute_literals
:
1262 md_flush_pending_output ();
1263 if (!absolute_literals_supported
&& !negated
)
1265 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1268 xtensa_set_frag_assembly_state (frag_now
);
1269 directive_push (directive
, negated
, 0);
1273 md_flush_pending_output ();
1274 xtensa_set_frag_assembly_state (frag_now
);
1275 directive_push (directive
, negated
, 0);
1279 demand_empty_rest_of_line ();
1284 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1286 directiveE begin_directive
, end_directive
;
1287 bfd_boolean begin_negated
, end_negated
;
1291 emit_state
**state_ptr
;
1294 if (cur_vinsn
.inside_bundle
)
1295 as_bad (_("directives are not valid inside bundles"));
1297 get_directive (&end_directive
, &end_negated
);
1299 md_flush_pending_output ();
1301 switch (end_directive
)
1303 case (directiveE
) XTENSA_UNDEFINED
:
1304 discard_rest_of_line ();
1307 case directive_density
:
1308 as_warn (_(".end [no-]density is ignored"));
1309 demand_empty_rest_of_line ();
1312 case directive_absolute_literals
:
1313 if (!absolute_literals_supported
&& !end_negated
)
1315 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1316 demand_empty_rest_of_line ();
1325 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1326 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1327 (const void **) state_ptr
);
1329 if (begin_directive
!= directive_none
)
1331 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1333 as_bad (_("does not match begin %s%s at %s:%d"),
1334 begin_negated
? "no-" : "",
1335 directive_info
[begin_directive
].name
, file
, line
);
1339 switch (end_directive
)
1341 case directive_literal
:
1342 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1343 xtensa_restore_emit_state (state
);
1344 xtensa_set_frag_assembly_state (frag_now
);
1346 if (!inside_directive (directive_literal
))
1348 /* Restore the list of current labels. */
1349 xtensa_clear_insn_labels ();
1350 insn_labels
= saved_insn_labels
;
1354 case directive_literal_prefix
:
1355 /* Restore the default collection sections from saved state. */
1356 s
= (lit_state
*) state
;
1359 default_lit_sections
= *s
;
1361 /* free the state storage */
1365 case directive_schedule
:
1366 case directive_freeregs
:
1370 xtensa_set_frag_assembly_state (frag_now
);
1376 demand_empty_rest_of_line ();
1380 /* Place an aligned literal fragment at the current location. */
1383 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1385 md_flush_pending_output ();
1387 if (inside_directive (directive_literal
))
1388 as_warn (_(".literal_position inside literal directive; ignoring"));
1389 xtensa_mark_literal_pool_location ();
1391 demand_empty_rest_of_line ();
1392 xtensa_clear_insn_labels ();
1396 /* Support .literal label, expr, ... */
1399 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1402 char *p
, *base_name
;
1406 if (inside_directive (directive_literal
))
1408 as_bad (_(".literal not allowed inside .begin literal region"));
1409 ignore_rest_of_line ();
1413 md_flush_pending_output ();
1415 /* Previous labels go with whatever follows this directive, not with
1416 the literal, so save them now. */
1417 saved_insn_labels
= insn_labels
;
1420 /* If we are using text-section literals, then this is the right value... */
1423 base_name
= input_line_pointer
;
1425 xtensa_switch_to_literal_fragment (&state
);
1427 /* ...but if we aren't using text-section-literals, then we
1428 need to put them in the section we just switched to. */
1429 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1432 /* All literals are aligned to four-byte boundaries. */
1433 frag_align (2, 0, 0);
1434 record_alignment (now_seg
, 2);
1436 c
= get_symbol_end ();
1437 /* Just after name is now '\0'. */
1438 p
= input_line_pointer
;
1442 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1444 as_bad (_("expected comma or colon after symbol name; "
1445 "rest of line ignored"));
1446 ignore_rest_of_line ();
1447 xtensa_restore_emit_state (&state
);
1455 input_line_pointer
++; /* skip ',' or ':' */
1457 xtensa_elf_cons (4);
1459 xtensa_restore_emit_state (&state
);
1461 /* Restore the list of current labels. */
1462 xtensa_clear_insn_labels ();
1463 insn_labels
= saved_insn_labels
;
1468 xtensa_literal_prefix (char const *start
, int len
)
1470 char *name
, *linkonce_suffix
;
1471 char *newname
, *newname4
;
1472 size_t linkonce_len
;
1474 /* Get a null-terminated copy of the name. */
1475 name
= xmalloc (len
+ 1);
1478 strncpy (name
, start
, len
);
1481 /* Allocate the sections (interesting note: the memory pointing to
1482 the name is actually used for the name by the new section). */
1484 newname
= xmalloc (len
+ strlen (".literal") + 1);
1485 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1487 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1488 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1489 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1491 strcpy (newname
, ".gnu.linkonce.literal");
1492 strcpy (newname4
, ".gnu.linkonce.lit4");
1494 strcat (newname
, linkonce_suffix
);
1495 strcat (newname4
, linkonce_suffix
);
1499 int suffix_pos
= len
;
1501 /* If the section name ends with ".text", then replace that suffix
1502 instead of appending an additional suffix. */
1503 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1506 strcpy (newname
, name
);
1507 strcpy (newname4
, name
);
1509 strcpy (newname
+ suffix_pos
, ".literal");
1510 strcpy (newname4
+ suffix_pos
, ".lit4");
1513 /* Note that cache_literal_section does not create a segment if
1514 it already exists. */
1515 default_lit_sections
.lit_seg
= NULL
;
1516 default_lit_sections
.lit4_seg
= NULL
;
1518 /* Canonicalizing section names allows renaming literal
1519 sections to occur correctly. */
1520 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1521 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1527 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1530 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1532 float fall_through_f
, target_f
;
1534 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1535 if (fall_through_f
< 0)
1537 as_bad (_("fall through frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1545 as_bad (_("branch target frequency must be greater than 0"));
1546 ignore_rest_of_line ();
1550 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1552 demand_empty_rest_of_line ();
1556 /* Like normal .long/.short/.word, except support @plt, etc.
1557 Clobbers input_line_pointer, checks end-of-line. */
1560 xtensa_elf_cons (int nbytes
)
1563 bfd_reloc_code_real_type reloc
;
1565 md_flush_pending_output ();
1567 if (cur_vinsn
.inside_bundle
)
1568 as_bad (_("directives are not valid inside bundles"));
1570 if (is_it_end_of_statement ())
1572 demand_empty_rest_of_line ();
1579 if (exp
.X_op
== O_symbol
1580 && *input_line_pointer
== '@'
1581 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1584 reloc_howto_type
*reloc_howto
=
1585 bfd_reloc_type_lookup (stdoutput
, reloc
);
1587 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1588 as_bad (_("unsupported relocation"));
1589 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1591 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1592 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1593 as_bad (_("opcode-specific %s relocation used outside "
1594 "an instruction"), reloc_howto
->name
);
1595 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1596 as_bad (_("%s relocations do not fit in %d bytes"),
1597 reloc_howto
->name
, nbytes
);
1600 char *p
= frag_more ((int) nbytes
);
1601 xtensa_set_frag_assembly_state (frag_now
);
1602 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1603 nbytes
, &exp
, 0, reloc
);
1607 emit_expr (&exp
, (unsigned int) nbytes
);
1609 while (*input_line_pointer
++ == ',');
1611 input_line_pointer
--; /* Put terminator back into stream. */
1612 demand_empty_rest_of_line ();
1616 /* Parsing and Idiom Translation. */
1618 /* Parse @plt, etc. and return the desired relocation. */
1619 static bfd_reloc_code_real_type
1620 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1626 bfd_reloc_code_real_type reloc
;
1634 struct map_bfd
*ptr
;
1636 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1638 static struct map_bfd mapping
[] =
1640 MAP ("l", BFD_RELOC_LO16
),
1641 MAP ("h", BFD_RELOC_HI16
),
1642 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1643 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1647 return BFD_RELOC_NONE
;
1649 for (ch
= *str
, str2
= ident
;
1650 (str2
< ident
+ sizeof (ident
) - 1
1651 && (ISALNUM (ch
) || ch
== '@'));
1654 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1661 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1662 if (ch
== ptr
->string
[0]
1663 && len
== ptr
->length
1664 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1666 /* Now check for "identifier@suffix+constant". */
1667 if (*str
== '-' || *str
== '+')
1669 char *orig_line
= input_line_pointer
;
1670 expressionS new_exp
;
1672 input_line_pointer
= str
;
1673 expression (&new_exp
);
1674 if (new_exp
.X_op
== O_constant
)
1676 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1677 str
= input_line_pointer
;
1680 if (&input_line_pointer
!= str_p
)
1681 input_line_pointer
= orig_line
;
1688 return BFD_RELOC_UNUSED
;
1693 expression_end (const char *name
)
1716 #define ERROR_REG_NUM ((unsigned) -1)
1719 tc_get_register (const char *prefix
)
1722 const char *next_expr
;
1723 const char *old_line_pointer
;
1726 old_line_pointer
= input_line_pointer
;
1728 if (*input_line_pointer
== '$')
1729 ++input_line_pointer
;
1731 /* Accept "sp" as a synonym for "a1". */
1732 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1733 && expression_end (input_line_pointer
+ 2))
1735 input_line_pointer
+= 2;
1736 return 1; /* AR[1] */
1739 while (*input_line_pointer
++ == *prefix
++)
1741 --input_line_pointer
;
1746 as_bad (_("bad register name: %s"), old_line_pointer
);
1747 return ERROR_REG_NUM
;
1750 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1752 as_bad (_("bad register number: %s"), input_line_pointer
);
1753 return ERROR_REG_NUM
;
1758 while (ISDIGIT ((int) *input_line_pointer
))
1759 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1761 if (!(next_expr
= expression_end (input_line_pointer
)))
1763 as_bad (_("bad register name: %s"), old_line_pointer
);
1764 return ERROR_REG_NUM
;
1767 input_line_pointer
= (char *) next_expr
;
1774 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1776 xtensa_isa isa
= xtensa_default_isa
;
1778 /* Check if this is an immediate operand. */
1779 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1781 bfd_reloc_code_real_type reloc
;
1782 segT t
= expression (tok
);
1783 if (t
== absolute_section
1784 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1786 assert (tok
->X_op
== O_constant
);
1787 tok
->X_op
= O_symbol
;
1788 tok
->X_add_symbol
= &abs_symbol
;
1791 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1792 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1793 && (reloc
!= BFD_RELOC_NONE
))
1798 case BFD_RELOC_UNUSED
:
1799 as_bad (_("unsupported relocation"));
1802 case BFD_RELOC_XTENSA_PLT
:
1803 tok
->X_op
= O_pltrel
;
1806 case BFD_RELOC_LO16
:
1807 if (tok
->X_op
== O_constant
)
1808 tok
->X_add_number
&= 0xffff;
1813 case BFD_RELOC_HI16
:
1814 if (tok
->X_op
== O_constant
)
1815 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1824 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1825 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1827 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1830 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1831 as_bad (_("register number out of range"));
1834 tok
->X_op
= O_register
;
1835 tok
->X_add_symbol
= 0;
1836 tok
->X_add_number
= reg
;
1841 /* Split up the arguments for an opcode or pseudo-op. */
1844 tokenize_arguments (char **args
, char *str
)
1846 char *old_input_line_pointer
;
1847 bfd_boolean saw_comma
= FALSE
;
1848 bfd_boolean saw_arg
= FALSE
;
1849 bfd_boolean saw_colon
= FALSE
;
1851 char *arg_end
, *arg
;
1854 /* Save and restore input_line_pointer around this function. */
1855 old_input_line_pointer
= input_line_pointer
;
1856 input_line_pointer
= str
;
1858 while (*input_line_pointer
)
1861 switch (*input_line_pointer
)
1868 input_line_pointer
++;
1869 if (saw_comma
|| saw_colon
|| !saw_arg
)
1875 input_line_pointer
++;
1876 if (saw_comma
|| saw_colon
|| !saw_arg
)
1882 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1885 arg_end
= input_line_pointer
+ 1;
1886 while (!expression_end (arg_end
))
1889 arg_len
= arg_end
- input_line_pointer
;
1890 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1891 args
[num_args
] = arg
;
1895 strncpy (arg
, input_line_pointer
, arg_len
);
1896 arg
[arg_len
] = '\0';
1898 input_line_pointer
= arg_end
;
1908 if (saw_comma
|| saw_colon
)
1910 input_line_pointer
= old_input_line_pointer
;
1915 as_bad (_("extra comma"));
1917 as_bad (_("extra colon"));
1919 as_bad (_("missing argument"));
1921 as_bad (_("missing comma or colon"));
1922 input_line_pointer
= old_input_line_pointer
;
1927 /* Parse the arguments to an opcode. Return TRUE on error. */
1930 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1932 expressionS
*tok
, *last_tok
;
1933 xtensa_opcode opcode
= insn
->opcode
;
1934 bfd_boolean had_error
= TRUE
;
1935 xtensa_isa isa
= xtensa_default_isa
;
1936 int n
, num_regs
= 0;
1937 int opcode_operand_count
;
1938 int opnd_cnt
, last_opnd_cnt
;
1939 unsigned int next_reg
= 0;
1940 char *old_input_line_pointer
;
1942 if (insn
->insn_type
== ITYPE_LITERAL
)
1943 opcode_operand_count
= 1;
1945 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1948 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1950 /* Save and restore input_line_pointer around this function. */
1951 old_input_line_pointer
= input_line_pointer
;
1957 /* Skip invisible operands. */
1958 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1964 for (n
= 0; n
< num_args
; n
++)
1966 input_line_pointer
= arg_strings
[n
];
1967 if (*input_line_pointer
== ':')
1969 xtensa_regfile opnd_rf
;
1970 input_line_pointer
++;
1973 assert (opnd_cnt
> 0);
1975 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1977 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1978 as_warn (_("incorrect register number, ignoring"));
1983 if (opnd_cnt
>= opcode_operand_count
)
1985 as_warn (_("too many arguments"));
1988 assert (opnd_cnt
< MAX_INSN_ARGS
);
1990 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1991 next_reg
= tok
->X_add_number
+ 1;
1993 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1995 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1997 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1998 /* minus 1 because we are seeing one right now */
2004 last_opnd_cnt
= opnd_cnt
;
2011 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2015 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2018 insn
->ntok
= tok
- insn
->tok
;
2022 input_line_pointer
= old_input_line_pointer
;
2028 get_invisible_operands (TInsn
*insn
)
2030 xtensa_isa isa
= xtensa_default_isa
;
2031 static xtensa_insnbuf slotbuf
= NULL
;
2033 xtensa_opcode opc
= insn
->opcode
;
2034 int slot
, opnd
, fmt_found
;
2038 slotbuf
= xtensa_insnbuf_alloc (isa
);
2040 /* Find format/slot where this can be encoded. */
2043 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2045 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2047 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2053 if (fmt_found
) break;
2058 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2062 /* First encode all the visible operands
2063 (to deal with shared field operands). */
2064 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2066 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2067 && (insn
->tok
[opnd
].X_op
== O_register
2068 || insn
->tok
[opnd
].X_op
== O_constant
))
2070 val
= insn
->tok
[opnd
].X_add_number
;
2071 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2072 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2076 /* Then pull out the values for the invisible ones. */
2077 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2079 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2081 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2082 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2083 insn
->tok
[opnd
].X_add_number
= val
;
2084 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2085 insn
->tok
[opnd
].X_op
= O_register
;
2087 insn
->tok
[opnd
].X_op
= O_constant
;
2096 xg_reverse_shift_count (char **cnt_argp
)
2098 char *cnt_arg
, *new_arg
;
2099 cnt_arg
= *cnt_argp
;
2101 /* replace the argument with "31-(argument)" */
2102 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2103 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2106 *cnt_argp
= new_arg
;
2110 /* If "arg" is a constant expression, return non-zero with the value
2114 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2117 char *save_ptr
= input_line_pointer
;
2119 input_line_pointer
= arg
;
2121 input_line_pointer
= save_ptr
;
2123 if (exp
.X_op
== O_constant
)
2125 *valp
= exp
.X_add_number
;
2134 xg_replace_opname (char **popname
, char *newop
)
2137 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2138 strcpy (*popname
, newop
);
2143 xg_check_num_args (int *pnum_args
,
2148 int num_args
= *pnum_args
;
2150 if (num_args
< expected_num
)
2152 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2153 num_args
, opname
, expected_num
);
2157 if (num_args
> expected_num
)
2159 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2160 num_args
, opname
, expected_num
);
2161 while (num_args
-- > expected_num
)
2163 free (arg_strings
[num_args
]);
2164 arg_strings
[num_args
] = 0;
2166 *pnum_args
= expected_num
;
2174 /* If the register is not specified as part of the opcode,
2175 then get it from the operand and move it to the opcode. */
2178 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2180 xtensa_isa isa
= xtensa_default_isa
;
2182 char *opname
, *new_opname
;
2183 const char *sr_name
;
2184 int is_user
, is_write
;
2189 is_user
= (opname
[1] == 'u');
2190 is_write
= (opname
[0] == 'w');
2192 /* Opname == [rw]ur or [rwx]sr... */
2194 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2197 /* Check if the argument is a symbolic register name. */
2198 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2199 /* Handle WSR to "INTSET" as a special case. */
2200 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2201 && !strcasecmp (arg_strings
[1], "intset"))
2202 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2203 if (sr
== XTENSA_UNDEFINED
2204 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2206 /* Maybe it's a register number.... */
2208 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2210 as_bad (_("invalid register '%s' for '%s' instruction"),
2211 arg_strings
[1], opname
);
2214 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2215 if (sr
== XTENSA_UNDEFINED
)
2217 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2218 (long) val
, opname
);
2223 /* Remove the last argument, which is now part of the opcode. */
2224 free (arg_strings
[1]);
2228 /* Translate the opcode. */
2229 sr_name
= xtensa_sysreg_name (isa
, sr
);
2230 /* Another special case for "WSR.INTSET".... */
2231 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2233 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2234 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2236 *popname
= new_opname
;
2243 xtensa_translate_old_userreg_ops (char **popname
)
2245 xtensa_isa isa
= xtensa_default_isa
;
2247 char *opname
, *new_opname
;
2248 const char *sr_name
;
2249 bfd_boolean has_underbar
= FALSE
;
2252 if (opname
[0] == '_')
2254 has_underbar
= TRUE
;
2258 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2259 if (sr
!= XTENSA_UNDEFINED
)
2261 /* The new default name ("nnn") is different from the old default
2262 name ("URnnn"). The old default is handled below, and we don't
2263 want to recognize [RW]nnn, so do nothing if the name is the (new)
2265 static char namebuf
[10];
2266 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2267 if (strcmp (namebuf
, opname
+ 1) == 0)
2275 /* Only continue if the reg name is "URnnn". */
2276 if (opname
[1] != 'u' || opname
[2] != 'r')
2278 val
= strtoul (opname
+ 3, &end
, 10);
2282 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2283 if (sr
== XTENSA_UNDEFINED
)
2285 as_bad (_("invalid register number (%ld) for '%s'"),
2286 (long) val
, opname
);
2291 /* Translate the opcode. */
2292 sr_name
= xtensa_sysreg_name (isa
, sr
);
2293 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2294 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2295 opname
[0], sr_name
);
2297 *popname
= new_opname
;
2304 xtensa_translate_zero_immed (char *old_op
,
2314 assert (opname
[0] != '_');
2316 if (strcmp (opname
, old_op
) != 0)
2319 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2321 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2323 xg_replace_opname (popname
, new_op
);
2324 free (arg_strings
[1]);
2325 arg_strings
[1] = arg_strings
[2];
2334 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2335 Returns non-zero if an error was found. */
2338 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2340 char *opname
= *popname
;
2341 bfd_boolean has_underbar
= FALSE
;
2343 if (cur_vinsn
.inside_bundle
)
2348 has_underbar
= TRUE
;
2352 if (strcmp (opname
, "mov") == 0)
2354 if (use_transform () && !has_underbar
&& density_supported
)
2355 xg_replace_opname (popname
, "mov.n");
2358 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2360 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2361 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2362 strcpy (arg_strings
[2], arg_strings
[1]);
2368 if (strcmp (opname
, "bbsi.l") == 0)
2370 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2373 if (target_big_endian
)
2374 xg_reverse_shift_count (&arg_strings
[1]);
2378 if (strcmp (opname
, "bbci.l") == 0)
2380 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2382 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2383 if (target_big_endian
)
2384 xg_reverse_shift_count (&arg_strings
[1]);
2388 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2389 && strcmp (opname
, "nop") == 0)
2391 if (use_transform () && !has_underbar
&& density_supported
)
2392 xg_replace_opname (popname
, "nop.n");
2395 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2397 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2398 arg_strings
[0] = (char *) xmalloc (3);
2399 arg_strings
[1] = (char *) xmalloc (3);
2400 arg_strings
[2] = (char *) xmalloc (3);
2401 strcpy (arg_strings
[0], "a1");
2402 strcpy (arg_strings
[1], "a1");
2403 strcpy (arg_strings
[2], "a1");
2409 /* Recognize [RW]UR and [RWX]SR. */
2410 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2411 && (opname
[1] == 'u' || opname
[1] == 's'))
2412 || (opname
[0] == 'x' && opname
[1] == 's'))
2414 && opname
[3] == '\0')
2415 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2417 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2418 [RW]<name> if <name> is the non-default name of a user register. */
2419 if ((opname
[0] == 'r' || opname
[0] == 'w')
2420 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2421 return xtensa_translate_old_userreg_ops (popname
);
2423 /* Relax branches that don't allow comparisons against an immediate value
2424 of zero to the corresponding branches with implicit zero immediates. */
2425 if (!has_underbar
&& use_transform ())
2427 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2428 pnum_args
, arg_strings
))
2431 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2432 pnum_args
, arg_strings
))
2435 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2436 pnum_args
, arg_strings
))
2439 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2440 pnum_args
, arg_strings
))
2448 /* Functions for dealing with the Xtensa ISA. */
2450 /* Currently the assembler only allows us to use a single target per
2451 fragment. Because of this, only one operand for a given
2452 instruction may be symbolic. If there is a PC-relative operand,
2453 the last one is chosen. Otherwise, the result is the number of the
2454 last immediate operand, and if there are none of those, we fail and
2458 get_relaxable_immed (xtensa_opcode opcode
)
2460 int last_immed
= -1;
2463 if (opcode
== XTENSA_UNDEFINED
)
2466 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2467 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2469 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2471 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2473 if (last_immed
== -1
2474 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2481 static xtensa_opcode
2482 get_opcode_from_buf (const char *buf
, int slot
)
2484 static xtensa_insnbuf insnbuf
= NULL
;
2485 static xtensa_insnbuf slotbuf
= NULL
;
2486 xtensa_isa isa
= xtensa_default_isa
;
2491 insnbuf
= xtensa_insnbuf_alloc (isa
);
2492 slotbuf
= xtensa_insnbuf_alloc (isa
);
2495 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2496 fmt
= xtensa_format_decode (isa
, insnbuf
);
2497 if (fmt
== XTENSA_UNDEFINED
)
2498 return XTENSA_UNDEFINED
;
2500 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2501 return XTENSA_UNDEFINED
;
2503 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2504 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2508 #ifdef TENSILICA_DEBUG
2510 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2513 xtensa_print_insn_table (void)
2515 int num_opcodes
, num_operands
;
2516 xtensa_opcode opcode
;
2517 xtensa_isa isa
= xtensa_default_isa
;
2519 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2520 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2523 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2524 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2525 for (opn
= 0; opn
< num_operands
; opn
++)
2527 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2529 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2531 xtensa_regfile opnd_rf
=
2532 xtensa_operand_regfile (isa
, opcode
, opn
);
2533 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2535 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2536 fputs ("[lLr] ", stderr
);
2538 fputs ("i ", stderr
);
2540 fprintf (stderr
, "\n");
2546 print_vliw_insn (xtensa_insnbuf vbuf
)
2548 xtensa_isa isa
= xtensa_default_isa
;
2549 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2550 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2553 fprintf (stderr
, "format = %d\n", f
);
2555 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2557 xtensa_opcode opcode
;
2561 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2562 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2563 opname
= xtensa_opcode_name (isa
, opcode
);
2565 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2566 fprintf (stderr
, " operands = ");
2568 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2572 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2574 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2575 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2576 fprintf (stderr
, "%d ", val
);
2578 fprintf (stderr
, "\n");
2580 xtensa_insnbuf_free (isa
, sbuf
);
2583 #endif /* TENSILICA_DEBUG */
2587 is_direct_call_opcode (xtensa_opcode opcode
)
2589 xtensa_isa isa
= xtensa_default_isa
;
2590 int n
, num_operands
;
2592 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2595 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2596 for (n
= 0; n
< num_operands
; n
++)
2598 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2599 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2606 /* Convert from BFD relocation type code to slot and operand number.
2607 Returns non-zero on failure. */
2610 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2612 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2613 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2615 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2618 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2619 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2621 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2631 /* Convert from slot number to BFD relocation type code for the
2632 standard PC-relative relocations. Return BFD_RELOC_NONE on
2635 static bfd_reloc_code_real_type
2636 encode_reloc (int slot
)
2638 if (slot
< 0 || slot
> 14)
2639 return BFD_RELOC_NONE
;
2641 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2645 /* Convert from slot numbers to BFD relocation type code for the
2646 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2648 static bfd_reloc_code_real_type
2649 encode_alt_reloc (int slot
)
2651 if (slot
< 0 || slot
> 14)
2652 return BFD_RELOC_NONE
;
2654 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2659 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2662 xtensa_opcode opcode
,
2668 uint32 valbuf
= value
;
2670 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2672 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2674 as_bad_where ((char *) file
, line
,
2675 _("operand %d of '%s' has out of range value '%u'"),
2677 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2680 as_bad_where ((char *) file
, line
,
2681 _("operand %d of '%s' has invalid value '%u'"),
2683 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2688 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2694 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2697 xtensa_opcode opcode
,
2701 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2702 fmt
, slot
, slotbuf
, &val
);
2703 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2708 /* Checks for rules from xtensa-relax tables. */
2710 /* The routine xg_instruction_matches_option_term must return TRUE
2711 when a given option term is true. The meaning of all of the option
2712 terms is given interpretation by this function. This is needed when
2713 an option depends on the state of a directive, but there are no such
2714 options in use right now. */
2717 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2718 const ReqOrOption
*option
)
2720 if (strcmp (option
->option_name
, "realnop") == 0
2721 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2723 /* These conditions were evaluated statically when building the
2724 relaxation table. There's no need to reevaluate them now. */
2729 as_fatal (_("internal error: unknown option name '%s'"),
2730 option
->option_name
);
2736 xg_instruction_matches_or_options (TInsn
*insn
,
2737 const ReqOrOptionList
*or_option
)
2739 const ReqOrOption
*option
;
2740 /* Must match each of the AND terms. */
2741 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2743 if (xg_instruction_matches_option_term (insn
, option
))
2751 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2753 const ReqOption
*req_options
;
2754 /* Must match each of the AND terms. */
2755 for (req_options
= options
;
2756 req_options
!= NULL
;
2757 req_options
= req_options
->next
)
2759 /* Must match one of the OR clauses. */
2760 if (!xg_instruction_matches_or_options (insn
,
2761 req_options
->or_option_terms
))
2768 /* Return the transition rule that matches or NULL if none matches. */
2771 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2773 PreconditionList
*condition_l
;
2775 if (rule
->opcode
!= insn
->opcode
)
2778 for (condition_l
= rule
->conditions
;
2779 condition_l
!= NULL
;
2780 condition_l
= condition_l
->next
)
2784 Precondition
*cond
= condition_l
->precond
;
2789 /* The expression must be the constant. */
2790 assert (cond
->op_num
< insn
->ntok
);
2791 exp1
= &insn
->tok
[cond
->op_num
];
2792 if (expr_is_const (exp1
))
2797 if (get_expr_const (exp1
) != cond
->op_data
)
2801 if (get_expr_const (exp1
) == cond
->op_data
)
2808 else if (expr_is_register (exp1
))
2813 if (get_expr_register (exp1
) != cond
->op_data
)
2817 if (get_expr_register (exp1
) == cond
->op_data
)
2829 assert (cond
->op_num
< insn
->ntok
);
2830 assert (cond
->op_data
< insn
->ntok
);
2831 exp1
= &insn
->tok
[cond
->op_num
];
2832 exp2
= &insn
->tok
[cond
->op_data
];
2837 if (!expr_is_equal (exp1
, exp2
))
2841 if (expr_is_equal (exp1
, exp2
))
2853 if (!xg_instruction_matches_options (insn
, rule
->options
))
2861 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2863 bfd_boolean a_greater
= FALSE
;
2864 bfd_boolean b_greater
= FALSE
;
2866 ReqOptionList
*l_a
= a
->options
;
2867 ReqOptionList
*l_b
= b
->options
;
2869 /* We only care if they both are the same except for
2870 a const16 vs. an l32r. */
2872 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2874 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2875 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2876 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2878 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2880 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2882 /* This is the case we care about. */
2883 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2884 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2891 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2892 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2902 l_or_a
= l_or_a
->next
;
2903 l_or_b
= l_or_b
->next
;
2905 if (l_or_a
|| l_or_b
)
2914 /* Incomparable if the substitution was used differently in two cases. */
2915 if (a_greater
&& b_greater
)
2927 static TransitionRule
*
2928 xg_instruction_match (TInsn
*insn
)
2930 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2932 assert (insn
->opcode
< table
->num_opcodes
);
2934 /* Walk through all of the possible transitions. */
2935 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2937 TransitionRule
*rule
= l
->rule
;
2938 if (xg_instruction_matches_rule (insn
, rule
))
2945 /* Various Other Internal Functions. */
2948 is_unique_insn_expansion (TransitionRule
*r
)
2950 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2952 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2958 /* Check if there is exactly one relaxation for INSN that converts it to
2959 another instruction of equal or larger size. If so, and if TARG is
2960 non-null, go ahead and generate the relaxed instruction into TARG. If
2961 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2962 instruction, i.e., ignore relaxations that convert to an instruction of
2963 equal size. In some contexts where this function is used, only
2964 a single widening is allowed and the NARROW_ONLY argument is used to
2965 exclude cases like ADDI being "widened" to an ADDMI, which may
2966 later be relaxed to an ADDMI/ADDI pair. */
2969 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2971 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2973 TransitionRule
*match
= 0;
2975 assert (insn
->insn_type
== ITYPE_INSN
);
2976 assert (insn
->opcode
< table
->num_opcodes
);
2978 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2980 TransitionRule
*rule
= l
->rule
;
2982 if (xg_instruction_matches_rule (insn
, rule
)
2983 && is_unique_insn_expansion (rule
)
2984 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2985 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2996 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3001 /* Return the maximum number of bytes this opcode can expand to. */
3004 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3008 int max_size
= xg_get_single_size (opcode
);
3010 assert (opcode
< table
->num_opcodes
);
3012 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3014 TransitionRule
*rule
= l
->rule
;
3015 BuildInstr
*build_list
;
3020 build_list
= rule
->to_instr
;
3021 if (is_unique_insn_expansion (rule
))
3023 assert (build_list
->typ
== INSTR_INSTR
);
3024 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3027 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3029 switch (build_list
->typ
)
3032 this_size
+= xg_get_single_size (build_list
->opcode
);
3034 case INSTR_LITERAL_DEF
:
3035 case INSTR_LABEL_DEF
:
3040 if (this_size
> max_size
)
3041 max_size
= this_size
;
3047 /* Return the maximum number of literal bytes this opcode can generate. */
3050 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3056 assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3077 case INSTR_LITERAL_DEF
:
3078 /* Hard-coded 4-byte literal. */
3082 case INSTR_LABEL_DEF
:
3087 if (this_size
> max_size
)
3088 max_size
= this_size
;
3095 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3097 int steps_taken
= 0;
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3101 assert (insn
->insn_type
== ITYPE_INSN
);
3102 assert (insn
->opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3108 if (xg_instruction_matches_rule (insn
, rule
))
3110 if (steps_taken
== lateral_steps
)
3120 get_special_literal_symbol (void)
3122 static symbolS
*sym
= NULL
;
3125 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3131 get_special_label_symbol (void)
3133 static symbolS
*sym
= NULL
;
3136 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3142 xg_valid_literal_expression (const expressionS
*exp
)
3159 /* This will check to see if the value can be converted into the
3160 operand type. It will return TRUE if it does not fit. */
3163 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3165 uint32 valbuf
= value
;
3166 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3172 /* Assumes: All immeds are constants. Check that all constants fit
3173 into their immeds; return FALSE if not. */
3176 xg_immeds_fit (const TInsn
*insn
)
3178 xtensa_isa isa
= xtensa_default_isa
;
3182 assert (insn
->insn_type
== ITYPE_INSN
);
3183 for (i
= 0; i
< n
; ++i
)
3185 const expressionS
*expr
= &insn
->tok
[i
];
3186 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3193 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3198 /* The symbol should have a fixup associated with it. */
3207 /* This should only be called after we have an initial
3208 estimate of the addresses. */
3211 xg_symbolic_immeds_fit (const TInsn
*insn
,
3217 xtensa_isa isa
= xtensa_default_isa
;
3225 assert (insn
->insn_type
== ITYPE_INSN
);
3227 for (i
= 0; i
< n
; ++i
)
3229 const expressionS
*expr
= &insn
->tok
[i
];
3230 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3237 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3243 /* Check for the worst case. */
3244 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3249 /* We only allow symbols for PC-relative references.
3250 If pc_frag == 0, then we don't have frag locations yet. */
3252 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3255 /* If it is a weak symbol, then assume it won't reach. */
3256 if (S_IS_WEAK (expr
->X_add_symbol
))
3259 if (is_direct_call_opcode (insn
->opcode
)
3260 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3262 /* If callee is undefined or in a different segment, be
3263 optimistic and assume it will be in range. */
3264 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3268 /* Only references within a segment can be known to fit in the
3269 operands at assembly time. */
3270 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3273 symbolP
= expr
->X_add_symbol
;
3274 sym_frag
= symbol_get_frag (symbolP
);
3275 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3276 pc
= pc_frag
->fr_address
+ pc_offset
;
3278 /* If frag has yet to be reached on this pass, assume it
3279 will move by STRETCH just as we did. If this is not so,
3280 it will be because some frag between grows, and that will
3281 force another pass. Beware zero-length frags. There
3282 should be a faster way to do this. */
3285 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3286 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3291 new_offset
= target
;
3292 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3293 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3298 /* The symbol should have a fixup associated with it. */
3307 /* Return TRUE on success. */
3310 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3315 memset (targ
, 0, sizeof (TInsn
));
3316 targ
->linenum
= insn
->linenum
;
3321 targ
->opcode
= bi
->opcode
;
3322 targ
->insn_type
= ITYPE_INSN
;
3323 targ
->is_specific_opcode
= FALSE
;
3325 for (; op
!= NULL
; op
= op
->next
)
3327 int op_num
= op
->op_num
;
3328 int op_data
= op
->op_data
;
3330 assert (op
->op_num
< MAX_INSN_ARGS
);
3332 if (targ
->ntok
<= op_num
)
3333 targ
->ntok
= op_num
+ 1;
3338 set_expr_const (&targ
->tok
[op_num
], op_data
);
3341 assert (op_data
< insn
->ntok
);
3342 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3345 sym
= get_special_literal_symbol ();
3346 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3349 sym
= get_special_label_symbol ();
3350 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3352 case OP_OPERAND_HI16U
:
3353 case OP_OPERAND_LOW16U
:
3354 assert (op_data
< insn
->ntok
);
3355 if (expr_is_const (&insn
->tok
[op_data
]))
3358 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3359 val
= xg_apply_userdef_op_fn (op
->typ
,
3362 targ
->tok
[op_num
].X_add_number
= val
;
3366 /* For const16 we can create relocations for these. */
3367 if (targ
->opcode
== XTENSA_UNDEFINED
3368 || (targ
->opcode
!= xtensa_const16_opcode
))
3370 assert (op_data
< insn
->ntok
);
3371 /* Need to build a O_lo16 or O_hi16. */
3372 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3373 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3375 if (op
->typ
== OP_OPERAND_HI16U
)
3376 targ
->tok
[op_num
].X_op
= O_hi16
;
3377 else if (op
->typ
== OP_OPERAND_LOW16U
)
3378 targ
->tok
[op_num
].X_op
= O_lo16
;
3385 /* currently handles:
3388 OP_OPERAND_F32MINUS */
3389 if (xg_has_userdef_op_fn (op
->typ
))
3391 assert (op_data
< insn
->ntok
);
3392 if (expr_is_const (&insn
->tok
[op_data
]))
3395 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3396 val
= xg_apply_userdef_op_fn (op
->typ
,
3399 targ
->tok
[op_num
].X_add_number
= val
;
3402 return FALSE
; /* We cannot use a relocation for this. */
3411 case INSTR_LITERAL_DEF
:
3413 targ
->opcode
= XTENSA_UNDEFINED
;
3414 targ
->insn_type
= ITYPE_LITERAL
;
3415 targ
->is_specific_opcode
= FALSE
;
3416 for (; op
!= NULL
; op
= op
->next
)
3418 int op_num
= op
->op_num
;
3419 int op_data
= op
->op_data
;
3420 assert (op
->op_num
< MAX_INSN_ARGS
);
3422 if (targ
->ntok
<= op_num
)
3423 targ
->ntok
= op_num
+ 1;
3428 assert (op_data
< insn
->ntok
);
3429 /* We can only pass resolvable literals through. */
3430 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3432 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3444 case INSTR_LABEL_DEF
:
3446 targ
->opcode
= XTENSA_UNDEFINED
;
3447 targ
->insn_type
= ITYPE_LABEL
;
3448 targ
->is_specific_opcode
= FALSE
;
3449 /* Literal with no ops is a label? */
3450 assert (op
== NULL
);
3461 /* Return TRUE on success. */
3464 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3466 for (; bi
!= NULL
; bi
= bi
->next
)
3468 TInsn
*next_insn
= istack_push_space (istack
);
3470 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3477 /* Return TRUE on valid expansion. */
3480 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3482 int stack_size
= istack
->ninsn
;
3483 int steps_taken
= 0;
3484 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3487 assert (insn
->insn_type
== ITYPE_INSN
);
3488 assert (insn
->opcode
< table
->num_opcodes
);
3490 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3492 TransitionRule
*rule
= l
->rule
;
3494 if (xg_instruction_matches_rule (insn
, rule
))
3496 if (lateral_steps
== steps_taken
)
3500 /* This is it. Expand the rule to the stack. */
3501 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3504 /* Check to see if it fits. */
3505 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3507 TInsn
*insn
= &istack
->insn
[i
];
3509 if (insn
->insn_type
== ITYPE_INSN
3510 && !tinsn_has_symbolic_operands (insn
)
3511 && !xg_immeds_fit (insn
))
3513 istack
->ninsn
= stack_size
;
3526 /* Relax the assembly instruction at least "min_steps".
3527 Return the number of steps taken. */
3530 xg_assembly_relax (IStack
*istack
,
3533 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3534 offsetT pc_offset
, /* offset in fragment */
3535 int min_steps
, /* minimum conversion steps */
3536 long stretch
) /* number of bytes stretched so far */
3538 int steps_taken
= 0;
3540 /* assert (has no symbolic operands)
3541 Some of its immeds don't fit.
3542 Try to build a relaxed version.
3543 This may go through a couple of stages
3544 of single instruction transformations before
3547 TInsn single_target
;
3549 int lateral_steps
= 0;
3550 int istack_size
= istack
->ninsn
;
3552 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3553 && steps_taken
>= min_steps
)
3555 istack_push (istack
, insn
);
3558 current_insn
= *insn
;
3560 /* Walk through all of the single instruction expansions. */
3561 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3564 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3567 if (steps_taken
>= min_steps
)
3569 istack_push (istack
, &single_target
);
3573 current_insn
= single_target
;
3576 /* Now check for a multi-instruction expansion. */
3577 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3579 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3582 if (steps_taken
>= min_steps
)
3584 istack_push (istack
, ¤t_insn
);
3589 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3591 if (steps_taken
>= min_steps
)
3595 istack
->ninsn
= istack_size
;
3598 /* It's not going to work -- use the original. */
3599 istack_push (istack
, insn
);
3605 xg_force_frag_space (int size
)
3607 /* This may have the side effect of creating a new fragment for the
3608 space to go into. I just do not like the name of the "frag"
3615 xg_finish_frag (char *last_insn
,
3616 enum xtensa_relax_statesE frag_state
,
3617 enum xtensa_relax_statesE slot0_state
,
3619 bfd_boolean is_insn
)
3621 /* Finish off this fragment so that it has at LEAST the desired
3622 max_growth. If it doesn't fit in this fragment, close this one
3623 and start a new one. In either case, return a pointer to the
3624 beginning of the growth area. */
3628 xg_force_frag_space (max_growth
);
3630 old_frag
= frag_now
;
3632 frag_now
->fr_opcode
= last_insn
;
3634 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3636 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3637 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3639 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3640 xtensa_set_frag_assembly_state (frag_now
);
3642 /* Just to make sure that we did not split it up. */
3643 assert (old_frag
->fr_next
== frag_now
);
3647 /* Return TRUE if the target frag is one of the next non-empty frags. */
3650 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3655 for (; fragP
; fragP
= fragP
->fr_next
)
3657 if (fragP
== target
)
3659 if (fragP
->fr_fix
!= 0)
3661 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3663 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3664 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3666 if (fragP
->fr_type
== rs_space
)
3674 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3676 xtensa_isa isa
= xtensa_default_isa
;
3678 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3683 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3684 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3687 for (i
= 0; i
< num_ops
; i
++)
3689 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3695 if (target_op
== -1)
3698 if (insn
->ntok
<= target_op
)
3701 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3704 sym
= insn
->tok
[target_op
].X_add_symbol
;
3708 if (insn
->tok
[target_op
].X_add_number
!= 0)
3711 target_frag
= symbol_get_frag (sym
);
3712 if (target_frag
== NULL
)
3715 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3716 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3724 xg_add_branch_and_loop_targets (TInsn
*insn
)
3726 xtensa_isa isa
= xtensa_default_isa
;
3727 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3729 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3732 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3733 && insn
->tok
[i
].X_op
== O_symbol
)
3734 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3738 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3739 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3743 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3745 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3746 && insn
->tok
[i
].X_op
== O_symbol
)
3748 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3749 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3750 if (S_IS_DEFINED (sym
))
3751 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3758 /* Return FALSE if no error. */
3761 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3766 switch (instr_spec
->typ
)
3769 new_insn
->insn_type
= ITYPE_INSN
;
3770 new_insn
->opcode
= instr_spec
->opcode
;
3771 new_insn
->is_specific_opcode
= FALSE
;
3772 new_insn
->linenum
= old_insn
->linenum
;
3774 case INSTR_LITERAL_DEF
:
3775 new_insn
->insn_type
= ITYPE_LITERAL
;
3776 new_insn
->opcode
= XTENSA_UNDEFINED
;
3777 new_insn
->is_specific_opcode
= FALSE
;
3778 new_insn
->linenum
= old_insn
->linenum
;
3780 case INSTR_LABEL_DEF
:
3781 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3785 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3788 const expressionS
*src_exp
;
3794 /* The expression must be the constant. */
3795 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3796 exp
= &new_insn
->tok
[b_op
->op_num
];
3797 set_expr_const (exp
, b_op
->op_data
);
3801 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3802 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3803 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3804 exp
= &new_insn
->tok
[b_op
->op_num
];
3805 copy_expr (exp
, src_exp
);
3810 as_bad (_("can't handle generation of literal/labels yet"));
3814 as_bad (_("can't handle undefined OP TYPE"));
3819 new_insn
->ntok
= num_ops
;
3824 /* Return TRUE if it was simplified. */
3827 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3829 TransitionRule
*rule
;
3830 BuildInstr
*insn_spec
;
3832 if (old_insn
->is_specific_opcode
|| !density_supported
)
3835 rule
= xg_instruction_match (old_insn
);
3839 insn_spec
= rule
->to_instr
;
3840 /* There should only be one. */
3841 assert (insn_spec
!= NULL
);
3842 assert (insn_spec
->next
== NULL
);
3843 if (insn_spec
->next
!= NULL
)
3846 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3852 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3853 l32i.n. (2) Check the number of operands. (3) Place the instruction
3854 tokens into the stack or relax it and place multiple
3855 instructions/literals onto the stack. Return FALSE if no error. */
3858 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3862 bfd_boolean do_expand
;
3864 memset (&new_insn
, 0, sizeof (TInsn
));
3866 /* Narrow it if we can. xg_simplify_insn now does all the
3867 appropriate checking (e.g., for the density option). */
3868 if (xg_simplify_insn (orig_insn
, &new_insn
))
3869 orig_insn
= &new_insn
;
3871 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3873 if (orig_insn
->ntok
< noperands
)
3875 as_bad (_("found %d operands for '%s': Expected %d"),
3877 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3881 if (orig_insn
->ntok
> noperands
)
3882 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3884 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3887 /* If there are not enough operands, we will assert above. If there
3888 are too many, just cut out the extras here. */
3889 orig_insn
->ntok
= noperands
;
3891 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3894 /* If the instruction will definitely need to be relaxed, it is better
3895 to expand it now for better scheduling. Decide whether to expand
3897 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3899 /* Calls should be expanded to longcalls only in the backend relaxation
3900 so that the assembly scheduler will keep the L32R/CALLX instructions
3902 if (is_direct_call_opcode (orig_insn
->opcode
))
3905 if (tinsn_has_symbolic_operands (orig_insn
))
3907 /* The values of symbolic operands are not known yet, so only expand
3908 now if an operand is "complex" (e.g., difference of symbols) and
3909 will have to be stored as a literal regardless of the value. */
3910 if (!tinsn_has_complex_operands (orig_insn
))
3913 else if (xg_immeds_fit (orig_insn
))
3917 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3919 istack_push (istack
, orig_insn
);
3925 /* Return TRUE if the section flags are marked linkonce
3926 or the name is .gnu.linkonce*. */
3929 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3931 flagword flags
, link_once_flags
;
3933 flags
= bfd_get_section_flags (abfd
, sec
);
3934 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3936 /* Flags might not be set yet. */
3937 if (!link_once_flags
)
3939 static size_t len
= sizeof ".gnu.linkonce.t.";
3941 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3942 link_once_flags
= SEC_LINK_ONCE
;
3944 return (link_once_flags
!= 0);
3949 xtensa_add_literal_sym (symbolS
*sym
)
3953 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3955 l
->next
= literal_syms
;
3961 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3963 static int lit_num
= 0;
3964 static char name
[256];
3967 sprintf (name
, ".L_lit_sym%d", lit_num
);
3969 /* Create a local symbol. If it is in a linkonce section, we have to
3970 be careful to make sure that if it is used in a relocation that the
3971 symbol will be in the output file. */
3972 if (get_is_linkonce_section (stdoutput
, sec
))
3974 symbolP
= symbol_new (name
, sec
, 0, frag
);
3975 S_CLEAR_EXTERNAL (symbolP
);
3976 /* symbolP->local = 1; */
3979 symbolP
= symbol_new (name
, sec
, 0, frag
);
3981 xtensa_add_literal_sym (symbolP
);
3983 frag
->tc_frag_data
.is_literal
= TRUE
;
3989 /* Currently all literals that are generated here are 32-bit L32R targets. */
3992 xg_assemble_literal (/* const */ TInsn
*insn
)
3995 symbolS
*lit_sym
= NULL
;
3997 /* size = 4 for L32R. It could easily be larger when we move to
3998 larger constants. Add a parameter later. */
3999 offsetT litsize
= 4;
4000 offsetT litalign
= 2; /* 2^2 = 4 */
4001 expressionS saved_loc
;
4002 expressionS
* emit_val
;
4004 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4006 assert (insn
->insn_type
== ITYPE_LITERAL
);
4007 assert (insn
->ntok
== 1); /* must be only one token here */
4009 xtensa_switch_to_literal_fragment (&state
);
4011 emit_val
= &insn
->tok
[0];
4012 if (emit_val
->X_op
== O_big
)
4014 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4017 /* This happens when someone writes a "movi a2, big_number". */
4018 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4019 _("invalid immediate"));
4020 xtensa_restore_emit_state (&state
);
4025 /* Force a 4-byte align here. Note that this opens a new frag, so all
4026 literals done with this function have a frag to themselves. That's
4027 important for the way text section literals work. */
4028 frag_align (litalign
, 0, 0);
4029 record_alignment (now_seg
, litalign
);
4031 if (emit_val
->X_op
== O_pltrel
)
4033 char *p
= frag_more (litsize
);
4034 xtensa_set_frag_assembly_state (frag_now
);
4035 if (emit_val
->X_add_symbol
)
4036 emit_val
->X_op
= O_symbol
;
4038 emit_val
->X_op
= O_constant
;
4039 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4040 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4043 emit_expr (emit_val
, litsize
);
4045 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4046 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4047 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4048 lit_sym
= frag_now
->fr_symbol
;
4049 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4052 xtensa_restore_emit_state (&state
);
4058 xg_assemble_literal_space (/* const */ int size
, int slot
)
4061 /* We might have to do something about this alignment. It only
4062 takes effect if something is placed here. */
4063 offsetT litalign
= 2; /* 2^2 = 4 */
4064 fragS
*lit_saved_frag
;
4066 assert (size
% 4 == 0);
4068 xtensa_switch_to_literal_fragment (&state
);
4070 /* Force a 4-byte align here. */
4071 frag_align (litalign
, 0, 0);
4072 record_alignment (now_seg
, litalign
);
4074 xg_force_frag_space (size
);
4076 lit_saved_frag
= frag_now
;
4077 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4078 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4079 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4080 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4083 xtensa_restore_emit_state (&state
);
4084 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4088 /* Put in a fixup record based on the opcode.
4089 Return TRUE on success. */
4092 xg_add_opcode_fix (TInsn
*tinsn
,
4100 xtensa_opcode opcode
= tinsn
->opcode
;
4101 bfd_reloc_code_real_type reloc
;
4102 reloc_howto_type
*howto
;
4106 reloc
= BFD_RELOC_NONE
;
4108 /* First try the special cases for "alternate" relocs. */
4109 if (opcode
== xtensa_l32r_opcode
)
4111 if (fragP
->tc_frag_data
.use_absolute_literals
)
4112 reloc
= encode_alt_reloc (slot
);
4114 else if (opcode
== xtensa_const16_opcode
)
4116 if (expr
->X_op
== O_lo16
)
4118 reloc
= encode_reloc (slot
);
4119 expr
->X_op
= O_symbol
;
4121 else if (expr
->X_op
== O_hi16
)
4123 reloc
= encode_alt_reloc (slot
);
4124 expr
->X_op
= O_symbol
;
4128 if (opnum
!= get_relaxable_immed (opcode
))
4130 as_bad (_("invalid relocation for operand %i of '%s'"),
4131 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4135 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4136 into the symbol table where the generic portions of the assembler
4137 won't know what to do with them. */
4138 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4140 as_bad (_("invalid expression for operand %i of '%s'"),
4141 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4145 /* Next try the generic relocs. */
4146 if (reloc
== BFD_RELOC_NONE
)
4147 reloc
= encode_reloc (slot
);
4148 if (reloc
== BFD_RELOC_NONE
)
4150 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4154 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4157 as_bad (_("undefined symbol for opcode \"%s\""),
4158 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4162 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4163 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4164 howto
->pc_relative
, reloc
);
4165 the_fix
->fx_no_overflow
= 1;
4167 if (expr
->X_add_symbol
4168 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4169 || S_IS_WEAK (expr
->X_add_symbol
)))
4170 the_fix
->fx_plt
= TRUE
;
4172 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4173 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4174 the_fix
->tc_fix_data
.slot
= slot
;
4181 xg_emit_insn_to_buf (TInsn
*tinsn
,
4185 bfd_boolean build_fix
)
4187 static xtensa_insnbuf insnbuf
= NULL
;
4188 bfd_boolean has_symbolic_immed
= FALSE
;
4189 bfd_boolean ok
= TRUE
;
4192 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4194 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4195 if (has_symbolic_immed
&& build_fix
)
4198 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4199 int slot
= xg_get_single_slot (tinsn
->opcode
);
4200 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4201 expressionS
*exp
= &tinsn
->tok
[opnum
];
4203 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4206 fragP
->tc_frag_data
.is_insn
= TRUE
;
4207 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4208 (unsigned char *) buf
, 0);
4214 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4216 symbolS
*sym
= get_special_literal_symbol ();
4220 assert (insn
->insn_type
== ITYPE_INSN
);
4221 for (i
= 0; i
< insn
->ntok
; i
++)
4222 if (insn
->tok
[i
].X_add_symbol
== sym
)
4223 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4229 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4231 symbolS
*sym
= get_special_label_symbol ();
4233 /* assert (!insn->is_literal); */
4234 for (i
= 0; i
< insn
->ntok
; i
++)
4235 if (insn
->tok
[i
].X_add_symbol
== sym
)
4236 insn
->tok
[i
].X_add_symbol
= label_sym
;
4241 /* Return TRUE if the instruction can write to the specified
4242 integer register. */
4245 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4249 xtensa_isa isa
= xtensa_default_isa
;
4251 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4253 for (i
= 0; i
< num_ops
; i
++)
4256 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4257 if ((inout
== 'o' || inout
== 'm')
4258 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4260 xtensa_regfile opnd_rf
=
4261 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4262 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4264 if ((insn
->tok
[i
].X_op
== O_register
)
4265 && (insn
->tok
[i
].X_add_number
== regnum
))
4275 is_bad_loopend_opcode (const TInsn
*tinsn
)
4277 xtensa_opcode opcode
= tinsn
->opcode
;
4279 if (opcode
== XTENSA_UNDEFINED
)
4282 if (opcode
== xtensa_call0_opcode
4283 || opcode
== xtensa_callx0_opcode
4284 || opcode
== xtensa_call4_opcode
4285 || opcode
== xtensa_callx4_opcode
4286 || opcode
== xtensa_call8_opcode
4287 || opcode
== xtensa_callx8_opcode
4288 || opcode
== xtensa_call12_opcode
4289 || opcode
== xtensa_callx12_opcode
4290 || opcode
== xtensa_isync_opcode
4291 || opcode
== xtensa_ret_opcode
4292 || opcode
== xtensa_ret_n_opcode
4293 || opcode
== xtensa_retw_opcode
4294 || opcode
== xtensa_retw_n_opcode
4295 || opcode
== xtensa_waiti_opcode
4296 || opcode
== xtensa_rsr_lcount_opcode
)
4303 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4304 This allows the debugger to add unaligned labels.
4305 Also, the assembler generates stabs labels that need
4306 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4309 is_unaligned_label (symbolS
*sym
)
4311 const char *name
= S_GET_NAME (sym
);
4312 static size_t fake_size
= 0;
4316 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4319 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4321 fake_size
= strlen (FAKE_LABEL_NAME
);
4324 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4325 && (name
[fake_size
] == 'F'
4326 || name
[fake_size
] == 'L'
4327 || (name
[fake_size
] == 'e'
4328 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4336 next_non_empty_frag (const fragS
*fragP
)
4338 fragS
*next_fragP
= fragP
->fr_next
;
4340 /* Sometimes an empty will end up here due storage allocation issues.
4341 So we have to skip until we find something legit. */
4342 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4343 next_fragP
= next_fragP
->fr_next
;
4345 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4353 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4355 xtensa_opcode out_opcode
;
4356 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4358 if (next_fragP
== NULL
)
4361 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4362 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4364 *opcode
= out_opcode
;
4372 frag_format_size (const fragS
*fragP
)
4374 static xtensa_insnbuf insnbuf
= NULL
;
4375 xtensa_isa isa
= xtensa_default_isa
;
4380 insnbuf
= xtensa_insnbuf_alloc (isa
);
4383 return XTENSA_UNDEFINED
;
4385 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4386 (unsigned char *) fragP
->fr_literal
, 0);
4388 fmt
= xtensa_format_decode (isa
, insnbuf
);
4389 if (fmt
== XTENSA_UNDEFINED
)
4390 return XTENSA_UNDEFINED
;
4391 fmt_size
= xtensa_format_length (isa
, fmt
);
4393 /* If the next format won't be changing due to relaxation, just
4394 return the length of the first format. */
4395 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4398 /* If during relaxation we have to pull an instruction out of a
4399 multi-slot instruction, we will return the more conservative
4400 number. This works because alignment on bigger instructions
4401 is more restrictive than alignment on smaller instructions.
4402 This is more conservative than we would like, but it happens
4405 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4408 /* If we aren't doing one of our own relaxations or it isn't
4409 slot-based, then the insn size won't change. */
4410 if (fragP
->fr_type
!= rs_machine_dependent
)
4412 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4415 /* If an instruction is about to grow, return the longer size. */
4416 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4417 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4420 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4421 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4428 next_frag_format_size (const fragS
*fragP
)
4430 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4431 return frag_format_size (next_fragP
);
4435 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4436 required two-byte instructions to be treated as three-byte instructions
4437 for loop instruction alignment. This restriction was removed beginning
4438 with Xtensa LX. Now the only requirement on loop instruction alignment
4439 is that the first instruction of the loop must appear at an address that
4440 does not cross a fetch boundary. */
4443 get_loop_align_size (int insn_size
)
4445 if (insn_size
== XTENSA_UNDEFINED
)
4446 return xtensa_fetch_width
;
4448 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4455 /* If the next legit fragment is an end-of-loop marker,
4456 switch its state so it will instantiate a NOP. */
4459 update_next_frag_state (fragS
*fragP
)
4461 fragS
*next_fragP
= fragP
->fr_next
;
4462 fragS
*new_target
= NULL
;
4466 /* We are guaranteed there will be one of these... */
4467 while (!(next_fragP
->fr_type
== rs_machine_dependent
4468 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4469 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4470 next_fragP
= next_fragP
->fr_next
;
4472 assert (next_fragP
->fr_type
== rs_machine_dependent
4473 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4474 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4476 /* ...and one of these. */
4477 new_target
= next_fragP
->fr_next
;
4478 while (!(new_target
->fr_type
== rs_machine_dependent
4479 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4480 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4481 new_target
= new_target
->fr_next
;
4483 assert (new_target
->fr_type
== rs_machine_dependent
4484 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4485 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4488 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4490 if (next_fragP
->fr_type
== rs_machine_dependent
4491 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4493 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4497 next_fragP
= next_fragP
->fr_next
;
4503 next_frag_is_branch_target (const fragS
*fragP
)
4505 /* Sometimes an empty will end up here due to storage allocation issues,
4506 so we have to skip until we find something legit. */
4507 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4509 if (fragP
->tc_frag_data
.is_branch_target
)
4511 if (fragP
->fr_fix
!= 0)
4519 next_frag_is_loop_target (const fragS
*fragP
)
4521 /* Sometimes an empty will end up here due storage allocation issues.
4522 So we have to skip until we find something legit. */
4523 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4525 if (fragP
->tc_frag_data
.is_loop_target
)
4527 if (fragP
->fr_fix
!= 0)
4535 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4537 const fragS
*next_fragp
= fragp
->fr_next
;
4538 xtensa_opcode next_opcode
;
4540 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4543 /* Sometimes an empty will end up here due to storage allocation issues,
4544 so we have to skip until we find something legit. */
4545 while (next_fragp
->fr_fix
== 0)
4546 next_fragp
= next_fragp
->fr_next
;
4548 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4551 /* There is some implicit knowledge encoded in here.
4552 The LOOP instructions that are NOT RELAX_IMMED have
4553 been relaxed. Note that we can assume that the LOOP
4554 instruction is in slot 0 because loops aren't bundleable. */
4555 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4556 return get_expanded_loop_offset (next_opcode
);
4562 /* Mark a location where we can later insert literal frags. Update
4563 the section's literal_pool_loc, so subsequent literals can be
4564 placed nearest to their use. */
4567 xtensa_mark_literal_pool_location (void)
4569 /* Any labels pointing to the current location need
4570 to be adjusted to after the literal pool. */
4572 fragS
*pool_location
;
4574 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4577 frag_align (2, 0, 0);
4578 record_alignment (now_seg
, 2);
4580 /* We stash info in these frags so we can later move the literal's
4581 fixes into this frchain's fix list. */
4582 pool_location
= frag_now
;
4583 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4584 frag_variant (rs_machine_dependent
, 0, 0,
4585 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4586 xtensa_set_frag_assembly_state (frag_now
);
4587 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4588 frag_variant (rs_machine_dependent
, 0, 0,
4589 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4590 xtensa_set_frag_assembly_state (frag_now
);
4592 /* Now put a frag into the literal pool that points to this location. */
4593 set_literal_pool_location (now_seg
, pool_location
);
4594 xtensa_switch_to_non_abs_literal_fragment (&s
);
4595 frag_align (2, 0, 0);
4596 record_alignment (now_seg
, 2);
4598 /* Close whatever frag is there. */
4599 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4600 xtensa_set_frag_assembly_state (frag_now
);
4601 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4602 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4603 xtensa_restore_emit_state (&s
);
4604 xtensa_set_frag_assembly_state (frag_now
);
4608 /* Build a nop of the correct size into tinsn. */
4611 build_nop (TInsn
*tinsn
, int size
)
4617 tinsn
->opcode
= xtensa_nop_n_opcode
;
4619 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4620 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4624 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4626 tinsn
->opcode
= xtensa_or_opcode
;
4627 set_expr_const (&tinsn
->tok
[0], 1);
4628 set_expr_const (&tinsn
->tok
[1], 1);
4629 set_expr_const (&tinsn
->tok
[2], 1);
4633 tinsn
->opcode
= xtensa_nop_opcode
;
4635 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4640 /* Assemble a NOP of the requested size in the buffer. User must have
4641 allocated "buf" with at least "size" bytes. */
4644 assemble_nop (int size
, char *buf
)
4646 static xtensa_insnbuf insnbuf
= NULL
;
4649 build_nop (&tinsn
, size
);
4652 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4654 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4655 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4656 (unsigned char *) buf
, 0);
4660 /* Return the number of bytes for the offset of the expanded loop
4661 instruction. This should be incorporated into the relaxation
4662 specification but is hard-coded here. This is used to auto-align
4663 the loop instruction. It is invalid to call this function if the
4664 configuration does not have loops or if the opcode is not a loop
4668 get_expanded_loop_offset (xtensa_opcode opcode
)
4670 /* This is the OFFSET of the loop instruction in the expanded loop.
4671 This MUST correspond directly to the specification of the loop
4672 expansion. It will be validated on fragment conversion. */
4673 assert (opcode
!= XTENSA_UNDEFINED
);
4674 if (opcode
== xtensa_loop_opcode
)
4676 if (opcode
== xtensa_loopnez_opcode
)
4678 if (opcode
== xtensa_loopgtz_opcode
)
4680 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4686 get_literal_pool_location (segT seg
)
4688 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4693 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4695 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4699 /* Set frag assembly state should be called when a new frag is
4700 opened and after a frag has been closed. */
4703 xtensa_set_frag_assembly_state (fragS
*fragP
)
4705 if (!density_supported
)
4706 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4708 /* This function is called from subsegs_finish, which is called
4709 after xtensa_end, so we can't use "use_transform" or
4710 "use_schedule" here. */
4711 if (!directive_state
[directive_transform
])
4712 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4713 if (directive_state
[directive_longcalls
])
4714 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4715 fragP
->tc_frag_data
.use_absolute_literals
=
4716 directive_state
[directive_absolute_literals
];
4717 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4722 relaxable_section (asection
*sec
)
4724 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4729 xtensa_find_unmarked_state_frags (void)
4733 /* Walk over each fragment of all of the current segments. For each
4734 unmarked fragment, mark it with the same info as the previous
4736 for (seclist
= &stdoutput
->sections
;
4737 seclist
&& *seclist
;
4738 seclist
= &(*seclist
)->next
)
4740 segT sec
= *seclist
;
4741 segment_info_type
*seginfo
;
4744 flags
= bfd_get_section_flags (stdoutput
, sec
);
4745 if (flags
& SEC_DEBUGGING
)
4747 if (!(flags
& SEC_ALLOC
))
4750 seginfo
= seg_info (sec
);
4751 if (seginfo
&& seginfo
->frchainP
)
4753 fragS
*last_fragP
= 0;
4754 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4755 fragP
= fragP
->fr_next
)
4757 if (fragP
->fr_fix
!= 0
4758 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4760 if (last_fragP
== 0)
4762 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4763 _("assembly state not set for first frag in section %s"),
4768 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4769 fragP
->tc_frag_data
.is_no_density
=
4770 last_fragP
->tc_frag_data
.is_no_density
;
4771 fragP
->tc_frag_data
.is_no_transform
=
4772 last_fragP
->tc_frag_data
.is_no_transform
;
4773 fragP
->tc_frag_data
.use_longcalls
=
4774 last_fragP
->tc_frag_data
.use_longcalls
;
4775 fragP
->tc_frag_data
.use_absolute_literals
=
4776 last_fragP
->tc_frag_data
.use_absolute_literals
;
4779 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4788 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4790 void *unused ATTRIBUTE_UNUSED
)
4792 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4793 segment_info_type
*seginfo
= seg_info (sec
);
4794 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4796 if (flags
& SEC_CODE
)
4798 xtensa_isa isa
= xtensa_default_isa
;
4799 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4800 while (frag
!= NULL
)
4802 if (frag
->tc_frag_data
.is_branch_target
)
4805 addressT branch_align
, frag_addr
;
4808 xtensa_insnbuf_from_chars
4809 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4810 fmt
= xtensa_format_decode (isa
, insnbuf
);
4811 op_size
= xtensa_format_length (isa
, fmt
);
4812 branch_align
= 1 << branch_align_power (sec
);
4813 frag_addr
= frag
->fr_address
% branch_align
;
4814 if (frag_addr
+ op_size
> branch_align
)
4815 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4816 _("unaligned branch target: %d bytes at 0x%lx"),
4817 op_size
, (long) frag
->fr_address
);
4819 frag
= frag
->fr_next
;
4821 xtensa_insnbuf_free (isa
, insnbuf
);
4827 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4829 void *unused ATTRIBUTE_UNUSED
)
4831 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4832 segment_info_type
*seginfo
= seg_info (sec
);
4833 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4834 xtensa_isa isa
= xtensa_default_isa
;
4836 if (flags
& SEC_CODE
)
4838 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4839 while (frag
!= NULL
)
4841 if (frag
->tc_frag_data
.is_first_loop_insn
)
4847 xtensa_insnbuf_from_chars
4848 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4849 fmt
= xtensa_format_decode (isa
, insnbuf
);
4850 op_size
= xtensa_format_length (isa
, fmt
);
4851 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4853 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4854 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4855 _("unaligned loop: %d bytes at 0x%lx"),
4856 op_size
, (long) frag
->fr_address
);
4858 frag
= frag
->fr_next
;
4860 xtensa_insnbuf_free (isa
, insnbuf
);
4866 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4868 xtensa_isa isa
= xtensa_default_isa
;
4869 static xtensa_insnbuf insnbuf
= NULL
;
4870 static xtensa_insnbuf slotbuf
= NULL
;
4873 bfd_boolean alt_reloc
;
4874 xtensa_opcode opcode
;
4875 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4877 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4879 as_fatal (_("unexpected fix"));
4883 insnbuf
= xtensa_insnbuf_alloc (isa
);
4884 slotbuf
= xtensa_insnbuf_alloc (isa
);
4887 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4888 fmt
= xtensa_format_decode (isa
, insnbuf
);
4889 if (fmt
== XTENSA_UNDEFINED
)
4890 as_fatal (_("undecodable fix"));
4891 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4892 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4893 if (opcode
== XTENSA_UNDEFINED
)
4894 as_fatal (_("undecodable fix"));
4896 /* CONST16 immediates are not PC-relative, despite the fact that we
4897 reuse the normal PC-relative operand relocations for the low part
4898 of a CONST16 operand. */
4899 if (opcode
== xtensa_const16_opcode
)
4902 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4903 get_relaxable_immed (opcode
), val
,
4904 fixP
->fx_file
, fixP
->fx_line
);
4906 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4907 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4913 /* External Functions and Other GAS Hooks. */
4916 xtensa_target_format (void)
4918 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4923 xtensa_file_arch_init (bfd
*abfd
)
4925 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4930 md_number_to_chars (char *buf
, valueT val
, int n
)
4932 if (target_big_endian
)
4933 number_to_chars_bigendian (buf
, val
, n
);
4935 number_to_chars_littleendian (buf
, val
, n
);
4939 /* This function is called once, at assembler startup time. It should
4940 set up all the tables, etc. that the MD part of the assembler will
4946 segT current_section
= now_seg
;
4947 int current_subsec
= now_subseg
;
4950 xtensa_default_isa
= xtensa_isa_init (0, 0);
4951 isa
= xtensa_default_isa
;
4955 /* Set up the .literal, .fini.literal and .init.literal sections. */
4956 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4957 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4958 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4959 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4960 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4962 subseg_set (current_section
, current_subsec
);
4964 xg_init_vinsn (&cur_vinsn
);
4966 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4967 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4968 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4969 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4970 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4971 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4972 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4973 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4974 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4975 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4976 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4977 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4978 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4979 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4980 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4981 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4982 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4983 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4984 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4985 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4986 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4987 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4988 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4989 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4990 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4991 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4992 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4993 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4994 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4996 init_op_placement_info_table ();
4998 /* Set up the assembly state. */
4999 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5000 xtensa_set_frag_assembly_state (frag_now
);
5004 /* TC_INIT_FIX_DATA hook */
5007 xtensa_init_fix_data (fixS
*x
)
5009 x
->tc_fix_data
.slot
= 0;
5010 x
->tc_fix_data
.X_add_symbol
= NULL
;
5011 x
->tc_fix_data
.X_add_number
= 0;
5015 /* tc_frob_label hook */
5018 xtensa_frob_label (symbolS
*sym
)
5022 if (cur_vinsn
.inside_bundle
)
5024 as_bad (_("labels are not valid inside bundles"));
5028 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5030 /* Since the label was already attached to a frag associated with the
5031 previous basic block, it now needs to be reset to the current frag. */
5032 symbol_set_frag (sym
, frag_now
);
5033 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5035 if (generating_literals
)
5036 xtensa_add_literal_sym (sym
);
5038 xtensa_add_insn_label (sym
);
5040 if (symbol_get_tc (sym
)->is_loop_target
)
5042 if ((get_last_insn_flags (now_seg
, now_subseg
)
5043 & FLAG_IS_BAD_LOOPEND
) != 0)
5044 as_bad (_("invalid last instruction for a zero-overhead loop"));
5046 xtensa_set_frag_assembly_state (frag_now
);
5047 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5048 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5050 xtensa_set_frag_assembly_state (frag_now
);
5051 xtensa_move_labels (frag_now
, 0, TRUE
);
5054 /* No target aligning in the absolute section. */
5055 if (now_seg
!= absolute_section
5056 && do_align_targets ()
5057 && !is_unaligned_label (sym
)
5058 && !generating_literals
)
5060 xtensa_set_frag_assembly_state (frag_now
);
5062 frag_var (rs_machine_dependent
,
5064 RELAX_DESIRE_ALIGN_IF_TARGET
,
5065 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5066 xtensa_set_frag_assembly_state (frag_now
);
5067 xtensa_move_labels (frag_now
, 0, TRUE
);
5070 /* We need to mark the following properties even if we aren't aligning. */
5072 /* If the label is already known to be a branch target, i.e., a
5073 forward branch, mark the frag accordingly. Backward branches
5074 are handled by xg_add_branch_and_loop_targets. */
5075 if (symbol_get_tc (sym
)->is_branch_target
)
5076 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5078 /* Loops only go forward, so they can be identified here. */
5079 if (symbol_get_tc (sym
)->is_loop_target
)
5080 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5082 dwarf2_emit_label (sym
);
5086 /* tc_unrecognized_line hook */
5089 xtensa_unrecognized_line (int ch
)
5094 if (cur_vinsn
.inside_bundle
== 0)
5096 /* PR8110: Cannot emit line number info inside a FLIX bundle
5097 when using --gstabs. Temporarily disable debug info. */
5098 generate_lineno_debug ();
5099 if (debug_type
== DEBUG_STABS
)
5101 xt_saved_debug_type
= debug_type
;
5102 debug_type
= DEBUG_NONE
;
5105 cur_vinsn
.inside_bundle
= 1;
5109 as_bad (_("extra opening brace"));
5115 if (cur_vinsn
.inside_bundle
)
5116 finish_vinsn (&cur_vinsn
);
5119 as_bad (_("extra closing brace"));
5124 as_bad (_("syntax error"));
5131 /* md_flush_pending_output hook */
5134 xtensa_flush_pending_output (void)
5136 if (cur_vinsn
.inside_bundle
)
5137 as_bad (_("missing closing brace"));
5139 /* If there is a non-zero instruction fragment, close it. */
5140 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5142 frag_wane (frag_now
);
5144 xtensa_set_frag_assembly_state (frag_now
);
5146 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5148 xtensa_clear_insn_labels ();
5152 /* We had an error while parsing an instruction. The string might look
5153 like this: "insn arg1, arg2 }". If so, we need to see the closing
5154 brace and reset some fields. Otherwise, the vinsn never gets closed
5155 and the num_slots field will grow past the end of the array of slots,
5156 and bad things happen. */
5159 error_reset_cur_vinsn (void)
5161 if (cur_vinsn
.inside_bundle
)
5163 if (*input_line_pointer
== '}'
5164 || *(input_line_pointer
- 1) == '}'
5165 || *(input_line_pointer
- 2) == '}')
5166 xg_clear_vinsn (&cur_vinsn
);
5172 md_assemble (char *str
)
5174 xtensa_isa isa
= xtensa_default_isa
;
5175 char *opname
, *file_name
;
5177 bfd_boolean has_underbar
= FALSE
;
5178 char *arg_strings
[MAX_INSN_ARGS
];
5180 TInsn orig_insn
; /* Original instruction from the input. */
5182 tinsn_init (&orig_insn
);
5184 /* Split off the opcode. */
5185 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5186 opname
= xmalloc (opnamelen
+ 1);
5187 memcpy (opname
, str
, opnamelen
);
5188 opname
[opnamelen
] = '\0';
5190 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5193 as_bad (_("syntax error"));
5197 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5200 /* Check for an underbar prefix. */
5203 has_underbar
= TRUE
;
5207 orig_insn
.insn_type
= ITYPE_INSN
;
5209 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5211 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5212 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5214 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5215 if (fmt
== XTENSA_UNDEFINED
)
5217 as_bad (_("unknown opcode or format name '%s'"), opname
);
5218 error_reset_cur_vinsn ();
5221 if (!cur_vinsn
.inside_bundle
)
5223 as_bad (_("format names only valid inside bundles"));
5224 error_reset_cur_vinsn ();
5227 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5228 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5230 cur_vinsn
.format
= fmt
;
5231 free (has_underbar
? opname
- 1 : opname
);
5232 error_reset_cur_vinsn ();
5236 /* Parse the arguments. */
5237 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5239 as_bad (_("syntax error"));
5240 error_reset_cur_vinsn ();
5244 /* Free the opcode and argument strings, now that they've been parsed. */
5245 free (has_underbar
? opname
- 1 : opname
);
5247 while (num_args
-- > 0)
5248 free (arg_strings
[num_args
]);
5250 /* Get expressions for invisible operands. */
5251 if (get_invisible_operands (&orig_insn
))
5253 error_reset_cur_vinsn ();
5257 /* Check for the right number and type of arguments. */
5258 if (tinsn_check_arguments (&orig_insn
))
5260 error_reset_cur_vinsn ();
5264 /* A FLIX bundle may be spread across multiple input lines. We want to
5265 report the first such line in the debug information. Record the line
5266 number for each TInsn (assume the file name doesn't change), so the
5267 first line can be found later. */
5268 as_where (&file_name
, &orig_insn
.linenum
);
5270 xg_add_branch_and_loop_targets (&orig_insn
);
5272 /* Check that immediate value for ENTRY is >= 16. */
5273 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5275 expressionS
*exp
= &orig_insn
.tok
[2];
5276 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5277 as_warn (_("entry instruction with stack decrement < 16"));
5281 assemble_tokens (opcode, tok, ntok);
5282 expand the tokens from the orig_insn into the
5283 stack of instructions that will not expand
5284 unless required at relaxation time. */
5286 if (!cur_vinsn
.inside_bundle
)
5287 emit_single_op (&orig_insn
);
5288 else /* We are inside a bundle. */
5290 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5291 cur_vinsn
.num_slots
++;
5292 if (*input_line_pointer
== '}'
5293 || *(input_line_pointer
- 1) == '}'
5294 || *(input_line_pointer
- 2) == '}')
5295 finish_vinsn (&cur_vinsn
);
5298 /* We've just emitted a new instruction so clear the list of labels. */
5299 xtensa_clear_insn_labels ();
5303 /* HANDLE_ALIGN hook */
5305 /* For a .align directive, we mark the previous block with the alignment
5306 information. This will be placed in the object file in the
5307 property section corresponding to this section. */
5310 xtensa_handle_align (fragS
*fragP
)
5313 && ! fragP
->tc_frag_data
.is_literal
5314 && (fragP
->fr_type
== rs_align
5315 || fragP
->fr_type
== rs_align_code
)
5316 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5317 && fragP
->fr_offset
> 0
5318 && now_seg
!= bss_section
)
5320 fragP
->tc_frag_data
.is_align
= TRUE
;
5321 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5324 if (fragP
->fr_type
== rs_align_test
)
5327 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5329 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5330 _("unaligned entry instruction"));
5335 /* TC_FRAG_INIT hook */
5338 xtensa_frag_init (fragS
*frag
)
5340 xtensa_set_frag_assembly_state (frag
);
5345 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5351 /* Round up a section size to the appropriate boundary. */
5354 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5356 return size
; /* Byte alignment is fine. */
5361 md_pcrel_from (fixS
*fixP
)
5364 static xtensa_insnbuf insnbuf
= NULL
;
5365 static xtensa_insnbuf slotbuf
= NULL
;
5368 xtensa_opcode opcode
;
5371 xtensa_isa isa
= xtensa_default_isa
;
5372 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5373 bfd_boolean alt_reloc
;
5375 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5380 insnbuf
= xtensa_insnbuf_alloc (isa
);
5381 slotbuf
= xtensa_insnbuf_alloc (isa
);
5384 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5385 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5386 fmt
= xtensa_format_decode (isa
, insnbuf
);
5388 if (fmt
== XTENSA_UNDEFINED
)
5389 as_fatal (_("bad instruction format"));
5391 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5392 as_fatal (_("invalid relocation"));
5394 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5395 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5397 /* Check for "alternate" relocations (operand not specified). None
5398 of the current uses for these are really PC-relative. */
5399 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5401 if (opcode
!= xtensa_l32r_opcode
5402 && opcode
!= xtensa_const16_opcode
)
5403 as_fatal (_("invalid relocation for '%s' instruction"),
5404 xtensa_opcode_name (isa
, opcode
));
5408 opnum
= get_relaxable_immed (opcode
);
5410 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5411 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5413 as_bad_where (fixP
->fx_file
,
5415 _("invalid relocation for operand %d of '%s'"),
5416 opnum
, xtensa_opcode_name (isa
, opcode
));
5419 return 0 - opnd_value
;
5423 /* TC_FORCE_RELOCATION hook */
5426 xtensa_force_relocation (fixS
*fix
)
5428 switch (fix
->fx_r_type
)
5430 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5431 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5440 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5441 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5442 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5443 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5444 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5445 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5451 if (linkrelax
&& fix
->fx_addsy
5452 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5455 return generic_force_reloc (fix
);
5459 /* TC_VALIDATE_FIX_SUB hook */
5462 xtensa_validate_fix_sub (fixS
*fix
)
5464 segT add_symbol_segment
, sub_symbol_segment
;
5466 /* The difference of two symbols should be resolved by the assembler when
5467 linkrelax is not set. If the linker may relax the section containing
5468 the symbols, then an Xtensa DIFF relocation must be generated so that
5469 the linker knows to adjust the difference value. */
5470 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5473 /* Make sure both symbols are in the same segment, and that segment is
5474 "normal" and relaxable. If the segment is not "normal", then the
5475 fix is not valid. If the segment is not "relaxable", then the fix
5476 should have been handled earlier. */
5477 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5478 if (! SEG_NORMAL (add_symbol_segment
) ||
5479 ! relaxable_section (add_symbol_segment
))
5481 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5482 return (sub_symbol_segment
== add_symbol_segment
);
5486 /* NO_PSEUDO_DOT hook */
5488 /* This function has nothing to do with pseudo dots, but this is the
5489 nearest macro to where the check needs to take place. FIXME: This
5493 xtensa_check_inside_bundle (void)
5495 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5496 as_bad (_("directives are not valid inside bundles"));
5498 /* This function must always return FALSE because it is called via a
5499 macro that has nothing to do with bundling. */
5504 /* md_elf_section_change_hook */
5507 xtensa_elf_section_change_hook (void)
5509 /* Set up the assembly state. */
5510 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5511 xtensa_set_frag_assembly_state (frag_now
);
5515 /* tc_fix_adjustable hook */
5518 xtensa_fix_adjustable (fixS
*fixP
)
5520 /* An offset is not allowed in combination with the difference of two
5521 symbols, but that cannot be easily detected after a local symbol
5522 has been adjusted to a (section+offset) form. Return 0 so that such
5523 an fix will not be adjusted. */
5524 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5525 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5528 /* We need the symbol name for the VTABLE entries. */
5529 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5530 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5538 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5540 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5543 /* Subtracted symbols are only allowed for a few relocation types, and
5544 unless linkrelax is enabled, they should not make it to this point. */
5545 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5546 || fixP
->fx_r_type
== BFD_RELOC_16
5547 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5550 switch (fixP
->fx_r_type
)
5557 switch (fixP
->fx_r_type
)
5560 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5563 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5566 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5572 /* An offset is only allowed when it results from adjusting a
5573 local symbol into a section-relative offset. If the offset
5574 came from the original expression, tc_fix_adjustable will have
5575 prevented the fix from being converted to a section-relative
5576 form so that we can flag the error here. */
5577 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5579 _("cannot represent subtraction with an offset"));
5581 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5582 - S_GET_VALUE (fixP
->fx_subsy
));
5584 /* The difference value gets written out, and the DIFF reloc
5585 identifies the address of the subtracted symbol (i.e., the one
5586 with the lowest address). */
5588 fixP
->fx_offset
-= val
;
5589 fixP
->fx_subsy
= NULL
;
5591 else if (! fixP
->fx_addsy
)
5598 case BFD_RELOC_XTENSA_PLT
:
5599 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5600 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5603 case BFD_RELOC_XTENSA_SLOT0_OP
:
5604 case BFD_RELOC_XTENSA_SLOT1_OP
:
5605 case BFD_RELOC_XTENSA_SLOT2_OP
:
5606 case BFD_RELOC_XTENSA_SLOT3_OP
:
5607 case BFD_RELOC_XTENSA_SLOT4_OP
:
5608 case BFD_RELOC_XTENSA_SLOT5_OP
:
5609 case BFD_RELOC_XTENSA_SLOT6_OP
:
5610 case BFD_RELOC_XTENSA_SLOT7_OP
:
5611 case BFD_RELOC_XTENSA_SLOT8_OP
:
5612 case BFD_RELOC_XTENSA_SLOT9_OP
:
5613 case BFD_RELOC_XTENSA_SLOT10_OP
:
5614 case BFD_RELOC_XTENSA_SLOT11_OP
:
5615 case BFD_RELOC_XTENSA_SLOT12_OP
:
5616 case BFD_RELOC_XTENSA_SLOT13_OP
:
5617 case BFD_RELOC_XTENSA_SLOT14_OP
:
5620 /* Write the tentative value of a PC-relative relocation to a
5621 local symbol into the instruction. The value will be ignored
5622 by the linker, and it makes the object file disassembly
5623 readable when all branch targets are encoded in relocations. */
5625 assert (fixP
->fx_addsy
);
5626 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5627 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5629 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5630 - md_pcrel_from (fixP
));
5631 (void) xg_apply_fix_value (fixP
, val
);
5634 else if (! fixP
->fx_addsy
)
5637 if (xg_apply_fix_value (fixP
, val
))
5642 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5643 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5648 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5649 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5651 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5652 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5653 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5654 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5655 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5656 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5657 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5658 /* These all need to be resolved at link-time. Do nothing now. */
5661 case BFD_RELOC_VTABLE_INHERIT
:
5662 case BFD_RELOC_VTABLE_ENTRY
:
5667 as_bad (_("unhandled local relocation fix %s"),
5668 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5674 md_atof (int type
, char *litP
, int *sizeP
)
5677 LITTLENUM_TYPE words
[4];
5693 return "bad call to md_atof";
5696 t
= atof_ieee (input_line_pointer
, type
, words
);
5698 input_line_pointer
= t
;
5702 for (i
= prec
- 1; i
>= 0; i
--)
5705 if (target_big_endian
)
5706 idx
= (prec
- 1 - i
);
5708 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5717 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5719 return total_frag_text_expansion (fragP
);
5723 /* Translate internal representation of relocation info to BFD target
5727 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5731 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5732 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5733 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5734 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5736 /* Make sure none of our internal relocations make it this far.
5737 They'd better have been fully resolved by this point. */
5738 assert ((int) fixp
->fx_r_type
> 0);
5740 reloc
->addend
= fixp
->fx_offset
;
5742 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5743 if (reloc
->howto
== NULL
)
5745 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5746 _("cannot represent `%s' relocation in object file"),
5747 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5748 free (reloc
->sym_ptr_ptr
);
5753 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5754 as_fatal (_("internal error? cannot generate `%s' relocation"),
5755 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5761 /* Checks for resource conflicts between instructions. */
5763 /* The func unit stuff could be implemented as bit-vectors rather
5764 than the iterative approach here. If it ends up being too
5765 slow, we will switch it. */
5768 new_resource_table (void *data
,
5771 unit_num_copies_func uncf
,
5772 opcode_num_units_func onuf
,
5773 opcode_funcUnit_use_unit_func ouuf
,
5774 opcode_funcUnit_use_stage_func ousf
)
5777 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5779 rt
->cycles
= cycles
;
5780 rt
->allocated_cycles
= cycles
;
5782 rt
->unit_num_copies
= uncf
;
5783 rt
->opcode_num_units
= onuf
;
5784 rt
->opcode_unit_use
= ouuf
;
5785 rt
->opcode_unit_stage
= ousf
;
5787 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5788 for (i
= 0; i
< cycles
; i
++)
5789 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5796 clear_resource_table (resource_table
*rt
)
5799 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5800 for (j
= 0; j
< rt
->num_units
; j
++)
5801 rt
->units
[i
][j
] = 0;
5805 /* We never shrink it, just fake it into thinking so. */
5808 resize_resource_table (resource_table
*rt
, int cycles
)
5812 rt
->cycles
= cycles
;
5813 if (cycles
<= rt
->allocated_cycles
)
5816 old_cycles
= rt
->allocated_cycles
;
5817 rt
->allocated_cycles
= cycles
;
5819 rt
->units
= xrealloc (rt
->units
,
5820 rt
->allocated_cycles
* sizeof (unsigned char *));
5821 for (i
= 0; i
< old_cycles
; i
++)
5822 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5823 rt
->num_units
* sizeof (unsigned char));
5824 for (i
= old_cycles
; i
< cycles
; i
++)
5825 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5830 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5833 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5835 for (i
= 0; i
< uses
; i
++)
5837 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5838 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5839 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5840 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5841 if (copies_in_use
>= copies
)
5849 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5852 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5854 for (i
= 0; i
< uses
; i
++)
5856 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5857 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5858 /* Note that this allows resources to be oversubscribed. That's
5859 essential to the way the optional scheduler works.
5860 resources_available reports when a resource is over-subscribed,
5861 so it's easy to tell. */
5862 rt
->units
[stage
+ cycle
][unit
]++;
5868 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5871 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5873 for (i
= 0; i
< uses
; i
++)
5875 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5876 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5877 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5878 rt
->units
[stage
+ cycle
][unit
]--;
5883 /* Wrapper functions make parameterized resource reservation
5887 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5889 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5895 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5897 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5902 /* Note that this function does not check issue constraints, but
5903 solely whether the hardware is available to execute the given
5904 instructions together. It also doesn't check if the tinsns
5905 write the same state, or access the same tieports. That is
5906 checked by check_t1_t2_reads_and_writes. */
5909 resources_conflict (vliw_insn
*vinsn
)
5912 static resource_table
*rt
= NULL
;
5914 /* This is the most common case by far. Optimize it. */
5915 if (vinsn
->num_slots
== 1)
5920 xtensa_isa isa
= xtensa_default_isa
;
5921 rt
= new_resource_table
5922 (isa
, xtensa_isa_num_pipe_stages (isa
),
5923 xtensa_isa_num_funcUnits (isa
),
5924 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5925 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5926 opcode_funcUnit_use_unit
,
5927 opcode_funcUnit_use_stage
);
5930 clear_resource_table (rt
);
5932 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5934 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5936 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5943 /* finish_vinsn, emit_single_op and helper functions. */
5945 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5946 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5947 static void xg_assemble_vliw_tokens (vliw_insn
*);
5950 /* We have reached the end of a bundle; emit into the frag. */
5953 finish_vinsn (vliw_insn
*vinsn
)
5960 if (find_vinsn_conflicts (vinsn
))
5962 xg_clear_vinsn (vinsn
);
5966 /* First, find a format that works. */
5967 if (vinsn
->format
== XTENSA_UNDEFINED
)
5968 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5970 if (vinsn
->format
== XTENSA_UNDEFINED
)
5972 as_where (&file_name
, &line
);
5973 as_bad_where (file_name
, line
,
5974 _("couldn't find a valid instruction format"));
5975 fprintf (stderr
, _(" ops were: "));
5976 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5977 fprintf (stderr
, _(" %s;"),
5978 xtensa_opcode_name (xtensa_default_isa
,
5979 vinsn
->slots
[i
].opcode
));
5980 fprintf (stderr
, _("\n"));
5981 xg_clear_vinsn (vinsn
);
5985 if (vinsn
->num_slots
5986 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5988 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5989 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5990 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5992 xg_clear_vinsn (vinsn
);
5996 if (resources_conflict (vinsn
))
5998 as_where (&file_name
, &line
);
5999 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6000 fprintf (stderr
, " ops were: ");
6001 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6002 fprintf (stderr
, " %s;",
6003 xtensa_opcode_name (xtensa_default_isa
,
6004 vinsn
->slots
[i
].opcode
));
6005 fprintf (stderr
, "\n");
6006 xg_clear_vinsn (vinsn
);
6010 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6012 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6014 symbolS
*lit_sym
= NULL
;
6016 bfd_boolean e
= FALSE
;
6017 bfd_boolean saved_density
= density_supported
;
6019 /* We don't want to narrow ops inside multi-slot bundles. */
6020 if (vinsn
->num_slots
> 1)
6021 density_supported
= FALSE
;
6023 istack_init (&slotstack
);
6024 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6026 vinsn
->slots
[i
].opcode
=
6027 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6029 vinsn
->slots
[i
].ntok
= 0;
6032 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6038 density_supported
= saved_density
;
6042 xg_clear_vinsn (vinsn
);
6046 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6048 TInsn
*insn
= &slotstack
.insn
[j
];
6049 if (insn
->insn_type
== ITYPE_LITERAL
)
6051 assert (lit_sym
== NULL
);
6052 lit_sym
= xg_assemble_literal (insn
);
6056 assert (insn
->insn_type
== ITYPE_INSN
);
6058 xg_resolve_literals (insn
, lit_sym
);
6059 if (j
!= slotstack
.ninsn
- 1)
6060 emit_single_op (insn
);
6064 if (vinsn
->num_slots
> 1)
6066 if (opcode_fits_format_slot
6067 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6070 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6074 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6075 if (vinsn
->format
== XTENSA_UNDEFINED
)
6076 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6078 vinsn
->slots
[i
].opcode
6079 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6082 vinsn
->slots
[i
].ntok
= 0;
6087 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6088 vinsn
->format
= XTENSA_UNDEFINED
;
6093 /* Now check resource conflicts on the modified bundle. */
6094 if (resources_conflict (vinsn
))
6096 as_where (&file_name
, &line
);
6097 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6098 fprintf (stderr
, " ops were: ");
6099 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6100 fprintf (stderr
, " %s;",
6101 xtensa_opcode_name (xtensa_default_isa
,
6102 vinsn
->slots
[i
].opcode
));
6103 fprintf (stderr
, "\n");
6104 xg_clear_vinsn (vinsn
);
6108 /* First, find a format that works. */
6109 if (vinsn
->format
== XTENSA_UNDEFINED
)
6110 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6112 xg_assemble_vliw_tokens (vinsn
);
6114 xg_clear_vinsn (vinsn
);
6118 /* Given an vliw instruction, what conflicts are there in register
6119 usage and in writes to states and queues?
6121 This function does two things:
6122 1. Reports an error when a vinsn contains illegal combinations
6123 of writes to registers states or queues.
6124 2. Marks individual tinsns as not relaxable if the combination
6125 contains antidependencies.
6127 Job 2 handles things like swap semantics in instructions that need
6128 to be relaxed. For example,
6132 normally would be relaxed to
6137 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6139 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6141 then we can't relax it into
6144 { add a0, a1, a0 ; add a2, a0, a4 ; }
6146 because the value of a0 is trashed before the second add can read it. */
6148 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6151 find_vinsn_conflicts (vliw_insn
*vinsn
)
6155 xtensa_isa isa
= xtensa_default_isa
;
6157 assert (!past_xtensa_end
);
6159 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6161 TInsn
*op1
= &vinsn
->slots
[i
];
6162 if (op1
->is_specific_opcode
)
6163 op1
->keep_wide
= TRUE
;
6165 op1
->keep_wide
= FALSE
;
6168 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6170 TInsn
*op1
= &vinsn
->slots
[i
];
6172 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6175 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6179 TInsn
*op2
= &vinsn
->slots
[j
];
6180 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6181 switch (conflict_type
)
6184 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6185 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6186 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6189 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6190 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6191 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6194 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6195 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6196 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6199 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6200 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6201 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6204 /* Everything is OK. */
6207 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6208 || conflict_type
== 'a');
6215 as_bad (_("multiple branches or jumps in the same bundle"));
6223 /* Check how the state used by t1 and t2 relate.
6226 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6227 case B: no relationship between what is read and written (both could
6228 read the same reg though)
6229 case C: t1 writes a register t2 writes (a register conflict within a
6231 case D: t1 writes a state that t2 also writes
6232 case E: t1 writes a tie queue that t2 also writes
6233 case F: two volatile queue accesses
6237 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6239 xtensa_isa isa
= xtensa_default_isa
;
6240 xtensa_regfile t1_regfile
, t2_regfile
;
6242 int t1_base_reg
, t1_last_reg
;
6243 int t2_base_reg
, t2_last_reg
;
6244 char t1_inout
, t2_inout
;
6246 char conflict
= 'b';
6251 bfd_boolean t1_volatile
= FALSE
;
6252 bfd_boolean t2_volatile
= FALSE
;
6254 /* Check registers. */
6255 for (j
= 0; j
< t2
->ntok
; j
++)
6257 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6260 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6261 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6262 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6264 for (i
= 0; i
< t1
->ntok
; i
++)
6266 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6269 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6271 if (t1_regfile
!= t2_regfile
)
6274 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6275 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6277 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6278 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6280 if (t1_inout
== 'm' || t1_inout
== 'o'
6281 || t2_inout
== 'm' || t2_inout
== 'o')
6288 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6289 t1_last_reg
= (t1_base_reg
6290 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6292 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6294 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6296 if (t1_reg
!= t2_reg
)
6299 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6305 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6311 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6319 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6320 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6321 for (j
= 0; j
< t2_states
; j
++)
6323 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6324 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6325 for (i
= 0; i
< t1_states
; i
++)
6327 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6328 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6332 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6338 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6344 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6349 /* Check tieports. */
6350 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6351 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6352 for (j
= 0; j
< t2_interfaces
; j
++)
6354 xtensa_interface t2_int
6355 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6356 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6358 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6359 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6362 for (i
= 0; i
< t1_interfaces
; i
++)
6364 xtensa_interface t1_int
6365 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6366 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6368 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6369 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6372 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6375 if (t1_int
!= t2_int
)
6378 if (t2_inout
== 'i' && t1_inout
== 'o')
6384 if (t1_inout
== 'i' && t2_inout
== 'o')
6390 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6399 static xtensa_format
6400 xg_find_narrowest_format (vliw_insn
*vinsn
)
6402 /* Right now we assume that the ops within the vinsn are properly
6403 ordered for the slots that the programmer wanted them in. In
6404 other words, we don't rearrange the ops in hopes of finding a
6405 better format. The scheduler handles that. */
6407 xtensa_isa isa
= xtensa_default_isa
;
6408 xtensa_format format
;
6409 vliw_insn v_copy
= *vinsn
;
6410 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6412 if (vinsn
->num_slots
== 1)
6413 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6415 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6418 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6422 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6424 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6426 v_copy
.slots
[slot
].opcode
=
6427 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6428 v_copy
.slots
[slot
].ntok
= 0;
6431 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6434 else if (v_copy
.num_slots
> 1)
6437 /* Try the widened version. */
6438 if (!v_copy
.slots
[slot
].keep_wide
6439 && !v_copy
.slots
[slot
].is_specific_opcode
6440 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6442 && opcode_fits_format_slot (widened
.opcode
,
6445 v_copy
.slots
[slot
] = widened
;
6450 if (fit
== v_copy
.num_slots
)
6453 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6454 vinsn
->format
= format
;
6460 if (format
== xtensa_isa_num_formats (isa
))
6461 return XTENSA_UNDEFINED
;
6467 /* Return the additional space needed in a frag
6468 for possible relaxations of any ops in a VLIW insn.
6469 Also fill out the relaxations that might be required of
6470 each tinsn in the vinsn. */
6473 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6475 bfd_boolean finish_frag
= FALSE
;
6476 int extra_space
= 0;
6479 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6481 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6482 if (!tinsn_has_symbolic_operands (tinsn
))
6484 /* A narrow instruction could be widened later to help
6485 alignment issues. */
6486 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6487 && !tinsn
->is_specific_opcode
6488 && vinsn
->num_slots
== 1)
6490 /* Difference in bytes between narrow and wide insns... */
6492 tinsn
->subtype
= RELAX_NARROW
;
6497 if (workaround_b_j_loop_end
6498 && tinsn
->opcode
== xtensa_jx_opcode
6499 && use_transform ())
6501 /* Add 2 of these. */
6502 extra_space
+= 3; /* for the nop size */
6503 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6506 /* Need to assemble it with space for the relocation. */
6507 if (xg_is_relaxable_insn (tinsn
, 0)
6508 && !tinsn
->is_specific_opcode
)
6510 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6511 int max_literal_size
=
6512 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6514 tinsn
->literal_space
= max_literal_size
;
6516 tinsn
->subtype
= RELAX_IMMED
;
6517 extra_space
+= max_size
;
6521 /* A fix record will be added for this instruction prior
6522 to relaxation, so make it end the frag. */
6527 *pfinish_frag
= finish_frag
;
6533 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6535 xtensa_isa isa
= xtensa_default_isa
;
6536 int slot
, chosen_slot
;
6538 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6539 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6540 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6542 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6543 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6545 if (slot
== chosen_slot
)
6546 vinsn
->slots
[slot
] = *tinsn
;
6549 vinsn
->slots
[slot
].opcode
=
6550 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6551 vinsn
->slots
[slot
].ntok
= 0;
6552 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6559 emit_single_op (TInsn
*orig_insn
)
6562 IStack istack
; /* put instructions into here */
6563 symbolS
*lit_sym
= NULL
;
6564 symbolS
*label_sym
= NULL
;
6566 istack_init (&istack
);
6568 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6569 Because the scheduling and bundling characteristics of movi and
6570 l32r or const16 are so different, we can do much better if we relax
6571 it prior to scheduling and bundling, rather than after. */
6572 if ((orig_insn
->opcode
== xtensa_movi_opcode
6573 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6574 && !cur_vinsn
.inside_bundle
6575 && (orig_insn
->tok
[1].X_op
== O_symbol
6576 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6577 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6579 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6582 for (i
= 0; i
< istack
.ninsn
; i
++)
6584 TInsn
*insn
= &istack
.insn
[i
];
6585 switch (insn
->insn_type
)
6588 assert (lit_sym
== NULL
);
6589 lit_sym
= xg_assemble_literal (insn
);
6593 static int relaxed_sym_idx
= 0;
6594 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6595 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6597 assert (label_sym
== NULL
);
6598 label_sym
= symbol_find_or_make (label
);
6607 xg_resolve_literals (insn
, lit_sym
);
6609 xg_resolve_labels (insn
, label_sym
);
6611 bundle_tinsn (insn
, &v
);
6626 total_frag_text_expansion (fragS
*fragP
)
6629 int total_expansion
= 0;
6631 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6632 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6634 return total_expansion
;
6638 /* Emit a vliw instruction to the current fragment. */
6641 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6643 bfd_boolean finish_frag
;
6644 bfd_boolean is_jump
= FALSE
;
6645 bfd_boolean is_branch
= FALSE
;
6646 xtensa_isa isa
= xtensa_default_isa
;
6652 unsigned current_line
, best_linenum
;
6655 best_linenum
= UINT_MAX
;
6657 if (generating_literals
)
6659 static int reported
= 0;
6661 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6662 _("cannot assemble into a literal fragment"));
6669 if (frag_now_fix () != 0
6670 && (! frag_now
->tc_frag_data
.is_insn
6671 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6672 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6673 || (directive_state
[directive_longcalls
]
6674 != frag_now
->tc_frag_data
.use_longcalls
)
6675 || (directive_state
[directive_absolute_literals
]
6676 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6678 frag_wane (frag_now
);
6680 xtensa_set_frag_assembly_state (frag_now
);
6683 if (workaround_a0_b_retw
6684 && vinsn
->num_slots
== 1
6685 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6686 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6687 && use_transform ())
6689 has_a0_b_retw
= TRUE
;
6691 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6692 After the first assembly pass we will check all of them and
6693 add a nop if needed. */
6694 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6695 frag_var (rs_machine_dependent
, 4, 4,
6696 RELAX_ADD_NOP_IF_A0_B_RETW
,
6697 frag_now
->fr_symbol
,
6698 frag_now
->fr_offset
,
6700 xtensa_set_frag_assembly_state (frag_now
);
6701 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6702 frag_var (rs_machine_dependent
, 4, 4,
6703 RELAX_ADD_NOP_IF_A0_B_RETW
,
6704 frag_now
->fr_symbol
,
6705 frag_now
->fr_offset
,
6707 xtensa_set_frag_assembly_state (frag_now
);
6710 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6712 /* See if the instruction implies an aligned section. */
6713 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6714 record_alignment (now_seg
, 2);
6716 /* Also determine the best line number for debug info. */
6717 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6718 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6721 /* Special cases for instructions that force an alignment... */
6722 /* None of these opcodes are bundle-able. */
6723 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6727 xtensa_set_frag_assembly_state (frag_now
);
6728 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6730 max_fill
= get_text_align_max_fill_size
6731 (get_text_align_power (xtensa_fetch_width
),
6732 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6734 if (use_transform ())
6735 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6736 RELAX_ALIGN_NEXT_OPCODE
,
6737 frag_now
->fr_symbol
,
6738 frag_now
->fr_offset
,
6741 frag_var (rs_machine_dependent
, 0, 0,
6742 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6743 xtensa_set_frag_assembly_state (frag_now
);
6745 xtensa_move_labels (frag_now
, 0, FALSE
);
6748 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6749 && !vinsn
->slots
[0].is_specific_opcode
)
6751 xtensa_mark_literal_pool_location ();
6752 xtensa_move_labels (frag_now
, 0, TRUE
);
6753 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6756 if (vinsn
->num_slots
== 1)
6758 if (workaround_a0_b_retw
&& use_transform ())
6759 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6760 is_register_writer (&vinsn
->slots
[0], "a", 0));
6762 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6763 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6766 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6768 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6770 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6772 /* vinsn_to_insnbuf will produce the error. */
6773 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6775 f
= frag_more (insn_size
+ extra_space
);
6776 xtensa_set_frag_assembly_state (frag_now
);
6777 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6780 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6781 if (vinsn
->format
== XTENSA_UNDEFINED
)
6784 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6786 /* Temporarily set the logical line number to the one we want to appear
6787 in the debug information. */
6788 as_where (¤t_file
, ¤t_line
);
6789 new_logical_line (current_file
, best_linenum
);
6790 dwarf2_emit_insn (insn_size
+ extra_space
);
6791 new_logical_line (current_file
, current_line
);
6793 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6795 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6796 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6797 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6798 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6799 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6800 if (tinsn
->literal_space
!= 0)
6801 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6803 if (tinsn
->subtype
== RELAX_NARROW
)
6804 assert (vinsn
->num_slots
== 1);
6805 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6807 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6810 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6811 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6815 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6816 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6820 frag_variant (rs_machine_dependent
,
6821 extra_space
, extra_space
, RELAX_SLOTS
,
6822 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6823 xtensa_set_frag_assembly_state (frag_now
);
6826 /* Special cases for loops:
6827 close_loop_end should be inserted AFTER short_loop.
6828 Make sure that CLOSE loops are processed BEFORE short_loops
6829 when converting them. */
6831 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6832 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6833 && !vinsn
->slots
[0].is_specific_opcode
)
6835 if (workaround_short_loop
&& use_transform ())
6837 maybe_has_short_loop
= TRUE
;
6838 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6839 frag_var (rs_machine_dependent
, 4, 4,
6840 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6841 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6842 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6843 frag_var (rs_machine_dependent
, 4, 4,
6844 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6845 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6848 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6849 loop at least 12 bytes away from another loop's end. */
6850 if (workaround_close_loop_end
&& use_transform ())
6852 maybe_has_close_loop_end
= TRUE
;
6853 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6854 frag_var (rs_machine_dependent
, 12, 12,
6855 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6856 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6860 if (use_transform ())
6864 assert (finish_frag
);
6865 frag_var (rs_machine_dependent
,
6866 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6868 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6869 xtensa_set_frag_assembly_state (frag_now
);
6871 else if (is_branch
&& do_align_targets ())
6873 assert (finish_frag
);
6874 frag_var (rs_machine_dependent
,
6875 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6876 RELAX_MAYBE_UNREACHABLE
,
6877 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6878 xtensa_set_frag_assembly_state (frag_now
);
6879 frag_var (rs_machine_dependent
,
6881 RELAX_MAYBE_DESIRE_ALIGN
,
6882 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6883 xtensa_set_frag_assembly_state (frag_now
);
6887 /* Now, if the original opcode was a call... */
6888 if (do_align_targets ()
6889 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6891 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6892 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6893 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6894 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6895 xtensa_set_frag_assembly_state (frag_now
);
6898 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6900 frag_wane (frag_now
);
6902 xtensa_set_frag_assembly_state (frag_now
);
6907 /* xtensa_end and helper functions. */
6909 static void xtensa_cleanup_align_frags (void);
6910 static void xtensa_fix_target_frags (void);
6911 static void xtensa_mark_narrow_branches (void);
6912 static void xtensa_mark_zcl_first_insns (void);
6913 static void xtensa_fix_a0_b_retw_frags (void);
6914 static void xtensa_fix_b_j_loop_end_frags (void);
6915 static void xtensa_fix_close_loop_end_frags (void);
6916 static void xtensa_fix_short_loop_frags (void);
6917 static void xtensa_sanity_check (void);
6922 directive_balance ();
6923 xtensa_flush_pending_output ();
6925 past_xtensa_end
= TRUE
;
6927 xtensa_move_literals ();
6929 xtensa_reorder_segments ();
6930 xtensa_cleanup_align_frags ();
6931 xtensa_fix_target_frags ();
6932 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6933 xtensa_fix_a0_b_retw_frags ();
6934 if (workaround_b_j_loop_end
)
6935 xtensa_fix_b_j_loop_end_frags ();
6937 /* "close_loop_end" should be processed BEFORE "short_loop". */
6938 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6939 xtensa_fix_close_loop_end_frags ();
6941 if (workaround_short_loop
&& maybe_has_short_loop
)
6942 xtensa_fix_short_loop_frags ();
6944 xtensa_mark_narrow_branches ();
6945 xtensa_mark_zcl_first_insns ();
6947 xtensa_sanity_check ();
6952 xtensa_cleanup_align_frags (void)
6956 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6959 /* Walk over all of the fragments in a subsection. */
6960 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6962 if ((fragP
->fr_type
== rs_align
6963 || fragP
->fr_type
== rs_align_code
6964 || (fragP
->fr_type
== rs_machine_dependent
6965 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6966 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6967 && fragP
->fr_fix
== 0)
6969 fragS
*next
= fragP
->fr_next
;
6972 && next
->fr_fix
== 0
6973 && next
->fr_type
== rs_machine_dependent
6974 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6977 next
= next
->fr_next
;
6980 /* If we don't widen branch targets, then they
6981 will be easier to align. */
6982 if (fragP
->tc_frag_data
.is_branch_target
6983 && fragP
->fr_opcode
== fragP
->fr_literal
6984 && fragP
->fr_type
== rs_machine_dependent
6985 && fragP
->fr_subtype
== RELAX_SLOTS
6986 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6988 if (fragP
->fr_type
== rs_machine_dependent
6989 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6990 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6996 /* Re-process all of the fragments looking to convert all of the
6997 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6998 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6999 Otherwise, convert to a .fill 0. */
7002 xtensa_fix_target_frags (void)
7006 /* When this routine is called, all of the subsections are still intact
7007 so we walk over subsections instead of sections. */
7008 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7012 /* Walk over all of the fragments in a subsection. */
7013 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7015 if (fragP
->fr_type
== rs_machine_dependent
7016 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7018 if (next_frag_is_branch_target (fragP
))
7019 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7028 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7031 xtensa_mark_narrow_branches (void)
7035 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7038 /* Walk over all of the fragments in a subsection. */
7039 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7041 if (fragP
->fr_type
== rs_machine_dependent
7042 && fragP
->fr_subtype
== RELAX_SLOTS
7043 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7047 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7048 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7050 if (vinsn
.num_slots
== 1
7051 && xtensa_opcode_is_branch (xtensa_default_isa
,
7052 vinsn
.slots
[0].opcode
)
7053 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7054 && is_narrow_branch_guaranteed_in_range (fragP
,
7057 fragP
->fr_subtype
= RELAX_SLOTS
;
7058 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7059 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7067 /* A branch is typically widened only when its target is out of
7068 range. However, we would like to widen them to align a subsequent
7069 branch target when possible.
7071 Because the branch relaxation code is so convoluted, the optimal solution
7072 (combining the two cases) is difficult to get right in all circumstances.
7073 We therefore go with an "almost as good" solution, where we only
7074 use for alignment narrow branches that definitely will not expand to a
7075 jump and a branch. These functions find and mark these cases. */
7077 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7078 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7079 We start counting beginning with the frag after the 2-byte branch, so the
7080 maximum offset is (4 - 2) + 63 = 65. */
7081 #define MAX_IMMED6 65
7083 static offsetT
unrelaxed_frag_max_size (fragS
*);
7086 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7088 const expressionS
*expr
= &tinsn
->tok
[1];
7089 symbolS
*symbolP
= expr
->X_add_symbol
;
7090 offsetT max_distance
= expr
->X_add_number
;
7093 if (expr
->X_op
!= O_symbol
)
7096 target_frag
= symbol_get_frag (symbolP
);
7098 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7099 if (is_branch_jmp_to_next (tinsn
, fragP
))
7102 /* The branch doesn't branch over it's own frag,
7103 but over the subsequent ones. */
7104 fragP
= fragP
->fr_next
;
7105 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7107 max_distance
+= unrelaxed_frag_max_size (fragP
);
7108 fragP
= fragP
->fr_next
;
7110 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7117 xtensa_mark_zcl_first_insns (void)
7121 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7124 /* Walk over all of the fragments in a subsection. */
7125 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7127 if (fragP
->fr_type
== rs_machine_dependent
7128 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7129 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7131 /* Find the loop frag. */
7132 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7133 /* Find the first insn frag. */
7134 targ_frag
= next_non_empty_frag (targ_frag
);
7136 /* Of course, sometimes (mostly for toy test cases) a
7137 zero-cost loop instruction is the last in a section. */
7140 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7141 /* Do not widen a frag that is the first instruction of a
7142 zero-cost loop. It makes that loop harder to align. */
7143 if (targ_frag
->fr_type
== rs_machine_dependent
7144 && targ_frag
->fr_subtype
== RELAX_SLOTS
7145 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7148 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7149 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7152 frag_wane (targ_frag
);
7153 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7157 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7165 /* Re-process all of the fragments looking to convert all of the
7166 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7167 conditional branch or a retw/retw.n, convert this frag to one that
7168 will generate a NOP. In any case close it off with a .fill 0. */
7170 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7173 xtensa_fix_a0_b_retw_frags (void)
7177 /* When this routine is called, all of the subsections are still intact
7178 so we walk over subsections instead of sections. */
7179 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7183 /* Walk over all of the fragments in a subsection. */
7184 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7186 if (fragP
->fr_type
== rs_machine_dependent
7187 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7189 if (next_instrs_are_b_retw (fragP
))
7191 if (fragP
->tc_frag_data
.is_no_transform
)
7192 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7194 relax_frag_add_nop (fragP
);
7204 next_instrs_are_b_retw (fragS
*fragP
)
7206 xtensa_opcode opcode
;
7208 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7209 static xtensa_insnbuf insnbuf
= NULL
;
7210 static xtensa_insnbuf slotbuf
= NULL
;
7211 xtensa_isa isa
= xtensa_default_isa
;
7214 bfd_boolean branch_seen
= FALSE
;
7218 insnbuf
= xtensa_insnbuf_alloc (isa
);
7219 slotbuf
= xtensa_insnbuf_alloc (isa
);
7222 if (next_fragP
== NULL
)
7225 /* Check for the conditional branch. */
7226 xtensa_insnbuf_from_chars
7227 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7228 fmt
= xtensa_format_decode (isa
, insnbuf
);
7229 if (fmt
== XTENSA_UNDEFINED
)
7232 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7234 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7235 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7237 branch_seen
= (branch_seen
7238 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7244 offset
+= xtensa_format_length (isa
, fmt
);
7245 if (offset
== next_fragP
->fr_fix
)
7247 next_fragP
= next_non_empty_frag (next_fragP
);
7251 if (next_fragP
== NULL
)
7254 /* Check for the retw/retw.n. */
7255 xtensa_insnbuf_from_chars
7256 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7257 fmt
= xtensa_format_decode (isa
, insnbuf
);
7259 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7260 have no problems. */
7261 if (fmt
== XTENSA_UNDEFINED
7262 || xtensa_format_num_slots (isa
, fmt
) != 1)
7265 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7266 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7268 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7275 /* Re-process all of the fragments looking to convert all of the
7276 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7277 loop end label, convert this frag to one that will generate a NOP.
7278 In any case close it off with a .fill 0. */
7280 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7283 xtensa_fix_b_j_loop_end_frags (void)
7287 /* When this routine is called, all of the subsections are still intact
7288 so we walk over subsections instead of sections. */
7289 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7293 /* Walk over all of the fragments in a subsection. */
7294 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7296 if (fragP
->fr_type
== rs_machine_dependent
7297 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7299 if (next_instr_is_loop_end (fragP
))
7301 if (fragP
->tc_frag_data
.is_no_transform
)
7302 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7304 relax_frag_add_nop (fragP
);
7314 next_instr_is_loop_end (fragS
*fragP
)
7316 const fragS
*next_fragP
;
7318 if (next_frag_is_loop_target (fragP
))
7321 next_fragP
= next_non_empty_frag (fragP
);
7322 if (next_fragP
== NULL
)
7325 if (!next_frag_is_loop_target (next_fragP
))
7328 /* If the size is >= 3 then there is more than one instruction here.
7329 The hardware bug will not fire. */
7330 if (next_fragP
->fr_fix
> 3)
7337 /* Re-process all of the fragments looking to convert all of the
7338 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7339 not MY loop's loop end within 12 bytes, add enough nops here to
7340 make it at least 12 bytes away. In any case close it off with a
7343 static offsetT min_bytes_to_other_loop_end
7344 (fragS
*, fragS
*, offsetT
, offsetT
);
7347 xtensa_fix_close_loop_end_frags (void)
7351 /* When this routine is called, all of the subsections are still intact
7352 so we walk over subsections instead of sections. */
7353 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7357 fragS
*current_target
= NULL
;
7358 offsetT current_offset
= 0;
7360 /* Walk over all of the fragments in a subsection. */
7361 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7363 if (fragP
->fr_type
== rs_machine_dependent
7364 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7365 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7366 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7369 /* Read it. If the instruction is a loop, get the target. */
7371 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7372 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7373 t_insn
.opcode
) == 1)
7375 /* Get the current fragment target. */
7376 if (fragP
->tc_frag_data
.slot_symbols
[0])
7378 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7379 current_target
= symbol_get_frag (sym
);
7380 current_offset
= fragP
->fr_offset
;
7386 && fragP
->fr_type
== rs_machine_dependent
7387 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7390 int bytes_added
= 0;
7392 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7393 /* Max out at 12. */
7394 min_bytes
= min_bytes_to_other_loop_end
7395 (fragP
->fr_next
, current_target
, current_offset
,
7396 REQUIRED_LOOP_DIVIDING_BYTES
);
7398 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7400 if (fragP
->tc_frag_data
.is_no_transform
)
7401 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7404 while (min_bytes
+ bytes_added
7405 < REQUIRED_LOOP_DIVIDING_BYTES
)
7409 if (fragP
->fr_var
< length
)
7410 as_fatal (_("fr_var %lu < length %d"),
7411 (long) fragP
->fr_var
, length
);
7414 assemble_nop (length
,
7415 fragP
->fr_literal
+ fragP
->fr_fix
);
7416 fragP
->fr_fix
+= length
;
7417 fragP
->fr_var
-= length
;
7419 bytes_added
+= length
;
7425 assert (fragP
->fr_type
!= rs_machine_dependent
7426 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7432 static offsetT
unrelaxed_frag_min_size (fragS
*);
7435 min_bytes_to_other_loop_end (fragS
*fragP
,
7436 fragS
*current_target
,
7437 offsetT current_offset
,
7441 fragS
*current_fragP
;
7443 for (current_fragP
= fragP
;
7445 current_fragP
= current_fragP
->fr_next
)
7447 if (current_fragP
->tc_frag_data
.is_loop_target
7448 && current_fragP
!= current_target
)
7449 return offset
+ current_offset
;
7451 offset
+= unrelaxed_frag_min_size (current_fragP
);
7453 if (offset
+ current_offset
>= max_size
)
7461 unrelaxed_frag_min_size (fragS
*fragP
)
7463 offsetT size
= fragP
->fr_fix
;
7465 /* Add fill size. */
7466 if (fragP
->fr_type
== rs_fill
)
7467 size
+= fragP
->fr_offset
;
7474 unrelaxed_frag_max_size (fragS
*fragP
)
7476 offsetT size
= fragP
->fr_fix
;
7477 switch (fragP
->fr_type
)
7480 /* Empty frags created by the obstack allocation scheme
7481 end up with type 0. */
7486 size
+= fragP
->fr_offset
;
7494 /* No further adjustments needed. */
7496 case rs_machine_dependent
:
7497 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7498 size
+= fragP
->fr_var
;
7501 /* We had darn well better know how big it is. */
7510 /* Re-process all of the fragments looking to convert all
7511 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7514 1) the instruction size count to the loop end label
7515 is too short (<= 2 instructions),
7516 2) loop has a jump or branch in it
7519 1) workaround_all_short_loops is TRUE
7520 2) The generating loop was a 'loopgtz' or 'loopnez'
7521 3) the instruction size count to the loop end label is too short
7523 then convert this frag (and maybe the next one) to generate a NOP.
7524 In any case close it off with a .fill 0. */
7526 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7527 static bfd_boolean
branch_before_loop_end (fragS
*);
7530 xtensa_fix_short_loop_frags (void)
7534 /* When this routine is called, all of the subsections are still intact
7535 so we walk over subsections instead of sections. */
7536 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7539 fragS
*current_target
= NULL
;
7540 offsetT current_offset
= 0;
7541 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7543 /* Walk over all of the fragments in a subsection. */
7544 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7546 /* Check on the current loop. */
7547 if (fragP
->fr_type
== rs_machine_dependent
7548 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7549 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7550 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7555 /* Read it. If the instruction is a loop, get the target. */
7556 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7557 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7558 t_insn
.opcode
) == 1)
7560 /* Get the current fragment target. */
7561 if (fragP
->tc_frag_data
.slot_symbols
[0])
7563 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7564 current_target
= symbol_get_frag (sym
);
7565 current_offset
= fragP
->fr_offset
;
7566 current_opcode
= t_insn
.opcode
;
7571 if (fragP
->fr_type
== rs_machine_dependent
7572 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7574 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7575 && (branch_before_loop_end (fragP
->fr_next
)
7576 || (workaround_all_short_loops
7577 && current_opcode
!= XTENSA_UNDEFINED
7578 && current_opcode
!= xtensa_loop_opcode
)))
7580 if (fragP
->tc_frag_data
.is_no_transform
)
7581 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7583 relax_frag_add_nop (fragP
);
7592 static int unrelaxed_frag_min_insn_count (fragS
*);
7595 count_insns_to_loop_end (fragS
*base_fragP
,
7596 bfd_boolean count_relax_add
,
7599 fragS
*fragP
= NULL
;
7604 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7606 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7607 if (insn_count
>= max_count
)
7610 if (count_relax_add
)
7612 if (fragP
->fr_type
== rs_machine_dependent
7613 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7615 /* In order to add the appropriate number of
7616 NOPs, we count an instruction for downstream
7619 if (insn_count
>= max_count
)
7629 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7631 xtensa_isa isa
= xtensa_default_isa
;
7632 static xtensa_insnbuf insnbuf
= NULL
;
7636 if (!fragP
->tc_frag_data
.is_insn
)
7640 insnbuf
= xtensa_insnbuf_alloc (isa
);
7642 /* Decode the fixed instructions. */
7643 while (offset
< fragP
->fr_fix
)
7647 xtensa_insnbuf_from_chars
7648 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7649 fmt
= xtensa_format_decode (isa
, insnbuf
);
7651 if (fmt
== XTENSA_UNDEFINED
)
7653 as_fatal (_("undecodable instruction in instruction frag"));
7656 offset
+= xtensa_format_length (isa
, fmt
);
7664 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7667 branch_before_loop_end (fragS
*base_fragP
)
7671 for (fragP
= base_fragP
;
7672 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7673 fragP
= fragP
->fr_next
)
7675 if (unrelaxed_frag_has_b_j (fragP
))
7683 unrelaxed_frag_has_b_j (fragS
*fragP
)
7685 static xtensa_insnbuf insnbuf
= NULL
;
7686 xtensa_isa isa
= xtensa_default_isa
;
7689 if (!fragP
->tc_frag_data
.is_insn
)
7693 insnbuf
= xtensa_insnbuf_alloc (isa
);
7695 /* Decode the fixed instructions. */
7696 while (offset
< fragP
->fr_fix
)
7701 xtensa_insnbuf_from_chars
7702 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7703 fmt
= xtensa_format_decode (isa
, insnbuf
);
7704 if (fmt
== XTENSA_UNDEFINED
)
7707 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7709 xtensa_opcode opcode
=
7710 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7711 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7712 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7715 offset
+= xtensa_format_length (isa
, fmt
);
7721 /* Checks to be made after initial assembly but before relaxation. */
7723 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7724 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7727 xtensa_sanity_check (void)
7734 as_where (&file_name
, &line
);
7735 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7739 /* Walk over all of the fragments in a subsection. */
7740 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7742 /* Currently we only check for empty loops here. */
7743 if (fragP
->fr_type
== rs_machine_dependent
7744 && fragP
->fr_subtype
== RELAX_IMMED
)
7746 static xtensa_insnbuf insnbuf
= NULL
;
7749 if (fragP
->fr_opcode
!= NULL
)
7752 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7753 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7754 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7756 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7757 t_insn
.opcode
) == 1)
7759 if (is_empty_loop (&t_insn
, fragP
))
7761 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7762 as_bad (_("invalid empty loop"));
7764 if (!is_local_forward_loop (&t_insn
, fragP
))
7766 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7767 as_bad (_("loop target does not follow "
7768 "loop instruction in section"));
7775 new_logical_line (file_name
, line
);
7779 #define LOOP_IMMED_OPN 1
7781 /* Return TRUE if the loop target is the next non-zero fragment. */
7784 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7786 const expressionS
*expr
;
7790 if (insn
->insn_type
!= ITYPE_INSN
)
7793 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7796 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7799 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7801 if (expr
->X_op
!= O_symbol
)
7804 symbolP
= expr
->X_add_symbol
;
7808 if (symbol_get_frag (symbolP
) == NULL
)
7811 if (S_GET_VALUE (symbolP
) != 0)
7814 /* Walk through the zero-size fragments from this one. If we find
7815 the target fragment, then this is a zero-size loop. */
7817 for (next_fragP
= fragP
->fr_next
;
7819 next_fragP
= next_fragP
->fr_next
)
7821 if (next_fragP
== symbol_get_frag (symbolP
))
7823 if (next_fragP
->fr_fix
!= 0)
7831 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7833 const expressionS
*expr
;
7837 if (insn
->insn_type
!= ITYPE_INSN
)
7840 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7843 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7846 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7848 if (expr
->X_op
!= O_symbol
)
7851 symbolP
= expr
->X_add_symbol
;
7855 if (symbol_get_frag (symbolP
) == NULL
)
7858 /* Walk through fragments until we find the target.
7859 If we do not find the target, then this is an invalid loop. */
7861 for (next_fragP
= fragP
->fr_next
;
7863 next_fragP
= next_fragP
->fr_next
)
7865 if (next_fragP
== symbol_get_frag (symbolP
))
7873 /* Alignment Functions. */
7876 get_text_align_power (unsigned target_size
)
7878 if (target_size
<= 4)
7880 assert (target_size
== 8);
7886 get_text_align_max_fill_size (int align_pow
,
7887 bfd_boolean use_nops
,
7888 bfd_boolean use_no_density
)
7891 return (1 << align_pow
);
7893 return 3 * (1 << align_pow
);
7895 return 1 + (1 << align_pow
);
7899 /* Calculate the minimum bytes of fill needed at "address" to align a
7900 target instruction of size "target_size" so that it does not cross a
7901 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7902 the fill can be an arbitrary number of bytes. Otherwise, the space must
7903 be filled by NOP instructions. */
7906 get_text_align_fill_size (addressT address
,
7909 bfd_boolean use_nops
,
7910 bfd_boolean use_no_density
)
7912 addressT alignment
, fill
, fill_limit
, fill_step
;
7913 bfd_boolean skip_one
= FALSE
;
7915 alignment
= (1 << align_pow
);
7916 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7920 fill_limit
= alignment
;
7923 else if (!use_no_density
)
7925 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7926 fill_limit
= alignment
* 2;
7932 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7933 fill_limit
= alignment
* 3;
7937 /* Try all fill sizes until finding one that works. */
7938 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7940 if (skip_one
&& fill
== 1)
7942 if ((address
+ fill
) >> align_pow
7943 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7952 branch_align_power (segT sec
)
7954 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7955 is aligned to at least an 8-byte boundary, then a branch target need
7956 only fit within an 8-byte aligned block of memory to avoid a stall.
7957 Otherwise, try to fit branch targets within 4-byte aligned blocks
7958 (which may be insufficient, e.g., if the section has no alignment, but
7959 it's good enough). */
7960 if (xtensa_fetch_width
== 8)
7962 if (get_recorded_alignment (sec
) >= 3)
7966 assert (xtensa_fetch_width
== 4);
7972 /* This will assert if it is not possible. */
7975 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7981 assert (fill_size
% 3 == 0);
7982 return (fill_size
/ 3);
7985 assert (fill_size
!= 1); /* Bad argument. */
7987 while (fill_size
> 1)
7990 if (fill_size
== 2 || fill_size
== 4)
7992 fill_size
-= insn_size
;
7995 assert (fill_size
!= 1); /* Bad algorithm. */
8001 get_text_align_nth_nop_size (offsetT fill_size
,
8003 bfd_boolean use_no_density
)
8010 assert (fill_size
!= 1); /* Bad argument. */
8012 while (fill_size
> 1)
8015 if (fill_size
== 2 || fill_size
== 4)
8017 fill_size
-= insn_size
;
8027 /* For the given fragment, find the appropriate address
8028 for it to begin at if we are using NOPs to align it. */
8031 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8033 /* The rule is: get next fragment's FIRST instruction. Find
8034 the smallest number of bytes that need to be added to
8035 ensure that the next fragment's FIRST instruction will fit
8038 E.G., 2 bytes : 0, 1, 2 mod 4
8041 If the FIRST instruction MIGHT be relaxed,
8042 assume that it will become a 3-byte instruction.
8044 Note again here that LOOP instructions are not bundleable,
8045 and this relaxation only applies to LOOP opcodes. */
8048 int first_insn_size
;
8050 addressT pre_opcode_bytes
;
8053 xtensa_opcode opcode
;
8054 bfd_boolean is_loop
;
8056 assert (fragP
->fr_type
== rs_machine_dependent
);
8057 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8059 /* Find the loop frag. */
8060 first_insn
= next_non_empty_frag (fragP
);
8061 /* Now find the first insn frag. */
8062 first_insn
= next_non_empty_frag (first_insn
);
8064 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8066 loop_insn_size
= xg_get_single_size (opcode
);
8068 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8069 pre_opcode_bytes
+= loop_insn_size
;
8071 /* For loops, the alignment depends on the size of the
8072 instruction following the loop, not the LOOP instruction. */
8074 if (first_insn
== NULL
)
8075 first_insn_size
= xtensa_fetch_width
;
8077 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8079 /* If it was 8, then we'll need a larger alignment for the section. */
8080 align_power
= get_text_align_power (first_insn_size
);
8081 record_alignment (now_seg
, align_power
);
8083 fill_size
= get_text_align_fill_size
8084 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8085 fragP
->tc_frag_data
.is_no_density
);
8087 return address
+ fill_size
;
8091 /* 3 mechanisms for relaxing an alignment:
8093 Align to a power of 2.
8094 Align so the next fragment's instruction does not cross a word boundary.
8095 Align the current instruction so that if the next instruction
8096 were 3 bytes, it would not cross a word boundary.
8100 zeros - This is easy; always insert zeros.
8101 nops - 3-byte and 2-byte instructions
8105 >=5 : 3-byte instruction + fn (n-3)
8106 widening - widen previous instructions. */
8109 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8111 addressT target_address
, loop_insn_offset
;
8113 xtensa_opcode loop_opcode
;
8114 bfd_boolean is_loop
;
8117 offsetT branch_align
;
8119 assert (fragP
->fr_type
== rs_machine_dependent
);
8120 switch (fragP
->fr_subtype
)
8122 case RELAX_DESIRE_ALIGN
:
8123 target_size
= next_frag_format_size (fragP
);
8124 if (target_size
== XTENSA_UNDEFINED
)
8126 align_power
= branch_align_power (now_seg
);
8127 branch_align
= 1 << align_power
;
8128 /* Don't count on the section alignment being as large as the target. */
8129 if (target_size
> branch_align
)
8130 target_size
= branch_align
;
8131 opt_diff
= get_text_align_fill_size (address
, align_power
,
8132 target_size
, FALSE
, FALSE
);
8134 *max_diff
= (opt_diff
+ branch_align
8135 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8136 assert (*max_diff
>= opt_diff
);
8139 case RELAX_ALIGN_NEXT_OPCODE
:
8140 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8141 loop_insn_offset
= 0;
8142 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8145 /* If the loop has been expanded then the LOOP instruction
8146 could be at an offset from this fragment. */
8147 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8149 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8151 /* In an ideal world, which is what we are shooting for here,
8152 we wouldn't need to use any NOPs immediately prior to the
8153 LOOP instruction. If this approach fails, relax_frag_loop_align
8154 will call get_noop_aligned_address. */
8156 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8157 align_power
= get_text_align_power (target_size
),
8158 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8159 target_size
, FALSE
, FALSE
);
8161 *max_diff
= xtensa_fetch_width
8162 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8163 - target_size
+ opt_diff
;
8164 assert (*max_diff
>= opt_diff
);
8175 /* md_relax_frag Hook and Helper Functions. */
8177 static long relax_frag_loop_align (fragS
*, long);
8178 static long relax_frag_for_align (fragS
*, long);
8179 static long relax_frag_immed
8180 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8183 /* Return the number of bytes added to this fragment, given that the
8184 input has been stretched already by "stretch". */
8187 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8189 xtensa_isa isa
= xtensa_default_isa
;
8190 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8191 long new_stretch
= 0;
8195 static xtensa_insnbuf vbuf
= NULL
;
8196 int slot
, num_slots
;
8199 as_where (&file_name
, &line
);
8200 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8202 fragP
->tc_frag_data
.unreported_expansion
= 0;
8204 switch (fragP
->fr_subtype
)
8206 case RELAX_ALIGN_NEXT_OPCODE
:
8207 /* Always convert. */
8208 if (fragP
->tc_frag_data
.relax_seen
)
8209 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8212 case RELAX_LOOP_END
:
8216 case RELAX_LOOP_END_ADD_NOP
:
8217 /* Add a NOP and switch to .fill 0. */
8218 new_stretch
= relax_frag_add_nop (fragP
);
8222 case RELAX_DESIRE_ALIGN
:
8223 /* Do nothing. The narrowing before this frag will either align
8228 case RELAX_LITERAL_FINAL
:
8231 case RELAX_LITERAL_NR
:
8233 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8234 assert (unreported
== lit_size
);
8235 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8236 fragP
->fr_var
-= lit_size
;
8237 fragP
->fr_fix
+= lit_size
;
8243 vbuf
= xtensa_insnbuf_alloc (isa
);
8245 xtensa_insnbuf_from_chars
8246 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8247 fmt
= xtensa_format_decode (isa
, vbuf
);
8248 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8250 for (slot
= 0; slot
< num_slots
; slot
++)
8252 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8255 if (fragP
->tc_frag_data
.relax_seen
)
8256 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8260 case RELAX_IMMED_STEP1
:
8261 case RELAX_IMMED_STEP2
:
8262 /* Place the immediate. */
8263 new_stretch
+= relax_frag_immed
8264 (now_seg
, fragP
, stretch
,
8265 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8266 fmt
, slot
, stretched_p
, FALSE
);
8270 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8276 case RELAX_LITERAL_POOL_BEGIN
:
8277 case RELAX_LITERAL_POOL_END
:
8278 case RELAX_MAYBE_UNREACHABLE
:
8279 case RELAX_MAYBE_DESIRE_ALIGN
:
8280 /* No relaxation required. */
8283 case RELAX_FILL_NOP
:
8284 case RELAX_UNREACHABLE
:
8285 if (fragP
->tc_frag_data
.relax_seen
)
8286 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8290 as_bad (_("bad relaxation state"));
8293 /* Tell gas we need another relaxation pass. */
8294 if (! fragP
->tc_frag_data
.relax_seen
)
8296 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8300 new_logical_line (file_name
, line
);
8306 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8308 addressT old_address
, old_next_address
, old_size
;
8309 addressT new_address
, new_next_address
, new_size
;
8312 /* All the frags with relax_frag_for_alignment prior to this one in the
8313 section have been done, hopefully eliminating the need for a NOP here.
8314 But, this will put it in if necessary. */
8316 /* Calculate the old address of this fragment and the next fragment. */
8317 old_address
= fragP
->fr_address
- stretch
;
8318 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8319 fragP
->tc_frag_data
.text_expansion
[0]);
8320 old_size
= old_next_address
- old_address
;
8322 /* Calculate the new address of this fragment and the next fragment. */
8323 new_address
= fragP
->fr_address
;
8325 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8326 new_size
= new_next_address
- new_address
;
8328 growth
= new_size
- old_size
;
8330 /* Fix up the text_expansion field and return the new growth. */
8331 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8336 /* Add a NOP instruction. */
8339 relax_frag_add_nop (fragS
*fragP
)
8341 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8342 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8343 assemble_nop (length
, nop_buf
);
8344 fragP
->tc_frag_data
.is_insn
= TRUE
;
8346 if (fragP
->fr_var
< length
)
8348 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8352 fragP
->fr_fix
+= length
;
8353 fragP
->fr_var
-= length
;
8358 static long future_alignment_required (fragS
*, long);
8361 relax_frag_for_align (fragS
*fragP
, long stretch
)
8363 /* Overview of the relaxation procedure for alignment:
8364 We can widen with NOPs or by widening instructions or by filling
8365 bytes after jump instructions. Find the opportune places and widen
8366 them if necessary. */
8371 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8372 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8373 || (fragP
->fr_subtype
== RELAX_SLOTS
8374 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8376 stretch_me
= future_alignment_required (fragP
, stretch
);
8377 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8383 /* We expanded on a previous pass. Can we shrink now? */
8384 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8385 if (shrink
<= stretch
&& stretch
> 0)
8387 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8393 /* Below here, diff > 0. */
8394 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8400 /* Return the address of the next frag that should be aligned.
8402 By "address" we mean the address it _would_ be at if there
8403 is no action taken to align it between here and the target frag.
8404 In other words, if no narrows and no fill nops are used between
8405 here and the frag to align, _even_if_ some of the frags we use
8406 to align targets have already expanded on a previous relaxation
8409 Also, count each frag that may be used to help align the target.
8411 Return 0 if there are no frags left in the chain that need to be
8415 find_address_of_next_align_frag (fragS
**fragPP
,
8419 bfd_boolean
*paddable
)
8421 fragS
*fragP
= *fragPP
;
8422 addressT address
= fragP
->fr_address
;
8424 /* Do not reset the counts to 0. */
8428 /* Limit this to a small search. */
8429 if (*widens
>= (int) xtensa_fetch_width
)
8434 address
+= fragP
->fr_fix
;
8436 if (fragP
->fr_type
== rs_fill
)
8437 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8438 else if (fragP
->fr_type
== rs_machine_dependent
)
8440 switch (fragP
->fr_subtype
)
8442 case RELAX_UNREACHABLE
:
8446 case RELAX_FILL_NOP
:
8448 if (!fragP
->tc_frag_data
.is_no_density
)
8453 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8458 address
+= total_frag_text_expansion (fragP
);;
8462 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8465 case RELAX_ALIGN_NEXT_OPCODE
:
8466 case RELAX_DESIRE_ALIGN
:
8470 case RELAX_MAYBE_UNREACHABLE
:
8471 case RELAX_MAYBE_DESIRE_ALIGN
:
8476 /* Just punt if we don't know the type. */
8483 /* Just punt if we don't know the type. */
8487 fragP
= fragP
->fr_next
;
8495 static long bytes_to_stretch (fragS
*, int, int, int, int);
8498 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8500 fragS
*this_frag
= fragP
;
8504 int narrow_nops
= 0;
8505 bfd_boolean paddable
= FALSE
;
8506 offsetT local_opt_diff
;
8509 int stretch_amount
= 0;
8510 int local_stretch_amount
;
8511 int global_stretch_amount
;
8513 address
= find_address_of_next_align_frag
8514 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8518 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8519 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8521 frag_wane (this_frag
);
8525 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8526 opt_diff
= local_opt_diff
;
8527 assert (opt_diff
>= 0);
8528 assert (max_diff
>= opt_diff
);
8533 fragP
= fragP
->fr_next
;
8535 while (fragP
&& opt_diff
< max_diff
&& address
)
8537 /* We only use these to determine if we can exit early
8538 because there will be plenty of ways to align future
8540 int glob_widens
= 0;
8543 bfd_boolean glob_pad
= 0;
8544 address
= find_address_of_next_align_frag
8545 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8546 /* If there is a padable portion, then skip. */
8547 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8552 offsetT next_m_diff
;
8553 offsetT next_o_diff
;
8555 /* Downrange frags haven't had stretch added to them yet. */
8558 /* The address also includes any text expansion from this
8559 frag in a previous pass, but we don't want that. */
8560 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8562 /* Assume we are going to move at least opt_diff. In
8563 reality, we might not be able to, but assuming that
8564 we will helps catch cases where moving opt_diff pushes
8565 the next target from aligned to unaligned. */
8566 address
+= opt_diff
;
8568 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8570 /* Now cleanup for the adjustments to address. */
8571 next_o_diff
+= opt_diff
;
8572 next_m_diff
+= opt_diff
;
8573 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8574 opt_diff
= next_o_diff
;
8575 if (next_m_diff
< max_diff
)
8576 max_diff
= next_m_diff
;
8577 fragP
= fragP
->fr_next
;
8581 /* If there are enough wideners in between, do it. */
8584 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8586 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8591 local_stretch_amount
8592 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8593 num_widens
, local_opt_diff
);
8594 global_stretch_amount
8595 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8596 num_widens
, opt_diff
);
8597 /* If the condition below is true, then the frag couldn't
8598 stretch the correct amount for the global case, so we just
8599 optimize locally. We'll rely on the subsequent frags to get
8600 the correct alignment in the global case. */
8601 if (global_stretch_amount
< local_stretch_amount
)
8602 stretch_amount
= local_stretch_amount
;
8604 stretch_amount
= global_stretch_amount
;
8606 if (this_frag
->fr_subtype
== RELAX_SLOTS
8607 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8608 assert (stretch_amount
<= 1);
8609 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8611 if (this_frag
->tc_frag_data
.is_no_density
)
8612 assert (stretch_amount
== 3 || stretch_amount
== 0);
8614 assert (stretch_amount
<= 3);
8617 return stretch_amount
;
8621 /* The idea: widen everything you can to get a target or loop aligned,
8622 then start using NOPs.
8624 When we must have a NOP, here is a table of how we decide
8625 (so you don't have to fight through the control flow below):
8627 wide_nops = the number of wide NOPs available for aligning
8628 narrow_nops = the number of narrow NOPs available for aligning
8629 (a subset of wide_nops)
8630 widens = the number of narrow instructions that should be widened
8637 b 0 1 1 (case 3a makes this case unnecessary)
8640 c 0 1 2 (case 4a makes this case unnecessary)
8643 c 0 2 1 (case 5b makes this case unnecessary)
8646 c 0 1 4 (case 6b makes this case unneccesary)
8647 d 1 1 1 (case 6a makes this case unnecessary)
8648 e 0 2 2 (case 6a makes this case unnecessary)
8649 f 0 3 0 (case 6a makes this case unnecessary)
8652 c 1 1 2 (case 7b makes this case unnecessary)
8653 d 0 1 5 (case 7a makes this case unnecessary)
8654 e 0 2 3 (case 7b makes this case unnecessary)
8655 f 0 3 1 (case 7b makes this case unnecessary)
8656 g 1 2 1 (case 7b makes this case unnecessary)
8660 bytes_to_stretch (fragS
*this_frag
,
8666 int bytes_short
= desired_diff
- num_widens
;
8668 assert (desired_diff
>= 0 && desired_diff
< 8);
8669 if (desired_diff
== 0)
8672 assert (wide_nops
> 0 || num_widens
> 0);
8674 /* Always prefer widening to NOP-filling. */
8675 if (bytes_short
< 0)
8677 /* There are enough RELAX_NARROW frags after this one
8678 to align the target without widening this frag in any way. */
8682 if (bytes_short
== 0)
8684 /* Widen every narrow between here and the align target
8685 and the align target will be properly aligned. */
8686 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8692 /* From here we will need at least one NOP to get an alignment.
8693 However, we may not be able to align at all, in which case,
8695 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8697 switch (desired_diff
)
8702 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8703 return 2; /* case 2 */
8709 return 3; /* case 3a */
8711 if (num_widens
>= 1 && wide_nops
== 1)
8712 return 3; /* case 4a */
8713 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8714 return 2; /* case 4b */
8717 if (num_widens
>= 2 && wide_nops
== 1)
8718 return 3; /* case 5a */
8719 /* We will need two nops. Are there enough nops
8720 between here and the align target? */
8721 if (wide_nops
< 2 || narrow_nops
== 0)
8723 /* Are there other nops closer that can serve instead? */
8724 if (wide_nops
> 2 && narrow_nops
> 1)
8726 /* Take the density one first, because there might not be
8727 another density one available. */
8728 if (!this_frag
->tc_frag_data
.is_no_density
)
8729 return 2; /* case 5b narrow */
8731 return 3; /* case 5b wide */
8735 return 3; /* case 6a */
8736 else if (num_widens
>= 3 && wide_nops
== 1)
8737 return 3; /* case 6b */
8740 if (wide_nops
== 1 && num_widens
>= 4)
8741 return 3; /* case 7a */
8742 else if (wide_nops
== 2 && num_widens
>= 1)
8743 return 3; /* case 7b */
8751 /* We will need a NOP no matter what, but should we widen
8752 this instruction to help?
8754 This is a RELAX_NARROW frag. */
8755 switch (desired_diff
)
8764 if (wide_nops
>= 1 && num_widens
== 1)
8765 return 1; /* case 4a */
8768 if (wide_nops
>= 1 && num_widens
== 2)
8769 return 1; /* case 5a */
8773 return 0; /* case 6a */
8774 else if (wide_nops
>= 1 && num_widens
== 3)
8775 return 1; /* case 6b */
8778 if (wide_nops
>= 1 && num_widens
== 4)
8779 return 1; /* case 7a */
8780 else if (wide_nops
>= 2 && num_widens
== 1)
8781 return 1; /* case 7b */
8794 relax_frag_immed (segT segP
,
8801 bfd_boolean estimate_only
)
8805 bfd_boolean negatable_branch
= FALSE
;
8806 bfd_boolean branch_jmp_to_next
= FALSE
;
8807 bfd_boolean wide_insn
= FALSE
;
8808 xtensa_isa isa
= xtensa_default_isa
;
8810 offsetT frag_offset
;
8813 int num_text_bytes
, num_literal_bytes
;
8814 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8816 assert (fragP
->fr_opcode
!= NULL
);
8818 xg_clear_vinsn (&cur_vinsn
);
8819 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8820 if (cur_vinsn
.num_slots
> 1)
8823 tinsn
= cur_vinsn
.slots
[slot
];
8824 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8826 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8829 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8830 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8832 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8834 old_size
= xtensa_format_length (isa
, fmt
);
8836 /* Special case: replace a branch to the next instruction with a NOP.
8837 This is required to work around a hardware bug in T1040.0 and also
8838 serves as an optimization. */
8840 if (branch_jmp_to_next
8841 && ((old_size
== 2) || (old_size
== 3))
8842 && !next_frag_is_loop_target (fragP
))
8845 /* Here is the fun stuff: Get the immediate field from this
8846 instruction. If it fits, we are done. If not, find the next
8847 instruction sequence that fits. */
8849 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8850 istack_init (&istack
);
8851 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8852 min_steps
, stretch
);
8853 if (num_steps
< min_steps
)
8855 as_fatal (_("internal error: relaxation failed"));
8859 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8861 as_fatal (_("internal error: relaxation requires too many steps"));
8865 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8867 /* Figure out the number of bytes needed. */
8869 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8871 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8873 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8875 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8878 num_text_bytes
+= old_size
;
8879 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8880 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8882 total_text_diff
= num_text_bytes
- old_size
;
8883 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8885 /* It MUST get larger. If not, we could get an infinite loop. */
8886 assert (num_text_bytes
>= 0);
8887 assert (literal_diff
>= 0);
8888 assert (total_text_diff
>= 0);
8890 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8891 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8892 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8893 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8895 /* Find the associated expandable literal for this. */
8896 if (literal_diff
!= 0)
8898 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8901 assert (literal_diff
== 4);
8902 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8904 /* We expect that the literal section state has NOT been
8906 assert (lit_fragP
->fr_type
== rs_machine_dependent
8907 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8908 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8910 /* We need to mark this section for another iteration
8916 if (negatable_branch
&& istack
.ninsn
> 1)
8917 update_next_frag_state (fragP
);
8919 return this_text_diff
;
8923 /* md_convert_frag Hook and Helper Functions. */
8925 static void convert_frag_align_next_opcode (fragS
*);
8926 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8927 static void convert_frag_fill_nop (fragS
*);
8928 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8931 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8933 static xtensa_insnbuf vbuf
= NULL
;
8934 xtensa_isa isa
= xtensa_default_isa
;
8941 as_where (&file_name
, &line
);
8942 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8944 switch (fragp
->fr_subtype
)
8946 case RELAX_ALIGN_NEXT_OPCODE
:
8947 /* Always convert. */
8948 convert_frag_align_next_opcode (fragp
);
8951 case RELAX_DESIRE_ALIGN
:
8952 /* Do nothing. If not aligned already, too bad. */
8956 case RELAX_LITERAL_FINAL
:
8961 vbuf
= xtensa_insnbuf_alloc (isa
);
8963 xtensa_insnbuf_from_chars
8964 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8965 fmt
= xtensa_format_decode (isa
, vbuf
);
8966 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8968 for (slot
= 0; slot
< num_slots
; slot
++)
8970 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8973 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8977 case RELAX_IMMED_STEP1
:
8978 case RELAX_IMMED_STEP2
:
8979 /* Place the immediate. */
8982 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8987 /* This is OK because some slots could have
8988 relaxations and others have none. */
8994 case RELAX_UNREACHABLE
:
8995 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8996 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8997 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9001 case RELAX_MAYBE_UNREACHABLE
:
9002 case RELAX_MAYBE_DESIRE_ALIGN
:
9006 case RELAX_FILL_NOP
:
9007 convert_frag_fill_nop (fragp
);
9010 case RELAX_LITERAL_NR
:
9011 if (use_literal_section
)
9013 /* This should have been handled during relaxation. When
9014 relaxing a code segment, literals sometimes need to be
9015 added to the corresponding literal segment. If that
9016 literal segment has already been relaxed, then we end up
9017 in this situation. Marking the literal segments as data
9018 would make this happen less often (since GAS always relaxes
9019 code before data), but we could still get into trouble if
9020 there are instructions in a segment that is not marked as
9021 containing code. Until we can implement a better solution,
9022 cheat and adjust the addresses of all the following frags.
9023 This could break subsequent alignments, but the linker's
9024 literal coalescing will do that anyway. */
9027 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9028 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9029 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9032 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9036 as_bad (_("invalid relaxation fragment result"));
9041 new_logical_line (file_name
, line
);
9046 convert_frag_align_next_opcode (fragS
*fragp
)
9048 char *nop_buf
; /* Location for Writing. */
9049 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9050 addressT aligned_address
;
9054 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9056 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9057 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9058 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9060 for (nop
= 0; nop
< nop_count
; nop
++)
9063 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9065 assemble_nop (nop_size
, nop_buf
);
9066 nop_buf
+= nop_size
;
9069 fragp
->fr_fix
+= fill_size
;
9070 fragp
->fr_var
-= fill_size
;
9075 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9077 TInsn tinsn
, single_target
;
9078 int size
, old_size
, diff
;
9079 offsetT frag_offset
;
9082 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9084 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9086 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9087 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9088 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9093 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9095 /* No conversion. */
9100 assert (fragP
->fr_opcode
!= NULL
);
9102 /* Frags in this relaxation state should only contain
9103 single instruction bundles. */
9104 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9106 /* Just convert it to a wide form.... */
9108 old_size
= xg_get_single_size (tinsn
.opcode
);
9110 tinsn_init (&single_target
);
9111 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9113 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9115 as_bad (_("unable to widen instruction"));
9119 size
= xg_get_single_size (single_target
.opcode
);
9120 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9123 diff
= size
- old_size
;
9125 assert (diff
<= fragP
->fr_var
);
9126 fragP
->fr_var
-= diff
;
9127 fragP
->fr_fix
+= diff
;
9135 convert_frag_fill_nop (fragS
*fragP
)
9137 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9138 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9139 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9140 - fragP
->fr_address
- fragP
->fr_fix
));
9143 /* No conversion. */
9147 assemble_nop (size
, loc
);
9148 fragP
->tc_frag_data
.is_insn
= TRUE
;
9149 fragP
->fr_var
-= size
;
9150 fragP
->fr_fix
+= size
;
9155 static fixS
*fix_new_exp_in_seg
9156 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9157 bfd_reloc_code_real_type
);
9158 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9161 convert_frag_immed (segT segP
,
9167 char *immed_instr
= fragP
->fr_opcode
;
9169 bfd_boolean expanded
= FALSE
;
9170 bfd_boolean branch_jmp_to_next
= FALSE
;
9171 char *fr_opcode
= fragP
->fr_opcode
;
9172 xtensa_isa isa
= xtensa_default_isa
;
9173 bfd_boolean wide_insn
= FALSE
;
9175 bfd_boolean is_loop
;
9177 assert (fr_opcode
!= NULL
);
9179 xg_clear_vinsn (&cur_vinsn
);
9181 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9182 if (cur_vinsn
.num_slots
> 1)
9185 orig_tinsn
= cur_vinsn
.slots
[slot
];
9186 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9188 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9190 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9191 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9193 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9195 /* Conversion just inserts a NOP and marks the fix as completed. */
9196 bytes
= xtensa_format_length (isa
, fmt
);
9199 cur_vinsn
.slots
[slot
].opcode
=
9200 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9201 cur_vinsn
.slots
[slot
].ntok
= 0;
9205 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9206 assert (bytes
== 2 || bytes
== 3);
9207 build_nop (&cur_vinsn
.slots
[0], bytes
);
9208 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9210 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9211 xtensa_insnbuf_to_chars
9212 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9217 /* Here is the fun stuff: Get the immediate field from this
9218 instruction. If it fits, we're done. If not, find the next
9219 instruction sequence that fits. */
9223 symbolS
*lit_sym
= NULL
;
9225 int target_offset
= 0;
9228 symbolS
*gen_label
= NULL
;
9229 offsetT frag_offset
;
9230 bfd_boolean first
= TRUE
;
9231 bfd_boolean last_is_jump
;
9233 /* It does not fit. Find something that does and
9234 convert immediately. */
9235 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9236 istack_init (&istack
);
9237 xg_assembly_relax (&istack
, &orig_tinsn
,
9238 segP
, fragP
, frag_offset
, min_steps
, 0);
9240 old_size
= xtensa_format_length (isa
, fmt
);
9242 /* Assemble this right inline. */
9244 /* First, create the mapping from a label name to the REAL label. */
9246 for (i
= 0; i
< istack
.ninsn
; i
++)
9248 TInsn
*tinsn
= &istack
.insn
[i
];
9251 switch (tinsn
->insn_type
)
9254 if (lit_sym
!= NULL
)
9255 as_bad (_("multiple literals in expansion"));
9256 /* First find the appropriate space in the literal pool. */
9257 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9258 if (lit_frag
== NULL
)
9259 as_bad (_("no registered fragment for literal"));
9260 if (tinsn
->ntok
!= 1)
9261 as_bad (_("number of literal tokens != 1"));
9263 /* Set the literal symbol and add a fixup. */
9264 lit_sym
= lit_frag
->fr_symbol
;
9268 if (align_targets
&& !is_loop
)
9270 fragS
*unreach
= fragP
->fr_next
;
9271 while (!(unreach
->fr_type
== rs_machine_dependent
9272 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9273 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9275 unreach
= unreach
->fr_next
;
9278 assert (unreach
->fr_type
== rs_machine_dependent
9279 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9280 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9282 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9284 assert (gen_label
== NULL
);
9285 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9286 fr_opcode
- fragP
->fr_literal
9287 + target_offset
, fragP
);
9291 if (first
&& wide_insn
)
9293 target_offset
+= xtensa_format_length (isa
, fmt
);
9295 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9296 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9299 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9306 last_is_jump
= FALSE
;
9307 for (i
= 0; i
< istack
.ninsn
; i
++)
9309 TInsn
*tinsn
= &istack
.insn
[i
];
9313 bfd_reloc_code_real_type reloc_type
;
9315 switch (tinsn
->insn_type
)
9318 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9319 /* Already checked. */
9320 assert (lit_frag
!= NULL
);
9321 assert (lit_sym
!= NULL
);
9322 assert (tinsn
->ntok
== 1);
9324 target_seg
= S_GET_SEGMENT (lit_sym
);
9325 assert (target_seg
);
9326 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9327 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9329 reloc_type
= BFD_RELOC_32
;
9330 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9331 &tinsn
->tok
[0], FALSE
, reloc_type
);
9338 xg_resolve_labels (tinsn
, gen_label
);
9339 xg_resolve_literals (tinsn
, lit_sym
);
9340 if (wide_insn
&& first
)
9343 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9345 cur_vinsn
.slots
[slot
] = *tinsn
;
9349 cur_vinsn
.slots
[slot
].opcode
=
9350 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9351 cur_vinsn
.slots
[slot
].ntok
= 0;
9353 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9354 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9355 (unsigned char *) immed_instr
, 0);
9356 fragP
->tc_frag_data
.is_insn
= TRUE
;
9357 size
= xtensa_format_length (isa
, fmt
);
9358 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9361 (tinsn
, immed_instr
+ size
, fragP
,
9362 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9363 size
+= xg_get_single_size (tinsn
->opcode
);
9368 size
= xg_get_single_size (tinsn
->opcode
);
9369 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9370 immed_instr
- fragP
->fr_literal
, TRUE
);
9372 immed_instr
+= size
;
9378 diff
= total_size
- old_size
;
9382 assert (diff
<= fragP
->fr_var
);
9383 fragP
->fr_var
-= diff
;
9384 fragP
->fr_fix
+= diff
;
9387 /* Check for undefined immediates in LOOP instructions. */
9391 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9392 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9394 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9397 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9398 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9400 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9405 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9406 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9408 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9410 /* Add an expansion note on the expanded instruction. */
9411 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9412 &orig_tinsn
.tok
[0], TRUE
,
9413 BFD_RELOC_XTENSA_ASM_EXPAND
);
9418 /* Add a new fix expression into the desired segment. We have to
9419 switch to that segment to do this. */
9422 fix_new_exp_in_seg (segT new_seg
,
9429 bfd_reloc_code_real_type r_type
)
9433 subsegT subseg
= now_subseg
;
9435 assert (new_seg
!= 0);
9436 subseg_set (new_seg
, new_subseg
);
9438 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9439 subseg_set (seg
, subseg
);
9444 /* Relax a loop instruction so that it can span loop >256 bytes.
9450 addi as, as, lo8 (label-.L1)
9451 addmi as, as, mid8 (label-.L1)
9462 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9467 unsigned long target
;
9468 static xtensa_insnbuf insnbuf
= NULL
;
9469 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9470 xtensa_isa isa
= xtensa_default_isa
;
9471 addressT loop_offset
;
9472 addressT addi_offset
= 9;
9473 addressT addmi_offset
= 12;
9478 insnbuf
= xtensa_insnbuf_alloc (isa
);
9480 /* Get the loop offset. */
9481 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9483 /* Validate that there really is a LOOP at the loop_offset. Because
9484 loops are not bundleable, we can assume that the instruction will be
9486 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9487 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9489 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9490 addi_offset
+= loop_offset
;
9491 addmi_offset
+= loop_offset
;
9493 assert (tinsn
->ntok
== 2);
9494 if (tinsn
->tok
[1].X_op
== O_constant
)
9495 target
= tinsn
->tok
[1].X_add_number
;
9496 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9498 /* Find the fragment. */
9499 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9500 assert (S_GET_SEGMENT (sym
) == segP
9501 || S_GET_SEGMENT (sym
) == absolute_section
);
9502 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9506 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9511 know (symbolP
->sy_frag
);
9512 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9513 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9515 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9516 loop_length_hi
= loop_length
& ~0x0ff;
9517 loop_length_lo
= loop_length
& 0x0ff;
9518 if (loop_length_lo
>= 128)
9520 loop_length_lo
-= 256;
9521 loop_length_hi
+= 256;
9524 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9525 32512. If the loop is larger than that, then we just fail. */
9526 if (loop_length_hi
> 32512)
9527 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9528 _("loop too long for LOOP instruction"));
9530 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9531 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9533 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9534 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9536 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9537 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9539 fragP
->tc_frag_data
.is_insn
= TRUE
;
9540 xtensa_insnbuf_to_chars
9541 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9543 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9544 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9545 xtensa_insnbuf_to_chars
9546 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9548 /* Walk through all of the frags from here to the loop end
9549 and mark them as no_transform to keep them from being modified
9550 by the linker. If we ever have a relocation for the
9551 addi/addmi of the difference of two symbols we can remove this. */
9554 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9555 next_fragP
= next_fragP
->fr_next
)
9557 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9558 if (next_fragP
->tc_frag_data
.is_loop_target
)
9560 if (target_count
== 2)
9566 /* A map that keeps information on a per-subsegment basis. This is
9567 maintained during initial assembly, but is invalid once the
9568 subsegments are smashed together. I.E., it cannot be used during
9571 typedef struct subseg_map_struct
9579 float total_freq
; /* fall-through + branch target frequency */
9580 float target_freq
; /* branch target frequency alone */
9582 struct subseg_map_struct
*next
;
9586 static subseg_map
*sseg_map
= NULL
;
9589 get_subseg_info (segT seg
, subsegT subseg
)
9591 subseg_map
*subseg_e
;
9593 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9595 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9603 add_subseg_info (segT seg
, subsegT subseg
)
9605 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9606 memset (subseg_e
, 0, sizeof (subseg_map
));
9607 subseg_e
->seg
= seg
;
9608 subseg_e
->subseg
= subseg
;
9609 subseg_e
->flags
= 0;
9610 /* Start off considering every branch target very important. */
9611 subseg_e
->target_freq
= 1.0;
9612 subseg_e
->total_freq
= 1.0;
9613 subseg_e
->next
= sseg_map
;
9614 sseg_map
= subseg_e
;
9620 get_last_insn_flags (segT seg
, subsegT subseg
)
9622 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9624 return subseg_e
->flags
;
9630 set_last_insn_flags (segT seg
,
9635 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9637 subseg_e
= add_subseg_info (seg
, subseg
);
9639 subseg_e
->flags
|= fl
;
9641 subseg_e
->flags
&= ~fl
;
9646 get_subseg_total_freq (segT seg
, subsegT subseg
)
9648 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9650 return subseg_e
->total_freq
;
9656 get_subseg_target_freq (segT seg
, subsegT subseg
)
9658 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9660 return subseg_e
->target_freq
;
9666 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9668 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9670 subseg_e
= add_subseg_info (seg
, subseg
);
9671 subseg_e
->total_freq
= total_f
;
9672 subseg_e
->target_freq
= target_f
;
9676 /* Segment Lists and emit_state Stuff. */
9679 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9684 segT literal_section
= head
->seg
;
9686 /* Move the literal section to the front of the section list. */
9687 assert (literal_section
);
9688 if (literal_section
!= stdoutput
->sections
)
9690 bfd_section_list_remove (stdoutput
, literal_section
);
9691 bfd_section_list_prepend (stdoutput
, literal_section
);
9698 static void mark_literal_frags (seg_list
*);
9701 xtensa_move_literals (void)
9704 frchainS
*frchain_from
, *frchain_to
;
9705 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9706 fragS
**frag_splice
;
9709 fixS
*fix
, *next_fix
, **fix_splice
;
9712 mark_literal_frags (literal_head
->next
);
9713 mark_literal_frags (init_literal_head
->next
);
9714 mark_literal_frags (fini_literal_head
->next
);
9716 if (use_literal_section
)
9719 segment
= literal_head
->next
;
9722 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9723 search_frag
= frchain_from
->frch_root
;
9724 literal_pool
= NULL
;
9726 frag_splice
= &(frchain_from
->frch_root
);
9728 while (!search_frag
->tc_frag_data
.literal_frag
)
9730 assert (search_frag
->fr_fix
== 0
9731 || search_frag
->fr_type
== rs_align
);
9732 search_frag
= search_frag
->fr_next
;
9735 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9736 == RELAX_LITERAL_POOL_BEGIN
);
9737 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9739 /* Make sure that all the frags in this series are closed, and
9740 that there is at least one left over of zero-size. This
9741 prevents us from making a segment with an frchain without any
9743 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9744 xtensa_set_frag_assembly_state (frag_now
);
9745 last_frag
= frag_now
;
9746 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9747 xtensa_set_frag_assembly_state (frag_now
);
9749 while (search_frag
!= frag_now
)
9751 next_frag
= search_frag
->fr_next
;
9753 /* First, move the frag out of the literal section and
9754 to the appropriate place. */
9755 if (search_frag
->tc_frag_data
.literal_frag
)
9757 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9758 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9759 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9760 assert (frchain_to
);
9762 insert_after
= literal_pool
;
9764 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9765 insert_after
= insert_after
->fr_next
;
9767 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9769 *frag_splice
= next_frag
;
9770 search_frag
->fr_next
= insert_after
->fr_next
;
9771 insert_after
->fr_next
= search_frag
;
9772 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9774 /* Now move any fixups associated with this frag to the
9776 fix
= frchain_from
->fix_root
;
9777 fix_splice
= &(frchain_from
->fix_root
);
9780 next_fix
= fix
->fx_next
;
9781 if (fix
->fx_frag
== search_frag
)
9783 *fix_splice
= next_fix
;
9784 fix
->fx_next
= frchain_to
->fix_root
;
9785 frchain_to
->fix_root
= fix
;
9786 if (frchain_to
->fix_tail
== NULL
)
9787 frchain_to
->fix_tail
= fix
;
9790 fix_splice
= &(fix
->fx_next
);
9793 search_frag
= next_frag
;
9796 if (frchain_from
->fix_root
!= NULL
)
9798 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9799 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9801 assert (frchain_from
->fix_root
== NULL
);
9803 frchain_from
->fix_tail
= NULL
;
9804 xtensa_restore_emit_state (&state
);
9805 segment
= segment
->next
;
9808 /* Now fix up the SEGMENT value for all the literal symbols. */
9809 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9811 symbolS
*lit_sym
= lit
->sym
;
9812 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9814 S_SET_SEGMENT (lit_sym
, dest_seg
);
9819 /* Walk over all the frags for segments in a list and mark them as
9820 containing literals. As clunky as this is, we can't rely on frag_var
9821 and frag_variant to get called in all situations. */
9824 mark_literal_frags (seg_list
*segment
)
9826 frchainS
*frchain_from
;
9831 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9832 search_frag
= frchain_from
->frch_root
;
9835 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9836 search_frag
= search_frag
->fr_next
;
9838 segment
= segment
->next
;
9844 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9846 /* Move all of the sections in the section list to come
9847 after "after" in the gnu segment list. */
9852 segT literal_section
= head
->seg
;
9854 /* Move the literal section after "after". */
9855 assert (literal_section
);
9856 if (literal_section
!= after
)
9858 bfd_section_list_remove (stdoutput
, literal_section
);
9859 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9867 /* Push all the literal segments to the end of the gnu list. */
9870 xtensa_reorder_segments (void)
9877 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9883 /* Now that we have the last section, push all the literal
9884 sections to the end. */
9885 xtensa_reorder_seg_list (literal_head
, last_sec
);
9886 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9887 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9889 /* Now perform the final error check. */
9890 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9892 assert (new_count
== old_count
);
9896 /* Change the emit state (seg, subseg, and frag related stuff) to the
9897 correct location. Return a emit_state which can be passed to
9898 xtensa_restore_emit_state to return to current fragment. */
9901 xtensa_switch_to_literal_fragment (emit_state
*result
)
9903 if (directive_state
[directive_absolute_literals
])
9905 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9906 &default_lit_sections
.lit4_seg
, FALSE
);
9907 xtensa_switch_section_emit_state (result
,
9908 default_lit_sections
.lit4_seg
, 0);
9911 xtensa_switch_to_non_abs_literal_fragment (result
);
9913 /* Do a 4-byte align here. */
9914 frag_align (2, 0, 0);
9915 record_alignment (now_seg
, 2);
9920 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9922 /* When we mark a literal pool location, we want to put a frag in
9923 the literal pool that points to it. But to do that, we want to
9924 switch_to_literal_fragment. But literal sections don't have
9925 literal pools, so their location is always null, so we would
9926 recurse forever. This is kind of hacky, but it works. */
9928 static bfd_boolean recursive
= FALSE
;
9929 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9930 bfd_boolean is_init
=
9931 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9933 bfd_boolean is_fini
=
9934 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9936 if (pool_location
== NULL
9937 && !use_literal_section
9939 && !is_init
&& ! is_fini
)
9941 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9943 xtensa_mark_literal_pool_location ();
9947 /* Special case: If we are in the ".fini" or ".init" section, then
9948 we will ALWAYS be generating to the ".fini.literal" and
9949 ".init.literal" sections. */
9953 cache_literal_section (init_literal_head
,
9954 default_lit_sections
.init_lit_seg_name
,
9955 &default_lit_sections
.init_lit_seg
, TRUE
);
9956 xtensa_switch_section_emit_state (result
,
9957 default_lit_sections
.init_lit_seg
, 0);
9961 cache_literal_section (fini_literal_head
,
9962 default_lit_sections
.fini_lit_seg_name
,
9963 &default_lit_sections
.fini_lit_seg
, TRUE
);
9964 xtensa_switch_section_emit_state (result
,
9965 default_lit_sections
.fini_lit_seg
, 0);
9969 cache_literal_section (literal_head
,
9970 default_lit_sections
.lit_seg_name
,
9971 &default_lit_sections
.lit_seg
, TRUE
);
9972 xtensa_switch_section_emit_state (result
,
9973 default_lit_sections
.lit_seg
, 0);
9976 if (!use_literal_section
9977 && !is_init
&& !is_fini
9978 && get_literal_pool_location (now_seg
) != pool_location
)
9980 /* Close whatever frag is there. */
9981 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9982 xtensa_set_frag_assembly_state (frag_now
);
9983 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9984 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9985 xtensa_set_frag_assembly_state (frag_now
);
9990 /* Call this function before emitting data into the literal section.
9991 This is a helper function for xtensa_switch_to_literal_fragment.
9992 This is similar to a .section new_now_seg subseg. */
9995 xtensa_switch_section_emit_state (emit_state
*state
,
9997 subsegT new_now_subseg
)
9999 state
->name
= now_seg
->name
;
10000 state
->now_seg
= now_seg
;
10001 state
->now_subseg
= now_subseg
;
10002 state
->generating_literals
= generating_literals
;
10003 generating_literals
++;
10004 subseg_set (new_now_seg
, new_now_subseg
);
10008 /* Use to restore the emitting into the normal place. */
10011 xtensa_restore_emit_state (emit_state
*state
)
10013 generating_literals
= state
->generating_literals
;
10014 subseg_set (state
->now_seg
, state
->now_subseg
);
10018 /* Get a segment of a given name. If the segment is already
10019 present, return it; otherwise, create a new one. */
10022 cache_literal_section (seg_list
*head
,
10025 bfd_boolean is_code
)
10027 segT current_section
= now_seg
;
10028 int current_subsec
= now_subseg
;
10034 /* Check if the named section exists. */
10035 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10037 if (!strcmp (segment_name (seg
), name
))
10043 /* Create a new literal section. */
10044 seg
= subseg_new (name
, (subsegT
) 0);
10047 /* Add the newly created literal segment to the specified list. */
10048 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10050 n
->next
= head
->next
;
10053 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10054 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10055 | (is_code
? SEC_CODE
: SEC_DATA
));
10056 bfd_set_section_alignment (stdoutput
, seg
, 2);
10060 subseg_set (current_section
, current_subsec
);
10064 /* Property Tables Stuff. */
10066 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10067 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10068 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10070 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10071 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10073 static bfd_boolean
get_frag_is_literal (const fragS
*);
10074 static void xtensa_create_property_segments
10075 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10076 static void xtensa_create_xproperty_segments
10077 (frag_flags_fn
, const char *, xt_section_type
);
10078 static segment_info_type
*retrieve_segment_info (segT
);
10079 static segT
retrieve_xtensa_section (char *);
10080 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10081 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10082 static void add_xt_block_frags
10083 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10084 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10085 static void xtensa_frag_flags_init (frag_flags
*);
10086 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10087 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10088 static void add_xt_prop_frags
10089 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10091 /* Set up property tables after relaxation. */
10094 xtensa_post_relax_hook (void)
10096 xtensa_move_seg_list_to_beginning (literal_head
);
10097 xtensa_move_seg_list_to_beginning (init_literal_head
);
10098 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10100 xtensa_find_unmarked_state_frags ();
10102 xtensa_create_property_segments (get_frag_is_literal
,
10104 XTENSA_LIT_SEC_NAME
,
10106 xtensa_create_xproperty_segments (get_frag_property_flags
,
10107 XTENSA_PROP_SEC_NAME
,
10110 if (warn_unaligned_branch_targets
)
10111 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10112 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10116 /* This function is only meaningful after xtensa_move_literals. */
10119 get_frag_is_literal (const fragS
*fragP
)
10121 assert (fragP
!= NULL
);
10122 return fragP
->tc_frag_data
.is_literal
;
10127 xtensa_create_property_segments (frag_predicate property_function
,
10128 frag_predicate end_property_function
,
10129 const char *section_name_base
,
10130 xt_section_type sec_type
)
10134 /* Walk over all of the current segments.
10135 Walk over each fragment
10136 For each non-empty fragment,
10137 Build a property record (append where possible). */
10139 for (seclist
= &stdoutput
->sections
;
10140 seclist
&& *seclist
;
10141 seclist
= &(*seclist
)->next
)
10143 segT sec
= *seclist
;
10146 flags
= bfd_get_section_flags (stdoutput
, sec
);
10147 if (flags
& SEC_DEBUGGING
)
10149 if (!(flags
& SEC_ALLOC
))
10152 if (section_has_property (sec
, property_function
))
10154 char *property_section_name
=
10155 xtensa_get_property_section_name (sec
, section_name_base
);
10156 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10157 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10158 xtensa_block_info
**xt_blocks
=
10159 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10160 /* Walk over all of the frchains here and add new sections. */
10161 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10162 end_property_function
);
10166 /* Now we fill them out.... */
10168 for (seclist
= &stdoutput
->sections
;
10169 seclist
&& *seclist
;
10170 seclist
= &(*seclist
)->next
)
10172 segment_info_type
*seginfo
;
10173 xtensa_block_info
*block
;
10174 segT sec
= *seclist
;
10176 seginfo
= seg_info (sec
);
10177 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10181 xtensa_block_info
*cur_block
;
10182 /* This is a section with some data. */
10184 bfd_size_type rec_size
;
10186 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10189 rec_size
= num_recs
* 8;
10190 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10192 /* In order to make this work with the assembler, we have to
10193 build some frags and then build the "fixups" for it. It
10194 would be easier to just set the contents then set the
10199 /* Allocate a fragment and leak it. */
10201 bfd_size_type frag_size
;
10203 frchainS
*frchainP
;
10207 frag_size
= sizeof (fragS
) + rec_size
;
10208 fragP
= (fragS
*) xmalloc (frag_size
);
10210 memset (fragP
, 0, frag_size
);
10211 fragP
->fr_address
= 0;
10212 fragP
->fr_next
= NULL
;
10213 fragP
->fr_fix
= rec_size
;
10215 fragP
->fr_type
= rs_fill
;
10216 /* The rest are zeros. */
10218 frchainP
= seginfo
->frchainP
;
10219 frchainP
->frch_root
= fragP
;
10220 frchainP
->frch_last
= fragP
;
10222 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10223 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10225 seginfo
->fix_root
= fixes
;
10226 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10228 frag_data
= &fragP
->fr_literal
[0];
10229 for (i
= 0; i
< num_recs
; i
++)
10231 fixS
*fix
= &fixes
[i
];
10232 assert (cur_block
);
10234 /* Write the fixup. */
10235 if (i
!= num_recs
- 1)
10236 fix
->fx_next
= &fixes
[i
+ 1];
10238 fix
->fx_next
= NULL
;
10241 fix
->fx_frag
= fragP
;
10242 fix
->fx_where
= i
* 8;
10243 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10244 fix
->fx_offset
= cur_block
->offset
;
10245 fix
->fx_r_type
= BFD_RELOC_32
;
10246 fix
->fx_file
= "Internal Assembly";
10249 /* Write the length. */
10250 md_number_to_chars (&frag_data
[4 + 8 * i
],
10251 cur_block
->size
, 4);
10252 cur_block
= cur_block
->next
;
10261 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10262 const char *section_name_base
,
10263 xt_section_type sec_type
)
10267 /* Walk over all of the current segments.
10268 Walk over each fragment.
10269 For each fragment that has instructions,
10270 build an instruction record (append where possible). */
10272 for (seclist
= &stdoutput
->sections
;
10273 seclist
&& *seclist
;
10274 seclist
= &(*seclist
)->next
)
10276 segT sec
= *seclist
;
10279 flags
= bfd_get_section_flags (stdoutput
, sec
);
10280 if ((flags
& SEC_DEBUGGING
)
10281 || !(flags
& SEC_ALLOC
)
10282 || (flags
& SEC_MERGE
))
10285 if (section_has_xproperty (sec
, flag_fn
))
10287 char *property_section_name
=
10288 xtensa_get_property_section_name (sec
, section_name_base
);
10289 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10290 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10291 xtensa_block_info
**xt_blocks
=
10292 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10293 /* Walk over all of the frchains here and add new sections. */
10294 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10298 /* Now we fill them out.... */
10300 for (seclist
= &stdoutput
->sections
;
10301 seclist
&& *seclist
;
10302 seclist
= &(*seclist
)->next
)
10304 segment_info_type
*seginfo
;
10305 xtensa_block_info
*block
;
10306 segT sec
= *seclist
;
10308 seginfo
= seg_info (sec
);
10309 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10313 xtensa_block_info
*cur_block
;
10314 /* This is a section with some data. */
10316 bfd_size_type rec_size
;
10318 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10321 rec_size
= num_recs
* (8 + 4);
10322 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10324 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10326 /* In order to make this work with the assembler, we have to build
10327 some frags then build the "fixups" for it. It would be easier to
10328 just set the contents then set the arlents. */
10332 /* Allocate a fragment and (unfortunately) leak it. */
10334 bfd_size_type frag_size
;
10336 frchainS
*frchainP
;
10340 frag_size
= sizeof (fragS
) + rec_size
;
10341 fragP
= (fragS
*) xmalloc (frag_size
);
10343 memset (fragP
, 0, frag_size
);
10344 fragP
->fr_address
= 0;
10345 fragP
->fr_next
= NULL
;
10346 fragP
->fr_fix
= rec_size
;
10348 fragP
->fr_type
= rs_fill
;
10349 /* The rest are zeros. */
10351 frchainP
= seginfo
->frchainP
;
10352 frchainP
->frch_root
= fragP
;
10353 frchainP
->frch_last
= fragP
;
10355 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10356 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10358 seginfo
->fix_root
= fixes
;
10359 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10361 frag_data
= &fragP
->fr_literal
[0];
10362 for (i
= 0; i
< num_recs
; i
++)
10364 fixS
*fix
= &fixes
[i
];
10365 assert (cur_block
);
10367 /* Write the fixup. */
10368 if (i
!= num_recs
- 1)
10369 fix
->fx_next
= &fixes
[i
+ 1];
10371 fix
->fx_next
= NULL
;
10374 fix
->fx_frag
= fragP
;
10375 fix
->fx_where
= i
* (8 + 4);
10376 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10377 fix
->fx_offset
= cur_block
->offset
;
10378 fix
->fx_r_type
= BFD_RELOC_32
;
10379 fix
->fx_file
= "Internal Assembly";
10382 /* Write the length. */
10383 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10384 cur_block
->size
, 4);
10385 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10386 frag_flags_to_number (&cur_block
->flags
),
10388 cur_block
= cur_block
->next
;
10396 static segment_info_type
*
10397 retrieve_segment_info (segT seg
)
10399 segment_info_type
*seginfo
;
10400 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10403 frchainS
*frchainP
;
10405 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10406 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10407 seginfo
->fix_root
= NULL
;
10408 seginfo
->fix_tail
= NULL
;
10409 seginfo
->bfd_section
= seg
;
10411 /* We will not be dealing with these, only our special ones. */
10412 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10414 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10415 frchainP
->frch_root
= NULL
;
10416 frchainP
->frch_last
= NULL
;
10417 frchainP
->frch_next
= NULL
;
10418 frchainP
->frch_seg
= seg
;
10419 frchainP
->frch_subseg
= 0;
10420 frchainP
->fix_root
= NULL
;
10421 frchainP
->fix_tail
= NULL
;
10422 /* Do not init the objstack. */
10423 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10424 /* frchainP->frch_frag_now = fragP; */
10425 frchainP
->frch_frag_now
= NULL
;
10427 seginfo
->frchainP
= frchainP
;
10435 retrieve_xtensa_section (char *sec_name
)
10437 bfd
*abfd
= stdoutput
;
10438 flagword flags
, out_flags
, link_once_flags
;
10441 flags
= bfd_get_section_flags (abfd
, now_seg
);
10442 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10443 if (link_once_flags
)
10444 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10445 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10447 s
= bfd_make_section_old_way (abfd
, sec_name
);
10449 as_bad (_("could not create section %s"), sec_name
);
10450 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10451 as_bad (_("invalid flag combination on section %s"), sec_name
);
10458 section_has_property (segT sec
, frag_predicate property_function
)
10460 segment_info_type
*seginfo
= seg_info (sec
);
10463 if (seginfo
&& seginfo
->frchainP
)
10465 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10467 if (property_function (fragP
)
10468 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10477 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10479 segment_info_type
*seginfo
= seg_info (sec
);
10482 if (seginfo
&& seginfo
->frchainP
)
10484 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10486 frag_flags prop_flags
;
10487 property_function (fragP
, &prop_flags
);
10488 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10496 /* Two types of block sections exist right now: literal and insns. */
10499 add_xt_block_frags (segT sec
,
10501 xtensa_block_info
**xt_block
,
10502 frag_predicate property_function
,
10503 frag_predicate end_property_function
)
10505 segment_info_type
*seg_info
;
10506 segment_info_type
*xt_seg_info
;
10507 bfd_vma seg_offset
;
10510 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10511 seg_info
= retrieve_segment_info (sec
);
10513 /* Build it if needed. */
10514 while (*xt_block
!= NULL
)
10515 xt_block
= &(*xt_block
)->next
;
10516 /* We are either at NULL at the beginning or at the end. */
10518 /* Walk through the frags. */
10521 if (seg_info
->frchainP
)
10523 for (fragP
= seg_info
->frchainP
->frch_root
;
10525 fragP
= fragP
->fr_next
)
10527 if (property_function (fragP
)
10528 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10530 if (*xt_block
!= NULL
)
10532 if ((*xt_block
)->offset
+ (*xt_block
)->size
10533 == fragP
->fr_address
)
10534 (*xt_block
)->size
+= fragP
->fr_fix
;
10536 xt_block
= &((*xt_block
)->next
);
10538 if (*xt_block
== NULL
)
10540 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10541 xmalloc (sizeof (xtensa_block_info
));
10542 new_block
->sec
= sec
;
10543 new_block
->offset
= fragP
->fr_address
;
10544 new_block
->size
= fragP
->fr_fix
;
10545 new_block
->next
= NULL
;
10546 xtensa_frag_flags_init (&new_block
->flags
);
10547 *xt_block
= new_block
;
10549 if (end_property_function
10550 && end_property_function (fragP
))
10552 xt_block
= &((*xt_block
)->next
);
10560 /* Break the encapsulation of add_xt_prop_frags here. */
10563 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10565 if (prop_flags
->is_literal
10566 || prop_flags
->is_insn
10567 || prop_flags
->is_data
10568 || prop_flags
->is_unreachable
)
10575 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10577 memset (prop_flags
, 0, sizeof (frag_flags
));
10582 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10584 xtensa_frag_flags_init (prop_flags
);
10585 if (fragP
->tc_frag_data
.is_literal
)
10586 prop_flags
->is_literal
= TRUE
;
10587 if (fragP
->tc_frag_data
.is_unreachable
)
10588 prop_flags
->is_unreachable
= TRUE
;
10589 else if (fragP
->tc_frag_data
.is_insn
)
10591 prop_flags
->is_insn
= TRUE
;
10592 if (fragP
->tc_frag_data
.is_loop_target
)
10593 prop_flags
->insn
.is_loop_target
= TRUE
;
10594 if (fragP
->tc_frag_data
.is_branch_target
)
10595 prop_flags
->insn
.is_branch_target
= TRUE
;
10596 if (fragP
->tc_frag_data
.is_specific_opcode
10597 || fragP
->tc_frag_data
.is_no_transform
)
10598 prop_flags
->insn
.is_no_transform
= TRUE
;
10599 if (fragP
->tc_frag_data
.is_no_density
)
10600 prop_flags
->insn
.is_no_density
= TRUE
;
10601 if (fragP
->tc_frag_data
.use_absolute_literals
)
10602 prop_flags
->insn
.is_abslit
= TRUE
;
10604 if (fragP
->tc_frag_data
.is_align
)
10606 prop_flags
->is_align
= TRUE
;
10607 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10608 if (xtensa_frag_flags_is_empty (prop_flags
))
10609 prop_flags
->is_data
= TRUE
;
10615 frag_flags_to_number (const frag_flags
*prop_flags
)
10618 if (prop_flags
->is_literal
)
10619 num
|= XTENSA_PROP_LITERAL
;
10620 if (prop_flags
->is_insn
)
10621 num
|= XTENSA_PROP_INSN
;
10622 if (prop_flags
->is_data
)
10623 num
|= XTENSA_PROP_DATA
;
10624 if (prop_flags
->is_unreachable
)
10625 num
|= XTENSA_PROP_UNREACHABLE
;
10626 if (prop_flags
->insn
.is_loop_target
)
10627 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10628 if (prop_flags
->insn
.is_branch_target
)
10630 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10631 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10634 if (prop_flags
->insn
.is_no_density
)
10635 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10636 if (prop_flags
->insn
.is_no_transform
)
10637 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10638 if (prop_flags
->insn
.is_no_reorder
)
10639 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10640 if (prop_flags
->insn
.is_abslit
)
10641 num
|= XTENSA_PROP_INSN_ABSLIT
;
10643 if (prop_flags
->is_align
)
10645 num
|= XTENSA_PROP_ALIGN
;
10646 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10654 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10655 const frag_flags
*prop_flags_2
)
10657 /* Cannot combine with an end marker. */
10659 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10661 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10663 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10666 if (prop_flags_1
->is_insn
)
10668 /* Properties of the beginning of the frag. */
10669 if (prop_flags_2
->insn
.is_loop_target
)
10671 if (prop_flags_2
->insn
.is_branch_target
)
10673 if (prop_flags_1
->insn
.is_no_density
!=
10674 prop_flags_2
->insn
.is_no_density
)
10676 if (prop_flags_1
->insn
.is_no_transform
!=
10677 prop_flags_2
->insn
.is_no_transform
)
10679 if (prop_flags_1
->insn
.is_no_reorder
!=
10680 prop_flags_2
->insn
.is_no_reorder
)
10682 if (prop_flags_1
->insn
.is_abslit
!=
10683 prop_flags_2
->insn
.is_abslit
)
10687 if (prop_flags_1
->is_align
)
10695 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10698 unsigned align_bits
;
10700 if (!xt_block
->flags
.is_align
)
10701 return xt_block
->size
;
10703 end_addr
= xt_block
->offset
+ xt_block
->size
;
10704 align_bits
= xt_block
->flags
.alignment
;
10705 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10706 return end_addr
- xt_block
->offset
;
10711 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10712 const xtensa_block_info
*xt_block_2
)
10714 if (xt_block
->sec
!= xt_block_2
->sec
)
10716 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10717 != xt_block_2
->offset
)
10720 if (xt_block_2
->size
== 0
10721 && (!xt_block_2
->flags
.is_unreachable
10722 || xt_block
->flags
.is_unreachable
))
10724 if (xt_block_2
->flags
.is_align
10725 && xt_block
->flags
.is_align
)
10727 /* Nothing needed. */
10728 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10733 if (xt_block_2
->flags
.is_align
)
10735 /* Push alignment to previous entry. */
10736 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10737 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10742 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10743 &xt_block_2
->flags
))
10746 xt_block
->size
+= xt_block_2
->size
;
10748 if (xt_block_2
->flags
.is_align
)
10750 xt_block
->flags
.is_align
= TRUE
;
10751 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10759 add_xt_prop_frags (segT sec
,
10761 xtensa_block_info
**xt_block
,
10762 frag_flags_fn property_function
)
10764 segment_info_type
*seg_info
;
10765 segment_info_type
*xt_seg_info
;
10766 bfd_vma seg_offset
;
10769 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10770 seg_info
= retrieve_segment_info (sec
);
10771 /* Build it if needed. */
10772 while (*xt_block
!= NULL
)
10774 xt_block
= &(*xt_block
)->next
;
10776 /* We are either at NULL at the beginning or at the end. */
10778 /* Walk through the frags. */
10781 if (seg_info
->frchainP
)
10783 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10784 fragP
= fragP
->fr_next
)
10786 xtensa_block_info tmp_block
;
10787 tmp_block
.sec
= sec
;
10788 tmp_block
.offset
= fragP
->fr_address
;
10789 tmp_block
.size
= fragP
->fr_fix
;
10790 tmp_block
.next
= NULL
;
10791 property_function (fragP
, &tmp_block
.flags
);
10793 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10794 /* && fragP->fr_fix != 0) */
10796 if ((*xt_block
) == NULL
10797 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10799 xtensa_block_info
*new_block
;
10800 if ((*xt_block
) != NULL
)
10801 xt_block
= &(*xt_block
)->next
;
10802 new_block
= (xtensa_block_info
*)
10803 xmalloc (sizeof (xtensa_block_info
));
10804 *new_block
= tmp_block
;
10805 *xt_block
= new_block
;
10813 /* op_placement_info_table */
10815 /* op_placement_info makes it easier to determine which
10816 ops can go in which slots. */
10819 init_op_placement_info_table (void)
10821 xtensa_isa isa
= xtensa_default_isa
;
10822 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10823 xtensa_opcode opcode
;
10826 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10828 op_placement_table
= (op_placement_info_table
)
10829 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10830 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10832 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10834 op_placement_info
*opi
= &op_placement_table
[opcode
];
10835 /* FIXME: Make tinsn allocation dynamic. */
10836 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10837 as_fatal (_("too many operands in instruction"));
10838 opi
->narrowest
= XTENSA_UNDEFINED
;
10839 opi
->narrowest_size
= 0x7F;
10840 opi
->narrowest_slot
= 0;
10842 opi
->num_formats
= 0;
10844 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10846 opi
->slots
[fmt
] = 0;
10847 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10849 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10851 int fmt_length
= xtensa_format_length (isa
, fmt
);
10853 set_bit (fmt
, opi
->formats
);
10854 set_bit (slot
, opi
->slots
[fmt
]);
10855 /* opi->slot_count[fmt]++; */
10856 if (fmt_length
< opi
->narrowest_size
)
10858 opi
->narrowest
= fmt
;
10859 opi
->narrowest_size
= fmt_length
;
10860 opi
->narrowest_slot
= slot
;
10865 opi
->num_formats
++;
10868 xtensa_insnbuf_free (isa
, ibuf
);
10873 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10875 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10879 /* If the opcode is available in a single slot format, return its size. */
10882 xg_get_single_size (xtensa_opcode opcode
)
10884 return op_placement_table
[opcode
].narrowest_size
;
10888 static xtensa_format
10889 xg_get_single_format (xtensa_opcode opcode
)
10891 return op_placement_table
[opcode
].narrowest
;
10896 xg_get_single_slot (xtensa_opcode opcode
)
10898 return op_placement_table
[opcode
].narrowest_slot
;
10902 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10905 istack_init (IStack
*stack
)
10907 memset (stack
, 0, sizeof (IStack
));
10913 istack_empty (IStack
*stack
)
10915 return (stack
->ninsn
== 0);
10920 istack_full (IStack
*stack
)
10922 return (stack
->ninsn
== MAX_ISTACK
);
10926 /* Return a pointer to the top IStack entry.
10927 It is an error to call this if istack_empty () is TRUE. */
10930 istack_top (IStack
*stack
)
10932 int rec
= stack
->ninsn
- 1;
10933 assert (!istack_empty (stack
));
10934 return &stack
->insn
[rec
];
10938 /* Add a new TInsn to an IStack.
10939 It is an error to call this if istack_full () is TRUE. */
10942 istack_push (IStack
*stack
, TInsn
*insn
)
10944 int rec
= stack
->ninsn
;
10945 assert (!istack_full (stack
));
10946 stack
->insn
[rec
] = *insn
;
10951 /* Clear space for the next TInsn on the IStack and return a pointer
10952 to it. It is an error to call this if istack_full () is TRUE. */
10955 istack_push_space (IStack
*stack
)
10957 int rec
= stack
->ninsn
;
10959 assert (!istack_full (stack
));
10960 insn
= &stack
->insn
[rec
];
10961 memset (insn
, 0, sizeof (TInsn
));
10967 /* Remove the last pushed instruction. It is an error to call this if
10968 istack_empty () returns TRUE. */
10971 istack_pop (IStack
*stack
)
10973 int rec
= stack
->ninsn
- 1;
10974 assert (!istack_empty (stack
));
10976 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10980 /* TInsn functions. */
10983 tinsn_init (TInsn
*dst
)
10985 memset (dst
, 0, sizeof (TInsn
));
10989 /* Get the ``num''th token of the TInsn.
10990 It is illegal to call this if num > insn->ntoks. */
10993 tinsn_get_tok (TInsn
*insn
, int num
)
10995 assert (num
< insn
->ntok
);
10996 return &insn
->tok
[num
];
11000 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11003 tinsn_has_symbolic_operands (const TInsn
*insn
)
11006 int n
= insn
->ntok
;
11008 assert (insn
->insn_type
== ITYPE_INSN
);
11010 for (i
= 0; i
< n
; ++i
)
11012 switch (insn
->tok
[i
].X_op
)
11026 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11028 xtensa_isa isa
= xtensa_default_isa
;
11030 int n
= insn
->ntok
;
11032 assert (insn
->insn_type
== ITYPE_INSN
);
11034 for (i
= 0; i
< n
; ++i
)
11036 switch (insn
->tok
[i
].X_op
)
11044 /* Errors for these types are caught later. */
11049 /* Symbolic immediates are only allowed on the last immediate
11050 operand. At this time, CONST16 is the only opcode where we
11051 support non-PC-relative relocations. */
11052 if (i
!= get_relaxable_immed (insn
->opcode
)
11053 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11054 && insn
->opcode
!= xtensa_const16_opcode
))
11056 as_bad (_("invalid symbolic operand"));
11065 /* For assembly code with complex expressions (e.g. subtraction),
11066 we have to build them in the literal pool so that
11067 their results are calculated correctly after relaxation.
11068 The relaxation only handles expressions that
11069 boil down to SYMBOL + OFFSET. */
11072 tinsn_has_complex_operands (const TInsn
*insn
)
11075 int n
= insn
->ntok
;
11076 assert (insn
->insn_type
== ITYPE_INSN
);
11077 for (i
= 0; i
< n
; ++i
)
11079 switch (insn
->tok
[i
].X_op
)
11095 /* Encode a TInsn opcode and its constant operands into slotbuf.
11096 Return TRUE if there is a symbol in the immediate field. This
11097 function assumes that:
11098 1) The number of operands are correct.
11099 2) The insn_type is ITYPE_INSN.
11100 3) The opcode can be encoded in the specified format and slot.
11101 4) Operands are either O_constant or O_symbol, and all constants fit. */
11104 tinsn_to_slotbuf (xtensa_format fmt
,
11107 xtensa_insnbuf slotbuf
)
11109 xtensa_isa isa
= xtensa_default_isa
;
11110 xtensa_opcode opcode
= tinsn
->opcode
;
11111 bfd_boolean has_fixup
= FALSE
;
11112 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11115 assert (tinsn
->insn_type
== ITYPE_INSN
);
11116 if (noperands
!= tinsn
->ntok
)
11117 as_fatal (_("operand number mismatch"));
11119 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11121 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11122 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11126 for (i
= 0; i
< noperands
; i
++)
11128 expressionS
*expr
= &tinsn
->tok
[i
];
11134 switch (expr
->X_op
)
11137 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11139 /* The register number has already been checked in
11140 expression_maybe_register, so we don't need to check here. */
11141 opnd_value
= expr
->X_add_number
;
11142 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11143 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11146 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11150 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11152 as_where (&file_name
, &line
);
11153 /* It is a constant and we called this function
11154 then we have to try to fit it. */
11155 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11156 expr
->X_add_number
, file_name
, line
);
11169 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11170 into a multi-slot instruction, fill the other slots with NOPs.
11171 Return TRUE if there is a symbol in the immediate field. See also the
11172 assumptions listed for tinsn_to_slotbuf. */
11175 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11177 static xtensa_insnbuf slotbuf
= 0;
11178 static vliw_insn vinsn
;
11179 xtensa_isa isa
= xtensa_default_isa
;
11180 bfd_boolean has_fixup
= FALSE
;
11185 slotbuf
= xtensa_insnbuf_alloc (isa
);
11186 xg_init_vinsn (&vinsn
);
11189 xg_clear_vinsn (&vinsn
);
11191 bundle_tinsn (tinsn
, &vinsn
);
11193 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11195 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11197 /* Only one slot may have a fix-up because the rest contains NOPs. */
11199 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11200 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11207 /* Check the instruction arguments. Return TRUE on failure. */
11210 tinsn_check_arguments (const TInsn
*insn
)
11212 xtensa_isa isa
= xtensa_default_isa
;
11213 xtensa_opcode opcode
= insn
->opcode
;
11215 if (opcode
== XTENSA_UNDEFINED
)
11217 as_bad (_("invalid opcode"));
11221 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11223 as_bad (_("too few operands"));
11227 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11229 as_bad (_("too many operands"));
11236 /* Load an instruction from its encoded form. */
11239 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11243 xg_init_vinsn (&vinsn
);
11244 vinsn_from_chars (&vinsn
, f
);
11246 *tinsn
= vinsn
.slots
[slot
];
11247 xg_free_vinsn (&vinsn
);
11252 tinsn_from_insnbuf (TInsn
*tinsn
,
11253 xtensa_insnbuf slotbuf
,
11258 xtensa_isa isa
= xtensa_default_isa
;
11260 /* Find the immed. */
11261 tinsn_init (tinsn
);
11262 tinsn
->insn_type
= ITYPE_INSN
;
11263 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11264 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11265 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11266 for (i
= 0; i
< tinsn
->ntok
; i
++)
11268 set_expr_const (&tinsn
->tok
[i
],
11269 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11270 tinsn
->opcode
, i
));
11275 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11278 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11280 xtensa_opcode opcode
= tinsn
->opcode
;
11283 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11285 opnum
= get_relaxable_immed (opcode
);
11286 assert (opnum
>= 0);
11287 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11288 fragP
->tc_frag_data
.slot_symbols
[slot
],
11289 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11295 get_num_stack_text_bytes (IStack
*istack
)
11298 int text_bytes
= 0;
11300 for (i
= 0; i
< istack
->ninsn
; i
++)
11302 TInsn
*tinsn
= &istack
->insn
[i
];
11303 if (tinsn
->insn_type
== ITYPE_INSN
)
11304 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11311 get_num_stack_literal_bytes (IStack
*istack
)
11316 for (i
= 0; i
< istack
->ninsn
; i
++)
11318 TInsn
*tinsn
= &istack
->insn
[i
];
11319 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11326 /* vliw_insn functions. */
11329 xg_init_vinsn (vliw_insn
*v
)
11332 xtensa_isa isa
= xtensa_default_isa
;
11334 xg_clear_vinsn (v
);
11336 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11337 if (v
->insnbuf
== NULL
)
11338 as_fatal (_("out of memory"));
11340 for (i
= 0; i
< MAX_SLOTS
; i
++)
11342 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11343 if (v
->slotbuf
[i
] == NULL
)
11344 as_fatal (_("out of memory"));
11350 xg_clear_vinsn (vliw_insn
*v
)
11354 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11356 v
->format
= XTENSA_UNDEFINED
;
11358 v
->inside_bundle
= FALSE
;
11360 if (xt_saved_debug_type
!= DEBUG_NONE
)
11361 debug_type
= xt_saved_debug_type
;
11363 for (i
= 0; i
< MAX_SLOTS
; i
++)
11364 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11369 vinsn_has_specific_opcodes (vliw_insn
*v
)
11373 for (i
= 0; i
< v
->num_slots
; i
++)
11375 if (v
->slots
[i
].is_specific_opcode
)
11383 xg_free_vinsn (vliw_insn
*v
)
11386 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11387 for (i
= 0; i
< MAX_SLOTS
; i
++)
11388 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11392 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11393 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11396 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11399 bfd_boolean record_fixup
)
11401 xtensa_isa isa
= xtensa_default_isa
;
11402 xtensa_format fmt
= vinsn
->format
;
11403 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11405 bfd_boolean has_fixup
= FALSE
;
11407 xtensa_format_encode (isa
, fmt
, insnbuf
);
11409 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11411 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11412 bfd_boolean tinsn_has_fixup
=
11413 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11414 vinsn
->slotbuf
[slot
]);
11416 xtensa_format_set_slot (isa
, fmt
, slot
,
11417 insnbuf
, vinsn
->slotbuf
[slot
]);
11418 if (tinsn_has_fixup
)
11421 xtensa_opcode opcode
= tinsn
->opcode
;
11422 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11425 for (i
= 0; i
< noperands
; i
++)
11427 expressionS
* expr
= &tinsn
->tok
[i
];
11428 switch (expr
->X_op
)
11433 if (get_relaxable_immed (opcode
) == i
)
11435 /* Add a fix record for the instruction, except if this
11436 function is being called prior to relaxation, i.e.,
11437 if record_fixup is false, and the instruction might
11438 be relaxed later. */
11440 || tinsn
->is_specific_opcode
11441 || !xg_is_relaxable_insn (tinsn
, 0))
11443 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11444 frag_offset
- fragP
->fr_literal
);
11448 if (expr
->X_op
!= O_symbol
)
11449 as_bad (_("invalid operand"));
11450 tinsn
->symbol
= expr
->X_add_symbol
;
11451 tinsn
->offset
= expr
->X_add_number
;
11455 as_bad (_("symbolic operand not allowed"));
11463 as_bad (_("expression too complex"));
11475 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11477 static xtensa_insnbuf insnbuf
= NULL
;
11478 static xtensa_insnbuf slotbuf
= NULL
;
11481 xtensa_isa isa
= xtensa_default_isa
;
11485 insnbuf
= xtensa_insnbuf_alloc (isa
);
11486 slotbuf
= xtensa_insnbuf_alloc (isa
);
11489 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11490 fmt
= xtensa_format_decode (isa
, insnbuf
);
11491 if (fmt
== XTENSA_UNDEFINED
)
11492 as_fatal (_("cannot decode instruction format"));
11493 vinsn
->format
= fmt
;
11494 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11496 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11498 TInsn
*tinsn
= &vinsn
->slots
[i
];
11499 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11500 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11505 /* Expression utilities. */
11507 /* Return TRUE if the expression is an integer constant. */
11510 expr_is_const (const expressionS
*s
)
11512 return (s
->X_op
== O_constant
);
11516 /* Get the expression constant.
11517 Calling this is illegal if expr_is_const () returns TRUE. */
11520 get_expr_const (const expressionS
*s
)
11522 assert (expr_is_const (s
));
11523 return s
->X_add_number
;
11527 /* Set the expression to a constant value. */
11530 set_expr_const (expressionS
*s
, offsetT val
)
11532 s
->X_op
= O_constant
;
11533 s
->X_add_number
= val
;
11534 s
->X_add_symbol
= NULL
;
11535 s
->X_op_symbol
= NULL
;
11540 expr_is_register (const expressionS
*s
)
11542 return (s
->X_op
== O_register
);
11546 /* Get the expression constant.
11547 Calling this is illegal if expr_is_const () returns TRUE. */
11550 get_expr_register (const expressionS
*s
)
11552 assert (expr_is_register (s
));
11553 return s
->X_add_number
;
11557 /* Set the expression to a symbol + constant offset. */
11560 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11562 s
->X_op
= O_symbol
;
11563 s
->X_add_symbol
= sym
;
11564 s
->X_op_symbol
= NULL
; /* unused */
11565 s
->X_add_number
= offset
;
11569 /* Return TRUE if the two expressions are equal. */
11572 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11574 if (s1
->X_op
!= s2
->X_op
)
11576 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11578 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11580 if (s1
->X_add_number
!= s2
->X_add_number
)
11587 copy_expr (expressionS
*dst
, const expressionS
*src
)
11589 memcpy (dst
, src
, sizeof (expressionS
));
11593 /* Support for the "--rename-section" option. */
11595 struct rename_section_struct
11599 struct rename_section_struct
*next
;
11602 static struct rename_section_struct
*section_rename
;
11605 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11606 entries to the section_rename list. Note: Specifying multiple
11607 renamings separated by colons is not documented and is retained only
11608 for backward compatibility. */
11611 build_section_rename (const char *arg
)
11613 struct rename_section_struct
*r
;
11614 char *this_arg
= NULL
;
11615 char *next_arg
= NULL
;
11617 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11619 char *old_name
, *new_name
;
11623 next_arg
= strchr (this_arg
, ':');
11631 old_name
= this_arg
;
11632 new_name
= strchr (this_arg
, '=');
11634 if (*old_name
== '\0')
11636 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11639 if (!new_name
|| new_name
[1] == '\0')
11641 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11648 /* Check for invalid section renaming. */
11649 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11651 if (strcmp (r
->old_name
, old_name
) == 0)
11652 as_bad (_("section %s renamed multiple times"), old_name
);
11653 if (strcmp (r
->new_name
, new_name
) == 0)
11654 as_bad (_("multiple sections remapped to output section %s"),
11659 r
= (struct rename_section_struct
*)
11660 xmalloc (sizeof (struct rename_section_struct
));
11661 r
->old_name
= xstrdup (old_name
);
11662 r
->new_name
= xstrdup (new_name
);
11663 r
->next
= section_rename
;
11664 section_rename
= r
;
11670 xtensa_section_rename (char *name
)
11672 struct rename_section_struct
*r
= section_rename
;
11674 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11676 if (strcmp (r
->old_name
, name
) == 0)
11677 return r
->new_name
;