1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
32 #include "elf/xtensa.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
;
76 bfd_boolean absolute_literals_supported
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
218 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
219 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
222 /* Alignment is specified in the block BEFORE the one that needs
223 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
224 get the required alignment specified as a power of 2. Use
225 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
226 alignment. Be careful of side effects since the SET will evaluate
227 flags twice. Also, note that the SIZE of a block in the property
228 table does not include the alignment size, so the alignment fill
229 must be calculated to determine if two blocks are contiguous.
230 TEXT_ALIGN is not currently implemented but is a placeholder for a
231 possible future implementation. */
233 #define XTENSA_PROP_ALIGN 0x00000800
235 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
237 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
238 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
239 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
241 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
244 /* Structure for saving instruction and alignment per-fragment data
245 that will be written to the object file. This structure is
246 equivalent to the actual data that will be written out to the file
247 but is easier to use. We provide a conversion to file flags
248 in frag_flags_to_number. */
250 typedef struct frag_flags_struct frag_flags
;
252 struct frag_flags_struct
254 /* is_literal should only be used after xtensa_move_literals.
255 If you need to check if you are generating a literal fragment,
256 then use the generating_literals global. */
258 unsigned is_literal
: 1;
259 unsigned is_insn
: 1;
260 unsigned is_data
: 1;
261 unsigned is_unreachable
: 1;
263 /* is_specific_opcode implies no_transform. */
264 unsigned is_no_transform
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
275 unsigned is_no_reorder
: 1;
277 /* Uses absolute literal addressing for l32r. */
278 unsigned is_abslit
: 1;
280 unsigned is_align
: 1;
281 unsigned alignment
: 5;
285 /* Structure for saving information about a block of property data
286 for frags that have the same flags. */
287 struct xtensa_block_info_struct
293 struct xtensa_block_info_struct
*next
;
297 /* Structure for saving the current state before emitting literals. */
298 typedef struct emit_state_struct
303 int generating_literals
;
307 /* Opcode placement information */
309 typedef unsigned long long bitfield
;
310 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
311 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
312 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
314 #define MAX_FORMATS 32
316 typedef struct op_placement_info_struct
319 /* A number describing how restrictive the issue is for this
320 opcode. For example, an opcode that fits lots of different
321 formats has a high freedom, as does an opcode that fits
322 only one format but many slots in that format. The most
323 restrictive is the opcode that fits only one slot in one
326 xtensa_format narrowest
;
330 /* formats is a bitfield with the Nth bit set
331 if the opcode fits in the Nth xtensa_format. */
334 /* slots[N]'s Mth bit is set if the op fits in the
335 Mth slot of the Nth xtensa_format. */
336 bitfield slots
[MAX_FORMATS
];
338 /* A count of the number of slots in a given format
339 an op can fit (i.e., the bitcount of the slot field above). */
340 char slots_in_format
[MAX_FORMATS
];
342 } op_placement_info
, *op_placement_info_table
;
344 op_placement_info_table op_placement_table
;
347 /* Extra expression types. */
349 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
350 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
351 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
352 #define O_pcrel O_md4 /* value is a PC-relative offset */
353 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
354 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
355 #define O_tlscall O_md7 /* TLS_CALL relocation */
356 #define O_tpoff O_md8 /* TPOFF relocation */
357 #define O_dtpoff O_md9 /* DTPOFF relocation */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
376 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
377 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
378 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
379 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
393 directive_literal_prefix
,
395 directive_absolute_literals
,
396 directive_last_directive
402 bfd_boolean can_be_negated
;
405 const directive_infoS directive_info
[] =
408 { "literal", FALSE
},
410 { "transform", TRUE
},
411 { "freeregs", FALSE
},
412 { "longcalls", TRUE
},
413 { "literal_prefix", FALSE
},
414 { "schedule", TRUE
},
415 { "absolute-literals", TRUE
}
418 bfd_boolean directive_state
[] =
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 FALSE
/* absolute_literals */
431 /* A circular list of all potential and actual literal pool locations
435 struct litpool_frag
*next
;
436 struct litpool_frag
*prev
;
439 short priority
; /* 1, 2, or 3 -- 1 is highest */
440 short original_priority
;
443 /* Map a segment to its litpool_frag list. */
446 struct litpool_seg
*next
;
448 struct litpool_frag frag_list
;
449 int frag_count
; /* since last litpool location */
452 static struct litpool_seg litpool_seg_list
;
455 /* Directive functions. */
457 static void xtensa_begin_directive (int);
458 static void xtensa_end_directive (int);
459 static void xtensa_literal_prefix (void);
460 static void xtensa_literal_position (int);
461 static void xtensa_literal_pseudo (int);
462 static void xtensa_frequency_pseudo (int);
463 static void xtensa_elf_cons (int);
464 static void xtensa_leb128 (int);
466 /* Parsing and Idiom Translation. */
468 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
470 /* Various Other Internal Functions. */
472 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
473 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
474 static void xtensa_mark_literal_pool_location (void);
475 static addressT
get_expanded_loop_offset (xtensa_opcode
);
476 static fragS
*get_literal_pool_location (segT
);
477 static void set_literal_pool_location (segT
, fragS
*);
478 static void xtensa_set_frag_assembly_state (fragS
*);
479 static void finish_vinsn (vliw_insn
*);
480 static bfd_boolean
emit_single_op (TInsn
*);
481 static int total_frag_text_expansion (fragS
*);
482 static bfd_boolean use_trampolines
= TRUE
;
483 static void xtensa_check_frag_count (void);
484 static void xtensa_create_trampoline_frag (bfd_boolean
);
485 static void xtensa_maybe_create_trampoline_frag (void);
486 struct trampoline_frag
;
487 static int init_trampoline_frag (struct trampoline_frag
*);
488 static fixS
*xg_append_jump (fragS
*fragP
, fixS
*jump_around
,
489 symbolS
*sym
, offsetT offset
);
490 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
491 static bfd_boolean auto_litpools
= FALSE
;
492 static int auto_litpool_limit
= 10000;
494 /* Alignment Functions. */
496 static int get_text_align_power (unsigned);
497 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
498 static int branch_align_power (segT
);
500 /* Helpers for xtensa_relax_frag(). */
502 static long relax_frag_add_nop (fragS
*);
504 /* Accessors for additional per-subsegment information. */
506 static unsigned get_last_insn_flags (segT
, subsegT
);
507 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
508 static float get_subseg_total_freq (segT
, subsegT
);
509 static float get_subseg_target_freq (segT
, subsegT
);
510 static void set_subseg_freq (segT
, subsegT
, float, float);
512 /* Segment list functions. */
514 static void xtensa_move_literals (void);
515 static void xtensa_reorder_segments (void);
516 static void xtensa_switch_to_literal_fragment (emit_state
*);
517 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
518 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
519 static void xtensa_restore_emit_state (emit_state
*);
520 static segT
cache_literal_section (bfd_boolean
);
522 /* op_placement_info functions. */
524 static void init_op_placement_info_table (void);
525 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
526 static int xg_get_single_size (xtensa_opcode
);
527 static xtensa_format
xg_get_single_format (xtensa_opcode
);
528 static int xg_get_single_slot (xtensa_opcode
);
530 /* TInsn and IStack functions. */
532 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
533 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
534 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
535 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
536 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
537 static void tinsn_from_chars (TInsn
*, char *, int);
538 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
539 static int get_num_stack_text_bytes (IStack
*);
540 static int get_num_stack_literal_bytes (IStack
*);
541 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
543 /* vliw_insn functions. */
545 static void xg_init_vinsn (vliw_insn
*);
546 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
547 static void xg_clear_vinsn (vliw_insn
*);
548 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
549 static void xg_free_vinsn (vliw_insn
*);
550 static bfd_boolean vinsn_to_insnbuf
551 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
552 static void vinsn_from_chars (vliw_insn
*, char *);
554 /* Expression Utilities. */
556 bfd_boolean
expr_is_const (const expressionS
*);
557 offsetT
get_expr_const (const expressionS
*);
558 void set_expr_const (expressionS
*, offsetT
);
559 bfd_boolean
expr_is_register (const expressionS
*);
560 offsetT
get_expr_register (const expressionS
*);
561 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
562 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
563 static void copy_expr (expressionS
*, const expressionS
*);
565 /* Section renaming. */
567 static void build_section_rename (const char *);
570 /* ISA imported from bfd. */
571 extern xtensa_isa xtensa_default_isa
;
573 extern int target_big_endian
;
575 static xtensa_opcode xtensa_addi_opcode
;
576 static xtensa_opcode xtensa_addmi_opcode
;
577 static xtensa_opcode xtensa_call0_opcode
;
578 static xtensa_opcode xtensa_call4_opcode
;
579 static xtensa_opcode xtensa_call8_opcode
;
580 static xtensa_opcode xtensa_call12_opcode
;
581 static xtensa_opcode xtensa_callx0_opcode
;
582 static xtensa_opcode xtensa_callx4_opcode
;
583 static xtensa_opcode xtensa_callx8_opcode
;
584 static xtensa_opcode xtensa_callx12_opcode
;
585 static xtensa_opcode xtensa_const16_opcode
;
586 static xtensa_opcode xtensa_entry_opcode
;
587 static xtensa_opcode xtensa_extui_opcode
;
588 static xtensa_opcode xtensa_movi_opcode
;
589 static xtensa_opcode xtensa_movi_n_opcode
;
590 static xtensa_opcode xtensa_isync_opcode
;
591 static xtensa_opcode xtensa_j_opcode
;
592 static xtensa_opcode xtensa_jx_opcode
;
593 static xtensa_opcode xtensa_l32r_opcode
;
594 static xtensa_opcode xtensa_loop_opcode
;
595 static xtensa_opcode xtensa_loopnez_opcode
;
596 static xtensa_opcode xtensa_loopgtz_opcode
;
597 static xtensa_opcode xtensa_nop_opcode
;
598 static xtensa_opcode xtensa_nop_n_opcode
;
599 static xtensa_opcode xtensa_or_opcode
;
600 static xtensa_opcode xtensa_ret_opcode
;
601 static xtensa_opcode xtensa_ret_n_opcode
;
602 static xtensa_opcode xtensa_retw_opcode
;
603 static xtensa_opcode xtensa_retw_n_opcode
;
604 static xtensa_opcode xtensa_rsr_lcount_opcode
;
605 static xtensa_opcode xtensa_waiti_opcode
;
606 static int config_max_slots
= 0;
609 /* Command-line Options. */
611 bfd_boolean use_literal_section
= TRUE
;
612 enum flix_level produce_flix
= FLIX_ALL
;
613 static bfd_boolean align_targets
= TRUE
;
614 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
615 static bfd_boolean has_a0_b_retw
= FALSE
;
616 static bfd_boolean workaround_a0_b_retw
= FALSE
;
617 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
618 static bfd_boolean workaround_short_loop
= FALSE
;
619 static bfd_boolean maybe_has_short_loop
= FALSE
;
620 static bfd_boolean workaround_close_loop_end
= FALSE
;
621 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
622 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
624 /* When workaround_short_loops is TRUE, all loops with early exits must
625 have at least 3 instructions. workaround_all_short_loops is a modifier
626 to the workaround_short_loop flag. In addition to the
627 workaround_short_loop actions, all straightline loopgtz and loopnez
628 must have at least 3 instructions. */
630 static bfd_boolean workaround_all_short_loops
= FALSE
;
634 xtensa_setup_hw_workarounds (int earliest
, int latest
)
636 if (earliest
> latest
)
637 as_fatal (_("illegal range of target hardware versions"));
639 /* Enable all workarounds for pre-T1050.0 hardware. */
640 if (earliest
< 105000 || latest
< 105000)
642 workaround_a0_b_retw
|= TRUE
;
643 workaround_b_j_loop_end
|= TRUE
;
644 workaround_short_loop
|= TRUE
;
645 workaround_close_loop_end
|= TRUE
;
646 workaround_all_short_loops
|= TRUE
;
647 enforce_three_byte_loop_align
= TRUE
;
654 option_density
= OPTION_MD_BASE
,
658 option_no_generate_flix
,
665 option_no_link_relax
,
673 option_text_section_literals
,
674 option_no_text_section_literals
,
676 option_absolute_literals
,
677 option_no_absolute_literals
,
679 option_align_targets
,
680 option_no_align_targets
,
682 option_warn_unaligned_targets
,
687 option_workaround_a0_b_retw
,
688 option_no_workaround_a0_b_retw
,
690 option_workaround_b_j_loop_end
,
691 option_no_workaround_b_j_loop_end
,
693 option_workaround_short_loop
,
694 option_no_workaround_short_loop
,
696 option_workaround_all_short_loops
,
697 option_no_workaround_all_short_loops
,
699 option_workaround_close_loop_end
,
700 option_no_workaround_close_loop_end
,
702 option_no_workarounds
,
704 option_rename_section_name
,
707 option_prefer_const16
,
709 option_target_hardware
,
712 option_no_trampolines
,
714 option_auto_litpools
,
715 option_no_auto_litpools
,
716 option_auto_litpool_limit
,
719 const char *md_shortopts
= "";
721 struct option md_longopts
[] =
723 { "density", no_argument
, NULL
, option_density
},
724 { "no-density", no_argument
, NULL
, option_no_density
},
726 { "flix", no_argument
, NULL
, option_flix
},
727 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
728 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
730 /* Both "relax" and "generics" are deprecated and treated as equivalent
731 to the "transform" option. */
732 { "relax", no_argument
, NULL
, option_relax
},
733 { "no-relax", no_argument
, NULL
, option_no_relax
},
734 { "generics", no_argument
, NULL
, option_generics
},
735 { "no-generics", no_argument
, NULL
, option_no_generics
},
737 { "transform", no_argument
, NULL
, option_transform
},
738 { "no-transform", no_argument
, NULL
, option_no_transform
},
739 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
740 { "no-text-section-literals", no_argument
, NULL
,
741 option_no_text_section_literals
},
742 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
743 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
744 /* This option was changed from -align-target to -target-align
745 because it conflicted with the "-al" option. */
746 { "target-align", no_argument
, NULL
, option_align_targets
},
747 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
748 { "warn-unaligned-targets", no_argument
, NULL
,
749 option_warn_unaligned_targets
},
750 { "longcalls", no_argument
, NULL
, option_longcalls
},
751 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
753 { "no-workaround-a0-b-retw", no_argument
, NULL
,
754 option_no_workaround_a0_b_retw
},
755 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
757 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
758 option_no_workaround_b_j_loop_end
},
759 { "workaround-b-j-loop-end", no_argument
, NULL
,
760 option_workaround_b_j_loop_end
},
762 { "no-workaround-short-loops", no_argument
, NULL
,
763 option_no_workaround_short_loop
},
764 { "workaround-short-loops", no_argument
, NULL
,
765 option_workaround_short_loop
},
767 { "no-workaround-all-short-loops", no_argument
, NULL
,
768 option_no_workaround_all_short_loops
},
769 { "workaround-all-short-loop", no_argument
, NULL
,
770 option_workaround_all_short_loops
},
772 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
773 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
775 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
777 { "no-workaround-close-loop-end", no_argument
, NULL
,
778 option_no_workaround_close_loop_end
},
779 { "workaround-close-loop-end", no_argument
, NULL
,
780 option_workaround_close_loop_end
},
782 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
784 { "link-relax", no_argument
, NULL
, option_link_relax
},
785 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
787 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
789 { "trampolines", no_argument
, NULL
, option_trampolines
},
790 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
792 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
793 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
794 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
796 { NULL
, no_argument
, NULL
, 0 }
799 size_t md_longopts_size
= sizeof md_longopts
;
803 md_parse_option (int c
, const char *arg
)
808 as_warn (_("--density option is ignored"));
810 case option_no_density
:
811 as_warn (_("--no-density option is ignored"));
813 case option_link_relax
:
816 case option_no_link_relax
:
820 produce_flix
= FLIX_ALL
;
822 case option_no_generate_flix
:
823 produce_flix
= FLIX_NO_GENERATE
;
826 produce_flix
= FLIX_NONE
;
828 case option_generics
:
829 as_warn (_("--generics is deprecated; use --transform instead"));
830 return md_parse_option (option_transform
, arg
);
831 case option_no_generics
:
832 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
833 return md_parse_option (option_no_transform
, arg
);
835 as_warn (_("--relax is deprecated; use --transform instead"));
836 return md_parse_option (option_transform
, arg
);
837 case option_no_relax
:
838 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
839 return md_parse_option (option_no_transform
, arg
);
840 case option_longcalls
:
841 directive_state
[directive_longcalls
] = TRUE
;
843 case option_no_longcalls
:
844 directive_state
[directive_longcalls
] = FALSE
;
846 case option_text_section_literals
:
847 use_literal_section
= FALSE
;
849 case option_no_text_section_literals
:
850 use_literal_section
= TRUE
;
852 case option_absolute_literals
:
853 if (!absolute_literals_supported
)
855 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
858 directive_state
[directive_absolute_literals
] = TRUE
;
860 case option_no_absolute_literals
:
861 directive_state
[directive_absolute_literals
] = FALSE
;
864 case option_workaround_a0_b_retw
:
865 workaround_a0_b_retw
= TRUE
;
867 case option_no_workaround_a0_b_retw
:
868 workaround_a0_b_retw
= FALSE
;
870 case option_workaround_b_j_loop_end
:
871 workaround_b_j_loop_end
= TRUE
;
873 case option_no_workaround_b_j_loop_end
:
874 workaround_b_j_loop_end
= FALSE
;
877 case option_workaround_short_loop
:
878 workaround_short_loop
= TRUE
;
880 case option_no_workaround_short_loop
:
881 workaround_short_loop
= FALSE
;
884 case option_workaround_all_short_loops
:
885 workaround_all_short_loops
= TRUE
;
887 case option_no_workaround_all_short_loops
:
888 workaround_all_short_loops
= FALSE
;
891 case option_workaround_close_loop_end
:
892 workaround_close_loop_end
= TRUE
;
894 case option_no_workaround_close_loop_end
:
895 workaround_close_loop_end
= FALSE
;
898 case option_no_workarounds
:
899 workaround_a0_b_retw
= FALSE
;
900 workaround_b_j_loop_end
= FALSE
;
901 workaround_short_loop
= FALSE
;
902 workaround_all_short_loops
= FALSE
;
903 workaround_close_loop_end
= FALSE
;
906 case option_align_targets
:
907 align_targets
= TRUE
;
909 case option_no_align_targets
:
910 align_targets
= FALSE
;
913 case option_warn_unaligned_targets
:
914 warn_unaligned_branch_targets
= TRUE
;
917 case option_rename_section_name
:
918 build_section_rename (arg
);
922 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
923 should be emitted or not. FIXME: Not implemented. */
926 case option_prefer_l32r
:
928 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
932 case option_prefer_const16
:
934 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
938 case option_target_hardware
:
940 int earliest
, latest
= 0;
942 if (*arg
== 0 || *arg
== '-')
943 as_fatal (_("invalid target hardware version"));
945 earliest
= strtol (arg
, &end
, 0);
949 else if (*end
== '-')
952 as_fatal (_("invalid target hardware version"));
953 latest
= strtol (end
, &end
, 0);
956 as_fatal (_("invalid target hardware version"));
958 xtensa_setup_hw_workarounds (earliest
, latest
);
962 case option_transform
:
963 /* This option has no affect other than to use the defaults,
964 which are already set. */
967 case option_no_transform
:
968 /* This option turns off all transformations of any kind.
969 However, because we want to preserve the state of other
970 directives, we only change its own field. Thus, before
971 you perform any transformation, always check if transform
972 is available. If you use the functions we provide for this
973 purpose, you will be ok. */
974 directive_state
[directive_transform
] = FALSE
;
977 case option_trampolines
:
978 use_trampolines
= TRUE
;
981 case option_no_trampolines
:
982 use_trampolines
= FALSE
;
985 case option_auto_litpools
:
986 auto_litpools
= TRUE
;
987 use_literal_section
= FALSE
;
990 case option_no_auto_litpools
:
991 auto_litpools
= FALSE
;
992 auto_litpool_limit
= -1;
995 case option_auto_litpool_limit
:
999 if (auto_litpool_limit
< 0)
1000 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1001 if (*arg
== 0 || *arg
== '-')
1002 as_fatal (_("invalid auto-litpool-limit argument"));
1003 value
= strtol (arg
, &end
, 10);
1005 as_fatal (_("invalid auto-litpool-limit argument"));
1006 if (value
< 100 || value
> 10000)
1007 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1008 auto_litpool_limit
= value
;
1009 auto_litpools
= TRUE
;
1010 use_literal_section
= FALSE
;
1021 md_show_usage (FILE *stream
)
1025 --[no-]text-section-literals\n\
1026 [Do not] put literals in the text section\n\
1027 --[no-]absolute-literals\n\
1028 [Do not] default to use non-PC-relative literals\n\
1029 --[no-]target-align [Do not] try to align branch targets\n\
1030 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1031 --[no-]transform [Do not] transform instructions\n\
1032 --flix both allow hand-written and generate flix bundles\n\
1033 --no-generate-flix allow hand-written but do not generate\n\
1035 --no-allow-flix neither allow hand-written nor generate\n\
1037 --rename-section old=new Rename section 'old' to 'new'\n\
1038 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1039 when jumps do not reach their targets\n\
1040 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1041 --auto-litpool-limit=<value>\n\
1042 (range 100-10000) Maximum number of blocks of\n\
1043 instructions to emit between literal pool\n\
1044 locations; implies --auto-litpools flag\n", stream
);
1048 /* Functions related to the list of current label symbols. */
1051 xtensa_add_insn_label (symbolS
*sym
)
1055 if (!free_insn_labels
)
1056 l
= XNEW (sym_list
);
1059 l
= free_insn_labels
;
1060 free_insn_labels
= l
->next
;
1064 l
->next
= insn_labels
;
1070 xtensa_clear_insn_labels (void)
1074 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1082 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1086 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1088 symbolS
*lit_sym
= lit
->sym
;
1089 S_SET_VALUE (lit_sym
, new_offset
);
1090 symbol_set_frag (lit_sym
, new_frag
);
1095 /* Directive data and functions. */
1097 typedef struct state_stackS_struct
1099 directiveE directive
;
1100 bfd_boolean negated
;
1101 bfd_boolean old_state
;
1105 struct state_stackS_struct
*prev
;
1108 state_stackS
*directive_state_stack
;
1110 const pseudo_typeS md_pseudo_table
[] =
1112 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1113 { "literal_position", xtensa_literal_position
, 0 },
1114 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1115 { "long", xtensa_elf_cons
, 4 },
1116 { "word", xtensa_elf_cons
, 4 },
1117 { "4byte", xtensa_elf_cons
, 4 },
1118 { "short", xtensa_elf_cons
, 2 },
1119 { "2byte", xtensa_elf_cons
, 2 },
1120 { "sleb128", xtensa_leb128
, 1},
1121 { "uleb128", xtensa_leb128
, 0},
1122 { "begin", xtensa_begin_directive
, 0 },
1123 { "end", xtensa_end_directive
, 0 },
1124 { "literal", xtensa_literal_pseudo
, 0 },
1125 { "frequency", xtensa_frequency_pseudo
, 0 },
1131 use_transform (void)
1133 /* After md_end, you should be checking frag by frag, rather
1134 than state directives. */
1135 gas_assert (!past_xtensa_end
);
1136 return directive_state
[directive_transform
];
1141 do_align_targets (void)
1143 /* Do not use this function after md_end; just look at align_targets
1144 instead. There is no target-align directive, so alignment is either
1145 enabled for all frags or not done at all. */
1146 gas_assert (!past_xtensa_end
);
1147 return align_targets
&& use_transform ();
1152 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1156 state_stackS
*stack
= XNEW (state_stackS
);
1158 file
= as_where (&line
);
1160 stack
->directive
= directive
;
1161 stack
->negated
= negated
;
1162 stack
->old_state
= directive_state
[directive
];
1165 stack
->datum
= datum
;
1166 stack
->prev
= directive_state_stack
;
1167 directive_state_stack
= stack
;
1169 directive_state
[directive
] = !negated
;
1174 directive_pop (directiveE
*directive
,
1175 bfd_boolean
*negated
,
1180 state_stackS
*top
= directive_state_stack
;
1182 if (!directive_state_stack
)
1184 as_bad (_("unmatched .end directive"));
1185 *directive
= directive_none
;
1189 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1190 *directive
= top
->directive
;
1191 *negated
= top
->negated
;
1194 *datum
= top
->datum
;
1195 directive_state_stack
= top
->prev
;
1201 directive_balance (void)
1203 while (directive_state_stack
)
1205 directiveE directive
;
1206 bfd_boolean negated
;
1211 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1212 as_warn_where ((char *) file
, line
,
1213 _(".begin directive with no matching .end directive"));
1219 inside_directive (directiveE dir
)
1221 state_stackS
*top
= directive_state_stack
;
1223 while (top
&& top
->directive
!= dir
)
1226 return (top
!= NULL
);
1231 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1235 const char *directive_string
;
1237 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1242 input_line_pointer
+= 3;
1245 len
= strspn (input_line_pointer
,
1246 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1248 /* This code is a hack to make .begin [no-][generics|relax] exactly
1249 equivalent to .begin [no-]transform. We should remove it when
1250 we stop accepting those options. */
1252 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1254 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1255 directive_string
= "transform";
1257 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1259 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1260 directive_string
= "transform";
1263 directive_string
= input_line_pointer
;
1265 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1267 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1269 input_line_pointer
+= len
;
1270 *directive
= (directiveE
) i
;
1271 if (*negated
&& !directive_info
[i
].can_be_negated
)
1272 as_bad (_("directive %s cannot be negated"),
1273 directive_info
[i
].name
);
1278 as_bad (_("unknown directive"));
1279 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1284 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1286 directiveE directive
;
1287 bfd_boolean negated
;
1291 get_directive (&directive
, &negated
);
1292 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1294 discard_rest_of_line ();
1298 if (cur_vinsn
.inside_bundle
)
1299 as_bad (_("directives are not valid inside bundles"));
1303 case directive_literal
:
1304 if (!inside_directive (directive_literal
))
1306 /* Previous labels go with whatever follows this directive, not with
1307 the literal, so save them now. */
1308 saved_insn_labels
= insn_labels
;
1311 as_warn (_(".begin literal is deprecated; use .literal instead"));
1312 state
= XNEW (emit_state
);
1313 xtensa_switch_to_literal_fragment (state
);
1314 directive_push (directive_literal
, negated
, state
);
1317 case directive_literal_prefix
:
1318 /* Have to flush pending output because a movi relaxed to an l32r
1319 might produce a literal. */
1320 md_flush_pending_output ();
1321 /* Check to see if the current fragment is a literal
1322 fragment. If it is, then this operation is not allowed. */
1323 if (generating_literals
)
1325 as_bad (_("cannot set literal_prefix inside literal fragment"));
1329 /* Allocate the literal state for this section and push
1330 onto the directive stack. */
1331 ls
= XNEW (lit_state
);
1334 *ls
= default_lit_sections
;
1335 directive_push (directive_literal_prefix
, negated
, ls
);
1337 /* Process the new prefix. */
1338 xtensa_literal_prefix ();
1341 case directive_freeregs
:
1342 /* This information is currently unused, but we'll accept the statement
1343 and just discard the rest of the line. This won't check the syntax,
1344 but it will accept every correct freeregs directive. */
1345 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1346 directive_push (directive_freeregs
, negated
, 0);
1349 case directive_schedule
:
1350 md_flush_pending_output ();
1351 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1352 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1353 directive_push (directive_schedule
, negated
, 0);
1354 xtensa_set_frag_assembly_state (frag_now
);
1357 case directive_density
:
1358 as_warn (_(".begin [no-]density is ignored"));
1361 case directive_absolute_literals
:
1362 md_flush_pending_output ();
1363 if (!absolute_literals_supported
&& !negated
)
1365 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1368 xtensa_set_frag_assembly_state (frag_now
);
1369 directive_push (directive
, negated
, 0);
1373 md_flush_pending_output ();
1374 xtensa_set_frag_assembly_state (frag_now
);
1375 directive_push (directive
, negated
, 0);
1379 demand_empty_rest_of_line ();
1384 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1386 directiveE begin_directive
, end_directive
;
1387 bfd_boolean begin_negated
, end_negated
;
1391 emit_state
**state_ptr
;
1394 if (cur_vinsn
.inside_bundle
)
1395 as_bad (_("directives are not valid inside bundles"));
1397 get_directive (&end_directive
, &end_negated
);
1399 md_flush_pending_output ();
1401 switch ((int) end_directive
)
1403 case XTENSA_UNDEFINED
:
1404 discard_rest_of_line ();
1407 case (int) directive_density
:
1408 as_warn (_(".end [no-]density is ignored"));
1409 demand_empty_rest_of_line ();
1412 case (int) directive_absolute_literals
:
1413 if (!absolute_literals_supported
&& !end_negated
)
1415 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1416 demand_empty_rest_of_line ();
1425 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1426 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1427 (const void **) state_ptr
);
1429 if (begin_directive
!= directive_none
)
1431 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1433 as_bad (_("does not match begin %s%s at %s:%d"),
1434 begin_negated
? "no-" : "",
1435 directive_info
[begin_directive
].name
, file
, line
);
1439 switch (end_directive
)
1441 case directive_literal
:
1442 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1443 xtensa_restore_emit_state (state
);
1444 xtensa_set_frag_assembly_state (frag_now
);
1446 if (!inside_directive (directive_literal
))
1448 /* Restore the list of current labels. */
1449 xtensa_clear_insn_labels ();
1450 insn_labels
= saved_insn_labels
;
1454 case directive_literal_prefix
:
1455 /* Restore the default collection sections from saved state. */
1456 s
= (lit_state
*) state
;
1458 default_lit_sections
= *s
;
1460 /* Free the state storage. */
1461 free (s
->lit_prefix
);
1465 case directive_schedule
:
1466 case directive_freeregs
:
1470 xtensa_set_frag_assembly_state (frag_now
);
1476 demand_empty_rest_of_line ();
1480 /* Place an aligned literal fragment at the current location. */
1483 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1485 md_flush_pending_output ();
1487 if (inside_directive (directive_literal
))
1488 as_warn (_(".literal_position inside literal directive; ignoring"));
1489 xtensa_mark_literal_pool_location ();
1491 demand_empty_rest_of_line ();
1492 xtensa_clear_insn_labels ();
1496 /* Support .literal label, expr, ... */
1499 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1502 char *p
, *base_name
;
1506 if (inside_directive (directive_literal
))
1508 as_bad (_(".literal not allowed inside .begin literal region"));
1509 ignore_rest_of_line ();
1513 md_flush_pending_output ();
1515 /* Previous labels go with whatever follows this directive, not with
1516 the literal, so save them now. */
1517 saved_insn_labels
= insn_labels
;
1520 /* If we are using text-section literals, then this is the right value... */
1523 base_name
= input_line_pointer
;
1525 xtensa_switch_to_literal_fragment (&state
);
1527 /* ...but if we aren't using text-section-literals, then we
1528 need to put them in the section we just switched to. */
1529 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1532 /* FIXME, despite the previous comments, dest_seg is unused... */
1535 /* All literals are aligned to four-byte boundaries. */
1536 frag_align (2, 0, 0);
1537 record_alignment (now_seg
, 2);
1539 c
= get_symbol_name (&base_name
);
1540 /* Just after name is now '\0'. */
1541 p
= input_line_pointer
;
1543 SKIP_WHITESPACE_AFTER_NAME ();
1545 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1547 as_bad (_("expected comma or colon after symbol name; "
1548 "rest of line ignored"));
1549 ignore_rest_of_line ();
1550 xtensa_restore_emit_state (&state
);
1558 input_line_pointer
++; /* skip ',' or ':' */
1560 xtensa_elf_cons (4);
1562 xtensa_restore_emit_state (&state
);
1564 /* Restore the list of current labels. */
1565 xtensa_clear_insn_labels ();
1566 insn_labels
= saved_insn_labels
;
1571 xtensa_literal_prefix (void)
1576 /* Parse the new prefix from the input_line_pointer. */
1578 len
= strspn (input_line_pointer
,
1579 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1580 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1582 /* Get a null-terminated copy of the name. */
1583 name
= xmemdup0 (input_line_pointer
, len
);
1585 /* Skip the name in the input line. */
1586 input_line_pointer
+= len
;
1588 default_lit_sections
.lit_prefix
= name
;
1590 /* Clear cached literal sections, since the prefix has changed. */
1591 default_lit_sections
.lit_seg
= NULL
;
1592 default_lit_sections
.lit4_seg
= NULL
;
1596 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1599 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1601 float fall_through_f
, target_f
;
1603 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1604 if (fall_through_f
< 0)
1606 as_bad (_("fall through frequency must be greater than 0"));
1607 ignore_rest_of_line ();
1611 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1614 as_bad (_("branch target frequency must be greater than 0"));
1615 ignore_rest_of_line ();
1619 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1621 demand_empty_rest_of_line ();
1625 /* Like normal .long/.short/.word, except support @plt, etc.
1626 Clobbers input_line_pointer, checks end-of-line. */
1629 xtensa_elf_cons (int nbytes
)
1632 bfd_reloc_code_real_type reloc
;
1634 md_flush_pending_output ();
1636 if (cur_vinsn
.inside_bundle
)
1637 as_bad (_("directives are not valid inside bundles"));
1639 if (is_it_end_of_statement ())
1641 demand_empty_rest_of_line ();
1648 if (exp
.X_op
== O_symbol
1649 && *input_line_pointer
== '@'
1650 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1653 reloc_howto_type
*reloc_howto
=
1654 bfd_reloc_type_lookup (stdoutput
, reloc
);
1656 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1657 as_bad (_("unsupported relocation"));
1658 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1659 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1660 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1661 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1662 as_bad (_("opcode-specific %s relocation used outside "
1663 "an instruction"), reloc_howto
->name
);
1664 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1665 as_bad (ngettext ("%s relocations do not fit in %d byte",
1666 "%s relocations do not fit in %d bytes",
1668 reloc_howto
->name
, nbytes
);
1669 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1670 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1671 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1672 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1675 char *p
= frag_more ((int) nbytes
);
1676 xtensa_set_frag_assembly_state (frag_now
);
1677 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1678 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1683 xtensa_set_frag_assembly_state (frag_now
);
1684 emit_expr (&exp
, (unsigned int) nbytes
);
1687 while (*input_line_pointer
++ == ',');
1689 input_line_pointer
--; /* Put terminator back into stream. */
1690 demand_empty_rest_of_line ();
1693 static bfd_boolean is_leb128_expr
;
1696 xtensa_leb128 (int sign
)
1698 is_leb128_expr
= TRUE
;
1700 is_leb128_expr
= FALSE
;
1704 /* Parsing and Idiom Translation. */
1706 /* Parse @plt, etc. and return the desired relocation. */
1707 static bfd_reloc_code_real_type
1708 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1718 return BFD_RELOC_NONE
;
1720 for (ch
= *str
, str2
= ident
;
1721 (str2
< ident
+ sizeof (ident
) - 1
1722 && (ISALNUM (ch
) || ch
== '@'));
1725 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1732 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1733 if (ch
== suffix_relocs
[i
].suffix
[0]
1734 && len
== suffix_relocs
[i
].length
1735 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1737 /* Now check for "identifier@suffix+constant". */
1738 if (*str
== '-' || *str
== '+')
1740 char *orig_line
= input_line_pointer
;
1741 expressionS new_exp
;
1743 input_line_pointer
= str
;
1744 expression (&new_exp
);
1745 if (new_exp
.X_op
== O_constant
)
1747 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1748 str
= input_line_pointer
;
1751 if (&input_line_pointer
!= str_p
)
1752 input_line_pointer
= orig_line
;
1756 return suffix_relocs
[i
].reloc
;
1759 return BFD_RELOC_UNUSED
;
1763 /* Find the matching operator type. */
1765 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1767 operatorT
operator = O_illegal
;
1770 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1772 if (suffix_relocs
[i
].reloc
== reloc
)
1774 operator = suffix_relocs
[i
].operator;
1778 gas_assert (operator != O_illegal
);
1783 /* Find the matching reloc type. */
1784 static bfd_reloc_code_real_type
1785 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1788 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1790 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1792 if (suffix_relocs
[i
].operator == operator)
1794 reloc
= suffix_relocs
[i
].reloc
;
1801 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1802 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1803 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1804 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1807 if (reloc
== BFD_RELOC_UNUSED
)
1808 return BFD_RELOC_32
;
1815 expression_end (const char *name
)
1838 #define ERROR_REG_NUM ((unsigned) -1)
1841 tc_get_register (const char *prefix
)
1844 const char *next_expr
;
1845 const char *old_line_pointer
;
1848 old_line_pointer
= input_line_pointer
;
1850 if (*input_line_pointer
== '$')
1851 ++input_line_pointer
;
1853 /* Accept "sp" as a synonym for "a1". */
1854 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1855 && expression_end (input_line_pointer
+ 2))
1857 input_line_pointer
+= 2;
1858 return 1; /* AR[1] */
1861 while (*input_line_pointer
++ == *prefix
++)
1863 --input_line_pointer
;
1868 as_bad (_("bad register name: %s"), old_line_pointer
);
1869 return ERROR_REG_NUM
;
1872 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1874 as_bad (_("bad register number: %s"), input_line_pointer
);
1875 return ERROR_REG_NUM
;
1880 while (ISDIGIT ((int) *input_line_pointer
))
1881 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1883 if (!(next_expr
= expression_end (input_line_pointer
)))
1885 as_bad (_("bad register name: %s"), old_line_pointer
);
1886 return ERROR_REG_NUM
;
1889 input_line_pointer
= (char *) next_expr
;
1896 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1898 xtensa_isa isa
= xtensa_default_isa
;
1900 /* Check if this is an immediate operand. */
1901 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1903 bfd_reloc_code_real_type reloc
;
1904 segT t
= expression (tok
);
1906 if (t
== absolute_section
1907 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1909 gas_assert (tok
->X_op
== O_constant
);
1910 tok
->X_op
= O_symbol
;
1911 tok
->X_add_symbol
= &abs_symbol
;
1914 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1915 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1920 case BFD_RELOC_LO16
:
1921 if (tok
->X_op
== O_constant
)
1923 tok
->X_add_number
&= 0xffff;
1927 case BFD_RELOC_HI16
:
1928 if (tok
->X_op
== O_constant
)
1930 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1934 case BFD_RELOC_UNUSED
:
1935 as_bad (_("unsupported relocation"));
1937 case BFD_RELOC_32_PCREL
:
1938 as_bad (_("pcrel relocation not allowed in an instruction"));
1943 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1948 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1949 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1951 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1954 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1955 as_bad (_("register number out of range"));
1958 tok
->X_op
= O_register
;
1959 tok
->X_add_symbol
= 0;
1960 tok
->X_add_number
= reg
;
1965 /* Split up the arguments for an opcode or pseudo-op. */
1968 tokenize_arguments (char **args
, char *str
)
1970 char *old_input_line_pointer
;
1971 bfd_boolean saw_comma
= FALSE
;
1972 bfd_boolean saw_arg
= FALSE
;
1973 bfd_boolean saw_colon
= FALSE
;
1975 char *arg_end
, *arg
;
1978 /* Save and restore input_line_pointer around this function. */
1979 old_input_line_pointer
= input_line_pointer
;
1980 input_line_pointer
= str
;
1982 while (*input_line_pointer
)
1985 switch (*input_line_pointer
)
1992 input_line_pointer
++;
1993 if (saw_comma
|| saw_colon
|| !saw_arg
)
1999 input_line_pointer
++;
2000 if (saw_comma
|| saw_colon
|| !saw_arg
)
2006 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2009 arg_end
= input_line_pointer
+ 1;
2010 while (!expression_end (arg_end
))
2013 arg_len
= arg_end
- input_line_pointer
;
2014 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2015 args
[num_args
] = arg
;
2019 strncpy (arg
, input_line_pointer
, arg_len
);
2020 arg
[arg_len
] = '\0';
2022 input_line_pointer
= arg_end
;
2032 if (saw_comma
|| saw_colon
)
2034 input_line_pointer
= old_input_line_pointer
;
2039 as_bad (_("extra comma"));
2041 as_bad (_("extra colon"));
2043 as_bad (_("missing argument"));
2045 as_bad (_("missing comma or colon"));
2046 input_line_pointer
= old_input_line_pointer
;
2051 /* Parse the arguments to an opcode. Return TRUE on error. */
2054 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2056 expressionS
*tok
, *last_tok
;
2057 xtensa_opcode opcode
= insn
->opcode
;
2058 bfd_boolean had_error
= TRUE
;
2059 xtensa_isa isa
= xtensa_default_isa
;
2060 int n
, num_regs
= 0;
2061 int opcode_operand_count
;
2062 int opnd_cnt
, last_opnd_cnt
;
2063 unsigned int next_reg
= 0;
2064 char *old_input_line_pointer
;
2066 if (insn
->insn_type
== ITYPE_LITERAL
)
2067 opcode_operand_count
= 1;
2069 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2072 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2074 /* Save and restore input_line_pointer around this function. */
2075 old_input_line_pointer
= input_line_pointer
;
2081 /* Skip invisible operands. */
2082 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2088 for (n
= 0; n
< num_args
; n
++)
2090 input_line_pointer
= arg_strings
[n
];
2091 if (*input_line_pointer
== ':')
2093 xtensa_regfile opnd_rf
;
2094 input_line_pointer
++;
2097 gas_assert (opnd_cnt
> 0);
2099 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2101 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2102 as_warn (_("incorrect register number, ignoring"));
2107 if (opnd_cnt
>= opcode_operand_count
)
2109 as_warn (_("too many arguments"));
2112 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2114 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2115 next_reg
= tok
->X_add_number
+ 1;
2117 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2119 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2121 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2122 /* minus 1 because we are seeing one right now */
2128 last_opnd_cnt
= opnd_cnt
;
2129 demand_empty_rest_of_line ();
2136 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2140 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2143 insn
->ntok
= tok
- insn
->tok
;
2147 input_line_pointer
= old_input_line_pointer
;
2153 get_invisible_operands (TInsn
*insn
)
2155 xtensa_isa isa
= xtensa_default_isa
;
2156 static xtensa_insnbuf slotbuf
= NULL
;
2158 xtensa_opcode opc
= insn
->opcode
;
2159 int slot
, opnd
, fmt_found
;
2163 slotbuf
= xtensa_insnbuf_alloc (isa
);
2165 /* Find format/slot where this can be encoded. */
2168 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2170 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2172 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2178 if (fmt_found
) break;
2183 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2187 /* First encode all the visible operands
2188 (to deal with shared field operands). */
2189 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2191 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2192 && (insn
->tok
[opnd
].X_op
== O_register
2193 || insn
->tok
[opnd
].X_op
== O_constant
))
2195 val
= insn
->tok
[opnd
].X_add_number
;
2196 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2197 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2201 /* Then pull out the values for the invisible ones. */
2202 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2204 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2206 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2207 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2208 insn
->tok
[opnd
].X_add_number
= val
;
2209 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2210 insn
->tok
[opnd
].X_op
= O_register
;
2212 insn
->tok
[opnd
].X_op
= O_constant
;
2221 xg_reverse_shift_count (char **cnt_argp
)
2223 char *cnt_arg
, *new_arg
;
2224 cnt_arg
= *cnt_argp
;
2226 /* replace the argument with "31-(argument)" */
2227 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2230 *cnt_argp
= new_arg
;
2234 /* If "arg" is a constant expression, return non-zero with the value
2238 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2241 char *save_ptr
= input_line_pointer
;
2243 input_line_pointer
= arg
;
2245 input_line_pointer
= save_ptr
;
2247 if (exp
.X_op
== O_constant
)
2249 *valp
= exp
.X_add_number
;
2258 xg_replace_opname (char **popname
, const char *newop
)
2261 *popname
= xstrdup (newop
);
2266 xg_check_num_args (int *pnum_args
,
2271 int num_args
= *pnum_args
;
2273 if (num_args
< expected_num
)
2275 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2276 num_args
, opname
, expected_num
);
2280 if (num_args
> expected_num
)
2282 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2283 num_args
, opname
, expected_num
);
2284 while (num_args
-- > expected_num
)
2286 free (arg_strings
[num_args
]);
2287 arg_strings
[num_args
] = 0;
2289 *pnum_args
= expected_num
;
2297 /* If the register is not specified as part of the opcode,
2298 then get it from the operand and move it to the opcode. */
2301 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2303 xtensa_isa isa
= xtensa_default_isa
;
2305 char *opname
, *new_opname
;
2306 const char *sr_name
;
2307 int is_user
, is_write
;
2312 is_user
= (opname
[1] == 'u');
2313 is_write
= (opname
[0] == 'w');
2315 /* Opname == [rw]ur or [rwx]sr... */
2317 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2320 /* Check if the argument is a symbolic register name. */
2321 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2322 /* Handle WSR to "INTSET" as a special case. */
2323 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2324 && !strcasecmp (arg_strings
[1], "intset"))
2325 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2326 if (sr
== XTENSA_UNDEFINED
2327 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2329 /* Maybe it's a register number.... */
2331 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2333 as_bad (_("invalid register '%s' for '%s' instruction"),
2334 arg_strings
[1], opname
);
2337 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2338 if (sr
== XTENSA_UNDEFINED
)
2340 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2341 (long) val
, opname
);
2346 /* Remove the last argument, which is now part of the opcode. */
2347 free (arg_strings
[1]);
2351 /* Translate the opcode. */
2352 sr_name
= xtensa_sysreg_name (isa
, sr
);
2353 /* Another special case for "WSR.INTSET".... */
2354 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2356 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2358 *popname
= new_opname
;
2365 xtensa_translate_old_userreg_ops (char **popname
)
2367 xtensa_isa isa
= xtensa_default_isa
;
2369 char *opname
, *new_opname
;
2370 const char *sr_name
;
2371 bfd_boolean has_underbar
= FALSE
;
2374 if (opname
[0] == '_')
2376 has_underbar
= TRUE
;
2380 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2381 if (sr
!= XTENSA_UNDEFINED
)
2383 /* The new default name ("nnn") is different from the old default
2384 name ("URnnn"). The old default is handled below, and we don't
2385 want to recognize [RW]nnn, so do nothing if the name is the (new)
2387 static char namebuf
[10];
2388 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2389 if (strcmp (namebuf
, opname
+ 1) == 0)
2397 /* Only continue if the reg name is "URnnn". */
2398 if (opname
[1] != 'u' || opname
[2] != 'r')
2400 val
= strtoul (opname
+ 3, &end
, 10);
2404 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2405 if (sr
== XTENSA_UNDEFINED
)
2407 as_bad (_("invalid register number (%ld) for '%s'"),
2408 (long) val
, opname
);
2413 /* Translate the opcode. */
2414 sr_name
= xtensa_sysreg_name (isa
, sr
);
2415 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2416 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2417 opname
[0], sr_name
);
2419 *popname
= new_opname
;
2426 xtensa_translate_zero_immed (const char *old_op
,
2436 gas_assert (opname
[0] != '_');
2438 if (strcmp (opname
, old_op
) != 0)
2441 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2443 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2445 xg_replace_opname (popname
, new_op
);
2446 free (arg_strings
[1]);
2447 arg_strings
[1] = arg_strings
[2];
2456 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2457 Returns non-zero if an error was found. */
2460 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2462 char *opname
= *popname
;
2463 bfd_boolean has_underbar
= FALSE
;
2467 has_underbar
= TRUE
;
2471 if (strcmp (opname
, "mov") == 0)
2473 if (use_transform () && !has_underbar
&& density_supported
)
2474 xg_replace_opname (popname
, "mov.n");
2477 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2479 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2480 arg_strings
[2] = xstrdup (arg_strings
[1]);
2486 if (strcmp (opname
, "bbsi.l") == 0)
2488 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2490 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2491 if (target_big_endian
)
2492 xg_reverse_shift_count (&arg_strings
[1]);
2496 if (strcmp (opname
, "bbci.l") == 0)
2498 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2500 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2501 if (target_big_endian
)
2502 xg_reverse_shift_count (&arg_strings
[1]);
2506 /* Don't do anything special with NOPs inside FLIX instructions. They
2507 are handled elsewhere. Real NOP instructions are always available
2508 in configurations with FLIX, so this should never be an issue but
2509 check for it anyway. */
2510 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2511 && strcmp (opname
, "nop") == 0)
2513 if (use_transform () && !has_underbar
&& density_supported
)
2514 xg_replace_opname (popname
, "nop.n");
2517 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2519 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2520 arg_strings
[0] = xstrdup ("a1");
2521 arg_strings
[1] = xstrdup ("a1");
2522 arg_strings
[2] = xstrdup ("a1");
2528 /* Recognize [RW]UR and [RWX]SR. */
2529 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2530 && (opname
[1] == 'u' || opname
[1] == 's'))
2531 || (opname
[0] == 'x' && opname
[1] == 's'))
2533 && opname
[3] == '\0')
2534 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2536 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2537 [RW]<name> if <name> is the non-default name of a user register. */
2538 if ((opname
[0] == 'r' || opname
[0] == 'w')
2539 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2540 return xtensa_translate_old_userreg_ops (popname
);
2542 /* Relax branches that don't allow comparisons against an immediate value
2543 of zero to the corresponding branches with implicit zero immediates. */
2544 if (!has_underbar
&& use_transform ())
2546 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2547 pnum_args
, arg_strings
))
2550 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2551 pnum_args
, arg_strings
))
2554 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2555 pnum_args
, arg_strings
))
2558 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2559 pnum_args
, arg_strings
))
2567 /* Functions for dealing with the Xtensa ISA. */
2569 /* Currently the assembler only allows us to use a single target per
2570 fragment. Because of this, only one operand for a given
2571 instruction may be symbolic. If there is a PC-relative operand,
2572 the last one is chosen. Otherwise, the result is the number of the
2573 last immediate operand, and if there are none of those, we fail and
2577 get_relaxable_immed (xtensa_opcode opcode
)
2579 int last_immed
= -1;
2582 if (opcode
== XTENSA_UNDEFINED
)
2585 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2586 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2588 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2590 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2592 if (last_immed
== -1
2593 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2600 static xtensa_opcode
2601 get_opcode_from_buf (const char *buf
, int slot
)
2603 static xtensa_insnbuf insnbuf
= NULL
;
2604 static xtensa_insnbuf slotbuf
= NULL
;
2605 xtensa_isa isa
= xtensa_default_isa
;
2610 insnbuf
= xtensa_insnbuf_alloc (isa
);
2611 slotbuf
= xtensa_insnbuf_alloc (isa
);
2614 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2615 fmt
= xtensa_format_decode (isa
, insnbuf
);
2616 if (fmt
== XTENSA_UNDEFINED
)
2617 return XTENSA_UNDEFINED
;
2619 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2620 return XTENSA_UNDEFINED
;
2622 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2623 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2627 #ifdef TENSILICA_DEBUG
2629 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2632 xtensa_print_insn_table (void)
2634 int num_opcodes
, num_operands
;
2635 xtensa_opcode opcode
;
2636 xtensa_isa isa
= xtensa_default_isa
;
2638 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2639 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2642 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2643 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2644 for (opn
= 0; opn
< num_operands
; opn
++)
2646 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2648 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2650 xtensa_regfile opnd_rf
=
2651 xtensa_operand_regfile (isa
, opcode
, opn
);
2652 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2654 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2655 fputs ("[lLr] ", stderr
);
2657 fputs ("i ", stderr
);
2659 fprintf (stderr
, "\n");
2665 print_vliw_insn (xtensa_insnbuf vbuf
)
2667 xtensa_isa isa
= xtensa_default_isa
;
2668 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2669 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2672 fprintf (stderr
, "format = %d\n", f
);
2674 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2676 xtensa_opcode opcode
;
2680 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2681 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2682 opname
= xtensa_opcode_name (isa
, opcode
);
2684 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2685 fprintf (stderr
, " operands = ");
2687 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2691 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2693 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2694 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2695 fprintf (stderr
, "%d ", val
);
2697 fprintf (stderr
, "\n");
2699 xtensa_insnbuf_free (isa
, sbuf
);
2702 #endif /* TENSILICA_DEBUG */
2706 is_direct_call_opcode (xtensa_opcode opcode
)
2708 xtensa_isa isa
= xtensa_default_isa
;
2709 int n
, num_operands
;
2711 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2714 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2715 for (n
= 0; n
< num_operands
; n
++)
2717 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2718 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2725 /* Convert from BFD relocation type code to slot and operand number.
2726 Returns non-zero on failure. */
2729 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2731 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2732 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2734 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2737 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2738 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2740 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2750 /* Convert from slot number to BFD relocation type code for the
2751 standard PC-relative relocations. Return BFD_RELOC_NONE on
2754 static bfd_reloc_code_real_type
2755 encode_reloc (int slot
)
2757 if (slot
< 0 || slot
> 14)
2758 return BFD_RELOC_NONE
;
2760 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2764 /* Convert from slot numbers to BFD relocation type code for the
2765 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2767 static bfd_reloc_code_real_type
2768 encode_alt_reloc (int slot
)
2770 if (slot
< 0 || slot
> 14)
2771 return BFD_RELOC_NONE
;
2773 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2778 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2781 xtensa_opcode opcode
,
2787 uint32 valbuf
= value
;
2789 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2791 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2793 as_bad_where ((char *) file
, line
,
2794 _("operand %d of '%s' has out of range value '%u'"),
2796 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2799 as_bad_where ((char *) file
, line
,
2800 _("operand %d of '%s' has invalid value '%u'"),
2802 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2807 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2813 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2816 xtensa_opcode opcode
,
2820 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2821 fmt
, slot
, slotbuf
, &val
);
2822 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2827 /* Checks for rules from xtensa-relax tables. */
2829 /* The routine xg_instruction_matches_option_term must return TRUE
2830 when a given option term is true. The meaning of all of the option
2831 terms is given interpretation by this function. */
2834 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2836 if (strcmp (option
->option_name
, "realnop") == 0
2837 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2839 /* These conditions were evaluated statically when building the
2840 relaxation table. There's no need to reevaluate them now. */
2843 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2844 return insn
->extra_arg
.X_op
== O_register
;
2847 as_fatal (_("internal error: unknown option name '%s'"),
2848 option
->option_name
);
2854 xg_instruction_matches_or_options (TInsn
*insn
,
2855 const ReqOrOptionList
*or_option
)
2857 const ReqOrOption
*option
;
2858 /* Must match each of the AND terms. */
2859 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2861 if (xg_instruction_matches_option_term (insn
, option
))
2869 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2871 const ReqOption
*req_options
;
2872 /* Must match each of the AND terms. */
2873 for (req_options
= options
;
2874 req_options
!= NULL
;
2875 req_options
= req_options
->next
)
2877 /* Must match one of the OR clauses. */
2878 if (!xg_instruction_matches_or_options (insn
,
2879 req_options
->or_option_terms
))
2886 /* Return the transition rule that matches or NULL if none matches. */
2889 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2891 PreconditionList
*condition_l
;
2893 if (rule
->opcode
!= insn
->opcode
)
2896 for (condition_l
= rule
->conditions
;
2897 condition_l
!= NULL
;
2898 condition_l
= condition_l
->next
)
2902 Precondition
*cond
= condition_l
->precond
;
2907 /* The expression must be the constant. */
2908 gas_assert (cond
->op_num
< insn
->ntok
);
2909 exp1
= &insn
->tok
[cond
->op_num
];
2910 if (expr_is_const (exp1
))
2915 if (get_expr_const (exp1
) != cond
->op_data
)
2919 if (get_expr_const (exp1
) == cond
->op_data
)
2926 else if (expr_is_register (exp1
))
2931 if (get_expr_register (exp1
) != cond
->op_data
)
2935 if (get_expr_register (exp1
) == cond
->op_data
)
2947 gas_assert (cond
->op_num
< insn
->ntok
);
2948 gas_assert (cond
->op_data
< insn
->ntok
);
2949 exp1
= &insn
->tok
[cond
->op_num
];
2950 exp2
= &insn
->tok
[cond
->op_data
];
2955 if (!expr_is_equal (exp1
, exp2
))
2959 if (expr_is_equal (exp1
, exp2
))
2971 if (!xg_instruction_matches_options (insn
, rule
->options
))
2979 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2981 bfd_boolean a_greater
= FALSE
;
2982 bfd_boolean b_greater
= FALSE
;
2984 ReqOptionList
*l_a
= a
->options
;
2985 ReqOptionList
*l_b
= b
->options
;
2987 /* We only care if they both are the same except for
2988 a const16 vs. an l32r. */
2990 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2992 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2993 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2994 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2996 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2998 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3000 /* This is the case we care about. */
3001 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3002 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3009 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3010 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3020 l_or_a
= l_or_a
->next
;
3021 l_or_b
= l_or_b
->next
;
3023 if (l_or_a
|| l_or_b
)
3032 /* Incomparable if the substitution was used differently in two cases. */
3033 if (a_greater
&& b_greater
)
3045 static TransitionRule
*
3046 xg_instruction_match (TInsn
*insn
)
3048 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3050 gas_assert (insn
->opcode
< table
->num_opcodes
);
3052 /* Walk through all of the possible transitions. */
3053 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3055 TransitionRule
*rule
= l
->rule
;
3056 if (xg_instruction_matches_rule (insn
, rule
))
3063 /* Various Other Internal Functions. */
3066 is_unique_insn_expansion (TransitionRule
*r
)
3068 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3070 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3076 /* Check if there is exactly one relaxation for INSN that converts it to
3077 another instruction of equal or larger size. If so, and if TARG is
3078 non-null, go ahead and generate the relaxed instruction into TARG. If
3079 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3080 instruction, i.e., ignore relaxations that convert to an instruction of
3081 equal size. In some contexts where this function is used, only
3082 a single widening is allowed and the NARROW_ONLY argument is used to
3083 exclude cases like ADDI being "widened" to an ADDMI, which may
3084 later be relaxed to an ADDMI/ADDI pair. */
3087 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3089 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3091 TransitionRule
*match
= 0;
3093 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3094 gas_assert (insn
->opcode
< table
->num_opcodes
);
3096 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3098 TransitionRule
*rule
= l
->rule
;
3100 if (xg_instruction_matches_rule (insn
, rule
)
3101 && is_unique_insn_expansion (rule
)
3102 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3103 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3114 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3119 /* Return the maximum number of bytes this opcode can expand to. */
3122 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3124 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3126 int max_size
= xg_get_single_size (opcode
);
3128 gas_assert (opcode
< table
->num_opcodes
);
3130 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3132 TransitionRule
*rule
= l
->rule
;
3133 BuildInstr
*build_list
;
3138 build_list
= rule
->to_instr
;
3139 if (is_unique_insn_expansion (rule
))
3141 gas_assert (build_list
->typ
== INSTR_INSTR
);
3142 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3145 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3147 switch (build_list
->typ
)
3150 this_size
+= xg_get_single_size (build_list
->opcode
);
3152 case INSTR_LITERAL_DEF
:
3153 case INSTR_LABEL_DEF
:
3158 if (this_size
> max_size
)
3159 max_size
= this_size
;
3165 /* Return the maximum number of literal bytes this opcode can generate. */
3168 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3170 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3174 gas_assert (opcode
< table
->num_opcodes
);
3176 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3178 TransitionRule
*rule
= l
->rule
;
3179 BuildInstr
*build_list
;
3184 build_list
= rule
->to_instr
;
3185 if (is_unique_insn_expansion (rule
))
3187 gas_assert (build_list
->typ
== INSTR_INSTR
);
3188 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3191 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3193 switch (build_list
->typ
)
3195 case INSTR_LITERAL_DEF
:
3196 /* Hard-coded 4-byte literal. */
3200 case INSTR_LABEL_DEF
:
3205 if (this_size
> max_size
)
3206 max_size
= this_size
;
3213 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3215 int steps_taken
= 0;
3216 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3219 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3220 gas_assert (insn
->opcode
< table
->num_opcodes
);
3222 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3224 TransitionRule
*rule
= l
->rule
;
3226 if (xg_instruction_matches_rule (insn
, rule
))
3228 if (steps_taken
== lateral_steps
)
3238 get_special_literal_symbol (void)
3240 static symbolS
*sym
= NULL
;
3243 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3249 get_special_label_symbol (void)
3251 static symbolS
*sym
= NULL
;
3254 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3260 xg_valid_literal_expression (const expressionS
*exp
)
3282 /* This will check to see if the value can be converted into the
3283 operand type. It will return TRUE if it does not fit. */
3286 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3288 uint32 valbuf
= value
;
3289 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3295 /* Assumes: All immeds are constants. Check that all constants fit
3296 into their immeds; return FALSE if not. */
3299 xg_immeds_fit (const TInsn
*insn
)
3301 xtensa_isa isa
= xtensa_default_isa
;
3305 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3306 for (i
= 0; i
< n
; ++i
)
3308 const expressionS
*exp
= &insn
->tok
[i
];
3310 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3317 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3322 /* The symbol should have a fixup associated with it. */
3331 /* This should only be called after we have an initial
3332 estimate of the addresses. */
3335 xg_symbolic_immeds_fit (const TInsn
*insn
,
3341 xtensa_isa isa
= xtensa_default_isa
;
3349 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3351 for (i
= 0; i
< n
; ++i
)
3353 const expressionS
*exp
= &insn
->tok
[i
];
3355 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3362 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3368 /* Check for the worst case. */
3369 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3374 /* We only allow symbols for PC-relative references.
3375 If pc_frag == 0, then we don't have frag locations yet. */
3377 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3380 /* If it is a weak symbol or a symbol in a different section,
3381 it cannot be known to fit at assembly time. */
3382 if (S_IS_WEAK (exp
->X_add_symbol
)
3383 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3385 /* For a direct call with --no-longcalls, be optimistic and
3386 assume it will be in range. If the symbol is weak and
3387 undefined, it may remain undefined at link-time, in which
3388 case it will have a zero value and almost certainly be out
3389 of range for a direct call; thus, relax for undefined weak
3390 symbols even if longcalls is not enabled. */
3391 if (is_direct_call_opcode (insn
->opcode
)
3392 && ! pc_frag
->tc_frag_data
.use_longcalls
3393 && (! S_IS_WEAK (exp
->X_add_symbol
)
3394 || S_IS_DEFINED (exp
->X_add_symbol
)))
3400 symbolP
= exp
->X_add_symbol
;
3401 sym_frag
= symbol_get_frag (symbolP
);
3402 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3403 pc
= pc_frag
->fr_address
+ pc_offset
;
3405 /* If frag has yet to be reached on this pass, assume it
3406 will move by STRETCH just as we did. If this is not so,
3407 it will be because some frag between grows, and that will
3408 force another pass. Beware zero-length frags. There
3409 should be a faster way to do this. */
3412 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3413 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3418 new_offset
= target
;
3419 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3420 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3425 /* The symbol should have a fixup associated with it. */
3434 /* Return TRUE on success. */
3437 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3443 targ
->debug_line
= insn
->debug_line
;
3444 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3449 targ
->opcode
= bi
->opcode
;
3450 targ
->insn_type
= ITYPE_INSN
;
3451 targ
->is_specific_opcode
= FALSE
;
3453 for (; op
!= NULL
; op
= op
->next
)
3455 int op_num
= op
->op_num
;
3456 int op_data
= op
->op_data
;
3458 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3460 if (targ
->ntok
<= op_num
)
3461 targ
->ntok
= op_num
+ 1;
3466 set_expr_const (&targ
->tok
[op_num
], op_data
);
3469 gas_assert (op_data
< insn
->ntok
);
3470 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3473 if (insn
->extra_arg
.X_op
!= O_register
)
3475 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3478 sym
= get_special_literal_symbol ();
3479 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3480 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3481 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3482 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3485 sym
= get_special_label_symbol ();
3486 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3488 case OP_OPERAND_HI16U
:
3489 case OP_OPERAND_LOW16U
:
3490 gas_assert (op_data
< insn
->ntok
);
3491 if (expr_is_const (&insn
->tok
[op_data
]))
3494 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3495 val
= xg_apply_userdef_op_fn (op
->typ
,
3498 targ
->tok
[op_num
].X_add_number
= val
;
3502 /* For const16 we can create relocations for these. */
3503 if (targ
->opcode
== XTENSA_UNDEFINED
3504 || (targ
->opcode
!= xtensa_const16_opcode
))
3506 gas_assert (op_data
< insn
->ntok
);
3507 /* Need to build a O_lo16 or O_hi16. */
3508 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3509 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3511 if (op
->typ
== OP_OPERAND_HI16U
)
3512 targ
->tok
[op_num
].X_op
= O_hi16
;
3513 else if (op
->typ
== OP_OPERAND_LOW16U
)
3514 targ
->tok
[op_num
].X_op
= O_lo16
;
3521 /* currently handles:
3524 OP_OPERAND_F32MINUS */
3525 if (xg_has_userdef_op_fn (op
->typ
))
3527 gas_assert (op_data
< insn
->ntok
);
3528 if (expr_is_const (&insn
->tok
[op_data
]))
3531 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3532 val
= xg_apply_userdef_op_fn (op
->typ
,
3535 targ
->tok
[op_num
].X_add_number
= val
;
3538 return FALSE
; /* We cannot use a relocation for this. */
3547 case INSTR_LITERAL_DEF
:
3549 targ
->opcode
= XTENSA_UNDEFINED
;
3550 targ
->insn_type
= ITYPE_LITERAL
;
3551 targ
->is_specific_opcode
= FALSE
;
3552 for (; op
!= NULL
; op
= op
->next
)
3554 int op_num
= op
->op_num
;
3555 int op_data
= op
->op_data
;
3556 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3558 if (targ
->ntok
<= op_num
)
3559 targ
->ntok
= op_num
+ 1;
3564 gas_assert (op_data
< insn
->ntok
);
3565 /* We can only pass resolvable literals through. */
3566 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3568 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3580 case INSTR_LABEL_DEF
:
3582 targ
->opcode
= XTENSA_UNDEFINED
;
3583 targ
->insn_type
= ITYPE_LABEL
;
3584 targ
->is_specific_opcode
= FALSE
;
3585 /* Literal with no ops is a label? */
3586 gas_assert (op
== NULL
);
3597 /* Return TRUE on success. */
3600 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3602 for (; bi
!= NULL
; bi
= bi
->next
)
3604 TInsn
*next_insn
= istack_push_space (istack
);
3606 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3613 /* Return TRUE on valid expansion. */
3616 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3618 int stack_size
= istack
->ninsn
;
3619 int steps_taken
= 0;
3620 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3623 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3624 gas_assert (insn
->opcode
< table
->num_opcodes
);
3626 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3628 TransitionRule
*rule
= l
->rule
;
3630 if (xg_instruction_matches_rule (insn
, rule
))
3632 if (lateral_steps
== steps_taken
)
3636 /* This is it. Expand the rule to the stack. */
3637 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3640 /* Check to see if it fits. */
3641 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3643 TInsn
*tinsn
= &istack
->insn
[i
];
3645 if (tinsn
->insn_type
== ITYPE_INSN
3646 && !tinsn_has_symbolic_operands (tinsn
)
3647 && !xg_immeds_fit (tinsn
))
3649 istack
->ninsn
= stack_size
;
3662 /* Relax the assembly instruction at least "min_steps".
3663 Return the number of steps taken.
3665 For relaxation to correctly terminate, every relaxation chain must
3666 terminate in one of two ways:
3668 1. If the chain from one instruction to the next consists entirely of
3669 single instructions, then the chain *must* handle all possible
3670 immediates without failing. It must not ever fail because an
3671 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3672 chain is one example. L32R loads 32 bits, and there cannot be an
3673 immediate larger than 32 bits, so it satisfies this condition.
3674 Single instruction relaxation chains are as defined by
3675 xg_is_single_relaxable_instruction.
3677 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3678 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3680 Strictly speaking, in most cases you can violate condition 1 and be OK
3681 -- in particular when the last two instructions have the same single
3682 size. But nevertheless, you should guarantee the above two conditions.
3684 We could fix this so that single-instruction expansions correctly
3685 terminate when they can't handle the range, but the error messages are
3686 worse, and it actually turns out that in every case but one (18-bit wide
3687 branches), you need a multi-instruction expansion to get the full range
3688 anyway. And because 18-bit branches are handled identically to 15-bit
3689 branches, there isn't any point in changing it. */
3692 xg_assembly_relax (IStack
*istack
,
3695 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3696 offsetT pc_offset
, /* offset in fragment */
3697 int min_steps
, /* minimum conversion steps */
3698 long stretch
) /* number of bytes stretched so far */
3700 int steps_taken
= 0;
3702 /* Some of its immeds don't fit. Try to build a relaxed version.
3703 This may go through a couple of stages of single instruction
3704 transformations before we get there. */
3706 TInsn single_target
;
3708 int lateral_steps
= 0;
3709 int istack_size
= istack
->ninsn
;
3711 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3712 && steps_taken
>= min_steps
)
3714 istack_push (istack
, insn
);
3717 current_insn
= *insn
;
3719 /* Walk through all of the single instruction expansions. */
3720 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3723 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3726 if (steps_taken
>= min_steps
)
3728 istack_push (istack
, &single_target
);
3732 current_insn
= single_target
;
3735 /* Now check for a multi-instruction expansion. */
3736 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3738 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3741 if (steps_taken
>= min_steps
)
3743 istack_push (istack
, ¤t_insn
);
3748 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3750 if (steps_taken
>= min_steps
)
3754 istack
->ninsn
= istack_size
;
3757 /* It's not going to work -- use the original. */
3758 istack_push (istack
, insn
);
3764 xg_finish_frag (char *last_insn
,
3765 enum xtensa_relax_statesE frag_state
,
3766 enum xtensa_relax_statesE slot0_state
,
3768 bfd_boolean is_insn
)
3770 /* Finish off this fragment so that it has at LEAST the desired
3771 max_growth. If it doesn't fit in this fragment, close this one
3772 and start a new one. In either case, return a pointer to the
3773 beginning of the growth area. */
3777 frag_grow (max_growth
);
3778 old_frag
= frag_now
;
3780 frag_now
->fr_opcode
= last_insn
;
3782 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3784 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3785 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3787 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3788 xtensa_set_frag_assembly_state (frag_now
);
3790 /* Just to make sure that we did not split it up. */
3791 gas_assert (old_frag
->fr_next
== frag_now
);
3795 /* Return TRUE if the target frag is one of the next non-empty frags. */
3798 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3803 for (; fragP
; fragP
= fragP
->fr_next
)
3805 if (fragP
== target
)
3807 if (fragP
->fr_fix
!= 0)
3809 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3811 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3812 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3814 if (fragP
->fr_type
== rs_space
)
3822 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3824 xtensa_isa isa
= xtensa_default_isa
;
3826 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3831 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3832 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3835 for (i
= 0; i
< num_ops
; i
++)
3837 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3843 if (target_op
== -1)
3846 if (insn
->ntok
<= target_op
)
3849 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3852 sym
= insn
->tok
[target_op
].X_add_symbol
;
3856 if (insn
->tok
[target_op
].X_add_number
!= 0)
3859 target_frag
= symbol_get_frag (sym
);
3860 if (target_frag
== NULL
)
3863 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3864 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3872 xg_add_branch_and_loop_targets (TInsn
*insn
)
3874 xtensa_isa isa
= xtensa_default_isa
;
3875 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3877 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3880 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3881 && insn
->tok
[i
].X_op
== O_symbol
)
3882 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3886 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3887 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3891 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3893 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3894 && insn
->tok
[i
].X_op
== O_symbol
)
3896 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3897 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3898 if (S_IS_DEFINED (sym
))
3899 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3906 /* Return FALSE if no error. */
3909 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3914 switch (instr_spec
->typ
)
3917 new_insn
->insn_type
= ITYPE_INSN
;
3918 new_insn
->opcode
= instr_spec
->opcode
;
3920 case INSTR_LITERAL_DEF
:
3921 new_insn
->insn_type
= ITYPE_LITERAL
;
3922 new_insn
->opcode
= XTENSA_UNDEFINED
;
3924 case INSTR_LABEL_DEF
:
3927 new_insn
->is_specific_opcode
= FALSE
;
3928 new_insn
->debug_line
= old_insn
->debug_line
;
3929 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3931 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3934 const expressionS
*src_exp
;
3940 /* The expression must be the constant. */
3941 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3942 exp
= &new_insn
->tok
[b_op
->op_num
];
3943 set_expr_const (exp
, b_op
->op_data
);
3947 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3948 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3949 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3950 exp
= &new_insn
->tok
[b_op
->op_num
];
3951 copy_expr (exp
, src_exp
);
3956 as_bad (_("can't handle generation of literal/labels yet"));
3960 as_bad (_("can't handle undefined OP TYPE"));
3965 new_insn
->ntok
= num_ops
;
3970 /* Return TRUE if it was simplified. */
3973 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3975 TransitionRule
*rule
;
3976 BuildInstr
*insn_spec
;
3978 if (old_insn
->is_specific_opcode
|| !density_supported
)
3981 rule
= xg_instruction_match (old_insn
);
3985 insn_spec
= rule
->to_instr
;
3986 /* There should only be one. */
3987 gas_assert (insn_spec
!= NULL
);
3988 gas_assert (insn_spec
->next
== NULL
);
3989 if (insn_spec
->next
!= NULL
)
3992 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3998 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3999 l32i.n. (2) Check the number of operands. (3) Place the instruction
4000 tokens into the stack or relax it and place multiple
4001 instructions/literals onto the stack. Return FALSE if no error. */
4004 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4008 bfd_boolean do_expand
;
4010 tinsn_init (&new_insn
);
4012 /* Narrow it if we can. xg_simplify_insn now does all the
4013 appropriate checking (e.g., for the density option). */
4014 if (xg_simplify_insn (orig_insn
, &new_insn
))
4015 orig_insn
= &new_insn
;
4017 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4019 if (orig_insn
->ntok
< noperands
)
4021 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4022 "found %d operands for '%s': Expected %d",
4025 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4029 if (orig_insn
->ntok
> noperands
)
4030 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4031 "found %d operands for '%s': Expected %d",
4034 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4037 /* If there are not enough operands, we will assert above. If there
4038 are too many, just cut out the extras here. */
4039 orig_insn
->ntok
= noperands
;
4041 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4044 /* Special case for extui opcode which has constraints not handled
4045 by the ordinary operand encoding checks. The number of operands
4046 and related syntax issues have already been checked. */
4047 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4049 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4050 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4051 if (shiftimm
+ maskimm
> 32)
4053 as_bad (_("immediate operands sum to greater than 32"));
4058 /* If the instruction will definitely need to be relaxed, it is better
4059 to expand it now for better scheduling. Decide whether to expand
4061 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4063 /* Calls should be expanded to longcalls only in the backend relaxation
4064 so that the assembly scheduler will keep the L32R/CALLX instructions
4066 if (is_direct_call_opcode (orig_insn
->opcode
))
4069 if (tinsn_has_symbolic_operands (orig_insn
))
4071 /* The values of symbolic operands are not known yet, so only expand
4072 now if an operand is "complex" (e.g., difference of symbols) and
4073 will have to be stored as a literal regardless of the value. */
4074 if (!tinsn_has_complex_operands (orig_insn
))
4077 else if (xg_immeds_fit (orig_insn
))
4081 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4083 istack_push (istack
, orig_insn
);
4089 /* Return TRUE if the section flags are marked linkonce
4090 or the name is .gnu.linkonce.*. */
4092 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4095 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4097 flagword flags
, link_once_flags
;
4099 flags
= bfd_get_section_flags (abfd
, sec
);
4100 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4102 /* Flags might not be set yet. */
4103 if (!link_once_flags
4104 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4105 link_once_flags
= SEC_LINK_ONCE
;
4107 return (link_once_flags
!= 0);
4112 xtensa_add_literal_sym (symbolS
*sym
)
4116 l
= XNEW (sym_list
);
4118 l
->next
= literal_syms
;
4124 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4126 static int lit_num
= 0;
4127 static char name
[256];
4130 sprintf (name
, ".L_lit_sym%d", lit_num
);
4132 /* Create a local symbol. If it is in a linkonce section, we have to
4133 be careful to make sure that if it is used in a relocation that the
4134 symbol will be in the output file. */
4135 if (get_is_linkonce_section (stdoutput
, sec
))
4137 symbolP
= symbol_new (name
, sec
, 0, frag
);
4138 S_CLEAR_EXTERNAL (symbolP
);
4139 /* symbolP->local = 1; */
4142 symbolP
= symbol_new (name
, sec
, 0, frag
);
4144 xtensa_add_literal_sym (symbolP
);
4151 /* Currently all literals that are generated here are 32-bit L32R targets. */
4154 xg_assemble_literal (/* const */ TInsn
*insn
)
4157 symbolS
*lit_sym
= NULL
;
4158 bfd_reloc_code_real_type reloc
;
4159 bfd_boolean pcrel
= FALSE
;
4162 /* size = 4 for L32R. It could easily be larger when we move to
4163 larger constants. Add a parameter later. */
4164 offsetT litsize
= 4;
4165 offsetT litalign
= 2; /* 2^2 = 4 */
4166 expressionS saved_loc
;
4167 expressionS
* emit_val
;
4169 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4171 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4172 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4174 xtensa_switch_to_literal_fragment (&state
);
4176 emit_val
= &insn
->tok
[0];
4177 if (emit_val
->X_op
== O_big
)
4179 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4182 /* This happens when someone writes a "movi a2, big_number". */
4183 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4184 _("invalid immediate"));
4185 xtensa_restore_emit_state (&state
);
4190 /* Force a 4-byte align here. Note that this opens a new frag, so all
4191 literals done with this function have a frag to themselves. That's
4192 important for the way text section literals work. */
4193 frag_align (litalign
, 0, 0);
4194 record_alignment (now_seg
, litalign
);
4196 switch (emit_val
->X_op
)
4206 p
= frag_more (litsize
);
4207 xtensa_set_frag_assembly_state (frag_now
);
4208 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4209 if (emit_val
->X_add_symbol
)
4210 emit_val
->X_op
= O_symbol
;
4212 emit_val
->X_op
= O_constant
;
4213 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4214 litsize
, emit_val
, pcrel
, reloc
);
4218 emit_expr (emit_val
, litsize
);
4222 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4223 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4224 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4225 lit_sym
= frag_now
->fr_symbol
;
4228 xtensa_restore_emit_state (&state
);
4234 xg_assemble_literal_space (/* const */ int size
, int slot
)
4237 /* We might have to do something about this alignment. It only
4238 takes effect if something is placed here. */
4239 offsetT litalign
= 2; /* 2^2 = 4 */
4240 fragS
*lit_saved_frag
;
4242 gas_assert (size
% 4 == 0);
4244 xtensa_switch_to_literal_fragment (&state
);
4246 /* Force a 4-byte align here. */
4247 frag_align (litalign
, 0, 0);
4248 record_alignment (now_seg
, litalign
);
4252 lit_saved_frag
= frag_now
;
4253 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4254 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4255 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4258 xtensa_restore_emit_state (&state
);
4259 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4263 /* Put in a fixup record based on the opcode.
4264 Return TRUE on success. */
4267 xg_add_opcode_fix (TInsn
*tinsn
,
4275 xtensa_opcode opcode
= tinsn
->opcode
;
4276 bfd_reloc_code_real_type reloc
;
4277 reloc_howto_type
*howto
;
4281 reloc
= BFD_RELOC_NONE
;
4283 /* First try the special cases for "alternate" relocs. */
4284 if (opcode
== xtensa_l32r_opcode
)
4286 if (fragP
->tc_frag_data
.use_absolute_literals
)
4287 reloc
= encode_alt_reloc (slot
);
4289 else if (opcode
== xtensa_const16_opcode
)
4291 if (exp
->X_op
== O_lo16
)
4293 reloc
= encode_reloc (slot
);
4294 exp
->X_op
= O_symbol
;
4296 else if (exp
->X_op
== O_hi16
)
4298 reloc
= encode_alt_reloc (slot
);
4299 exp
->X_op
= O_symbol
;
4303 if (opnum
!= get_relaxable_immed (opcode
))
4305 as_bad (_("invalid relocation for operand %i of '%s'"),
4306 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4310 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4311 into the symbol table where the generic portions of the assembler
4312 won't know what to do with them. */
4313 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4315 as_bad (_("invalid expression for operand %i of '%s'"),
4316 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4320 /* Next try the generic relocs. */
4321 if (reloc
== BFD_RELOC_NONE
)
4322 reloc
= encode_reloc (slot
);
4323 if (reloc
== BFD_RELOC_NONE
)
4325 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4329 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4332 as_bad (_("undefined symbol for opcode \"%s\""),
4333 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4337 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4338 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4339 howto
->pc_relative
, reloc
);
4340 the_fix
->fx_no_overflow
= 1;
4341 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4342 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4343 the_fix
->tc_fix_data
.slot
= slot
;
4350 xg_emit_insn_to_buf (TInsn
*tinsn
,
4354 bfd_boolean build_fix
)
4356 static xtensa_insnbuf insnbuf
= NULL
;
4357 bfd_boolean has_symbolic_immed
= FALSE
;
4358 bfd_boolean ok
= TRUE
;
4361 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4363 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4364 if (has_symbolic_immed
&& build_fix
)
4367 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4368 int slot
= xg_get_single_slot (tinsn
->opcode
);
4369 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4370 expressionS
*exp
= &tinsn
->tok
[opnum
];
4372 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4375 fragP
->tc_frag_data
.is_insn
= TRUE
;
4376 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4377 (unsigned char *) buf
, 0);
4383 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4385 symbolS
*sym
= get_special_literal_symbol ();
4389 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4390 for (i
= 0; i
< insn
->ntok
; i
++)
4391 if (insn
->tok
[i
].X_add_symbol
== sym
)
4392 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4398 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4400 symbolS
*sym
= get_special_label_symbol ();
4402 for (i
= 0; i
< insn
->ntok
; i
++)
4403 if (insn
->tok
[i
].X_add_symbol
== sym
)
4404 insn
->tok
[i
].X_add_symbol
= label_sym
;
4409 /* Return TRUE if the instruction can write to the specified
4410 integer register. */
4413 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4417 xtensa_isa isa
= xtensa_default_isa
;
4419 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4421 for (i
= 0; i
< num_ops
; i
++)
4424 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4425 if ((inout
== 'o' || inout
== 'm')
4426 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4428 xtensa_regfile opnd_rf
=
4429 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4430 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4432 if ((insn
->tok
[i
].X_op
== O_register
)
4433 && (insn
->tok
[i
].X_add_number
== regnum
))
4443 is_bad_loopend_opcode (const TInsn
*tinsn
)
4445 xtensa_opcode opcode
= tinsn
->opcode
;
4447 if (opcode
== XTENSA_UNDEFINED
)
4450 if (opcode
== xtensa_call0_opcode
4451 || opcode
== xtensa_callx0_opcode
4452 || opcode
== xtensa_call4_opcode
4453 || opcode
== xtensa_callx4_opcode
4454 || opcode
== xtensa_call8_opcode
4455 || opcode
== xtensa_callx8_opcode
4456 || opcode
== xtensa_call12_opcode
4457 || opcode
== xtensa_callx12_opcode
4458 || opcode
== xtensa_isync_opcode
4459 || opcode
== xtensa_ret_opcode
4460 || opcode
== xtensa_ret_n_opcode
4461 || opcode
== xtensa_retw_opcode
4462 || opcode
== xtensa_retw_n_opcode
4463 || opcode
== xtensa_waiti_opcode
4464 || opcode
== xtensa_rsr_lcount_opcode
)
4471 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4472 This allows the debugger to add unaligned labels.
4473 Also, the assembler generates stabs labels that need
4474 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4477 is_unaligned_label (symbolS
*sym
)
4479 const char *name
= S_GET_NAME (sym
);
4480 static size_t fake_size
= 0;
4484 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4487 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4489 fake_size
= strlen (FAKE_LABEL_NAME
);
4492 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4493 && (name
[fake_size
] == 'F'
4494 || name
[fake_size
] == 'L'
4495 || (name
[fake_size
] == 'e'
4496 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4504 next_non_empty_frag (const fragS
*fragP
)
4506 fragS
*next_fragP
= fragP
->fr_next
;
4508 /* Sometimes an empty will end up here due storage allocation issues.
4509 So we have to skip until we find something legit. */
4510 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4511 next_fragP
= next_fragP
->fr_next
;
4513 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4521 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4523 xtensa_opcode out_opcode
;
4524 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4526 if (next_fragP
== NULL
)
4529 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4530 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4532 *opcode
= out_opcode
;
4540 frag_format_size (const fragS
*fragP
)
4542 static xtensa_insnbuf insnbuf
= NULL
;
4543 xtensa_isa isa
= xtensa_default_isa
;
4548 insnbuf
= xtensa_insnbuf_alloc (isa
);
4551 return XTENSA_UNDEFINED
;
4553 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4554 (unsigned char *) fragP
->fr_literal
, 0);
4556 fmt
= xtensa_format_decode (isa
, insnbuf
);
4557 if (fmt
== XTENSA_UNDEFINED
)
4558 return XTENSA_UNDEFINED
;
4559 fmt_size
= xtensa_format_length (isa
, fmt
);
4561 /* If the next format won't be changing due to relaxation, just
4562 return the length of the first format. */
4563 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4566 /* If during relaxation we have to pull an instruction out of a
4567 multi-slot instruction, we will return the more conservative
4568 number. This works because alignment on bigger instructions
4569 is more restrictive than alignment on smaller instructions.
4570 This is more conservative than we would like, but it happens
4573 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4576 /* If we aren't doing one of our own relaxations or it isn't
4577 slot-based, then the insn size won't change. */
4578 if (fragP
->fr_type
!= rs_machine_dependent
)
4580 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4583 /* If an instruction is about to grow, return the longer size. */
4584 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4585 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4586 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4588 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4589 instruction in the relaxed version is of length 3. (The case
4590 where we have to pull the instruction out of a FLIX bundle
4591 is handled conservatively above.) However, frags with opcodes
4592 that are expanding to wide branches end up having formats that
4593 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4594 we can't tell directly what format the relaxer picked. This
4595 is a wart in the design of the relaxer that should someday be
4596 fixed, but would require major changes, or at least should
4597 be accompanied by major changes to make use of that data.
4599 In any event, we can tell that we are expanding from a single-slot
4600 format to a wider one with the logic below. */
4603 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4605 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4607 if (relaxed_size
== xtensa_format_length (isa
, i
))
4608 return relaxed_size
;
4614 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4615 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4622 next_frag_format_size (const fragS
*fragP
)
4624 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4625 return frag_format_size (next_fragP
);
4629 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4630 required two-byte instructions to be treated as three-byte instructions
4631 for loop instruction alignment. This restriction was removed beginning
4632 with Xtensa LX. Now the only requirement on loop instruction alignment
4633 is that the first instruction of the loop must appear at an address that
4634 does not cross a fetch boundary. */
4637 get_loop_align_size (int insn_size
)
4639 if (insn_size
== XTENSA_UNDEFINED
)
4640 return xtensa_fetch_width
;
4642 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4649 /* If the next legit fragment is an end-of-loop marker,
4650 switch its state so it will instantiate a NOP. */
4653 update_next_frag_state (fragS
*fragP
)
4655 fragS
*next_fragP
= fragP
->fr_next
;
4656 fragS
*new_target
= NULL
;
4660 /* We are guaranteed there will be one of these... */
4661 while (!(next_fragP
->fr_type
== rs_machine_dependent
4662 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4663 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4664 next_fragP
= next_fragP
->fr_next
;
4666 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4667 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4668 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4670 /* ...and one of these. */
4671 new_target
= next_fragP
->fr_next
;
4672 while (!(new_target
->fr_type
== rs_machine_dependent
4673 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4674 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4675 new_target
= new_target
->fr_next
;
4677 gas_assert (new_target
->fr_type
== rs_machine_dependent
4678 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4679 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4682 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4684 if (next_fragP
->fr_type
== rs_machine_dependent
4685 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4687 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4691 next_fragP
= next_fragP
->fr_next
;
4697 next_frag_is_branch_target (const fragS
*fragP
)
4699 /* Sometimes an empty will end up here due to storage allocation issues,
4700 so we have to skip until we find something legit. */
4701 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4703 if (fragP
->tc_frag_data
.is_branch_target
)
4705 if (fragP
->fr_fix
!= 0)
4713 next_frag_is_loop_target (const fragS
*fragP
)
4715 /* Sometimes an empty will end up here due storage allocation issues.
4716 So we have to skip until we find something legit. */
4717 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4719 if (fragP
->tc_frag_data
.is_loop_target
)
4721 if (fragP
->fr_fix
!= 0)
4728 /* As specified in the relaxation table, when a loop instruction is
4729 relaxed, there are 24 bytes between the loop instruction itself and
4730 the first instruction in the loop. */
4732 #define RELAXED_LOOP_INSN_BYTES 24
4735 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4737 const fragS
*next_fragp
= fragp
->fr_next
;
4738 xtensa_opcode next_opcode
;
4740 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4743 /* Sometimes an empty will end up here due to storage allocation issues,
4744 so we have to skip until we find something legit. */
4745 while (next_fragp
->fr_fix
== 0)
4746 next_fragp
= next_fragp
->fr_next
;
4748 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4751 /* There is some implicit knowledge encoded in here.
4752 The LOOP instructions that are NOT RELAX_IMMED have
4753 been relaxed. Note that we can assume that the LOOP
4754 instruction is in slot 0 because loops aren't bundleable. */
4755 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4756 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4762 /* Mark a location where we can later insert literal frags. Update
4763 the section's literal_pool_loc, so subsequent literals can be
4764 placed nearest to their use. */
4767 xtensa_mark_literal_pool_location (void)
4769 /* Any labels pointing to the current location need
4770 to be adjusted to after the literal pool. */
4772 fragS
*pool_location
;
4774 if (use_literal_section
)
4777 /* We stash info in these frags so we can later move the literal's
4778 fixes into this frchain's fix list. */
4779 pool_location
= frag_now
;
4780 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4781 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4782 /* Just record this frag. */
4783 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4784 frag_variant (rs_machine_dependent
, 0, 0,
4785 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4786 xtensa_set_frag_assembly_state (frag_now
);
4787 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4788 frag_variant (rs_machine_dependent
, 0, 0,
4789 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4790 xtensa_set_frag_assembly_state (frag_now
);
4792 /* Now put a frag into the literal pool that points to this location. */
4793 set_literal_pool_location (now_seg
, pool_location
);
4794 xtensa_switch_to_non_abs_literal_fragment (&s
);
4795 frag_align (2, 0, 0);
4796 record_alignment (now_seg
, 2);
4798 /* Close whatever frag is there. */
4799 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4800 xtensa_set_frag_assembly_state (frag_now
);
4801 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4802 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4803 xtensa_restore_emit_state (&s
);
4804 xtensa_set_frag_assembly_state (frag_now
);
4808 /* Build a nop of the correct size into tinsn. */
4811 build_nop (TInsn
*tinsn
, int size
)
4817 tinsn
->opcode
= xtensa_nop_n_opcode
;
4819 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4820 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4824 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4826 tinsn
->opcode
= xtensa_or_opcode
;
4827 set_expr_const (&tinsn
->tok
[0], 1);
4828 set_expr_const (&tinsn
->tok
[1], 1);
4829 set_expr_const (&tinsn
->tok
[2], 1);
4833 tinsn
->opcode
= xtensa_nop_opcode
;
4835 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4840 /* Assemble a NOP of the requested size in the buffer. User must have
4841 allocated "buf" with at least "size" bytes. */
4844 assemble_nop (int size
, char *buf
)
4846 static xtensa_insnbuf insnbuf
= NULL
;
4849 build_nop (&tinsn
, size
);
4852 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4854 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4855 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4856 (unsigned char *) buf
, 0);
4860 /* Return the number of bytes for the offset of the expanded loop
4861 instruction. This should be incorporated into the relaxation
4862 specification but is hard-coded here. This is used to auto-align
4863 the loop instruction. It is invalid to call this function if the
4864 configuration does not have loops or if the opcode is not a loop
4868 get_expanded_loop_offset (xtensa_opcode opcode
)
4870 /* This is the OFFSET of the loop instruction in the expanded loop.
4871 This MUST correspond directly to the specification of the loop
4872 expansion. It will be validated on fragment conversion. */
4873 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4874 if (opcode
== xtensa_loop_opcode
)
4876 if (opcode
== xtensa_loopnez_opcode
)
4878 if (opcode
== xtensa_loopgtz_opcode
)
4880 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4886 get_literal_pool_location (segT seg
)
4888 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4889 struct litpool_frag
*lpf
;
4890 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4894 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4895 { /* Skip "candidates" for now. */
4896 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4900 /* Must convert a lower-priority pool. */
4901 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4903 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4906 /* Still no match -- try for a low priority pool. */
4907 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4909 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4913 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4918 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4920 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4924 /* Set frag assembly state should be called when a new frag is
4925 opened and after a frag has been closed. */
4928 xtensa_set_frag_assembly_state (fragS
*fragP
)
4930 if (!density_supported
)
4931 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4933 /* This function is called from subsegs_finish, which is called
4934 after xtensa_end, so we can't use "use_transform" or
4935 "use_schedule" here. */
4936 if (!directive_state
[directive_transform
])
4937 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4938 if (directive_state
[directive_longcalls
])
4939 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4940 fragP
->tc_frag_data
.use_absolute_literals
=
4941 directive_state
[directive_absolute_literals
];
4942 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4947 relaxable_section (asection
*sec
)
4949 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4950 && strcmp (sec
->name
, ".eh_frame") != 0);
4955 xtensa_mark_frags_for_org (void)
4959 /* Walk over each fragment of all of the current segments. If we find
4960 a .org frag in any of the segments, mark all frags prior to it as
4961 "no transform", which will prevent linker optimizations from messing
4962 up the .org distance. This should be done after
4963 xtensa_find_unmarked_state_frags, because we don't want to worry here
4964 about that function trashing the data we save here. */
4966 for (seclist
= &stdoutput
->sections
;
4967 seclist
&& *seclist
;
4968 seclist
= &(*seclist
)->next
)
4970 segT sec
= *seclist
;
4971 segment_info_type
*seginfo
;
4974 flags
= bfd_get_section_flags (stdoutput
, sec
);
4975 if (flags
& SEC_DEBUGGING
)
4977 if (!(flags
& SEC_ALLOC
))
4980 seginfo
= seg_info (sec
);
4981 if (seginfo
&& seginfo
->frchainP
)
4983 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4984 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4985 fragP
= fragP
->fr_next
)
4987 /* cvt_frag_to_fill has changed the fr_type of org frags to
4988 rs_fill, so use the value as cached in rs_subtype here. */
4989 if (fragP
->fr_subtype
== RELAX_ORG
)
4991 while (last_fragP
!= fragP
->fr_next
)
4993 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4994 last_fragP
= last_fragP
->fr_next
;
5004 xtensa_find_unmarked_state_frags (void)
5008 /* Walk over each fragment of all of the current segments. For each
5009 unmarked fragment, mark it with the same info as the previous
5011 for (seclist
= &stdoutput
->sections
;
5012 seclist
&& *seclist
;
5013 seclist
= &(*seclist
)->next
)
5015 segT sec
= *seclist
;
5016 segment_info_type
*seginfo
;
5019 flags
= bfd_get_section_flags (stdoutput
, sec
);
5020 if (flags
& SEC_DEBUGGING
)
5022 if (!(flags
& SEC_ALLOC
))
5025 seginfo
= seg_info (sec
);
5026 if (seginfo
&& seginfo
->frchainP
)
5028 fragS
*last_fragP
= 0;
5029 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5030 fragP
= fragP
->fr_next
)
5032 if (fragP
->fr_fix
!= 0
5033 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5035 if (last_fragP
== 0)
5037 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5038 _("assembly state not set for first frag in section %s"),
5043 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5044 fragP
->tc_frag_data
.is_no_density
=
5045 last_fragP
->tc_frag_data
.is_no_density
;
5046 fragP
->tc_frag_data
.is_no_transform
=
5047 last_fragP
->tc_frag_data
.is_no_transform
;
5048 fragP
->tc_frag_data
.use_longcalls
=
5049 last_fragP
->tc_frag_data
.use_longcalls
;
5050 fragP
->tc_frag_data
.use_absolute_literals
=
5051 last_fragP
->tc_frag_data
.use_absolute_literals
;
5054 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5063 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5065 void *unused ATTRIBUTE_UNUSED
)
5067 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5068 segment_info_type
*seginfo
= seg_info (sec
);
5069 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5071 if (flags
& SEC_CODE
)
5073 xtensa_isa isa
= xtensa_default_isa
;
5074 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5075 while (frag
!= NULL
)
5077 if (frag
->tc_frag_data
.is_branch_target
)
5080 addressT branch_align
, frag_addr
;
5083 xtensa_insnbuf_from_chars
5084 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5085 fmt
= xtensa_format_decode (isa
, insnbuf
);
5086 op_size
= xtensa_format_length (isa
, fmt
);
5087 branch_align
= 1 << branch_align_power (sec
);
5088 frag_addr
= frag
->fr_address
% branch_align
;
5089 if (frag_addr
+ op_size
> branch_align
)
5090 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5091 _("unaligned branch target: %d bytes at 0x%lx"),
5092 op_size
, (long) frag
->fr_address
);
5094 frag
= frag
->fr_next
;
5096 xtensa_insnbuf_free (isa
, insnbuf
);
5102 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5104 void *unused ATTRIBUTE_UNUSED
)
5106 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5107 segment_info_type
*seginfo
= seg_info (sec
);
5108 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5109 xtensa_isa isa
= xtensa_default_isa
;
5111 if (flags
& SEC_CODE
)
5113 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5114 while (frag
!= NULL
)
5116 if (frag
->tc_frag_data
.is_first_loop_insn
)
5122 if (frag
->fr_fix
== 0)
5123 frag
= next_non_empty_frag (frag
);
5127 xtensa_insnbuf_from_chars
5128 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5129 fmt
= xtensa_format_decode (isa
, insnbuf
);
5130 op_size
= xtensa_format_length (isa
, fmt
);
5131 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5133 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5134 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5135 _("unaligned loop: %d bytes at 0x%lx"),
5136 op_size
, (long) frag
->fr_address
);
5139 frag
= frag
->fr_next
;
5141 xtensa_insnbuf_free (isa
, insnbuf
);
5147 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5149 xtensa_isa isa
= xtensa_default_isa
;
5150 static xtensa_insnbuf insnbuf
= NULL
;
5151 static xtensa_insnbuf slotbuf
= NULL
;
5154 bfd_boolean alt_reloc
;
5155 xtensa_opcode opcode
;
5156 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5158 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5160 as_fatal (_("unexpected fix"));
5164 insnbuf
= xtensa_insnbuf_alloc (isa
);
5165 slotbuf
= xtensa_insnbuf_alloc (isa
);
5168 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5169 fmt
= xtensa_format_decode (isa
, insnbuf
);
5170 if (fmt
== XTENSA_UNDEFINED
)
5171 as_fatal (_("undecodable fix"));
5172 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5173 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5174 if (opcode
== XTENSA_UNDEFINED
)
5175 as_fatal (_("undecodable fix"));
5177 /* CONST16 immediates are not PC-relative, despite the fact that we
5178 reuse the normal PC-relative operand relocations for the low part
5179 of a CONST16 operand. */
5180 if (opcode
== xtensa_const16_opcode
)
5183 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5184 get_relaxable_immed (opcode
), val
,
5185 fixP
->fx_file
, fixP
->fx_line
);
5187 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5188 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5194 /* External Functions and Other GAS Hooks. */
5197 xtensa_target_format (void)
5199 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5204 xtensa_file_arch_init (bfd
*abfd
)
5206 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5211 md_number_to_chars (char *buf
, valueT val
, int n
)
5213 if (target_big_endian
)
5214 number_to_chars_bigendian (buf
, val
, n
);
5216 number_to_chars_littleendian (buf
, val
, n
);
5220 xg_init_global_config (void)
5222 target_big_endian
= XCHAL_HAVE_BE
;
5224 density_supported
= XCHAL_HAVE_DENSITY
;
5225 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5226 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5228 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5229 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5233 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5235 xg_init_global_config ();
5238 /* This function is called once, at assembler startup time. It should
5239 set up all the tables, etc. that the MD part of the assembler will
5245 segT current_section
= now_seg
;
5246 int current_subsec
= now_subseg
;
5250 xtensa_default_isa
= xtensa_isa_init (0, 0);
5251 isa
= xtensa_default_isa
;
5255 /* Set up the literal sections. */
5256 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5258 subseg_set (current_section
, current_subsec
);
5260 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5261 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5262 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5263 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5264 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5265 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5266 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5267 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5268 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5269 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5270 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5271 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5272 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5273 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5274 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5275 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5276 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5277 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5278 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5279 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5280 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5281 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5282 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5283 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5284 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5285 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5286 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5287 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5288 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5289 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5290 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5292 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5294 int format_slots
= xtensa_format_num_slots (isa
, i
);
5295 if (format_slots
> config_max_slots
)
5296 config_max_slots
= format_slots
;
5299 xg_init_vinsn (&cur_vinsn
);
5301 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5303 init_op_placement_info_table ();
5305 /* Set up the assembly state. */
5306 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5307 xtensa_set_frag_assembly_state (frag_now
);
5311 /* TC_INIT_FIX_DATA hook */
5314 xtensa_init_fix_data (fixS
*x
)
5316 x
->tc_fix_data
.slot
= 0;
5317 x
->tc_fix_data
.X_add_symbol
= NULL
;
5318 x
->tc_fix_data
.X_add_number
= 0;
5322 /* tc_frob_label hook */
5325 xtensa_frob_label (symbolS
*sym
)
5329 if (cur_vinsn
.inside_bundle
)
5331 as_bad (_("labels are not valid inside bundles"));
5335 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5337 /* Since the label was already attached to a frag associated with the
5338 previous basic block, it now needs to be reset to the current frag. */
5339 symbol_set_frag (sym
, frag_now
);
5340 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5342 if (generating_literals
)
5343 xtensa_add_literal_sym (sym
);
5345 xtensa_add_insn_label (sym
);
5347 if (symbol_get_tc (sym
)->is_loop_target
)
5349 if ((get_last_insn_flags (now_seg
, now_subseg
)
5350 & FLAG_IS_BAD_LOOPEND
) != 0)
5351 as_bad (_("invalid last instruction for a zero-overhead loop"));
5353 xtensa_set_frag_assembly_state (frag_now
);
5354 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5355 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5357 xtensa_set_frag_assembly_state (frag_now
);
5358 xtensa_move_labels (frag_now
, 0);
5361 /* No target aligning in the absolute section. */
5362 if (now_seg
!= absolute_section
5363 && !is_unaligned_label (sym
)
5364 && !generating_literals
)
5366 xtensa_set_frag_assembly_state (frag_now
);
5368 if (do_align_targets ())
5369 frag_var (rs_machine_dependent
, 0, (int) freq
,
5370 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5371 frag_now
->fr_offset
, NULL
);
5373 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5374 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5375 xtensa_set_frag_assembly_state (frag_now
);
5376 xtensa_move_labels (frag_now
, 0);
5379 /* We need to mark the following properties even if we aren't aligning. */
5381 /* If the label is already known to be a branch target, i.e., a
5382 forward branch, mark the frag accordingly. Backward branches
5383 are handled by xg_add_branch_and_loop_targets. */
5384 if (symbol_get_tc (sym
)->is_branch_target
)
5385 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5387 /* Loops only go forward, so they can be identified here. */
5388 if (symbol_get_tc (sym
)->is_loop_target
)
5389 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5391 dwarf2_emit_label (sym
);
5395 /* tc_unrecognized_line hook */
5398 xtensa_unrecognized_line (int ch
)
5403 if (cur_vinsn
.inside_bundle
== 0)
5405 /* PR8110: Cannot emit line number info inside a FLIX bundle
5406 when using --gstabs. Temporarily disable debug info. */
5407 generate_lineno_debug ();
5408 if (debug_type
== DEBUG_STABS
)
5410 xt_saved_debug_type
= debug_type
;
5411 debug_type
= DEBUG_NONE
;
5414 cur_vinsn
.inside_bundle
= 1;
5418 as_bad (_("extra opening brace"));
5424 if (cur_vinsn
.inside_bundle
)
5425 finish_vinsn (&cur_vinsn
);
5428 as_bad (_("extra closing brace"));
5433 as_bad (_("syntax error"));
5440 /* md_flush_pending_output hook */
5443 xtensa_flush_pending_output (void)
5445 /* This line fixes a bug where automatically generated gstabs info
5446 separates a function label from its entry instruction, ending up
5447 with the literal position between the function label and the entry
5448 instruction and crashing code. It only happens with --gstabs and
5449 --text-section-literals, and when several other obscure relaxation
5450 conditions are met. */
5451 if (outputting_stabs_line_debug
)
5454 if (cur_vinsn
.inside_bundle
)
5455 as_bad (_("missing closing brace"));
5457 /* If there is a non-zero instruction fragment, close it. */
5458 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5460 frag_wane (frag_now
);
5462 xtensa_set_frag_assembly_state (frag_now
);
5464 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5466 xtensa_clear_insn_labels ();
5470 /* We had an error while parsing an instruction. The string might look
5471 like this: "insn arg1, arg2 }". If so, we need to see the closing
5472 brace and reset some fields. Otherwise, the vinsn never gets closed
5473 and the num_slots field will grow past the end of the array of slots,
5474 and bad things happen. */
5477 error_reset_cur_vinsn (void)
5479 if (cur_vinsn
.inside_bundle
)
5481 if (*input_line_pointer
== '}'
5482 || *(input_line_pointer
- 1) == '}'
5483 || *(input_line_pointer
- 2) == '}')
5484 xg_clear_vinsn (&cur_vinsn
);
5490 md_assemble (char *str
)
5492 xtensa_isa isa
= xtensa_default_isa
;
5495 bfd_boolean has_underbar
= FALSE
;
5496 char *arg_strings
[MAX_INSN_ARGS
];
5498 TInsn orig_insn
; /* Original instruction from the input. */
5500 tinsn_init (&orig_insn
);
5502 /* Split off the opcode. */
5503 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5504 opname
= xstrndup (str
, opnamelen
);
5506 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5509 as_bad (_("syntax error"));
5513 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5516 /* Check for an underbar prefix. */
5519 has_underbar
= TRUE
;
5523 orig_insn
.insn_type
= ITYPE_INSN
;
5525 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5526 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5528 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5529 extra argument and set the opcode to "CALLXn". */
5530 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5531 && strncasecmp (opname
, "callx", 5) == 0)
5533 unsigned long window_size
;
5536 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5537 if (suffix
!= opname
+ 5
5538 && (window_size
== 0
5541 || window_size
== 12)
5542 && strcasecmp (suffix
, ".tls") == 0)
5544 switch (window_size
)
5546 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5547 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5548 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5549 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5553 as_bad (_("wrong number of operands for '%s'"), opname
);
5556 bfd_reloc_code_real_type reloc
;
5557 char *old_input_line_pointer
;
5558 expressionS
*tok
= &orig_insn
.extra_arg
;
5560 old_input_line_pointer
= input_line_pointer
;
5561 input_line_pointer
= arg_strings
[num_args
- 1];
5564 if (tok
->X_op
== O_symbol
5565 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5566 == BFD_RELOC_XTENSA_TLS_CALL
))
5567 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5569 as_bad (_("bad relocation expression for '%s'"), opname
);
5571 input_line_pointer
= old_input_line_pointer
;
5577 /* Special case: Check for "j.l" pseudo op. */
5578 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5579 && strncasecmp (opname
, "j.l", 3) == 0)
5582 as_bad (_("wrong number of operands for '%s'"), opname
);
5585 char *old_input_line_pointer
;
5586 expressionS
*tok
= &orig_insn
.extra_arg
;
5588 old_input_line_pointer
= input_line_pointer
;
5589 input_line_pointer
= arg_strings
[num_args
- 1];
5591 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5592 input_line_pointer
= old_input_line_pointer
;
5595 orig_insn
.opcode
= xtensa_j_opcode
;
5599 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5601 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5602 if (fmt
== XTENSA_UNDEFINED
)
5604 as_bad (_("unknown opcode or format name '%s'"), opname
);
5605 error_reset_cur_vinsn ();
5608 if (!cur_vinsn
.inside_bundle
)
5610 as_bad (_("format names only valid inside bundles"));
5611 error_reset_cur_vinsn ();
5614 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5615 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5617 cur_vinsn
.format
= fmt
;
5618 free (has_underbar
? opname
- 1 : opname
);
5619 error_reset_cur_vinsn ();
5623 /* Parse the arguments. */
5624 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5626 as_bad (_("syntax error"));
5627 error_reset_cur_vinsn ();
5631 /* Free the opcode and argument strings, now that they've been parsed. */
5632 free (has_underbar
? opname
- 1 : opname
);
5634 while (num_args
-- > 0)
5635 free (arg_strings
[num_args
]);
5637 /* Get expressions for invisible operands. */
5638 if (get_invisible_operands (&orig_insn
))
5640 error_reset_cur_vinsn ();
5644 /* Check for the right number and type of arguments. */
5645 if (tinsn_check_arguments (&orig_insn
))
5647 error_reset_cur_vinsn ();
5651 /* Record the line number for each TInsn, because a FLIX bundle may be
5652 spread across multiple input lines and individual instructions may be
5653 moved around in some cases. */
5654 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5655 dwarf2_where (&orig_insn
.debug_line
);
5656 dwarf2_consume_line_info ();
5658 xg_add_branch_and_loop_targets (&orig_insn
);
5660 /* Check that immediate value for ENTRY is >= 16. */
5661 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5663 expressionS
*exp
= &orig_insn
.tok
[2];
5664 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5665 as_warn (_("entry instruction with stack decrement < 16"));
5669 assemble_tokens (opcode, tok, ntok);
5670 expand the tokens from the orig_insn into the
5671 stack of instructions that will not expand
5672 unless required at relaxation time. */
5674 if (!cur_vinsn
.inside_bundle
)
5675 emit_single_op (&orig_insn
);
5676 else /* We are inside a bundle. */
5678 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5679 cur_vinsn
.num_slots
++;
5680 if (*input_line_pointer
== '}'
5681 || *(input_line_pointer
- 1) == '}'
5682 || *(input_line_pointer
- 2) == '}')
5683 finish_vinsn (&cur_vinsn
);
5686 /* We've just emitted a new instruction so clear the list of labels. */
5687 xtensa_clear_insn_labels ();
5689 xtensa_check_frag_count ();
5693 /* HANDLE_ALIGN hook */
5695 /* For a .align directive, we mark the previous block with the alignment
5696 information. This will be placed in the object file in the
5697 property section corresponding to this section. */
5700 xtensa_handle_align (fragS
*fragP
)
5703 && ! fragP
->tc_frag_data
.is_literal
5704 && (fragP
->fr_type
== rs_align
5705 || fragP
->fr_type
== rs_align_code
)
5706 && fragP
->fr_offset
> 0
5707 && now_seg
!= bss_section
)
5709 fragP
->tc_frag_data
.is_align
= TRUE
;
5710 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5713 if (fragP
->fr_type
== rs_align_test
)
5716 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5718 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5719 _("unaligned entry instruction"));
5722 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5723 fragP
->fr_subtype
= RELAX_ORG
;
5727 /* TC_FRAG_INIT hook */
5730 xtensa_frag_init (fragS
*frag
)
5732 xtensa_set_frag_assembly_state (frag
);
5737 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5743 /* Round up a section size to the appropriate boundary. */
5746 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5748 return size
; /* Byte alignment is fine. */
5753 md_pcrel_from (fixS
*fixP
)
5756 static xtensa_insnbuf insnbuf
= NULL
;
5757 static xtensa_insnbuf slotbuf
= NULL
;
5760 xtensa_opcode opcode
;
5763 xtensa_isa isa
= xtensa_default_isa
;
5764 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5765 bfd_boolean alt_reloc
;
5767 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5770 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5775 insnbuf
= xtensa_insnbuf_alloc (isa
);
5776 slotbuf
= xtensa_insnbuf_alloc (isa
);
5779 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5780 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5781 fmt
= xtensa_format_decode (isa
, insnbuf
);
5783 if (fmt
== XTENSA_UNDEFINED
)
5784 as_fatal (_("bad instruction format"));
5786 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5787 as_fatal (_("invalid relocation"));
5789 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5790 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5792 /* Check for "alternate" relocations (operand not specified). None
5793 of the current uses for these are really PC-relative. */
5794 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5796 if (opcode
!= xtensa_l32r_opcode
5797 && opcode
!= xtensa_const16_opcode
)
5798 as_fatal (_("invalid relocation for '%s' instruction"),
5799 xtensa_opcode_name (isa
, opcode
));
5803 opnum
= get_relaxable_immed (opcode
);
5805 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5806 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5808 as_bad_where (fixP
->fx_file
,
5810 _("invalid relocation for operand %d of '%s'"),
5811 opnum
, xtensa_opcode_name (isa
, opcode
));
5814 return 0 - opnd_value
;
5818 /* TC_FORCE_RELOCATION hook */
5821 xtensa_force_relocation (fixS
*fix
)
5823 switch (fix
->fx_r_type
)
5825 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5826 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5827 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5828 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5829 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5830 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5831 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5832 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5833 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5834 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5835 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5836 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5837 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5838 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5839 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5840 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5846 if (linkrelax
&& fix
->fx_addsy
5847 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5850 return generic_force_reloc (fix
);
5854 /* TC_VALIDATE_FIX_SUB hook */
5857 xtensa_validate_fix_sub (fixS
*fix
)
5859 segT add_symbol_segment
, sub_symbol_segment
;
5861 /* The difference of two symbols should be resolved by the assembler when
5862 linkrelax is not set. If the linker may relax the section containing
5863 the symbols, then an Xtensa DIFF relocation must be generated so that
5864 the linker knows to adjust the difference value. */
5865 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5868 /* Make sure both symbols are in the same segment, and that segment is
5869 "normal" and relaxable. If the segment is not "normal", then the
5870 fix is not valid. If the segment is not "relaxable", then the fix
5871 should have been handled earlier. */
5872 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5873 if (! SEG_NORMAL (add_symbol_segment
) ||
5874 ! relaxable_section (add_symbol_segment
))
5876 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5877 return (sub_symbol_segment
== add_symbol_segment
);
5881 /* NO_PSEUDO_DOT hook */
5883 /* This function has nothing to do with pseudo dots, but this is the
5884 nearest macro to where the check needs to take place. FIXME: This
5888 xtensa_check_inside_bundle (void)
5890 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5891 as_bad (_("directives are not valid inside bundles"));
5893 /* This function must always return FALSE because it is called via a
5894 macro that has nothing to do with bundling. */
5899 /* md_elf_section_change_hook */
5902 xtensa_elf_section_change_hook (void)
5904 /* Set up the assembly state. */
5905 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5906 xtensa_set_frag_assembly_state (frag_now
);
5910 /* tc_fix_adjustable hook */
5913 xtensa_fix_adjustable (fixS
*fixP
)
5915 /* We need the symbol name for the VTABLE entries. */
5916 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5917 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5924 /* tc_symbol_new_hook */
5926 symbolS
*expr_symbols
= NULL
;
5929 xtensa_symbol_new_hook (symbolS
*sym
)
5931 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5933 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5940 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5942 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5945 /* Subtracted symbols are only allowed for a few relocation types, and
5946 unless linkrelax is enabled, they should not make it to this point. */
5947 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5948 || fixP
->fx_r_type
== BFD_RELOC_16
5949 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5952 switch (fixP
->fx_r_type
)
5954 case BFD_RELOC_32_PCREL
:
5960 switch (fixP
->fx_r_type
)
5963 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5964 fixP
->fx_signed
= 0;
5967 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5968 fixP
->fx_signed
= 0;
5971 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5972 fixP
->fx_signed
= 0;
5978 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5979 - S_GET_VALUE (fixP
->fx_subsy
));
5981 /* The difference value gets written out, and the DIFF reloc
5982 identifies the address of the subtracted symbol (i.e., the one
5983 with the lowest address). */
5985 fixP
->fx_offset
-= val
;
5986 fixP
->fx_subsy
= NULL
;
5988 else if (! fixP
->fx_addsy
)
5995 case BFD_RELOC_XTENSA_PLT
:
5996 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5997 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6000 case BFD_RELOC_XTENSA_TLSDESC_FN
:
6001 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6002 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6003 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6004 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6005 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6006 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6009 case BFD_RELOC_XTENSA_SLOT0_OP
:
6010 case BFD_RELOC_XTENSA_SLOT1_OP
:
6011 case BFD_RELOC_XTENSA_SLOT2_OP
:
6012 case BFD_RELOC_XTENSA_SLOT3_OP
:
6013 case BFD_RELOC_XTENSA_SLOT4_OP
:
6014 case BFD_RELOC_XTENSA_SLOT5_OP
:
6015 case BFD_RELOC_XTENSA_SLOT6_OP
:
6016 case BFD_RELOC_XTENSA_SLOT7_OP
:
6017 case BFD_RELOC_XTENSA_SLOT8_OP
:
6018 case BFD_RELOC_XTENSA_SLOT9_OP
:
6019 case BFD_RELOC_XTENSA_SLOT10_OP
:
6020 case BFD_RELOC_XTENSA_SLOT11_OP
:
6021 case BFD_RELOC_XTENSA_SLOT12_OP
:
6022 case BFD_RELOC_XTENSA_SLOT13_OP
:
6023 case BFD_RELOC_XTENSA_SLOT14_OP
:
6026 /* Write the tentative value of a PC-relative relocation to a
6027 local symbol into the instruction. The value will be ignored
6028 by the linker, and it makes the object file disassembly
6029 readable when all branch targets are encoded in relocations. */
6031 gas_assert (fixP
->fx_addsy
);
6032 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6033 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6035 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6036 - md_pcrel_from (fixP
));
6037 (void) xg_apply_fix_value (fixP
, val
);
6040 else if (! fixP
->fx_addsy
)
6043 if (xg_apply_fix_value (fixP
, val
))
6048 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6049 case BFD_RELOC_XTENSA_TLS_FUNC
:
6050 case BFD_RELOC_XTENSA_TLS_ARG
:
6051 case BFD_RELOC_XTENSA_TLS_CALL
:
6052 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6053 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6054 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6055 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6056 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6057 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6058 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6059 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6060 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6061 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6062 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6063 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6064 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6065 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6066 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6067 /* These all need to be resolved at link-time. Do nothing now. */
6070 case BFD_RELOC_VTABLE_INHERIT
:
6071 case BFD_RELOC_VTABLE_ENTRY
:
6076 as_bad (_("unhandled local relocation fix %s"),
6077 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6083 md_atof (int type
, char *litP
, int *sizeP
)
6085 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6090 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6092 return total_frag_text_expansion (fragP
);
6096 /* Translate internal representation of relocation info to BFD target
6100 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6104 reloc
= XNEW (arelent
);
6105 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6106 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6107 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6109 /* Make sure none of our internal relocations make it this far.
6110 They'd better have been fully resolved by this point. */
6111 gas_assert ((int) fixp
->fx_r_type
> 0);
6113 reloc
->addend
= fixp
->fx_offset
;
6115 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6116 if (reloc
->howto
== NULL
)
6118 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6119 _("cannot represent `%s' relocation in object file"),
6120 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6121 free (reloc
->sym_ptr_ptr
);
6126 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6127 as_fatal (_("internal error; cannot generate `%s' relocation"),
6128 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6134 /* Checks for resource conflicts between instructions. */
6136 /* The func unit stuff could be implemented as bit-vectors rather
6137 than the iterative approach here. If it ends up being too
6138 slow, we will switch it. */
6141 new_resource_table (void *data
,
6144 unit_num_copies_func uncf
,
6145 opcode_num_units_func onuf
,
6146 opcode_funcUnit_use_unit_func ouuf
,
6147 opcode_funcUnit_use_stage_func ousf
)
6150 resource_table
*rt
= XNEW (resource_table
);
6152 rt
->cycles
= cycles
;
6153 rt
->allocated_cycles
= cycles
;
6155 rt
->unit_num_copies
= uncf
;
6156 rt
->opcode_num_units
= onuf
;
6157 rt
->opcode_unit_use
= ouuf
;
6158 rt
->opcode_unit_stage
= ousf
;
6160 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6161 for (i
= 0; i
< cycles
; i
++)
6162 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6169 clear_resource_table (resource_table
*rt
)
6172 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6173 for (j
= 0; j
< rt
->num_units
; j
++)
6174 rt
->units
[i
][j
] = 0;
6178 /* We never shrink it, just fake it into thinking so. */
6181 resize_resource_table (resource_table
*rt
, int cycles
)
6185 rt
->cycles
= cycles
;
6186 if (cycles
<= rt
->allocated_cycles
)
6189 old_cycles
= rt
->allocated_cycles
;
6190 rt
->allocated_cycles
= cycles
;
6192 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6193 for (i
= 0; i
< old_cycles
; i
++)
6194 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6195 for (i
= old_cycles
; i
< cycles
; i
++)
6196 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6201 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6204 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6206 for (i
= 0; i
< uses
; i
++)
6208 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6209 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6210 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6211 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6212 if (copies_in_use
>= copies
)
6220 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6223 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6225 for (i
= 0; i
< uses
; i
++)
6227 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6228 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6229 /* Note that this allows resources to be oversubscribed. That's
6230 essential to the way the optional scheduler works.
6231 resources_available reports when a resource is over-subscribed,
6232 so it's easy to tell. */
6233 rt
->units
[stage
+ cycle
][unit
]++;
6239 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6242 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6244 for (i
= 0; i
< uses
; i
++)
6246 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6247 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6248 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6249 rt
->units
[stage
+ cycle
][unit
]--;
6254 /* Wrapper functions make parameterized resource reservation
6258 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6260 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6266 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6268 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6273 /* Note that this function does not check issue constraints, but
6274 solely whether the hardware is available to execute the given
6275 instructions together. It also doesn't check if the tinsns
6276 write the same state, or access the same tieports. That is
6277 checked by check_t1_t2_reads_and_writes. */
6280 resources_conflict (vliw_insn
*vinsn
)
6283 static resource_table
*rt
= NULL
;
6285 /* This is the most common case by far. Optimize it. */
6286 if (vinsn
->num_slots
== 1)
6291 xtensa_isa isa
= xtensa_default_isa
;
6292 rt
= new_resource_table
6293 (isa
, xtensa_num_pipe_stages
,
6294 xtensa_isa_num_funcUnits (isa
),
6295 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6296 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6297 opcode_funcUnit_use_unit
,
6298 opcode_funcUnit_use_stage
);
6301 clear_resource_table (rt
);
6303 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6305 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6307 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6314 /* finish_vinsn, emit_single_op and helper functions. */
6316 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6317 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6318 static void xg_assemble_vliw_tokens (vliw_insn
*);
6321 /* We have reached the end of a bundle; emit into the frag. */
6324 finish_vinsn (vliw_insn
*vinsn
)
6330 if (find_vinsn_conflicts (vinsn
))
6332 xg_clear_vinsn (vinsn
);
6336 /* First, find a format that works. */
6337 if (vinsn
->format
== XTENSA_UNDEFINED
)
6338 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6340 slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6342 && produce_flix
== FLIX_NONE
)
6344 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6345 xg_clear_vinsn (vinsn
);
6349 if (vinsn
->format
== XTENSA_UNDEFINED
)
6351 as_bad (_("couldn't find a valid instruction format"));
6352 fprintf (stderr
, _(" ops were: "));
6353 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6354 fprintf (stderr
, _(" %s;"),
6355 xtensa_opcode_name (xtensa_default_isa
,
6356 vinsn
->slots
[i
].opcode
));
6357 fprintf (stderr
, _("\n"));
6358 xg_clear_vinsn (vinsn
);
6362 if (vinsn
->num_slots
!= slots
)
6364 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6365 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6366 slots
, vinsn
->num_slots
);
6367 xg_clear_vinsn (vinsn
);
6371 if (resources_conflict (vinsn
))
6373 as_bad (_("illegal resource usage in bundle"));
6374 fprintf (stderr
, " ops were: ");
6375 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6376 fprintf (stderr
, " %s;",
6377 xtensa_opcode_name (xtensa_default_isa
,
6378 vinsn
->slots
[i
].opcode
));
6379 fprintf (stderr
, "\n");
6380 xg_clear_vinsn (vinsn
);
6384 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6386 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6388 symbolS
*lit_sym
= NULL
;
6390 bfd_boolean e
= FALSE
;
6391 bfd_boolean saved_density
= density_supported
;
6393 /* We don't want to narrow ops inside multi-slot bundles. */
6394 if (vinsn
->num_slots
> 1)
6395 density_supported
= FALSE
;
6397 istack_init (&slotstack
);
6398 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6400 vinsn
->slots
[i
].opcode
=
6401 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6403 vinsn
->slots
[i
].ntok
= 0;
6406 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6412 density_supported
= saved_density
;
6416 xg_clear_vinsn (vinsn
);
6420 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6422 TInsn
*insn
= &slotstack
.insn
[j
];
6423 if (insn
->insn_type
== ITYPE_LITERAL
)
6425 gas_assert (lit_sym
== NULL
);
6426 lit_sym
= xg_assemble_literal (insn
);
6430 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6432 xg_resolve_literals (insn
, lit_sym
);
6433 if (j
!= slotstack
.ninsn
- 1)
6434 emit_single_op (insn
);
6438 if (vinsn
->num_slots
> 1)
6440 if (opcode_fits_format_slot
6441 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6444 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6448 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6449 if (vinsn
->format
== XTENSA_UNDEFINED
)
6450 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6452 vinsn
->slots
[i
].opcode
6453 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6456 vinsn
->slots
[i
].ntok
= 0;
6461 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6462 vinsn
->format
= XTENSA_UNDEFINED
;
6467 /* Now check resource conflicts on the modified bundle. */
6468 if (resources_conflict (vinsn
))
6470 as_bad (_("illegal resource usage in bundle"));
6471 fprintf (stderr
, " ops were: ");
6472 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6473 fprintf (stderr
, " %s;",
6474 xtensa_opcode_name (xtensa_default_isa
,
6475 vinsn
->slots
[i
].opcode
));
6476 fprintf (stderr
, "\n");
6477 xg_clear_vinsn (vinsn
);
6481 /* First, find a format that works. */
6482 if (vinsn
->format
== XTENSA_UNDEFINED
)
6483 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6485 xg_assemble_vliw_tokens (vinsn
);
6487 xg_clear_vinsn (vinsn
);
6489 xtensa_check_frag_count ();
6493 /* Given an vliw instruction, what conflicts are there in register
6494 usage and in writes to states and queues?
6496 This function does two things:
6497 1. Reports an error when a vinsn contains illegal combinations
6498 of writes to registers states or queues.
6499 2. Marks individual tinsns as not relaxable if the combination
6500 contains antidependencies.
6502 Job 2 handles things like swap semantics in instructions that need
6503 to be relaxed. For example,
6507 normally would be relaxed to
6512 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6514 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6516 then we can't relax it into
6519 { add a0, a1, a0 ; add a2, a0, a4 ; }
6521 because the value of a0 is trashed before the second add can read it. */
6523 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6526 find_vinsn_conflicts (vliw_insn
*vinsn
)
6530 xtensa_isa isa
= xtensa_default_isa
;
6532 gas_assert (!past_xtensa_end
);
6534 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6536 TInsn
*op1
= &vinsn
->slots
[i
];
6537 if (op1
->is_specific_opcode
)
6538 op1
->keep_wide
= TRUE
;
6540 op1
->keep_wide
= FALSE
;
6543 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6545 TInsn
*op1
= &vinsn
->slots
[i
];
6547 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6550 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6554 TInsn
*op2
= &vinsn
->slots
[j
];
6555 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6556 switch (conflict_type
)
6559 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6560 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6561 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6564 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6565 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6566 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6569 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6570 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6571 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6574 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6575 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6576 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6579 /* Everything is OK. */
6582 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6583 || conflict_type
== 'a');
6590 as_bad (_("multiple branches or jumps in the same bundle"));
6598 /* Check how the state used by t1 and t2 relate.
6601 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6602 case B: no relationship between what is read and written (both could
6603 read the same reg though)
6604 case C: t1 writes a register t2 writes (a register conflict within a
6606 case D: t1 writes a state that t2 also writes
6607 case E: t1 writes a tie queue that t2 also writes
6608 case F: two volatile queue accesses
6612 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6614 xtensa_isa isa
= xtensa_default_isa
;
6615 xtensa_regfile t1_regfile
, t2_regfile
;
6617 int t1_base_reg
, t1_last_reg
;
6618 int t2_base_reg
, t2_last_reg
;
6619 char t1_inout
, t2_inout
;
6621 char conflict
= 'b';
6626 bfd_boolean t1_volatile
= FALSE
;
6627 bfd_boolean t2_volatile
= FALSE
;
6629 /* Check registers. */
6630 for (j
= 0; j
< t2
->ntok
; j
++)
6632 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6635 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6636 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6637 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6639 for (i
= 0; i
< t1
->ntok
; i
++)
6641 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6644 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6646 if (t1_regfile
!= t2_regfile
)
6649 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6650 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6652 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6653 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6655 if (t1_inout
== 'm' || t1_inout
== 'o'
6656 || t2_inout
== 'm' || t2_inout
== 'o')
6663 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6664 t1_last_reg
= (t1_base_reg
6665 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6667 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6669 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6671 if (t1_reg
!= t2_reg
)
6674 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6680 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6686 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6694 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6695 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6696 for (j
= 0; j
< t2_states
; j
++)
6698 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6699 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6700 for (i
= 0; i
< t1_states
; i
++)
6702 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6703 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6704 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6707 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6713 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6719 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6724 /* Check tieports. */
6725 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6726 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6727 for (j
= 0; j
< t2_interfaces
; j
++)
6729 xtensa_interface t2_int
6730 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6731 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6733 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6734 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6737 for (i
= 0; i
< t1_interfaces
; i
++)
6739 xtensa_interface t1_int
6740 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6741 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6743 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6744 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6747 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6750 if (t1_int
!= t2_int
)
6753 if (t2_inout
== 'i' && t1_inout
== 'o')
6759 if (t1_inout
== 'i' && t2_inout
== 'o')
6765 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6774 static xtensa_format
6775 xg_find_narrowest_format (vliw_insn
*vinsn
)
6777 /* Right now we assume that the ops within the vinsn are properly
6778 ordered for the slots that the programmer wanted them in. In
6779 other words, we don't rearrange the ops in hopes of finding a
6780 better format. The scheduler handles that. */
6782 xtensa_isa isa
= xtensa_default_isa
;
6783 xtensa_format format
;
6784 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6786 if (vinsn
->num_slots
== 1)
6787 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6789 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6792 xg_copy_vinsn (&v_copy
, vinsn
);
6793 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6797 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6799 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6801 v_copy
.slots
[slot
].opcode
=
6802 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6803 v_copy
.slots
[slot
].ntok
= 0;
6806 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6809 else if (v_copy
.num_slots
> 1)
6812 /* Try the widened version. */
6813 if (!v_copy
.slots
[slot
].keep_wide
6814 && !v_copy
.slots
[slot
].is_specific_opcode
6815 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6817 && opcode_fits_format_slot (widened
.opcode
,
6820 v_copy
.slots
[slot
] = widened
;
6825 if (fit
== v_copy
.num_slots
)
6827 xg_copy_vinsn (vinsn
, &v_copy
);
6828 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6829 vinsn
->format
= format
;
6835 if (format
== xtensa_isa_num_formats (isa
))
6836 return XTENSA_UNDEFINED
;
6842 /* Return the additional space needed in a frag
6843 for possible relaxations of any ops in a VLIW insn.
6844 Also fill out the relaxations that might be required of
6845 each tinsn in the vinsn. */
6848 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6850 bfd_boolean finish_frag
= FALSE
;
6851 int extra_space
= 0;
6854 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6856 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6857 if (!tinsn_has_symbolic_operands (tinsn
))
6859 /* A narrow instruction could be widened later to help
6860 alignment issues. */
6861 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6862 && !tinsn
->is_specific_opcode
6863 && vinsn
->num_slots
== 1)
6865 /* Difference in bytes between narrow and wide insns... */
6867 tinsn
->subtype
= RELAX_NARROW
;
6872 if (workaround_b_j_loop_end
6873 && tinsn
->opcode
== xtensa_jx_opcode
6874 && use_transform ())
6876 /* Add 2 of these. */
6877 extra_space
+= 3; /* for the nop size */
6878 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6881 /* Need to assemble it with space for the relocation. */
6882 if (xg_is_relaxable_insn (tinsn
, 0)
6883 && !tinsn
->is_specific_opcode
)
6885 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6886 int max_literal_size
=
6887 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6889 tinsn
->literal_space
= max_literal_size
;
6891 tinsn
->subtype
= RELAX_IMMED
;
6892 extra_space
+= max_size
;
6896 /* A fix record will be added for this instruction prior
6897 to relaxation, so make it end the frag. */
6902 *pfinish_frag
= finish_frag
;
6908 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6910 xtensa_isa isa
= xtensa_default_isa
;
6911 int slot
, chosen_slot
;
6913 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6914 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6915 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6917 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6918 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6920 if (slot
== chosen_slot
)
6921 vinsn
->slots
[slot
] = *tinsn
;
6924 vinsn
->slots
[slot
].opcode
=
6925 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6926 vinsn
->slots
[slot
].ntok
= 0;
6927 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6934 emit_single_op (TInsn
*orig_insn
)
6937 IStack istack
; /* put instructions into here */
6938 symbolS
*lit_sym
= NULL
;
6939 symbolS
*label_sym
= NULL
;
6941 istack_init (&istack
);
6943 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6944 Because the scheduling and bundling characteristics of movi and
6945 l32r or const16 are so different, we can do much better if we relax
6946 it prior to scheduling and bundling, rather than after. */
6947 if ((orig_insn
->opcode
== xtensa_movi_opcode
6948 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6949 && !cur_vinsn
.inside_bundle
6950 && (orig_insn
->tok
[1].X_op
== O_symbol
6951 || orig_insn
->tok
[1].X_op
== O_pltrel
6952 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6953 || orig_insn
->tok
[1].X_op
== O_tlsarg
6954 || orig_insn
->tok
[1].X_op
== O_tpoff
6955 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6956 && !orig_insn
->is_specific_opcode
&& use_transform ())
6957 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6959 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6962 for (i
= 0; i
< istack
.ninsn
; i
++)
6964 TInsn
*insn
= &istack
.insn
[i
];
6965 switch (insn
->insn_type
)
6968 gas_assert (lit_sym
== NULL
);
6969 lit_sym
= xg_assemble_literal (insn
);
6973 static int relaxed_sym_idx
= 0;
6974 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6975 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6977 gas_assert (label_sym
== NULL
);
6978 label_sym
= symbol_find_or_make (label
);
6979 gas_assert (label_sym
);
6987 xg_resolve_literals (insn
, lit_sym
);
6989 xg_resolve_labels (insn
, label_sym
);
6991 bundle_tinsn (insn
, &v
);
7006 total_frag_text_expansion (fragS
*fragP
)
7009 int total_expansion
= 0;
7011 for (slot
= 0; slot
< config_max_slots
; slot
++)
7012 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7014 return total_expansion
;
7018 /* Emit a vliw instruction to the current fragment. */
7021 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7023 bfd_boolean finish_frag
;
7024 bfd_boolean is_jump
= FALSE
;
7025 bfd_boolean is_branch
= FALSE
;
7026 xtensa_isa isa
= xtensa_default_isa
;
7031 struct dwarf2_line_info debug_line
;
7032 bfd_boolean loc_directive_seen
= FALSE
;
7035 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7037 if (generating_literals
)
7039 static int reported
= 0;
7041 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7042 _("cannot assemble into a literal fragment"));
7049 if (frag_now_fix () != 0
7050 && (! frag_now
->tc_frag_data
.is_insn
7051 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7052 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7053 || (directive_state
[directive_longcalls
]
7054 != frag_now
->tc_frag_data
.use_longcalls
)
7055 || (directive_state
[directive_absolute_literals
]
7056 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7058 frag_wane (frag_now
);
7060 xtensa_set_frag_assembly_state (frag_now
);
7063 if (workaround_a0_b_retw
7064 && vinsn
->num_slots
== 1
7065 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7066 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7067 && use_transform ())
7069 has_a0_b_retw
= TRUE
;
7071 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7072 After the first assembly pass we will check all of them and
7073 add a nop if needed. */
7074 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7075 frag_var (rs_machine_dependent
, 4, 4,
7076 RELAX_ADD_NOP_IF_A0_B_RETW
,
7077 frag_now
->fr_symbol
,
7078 frag_now
->fr_offset
,
7080 xtensa_set_frag_assembly_state (frag_now
);
7081 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7082 frag_var (rs_machine_dependent
, 4, 4,
7083 RELAX_ADD_NOP_IF_A0_B_RETW
,
7084 frag_now
->fr_symbol
,
7085 frag_now
->fr_offset
,
7087 xtensa_set_frag_assembly_state (frag_now
);
7090 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7092 tinsn
= &vinsn
->slots
[slot
];
7094 /* See if the instruction implies an aligned section. */
7095 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7096 record_alignment (now_seg
, 2);
7098 /* Determine the best line number for debug info. */
7099 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7100 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7101 || tinsn
->debug_line
.line
< debug_line
.line
7102 || tinsn
->debug_line
.column
< debug_line
.column
))
7103 debug_line
= tinsn
->debug_line
;
7104 if (tinsn
->loc_directive_seen
)
7105 loc_directive_seen
= TRUE
;
7108 /* Special cases for instructions that force an alignment... */
7109 /* None of these opcodes are bundle-able. */
7110 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7114 /* Remember the symbol that marks the end of the loop in the frag
7115 that marks the start of the loop. This way we can easily find
7116 the end of the loop at the beginning, without adding special code
7117 to mark the loop instructions themselves. */
7118 symbolS
*target_sym
= NULL
;
7119 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7120 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7122 xtensa_set_frag_assembly_state (frag_now
);
7123 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7125 max_fill
= get_text_align_max_fill_size
7126 (get_text_align_power (xtensa_fetch_width
),
7127 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7129 if (use_transform ())
7130 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7131 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7133 frag_var (rs_machine_dependent
, 0, 0,
7134 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7135 xtensa_set_frag_assembly_state (frag_now
);
7138 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7139 && !vinsn
->slots
[0].is_specific_opcode
)
7141 xtensa_mark_literal_pool_location ();
7142 xtensa_move_labels (frag_now
, 0);
7143 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7146 if (vinsn
->num_slots
== 1)
7148 if (workaround_a0_b_retw
&& use_transform ())
7149 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7150 is_register_writer (&vinsn
->slots
[0], "a", 0));
7152 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7153 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7156 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7158 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7160 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7162 /* vinsn_to_insnbuf will produce the error. */
7163 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7165 f
= frag_more (insn_size
+ extra_space
);
7166 xtensa_set_frag_assembly_state (frag_now
);
7167 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7170 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7171 if (vinsn
->format
== XTENSA_UNDEFINED
)
7174 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7176 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7177 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7180 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7182 tinsn
= &vinsn
->slots
[slot
];
7183 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7184 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7185 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7186 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7187 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7189 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7190 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7192 if (tinsn
->literal_space
!= 0)
7193 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7194 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7196 if (tinsn
->subtype
== RELAX_NARROW
)
7197 gas_assert (vinsn
->num_slots
== 1);
7198 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7200 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7203 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7204 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7208 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7209 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7213 frag_variant (rs_machine_dependent
,
7214 extra_space
, extra_space
, RELAX_SLOTS
,
7215 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7216 xtensa_set_frag_assembly_state (frag_now
);
7219 /* Special cases for loops:
7220 close_loop_end should be inserted AFTER short_loop.
7221 Make sure that CLOSE loops are processed BEFORE short_loops
7222 when converting them. */
7224 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7225 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7226 && !vinsn
->slots
[0].is_specific_opcode
)
7228 if (workaround_short_loop
&& use_transform ())
7230 maybe_has_short_loop
= TRUE
;
7231 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7232 frag_var (rs_machine_dependent
, 4, 4,
7233 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7234 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7235 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7236 frag_var (rs_machine_dependent
, 4, 4,
7237 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7238 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7241 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7242 loop at least 12 bytes away from another loop's end. */
7243 if (workaround_close_loop_end
&& use_transform ())
7245 maybe_has_close_loop_end
= TRUE
;
7246 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7247 frag_var (rs_machine_dependent
, 12, 12,
7248 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7249 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7253 if (use_transform ())
7257 gas_assert (finish_frag
);
7258 frag_var (rs_machine_dependent
,
7259 xtensa_fetch_width
, xtensa_fetch_width
,
7261 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7262 xtensa_set_frag_assembly_state (frag_now
);
7263 xtensa_maybe_create_trampoline_frag ();
7264 /* Always create one here. */
7265 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7267 else if (is_branch
&& do_align_targets ())
7269 gas_assert (finish_frag
);
7270 frag_var (rs_machine_dependent
,
7271 xtensa_fetch_width
, xtensa_fetch_width
,
7272 RELAX_MAYBE_UNREACHABLE
,
7273 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7274 xtensa_set_frag_assembly_state (frag_now
);
7275 frag_var (rs_machine_dependent
,
7277 RELAX_MAYBE_DESIRE_ALIGN
,
7278 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7279 xtensa_set_frag_assembly_state (frag_now
);
7283 /* Now, if the original opcode was a call... */
7284 if (do_align_targets ()
7285 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7287 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7288 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7289 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7290 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7291 xtensa_set_frag_assembly_state (frag_now
);
7294 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7296 frag_wane (frag_now
);
7298 xtensa_set_frag_assembly_state (frag_now
);
7303 /* xtensa_end and helper functions. */
7305 static void xtensa_cleanup_align_frags (void);
7306 static void xtensa_fix_target_frags (void);
7307 static void xtensa_mark_narrow_branches (void);
7308 static void xtensa_mark_zcl_first_insns (void);
7309 static void xtensa_mark_difference_of_two_symbols (void);
7310 static void xtensa_fix_a0_b_retw_frags (void);
7311 static void xtensa_fix_b_j_loop_end_frags (void);
7312 static void xtensa_fix_close_loop_end_frags (void);
7313 static void xtensa_fix_short_loop_frags (void);
7314 static void xtensa_sanity_check (void);
7315 static void xtensa_add_config_info (void);
7320 directive_balance ();
7321 xtensa_flush_pending_output ();
7323 past_xtensa_end
= TRUE
;
7325 xtensa_move_literals ();
7327 xtensa_reorder_segments ();
7328 xtensa_cleanup_align_frags ();
7329 xtensa_fix_target_frags ();
7330 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7331 xtensa_fix_a0_b_retw_frags ();
7332 if (workaround_b_j_loop_end
)
7333 xtensa_fix_b_j_loop_end_frags ();
7335 /* "close_loop_end" should be processed BEFORE "short_loop". */
7336 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7337 xtensa_fix_close_loop_end_frags ();
7339 if (workaround_short_loop
&& maybe_has_short_loop
)
7340 xtensa_fix_short_loop_frags ();
7342 xtensa_mark_narrow_branches ();
7343 xtensa_mark_zcl_first_insns ();
7345 xtensa_sanity_check ();
7347 xtensa_add_config_info ();
7349 xtensa_check_frag_count ();
7353 struct trampoline_frag
7355 struct trampoline_frag
*next
;
7356 bfd_boolean needs_jump_around
;
7361 struct trampoline_seg
7363 struct trampoline_seg
*next
;
7365 struct trampoline_frag trampoline_list
;
7368 static struct trampoline_seg trampoline_seg_list
;
7369 #define J_RANGE (128 * 1024)
7371 static int unreachable_count
= 0;
7375 xtensa_maybe_create_trampoline_frag (void)
7377 if (!use_trampolines
)
7380 /* We create an area for possible trampolines every 10 unreachable frags.
7381 These are preferred over the ones not preceded by an unreachable frag,
7382 because we don't have to jump around them. This function is called after
7383 each RELAX_UNREACHABLE frag is created. */
7385 if (++unreachable_count
> 10)
7387 xtensa_create_trampoline_frag (FALSE
);
7388 clear_frag_count ();
7389 unreachable_count
= 0;
7394 xtensa_check_frag_count (void)
7396 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7399 /* We create an area for possible trampolines every 8000 frags or so. This
7400 is an estimate based on the max range of a "j" insn (+/-128K) divided
7401 by a typical frag byte count (16), minus a few for safety. This function
7402 is called after each source line is processed. */
7404 if (get_frag_count () > 8000)
7406 xtensa_create_trampoline_frag (TRUE
);
7407 clear_frag_count ();
7408 unreachable_count
= 0;
7411 /* We create an area for a possible literal pool every N (default 5000)
7413 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7416 static xtensa_insnbuf trampoline_buf
= NULL
;
7417 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7419 static xtensa_insnbuf litpool_buf
= NULL
;
7420 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7422 #define TRAMPOLINE_FRAG_SIZE 3000
7425 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7427 /* Emit a frag where we can place intermediate jump instructions,
7428 in case we need to jump farther than 128K bytes.
7429 Each jump instruction takes three bytes.
7430 We allocate enough for 1000 trampolines in each frag.
7431 If that's not enough, oh well. */
7433 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7434 struct trampoline_frag
*tf
;
7437 int size
= TRAMPOLINE_FRAG_SIZE
;
7439 for ( ; ts
; ts
= ts
->next
)
7441 if (ts
->seg
== now_seg
)
7447 ts
= XCNEW(struct trampoline_seg
);
7448 ts
->next
= trampoline_seg_list
.next
;
7449 trampoline_seg_list
.next
= ts
;
7453 frag_wane (frag_now
);
7455 xtensa_set_frag_assembly_state (frag_now
);
7456 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7457 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7458 if (trampoline_buf
== NULL
)
7460 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7461 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7463 tf
= XNEW (struct trampoline_frag
);
7464 tf
->next
= ts
->trampoline_list
.next
;
7465 ts
->trampoline_list
.next
= tf
;
7466 tf
->needs_jump_around
= needs_jump_around
;
7472 static struct trampoline_seg
*
7473 find_trampoline_seg (asection
*seg
)
7475 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7477 for ( ; ts
; ts
= ts
->next
)
7487 void dump_trampolines (void);
7490 dump_trampolines (void)
7492 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7494 for ( ; ts
; ts
= ts
->next
)
7496 asection
*seg
= ts
->seg
;
7500 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7501 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7502 for ( ; tf
; tf
= tf
->next
)
7504 if (tf
->fragP
== NULL
)
7506 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7507 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7508 tf
->needs_jump_around
? "T" : "F");
7513 static void dump_litpools (void) __attribute__ ((unused
));
7516 dump_litpools (void)
7518 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7519 struct litpool_frag
*lpf
;
7521 for ( ; lps
; lps
= lps
->next
)
7523 printf("litpool seg %s\n", lps
->seg
->name
);
7524 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7526 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7528 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7530 if (litfrag
->fr_fix
== 4)
7532 litfrag
= litfrag
->fr_next
;
7534 printf(" %ld <%d:%d> (%d) [%d]: ",
7535 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7536 lpf
->fragP
->fr_line
, count
);
7537 //dump_frag(lpf->fragP);
7543 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7544 bfd_boolean only_if_needed
)
7546 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7548 struct litpool_frag
*lpf
;
7549 bfd_boolean needed
= FALSE
;
7551 if (use_literal_section
|| !auto_litpools
)
7554 for ( ; lps
; lps
= lps
->next
)
7556 if (lps
->seg
== now_seg
)
7562 lps
= XCNEW (struct litpool_seg
);
7563 lps
->next
= litpool_seg_list
.next
;
7564 litpool_seg_list
.next
= lps
;
7566 lps
->frag_list
.next
= &lps
->frag_list
;
7567 lps
->frag_list
.prev
= &lps
->frag_list
;
7568 /* Put candidate literal pool at the beginning of every section,
7569 so that even when section starts with literal load there's a
7570 literal pool available. */
7571 lps
->frag_count
= auto_litpool_limit
;
7580 if (past_xtensa_end
|| !use_transform() ||
7581 frag_now
->tc_frag_data
.is_no_transform
)
7585 if (auto_litpool_limit
<= 0)
7587 /* Don't create a litpool based only on frag count. */
7590 else if (lps
->frag_count
> auto_litpool_limit
)
7607 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7608 /* Create a potential site for a literal pool. */
7609 frag_wane (frag_now
);
7611 xtensa_set_frag_assembly_state (frag_now
);
7613 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7614 fragP
->tc_frag_data
.literal_frag
= fragP
;
7615 frag_var (rs_machine_dependent
, size
, size
,
7617 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7618 RELAX_LITERAL_POOL_BEGIN
,
7620 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7621 frag_variant (rs_machine_dependent
, 0, 0,
7622 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7623 xtensa_set_frag_assembly_state (frag_now
);
7627 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7628 just record it here. */
7632 lpf
= XNEW (struct litpool_frag
);
7633 /* Insert at tail of circular list. */
7635 lps
->frag_list
.prev
->next
= lpf
;
7636 lpf
->next
= &lps
->frag_list
;
7637 lpf
->prev
= lps
->frag_list
.prev
;
7638 lps
->frag_list
.prev
= lpf
;
7640 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7641 lpf
->original_priority
= lpf
->priority
;
7643 lps
->frag_count
= 0;
7647 xtensa_cleanup_align_frags (void)
7652 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7653 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7656 /* Walk over all of the fragments in a subsection. */
7657 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7659 if ((fragP
->fr_type
== rs_align
7660 || fragP
->fr_type
== rs_align_code
7661 || (fragP
->fr_type
== rs_machine_dependent
7662 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7663 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7664 && fragP
->fr_fix
== 0)
7666 fragS
*next
= fragP
->fr_next
;
7669 && next
->fr_fix
== 0
7670 && next
->fr_type
== rs_machine_dependent
7671 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7674 next
= next
->fr_next
;
7677 /* If we don't widen branch targets, then they
7678 will be easier to align. */
7679 if (fragP
->tc_frag_data
.is_branch_target
7680 && fragP
->fr_opcode
== fragP
->fr_literal
7681 && fragP
->fr_type
== rs_machine_dependent
7682 && fragP
->fr_subtype
== RELAX_SLOTS
7683 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7685 if (fragP
->fr_type
== rs_machine_dependent
7686 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7687 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7693 /* Re-process all of the fragments looking to convert all of the
7694 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7695 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7696 Otherwise, convert to a .fill 0. */
7699 xtensa_fix_target_frags (void)
7704 /* When this routine is called, all of the subsections are still intact
7705 so we walk over subsections instead of sections. */
7706 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7707 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7711 /* Walk over all of the fragments in a subsection. */
7712 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7714 if (fragP
->fr_type
== rs_machine_dependent
7715 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7717 if (next_frag_is_branch_target (fragP
))
7718 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7727 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7730 xtensa_mark_narrow_branches (void)
7735 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7736 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7739 /* Walk over all of the fragments in a subsection. */
7740 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7742 if (fragP
->fr_type
== rs_machine_dependent
7743 && fragP
->fr_subtype
== RELAX_SLOTS
7744 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7748 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7749 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7751 if (vinsn
.num_slots
== 1
7752 && xtensa_opcode_is_branch (xtensa_default_isa
,
7753 vinsn
.slots
[0].opcode
) == 1
7754 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7755 && is_narrow_branch_guaranteed_in_range (fragP
,
7758 fragP
->fr_subtype
= RELAX_SLOTS
;
7759 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7760 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7768 /* A branch is typically widened only when its target is out of
7769 range. However, we would like to widen them to align a subsequent
7770 branch target when possible.
7772 Because the branch relaxation code is so convoluted, the optimal solution
7773 (combining the two cases) is difficult to get right in all circumstances.
7774 We therefore go with an "almost as good" solution, where we only
7775 use for alignment narrow branches that definitely will not expand to a
7776 jump and a branch. These functions find and mark these cases. */
7778 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7779 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7780 We start counting beginning with the frag after the 2-byte branch, so the
7781 maximum offset is (4 - 2) + 63 = 65. */
7782 #define MAX_IMMED6 65
7784 static offsetT
unrelaxed_frag_max_size (fragS
*);
7787 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7789 const expressionS
*exp
= &tinsn
->tok
[1];
7790 symbolS
*symbolP
= exp
->X_add_symbol
;
7791 offsetT max_distance
= exp
->X_add_number
;
7794 if (exp
->X_op
!= O_symbol
)
7797 target_frag
= symbol_get_frag (symbolP
);
7799 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7800 if (is_branch_jmp_to_next (tinsn
, fragP
))
7803 /* The branch doesn't branch over it's own frag,
7804 but over the subsequent ones. */
7805 fragP
= fragP
->fr_next
;
7806 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7808 max_distance
+= unrelaxed_frag_max_size (fragP
);
7809 fragP
= fragP
->fr_next
;
7811 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7818 xtensa_mark_zcl_first_insns (void)
7823 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7824 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7827 /* Walk over all of the fragments in a subsection. */
7828 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7830 if (fragP
->fr_type
== rs_machine_dependent
7831 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7832 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7834 /* Find the loop frag. */
7835 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7836 /* Find the first insn frag. */
7837 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7839 /* Handle a corner case that comes up in hardware
7840 diagnostics. The original assembly looks like this:
7843 <empty_frag>--not found by next_non_empty_frag
7846 Depending on the start address, the assembler may or
7847 may not change it to look something like this:
7850 nop--frag isn't empty anymore
7853 So set up to check the alignment of the nop if it
7855 while (loop_frag
!= targ_frag
)
7857 if (loop_frag
->fr_type
== rs_machine_dependent
7858 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7859 || loop_frag
->fr_subtype
7860 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7861 targ_frag
= loop_frag
;
7863 loop_frag
= loop_frag
->fr_next
;
7866 /* Of course, sometimes (mostly for toy test cases) a
7867 zero-cost loop instruction is the last in a section. */
7870 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7871 /* Do not widen a frag that is the first instruction of a
7872 zero-cost loop. It makes that loop harder to align. */
7873 if (targ_frag
->fr_type
== rs_machine_dependent
7874 && targ_frag
->fr_subtype
== RELAX_SLOTS
7875 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7878 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7879 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7882 frag_wane (targ_frag
);
7883 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7887 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7895 /* When a difference-of-symbols expression is encoded as a uleb128 or
7896 sleb128 value, the linker is unable to adjust that value to account for
7897 link-time relaxation. Mark all the code between such symbols so that
7898 its size cannot be changed by linker relaxation. */
7901 xtensa_mark_difference_of_two_symbols (void)
7905 for (expr_sym
= expr_symbols
; expr_sym
;
7906 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7908 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7910 if (exp
->X_op
== O_subtract
)
7912 symbolS
*left
= exp
->X_add_symbol
;
7913 symbolS
*right
= exp
->X_op_symbol
;
7915 /* Difference of two symbols not in the same section
7916 are handled with relocations in the linker. */
7917 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7923 if (symbol_get_frag (left
)->fr_address
7924 <= symbol_get_frag (right
)->fr_address
)
7926 start
= symbol_get_frag (left
);
7927 end
= symbol_get_frag (right
);
7931 start
= symbol_get_frag (right
);
7932 end
= symbol_get_frag (left
);
7935 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7936 walk
= start
->tc_frag_data
.no_transform_end
;
7941 walk
->tc_frag_data
.is_no_transform
= 1;
7942 walk
= walk
->fr_next
;
7944 while (walk
&& walk
->fr_address
< end
->fr_address
);
7946 start
->tc_frag_data
.no_transform_end
= walk
;
7953 /* Re-process all of the fragments looking to convert all of the
7954 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7955 conditional branch or a retw/retw.n, convert this frag to one that
7956 will generate a NOP. In any case close it off with a .fill 0. */
7958 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7961 xtensa_fix_a0_b_retw_frags (void)
7966 /* When this routine is called, all of the subsections are still intact
7967 so we walk over subsections instead of sections. */
7968 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7969 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7973 /* Walk over all of the fragments in a subsection. */
7974 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7976 if (fragP
->fr_type
== rs_machine_dependent
7977 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7979 if (next_instrs_are_b_retw (fragP
))
7981 if (fragP
->tc_frag_data
.is_no_transform
)
7982 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7984 relax_frag_add_nop (fragP
);
7994 next_instrs_are_b_retw (fragS
*fragP
)
7996 xtensa_opcode opcode
;
7998 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7999 static xtensa_insnbuf insnbuf
= NULL
;
8000 static xtensa_insnbuf slotbuf
= NULL
;
8001 xtensa_isa isa
= xtensa_default_isa
;
8004 bfd_boolean branch_seen
= FALSE
;
8008 insnbuf
= xtensa_insnbuf_alloc (isa
);
8009 slotbuf
= xtensa_insnbuf_alloc (isa
);
8012 if (next_fragP
== NULL
)
8015 /* Check for the conditional branch. */
8016 xtensa_insnbuf_from_chars
8017 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8018 fmt
= xtensa_format_decode (isa
, insnbuf
);
8019 if (fmt
== XTENSA_UNDEFINED
)
8022 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8024 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8025 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8027 branch_seen
= (branch_seen
8028 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8034 offset
+= xtensa_format_length (isa
, fmt
);
8035 if (offset
== next_fragP
->fr_fix
)
8037 next_fragP
= next_non_empty_frag (next_fragP
);
8041 if (next_fragP
== NULL
)
8044 /* Check for the retw/retw.n. */
8045 xtensa_insnbuf_from_chars
8046 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8047 fmt
= xtensa_format_decode (isa
, insnbuf
);
8049 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8050 have no problems. */
8051 if (fmt
== XTENSA_UNDEFINED
8052 || xtensa_format_num_slots (isa
, fmt
) != 1)
8055 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8056 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8058 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8065 /* Re-process all of the fragments looking to convert all of the
8066 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8067 loop end label, convert this frag to one that will generate a NOP.
8068 In any case close it off with a .fill 0. */
8070 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8073 xtensa_fix_b_j_loop_end_frags (void)
8078 /* When this routine is called, all of the subsections are still intact
8079 so we walk over subsections instead of sections. */
8080 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8081 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8085 /* Walk over all of the fragments in a subsection. */
8086 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8088 if (fragP
->fr_type
== rs_machine_dependent
8089 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8091 if (next_instr_is_loop_end (fragP
))
8093 if (fragP
->tc_frag_data
.is_no_transform
)
8094 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8096 relax_frag_add_nop (fragP
);
8106 next_instr_is_loop_end (fragS
*fragP
)
8108 const fragS
*next_fragP
;
8110 if (next_frag_is_loop_target (fragP
))
8113 next_fragP
= next_non_empty_frag (fragP
);
8114 if (next_fragP
== NULL
)
8117 if (!next_frag_is_loop_target (next_fragP
))
8120 /* If the size is >= 3 then there is more than one instruction here.
8121 The hardware bug will not fire. */
8122 if (next_fragP
->fr_fix
> 3)
8129 /* Re-process all of the fragments looking to convert all of the
8130 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8131 not MY loop's loop end within 12 bytes, add enough nops here to
8132 make it at least 12 bytes away. In any case close it off with a
8135 static offsetT min_bytes_to_other_loop_end
8136 (fragS
*, fragS
*, offsetT
);
8139 xtensa_fix_close_loop_end_frags (void)
8144 /* When this routine is called, all of the subsections are still intact
8145 so we walk over subsections instead of sections. */
8146 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8147 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8151 fragS
*current_target
= NULL
;
8153 /* Walk over all of the fragments in a subsection. */
8154 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8156 if (fragP
->fr_type
== rs_machine_dependent
8157 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8158 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8159 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8162 && fragP
->fr_type
== rs_machine_dependent
8163 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8166 int bytes_added
= 0;
8168 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8169 /* Max out at 12. */
8170 min_bytes
= min_bytes_to_other_loop_end
8171 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8173 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8175 if (fragP
->tc_frag_data
.is_no_transform
)
8176 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8179 while (min_bytes
+ bytes_added
8180 < REQUIRED_LOOP_DIVIDING_BYTES
)
8184 if (fragP
->fr_var
< length
)
8185 as_fatal (_("fr_var %lu < length %d"),
8186 (long) fragP
->fr_var
, length
);
8189 assemble_nop (length
,
8190 fragP
->fr_literal
+ fragP
->fr_fix
);
8191 fragP
->fr_fix
+= length
;
8192 fragP
->fr_var
-= length
;
8194 bytes_added
+= length
;
8200 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8201 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8207 static offsetT
unrelaxed_frag_min_size (fragS
*);
8210 min_bytes_to_other_loop_end (fragS
*fragP
,
8211 fragS
*current_target
,
8215 fragS
*current_fragP
;
8217 for (current_fragP
= fragP
;
8219 current_fragP
= current_fragP
->fr_next
)
8221 if (current_fragP
->tc_frag_data
.is_loop_target
8222 && current_fragP
!= current_target
)
8225 offset
+= unrelaxed_frag_min_size (current_fragP
);
8227 if (offset
>= max_size
)
8235 unrelaxed_frag_min_size (fragS
*fragP
)
8237 offsetT size
= fragP
->fr_fix
;
8239 /* Add fill size. */
8240 if (fragP
->fr_type
== rs_fill
)
8241 size
+= fragP
->fr_offset
;
8248 unrelaxed_frag_max_size (fragS
*fragP
)
8250 offsetT size
= fragP
->fr_fix
;
8251 switch (fragP
->fr_type
)
8254 /* Empty frags created by the obstack allocation scheme
8255 end up with type 0. */
8260 size
+= fragP
->fr_offset
;
8268 /* No further adjustments needed. */
8270 case rs_machine_dependent
:
8271 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8272 size
+= fragP
->fr_var
;
8275 /* We had darn well better know how big it is. */
8284 /* Re-process all of the fragments looking to convert all
8285 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8288 1) the instruction size count to the loop end label
8289 is too short (<= 2 instructions),
8290 2) loop has a jump or branch in it
8293 1) workaround_all_short_loops is TRUE
8294 2) The generating loop was a 'loopgtz' or 'loopnez'
8295 3) the instruction size count to the loop end label is too short
8297 then convert this frag (and maybe the next one) to generate a NOP.
8298 In any case close it off with a .fill 0. */
8300 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8301 static bfd_boolean
branch_before_loop_end (fragS
*);
8304 xtensa_fix_short_loop_frags (void)
8309 /* When this routine is called, all of the subsections are still intact
8310 so we walk over subsections instead of sections. */
8311 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8312 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8315 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8317 /* Walk over all of the fragments in a subsection. */
8318 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8320 if (fragP
->fr_type
== rs_machine_dependent
8321 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8322 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8325 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8326 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8327 current_opcode
= t_insn
.opcode
;
8328 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8329 current_opcode
) == 1);
8332 if (fragP
->fr_type
== rs_machine_dependent
8333 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8335 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8336 && (branch_before_loop_end (fragP
->fr_next
)
8337 || (workaround_all_short_loops
8338 && current_opcode
!= XTENSA_UNDEFINED
8339 && current_opcode
!= xtensa_loop_opcode
)))
8341 if (fragP
->tc_frag_data
.is_no_transform
)
8342 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8344 relax_frag_add_nop (fragP
);
8353 static int unrelaxed_frag_min_insn_count (fragS
*);
8356 count_insns_to_loop_end (fragS
*base_fragP
,
8357 bfd_boolean count_relax_add
,
8360 fragS
*fragP
= NULL
;
8365 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8367 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8368 if (insn_count
>= max_count
)
8371 if (count_relax_add
)
8373 if (fragP
->fr_type
== rs_machine_dependent
8374 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8376 /* In order to add the appropriate number of
8377 NOPs, we count an instruction for downstream
8380 if (insn_count
>= max_count
)
8390 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8392 xtensa_isa isa
= xtensa_default_isa
;
8393 static xtensa_insnbuf insnbuf
= NULL
;
8397 if (!fragP
->tc_frag_data
.is_insn
)
8401 insnbuf
= xtensa_insnbuf_alloc (isa
);
8403 /* Decode the fixed instructions. */
8404 while (offset
< fragP
->fr_fix
)
8408 xtensa_insnbuf_from_chars
8409 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8410 fmt
= xtensa_format_decode (isa
, insnbuf
);
8412 if (fmt
== XTENSA_UNDEFINED
)
8414 as_fatal (_("undecodable instruction in instruction frag"));
8417 offset
+= xtensa_format_length (isa
, fmt
);
8425 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8428 branch_before_loop_end (fragS
*base_fragP
)
8432 for (fragP
= base_fragP
;
8433 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8434 fragP
= fragP
->fr_next
)
8436 if (unrelaxed_frag_has_b_j (fragP
))
8444 unrelaxed_frag_has_b_j (fragS
*fragP
)
8446 static xtensa_insnbuf insnbuf
= NULL
;
8447 xtensa_isa isa
= xtensa_default_isa
;
8450 if (!fragP
->tc_frag_data
.is_insn
)
8454 insnbuf
= xtensa_insnbuf_alloc (isa
);
8456 /* Decode the fixed instructions. */
8457 while (offset
< fragP
->fr_fix
)
8462 xtensa_insnbuf_from_chars
8463 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8464 fmt
= xtensa_format_decode (isa
, insnbuf
);
8465 if (fmt
== XTENSA_UNDEFINED
)
8468 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8470 xtensa_opcode opcode
=
8471 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8472 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8473 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8476 offset
+= xtensa_format_length (isa
, fmt
);
8482 /* Checks to be made after initial assembly but before relaxation. */
8484 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8485 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8488 xtensa_sanity_check (void)
8490 const char *file_name
;
8495 file_name
= as_where (&line
);
8496 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8497 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8501 /* Walk over all of the fragments in a subsection. */
8502 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8504 if (fragP
->fr_type
== rs_machine_dependent
8505 && fragP
->fr_subtype
== RELAX_SLOTS
8506 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8508 static xtensa_insnbuf insnbuf
= NULL
;
8511 if (fragP
->fr_opcode
!= NULL
)
8514 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8515 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8516 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8518 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8519 t_insn
.opcode
) == 1)
8521 if (is_empty_loop (&t_insn
, fragP
))
8523 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8524 as_bad (_("invalid empty loop"));
8526 if (!is_local_forward_loop (&t_insn
, fragP
))
8528 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8529 as_bad (_("loop target does not follow "
8530 "loop instruction in section"));
8537 new_logical_line (file_name
, line
);
8541 #define LOOP_IMMED_OPN 1
8543 /* Return TRUE if the loop target is the next non-zero fragment. */
8546 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8548 const expressionS
*exp
;
8552 if (insn
->insn_type
!= ITYPE_INSN
)
8555 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8558 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8561 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8563 if (exp
->X_op
!= O_symbol
)
8566 symbolP
= exp
->X_add_symbol
;
8570 if (symbol_get_frag (symbolP
) == NULL
)
8573 if (S_GET_VALUE (symbolP
) != 0)
8576 /* Walk through the zero-size fragments from this one. If we find
8577 the target fragment, then this is a zero-size loop. */
8579 for (next_fragP
= fragP
->fr_next
;
8581 next_fragP
= next_fragP
->fr_next
)
8583 if (next_fragP
== symbol_get_frag (symbolP
))
8585 if (next_fragP
->fr_fix
!= 0)
8593 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8595 const expressionS
*exp
;
8599 if (insn
->insn_type
!= ITYPE_INSN
)
8602 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8605 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8608 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8610 if (exp
->X_op
!= O_symbol
)
8613 symbolP
= exp
->X_add_symbol
;
8617 if (symbol_get_frag (symbolP
) == NULL
)
8620 /* Walk through fragments until we find the target.
8621 If we do not find the target, then this is an invalid loop. */
8623 for (next_fragP
= fragP
->fr_next
;
8625 next_fragP
= next_fragP
->fr_next
)
8627 if (next_fragP
== symbol_get_frag (symbolP
))
8635 #define XTINFO_NAME "Xtensa_Info"
8636 #define XTINFO_NAMESZ 12
8637 #define XTINFO_TYPE 1
8640 xtensa_add_config_info (void)
8646 info_sec
= subseg_new (".xtensa.info", 0);
8647 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8649 data
= XNEWVEC (char, 100);
8650 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8651 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8652 sz
= strlen (data
) + 1;
8654 /* Add enough null terminators to pad to a word boundary. */
8657 while ((sz
& 3) != 0);
8659 /* Follow the standard note section layout:
8660 First write the length of the name string. */
8662 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8664 /* Next comes the length of the "descriptor", i.e., the actual data. */
8666 md_number_to_chars (p
, (valueT
) sz
, 4);
8668 /* Write the note type. */
8670 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8672 /* Write the name field. */
8673 p
= frag_more (XTINFO_NAMESZ
);
8674 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8676 /* Finally, write the descriptor. */
8678 memcpy (p
, data
, sz
);
8684 /* Alignment Functions. */
8687 get_text_align_power (unsigned target_size
)
8689 if (target_size
<= 4)
8692 if (target_size
<= 8)
8695 if (target_size
<= 16)
8698 if (target_size
<= 32)
8701 if (target_size
<= 64)
8704 if (target_size
<= 128)
8707 if (target_size
<= 256)
8710 if (target_size
<= 512)
8713 if (target_size
<= 1024)
8722 get_text_align_max_fill_size (int align_pow
,
8723 bfd_boolean use_nops
,
8724 bfd_boolean use_no_density
)
8727 return (1 << align_pow
);
8729 return 3 * (1 << align_pow
);
8731 return 1 + (1 << align_pow
);
8735 /* Calculate the minimum bytes of fill needed at "address" to align a
8736 target instruction of size "target_size" so that it does not cross a
8737 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8738 the fill can be an arbitrary number of bytes. Otherwise, the space must
8739 be filled by NOP instructions. */
8742 get_text_align_fill_size (addressT address
,
8745 bfd_boolean use_nops
,
8746 bfd_boolean use_no_density
)
8748 addressT alignment
, fill
, fill_limit
, fill_step
;
8749 bfd_boolean skip_one
= FALSE
;
8751 alignment
= (1 << align_pow
);
8752 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8756 fill_limit
= alignment
;
8759 else if (!use_no_density
)
8761 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8762 fill_limit
= alignment
* 2;
8768 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8769 fill_limit
= alignment
* 3;
8773 /* Try all fill sizes until finding one that works. */
8774 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8776 if (skip_one
&& fill
== 1)
8778 if ((address
+ fill
) >> align_pow
8779 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8788 branch_align_power (segT sec
)
8790 /* If the Xtensa processor has a fetch width of X, and
8791 the section is aligned to at least that boundary, then a branch
8792 target need only fit within that aligned block of memory to avoid
8793 a stall. Otherwise, try to fit branch targets within 4-byte
8794 aligned blocks (which may be insufficient, e.g., if the section
8795 has no alignment, but it's good enough). */
8796 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8797 int sec_align
= get_recorded_alignment (sec
);
8799 if (sec_align
>= fetch_align
)
8806 /* This will assert if it is not possible. */
8809 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8815 gas_assert (fill_size
% 3 == 0);
8816 return (fill_size
/ 3);
8819 gas_assert (fill_size
!= 1); /* Bad argument. */
8821 while (fill_size
> 1)
8824 if (fill_size
== 2 || fill_size
== 4)
8826 fill_size
-= insn_size
;
8829 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8835 get_text_align_nth_nop_size (offsetT fill_size
,
8837 bfd_boolean use_no_density
)
8844 gas_assert (fill_size
!= 1); /* Bad argument. */
8846 while (fill_size
> 1)
8849 if (fill_size
== 2 || fill_size
== 4)
8851 fill_size
-= insn_size
;
8861 /* For the given fragment, find the appropriate address
8862 for it to begin at if we are using NOPs to align it. */
8865 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8867 /* The rule is: get next fragment's FIRST instruction. Find
8868 the smallest number of bytes that need to be added to
8869 ensure that the next fragment's FIRST instruction will fit
8872 E.G., 2 bytes : 0, 1, 2 mod 4
8875 If the FIRST instruction MIGHT be relaxed,
8876 assume that it will become a 3-byte instruction.
8878 Note again here that LOOP instructions are not bundleable,
8879 and this relaxation only applies to LOOP opcodes. */
8882 int first_insn_size
;
8884 addressT pre_opcode_bytes
;
8887 xtensa_opcode opcode
;
8888 bfd_boolean is_loop
;
8890 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8891 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8893 /* Find the loop frag. */
8894 first_insn
= next_non_empty_frag (fragP
);
8895 /* Now find the first insn frag. */
8896 first_insn
= next_non_empty_frag (first_insn
);
8898 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8899 gas_assert (is_loop
);
8900 loop_insn_size
= xg_get_single_size (opcode
);
8902 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8903 pre_opcode_bytes
+= loop_insn_size
;
8905 /* For loops, the alignment depends on the size of the
8906 instruction following the loop, not the LOOP instruction. */
8908 if (first_insn
== NULL
)
8909 first_insn_size
= xtensa_fetch_width
;
8911 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8913 /* If it was 8, then we'll need a larger alignment for the section. */
8914 align_power
= get_text_align_power (first_insn_size
);
8915 record_alignment (now_seg
, align_power
);
8917 fill_size
= get_text_align_fill_size
8918 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8919 fragP
->tc_frag_data
.is_no_density
);
8921 return address
+ fill_size
;
8925 /* 3 mechanisms for relaxing an alignment:
8927 Align to a power of 2.
8928 Align so the next fragment's instruction does not cross a word boundary.
8929 Align the current instruction so that if the next instruction
8930 were 3 bytes, it would not cross a word boundary.
8934 zeros - This is easy; always insert zeros.
8935 nops - 3-byte and 2-byte instructions
8939 >=5 : 3-byte instruction + fn (n-3)
8940 widening - widen previous instructions. */
8943 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8945 addressT target_address
, loop_insn_offset
;
8947 xtensa_opcode loop_opcode
;
8948 bfd_boolean is_loop
;
8951 offsetT branch_align
;
8954 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8955 switch (fragP
->fr_subtype
)
8957 case RELAX_DESIRE_ALIGN
:
8958 target_size
= next_frag_format_size (fragP
);
8959 if (target_size
== XTENSA_UNDEFINED
)
8961 align_power
= branch_align_power (now_seg
);
8962 branch_align
= 1 << align_power
;
8963 /* Don't count on the section alignment being as large as the target. */
8964 if (target_size
> branch_align
)
8965 target_size
= branch_align
;
8966 opt_diff
= get_text_align_fill_size (address
, align_power
,
8967 target_size
, FALSE
, FALSE
);
8969 *max_diff
= (opt_diff
+ branch_align
8970 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8971 gas_assert (*max_diff
>= opt_diff
);
8974 case RELAX_ALIGN_NEXT_OPCODE
:
8975 /* The next non-empty frag after this one holds the LOOP instruction
8976 that needs to be aligned. The required alignment depends on the
8977 size of the next non-empty frag after the loop frag, i.e., the
8978 first instruction in the loop. */
8979 loop_frag
= next_non_empty_frag (fragP
);
8980 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8981 loop_insn_offset
= 0;
8982 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8983 gas_assert (is_loop
);
8985 /* If the loop has been expanded then the LOOP instruction
8986 could be at an offset from this fragment. */
8987 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8988 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8990 /* In an ideal world, which is what we are shooting for here,
8991 we wouldn't need to use any NOPs immediately prior to the
8992 LOOP instruction. If this approach fails, relax_frag_loop_align
8993 will call get_noop_aligned_address. */
8995 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8996 align_power
= get_text_align_power (target_size
);
8997 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8998 target_size
, FALSE
, FALSE
);
9000 *max_diff
= xtensa_fetch_width
9001 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9002 - target_size
+ opt_diff
;
9003 gas_assert (*max_diff
>= opt_diff
);
9014 /* md_relax_frag Hook and Helper Functions. */
9016 static long relax_frag_loop_align (fragS
*, long);
9017 static long relax_frag_for_align (fragS
*, long);
9018 static long relax_frag_immed
9019 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9021 typedef struct cached_fixup cached_fixupS
;
9030 typedef struct fixup_cache fixup_cacheS
;
9033 cached_fixupS
*fixups
;
9041 static int fixup_order (const void *a
, const void *b
)
9043 const cached_fixupS
*pa
= a
;
9044 const cached_fixupS
*pb
= b
;
9046 if (pa
->addr
== pb
->addr
)
9048 if (pa
->target
== pb
->target
)
9050 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
9052 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
9054 return pa
->target
- pb
->target
;
9056 return pa
->addr
- pb
->addr
;
9059 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
9061 xtensa_isa isa
= xtensa_default_isa
;
9062 int addr
= fixP
->fx_frag
->fr_address
;
9065 symbolS
*s
= fixP
->fx_addsy
;
9068 xtensa_opcode opcode
;
9070 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9071 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9073 target
= S_GET_VALUE (s
);
9074 delta
= target
- addr
;
9076 if (abs(delta
) < J_RANGE
/ 2)
9079 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9080 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9082 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9083 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9084 slot
= fixP
->tc_fix_data
.slot
;
9085 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9086 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9087 if (opcode
!= xtensa_j_opcode
)
9098 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
9100 if (cache
->n_fixups
+ add
> cache
->n_max
)
9102 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
9103 cache
->fixups
= XRESIZEVEC (cached_fixupS
, cache
->fixups
, cache
->n_max
);
9107 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
9108 segment_info_type
*seginfo
)
9112 cache
->n_fixups
= 0;
9114 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
9116 xtensa_realloc_fixup_cache (cache
, 1);
9118 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
9121 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
9124 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
9128 unsigned b
= cache
->n_fixups
;
9132 unsigned c
= (a
+ b
) / 2;
9134 if (cache
->fixups
[c
].addr
< addr
)
9142 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
9144 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
9145 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
9149 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
9154 if (!xtensa_make_cached_fixup (&o
, fixP
))
9156 xtensa_realloc_fixup_cache (cache
, 1);
9157 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
9158 if (i
< cache
->n_fixups
)
9161 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
9162 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
9164 cache
->fixups
[i
] = o
;
9169 static void xg_relax_trampoline (fragS
*fragP
, long stretch
, long *new_stretch
)
9171 static fixup_cacheS fixup_cache
;
9172 segment_info_type
*seginfo
= seg_info (now_seg
);
9173 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9174 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9177 if (now_seg
!= fixup_cache
.seg
||
9178 fragP
== fixup_cache
.first_frag
||
9179 fixup_cache
.first_frag
== NULL
)
9181 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9182 fixup_cache
.seg
= now_seg
;
9183 fixup_cache
.first_frag
= fragP
;
9186 /* Scan for jumps that will not reach. */
9187 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9188 i
< fixup_cache
.n_fixups
; ++i
)
9191 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9192 int target
= fixup_cache
.fixups
[i
].target
;
9193 int addr
= fixup_cache
.fixups
[i
].addr
;
9194 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9196 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9198 if (addr
+ J_RANGE
< trampaddr
)
9200 if (addr
> trampaddr
+ J_RANGE
)
9202 if (abs (delta
) < J_RANGE
)
9205 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9206 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9207 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9208 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9209 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9210 int lower
= (target
< addr
) ? target
: addr
;
9211 int upper
= (target
> addr
) ? target
: addr
;
9212 int midpoint
= lower
+ (upper
- lower
) / 2;
9214 if ((upper
- lower
) > 2 * J_RANGE
)
9216 /* One trampoline won't suffice; we need multiple jumps.
9217 Jump to the trampoline that's farthest, but still in
9218 range relative to the original "j" instruction. */
9219 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9221 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9222 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9227 if (this_addr
- addr
< J_RANGE
)
9232 /* Backward jump. */
9233 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9240 struct trampoline_frag
*best_tf
= NULL
;
9241 struct trampoline_frag
*best_tf_prev
= NULL
;
9244 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9246 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9247 int this_delta
= abs (this_addr
- midpoint
);
9249 if (!best_tf
|| this_delta
< best_delta
)
9252 best_delta
= this_delta
;
9253 best_tf_prev
= prev
;
9257 prev
= best_tf_prev
;
9259 if (tf
->fragP
== fragP
)
9261 if (abs (addr
- trampaddr
) < J_RANGE
)
9262 { /* The trampoline is in range of original; fix it! */
9265 new_stretch
+= init_trampoline_frag (tf
) + 3;
9266 /* Assemble a jump to the target label in the trampoline frag. */
9267 newfixP
= xg_append_jump (fragP
, tf
->fixP
,
9268 fixP
->fx_addsy
, fixP
->fx_offset
);
9270 /* Adjust the fixup for the original "j" instruction to
9271 point to the newly added jump. */
9272 fixP
->fx_addsy
= fragP
->fr_symbol
;
9273 fixP
->fx_offset
= fragP
->fr_fix
- 3;
9274 fixP
->tc_fix_data
.X_add_symbol
= fragP
->fr_symbol
;
9275 fixP
->tc_fix_data
.X_add_number
= fragP
->fr_fix
- 3;
9278 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9279 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9281 /* re-do current fixup */
9284 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9285 /* Do we have room for more? */
9286 if (fragP
->fr_var
< 3)
9287 { /* No, convert to fill. */
9289 fragP
->fr_subtype
= 0;
9290 /* Remove from the trampoline_list. */
9291 prev
->next
= tf
->next
;
9292 if (fragP
== fixup_cache
.first_frag
)
9293 fixup_cache
.first_frag
= NULL
;
9302 /* Return the number of bytes added to this fragment, given that the
9303 input has been stretched already by "stretch". */
9306 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9308 xtensa_isa isa
= xtensa_default_isa
;
9309 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9310 long new_stretch
= 0;
9311 const char *file_name
;
9314 static xtensa_insnbuf vbuf
= NULL
;
9315 int slot
, num_slots
;
9318 file_name
= as_where (&line
);
9319 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9321 fragP
->tc_frag_data
.unreported_expansion
= 0;
9323 switch (fragP
->fr_subtype
)
9325 case RELAX_ALIGN_NEXT_OPCODE
:
9326 /* Always convert. */
9327 if (fragP
->tc_frag_data
.relax_seen
)
9328 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9331 case RELAX_LOOP_END
:
9335 case RELAX_LOOP_END_ADD_NOP
:
9336 /* Add a NOP and switch to .fill 0. */
9337 new_stretch
= relax_frag_add_nop (fragP
);
9341 case RELAX_DESIRE_ALIGN
:
9342 /* Do nothing. The narrowing before this frag will either align
9347 case RELAX_LITERAL_FINAL
:
9350 case RELAX_LITERAL_NR
:
9352 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9353 gas_assert (unreported
== lit_size
);
9354 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9355 fragP
->fr_var
-= lit_size
;
9356 fragP
->fr_fix
+= lit_size
;
9362 vbuf
= xtensa_insnbuf_alloc (isa
);
9364 xtensa_insnbuf_from_chars
9365 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9366 fmt
= xtensa_format_decode (isa
, vbuf
);
9367 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9369 for (slot
= 0; slot
< num_slots
; slot
++)
9371 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9374 if (fragP
->tc_frag_data
.relax_seen
)
9375 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9379 case RELAX_IMMED_STEP1
:
9380 case RELAX_IMMED_STEP2
:
9381 case RELAX_IMMED_STEP3
:
9382 /* Place the immediate. */
9383 new_stretch
+= relax_frag_immed
9384 (now_seg
, fragP
, stretch
,
9385 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9386 fmt
, slot
, stretched_p
, FALSE
);
9390 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9396 case RELAX_LITERAL_POOL_BEGIN
:
9397 if (fragP
->fr_var
!= 0)
9399 /* We have a converted "candidate" literal pool;
9400 assemble a jump around it. */
9402 if (!litpool_slotbuf
)
9404 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9405 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9408 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9409 fragP
->tc_frag_data
.is_insn
= TRUE
;
9411 insn
.insn_type
= ITYPE_INSN
;
9412 insn
.opcode
= xtensa_j_opcode
;
9414 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9416 fmt
= xg_get_single_format (xtensa_j_opcode
);
9417 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9418 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9419 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9420 (unsigned char *)fragP
->fr_literal
+
9425 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9426 BFD_RELOC_XTENSA_SLOT0_OP
);
9430 case RELAX_LITERAL_POOL_END
:
9431 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9432 case RELAX_MAYBE_UNREACHABLE
:
9433 case RELAX_MAYBE_DESIRE_ALIGN
:
9434 /* No relaxation required. */
9437 case RELAX_FILL_NOP
:
9438 case RELAX_UNREACHABLE
:
9439 if (fragP
->tc_frag_data
.relax_seen
)
9440 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9443 case RELAX_TRAMPOLINE
:
9444 if (fragP
->tc_frag_data
.relax_seen
)
9445 xg_relax_trampoline (fragP
, stretch
, &new_stretch
);
9449 as_bad (_("bad relaxation state"));
9452 /* Tell gas we need another relaxation pass. */
9453 if (! fragP
->tc_frag_data
.relax_seen
)
9455 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9459 new_logical_line (file_name
, line
);
9465 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9467 addressT old_address
, old_next_address
, old_size
;
9468 addressT new_address
, new_next_address
, new_size
;
9471 /* All the frags with relax_frag_for_alignment prior to this one in the
9472 section have been done, hopefully eliminating the need for a NOP here.
9473 But, this will put it in if necessary. */
9475 /* Calculate the old address of this fragment and the next fragment. */
9476 old_address
= fragP
->fr_address
- stretch
;
9477 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9478 fragP
->tc_frag_data
.text_expansion
[0]);
9479 old_size
= old_next_address
- old_address
;
9481 /* Calculate the new address of this fragment and the next fragment. */
9482 new_address
= fragP
->fr_address
;
9484 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9485 new_size
= new_next_address
- new_address
;
9487 growth
= new_size
- old_size
;
9489 /* Fix up the text_expansion field and return the new growth. */
9490 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9495 /* Add a NOP instruction. */
9498 relax_frag_add_nop (fragS
*fragP
)
9500 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9501 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9502 assemble_nop (length
, nop_buf
);
9503 fragP
->tc_frag_data
.is_insn
= TRUE
;
9505 if (fragP
->fr_var
< length
)
9507 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9511 fragP
->fr_fix
+= length
;
9512 fragP
->fr_var
-= length
;
9517 static long future_alignment_required (fragS
*, long);
9520 relax_frag_for_align (fragS
*fragP
, long stretch
)
9522 /* Overview of the relaxation procedure for alignment:
9523 We can widen with NOPs or by widening instructions or by filling
9524 bytes after jump instructions. Find the opportune places and widen
9525 them if necessary. */
9530 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9531 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9532 || (fragP
->fr_subtype
== RELAX_SLOTS
9533 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9535 stretch_me
= future_alignment_required (fragP
, stretch
);
9536 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9542 /* We expanded on a previous pass. Can we shrink now? */
9543 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9544 if (shrink
<= stretch
&& stretch
> 0)
9546 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9552 /* Below here, diff > 0. */
9553 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9559 /* Return the address of the next frag that should be aligned.
9561 By "address" we mean the address it _would_ be at if there
9562 is no action taken to align it between here and the target frag.
9563 In other words, if no narrows and no fill nops are used between
9564 here and the frag to align, _even_if_ some of the frags we use
9565 to align targets have already expanded on a previous relaxation
9568 Also, count each frag that may be used to help align the target.
9570 Return 0 if there are no frags left in the chain that need to be
9574 find_address_of_next_align_frag (fragS
**fragPP
,
9578 bfd_boolean
*paddable
)
9580 fragS
*fragP
= *fragPP
;
9581 addressT address
= fragP
->fr_address
;
9583 /* Do not reset the counts to 0. */
9587 /* Limit this to a small search. */
9588 if (*widens
>= (int) xtensa_fetch_width
)
9593 address
+= fragP
->fr_fix
;
9595 if (fragP
->fr_type
== rs_fill
)
9596 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9597 else if (fragP
->fr_type
== rs_machine_dependent
)
9599 switch (fragP
->fr_subtype
)
9601 case RELAX_UNREACHABLE
:
9605 case RELAX_FILL_NOP
:
9607 if (!fragP
->tc_frag_data
.is_no_density
)
9612 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9617 address
+= total_frag_text_expansion (fragP
);
9621 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9624 case RELAX_ALIGN_NEXT_OPCODE
:
9625 case RELAX_DESIRE_ALIGN
:
9629 case RELAX_MAYBE_UNREACHABLE
:
9630 case RELAX_MAYBE_DESIRE_ALIGN
:
9635 /* Just punt if we don't know the type. */
9642 /* Just punt if we don't know the type. */
9646 fragP
= fragP
->fr_next
;
9654 static long bytes_to_stretch (fragS
*, int, int, int, int);
9657 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9659 fragS
*this_frag
= fragP
;
9663 int narrow_nops
= 0;
9664 bfd_boolean paddable
= FALSE
;
9665 offsetT local_opt_diff
;
9668 int stretch_amount
= 0;
9669 int local_stretch_amount
;
9670 int global_stretch_amount
;
9672 address
= find_address_of_next_align_frag
9673 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9677 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9678 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9680 frag_wane (this_frag
);
9684 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9685 opt_diff
= local_opt_diff
;
9686 gas_assert (opt_diff
>= 0);
9687 gas_assert (max_diff
>= opt_diff
);
9692 fragP
= fragP
->fr_next
;
9694 while (fragP
&& opt_diff
< max_diff
&& address
)
9696 /* We only use these to determine if we can exit early
9697 because there will be plenty of ways to align future
9699 int glob_widens
= 0;
9702 bfd_boolean glob_pad
= 0;
9703 address
= find_address_of_next_align_frag
9704 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9705 /* If there is a padable portion, then skip. */
9706 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9711 offsetT next_m_diff
;
9712 offsetT next_o_diff
;
9714 /* Downrange frags haven't had stretch added to them yet. */
9717 /* The address also includes any text expansion from this
9718 frag in a previous pass, but we don't want that. */
9719 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9721 /* Assume we are going to move at least opt_diff. In
9722 reality, we might not be able to, but assuming that
9723 we will helps catch cases where moving opt_diff pushes
9724 the next target from aligned to unaligned. */
9725 address
+= opt_diff
;
9727 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9729 /* Now cleanup for the adjustments to address. */
9730 next_o_diff
+= opt_diff
;
9731 next_m_diff
+= opt_diff
;
9732 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9733 opt_diff
= next_o_diff
;
9734 if (next_m_diff
< max_diff
)
9735 max_diff
= next_m_diff
;
9736 fragP
= fragP
->fr_next
;
9740 /* If there are enough wideners in between, do it. */
9743 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9745 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9750 local_stretch_amount
9751 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9752 num_widens
, local_opt_diff
);
9753 global_stretch_amount
9754 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9755 num_widens
, opt_diff
);
9756 /* If the condition below is true, then the frag couldn't
9757 stretch the correct amount for the global case, so we just
9758 optimize locally. We'll rely on the subsequent frags to get
9759 the correct alignment in the global case. */
9760 if (global_stretch_amount
< local_stretch_amount
)
9761 stretch_amount
= local_stretch_amount
;
9763 stretch_amount
= global_stretch_amount
;
9765 if (this_frag
->fr_subtype
== RELAX_SLOTS
9766 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9767 gas_assert (stretch_amount
<= 1);
9768 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9770 if (this_frag
->tc_frag_data
.is_no_density
)
9771 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9773 gas_assert (stretch_amount
<= 3);
9776 return stretch_amount
;
9780 /* The idea: widen everything you can to get a target or loop aligned,
9781 then start using NOPs.
9783 wide_nops = the number of wide NOPs available for aligning
9784 narrow_nops = the number of narrow NOPs available for aligning
9785 (a subset of wide_nops)
9786 widens = the number of narrow instructions that should be widened
9791 bytes_to_stretch (fragS
*this_frag
,
9800 int bytes_short
= desired_diff
- num_widens
;
9802 gas_assert (desired_diff
>= 0
9803 && desired_diff
< (signed) xtensa_fetch_width
);
9804 if (desired_diff
== 0)
9807 gas_assert (wide_nops
> 0 || num_widens
> 0);
9809 /* Always prefer widening to NOP-filling. */
9810 if (bytes_short
< 0)
9812 /* There are enough RELAX_NARROW frags after this one
9813 to align the target without widening this frag in any way. */
9817 if (bytes_short
== 0)
9819 /* Widen every narrow between here and the align target
9820 and the align target will be properly aligned. */
9821 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9827 /* From here we will need at least one NOP to get an alignment.
9828 However, we may not be able to align at all, in which case,
9830 nops_needed
= desired_diff
/ 3;
9832 /* If there aren't enough nops, don't widen. */
9833 if (nops_needed
> wide_nops
)
9836 /* First try it with all wide nops. */
9837 nop_bytes
= nops_needed
* 3;
9838 extra_bytes
= desired_diff
- nop_bytes
;
9840 if (nop_bytes
+ num_widens
>= desired_diff
)
9842 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9844 else if (num_widens
== extra_bytes
)
9849 /* Add a narrow nop. */
9853 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9856 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9858 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9859 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9860 else if (num_widens
== extra_bytes
)
9865 /* Replace a wide nop with a narrow nop--we can get here if
9866 extra_bytes was negative in the previous conditional. */
9867 if (narrow_nops
== 1)
9871 if (nop_bytes
+ num_widens
>= desired_diff
)
9873 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9874 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9875 else if (num_widens
== extra_bytes
)
9880 /* If we can't satisfy any of the above cases, then we can't align
9881 using padding or fill nops. */
9886 static struct trampoline_frag
*
9887 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9889 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9890 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9891 struct trampoline_frag
*best_tf
= NULL
;
9894 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9895 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9896 offsetT addr
= fragP
->fr_address
;
9897 offsetT lower
= (addr
< target
) ? addr
: target
;
9898 offsetT upper
= (addr
> target
) ? addr
: target
;
9899 int delta
= upper
- lower
;
9900 offsetT midpoint
= lower
+ delta
/ 2;
9901 int this_delta
= -1;
9904 if (delta
> 2 * J_RANGE
)
9906 /* One trampoline won't do; we need multiple.
9907 Choose the farthest trampoline that's still in range of the original
9908 and let a later pass finish the job. */
9909 for ( ; tf
; tf
= tf
->next
)
9911 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9913 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9917 if (this_addr
- addr
< J_RANGE
)
9922 /* Backward jump. */
9923 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9927 if (abs (addr
- this_addr
) < J_RANGE
)
9932 for ( ; tf
; tf
= tf
->next
)
9934 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9935 this_delta
= abs (this_addr
- midpoint
);
9936 if (unreachable_only
&& tf
->needs_jump_around
)
9938 if (!best_tf
|| this_delta
< best_delta
)
9941 best_delta
= this_delta
;
9942 best_addr
= this_addr
;
9947 best_delta
< J_RANGE
&&
9948 abs(best_addr
- lower
) < J_RANGE
&&
9949 abs(best_addr
- upper
) < J_RANGE
)
9952 return NULL
; /* No suitable trampoline found. */
9956 static struct trampoline_frag
*
9957 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9959 struct trampoline_frag
*tf
= NULL
;
9961 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9964 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9971 check_and_update_trampolines (void)
9973 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9974 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9975 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9977 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9979 if (tf
->fragP
->fr_var
< 3)
9981 frag_wane (tf
->fragP
);
9982 prev
->next
= tf
->next
;
9988 static fixS
*xg_append_jump (fragS
*fragP
, fixS
*jump_around
,
9989 symbolS
*sym
, offsetT offset
)
9994 xtensa_isa isa
= xtensa_default_isa
;
9996 gas_assert (fragP
->fr_var
>= 3);
9998 insn
.insn_type
= ITYPE_INSN
;
9999 insn
.opcode
= xtensa_j_opcode
;
10001 set_expr_symbol_offset (&insn
.tok
[0], sym
, offset
);
10002 fmt
= xg_get_single_format (xtensa_j_opcode
);
10003 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10004 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10005 xtensa_insnbuf_to_chars (isa
, trampoline_buf
,
10006 (unsigned char *)fragP
->fr_literal
+ fragP
->fr_fix
, 3);
10007 fixP
= fix_new (fragP
, fragP
->fr_fix
, 3, sym
, offset
, TRUE
,
10008 BFD_RELOC_XTENSA_SLOT0_OP
);
10009 fixP
->tc_fix_data
.slot
= 0;
10011 fragP
->fr_fix
+= 3;
10012 fragP
->fr_var
-= 3;
10014 /* Adjust the jump around this trampoline (if present). */
10016 jump_around
->fx_offset
+= 3;
10023 init_trampoline_frag (struct trampoline_frag
*trampP
)
10025 fragS
*fp
= trampP
->fragP
;
10028 if (fp
->fr_fix
== 0)
10031 char label
[10 + 2 * sizeof(fp
)];
10033 sprintf (label
, ".L0_TR_%p", fp
);
10034 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10035 fp
->fr_symbol
= lsym
;
10036 if (trampP
->needs_jump_around
)
10038 trampP
->fixP
= xg_append_jump (fp
, NULL
, lsym
, 3);
10047 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
10049 fragS
*tramp
= trampP
->fragP
;
10052 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10053 if (origfrag
->tc_frag_data
.slot_symbols
[i
])
10055 gas_assert (slot
== -1);
10059 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10061 /* Assemble a jump to the target label in the trampoline frag. */
10062 xg_append_jump (tramp
, trampP
->fixP
,
10063 origfrag
->tc_frag_data
.slot_symbols
[slot
],
10064 origfrag
->tc_frag_data
.slot_offsets
[slot
]);
10066 /* Modify the original j to point here. */
10067 origfrag
->tc_frag_data
.slot_symbols
[slot
] = tramp
->fr_symbol
;
10068 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10070 /* If trampoline is full, remove it from the list. */
10071 check_and_update_trampolines ();
10078 relax_frag_immed (segT segP
,
10085 bfd_boolean estimate_only
)
10089 bfd_boolean negatable_branch
= FALSE
;
10090 bfd_boolean branch_jmp_to_next
= FALSE
;
10091 bfd_boolean from_wide_insn
= FALSE
;
10092 xtensa_isa isa
= xtensa_default_isa
;
10094 offsetT frag_offset
;
10096 int num_text_bytes
, num_literal_bytes
;
10097 int literal_diff
, total_text_diff
, this_text_diff
;
10099 gas_assert (fragP
->fr_opcode
!= NULL
);
10101 xg_clear_vinsn (&cur_vinsn
);
10102 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10103 if (cur_vinsn
.num_slots
> 1)
10104 from_wide_insn
= TRUE
;
10106 tinsn
= cur_vinsn
.slots
[slot
];
10107 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10109 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10112 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10113 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10115 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10117 old_size
= xtensa_format_length (isa
, fmt
);
10119 /* Special case: replace a branch to the next instruction with a NOP.
10120 This is required to work around a hardware bug in T1040.0 and also
10121 serves as an optimization. */
10123 if (branch_jmp_to_next
10124 && ((old_size
== 2) || (old_size
== 3))
10125 && !next_frag_is_loop_target (fragP
))
10128 /* Here is the fun stuff: Get the immediate field from this
10129 instruction. If it fits, we are done. If not, find the next
10130 instruction sequence that fits. */
10132 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10133 istack_init (&istack
);
10134 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10135 min_steps
, stretch
);
10136 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10138 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10140 /* Figure out the number of bytes needed. */
10141 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10143 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10144 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10146 if (from_wide_insn
)
10149 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10152 num_text_bytes
+= old_size
;
10153 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10154 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10157 /* The first instruction in the relaxed sequence will go after
10158 the current wide instruction, and thus its symbolic immediates
10161 istack_init (&istack
);
10162 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10163 frag_offset
+ old_size
,
10164 min_steps
, stretch
+ old_size
);
10165 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10167 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10168 = (int) RELAX_IMMED
+ num_steps
;
10170 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10172 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10174 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10178 total_text_diff
= num_text_bytes
- old_size
;
10179 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10181 /* It MUST get larger. If not, we could get an infinite loop. */
10182 gas_assert (num_text_bytes
>= 0);
10183 gas_assert (literal_diff
>= 0);
10184 gas_assert (total_text_diff
>= 0);
10186 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10187 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10188 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10189 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10191 /* Find the associated expandable literal for this. */
10192 if (literal_diff
!= 0)
10194 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10197 gas_assert (literal_diff
== 4);
10198 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10200 /* We expect that the literal section state has NOT been
10202 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10203 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10204 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10206 /* We need to mark this section for another iteration
10212 if (negatable_branch
&& istack
.ninsn
> 1)
10213 update_next_frag_state (fragP
);
10215 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10216 if (istack
.ninsn
> 2 &&
10217 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10218 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10219 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10221 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10223 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
10225 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
10229 this_text_diff
+= init_trampoline_frag (tf
);
10230 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
10234 /* If target symbol is undefined, assume it will reach once linked. */
10235 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10237 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10239 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10240 _("jump target out of range; no usable trampoline found"));
10246 return this_text_diff
;
10250 /* md_convert_frag Hook and Helper Functions. */
10252 static void convert_frag_align_next_opcode (fragS
*);
10253 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10254 static void convert_frag_fill_nop (fragS
*);
10255 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10258 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10260 static xtensa_insnbuf vbuf
= NULL
;
10261 xtensa_isa isa
= xtensa_default_isa
;
10265 const char *file_name
;
10268 file_name
= as_where (&line
);
10269 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10271 switch (fragp
->fr_subtype
)
10273 case RELAX_ALIGN_NEXT_OPCODE
:
10274 /* Always convert. */
10275 convert_frag_align_next_opcode (fragp
);
10278 case RELAX_DESIRE_ALIGN
:
10279 /* Do nothing. If not aligned already, too bad. */
10282 case RELAX_LITERAL
:
10283 case RELAX_LITERAL_FINAL
:
10288 vbuf
= xtensa_insnbuf_alloc (isa
);
10290 xtensa_insnbuf_from_chars
10291 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10292 fmt
= xtensa_format_decode (isa
, vbuf
);
10293 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10295 for (slot
= 0; slot
< num_slots
; slot
++)
10297 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10300 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10304 case RELAX_IMMED_STEP1
:
10305 case RELAX_IMMED_STEP2
:
10306 case RELAX_IMMED_STEP3
:
10307 /* Place the immediate. */
10310 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10315 /* This is OK because some slots could have
10316 relaxations and others have none. */
10322 case RELAX_UNREACHABLE
:
10323 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10324 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10325 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10329 case RELAX_MAYBE_UNREACHABLE
:
10330 case RELAX_MAYBE_DESIRE_ALIGN
:
10334 case RELAX_FILL_NOP
:
10335 convert_frag_fill_nop (fragp
);
10338 case RELAX_LITERAL_NR
:
10339 if (use_literal_section
)
10341 /* This should have been handled during relaxation. When
10342 relaxing a code segment, literals sometimes need to be
10343 added to the corresponding literal segment. If that
10344 literal segment has already been relaxed, then we end up
10345 in this situation. Marking the literal segments as data
10346 would make this happen less often (since GAS always relaxes
10347 code before data), but we could still get into trouble if
10348 there are instructions in a segment that is not marked as
10349 containing code. Until we can implement a better solution,
10350 cheat and adjust the addresses of all the following frags.
10351 This could break subsequent alignments, but the linker's
10352 literal coalescing will do that anyway. */
10355 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10356 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10357 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10358 fragp
->fr_var
-= 4;
10359 fragp
->fr_fix
+= 4;
10360 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10361 f
->fr_address
+= 4;
10364 as_bad (_("invalid relaxation fragment result"));
10367 case RELAX_TRAMPOLINE
:
10372 new_logical_line (file_name
, line
);
10377 convert_frag_align_next_opcode (fragS
*fragp
)
10379 char *nop_buf
; /* Location for Writing. */
10380 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10381 addressT aligned_address
;
10383 int nop
, nop_count
;
10385 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10387 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10388 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10389 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10391 for (nop
= 0; nop
< nop_count
; nop
++)
10394 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10396 assemble_nop (nop_size
, nop_buf
);
10397 nop_buf
+= nop_size
;
10400 fragp
->fr_fix
+= fill_size
;
10401 fragp
->fr_var
-= fill_size
;
10406 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10408 TInsn tinsn
, single_target
;
10409 int size
, old_size
, diff
;
10410 offsetT frag_offset
;
10412 gas_assert (slot
== 0);
10413 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10415 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10417 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10418 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10419 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10424 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10426 /* No conversion. */
10431 gas_assert (fragP
->fr_opcode
!= NULL
);
10433 /* Frags in this relaxation state should only contain
10434 single instruction bundles. */
10435 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10437 /* Just convert it to a wide form.... */
10439 old_size
= xg_get_single_size (tinsn
.opcode
);
10441 tinsn_init (&single_target
);
10442 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10444 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10446 as_bad (_("unable to widen instruction"));
10450 size
= xg_get_single_size (single_target
.opcode
);
10451 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10452 frag_offset
, TRUE
);
10454 diff
= size
- old_size
;
10455 gas_assert (diff
>= 0);
10456 gas_assert (diff
<= fragP
->fr_var
);
10457 fragP
->fr_var
-= diff
;
10458 fragP
->fr_fix
+= diff
;
10466 convert_frag_fill_nop (fragS
*fragP
)
10468 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10469 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10470 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10471 - fragP
->fr_address
- fragP
->fr_fix
));
10474 /* No conversion. */
10478 assemble_nop (size
, loc
);
10479 fragP
->tc_frag_data
.is_insn
= TRUE
;
10480 fragP
->fr_var
-= size
;
10481 fragP
->fr_fix
+= size
;
10486 static fixS
*fix_new_exp_in_seg
10487 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10488 bfd_reloc_code_real_type
);
10489 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10492 convert_frag_immed (segT segP
,
10498 char *immed_instr
= fragP
->fr_opcode
;
10500 bfd_boolean expanded
= FALSE
;
10501 bfd_boolean branch_jmp_to_next
= FALSE
;
10502 char *fr_opcode
= fragP
->fr_opcode
;
10503 xtensa_isa isa
= xtensa_default_isa
;
10504 bfd_boolean from_wide_insn
= FALSE
;
10506 bfd_boolean is_loop
;
10508 gas_assert (fr_opcode
!= NULL
);
10510 xg_clear_vinsn (&cur_vinsn
);
10512 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10513 if (cur_vinsn
.num_slots
> 1)
10514 from_wide_insn
= TRUE
;
10516 orig_tinsn
= cur_vinsn
.slots
[slot
];
10517 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10519 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10521 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10522 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10524 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10526 /* Conversion just inserts a NOP and marks the fix as completed. */
10527 bytes
= xtensa_format_length (isa
, fmt
);
10530 cur_vinsn
.slots
[slot
].opcode
=
10531 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10532 cur_vinsn
.slots
[slot
].ntok
= 0;
10536 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10537 gas_assert (bytes
== 2 || bytes
== 3);
10538 build_nop (&cur_vinsn
.slots
[0], bytes
);
10539 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10541 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10542 xtensa_insnbuf_to_chars
10543 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10548 /* Here is the fun stuff: Get the immediate field from this
10549 instruction. If it fits, we're done. If not, find the next
10550 instruction sequence that fits. */
10554 symbolS
*lit_sym
= NULL
;
10555 int total_size
= 0;
10556 int target_offset
= 0;
10559 symbolS
*gen_label
= NULL
;
10560 offsetT frag_offset
;
10561 bfd_boolean first
= TRUE
;
10563 /* It does not fit. Find something that does and
10564 convert immediately. */
10565 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10566 istack_init (&istack
);
10567 xg_assembly_relax (&istack
, &orig_tinsn
,
10568 segP
, fragP
, frag_offset
, min_steps
, 0);
10570 old_size
= xtensa_format_length (isa
, fmt
);
10572 /* Assemble this right inline. */
10574 /* First, create the mapping from a label name to the REAL label. */
10576 for (i
= 0; i
< istack
.ninsn
; i
++)
10578 TInsn
*tinsn
= &istack
.insn
[i
];
10581 switch (tinsn
->insn_type
)
10583 case ITYPE_LITERAL
:
10584 if (lit_sym
!= NULL
)
10585 as_bad (_("multiple literals in expansion"));
10586 /* First find the appropriate space in the literal pool. */
10587 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10588 if (lit_frag
== NULL
)
10589 as_bad (_("no registered fragment for literal"));
10590 if (tinsn
->ntok
!= 1)
10591 as_bad (_("number of literal tokens != 1"));
10593 /* Set the literal symbol and add a fixup. */
10594 lit_sym
= lit_frag
->fr_symbol
;
10598 if (align_targets
&& !is_loop
)
10600 fragS
*unreach
= fragP
->fr_next
;
10601 while (!(unreach
->fr_type
== rs_machine_dependent
10602 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10603 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10605 unreach
= unreach
->fr_next
;
10608 gas_assert (unreach
->fr_type
== rs_machine_dependent
10609 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10610 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10612 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10614 gas_assert (gen_label
== NULL
);
10615 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10616 fr_opcode
- fragP
->fr_literal
10617 + target_offset
, fragP
);
10621 if (first
&& from_wide_insn
)
10623 target_offset
+= xtensa_format_length (isa
, fmt
);
10625 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10626 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10629 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10636 for (i
= 0; i
< istack
.ninsn
; i
++)
10638 TInsn
*tinsn
= &istack
.insn
[i
];
10642 bfd_reloc_code_real_type reloc_type
;
10644 switch (tinsn
->insn_type
)
10646 case ITYPE_LITERAL
:
10647 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10648 /* Already checked. */
10649 gas_assert (lit_frag
!= NULL
);
10650 gas_assert (lit_sym
!= NULL
);
10651 gas_assert (tinsn
->ntok
== 1);
10653 target_seg
= S_GET_SEGMENT (lit_sym
);
10654 gas_assert (target_seg
);
10655 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10656 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10657 &tinsn
->tok
[0], FALSE
, reloc_type
);
10664 xg_resolve_labels (tinsn
, gen_label
);
10665 xg_resolve_literals (tinsn
, lit_sym
);
10666 if (from_wide_insn
&& first
)
10669 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10671 cur_vinsn
.slots
[slot
] = *tinsn
;
10675 cur_vinsn
.slots
[slot
].opcode
=
10676 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10677 cur_vinsn
.slots
[slot
].ntok
= 0;
10679 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10680 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10681 (unsigned char *) immed_instr
, 0);
10682 fragP
->tc_frag_data
.is_insn
= TRUE
;
10683 size
= xtensa_format_length (isa
, fmt
);
10684 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10686 xg_emit_insn_to_buf
10687 (tinsn
, immed_instr
+ size
, fragP
,
10688 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10689 size
+= xg_get_single_size (tinsn
->opcode
);
10694 size
= xg_get_single_size (tinsn
->opcode
);
10695 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10696 immed_instr
- fragP
->fr_literal
, TRUE
);
10698 immed_instr
+= size
;
10699 total_size
+= size
;
10704 diff
= total_size
- old_size
;
10705 gas_assert (diff
>= 0);
10708 gas_assert (diff
<= fragP
->fr_var
);
10709 fragP
->fr_var
-= diff
;
10710 fragP
->fr_fix
+= diff
;
10713 /* Check for undefined immediates in LOOP instructions. */
10717 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10718 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10720 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10723 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10724 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10726 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10731 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10732 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10734 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10736 /* Add an expansion note on the expanded instruction. */
10737 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10738 &orig_tinsn
.tok
[0], TRUE
,
10739 BFD_RELOC_XTENSA_ASM_EXPAND
);
10744 /* Add a new fix expression into the desired segment. We have to
10745 switch to that segment to do this. */
10748 fix_new_exp_in_seg (segT new_seg
,
10749 subsegT new_subseg
,
10755 bfd_reloc_code_real_type r_type
)
10758 segT seg
= now_seg
;
10759 subsegT subseg
= now_subseg
;
10761 gas_assert (new_seg
!= 0);
10762 subseg_set (new_seg
, new_subseg
);
10764 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10765 subseg_set (seg
, subseg
);
10770 /* Relax a loop instruction so that it can span loop >256 bytes.
10776 addi as, as, lo8 (label-.L1)
10777 addmi as, as, mid8 (label-.L1)
10788 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10793 unsigned long target
;
10794 static xtensa_insnbuf insnbuf
= NULL
;
10795 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10796 xtensa_isa isa
= xtensa_default_isa
;
10797 addressT loop_offset
;
10798 addressT addi_offset
= 9;
10799 addressT addmi_offset
= 12;
10804 insnbuf
= xtensa_insnbuf_alloc (isa
);
10806 /* Get the loop offset. */
10807 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10809 /* Validate that there really is a LOOP at the loop_offset. Because
10810 loops are not bundleable, we can assume that the instruction will be
10812 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10813 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10815 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10816 addi_offset
+= loop_offset
;
10817 addmi_offset
+= loop_offset
;
10819 gas_assert (tinsn
->ntok
== 2);
10820 if (tinsn
->tok
[1].X_op
== O_constant
)
10821 target
= tinsn
->tok
[1].X_add_number
;
10822 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10824 /* Find the fragment. */
10825 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10826 gas_assert (S_GET_SEGMENT (sym
) == segP
10827 || S_GET_SEGMENT (sym
) == absolute_section
);
10828 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10832 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10836 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10837 loop_length_hi
= loop_length
& ~0x0ff;
10838 loop_length_lo
= loop_length
& 0x0ff;
10839 if (loop_length_lo
>= 128)
10841 loop_length_lo
-= 256;
10842 loop_length_hi
+= 256;
10845 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10846 32512. If the loop is larger than that, then we just fail. */
10847 if (loop_length_hi
> 32512)
10848 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10849 _("loop too long for LOOP instruction"));
10851 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10852 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10854 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10855 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10857 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10858 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10860 fragP
->tc_frag_data
.is_insn
= TRUE
;
10861 xtensa_insnbuf_to_chars
10862 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10864 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10865 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10866 xtensa_insnbuf_to_chars
10867 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10869 /* Walk through all of the frags from here to the loop end
10870 and mark them as no_transform to keep them from being modified
10871 by the linker. If we ever have a relocation for the
10872 addi/addmi of the difference of two symbols we can remove this. */
10875 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10876 next_fragP
= next_fragP
->fr_next
)
10878 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10879 if (next_fragP
->tc_frag_data
.is_loop_target
)
10881 if (target_count
== 2)
10887 /* A map that keeps information on a per-subsegment basis. This is
10888 maintained during initial assembly, but is invalid once the
10889 subsegments are smashed together. I.E., it cannot be used during
10892 typedef struct subseg_map_struct
10900 float total_freq
; /* fall-through + branch target frequency */
10901 float target_freq
; /* branch target frequency alone */
10903 struct subseg_map_struct
*next
;
10907 static subseg_map
*sseg_map
= NULL
;
10909 static subseg_map
*
10910 get_subseg_info (segT seg
, subsegT subseg
)
10912 subseg_map
*subseg_e
;
10914 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10916 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10923 static subseg_map
*
10924 add_subseg_info (segT seg
, subsegT subseg
)
10926 subseg_map
*subseg_e
= XNEW (subseg_map
);
10927 memset (subseg_e
, 0, sizeof (subseg_map
));
10928 subseg_e
->seg
= seg
;
10929 subseg_e
->subseg
= subseg
;
10930 subseg_e
->flags
= 0;
10931 /* Start off considering every branch target very important. */
10932 subseg_e
->target_freq
= 1.0;
10933 subseg_e
->total_freq
= 1.0;
10934 subseg_e
->next
= sseg_map
;
10935 sseg_map
= subseg_e
;
10941 get_last_insn_flags (segT seg
, subsegT subseg
)
10943 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10945 return subseg_e
->flags
;
10951 set_last_insn_flags (segT seg
,
10956 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10958 subseg_e
= add_subseg_info (seg
, subseg
);
10960 subseg_e
->flags
|= fl
;
10962 subseg_e
->flags
&= ~fl
;
10967 get_subseg_total_freq (segT seg
, subsegT subseg
)
10969 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10971 return subseg_e
->total_freq
;
10977 get_subseg_target_freq (segT seg
, subsegT subseg
)
10979 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10981 return subseg_e
->target_freq
;
10987 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10989 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10991 subseg_e
= add_subseg_info (seg
, subseg
);
10992 subseg_e
->total_freq
= total_f
;
10993 subseg_e
->target_freq
= target_f
;
10997 /* Segment Lists and emit_state Stuff. */
11000 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11005 segT literal_section
= head
->seg
;
11007 /* Move the literal section to the front of the section list. */
11008 gas_assert (literal_section
);
11009 if (literal_section
!= stdoutput
->sections
)
11011 bfd_section_list_remove (stdoutput
, literal_section
);
11012 bfd_section_list_prepend (stdoutput
, literal_section
);
11019 static void mark_literal_frags (seg_list
*);
11022 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11023 struct litpool_frag
*lp
)
11028 char label
[10 + 2 * sizeof (fragS
*)];
11030 poolbeg
= lp
->fragP
;
11032 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11033 poolend
= poolbeg
->fr_next
;
11034 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11035 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11036 /* Create a local symbol pointing to the
11037 end of the pool. */
11038 sprintf (label
, ".L0_LT_%p", poolbeg
);
11039 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11041 poolbeg
->fr_symbol
= lsym
;
11042 /* Rest is done in xtensa_relax_frag. */
11046 xtensa_move_literals (void)
11049 frchainS
*frchain_from
, *frchain_to
;
11050 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11051 fragS
**frag_splice
;
11054 fixS
*fix
, *next_fix
, **fix_splice
;
11056 struct litpool_seg
*lps
;
11057 const char *init_name
= INIT_SECTION_NAME
;
11058 const char *fini_name
= FINI_SECTION_NAME
;
11059 int init_name_len
= strlen(init_name
);
11060 int fini_name_len
= strlen(fini_name
);
11062 mark_literal_frags (literal_head
->next
);
11064 if (use_literal_section
)
11067 /* Assign addresses (rough estimates) to the potential literal pool locations
11068 and create new ones if the gaps are too large. */
11070 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11072 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11073 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11076 for ( ; frchP
; frchP
= frchP
->frch_next
)
11079 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11081 if (lpf
&& fragP
== lpf
->fragP
)
11083 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11084 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11085 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11086 /* Found a litpool location. */
11090 if (fragP
->fr_type
== rs_machine_dependent
&&
11091 fragP
->fr_subtype
== RELAX_SLOTS
)
11094 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11096 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11098 /* L32R; point its literal to the nearest litpool
11099 preferring non-"candidate" positions to avoid
11100 the jump-around. */
11101 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11102 struct litpool_frag
*lp
= lpf
->prev
;
11107 while (lp
->fragP
->fr_subtype
==
11108 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11111 if (lp
->fragP
== NULL
)
11113 /* End of list; have to bite the bullet.
11114 Take the nearest. */
11118 /* Does it (conservatively) reach? */
11119 if (addr
- lp
->addr
<= 128 * 1024)
11121 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
11123 /* Found a good one. */
11126 else if (lp
->prev
->fragP
&&
11127 addr
- lp
->prev
->addr
> 128 * 1024)
11129 /* This is still a "candidate" but the next one
11130 will be too far away, so revert to the nearest
11131 one, convert it and add the jump around. */
11138 /* Convert candidate and add the jump around. */
11139 if (lp
->fragP
->fr_subtype
==
11140 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11141 xg_promote_candidate_litpool (lps
, lp
);
11143 if (! litfrag
->tc_frag_data
.literal_frag
)
11145 /* Take earliest use of this literal to avoid
11147 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11152 addr
+= fragP
->fr_fix
;
11153 if (fragP
->fr_type
== rs_fill
)
11154 addr
+= fragP
->fr_offset
;
11159 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11161 const char *seg_name
= segment_name (segment
->seg
);
11163 /* Keep the literals for .init and .fini in separate sections. */
11164 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11165 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11166 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11167 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11170 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11171 search_frag
= frchain_from
->frch_root
;
11172 literal_pool
= NULL
;
11174 frag_splice
= &(frchain_from
->frch_root
);
11176 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11178 gas_assert (search_frag
->fr_fix
== 0
11179 || search_frag
->fr_type
== rs_align
);
11180 search_frag
= search_frag
->fr_next
;
11185 search_frag
= frchain_from
->frch_root
;
11186 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11187 _("literal pool location required for text-section-literals; specify with .literal_position"));
11191 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11192 == RELAX_LITERAL_POOL_BEGIN
);
11193 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11195 /* Make sure that all the frags in this series are closed, and
11196 that there is at least one left over of zero-size. This
11197 prevents us from making a segment with an frchain without any
11199 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11200 xtensa_set_frag_assembly_state (frag_now
);
11201 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11202 xtensa_set_frag_assembly_state (frag_now
);
11204 while (search_frag
!= frag_now
)
11206 next_frag
= search_frag
->fr_next
;
11207 if (search_frag
->tc_frag_data
.literal_frag
)
11209 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11210 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11211 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11212 gas_assert (frchain_to
);
11215 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11217 /* Skip empty fill frags. */
11218 *frag_splice
= next_frag
;
11219 search_frag
= next_frag
;
11223 if (search_frag
->fr_type
== rs_align
)
11225 /* Skip alignment frags, because the pool as a whole will be
11226 aligned if used, and we don't want to force alignment if the
11228 *frag_splice
= next_frag
;
11229 search_frag
= next_frag
;
11233 /* First, move the frag out of the literal section and
11234 to the appropriate place. */
11236 /* Insert an alignment frag at start of pool. */
11237 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11238 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11240 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11241 emit_state prev_state
;
11244 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11245 prev_frag
= frag_now
;
11246 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11247 align_frag
= frag_now
;
11248 frag_align (2, 0, 0);
11249 /* Splice it into the right place. */
11250 prev_frag
->fr_next
= align_frag
->fr_next
;
11251 align_frag
->fr_next
= literal_pool
->fr_next
;
11252 literal_pool
->fr_next
= align_frag
;
11253 /* Insert after this one. */
11254 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11255 xtensa_restore_emit_state (&prev_state
);
11257 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11258 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11259 /* Skip align frag. */
11260 if (insert_after
->fr_next
->fr_type
== rs_align
)
11262 insert_after
= insert_after
->fr_next
;
11265 *frag_splice
= next_frag
;
11266 search_frag
->fr_next
= insert_after
->fr_next
;
11267 insert_after
->fr_next
= search_frag
;
11268 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11269 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11271 /* Now move any fixups associated with this frag to the
11273 fix
= frchain_from
->fix_root
;
11274 fix_splice
= &(frchain_from
->fix_root
);
11277 next_fix
= fix
->fx_next
;
11278 if (fix
->fx_frag
== search_frag
)
11280 *fix_splice
= next_fix
;
11281 fix
->fx_next
= frchain_to
->fix_root
;
11282 frchain_to
->fix_root
= fix
;
11283 if (frchain_to
->fix_tail
== NULL
)
11284 frchain_to
->fix_tail
= fix
;
11287 fix_splice
= &(fix
->fx_next
);
11290 search_frag
= next_frag
;
11293 if (frchain_from
->fix_root
!= NULL
)
11295 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11296 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11298 gas_assert (frchain_from
->fix_root
== NULL
);
11300 frchain_from
->fix_tail
= NULL
;
11301 xtensa_restore_emit_state (&state
);
11304 /* Now fix up the SEGMENT value for all the literal symbols. */
11305 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11307 symbolS
*lit_sym
= lit
->sym
;
11308 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11310 S_SET_SEGMENT (lit_sym
, dseg
);
11315 /* Walk over all the frags for segments in a list and mark them as
11316 containing literals. As clunky as this is, we can't rely on frag_var
11317 and frag_variant to get called in all situations. */
11320 mark_literal_frags (seg_list
*segment
)
11322 frchainS
*frchain_from
;
11323 fragS
*search_frag
;
11327 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11328 search_frag
= frchain_from
->frch_root
;
11329 while (search_frag
)
11331 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11332 search_frag
= search_frag
->fr_next
;
11334 segment
= segment
->next
;
11340 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11342 /* Move all of the sections in the section list to come
11343 after "after" in the gnu segment list. */
11348 segT literal_section
= head
->seg
;
11350 /* Move the literal section after "after". */
11351 gas_assert (literal_section
);
11352 if (literal_section
!= after
)
11354 bfd_section_list_remove (stdoutput
, literal_section
);
11355 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11363 /* Push all the literal segments to the end of the gnu list. */
11366 xtensa_reorder_segments (void)
11373 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11379 /* Now that we have the last section, push all the literal
11380 sections to the end. */
11381 xtensa_reorder_seg_list (literal_head
, last_sec
);
11383 /* Now perform the final error check. */
11384 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11386 gas_assert (new_count
== old_count
);
11390 /* Change the emit state (seg, subseg, and frag related stuff) to the
11391 correct location. Return a emit_state which can be passed to
11392 xtensa_restore_emit_state to return to current fragment. */
11395 xtensa_switch_to_literal_fragment (emit_state
*result
)
11397 if (directive_state
[directive_absolute_literals
])
11399 segT lit4_seg
= cache_literal_section (TRUE
);
11400 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11403 xtensa_switch_to_non_abs_literal_fragment (result
);
11405 /* Do a 4-byte align here. */
11406 frag_align (2, 0, 0);
11407 record_alignment (now_seg
, 2);
11412 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11414 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11416 bfd_boolean is_init
=
11417 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11418 bfd_boolean is_fini
=
11419 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11421 if (pool_location
== NULL
11422 && !use_literal_section
11423 && !is_init
&& ! is_fini
)
11425 if (!auto_litpools
)
11427 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11429 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11430 pool_location
= get_literal_pool_location (now_seg
);
11433 lit_seg
= cache_literal_section (FALSE
);
11434 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11436 if (!use_literal_section
11437 && !is_init
&& !is_fini
11438 && get_literal_pool_location (now_seg
) != pool_location
)
11440 /* Close whatever frag is there. */
11441 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11442 xtensa_set_frag_assembly_state (frag_now
);
11443 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11444 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11445 xtensa_set_frag_assembly_state (frag_now
);
11450 /* Call this function before emitting data into the literal section.
11451 This is a helper function for xtensa_switch_to_literal_fragment.
11452 This is similar to a .section new_now_seg subseg. */
11455 xtensa_switch_section_emit_state (emit_state
*state
,
11457 subsegT new_now_subseg
)
11459 state
->name
= now_seg
->name
;
11460 state
->now_seg
= now_seg
;
11461 state
->now_subseg
= now_subseg
;
11462 state
->generating_literals
= generating_literals
;
11463 generating_literals
++;
11464 subseg_set (new_now_seg
, new_now_subseg
);
11468 /* Use to restore the emitting into the normal place. */
11471 xtensa_restore_emit_state (emit_state
*state
)
11473 generating_literals
= state
->generating_literals
;
11474 subseg_set (state
->now_seg
, state
->now_subseg
);
11478 /* Predicate function used to look up a section in a particular group. */
11481 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11483 const char *gname
= inf
;
11484 const char *group_name
= elf_group_name (sec
);
11486 return (group_name
== gname
11487 || (group_name
!= NULL
11489 && strcmp (group_name
, gname
) == 0));
11493 /* Get the literal section to be used for the current text section.
11494 The result may be cached in the default_lit_sections structure. */
11497 cache_literal_section (bfd_boolean use_abs_literals
)
11499 const char *text_name
, *group_name
= 0;
11500 const char *base_name
, *suffix
;
11503 segT seg
, current_section
;
11504 int current_subsec
;
11505 bfd_boolean linkonce
= FALSE
;
11507 /* Save the current section/subsection. */
11508 current_section
= now_seg
;
11509 current_subsec
= now_subseg
;
11511 /* Clear the cached values if they are no longer valid. */
11512 if (now_seg
!= default_lit_sections
.current_text_seg
)
11514 default_lit_sections
.current_text_seg
= now_seg
;
11515 default_lit_sections
.lit_seg
= NULL
;
11516 default_lit_sections
.lit4_seg
= NULL
;
11519 /* Check if the literal section is already cached. */
11520 if (use_abs_literals
)
11521 pcached
= &default_lit_sections
.lit4_seg
;
11523 pcached
= &default_lit_sections
.lit_seg
;
11528 text_name
= default_lit_sections
.lit_prefix
;
11529 if (! text_name
|| ! *text_name
)
11531 text_name
= segment_name (current_section
);
11532 group_name
= elf_group_name (current_section
);
11533 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11536 base_name
= use_abs_literals
? ".lit4" : ".literal";
11539 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11541 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11543 suffix
= strchr (text_name
+ linkonce_len
, '.');
11545 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11551 /* If the section name begins or ends with ".text", then replace
11552 that portion instead of appending an additional suffix. */
11553 size_t len
= strlen (text_name
);
11555 && (strcmp (text_name
+ len
- 5, ".text") == 0
11556 || strncmp (text_name
, ".text", 5) == 0))
11559 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11560 if (strncmp (text_name
, ".text", 5) == 0)
11562 strcpy (name
, base_name
);
11563 strcat (name
, text_name
+ 5);
11567 strcpy (name
, text_name
);
11568 strcpy (name
+ len
, base_name
);
11572 /* Canonicalize section names to allow renaming literal sections.
11573 The group name, if any, came from the current text section and
11574 has already been canonicalized. */
11575 name
= tc_canonicalize_symbol_name (name
);
11577 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11578 (void *) group_name
);
11583 seg
= subseg_force_new (name
, 0);
11585 if (! use_abs_literals
)
11587 /* Add the newly created literal segment to the list. */
11588 seg_list
*n
= XNEW (seg_list
);
11590 n
->next
= literal_head
->next
;
11591 literal_head
->next
= n
;
11594 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11595 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11596 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11598 elf_group_name (seg
) = group_name
;
11600 bfd_set_section_flags (stdoutput
, seg
, flags
);
11601 bfd_set_section_alignment (stdoutput
, seg
, 2);
11605 subseg_set (current_section
, current_subsec
);
11610 /* Property Tables Stuff. */
11612 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11613 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11614 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11616 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11617 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11619 static bfd_boolean
get_frag_is_literal (const fragS
*);
11620 static void xtensa_create_property_segments
11621 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11622 static void xtensa_create_xproperty_segments
11623 (frag_flags_fn
, const char *, xt_section_type
);
11624 static bfd_boolean
exclude_section_from_property_tables (segT
);
11625 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11626 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11627 static void add_xt_block_frags
11628 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11629 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11630 static void xtensa_frag_flags_init (frag_flags
*);
11631 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11632 static flagword
frag_flags_to_number (const frag_flags
*);
11633 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11635 /* Set up property tables after relaxation. */
11638 xtensa_post_relax_hook (void)
11640 xtensa_move_seg_list_to_beginning (literal_head
);
11642 xtensa_find_unmarked_state_frags ();
11643 xtensa_mark_frags_for_org ();
11644 xtensa_mark_difference_of_two_symbols ();
11646 xtensa_create_property_segments (get_frag_is_literal
,
11648 XTENSA_LIT_SEC_NAME
,
11650 xtensa_create_xproperty_segments (get_frag_property_flags
,
11651 XTENSA_PROP_SEC_NAME
,
11654 if (warn_unaligned_branch_targets
)
11655 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11656 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11660 /* This function is only meaningful after xtensa_move_literals. */
11663 get_frag_is_literal (const fragS
*fragP
)
11665 gas_assert (fragP
!= NULL
);
11666 return fragP
->tc_frag_data
.is_literal
;
11671 xtensa_create_property_segments (frag_predicate property_function
,
11672 frag_predicate end_property_function
,
11673 const char *section_name_base
,
11674 xt_section_type sec_type
)
11678 /* Walk over all of the current segments.
11679 Walk over each fragment
11680 For each non-empty fragment,
11681 Build a property record (append where possible). */
11683 for (seclist
= &stdoutput
->sections
;
11684 seclist
&& *seclist
;
11685 seclist
= &(*seclist
)->next
)
11687 segT sec
= *seclist
;
11689 if (exclude_section_from_property_tables (sec
))
11692 if (section_has_property (sec
, property_function
))
11694 segment_info_type
*xt_seg_info
;
11695 xtensa_block_info
**xt_blocks
;
11696 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11698 prop_sec
->output_section
= prop_sec
;
11699 subseg_set (prop_sec
, 0);
11700 xt_seg_info
= seg_info (prop_sec
);
11701 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11703 /* Walk over all of the frchains here and add new sections. */
11704 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11705 end_property_function
);
11709 /* Now we fill them out.... */
11711 for (seclist
= &stdoutput
->sections
;
11712 seclist
&& *seclist
;
11713 seclist
= &(*seclist
)->next
)
11715 segment_info_type
*seginfo
;
11716 xtensa_block_info
*block
;
11717 segT sec
= *seclist
;
11719 seginfo
= seg_info (sec
);
11720 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11724 xtensa_block_info
*cur_block
;
11726 bfd_size_type rec_size
;
11728 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11731 rec_size
= num_recs
* 8;
11732 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11739 subseg_set (sec
, 0);
11740 frag_data
= frag_more (rec_size
);
11742 for (i
= 0; i
< num_recs
; i
++)
11746 /* Write the fixup. */
11747 gas_assert (cur_block
);
11748 fix
= fix_new (frag_now
, i
* 8, 4,
11749 section_symbol (cur_block
->sec
),
11751 FALSE
, BFD_RELOC_32
);
11752 fix
->fx_file
= "<internal>";
11755 /* Write the length. */
11756 md_number_to_chars (&frag_data
[4 + i
* 8],
11757 cur_block
->size
, 4);
11758 cur_block
= cur_block
->next
;
11760 frag_wane (frag_now
);
11762 frag_wane (frag_now
);
11770 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11771 const char *section_name_base
,
11772 xt_section_type sec_type
)
11776 /* Walk over all of the current segments.
11777 Walk over each fragment.
11778 For each fragment that has instructions,
11779 build an instruction record (append where possible). */
11781 for (seclist
= &stdoutput
->sections
;
11782 seclist
&& *seclist
;
11783 seclist
= &(*seclist
)->next
)
11785 segT sec
= *seclist
;
11787 if (exclude_section_from_property_tables (sec
))
11790 if (section_has_xproperty (sec
, flag_fn
))
11792 segment_info_type
*xt_seg_info
;
11793 xtensa_block_info
**xt_blocks
;
11794 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11796 prop_sec
->output_section
= prop_sec
;
11797 subseg_set (prop_sec
, 0);
11798 xt_seg_info
= seg_info (prop_sec
);
11799 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11801 /* Walk over all of the frchains here and add new sections. */
11802 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11806 /* Now we fill them out.... */
11808 for (seclist
= &stdoutput
->sections
;
11809 seclist
&& *seclist
;
11810 seclist
= &(*seclist
)->next
)
11812 segment_info_type
*seginfo
;
11813 xtensa_block_info
*block
;
11814 segT sec
= *seclist
;
11816 seginfo
= seg_info (sec
);
11817 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11821 xtensa_block_info
*cur_block
;
11823 bfd_size_type rec_size
;
11825 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11828 rec_size
= num_recs
* (8 + 4);
11829 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11830 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11837 subseg_set (sec
, 0);
11838 frag_data
= frag_more (rec_size
);
11840 for (i
= 0; i
< num_recs
; i
++)
11844 /* Write the fixup. */
11845 gas_assert (cur_block
);
11846 fix
= fix_new (frag_now
, i
* 12, 4,
11847 section_symbol (cur_block
->sec
),
11849 FALSE
, BFD_RELOC_32
);
11850 fix
->fx_file
= "<internal>";
11853 /* Write the length. */
11854 md_number_to_chars (&frag_data
[4 + i
* 12],
11855 cur_block
->size
, 4);
11856 md_number_to_chars (&frag_data
[8 + i
* 12],
11857 frag_flags_to_number (&cur_block
->flags
),
11858 sizeof (flagword
));
11859 cur_block
= cur_block
->next
;
11861 frag_wane (frag_now
);
11863 frag_wane (frag_now
);
11871 exclude_section_from_property_tables (segT sec
)
11873 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11875 /* Sections that don't contribute to the memory footprint are excluded. */
11876 if ((flags
& SEC_DEBUGGING
)
11877 || !(flags
& SEC_ALLOC
)
11878 || (flags
& SEC_MERGE
))
11881 /* Linker cie and fde optimizations mess up property entries for
11882 eh_frame sections, but there is nothing inside them relevant to
11883 property tables anyway. */
11884 if (strcmp (sec
->name
, ".eh_frame") == 0)
11892 section_has_property (segT sec
, frag_predicate property_function
)
11894 segment_info_type
*seginfo
= seg_info (sec
);
11897 if (seginfo
&& seginfo
->frchainP
)
11899 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11901 if (property_function (fragP
)
11902 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11911 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11913 segment_info_type
*seginfo
= seg_info (sec
);
11916 if (seginfo
&& seginfo
->frchainP
)
11918 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11920 frag_flags prop_flags
;
11921 property_function (fragP
, &prop_flags
);
11922 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11930 /* Two types of block sections exist right now: literal and insns. */
11933 add_xt_block_frags (segT sec
,
11934 xtensa_block_info
**xt_block
,
11935 frag_predicate property_function
,
11936 frag_predicate end_property_function
)
11940 /* Build it if needed. */
11941 while (*xt_block
!= NULL
)
11942 xt_block
= &(*xt_block
)->next
;
11943 /* We are either at NULL at the beginning or at the end. */
11945 /* Walk through the frags. */
11946 if (seg_info (sec
)->frchainP
)
11948 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11950 fragP
= fragP
->fr_next
)
11952 if (property_function (fragP
)
11953 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11955 if (*xt_block
!= NULL
)
11957 if ((*xt_block
)->offset
+ (*xt_block
)->size
11958 == fragP
->fr_address
)
11959 (*xt_block
)->size
+= fragP
->fr_fix
;
11961 xt_block
= &((*xt_block
)->next
);
11963 if (*xt_block
== NULL
)
11965 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
11966 new_block
->sec
= sec
;
11967 new_block
->offset
= fragP
->fr_address
;
11968 new_block
->size
= fragP
->fr_fix
;
11969 new_block
->next
= NULL
;
11970 xtensa_frag_flags_init (&new_block
->flags
);
11971 *xt_block
= new_block
;
11973 if (end_property_function
11974 && end_property_function (fragP
))
11976 xt_block
= &((*xt_block
)->next
);
11984 /* Break the encapsulation of add_xt_prop_frags here. */
11987 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
11989 if (prop_flags
->is_literal
11990 || prop_flags
->is_insn
11991 || prop_flags
->is_data
11992 || prop_flags
->is_unreachable
)
11999 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12001 memset (prop_flags
, 0, sizeof (frag_flags
));
12006 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12008 xtensa_frag_flags_init (prop_flags
);
12009 if (fragP
->tc_frag_data
.is_literal
)
12010 prop_flags
->is_literal
= TRUE
;
12011 if (fragP
->tc_frag_data
.is_specific_opcode
12012 || fragP
->tc_frag_data
.is_no_transform
)
12014 prop_flags
->is_no_transform
= TRUE
;
12015 if (xtensa_frag_flags_is_empty (prop_flags
))
12016 prop_flags
->is_data
= TRUE
;
12018 if (fragP
->tc_frag_data
.is_unreachable
)
12019 prop_flags
->is_unreachable
= TRUE
;
12020 else if (fragP
->tc_frag_data
.is_insn
)
12022 prop_flags
->is_insn
= TRUE
;
12023 if (fragP
->tc_frag_data
.is_loop_target
)
12024 prop_flags
->insn
.is_loop_target
= TRUE
;
12025 if (fragP
->tc_frag_data
.is_branch_target
)
12026 prop_flags
->insn
.is_branch_target
= TRUE
;
12027 if (fragP
->tc_frag_data
.is_no_density
)
12028 prop_flags
->insn
.is_no_density
= TRUE
;
12029 if (fragP
->tc_frag_data
.use_absolute_literals
)
12030 prop_flags
->insn
.is_abslit
= TRUE
;
12032 if (fragP
->tc_frag_data
.is_align
)
12034 prop_flags
->is_align
= TRUE
;
12035 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12036 if (xtensa_frag_flags_is_empty (prop_flags
))
12037 prop_flags
->is_data
= TRUE
;
12043 frag_flags_to_number (const frag_flags
*prop_flags
)
12046 if (prop_flags
->is_literal
)
12047 num
|= XTENSA_PROP_LITERAL
;
12048 if (prop_flags
->is_insn
)
12049 num
|= XTENSA_PROP_INSN
;
12050 if (prop_flags
->is_data
)
12051 num
|= XTENSA_PROP_DATA
;
12052 if (prop_flags
->is_unreachable
)
12053 num
|= XTENSA_PROP_UNREACHABLE
;
12054 if (prop_flags
->insn
.is_loop_target
)
12055 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12056 if (prop_flags
->insn
.is_branch_target
)
12058 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12059 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12062 if (prop_flags
->insn
.is_no_density
)
12063 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12064 if (prop_flags
->is_no_transform
)
12065 num
|= XTENSA_PROP_NO_TRANSFORM
;
12066 if (prop_flags
->insn
.is_no_reorder
)
12067 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12068 if (prop_flags
->insn
.is_abslit
)
12069 num
|= XTENSA_PROP_INSN_ABSLIT
;
12071 if (prop_flags
->is_align
)
12073 num
|= XTENSA_PROP_ALIGN
;
12074 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12082 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12083 const frag_flags
*prop_flags_2
)
12085 /* Cannot combine with an end marker. */
12087 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12089 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12091 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12094 if (prop_flags_1
->is_insn
)
12096 /* Properties of the beginning of the frag. */
12097 if (prop_flags_2
->insn
.is_loop_target
)
12099 if (prop_flags_2
->insn
.is_branch_target
)
12101 if (prop_flags_1
->insn
.is_no_density
!=
12102 prop_flags_2
->insn
.is_no_density
)
12104 if (prop_flags_1
->is_no_transform
!=
12105 prop_flags_2
->is_no_transform
)
12107 if (prop_flags_1
->insn
.is_no_reorder
!=
12108 prop_flags_2
->insn
.is_no_reorder
)
12110 if (prop_flags_1
->insn
.is_abslit
!=
12111 prop_flags_2
->insn
.is_abslit
)
12115 if (prop_flags_1
->is_align
)
12123 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12126 unsigned align_bits
;
12128 if (!xt_block
->flags
.is_align
)
12129 return xt_block
->size
;
12131 end_addr
= xt_block
->offset
+ xt_block
->size
;
12132 align_bits
= xt_block
->flags
.alignment
;
12133 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12134 return end_addr
- xt_block
->offset
;
12139 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12140 const xtensa_block_info
*xt_block_2
)
12142 if (xt_block
->sec
!= xt_block_2
->sec
)
12144 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12145 != xt_block_2
->offset
)
12148 if (xt_block_2
->size
== 0
12149 && (!xt_block_2
->flags
.is_unreachable
12150 || xt_block
->flags
.is_unreachable
))
12152 if (xt_block_2
->flags
.is_align
12153 && xt_block
->flags
.is_align
)
12155 /* Nothing needed. */
12156 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12161 if (xt_block_2
->flags
.is_align
)
12163 /* Push alignment to previous entry. */
12164 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12165 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12170 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12171 &xt_block_2
->flags
))
12174 xt_block
->size
+= xt_block_2
->size
;
12176 if (xt_block_2
->flags
.is_align
)
12178 xt_block
->flags
.is_align
= TRUE
;
12179 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12187 add_xt_prop_frags (segT sec
,
12188 xtensa_block_info
**xt_block
,
12189 frag_flags_fn property_function
)
12193 /* Build it if needed. */
12194 while (*xt_block
!= NULL
)
12196 xt_block
= &(*xt_block
)->next
;
12198 /* We are either at NULL at the beginning or at the end. */
12200 /* Walk through the frags. */
12201 if (seg_info (sec
)->frchainP
)
12203 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12204 fragP
= fragP
->fr_next
)
12206 xtensa_block_info tmp_block
;
12207 tmp_block
.sec
= sec
;
12208 tmp_block
.offset
= fragP
->fr_address
;
12209 tmp_block
.size
= fragP
->fr_fix
;
12210 tmp_block
.next
= NULL
;
12211 property_function (fragP
, &tmp_block
.flags
);
12213 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12214 /* && fragP->fr_fix != 0) */
12216 if ((*xt_block
) == NULL
12217 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12219 xtensa_block_info
*new_block
;
12220 if ((*xt_block
) != NULL
)
12221 xt_block
= &(*xt_block
)->next
;
12222 new_block
= XNEW (xtensa_block_info
);
12223 *new_block
= tmp_block
;
12224 *xt_block
= new_block
;
12232 /* op_placement_info_table */
12234 /* op_placement_info makes it easier to determine which
12235 ops can go in which slots. */
12238 init_op_placement_info_table (void)
12240 xtensa_isa isa
= xtensa_default_isa
;
12241 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12242 xtensa_opcode opcode
;
12245 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12247 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12248 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12250 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12252 op_placement_info
*opi
= &op_placement_table
[opcode
];
12253 /* FIXME: Make tinsn allocation dynamic. */
12254 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12255 as_fatal (_("too many operands in instruction"));
12256 opi
->narrowest
= XTENSA_UNDEFINED
;
12257 opi
->narrowest_size
= 0x7F;
12258 opi
->narrowest_slot
= 0;
12260 opi
->num_formats
= 0;
12262 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12264 opi
->slots
[fmt
] = 0;
12265 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12267 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12269 int fmt_length
= xtensa_format_length (isa
, fmt
);
12271 set_bit (fmt
, opi
->formats
);
12272 set_bit (slot
, opi
->slots
[fmt
]);
12273 if (fmt_length
< opi
->narrowest_size
12274 || (fmt_length
== opi
->narrowest_size
12275 && (xtensa_format_num_slots (isa
, fmt
)
12276 < xtensa_format_num_slots (isa
,
12279 opi
->narrowest
= fmt
;
12280 opi
->narrowest_size
= fmt_length
;
12281 opi
->narrowest_slot
= slot
;
12286 opi
->num_formats
++;
12289 xtensa_insnbuf_free (isa
, ibuf
);
12294 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12296 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12300 /* If the opcode is available in a single slot format, return its size. */
12303 xg_get_single_size (xtensa_opcode opcode
)
12305 return op_placement_table
[opcode
].narrowest_size
;
12309 static xtensa_format
12310 xg_get_single_format (xtensa_opcode opcode
)
12312 return op_placement_table
[opcode
].narrowest
;
12317 xg_get_single_slot (xtensa_opcode opcode
)
12319 return op_placement_table
[opcode
].narrowest_slot
;
12323 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12326 istack_init (IStack
*stack
)
12333 istack_empty (IStack
*stack
)
12335 return (stack
->ninsn
== 0);
12340 istack_full (IStack
*stack
)
12342 return (stack
->ninsn
== MAX_ISTACK
);
12346 /* Return a pointer to the top IStack entry.
12347 It is an error to call this if istack_empty () is TRUE. */
12350 istack_top (IStack
*stack
)
12352 int rec
= stack
->ninsn
- 1;
12353 gas_assert (!istack_empty (stack
));
12354 return &stack
->insn
[rec
];
12358 /* Add a new TInsn to an IStack.
12359 It is an error to call this if istack_full () is TRUE. */
12362 istack_push (IStack
*stack
, TInsn
*insn
)
12364 int rec
= stack
->ninsn
;
12365 gas_assert (!istack_full (stack
));
12366 stack
->insn
[rec
] = *insn
;
12371 /* Clear space for the next TInsn on the IStack and return a pointer
12372 to it. It is an error to call this if istack_full () is TRUE. */
12375 istack_push_space (IStack
*stack
)
12377 int rec
= stack
->ninsn
;
12379 gas_assert (!istack_full (stack
));
12380 insn
= &stack
->insn
[rec
];
12387 /* Remove the last pushed instruction. It is an error to call this if
12388 istack_empty () returns TRUE. */
12391 istack_pop (IStack
*stack
)
12393 int rec
= stack
->ninsn
- 1;
12394 gas_assert (!istack_empty (stack
));
12396 tinsn_init (&stack
->insn
[rec
]);
12400 /* TInsn functions. */
12403 tinsn_init (TInsn
*dst
)
12405 memset (dst
, 0, sizeof (TInsn
));
12409 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12412 tinsn_has_symbolic_operands (const TInsn
*insn
)
12415 int n
= insn
->ntok
;
12417 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12419 for (i
= 0; i
< n
; ++i
)
12421 switch (insn
->tok
[i
].X_op
)
12435 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12437 xtensa_isa isa
= xtensa_default_isa
;
12439 int n
= insn
->ntok
;
12441 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12443 for (i
= 0; i
< n
; ++i
)
12445 switch (insn
->tok
[i
].X_op
)
12453 /* Errors for these types are caught later. */
12458 /* Symbolic immediates are only allowed on the last immediate
12459 operand. At this time, CONST16 is the only opcode where we
12460 support non-PC-relative relocations. */
12461 if (i
!= get_relaxable_immed (insn
->opcode
)
12462 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12463 && insn
->opcode
!= xtensa_const16_opcode
))
12465 as_bad (_("invalid symbolic operand"));
12474 /* For assembly code with complex expressions (e.g. subtraction),
12475 we have to build them in the literal pool so that
12476 their results are calculated correctly after relaxation.
12477 The relaxation only handles expressions that
12478 boil down to SYMBOL + OFFSET. */
12481 tinsn_has_complex_operands (const TInsn
*insn
)
12484 int n
= insn
->ntok
;
12485 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12486 for (i
= 0; i
< n
; ++i
)
12488 switch (insn
->tok
[i
].X_op
)
12504 /* Encode a TInsn opcode and its constant operands into slotbuf.
12505 Return TRUE if there is a symbol in the immediate field. This
12506 function assumes that:
12507 1) The number of operands are correct.
12508 2) The insn_type is ITYPE_INSN.
12509 3) The opcode can be encoded in the specified format and slot.
12510 4) Operands are either O_constant or O_symbol, and all constants fit. */
12513 tinsn_to_slotbuf (xtensa_format fmt
,
12516 xtensa_insnbuf slotbuf
)
12518 xtensa_isa isa
= xtensa_default_isa
;
12519 xtensa_opcode opcode
= tinsn
->opcode
;
12520 bfd_boolean has_fixup
= FALSE
;
12521 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12524 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12525 if (noperands
!= tinsn
->ntok
)
12526 as_fatal (_("operand number mismatch"));
12528 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12530 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12531 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12535 for (i
= 0; i
< noperands
; i
++)
12537 expressionS
*exp
= &tinsn
->tok
[i
];
12540 const char *file_name
;
12546 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12548 /* The register number has already been checked in
12549 expression_maybe_register, so we don't need to check here. */
12550 opnd_value
= exp
->X_add_number
;
12551 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12552 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12555 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12559 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12561 file_name
= as_where (&line
);
12562 /* It is a constant and we called this function
12563 then we have to try to fit it. */
12564 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12565 exp
->X_add_number
, file_name
, line
);
12578 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12579 into a multi-slot instruction, fill the other slots with NOPs.
12580 Return TRUE if there is a symbol in the immediate field. See also the
12581 assumptions listed for tinsn_to_slotbuf. */
12584 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12586 static xtensa_insnbuf slotbuf
= 0;
12587 static vliw_insn vinsn
;
12588 xtensa_isa isa
= xtensa_default_isa
;
12589 bfd_boolean has_fixup
= FALSE
;
12594 slotbuf
= xtensa_insnbuf_alloc (isa
);
12595 xg_init_vinsn (&vinsn
);
12598 xg_clear_vinsn (&vinsn
);
12600 bundle_tinsn (tinsn
, &vinsn
);
12602 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12604 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12606 /* Only one slot may have a fix-up because the rest contains NOPs. */
12608 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12609 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12616 /* Check the instruction arguments. Return TRUE on failure. */
12619 tinsn_check_arguments (const TInsn
*insn
)
12621 xtensa_isa isa
= xtensa_default_isa
;
12622 xtensa_opcode opcode
= insn
->opcode
;
12623 xtensa_regfile t1_regfile
, t2_regfile
;
12624 int t1_reg
, t2_reg
;
12625 int t1_base_reg
, t1_last_reg
;
12626 int t2_base_reg
, t2_last_reg
;
12627 char t1_inout
, t2_inout
;
12630 if (opcode
== XTENSA_UNDEFINED
)
12632 as_bad (_("invalid opcode"));
12636 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12638 as_bad (_("too few operands"));
12642 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12644 as_bad (_("too many operands"));
12648 /* Check registers. */
12649 for (j
= 0; j
< insn
->ntok
; j
++)
12651 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12654 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12655 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12657 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12659 for (i
= 0; i
< insn
->ntok
; i
++)
12664 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12667 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12669 if (t1_regfile
!= t2_regfile
)
12672 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12673 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12675 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12676 t1_last_reg
= (t1_base_reg
12677 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12679 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12681 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12683 if (t1_reg
!= t2_reg
)
12686 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12688 as_bad (_("multiple writes to the same register"));
12699 /* Load an instruction from its encoded form. */
12702 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12706 xg_init_vinsn (&vinsn
);
12707 vinsn_from_chars (&vinsn
, f
);
12709 *tinsn
= vinsn
.slots
[slot
];
12710 xg_free_vinsn (&vinsn
);
12715 tinsn_from_insnbuf (TInsn
*tinsn
,
12716 xtensa_insnbuf slotbuf
,
12721 xtensa_isa isa
= xtensa_default_isa
;
12723 /* Find the immed. */
12724 tinsn_init (tinsn
);
12725 tinsn
->insn_type
= ITYPE_INSN
;
12726 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12727 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12728 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12729 for (i
= 0; i
< tinsn
->ntok
; i
++)
12731 set_expr_const (&tinsn
->tok
[i
],
12732 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12733 tinsn
->opcode
, i
));
12738 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12741 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12743 xtensa_opcode opcode
= tinsn
->opcode
;
12746 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12748 opnum
= get_relaxable_immed (opcode
);
12749 gas_assert (opnum
>= 0);
12750 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12751 fragP
->tc_frag_data
.slot_symbols
[slot
],
12752 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12754 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12759 get_num_stack_text_bytes (IStack
*istack
)
12762 int text_bytes
= 0;
12764 for (i
= 0; i
< istack
->ninsn
; i
++)
12766 TInsn
*tinsn
= &istack
->insn
[i
];
12767 if (tinsn
->insn_type
== ITYPE_INSN
)
12768 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12775 get_num_stack_literal_bytes (IStack
*istack
)
12780 for (i
= 0; i
< istack
->ninsn
; i
++)
12782 TInsn
*tinsn
= &istack
->insn
[i
];
12783 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12790 /* vliw_insn functions. */
12793 xg_init_vinsn (vliw_insn
*v
)
12796 xtensa_isa isa
= xtensa_default_isa
;
12798 xg_clear_vinsn (v
);
12800 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12801 if (v
->insnbuf
== NULL
)
12802 as_fatal (_("out of memory"));
12804 for (i
= 0; i
< config_max_slots
; i
++)
12806 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12807 if (v
->slotbuf
[i
] == NULL
)
12808 as_fatal (_("out of memory"));
12814 xg_clear_vinsn (vliw_insn
*v
)
12818 memset (v
, 0, offsetof (vliw_insn
, slots
)
12819 + sizeof(TInsn
) * config_max_slots
);
12821 v
->format
= XTENSA_UNDEFINED
;
12823 v
->inside_bundle
= FALSE
;
12825 if (xt_saved_debug_type
!= DEBUG_NONE
)
12826 debug_type
= xt_saved_debug_type
;
12828 for (i
= 0; i
< config_max_slots
; i
++)
12829 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12834 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12837 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12838 dst
->insnbuf
= src
->insnbuf
;
12839 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12844 vinsn_has_specific_opcodes (vliw_insn
*v
)
12848 for (i
= 0; i
< v
->num_slots
; i
++)
12850 if (v
->slots
[i
].is_specific_opcode
)
12858 xg_free_vinsn (vliw_insn
*v
)
12861 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12862 for (i
= 0; i
< config_max_slots
; i
++)
12863 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12867 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12868 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12871 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12874 bfd_boolean record_fixup
)
12876 xtensa_isa isa
= xtensa_default_isa
;
12877 xtensa_format fmt
= vinsn
->format
;
12878 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12880 bfd_boolean has_fixup
= FALSE
;
12882 xtensa_format_encode (isa
, fmt
, insnbuf
);
12884 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12886 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12887 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12888 bfd_boolean tinsn_has_fixup
=
12889 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12890 vinsn
->slotbuf
[slot
]);
12892 xtensa_format_set_slot (isa
, fmt
, slot
,
12893 insnbuf
, vinsn
->slotbuf
[slot
]);
12894 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12896 if (vinsn
->num_slots
!= 1)
12897 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12898 else if (record_fixup
)
12899 /* Instructions that generate TLS relocations should always be
12900 relaxed in the front-end. If "record_fixup" is set, then this
12901 function is being called during back-end relaxation, so flag
12902 the unexpected behavior as an error. */
12903 as_bad (_("unexpected TLS relocation"));
12905 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12906 xtensa_format_length (isa
, fmt
),
12907 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12908 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12910 if (tinsn_has_fixup
)
12913 xtensa_opcode opcode
= tinsn
->opcode
;
12914 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12917 for (i
= 0; i
< noperands
; i
++)
12919 expressionS
* exp
= &tinsn
->tok
[i
];
12925 if (get_relaxable_immed (opcode
) == i
)
12927 /* Add a fix record for the instruction, except if this
12928 function is being called prior to relaxation, i.e.,
12929 if record_fixup is false, and the instruction might
12930 be relaxed later. */
12932 || tinsn
->is_specific_opcode
12933 || !xg_is_relaxable_insn (tinsn
, 0))
12935 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12936 frag_offset
- fragP
->fr_literal
);
12940 if (exp
->X_op
!= O_symbol
)
12941 as_bad (_("invalid operand"));
12942 tinsn
->symbol
= exp
->X_add_symbol
;
12943 tinsn
->offset
= exp
->X_add_number
;
12947 as_bad (_("symbolic operand not allowed"));
12955 as_bad (_("expression too complex"));
12967 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12969 static xtensa_insnbuf insnbuf
= NULL
;
12970 static xtensa_insnbuf slotbuf
= NULL
;
12973 xtensa_isa isa
= xtensa_default_isa
;
12977 insnbuf
= xtensa_insnbuf_alloc (isa
);
12978 slotbuf
= xtensa_insnbuf_alloc (isa
);
12981 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12982 fmt
= xtensa_format_decode (isa
, insnbuf
);
12983 if (fmt
== XTENSA_UNDEFINED
)
12984 as_fatal (_("cannot decode instruction format"));
12985 vinsn
->format
= fmt
;
12986 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12988 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12990 TInsn
*tinsn
= &vinsn
->slots
[i
];
12991 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
12992 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
12997 /* Expression utilities. */
12999 /* Return TRUE if the expression is an integer constant. */
13002 expr_is_const (const expressionS
*s
)
13004 return (s
->X_op
== O_constant
);
13008 /* Get the expression constant.
13009 Calling this is illegal if expr_is_const () returns TRUE. */
13012 get_expr_const (const expressionS
*s
)
13014 gas_assert (expr_is_const (s
));
13015 return s
->X_add_number
;
13019 /* Set the expression to a constant value. */
13022 set_expr_const (expressionS
*s
, offsetT val
)
13024 s
->X_op
= O_constant
;
13025 s
->X_add_number
= val
;
13026 s
->X_add_symbol
= NULL
;
13027 s
->X_op_symbol
= NULL
;
13032 expr_is_register (const expressionS
*s
)
13034 return (s
->X_op
== O_register
);
13038 /* Get the expression constant.
13039 Calling this is illegal if expr_is_const () returns TRUE. */
13042 get_expr_register (const expressionS
*s
)
13044 gas_assert (expr_is_register (s
));
13045 return s
->X_add_number
;
13049 /* Set the expression to a symbol + constant offset. */
13052 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13054 s
->X_op
= O_symbol
;
13055 s
->X_add_symbol
= sym
;
13056 s
->X_op_symbol
= NULL
; /* unused */
13057 s
->X_add_number
= offset
;
13061 /* Return TRUE if the two expressions are equal. */
13064 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13066 if (s1
->X_op
!= s2
->X_op
)
13068 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13070 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13072 if (s1
->X_add_number
!= s2
->X_add_number
)
13079 copy_expr (expressionS
*dst
, const expressionS
*src
)
13081 memcpy (dst
, src
, sizeof (expressionS
));
13085 /* Support for the "--rename-section" option. */
13087 struct rename_section_struct
13089 const char *old_name
;
13091 struct rename_section_struct
*next
;
13094 static struct rename_section_struct
*section_rename
;
13097 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13098 entries to the section_rename list. Note: Specifying multiple
13099 renamings separated by colons is not documented and is retained only
13100 for backward compatibility. */
13103 build_section_rename (const char *arg
)
13105 struct rename_section_struct
*r
;
13106 char *this_arg
= NULL
;
13107 char *next_arg
= NULL
;
13109 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13111 char *old_name
, *new_name
;
13115 next_arg
= strchr (this_arg
, ':');
13123 old_name
= this_arg
;
13124 new_name
= strchr (this_arg
, '=');
13126 if (*old_name
== '\0')
13128 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13131 if (!new_name
|| new_name
[1] == '\0')
13133 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13140 /* Check for invalid section renaming. */
13141 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13143 if (strcmp (r
->old_name
, old_name
) == 0)
13144 as_bad (_("section %s renamed multiple times"), old_name
);
13145 if (strcmp (r
->new_name
, new_name
) == 0)
13146 as_bad (_("multiple sections remapped to output section %s"),
13151 r
= XNEW (struct rename_section_struct
);
13152 r
->old_name
= xstrdup (old_name
);
13153 r
->new_name
= xstrdup (new_name
);
13154 r
->next
= section_rename
;
13155 section_rename
= r
;
13161 xtensa_section_rename (const char *name
)
13163 struct rename_section_struct
*r
= section_rename
;
13165 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13167 if (strcmp (r
->old_name
, name
) == 0)
13168 return r
->new_name
;
13171 return (char *) name
;