1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 /* Exported constants. */
30 const char comment_chars
[] = ";\0";
31 const char line_comment_chars
[] = "#;\0";
32 const char line_separator_chars
[] = "\0";
33 const char EXP_CHARS
[] = "eE\0";
34 const char FLT_CHARS
[] = "RrDdFfSsHh\0";
36 /* For machine specific options. */
37 const char * md_shortopts
= ""; /* None yet. */
41 OPTION_MARCH
= OPTION_MD_BASE
,
55 OPTION_FP_SINGLE_FORMAT
,
56 OPTION_FP_DOUBLE_FORMAT
,
57 OPTION_COMPAT_LL_PREFIX
,
58 OPTION_COMPAT_COLONLESS
,
62 #define INS_Z80 (1 << 0)
63 #define INS_R800 (1 << 1)
64 #define INS_GBZ80 (1 << 2)
65 #define INS_Z180 (1 << 3)
66 #define INS_EZ80 (1 << 4)
67 #define INS_Z80N (1 << 5)
68 #define INS_MARCH_MASK 0xffff
70 #define INS_IDX_HALF (1 << 16)
71 #define INS_IN_F_C (1 << 17)
72 #define INS_OUT_C_0 (1 << 18)
73 #define INS_SLI (1 << 19)
74 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
75 #define INS_TUNE_MASK 0xffff0000
77 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
80 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
81 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
83 struct option md_longopts
[] =
85 { "march", required_argument
, NULL
, OPTION_MARCH
},
86 { "z80", no_argument
, NULL
, OPTION_MACH_Z80
},
87 { "r800", no_argument
, NULL
, OPTION_MACH_R800
},
88 { "z180", no_argument
, NULL
, OPTION_MACH_Z180
},
89 { "ez80", no_argument
, NULL
, OPTION_MACH_EZ80_Z80
},
90 { "ez80-adl", no_argument
, NULL
, OPTION_MACH_EZ80_ADL
},
91 { "fp-s", required_argument
, NULL
, OPTION_FP_SINGLE_FORMAT
},
92 { "fp-d", required_argument
, NULL
, OPTION_FP_DOUBLE_FORMAT
},
93 { "strict", no_argument
, NULL
, OPTION_MACH_FUD
},
94 { "full", no_argument
, NULL
, OPTION_MACH_IUP
},
95 { "with-inst", required_argument
, NULL
, OPTION_MACH_INST
},
96 { "Wnins", required_argument
, NULL
, OPTION_MACH_INST
},
97 { "without-inst", required_argument
, NULL
, OPTION_MACH_NO_INST
},
98 { "local-prefix", required_argument
, NULL
, OPTION_COMPAT_LL_PREFIX
},
99 { "colonless", no_argument
, NULL
, OPTION_COMPAT_COLONLESS
},
100 { "sdcc", no_argument
, NULL
, OPTION_COMPAT_SDCC
},
101 { "Fins", required_argument
, NULL
, OPTION_MACH_NO_INST
},
102 { "ignore-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_IUD
},
103 { "Wnud", no_argument
, NULL
, OPTION_MACH_IUD
},
104 { "warn-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_WUD
},
105 { "Wud", no_argument
, NULL
, OPTION_MACH_WUD
},
106 { "forbid-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_FUD
},
107 { "Fud", no_argument
, NULL
, OPTION_MACH_FUD
},
108 { "ignore-unportable-instructions", no_argument
, NULL
, OPTION_MACH_IUP
},
109 { "Wnup", no_argument
, NULL
, OPTION_MACH_IUP
},
110 { "warn-unportable-instructions", no_argument
, NULL
, OPTION_MACH_WUP
},
111 { "Wup", no_argument
, NULL
, OPTION_MACH_WUP
},
112 { "forbid-unportable-instructions", no_argument
, NULL
, OPTION_MACH_FUP
},
113 { "Fup", no_argument
, NULL
, OPTION_MACH_FUP
},
115 { NULL
, no_argument
, NULL
, 0 }
118 size_t md_longopts_size
= sizeof (md_longopts
);
120 extern int coff_flags
;
121 /* Instruction classes that silently assembled. */
122 static int ins_ok
= INS_Z80
| INS_UNDOC
;
123 /* Instruction classes that generate errors. */
124 static int ins_err
= ~(INS_Z80
| INS_UNDOC
);
125 /* eZ80 CPU mode (ADL or Z80) */
126 static int cpu_mode
= 0; /* 0 - Z80, 1 - ADL */
127 /* accept SDCC specific instruction encoding */
128 static int sdcc_compat
= 0;
129 /* accept colonless labels */
130 static int colonless_labels
= 0;
131 /* local label prefix (NULL - default) */
132 static const char *local_label_prefix
= NULL
;
133 /* floating point support */
134 typedef const char *(*str_to_float_t
)(char *litP
, int *sizeP
);
135 static str_to_float_t str_to_float
;
136 static str_to_float_t str_to_double
;
138 /* mode of current instruction */
139 #define INST_MODE_S 0 /* short data mode */
140 #define INST_MODE_IS 0 /* short instruction mode */
141 #define INST_MODE_L 2 /* long data mode */
142 #define INST_MODE_IL 1 /* long instruction mode */
143 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
144 static char inst_mode
;
155 static const struct match_info
158 {"z80", INS_Z80
, 0, 0, "Zilog Z80 (+infc+xyhl)" },
159 {"ez80", INS_EZ80
, 0, 0, "Zilog eZ80" },
160 {"gbz80", INS_GBZ80
, INS_UNDOC
|INS_UNPORT
, 0, "GameBoy Z80" },
161 {"r800", INS_R800
, INS_UNPORT
, 0, "Ascii R800" },
162 {"z180", INS_Z180
, INS_UNDOC
|INS_UNPORT
, 0, "Zilog Z180" },
163 {"z80n", INS_Z80N
, 0, 0, "Z80 Next" }
166 static const struct match_info
169 {"full", INS_UNDOC
|INS_UNPORT
, 0, 0, "assemble all known instructions" },
170 {"adl", 0, 0, 1, "eZ80 ADL mode by default" },
171 {"xyhl", INS_IDX_HALF
, 0, 0, "instructions with halves of index registers" },
172 {"infc", INS_IN_F_C
, 0, 0, "instruction IN F,(C)" },
173 {"outc0", INS_OUT_C_0
, 0, 0, "instruction OUT (C),0" },
174 {"sli", INS_SLI
, 0, 0, "instruction known as SLI, SLL, or SL1" },
175 {"xdcb", INS_ROT_II_LD
, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" }
179 setup_march (const char *name
, int *ok
, int *err
, int *mode
)
182 size_t len
= strcspn (name
, "+-");
183 for (i
= 0; i
< ARRAY_SIZE (match_cpu_table
); ++i
)
184 if (!strncasecmp (name
, match_cpu_table
[i
].name
, len
)
185 && strlen (match_cpu_table
[i
].name
) == len
)
187 *ok
= match_cpu_table
[i
].ins_ok
;
188 *err
= match_cpu_table
[i
].ins_err
;
189 *mode
= match_cpu_table
[i
].cpu_mode
;
193 if (i
>= ARRAY_SIZE (match_cpu_table
))
194 as_fatal (_("Invalid CPU is specified: %s"), name
);
198 name
= &name
[len
+ 1];
199 len
= strcspn (name
, "+-");
200 for (i
= 0; i
< ARRAY_SIZE (match_ext_table
); ++i
)
201 if (!strncasecmp (name
, match_ext_table
[i
].name
, len
)
202 && strlen (match_ext_table
[i
].name
) == len
)
206 *ok
|= match_ext_table
[i
].ins_ok
;
207 *err
&= ~match_ext_table
[i
].ins_ok
;
208 *mode
|= match_ext_table
[i
].cpu_mode
;
212 *ok
&= ~match_ext_table
[i
].ins_ok
;
213 *err
|= match_ext_table
[i
].ins_ok
;
214 *mode
&= ~match_ext_table
[i
].cpu_mode
;
218 if (i
>= ARRAY_SIZE (match_ext_table
))
219 as_fatal (_("Invalid EXTENTION is specified: %s"), name
);
224 setup_instruction (const char *inst
, int *add
, int *sub
)
227 if (!strcmp (inst
, "idx-reg-halves"))
229 else if (!strcmp (inst
, "sli"))
231 else if (!strcmp (inst
, "op-ii-ld"))
233 else if (!strcmp (inst
, "in-f-c"))
235 else if (!strcmp (inst
, "out-c-0"))
245 str_to_zeda32 (char *litP
, int *sizeP
);
247 str_to_float48 (char *litP
, int *sizeP
);
249 str_to_ieee754_h (char *litP
, int *sizeP
);
251 str_to_ieee754_s (char *litP
, int *sizeP
);
253 str_to_ieee754_d (char *litP
, int *sizeP
);
255 static str_to_float_t
256 get_str_to_float (const char *arg
)
258 if (strcasecmp (arg
, "zeda32") == 0)
259 return str_to_zeda32
;
261 if (strcasecmp (arg
, "math48") == 0)
262 return str_to_float48
;
264 if (strcasecmp (arg
, "half") != 0)
265 return str_to_ieee754_h
;
267 if (strcasecmp (arg
, "single") != 0)
268 return str_to_ieee754_s
;
270 if (strcasecmp (arg
, "double") != 0)
271 return str_to_ieee754_d
;
273 if (strcasecmp (arg
, "ieee754") == 0)
274 as_fatal (_("invalid floating point numbers type `%s'"), arg
);
279 setup_instruction_list (const char *list
, int *add
, int *sub
)
286 for (b
= list
; *b
!= '\0';)
293 if (sz
== 0 || sz
>= (int)sizeof (buf
))
295 as_bad (_("invalid INST in command line: %s"), b
);
300 if (setup_instruction (buf
, add
, sub
))
304 as_bad (_("invalid INST in command line: %s"), buf
);
315 md_parse_option (int c
, const char* arg
)
322 setup_march (arg
, & ins_ok
, & ins_err
, & cpu_mode
);
324 case OPTION_MACH_Z80
:
325 setup_march ("z80", & ins_ok
, & ins_err
, & cpu_mode
);
327 case OPTION_MACH_R800
:
328 setup_march ("r800", & ins_ok
, & ins_err
, & cpu_mode
);
330 case OPTION_MACH_Z180
:
331 setup_march ("z180", & ins_ok
, & ins_err
, & cpu_mode
);
333 case OPTION_MACH_EZ80_Z80
:
334 setup_march ("ez80", & ins_ok
, & ins_err
, & cpu_mode
);
336 case OPTION_MACH_EZ80_ADL
:
337 setup_march ("ez80+adl", & ins_ok
, & ins_err
, & cpu_mode
);
339 case OPTION_FP_SINGLE_FORMAT
:
340 str_to_float
= get_str_to_float (arg
);
342 case OPTION_FP_DOUBLE_FORMAT
:
343 str_to_double
= get_str_to_float (arg
);
345 case OPTION_MACH_INST
:
346 if ((ins_ok
& INS_GBZ80
) == 0)
347 return setup_instruction_list (arg
, & ins_ok
, & ins_err
);
349 case OPTION_MACH_NO_INST
:
350 if ((ins_ok
& INS_GBZ80
) == 0)
351 return setup_instruction_list (arg
, & ins_err
, & ins_ok
);
353 case OPTION_MACH_WUD
:
354 case OPTION_MACH_IUD
:
355 if ((ins_ok
& INS_GBZ80
) == 0)
358 ins_err
&= ~INS_UNDOC
;
361 case OPTION_MACH_WUP
:
362 case OPTION_MACH_IUP
:
363 if ((ins_ok
& INS_GBZ80
) == 0)
365 ins_ok
|= INS_UNDOC
| INS_UNPORT
;
366 ins_err
&= ~(INS_UNDOC
| INS_UNPORT
);
369 case OPTION_MACH_FUD
:
370 if ((ins_ok
& (INS_R800
| INS_GBZ80
)) == 0)
372 ins_ok
&= (INS_UNDOC
| INS_UNPORT
);
373 ins_err
|= INS_UNDOC
| INS_UNPORT
;
376 case OPTION_MACH_FUP
:
377 ins_ok
&= ~INS_UNPORT
;
378 ins_err
|= INS_UNPORT
;
380 case OPTION_COMPAT_LL_PREFIX
:
381 local_label_prefix
= (arg
&& *arg
) ? arg
: NULL
;
383 case OPTION_COMPAT_SDCC
:
386 case OPTION_COMPAT_COLONLESS
:
387 colonless_labels
= 1;
395 md_show_usage (FILE * f
)
399 CPU model options:\n\
400 -march=CPU[+EXT...][-EXT...]\n\
401 \t\t\t generate code for CPU, where CPU is one of:\n"));
402 for (i
= 0; i
< ARRAY_SIZE(match_cpu_table
); ++i
)
403 fprintf (f
, " %-8s\t\t %s\n", match_cpu_table
[i
].name
, match_cpu_table
[i
].comment
);
404 fprintf (f
, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n"));
405 for (i
= 0; i
< ARRAY_SIZE(match_ext_table
); ++i
)
406 fprintf (f
, " %-8s\t\t %s\n", match_ext_table
[i
].name
, match_ext_table
[i
].comment
);
408 Compatibility options:\n\
409 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
410 -colonless\t\t permit colonless labels\n\
411 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
412 -fp-s=FORMAT\t\t set single precission FP numbers format\n\
413 -fp-d=FORMAT\t\t set double precission FP numbers format\n\
414 Where FORMAT one of:\n\
415 ieee754\t\t IEEE754 compatible (depends on directive)\n\
416 half\t\t\t IEEE754 half precision (16 bit)\n\
417 single\t\t IEEE754 single precision (32 bit)\n\
418 double\t\t IEEE754 double precision (64 bit)\n\
419 zeda32\t\t Zeda z80float library 32 bit format\n\
420 math48\t\t 48 bit format from Math48 library\n\
422 Default: -march=z80+xyhl+infc\n"));
425 static symbolS
* zero
;
432 #define R_STACKABLE (0x80)
433 #define R_ARITH (0x40)
436 #define R_INDEX (R_IX | R_IY)
445 #define REG_F (6 | 8)
450 #define REG_AF (3 | R_STACKABLE)
451 #define REG_BC (0 | R_STACKABLE | R_ARITH)
452 #define REG_DE (1 | R_STACKABLE | R_ARITH)
453 #define REG_HL (2 | R_STACKABLE | R_ARITH)
454 #define REG_IX (REG_HL | R_IX)
455 #define REG_IY (REG_HL | R_IY)
456 #define REG_SP (3 | R_ARITH)
458 static const struct reg_entry regtable
[] =
473 {"ixh",REG_H
| R_IX
},
474 {"ixl",REG_L
| R_IX
},
476 {"iyh",REG_H
| R_IY
},
477 {"iyl",REG_L
| R_IY
},
484 #define BUFLEN 8 /* Large enough for any keyword. */
489 expressionS nul
, reg
;
491 unsigned int i
, j
, k
;
494 if (ins_ok
& INS_EZ80
) /* if select EZ80 cpu then */
495 listing_lhs_width
= 6; /* use 6 bytes per line in the listing */
497 reg
.X_op
= O_register
;
499 reg
.X_add_symbol
= reg
.X_op_symbol
= 0;
500 for ( i
= 0 ; i
< ARRAY_SIZE ( regtable
) ; ++i
)
502 reg
.X_add_number
= regtable
[i
].number
;
503 k
= strlen ( regtable
[i
].name
);
507 for ( j
= ( 1<<k
) ; j
; --j
)
509 for ( k
= 0 ; regtable
[i
].name
[k
] ; ++k
)
511 buf
[k
] = ( j
& ( 1<<k
) ) ? TOUPPER (regtable
[i
].name
[k
]) : regtable
[i
].name
[k
];
513 symbolS
* psym
= symbol_find_or_make (buf
);
514 S_SET_SEGMENT (psym
, reg_section
);
515 symbol_set_value_expression (psym
, ®
);
519 p
= input_line_pointer
;
520 input_line_pointer
= (char *) "0";
523 input_line_pointer
= p
;
524 zero
= make_expr_symbol (& nul
);
525 /* We do not use relaxation (yet). */
534 switch (ins_ok
& INS_MARCH_MASK
)
537 mach_type
= bfd_mach_z80
;
540 mach_type
= bfd_mach_r800
;
543 mach_type
= bfd_mach_z180
;
546 mach_type
= bfd_mach_gbz80
;
549 mach_type
= cpu_mode
? bfd_mach_ez80_adl
: bfd_mach_ez80_z80
;
552 mach_type
= bfd_mach_z80n
;
557 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_type
);
560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
562 z80_elf_final_processing (void)
563 {/* nothing to do, all is done by BFD itself */
566 elf_elfheader (stdoutput)->e_flags = elf_flags;
572 skip_space (const char *s
)
574 while (*s
== ' ' || *s
== '\t')
579 /* A non-zero return-value causes a continue in the
580 function read_a_source_file () in ../read.c. */
582 z80_start_line_hook (void)
587 /* Convert one character constants. */
588 for (p
= input_line_pointer
; *p
&& *p
!= '\n'; ++p
)
593 if (p
[1] != 0 && p
[1] != '\'' && p
[2] == '\'')
595 snprintf (buf
, 4, "%3d", (unsigned char)p
[1]);
603 for (quote
= *p
++; quote
!= *p
&& '\n' != *p
; ++p
)
607 as_bad (_("-- unterminated string"));
608 ignore_rest_of_line ();
614 *p
= (*skip_space (p
+ 1) == '(') ? '+' : ' ';
618 /* Check for <label>[:] [.](EQU|DEFL) <value>. */
619 if (is_name_beginner (*input_line_pointer
))
622 char c
, *rest
, *line_start
;
625 line_start
= input_line_pointer
;
629 c
= get_symbol_name (&name
);
630 rest
= input_line_pointer
+ 1;
632 if (ISSPACE (c
) && colonless_labels
)
636 bump_line_counters ();
643 /* remove second colon if SDCC compatibility enabled */
648 rest
= (char*)skip_space (rest
);
651 if (strncasecmp (rest
, "EQU", 3) == 0)
653 else if (strncasecmp (rest
, "DEFL", 4) == 0)
657 if (len
&& (!ISALPHA (rest
[len
])))
659 /* Handle assignment here. */
660 if (line_start
[-1] == '\n')
662 bump_line_counters ();
665 input_line_pointer
= rest
+ len
- 1;
666 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
667 equals (name
, len
== 4);
672 /* Restore line and pointer. */
673 (void) restore_line_pointer (c
);
674 input_line_pointer
= line_start
;
681 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
687 md_atof (int type
, char *litP
, int *sizeP
)
696 return str_to_float (litP
, sizeP
);
703 return str_to_double (litP
, sizeP
);
706 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
710 md_section_align (segT seg ATTRIBUTE_UNUSED
, valueT size
)
716 md_pcrel_from (fixS
* fixp
)
718 return fixp
->fx_where
+ fixp
->fx_frag
->fr_address
;
721 typedef const char * (asfunc
)(char, char, const char*);
723 typedef struct _table_t
726 unsigned char prefix
;
727 unsigned char opcode
;
729 unsigned inss
; /*0 - all CPU types or list of supported INS_* */
732 /* Compares the key for structs that start with a char * to the key. */
734 key_cmp (const void * a
, const void * b
)
736 const char *str_a
, *str_b
;
738 str_a
= *((const char**)a
);
739 str_b
= *((const char**)b
);
740 return strcmp (str_a
, str_b
);
744 const char *key
= buf
;
746 /* Prevent an error on a line from also generating
747 a "junk at end of line" error message. */
748 static char err_flag
;
751 error (const char * message
)
756 as_bad ("%s", message
);
763 error (_("illegal operand"));
767 wrong_mach (int ins_type
)
769 if (ins_type
& ins_err
)
772 as_warn (_("undocumented instruction"));
776 check_mach (int ins_type
)
778 if ((ins_type
& ins_ok
) == 0)
779 wrong_mach (ins_type
);
782 /* Check whether an expression is indirect. */
784 is_indir (const char *s
)
790 /* Indirection is indicated with parentheses. */
793 for (p
= s
, depth
= 0; *p
&& *p
!= ','; ++p
)
799 for (quote
= *p
++; quote
!= *p
&& *p
!= '\n'; ++p
)
800 if (*p
== '\\' && p
[1])
810 p
= skip_space (p
+ 1);
816 error (_("mismatched parentheses"));
822 error (_("mismatched parentheses"));
827 /* Check whether a symbol involves a register. */
829 contains_register (symbolS
*sym
)
833 expressionS
* ex
= symbol_get_value_expression (sym
);
842 if (ex
->X_op_symbol
&& contains_register (ex
->X_op_symbol
))
847 if (ex
->X_add_symbol
&& contains_register (ex
->X_add_symbol
))
859 /* Parse general expression, not looking for indexed addressing. */
861 parse_exp_not_indexed (const char *s
, expressionS
*op
)
868 if (sdcc_compat
&& (*p
== '<' || *p
== '>'))
872 case '<': /* LSB request */
875 case '>': /* MSB request */
876 make_shift
= cpu_mode
? 16 : 8;
883 op
->X_md
= indir
= is_indir (p
);
884 if (indir
&& (ins_ok
& INS_GBZ80
))
885 { /* check for instructions like ld a,(hl+), ld (hl-),a */
886 p
= skip_space (p
+1);
887 if (!strncasecmp (p
, "hl", 2))
890 if (*skip_space(p
+1) == ')' && (*p
== '+' || *p
== '-'))
893 op
->X_add_symbol
= NULL
;
894 op
->X_add_number
= (*p
== '+') ? REG_HL
: -REG_HL
;
895 input_line_pointer
= (char*)skip_space(p
+ 1) + 1;
896 return input_line_pointer
;
900 input_line_pointer
= (char*) s
;
905 error (_("missing operand"));
908 error (_("bad expression syntax"));
916 /* replace [op] by [op >> shift] */
918 op
->X_add_symbol
= make_expr_symbol (op
);
919 op
->X_add_number
= 0;
920 op
->X_op
= O_right_shift
;
921 memset (&data
, 0, sizeof (data
));
922 data
.X_op
= O_constant
;
923 data
.X_add_number
= make_shift
;
924 op
->X_op_symbol
= make_expr_symbol (&data
);
926 return input_line_pointer
;
930 unify_indexed (expressionS
*op
)
932 if (O_register
!= symbol_get_value_expression (op
->X_add_symbol
)->X_op
)
935 int rnum
= symbol_get_value_expression (op
->X_add_symbol
)->X_add_number
;
936 if ( ((REG_IX
!= rnum
) && (REG_IY
!= rnum
)) || contains_register (op
->X_op_symbol
))
942 /* Convert subtraction to addition of negative value. */
943 if (O_subtract
== op
->X_op
)
946 minus
.X_op
= O_uminus
;
947 minus
.X_add_number
= 0;
948 minus
.X_add_symbol
= op
->X_op_symbol
;
949 minus
.X_op_symbol
= 0;
950 op
->X_op_symbol
= make_expr_symbol (&minus
);
954 /* Clear X_add_number of the expression. */
955 if (op
->X_add_number
!= 0)
958 memset (&add
, 0, sizeof (add
));
960 add
.X_add_number
= op
->X_add_number
;
961 add
.X_add_symbol
= op
->X_op_symbol
;
963 op
->X_add_symbol
= make_expr_symbol (&add
);
966 op
->X_add_symbol
= op
->X_op_symbol
;
968 op
->X_add_number
= rnum
;
973 /* Parse expression, change operator to O_md1 for indexed addressing. */
975 parse_exp (const char *s
, expressionS
*op
)
977 const char* res
= parse_exp_not_indexed (s
, op
);
982 if (unify_indexed (op
) && op
->X_md
)
986 if (op
->X_md
&& ((REG_IX
== op
->X_add_number
) || (REG_IY
== op
->X_add_number
)))
988 op
->X_add_symbol
= zero
;
993 /* parse SDCC syntax where index register offset placed before parentheses */
994 if (sdcc_compat
&& is_indir (res
))
998 res
= parse_exp (res
, op
);
999 if (op
->X_op
!= O_md1
|| op
->X_add_symbol
!= zero
)
1002 op
->X_add_symbol
= make_expr_symbol (&off
);
1011 /* Condition codes, including some synonyms provided by HiTech zas. */
1012 static const struct reg_entry cc_tab
[] =
1030 /* Parse condition code. */
1032 parse_cc (const char *s
, char * op
)
1036 struct reg_entry
* cc_p
;
1038 for (i
= 0; i
< BUFLEN
; ++i
)
1040 if (!ISALPHA (s
[i
])) /* Condition codes consist of letters only. */
1042 buf
[i
] = TOLOWER (s
[i
]);
1046 && ((s
[i
] == 0) || (s
[i
] == ',')))
1049 cc_p
= bsearch (&key
, cc_tab
, ARRAY_SIZE (cc_tab
),
1050 sizeof (cc_tab
[0]), key_cmp
);
1067 emit_insn (char prefix
, char opcode
, const char * args
)
1082 void z80_cons_fix_new (fragS
*frag_p
, int offset
, int nbytes
, expressionS
*exp
)
1084 bfd_reloc_code_real_type r
[4] =
1092 if (nbytes
< 1 || nbytes
> 4)
1094 as_bad (_("unsupported BFD relocation size %u"), nbytes
);
1098 fix_new_exp (frag_p
, offset
, nbytes
, exp
, 0, r
[nbytes
-1]);
1103 emit_data_val (expressionS
* val
, int size
)
1106 bfd_reloc_code_real_type r_type
;
1108 p
= frag_more (size
);
1109 if (val
->X_op
== O_constant
)
1112 for (i
= 0; i
< size
; ++i
)
1113 p
[i
] = (char)(val
->X_add_number
>> (i
*8));
1119 case 1: r_type
= BFD_RELOC_8
; break;
1120 case 2: r_type
= BFD_RELOC_16
; break;
1121 case 3: r_type
= BFD_RELOC_24
; break;
1122 case 4: r_type
= BFD_RELOC_32
; break;
1123 case 8: r_type
= BFD_RELOC_64
; break;
1125 as_fatal (_("invalid data size %d"), size
);
1128 if ( (val
->X_op
== O_register
)
1129 || (val
->X_op
== O_md1
)
1130 || contains_register (val
->X_add_symbol
)
1131 || contains_register (val
->X_op_symbol
))
1134 if (size
<= 2 && val
->X_op_symbol
)
1136 bfd_boolean simplify
= TRUE
;
1137 int shift
= symbol_get_value_expression (val
->X_op_symbol
)->X_add_number
;
1138 if (val
->X_op
== O_bit_and
&& shift
== (1 << (size
*8))-1)
1140 else if (val
->X_op
!= O_right_shift
)
1147 case 0: r_type
= BFD_RELOC_Z80_BYTE0
; break;
1148 case 8: r_type
= BFD_RELOC_Z80_BYTE1
; break;
1149 case 16: r_type
= BFD_RELOC_Z80_BYTE2
; break;
1150 case 24: r_type
= BFD_RELOC_Z80_BYTE3
; break;
1151 default: simplify
= FALSE
;
1154 else /* if (size == 2) */
1158 case 0: r_type
= BFD_RELOC_Z80_WORD0
; break;
1159 case 16: r_type
= BFD_RELOC_Z80_WORD1
; break;
1160 default: simplify
= FALSE
;
1166 val
->X_op
= O_symbol
;
1167 val
->X_op_symbol
= NULL
;
1168 val
->X_add_number
= 0;
1172 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
, val
, FALSE
, r_type
);
1176 emit_byte (expressionS
* val
, bfd_reloc_code_real_type r_type
)
1180 if (r_type
== BFD_RELOC_8
)
1182 emit_data_val (val
, 1);
1186 *p
= val
->X_add_number
;
1187 if (contains_register (val
->X_add_symbol
) || contains_register (val
->X_op_symbol
))
1191 else if ((r_type
== BFD_RELOC_8_PCREL
) && (val
->X_op
== O_constant
))
1193 as_bad (_("cannot make a relative jump to an absolute location"));
1195 else if (val
->X_op
== O_constant
)
1197 if ((val
->X_add_number
< -128) || (val
->X_add_number
>= 128))
1199 if (r_type
== BFD_RELOC_Z80_DISP8
)
1200 as_bad (_("index overflow (%+ld)"), val
->X_add_number
);
1202 as_bad (_("offset overflow (%+ld)"), val
->X_add_number
);
1207 /* For symbols only, constants are stored at begin of function. */
1208 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 1, val
,
1209 (r_type
== BFD_RELOC_8_PCREL
) ? TRUE
: FALSE
, r_type
);
1214 emit_word (expressionS
* val
)
1216 emit_data_val (val
, (inst_mode
& INST_MODE_IL
) ? 3 : 2);
1220 emit_mx (char prefix
, char opcode
, int shift
, expressionS
* arg
)
1221 /* The operand m may be r, (hl), (ix+d), (iy+d),
1222 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1227 rnum
= arg
->X_add_number
;
1243 if ((prefix
== 0) && (rnum
& R_INDEX
))
1245 prefix
= (rnum
& R_IX
) ? 0xDD : 0xFD;
1246 if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
1247 check_mach (INS_IDX_HALF
);
1256 q
= frag_more (prefix
? 2 : 1);
1259 * q
++ = opcode
+ (rnum
<< shift
);
1262 if (ins_ok
& INS_GBZ80
)
1268 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1269 *q
= (prefix
) ? prefix
: (opcode
+ (6 << shift
));
1271 expressionS offset
= *arg
;
1272 offset
.X_op
= O_symbol
;
1273 offset
.X_add_number
= 0;
1274 emit_byte (&offset
, BFD_RELOC_Z80_DISP8
);
1279 *q
= opcode
+(6<<shift
);
1287 /* The operand m may be r, (hl), (ix+d), (iy+d),
1288 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1290 emit_m (char prefix
, char opcode
, const char *args
)
1295 p
= parse_exp (args
, &arg_m
);
1300 emit_mx (prefix
, opcode
, 0, &arg_m
);
1308 /* The operand m may be as above or one of the undocumented
1309 combinations (ix+d),r and (iy+d),r (if unportable instructions
1313 emit_mr (char prefix
, char opcode
, const char *args
)
1315 expressionS arg_m
, arg_r
;
1318 p
= parse_exp (args
, & arg_m
);
1325 p
= parse_exp (p
+ 1, & arg_r
);
1327 if ((arg_r
.X_md
== 0)
1328 && (arg_r
.X_op
== O_register
)
1329 && (arg_r
.X_add_number
< 8))
1330 opcode
+= arg_r
.X_add_number
- 6; /* Emit_mx () will add 6. */
1336 if (!(ins_ok
& INS_Z80N
))
1337 check_mach (INS_ROT_II_LD
);
1341 emit_mx (prefix
, opcode
, 0, & arg_m
);
1350 emit_sx (char prefix
, char opcode
, expressionS
* arg_p
)
1354 switch (arg_p
->X_op
)
1358 emit_mx (prefix
, opcode
, 0, arg_p
);
1365 q
= frag_more (prefix
? 2 : 1);
1369 emit_byte (arg_p
, BFD_RELOC_8
);
1374 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1376 emit_s (char prefix
, char opcode
, const char *args
)
1381 p
= parse_exp (args
, & arg_s
);
1382 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
1383 { /* possible instruction in generic format op A,x */
1384 if (!(ins_ok
& INS_EZ80
) && !sdcc_compat
)
1387 p
= parse_exp (p
, & arg_s
);
1389 emit_sx (prefix
, opcode
, & arg_s
);
1394 emit_sub (char prefix
, char opcode
, const char *args
)
1399 if (!(ins_ok
& INS_GBZ80
))
1400 return emit_s (prefix
, opcode
, args
);
1401 p
= parse_exp (args
, & arg_s
);
1404 error (_("bad instruction syntax"));
1408 if (arg_s
.X_md
!= 0 || arg_s
.X_op
!= O_register
|| arg_s
.X_add_number
!= REG_A
)
1411 p
= parse_exp (p
, & arg_s
);
1413 emit_sx (prefix
, opcode
, & arg_s
);
1418 emit_swap (char prefix
, char opcode
, const char *args
)
1424 if (!(ins_ok
& INS_Z80N
))
1425 return emit_mr (prefix
, opcode
, args
);
1427 /* check for alias swap a for swapnib of Z80N */
1428 p
= parse_exp (args
, ®
);
1429 if (reg
.X_md
!= 0 || reg
.X_op
!= O_register
|| reg
.X_add_number
!= REG_A
)
1439 emit_call (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1442 const char *p
; char *q
;
1444 p
= parse_exp_not_indexed (args
, &addr
);
1456 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1458 emit_incdec (char prefix
, char opcode
, const char * args
)
1460 expressionS operand
;
1462 const char *p
; char *q
;
1464 p
= parse_exp (args
, &operand
);
1465 rnum
= operand
.X_add_number
;
1466 if ((! operand
.X_md
)
1467 && (operand
.X_op
== O_register
)
1470 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1472 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1473 *q
= prefix
+ ((rnum
& 3) << 4);
1477 if ((operand
.X_op
== O_md1
) || (operand
.X_op
== O_register
))
1478 emit_mx (0, opcode
, 3, & operand
);
1486 emit_jr (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1492 p
= parse_exp_not_indexed (args
, &addr
);
1499 addr
.X_add_number
--; /* pcrel computes after offset code */
1500 emit_byte (&addr
, BFD_RELOC_8_PCREL
);
1506 emit_jp (char prefix
, char opcode
, const char * args
)
1513 p
= parse_exp_not_indexed (args
, & addr
);
1516 rnum
= addr
.X_add_number
;
1517 if ((O_register
== addr
.X_op
) && (REG_HL
== (rnum
& ~R_INDEX
)))
1519 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1521 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1524 else if (addr
.X_op
== O_register
&& rnum
== REG_C
&& (ins_ok
& INS_Z80N
))
1543 emit_im (char prefix
, char opcode
, const char * args
)
1549 p
= parse_exp (args
, & mode
);
1550 if (mode
.X_md
|| (mode
.X_op
!= O_constant
))
1553 switch (mode
.X_add_number
)
1557 ++mode
.X_add_number
;
1562 *q
= opcode
+ 8*mode
.X_add_number
;
1571 emit_pop (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1577 p
= parse_exp (args
, & regp
);
1579 && (regp
.X_op
== O_register
)
1580 && (regp
.X_add_number
& R_STACKABLE
))
1584 rnum
= regp
.X_add_number
;
1588 *q
++ = (rnum
&R_IX
)?0xDD:0xFD;
1592 *q
= opcode
+ ((rnum
& 3) << 4);
1601 emit_push (char prefix
, char opcode
, const char * args
)
1607 p
= parse_exp (args
, & arg
);
1608 if (arg
.X_op
== O_register
)
1609 return emit_pop (prefix
, opcode
, args
);
1611 if (arg
.X_md
|| arg
.X_op
== O_md1
|| !(ins_ok
& INS_Z80N
))
1619 fix_new_exp (frag_now
, q
- frag_now
->fr_literal
, 2, &arg
, FALSE
,
1620 BFD_RELOC_Z80_16_BE
);
1626 emit_retcc (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1631 p
= parse_cc (args
, &cc
);
1637 return p
? p
: args
;
1641 emit_adc (char prefix
, char opcode
, const char * args
)
1648 p
= parse_exp (args
, &term
);
1651 error (_("bad instruction syntax"));
1655 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1658 switch (term
.X_add_number
)
1661 p
= emit_s (0, prefix
, p
);
1664 p
= parse_exp (p
, &term
);
1665 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1667 rnum
= term
.X_add_number
;
1668 if (R_ARITH
== (rnum
& (R_ARITH
| R_INDEX
)))
1672 *q
= opcode
+ ((rnum
& 3) << 4);
1684 emit_add (char prefix
, char opcode
, const char * args
)
1691 p
= parse_exp (args
, &term
);
1694 error (_("bad instruction syntax"));
1698 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1701 switch (term
.X_add_number
)
1704 p
= emit_s (0, prefix
, p
);
1707 p
= parse_exp (p
, &term
);
1708 if (!(ins_ok
& INS_GBZ80
) || term
.X_md
|| term
.X_op
== O_register
)
1712 emit_byte (&term
, BFD_RELOC_Z80_DISP8
);
1716 if (!(ins_ok
& INS_Z80N
))
1725 lhs
= term
.X_add_number
;
1726 p
= parse_exp (p
, &term
);
1727 rhs
= term
.X_add_number
;
1728 if (term
.X_md
!= 0 || term
.X_op
== O_md1
)
1730 else if ((term
.X_op
== O_register
) && (rhs
& R_ARITH
) && (rhs
== lhs
|| (rhs
& ~R_INDEX
) != REG_HL
))
1734 q
= frag_more ((lhs
& R_INDEX
) ? 2 : 1);
1736 *q
++ = (lhs
& R_IX
) ? 0xDD : 0xFD;
1737 *q
= opcode
+ ((rhs
& 3) << 4);
1741 else if (!(lhs
& R_INDEX
) && (ins_ok
& INS_Z80N
))
1743 if (term
.X_op
== O_register
&& rhs
== REG_A
)
1744 { /* ADD BC/DE/HL,A */
1747 *q
= 0x33 - (lhs
& 3);
1750 else if (term
.X_op
!= O_register
&& term
.X_op
!= O_md1
)
1751 { /* ADD BC/DE/HL,nn */
1754 *q
= 0x36 - (lhs
& 3);
1767 emit_bit (char prefix
, char opcode
, const char * args
)
1773 p
= parse_exp (args
, &b
);
1775 error (_("bad instruction syntax"));
1777 bn
= b
.X_add_number
;
1779 && (b
.X_op
== O_constant
)
1784 /* Bit : no optional third operand. */
1785 p
= emit_m (prefix
, opcode
+ (bn
<< 3), p
);
1787 /* Set, res : resulting byte can be copied to register. */
1788 p
= emit_mr (prefix
, opcode
+ (bn
<< 3), p
);
1795 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
1797 emit_bshft (char prefix
, char opcode
, const char * args
)
1803 p
= parse_exp (args
, & r1
);
1805 error (_("bad instruction syntax"));
1806 p
= parse_exp (p
, & r2
);
1807 if (r1
.X_md
|| r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_DE
||
1808 r2
.X_md
|| r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_B
)
1817 emit_jpcc (char prefix
, char opcode
, const char * args
)
1822 p
= parse_cc (args
, & cc
);
1823 if (p
&& *p
++ == ',')
1824 p
= emit_call (0, opcode
+ cc
, p
);
1826 p
= (prefix
== (char)0xC3)
1827 ? emit_jp (0xE9, prefix
, args
)
1828 : emit_call (0, prefix
, args
);
1833 emit_jrcc (char prefix
, char opcode
, const char * args
)
1838 p
= parse_cc (args
, &cc
);
1839 if (p
&& *p
++ == ',')
1842 error (_("condition code invalid for jr"));
1844 p
= emit_jr (0, opcode
+ cc
, p
);
1847 p
= emit_jr (0, prefix
, args
);
1853 emit_ex (char prefix_in ATTRIBUTE_UNUSED
,
1854 char opcode_in ATTRIBUTE_UNUSED
, const char * args
)
1858 char prefix
, opcode
;
1860 p
= parse_exp_not_indexed (args
, &op
);
1864 error (_("bad instruction syntax"));
1868 prefix
= opcode
= 0;
1869 if (op
.X_op
== O_register
)
1870 switch (op
.X_add_number
| (op
.X_md
? 0x8000 : 0))
1873 if (TOLOWER (*p
++) == 'a' && TOLOWER (*p
++) == 'f')
1875 /* The scrubber changes '\'' to '`' in this context. */
1882 if (TOLOWER (*p
++) == 'h' && TOLOWER (*p
++) == 'l')
1886 p
= parse_exp (p
, & op
);
1887 if (op
.X_op
== O_register
1889 && (op
.X_add_number
& ~R_INDEX
) == REG_HL
)
1892 if (R_INDEX
& op
.X_add_number
)
1893 prefix
= (R_IX
& op
.X_add_number
) ? 0xDD : 0xFD;
1898 emit_insn (prefix
, opcode
, p
);
1906 emit_in (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1909 expressionS reg
, port
;
1913 p
= parse_exp (args
, ®
);
1914 if (reg
.X_md
&& reg
.X_op
== O_register
&& reg
.X_add_number
== REG_C
)
1915 { /* permit instruction in (c) as alias for in f,(c) */
1918 reg
.X_add_number
= REG_F
;
1924 error (_("bad instruction syntax"));
1927 p
= parse_exp (p
, &port
);
1930 && reg
.X_op
== O_register
1931 && (reg
.X_add_number
<= 7 || reg
.X_add_number
== REG_F
)
1934 if (port
.X_op
!= O_md1
&& port
.X_op
!= O_register
)
1936 if (REG_A
== reg
.X_add_number
)
1940 emit_byte (&port
, BFD_RELOC_8
);
1947 if (port
.X_add_number
== REG_C
|| port
.X_add_number
== REG_BC
)
1949 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
1951 else if (reg
.X_add_number
== REG_F
&& !(ins_ok
& (INS_R800
|INS_Z80N
)))
1952 check_mach (INS_IN_F_C
);
1955 *q
= 0x40|((reg
.X_add_number
&7)<<3);
1967 emit_in0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1970 expressionS reg
, port
;
1974 p
= parse_exp (args
, ®
);
1977 error (_("bad instruction syntax"));
1981 p
= parse_exp (p
, &port
);
1983 && reg
.X_op
== O_register
1984 && reg
.X_add_number
<= 7
1986 && port
.X_op
!= O_md1
1987 && port
.X_op
!= O_register
)
1991 *q
= 0x00|(reg
.X_add_number
<< 3);
1992 emit_byte (&port
, BFD_RELOC_8
);
2000 emit_out (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2003 expressionS reg
, port
;
2007 p
= parse_exp (args
, & port
);
2010 error (_("bad instruction syntax"));
2013 p
= parse_exp (p
, ®
);
2015 { ill_op (); return p
; }
2016 /* Allow "out (c), 0" as unportable instruction. */
2017 if (reg
.X_op
== O_constant
&& reg
.X_add_number
== 0)
2019 if (!(ins_ok
& INS_Z80N
))
2020 check_mach (INS_OUT_C_0
);
2021 reg
.X_op
= O_register
;
2022 reg
.X_add_number
= 6;
2025 || reg
.X_op
!= O_register
2026 || reg
.X_add_number
> 7)
2029 if (port
.X_op
!= O_register
&& port
.X_op
!= O_md1
)
2031 if (REG_A
== reg
.X_add_number
)
2035 emit_byte (&port
, BFD_RELOC_8
);
2042 if (REG_C
== port
.X_add_number
|| port
.X_add_number
== REG_BC
)
2044 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
2048 *q
= 0x41 | (reg
.X_add_number
<< 3);
2057 emit_out0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2060 expressionS reg
, port
;
2064 p
= parse_exp (args
, & port
);
2067 error (_("bad instruction syntax"));
2070 p
= parse_exp (p
, ®
);
2072 && port
.X_op
!= O_register
2073 && port
.X_op
!= O_md1
2075 && reg
.X_op
== O_register
2076 && reg
.X_add_number
<= 7)
2080 *q
= 0x01 | (reg
.X_add_number
<< 3);
2081 emit_byte (&port
, BFD_RELOC_8
);
2089 emit_rst (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2095 p
= parse_exp_not_indexed (args
, &addr
);
2096 if (addr
.X_op
!= O_constant
)
2098 error ("rst needs constant address");
2102 if (addr
.X_add_number
& ~(7 << 3))
2107 *q
= opcode
+ (addr
.X_add_number
& (7 << 3));
2112 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */
2114 emit_ld_m_n (expressionS
*dst
, expressionS
*src
)
2118 expressionS dst_offset
;
2120 switch (dst
->X_add_number
)
2122 case REG_HL
: prefix
= 0x00; break;
2123 case REG_IX
: prefix
= 0xDD; break;
2124 case REG_IY
: prefix
= 0xFD; break;
2130 q
= frag_more (prefix
? 2 : 1);
2137 dst_offset
.X_op
= O_symbol
;
2138 dst_offset
.X_add_number
= 0;
2139 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2141 emit_byte (src
, BFD_RELOC_8
);
2144 /* For 8-bit load register to memory instructions: LD (<expression>),r. */
2146 emit_ld_m_r (expressionS
*dst
, expressionS
*src
)
2150 expressionS dst_offset
;
2155 if (ins_ok
& INS_GBZ80
)
2156 { /* LD (HL+),A or LD (HL-),A */
2157 if (src
->X_op
!= O_register
|| src
->X_add_number
!= REG_A
)
2159 *frag_more (1) = (dst
->X_add_number
== REG_HL
) ? 0x22 : 0x32;
2163 prefix
= (dst
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2166 switch (dst
->X_add_number
)
2168 case REG_BC
: /* LD (BC),A */
2169 case REG_DE
: /* LD (DE),A */
2170 if (src
->X_add_number
== REG_A
)
2173 *q
= 0x02 | ((dst
->X_add_number
& 3) << 4);
2179 case REG_HL
: /* LD (HL),r or LD (ii+d),r */
2180 if (src
->X_add_number
<= 7)
2182 q
= frag_more (prefix
? 2 : 1);
2185 *q
= 0x70 | src
->X_add_number
;
2189 dst_offset
.X_op
= O_symbol
;
2190 dst_offset
.X_add_number
= 0;
2191 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2199 default: /* LD (nn),A */
2200 if (src
->X_add_number
== REG_A
)
2203 *q
= (ins_ok
& INS_GBZ80
) ? 0xEA : 0x32;
2212 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */
2214 emit_ld_m_rr (expressionS
*dst
, expressionS
*src
)
2219 expressionS dst_offset
;
2223 case O_md1
: /* eZ80 instructions LD (ii+d),rr */
2224 case O_register
: /* eZ80 instructions LD (HL),rr */
2225 if (!(ins_ok
& INS_EZ80
)) /* 16-bit indirect load group is supported by eZ80 only */
2227 switch (dst
->X_add_number
)
2229 case REG_IX
: prefix
= 0xDD; break;
2230 case REG_IY
: prefix
= 0xFD; break;
2231 case REG_HL
: prefix
= 0xED; break;
2235 switch (src
->X_add_number
)
2237 case REG_BC
: opcode
= 0x0F; break;
2238 case REG_DE
: opcode
= 0x1F; break;
2239 case REG_HL
: opcode
= 0x2F; break;
2240 case REG_IX
: opcode
= (prefix
!= 0xFD) ? 0x3F : 0x3E; break;
2241 case REG_IY
: opcode
= (prefix
!= 0xFD) ? 0x3E : 0x3F; break;
2245 q
= frag_more (prefix
? 2 : 1);
2248 if (prefix
== 0xFD || prefix
== 0xDD)
2251 dst_offset
.X_op
= O_symbol
;
2252 dst_offset
.X_add_number
= 0;
2253 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2256 default: /* LD (nn),rr */
2257 if (ins_ok
& INS_GBZ80
)
2259 /* GBZ80 supports only LD (nn),SP */
2260 if (src
->X_add_number
== REG_SP
)
2270 switch (src
->X_add_number
)
2272 case REG_BC
: prefix
= 0xED; opcode
= 0x43; break;
2273 case REG_DE
: prefix
= 0xED; opcode
= 0x53; break;
2274 case REG_HL
: prefix
= 0x00; opcode
= 0x22; break;
2275 case REG_IX
: prefix
= 0xDD; opcode
= 0x22; break;
2276 case REG_IY
: prefix
= 0xFD; opcode
= 0x22; break;
2277 case REG_SP
: prefix
= 0xED; opcode
= 0x73; break;
2282 q
= frag_more (prefix
? 2 : 1);
2291 emit_ld_r_m (expressionS
*dst
, expressionS
*src
)
2292 { /* for 8-bit memory load to register: LD r,(xxx) */
2296 expressionS src_offset
;
2298 if (dst
->X_add_number
== REG_A
&& src
->X_op
== O_register
)
2299 { /* LD A,(BC) or LD A,(DE) */
2300 switch (src
->X_add_number
)
2302 case REG_BC
: opcode
= 0x0A; break;
2303 case REG_DE
: opcode
= 0x1A; break;
2317 if (ins_ok
& INS_GBZ80
)
2318 { /* LD A,(HL+) or LD A,(HL-) */
2319 if (dst
->X_op
== O_register
&& dst
->X_add_number
== REG_A
)
2320 *frag_more (1) = (src
->X_add_number
== REG_HL
) ? 0x2A : 0x3A;
2327 if (dst
->X_add_number
> 7)
2329 opcode
= 0x46; /* LD B,(HL) */
2330 switch (src
->X_add_number
)
2332 case REG_HL
: prefix
= 0x00; break;
2333 case REG_IX
: prefix
= 0xDD; break;
2334 case REG_IY
: prefix
= 0xFD; break;
2338 q
= frag_more (prefix
? 2 : 1);
2341 *q
= opcode
| ((dst
->X_add_number
& 7) << 3);
2345 src_offset
.X_op
= O_symbol
;
2346 src_offset
.X_add_number
= 0;
2347 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2350 default: /* LD A,(nn) */
2351 if (dst
->X_add_number
== REG_A
)
2354 *q
= (ins_ok
& INS_GBZ80
) ? 0xFA : 0x3A;
2361 emit_ld_r_n (expressionS
*dst
, expressionS
*src
)
2362 { /* for 8-bit immediate value load to register: LD r,n */
2366 switch (dst
->X_add_number
)
2389 q
= frag_more (prefix
? 2 : 1);
2392 if (ins_ok
& INS_GBZ80
)
2394 else if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2395 check_mach (INS_IDX_HALF
);
2398 *q
= 0x06 | ((dst
->X_add_number
& 7) << 3);
2399 emit_byte (src
, BFD_RELOC_8
);
2403 emit_ld_r_r (expressionS
*dst
, expressionS
*src
)
2404 { /* mostly 8-bit load register from register instructions: LD r,r */
2405 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2411 switch (dst
->X_add_number
)
2414 switch (src
->X_add_number
)
2416 case REG_HL
: prefix
= 0x00; break;
2417 case REG_IX
: prefix
= 0xDD; break;
2418 case REG_IY
: prefix
= 0xFD; break;
2425 if (!(ins_ok
& INS_EZ80
))
2427 if (src
->X_add_number
!= REG_I
)
2430 error (_("ADL mode instruction"));
2436 if (src
->X_add_number
== REG_HL
)
2438 if (!(ins_ok
& INS_EZ80
))
2441 error (_("ADL mode instruction"));
2445 else if (src
->X_add_number
== REG_A
)
2454 if (!(ins_ok
& INS_EZ80
) || (src
->X_add_number
!= REG_A
))
2457 error (_("ADL mode instruction"));
2462 if (src
->X_add_number
== REG_A
) /* LD R,A */
2471 if (src
->X_add_number
== REG_I
) /* LD A,I */
2477 else if (src
->X_add_number
== REG_R
) /* LD A,R */
2483 else if (src
->X_add_number
== REG_MB
) /* LD A,MB */
2485 if (!(ins_ok
& INS_EZ80
))
2490 error (_("ADL mode instruction"));
2521 switch (src
->X_add_number
)
2532 ill_op (); /* LD iiH/L,H/L are not permitted */
2536 if (prefix
== 0xFD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2537 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2543 if (prefix
== 0xDD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2544 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2551 opcode
= 0x40 + ((dst
->X_add_number
& 7) << 3) + (src
->X_add_number
& 7);
2553 if ((ins_ok
& INS_GBZ80
) && prefix
!= 0)
2555 if (ii_halves
&& !(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2556 check_mach (INS_IDX_HALF
);
2557 if (prefix
== 0 && (ins_ok
& INS_EZ80
))
2561 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2562 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2563 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2564 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2565 as_warn (_("unsupported instruction, assembled as NOP"));
2571 q
= frag_more (prefix
? 2 : 1);
2578 emit_ld_rr_m (expressionS
*dst
, expressionS
*src
)
2579 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2583 expressionS src_offset
;
2585 /* GBZ80 has no support for 16-bit load from memory instructions */
2586 if (ins_ok
& INS_GBZ80
)
2592 case O_md1
: /* LD rr,(ii+d) */
2593 prefix
= (src
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2595 case O_register
: /* LD rr,(HL) */
2596 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2597 if (!(ins_ok
& INS_EZ80
))
2599 switch (dst
->X_add_number
)
2601 case REG_BC
: opcode
= 0x07; break;
2602 case REG_DE
: opcode
= 0x17; break;
2603 case REG_HL
: opcode
= 0x27; break;
2604 case REG_IX
: opcode
= (prefix
== 0xED || prefix
== 0xDD) ? 0x37 : 0x31; break;
2605 case REG_IY
: opcode
= (prefix
== 0xED || prefix
== 0xDD) ? 0x31 : 0x37; break;
2615 src_offset
.X_op
= O_symbol
;
2616 src_offset
.X_add_number
= 0;
2617 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2620 default: /* LD rr,(nn) */
2621 switch (dst
->X_add_number
)
2623 case REG_BC
: prefix
= 0xED; opcode
= 0x4B; break;
2624 case REG_DE
: prefix
= 0xED; opcode
= 0x5B; break;
2625 case REG_HL
: prefix
= 0x00; opcode
= 0x2A; break;
2626 case REG_SP
: prefix
= 0xED; opcode
= 0x7B; break;
2627 case REG_IX
: prefix
= 0xDD; opcode
= 0x2A; break;
2628 case REG_IY
: prefix
= 0xFD; opcode
= 0x2A; break;
2632 q
= frag_more (prefix
? 2 : 1);
2642 emit_ld_rr_nn (expressionS
*dst
, expressionS
*src
)
2643 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2646 int opcode
= 0x21; /* LD HL,nn */
2647 switch (dst
->X_add_number
)
2660 opcode
= 0x01 + ((dst
->X_add_number
& 3) << 4);
2666 if (prefix
&& (ins_ok
& INS_GBZ80
))
2668 q
= frag_more (prefix
? 2 : 1);
2676 emit_ld (char prefix_in ATTRIBUTE_UNUSED
, char opcode_in ATTRIBUTE_UNUSED
,
2679 expressionS dst
, src
;
2682 p
= parse_exp (args
, & dst
);
2684 error (_("bad instruction syntax"));
2685 p
= parse_exp (p
, & src
);
2689 if (src
.X_op
== O_register
)
2691 if (src
.X_add_number
<= 7)
2692 emit_ld_m_r (& dst
, & src
); /* LD (xxx),r */
2694 emit_ld_m_rr (& dst
, & src
); /* LD (xxx),rr */
2697 emit_ld_m_n (& dst
, & src
); /* LD (hl),n or LD (ix/y+r),n */
2699 else if (dst
.X_op
== O_register
)
2703 if (dst
.X_add_number
<= 7)
2704 emit_ld_r_m (& dst
, & src
);
2706 emit_ld_rr_m (& dst
, & src
);
2708 else if (src
.X_op
== O_register
)
2709 emit_ld_r_r (& dst
, & src
);
2710 else if ((dst
.X_add_number
& ~R_INDEX
) <= 7)
2711 emit_ld_r_n (& dst
, & src
);
2713 emit_ld_rr_nn (& dst
, & src
);
2722 emit_lddldi (char prefix
, char opcode
, const char * args
)
2724 expressionS dst
, src
;
2728 if (!(ins_ok
& INS_GBZ80
))
2729 return emit_insn (prefix
, opcode
, args
);
2731 p
= parse_exp (args
, & dst
);
2733 error (_("bad instruction syntax"));
2734 p
= parse_exp (p
, & src
);
2736 if (dst
.X_op
!= O_register
|| src
.X_op
!= O_register
)
2739 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2740 opcode
= (opcode
& 0x08) * 2 + 0x22;
2743 && dst
.X_add_number
== REG_HL
2745 && src
.X_add_number
== REG_A
)
2746 opcode
|= 0x00; /* LDx (HL),A */
2747 else if (dst
.X_md
== 0
2748 && dst
.X_add_number
== REG_A
2750 && src
.X_add_number
== REG_HL
)
2751 opcode
|= 0x08; /* LDx A,(HL) */
2761 emit_ldh (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2764 expressionS dst
, src
;
2768 p
= parse_exp (args
, & dst
);
2771 error (_("bad instruction syntax"));
2775 p
= parse_exp (p
, & src
);
2777 && dst
.X_op
== O_register
2778 && dst
.X_add_number
== REG_A
2780 && src
.X_op
!= O_md1
)
2782 if (src
.X_op
!= O_register
)
2786 emit_byte (& src
, BFD_RELOC_8
);
2788 else if (src
.X_add_number
== REG_C
)
2789 *frag_more (1) = 0xF2;
2793 else if (dst
.X_md
!= 0
2794 && dst
.X_op
!= O_md1
2796 && src
.X_op
== O_register
2797 && src
.X_add_number
== REG_A
)
2799 if (dst
.X_op
== O_register
)
2801 if (dst
.X_add_number
== REG_C
)
2813 emit_byte (& dst
, BFD_RELOC_8
);
2823 emit_ldhl (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2825 expressionS dst
, src
;
2828 p
= parse_exp (args
, & dst
);
2831 error (_("bad instruction syntax"));
2835 p
= parse_exp (p
, & src
);
2836 if (dst
.X_md
|| dst
.X_op
!= O_register
|| dst
.X_add_number
!= REG_SP
2837 || src
.X_md
|| src
.X_op
== O_register
|| src
.X_op
== O_md1
)
2841 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2846 parse_lea_pea_args (const char * args
, expressionS
*op
)
2849 p
= parse_exp (args
, op
);
2850 if (sdcc_compat
&& *p
== ',' && op
->X_op
== O_register
)
2853 p
= parse_exp (p
+ 1, &off
);
2855 op
->X_add_symbol
= make_expr_symbol (&off
);
2861 emit_lea (char prefix
, char opcode
, const char * args
)
2863 expressionS dst
, src
;
2868 p
= parse_exp (args
, & dst
);
2869 if (dst
.X_md
!= 0 || dst
.X_op
!= O_register
)
2872 rnum
= dst
.X_add_number
;
2878 opcode
= 0x02 | ((rnum
& 0x03) << 4);
2881 opcode
= 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2884 opcode
= 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2891 error (_("bad instruction syntax"));
2893 p
= parse_lea_pea_args (p
, & src
);
2894 if (src
.X_md
!= 0 || src
.X_op
!= O_add
/*&& src.X_op != O_register*/)
2897 rnum
= src
.X_add_number
;
2902 case O_register
: /* permit instructions like LEA rr,IX without displacement specified */
2903 src
.X_add_symbol
= zero
;
2912 opcode
= (opcode
== (char)0x33) ? 0x55 : (opcode
|0x00);
2915 opcode
= (opcode
== (char)0x32) ? 0x54 : (opcode
|0x01);
2922 src
.X_op
= O_symbol
;
2923 src
.X_add_number
= 0;
2924 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2930 emit_mlt (char prefix
, char opcode
, const char * args
)
2936 p
= parse_exp (args
, & arg
);
2937 if (arg
.X_md
!= 0 || arg
.X_op
!= O_register
|| !(arg
.X_add_number
& R_ARITH
))
2941 if (ins_ok
& INS_Z80N
)
2943 if (arg
.X_add_number
!= REG_DE
)
2951 *q
= opcode
| ((arg
.X_add_number
& 3) << 4);
2957 /* MUL D,E (Z80N only) */
2959 emit_mul (char prefix
, char opcode
, const char * args
)
2965 p
= parse_exp (args
, & r1
);
2967 error (_("bad instruction syntax"));
2968 p
= parse_exp (p
, & r2
);
2970 if (r1
.X_md
!= 0 || r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_D
||
2971 r2
.X_md
!= 0 || r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_E
)
2982 emit_nextreg (char prefix
, char opcode ATTRIBUTE_UNUSED
, const char * args
)
2988 p
= parse_exp (args
, & rr
);
2990 error (_("bad instruction syntax"));
2991 p
= parse_exp (p
, & nn
);
2992 if (rr
.X_md
!= 0 || rr
.X_op
== O_register
|| rr
.X_op
== O_md1
||
2993 nn
.X_md
!= 0 || nn
.X_op
== O_md1
)
2997 emit_byte (&rr
, BFD_RELOC_8
);
2998 if (nn
.X_op
== O_register
&& nn
.X_add_number
== REG_A
)
3000 else if (nn
.X_op
!= O_register
)
3003 emit_byte (&nn
, BFD_RELOC_8
);
3011 emit_pea (char prefix
, char opcode
, const char * args
)
3017 p
= parse_lea_pea_args (args
, & arg
);
3019 || (/*arg.X_op != O_register &&*/ arg
.X_op
!= O_add
)
3020 || !(arg
.X_add_number
& R_INDEX
))
3022 /* PEA ii without displacement is mostly typo,
3023 because there is PUSH instruction which is shorter and faster */
3024 /*if (arg.X_op == O_register)
3025 as_warn (_("PEA is used without displacement, use PUSH instead"));*/
3029 *q
= opcode
+ (arg
.X_add_number
== REG_IY
? 1 : 0);
3031 arg
.X_op
= O_symbol
;
3032 arg
.X_add_number
= 0;
3033 emit_byte (& arg
, BFD_RELOC_Z80_DISP8
);
3039 emit_reti (char prefix
, char opcode
, const char * args
)
3041 if (ins_ok
& INS_GBZ80
)
3042 return emit_insn (0x00, 0xD9, args
);
3044 return emit_insn (prefix
, opcode
, args
);
3048 emit_tst (char prefix
, char opcode
, const char *args
)
3055 p
= parse_exp (args
, & arg_s
);
3056 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
3058 if (!(ins_ok
& INS_EZ80
))
3061 p
= parse_exp (p
, & arg_s
);
3064 rnum
= arg_s
.X_add_number
;
3071 rnum
= arg_s
.X_add_number
;
3072 if (arg_s
.X_md
!= 0)
3081 *q
= opcode
| (rnum
<< 3);
3087 if (ins_ok
& INS_Z80N
)
3097 emit_byte (& arg_s
, BFD_RELOC_8
);
3103 emit_insn_n (char prefix
, char opcode
, const char *args
)
3109 p
= parse_exp (args
, & arg
);
3110 if (arg
.X_md
|| arg
.X_op
== O_register
|| arg
.X_op
== O_md1
)
3116 emit_byte (& arg
, BFD_RELOC_8
);
3122 emit_data (int size ATTRIBUTE_UNUSED
)
3129 if (is_it_end_of_statement ())
3131 demand_empty_rest_of_line ();
3134 p
= skip_space (input_line_pointer
);
3138 if (*p
== '\"' || *p
== '\'')
3140 for (quote
= *p
, q
= ++p
, cnt
= 0; *p
&& quote
!= *p
; ++p
, ++cnt
)
3142 u
= frag_more (cnt
);
3145 as_warn (_("unterminated string"));
3147 p
= skip_space (p
+1);
3151 p
= parse_exp (p
, &exp
);
3152 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3158 as_warn (_("parentheses ignored"));
3159 emit_byte (&exp
, BFD_RELOC_8
);
3163 while (*p
++ == ',') ;
3164 input_line_pointer
= (char *)(p
-1);
3173 if (is_it_end_of_statement ())
3175 demand_empty_rest_of_line ();
3178 p
= skip_space (input_line_pointer
);
3182 p
= parse_exp (p
, &exp
);
3183 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3189 as_warn (_("parentheses ignored"));
3190 emit_data_val (&exp
, size
);
3192 } while (*p
++ == ',') ;
3193 input_line_pointer
= (char *)(p
-1);
3196 /* next functions were commented out because it is difficult to mix
3197 both ADL and Z80 mode instructions within one COFF file:
3198 objdump cannot recognize point of mode switching.
3201 set_cpu_mode (int mode
)
3203 if (ins_ok
& INS_EZ80
)
3206 error (_("CPU mode is unsupported by target"));
3210 assume (int arg ATTRIBUTE_UNUSED
)
3216 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3217 c
= get_symbol_name (& name
);
3218 if (strncasecmp (name
, "ADL", 4) != 0)
3224 restore_line_pointer (c
);
3225 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3226 if (*input_line_pointer
++ != '=')
3228 error (_("assignment expected"));
3231 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3232 n
= get_single_number ();
3238 emit_mulub (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3242 p
= skip_space (args
);
3243 if (TOLOWER (*p
++) != 'a' || *p
++ != ',')
3249 reg
= TOLOWER (*p
++);
3256 check_mach (INS_R800
);
3257 if (!*skip_space (p
))
3261 *q
= opcode
+ ((reg
- 'b') << 3);
3273 emit_muluw (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3277 p
= skip_space (args
);
3278 if (TOLOWER (*p
++) != 'h' || TOLOWER (*p
++) != 'l' || *p
++ != ',')
3285 p
= parse_exp (p
, & reg
);
3287 if ((!reg
.X_md
) && reg
.X_op
== O_register
)
3288 switch (reg
.X_add_number
)
3292 check_mach (INS_R800
);
3295 *q
= opcode
+ ((reg
.X_add_number
& 3) << 4);
3305 assemble_suffix (const char **suffix
)
3308 const char sf
[8][4] =
3328 for (i
= 0; (i
< 3) && (ISALPHA (*p
)); i
++)
3329 sbuf
[i
] = TOLOWER (*p
++);
3330 if (*p
&& !ISSPACE (*p
))
3335 t
= bsearch (sbuf
, sf
, ARRAY_SIZE (sf
), sizeof (sf
[0]), (int(*)(const void*, const void*)) strcmp
);
3342 i
= cpu_mode
? 0x5B : 0x52;
3345 i
= cpu_mode
? 0x49 : 0x40;
3348 i
= cpu_mode
? 0x5B : 0x49;
3357 i
= cpu_mode
? 0x52 : 0x40;
3366 *frag_more (1) = (char)i
;
3369 case 0x40: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IS
; break;
3370 case 0x49: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IS
; break;
3371 case 0x52: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IL
; break;
3372 case 0x5B: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IL
; break;
3380 #if defined(OBJ_ELF)
3381 return obj_elf_section (arg
);
3382 #elif defined(OBJ_COFF)
3383 return obj_coff_section (arg
);
3385 #error Unknown object format
3395 as_fatal (_("Invalid directive"));
3398 ins_ok
&= INS_MARCH_MASK
;
3400 if (old_ins
!= ins_ok
)
3405 ignore (int arg ATTRIBUTE_UNUSED
)
3407 ignore_rest_of_line ();
3415 as_fatal (_("Invalid directive"));
3416 for (p
= input_line_pointer
; *p
&& *p
!= '(' && *p
!= '\n'; p
++)
3423 ignore_rest_of_line ();
3429 /* Port specific pseudo ops. */
3430 const pseudo_typeS md_pseudo_table
[] =
3432 { ".area", area
, 0},
3433 { ".assume", assume
, 0},
3434 { ".ez80", set_inss
, INS_EZ80
},
3435 { ".gbz80", set_inss
, INS_GBZ80
},
3436 { ".module", ignore
, 0},
3437 { ".optsdcc", ignore
, 0},
3438 { ".r800", set_inss
, INS_R800
},
3439 { ".set", s_set
, 0},
3440 { ".z180", set_inss
, INS_Z180
},
3441 { ".z80", set_inss
, INS_Z80
},
3442 { ".z80n", set_inss
, INS_Z80N
},
3443 { "db" , emit_data
, 1},
3444 { "d24", z80_cons
, 3},
3445 { "d32", z80_cons
, 4},
3446 { "def24", z80_cons
, 3},
3447 { "def32", z80_cons
, 4},
3448 { "defb", emit_data
, 1},
3449 { "defm", emit_data
, 1},
3450 { "defs", s_space
, 1}, /* Synonym for ds on some assemblers. */
3451 { "defw", z80_cons
, 2},
3452 { "ds", s_space
, 1}, /* Fill with bytes rather than words. */
3453 { "dw", z80_cons
, 2},
3454 { "psect", psect
, 0}, /* TODO: Translate attributes. */
3455 { "set", 0, 0}, /* Real instruction on z80. */
3459 static table_t instab
[] =
3461 { "adc", 0x88, 0x4A, emit_adc
, INS_ALL
},
3462 { "add", 0x80, 0x09, emit_add
, INS_ALL
},
3463 { "and", 0x00, 0xA0, emit_s
, INS_ALL
},
3464 { "bit", 0xCB, 0x40, emit_bit
, INS_ALL
},
3465 { "brlc", 0xED, 0x2C, emit_bshft
,INS_Z80N
},
3466 { "bsla", 0xED, 0x28, emit_bshft
,INS_Z80N
},
3467 { "bsra", 0xED, 0x29, emit_bshft
,INS_Z80N
},
3468 { "bsrf", 0xED, 0x2B, emit_bshft
,INS_Z80N
},
3469 { "bsrl", 0xED, 0x2A, emit_bshft
,INS_Z80N
},
3470 { "call", 0xCD, 0xC4, emit_jpcc
, INS_ALL
},
3471 { "ccf", 0x00, 0x3F, emit_insn
, INS_ALL
},
3472 { "cp", 0x00, 0xB8, emit_s
, INS_ALL
},
3473 { "cpd", 0xED, 0xA9, emit_insn
, INS_NOT_GBZ80
},
3474 { "cpdr", 0xED, 0xB9, emit_insn
, INS_NOT_GBZ80
},
3475 { "cpi", 0xED, 0xA1, emit_insn
, INS_NOT_GBZ80
},
3476 { "cpir", 0xED, 0xB1, emit_insn
, INS_NOT_GBZ80
},
3477 { "cpl", 0x00, 0x2F, emit_insn
, INS_ALL
},
3478 { "daa", 0x00, 0x27, emit_insn
, INS_ALL
},
3479 { "dec", 0x0B, 0x05, emit_incdec
,INS_ALL
},
3480 { "di", 0x00, 0xF3, emit_insn
, INS_ALL
},
3481 { "djnz", 0x00, 0x10, emit_jr
, INS_NOT_GBZ80
},
3482 { "ei", 0x00, 0xFB, emit_insn
, INS_ALL
},
3483 { "ex", 0x00, 0x00, emit_ex
, INS_NOT_GBZ80
},
3484 { "exx", 0x00, 0xD9, emit_insn
, INS_NOT_GBZ80
},
3485 { "halt", 0x00, 0x76, emit_insn
, INS_ALL
},
3486 { "im", 0xED, 0x46, emit_im
, INS_NOT_GBZ80
},
3487 { "in", 0x00, 0x00, emit_in
, INS_NOT_GBZ80
},
3488 { "in0", 0xED, 0x00, emit_in0
, INS_Z180
|INS_EZ80
},
3489 { "inc", 0x03, 0x04, emit_incdec
,INS_ALL
},
3490 { "ind", 0xED, 0xAA, emit_insn
, INS_NOT_GBZ80
},
3491 { "ind2", 0xED, 0x8C, emit_insn
, INS_EZ80
},
3492 { "ind2r",0xED, 0x9C, emit_insn
, INS_EZ80
},
3493 { "indm", 0xED, 0x8A, emit_insn
, INS_EZ80
},
3494 { "indmr",0xED, 0x9A, emit_insn
, INS_EZ80
},
3495 { "indr", 0xED, 0xBA, emit_insn
, INS_NOT_GBZ80
},
3496 { "indrx",0xED, 0xCA, emit_insn
, INS_EZ80
},
3497 { "ini", 0xED, 0xA2, emit_insn
, INS_NOT_GBZ80
},
3498 { "ini2", 0xED, 0x84, emit_insn
, INS_EZ80
},
3499 { "ini2r",0xED, 0x94, emit_insn
, INS_EZ80
},
3500 { "inim", 0xED, 0x82, emit_insn
, INS_EZ80
},
3501 { "inimr",0xED, 0x92, emit_insn
, INS_EZ80
},
3502 { "inir", 0xED, 0xB2, emit_insn
, INS_NOT_GBZ80
},
3503 { "inirx",0xED, 0xC2, emit_insn
, INS_EZ80
},
3504 { "jp", 0xC3, 0xC2, emit_jpcc
, INS_ALL
},
3505 { "jr", 0x18, 0x20, emit_jrcc
, INS_ALL
},
3506 { "ld", 0x00, 0x00, emit_ld
, INS_ALL
},
3507 { "ldd", 0xED, 0xA8, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3508 { "lddr", 0xED, 0xB8, emit_insn
, INS_NOT_GBZ80
},
3509 { "lddrx",0xED, 0xBC, emit_insn
, INS_Z80N
},
3510 { "lddx", 0xED, 0xAC, emit_insn
, INS_Z80N
},
3511 { "ldh", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3512 { "ldhl", 0x00, 0xF8, emit_ldhl
, INS_GBZ80
},
3513 { "ldi", 0xED, 0xA0, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3514 { "ldir", 0xED, 0xB0, emit_insn
, INS_NOT_GBZ80
},
3515 { "ldirx",0xED, 0xB4, emit_insn
, INS_Z80N
},
3516 { "ldix", 0xED, 0xA4, emit_insn
, INS_Z80N
},
3517 { "ldpirx",0xED,0xB7, emit_insn
, INS_Z80N
},
3518 { "ldws", 0xED, 0xA5, emit_insn
, INS_Z80N
},
3519 { "lea", 0xED, 0x02, emit_lea
, INS_EZ80
},
3520 { "mirror",0xED,0x24, emit_insn
, INS_Z80N
},
3521 { "mlt", 0xED, 0x4C, emit_mlt
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3522 { "mul", 0xED, 0x30, emit_mul
, INS_Z80N
},
3523 { "mulub",0xED, 0xC5, emit_mulub
,INS_R800
},
3524 { "muluw",0xED, 0xC3, emit_muluw
,INS_R800
},
3525 { "neg", 0xED, 0x44, emit_insn
, INS_NOT_GBZ80
},
3526 { "nextreg",0xED,0x91,emit_nextreg
,INS_Z80N
},
3527 { "nop", 0x00, 0x00, emit_insn
, INS_ALL
},
3528 { "or", 0x00, 0xB0, emit_s
, INS_ALL
},
3529 { "otd2r",0xED, 0xBC, emit_insn
, INS_EZ80
},
3530 { "otdm", 0xED, 0x8B, emit_insn
, INS_Z180
|INS_EZ80
},
3531 { "otdmr",0xED, 0x9B, emit_insn
, INS_Z180
|INS_EZ80
},
3532 { "otdr", 0xED, 0xBB, emit_insn
, INS_NOT_GBZ80
},
3533 { "otdrx",0xED, 0xCB, emit_insn
, INS_EZ80
},
3534 { "oti2r",0xED, 0xB4, emit_insn
, INS_EZ80
},
3535 { "otim", 0xED, 0x83, emit_insn
, INS_Z180
|INS_EZ80
},
3536 { "otimr",0xED, 0x93, emit_insn
, INS_Z180
|INS_EZ80
},
3537 { "otir", 0xED, 0xB3, emit_insn
, INS_NOT_GBZ80
},
3538 { "otirx",0xED, 0xC3, emit_insn
, INS_EZ80
},
3539 { "out", 0x00, 0x00, emit_out
, INS_NOT_GBZ80
},
3540 { "out0", 0xED, 0x01, emit_out0
, INS_Z180
|INS_EZ80
},
3541 { "outd", 0xED, 0xAB, emit_insn
, INS_NOT_GBZ80
},
3542 { "outd2",0xED, 0xAC, emit_insn
, INS_EZ80
},
3543 { "outi", 0xED, 0xA3, emit_insn
, INS_NOT_GBZ80
},
3544 { "outi2",0xED, 0xA4, emit_insn
, INS_EZ80
},
3545 { "outinb",0xED,0x90, emit_insn
, INS_Z80N
},
3546 { "pea", 0xED, 0x65, emit_pea
, INS_EZ80
},
3547 { "pixelad",0xED,0x94,emit_insn
, INS_Z80N
},
3548 { "pixeldn",0xED,0x93,emit_insn
, INS_Z80N
},
3549 { "pop", 0x00, 0xC1, emit_pop
, INS_ALL
},
3550 { "push", 0x00, 0xC5, emit_push
, INS_ALL
},
3551 { "res", 0xCB, 0x80, emit_bit
, INS_ALL
},
3552 { "ret", 0xC9, 0xC0, emit_retcc
,INS_ALL
},
3553 { "reti", 0xED, 0x4D, emit_reti
, INS_ALL
}, /*GBZ80 has its own opcode for it*/
3554 { "retn", 0xED, 0x45, emit_insn
, INS_NOT_GBZ80
},
3555 { "rl", 0xCB, 0x10, emit_mr
, INS_ALL
},
3556 { "rla", 0x00, 0x17, emit_insn
, INS_ALL
},
3557 { "rlc", 0xCB, 0x00, emit_mr
, INS_ALL
},
3558 { "rlca", 0x00, 0x07, emit_insn
, INS_ALL
},
3559 { "rld", 0xED, 0x6F, emit_insn
, INS_NOT_GBZ80
},
3560 { "rr", 0xCB, 0x18, emit_mr
, INS_ALL
},
3561 { "rra", 0x00, 0x1F, emit_insn
, INS_ALL
},
3562 { "rrc", 0xCB, 0x08, emit_mr
, INS_ALL
},
3563 { "rrca", 0x00, 0x0F, emit_insn
, INS_ALL
},
3564 { "rrd", 0xED, 0x67, emit_insn
, INS_NOT_GBZ80
},
3565 { "rsmix",0xED, 0x7E, emit_insn
, INS_EZ80
},
3566 { "rst", 0x00, 0xC7, emit_rst
, INS_ALL
},
3567 { "sbc", 0x98, 0x42, emit_adc
, INS_ALL
},
3568 { "scf", 0x00, 0x37, emit_insn
, INS_ALL
},
3569 { "set", 0xCB, 0xC0, emit_bit
, INS_ALL
},
3570 { "setae",0xED, 0x95, emit_insn
, INS_Z80N
},
3571 { "sl1", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3572 { "sla", 0xCB, 0x20, emit_mr
, INS_ALL
},
3573 { "sli", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3574 { "sll", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3575 { "slp", 0xED, 0x76, emit_insn
, INS_Z180
|INS_EZ80
},
3576 { "sra", 0xCB, 0x28, emit_mr
, INS_ALL
},
3577 { "srl", 0xCB, 0x38, emit_mr
, INS_ALL
},
3578 { "stmix",0xED, 0x7D, emit_insn
, INS_EZ80
},
3579 { "stop", 0x00, 0x10, emit_insn
, INS_GBZ80
},
3580 { "sub", 0x00, 0x90, emit_sub
, INS_ALL
},
3581 { "swap", 0xCB, 0x30, emit_swap
, INS_GBZ80
|INS_Z80N
},
3582 { "swapnib",0xED,0x23,emit_insn
, INS_Z80N
},
3583 { "test", 0xED, 0x27, emit_insn_n
, INS_Z80N
},
3584 { "tst", 0xED, 0x04, emit_tst
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3585 { "tstio",0xED, 0x74, emit_insn_n
,INS_Z180
|INS_EZ80
},
3586 { "xor", 0x00, 0xA8, emit_s
, INS_ALL
},
3590 md_assemble (char *str
)
3598 inst_mode
= cpu_mode
? (INST_MODE_L
| INST_MODE_IL
) : (INST_MODE_S
| INST_MODE_IS
);
3599 old_ptr
= input_line_pointer
;
3600 p
= skip_space (str
);
3601 for (i
= 0; (i
< BUFLEN
) && (ISALPHA (*p
) || ISDIGIT (*p
));)
3602 buf
[i
++] = TOLOWER (*p
++);
3606 buf
[BUFLEN
-3] = buf
[BUFLEN
-2] = '.'; /* Mark opcode as abbreviated. */
3608 as_bad (_("Unknown instruction '%s'"), buf
);
3612 dwarf2_emit_insn (0);
3613 if ((*p
) && (!ISSPACE (*p
)))
3615 if (*p
!= '.' || !(ins_ok
& INS_EZ80
) || !assemble_suffix (&p
))
3617 as_bad (_("syntax error"));
3625 insp
= bsearch (&key
, instab
, ARRAY_SIZE (instab
),
3626 sizeof (instab
[0]), key_cmp
);
3627 if (!insp
|| (insp
->inss
&& !(insp
->inss
& ins_ok
)))
3630 as_bad (_("Unknown instruction `%s'"), buf
);
3634 p
= insp
->fp (insp
->prefix
, insp
->opcode
, p
);
3636 if ((!err_flag
) && *p
)
3637 as_bad (_("junk at end of line, "
3638 "first unrecognized character is `%c'"), *p
);
3642 input_line_pointer
= old_ptr
;
3646 is_overflow (long value
, unsigned bitsize
)
3648 long fieldmask
= (1 << bitsize
) - 1;
3649 long signmask
= ~fieldmask
;
3650 long a
= value
& fieldmask
;
3651 long ss
= a
& signmask
;
3652 if (ss
!= 0 && ss
!= (signmask
& fieldmask
))
3658 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
3661 char *p_lit
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3663 if (fixP
->fx_addsy
== NULL
)
3665 else if (fixP
->fx_pcrel
)
3667 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
3668 if (s
== seg
|| s
== absolute_section
)
3670 val
+= S_GET_VALUE (fixP
->fx_addsy
);
3675 switch (fixP
->fx_r_type
)
3677 case BFD_RELOC_8_PCREL
:
3678 case BFD_RELOC_Z80_DISP8
:
3683 case BFD_RELOC_Z80_16_BE
:
3684 fixP
->fx_no_overflow
= 0;
3687 fixP
->fx_no_overflow
= 1;
3691 switch (fixP
->fx_r_type
)
3693 case BFD_RELOC_8_PCREL
:
3694 case BFD_RELOC_Z80_DISP8
:
3695 if (fixP
->fx_done
&& (val
< -0x80 || val
> 0x7f))
3696 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3697 _("8-bit signed offset out of range (%+ld)"), val
);
3701 case BFD_RELOC_Z80_BYTE0
:
3705 case BFD_RELOC_Z80_BYTE1
:
3706 *p_lit
++ = (val
>> 8);
3709 case BFD_RELOC_Z80_BYTE2
:
3710 *p_lit
++ = (val
>> 16);
3713 case BFD_RELOC_Z80_BYTE3
:
3714 *p_lit
++ = (val
>> 24);
3718 if (fixP
->fx_done
&& is_overflow(val
, 8))
3719 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3720 _("8-bit overflow (%+ld)"), val
);
3724 case BFD_RELOC_Z80_WORD1
:
3725 *p_lit
++ = (val
>> 16);
3726 *p_lit
++ = (val
>> 24);
3729 case BFD_RELOC_Z80_WORD0
:
3731 *p_lit
++ = (val
>> 8);
3735 if (fixP
->fx_done
&& is_overflow(val
, 16))
3736 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3737 _("16-bit overflow (%+ld)"), val
);
3739 *p_lit
++ = (val
>> 8);
3742 case BFD_RELOC_24
: /* Def24 may produce this. */
3743 if (fixP
->fx_done
&& is_overflow(val
, 24))
3744 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3745 _("24-bit overflow (%+ld)"), val
);
3747 *p_lit
++ = (val
>> 8);
3748 *p_lit
++ = (val
>> 16);
3751 case BFD_RELOC_32
: /* Def32 and .long may produce this. */
3752 if (fixP
->fx_done
&& is_overflow(val
, 32))
3753 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3754 _("32-bit overflow (%+ld)"), val
);
3756 *p_lit
++ = (val
>> 8);
3757 *p_lit
++ = (val
>> 16);
3758 *p_lit
++ = (val
>> 24);
3761 case BFD_RELOC_Z80_16_BE
: /* Z80N PUSH nn instruction produce this. */
3762 *p_lit
++ = val
>> 8;
3767 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP
->fx_r_type
);
3772 /* GAS will call this to generate a reloc. GAS will pass the
3773 resulting reloc to `bfd_install_relocation'. This currently works
3774 poorly, as `bfd_install_relocation' often does the wrong thing, and
3775 instances of `tc_gen_reloc' have been written to work around the
3776 problems, which in turns makes it difficult to fix
3777 `bfd_install_relocation'. */
3779 /* If while processing a fixup, a reloc really
3780 needs to be created then it is done here. */
3783 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3787 if (fixp
->fx_subsy
!= NULL
)
3789 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
3793 reloc
= XNEW (arelent
);
3794 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3795 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3796 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3797 reloc
->addend
= fixp
->fx_offset
;
3798 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3799 if (reloc
->howto
== NULL
)
3801 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3802 _("reloc %d not supported by object file format"),
3803 (int) fixp
->fx_r_type
);
3807 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3808 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3809 reloc
->address
= fixp
->fx_offset
;
3815 z80_tc_label_is_local (const char *name
)
3819 if (local_label_prefix
== NULL
)
3821 for (p
= local_label_prefix
, n
= name
; *p
&& *n
&& *n
== *p
; p
++, n
++)
3826 /* Parse floating point number from string and compute mantissa and
3827 exponent. Mantissa is normalized.
3829 #define EXP_MIN -0x10000
3830 #define EXP_MAX 0x10000
3832 str_to_broken_float (bfd_boolean
*signP
, bfd_uint64_t
*mantissaP
, int *expP
)
3836 bfd_uint64_t mantissa
= 0;
3840 p
= (char*)skip_space (input_line_pointer
);
3843 if (sign
|| *p
== '+')
3845 if (strncasecmp (p
, "NaN", 3) == 0)
3849 input_line_pointer
= p
+ 3;
3852 if (strncasecmp (p
, "inf", 3) == 0)
3854 *mantissaP
= 1ull << 63;
3856 input_line_pointer
= p
+ 3;
3859 for (; ISDIGIT (*p
); ++p
)
3867 mantissa
= mantissa
* 10 + (*p
- '0');
3869 /* skip non-significant digits */
3870 for (; ISDIGIT (*p
); ++p
)
3876 if (!exponent
) /* If no precission overflow. */
3878 for (; ISDIGIT (*p
); ++p
, --exponent
)
3886 mantissa
= mantissa
* 10 + (*p
- '0');
3889 for (; ISDIGIT (*p
); ++p
)
3892 if (*p
== 'e' || *p
== 'E')
3898 if (es
|| *p
== '+')
3900 for (; ISDIGIT (*p
); ++p
)
3903 t
= t
* 10 + (*p
- '0');
3905 exponent
+= (es
) ? -t
: t
;
3907 if (ISALNUM (*p
) || *p
== '.')
3909 input_line_pointer
= p
;
3912 *mantissaP
= 1ull << 63;
3914 return 1; /* result is 0 */
3917 for (; mantissa
<= ~0ull/10; --exponent
)
3919 /* Now we have sign, mantissa, and signed decimal exponent
3920 need to recompute to binary exponent. */
3921 for (i
= 64; exponent
> 0; --exponent
)
3923 /* be sure that no integer overflow */
3924 while (mantissa
> ~0ull/10)
3931 for (; exponent
< 0; ++exponent
)
3933 while (!(mantissa
>> 63))
3941 for (; !(mantissa
>> 63); --i
)
3943 *mantissaP
= mantissa
;
3949 str_to_zeda32(char *litP
, int *sizeP
)
3951 bfd_uint64_t mantissa
;
3957 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3958 return _("invalid syntax");
3959 /* I do not know why decrement is needed */
3961 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
3965 /* make 24 bit mantissa */
3967 /* check for overflow */
3974 if (exponent
< -127)
3979 else if (exponent
> 127)
3982 mantissa
= sign
? 0xc00000 : 0x400000;
3984 else if (mantissa
== 0)
3987 mantissa
= 0x200000;
3990 mantissa
&= (1ull << 23) - 1;
3991 for (i
= 0; i
< 24; i
+= 8)
3992 *litP
++ = (char)(mantissa
>> i
);
3993 *litP
= (char)(0x80 + exponent
);
3998 Math48 by Anders Hejlsberg support.
3999 Mantissa is 39 bits wide, exponent 8 bit wide.
4002 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
4003 bit 7-0: exponent+128 (0 - value is null)
4004 MIN: 2.938735877e-39
4005 MAX: 1.701411835e+38
4008 str_to_float48(char *litP
, int *sizeP
)
4010 bfd_uint64_t mantissa
;
4016 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
4017 return _("invalid syntax");
4018 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
4022 /* make 40 bit mantissa */
4024 /* check for overflow */
4030 if (exponent
< -127)
4032 memset (litP
, 0, 6);
4036 return _("overflow");
4038 mantissa
&= (1ull << 39) - 1;
4039 *litP
++ = (char)(0x80 + exponent
);
4040 for (i
= 0; i
< 40; i
+= 8)
4041 *litP
++ = (char)(mantissa
>> i
);
4046 str_to_ieee754_h(char *litP
, int *sizeP
)
4048 return ieee_md_atof ('h', litP
, sizeP
, FALSE
);
4052 str_to_ieee754_s(char *litP
, int *sizeP
)
4054 return ieee_md_atof ('s', litP
, sizeP
, FALSE
);
4058 str_to_ieee754_d(char *litP
, int *sizeP
)
4060 return ieee_md_atof ('d', litP
, sizeP
, FALSE
);
4063 #ifdef TARGET_USE_CFIPOP
4064 /* Initialize the DWARF-2 unwind information for this procedure. */
4066 z80_tc_frame_initial_instructions (void)
4068 static int sp_regno
= -1;
4071 sp_regno
= z80_tc_regname_to_dw2regnum ("sp");
4073 cfi_add_CFA_def_cfa (sp_regno
, 0);
4077 z80_tc_regname_to_dw2regnum (const char *regname
)
4079 static const char *regs
[] =
4080 { /* same registers as for GDB */
4081 "af", "bc", "de", "hl",
4082 "sp", "pc", "ix", "iy",
4083 "af_", "bc_", "de_", "hl_",
4088 for (i
= 0; i
< ARRAY_SIZE(regs
); ++i
)
4089 if (!strcasecmp (regs
[i
], regname
))
4096 /* Implement DWARF2_ADDR_SIZE. */
4098 z80_dwarf2_addr_size (const bfd
*abfd
)
4100 switch (bfd_get_mach (abfd
))
4102 case bfd_mach_ez80_adl
: