1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
27 /* Exported constants. */
28 const char comment_chars
[] = ";\0";
29 const char line_comment_chars
[] = "#;\0";
30 const char line_separator_chars
[] = "\0";
31 const char EXP_CHARS
[] = "eE\0";
32 const char FLT_CHARS
[] = "RrFf\0";
34 /* For machine specific options. */
35 const char * md_shortopts
= ""; /* None yet. */
39 OPTION_MACH_Z80
= OPTION_MD_BASE
,
55 OPTION_COMPAT_LL_PREFIX
,
56 OPTION_COMPAT_COLONLESS
,
60 #define INS_Z80 (1 << 0)
61 #define INS_R800 (1 << 1)
62 #define INS_GBZ80 (1 << 2)
63 #define INS_Z180 (1 << 3)
64 #define INS_EZ80 (1 << 4)
65 #define INS_MARCH_MASK 0xffff
67 #define INS_IDX_HALF (1 << 16)
68 #define INS_IN_F_C (1 << 17)
69 #define INS_OUT_C_0 (1 << 18)
70 #define INS_SLI (1 << 19)
71 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
72 #define INS_TUNE_MASK 0xffff0000
74 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80)
77 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
78 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
80 struct option md_longopts
[] =
82 { "z80", no_argument
, NULL
, OPTION_MACH_Z80
},
83 { "r800", no_argument
, NULL
, OPTION_MACH_R800
},
84 { "z180", no_argument
, NULL
, OPTION_MACH_Z180
},
85 { "ez80", no_argument
, NULL
, OPTION_MACH_EZ80_Z80
},
86 { "ez80-adl", no_argument
, NULL
, OPTION_MACH_EZ80_ADL
},
87 { "float", required_argument
, NULL
, OPTION_FLOAT_FORMAT
},
88 { "double", required_argument
, NULL
, OPTION_DOUBLE_FORMAT
},
89 { "strict", no_argument
, NULL
, OPTION_MACH_FUD
},
90 { "full", no_argument
, NULL
, OPTION_MACH_IUP
},
91 { "with-inst", required_argument
, NULL
, OPTION_MACH_INST
},
92 { "Wnins", required_argument
, NULL
, OPTION_MACH_INST
},
93 { "without-inst", required_argument
, NULL
, OPTION_MACH_NO_INST
},
94 { "local-prefix", required_argument
, NULL
, OPTION_COMPAT_LL_PREFIX
},
95 { "colonless", no_argument
, NULL
, OPTION_COMPAT_COLONLESS
},
96 { "sdcc", no_argument
, NULL
, OPTION_COMPAT_SDCC
},
97 { "Fins", required_argument
, NULL
, OPTION_MACH_NO_INST
},
98 { "ignore-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_IUD
},
99 { "Wnud", no_argument
, NULL
, OPTION_MACH_IUD
},
100 { "warn-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_WUD
},
101 { "Wud", no_argument
, NULL
, OPTION_MACH_WUD
},
102 { "forbid-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_FUD
},
103 { "Fud", no_argument
, NULL
, OPTION_MACH_FUD
},
104 { "ignore-unportable-instructions", no_argument
, NULL
, OPTION_MACH_IUP
},
105 { "Wnup", no_argument
, NULL
, OPTION_MACH_IUP
},
106 { "warn-unportable-instructions", no_argument
, NULL
, OPTION_MACH_WUP
},
107 { "Wup", no_argument
, NULL
, OPTION_MACH_WUP
},
108 { "forbid-unportable-instructions", no_argument
, NULL
, OPTION_MACH_FUP
},
109 { "Fup", no_argument
, NULL
, OPTION_MACH_FUP
},
111 { NULL
, no_argument
, NULL
, 0 }
114 size_t md_longopts_size
= sizeof (md_longopts
);
116 extern int coff_flags
;
117 /* Instruction classes that silently assembled. */
118 static int ins_ok
= INS_Z80
| INS_UNDOC
;
119 /* Instruction classes that generate errors. */
120 static int ins_err
= ~(INS_Z80
| INS_UNDOC
);
121 /* eZ80 CPU mode (ADL or Z80) */
122 static int cpu_mode
= 0; /* 0 - Z80, 1 - ADL */
123 /* accept SDCC specific instruction encoding */
124 static int sdcc_compat
= 0;
125 /* accept colonless labels */
126 static int colonless_labels
= 0;
127 /* local label prefix (NULL - default) */
128 static const char *local_label_prefix
= NULL
;
129 /* floating point support */
130 typedef const char *(*str_to_float_t
)(char *litP
, int *sizeP
);
131 static str_to_float_t str_to_float
;
132 static str_to_float_t str_to_double
;
134 /* mode of current instruction */
135 #define INST_MODE_S 0 /* short data mode */
136 #define INST_MODE_IS 0 /* short instruction mode */
137 #define INST_MODE_L 2 /* long data mode */
138 #define INST_MODE_IL 1 /* long instruction mode */
139 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
140 static char inst_mode
;
143 setup_instruction (const char *inst
, int *add
, int *sub
)
146 if (!strcmp (inst
, "idx-reg-halves"))
148 else if (!strcmp (inst
, "sli"))
150 else if (!strcmp (inst
, "op-ii-ld"))
152 else if (!strcmp (inst
, "in-f-c"))
154 else if (!strcmp (inst
, "out-c-0"))
164 str_to_zeda32 (char *litP
, int *sizeP
);
166 str_to_float48 (char *litP
, int *sizeP
);
168 static str_to_float_t
169 get_str_to_float (const char *arg
)
171 if (strcasecmp(arg
, "zeda32") == 0)
172 return str_to_zeda32
;
174 if (strcasecmp(arg
, "math48") == 0)
175 return str_to_float48
;
177 if (strcasecmp(arg
, "ieee754") != 0)
178 as_fatal (_("invalid floating point numbers type `%s'"), arg
);
183 setup_instruction_list (const char *list
, int *add
, int *sub
)
190 for (b
= list
; *b
!= '\0';)
197 if (sz
== 0 || sz
>= (int)sizeof (buf
))
199 as_bad (_("invalid INST in command line: %s"), b
);
204 if (setup_instruction (buf
, add
, sub
))
208 as_bad (_("invalid INST in command line: %s"), buf
);
219 md_parse_option (int c
, const char* arg
)
225 case OPTION_MACH_Z80
:
226 ins_ok
= (ins_ok
& INS_TUNE_MASK
) | INS_Z80
;
227 ins_err
= (ins_err
& INS_MARCH_MASK
) | (~INS_Z80
& INS_MARCH_MASK
);
229 case OPTION_MACH_R800
:
230 ins_ok
= INS_R800
| INS_IDX_HALF
;
231 ins_err
= INS_UNPORT
;
233 case OPTION_MACH_Z180
:
235 ins_err
= INS_UNDOC
| INS_UNPORT
;
237 case OPTION_MACH_EZ80_Z80
:
239 ins_err
= (INS_UNDOC
| INS_UNPORT
) & ~INS_IDX_HALF
;
242 case OPTION_MACH_EZ80_ADL
:
244 ins_err
= (INS_UNDOC
| INS_UNPORT
) & ~INS_IDX_HALF
;
247 case OPTION_MACH_GBZ80
:
249 ins_err
= INS_UNDOC
| INS_UNPORT
;
251 case OPTION_FLOAT_FORMAT
:
252 str_to_float
= get_str_to_float (arg
);
254 case OPTION_DOUBLE_FORMAT
:
255 str_to_double
= get_str_to_float (arg
);
257 case OPTION_MACH_INST
:
258 if ((ins_ok
& INS_GBZ80
) == 0)
259 return setup_instruction_list(arg
, & ins_ok
, & ins_err
);
261 case OPTION_MACH_NO_INST
:
262 if ((ins_ok
& INS_GBZ80
) == 0)
263 return setup_instruction_list(arg
, & ins_err
, & ins_ok
);
265 case OPTION_MACH_WUD
:
266 case OPTION_MACH_IUD
:
267 if ((ins_ok
& INS_GBZ80
) == 0)
270 ins_err
&= ~INS_UNDOC
;
273 case OPTION_MACH_WUP
:
274 case OPTION_MACH_IUP
:
275 if ((ins_ok
& INS_GBZ80
) == 0)
277 ins_ok
|= INS_UNDOC
| INS_UNPORT
;
278 ins_err
&= ~(INS_UNDOC
| INS_UNPORT
);
281 case OPTION_MACH_FUD
:
282 if ((ins_ok
& (INS_R800
| INS_GBZ80
)) == 0)
284 ins_ok
&= (INS_UNDOC
| INS_UNPORT
);
285 ins_err
|= INS_UNDOC
| INS_UNPORT
;
288 case OPTION_MACH_FUP
:
289 ins_ok
&= ~INS_UNPORT
;
290 ins_err
|= INS_UNPORT
;
292 case OPTION_COMPAT_LL_PREFIX
:
293 local_label_prefix
= (arg
&& *arg
) ? arg
: NULL
;
295 case OPTION_COMPAT_SDCC
:
297 local_label_prefix
= "_";
299 case OPTION_COMPAT_COLONLESS
:
300 colonless_labels
= 1;
308 md_show_usage (FILE * f
)
311 CPU model options:\n\
312 -z80\t\t\t assemble for Z80\n\
313 -r800\t\t\t assemble for R800\n\
314 -z180\t\t\t assemble for Z180\n\
315 -ez80\t\t\t assemble for eZ80 in Z80 mode by default\n\
316 -ez80-adl\t\t assemble for eZ80 in ADL mode by default\n\
318 Compatibility options:\n\
319 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
320 -colonless\t\t permit colonless labels\n\
321 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
322 -float=FORMAT\t\t set floating point numbers format\n\
323 -double=FORMAT\t\t set floating point numbers format\n\
324 Where FORMAT one of:\n\
325 ieee754\t\t IEEE754 compatible\n\
326 zeda32\t\t\t Zeda z80float library 32 bit format\n\
327 math48\t\t 48 bit format from Math48 library\n\
329 Support for known undocumented instructions:\n\
330 -strict\t\t assemble only documented instructions\n\
331 -full\t\t\t assemble all undocumented instructions\n\
332 -with-inst=INST[,...]\n\
333 -Wnins INST[,...]\t assemble specified instruction(s)\n\
334 -without-inst=INST[,...]\n\
335 -Fins INST[,...]\t do not assemble specified instruction(s)\n\
336 Where INST is one of:\n\
337 idx-reg-halves\t instructions with halves of index registers\n\
338 sli\t\t\t instruction SLI/SLL\n\
339 op-ii-ld\t\t instructions like SLA (II+dd),R (opcodes DD/FD CB dd xx)\n\
340 in-f-c\t\t instruction IN F,(C)\n\
341 out-c-0\t\t instruction OUT (C),0\n\
344 -ignore-undocumented-instructions\n\
345 -Wnud\t\t\t silently assemble undocumented Z80-instructions that work on R800\n\
346 -ignore-unportable-instructions\n\
347 -Wnup\t\t\t silently assemble all undocumented Z80-instructions\n\
348 -warn-undocumented-instructions\n\
349 -Wud\t\t\t issue warnings for undocumented Z80-instructions that work on R800\n\
350 -warn-unportable-instructions\n\
351 -Wup\t\t\t issue warnings for other undocumented Z80-instructions\n\
352 -forbid-undocumented-instructions\n\
353 -Fud\t\t\t treat all undocumented Z80-instructions as errors\n\
354 -forbid-unportable-instructions\n\
355 -Fup\t\t\t treat undocumented Z80-instructions that do not work on R800 as errors\n\
357 Default: -z80 -ignore-undocumented-instructions -warn-unportable-instructions.\n");
360 static symbolS
* zero
;
367 #define R_STACKABLE (0x80)
368 #define R_ARITH (0x40)
371 #define R_INDEX (R_IX | R_IY)
380 #define REG_F (6 | 8)
385 #define REG_AF (3 | R_STACKABLE)
386 #define REG_BC (0 | R_STACKABLE | R_ARITH)
387 #define REG_DE (1 | R_STACKABLE | R_ARITH)
388 #define REG_HL (2 | R_STACKABLE | R_ARITH)
389 #define REG_IX (REG_HL | R_IX)
390 #define REG_IY (REG_HL | R_IY)
391 #define REG_SP (3 | R_ARITH)
393 static const struct reg_entry regtable
[] =
408 {"ixh",REG_H
| R_IX
},
409 {"ixl",REG_L
| R_IX
},
411 {"iyh",REG_H
| R_IY
},
412 {"iyl",REG_L
| R_IY
},
419 #define BUFLEN 8 /* Large enough for any keyword. */
424 expressionS nul
, reg
;
426 unsigned int i
, j
, k
;
429 if (ins_ok
& INS_EZ80
) /* if select EZ80 cpu then */
430 listing_lhs_width
= 6; /* use 6 bytes per line in the listing */
432 reg
.X_op
= O_register
;
434 reg
.X_add_symbol
= reg
.X_op_symbol
= 0;
435 for ( i
= 0 ; i
< ARRAY_SIZE ( regtable
) ; ++i
)
437 reg
.X_add_number
= regtable
[i
].number
;
438 k
= strlen ( regtable
[i
].name
);
442 for ( j
= ( 1<<k
) ; j
; --j
)
444 for ( k
= 0 ; regtable
[i
].name
[k
] ; ++k
)
446 buf
[k
] = ( j
& ( 1<<k
) ) ? TOUPPER ( regtable
[i
].name
[k
] ) : regtable
[i
].name
[k
];
448 symbolS
* psym
= symbol_find_or_make(buf
);
449 S_SET_SEGMENT(psym
, reg_section
);
450 symbol_set_value_expression(psym
, ®
);
454 p
= input_line_pointer
;
455 input_line_pointer
= (char *) "0";
458 input_line_pointer
= p
;
459 zero
= make_expr_symbol (& nul
);
460 /* We do not use relaxation (yet). */
469 switch (ins_ok
& INS_MARCH_MASK
)
472 if (ins_ok
& INS_UNPORT
)
473 mach_type
= bfd_mach_z80full
;
474 else if (ins_ok
& INS_UNDOC
)
475 mach_type
= bfd_mach_z80
;
477 mach_type
= bfd_mach_z80strict
;
480 mach_type
= bfd_mach_r800
;
483 mach_type
= bfd_mach_z180
;
486 mach_type
= bfd_mach_gbz80
;
489 mach_type
= cpu_mode
? bfd_mach_ez80_adl
: bfd_mach_ez80_z80
;
495 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_type
);
498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
500 z80_elf_final_processing (void)
503 switch (ins_ok
& INS_MARCH_MASK
)
506 elf_flags
= EF_Z80_MACH_Z80
;
509 elf_flags
= EF_Z80_MACH_R800
;
512 elf_flags
= EF_Z80_MACH_Z180
;
515 elf_flags
= EF_Z80_MACH_GBZ80
;
518 elf_flags
= cpu_mode
? EF_Z80_MACH_EZ80_ADL
: EF_Z80_MACH_EZ80_Z80
;
524 elf_elfheader (stdoutput
)->e_flags
= elf_flags
;
529 skip_space (const char *s
)
531 while (*s
== ' ' || *s
== '\t')
536 /* A non-zero return-value causes a continue in the
537 function read_a_source_file () in ../read.c. */
539 z80_start_line_hook (void)
544 /* Convert one character constants. */
545 for (p
= input_line_pointer
; *p
&& *p
!= '\n'; ++p
)
550 if (p
[1] != 0 && p
[1] != '\'' && p
[2] == '\'')
552 snprintf (buf
, 4, "%3d", (unsigned char)p
[1]);
560 for (quote
= *p
++; quote
!= *p
&& '\n' != *p
; ++p
)
564 as_bad (_("-- unterminated string"));
565 ignore_rest_of_line ();
571 *p
= (*skip_space (p
+ 1) == '(') ? '+' : ' ';
575 /* Check for <label>[:] [.](EQU|DEFL) <value>. */
576 if (is_name_beginner (*input_line_pointer
))
579 char c
, *rest
, *line_start
;
582 line_start
= input_line_pointer
;
586 c
= get_symbol_name (&name
);
587 rest
= input_line_pointer
+ 1;
589 if (ISSPACE(c
) && colonless_labels
)
593 bump_line_counters ();
598 if (c
== ':' && sdcc_compat
&& rest
[-2] != '$')
599 dollar_label_clear ();
602 /* remove second colon if SDCC compatibility enabled */
607 rest
= (char*)skip_space (rest
);
610 if (strncasecmp (rest
, "EQU", 3) == 0)
612 else if (strncasecmp (rest
, "DEFL", 4) == 0)
616 if (len
&& (!ISALPHA(rest
[len
]) ) )
618 /* Handle assignment here. */
619 if (line_start
[-1] == '\n')
621 bump_line_counters ();
624 input_line_pointer
= rest
+ len
- 1;
625 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
626 equals (name
, len
== 4);
631 /* Restore line and pointer. */
632 (void) restore_line_pointer (c
);
633 input_line_pointer
= line_start
;
640 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
646 md_atof (int type
, char *litP
, int *sizeP
)
653 return str_to_float (litP
, sizeP
);
658 return str_to_double (litP
, sizeP
);
661 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
665 md_section_align (segT seg ATTRIBUTE_UNUSED
, valueT size
)
671 md_pcrel_from (fixS
* fixp
)
673 return fixp
->fx_where
+ fixp
->fx_frag
->fr_address
;
676 typedef const char * (asfunc
)(char, char, const char*);
678 typedef struct _table_t
681 unsigned char prefix
;
682 unsigned char opcode
;
684 unsigned inss
; /*0 - all CPU types or list of supported INS_* */
687 /* Compares the key for structs that start with a char * to the key. */
689 key_cmp (const void * a
, const void * b
)
691 const char *str_a
, *str_b
;
693 str_a
= *((const char**)a
);
694 str_b
= *((const char**)b
);
695 return strcmp (str_a
, str_b
);
699 const char *key
= buf
;
701 /* Prevent an error on a line from also generating
702 a "junk at end of line" error message. */
703 static char err_flag
;
706 error (const char * message
)
711 as_bad ("%s", message
);
718 error (_("illegal operand"));
722 wrong_mach (int ins_type
)
724 if (ins_type
& ins_err
)
727 as_warn (_("undocumented instruction"));
731 check_mach (int ins_type
)
733 if ((ins_type
& ins_ok
) == 0)
734 wrong_mach (ins_type
);
737 /* Check whether an expression is indirect. */
739 is_indir (const char *s
)
745 /* Indirection is indicated with parentheses. */
748 for (p
= s
, depth
= 0; *p
&& *p
!= ','; ++p
)
754 for (quote
= *p
++; quote
!= *p
&& *p
!= '\n'; ++p
)
755 if (*p
== '\\' && p
[1])
765 p
= skip_space (p
+ 1);
771 error (_("mismatched parentheses"));
777 error (_("mismatched parentheses"));
782 /* Check whether a symbol involves a register. */
784 contains_register(symbolS
*sym
)
788 expressionS
* ex
= symbol_get_value_expression(sym
);
789 return (O_register
== ex
->X_op
)
790 || (ex
->X_add_symbol
&& contains_register(ex
->X_add_symbol
))
791 || (ex
->X_op_symbol
&& contains_register(ex
->X_op_symbol
));
797 /* Parse general expression, not looking for indexed addressing. */
799 parse_exp_not_indexed (const char *s
, expressionS
*op
)
806 if (sdcc_compat
&& (*p
== '<' || *p
== '>'))
810 case '<': /* LSB request */
813 case '>': /* MSB request */
814 make_shift
= cpu_mode
? 16 : 8;
821 op
->X_md
= indir
= is_indir (p
);
822 input_line_pointer
= (char*) s
;
827 error (_("missing operand"));
830 error (_("bad expression syntax"));
838 /* replace [op] by [op >> shift] */
840 op
->X_add_symbol
= make_expr_symbol (op
);
841 op
->X_add_number
= 0;
842 op
->X_op
= O_right_shift
;
843 memset (&data
, 0, sizeof (data
));
844 data
.X_op
= O_constant
;
845 data
.X_add_number
= make_shift
;
846 op
->X_op_symbol
= make_expr_symbol (&data
);
848 return input_line_pointer
;
852 unify_indexed (expressionS
*op
)
854 if (O_register
!= symbol_get_value_expression(op
->X_add_symbol
)->X_op
)
857 int rnum
= symbol_get_value_expression(op
->X_add_symbol
)->X_add_number
;
858 if ( ((REG_IX
!= rnum
) && (REG_IY
!= rnum
)) || contains_register(op
->X_op_symbol
) )
864 /* convert subtraction to addition of negative value */
865 if (O_subtract
== op
->X_op
)
868 minus
.X_op
= O_uminus
;
869 minus
.X_add_number
= 0;
870 minus
.X_add_symbol
= op
->X_op_symbol
;
871 minus
.X_op_symbol
= 0;
872 op
->X_op_symbol
= make_expr_symbol(&minus
);
875 /* clear X_add_number of the expression */
876 if (op
->X_add_number
!= 0)
879 memset (&add
, 0, sizeof (add
));
881 add
.X_add_number
= op
->X_add_number
;
882 add
.X_add_symbol
= op
->X_op_symbol
;
884 op
->X_add_symbol
= make_expr_symbol(&add
);
887 op
->X_add_symbol
= op
->X_op_symbol
;
889 op
->X_add_number
= rnum
;
894 /* Parse expression, change operator to O_md1 for indexed addressing*/
896 parse_exp (const char *s
, expressionS
*op
)
898 const char* res
= parse_exp_not_indexed (s
, op
);
903 if (unify_indexed(op
) && op
->X_md
)
907 if ( op
->X_md
&& ((REG_IX
== op
->X_add_number
)||(REG_IY
== op
->X_add_number
)) )
909 op
->X_add_symbol
= zero
;
914 /* parse SDCC syntax where index register offset placed before parentheses */
915 if (sdcc_compat
&& is_indir (res
))
919 res
= parse_exp (res
, op
);
920 if (op
->X_op
!= O_md1
|| op
->X_add_symbol
!= zero
)
923 op
->X_add_symbol
= make_expr_symbol (&off
);
932 /* Condition codes, including some synonyms provided by HiTech zas. */
933 static const struct reg_entry cc_tab
[] =
951 /* Parse condition code. */
953 parse_cc (const char *s
, char * op
)
957 struct reg_entry
* cc_p
;
959 for (i
= 0; i
< BUFLEN
; ++i
)
961 if (!ISALPHA (s
[i
])) /* Condition codes consist of letters only. */
963 buf
[i
] = TOLOWER (s
[i
]);
967 && ((s
[i
] == 0) || (s
[i
] == ',')))
970 cc_p
= bsearch (&key
, cc_tab
, ARRAY_SIZE (cc_tab
),
971 sizeof (cc_tab
[0]), key_cmp
);
988 emit_insn (char prefix
, char opcode
, const char * args
)
1003 void z80_cons_fix_new (fragS
*frag_p
, int offset
, int nbytes
, expressionS
*exp
)
1005 bfd_reloc_code_real_type r
[4] =
1013 if (nbytes
< 1 || nbytes
> 4)
1015 as_bad (_("unsupported BFD relocation size %u"), nbytes
);
1019 fix_new_exp (frag_p
, offset
, nbytes
, exp
, 0, r
[nbytes
-1]);
1024 emit_data_val (expressionS
* val
, int size
)
1027 bfd_reloc_code_real_type r_type
;
1029 p
= frag_more (size
);
1030 if (val
->X_op
== O_constant
)
1033 for (i
= 0; i
< size
; ++i
)
1034 p
[i
] = (char)(val
->X_add_number
>> (i
*8));
1040 case 1: r_type
= BFD_RELOC_8
; break;
1041 case 2: r_type
= BFD_RELOC_16
; break;
1042 case 3: r_type
= BFD_RELOC_24
; break;
1043 case 4: r_type
= BFD_RELOC_32
; break;
1044 case 8: r_type
= BFD_RELOC_64
; break;
1046 as_fatal (_("invalid data size %d"), size
);
1049 if ( (val
->X_op
== O_register
)
1050 || (val
->X_op
== O_md1
)
1051 || contains_register(val
->X_add_symbol
)
1052 || contains_register(val
->X_op_symbol
) )
1055 if (size
<= 2 && val
->X_op_symbol
)
1057 bfd_boolean simplify
= TRUE
;
1058 int shift
= symbol_get_value_expression(val
->X_op_symbol
)->X_add_number
;
1059 if (val
->X_op
== O_bit_and
&& shift
== (1 << (size
*8))-1)
1061 else if (val
->X_op
!= O_right_shift
)
1068 case 0: r_type
= BFD_RELOC_Z80_BYTE0
; break;
1069 case 8: r_type
= BFD_RELOC_Z80_BYTE1
; break;
1070 case 16: r_type
= BFD_RELOC_Z80_BYTE2
; break;
1071 case 24: r_type
= BFD_RELOC_Z80_BYTE3
; break;
1072 default: simplify
= FALSE
;
1075 else /* if (size == 2) */
1079 case 0: r_type
= BFD_RELOC_Z80_WORD0
; break;
1080 case 16: r_type
= BFD_RELOC_Z80_WORD1
; break;
1081 default: simplify
= FALSE
;
1087 val
->X_op
= O_symbol
;
1088 val
->X_op_symbol
= NULL
;
1089 val
->X_add_number
= 0;
1093 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
, val
, FALSE
, r_type
);
1097 emit_byte (expressionS
* val
, bfd_reloc_code_real_type r_type
)
1102 if (r_type
== BFD_RELOC_8
)
1104 emit_data_val (val
, 1);
1108 *p
= val
->X_add_number
;
1109 if ( contains_register(val
->X_add_symbol
) || contains_register(val
->X_op_symbol
) )
1113 else if ((r_type
== BFD_RELOC_8_PCREL
) && (val
->X_op
== O_constant
))
1115 as_bad (_("cannot make a relative jump to an absolute location"));
1117 else if (val
->X_op
== O_constant
)
1120 hi
= (BFD_RELOC_8
== r_type
) ? 255 : 127;
1122 if ((val
->X_add_number
< lo
) || (val
->X_add_number
> hi
))
1124 if (r_type
== BFD_RELOC_Z80_DISP8
)
1125 as_bad (_("offset too large"));
1127 as_warn (_("overflow"));
1132 /* For symbols only, constants are stored at begin of function */
1133 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 1, val
,
1134 (r_type
== BFD_RELOC_8_PCREL
) ? TRUE
: FALSE
, r_type
);
1139 emit_word (expressionS
* val
)
1141 emit_data_val (val
, (inst_mode
& INST_MODE_IL
) ? 3 : 2);
1145 emit_mx (char prefix
, char opcode
, int shift
, expressionS
* arg
)
1146 /* The operand m may be r, (hl), (ix+d), (iy+d),
1147 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1152 rnum
= arg
->X_add_number
;
1168 if ((prefix
== 0) && (rnum
& R_INDEX
))
1170 prefix
= (rnum
& R_IX
) ? 0xDD : 0xFD;
1171 if (!(ins_ok
& INS_EZ80
))
1172 check_mach (INS_IDX_HALF
);
1181 q
= frag_more (prefix
? 2 : 1);
1184 * q
++ = opcode
+ (rnum
<< shift
);
1187 if (ins_ok
& INS_GBZ80
)
1193 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1194 *q
= (prefix
) ? prefix
: (opcode
+ (6 << shift
));
1196 expressionS offset
= *arg
;
1197 offset
.X_op
= O_symbol
;
1198 offset
.X_add_number
= 0;
1199 emit_byte (&offset
, BFD_RELOC_Z80_DISP8
);
1204 *q
= opcode
+(6<<shift
);
1212 /* The operand m may be r, (hl), (ix+d), (iy+d),
1213 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1215 emit_m (char prefix
, char opcode
, const char *args
)
1220 p
= parse_exp (args
, &arg_m
);
1225 emit_mx (prefix
, opcode
, 0, &arg_m
);
1233 /* The operand m may be as above or one of the undocumented
1234 combinations (ix+d),r and (iy+d),r (if unportable instructions
1238 emit_mr (char prefix
, char opcode
, const char *args
)
1240 expressionS arg_m
, arg_r
;
1243 p
= parse_exp (args
, & arg_m
);
1250 p
= parse_exp (p
+ 1, & arg_r
);
1252 if ((arg_r
.X_md
== 0)
1253 && (arg_r
.X_op
== O_register
)
1254 && (arg_r
.X_add_number
< 8))
1255 opcode
+= arg_r
.X_add_number
- 6; /* Emit_mx () will add 6. */
1261 check_mach (INS_ROT_II_LD
);
1265 emit_mx (prefix
, opcode
, 0, & arg_m
);
1274 emit_sx (char prefix
, char opcode
, expressionS
* arg_p
)
1278 switch (arg_p
->X_op
)
1282 emit_mx (prefix
, opcode
, 0, arg_p
);
1289 q
= frag_more (prefix
? 2 : 1);
1293 emit_byte (arg_p
, BFD_RELOC_8
);
1298 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1300 emit_s (char prefix
, char opcode
, const char *args
)
1305 p
= parse_exp (args
, & arg_s
);
1306 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
1307 { /* possible instruction in generic format op A,x */
1308 if (!(ins_ok
& INS_EZ80
) && !sdcc_compat
)
1311 p
= parse_exp (p
, & arg_s
);
1313 emit_sx (prefix
, opcode
, & arg_s
);
1318 emit_call (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1321 const char *p
; char *q
;
1323 p
= parse_exp_not_indexed (args
, &addr
);
1335 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1337 emit_incdec (char prefix
, char opcode
, const char * args
)
1339 expressionS operand
;
1341 const char *p
; char *q
;
1343 p
= parse_exp (args
, &operand
);
1344 rnum
= operand
.X_add_number
;
1345 if ((! operand
.X_md
)
1346 && (operand
.X_op
== O_register
)
1349 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1351 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1352 *q
= prefix
+ ((rnum
& 3) << 4);
1356 if ((operand
.X_op
== O_md1
) || (operand
.X_op
== O_register
))
1357 emit_mx (0, opcode
, 3, & operand
);
1365 emit_jr (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1371 p
= parse_exp_not_indexed (args
, &addr
);
1378 addr
.X_add_number
--; /* pcrel computes after offset code */
1379 emit_byte (&addr
, BFD_RELOC_8_PCREL
);
1385 emit_jp (char prefix
, char opcode
, const char * args
)
1392 p
= parse_exp_not_indexed (args
, & addr
);
1395 rnum
= addr
.X_add_number
;
1396 if ((O_register
== addr
.X_op
) && (REG_HL
== (rnum
& ~R_INDEX
)))
1398 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1400 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1416 emit_im (char prefix
, char opcode
, const char * args
)
1422 p
= parse_exp (args
, & mode
);
1423 if (mode
.X_md
|| (mode
.X_op
!= O_constant
))
1426 switch (mode
.X_add_number
)
1430 ++mode
.X_add_number
;
1435 *q
= opcode
+ 8*mode
.X_add_number
;
1444 emit_pop (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1450 p
= parse_exp (args
, & regp
);
1452 && (regp
.X_op
== O_register
)
1453 && (regp
.X_add_number
& R_STACKABLE
))
1457 rnum
= regp
.X_add_number
;
1461 *q
++ = (rnum
&R_IX
)?0xDD:0xFD;
1465 *q
= opcode
+ ((rnum
& 3) << 4);
1474 emit_retcc (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1479 p
= parse_cc (args
, &cc
);
1485 return p
? p
: args
;
1489 emit_adc (char prefix
, char opcode
, const char * args
)
1496 p
= parse_exp (args
, &term
);
1499 error (_("bad instruction syntax"));
1503 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1506 switch (term
.X_add_number
)
1509 p
= emit_s (0, prefix
, p
);
1512 p
= parse_exp (p
, &term
);
1513 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1515 rnum
= term
.X_add_number
;
1516 if (R_ARITH
== (rnum
& (R_ARITH
| R_INDEX
)))
1520 *q
= opcode
+ ((rnum
& 3) << 4);
1532 emit_add (char prefix
, char opcode
, const char * args
)
1539 p
= parse_exp (args
, &term
);
1542 error (_("bad instruction syntax"));
1546 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1549 switch (term
.X_add_number
& ~R_INDEX
)
1552 p
= emit_s (0, prefix
, p
);
1555 lhs
= term
.X_add_number
;
1556 p
= parse_exp (p
, &term
);
1557 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1559 rhs
= term
.X_add_number
;
1561 && ((rhs
== lhs
) || ((rhs
& ~R_INDEX
) != REG_HL
)))
1563 q
= frag_more ((lhs
& R_INDEX
) ? 2 : 1);
1565 *q
++ = (lhs
& R_IX
) ? 0xDD : 0xFD;
1566 *q
= opcode
+ ((rhs
& 3) << 4);
1578 emit_bit (char prefix
, char opcode
, const char * args
)
1584 p
= parse_exp (args
, &b
);
1586 error (_("bad instruction syntax"));
1588 bn
= b
.X_add_number
;
1590 && (b
.X_op
== O_constant
)
1595 /* Bit : no optional third operand. */
1596 p
= emit_m (prefix
, opcode
+ (bn
<< 3), p
);
1598 /* Set, res : resulting byte can be copied to register. */
1599 p
= emit_mr (prefix
, opcode
+ (bn
<< 3), p
);
1607 emit_jpcc (char prefix
, char opcode
, const char * args
)
1612 p
= parse_cc (args
, & cc
);
1613 if (p
&& *p
++ == ',')
1614 p
= emit_call (0, opcode
+ cc
, p
);
1616 p
= (prefix
== (char)0xC3)
1617 ? emit_jp (0xE9, prefix
, args
)
1618 : emit_call (0, prefix
, args
);
1623 emit_jrcc (char prefix
, char opcode
, const char * args
)
1628 p
= parse_cc (args
, &cc
);
1629 if (p
&& *p
++ == ',')
1632 error (_("condition code invalid for jr"));
1634 p
= emit_jr (0, opcode
+ cc
, p
);
1637 p
= emit_jr (0, prefix
, args
);
1643 emit_ex (char prefix_in ATTRIBUTE_UNUSED
,
1644 char opcode_in ATTRIBUTE_UNUSED
, const char * args
)
1648 char prefix
, opcode
;
1650 p
= parse_exp_not_indexed (args
, &op
);
1654 error (_("bad instruction syntax"));
1658 prefix
= opcode
= 0;
1659 if (op
.X_op
== O_register
)
1660 switch (op
.X_add_number
| (op
.X_md
? 0x8000 : 0))
1663 if (TOLOWER (*p
++) == 'a' && TOLOWER (*p
++) == 'f')
1665 /* The scrubber changes '\'' to '`' in this context. */
1672 if (TOLOWER (*p
++) == 'h' && TOLOWER (*p
++) == 'l')
1676 p
= parse_exp (p
, & op
);
1677 if (op
.X_op
== O_register
1679 && (op
.X_add_number
& ~R_INDEX
) == REG_HL
)
1682 if (R_INDEX
& op
.X_add_number
)
1683 prefix
= (R_IX
& op
.X_add_number
) ? 0xDD : 0xFD;
1688 emit_insn (prefix
, opcode
, p
);
1696 emit_in (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1699 expressionS reg
, port
;
1703 p
= parse_exp (args
, ®
);
1706 error (_("bad instruction syntax"));
1710 p
= parse_exp (p
, &port
);
1712 && reg
.X_op
== O_register
1713 && (reg
.X_add_number
<= 7 || reg
.X_add_number
== REG_F
)
1716 if (port
.X_op
!= O_md1
&& port
.X_op
!= O_register
)
1718 if (REG_A
== reg
.X_add_number
)
1722 emit_byte (&port
, BFD_RELOC_8
);
1729 if (port
.X_add_number
== REG_C
|| port
.X_add_number
== REG_BC
)
1731 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
1733 else if (reg
.X_add_number
== REG_F
&& !(ins_ok
& INS_R800
))
1734 check_mach (INS_IN_F_C
);
1737 *q
= 0x40|((reg
.X_add_number
&7)<<3);
1749 emit_in0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1752 expressionS reg
, port
;
1756 p
= parse_exp (args
, ®
);
1759 error (_("bad instruction syntax"));
1763 p
= parse_exp (p
, &port
);
1765 && reg
.X_op
== O_register
1766 && reg
.X_add_number
<= 7
1768 && port
.X_op
!= O_md1
1769 && port
.X_op
!= O_register
)
1773 *q
= 0x00|(reg
.X_add_number
<< 3);
1774 emit_byte (&port
, BFD_RELOC_8
);
1782 emit_out (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1785 expressionS reg
, port
;
1789 p
= parse_exp (args
, & port
);
1792 error (_("bad instruction syntax"));
1795 p
= parse_exp (p
, ®
);
1797 { ill_op (); return p
; }
1798 /* Allow "out (c), 0" as unportable instruction. */
1799 if (reg
.X_op
== O_constant
&& reg
.X_add_number
== 0)
1801 check_mach (INS_OUT_C_0
);
1802 reg
.X_op
= O_register
;
1803 reg
.X_add_number
= 6;
1806 || reg
.X_op
!= O_register
1807 || reg
.X_add_number
> 7)
1810 if (port
.X_op
!= O_register
&& port
.X_op
!= O_md1
)
1812 if (REG_A
== reg
.X_add_number
)
1816 emit_byte (&port
, BFD_RELOC_8
);
1823 if (REG_C
== port
.X_add_number
|| port
.X_add_number
== REG_BC
)
1825 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
1829 *q
= 0x41 | (reg
.X_add_number
<< 3);
1838 emit_out0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1841 expressionS reg
, port
;
1845 p
= parse_exp (args
, & port
);
1848 error (_("bad instruction syntax"));
1851 p
= parse_exp (p
, ®
);
1853 && port
.X_op
!= O_register
1854 && port
.X_op
!= O_md1
1856 && reg
.X_op
== O_register
1857 && reg
.X_add_number
<= 7)
1861 *q
= 0x01 | (reg
.X_add_number
<< 3);
1862 emit_byte (&port
, BFD_RELOC_8
);
1870 emit_rst (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1876 p
= parse_exp_not_indexed (args
, &addr
);
1877 if (addr
.X_op
!= O_constant
)
1879 error ("rst needs constant address");
1883 if (addr
.X_add_number
& ~(7 << 3))
1888 *q
= opcode
+ (addr
.X_add_number
& (7 << 3));
1894 emit_ld_m_n(expressionS
*dst
, expressionS
*src
)
1895 { /* for 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n */
1898 expressionS dst_offset
;
1900 switch (dst
->X_add_number
)
1902 case REG_HL
: prefix
= 0x00; break;
1903 case REG_IX
: prefix
= 0xDD; break;
1904 case REG_IY
: prefix
= 0xFD; break;
1910 q
= frag_more (prefix
? 2 : 1);
1917 dst_offset
.X_op
= O_symbol
;
1918 dst_offset
.X_add_number
= 0;
1919 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
1921 emit_byte (src
, BFD_RELOC_8
);
1925 emit_ld_m_r(expressionS
*dst
, expressionS
*src
)
1926 { /* for 8-bit load register to memory instructions: LD (<expression>),r */
1929 expressionS dst_offset
;
1934 prefix
= (dst
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
1937 switch (dst
->X_add_number
)
1939 case REG_BC
: /* LD (BC),A */
1940 case REG_DE
: /* LD (DE),A */
1941 if (src
->X_add_number
== REG_A
)
1944 *q
= 0x02 | ((dst
->X_add_number
& 3) << 4);
1950 case REG_HL
: /* LD (HL),r or LD (ii+d),r */
1951 if (src
->X_add_number
<= 7)
1953 q
= frag_more (prefix
? 2 : 1);
1956 *q
= 0x70 | src
->X_add_number
;
1960 dst_offset
.X_op
= O_symbol
;
1961 dst_offset
.X_add_number
= 0;
1962 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
1970 default: /* LD (nn),A */
1971 if (src
->X_add_number
== REG_A
)
1984 emit_ld_m_rr(expressionS
*dst
, expressionS
*src
)
1985 { /* for 16-bit load register to memory instructions: LD (<expression>),rr */
1989 expressionS dst_offset
;
1993 case O_md1
: /* eZ80 instructions LD (ii+d),rr */
1994 case O_register
: /* eZ80 instructions LD (HL),rr */
1995 if (!(ins_ok
& INS_EZ80
)) /* 16-bit indirect load group is supported by eZ80 only */
1997 switch (dst
->X_add_number
)
1999 case REG_IX
: prefix
= 0xDD; break;
2000 case REG_IY
: prefix
= 0xFD; break;
2001 case REG_HL
: prefix
= 0xED; break;
2005 switch (src
->X_add_number
)
2007 case REG_BC
: opcode
= 0x0F; break;
2008 case REG_DE
: opcode
= 0x1F; break;
2009 case REG_HL
: opcode
= 0x2F; break;
2010 case REG_IX
: opcode
= (prefix
!= '\xfd') ? 0x3F : 0x3E; break;
2011 case REG_IY
: opcode
= (prefix
!= '\xfd') ? 0x3E : 0x3F; break;
2015 q
= frag_more (prefix
? 2 : 1);
2018 if (prefix
== '\xfd' || prefix
== '\xdd')
2021 dst_offset
.X_op
= O_symbol
;
2022 dst_offset
.X_add_number
= 0;
2023 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2026 default: /* LD (nn),rr */
2027 if (ins_ok
& INS_GBZ80
)
2029 /* GBZ80 supports only LD (nn),SP */
2030 if (src
->X_add_number
== REG_SP
)
2040 switch (src
->X_add_number
)
2042 case REG_BC
: prefix
= 0xED; opcode
= 0x43; break;
2043 case REG_DE
: prefix
= 0xED; opcode
= 0x53; break;
2044 case REG_HL
: prefix
= 0x00; opcode
= 0x22; break;
2045 case REG_IX
: prefix
= 0xDD; opcode
= 0x22; break;
2046 case REG_IY
: prefix
= 0xFD; opcode
= 0x22; break;
2047 case REG_SP
: prefix
= 0xED; opcode
= 0x73; break;
2052 q
= frag_more (prefix
? 2 : 1);
2061 emit_ld_r_m (expressionS
*dst
, expressionS
*src
)
2062 { /* for 8-bit memory load to register: LD r,(xxx) */
2066 expressionS src_offset
;
2068 if (dst
->X_add_number
== REG_A
&& src
->X_op
== O_register
)
2069 { /* LD A,(BC) or LD A,(DE) */
2070 switch (src
->X_add_number
)
2072 case REG_BC
: opcode
= 0x0A; break;
2073 case REG_DE
: opcode
= 0x1A; break;
2088 if (dst
->X_add_number
> 7)
2090 opcode
= 0x46; /* LD B,(HL) */
2091 switch (src
->X_add_number
)
2093 case REG_HL
: prefix
= 0x00; break;
2094 case REG_IX
: prefix
= 0xDD; break;
2095 case REG_IY
: prefix
= 0xFD; break;
2099 q
= frag_more (prefix
? 2 : 1);
2102 *q
= opcode
| ((dst
->X_add_number
& 7) << 3);
2106 src_offset
.X_op
= O_symbol
;
2107 src_offset
.X_add_number
= 0;
2108 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2111 default: /* LD A,(nn) */
2112 if (dst
->X_add_number
== REG_A
)
2122 emit_ld_r_n (expressionS
*dst
, expressionS
*src
)
2123 { /* for 8-bit immediate value load to register: LD r,n */
2127 switch (dst
->X_add_number
)
2150 q
= frag_more (prefix
? 2 : 1);
2153 if (ins_ok
& INS_GBZ80
)
2155 else if (!(ins_ok
& INS_EZ80
))
2156 check_mach (INS_IDX_HALF
);
2159 *q
= 0x06 | ((dst
->X_add_number
& 7) << 3);
2160 emit_byte (src
, BFD_RELOC_8
);
2164 emit_ld_r_r (expressionS
*dst
, expressionS
*src
)
2165 { /* mostly 8-bit load register from register instructions: LD r,r */
2166 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2172 switch (dst
->X_add_number
)
2175 switch (src
->X_add_number
)
2177 case REG_HL
: prefix
= 0x00; break;
2178 case REG_IX
: prefix
= 0xDD; break;
2179 case REG_IY
: prefix
= 0xFD; break;
2183 if (ins_ok
& INS_GBZ80
)
2188 if (!(ins_ok
& INS_EZ80
))
2190 if (src
->X_add_number
!= REG_I
)
2193 error (_("ADL mode instruction"));
2199 if (src
->X_add_number
== REG_HL
)
2201 if (!(ins_ok
& INS_EZ80
))
2204 error (_("ADL mode instruction"));
2208 else if (src
->X_add_number
== REG_A
)
2217 if (!(ins_ok
& INS_EZ80
) || (src
->X_add_number
!= REG_A
))
2220 error (_("ADL mode instruction"));
2225 if (src
->X_add_number
== REG_A
) /* LD R,A */
2234 if (src
->X_add_number
== REG_I
) /* LD A,I */
2240 else if (src
->X_add_number
== REG_R
) /* LD A,R */
2246 else if (src
->X_add_number
== REG_MB
) /* LD A,MB */
2248 if (!(ins_ok
& INS_EZ80
))
2253 error (_("ADL mode instruction"));
2284 switch (src
->X_add_number
)
2295 ill_op (); /* LD iiH/L,H/L are not permitted */
2299 if (prefix
== '\xfd' || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2300 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2306 if (prefix
== '\xdd' || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2307 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2314 opcode
= 0x40 + ((dst
->X_add_number
& 7) << 3) + (src
->X_add_number
& 7);
2316 if ((ins_ok
& INS_GBZ80
) && prefix
!= 0)
2318 if (ii_halves
&& !(ins_ok
& INS_EZ80
))
2319 check_mach (INS_IDX_HALF
);
2320 if (prefix
== 0 && (ins_ok
& INS_EZ80
))
2324 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2325 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2326 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2327 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2328 as_warn(_("unsupported instruction, assembled as NOP"));
2334 q
= frag_more (prefix
? 2 : 1);
2341 emit_ld_rr_m (expressionS
*dst
, expressionS
*src
)
2342 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2346 expressionS src_offset
;
2348 /* GBZ80 has no support for 16-bit load from memory instructions */
2349 if (ins_ok
& INS_GBZ80
)
2355 case O_md1
: /* LD rr,(ii+d) */
2356 prefix
= (src
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2358 case O_register
: /* LD rr,(HL) */
2359 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2360 if (!(ins_ok
& INS_EZ80
))
2362 switch (dst
->X_add_number
)
2364 case REG_BC
: opcode
= 0x07; break;
2365 case REG_DE
: opcode
= 0x17; break;
2366 case REG_HL
: opcode
= 0x27; break;
2367 case REG_IX
: opcode
= (!prefix
|| prefix
== '\xdd') ? 0x37 : 0x31; break;
2368 case REG_IY
: opcode
= prefix
? ((prefix
== '\xdd') ? 0x31 : 0x37) : 0x36; break;
2375 if (prefix
!= '\xed')
2378 src_offset
.X_op
= O_symbol
;
2379 src_offset
.X_add_number
= 0;
2380 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2383 default: /* LD rr,(nn) */
2384 switch (dst
->X_add_number
)
2386 case REG_BC
: prefix
= 0xED; opcode
= 0x4B; break;
2387 case REG_DE
: prefix
= 0xED; opcode
= 0x5B; break;
2388 case REG_HL
: prefix
= 0x00; opcode
= 0x2A; break;
2389 case REG_SP
: prefix
= 0xED; opcode
= 0x7B; break;
2390 case REG_IX
: prefix
= 0xDD; opcode
= 0x2A; break;
2391 case REG_IY
: prefix
= 0xFD; opcode
= 0x2A; break;
2395 q
= frag_more (prefix
? 2 : 1);
2405 emit_ld_rr_nn (expressionS
*dst
, expressionS
*src
)
2406 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2409 char opcode
= 0x21; /* LD HL,nn */
2410 switch (dst
->X_add_number
)
2423 opcode
= 0x01 + ((dst
->X_add_number
& 3) << 4);
2429 if (prefix
&& (ins_ok
& INS_GBZ80
))
2431 q
= frag_more (prefix
? 2 : 1);
2439 emit_ld (char prefix_in ATTRIBUTE_UNUSED
, char opcode_in ATTRIBUTE_UNUSED
,
2442 expressionS dst
, src
;
2445 p
= parse_exp (args
, & dst
);
2447 error (_("bad instruction syntax"));
2448 p
= parse_exp (p
, & src
);
2452 if (src
.X_op
== O_register
)
2454 if (src
.X_add_number
<= 7)
2455 emit_ld_m_r (& dst
, & src
); /* LD (xxx),r */
2457 emit_ld_m_rr (& dst
, & src
); /* LD (xxx),rr */
2460 emit_ld_m_n (& dst
, & src
); /* LD (hl),n or LD (ix/y+r),n */
2462 else if (dst
.X_op
== O_register
)
2466 if (dst
.X_add_number
<= 7)
2467 emit_ld_r_m (& dst
, & src
);
2469 emit_ld_rr_m (& dst
, & src
);
2471 else if (src
.X_op
== O_register
)
2472 emit_ld_r_r (& dst
, & src
);
2473 else if ((dst
.X_add_number
& ~R_INDEX
) <= 7)
2474 emit_ld_r_n (& dst
, & src
);
2476 emit_ld_rr_nn (& dst
, & src
);
2485 emit_lddldi (char prefix
, char opcode
, const char * args
)
2487 expressionS dst
, src
;
2491 if (!(ins_ok
& INS_GBZ80
))
2492 return emit_insn(prefix
, opcode
, args
);
2494 p
= parse_exp (args
, & dst
);
2496 error (_("bad instruction syntax"));
2497 p
= parse_exp (args
, & src
);
2499 if (dst
.X_op
!= O_register
|| src
.X_op
!= O_register
)
2502 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2503 opcode
= (opcode
& 0x08) * 2 + 0x22;
2506 && dst
.X_add_number
== REG_HL
2508 && src
.X_add_number
== REG_A
)
2509 opcode
|= 0x00; /* LDx (HL),A */
2510 else if (dst
.X_md
== 0
2511 && dst
.X_add_number
== REG_A
2513 && src
.X_add_number
== REG_HL
)
2514 opcode
|= 0x08; /* LDx A,(HL) */
2524 emit_ldh (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2527 expressionS dst
, src
;
2531 p
= parse_exp (args
, & dst
);
2534 error (_("bad instruction syntax"));
2538 p
= parse_exp (p
, & src
);
2540 && dst
.X_op
== O_register
2541 && dst
.X_add_number
== REG_A
2543 && src
.X_op
!= O_md1
2544 && src
.X_op
!= O_register
)
2548 emit_byte (& src
, BFD_RELOC_8
);
2550 else if (dst
.X_md
!= 0
2551 && dst
.X_op
!= O_md1
2553 && src
.X_op
== O_register
2554 && src
.X_add_number
== REG_A
)
2556 if (dst
.X_op
== O_register
)
2558 if (dst
.X_add_number
== REG_C
)
2570 emit_byte (& dst
, BFD_RELOC_8
);
2580 parse_lea_pea_args (const char * args
, expressionS
*op
)
2583 p
= parse_exp (args
, op
);
2584 if (sdcc_compat
&& *p
== ',' && op
->X_op
== O_register
)
2587 p
= parse_exp (p
+ 1, &off
);
2589 op
->X_add_symbol
= make_expr_symbol (&off
);
2595 emit_lea (char prefix
, char opcode
, const char * args
)
2597 expressionS dst
, src
;
2602 p
= parse_exp (args
, & dst
);
2603 if (dst
.X_md
!= 0 || dst
.X_op
!= O_register
)
2606 rnum
= dst
.X_add_number
;
2612 opcode
= 0x02 | ((rnum
& 0x03) << 4);
2615 opcode
= 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2618 opcode
= 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2625 error (_("bad instruction syntax"));
2627 p
= parse_lea_pea_args (p
, & src
);
2628 if (src
.X_md
!= 0 || src
.X_op
!= O_add
/*&& src.X_op != O_register*/)
2631 rnum
= src
.X_add_number
;
2636 case O_register
: /* permit instructions like LEA rr,IX without displacement specified */
2637 src
.X_add_symbol
= zero
;
2646 opcode
= (opcode
== 0x33) ? 0x55 : (opcode
|0x00);
2649 opcode
= (opcode
== 0x32) ? 0x54 : (opcode
|0x01);
2656 src
.X_op
= O_symbol
;
2657 src
.X_add_number
= 0;
2658 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2664 emit_mlt (char prefix
, char opcode
, const char * args
)
2670 p
= parse_exp (args
, & arg
);
2671 if (arg
.X_md
!= 0 || arg
.X_op
!= O_register
|| !(arg
.X_add_number
& R_ARITH
))
2676 *q
= opcode
| ((arg
.X_add_number
& 3) << 4);
2682 emit_pea (char prefix
, char opcode
, const char * args
)
2688 p
= parse_lea_pea_args (args
, & arg
);
2690 || (/*arg.X_op != O_register &&*/ arg
.X_op
!= O_add
)
2691 || !(arg
.X_add_number
& R_INDEX
))
2693 /* PEA ii without displacement is mostly typo,
2694 because there is PUSH instruction which is shorter and faster */
2695 /*if (arg.X_op == O_register)
2696 as_warn(_("PEA is used without displacement, use PUSH instead"));*/
2700 *q
= opcode
+ (arg
.X_add_number
== REG_IY
? 1 : 0);
2702 arg
.X_op
= O_symbol
;
2703 arg
.X_add_number
= 0;
2704 emit_byte (& arg
, BFD_RELOC_Z80_DISP8
);
2710 emit_reti (char prefix
, char opcode
, const char * args
)
2712 if (ins_ok
& INS_GBZ80
)
2713 return emit_insn(0x00, 0xD9, args
);
2715 return emit_insn(prefix
, opcode
, args
);
2719 emit_tst (char prefix
, char opcode
, const char *args
)
2726 p
= parse_exp (args
, & arg_s
);
2727 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
2729 if (!(ins_ok
& INS_EZ80
))
2732 p
= parse_exp (p
, & arg_s
);
2735 rnum
= arg_s
.X_add_number
;
2742 rnum
= arg_s
.X_add_number
;
2743 if (arg_s
.X_md
!= 0)
2752 *q
= opcode
| (rnum
<< 3);
2760 emit_byte (& arg_s
, BFD_RELOC_8
);
2766 emit_tstio (char prefix
, char opcode
, const char *args
)
2772 p
= parse_exp (args
, & arg
);
2773 if (arg
.X_md
|| arg
.X_op
== O_register
|| arg
.X_op
== O_md1
)
2779 emit_byte(& arg
, BFD_RELOC_8
);
2785 emit_data (int size ATTRIBUTE_UNUSED
)
2792 if (is_it_end_of_statement ())
2794 demand_empty_rest_of_line ();
2797 p
= skip_space (input_line_pointer
);
2801 if (*p
== '\"' || *p
== '\'')
2803 for (quote
= *p
, q
= ++p
, cnt
= 0; *p
&& quote
!= *p
; ++p
, ++cnt
)
2805 u
= frag_more (cnt
);
2808 as_warn (_("unterminated string"));
2810 p
= skip_space (p
+1);
2814 p
= parse_exp (p
, &exp
);
2815 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
2821 as_warn (_("parentheses ignored"));
2822 emit_byte (&exp
, BFD_RELOC_8
);
2826 while (*p
++ == ',') ;
2827 input_line_pointer
= (char *)(p
-1);
2836 if (is_it_end_of_statement ())
2838 demand_empty_rest_of_line ();
2841 p
= skip_space (input_line_pointer
);
2845 p
= parse_exp (p
, &exp
);
2846 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
2852 as_warn (_("parentheses ignored"));
2853 emit_data_val (&exp
, size
);
2855 } while (*p
++ == ',') ;
2856 input_line_pointer
= (char *)(p
-1);
2859 /* next functions were commented out because it is difficult to mix
2860 both ADL and Z80 mode instructions within one COFF file:
2861 objdump cannot recognize point of mode switching.
2864 set_cpu_mode (int mode
)
2866 if (ins_ok
& INS_EZ80
)
2869 error (_("CPU mode is unsupported by target"));
2873 assume (int arg ATTRIBUTE_UNUSED
)
2879 input_line_pointer
= (char*)skip_space (input_line_pointer
);
2880 c
= get_symbol_name (& name
);
2881 if (strncasecmp(name
, "ADL", 4) != 0)
2887 restore_line_pointer (c
);
2888 input_line_pointer
= (char*)skip_space (input_line_pointer
);
2889 if (*input_line_pointer
++ != '=')
2891 error (_("assignment expected"));
2894 input_line_pointer
= (char*)skip_space (input_line_pointer
);
2895 n
= get_single_number ();
2901 emit_mulub (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2905 p
= skip_space (args
);
2906 if (TOLOWER (*p
++) != 'a' || *p
++ != ',')
2912 reg
= TOLOWER (*p
++);
2919 check_mach (INS_R800
);
2920 if (!*skip_space (p
))
2924 *q
= opcode
+ ((reg
- 'b') << 3);
2936 emit_muluw (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2940 p
= skip_space (args
);
2941 if (TOLOWER (*p
++) != 'h' || TOLOWER (*p
++) != 'l' || *p
++ != ',')
2948 p
= parse_exp (p
, & reg
);
2950 if ((!reg
.X_md
) && reg
.X_op
== O_register
)
2951 switch (reg
.X_add_number
)
2955 check_mach (INS_R800
);
2958 *q
= opcode
+ ((reg
.X_add_number
& 3) << 4);
2968 assemble_suffix (const char **suffix
)
2971 const char sf
[8][4] =
2991 for (i
= 0; (i
< 3) && (ISALPHA (*p
)); i
++)
2992 sbuf
[i
] = TOLOWER (*p
++);
2993 if (*p
&& !ISSPACE(*p
))
2998 t
= bsearch(sbuf
, sf
, ARRAY_SIZE (sf
), sizeof(sf
[0]), (int(*)(const void*, const void*))strcmp
);
3005 i
= cpu_mode
? 0x5B : 0x52;
3008 i
= cpu_mode
? 0x49 : 0x40;
3011 i
= cpu_mode
? 0x5B : 0x49;
3020 i
= cpu_mode
? 0x52 : 0x40;
3029 *frag_more(1) = (char)i
;
3032 case 0x40: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IS
; break;
3033 case 0x49: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IS
; break;
3034 case 0x52: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IL
; break;
3035 case 0x5B: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IL
; break;
3043 #if defined(OBJ_ELF)
3044 return obj_elf_section (arg
);
3045 #elif defined(OBJ_COFF)
3046 return obj_coff_section (arg
);
3048 #error Unknown object format
3058 as_fatal (_("Invalid directive"));
3061 ins_ok
&= INS_MARCH_MASK
;
3063 if (old_ins
!= ins_ok
)
3068 ignore (int arg ATTRIBUTE_UNUSED
)
3070 ignore_rest_of_line ();
3078 as_fatal (_("Invalid directive"));
3079 for (p
= input_line_pointer
; *p
&& *p
!= '(' && *p
!= '\n'; p
++)
3086 ignore_rest_of_line ();
3092 /* Port specific pseudo ops. */
3093 const pseudo_typeS md_pseudo_table
[] =
3095 { ".area", area
, 0},
3096 { ".assume", assume
, 0},
3097 { ".ez80", set_inss
, INS_EZ80
},
3098 { ".gbz80", set_inss
, INS_GBZ80
},
3099 { ".module", ignore
, 0},
3100 { ".optsdcc", ignore
, 0},
3101 { ".r800", set_inss
, INS_R800
},
3102 { ".set", s_set
, 0},
3103 { ".z180", set_inss
, INS_Z180
},
3104 { ".z80", set_inss
, INS_Z80
},
3105 { "db" , emit_data
, 1},
3106 { "d24", z80_cons
, 3},
3107 { "d32", z80_cons
, 4},
3108 { "def24", z80_cons
, 3},
3109 { "def32", z80_cons
, 4},
3110 { "defb", emit_data
, 1},
3111 { "defm", emit_data
, 1},
3112 { "defs", s_space
, 1}, /* Synonym for ds on some assemblers. */
3113 { "defw", z80_cons
, 2},
3114 { "ds", s_space
, 1}, /* Fill with bytes rather than words. */
3115 { "dw", z80_cons
, 2},
3116 { "psect", psect
, 0}, /* TODO: Translate attributes. */
3117 { "set", 0, 0}, /* Real instruction on z80. */
3121 static table_t instab
[] =
3123 { "adc", 0x88, 0x4A, emit_adc
, INS_ALL
},
3124 { "add", 0x80, 0x09, emit_add
, INS_ALL
},
3125 { "and", 0x00, 0xA0, emit_s
, INS_ALL
},
3126 { "bit", 0xCB, 0x40, emit_bit
, INS_ALL
},
3127 { "call", 0xCD, 0xC4, emit_jpcc
, INS_ALL
},
3128 { "ccf", 0x00, 0x3F, emit_insn
, INS_ALL
},
3129 { "cp", 0x00, 0xB8, emit_s
, INS_ALL
},
3130 { "cpd", 0xED, 0xA9, emit_insn
, INS_NOT_GBZ80
},
3131 { "cpdr", 0xED, 0xB9, emit_insn
, INS_NOT_GBZ80
},
3132 { "cpi", 0xED, 0xA1, emit_insn
, INS_NOT_GBZ80
},
3133 { "cpir", 0xED, 0xB1, emit_insn
, INS_NOT_GBZ80
},
3134 { "cpl", 0x00, 0x2F, emit_insn
, INS_ALL
},
3135 { "daa", 0x00, 0x27, emit_insn
, INS_ALL
},
3136 { "dec", 0x0B, 0x05, emit_incdec
,INS_ALL
},
3137 { "di", 0x00, 0xF3, emit_insn
, INS_ALL
},
3138 { "djnz", 0x00, 0x10, emit_jr
, INS_NOT_GBZ80
},
3139 { "ei", 0x00, 0xFB, emit_insn
, INS_ALL
},
3140 { "ex", 0x00, 0x00, emit_ex
, INS_NOT_GBZ80
},
3141 { "exx", 0x00, 0xD9, emit_insn
, INS_NOT_GBZ80
},
3142 { "halt", 0x00, 0x76, emit_insn
, INS_ALL
},
3143 { "im", 0xED, 0x46, emit_im
, INS_NOT_GBZ80
},
3144 { "in", 0x00, 0x00, emit_in
, INS_NOT_GBZ80
},
3145 { "in0", 0xED, 0x00, emit_in0
, INS_Z180
|INS_EZ80
},
3146 { "inc", 0x03, 0x04, emit_incdec
,INS_ALL
},
3147 { "ind", 0xED, 0xAA, emit_insn
, INS_NOT_GBZ80
},
3148 { "ind2", 0xED, 0x8C, emit_insn
, INS_EZ80
},
3149 { "ind2r",0xED, 0x9C, emit_insn
, INS_EZ80
},
3150 { "indm", 0xED, 0x8A, emit_insn
, INS_EZ80
},
3151 { "indmr",0xED, 0x9A, emit_insn
, INS_EZ80
},
3152 { "indr", 0xED, 0xBA, emit_insn
, INS_NOT_GBZ80
},
3153 { "indrx",0xED, 0xCA, emit_insn
, INS_EZ80
},
3154 { "ini", 0xED, 0xA2, emit_insn
, INS_NOT_GBZ80
},
3155 { "ini2", 0xED, 0x84, emit_insn
, INS_EZ80
},
3156 { "ini2r",0xED, 0x94, emit_insn
, INS_EZ80
},
3157 { "inim", 0xED, 0x82, emit_insn
, INS_EZ80
},
3158 { "inimr",0xED, 0x92, emit_insn
, INS_EZ80
},
3159 { "inir", 0xED, 0xB2, emit_insn
, INS_NOT_GBZ80
},
3160 { "inirx",0xED, 0xC2, emit_insn
, INS_EZ80
},
3161 { "jp", 0xC3, 0xC2, emit_jpcc
, INS_ALL
},
3162 { "jr", 0x18, 0x20, emit_jrcc
, INS_ALL
},
3163 { "ld", 0x00, 0x00, emit_ld
, INS_ALL
},
3164 { "ldd", 0xED, 0xA8, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3165 { "lddr", 0xED, 0xB8, emit_insn
, INS_NOT_GBZ80
},
3166 { "ldh", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3167 { "ldhl", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3168 { "ldi", 0xED, 0xA0, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3169 { "ldir", 0xED, 0xB0, emit_insn
, INS_NOT_GBZ80
},
3170 { "lea", 0xED, 0x02, emit_lea
, INS_EZ80
},
3171 { "mlt", 0xED, 0x4C, emit_mlt
, INS_Z180
|INS_EZ80
},
3172 { "mulub",0xED, 0xC5, emit_mulub
,INS_R800
},
3173 { "muluw",0xED, 0xC3, emit_muluw
,INS_R800
},
3174 { "neg", 0xed, 0x44, emit_insn
, INS_NOT_GBZ80
},
3175 { "nop", 0x00, 0x00, emit_insn
, INS_ALL
},
3176 { "or", 0x00, 0xB0, emit_s
, INS_ALL
},
3177 { "otd2r",0xED, 0xBC, emit_insn
, INS_EZ80
},
3178 { "otdm", 0xED, 0x8B, emit_insn
, INS_Z180
|INS_EZ80
},
3179 { "otdmr",0xED, 0x9B, emit_insn
, INS_Z180
|INS_EZ80
},
3180 { "otdr", 0xED, 0xBB, emit_insn
, INS_NOT_GBZ80
},
3181 { "otdrx",0xED, 0xCB, emit_insn
, INS_EZ80
},
3182 { "oti2r",0xED, 0xB4, emit_insn
, INS_EZ80
},
3183 { "otim", 0xED, 0x83, emit_insn
, INS_Z180
|INS_EZ80
},
3184 { "otimr",0xED, 0x93, emit_insn
, INS_Z180
|INS_EZ80
},
3185 { "otir", 0xED, 0xB3, emit_insn
, INS_NOT_GBZ80
},
3186 { "otirx",0xED, 0xC3, emit_insn
, INS_EZ80
},
3187 { "out", 0x00, 0x00, emit_out
, INS_NOT_GBZ80
},
3188 { "out0", 0xED, 0x01, emit_out0
, INS_Z180
|INS_EZ80
},
3189 { "outd", 0xED, 0xAB, emit_insn
, INS_NOT_GBZ80
},
3190 { "outd2",0xED, 0xAC, emit_insn
, INS_EZ80
},
3191 { "outi", 0xED, 0xA3, emit_insn
, INS_NOT_GBZ80
},
3192 { "outi2",0xED, 0xA4, emit_insn
, INS_EZ80
},
3193 { "pea", 0xED, 0x65, emit_pea
, INS_EZ80
},
3194 { "pop", 0x00, 0xC1, emit_pop
, INS_ALL
},
3195 { "push", 0x00, 0xC5, emit_pop
, INS_ALL
},
3196 { "res", 0xCB, 0x80, emit_bit
, INS_ALL
},
3197 { "ret", 0xC9, 0xC0, emit_retcc
,INS_ALL
},
3198 { "reti", 0xED, 0x4D, emit_reti
, INS_ALL
}, /*GBZ80 has its own opcode for it*/
3199 { "retn", 0xED, 0x45, emit_insn
, INS_NOT_GBZ80
},
3200 { "rl", 0xCB, 0x10, emit_mr
, INS_ALL
},
3201 { "rla", 0x00, 0x17, emit_insn
, INS_ALL
},
3202 { "rlc", 0xCB, 0x00, emit_mr
, INS_ALL
},
3203 { "rlca", 0x00, 0x07, emit_insn
, INS_ALL
},
3204 { "rld", 0xED, 0x6F, emit_insn
, INS_NOT_GBZ80
},
3205 { "rr", 0xCB, 0x18, emit_mr
, INS_ALL
},
3206 { "rra", 0x00, 0x1F, emit_insn
, INS_ALL
},
3207 { "rrc", 0xCB, 0x08, emit_mr
, INS_ALL
},
3208 { "rrca", 0x00, 0x0F, emit_insn
, INS_ALL
},
3209 { "rrd", 0xED, 0x67, emit_insn
, INS_NOT_GBZ80
},
3210 { "rsmix",0xED, 0x7E, emit_insn
, INS_EZ80
},
3211 { "rst", 0x00, 0xC7, emit_rst
, INS_ALL
},
3212 { "sbc", 0x98, 0x42, emit_adc
, INS_ALL
},
3213 { "scf", 0x00, 0x37, emit_insn
, INS_ALL
},
3214 { "set", 0xCB, 0xC0, emit_bit
, INS_ALL
},
3215 { "sla", 0xCB, 0x20, emit_mr
, INS_ALL
},
3216 { "sli", 0xCB, 0x30, emit_mr
, INS_SLI
},
3217 { "sll", 0xCB, 0x30, emit_mr
, INS_SLI
},
3218 { "slp", 0xED, 0x76, emit_insn
, INS_Z180
|INS_EZ80
},
3219 { "sra", 0xCB, 0x28, emit_mr
, INS_ALL
},
3220 { "srl", 0xCB, 0x38, emit_mr
, INS_ALL
},
3221 { "stmix",0xED, 0x7D, emit_insn
, INS_EZ80
},
3222 { "stop", 0x00, 0x10, emit_insn
, INS_GBZ80
},
3223 { "sub", 0x00, 0x90, emit_s
, INS_ALL
},
3224 { "swap", 0xCB, 0x30, emit_mr
, INS_GBZ80
},
3225 { "tst", 0xED, 0x04, emit_tst
, INS_Z180
|INS_EZ80
},
3226 { "tstio",0xED, 0x74, emit_tstio
,INS_Z180
|INS_EZ80
},
3227 { "xor", 0x00, 0xA8, emit_s
, INS_ALL
},
3231 md_assemble (char *str
)
3239 inst_mode
= cpu_mode
? (INST_MODE_L
| INST_MODE_IL
) : (INST_MODE_S
| INST_MODE_IS
);
3240 old_ptr
= input_line_pointer
;
3241 p
= skip_space (str
);
3242 for (i
= 0; (i
< BUFLEN
) && (ISALPHA (*p
) || ISDIGIT (*p
));)
3243 buf
[i
++] = TOLOWER (*p
++);
3247 buf
[BUFLEN
-3] = buf
[BUFLEN
-2] = '.'; /* Mark opcode as abbreviated. */
3249 as_bad (_("Unknown instruction '%s'"), buf
);
3253 if ((*p
) && (!ISSPACE (*p
)))
3255 if (*p
!= '.' || !(ins_ok
& INS_EZ80
) || !assemble_suffix(&p
))
3257 as_bad (_("syntax error"));
3265 insp
= bsearch (&key
, instab
, ARRAY_SIZE (instab
),
3266 sizeof (instab
[0]), key_cmp
);
3267 if (!insp
|| (insp
->inss
&& !(insp
->inss
& ins_ok
)))
3269 as_bad (_("Unknown instruction '%s'"), buf
);
3274 p
= insp
->fp (insp
->prefix
, insp
->opcode
, p
);
3276 if ((!err_flag
) && *p
)
3277 as_bad (_("junk at end of line, first unrecognized character is `%c'"),
3282 input_line_pointer
= old_ptr
;
3286 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg ATTRIBUTE_UNUSED
)
3288 long val
= * (long *) valP
;
3289 char *p_lit
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3291 switch (fixP
->fx_r_type
)
3293 case BFD_RELOC_8_PCREL
:
3296 fixP
->fx_no_overflow
= 1;
3301 fixP
->fx_no_overflow
= (-128 <= val
&& val
< 128);
3302 if (!fixP
->fx_no_overflow
)
3303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3304 _("relative jump out of range"));
3310 case BFD_RELOC_Z80_DISP8
:
3313 fixP
->fx_no_overflow
= 1;
3318 fixP
->fx_no_overflow
= (-128 <= val
&& val
< 128);
3319 if (!fixP
->fx_no_overflow
)
3320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3321 _("index offset out of range"));
3327 case BFD_RELOC_Z80_BYTE0
:
3329 fixP
->fx_no_overflow
= 1;
3330 if (fixP
->fx_addsy
== NULL
)
3334 case BFD_RELOC_Z80_BYTE1
:
3335 *p_lit
++ = (val
>> 8);
3336 fixP
->fx_no_overflow
= 1;
3337 if (fixP
->fx_addsy
== NULL
)
3341 case BFD_RELOC_Z80_BYTE2
:
3342 *p_lit
++ = (val
>> 16);
3343 fixP
->fx_no_overflow
= 1;
3344 if (fixP
->fx_addsy
== NULL
)
3348 case BFD_RELOC_Z80_BYTE3
:
3349 *p_lit
++ = (val
>> 24);
3350 fixP
->fx_no_overflow
= 1;
3351 if (fixP
->fx_addsy
== NULL
)
3356 if (val
> 255 || val
< -128)
3357 as_warn_where (fixP
->fx_file
, fixP
->fx_line
, _("overflow"));
3359 fixP
->fx_no_overflow
= 1;
3360 if (fixP
->fx_addsy
== NULL
)
3364 case BFD_RELOC_Z80_WORD1
:
3365 *p_lit
++ = (val
>> 16);
3366 *p_lit
++ = (val
>> 24);
3367 fixP
->fx_no_overflow
= 1;
3368 if (fixP
->fx_addsy
== NULL
)
3372 case BFD_RELOC_Z80_WORD0
:
3375 *p_lit
++ = (val
>> 8);
3376 fixP
->fx_no_overflow
= 1;
3377 if (fixP
->fx_addsy
== NULL
)
3381 case BFD_RELOC_24
: /* Def24 may produce this. */
3383 *p_lit
++ = (val
>> 8);
3384 *p_lit
++ = (val
>> 16);
3385 fixP
->fx_no_overflow
= 1;
3386 if (fixP
->fx_addsy
== NULL
)
3390 case BFD_RELOC_32
: /* Def32 and .long may produce this. */
3392 *p_lit
++ = (val
>> 8);
3393 *p_lit
++ = (val
>> 16);
3394 *p_lit
++ = (val
>> 24);
3395 if (fixP
->fx_addsy
== NULL
)
3400 printf (_("md_apply_fix: unknown r_type 0x%x\n"), fixP
->fx_r_type
);
3405 /* GAS will call this to generate a reloc. GAS will pass the
3406 resulting reloc to `bfd_install_relocation'. This currently works
3407 poorly, as `bfd_install_relocation' often does the wrong thing, and
3408 instances of `tc_gen_reloc' have been written to work around the
3409 problems, which in turns makes it difficult to fix
3410 `bfd_install_relocation'. */
3412 /* If while processing a fixup, a reloc really
3413 needs to be created then it is done here. */
3416 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3420 if (! bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
))
3422 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3423 _("reloc %d not supported by object file format"),
3424 (int) fixp
->fx_r_type
);
3428 reloc
= XNEW (arelent
);
3429 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3430 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3431 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3432 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3433 reloc
->addend
= fixp
->fx_offset
;
3439 z80_tc_label_is_local (const char *name
)
3443 if (local_label_prefix
== NULL
)
3445 for (p
= local_label_prefix
, n
= name
; *p
&& *n
&& *n
== *p
; p
++, n
++)
3450 /* Parse floating point number from string and compute mantissa and
3451 exponent. Mantissa is normalized.
3453 #define EXP_MIN -0x10000
3454 #define EXP_MAX 0x10000
3456 str_to_broken_float (bfd_boolean
*signP
, bfd_uint64_t
*mantissaP
, int *expP
)
3460 bfd_uint64_t mantissa
= 0;
3464 p
= (char*)skip_space (input_line_pointer
);
3467 if (sign
|| *p
== '+')
3469 if (strncasecmp(p
, "NaN", 3) == 0)
3473 input_line_pointer
= p
+ 3;
3476 if (strncasecmp(p
, "inf", 3) == 0)
3478 *mantissaP
= 1ull << 63;
3480 input_line_pointer
= p
+ 3;
3483 for (; ISDIGIT(*p
); ++p
)
3491 mantissa
= mantissa
* 10 + (*p
- '0');
3493 /* skip non-significant digits */
3494 for (; ISDIGIT(*p
); ++p
)
3500 if (!exponent
) /* if no precission overflow */
3502 for (; ISDIGIT(*p
); ++p
, --exponent
)
3510 mantissa
= mantissa
* 10 + (*p
- '0');
3513 for (; ISDIGIT(*p
); ++p
)
3516 if (*p
== 'e' || *p
== 'E')
3522 if (es
|| *p
== '+')
3524 for (; ISDIGIT(*p
); ++p
)
3527 t
= t
* 10 + (*p
- '0');
3529 exponent
+= (es
) ? -t
: t
;
3531 if (ISALNUM(*p
) || *p
== '.')
3533 input_line_pointer
= p
;
3536 *mantissaP
= 1ull << 63;
3538 return 1; /* result is 0 */
3541 for (; mantissa
<= ~0ull/10; --exponent
)
3544 now we have sign, mantissa, and signed decimal exponent
3545 need to recompute to binary exponent
3547 for (i
= 64; exponent
> 0; --exponent
)
3549 /* be sure that no integer overflow */
3550 while (mantissa
> ~0ull/10)
3557 for (; exponent
< 0; ++exponent
)
3559 while (!(mantissa
>> 63))
3567 for (; !(mantissa
>> 63); --i
)
3569 *mantissaP
= mantissa
;
3575 str_to_zeda32(char *litP
, int *sizeP
)
3577 bfd_uint64_t mantissa
;
3583 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3584 return _("invalid syntax");
3585 /* I do not know why decrement is needed */
3587 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
3591 /* make 24 bit mantissa */
3593 /* check for overflow */
3600 if (exponent
< -127)
3605 else if (exponent
> 127)
3608 mantissa
= sign
? 0xc00000 : 0x400000;
3610 else if (mantissa
== 0)
3613 mantissa
= 0x200000;
3616 mantissa
&= (1ull << 23) - 1;
3617 for (i
= 0; i
< 24; i
+= 8)
3618 *litP
++ = (char)(mantissa
>> i
);
3619 *litP
= (char)(0x80 + exponent
);
3624 Math48 by Anders Hejlsberg support.
3625 Mantissa is 39 bits wide, exponent 8 bit wide.
3628 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
3629 bit 7-0: exponent+128 (0 - value is null)
3630 MIN: 2.938735877e-39
3631 MAX: 1.701411835e+38
3634 str_to_float48(char *litP
, int *sizeP
)
3636 bfd_uint64_t mantissa
;
3642 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3643 return _("invalid syntax");
3644 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
3648 /* make 40 bit mantissa */
3650 /* check for overflow */
3656 if (exponent
< -127)
3658 memset (litP
, 0, 6);
3662 return _("overflow");
3664 mantissa
&= (1ull << 39) - 1;
3665 *litP
++ = (char)(0x80 + exponent
);
3666 for (i
= 0; i
< 40; i
+= 8)
3667 *litP
++ = (char)(mantissa
>> i
);