1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 /* Exported constants. */
30 const char comment_chars
[] = ";\0";
31 const char line_comment_chars
[] = "#;\0";
32 const char line_separator_chars
[] = "\0";
33 const char EXP_CHARS
[] = "eE\0";
34 const char FLT_CHARS
[] = "RrDdFfSsHh\0";
36 /* For machine specific options. */
37 const char * md_shortopts
= ""; /* None yet. */
41 OPTION_MARCH
= OPTION_MD_BASE
,
55 OPTION_FP_SINGLE_FORMAT
,
56 OPTION_FP_DOUBLE_FORMAT
,
57 OPTION_COMPAT_LL_PREFIX
,
58 OPTION_COMPAT_COLONLESS
,
62 #define INS_Z80 (1 << 0)
63 #define INS_R800 (1 << 1)
64 #define INS_GBZ80 (1 << 2)
65 #define INS_Z180 (1 << 3)
66 #define INS_EZ80 (1 << 4)
67 #define INS_Z80N (1 << 5)
68 #define INS_MARCH_MASK 0xffff
70 #define INS_IDX_HALF (1 << 16)
71 #define INS_IN_F_C (1 << 17)
72 #define INS_OUT_C_0 (1 << 18)
73 #define INS_SLI (1 << 19)
74 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
75 #define INS_TUNE_MASK 0xffff0000
77 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
80 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
81 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
83 struct option md_longopts
[] =
85 { "march", required_argument
, NULL
, OPTION_MARCH
},
86 { "z80", no_argument
, NULL
, OPTION_MACH_Z80
},
87 { "r800", no_argument
, NULL
, OPTION_MACH_R800
},
88 { "z180", no_argument
, NULL
, OPTION_MACH_Z180
},
89 { "ez80", no_argument
, NULL
, OPTION_MACH_EZ80_Z80
},
90 { "ez80-adl", no_argument
, NULL
, OPTION_MACH_EZ80_ADL
},
91 { "fp-s", required_argument
, NULL
, OPTION_FP_SINGLE_FORMAT
},
92 { "fp-d", required_argument
, NULL
, OPTION_FP_DOUBLE_FORMAT
},
93 { "strict", no_argument
, NULL
, OPTION_MACH_FUD
},
94 { "full", no_argument
, NULL
, OPTION_MACH_IUP
},
95 { "with-inst", required_argument
, NULL
, OPTION_MACH_INST
},
96 { "Wnins", required_argument
, NULL
, OPTION_MACH_INST
},
97 { "without-inst", required_argument
, NULL
, OPTION_MACH_NO_INST
},
98 { "local-prefix", required_argument
, NULL
, OPTION_COMPAT_LL_PREFIX
},
99 { "colonless", no_argument
, NULL
, OPTION_COMPAT_COLONLESS
},
100 { "sdcc", no_argument
, NULL
, OPTION_COMPAT_SDCC
},
101 { "Fins", required_argument
, NULL
, OPTION_MACH_NO_INST
},
102 { "ignore-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_IUD
},
103 { "Wnud", no_argument
, NULL
, OPTION_MACH_IUD
},
104 { "warn-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_WUD
},
105 { "Wud", no_argument
, NULL
, OPTION_MACH_WUD
},
106 { "forbid-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_FUD
},
107 { "Fud", no_argument
, NULL
, OPTION_MACH_FUD
},
108 { "ignore-unportable-instructions", no_argument
, NULL
, OPTION_MACH_IUP
},
109 { "Wnup", no_argument
, NULL
, OPTION_MACH_IUP
},
110 { "warn-unportable-instructions", no_argument
, NULL
, OPTION_MACH_WUP
},
111 { "Wup", no_argument
, NULL
, OPTION_MACH_WUP
},
112 { "forbid-unportable-instructions", no_argument
, NULL
, OPTION_MACH_FUP
},
113 { "Fup", no_argument
, NULL
, OPTION_MACH_FUP
},
115 { NULL
, no_argument
, NULL
, 0 }
118 size_t md_longopts_size
= sizeof (md_longopts
);
120 extern int coff_flags
;
121 /* Instruction classes that silently assembled. */
122 static int ins_ok
= INS_Z80
| INS_UNDOC
;
123 /* Instruction classes that generate errors. */
124 static int ins_err
= ~(INS_Z80
| INS_UNDOC
);
125 /* eZ80 CPU mode (ADL or Z80) */
126 static int cpu_mode
= 0; /* 0 - Z80, 1 - ADL */
127 /* accept SDCC specific instruction encoding */
128 static int sdcc_compat
= 0;
129 /* accept colonless labels */
130 static int colonless_labels
= 0;
131 /* local label prefix (NULL - default) */
132 static const char *local_label_prefix
= NULL
;
133 /* floating point support */
134 typedef const char *(*str_to_float_t
)(char *litP
, int *sizeP
);
135 static str_to_float_t str_to_float
;
136 static str_to_float_t str_to_double
;
138 /* mode of current instruction */
139 #define INST_MODE_S 0 /* short data mode */
140 #define INST_MODE_IS 0 /* short instruction mode */
141 #define INST_MODE_L 2 /* long data mode */
142 #define INST_MODE_IL 1 /* long instruction mode */
143 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
144 static char inst_mode
;
155 static const struct match_info
158 {"z80", INS_Z80
, 0, 0, "Zilog Z80 (+infc+xyhl)" },
159 {"ez80", INS_EZ80
, 0, 0, "Zilog eZ80" },
160 {"gbz80", INS_GBZ80
, INS_UNDOC
|INS_UNPORT
, 0, "GameBoy Z80" },
161 {"r800", INS_R800
, INS_UNPORT
, 0, "Ascii R800" },
162 {"z180", INS_Z180
, INS_UNDOC
|INS_UNPORT
, 0, "Zilog Z180" },
163 {"z80n", INS_Z80N
, 0, 0, "Z80 Next" }
166 static const struct match_info
169 {"full", INS_UNDOC
|INS_UNPORT
, 0, 0, "assemble all known instructions" },
170 {"adl", 0, 0, 1, "eZ80 ADL mode by default" },
171 {"xyhl", INS_IDX_HALF
, 0, 0, "instructions with halves of index registers" },
172 {"infc", INS_IN_F_C
, 0, 0, "instruction IN F,(C)" },
173 {"outc0", INS_OUT_C_0
, 0, 0, "instruction OUT (C),0" },
174 {"sli", INS_SLI
, 0, 0, "instruction known as SLI, SLL, or SL1" },
175 {"xdcb", INS_ROT_II_LD
, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" }
179 setup_march (const char *name
, int *ok
, int *err
, int *mode
)
182 size_t len
= strcspn (name
, "+-");
183 for (i
= 0; i
< ARRAY_SIZE (match_cpu_table
); ++i
)
184 if (!strncasecmp (name
, match_cpu_table
[i
].name
, len
)
185 && strlen (match_cpu_table
[i
].name
) == len
)
187 *ok
= match_cpu_table
[i
].ins_ok
;
188 *err
= match_cpu_table
[i
].ins_err
;
189 *mode
= match_cpu_table
[i
].cpu_mode
;
193 if (i
>= ARRAY_SIZE (match_cpu_table
))
194 as_fatal (_("Invalid CPU is specified: %s"), name
);
198 name
= &name
[len
+ 1];
199 len
= strcspn (name
, "+-");
200 for (i
= 0; i
< ARRAY_SIZE (match_ext_table
); ++i
)
201 if (!strncasecmp (name
, match_ext_table
[i
].name
, len
)
202 && strlen (match_ext_table
[i
].name
) == len
)
206 *ok
|= match_ext_table
[i
].ins_ok
;
207 *err
&= ~match_ext_table
[i
].ins_ok
;
208 *mode
|= match_ext_table
[i
].cpu_mode
;
212 *ok
&= ~match_ext_table
[i
].ins_ok
;
213 *err
|= match_ext_table
[i
].ins_ok
;
214 *mode
&= ~match_ext_table
[i
].cpu_mode
;
218 if (i
>= ARRAY_SIZE (match_ext_table
))
219 as_fatal (_("Invalid EXTENTION is specified: %s"), name
);
224 setup_instruction (const char *inst
, int *add
, int *sub
)
227 if (!strcmp (inst
, "idx-reg-halves"))
229 else if (!strcmp (inst
, "sli"))
231 else if (!strcmp (inst
, "op-ii-ld"))
233 else if (!strcmp (inst
, "in-f-c"))
235 else if (!strcmp (inst
, "out-c-0"))
245 str_to_zeda32 (char *litP
, int *sizeP
);
247 str_to_float48 (char *litP
, int *sizeP
);
249 str_to_ieee754_h (char *litP
, int *sizeP
);
251 str_to_ieee754_s (char *litP
, int *sizeP
);
253 str_to_ieee754_d (char *litP
, int *sizeP
);
255 static str_to_float_t
256 get_str_to_float (const char *arg
)
258 if (strcasecmp (arg
, "zeda32") == 0)
259 return str_to_zeda32
;
261 if (strcasecmp (arg
, "math48") == 0)
262 return str_to_float48
;
264 if (strcasecmp (arg
, "half") != 0)
265 return str_to_ieee754_h
;
267 if (strcasecmp (arg
, "single") != 0)
268 return str_to_ieee754_s
;
270 if (strcasecmp (arg
, "double") != 0)
271 return str_to_ieee754_d
;
273 if (strcasecmp (arg
, "ieee754") == 0)
274 as_fatal (_("invalid floating point numbers type `%s'"), arg
);
279 setup_instruction_list (const char *list
, int *add
, int *sub
)
286 for (b
= list
; *b
!= '\0';)
293 if (sz
== 0 || sz
>= (int)sizeof (buf
))
295 as_bad (_("invalid INST in command line: %s"), b
);
300 if (setup_instruction (buf
, add
, sub
))
304 as_bad (_("invalid INST in command line: %s"), buf
);
315 md_parse_option (int c
, const char* arg
)
322 setup_march (arg
, & ins_ok
, & ins_err
, & cpu_mode
);
324 case OPTION_MACH_Z80
:
325 setup_march ("z80", & ins_ok
, & ins_err
, & cpu_mode
);
327 case OPTION_MACH_R800
:
328 setup_march ("r800", & ins_ok
, & ins_err
, & cpu_mode
);
330 case OPTION_MACH_Z180
:
331 setup_march ("z180", & ins_ok
, & ins_err
, & cpu_mode
);
333 case OPTION_MACH_EZ80_Z80
:
334 setup_march ("ez80", & ins_ok
, & ins_err
, & cpu_mode
);
336 case OPTION_MACH_EZ80_ADL
:
337 setup_march ("ez80+adl", & ins_ok
, & ins_err
, & cpu_mode
);
339 case OPTION_FP_SINGLE_FORMAT
:
340 str_to_float
= get_str_to_float (arg
);
342 case OPTION_FP_DOUBLE_FORMAT
:
343 str_to_double
= get_str_to_float (arg
);
345 case OPTION_MACH_INST
:
346 if ((ins_ok
& INS_GBZ80
) == 0)
347 return setup_instruction_list (arg
, & ins_ok
, & ins_err
);
349 case OPTION_MACH_NO_INST
:
350 if ((ins_ok
& INS_GBZ80
) == 0)
351 return setup_instruction_list (arg
, & ins_err
, & ins_ok
);
353 case OPTION_MACH_WUD
:
354 case OPTION_MACH_IUD
:
355 if ((ins_ok
& INS_GBZ80
) == 0)
358 ins_err
&= ~INS_UNDOC
;
361 case OPTION_MACH_WUP
:
362 case OPTION_MACH_IUP
:
363 if ((ins_ok
& INS_GBZ80
) == 0)
365 ins_ok
|= INS_UNDOC
| INS_UNPORT
;
366 ins_err
&= ~(INS_UNDOC
| INS_UNPORT
);
369 case OPTION_MACH_FUD
:
370 if ((ins_ok
& (INS_R800
| INS_GBZ80
)) == 0)
372 ins_ok
&= (INS_UNDOC
| INS_UNPORT
);
373 ins_err
|= INS_UNDOC
| INS_UNPORT
;
376 case OPTION_MACH_FUP
:
377 ins_ok
&= ~INS_UNPORT
;
378 ins_err
|= INS_UNPORT
;
380 case OPTION_COMPAT_LL_PREFIX
:
381 local_label_prefix
= (arg
&& *arg
) ? arg
: NULL
;
383 case OPTION_COMPAT_SDCC
:
386 case OPTION_COMPAT_COLONLESS
:
387 colonless_labels
= 1;
395 md_show_usage (FILE * f
)
399 CPU model options:\n\
400 -march=CPU[+EXT...][-EXT...]\n\
401 \t\t\t generate code for CPU, where CPU is one of:\n"));
402 for (i
= 0; i
< ARRAY_SIZE(match_cpu_table
); ++i
)
403 fprintf (f
, " %-8s\t\t %s\n", match_cpu_table
[i
].name
, match_cpu_table
[i
].comment
);
404 fprintf (f
, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n"));
405 for (i
= 0; i
< ARRAY_SIZE(match_ext_table
); ++i
)
406 fprintf (f
, " %-8s\t\t %s\n", match_ext_table
[i
].name
, match_ext_table
[i
].comment
);
408 Compatibility options:\n\
409 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
410 -colonless\t\t permit colonless labels\n\
411 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
412 -fp-s=FORMAT\t\t set single precission FP numbers format\n\
413 -fp-d=FORMAT\t\t set double precission FP numbers format\n\
414 Where FORMAT one of:\n\
415 ieee754\t\t IEEE754 compatible (depends on directive)\n\
416 half\t\t\t IEEE754 half precision (16 bit)\n\
417 single\t\t IEEE754 single precision (32 bit)\n\
418 double\t\t IEEE754 double precision (64 bit)\n\
419 zeda32\t\t Zeda z80float library 32 bit format\n\
420 math48\t\t 48 bit format from Math48 library\n\
422 Default: -march=z80+xyhl+infc\n"));
425 static symbolS
* zero
;
432 #define R_STACKABLE (0x80)
433 #define R_ARITH (0x40)
436 #define R_INDEX (R_IX | R_IY)
445 #define REG_F (6 | 8)
450 #define REG_AF (3 | R_STACKABLE)
451 #define REG_BC (0 | R_STACKABLE | R_ARITH)
452 #define REG_DE (1 | R_STACKABLE | R_ARITH)
453 #define REG_HL (2 | R_STACKABLE | R_ARITH)
454 #define REG_IX (REG_HL | R_IX)
455 #define REG_IY (REG_HL | R_IY)
456 #define REG_SP (3 | R_ARITH)
458 static const struct reg_entry regtable
[] =
473 {"ixh",REG_H
| R_IX
},
474 {"ixl",REG_L
| R_IX
},
476 {"iyh",REG_H
| R_IY
},
477 {"iyl",REG_L
| R_IY
},
484 #define BUFLEN 8 /* Large enough for any keyword. */
489 expressionS nul
, reg
;
491 unsigned int i
, j
, k
;
494 if (ins_ok
& INS_EZ80
) /* if select EZ80 cpu then */
495 listing_lhs_width
= 6; /* use 6 bytes per line in the listing */
497 reg
.X_op
= O_register
;
499 reg
.X_add_symbol
= reg
.X_op_symbol
= 0;
500 for ( i
= 0 ; i
< ARRAY_SIZE ( regtable
) ; ++i
)
502 reg
.X_add_number
= regtable
[i
].number
;
503 k
= strlen ( regtable
[i
].name
);
507 for ( j
= ( 1<<k
) ; j
; --j
)
509 for ( k
= 0 ; regtable
[i
].name
[k
] ; ++k
)
511 buf
[k
] = ( j
& ( 1<<k
) ) ? TOUPPER (regtable
[i
].name
[k
]) : regtable
[i
].name
[k
];
513 symbolS
* psym
= symbol_find_or_make (buf
);
514 S_SET_SEGMENT (psym
, reg_section
);
515 symbol_set_value_expression (psym
, ®
);
519 p
= input_line_pointer
;
520 input_line_pointer
= (char *) "0";
523 input_line_pointer
= p
;
524 zero
= make_expr_symbol (& nul
);
525 /* We do not use relaxation (yet). */
534 switch (ins_ok
& INS_MARCH_MASK
)
537 mach_type
= bfd_mach_z80
;
540 mach_type
= bfd_mach_r800
;
543 mach_type
= bfd_mach_z180
;
546 mach_type
= bfd_mach_gbz80
;
549 mach_type
= cpu_mode
? bfd_mach_ez80_adl
: bfd_mach_ez80_z80
;
552 mach_type
= bfd_mach_z80n
;
557 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_type
);
560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
562 z80_elf_final_processing (void)
563 {/* nothing to do, all is done by BFD itself */
566 elf_elfheader (stdoutput)->e_flags = elf_flags;
572 skip_space (const char *s
)
574 while (*s
== ' ' || *s
== '\t')
579 /* A non-zero return-value causes a continue in the
580 function read_a_source_file () in ../read.c. */
582 z80_start_line_hook (void)
587 /* Convert one character constants. */
588 for (p
= input_line_pointer
; *p
&& *p
!= '\n'; ++p
)
593 if (p
[1] != 0 && p
[1] != '\'' && p
[2] == '\'')
595 snprintf (buf
, 4, "%3d", (unsigned char)p
[1]);
603 for (quote
= *p
++; quote
!= *p
&& '\n' != *p
; ++p
)
607 as_bad (_("-- unterminated string"));
608 ignore_rest_of_line ();
614 *p
= (*skip_space (p
+ 1) == '(') ? '+' : ' ';
618 /* Check for <label>[:] [.](EQU|DEFL) <value>. */
619 if (is_name_beginner (*input_line_pointer
))
622 char c
, *rest
, *line_start
;
625 line_start
= input_line_pointer
;
629 c
= get_symbol_name (&name
);
630 rest
= input_line_pointer
+ 1;
632 if (ISSPACE (c
) && colonless_labels
)
636 bump_line_counters ();
643 /* remove second colon if SDCC compatibility enabled */
648 rest
= (char*)skip_space (rest
);
651 if (strncasecmp (rest
, "EQU", 3) == 0)
653 else if (strncasecmp (rest
, "DEFL", 4) == 0)
657 if (len
&& (!ISALPHA (rest
[len
])))
659 /* Handle assignment here. */
660 if (line_start
[-1] == '\n')
662 bump_line_counters ();
665 input_line_pointer
= rest
+ len
- 1;
666 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
667 equals (name
, len
== 4);
672 /* Restore line and pointer. */
673 (void) restore_line_pointer (c
);
674 input_line_pointer
= line_start
;
681 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
687 md_atof (int type
, char *litP
, int *sizeP
)
696 return str_to_float (litP
, sizeP
);
703 return str_to_double (litP
, sizeP
);
706 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
710 md_section_align (segT seg ATTRIBUTE_UNUSED
, valueT size
)
716 md_pcrel_from (fixS
* fixp
)
718 return fixp
->fx_where
+ fixp
->fx_frag
->fr_address
;
721 typedef const char * (asfunc
)(char, char, const char*);
723 typedef struct _table_t
726 unsigned char prefix
;
727 unsigned char opcode
;
729 unsigned inss
; /*0 - all CPU types or list of supported INS_* */
732 /* Compares the key for structs that start with a char * to the key. */
734 key_cmp (const void * a
, const void * b
)
736 const char *str_a
, *str_b
;
738 str_a
= *((const char**)a
);
739 str_b
= *((const char**)b
);
740 return strcmp (str_a
, str_b
);
744 const char *key
= buf
;
746 /* Prevent an error on a line from also generating
747 a "junk at end of line" error message. */
748 static char err_flag
;
751 error (const char * message
)
756 as_bad ("%s", message
);
763 error (_("illegal operand"));
767 wrong_mach (int ins_type
)
769 if (ins_type
& ins_err
)
772 as_warn (_("undocumented instruction"));
776 check_mach (int ins_type
)
778 if ((ins_type
& ins_ok
) == 0)
779 wrong_mach (ins_type
);
782 /* Check whether an expression is indirect. */
784 is_indir (const char *s
)
790 /* Indirection is indicated with parentheses. */
793 for (p
= s
, depth
= 0; *p
&& *p
!= ','; ++p
)
799 for (quote
= *p
++; quote
!= *p
&& *p
!= '\n'; ++p
)
800 if (*p
== '\\' && p
[1])
810 p
= skip_space (p
+ 1);
816 error (_("mismatched parentheses"));
822 error (_("mismatched parentheses"));
827 /* Check whether a symbol involves a register. */
829 contains_register (symbolS
*sym
)
833 expressionS
* ex
= symbol_get_value_expression(sym
);
835 return (O_register
== ex
->X_op
)
836 || (ex
->X_add_symbol
&& contains_register(ex
->X_add_symbol
))
837 || (ex
->X_op_symbol
&& contains_register(ex
->X_op_symbol
));
843 /* Parse general expression, not looking for indexed addressing. */
845 parse_exp_not_indexed (const char *s
, expressionS
*op
)
852 if (sdcc_compat
&& (*p
== '<' || *p
== '>'))
856 case '<': /* LSB request */
859 case '>': /* MSB request */
860 make_shift
= cpu_mode
? 16 : 8;
867 op
->X_md
= indir
= is_indir (p
);
868 if (indir
&& (ins_ok
& INS_GBZ80
))
869 { /* check for instructions like ld a,(hl+), ld (hl-),a */
870 p
= skip_space (p
+1);
871 if (!strncasecmp (p
, "hl", 2))
874 if (*skip_space(p
+1) == ')' && (*p
== '+' || *p
== '-'))
877 op
->X_add_symbol
= NULL
;
878 op
->X_add_number
= (*p
== '+') ? REG_HL
: -REG_HL
;
879 input_line_pointer
= (char*)skip_space(p
+ 1) + 1;
880 return input_line_pointer
;
884 input_line_pointer
= (char*) s
;
889 error (_("missing operand"));
892 error (_("bad expression syntax"));
900 /* replace [op] by [op >> shift] */
902 op
->X_add_symbol
= make_expr_symbol (op
);
903 op
->X_add_number
= 0;
904 op
->X_op
= O_right_shift
;
905 memset (&data
, 0, sizeof (data
));
906 data
.X_op
= O_constant
;
907 data
.X_add_number
= make_shift
;
908 op
->X_op_symbol
= make_expr_symbol (&data
);
910 return input_line_pointer
;
914 unify_indexed (expressionS
*op
)
916 if (O_register
!= symbol_get_value_expression (op
->X_add_symbol
)->X_op
)
919 int rnum
= symbol_get_value_expression (op
->X_add_symbol
)->X_add_number
;
920 if ( ((REG_IX
!= rnum
) && (REG_IY
!= rnum
)) || contains_register (op
->X_op_symbol
))
926 /* Convert subtraction to addition of negative value. */
927 if (O_subtract
== op
->X_op
)
930 minus
.X_op
= O_uminus
;
931 minus
.X_add_number
= 0;
932 minus
.X_add_symbol
= op
->X_op_symbol
;
933 minus
.X_op_symbol
= 0;
934 op
->X_op_symbol
= make_expr_symbol (&minus
);
938 /* Clear X_add_number of the expression. */
939 if (op
->X_add_number
!= 0)
942 memset (&add
, 0, sizeof (add
));
944 add
.X_add_number
= op
->X_add_number
;
945 add
.X_add_symbol
= op
->X_op_symbol
;
947 op
->X_add_symbol
= make_expr_symbol (&add
);
950 op
->X_add_symbol
= op
->X_op_symbol
;
952 op
->X_add_number
= rnum
;
957 /* Parse expression, change operator to O_md1 for indexed addressing. */
959 parse_exp (const char *s
, expressionS
*op
)
961 const char* res
= parse_exp_not_indexed (s
, op
);
966 if (unify_indexed (op
) && op
->X_md
)
970 if (op
->X_md
&& ((REG_IX
== op
->X_add_number
) || (REG_IY
== op
->X_add_number
)))
972 op
->X_add_symbol
= zero
;
977 /* parse SDCC syntax where index register offset placed before parentheses */
978 if (sdcc_compat
&& is_indir (res
))
982 res
= parse_exp (res
, op
);
983 if (op
->X_op
!= O_md1
|| op
->X_add_symbol
!= zero
)
986 op
->X_add_symbol
= make_expr_symbol (&off
);
995 /* Condition codes, including some synonyms provided by HiTech zas. */
996 static const struct reg_entry cc_tab
[] =
1014 /* Parse condition code. */
1016 parse_cc (const char *s
, char * op
)
1020 struct reg_entry
* cc_p
;
1022 for (i
= 0; i
< BUFLEN
; ++i
)
1024 if (!ISALPHA (s
[i
])) /* Condition codes consist of letters only. */
1026 buf
[i
] = TOLOWER (s
[i
]);
1030 && ((s
[i
] == 0) || (s
[i
] == ',')))
1033 cc_p
= bsearch (&key
, cc_tab
, ARRAY_SIZE (cc_tab
),
1034 sizeof (cc_tab
[0]), key_cmp
);
1051 emit_insn (char prefix
, char opcode
, const char * args
)
1066 void z80_cons_fix_new (fragS
*frag_p
, int offset
, int nbytes
, expressionS
*exp
)
1068 bfd_reloc_code_real_type r
[4] =
1076 if (nbytes
< 1 || nbytes
> 4)
1078 as_bad (_("unsupported BFD relocation size %u"), nbytes
);
1082 fix_new_exp (frag_p
, offset
, nbytes
, exp
, 0, r
[nbytes
-1]);
1087 emit_data_val (expressionS
* val
, int size
)
1090 bfd_reloc_code_real_type r_type
;
1092 p
= frag_more (size
);
1093 if (val
->X_op
== O_constant
)
1096 for (i
= 0; i
< size
; ++i
)
1097 p
[i
] = (char)(val
->X_add_number
>> (i
*8));
1103 case 1: r_type
= BFD_RELOC_8
; break;
1104 case 2: r_type
= BFD_RELOC_16
; break;
1105 case 3: r_type
= BFD_RELOC_24
; break;
1106 case 4: r_type
= BFD_RELOC_32
; break;
1107 case 8: r_type
= BFD_RELOC_64
; break;
1109 as_fatal (_("invalid data size %d"), size
);
1112 if ( (val
->X_op
== O_register
)
1113 || (val
->X_op
== O_md1
)
1114 || contains_register (val
->X_add_symbol
)
1115 || contains_register (val
->X_op_symbol
))
1118 if (size
<= 2 && val
->X_op_symbol
)
1120 bfd_boolean simplify
= TRUE
;
1121 int shift
= symbol_get_value_expression (val
->X_op_symbol
)->X_add_number
;
1122 if (val
->X_op
== O_bit_and
&& shift
== (1 << (size
*8))-1)
1124 else if (val
->X_op
!= O_right_shift
)
1131 case 0: r_type
= BFD_RELOC_Z80_BYTE0
; break;
1132 case 8: r_type
= BFD_RELOC_Z80_BYTE1
; break;
1133 case 16: r_type
= BFD_RELOC_Z80_BYTE2
; break;
1134 case 24: r_type
= BFD_RELOC_Z80_BYTE3
; break;
1135 default: simplify
= FALSE
;
1138 else /* if (size == 2) */
1142 case 0: r_type
= BFD_RELOC_Z80_WORD0
; break;
1143 case 16: r_type
= BFD_RELOC_Z80_WORD1
; break;
1144 default: simplify
= FALSE
;
1150 val
->X_op
= O_symbol
;
1151 val
->X_op_symbol
= NULL
;
1152 val
->X_add_number
= 0;
1156 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
, val
, FALSE
, r_type
);
1160 emit_byte (expressionS
* val
, bfd_reloc_code_real_type r_type
)
1164 if (r_type
== BFD_RELOC_8
)
1166 emit_data_val (val
, 1);
1170 *p
= val
->X_add_number
;
1171 if ( contains_register (val
->X_add_symbol
) || contains_register (val
->X_op_symbol
) )
1175 else if ((r_type
== BFD_RELOC_8_PCREL
) && (val
->X_op
== O_constant
))
1177 as_bad (_("cannot make a relative jump to an absolute location"));
1179 else if (val
->X_op
== O_constant
)
1181 if ((val
->X_add_number
< -128) || (val
->X_add_number
>= 128))
1183 if (r_type
== BFD_RELOC_Z80_DISP8
)
1184 as_bad (_("index overflow (%+ld)"), val
->X_add_number
);
1186 as_bad (_("offset overflow (%+ld)"), val
->X_add_number
);
1191 /* For symbols only, constants are stored at begin of function */
1192 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 1, val
,
1193 (r_type
== BFD_RELOC_8_PCREL
) ? TRUE
: FALSE
, r_type
);
1198 emit_word (expressionS
* val
)
1200 emit_data_val (val
, (inst_mode
& INST_MODE_IL
) ? 3 : 2);
1204 emit_mx (char prefix
, char opcode
, int shift
, expressionS
* arg
)
1205 /* The operand m may be r, (hl), (ix+d), (iy+d),
1206 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1211 rnum
= arg
->X_add_number
;
1227 if ((prefix
== 0) && (rnum
& R_INDEX
))
1229 prefix
= (rnum
& R_IX
) ? 0xDD : 0xFD;
1230 if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
1231 check_mach (INS_IDX_HALF
);
1240 q
= frag_more (prefix
? 2 : 1);
1243 * q
++ = opcode
+ (rnum
<< shift
);
1246 if (ins_ok
& INS_GBZ80
)
1252 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1253 *q
= (prefix
) ? prefix
: (opcode
+ (6 << shift
));
1255 expressionS offset
= *arg
;
1256 offset
.X_op
= O_symbol
;
1257 offset
.X_add_number
= 0;
1258 emit_byte (&offset
, BFD_RELOC_Z80_DISP8
);
1263 *q
= opcode
+(6<<shift
);
1271 /* The operand m may be r, (hl), (ix+d), (iy+d),
1272 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1274 emit_m (char prefix
, char opcode
, const char *args
)
1279 p
= parse_exp (args
, &arg_m
);
1284 emit_mx (prefix
, opcode
, 0, &arg_m
);
1292 /* The operand m may be as above or one of the undocumented
1293 combinations (ix+d),r and (iy+d),r (if unportable instructions
1297 emit_mr (char prefix
, char opcode
, const char *args
)
1299 expressionS arg_m
, arg_r
;
1302 p
= parse_exp (args
, & arg_m
);
1309 p
= parse_exp (p
+ 1, & arg_r
);
1311 if ((arg_r
.X_md
== 0)
1312 && (arg_r
.X_op
== O_register
)
1313 && (arg_r
.X_add_number
< 8))
1314 opcode
+= arg_r
.X_add_number
- 6; /* Emit_mx () will add 6. */
1320 if (!(ins_ok
& INS_Z80N
))
1321 check_mach (INS_ROT_II_LD
);
1325 emit_mx (prefix
, opcode
, 0, & arg_m
);
1334 emit_sx (char prefix
, char opcode
, expressionS
* arg_p
)
1338 switch (arg_p
->X_op
)
1342 emit_mx (prefix
, opcode
, 0, arg_p
);
1349 q
= frag_more (prefix
? 2 : 1);
1353 emit_byte (arg_p
, BFD_RELOC_8
);
1358 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1360 emit_s (char prefix
, char opcode
, const char *args
)
1365 p
= parse_exp (args
, & arg_s
);
1366 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
1367 { /* possible instruction in generic format op A,x */
1368 if (!(ins_ok
& INS_EZ80
) && !sdcc_compat
)
1371 p
= parse_exp (p
, & arg_s
);
1373 emit_sx (prefix
, opcode
, & arg_s
);
1378 emit_sub (char prefix
, char opcode
, const char *args
)
1383 if (!(ins_ok
& INS_GBZ80
))
1384 return emit_s (prefix
, opcode
, args
);
1385 p
= parse_exp (args
, & arg_s
);
1388 error (_("bad instruction syntax"));
1392 if (arg_s
.X_md
!= 0 || arg_s
.X_op
!= O_register
|| arg_s
.X_add_number
!= REG_A
)
1395 p
= parse_exp (p
, & arg_s
);
1397 emit_sx (prefix
, opcode
, & arg_s
);
1402 emit_swap (char prefix
, char opcode
, const char *args
)
1408 if (!(ins_ok
& INS_Z80N
))
1409 return emit_mr (prefix
, opcode
, args
);
1411 /* check for alias swap a for swapnib of Z80N */
1412 p
= parse_exp (args
, ®
);
1413 if (reg
.X_md
!= 0 || reg
.X_op
!= O_register
|| reg
.X_add_number
!= REG_A
)
1423 emit_call (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1426 const char *p
; char *q
;
1428 p
= parse_exp_not_indexed (args
, &addr
);
1440 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1442 emit_incdec (char prefix
, char opcode
, const char * args
)
1444 expressionS operand
;
1446 const char *p
; char *q
;
1448 p
= parse_exp (args
, &operand
);
1449 rnum
= operand
.X_add_number
;
1450 if ((! operand
.X_md
)
1451 && (operand
.X_op
== O_register
)
1454 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1456 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1457 *q
= prefix
+ ((rnum
& 3) << 4);
1461 if ((operand
.X_op
== O_md1
) || (operand
.X_op
== O_register
))
1462 emit_mx (0, opcode
, 3, & operand
);
1470 emit_jr (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1476 p
= parse_exp_not_indexed (args
, &addr
);
1483 addr
.X_add_number
--; /* pcrel computes after offset code */
1484 emit_byte (&addr
, BFD_RELOC_8_PCREL
);
1490 emit_jp (char prefix
, char opcode
, const char * args
)
1497 p
= parse_exp_not_indexed (args
, & addr
);
1500 rnum
= addr
.X_add_number
;
1501 if ((O_register
== addr
.X_op
) && (REG_HL
== (rnum
& ~R_INDEX
)))
1503 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1505 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1508 else if (addr
.X_op
== O_register
&& rnum
== REG_C
&& (ins_ok
& INS_Z80N
))
1527 emit_im (char prefix
, char opcode
, const char * args
)
1533 p
= parse_exp (args
, & mode
);
1534 if (mode
.X_md
|| (mode
.X_op
!= O_constant
))
1537 switch (mode
.X_add_number
)
1541 ++mode
.X_add_number
;
1546 *q
= opcode
+ 8*mode
.X_add_number
;
1555 emit_pop (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1561 p
= parse_exp (args
, & regp
);
1563 && (regp
.X_op
== O_register
)
1564 && (regp
.X_add_number
& R_STACKABLE
))
1568 rnum
= regp
.X_add_number
;
1572 *q
++ = (rnum
&R_IX
)?0xDD:0xFD;
1576 *q
= opcode
+ ((rnum
& 3) << 4);
1585 emit_push (char prefix
, char opcode
, const char * args
)
1591 p
= parse_exp (args
, & arg
);
1592 if (arg
.X_op
== O_register
)
1593 return emit_pop (prefix
, opcode
, args
);
1595 if (arg
.X_md
|| arg
.X_op
== O_md1
|| !(ins_ok
& INS_Z80N
))
1603 fix_new_exp (frag_now
, q
- frag_now
->fr_literal
, 2, &arg
, FALSE
,
1604 BFD_RELOC_Z80_16_BE
);
1610 emit_retcc (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1615 p
= parse_cc (args
, &cc
);
1621 return p
? p
: args
;
1625 emit_adc (char prefix
, char opcode
, const char * args
)
1632 p
= parse_exp (args
, &term
);
1635 error (_("bad instruction syntax"));
1639 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1642 switch (term
.X_add_number
)
1645 p
= emit_s (0, prefix
, p
);
1648 p
= parse_exp (p
, &term
);
1649 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1651 rnum
= term
.X_add_number
;
1652 if (R_ARITH
== (rnum
& (R_ARITH
| R_INDEX
)))
1656 *q
= opcode
+ ((rnum
& 3) << 4);
1668 emit_add (char prefix
, char opcode
, const char * args
)
1675 p
= parse_exp (args
, &term
);
1678 error (_("bad instruction syntax"));
1682 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1685 switch (term
.X_add_number
)
1688 p
= emit_s (0, prefix
, p
);
1691 p
= parse_exp (p
, &term
);
1692 if (!(ins_ok
& INS_GBZ80
) || term
.X_md
|| term
.X_op
== O_register
)
1696 emit_byte (&term
, BFD_RELOC_Z80_DISP8
);
1700 if (!(ins_ok
& INS_Z80N
))
1709 lhs
= term
.X_add_number
;
1710 p
= parse_exp (p
, &term
);
1711 rhs
= term
.X_add_number
;
1712 if (term
.X_md
!= 0 || term
.X_op
== O_md1
)
1714 else if ((term
.X_op
== O_register
) && (rhs
& R_ARITH
) && (rhs
== lhs
|| (rhs
& ~R_INDEX
) != REG_HL
))
1718 q
= frag_more ((lhs
& R_INDEX
) ? 2 : 1);
1720 *q
++ = (lhs
& R_IX
) ? 0xDD : 0xFD;
1721 *q
= opcode
+ ((rhs
& 3) << 4);
1725 else if (!(lhs
& R_INDEX
) && (ins_ok
& INS_Z80N
))
1727 if (term
.X_op
== O_register
&& rhs
== REG_A
)
1728 { /* ADD BC/DE/HL,A */
1731 *q
= 0x33 - (lhs
& 3);
1734 else if (term
.X_op
!= O_register
&& term
.X_op
!= O_md1
)
1735 { /* ADD BC/DE/HL,nn */
1738 *q
= 0x36 - (lhs
& 3);
1751 emit_bit (char prefix
, char opcode
, const char * args
)
1757 p
= parse_exp (args
, &b
);
1759 error (_("bad instruction syntax"));
1761 bn
= b
.X_add_number
;
1763 && (b
.X_op
== O_constant
)
1768 /* Bit : no optional third operand. */
1769 p
= emit_m (prefix
, opcode
+ (bn
<< 3), p
);
1771 /* Set, res : resulting byte can be copied to register. */
1772 p
= emit_mr (prefix
, opcode
+ (bn
<< 3), p
);
1779 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
1781 emit_bshft (char prefix
, char opcode
, const char * args
)
1787 p
= parse_exp (args
, & r1
);
1789 error (_("bad instruction syntax"));
1790 p
= parse_exp (p
, & r2
);
1791 if (r1
.X_md
|| r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_DE
||
1792 r2
.X_md
|| r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_B
)
1801 emit_jpcc (char prefix
, char opcode
, const char * args
)
1806 p
= parse_cc (args
, & cc
);
1807 if (p
&& *p
++ == ',')
1808 p
= emit_call (0, opcode
+ cc
, p
);
1810 p
= (prefix
== (char)0xC3)
1811 ? emit_jp (0xE9, prefix
, args
)
1812 : emit_call (0, prefix
, args
);
1817 emit_jrcc (char prefix
, char opcode
, const char * args
)
1822 p
= parse_cc (args
, &cc
);
1823 if (p
&& *p
++ == ',')
1826 error (_("condition code invalid for jr"));
1828 p
= emit_jr (0, opcode
+ cc
, p
);
1831 p
= emit_jr (0, prefix
, args
);
1837 emit_ex (char prefix_in ATTRIBUTE_UNUSED
,
1838 char opcode_in ATTRIBUTE_UNUSED
, const char * args
)
1842 char prefix
, opcode
;
1844 p
= parse_exp_not_indexed (args
, &op
);
1848 error (_("bad instruction syntax"));
1852 prefix
= opcode
= 0;
1853 if (op
.X_op
== O_register
)
1854 switch (op
.X_add_number
| (op
.X_md
? 0x8000 : 0))
1857 if (TOLOWER (*p
++) == 'a' && TOLOWER (*p
++) == 'f')
1859 /* The scrubber changes '\'' to '`' in this context. */
1866 if (TOLOWER (*p
++) == 'h' && TOLOWER (*p
++) == 'l')
1870 p
= parse_exp (p
, & op
);
1871 if (op
.X_op
== O_register
1873 && (op
.X_add_number
& ~R_INDEX
) == REG_HL
)
1876 if (R_INDEX
& op
.X_add_number
)
1877 prefix
= (R_IX
& op
.X_add_number
) ? 0xDD : 0xFD;
1882 emit_insn (prefix
, opcode
, p
);
1890 emit_in (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1893 expressionS reg
, port
;
1897 p
= parse_exp (args
, ®
);
1898 if (reg
.X_md
&& reg
.X_op
== O_register
&& reg
.X_add_number
== REG_C
)
1899 { /* permit instruction in (c) as alias for in f,(c) */
1902 reg
.X_add_number
= REG_F
;
1908 error (_("bad instruction syntax"));
1911 p
= parse_exp (p
, &port
);
1914 && reg
.X_op
== O_register
1915 && (reg
.X_add_number
<= 7 || reg
.X_add_number
== REG_F
)
1918 if (port
.X_op
!= O_md1
&& port
.X_op
!= O_register
)
1920 if (REG_A
== reg
.X_add_number
)
1924 emit_byte (&port
, BFD_RELOC_8
);
1931 if (port
.X_add_number
== REG_C
|| port
.X_add_number
== REG_BC
)
1933 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
1935 else if (reg
.X_add_number
== REG_F
&& !(ins_ok
& (INS_R800
|INS_Z80N
)))
1936 check_mach (INS_IN_F_C
);
1939 *q
= 0x40|((reg
.X_add_number
&7)<<3);
1951 emit_in0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1954 expressionS reg
, port
;
1958 p
= parse_exp (args
, ®
);
1961 error (_("bad instruction syntax"));
1965 p
= parse_exp (p
, &port
);
1967 && reg
.X_op
== O_register
1968 && reg
.X_add_number
<= 7
1970 && port
.X_op
!= O_md1
1971 && port
.X_op
!= O_register
)
1975 *q
= 0x00|(reg
.X_add_number
<< 3);
1976 emit_byte (&port
, BFD_RELOC_8
);
1984 emit_out (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1987 expressionS reg
, port
;
1991 p
= parse_exp (args
, & port
);
1994 error (_("bad instruction syntax"));
1997 p
= parse_exp (p
, ®
);
1999 { ill_op (); return p
; }
2000 /* Allow "out (c), 0" as unportable instruction. */
2001 if (reg
.X_op
== O_constant
&& reg
.X_add_number
== 0)
2003 if (!(ins_ok
& INS_Z80N
))
2004 check_mach (INS_OUT_C_0
);
2005 reg
.X_op
= O_register
;
2006 reg
.X_add_number
= 6;
2009 || reg
.X_op
!= O_register
2010 || reg
.X_add_number
> 7)
2013 if (port
.X_op
!= O_register
&& port
.X_op
!= O_md1
)
2015 if (REG_A
== reg
.X_add_number
)
2019 emit_byte (&port
, BFD_RELOC_8
);
2026 if (REG_C
== port
.X_add_number
|| port
.X_add_number
== REG_BC
)
2028 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
2032 *q
= 0x41 | (reg
.X_add_number
<< 3);
2041 emit_out0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2044 expressionS reg
, port
;
2048 p
= parse_exp (args
, & port
);
2051 error (_("bad instruction syntax"));
2054 p
= parse_exp (p
, ®
);
2056 && port
.X_op
!= O_register
2057 && port
.X_op
!= O_md1
2059 && reg
.X_op
== O_register
2060 && reg
.X_add_number
<= 7)
2064 *q
= 0x01 | (reg
.X_add_number
<< 3);
2065 emit_byte (&port
, BFD_RELOC_8
);
2073 emit_rst (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2079 p
= parse_exp_not_indexed (args
, &addr
);
2080 if (addr
.X_op
!= O_constant
)
2082 error ("rst needs constant address");
2086 if (addr
.X_add_number
& ~(7 << 3))
2091 *q
= opcode
+ (addr
.X_add_number
& (7 << 3));
2096 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */
2098 emit_ld_m_n (expressionS
*dst
, expressionS
*src
)
2102 expressionS dst_offset
;
2104 switch (dst
->X_add_number
)
2106 case REG_HL
: prefix
= 0x00; break;
2107 case REG_IX
: prefix
= 0xDD; break;
2108 case REG_IY
: prefix
= 0xFD; break;
2114 q
= frag_more (prefix
? 2 : 1);
2121 dst_offset
.X_op
= O_symbol
;
2122 dst_offset
.X_add_number
= 0;
2123 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2125 emit_byte (src
, BFD_RELOC_8
);
2128 /* For 8-bit load register to memory instructions: LD (<expression>),r. */
2130 emit_ld_m_r (expressionS
*dst
, expressionS
*src
)
2134 expressionS dst_offset
;
2139 if (ins_ok
& INS_GBZ80
)
2140 { /* LD (HL+),A or LD (HL-),A */
2141 if (src
->X_op
!= O_register
|| src
->X_add_number
!= REG_A
)
2143 *frag_more (1) = (dst
->X_add_number
== REG_HL
) ? 0x22 : 0x32;
2147 prefix
= (dst
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2150 switch (dst
->X_add_number
)
2152 case REG_BC
: /* LD (BC),A */
2153 case REG_DE
: /* LD (DE),A */
2154 if (src
->X_add_number
== REG_A
)
2157 *q
= 0x02 | ((dst
->X_add_number
& 3) << 4);
2163 case REG_HL
: /* LD (HL),r or LD (ii+d),r */
2164 if (src
->X_add_number
<= 7)
2166 q
= frag_more (prefix
? 2 : 1);
2169 *q
= 0x70 | src
->X_add_number
;
2173 dst_offset
.X_op
= O_symbol
;
2174 dst_offset
.X_add_number
= 0;
2175 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2183 default: /* LD (nn),A */
2184 if (src
->X_add_number
== REG_A
)
2187 *q
= (ins_ok
& INS_GBZ80
) ? 0xEA : 0x32;
2196 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */
2198 emit_ld_m_rr (expressionS
*dst
, expressionS
*src
)
2203 expressionS dst_offset
;
2207 case O_md1
: /* eZ80 instructions LD (ii+d),rr */
2208 case O_register
: /* eZ80 instructions LD (HL),rr */
2209 if (!(ins_ok
& INS_EZ80
)) /* 16-bit indirect load group is supported by eZ80 only */
2211 switch (dst
->X_add_number
)
2213 case REG_IX
: prefix
= 0xDD; break;
2214 case REG_IY
: prefix
= 0xFD; break;
2215 case REG_HL
: prefix
= 0xED; break;
2219 switch (src
->X_add_number
)
2221 case REG_BC
: opcode
= 0x0F; break;
2222 case REG_DE
: opcode
= 0x1F; break;
2223 case REG_HL
: opcode
= 0x2F; break;
2224 case REG_IX
: opcode
= (prefix
!= 0xFD) ? 0x3F : 0x3E; break;
2225 case REG_IY
: opcode
= (prefix
!= 0xFD) ? 0x3E : 0x3F; break;
2229 q
= frag_more (prefix
? 2 : 1);
2232 if (prefix
== 0xFD || prefix
== 0xDD)
2235 dst_offset
.X_op
= O_symbol
;
2236 dst_offset
.X_add_number
= 0;
2237 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2240 default: /* LD (nn),rr */
2241 if (ins_ok
& INS_GBZ80
)
2243 /* GBZ80 supports only LD (nn),SP */
2244 if (src
->X_add_number
== REG_SP
)
2254 switch (src
->X_add_number
)
2256 case REG_BC
: prefix
= 0xED; opcode
= 0x43; break;
2257 case REG_DE
: prefix
= 0xED; opcode
= 0x53; break;
2258 case REG_HL
: prefix
= 0x00; opcode
= 0x22; break;
2259 case REG_IX
: prefix
= 0xDD; opcode
= 0x22; break;
2260 case REG_IY
: prefix
= 0xFD; opcode
= 0x22; break;
2261 case REG_SP
: prefix
= 0xED; opcode
= 0x73; break;
2266 q
= frag_more (prefix
? 2 : 1);
2275 emit_ld_r_m (expressionS
*dst
, expressionS
*src
)
2276 { /* for 8-bit memory load to register: LD r,(xxx) */
2280 expressionS src_offset
;
2282 if (dst
->X_add_number
== REG_A
&& src
->X_op
== O_register
)
2283 { /* LD A,(BC) or LD A,(DE) */
2284 switch (src
->X_add_number
)
2286 case REG_BC
: opcode
= 0x0A; break;
2287 case REG_DE
: opcode
= 0x1A; break;
2301 if (ins_ok
& INS_GBZ80
)
2302 { /* LD A,(HL+) or LD A,(HL-) */
2303 if (dst
->X_op
== O_register
&& dst
->X_add_number
== REG_A
)
2304 *frag_more (1) = (src
->X_add_number
== REG_HL
) ? 0x2A : 0x3A;
2311 if (dst
->X_add_number
> 7)
2313 opcode
= 0x46; /* LD B,(HL) */
2314 switch (src
->X_add_number
)
2316 case REG_HL
: prefix
= 0x00; break;
2317 case REG_IX
: prefix
= 0xDD; break;
2318 case REG_IY
: prefix
= 0xFD; break;
2322 q
= frag_more (prefix
? 2 : 1);
2325 *q
= opcode
| ((dst
->X_add_number
& 7) << 3);
2329 src_offset
.X_op
= O_symbol
;
2330 src_offset
.X_add_number
= 0;
2331 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2334 default: /* LD A,(nn) */
2335 if (dst
->X_add_number
== REG_A
)
2338 *q
= (ins_ok
& INS_GBZ80
) ? 0xFA : 0x3A;
2345 emit_ld_r_n (expressionS
*dst
, expressionS
*src
)
2346 { /* for 8-bit immediate value load to register: LD r,n */
2350 switch (dst
->X_add_number
)
2373 q
= frag_more (prefix
? 2 : 1);
2376 if (ins_ok
& INS_GBZ80
)
2378 else if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2379 check_mach (INS_IDX_HALF
);
2382 *q
= 0x06 | ((dst
->X_add_number
& 7) << 3);
2383 emit_byte (src
, BFD_RELOC_8
);
2387 emit_ld_r_r (expressionS
*dst
, expressionS
*src
)
2388 { /* mostly 8-bit load register from register instructions: LD r,r */
2389 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2395 switch (dst
->X_add_number
)
2398 switch (src
->X_add_number
)
2400 case REG_HL
: prefix
= 0x00; break;
2401 case REG_IX
: prefix
= 0xDD; break;
2402 case REG_IY
: prefix
= 0xFD; break;
2409 if (!(ins_ok
& INS_EZ80
))
2411 if (src
->X_add_number
!= REG_I
)
2414 error (_("ADL mode instruction"));
2420 if (src
->X_add_number
== REG_HL
)
2422 if (!(ins_ok
& INS_EZ80
))
2425 error (_("ADL mode instruction"));
2429 else if (src
->X_add_number
== REG_A
)
2438 if (!(ins_ok
& INS_EZ80
) || (src
->X_add_number
!= REG_A
))
2441 error (_("ADL mode instruction"));
2446 if (src
->X_add_number
== REG_A
) /* LD R,A */
2455 if (src
->X_add_number
== REG_I
) /* LD A,I */
2461 else if (src
->X_add_number
== REG_R
) /* LD A,R */
2467 else if (src
->X_add_number
== REG_MB
) /* LD A,MB */
2469 if (!(ins_ok
& INS_EZ80
))
2474 error (_("ADL mode instruction"));
2505 switch (src
->X_add_number
)
2516 ill_op (); /* LD iiH/L,H/L are not permitted */
2520 if (prefix
== 0xFD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2521 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2527 if (prefix
== 0xDD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2528 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2535 opcode
= 0x40 + ((dst
->X_add_number
& 7) << 3) + (src
->X_add_number
& 7);
2537 if ((ins_ok
& INS_GBZ80
) && prefix
!= 0)
2539 if (ii_halves
&& !(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2540 check_mach (INS_IDX_HALF
);
2541 if (prefix
== 0 && (ins_ok
& INS_EZ80
))
2545 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2546 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2547 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2548 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2549 as_warn (_("unsupported instruction, assembled as NOP"));
2555 q
= frag_more (prefix
? 2 : 1);
2562 emit_ld_rr_m (expressionS
*dst
, expressionS
*src
)
2563 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2567 expressionS src_offset
;
2569 /* GBZ80 has no support for 16-bit load from memory instructions */
2570 if (ins_ok
& INS_GBZ80
)
2576 case O_md1
: /* LD rr,(ii+d) */
2577 prefix
= (src
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2579 case O_register
: /* LD rr,(HL) */
2580 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2581 if (!(ins_ok
& INS_EZ80
))
2583 switch (dst
->X_add_number
)
2585 case REG_BC
: opcode
= 0x07; break;
2586 case REG_DE
: opcode
= 0x17; break;
2587 case REG_HL
: opcode
= 0x27; break;
2588 case REG_IX
: opcode
= (!prefix
|| prefix
== 0xDD) ? 0x37 : 0x31; break;
2589 case REG_IY
: opcode
= prefix
? ((prefix
== 0xDD) ? 0x31 : 0x37) : 0x36; break;
2599 src_offset
.X_op
= O_symbol
;
2600 src_offset
.X_add_number
= 0;
2601 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2604 default: /* LD rr,(nn) */
2605 switch (dst
->X_add_number
)
2607 case REG_BC
: prefix
= 0xED; opcode
= 0x4B; break;
2608 case REG_DE
: prefix
= 0xED; opcode
= 0x5B; break;
2609 case REG_HL
: prefix
= 0x00; opcode
= 0x2A; break;
2610 case REG_SP
: prefix
= 0xED; opcode
= 0x7B; break;
2611 case REG_IX
: prefix
= 0xDD; opcode
= 0x2A; break;
2612 case REG_IY
: prefix
= 0xFD; opcode
= 0x2A; break;
2616 q
= frag_more (prefix
? 2 : 1);
2626 emit_ld_rr_nn (expressionS
*dst
, expressionS
*src
)
2627 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2630 int opcode
= 0x21; /* LD HL,nn */
2631 switch (dst
->X_add_number
)
2644 opcode
= 0x01 + ((dst
->X_add_number
& 3) << 4);
2650 if (prefix
&& (ins_ok
& INS_GBZ80
))
2652 q
= frag_more (prefix
? 2 : 1);
2660 emit_ld (char prefix_in ATTRIBUTE_UNUSED
, char opcode_in ATTRIBUTE_UNUSED
,
2663 expressionS dst
, src
;
2666 p
= parse_exp (args
, & dst
);
2668 error (_("bad instruction syntax"));
2669 p
= parse_exp (p
, & src
);
2673 if (src
.X_op
== O_register
)
2675 if (src
.X_add_number
<= 7)
2676 emit_ld_m_r (& dst
, & src
); /* LD (xxx),r */
2678 emit_ld_m_rr (& dst
, & src
); /* LD (xxx),rr */
2681 emit_ld_m_n (& dst
, & src
); /* LD (hl),n or LD (ix/y+r),n */
2683 else if (dst
.X_op
== O_register
)
2687 if (dst
.X_add_number
<= 7)
2688 emit_ld_r_m (& dst
, & src
);
2690 emit_ld_rr_m (& dst
, & src
);
2692 else if (src
.X_op
== O_register
)
2693 emit_ld_r_r (& dst
, & src
);
2694 else if ((dst
.X_add_number
& ~R_INDEX
) <= 7)
2695 emit_ld_r_n (& dst
, & src
);
2697 emit_ld_rr_nn (& dst
, & src
);
2706 emit_lddldi (char prefix
, char opcode
, const char * args
)
2708 expressionS dst
, src
;
2712 if (!(ins_ok
& INS_GBZ80
))
2713 return emit_insn (prefix
, opcode
, args
);
2715 p
= parse_exp (args
, & dst
);
2717 error (_("bad instruction syntax"));
2718 p
= parse_exp (p
, & src
);
2720 if (dst
.X_op
!= O_register
|| src
.X_op
!= O_register
)
2723 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2724 opcode
= (opcode
& 0x08) * 2 + 0x22;
2727 && dst
.X_add_number
== REG_HL
2729 && src
.X_add_number
== REG_A
)
2730 opcode
|= 0x00; /* LDx (HL),A */
2731 else if (dst
.X_md
== 0
2732 && dst
.X_add_number
== REG_A
2734 && src
.X_add_number
== REG_HL
)
2735 opcode
|= 0x08; /* LDx A,(HL) */
2745 emit_ldh (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2748 expressionS dst
, src
;
2752 p
= parse_exp (args
, & dst
);
2755 error (_("bad instruction syntax"));
2759 p
= parse_exp (p
, & src
);
2761 && dst
.X_op
== O_register
2762 && dst
.X_add_number
== REG_A
2764 && src
.X_op
!= O_md1
)
2766 if (src
.X_op
!= O_register
)
2770 emit_byte (& src
, BFD_RELOC_8
);
2772 else if (src
.X_add_number
== REG_C
)
2773 *frag_more (1) = 0xF2;
2777 else if (dst
.X_md
!= 0
2778 && dst
.X_op
!= O_md1
2780 && src
.X_op
== O_register
2781 && src
.X_add_number
== REG_A
)
2783 if (dst
.X_op
== O_register
)
2785 if (dst
.X_add_number
== REG_C
)
2797 emit_byte (& dst
, BFD_RELOC_8
);
2807 emit_ldhl (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2809 expressionS dst
, src
;
2812 p
= parse_exp (args
, & dst
);
2815 error (_("bad instruction syntax"));
2819 p
= parse_exp (p
, & src
);
2820 if (dst
.X_md
|| dst
.X_op
!= O_register
|| dst
.X_add_number
!= REG_SP
2821 || src
.X_md
|| src
.X_op
== O_register
|| src
.X_op
== O_md1
)
2825 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2830 parse_lea_pea_args (const char * args
, expressionS
*op
)
2833 p
= parse_exp (args
, op
);
2834 if (sdcc_compat
&& *p
== ',' && op
->X_op
== O_register
)
2837 p
= parse_exp (p
+ 1, &off
);
2839 op
->X_add_symbol
= make_expr_symbol (&off
);
2845 emit_lea (char prefix
, char opcode
, const char * args
)
2847 expressionS dst
, src
;
2852 p
= parse_exp (args
, & dst
);
2853 if (dst
.X_md
!= 0 || dst
.X_op
!= O_register
)
2856 rnum
= dst
.X_add_number
;
2862 opcode
= 0x02 | ((rnum
& 0x03) << 4);
2865 opcode
= 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2868 opcode
= 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2875 error (_("bad instruction syntax"));
2877 p
= parse_lea_pea_args (p
, & src
);
2878 if (src
.X_md
!= 0 || src
.X_op
!= O_add
/*&& src.X_op != O_register*/)
2881 rnum
= src
.X_add_number
;
2886 case O_register
: /* permit instructions like LEA rr,IX without displacement specified */
2887 src
.X_add_symbol
= zero
;
2896 opcode
= (opcode
== (char)0x33) ? 0x55 : (opcode
|0x00);
2899 opcode
= (opcode
== (char)0x32) ? 0x54 : (opcode
|0x01);
2906 src
.X_op
= O_symbol
;
2907 src
.X_add_number
= 0;
2908 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2914 emit_mlt (char prefix
, char opcode
, const char * args
)
2920 p
= parse_exp (args
, & arg
);
2921 if (arg
.X_md
!= 0 || arg
.X_op
!= O_register
|| !(arg
.X_add_number
& R_ARITH
))
2925 if (ins_ok
& INS_Z80N
)
2927 if (arg
.X_add_number
!= REG_DE
)
2935 *q
= opcode
| ((arg
.X_add_number
& 3) << 4);
2941 /* MUL D,E (Z80N only) */
2943 emit_mul (char prefix
, char opcode
, const char * args
)
2949 p
= parse_exp (args
, & r1
);
2951 error (_("bad instruction syntax"));
2952 p
= parse_exp (p
, & r2
);
2954 if (r1
.X_md
!= 0 || r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_D
||
2955 r2
.X_md
!= 0 || r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_E
)
2966 emit_nextreg (char prefix
, char opcode ATTRIBUTE_UNUSED
, const char * args
)
2972 p
= parse_exp (args
, & rr
);
2974 error (_("bad instruction syntax"));
2975 p
= parse_exp (p
, & nn
);
2976 if (rr
.X_md
!= 0 || rr
.X_op
== O_register
|| rr
.X_op
== O_md1
||
2977 nn
.X_md
!= 0 || nn
.X_op
== O_md1
)
2981 emit_byte (&rr
, BFD_RELOC_8
);
2982 if (nn
.X_op
== O_register
&& nn
.X_add_number
== REG_A
)
2984 else if (nn
.X_op
!= O_register
)
2987 emit_byte (&nn
, BFD_RELOC_8
);
2995 emit_pea (char prefix
, char opcode
, const char * args
)
3001 p
= parse_lea_pea_args (args
, & arg
);
3003 || (/*arg.X_op != O_register &&*/ arg
.X_op
!= O_add
)
3004 || !(arg
.X_add_number
& R_INDEX
))
3006 /* PEA ii without displacement is mostly typo,
3007 because there is PUSH instruction which is shorter and faster */
3008 /*if (arg.X_op == O_register)
3009 as_warn (_("PEA is used without displacement, use PUSH instead"));*/
3013 *q
= opcode
+ (arg
.X_add_number
== REG_IY
? 1 : 0);
3015 arg
.X_op
= O_symbol
;
3016 arg
.X_add_number
= 0;
3017 emit_byte (& arg
, BFD_RELOC_Z80_DISP8
);
3023 emit_reti (char prefix
, char opcode
, const char * args
)
3025 if (ins_ok
& INS_GBZ80
)
3026 return emit_insn (0x00, 0xD9, args
);
3028 return emit_insn (prefix
, opcode
, args
);
3032 emit_tst (char prefix
, char opcode
, const char *args
)
3039 p
= parse_exp (args
, & arg_s
);
3040 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
3042 if (!(ins_ok
& INS_EZ80
))
3045 p
= parse_exp (p
, & arg_s
);
3048 rnum
= arg_s
.X_add_number
;
3055 rnum
= arg_s
.X_add_number
;
3056 if (arg_s
.X_md
!= 0)
3065 *q
= opcode
| (rnum
<< 3);
3071 if (ins_ok
& INS_Z80N
)
3081 emit_byte (& arg_s
, BFD_RELOC_8
);
3087 emit_insn_n (char prefix
, char opcode
, const char *args
)
3093 p
= parse_exp (args
, & arg
);
3094 if (arg
.X_md
|| arg
.X_op
== O_register
|| arg
.X_op
== O_md1
)
3100 emit_byte (& arg
, BFD_RELOC_8
);
3106 emit_data (int size ATTRIBUTE_UNUSED
)
3113 if (is_it_end_of_statement ())
3115 demand_empty_rest_of_line ();
3118 p
= skip_space (input_line_pointer
);
3122 if (*p
== '\"' || *p
== '\'')
3124 for (quote
= *p
, q
= ++p
, cnt
= 0; *p
&& quote
!= *p
; ++p
, ++cnt
)
3126 u
= frag_more (cnt
);
3129 as_warn (_("unterminated string"));
3131 p
= skip_space (p
+1);
3135 p
= parse_exp (p
, &exp
);
3136 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3142 as_warn (_("parentheses ignored"));
3143 emit_byte (&exp
, BFD_RELOC_8
);
3147 while (*p
++ == ',') ;
3148 input_line_pointer
= (char *)(p
-1);
3157 if (is_it_end_of_statement ())
3159 demand_empty_rest_of_line ();
3162 p
= skip_space (input_line_pointer
);
3166 p
= parse_exp (p
, &exp
);
3167 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3173 as_warn (_("parentheses ignored"));
3174 emit_data_val (&exp
, size
);
3176 } while (*p
++ == ',') ;
3177 input_line_pointer
= (char *)(p
-1);
3180 /* next functions were commented out because it is difficult to mix
3181 both ADL and Z80 mode instructions within one COFF file:
3182 objdump cannot recognize point of mode switching.
3185 set_cpu_mode (int mode
)
3187 if (ins_ok
& INS_EZ80
)
3190 error (_("CPU mode is unsupported by target"));
3194 assume (int arg ATTRIBUTE_UNUSED
)
3200 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3201 c
= get_symbol_name (& name
);
3202 if (strncasecmp (name
, "ADL", 4) != 0)
3208 restore_line_pointer (c
);
3209 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3210 if (*input_line_pointer
++ != '=')
3212 error (_("assignment expected"));
3215 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3216 n
= get_single_number ();
3222 emit_mulub (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3226 p
= skip_space (args
);
3227 if (TOLOWER (*p
++) != 'a' || *p
++ != ',')
3233 reg
= TOLOWER (*p
++);
3240 check_mach (INS_R800
);
3241 if (!*skip_space (p
))
3245 *q
= opcode
+ ((reg
- 'b') << 3);
3257 emit_muluw (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3261 p
= skip_space (args
);
3262 if (TOLOWER (*p
++) != 'h' || TOLOWER (*p
++) != 'l' || *p
++ != ',')
3269 p
= parse_exp (p
, & reg
);
3271 if ((!reg
.X_md
) && reg
.X_op
== O_register
)
3272 switch (reg
.X_add_number
)
3276 check_mach (INS_R800
);
3279 *q
= opcode
+ ((reg
.X_add_number
& 3) << 4);
3289 assemble_suffix (const char **suffix
)
3292 const char sf
[8][4] =
3312 for (i
= 0; (i
< 3) && (ISALPHA (*p
)); i
++)
3313 sbuf
[i
] = TOLOWER (*p
++);
3314 if (*p
&& !ISSPACE (*p
))
3319 t
= bsearch (sbuf
, sf
, ARRAY_SIZE (sf
), sizeof (sf
[0]), (int(*)(const void*, const void*)) strcmp
);
3326 i
= cpu_mode
? 0x5B : 0x52;
3329 i
= cpu_mode
? 0x49 : 0x40;
3332 i
= cpu_mode
? 0x5B : 0x49;
3341 i
= cpu_mode
? 0x52 : 0x40;
3350 *frag_more (1) = (char)i
;
3353 case 0x40: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IS
; break;
3354 case 0x49: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IS
; break;
3355 case 0x52: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IL
; break;
3356 case 0x5B: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IL
; break;
3364 #if defined(OBJ_ELF)
3365 return obj_elf_section (arg
);
3366 #elif defined(OBJ_COFF)
3367 return obj_coff_section (arg
);
3369 #error Unknown object format
3379 as_fatal (_("Invalid directive"));
3382 ins_ok
&= INS_MARCH_MASK
;
3384 if (old_ins
!= ins_ok
)
3389 ignore (int arg ATTRIBUTE_UNUSED
)
3391 ignore_rest_of_line ();
3399 as_fatal (_("Invalid directive"));
3400 for (p
= input_line_pointer
; *p
&& *p
!= '(' && *p
!= '\n'; p
++)
3407 ignore_rest_of_line ();
3413 /* Port specific pseudo ops. */
3414 const pseudo_typeS md_pseudo_table
[] =
3416 { ".area", area
, 0},
3417 { ".assume", assume
, 0},
3418 { ".ez80", set_inss
, INS_EZ80
},
3419 { ".gbz80", set_inss
, INS_GBZ80
},
3420 { ".module", ignore
, 0},
3421 { ".optsdcc", ignore
, 0},
3422 { ".r800", set_inss
, INS_R800
},
3423 { ".set", s_set
, 0},
3424 { ".z180", set_inss
, INS_Z180
},
3425 { ".z80", set_inss
, INS_Z80
},
3426 { ".z80n", set_inss
, INS_Z80N
},
3427 { "db" , emit_data
, 1},
3428 { "d24", z80_cons
, 3},
3429 { "d32", z80_cons
, 4},
3430 { "def24", z80_cons
, 3},
3431 { "def32", z80_cons
, 4},
3432 { "defb", emit_data
, 1},
3433 { "defm", emit_data
, 1},
3434 { "defs", s_space
, 1}, /* Synonym for ds on some assemblers. */
3435 { "defw", z80_cons
, 2},
3436 { "ds", s_space
, 1}, /* Fill with bytes rather than words. */
3437 { "dw", z80_cons
, 2},
3438 { "psect", psect
, 0}, /* TODO: Translate attributes. */
3439 { "set", 0, 0}, /* Real instruction on z80. */
3443 static table_t instab
[] =
3445 { "adc", 0x88, 0x4A, emit_adc
, INS_ALL
},
3446 { "add", 0x80, 0x09, emit_add
, INS_ALL
},
3447 { "and", 0x00, 0xA0, emit_s
, INS_ALL
},
3448 { "bit", 0xCB, 0x40, emit_bit
, INS_ALL
},
3449 { "brlc", 0xED, 0x2C, emit_bshft
,INS_Z80N
},
3450 { "bsla", 0xED, 0x28, emit_bshft
,INS_Z80N
},
3451 { "bsra", 0xED, 0x29, emit_bshft
,INS_Z80N
},
3452 { "bsrf", 0xED, 0x2B, emit_bshft
,INS_Z80N
},
3453 { "bsrl", 0xED, 0x2A, emit_bshft
,INS_Z80N
},
3454 { "call", 0xCD, 0xC4, emit_jpcc
, INS_ALL
},
3455 { "ccf", 0x00, 0x3F, emit_insn
, INS_ALL
},
3456 { "cp", 0x00, 0xB8, emit_s
, INS_ALL
},
3457 { "cpd", 0xED, 0xA9, emit_insn
, INS_NOT_GBZ80
},
3458 { "cpdr", 0xED, 0xB9, emit_insn
, INS_NOT_GBZ80
},
3459 { "cpi", 0xED, 0xA1, emit_insn
, INS_NOT_GBZ80
},
3460 { "cpir", 0xED, 0xB1, emit_insn
, INS_NOT_GBZ80
},
3461 { "cpl", 0x00, 0x2F, emit_insn
, INS_ALL
},
3462 { "daa", 0x00, 0x27, emit_insn
, INS_ALL
},
3463 { "dec", 0x0B, 0x05, emit_incdec
,INS_ALL
},
3464 { "di", 0x00, 0xF3, emit_insn
, INS_ALL
},
3465 { "djnz", 0x00, 0x10, emit_jr
, INS_NOT_GBZ80
},
3466 { "ei", 0x00, 0xFB, emit_insn
, INS_ALL
},
3467 { "ex", 0x00, 0x00, emit_ex
, INS_NOT_GBZ80
},
3468 { "exx", 0x00, 0xD9, emit_insn
, INS_NOT_GBZ80
},
3469 { "halt", 0x00, 0x76, emit_insn
, INS_ALL
},
3470 { "im", 0xED, 0x46, emit_im
, INS_NOT_GBZ80
},
3471 { "in", 0x00, 0x00, emit_in
, INS_NOT_GBZ80
},
3472 { "in0", 0xED, 0x00, emit_in0
, INS_Z180
|INS_EZ80
},
3473 { "inc", 0x03, 0x04, emit_incdec
,INS_ALL
},
3474 { "ind", 0xED, 0xAA, emit_insn
, INS_NOT_GBZ80
},
3475 { "ind2", 0xED, 0x8C, emit_insn
, INS_EZ80
},
3476 { "ind2r",0xED, 0x9C, emit_insn
, INS_EZ80
},
3477 { "indm", 0xED, 0x8A, emit_insn
, INS_EZ80
},
3478 { "indmr",0xED, 0x9A, emit_insn
, INS_EZ80
},
3479 { "indr", 0xED, 0xBA, emit_insn
, INS_NOT_GBZ80
},
3480 { "indrx",0xED, 0xCA, emit_insn
, INS_EZ80
},
3481 { "ini", 0xED, 0xA2, emit_insn
, INS_NOT_GBZ80
},
3482 { "ini2", 0xED, 0x84, emit_insn
, INS_EZ80
},
3483 { "ini2r",0xED, 0x94, emit_insn
, INS_EZ80
},
3484 { "inim", 0xED, 0x82, emit_insn
, INS_EZ80
},
3485 { "inimr",0xED, 0x92, emit_insn
, INS_EZ80
},
3486 { "inir", 0xED, 0xB2, emit_insn
, INS_NOT_GBZ80
},
3487 { "inirx",0xED, 0xC2, emit_insn
, INS_EZ80
},
3488 { "jp", 0xC3, 0xC2, emit_jpcc
, INS_ALL
},
3489 { "jr", 0x18, 0x20, emit_jrcc
, INS_ALL
},
3490 { "ld", 0x00, 0x00, emit_ld
, INS_ALL
},
3491 { "ldd", 0xED, 0xA8, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3492 { "lddr", 0xED, 0xB8, emit_insn
, INS_NOT_GBZ80
},
3493 { "lddrx",0xED, 0xBC, emit_insn
, INS_Z80N
},
3494 { "lddx", 0xED, 0xAC, emit_insn
, INS_Z80N
},
3495 { "ldh", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3496 { "ldhl", 0x00, 0xF8, emit_ldhl
, INS_GBZ80
},
3497 { "ldi", 0xED, 0xA0, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3498 { "ldir", 0xED, 0xB0, emit_insn
, INS_NOT_GBZ80
},
3499 { "ldirx",0xED, 0xB4, emit_insn
, INS_Z80N
},
3500 { "ldix", 0xED, 0xA4, emit_insn
, INS_Z80N
},
3501 { "ldpirx",0xED,0xB7, emit_insn
, INS_Z80N
},
3502 { "ldws", 0xED, 0xA5, emit_insn
, INS_Z80N
},
3503 { "lea", 0xED, 0x02, emit_lea
, INS_EZ80
},
3504 { "mirror",0xED,0x24, emit_insn
, INS_Z80N
},
3505 { "mlt", 0xED, 0x4C, emit_mlt
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3506 { "mul", 0xED, 0x30, emit_mul
, INS_Z80N
},
3507 { "mulub",0xED, 0xC5, emit_mulub
,INS_R800
},
3508 { "muluw",0xED, 0xC3, emit_muluw
,INS_R800
},
3509 { "neg", 0xED, 0x44, emit_insn
, INS_NOT_GBZ80
},
3510 { "nextreg",0xED,0x91,emit_nextreg
,INS_Z80N
},
3511 { "nop", 0x00, 0x00, emit_insn
, INS_ALL
},
3512 { "or", 0x00, 0xB0, emit_s
, INS_ALL
},
3513 { "otd2r",0xED, 0xBC, emit_insn
, INS_EZ80
},
3514 { "otdm", 0xED, 0x8B, emit_insn
, INS_Z180
|INS_EZ80
},
3515 { "otdmr",0xED, 0x9B, emit_insn
, INS_Z180
|INS_EZ80
},
3516 { "otdr", 0xED, 0xBB, emit_insn
, INS_NOT_GBZ80
},
3517 { "otdrx",0xED, 0xCB, emit_insn
, INS_EZ80
},
3518 { "oti2r",0xED, 0xB4, emit_insn
, INS_EZ80
},
3519 { "otim", 0xED, 0x83, emit_insn
, INS_Z180
|INS_EZ80
},
3520 { "otimr",0xED, 0x93, emit_insn
, INS_Z180
|INS_EZ80
},
3521 { "otir", 0xED, 0xB3, emit_insn
, INS_NOT_GBZ80
},
3522 { "otirx",0xED, 0xC3, emit_insn
, INS_EZ80
},
3523 { "out", 0x00, 0x00, emit_out
, INS_NOT_GBZ80
},
3524 { "out0", 0xED, 0x01, emit_out0
, INS_Z180
|INS_EZ80
},
3525 { "outd", 0xED, 0xAB, emit_insn
, INS_NOT_GBZ80
},
3526 { "outd2",0xED, 0xAC, emit_insn
, INS_EZ80
},
3527 { "outi", 0xED, 0xA3, emit_insn
, INS_NOT_GBZ80
},
3528 { "outi2",0xED, 0xA4, emit_insn
, INS_EZ80
},
3529 { "outinb",0xED,0x90, emit_insn
, INS_Z80N
},
3530 { "pea", 0xED, 0x65, emit_pea
, INS_EZ80
},
3531 { "pixelad",0xED,0x94,emit_insn
, INS_Z80N
},
3532 { "pixeldn",0xED,0x93,emit_insn
, INS_Z80N
},
3533 { "pop", 0x00, 0xC1, emit_pop
, INS_ALL
},
3534 { "push", 0x00, 0xC5, emit_push
, INS_ALL
},
3535 { "res", 0xCB, 0x80, emit_bit
, INS_ALL
},
3536 { "ret", 0xC9, 0xC0, emit_retcc
,INS_ALL
},
3537 { "reti", 0xED, 0x4D, emit_reti
, INS_ALL
}, /*GBZ80 has its own opcode for it*/
3538 { "retn", 0xED, 0x45, emit_insn
, INS_NOT_GBZ80
},
3539 { "rl", 0xCB, 0x10, emit_mr
, INS_ALL
},
3540 { "rla", 0x00, 0x17, emit_insn
, INS_ALL
},
3541 { "rlc", 0xCB, 0x00, emit_mr
, INS_ALL
},
3542 { "rlca", 0x00, 0x07, emit_insn
, INS_ALL
},
3543 { "rld", 0xED, 0x6F, emit_insn
, INS_NOT_GBZ80
},
3544 { "rr", 0xCB, 0x18, emit_mr
, INS_ALL
},
3545 { "rra", 0x00, 0x1F, emit_insn
, INS_ALL
},
3546 { "rrc", 0xCB, 0x08, emit_mr
, INS_ALL
},
3547 { "rrca", 0x00, 0x0F, emit_insn
, INS_ALL
},
3548 { "rrd", 0xED, 0x67, emit_insn
, INS_NOT_GBZ80
},
3549 { "rsmix",0xED, 0x7E, emit_insn
, INS_EZ80
},
3550 { "rst", 0x00, 0xC7, emit_rst
, INS_ALL
},
3551 { "sbc", 0x98, 0x42, emit_adc
, INS_ALL
},
3552 { "scf", 0x00, 0x37, emit_insn
, INS_ALL
},
3553 { "set", 0xCB, 0xC0, emit_bit
, INS_ALL
},
3554 { "setae",0xED, 0x95, emit_insn
, INS_Z80N
},
3555 { "sl1", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3556 { "sla", 0xCB, 0x20, emit_mr
, INS_ALL
},
3557 { "sli", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3558 { "sll", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3559 { "slp", 0xED, 0x76, emit_insn
, INS_Z180
|INS_EZ80
},
3560 { "sra", 0xCB, 0x28, emit_mr
, INS_ALL
},
3561 { "srl", 0xCB, 0x38, emit_mr
, INS_ALL
},
3562 { "stmix",0xED, 0x7D, emit_insn
, INS_EZ80
},
3563 { "stop", 0x00, 0x10, emit_insn
, INS_GBZ80
},
3564 { "sub", 0x00, 0x90, emit_sub
, INS_ALL
},
3565 { "swap", 0xCB, 0x30, emit_swap
, INS_GBZ80
|INS_Z80N
},
3566 { "swapnib",0xED,0x23,emit_insn
, INS_Z80N
},
3567 { "test", 0xED, 0x27, emit_insn_n
, INS_Z80N
},
3568 { "tst", 0xED, 0x04, emit_tst
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3569 { "tstio",0xED, 0x74, emit_insn_n
,INS_Z180
|INS_EZ80
},
3570 { "xor", 0x00, 0xA8, emit_s
, INS_ALL
},
3574 md_assemble (char *str
)
3582 inst_mode
= cpu_mode
? (INST_MODE_L
| INST_MODE_IL
) : (INST_MODE_S
| INST_MODE_IS
);
3583 old_ptr
= input_line_pointer
;
3584 p
= skip_space (str
);
3585 for (i
= 0; (i
< BUFLEN
) && (ISALPHA (*p
) || ISDIGIT (*p
));)
3586 buf
[i
++] = TOLOWER (*p
++);
3590 buf
[BUFLEN
-3] = buf
[BUFLEN
-2] = '.'; /* Mark opcode as abbreviated. */
3592 as_bad (_("Unknown instruction '%s'"), buf
);
3596 dwarf2_emit_insn (0);
3597 if ((*p
) && (!ISSPACE (*p
)))
3599 if (*p
!= '.' || !(ins_ok
& INS_EZ80
) || !assemble_suffix (&p
))
3601 as_bad (_("syntax error"));
3609 insp
= bsearch (&key
, instab
, ARRAY_SIZE (instab
),
3610 sizeof (instab
[0]), key_cmp
);
3611 if (!insp
|| (insp
->inss
&& !(insp
->inss
& ins_ok
)))
3614 as_bad (_("Unknown instruction `%s'"), buf
);
3618 p
= insp
->fp (insp
->prefix
, insp
->opcode
, p
);
3620 if ((!err_flag
) && *p
)
3621 as_bad (_("junk at end of line, "
3622 "first unrecognized character is `%c'"), *p
);
3626 input_line_pointer
= old_ptr
;
3630 is_overflow (long value
, unsigned bitsize
)
3632 long fieldmask
= (1 << bitsize
) - 1;
3633 long signmask
= ~fieldmask
;
3634 long a
= value
& fieldmask
;
3635 long ss
= a
& signmask
;
3636 if (ss
!= 0 && ss
!= (signmask
& fieldmask
))
3642 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
3645 char *p_lit
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3647 if (fixP
->fx_addsy
== NULL
)
3649 else if (fixP
->fx_pcrel
)
3651 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
3652 if (s
== seg
|| s
== absolute_section
)
3654 val
+= S_GET_VALUE (fixP
->fx_addsy
);
3659 switch (fixP
->fx_r_type
)
3661 case BFD_RELOC_8_PCREL
:
3662 case BFD_RELOC_Z80_DISP8
:
3667 case BFD_RELOC_Z80_16_BE
:
3668 fixP
->fx_no_overflow
= 0;
3671 fixP
->fx_no_overflow
= 1;
3675 switch (fixP
->fx_r_type
)
3677 case BFD_RELOC_8_PCREL
:
3678 case BFD_RELOC_Z80_DISP8
:
3679 if (fixP
->fx_done
&& (val
< -0x80 || val
> 0x7f))
3680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3681 _("8-bit signed offset out of range (%+ld)"), val
);
3685 case BFD_RELOC_Z80_BYTE0
:
3689 case BFD_RELOC_Z80_BYTE1
:
3690 *p_lit
++ = (val
>> 8);
3693 case BFD_RELOC_Z80_BYTE2
:
3694 *p_lit
++ = (val
>> 16);
3697 case BFD_RELOC_Z80_BYTE3
:
3698 *p_lit
++ = (val
>> 24);
3702 if (fixP
->fx_done
&& is_overflow(val
, 8))
3703 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3704 _("8-bit overflow (%+ld)"), val
);
3708 case BFD_RELOC_Z80_WORD1
:
3709 *p_lit
++ = (val
>> 16);
3710 *p_lit
++ = (val
>> 24);
3713 case BFD_RELOC_Z80_WORD0
:
3715 *p_lit
++ = (val
>> 8);
3719 if (fixP
->fx_done
&& is_overflow(val
, 16))
3720 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3721 _("16-bit overflow (%+ld)"), val
);
3723 *p_lit
++ = (val
>> 8);
3726 case BFD_RELOC_24
: /* Def24 may produce this. */
3727 if (fixP
->fx_done
&& is_overflow(val
, 24))
3728 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3729 _("24-bit overflow (%+ld)"), val
);
3731 *p_lit
++ = (val
>> 8);
3732 *p_lit
++ = (val
>> 16);
3735 case BFD_RELOC_32
: /* Def32 and .long may produce this. */
3736 if (fixP
->fx_done
&& is_overflow(val
, 32))
3737 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3738 _("32-bit overflow (%+ld)"), val
);
3740 *p_lit
++ = (val
>> 8);
3741 *p_lit
++ = (val
>> 16);
3742 *p_lit
++ = (val
>> 24);
3745 case BFD_RELOC_Z80_16_BE
: /* Z80N PUSH nn instruction produce this. */
3746 *p_lit
++ = val
>> 8;
3751 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP
->fx_r_type
);
3756 /* GAS will call this to generate a reloc. GAS will pass the
3757 resulting reloc to `bfd_install_relocation'. This currently works
3758 poorly, as `bfd_install_relocation' often does the wrong thing, and
3759 instances of `tc_gen_reloc' have been written to work around the
3760 problems, which in turns makes it difficult to fix
3761 `bfd_install_relocation'. */
3763 /* If while processing a fixup, a reloc really
3764 needs to be created then it is done here. */
3767 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3771 if (fixp
->fx_subsy
!= NULL
)
3773 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
3777 reloc
= XNEW (arelent
);
3778 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3779 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3780 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3781 reloc
->addend
= fixp
->fx_offset
;
3782 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3783 if (reloc
->howto
== NULL
)
3785 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3786 _("reloc %d not supported by object file format"),
3787 (int) fixp
->fx_r_type
);
3791 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3792 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3793 reloc
->address
= fixp
->fx_offset
;
3799 z80_tc_label_is_local (const char *name
)
3803 if (local_label_prefix
== NULL
)
3805 for (p
= local_label_prefix
, n
= name
; *p
&& *n
&& *n
== *p
; p
++, n
++)
3810 /* Parse floating point number from string and compute mantissa and
3811 exponent. Mantissa is normalized.
3813 #define EXP_MIN -0x10000
3814 #define EXP_MAX 0x10000
3816 str_to_broken_float (bfd_boolean
*signP
, bfd_uint64_t
*mantissaP
, int *expP
)
3820 bfd_uint64_t mantissa
= 0;
3824 p
= (char*)skip_space (input_line_pointer
);
3827 if (sign
|| *p
== '+')
3829 if (strncasecmp (p
, "NaN", 3) == 0)
3833 input_line_pointer
= p
+ 3;
3836 if (strncasecmp (p
, "inf", 3) == 0)
3838 *mantissaP
= 1ull << 63;
3840 input_line_pointer
= p
+ 3;
3843 for (; ISDIGIT (*p
); ++p
)
3851 mantissa
= mantissa
* 10 + (*p
- '0');
3853 /* skip non-significant digits */
3854 for (; ISDIGIT (*p
); ++p
)
3860 if (!exponent
) /* If no precission overflow. */
3862 for (; ISDIGIT (*p
); ++p
, --exponent
)
3870 mantissa
= mantissa
* 10 + (*p
- '0');
3873 for (; ISDIGIT (*p
); ++p
)
3876 if (*p
== 'e' || *p
== 'E')
3882 if (es
|| *p
== '+')
3884 for (; ISDIGIT (*p
); ++p
)
3887 t
= t
* 10 + (*p
- '0');
3889 exponent
+= (es
) ? -t
: t
;
3891 if (ISALNUM (*p
) || *p
== '.')
3893 input_line_pointer
= p
;
3896 *mantissaP
= 1ull << 63;
3898 return 1; /* result is 0 */
3901 for (; mantissa
<= ~0ull/10; --exponent
)
3903 /* Now we have sign, mantissa, and signed decimal exponent
3904 need to recompute to binary exponent. */
3905 for (i
= 64; exponent
> 0; --exponent
)
3907 /* be sure that no integer overflow */
3908 while (mantissa
> ~0ull/10)
3915 for (; exponent
< 0; ++exponent
)
3917 while (!(mantissa
>> 63))
3925 for (; !(mantissa
>> 63); --i
)
3927 *mantissaP
= mantissa
;
3933 str_to_zeda32(char *litP
, int *sizeP
)
3935 bfd_uint64_t mantissa
;
3941 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
3942 return _("invalid syntax");
3943 /* I do not know why decrement is needed */
3945 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
3949 /* make 24 bit mantissa */
3951 /* check for overflow */
3958 if (exponent
< -127)
3963 else if (exponent
> 127)
3966 mantissa
= sign
? 0xc00000 : 0x400000;
3968 else if (mantissa
== 0)
3971 mantissa
= 0x200000;
3974 mantissa
&= (1ull << 23) - 1;
3975 for (i
= 0; i
< 24; i
+= 8)
3976 *litP
++ = (char)(mantissa
>> i
);
3977 *litP
= (char)(0x80 + exponent
);
3982 Math48 by Anders Hejlsberg support.
3983 Mantissa is 39 bits wide, exponent 8 bit wide.
3986 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
3987 bit 7-0: exponent+128 (0 - value is null)
3988 MIN: 2.938735877e-39
3989 MAX: 1.701411835e+38
3992 str_to_float48(char *litP
, int *sizeP
)
3994 bfd_uint64_t mantissa
;
4000 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
4001 return _("invalid syntax");
4002 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
4006 /* make 40 bit mantissa */
4008 /* check for overflow */
4014 if (exponent
< -127)
4016 memset (litP
, 0, 6);
4020 return _("overflow");
4022 mantissa
&= (1ull << 39) - 1;
4023 *litP
++ = (char)(0x80 + exponent
);
4024 for (i
= 0; i
< 40; i
+= 8)
4025 *litP
++ = (char)(mantissa
>> i
);
4030 str_to_ieee754_h(char *litP
, int *sizeP
)
4032 return ieee_md_atof ('h', litP
, sizeP
, FALSE
);
4036 str_to_ieee754_s(char *litP
, int *sizeP
)
4038 return ieee_md_atof ('s', litP
, sizeP
, FALSE
);
4042 str_to_ieee754_d(char *litP
, int *sizeP
)
4044 return ieee_md_atof ('d', litP
, sizeP
, FALSE
);
4047 #ifdef TARGET_USE_CFIPOP
4048 /* Initialize the DWARF-2 unwind information for this procedure. */
4050 z80_tc_frame_initial_instructions (void)
4052 static int sp_regno
= -1;
4055 sp_regno
= z80_tc_regname_to_dw2regnum ("sp");
4057 cfi_add_CFA_def_cfa (sp_regno
, 0);
4061 z80_tc_regname_to_dw2regnum (const char *regname
)
4063 static const char *regs
[] =
4064 { /* same registers as for GDB */
4065 "af", "bc", "de", "hl",
4066 "sp", "pc", "ix", "iy",
4067 "af_", "bc_", "de_", "hl_",
4072 for (i
= 0; i
< ARRAY_SIZE(regs
); ++i
)
4073 if (!strcasecmp (regs
[i
], regname
))
4080 /* Implement DWARF2_ADDR_SIZE. */
4082 z80_dwarf2_addr_size (const bfd
*abfd
)
4084 switch (bfd_get_mach (abfd
))
4086 case bfd_mach_ez80_adl
: