1 @c Copyright (C) 2009-2018 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
75 The special name @code{all} may be used to allow the assembler to accept
76 instructions valid for any supported processor, including all optional
79 In addition to the basic instruction set, the assembler can be told to
80 accept, or restrict, various extension mnemonics that extend the
81 processor. @xref{AArch64 Extensions}.
83 If some implementations of a particular processor can have an
84 extension, then then those extensions are automatically enabled.
85 Consequently, you will not normally have to specify any additional
88 @cindex @option{-march=} command line option, AArch64
89 @item -march=@var{architecture}[+@var{extension}@dots{}]
90 This option specifies the target architecture. The assembler will
91 issue an error message if an attempt is made to assemble an
92 instruction which will not execute on the target architecture. The
93 following architecture names are recognized: @code{armv8-a},
94 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
96 If both @option{-mcpu} and @option{-march} are specified, the
97 assembler will use the setting for @option{-mcpu}. If neither are
98 specified, the assembler will default to @option{-mcpu=all}.
100 The architecture option can be extended with the same instruction set
101 extension options as the @option{-mcpu} option. Unlike
102 @option{-mcpu}, extensions are not always enabled by default,
103 @xref{AArch64 Extensions}.
105 @cindex @code{-mverbose-error} command line option, AArch64
106 @item -mverbose-error
107 This option enables verbose error messages for AArch64 gas. This option
108 is enabled by default.
110 @cindex @code{-mno-verbose-error} command line option, AArch64
111 @item -mno-verbose-error
112 This option disables verbose error messages in AArch64 gas.
117 @node AArch64 Extensions
118 @section Architecture Extensions
120 The table below lists the permitted architecture extensions that are
121 supported by the assembler and the conditions under which they are
122 automatically enabled.
124 Multiple extensions may be specified, separated by a @code{+}.
125 Extension mnemonics may also be removed from those the assembler
126 accepts. This is done by prepending @code{no} to the option that adds
127 the extension. Extensions that are removed must be listed after all
128 extensions that have been added.
130 Enabling an extension that requires other extensions will
131 automatically cause those extensions to be enabled. Similarly,
132 disabling an extension that is required by other extensions will
133 automatically cause those extensions to be disabled.
135 @multitable @columnfractions .12 .17 .17 .54
136 @headitem Extension @tab Minimum Architecture @tab Enabled by default
138 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
139 @tab Enable the complex number SIMD extensions. This implies
140 @code{fp16} and @code{simd}.
141 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
142 @tab Enable CRC instructions.
143 @item @code{crypto} @tab ARMv8-A @tab No
144 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
145 @item @code{aes} @tab ARMv8-A @tab No
146 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
147 @item @code{sha2} @tab ARMv8-A @tab No
148 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
149 @item @code{sha3} @tab ARMv8.2-A @tab No
150 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
151 @item @code{sm4} @tab ARMv8.2-A @tab No
152 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
153 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
154 @tab Enable floating-point extensions.
155 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
156 @tab Enable ARMv8.2 16-bit floating-point support. This implies
158 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
159 @tab Enable Limited Ordering Regions extensions.
160 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
161 @tab Enable Large System extensions.
162 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
163 @tab Enable Privileged Access Never support.
164 @item @code{profile} @tab ARMv8.2-A @tab No
165 @tab Enable statistical profiling extensions.
166 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
167 @tab Enable the Reliability, Availability and Serviceability
169 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
170 @tab Enable the weak release consistency extension.
171 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
172 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
173 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
174 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
175 @item @code{sve} @tab ARMv8.2-A @tab No
176 @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
177 @code{simd} and @code{compnum}.
178 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
179 @tab Enable the Dot Product extension. This implies @code{simd}.
180 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
181 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
182 This implies @code{fp16}.
188 * AArch64-Chars:: Special Characters
189 * AArch64-Regs:: Register Names
190 * AArch64-Relocations:: Relocations
194 @subsection Special Characters
196 @cindex line comment character, AArch64
197 @cindex AArch64 line comment character
198 The presence of a @samp{//} on a line indicates the start of a comment
199 that extends to the end of the current line. If a @samp{#} appears as
200 the first character of a line, the whole line is treated as a comment.
202 @cindex line separator, AArch64
203 @cindex statement separator, AArch64
204 @cindex AArch64 line separator
205 The @samp{;} character can be used instead of a newline to separate
208 @cindex immediate character, AArch64
209 @cindex AArch64 immediate character
210 The @samp{#} can be optionally used to indicate immediate operands.
213 @subsection Register Names
215 @cindex AArch64 register names
216 @cindex register names, AArch64
217 Please refer to the section @samp{4.4 Register Names} of
218 @samp{ARMv8 Instruction Set Overview}, which is available at
219 @uref{http://infocenter.arm.com}.
221 @node AArch64-Relocations
222 @subsection Relocations
224 @cindex relocations, AArch64
225 @cindex AArch64 relocations
226 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
227 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
228 by prefixing the label with @samp{#:abs_g2:} etc.
229 For example to load the 48-bit absolute address of @var{foo} into x0:
232 movz x0, #:abs_g2:foo // bits 32-47, overflow check
233 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
234 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
237 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
238 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
239 instructions can be generated by prefixing the label with
240 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
242 For example to use 33-bit (+/-4GB) pc-relative addressing to
243 load the address of @var{foo} into x0:
246 adrp x0, :pg_hi21:foo
247 add x0, x0, #:lo12:foo
250 Or to load the value of @var{foo} into x0:
253 adrp x0, :pg_hi21:foo
254 ldr x0, [x0, #:lo12:foo]
257 Note that @samp{:pg_hi21:} is optional.
266 adrp x0, :pg_hi21:foo
269 @node AArch64 Floating Point
270 @section Floating Point
272 @cindex floating point, AArch64 (@sc{ieee})
273 @cindex AArch64 floating point (@sc{ieee})
274 The AArch64 architecture uses @sc{ieee} floating-point numbers.
276 @node AArch64 Directives
277 @section AArch64 Machine Directives
279 @cindex machine directives, AArch64
280 @cindex AArch64 machine directives
283 @c AAAAAAAAAAAAAAAAAAAAAAAAA
285 @cindex @code{.arch} directive, AArch64
286 @item .arch @var{name}
287 Select the target architecture. Valid values for @var{name} are the same as
288 for the @option{-march} commandline option.
290 Specifying @code{.arch} clears any previously selected architecture
293 @cindex @code{.arch_extension} directive, AArch64
294 @item .arch_extension @var{name}
295 Add or remove an architecture extension to the target architecture. Valid
296 values for @var{name} are the same as those accepted as architectural
297 extensions by the @option{-mcpu} commandline option.
299 @code{.arch_extension} may be used multiple times to add or remove extensions
300 incrementally to the architecture being compiled for.
302 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
304 @cindex @code{.bss} directive, AArch64
306 This directive switches to the @code{.bss} section.
308 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
310 @cindex @code{.cpu} directive, AArch64
311 @item .cpu @var{name}
312 Set the target processor. Valid values for @var{name} are the same as
313 those accepted by the @option{-mcpu=} command line option.
315 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
317 @cindex @code{.dword} directive, AArch64
318 @item .dword @var{expressions}
319 The @code{.dword} directive produces 64 bit values.
321 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
323 @cindex @code{.even} directive, AArch64
325 The @code{.even} directive aligns the output on the next even byte
328 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
329 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
330 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
331 @c IIIIIIIIIIIIIIIIIIIIIIIIII
333 @cindex @code{.inst} directive, AArch64
334 @item .inst @var{expressions}
335 Inserts the expressions into the output as if they were instructions,
338 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
339 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
340 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
342 @cindex @code{.ltorg} directive, AArch64
344 This directive causes the current contents of the literal pool to be
345 dumped into the current section (which is assumed to be the .text
346 section) at the current location (aligned to a word boundary).
347 GAS maintains a separate literal pool for each section and each
348 sub-section. The @code{.ltorg} directive will only affect the literal
349 pool of the current section and sub-section. At the end of assembly
350 all remaining, un-empty literal pools will automatically be dumped.
352 Note - older versions of GAS would dump the current literal
353 pool any time a section change occurred. This is no longer done, since
354 it prevents accurate control of the placement of literal pools.
356 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
358 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
359 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
361 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
363 @cindex @code{.pool} directive, AArch64
365 This is a synonym for .ltorg.
367 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
368 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
370 @cindex @code{.req} directive, AArch64
371 @item @var{name} .req @var{register name}
372 This creates an alias for @var{register name} called @var{name}. For
379 ip0, ip1, lr and fp are automatically defined to
380 alias to X16, X17, X30 and X29 respectively.
382 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
384 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
386 @cindex @code{.tlsdescadd} directive, AArch64
387 @item @code{.tlsdescadd}
388 Emits a TLSDESC_ADD reloc on the next instruction.
390 @cindex @code{.tlsdesccall} directive, AArch64
391 @item @code{.tlsdesccall}
392 Emits a TLSDESC_CALL reloc on the next instruction.
394 @cindex @code{.tlsdescldr} directive, AArch64
395 @item @code{.tlsdescldr}
396 Emits a TLSDESC_LDR reloc on the next instruction.
398 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
400 @cindex @code{.unreq} directive, AArch64
401 @item .unreq @var{alias-name}
402 This undefines a register alias which was previously defined using the
403 @code{req} directive. For example:
410 An error occurs if the name is undefined. Note - this pseudo op can
411 be used to delete builtin in register name aliases (eg 'w0'). This
412 should only be done if it is really necessary.
414 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
416 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
417 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
419 @cindex @code{.xword} directive, AArch64
420 @item .xword @var{expressions}
421 The @code{.xword} directive produces 64 bit values. This is the same
422 as the @code{.dword} directive.
424 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
425 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
429 @node AArch64 Opcodes
432 @cindex AArch64 opcodes
433 @cindex opcodes for AArch64
434 GAS implements all the standard AArch64 opcodes. It also
435 implements several pseudo opcodes, including several synthetic load
440 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
443 ldr <register> , =<expression>
446 The constant expression will be placed into the nearest literal pool (if it not
447 already there) and a PC-relative LDR instruction will be generated.
451 For more information on the AArch64 instruction set and assembly language
452 notation, see @samp{ARMv8 Instruction Set Overview} available at
453 @uref{http://infocenter.arm.com}.
456 @node AArch64 Mapping Symbols
457 @section Mapping Symbols
459 The AArch64 ELF specification requires that special symbols be inserted
460 into object files to mark certain features:
466 At the start of a region of code containing AArch64 instructions.
470 At the start of a region of data.