1 @c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
21 * AArch64 Options:: Options
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @code{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @code{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
53 * AArch64-Chars:: Special Characters
54 * AArch64-Regs:: Register Names
55 * AArch64-Relocations:: Relocations
59 @subsection Special Characters
61 @cindex line comment character, AArch64
62 @cindex AArch64 line comment character
63 The presence of a @samp{//} on a line indicates the start of a comment
64 that extends to the end of the current line. If a @samp{#} appears as
65 the first character of a line, the whole line is treated as a comment.
67 @cindex line separator, AArch64
68 @cindex statement separator, AArch64
69 @cindex AArch64 line separator
70 The @samp{;} character can be used instead of a newline to separate
73 @cindex immediate character, AArch64
74 @cindex AArch64 immediate character
75 The @samp{#} can be optionally used to indicate immediate operands.
78 @subsection Register Names
80 @cindex AArch64 register names
81 @cindex register names, AArch64
82 Please refer to the section @samp{4.4 Register Names} of
83 @samp{ARMv8 Instruction Set Overview}, which is available at
84 @uref{http://infocenter.arm.com}.
86 @node AArch64-Relocations
87 @subsection Relocations
89 @cindex relocations, AArch64
90 @cindex AArch64 relocations
91 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
92 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
93 by prefixing the label with @samp{#:abs_g2:} etc.
94 For example to load the 48-bit absolute address of @var{foo} into x0:
97 movz x0, #:abs_g2:foo // bits 32-47, overflow check
98 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
99 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
102 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
103 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
104 instructions can be generated by prefixing the label with
105 @samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
107 For example to use 33-bit (+/-4GB) pc-relative addressing to
108 load the address of @var{foo} into x0:
111 adrp x0, #:pg_hi21:foo
112 add x0, x0, #:lo12:foo
115 Or to load the value of @var{foo} into x0:
118 adrp x0, #:pg_hi21:foo
119 ldr x0, [x0, #:lo12:foo]
122 Note that @samp{#:pg_hi21:} is optional.
131 adrp x0, #:pg_hi21:foo
134 @node AArch64 Floating Point
135 @section Floating Point
137 @cindex floating point, AArch64 (@sc{ieee})
138 @cindex AArch64 floating point (@sc{ieee})
139 The AArch64 architecture uses @sc{ieee} floating-point numbers.
141 @node AArch64 Directives
142 @section AArch64 Machine Directives
144 @cindex machine directives, AArch64
145 @cindex AArch64 machine directives
148 @c AAAAAAAAAAAAAAAAAAAAAAAAA
149 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
151 @cindex @code{.bss} directive, AArch64
153 This directive switches to the @code{.bss} section.
155 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
156 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
157 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
158 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
159 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
160 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
161 @c IIIIIIIIIIIIIIIIIIIIIIIIII
162 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
163 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
164 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
166 @cindex @code{.ltorg} directive, AArch64
168 This directive causes the current contents of the literal pool to be
169 dumped into the current section (which is assumed to be the .text
170 section) at the current location (aligned to a word boundary).
171 @code{GAS} maintains a separate literal pool for each section and each
172 sub-section. The @code{.ltorg} directive will only affect the literal
173 pool of the current section and sub-section. At the end of assembly
174 all remaining, un-empty literal pools will automatically be dumped.
176 Note - older versions of @code{GAS} would dump the current literal
177 pool any time a section change occurred. This is no longer done, since
178 it prevents accurate control of the placement of literal pools.
180 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
182 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
183 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
185 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
187 @cindex @code{.pool} directive, AArch64
189 This is a synonym for .ltorg.
191 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
192 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
194 @cindex @code{.req} directive, AArch64
195 @item @var{name} .req @var{register name}
196 This creates an alias for @var{register name} called @var{name}. For
203 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
205 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
207 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
209 @cindex @code{.unreq} directive, AArch64
210 @item .unreq @var{alias-name}
211 This undefines a register alias which was previously defined using the
212 @code{req} directive. For example:
219 An error occurs if the name is undefined. Note - this pseudo op can
220 be used to delete builtin in register name aliases (eg 'w0'). This
221 should only be done if it is really necessary.
223 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
225 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
226 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
227 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
228 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
232 @node AArch64 Opcodes
235 @cindex AArch64 opcodes
236 @cindex opcodes for AArch64
237 @code{@value{AS}} implements all the standard AArch64 opcodes. It also
238 implements several pseudo opcodes, including several synthetic load
243 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
246 ldr <register> , =<expression>
249 The constant expression will be placed into the nearest literal pool (if it not
250 already there) and a PC-relative LDR instruction will be generated.
254 For more information on the AArch64 instruction set and assembly language
255 notation, see @samp{ARMv8 Instruction Set Overview} available at
256 @uref{http://infocenter.arm.com}.
259 @node AArch64 Mapping Symbols
260 @section Mapping Symbols
262 The AArch64 ELF specification requires that special symbols be inserted
263 into object files to mark certain features:
269 At the start of a region of code containing AArch64 instructions.
273 At the start of a region of data.