gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2019 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{cortex-a76},
  66 @code{ares},
  67 @code{exynos-m1},
  68 @code{falkor},
  69 @code{neoverse-n1},
  70 @code{neoverse-e1},
  71 @code{qdf24xx},
  72 @code{saphira},
  73 @code{thunderx},
  74 @code{vulcan},
  75 @code{xgene1}
  76 and
  77 @code{xgene2}.
  78 The special name @code{all} may be used to allow the assembler to accept
  79 instructions valid for any supported processor, including all optional
  80 extensions.
  81
  82 In addition to the basic instruction set, the assembler can be told to
  83 accept, or restrict, various extension mnemonics that extend the
  84 processor.  @xref{AArch64 Extensions}.
  85
  86 If some implementations of a particular processor can have an
  87 extension, then then those extensions are automatically enabled.
  88 Consequently, you will not normally have to specify any additional
  89 extensions.
  90
  91 @cindex @option{-march=} command-line option, AArch64
  92 @item -march=@var{architecture}[+@var{extension}@dots{}]
  93 This option specifies the target architecture.  The assembler will
  94 issue an error message if an attempt is made to assemble an
  95 instruction which will not execute on the target architecture.  The
  96 following architecture names are recognized: @code{armv8-a},
  97 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
  98 and @code{armv8.5-a}.
  99
 100 If both @option{-mcpu} and @option{-march} are specified, the
 101 assembler will use the setting for @option{-mcpu}.  If neither are
 102 specified, the assembler will default to @option{-mcpu=all}.
 103
 104 The architecture option can be extended with the same instruction set
 105 extension options as the @option{-mcpu} option.  Unlike
 106 @option{-mcpu}, extensions are not always enabled by default,
 107 @xref{AArch64 Extensions}.
 108
 109 @cindex @code{-mverbose-error} command-line option, AArch64
 110 @item -mverbose-error
 111 This option enables verbose error messages for AArch64 gas.  This option
 112 is enabled by default.
 113
 114 @cindex @code{-mno-verbose-error} command-line option, AArch64
 115 @item -mno-verbose-error
 116 This option disables verbose error messages in AArch64 gas.
 117
 118 @end table
 119 @c man end
 120
 121 @node AArch64 Extensions
 122 @section Architecture Extensions
 123
 124 The table below lists the permitted architecture extensions that are
 125 supported by the assembler and the conditions under which they are
 126 automatically enabled.
 127
 128 Multiple extensions may be specified, separated by a @code{+}.
 129 Extension mnemonics may also be removed from those the assembler
 130 accepts.  This is done by prepending @code{no} to the option that adds
 131 the extension.  Extensions that are removed must be listed after all
 132 extensions that have been added.
 133
 134 Enabling an extension that requires other extensions will
 135 automatically cause those extensions to be enabled.  Similarly,
 136 disabling an extension that is required by other extensions will
 137 automatically cause those extensions to be disabled.
 138
 139 @multitable @columnfractions .12 .17 .17 .54
 140 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 141  @tab Description
 142 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 143  @tab Enable the complex number SIMD extensions.  This implies
 144  @code{fp16} and @code{simd}.
 145 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 146  @tab Enable CRC instructions.
 147 @item @code{crypto} @tab ARMv8-A @tab No
 148  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 149 @item @code{aes} @tab ARMv8-A @tab No
 150  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 151 @item @code{sha2} @tab ARMv8-A @tab No
 152  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 153 @item @code{sha3} @tab ARMv8.2-A @tab No
 154  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 155 @item @code{sm4} @tab ARMv8.2-A @tab No
 156  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 157 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 158  @tab Enable floating-point extensions.
 159 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 160  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 161  @code{fp}.
 162 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 163  @tab Enable Limited Ordering Regions extensions.
 164 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 165  @tab Enable Large System extensions.
 166 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 167  @tab Enable Privileged Access Never support.
 168 @item @code{profile} @tab ARMv8.2-A @tab No
 169  @tab Enable statistical profiling extensions.
 170 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 171  @tab Enable the Reliability, Availability and Serviceability
 172  extension.
 173 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 174  @tab Enable the weak release consistency extension.
 175 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 176  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 177 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 178  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 179 @item @code{sve} @tab ARMv8.2-A @tab No
 180  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 181  @code{simd} and @code{compnum}.
 182 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 183  @tab Enable the Dot Product extension.  This implies @code{simd}.
 184 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 185  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 186  This implies @code{fp16}.
 187 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 188  @tab Enable the speculation barrier instruction sb.
 189 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 190  @tab Enable the Execution and Data and Prediction instructions.
 191 @item @code{rng} @tab ARMv8.5-A @tab No
 192  @tab Enable ARMv8.5-A random number instructions.
 193 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 194  @tab Enable Speculative Store Bypassing Safe state read and write.
 195 @item @code{memtag} @tab ARMv8.5-A @tab No
 196  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 197 @end multitable
 198
 199 @node AArch64 Syntax
 200 @section Syntax
 201 @menu
 202 * AArch64-Chars::                Special Characters
 203 * AArch64-Regs::                 Register Names
 204 * AArch64-Relocations::      Relocations
 205 @end menu
 206
 207 @node AArch64-Chars
 208 @subsection Special Characters
 209
 210 @cindex line comment character, AArch64
 211 @cindex AArch64 line comment character
 212 The presence of a @samp{//} on a line indicates the start of a comment
 213 that extends to the end of the current line.  If a @samp{#} appears as
 214 the first character of a line, the whole line is treated as a comment.
 215
 216 @cindex line separator, AArch64
 217 @cindex statement separator, AArch64
 218 @cindex AArch64 line separator
 219 The @samp{;} character can be used instead of a newline to separate
 220 statements.
 221
 222 @cindex immediate character, AArch64
 223 @cindex AArch64 immediate character
 224 The @samp{#} can be optionally used to indicate immediate operands.
 225
 226 @node AArch64-Regs
 227 @subsection Register Names
 228
 229 @cindex AArch64 register names
 230 @cindex register names, AArch64
 231 Please refer to the section @samp{4.4 Register Names} of
 232 @samp{ARMv8 Instruction Set Overview}, which is available at
 233 @uref{http://infocenter.arm.com}.
 234
 235 @node AArch64-Relocations
 236 @subsection Relocations
 237
 238 @cindex relocations, AArch64
 239 @cindex AArch64 relocations
 240 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 241 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 242 by prefixing the label with @samp{#:abs_g2:} etc.
 243 For example to load the 48-bit absolute address of @var{foo} into x0:
 244
 245 @smallexample
 246         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 247         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 248         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 249 @end smallexample
 250
 251 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 252 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 253 instructions can be generated by prefixing the label with
 254 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 255
 256 For example to use 33-bit (+/-4GB) pc-relative addressing to
 257 load the address of @var{foo} into x0:
 258
 259 @smallexample
 260         adrp x0, :pg_hi21:foo
 261         add  x0, x0, #:lo12:foo
 262 @end smallexample
 263
 264 Or to load the value of @var{foo} into x0:
 265
 266 @smallexample
 267         adrp x0, :pg_hi21:foo
 268         ldr  x0, [x0, #:lo12:foo]
 269 @end smallexample
 270
 271 Note that @samp{:pg_hi21:} is optional.
 272
 273 @smallexample
 274         adrp x0, foo
 275 @end smallexample
 276
 277 is equivalent to
 278
 279 @smallexample
 280         adrp x0, :pg_hi21:foo
 281 @end smallexample
 282
 283 @node AArch64 Floating Point
 284 @section Floating Point
 285
 286 @cindex floating point, AArch64 (@sc{ieee})
 287 @cindex AArch64 floating point (@sc{ieee})
 288 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 289
 290 @node AArch64 Directives
 291 @section AArch64 Machine Directives
 292
 293 @cindex machine directives, AArch64
 294 @cindex AArch64 machine directives
 295 @table @code
 296
 297 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 298
 299 @cindex @code{.arch} directive, AArch64
 300 @item .arch @var{name}
 301 Select the target architecture.  Valid values for @var{name} are the same as
 302 for the @option{-march} command-line option.
 303
 304 Specifying @code{.arch} clears any previously selected architecture
 305 extensions.
 306
 307 @cindex @code{.arch_extension} directive, AArch64
 308 @item .arch_extension @var{name}
 309 Add or remove an architecture extension to the target architecture.  Valid
 310 values for @var{name} are the same as those accepted as architectural
 311 extensions by the @option{-mcpu} command-line option.
 312
 313 @code{.arch_extension} may be used multiple times to add or remove extensions
 314 incrementally to the architecture being compiled for.
 315
 316 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 317
 318 @cindex @code{.bss} directive, AArch64
 319 @item .bss
 320 This directive switches to the @code{.bss} section.
 321
 322 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 323
 324 @cindex @code{.cpu} directive, AArch64
 325 @item .cpu @var{name}
 326 Set the target processor.  Valid values for @var{name} are the same as
 327 those accepted by the @option{-mcpu=} command-line option.
 328
 329 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 330
 331 @cindex @code{.dword} directive, AArch64
 332 @item .dword @var{expressions}
 333 The @code{.dword} directive produces 64 bit values.
 334
 335 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 336
 337 @cindex @code{.even} directive, AArch64
 338 @item .even
 339 The @code{.even} directive aligns the output on the next even byte
 340 boundary.
 341
 342 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 343 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 344 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 345 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 346
 347 @cindex @code{.inst} directive, AArch64
 348 @item .inst @var{expressions}
 349 Inserts the expressions into the output as if they were instructions,
 350 rather than data.
 351
 352 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 353 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 354 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 355
 356 @cindex @code{.ltorg} directive, AArch64
 357 @item .ltorg
 358 This directive causes the current contents of the literal pool to be
 359 dumped into the current section (which is assumed to be the .text
 360 section) at the current location (aligned to a word boundary).
 361 GAS maintains a separate literal pool for each section and each
 362 sub-section.  The @code{.ltorg} directive will only affect the literal
 363 pool of the current section and sub-section.  At the end of assembly
 364 all remaining, un-empty literal pools will automatically be dumped.
 365
 366 Note - older versions of GAS would dump the current literal
 367 pool any time a section change occurred.  This is no longer done, since
 368 it prevents accurate control of the placement of literal pools.
 369
 370 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 371
 372 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 373 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 374
 375 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 376
 377 @cindex @code{.pool} directive, AArch64
 378 @item .pool
 379 This is a synonym for .ltorg.
 380
 381 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 382 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 383
 384 @cindex @code{.req} directive, AArch64
 385 @item @var{name} .req @var{register name}
 386 This creates an alias for @var{register name} called @var{name}.  For
 387 example:
 388
 389 @smallexample
 390         foo .req w0
 391 @end smallexample
 392
 393 ip0, ip1, lr and fp are automatically defined to
 394 alias to X16, X17, X30 and X29 respectively.
 395
 396 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 397
 398 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 399
 400 @cindex @code{.tlsdescadd} directive, AArch64
 401 @item   @code{.tlsdescadd}
 402 Emits a TLSDESC_ADD reloc on the next instruction.
 403
 404 @cindex @code{.tlsdesccall} directive, AArch64
 405 @item   @code{.tlsdesccall}
 406 Emits a TLSDESC_CALL reloc on the next instruction.
 407
 408 @cindex @code{.tlsdescldr} directive, AArch64
 409 @item   @code{.tlsdescldr}
 410 Emits a TLSDESC_LDR reloc on the next instruction.
 411
 412 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 413
 414 @cindex @code{.unreq} directive, AArch64
 415 @item .unreq @var{alias-name}
 416 This undefines a register alias which was previously defined using the
 417 @code{req} directive.  For example:
 418
 419 @smallexample
 420         foo .req w0
 421         .unreq foo
 422 @end smallexample
 423
 424 An error occurs if the name is undefined.  Note - this pseudo op can
 425 be used to delete builtin in register name aliases (eg 'w0').  This
 426 should only be done if it is really necessary.
 427
 428 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 429
 430 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 431 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 432
 433 @cindex @code{.xword} directive, AArch64
 434 @item .xword @var{expressions}
 435 The @code{.xword} directive produces 64 bit values.  This is the same
 436 as the @code{.dword} directive.
 437
 438 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 439 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 440
 441 @cindex @code{.cfi_b_key_frame} directive, AArch64
 442 @item   @code{.cfi_b_key_frame}
 443 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 444 corresponding to the current frame's FDE, meaning that its return address has
 445 been signed with the B-key.  If two frames are signed with differing keys then
 446 they will not share the same CIE.  This information is intended to be used by
 447 the stack unwinder in order to properly authenticate return addresses.
 448
 449 @end table
 450
 451 @node AArch64 Opcodes
 452 @section Opcodes
 453
 454 @cindex AArch64 opcodes
 455 @cindex opcodes for AArch64
 456 GAS implements all the standard AArch64 opcodes.  It also
 457 implements several pseudo opcodes, including several synthetic load
 458 instructions.
 459
 460 @table @code
 461
 462 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 463 @item LDR =
 464 @smallexample
 465   ldr <register> , =<expression>
 466 @end smallexample
 467
 468 The constant expression will be placed into the nearest literal pool (if it not
 469 already there) and a PC-relative LDR instruction will be generated.
 470
 471 @end table
 472
 473 For more information on the AArch64 instruction set and assembly language
 474 notation, see @samp{ARMv8 Instruction Set Overview} available at
 475 @uref{http://infocenter.arm.com}.
 476
 477
 478 @node AArch64 Mapping Symbols
 479 @section Mapping Symbols
 480
 481 The AArch64 ELF specification requires that special symbols be inserted
 482 into object files to mark certain features:
 483
 484 @table @code
 485
 486 @cindex @code{$x}
 487 @item $x
 488 At the start of a region of code containing AArch64 instructions.
 489
 490 @cindex @code{$d}
 491 @item $d
 492 At the start of a region of data.
 493
 494 @end table