1 @c Copyright (C) 2009-2016 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
69 The special name @code{all} may be used to allow the assembler to accept
70 instructions valid for any supported processor, including all optional
73 In addition to the basic instruction set, the assembler can be told to
74 accept, or restrict, various extension mnemonics that extend the
75 processor. @xref{AArch64 Extensions}.
77 If some implementations of a particular processor can have an
78 extension, then then those extensions are automatically enabled.
79 Consequently, you will not normally have to specify any additional
82 @cindex @option{-march=} command line option, AArch64
83 @item -march=@var{architecture}[+@var{extension}@dots{}]
84 This option specifies the target architecture. The assembler will
85 issue an error message if an attempt is made to assemble an
86 instruction which will not execute on the target architecture. The
87 following architecture names are recognized: @code{armv8-a},
88 @code{armv8.1-a} and @code{armv8.2-a}.
90 If both @option{-mcpu} and @option{-march} are specified, the
91 assembler will use the setting for @option{-mcpu}. If neither are
92 specified, the assembler will default to @option{-mcpu=all}.
94 The architecture option can be extended with the same instruction set
95 extension options as the @option{-mcpu} option. Unlike
96 @option{-mcpu}, extensions are not always enabled by default,
97 @xref{AArch64 Extensions}.
99 @cindex @code{-mverbose-error} command line option, AArch64
100 @item -mverbose-error
101 This option enables verbose error messages for AArch64 gas. This option
102 is enabled by default.
104 @cindex @code{-mno-verbose-error} command line option, AArch64
105 @item -mno-verbose-error
106 This option disables verbose error messages in AArch64 gas.
111 @node AArch64 Extensions
112 @section Architecture Extensions
114 The table below lists the permitted architecture extensions that are
115 supported by the assembler and the conditions under which they are
116 automatically enabled.
118 Multiple extensions may be specified, separated by a @code{+}.
119 Extension mnemonics may also be removed from those the assembler
120 accepts. This is done by prepending @code{no} to the option that adds
121 the extension. Extensions that are removed must be listed after all
122 extensions that have been added.
124 Enabling an extension that requires other extensions will
125 automatically cause those extensions to be enabled. Similarly,
126 disabling an extension that is required by other extensions will
127 automatically cause those extensions to be disabled.
129 @multitable @columnfractions .12 .17 .17 .54
130 @headitem Extension @tab Minimum Architecture @tab Enabled by default
132 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
133 @tab Enable CRC instructions.
134 @item @code{crypto} @tab ARMv8-A @tab No
135 @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
136 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
137 @tab Enable floating-point extensions.
138 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
139 @tab Enable ARMv8.2 16-bit floating-point support. This implies
141 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
142 @tab Enable Limited Ordering Regions extensions.
143 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
144 @tab Enable Large System extensions.
145 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
146 @tab Enable Privileged Access Never support.
147 @item @code{profile} @tab ARMv8.2-A @tab No
148 @tab Enable statistical profiling extensions.
149 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
150 @tab Enable the Reliability, Availability and Serviceability
152 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
153 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
154 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
155 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
161 * AArch64-Chars:: Special Characters
162 * AArch64-Regs:: Register Names
163 * AArch64-Relocations:: Relocations
167 @subsection Special Characters
169 @cindex line comment character, AArch64
170 @cindex AArch64 line comment character
171 The presence of a @samp{//} on a line indicates the start of a comment
172 that extends to the end of the current line. If a @samp{#} appears as
173 the first character of a line, the whole line is treated as a comment.
175 @cindex line separator, AArch64
176 @cindex statement separator, AArch64
177 @cindex AArch64 line separator
178 The @samp{;} character can be used instead of a newline to separate
181 @cindex immediate character, AArch64
182 @cindex AArch64 immediate character
183 The @samp{#} can be optionally used to indicate immediate operands.
186 @subsection Register Names
188 @cindex AArch64 register names
189 @cindex register names, AArch64
190 Please refer to the section @samp{4.4 Register Names} of
191 @samp{ARMv8 Instruction Set Overview}, which is available at
192 @uref{http://infocenter.arm.com}.
194 @node AArch64-Relocations
195 @subsection Relocations
197 @cindex relocations, AArch64
198 @cindex AArch64 relocations
199 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
200 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
201 by prefixing the label with @samp{#:abs_g2:} etc.
202 For example to load the 48-bit absolute address of @var{foo} into x0:
205 movz x0, #:abs_g2:foo // bits 32-47, overflow check
206 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
207 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
210 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
211 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
212 instructions can be generated by prefixing the label with
213 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
215 For example to use 33-bit (+/-4GB) pc-relative addressing to
216 load the address of @var{foo} into x0:
219 adrp x0, :pg_hi21:foo
220 add x0, x0, #:lo12:foo
223 Or to load the value of @var{foo} into x0:
226 adrp x0, :pg_hi21:foo
227 ldr x0, [x0, #:lo12:foo]
230 Note that @samp{:pg_hi21:} is optional.
239 adrp x0, :pg_hi21:foo
242 @node AArch64 Floating Point
243 @section Floating Point
245 @cindex floating point, AArch64 (@sc{ieee})
246 @cindex AArch64 floating point (@sc{ieee})
247 The AArch64 architecture uses @sc{ieee} floating-point numbers.
249 @node AArch64 Directives
250 @section AArch64 Machine Directives
252 @cindex machine directives, AArch64
253 @cindex AArch64 machine directives
256 @c AAAAAAAAAAAAAAAAAAAAAAAAA
258 @cindex @code{.arch} directive, AArch64
259 @item .arch @var{name}
260 Select the target architecture. Valid values for @var{name} are the same as
261 for the @option{-march} commandline option.
263 Specifying @code{.arch} clears any previously selected architecture
266 @cindex @code{.arch_extension} directive, AArch64
267 @item .arch_extension @var{name}
268 Add or remove an architecture extension to the target architecture. Valid
269 values for @var{name} are the same as those accepted as architectural
270 extensions by the @option{-mcpu} commandline option.
272 @code{.arch_extension} may be used multiple times to add or remove extensions
273 incrementally to the architecture being compiled for.
275 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
277 @cindex @code{.bss} directive, AArch64
279 This directive switches to the @code{.bss} section.
281 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
283 @cindex @code{.cpu} directive, AArch64
284 @item .cpu @var{name}
285 Set the target processor. Valid values for @var{name} are the same as
286 those accepted by the @option{-mcpu=} command line option.
288 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
290 @cindex @code{.dword} directive, AArch64
291 @item .dword @var{expressions}
292 The @code{.dword} directive produces 64 bit values.
294 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
296 @cindex @code{.even} directive, AArch64
298 The @code{.even} directive aligns the output on the next even byte
301 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
302 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
303 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
304 @c IIIIIIIIIIIIIIIIIIIIIIIIII
306 @cindex @code{.inst} directive, AArch64
307 @item .inst @var{expressions}
308 Inserts the expressions into the output as if they were instructions,
311 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
312 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
313 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
315 @cindex @code{.ltorg} directive, AArch64
317 This directive causes the current contents of the literal pool to be
318 dumped into the current section (which is assumed to be the .text
319 section) at the current location (aligned to a word boundary).
320 GAS maintains a separate literal pool for each section and each
321 sub-section. The @code{.ltorg} directive will only affect the literal
322 pool of the current section and sub-section. At the end of assembly
323 all remaining, un-empty literal pools will automatically be dumped.
325 Note - older versions of GAS would dump the current literal
326 pool any time a section change occurred. This is no longer done, since
327 it prevents accurate control of the placement of literal pools.
329 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
331 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
332 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
334 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
336 @cindex @code{.pool} directive, AArch64
338 This is a synonym for .ltorg.
340 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
341 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
343 @cindex @code{.req} directive, AArch64
344 @item @var{name} .req @var{register name}
345 This creates an alias for @var{register name} called @var{name}. For
352 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
354 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
356 @cindex @code{.tlsdescadd} directive, AArch64
357 @item @code{.tlsdescadd}
358 Emits a TLSDESC_ADD reloc on the next instruction.
360 @cindex @code{.tlsdesccall} directive, AArch64
361 @item @code{.tlsdesccall}
362 Emits a TLSDESC_CALL reloc on the next instruction.
364 @cindex @code{.tlsdescldr} directive, AArch64
365 @item @code{.tlsdescldr}
366 Emits a TLSDESC_LDR reloc on the next instruction.
368 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
370 @cindex @code{.unreq} directive, AArch64
371 @item .unreq @var{alias-name}
372 This undefines a register alias which was previously defined using the
373 @code{req} directive. For example:
380 An error occurs if the name is undefined. Note - this pseudo op can
381 be used to delete builtin in register name aliases (eg 'w0'). This
382 should only be done if it is really necessary.
384 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
386 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
387 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
389 @cindex @code{.xword} directive, AArch64
390 @item .xword @var{expressions}
391 The @code{.xword} directive produces 64 bit values. This is the same
392 as the @code{.dword} directive.
394 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
395 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
399 @node AArch64 Opcodes
402 @cindex AArch64 opcodes
403 @cindex opcodes for AArch64
404 GAS implements all the standard AArch64 opcodes. It also
405 implements several pseudo opcodes, including several synthetic load
410 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
413 ldr <register> , =<expression>
416 The constant expression will be placed into the nearest literal pool (if it not
417 already there) and a PC-relative LDR instruction will be generated.
421 For more information on the AArch64 instruction set and assembly language
422 notation, see @samp{ARMv8 Instruction Set Overview} available at
423 @uref{http://infocenter.arm.com}.
426 @node AArch64 Mapping Symbols
427 @section Mapping Symbols
429 The AArch64 ELF specification requires that special symbols be inserted
430 into object files to mark certain features:
436 At the start of a region of code containing AArch64 instructions.
440 At the start of a region of data.