1 @c Copyright (C) 2009-2019 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command-line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command-line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command-line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command-line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
76 The special name @code{all} may be used to allow the assembler to accept
77 instructions valid for any supported processor, including all optional
80 In addition to the basic instruction set, the assembler can be told to
81 accept, or restrict, various extension mnemonics that extend the
82 processor. @xref{AArch64 Extensions}.
84 If some implementations of a particular processor can have an
85 extension, then then those extensions are automatically enabled.
86 Consequently, you will not normally have to specify any additional
89 @cindex @option{-march=} command-line option, AArch64
90 @item -march=@var{architecture}[+@var{extension}@dots{}]
91 This option specifies the target architecture. The assembler will
92 issue an error message if an attempt is made to assemble an
93 instruction which will not execute on the target architecture. The
94 following architecture names are recognized: @code{armv8-a},
95 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
98 If both @option{-mcpu} and @option{-march} are specified, the
99 assembler will use the setting for @option{-mcpu}. If neither are
100 specified, the assembler will default to @option{-mcpu=all}.
102 The architecture option can be extended with the same instruction set
103 extension options as the @option{-mcpu} option. Unlike
104 @option{-mcpu}, extensions are not always enabled by default,
105 @xref{AArch64 Extensions}.
107 @cindex @code{-mverbose-error} command-line option, AArch64
108 @item -mverbose-error
109 This option enables verbose error messages for AArch64 gas. This option
110 is enabled by default.
112 @cindex @code{-mno-verbose-error} command-line option, AArch64
113 @item -mno-verbose-error
114 This option disables verbose error messages in AArch64 gas.
119 @node AArch64 Extensions
120 @section Architecture Extensions
122 The table below lists the permitted architecture extensions that are
123 supported by the assembler and the conditions under which they are
124 automatically enabled.
126 Multiple extensions may be specified, separated by a @code{+}.
127 Extension mnemonics may also be removed from those the assembler
128 accepts. This is done by prepending @code{no} to the option that adds
129 the extension. Extensions that are removed must be listed after all
130 extensions that have been added.
132 Enabling an extension that requires other extensions will
133 automatically cause those extensions to be enabled. Similarly,
134 disabling an extension that is required by other extensions will
135 automatically cause those extensions to be disabled.
137 @multitable @columnfractions .12 .17 .17 .54
138 @headitem Extension @tab Minimum Architecture @tab Enabled by default
140 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
141 @tab Enable the complex number SIMD extensions. This implies
142 @code{fp16} and @code{simd}.
143 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
144 @tab Enable CRC instructions.
145 @item @code{crypto} @tab ARMv8-A @tab No
146 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
147 @item @code{aes} @tab ARMv8-A @tab No
148 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
149 @item @code{sha2} @tab ARMv8-A @tab No
150 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
151 @item @code{sha3} @tab ARMv8.2-A @tab No
152 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
153 @item @code{sm4} @tab ARMv8.2-A @tab No
154 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
155 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
156 @tab Enable floating-point extensions.
157 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
158 @tab Enable ARMv8.2 16-bit floating-point support. This implies
160 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
161 @tab Enable Limited Ordering Regions extensions.
162 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
163 @tab Enable Large System extensions.
164 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
165 @tab Enable Privileged Access Never support.
166 @item @code{profile} @tab ARMv8.2-A @tab No
167 @tab Enable statistical profiling extensions.
168 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
169 @tab Enable the Reliability, Availability and Serviceability
171 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
172 @tab Enable the weak release consistency extension.
173 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
174 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
175 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
176 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
177 @item @code{sve} @tab ARMv8.2-A @tab No
178 @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
179 @code{simd} and @code{compnum}.
180 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
181 @tab Enable the Dot Product extension. This implies @code{simd}.
182 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
183 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
184 This implies @code{fp16}.
185 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
186 @tab Enable the speculation barrier instruction sb.
187 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
188 @tab Enable the Execution and Data and Prediction instructions.
189 @item @code{rng} @tab ARMv8.5-A @tab No
190 @tab Enable ARMv8.5-A random number instructions.
191 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
192 @tab Enable Speculative Store Bypassing Safe state read and write.
193 @item @code{memtag} @tab ARMv8.5-A @tab No
194 @tab Enable ARMv8.5-A Memory Tagging Extensions.
200 * AArch64-Chars:: Special Characters
201 * AArch64-Regs:: Register Names
202 * AArch64-Relocations:: Relocations
206 @subsection Special Characters
208 @cindex line comment character, AArch64
209 @cindex AArch64 line comment character
210 The presence of a @samp{//} on a line indicates the start of a comment
211 that extends to the end of the current line. If a @samp{#} appears as
212 the first character of a line, the whole line is treated as a comment.
214 @cindex line separator, AArch64
215 @cindex statement separator, AArch64
216 @cindex AArch64 line separator
217 The @samp{;} character can be used instead of a newline to separate
220 @cindex immediate character, AArch64
221 @cindex AArch64 immediate character
222 The @samp{#} can be optionally used to indicate immediate operands.
225 @subsection Register Names
227 @cindex AArch64 register names
228 @cindex register names, AArch64
229 Please refer to the section @samp{4.4 Register Names} of
230 @samp{ARMv8 Instruction Set Overview}, which is available at
231 @uref{http://infocenter.arm.com}.
233 @node AArch64-Relocations
234 @subsection Relocations
236 @cindex relocations, AArch64
237 @cindex AArch64 relocations
238 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
239 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
240 by prefixing the label with @samp{#:abs_g2:} etc.
241 For example to load the 48-bit absolute address of @var{foo} into x0:
244 movz x0, #:abs_g2:foo // bits 32-47, overflow check
245 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
246 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
249 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
250 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
251 instructions can be generated by prefixing the label with
252 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
254 For example to use 33-bit (+/-4GB) pc-relative addressing to
255 load the address of @var{foo} into x0:
258 adrp x0, :pg_hi21:foo
259 add x0, x0, #:lo12:foo
262 Or to load the value of @var{foo} into x0:
265 adrp x0, :pg_hi21:foo
266 ldr x0, [x0, #:lo12:foo]
269 Note that @samp{:pg_hi21:} is optional.
278 adrp x0, :pg_hi21:foo
281 @node AArch64 Floating Point
282 @section Floating Point
284 @cindex floating point, AArch64 (@sc{ieee})
285 @cindex AArch64 floating point (@sc{ieee})
286 The AArch64 architecture uses @sc{ieee} floating-point numbers.
288 @node AArch64 Directives
289 @section AArch64 Machine Directives
291 @cindex machine directives, AArch64
292 @cindex AArch64 machine directives
295 @c AAAAAAAAAAAAAAAAAAAAAAAAA
297 @cindex @code{.arch} directive, AArch64
298 @item .arch @var{name}
299 Select the target architecture. Valid values for @var{name} are the same as
300 for the @option{-march} command-line option.
302 Specifying @code{.arch} clears any previously selected architecture
305 @cindex @code{.arch_extension} directive, AArch64
306 @item .arch_extension @var{name}
307 Add or remove an architecture extension to the target architecture. Valid
308 values for @var{name} are the same as those accepted as architectural
309 extensions by the @option{-mcpu} command-line option.
311 @code{.arch_extension} may be used multiple times to add or remove extensions
312 incrementally to the architecture being compiled for.
314 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
316 @cindex @code{.bss} directive, AArch64
318 This directive switches to the @code{.bss} section.
320 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
322 @cindex @code{.cpu} directive, AArch64
323 @item .cpu @var{name}
324 Set the target processor. Valid values for @var{name} are the same as
325 those accepted by the @option{-mcpu=} command-line option.
327 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
329 @cindex @code{.dword} directive, AArch64
330 @item .dword @var{expressions}
331 The @code{.dword} directive produces 64 bit values.
333 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
335 @cindex @code{.even} directive, AArch64
337 The @code{.even} directive aligns the output on the next even byte
340 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
341 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
342 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
343 @c IIIIIIIIIIIIIIIIIIIIIIIIII
345 @cindex @code{.inst} directive, AArch64
346 @item .inst @var{expressions}
347 Inserts the expressions into the output as if they were instructions,
350 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
351 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
352 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
354 @cindex @code{.ltorg} directive, AArch64
356 This directive causes the current contents of the literal pool to be
357 dumped into the current section (which is assumed to be the .text
358 section) at the current location (aligned to a word boundary).
359 GAS maintains a separate literal pool for each section and each
360 sub-section. The @code{.ltorg} directive will only affect the literal
361 pool of the current section and sub-section. At the end of assembly
362 all remaining, un-empty literal pools will automatically be dumped.
364 Note - older versions of GAS would dump the current literal
365 pool any time a section change occurred. This is no longer done, since
366 it prevents accurate control of the placement of literal pools.
368 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
370 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
371 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
373 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
375 @cindex @code{.pool} directive, AArch64
377 This is a synonym for .ltorg.
379 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
380 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
382 @cindex @code{.req} directive, AArch64
383 @item @var{name} .req @var{register name}
384 This creates an alias for @var{register name} called @var{name}. For
391 ip0, ip1, lr and fp are automatically defined to
392 alias to X16, X17, X30 and X29 respectively.
394 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
396 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
398 @cindex @code{.tlsdescadd} directive, AArch64
399 @item @code{.tlsdescadd}
400 Emits a TLSDESC_ADD reloc on the next instruction.
402 @cindex @code{.tlsdesccall} directive, AArch64
403 @item @code{.tlsdesccall}
404 Emits a TLSDESC_CALL reloc on the next instruction.
406 @cindex @code{.tlsdescldr} directive, AArch64
407 @item @code{.tlsdescldr}
408 Emits a TLSDESC_LDR reloc on the next instruction.
410 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
412 @cindex @code{.unreq} directive, AArch64
413 @item .unreq @var{alias-name}
414 This undefines a register alias which was previously defined using the
415 @code{req} directive. For example:
422 An error occurs if the name is undefined. Note - this pseudo op can
423 be used to delete builtin in register name aliases (eg 'w0'). This
424 should only be done if it is really necessary.
426 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
428 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
429 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
431 @cindex @code{.xword} directive, AArch64
432 @item .xword @var{expressions}
433 The @code{.xword} directive produces 64 bit values. This is the same
434 as the @code{.dword} directive.
436 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
437 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
439 @cindex @code{.cfi_b_key_frame} directive, AArch64
440 @item @code{.cfi_b_key_frame}
441 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
442 corresponding to the current frame's FDE, meaning that its return address has
443 been signed with the B-key. If two frames are signed with differing keys then
444 they will not share the same CIE. This information is intended to be used by
445 the stack unwinder in order to properly authenticate return addresses.
449 @node AArch64 Opcodes
452 @cindex AArch64 opcodes
453 @cindex opcodes for AArch64
454 GAS implements all the standard AArch64 opcodes. It also
455 implements several pseudo opcodes, including several synthetic load
460 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
463 ldr <register> , =<expression>
466 The constant expression will be placed into the nearest literal pool (if it not
467 already there) and a PC-relative LDR instruction will be generated.
471 For more information on the AArch64 instruction set and assembly language
472 notation, see @samp{ARMv8 Instruction Set Overview} available at
473 @uref{http://infocenter.arm.com}.
476 @node AArch64 Mapping Symbols
477 @section Mapping Symbols
479 The AArch64 ELF specification requires that special symbols be inserted
480 into object files to mark certain features:
486 At the start of a region of code containing AArch64 instructions.
490 At the start of a region of data.