1 @c Copyright (C) 2009-2019 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command-line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command-line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command-line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command-line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
83 The special name @code{all} may be used to allow the assembler to accept
84 instructions valid for any supported processor, including all optional
87 In addition to the basic instruction set, the assembler can be told to
88 accept, or restrict, various extension mnemonics that extend the
89 processor. @xref{AArch64 Extensions}.
91 If some implementations of a particular processor can have an
92 extension, then then those extensions are automatically enabled.
93 Consequently, you will not normally have to specify any additional
96 @cindex @option{-march=} command-line option, AArch64
97 @item -march=@var{architecture}[+@var{extension}@dots{}]
98 This option specifies the target architecture. The assembler will
99 issue an error message if an attempt is made to assemble an
100 instruction which will not execute on the target architecture. The
101 following architecture names are recognized: @code{armv8-a},
102 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
103 @code{armv8.5-a}, and @code{armv8.6-a}.
105 If both @option{-mcpu} and @option{-march} are specified, the
106 assembler will use the setting for @option{-mcpu}. If neither are
107 specified, the assembler will default to @option{-mcpu=all}.
109 The architecture option can be extended with the same instruction set
110 extension options as the @option{-mcpu} option. Unlike
111 @option{-mcpu}, extensions are not always enabled by default,
112 @xref{AArch64 Extensions}.
114 @cindex @code{-mverbose-error} command-line option, AArch64
115 @item -mverbose-error
116 This option enables verbose error messages for AArch64 gas. This option
117 is enabled by default.
119 @cindex @code{-mno-verbose-error} command-line option, AArch64
120 @item -mno-verbose-error
121 This option disables verbose error messages in AArch64 gas.
126 @node AArch64 Extensions
127 @section Architecture Extensions
129 The table below lists the permitted architecture extensions that are
130 supported by the assembler and the conditions under which they are
131 automatically enabled.
133 Multiple extensions may be specified, separated by a @code{+}.
134 Extension mnemonics may also be removed from those the assembler
135 accepts. This is done by prepending @code{no} to the option that adds
136 the extension. Extensions that are removed must be listed after all
137 extensions that have been added.
139 Enabling an extension that requires other extensions will
140 automatically cause those extensions to be enabled. Similarly,
141 disabling an extension that is required by other extensions will
142 automatically cause those extensions to be disabled.
144 @multitable @columnfractions .12 .17 .17 .54
145 @headitem Extension @tab Minimum Architecture @tab Enabled by default
147 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
148 @tab Enable the complex number SIMD extensions. This implies
149 @code{fp16} and @code{simd}.
150 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
151 @tab Enable CRC instructions.
152 @item @code{crypto} @tab ARMv8-A @tab No
153 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
154 @item @code{aes} @tab ARMv8-A @tab No
155 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
156 @item @code{sha2} @tab ARMv8-A @tab No
157 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
158 @item @code{sha3} @tab ARMv8.2-A @tab No
159 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
160 @item @code{sm4} @tab ARMv8.2-A @tab No
161 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
162 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
163 @tab Enable floating-point extensions.
164 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
165 @tab Enable ARMv8.2 16-bit floating-point support. This implies
167 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
168 @tab Enable Limited Ordering Regions extensions.
169 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
170 @tab Enable Large System extensions.
171 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
172 @tab Enable Privileged Access Never support.
173 @item @code{profile} @tab ARMv8.2-A @tab No
174 @tab Enable statistical profiling extensions.
175 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
176 @tab Enable the Reliability, Availability and Serviceability
178 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
179 @tab Enable the weak release consistency extension.
180 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
181 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
182 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
183 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
184 @item @code{sve} @tab ARMv8.2-A @tab No
185 @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
186 @code{simd} and @code{compnum}.
187 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
188 @tab Enable the Dot Product extension. This implies @code{simd}.
189 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
190 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
191 This implies @code{fp16}.
192 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
193 @tab Enable the speculation barrier instruction sb.
194 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
195 @tab Enable the Execution and Data and Prediction instructions.
196 @item @code{rng} @tab ARMv8.5-A @tab No
197 @tab Enable ARMv8.5-A random number instructions.
198 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
199 @tab Enable Speculative Store Bypassing Safe state read and write.
200 @item @code{memtag} @tab ARMv8.5-A @tab No
201 @tab Enable ARMv8.5-A Memory Tagging Extensions.
202 @item @code{tme} @tab ARMv8-A @tab No
203 @tab Enable Transactional Memory Extensions.
204 @item @code{sve2} @tab ARMv8-A @tab No
205 @tab Enable the SVE2 Extension.
206 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
207 @tab Enable SVE2 BITPERM Extension.
208 @item @code{sve2-sm4} @tab ARMv8-A @tab No
209 @tab Enable SVE2 SM4 Extension.
210 @item @code{sve2-aes} @tab ARMv8-A @tab No
211 @tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the
212 @code{pmullt} and @code{pmullb} instructions.
213 @item @code{sve2-sha3} @tab ARMv8-A @tab No
214 @tab Enable SVE2 SHA3 Extension.
220 * AArch64-Chars:: Special Characters
221 * AArch64-Regs:: Register Names
222 * AArch64-Relocations:: Relocations
226 @subsection Special Characters
228 @cindex line comment character, AArch64
229 @cindex AArch64 line comment character
230 The presence of a @samp{//} on a line indicates the start of a comment
231 that extends to the end of the current line. If a @samp{#} appears as
232 the first character of a line, the whole line is treated as a comment.
234 @cindex line separator, AArch64
235 @cindex statement separator, AArch64
236 @cindex AArch64 line separator
237 The @samp{;} character can be used instead of a newline to separate
240 @cindex immediate character, AArch64
241 @cindex AArch64 immediate character
242 The @samp{#} can be optionally used to indicate immediate operands.
245 @subsection Register Names
247 @cindex AArch64 register names
248 @cindex register names, AArch64
249 Please refer to the section @samp{4.4 Register Names} of
250 @samp{ARMv8 Instruction Set Overview}, which is available at
251 @uref{http://infocenter.arm.com}.
253 @node AArch64-Relocations
254 @subsection Relocations
256 @cindex relocations, AArch64
257 @cindex AArch64 relocations
258 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
259 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
260 by prefixing the label with @samp{#:abs_g2:} etc.
261 For example to load the 48-bit absolute address of @var{foo} into x0:
264 movz x0, #:abs_g2:foo // bits 32-47, overflow check
265 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
266 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
269 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
270 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
271 instructions can be generated by prefixing the label with
272 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
274 For example to use 33-bit (+/-4GB) pc-relative addressing to
275 load the address of @var{foo} into x0:
278 adrp x0, :pg_hi21:foo
279 add x0, x0, #:lo12:foo
282 Or to load the value of @var{foo} into x0:
285 adrp x0, :pg_hi21:foo
286 ldr x0, [x0, #:lo12:foo]
289 Note that @samp{:pg_hi21:} is optional.
298 adrp x0, :pg_hi21:foo
301 @node AArch64 Floating Point
302 @section Floating Point
304 @cindex floating point, AArch64 (@sc{ieee})
305 @cindex AArch64 floating point (@sc{ieee})
306 The AArch64 architecture uses @sc{ieee} floating-point numbers.
308 @node AArch64 Directives
309 @section AArch64 Machine Directives
311 @cindex machine directives, AArch64
312 @cindex AArch64 machine directives
315 @c AAAAAAAAAAAAAAAAAAAAAAAAA
317 @cindex @code{.arch} directive, AArch64
318 @item .arch @var{name}
319 Select the target architecture. Valid values for @var{name} are the same as
320 for the @option{-march} command-line option.
322 Specifying @code{.arch} clears any previously selected architecture
325 @cindex @code{.arch_extension} directive, AArch64
326 @item .arch_extension @var{name}
327 Add or remove an architecture extension to the target architecture. Valid
328 values for @var{name} are the same as those accepted as architectural
329 extensions by the @option{-mcpu} command-line option.
331 @code{.arch_extension} may be used multiple times to add or remove extensions
332 incrementally to the architecture being compiled for.
334 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
336 @cindex @code{.bss} directive, AArch64
338 This directive switches to the @code{.bss} section.
340 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
342 @cindex @code{.cpu} directive, AArch64
343 @item .cpu @var{name}
344 Set the target processor. Valid values for @var{name} are the same as
345 those accepted by the @option{-mcpu=} command-line option.
347 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
349 @cindex @code{.dword} directive, AArch64
350 @item .dword @var{expressions}
351 The @code{.dword} directive produces 64 bit values.
353 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
355 @cindex @code{.even} directive, AArch64
357 The @code{.even} directive aligns the output on the next even byte
360 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
362 @cindex @code{.float16} directive, AArch64
363 @item .float16 @var{value [,...,value_n]}
364 Place the half precision floating point representation of one or more
365 floating-point values into the current section.
366 The format used to encode the floating point values is always the
367 IEEE 754-2008 half precision floating point format.
369 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
370 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
371 @c IIIIIIIIIIIIIIIIIIIIIIIIII
373 @cindex @code{.inst} directive, AArch64
374 @item .inst @var{expressions}
375 Inserts the expressions into the output as if they were instructions,
378 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
379 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
380 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
382 @cindex @code{.ltorg} directive, AArch64
384 This directive causes the current contents of the literal pool to be
385 dumped into the current section (which is assumed to be the .text
386 section) at the current location (aligned to a word boundary).
387 GAS maintains a separate literal pool for each section and each
388 sub-section. The @code{.ltorg} directive will only affect the literal
389 pool of the current section and sub-section. At the end of assembly
390 all remaining, un-empty literal pools will automatically be dumped.
392 Note - older versions of GAS would dump the current literal
393 pool any time a section change occurred. This is no longer done, since
394 it prevents accurate control of the placement of literal pools.
396 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
398 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
399 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
401 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
403 @cindex @code{.pool} directive, AArch64
405 This is a synonym for .ltorg.
407 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
408 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
410 @cindex @code{.req} directive, AArch64
411 @item @var{name} .req @var{register name}
412 This creates an alias for @var{register name} called @var{name}. For
419 ip0, ip1, lr and fp are automatically defined to
420 alias to X16, X17, X30 and X29 respectively.
422 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
424 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
426 @cindex @code{.tlsdescadd} directive, AArch64
427 @item @code{.tlsdescadd}
428 Emits a TLSDESC_ADD reloc on the next instruction.
430 @cindex @code{.tlsdesccall} directive, AArch64
431 @item @code{.tlsdesccall}
432 Emits a TLSDESC_CALL reloc on the next instruction.
434 @cindex @code{.tlsdescldr} directive, AArch64
435 @item @code{.tlsdescldr}
436 Emits a TLSDESC_LDR reloc on the next instruction.
438 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
440 @cindex @code{.unreq} directive, AArch64
441 @item .unreq @var{alias-name}
442 This undefines a register alias which was previously defined using the
443 @code{req} directive. For example:
450 An error occurs if the name is undefined. Note - this pseudo op can
451 be used to delete builtin in register name aliases (eg 'w0'). This
452 should only be done if it is really necessary.
454 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
456 @cindex @code{.variant_pcs} directive, AArch64
457 @item .variant_pcs @var{symbol}
458 This directive marks @var{symbol} referencing a function that may
459 follow a variant procedure call standard with different register
460 usage convention from the base procedure call standard.
462 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
463 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
465 @cindex @code{.xword} directive, AArch64
466 @item .xword @var{expressions}
467 The @code{.xword} directive produces 64 bit values. This is the same
468 as the @code{.dword} directive.
470 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
471 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
473 @cindex @code{.cfi_b_key_frame} directive, AArch64
474 @item @code{.cfi_b_key_frame}
475 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
476 corresponding to the current frame's FDE, meaning that its return address has
477 been signed with the B-key. If two frames are signed with differing keys then
478 they will not share the same CIE. This information is intended to be used by
479 the stack unwinder in order to properly authenticate return addresses.
483 @node AArch64 Opcodes
486 @cindex AArch64 opcodes
487 @cindex opcodes for AArch64
488 GAS implements all the standard AArch64 opcodes. It also
489 implements several pseudo opcodes, including several synthetic load
494 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
497 ldr <register> , =<expression>
500 The constant expression will be placed into the nearest literal pool (if it not
501 already there) and a PC-relative LDR instruction will be generated.
505 For more information on the AArch64 instruction set and assembly language
506 notation, see @samp{ARMv8 Instruction Set Overview} available at
507 @uref{http://infocenter.arm.com}.
510 @node AArch64 Mapping Symbols
511 @section Mapping Symbols
513 The AArch64 ELF specification requires that special symbols be inserted
514 into object files to mark certain features:
520 At the start of a region of code containing AArch64 instructions.
524 At the start of a region of data.